if_txp.c revision 1.51
1 /* $NetBSD: if_txp.c,v 1.51 2018/12/09 11:14:02 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.51 2018/12/09 11:14:02 jdolecek Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_types.h> 52 #include <net/if_ether.h> 53 #include <net/if_arp.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_inarp.h> 61 #endif 62 63 #include <net/if_media.h> 64 65 #include <net/bpf.h> 66 67 #include <sys/bus.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/pci/if_txpreg.h> 76 77 #include <dev/microcode/typhoon/3c990img.h> 78 79 /* 80 * These currently break the 3c990 firmware, hopefully will be resolved 81 * at some point. 82 */ 83 #undef TRY_TX_UDP_CSUM 84 #undef TRY_TX_TCP_CSUM 85 86 int txp_probe(device_t, cfdata_t, void *); 87 void txp_attach(device_t, device_t, void *); 88 int txp_intr(void *); 89 void txp_tick(void *); 90 bool txp_shutdown(device_t, int); 91 int txp_ioctl(struct ifnet *, u_long, void *); 92 void txp_start(struct ifnet *); 93 void txp_stop(struct txp_softc *); 94 void txp_init(struct txp_softc *); 95 void txp_watchdog(struct ifnet *); 96 97 int txp_chip_init(struct txp_softc *); 98 int txp_reset_adapter(struct txp_softc *); 99 int txp_download_fw(struct txp_softc *); 100 int txp_download_fw_wait(struct txp_softc *); 101 int txp_download_fw_section(struct txp_softc *, 102 const struct txp_fw_section_header *, int); 103 int txp_alloc_rings(struct txp_softc *); 104 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 105 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 106 void txp_set_filter(struct txp_softc *); 107 108 int txp_cmd_desc_numfree(struct txp_softc *); 109 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 110 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 111 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 112 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 113 struct txp_rsp_desc **, int); 114 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 115 struct txp_rsp_desc **); 116 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 117 struct txp_rsp_desc *); 118 void txp_capabilities(struct txp_softc *); 119 120 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121 int txp_ifmedia_upd(struct ifnet *); 122 void txp_show_descriptor(void *); 123 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 124 struct txp_dma_alloc *); 125 void txp_rxbuf_reclaim(struct txp_softc *); 126 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 127 struct txp_dma_alloc *); 128 129 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 130 NULL, NULL); 131 132 const struct txp_pci_match { 133 int vid, did, flags; 134 } txp_devices[] = { 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 143 }; 144 145 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 146 147 static const struct { 148 u_int16_t mask, value; 149 int flags; 150 } txp_subsysinfo[] = { 151 {0xf000, 0x2000, TXP_SERVERVERSION}, 152 {0x0100, 0x0100, TXP_FIBER}, 153 #if 0 /* information from 3com header, unused */ 154 {0x0010, 0x0010, /* secured firmware */}, 155 {0x0003, 0x0000, /* variable DES */}, 156 {0x0003, 0x0001, /* single DES - "95" */}, 157 {0x0003, 0x0002, /* triple DES - "97" */}, 158 #endif 159 }; 160 161 static const struct txp_pci_match * 162 txp_pcilookup(pcireg_t id) 163 { 164 int i; 165 166 for (i = 0; i < __arraycount(txp_devices); i++) 167 if (PCI_VENDOR(id) == txp_devices[i].vid && 168 PCI_PRODUCT(id) == txp_devices[i].did) 169 return &txp_devices[i]; 170 return (0); 171 } 172 173 int 174 txp_probe(device_t parent, cfdata_t match, void *aux) 175 { 176 struct pci_attach_args *pa = aux; 177 178 if (txp_pcilookup(pa->pa_id)) 179 return (1); 180 return (0); 181 } 182 183 void 184 txp_attach(device_t parent, device_t self, void *aux) 185 { 186 struct txp_softc *sc = device_private(self); 187 struct pci_attach_args *pa = aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 pci_intr_handle_t ih; 190 const char *intrstr = NULL; 191 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 192 u_int32_t command; 193 u_int16_t p1; 194 u_int32_t p2; 195 u_char enaddr[6]; 196 const struct txp_pci_match *match; 197 u_int16_t subsys; 198 int i, flags; 199 char devinfo[256]; 200 char intrbuf[PCI_INTRSTR_LEN]; 201 202 sc->sc_dev = self; 203 sc->sc_cold = 1; 204 205 match = txp_pcilookup(pa->pa_id); 206 flags = match->flags; 207 if (match->flags & TXP_USESUBSYSTEM) { 208 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 209 PCI_SUBSYS_ID_REG)); 210 for (i = 0; 211 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 212 i++) 213 if ((subsys & txp_subsysinfo[i].mask) == 214 txp_subsysinfo[i].value) 215 flags |= txp_subsysinfo[i].flags; 216 } 217 sc->sc_flags = flags; 218 219 aprint_naive("\n"); 220 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 221 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 222 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 223 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 224 device_xname(sc->sc_dev)); 225 226 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 227 228 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 229 aprint_error(": failed to enable bus mastering\n"); 230 return; 231 } 232 233 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 234 aprint_error(": failed to enable memory mapping\n"); 235 return; 236 } 237 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 238 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 239 aprint_error(": can't map mem space %d\n", 0); 240 return; 241 } 242 243 sc->sc_dmat = pa->pa_dmat; 244 245 /* 246 * Allocate our interrupt. 247 */ 248 if (pci_intr_map(pa, &ih)) { 249 aprint_error(": couldn't map interrupt\n"); 250 return; 251 } 252 253 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 254 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, txp_intr, sc, 255 device_xname(self)); 256 if (sc->sc_ih == NULL) { 257 aprint_error(": couldn't establish interrupt"); 258 if (intrstr != NULL) 259 aprint_normal(" at %s", intrstr); 260 aprint_normal("\n"); 261 return; 262 } 263 aprint_error(": interrupting at %s\n", intrstr); 264 265 if (txp_chip_init(sc)) 266 goto cleanupintr; 267 268 if (txp_download_fw(sc)) 269 goto cleanupintr; 270 271 if (txp_alloc_rings(sc)) 272 goto cleanupintr; 273 274 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 275 NULL, NULL, NULL, 1)) 276 goto cleanupintr; 277 278 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 279 &p1, &p2, NULL, 1)) 280 goto cleanupintr; 281 282 txp_set_filter(sc); 283 284 p1 = htole16(p1); 285 enaddr[0] = ((u_int8_t *)&p1)[1]; 286 enaddr[1] = ((u_int8_t *)&p1)[0]; 287 p2 = htole32(p2); 288 enaddr[2] = ((u_int8_t *)&p2)[3]; 289 enaddr[3] = ((u_int8_t *)&p2)[2]; 290 enaddr[4] = ((u_int8_t *)&p2)[1]; 291 enaddr[5] = ((u_int8_t *)&p2)[0]; 292 293 aprint_normal_dev(self, "Ethernet address %s\n", 294 ether_sprintf(enaddr)); 295 sc->sc_cold = 0; 296 297 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 298 if (flags & TXP_FIBER) { 299 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 300 0, NULL); 301 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 302 0, NULL); 303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 304 0, NULL); 305 } else { 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 309 0, NULL); 310 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 311 0, NULL); 312 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 313 0, NULL); 314 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 315 0, NULL); 316 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 317 0, NULL); 318 } 319 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 320 321 sc->sc_xcvr = TXP_XCVR_AUTO; 322 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 323 NULL, NULL, NULL, 0); 324 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 325 326 ifp->if_softc = sc; 327 ifp->if_mtu = ETHERMTU; 328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 329 ifp->if_ioctl = txp_ioctl; 330 ifp->if_start = txp_start; 331 ifp->if_watchdog = txp_watchdog; 332 ifp->if_baudrate = 10000000; 333 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 334 IFQ_SET_READY(&ifp->if_snd); 335 ifp->if_capabilities = 0; 336 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 337 338 txp_capabilities(sc); 339 340 callout_init(&sc->sc_tick, 0); 341 callout_setfunc(&sc->sc_tick, txp_tick, sc); 342 343 /* 344 * Attach us everywhere 345 */ 346 if_attach(ifp); 347 if_deferred_start_init(ifp, NULL); 348 ether_ifattach(ifp, enaddr); 349 350 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 351 pmf_class_network_register(self, ifp); 352 else 353 aprint_error_dev(self, "couldn't establish power handler\n"); 354 355 return; 356 357 cleanupintr: 358 pci_intr_disestablish(pc,sc->sc_ih); 359 360 return; 361 362 } 363 364 int 365 txp_chip_init(struct txp_softc *sc) 366 { 367 /* disable interrupts */ 368 WRITE_REG(sc, TXP_IER, 0); 369 WRITE_REG(sc, TXP_IMR, 370 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 371 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 372 TXP_INT_LATCH); 373 374 /* ack all interrupts */ 375 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 376 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 377 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 378 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 379 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 380 381 if (txp_reset_adapter(sc)) 382 return (-1); 383 384 /* disable interrupts */ 385 WRITE_REG(sc, TXP_IER, 0); 386 WRITE_REG(sc, TXP_IMR, 387 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 388 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 389 TXP_INT_LATCH); 390 391 /* ack all interrupts */ 392 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 393 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 394 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 395 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 396 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 397 398 return (0); 399 } 400 401 int 402 txp_reset_adapter(struct txp_softc *sc) 403 { 404 u_int32_t r; 405 int i; 406 407 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 408 DELAY(1000); 409 WRITE_REG(sc, TXP_SRR, 0); 410 411 /* Should wait max 6 seconds */ 412 for (i = 0; i < 6000; i++) { 413 r = READ_REG(sc, TXP_A2H_0); 414 if (r == STAT_WAITING_FOR_HOST_REQUEST) 415 break; 416 DELAY(1000); 417 } 418 419 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 420 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 421 return (-1); 422 } 423 424 return (0); 425 } 426 427 int 428 txp_download_fw(struct txp_softc *sc) 429 { 430 const struct txp_fw_file_header *fileheader; 431 const struct txp_fw_section_header *secthead; 432 int sect; 433 u_int32_t r, i, ier, imr; 434 435 ier = READ_REG(sc, TXP_IER); 436 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 437 438 imr = READ_REG(sc, TXP_IMR); 439 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 440 441 for (i = 0; i < 10000; i++) { 442 r = READ_REG(sc, TXP_A2H_0); 443 if (r == STAT_WAITING_FOR_HOST_REQUEST) 444 break; 445 DELAY(50); 446 } 447 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 448 printf(": not waiting for host request\n"); 449 return (-1); 450 } 451 452 /* Ack the status */ 453 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 454 455 fileheader = (const struct txp_fw_file_header *)tc990image; 456 if (memcmp("TYPHOON", fileheader->magicid, 457 sizeof(fileheader->magicid))) { 458 printf(": fw invalid magic\n"); 459 return (-1); 460 } 461 462 /* Tell boot firmware to get ready for image */ 463 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 464 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 465 466 if (txp_download_fw_wait(sc)) { 467 printf("%s: fw wait failed, initial\n", 468 device_xname(sc->sc_dev)); 469 return (-1); 470 } 471 472 secthead = (const struct txp_fw_section_header *) 473 (((const u_int8_t *)tc990image) + 474 sizeof(struct txp_fw_file_header)); 475 476 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 477 if (txp_download_fw_section(sc, secthead, sect)) 478 return (-1); 479 secthead = (const struct txp_fw_section_header *) 480 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 481 sizeof(*secthead)); 482 } 483 484 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 485 486 for (i = 0; i < 10000; i++) { 487 r = READ_REG(sc, TXP_A2H_0); 488 if (r == STAT_WAITING_FOR_BOOT) 489 break; 490 DELAY(50); 491 } 492 if (r != STAT_WAITING_FOR_BOOT) { 493 printf(": not waiting for boot\n"); 494 return (-1); 495 } 496 497 WRITE_REG(sc, TXP_IER, ier); 498 WRITE_REG(sc, TXP_IMR, imr); 499 500 return (0); 501 } 502 503 int 504 txp_download_fw_wait(struct txp_softc *sc) 505 { 506 u_int32_t i, r; 507 508 for (i = 0; i < 10000; i++) { 509 r = READ_REG(sc, TXP_ISR); 510 if (r & TXP_INT_A2H_0) 511 break; 512 DELAY(50); 513 } 514 515 if (!(r & TXP_INT_A2H_0)) { 516 printf(": fw wait failed comm0\n"); 517 return (-1); 518 } 519 520 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 521 522 r = READ_REG(sc, TXP_A2H_0); 523 if (r != STAT_WAITING_FOR_SEGMENT) { 524 printf(": fw not waiting for segment\n"); 525 return (-1); 526 } 527 return (0); 528 } 529 530 int 531 txp_download_fw_section(struct txp_softc *sc, 532 const struct txp_fw_section_header *sect, int sectnum) 533 { 534 struct txp_dma_alloc dma; 535 int rseg, err = 0; 536 struct mbuf m; 537 #ifdef INET 538 u_int16_t csum; 539 #endif 540 541 /* Skip zero length sections */ 542 if (sect->nbytes == 0) 543 return (0); 544 545 /* Make sure we aren't past the end of the image */ 546 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 547 if (rseg >= sizeof(tc990image)) { 548 printf(": fw invalid section address, section %d\n", sectnum); 549 return (-1); 550 } 551 552 /* Make sure this section doesn't go past the end */ 553 rseg += le32toh(sect->nbytes); 554 if (rseg >= sizeof(tc990image)) { 555 printf(": fw truncated section %d\n", sectnum); 556 return (-1); 557 } 558 559 /* map a buffer, copy segment to it, get physaddr */ 560 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 561 printf(": fw dma malloc failed, section %d\n", sectnum); 562 return (-1); 563 } 564 565 memcpy(dma.dma_vaddr, ((const u_int8_t *)sect) + sizeof(*sect), 566 le32toh(sect->nbytes)); 567 568 /* 569 * dummy up mbuf and verify section checksum 570 */ 571 m.m_type = MT_DATA; 572 m.m_next = m.m_nextpkt = NULL; 573 m.m_owner = NULL; 574 m.m_len = le32toh(sect->nbytes); 575 m.m_data = dma.dma_vaddr; 576 m.m_flags = 0; 577 #ifdef INET 578 csum = in_cksum(&m, le32toh(sect->nbytes)); 579 if (csum != sect->cksum) { 580 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 581 sectnum, sect->cksum, csum); 582 txp_dma_free(sc, &dma); 583 return -1; 584 } 585 #endif 586 587 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 588 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 589 590 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 591 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 592 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 593 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 594 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 595 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 596 597 if (txp_download_fw_wait(sc)) { 598 printf("%s: fw wait failed, section %d\n", 599 device_xname(sc->sc_dev), sectnum); 600 err = -1; 601 } 602 603 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 604 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 605 606 txp_dma_free(sc, &dma); 607 return (err); 608 } 609 610 int 611 txp_intr(void *vsc) 612 { 613 struct txp_softc *sc = vsc; 614 struct txp_hostvar *hv = sc->sc_hostvar; 615 u_int32_t isr; 616 int claimed = 0; 617 618 /* mask all interrupts */ 619 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 620 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 621 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 622 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 623 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 624 625 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 626 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 627 628 isr = READ_REG(sc, TXP_ISR); 629 while (isr) { 630 claimed = 1; 631 WRITE_REG(sc, TXP_ISR, isr); 632 633 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 634 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 635 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 636 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 637 638 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 639 txp_rxbuf_reclaim(sc); 640 641 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 642 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 643 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 644 645 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 646 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 647 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 648 649 isr = READ_REG(sc, TXP_ISR); 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 653 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 654 655 /* unmask all interrupts */ 656 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 657 658 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 659 660 return (claimed); 661 } 662 663 void 664 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 665 struct txp_dma_alloc *dma) 666 { 667 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 668 struct txp_rx_desc *rxd; 669 struct mbuf *m; 670 struct txp_swdesc *sd; 671 u_int32_t roff, woff; 672 int sumflags = 0; 673 int idx; 674 675 roff = le32toh(*r->r_roff); 676 woff = le32toh(*r->r_woff); 677 idx = roff / sizeof(struct txp_rx_desc); 678 rxd = r->r_desc + idx; 679 680 while (roff != woff) { 681 682 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 683 idx * sizeof(struct txp_rx_desc), 684 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 685 686 if (rxd->rx_flags & RX_FLAGS_ERROR) { 687 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 688 le32toh(rxd->rx_stat)); 689 ifp->if_ierrors++; 690 goto next; 691 } 692 693 /* retrieve stashed pointer */ 694 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 695 696 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 697 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 698 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 699 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 700 m = sd->sd_mbuf; 701 free(sd, M_DEVBUF); 702 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 703 704 #ifdef __STRICT_ALIGNMENT 705 { 706 /* 707 * XXX Nice chip, except it won't accept "off by 2" 708 * buffers, so we're force to copy. Supposedly 709 * this will be fixed in a newer firmware rev 710 * and this will be temporary. 711 */ 712 struct mbuf *mnew; 713 714 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 715 if (mnew == NULL) { 716 m_freem(m); 717 goto next; 718 } 719 if (m->m_len > (MHLEN - 2)) { 720 MCLGET(mnew, M_DONTWAIT); 721 if (!(mnew->m_flags & M_EXT)) { 722 m_freem(mnew); 723 m_freem(m); 724 goto next; 725 } 726 } 727 m_set_rcvif(mnew, ifp); 728 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 729 mnew->m_data += 2; 730 memcpy(mnew->m_data, m->m_data, m->m_len); 731 m_freem(m); 732 m = mnew; 733 } 734 #endif 735 736 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 737 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 738 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 739 sumflags |= M_CSUM_IPv4; 740 741 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 742 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 743 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 744 sumflags |= M_CSUM_TCPv4; 745 746 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 747 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 748 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 749 sumflags |= M_CSUM_UDPv4; 750 751 m->m_pkthdr.csum_flags = sumflags; 752 753 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 754 vlan_set_tag(m, htons(rxd->rx_vlan >> 16)); 755 } 756 757 if_percpuq_enqueue(ifp->if_percpuq, m); 758 759 next: 760 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 761 idx * sizeof(struct txp_rx_desc), 762 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 763 764 roff += sizeof(struct txp_rx_desc); 765 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 766 idx = 0; 767 roff = 0; 768 rxd = r->r_desc; 769 } else { 770 idx++; 771 rxd++; 772 } 773 woff = le32toh(*r->r_woff); 774 } 775 776 *r->r_roff = htole32(woff); 777 } 778 779 void 780 txp_rxbuf_reclaim(struct txp_softc *sc) 781 { 782 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 783 struct txp_hostvar *hv = sc->sc_hostvar; 784 struct txp_rxbuf_desc *rbd; 785 struct txp_swdesc *sd; 786 u_int32_t i, end; 787 788 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 789 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 790 791 if (++i == RXBUF_ENTRIES) 792 i = 0; 793 794 rbd = sc->sc_rxbufs + i; 795 796 while (i != end) { 797 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 798 M_DEVBUF, M_NOWAIT); 799 if (sd == NULL) 800 break; 801 802 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 803 if (sd->sd_mbuf == NULL) 804 goto err_sd; 805 806 MCLGET(sd->sd_mbuf, M_DONTWAIT); 807 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 808 goto err_mbuf; 809 m_set_rcvif(sd->sd_mbuf, ifp); 810 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 811 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 812 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 813 goto err_mbuf; 814 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 815 BUS_DMA_NOWAIT)) { 816 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 817 goto err_mbuf; 818 } 819 820 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 821 i * sizeof(struct txp_rxbuf_desc), 822 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 823 824 /* stash away pointer */ 825 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 826 827 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 828 & 0xffffffff; 829 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 830 >> 32; 831 832 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 833 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 834 835 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 836 i * sizeof(struct txp_rxbuf_desc), 837 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 838 839 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 840 841 if (++i == RXBUF_ENTRIES) { 842 i = 0; 843 rbd = sc->sc_rxbufs; 844 } else 845 rbd++; 846 } 847 return; 848 849 err_mbuf: 850 m_freem(sd->sd_mbuf); 851 err_sd: 852 free(sd, M_DEVBUF); 853 } 854 855 /* 856 * Reclaim mbufs and entries from a transmit ring. 857 */ 858 void 859 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 860 struct txp_dma_alloc *dma) 861 { 862 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 863 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 864 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 865 struct txp_tx_desc *txd = r->r_desc + cons; 866 struct txp_swdesc *sd = sc->sc_txd + cons; 867 struct mbuf *m; 868 869 while (cons != idx) { 870 if (cnt == 0) 871 break; 872 873 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 874 cons * sizeof(struct txp_tx_desc), 875 sizeof(struct txp_tx_desc), 876 BUS_DMASYNC_POSTWRITE); 877 878 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 879 TX_FLAGS_TYPE_DATA) { 880 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 881 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 882 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 883 m = sd->sd_mbuf; 884 if (m != NULL) { 885 m_freem(m); 886 txd->tx_addrlo = 0; 887 txd->tx_addrhi = 0; 888 ifp->if_opackets++; 889 } 890 } 891 ifp->if_flags &= ~IFF_OACTIVE; 892 893 if (++cons == TX_ENTRIES) { 894 txd = r->r_desc; 895 cons = 0; 896 sd = sc->sc_txd; 897 } else { 898 txd++; 899 sd++; 900 } 901 902 cnt--; 903 } 904 905 r->r_cons = cons; 906 r->r_cnt = cnt; 907 if (cnt == 0) 908 ifp->if_timer = 0; 909 } 910 911 bool 912 txp_shutdown(device_t self, int howto) 913 { 914 struct txp_softc *sc; 915 916 sc = device_private(self); 917 918 /* mask all interrupts */ 919 WRITE_REG(sc, TXP_IMR, 920 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 921 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 922 TXP_INT_LATCH); 923 924 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 925 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 926 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 927 928 return true; 929 } 930 931 int 932 txp_alloc_rings(struct txp_softc *sc) 933 { 934 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 935 struct txp_boot_record *boot; 936 struct txp_swdesc *sd; 937 u_int32_t r; 938 int i, j, nb; 939 940 /* boot record */ 941 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 942 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 943 printf(": can't allocate boot record\n"); 944 return (-1); 945 } 946 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 947 memset(boot, 0, sizeof(*boot)); 948 sc->sc_boot = boot; 949 950 /* host variables */ 951 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 952 BUS_DMA_COHERENT)) { 953 printf(": can't allocate host ring\n"); 954 goto bail_boot; 955 } 956 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 957 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 958 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 959 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 960 961 /* high priority tx ring */ 962 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 963 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 964 printf(": can't allocate high tx ring\n"); 965 goto bail_host; 966 } 967 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 968 sizeof(struct txp_tx_desc) * TX_ENTRIES); 969 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 970 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 971 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 972 sc->sc_txhir.r_reg = TXP_H2A_1; 973 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 974 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 975 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 976 for (i = 0; i < TX_ENTRIES; i++) { 977 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 978 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 979 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 980 for (j = 0; j < i; j++) { 981 bus_dmamap_destroy(sc->sc_dmat, 982 sc->sc_txd[j].sd_map); 983 sc->sc_txd[j].sd_map = NULL; 984 } 985 goto bail_txhiring; 986 } 987 } 988 989 /* low priority tx ring */ 990 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 991 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 992 printf(": can't allocate low tx ring\n"); 993 goto bail_txhiring; 994 } 995 memset(sc->sc_txloring_dma.dma_vaddr, 0, 996 sizeof(struct txp_tx_desc) * TX_ENTRIES); 997 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 998 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 999 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1000 sc->sc_txlor.r_reg = TXP_H2A_3; 1001 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1002 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1003 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1004 1005 /* high priority rx ring */ 1006 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1007 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1008 printf(": can't allocate high rx ring\n"); 1009 goto bail_txloring; 1010 } 1011 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1012 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1013 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1014 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1015 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1016 sc->sc_rxhir.r_desc = 1017 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1018 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1019 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1020 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1021 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1022 1023 /* low priority ring */ 1024 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1025 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1026 printf(": can't allocate low rx ring\n"); 1027 goto bail_rxhiring; 1028 } 1029 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1030 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1031 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1032 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1033 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1034 sc->sc_rxlor.r_desc = 1035 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1036 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1037 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1038 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1039 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1040 1041 /* command ring */ 1042 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1043 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1044 printf(": can't allocate command ring\n"); 1045 goto bail_rxloring; 1046 } 1047 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1048 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1049 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1050 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1051 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1052 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1053 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1054 sc->sc_cmdring.lastwrite = 0; 1055 1056 /* response ring */ 1057 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1058 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1059 printf(": can't allocate response ring\n"); 1060 goto bail_cmdring; 1061 } 1062 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1063 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1064 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1065 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1066 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1067 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1068 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1069 sc->sc_rspring.lastwrite = 0; 1070 1071 /* receive buffer ring */ 1072 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1073 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1074 printf(": can't allocate rx buffer ring\n"); 1075 goto bail_rspring; 1076 } 1077 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1078 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1079 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1080 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1081 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1082 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1083 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1084 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1085 M_DEVBUF, M_NOWAIT); 1086 /* stash away pointer */ 1087 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, 1088 sizeof(sd)); 1089 if (sd == NULL) 1090 break; 1091 1092 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1093 if (sd->sd_mbuf == NULL) { 1094 goto bail_rxbufring; 1095 } 1096 1097 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1098 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1099 goto bail_rxbufring; 1100 } 1101 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1102 m_set_rcvif(sd->sd_mbuf, ifp); 1103 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1104 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1105 goto bail_rxbufring; 1106 } 1107 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1108 BUS_DMA_NOWAIT)) { 1109 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1110 goto bail_rxbufring; 1111 } 1112 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1113 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1114 1115 1116 sc->sc_rxbufs[nb].rb_paddrlo = 1117 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1118 sc->sc_rxbufs[nb].rb_paddrhi = 1119 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1120 } 1121 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1122 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1123 BUS_DMASYNC_PREWRITE); 1124 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1125 sizeof(struct txp_rxbuf_desc)); 1126 1127 /* zero dma */ 1128 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1129 BUS_DMA_COHERENT)) { 1130 printf(": can't allocate response ring\n"); 1131 goto bail_rxbufring; 1132 } 1133 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(u_int32_t)); 1134 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1135 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1136 1137 /* See if it's waiting for boot, and try to boot it */ 1138 for (i = 0; i < 10000; i++) { 1139 r = READ_REG(sc, TXP_A2H_0); 1140 if (r == STAT_WAITING_FOR_BOOT) 1141 break; 1142 DELAY(50); 1143 } 1144 if (r != STAT_WAITING_FOR_BOOT) { 1145 printf(": not waiting for boot\n"); 1146 goto bail; 1147 } 1148 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1149 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1150 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1151 1152 /* See if it booted */ 1153 for (i = 0; i < 10000; i++) { 1154 r = READ_REG(sc, TXP_A2H_0); 1155 if (r == STAT_RUNNING) 1156 break; 1157 DELAY(50); 1158 } 1159 if (r != STAT_RUNNING) { 1160 printf(": fw not running\n"); 1161 goto bail; 1162 } 1163 1164 /* Clear TX and CMD ring write registers */ 1165 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1166 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1167 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1168 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1169 1170 return (0); 1171 1172 bail: 1173 txp_dma_free(sc, &sc->sc_zero_dma); 1174 bail_rxbufring: 1175 if (nb == RXBUF_ENTRIES) 1176 nb--; 1177 for (i = 0; i <= nb; i++) { 1178 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1179 sizeof(sd)); 1180 if (sd) 1181 free(sd, M_DEVBUF); 1182 } 1183 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1184 bail_rspring: 1185 txp_dma_free(sc, &sc->sc_rspring_dma); 1186 bail_cmdring: 1187 txp_dma_free(sc, &sc->sc_cmdring_dma); 1188 bail_rxloring: 1189 txp_dma_free(sc, &sc->sc_rxloring_dma); 1190 bail_rxhiring: 1191 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1192 bail_txloring: 1193 txp_dma_free(sc, &sc->sc_txloring_dma); 1194 bail_txhiring: 1195 txp_dma_free(sc, &sc->sc_txhiring_dma); 1196 bail_host: 1197 txp_dma_free(sc, &sc->sc_host_dma); 1198 bail_boot: 1199 txp_dma_free(sc, &sc->sc_boot_dma); 1200 return (-1); 1201 } 1202 1203 int 1204 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1205 struct txp_dma_alloc *dma, int mapflags) 1206 { 1207 int r; 1208 1209 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1210 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1211 goto fail_0; 1212 1213 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1214 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1215 goto fail_1; 1216 1217 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1218 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1219 goto fail_2; 1220 1221 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1222 size, NULL, BUS_DMA_NOWAIT)) != 0) 1223 goto fail_3; 1224 1225 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1226 return (0); 1227 1228 fail_3: 1229 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1230 fail_2: 1231 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1232 fail_1: 1233 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1234 fail_0: 1235 return (r); 1236 } 1237 1238 void 1239 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1240 { 1241 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1242 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1243 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1244 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1245 } 1246 1247 int 1248 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1249 { 1250 struct txp_softc *sc = ifp->if_softc; 1251 struct ifreq *ifr = (struct ifreq *)data; 1252 struct ifaddr *ifa = (struct ifaddr *)data; 1253 int s, error = 0; 1254 1255 s = splnet(); 1256 1257 #if 0 1258 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1259 splx(s); 1260 return error; 1261 } 1262 #endif 1263 1264 switch(command) { 1265 case SIOCINITIFADDR: 1266 ifp->if_flags |= IFF_UP; 1267 txp_init(sc); 1268 switch (ifa->ifa_addr->sa_family) { 1269 #ifdef INET 1270 case AF_INET: 1271 arp_ifinit(ifp, ifa); 1272 break; 1273 #endif /* INET */ 1274 default: 1275 break; 1276 } 1277 break; 1278 case SIOCSIFFLAGS: 1279 if ((error = ifioctl_common(ifp, command, data)) != 0) 1280 break; 1281 if (ifp->if_flags & IFF_UP) { 1282 txp_init(sc); 1283 } else { 1284 if (ifp->if_flags & IFF_RUNNING) 1285 txp_stop(sc); 1286 } 1287 break; 1288 case SIOCADDMULTI: 1289 case SIOCDELMULTI: 1290 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1291 break; 1292 1293 error = 0; 1294 1295 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1296 ; 1297 else if (ifp->if_flags & IFF_RUNNING) { 1298 /* 1299 * Multicast list has changed; set the hardware 1300 * filter accordingly. 1301 */ 1302 txp_set_filter(sc); 1303 } 1304 break; 1305 case SIOCGIFMEDIA: 1306 case SIOCSIFMEDIA: 1307 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1308 break; 1309 default: 1310 error = ether_ioctl(ifp, command, data); 1311 break; 1312 } 1313 1314 splx(s); 1315 1316 return(error); 1317 } 1318 1319 void 1320 txp_init(struct txp_softc *sc) 1321 { 1322 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1323 int s; 1324 1325 txp_stop(sc); 1326 1327 s = splnet(); 1328 1329 txp_set_filter(sc); 1330 1331 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1332 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1333 1334 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1335 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1336 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1337 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1338 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1339 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1340 1341 ifp->if_flags |= IFF_RUNNING; 1342 ifp->if_flags &= ~IFF_OACTIVE; 1343 ifp->if_timer = 0; 1344 1345 if (!callout_pending(&sc->sc_tick)) 1346 callout_schedule(&sc->sc_tick, hz); 1347 1348 splx(s); 1349 } 1350 1351 void 1352 txp_tick(void *vsc) 1353 { 1354 struct txp_softc *sc = vsc; 1355 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1356 struct txp_rsp_desc *rsp = NULL; 1357 struct txp_ext_desc *ext; 1358 int s; 1359 1360 s = splnet(); 1361 txp_rxbuf_reclaim(sc); 1362 1363 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1364 &rsp, 1)) 1365 goto out; 1366 if (rsp->rsp_numdesc != 6) 1367 goto out; 1368 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1369 NULL, NULL, NULL, 1)) 1370 goto out; 1371 ext = (struct txp_ext_desc *)(rsp + 1); 1372 1373 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1374 ext[4].ext_1 + ext[4].ext_4; 1375 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1376 ext[2].ext_1; 1377 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1378 ext[1].ext_3; 1379 ifp->if_opackets += rsp->rsp_par2; 1380 ifp->if_ipackets += ext[2].ext_3; 1381 1382 out: 1383 if (rsp != NULL) 1384 free(rsp, M_DEVBUF); 1385 1386 splx(s); 1387 callout_schedule(&sc->sc_tick, hz); 1388 } 1389 1390 void 1391 txp_start(struct ifnet *ifp) 1392 { 1393 struct txp_softc *sc = ifp->if_softc; 1394 struct txp_tx_ring *r = &sc->sc_txhir; 1395 struct txp_tx_desc *txd; 1396 int txdidx; 1397 struct txp_frag_desc *fxd; 1398 struct mbuf *m, *mnew; 1399 struct txp_swdesc *sd; 1400 u_int32_t firstprod, firstcnt, prod, cnt, i; 1401 1402 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1403 return; 1404 1405 prod = r->r_prod; 1406 cnt = r->r_cnt; 1407 1408 while (1) { 1409 IFQ_POLL(&ifp->if_snd, m); 1410 if (m == NULL) 1411 break; 1412 mnew = NULL; 1413 1414 firstprod = prod; 1415 firstcnt = cnt; 1416 1417 sd = sc->sc_txd + prod; 1418 sd->sd_mbuf = m; 1419 1420 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1421 BUS_DMA_NOWAIT)) { 1422 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1423 if (mnew == NULL) 1424 goto oactive1; 1425 if (m->m_pkthdr.len > MHLEN) { 1426 MCLGET(mnew, M_DONTWAIT); 1427 if ((mnew->m_flags & M_EXT) == 0) { 1428 m_freem(mnew); 1429 goto oactive1; 1430 } 1431 } 1432 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1433 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1434 IFQ_DEQUEUE(&ifp->if_snd, m); 1435 m_freem(m); 1436 m = mnew; 1437 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1438 BUS_DMA_NOWAIT)) 1439 goto oactive1; 1440 } 1441 1442 if ((TX_ENTRIES - cnt) < 4) 1443 goto oactive; 1444 1445 txd = r->r_desc + prod; 1446 txdidx = prod; 1447 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1448 txd->tx_numdesc = 0; 1449 txd->tx_addrlo = 0; 1450 txd->tx_addrhi = 0; 1451 txd->tx_totlen = m->m_pkthdr.len; 1452 txd->tx_pflags = 0; 1453 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1454 1455 if (++prod == TX_ENTRIES) 1456 prod = 0; 1457 1458 if (++cnt >= (TX_ENTRIES - 4)) 1459 goto oactive; 1460 1461 if (vlan_has_tag(m)) 1462 txd->tx_pflags = TX_PFLAGS_VLAN | 1463 (htons(vlan_get_tag(m)) << TX_PFLAGS_VLANTAG_S); 1464 1465 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1466 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1467 #ifdef TRY_TX_TCP_CSUM 1468 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1469 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1470 #endif 1471 #ifdef TRY_TX_UDP_CSUM 1472 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1473 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1474 #endif 1475 1476 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1477 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1478 1479 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1480 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1481 if (++cnt >= (TX_ENTRIES - 4)) { 1482 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1483 0, sd->sd_map->dm_mapsize, 1484 BUS_DMASYNC_POSTWRITE); 1485 goto oactive; 1486 } 1487 1488 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1489 FRAG_FLAGS_VALID; 1490 fxd->frag_rsvd1 = 0; 1491 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1492 fxd->frag_addrlo = 1493 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1494 0xffffffff; 1495 fxd->frag_addrhi = 1496 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1497 32; 1498 fxd->frag_rsvd2 = 0; 1499 1500 bus_dmamap_sync(sc->sc_dmat, 1501 sc->sc_txhiring_dma.dma_map, 1502 prod * sizeof(struct txp_frag_desc), 1503 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1504 1505 if (++prod == TX_ENTRIES) { 1506 fxd = (struct txp_frag_desc *)r->r_desc; 1507 prod = 0; 1508 } else 1509 fxd++; 1510 1511 } 1512 1513 /* 1514 * if mnew isn't NULL, we already dequeued and copied 1515 * the packet. 1516 */ 1517 if (mnew == NULL) 1518 IFQ_DEQUEUE(&ifp->if_snd, m); 1519 1520 ifp->if_timer = 5; 1521 1522 bpf_mtap(ifp, m, BPF_D_OUT); 1523 1524 txd->tx_flags |= TX_FLAGS_VALID; 1525 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1526 txdidx * sizeof(struct txp_tx_desc), 1527 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1528 1529 #if 0 1530 { 1531 struct mbuf *mx; 1532 int i; 1533 1534 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1535 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1536 txd->tx_pflags); 1537 for (mx = m; mx != NULL; mx = mx->m_next) { 1538 for (i = 0; i < mx->m_len; i++) { 1539 printf(":%02x", 1540 (u_int8_t)m->m_data[i]); 1541 } 1542 } 1543 printf("\n"); 1544 } 1545 #endif 1546 1547 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1548 } 1549 1550 r->r_prod = prod; 1551 r->r_cnt = cnt; 1552 return; 1553 1554 oactive: 1555 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1556 oactive1: 1557 ifp->if_flags |= IFF_OACTIVE; 1558 r->r_prod = firstprod; 1559 r->r_cnt = firstcnt; 1560 } 1561 1562 /* 1563 * Handle simple commands sent to the typhoon 1564 */ 1565 int 1566 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, 1567 u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3, int wait) 1568 { 1569 struct txp_rsp_desc *rsp = NULL; 1570 1571 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1572 return (-1); 1573 1574 if (!wait) 1575 return (0); 1576 1577 if (out1 != NULL) 1578 *out1 = le16toh(rsp->rsp_par1); 1579 if (out2 != NULL) 1580 *out2 = le32toh(rsp->rsp_par2); 1581 if (out3 != NULL) 1582 *out3 = le32toh(rsp->rsp_par3); 1583 free(rsp, M_DEVBUF); 1584 return (0); 1585 } 1586 1587 int 1588 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, 1589 u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn, 1590 struct txp_rsp_desc **rspp, int wait) 1591 { 1592 struct txp_hostvar *hv = sc->sc_hostvar; 1593 struct txp_cmd_desc *cmd; 1594 struct txp_ext_desc *ext; 1595 u_int32_t idx, i; 1596 u_int16_t seq; 1597 1598 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1599 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1600 return (-1); 1601 } 1602 1603 idx = sc->sc_cmdring.lastwrite; 1604 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1605 memset(cmd, 0, sizeof(*cmd)); 1606 1607 cmd->cmd_numdesc = in_extn; 1608 seq = sc->sc_seq++; 1609 cmd->cmd_seq = htole16(seq); 1610 cmd->cmd_id = htole16(id); 1611 cmd->cmd_par1 = htole16(in1); 1612 cmd->cmd_par2 = htole32(in2); 1613 cmd->cmd_par3 = htole32(in3); 1614 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1615 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1616 1617 idx += sizeof(struct txp_cmd_desc); 1618 if (idx == sc->sc_cmdring.size) 1619 idx = 0; 1620 1621 for (i = 0; i < in_extn; i++) { 1622 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1623 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1624 in_extp++; 1625 idx += sizeof(struct txp_cmd_desc); 1626 if (idx == sc->sc_cmdring.size) 1627 idx = 0; 1628 } 1629 1630 sc->sc_cmdring.lastwrite = idx; 1631 1632 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1633 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1634 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1635 1636 if (!wait) 1637 return (0); 1638 1639 for (i = 0; i < 10000; i++) { 1640 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1641 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1642 idx = le32toh(hv->hv_resp_read_idx); 1643 if (idx != le32toh(hv->hv_resp_write_idx)) { 1644 *rspp = NULL; 1645 if (txp_response(sc, idx, id, seq, rspp)) 1646 return (-1); 1647 if (*rspp != NULL) 1648 break; 1649 } 1650 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1651 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1652 DELAY(50); 1653 } 1654 if (i == 1000 || (*rspp) == NULL) { 1655 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1656 return (-1); 1657 } 1658 1659 return (0); 1660 } 1661 1662 int 1663 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq, 1664 struct txp_rsp_desc **rspp) 1665 { 1666 struct txp_hostvar *hv = sc->sc_hostvar; 1667 struct txp_rsp_desc *rsp; 1668 1669 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1670 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1671 1672 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1673 *rspp = (struct txp_rsp_desc *)malloc( 1674 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1675 M_DEVBUF, M_NOWAIT); 1676 if ((*rspp) == NULL) 1677 return (-1); 1678 txp_rsp_fixup(sc, rsp, *rspp); 1679 return (0); 1680 } 1681 1682 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1683 printf("%s: response error: id 0x%x\n", 1684 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1685 txp_rsp_fixup(sc, rsp, NULL); 1686 ridx = le32toh(hv->hv_resp_read_idx); 1687 continue; 1688 } 1689 1690 switch (le16toh(rsp->rsp_id)) { 1691 case TXP_CMD_CYCLE_STATISTICS: 1692 case TXP_CMD_MEDIA_STATUS_READ: 1693 break; 1694 case TXP_CMD_HELLO_RESPONSE: 1695 printf("%s: hello\n", TXP_DEVNAME(sc)); 1696 break; 1697 default: 1698 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1699 le16toh(rsp->rsp_id)); 1700 } 1701 1702 txp_rsp_fixup(sc, rsp, NULL); 1703 ridx = le32toh(hv->hv_resp_read_idx); 1704 hv->hv_resp_read_idx = le32toh(ridx); 1705 } 1706 1707 return (0); 1708 } 1709 1710 void 1711 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1712 struct txp_rsp_desc *dst) 1713 { 1714 struct txp_rsp_desc *src = rsp; 1715 struct txp_hostvar *hv = sc->sc_hostvar; 1716 u_int32_t i, ridx; 1717 1718 ridx = le32toh(hv->hv_resp_read_idx); 1719 1720 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1721 if (dst != NULL) 1722 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1723 ridx += sizeof(struct txp_rsp_desc); 1724 if (ridx == sc->sc_rspring.size) { 1725 src = sc->sc_rspring.base; 1726 ridx = 0; 1727 } else 1728 src++; 1729 sc->sc_rspring.lastwrite = ridx; 1730 hv->hv_resp_read_idx = htole32(ridx); 1731 } 1732 1733 hv->hv_resp_read_idx = htole32(ridx); 1734 } 1735 1736 int 1737 txp_cmd_desc_numfree(struct txp_softc *sc) 1738 { 1739 struct txp_hostvar *hv = sc->sc_hostvar; 1740 struct txp_boot_record *br = sc->sc_boot; 1741 u_int32_t widx, ridx, nfree; 1742 1743 widx = sc->sc_cmdring.lastwrite; 1744 ridx = le32toh(hv->hv_cmd_read_idx); 1745 1746 if (widx == ridx) { 1747 /* Ring is completely free */ 1748 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1749 } else { 1750 if (widx > ridx) 1751 nfree = le32toh(br->br_cmd_siz) - 1752 (widx - ridx + sizeof(struct txp_cmd_desc)); 1753 else 1754 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1755 } 1756 1757 return (nfree / sizeof(struct txp_cmd_desc)); 1758 } 1759 1760 void 1761 txp_stop(struct txp_softc *sc) 1762 { 1763 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1764 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1765 1766 if (callout_pending(&sc->sc_tick)) 1767 callout_stop(&sc->sc_tick); 1768 } 1769 1770 void 1771 txp_watchdog(struct ifnet *ifp) 1772 { 1773 } 1774 1775 int 1776 txp_ifmedia_upd(struct ifnet *ifp) 1777 { 1778 struct txp_softc *sc = ifp->if_softc; 1779 struct ifmedia *ifm = &sc->sc_ifmedia; 1780 u_int16_t new_xcvr; 1781 1782 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1783 return (EINVAL); 1784 1785 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1786 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1787 new_xcvr = TXP_XCVR_10_FDX; 1788 else 1789 new_xcvr = TXP_XCVR_10_HDX; 1790 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1791 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1792 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1793 new_xcvr = TXP_XCVR_100_FDX; 1794 else 1795 new_xcvr = TXP_XCVR_100_HDX; 1796 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1797 new_xcvr = TXP_XCVR_AUTO; 1798 } else 1799 return (EINVAL); 1800 1801 /* nothing to do */ 1802 if (sc->sc_xcvr == new_xcvr) 1803 return (0); 1804 1805 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1806 NULL, NULL, NULL, 0); 1807 sc->sc_xcvr = new_xcvr; 1808 1809 return (0); 1810 } 1811 1812 void 1813 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1814 { 1815 struct txp_softc *sc = ifp->if_softc; 1816 struct ifmedia *ifm = &sc->sc_ifmedia; 1817 u_int16_t bmsr, bmcr, anlpar; 1818 1819 ifmr->ifm_status = IFM_AVALID; 1820 ifmr->ifm_active = IFM_ETHER; 1821 1822 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1823 &bmsr, NULL, NULL, 1)) 1824 goto bail; 1825 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1826 &bmsr, NULL, NULL, 1)) 1827 goto bail; 1828 1829 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1830 &bmcr, NULL, NULL, 1)) 1831 goto bail; 1832 1833 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1834 &anlpar, NULL, NULL, 1)) 1835 goto bail; 1836 1837 if (bmsr & BMSR_LINK) 1838 ifmr->ifm_status |= IFM_ACTIVE; 1839 1840 if (bmcr & BMCR_ISO) { 1841 ifmr->ifm_active |= IFM_NONE; 1842 ifmr->ifm_status = 0; 1843 return; 1844 } 1845 1846 if (bmcr & BMCR_LOOP) 1847 ifmr->ifm_active |= IFM_LOOP; 1848 1849 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1850 if ((bmsr & BMSR_ACOMP) == 0) { 1851 ifmr->ifm_active |= IFM_NONE; 1852 return; 1853 } 1854 1855 if (anlpar & ANLPAR_TX_FD) 1856 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1857 else if (anlpar & ANLPAR_T4) 1858 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1859 else if (anlpar & ANLPAR_TX) 1860 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1861 else if (anlpar & ANLPAR_10_FD) 1862 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1863 else if (anlpar & ANLPAR_10) 1864 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1865 else 1866 ifmr->ifm_active |= IFM_NONE; 1867 } else 1868 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1869 return; 1870 1871 bail: 1872 ifmr->ifm_active |= IFM_NONE; 1873 ifmr->ifm_status &= ~IFM_AVALID; 1874 } 1875 1876 void 1877 txp_show_descriptor(void *d) 1878 { 1879 struct txp_cmd_desc *cmd = d; 1880 struct txp_rsp_desc *rsp = d; 1881 struct txp_tx_desc *txd = d; 1882 struct txp_frag_desc *frgd = d; 1883 1884 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1885 case CMD_FLAGS_TYPE_CMD: 1886 /* command descriptor */ 1887 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1888 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1889 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1890 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1891 break; 1892 case CMD_FLAGS_TYPE_RESP: 1893 /* response descriptor */ 1894 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1895 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1896 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1897 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1898 break; 1899 case CMD_FLAGS_TYPE_DATA: 1900 /* data header (assuming tx for now) */ 1901 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1902 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1903 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1904 break; 1905 case CMD_FLAGS_TYPE_FRAG: 1906 /* fragment descriptor */ 1907 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1908 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1909 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1910 break; 1911 default: 1912 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1913 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1914 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1915 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1916 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1917 break; 1918 } 1919 } 1920 1921 void 1922 txp_set_filter(struct txp_softc *sc) 1923 { 1924 struct ethercom *ac = &sc->sc_arpcom; 1925 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1926 u_int32_t crc, carry, hashbit, hash[2]; 1927 u_int16_t filter; 1928 u_int8_t octet; 1929 int i, j, mcnt = 0; 1930 struct ether_multi *enm; 1931 struct ether_multistep step; 1932 1933 if (ifp->if_flags & IFF_PROMISC) { 1934 filter = TXP_RXFILT_PROMISC; 1935 goto setit; 1936 } 1937 1938 again: 1939 filter = TXP_RXFILT_DIRECT; 1940 1941 if (ifp->if_flags & IFF_BROADCAST) 1942 filter |= TXP_RXFILT_BROADCAST; 1943 1944 if (ifp->if_flags & IFF_ALLMULTI) 1945 filter |= TXP_RXFILT_ALLMULTI; 1946 else { 1947 hash[0] = hash[1] = 0; 1948 1949 ETHER_FIRST_MULTI(step, ac, enm); 1950 while (enm != NULL) { 1951 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1952 ETHER_ADDR_LEN)) { 1953 /* 1954 * We must listen to a range of multicast 1955 * addresses. For now, just accept all 1956 * multicasts, rather than trying to set only 1957 * those filter bits needed to match the range. 1958 * (At this time, the only use of address 1959 * ranges is for IP multicast routing, for 1960 * which the range is big enough to require 1961 * all bits set.) 1962 */ 1963 ifp->if_flags |= IFF_ALLMULTI; 1964 goto again; 1965 } 1966 1967 mcnt++; 1968 crc = 0xffffffff; 1969 1970 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1971 octet = enm->enm_addrlo[i]; 1972 for (j = 0; j < 8; j++) { 1973 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1974 (octet & 1); 1975 crc <<= 1; 1976 octet >>= 1; 1977 if (carry) 1978 crc = (crc ^ TXP_POLYNOMIAL) | 1979 carry; 1980 } 1981 } 1982 hashbit = (u_int16_t)(crc & (64 - 1)); 1983 hash[hashbit / 32] |= (1 << hashbit % 32); 1984 ETHER_NEXT_MULTI(step, enm); 1985 } 1986 1987 if (mcnt > 0) { 1988 filter |= TXP_RXFILT_HASHMULTI; 1989 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1990 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1991 } 1992 } 1993 1994 setit: 1995 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1996 NULL, NULL, NULL, 1); 1997 } 1998 1999 void 2000 txp_capabilities(struct txp_softc *sc) 2001 { 2002 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2003 struct txp_rsp_desc *rsp = NULL; 2004 struct txp_ext_desc *ext; 2005 2006 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2007 goto out; 2008 2009 if (rsp->rsp_numdesc != 1) 2010 goto out; 2011 ext = (struct txp_ext_desc *)(rsp + 1); 2012 2013 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2014 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2015 2016 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2017 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2018 sc->sc_tx_capability |= OFFLOAD_VLAN; 2019 sc->sc_rx_capability |= OFFLOAD_VLAN; 2020 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2021 } 2022 2023 #if 0 2024 /* not ready yet */ 2025 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2026 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2027 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2028 ifp->if_capabilities |= IFCAP_IPSEC; 2029 } 2030 #endif 2031 2032 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2033 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2034 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2035 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2036 } 2037 2038 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2039 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2040 #ifdef TRY_TX_TCP_CSUM 2041 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2042 ifp->if_capabilities |= 2043 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2044 #endif 2045 } 2046 2047 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2048 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2049 #ifdef TRY_TX_UDP_CSUM 2050 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2051 ifp->if_capabilities |= 2052 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2053 #endif 2054 } 2055 2056 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2057 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2058 goto out; 2059 2060 out: 2061 if (rsp != NULL) 2062 free(rsp, M_DEVBUF); 2063 } 2064
Indexes created Tue Sep 30 20:09:53 GMT 2025