if_txp.c revision 1.61
1 /* $NetBSD: if_txp.c,v 1.61 2019/11/10 21:16:36 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.61 2019/11/10 21:16:36 chs Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 #include <net/if_media.h> 56 #include <net/bpf.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/pci/if_txpreg.h> 73 74 #include <dev/microcode/typhoon/3c990img.h> 75 76 /* 77 * These currently break the 3c990 firmware, hopefully will be resolved 78 * at some point. 79 */ 80 #undef TRY_TX_UDP_CSUM 81 #undef TRY_TX_TCP_CSUM 82 83 int txp_probe(device_t, cfdata_t, void *); 84 void txp_attach(device_t, device_t, void *); 85 int txp_intr(void *); 86 void txp_tick(void *); 87 bool txp_shutdown(device_t, int); 88 int txp_ioctl(struct ifnet *, u_long, void *); 89 void txp_start(struct ifnet *); 90 void txp_stop(struct txp_softc *); 91 void txp_init(struct txp_softc *); 92 void txp_watchdog(struct ifnet *); 93 94 int txp_chip_init(struct txp_softc *); 95 int txp_reset_adapter(struct txp_softc *); 96 int txp_download_fw(struct txp_softc *); 97 int txp_download_fw_wait(struct txp_softc *); 98 int txp_download_fw_section(struct txp_softc *, 99 const struct txp_fw_section_header *, int); 100 int txp_alloc_rings(struct txp_softc *); 101 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 102 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 103 void txp_set_filter(struct txp_softc *); 104 105 int txp_cmd_desc_numfree(struct txp_softc *); 106 int txp_command(struct txp_softc *, uint16_t, uint16_t, uint32_t, 107 uint32_t, uint16_t *, uint32_t *, uint32_t *, int); 108 int txp_command2(struct txp_softc *, uint16_t, uint16_t, 109 uint32_t, uint32_t, struct txp_ext_desc *, uint8_t, 110 struct txp_rsp_desc **, int); 111 int txp_response(struct txp_softc *, uint32_t, uint16_t, uint16_t, 112 struct txp_rsp_desc **); 113 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 114 struct txp_rsp_desc *); 115 void txp_capabilities(struct txp_softc *); 116 117 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 int txp_ifmedia_upd(struct ifnet *); 119 void txp_show_descriptor(void *); 120 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 121 struct txp_dma_alloc *); 122 void txp_rxbuf_reclaim(struct txp_softc *); 123 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 124 struct txp_dma_alloc *); 125 126 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 127 NULL, NULL); 128 129 const struct txp_pci_match { 130 int vid, did, flags; 131 } txp_devices[] = { 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 140 }; 141 142 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 143 144 static const struct { 145 uint16_t mask, value; 146 int flags; 147 } txp_subsysinfo[] = { 148 {0xf000, 0x2000, TXP_SERVERVERSION}, 149 {0x0100, 0x0100, TXP_FIBER}, 150 #if 0 /* information from 3com header, unused */ 151 {0x0010, 0x0010, /* secured firmware */}, 152 {0x0003, 0x0000, /* variable DES */}, 153 {0x0003, 0x0001, /* single DES - "95" */}, 154 {0x0003, 0x0002, /* triple DES - "97" */}, 155 #endif 156 }; 157 158 static const struct txp_pci_match * 159 txp_pcilookup(pcireg_t id) 160 { 161 int i; 162 163 for (i = 0; i < __arraycount(txp_devices); i++) 164 if (PCI_VENDOR(id) == txp_devices[i].vid && 165 PCI_PRODUCT(id) == txp_devices[i].did) 166 return &txp_devices[i]; 167 return (0); 168 } 169 170 int 171 txp_probe(device_t parent, cfdata_t match, void *aux) 172 { 173 struct pci_attach_args *pa = aux; 174 175 if (txp_pcilookup(pa->pa_id)) 176 return (1); 177 return (0); 178 } 179 180 void 181 txp_attach(device_t parent, device_t self, void *aux) 182 { 183 struct txp_softc *sc = device_private(self); 184 struct pci_attach_args *pa = aux; 185 pci_chipset_tag_t pc = pa->pa_pc; 186 pci_intr_handle_t ih; 187 const char *intrstr = NULL; 188 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 189 uint32_t command; 190 uint16_t p1; 191 uint32_t p2; 192 u_char enaddr[6]; 193 const struct txp_pci_match *match; 194 uint16_t subsys; 195 int i, flags; 196 char devinfo[256]; 197 char intrbuf[PCI_INTRSTR_LEN]; 198 199 sc->sc_dev = self; 200 sc->sc_cold = 1; 201 202 match = txp_pcilookup(pa->pa_id); 203 flags = match->flags; 204 if (match->flags & TXP_USESUBSYSTEM) { 205 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 206 PCI_SUBSYS_ID_REG)); 207 for (i = 0; 208 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 209 i++) 210 if ((subsys & txp_subsysinfo[i].mask) == 211 txp_subsysinfo[i].value) 212 flags |= txp_subsysinfo[i].flags; 213 } 214 sc->sc_flags = flags; 215 216 aprint_naive("\n"); 217 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 218 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM | TXP_SERVERVERSION)) == \ 219 (TXP_USESUBSYSTEM | TXP_SERVERVERSION) ? " (SVR)" : "") 220 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 221 device_xname(sc->sc_dev)); 222 223 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 224 225 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 226 aprint_error(": failed to enable bus mastering\n"); 227 return; 228 } 229 230 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 231 aprint_error(": failed to enable memory mapping\n"); 232 return; 233 } 234 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 235 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 236 aprint_error(": can't map mem space %d\n", 0); 237 return; 238 } 239 240 sc->sc_dmat = pa->pa_dmat; 241 242 /* 243 * Allocate our interrupt. 244 */ 245 if (pci_intr_map(pa, &ih)) { 246 aprint_error(": couldn't map interrupt\n"); 247 return; 248 } 249 250 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 251 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, txp_intr, sc, 252 device_xname(self)); 253 if (sc->sc_ih == NULL) { 254 aprint_error(": couldn't establish interrupt"); 255 if (intrstr != NULL) 256 aprint_normal(" at %s", intrstr); 257 aprint_normal("\n"); 258 return; 259 } 260 aprint_normal(": interrupting at %s\n", intrstr); 261 262 if (txp_chip_init(sc)) 263 goto cleanupintr; 264 265 if (txp_download_fw(sc)) 266 goto cleanupintr; 267 268 if (txp_alloc_rings(sc)) 269 goto cleanupintr; 270 271 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 272 NULL, NULL, NULL, 1)) 273 goto cleanupintr; 274 275 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 276 &p1, &p2, NULL, 1)) 277 goto cleanupintr; 278 279 p1 = htole16(p1); 280 enaddr[0] = ((uint8_t *)&p1)[1]; 281 enaddr[1] = ((uint8_t *)&p1)[0]; 282 p2 = htole32(p2); 283 enaddr[2] = ((uint8_t *)&p2)[3]; 284 enaddr[3] = ((uint8_t *)&p2)[2]; 285 enaddr[4] = ((uint8_t *)&p2)[1]; 286 enaddr[5] = ((uint8_t *)&p2)[0]; 287 288 aprint_normal_dev(self, "Ethernet address %s\n", 289 ether_sprintf(enaddr)); 290 sc->sc_cold = 0; 291 292 /* Initialize ifmedia structures. */ 293 sc->sc_arpcom.ec_ifmedia = &sc->sc_ifmedia; 294 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 295 if (flags & TXP_FIBER) { 296 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX, 297 0, NULL); 298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_HDX, 299 0, NULL); 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_FDX, 301 0, NULL); 302 } else { 303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 304 0, NULL); 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 314 0, NULL); 315 } 316 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 317 318 sc->sc_xcvr = TXP_XCVR_AUTO; 319 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 320 NULL, NULL, NULL, 0); 321 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 322 323 ifp->if_softc = sc; 324 ifp->if_mtu = ETHERMTU; 325 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 326 ifp->if_ioctl = txp_ioctl; 327 ifp->if_start = txp_start; 328 ifp->if_watchdog = txp_watchdog; 329 ifp->if_baudrate = 10000000; 330 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 331 IFQ_SET_READY(&ifp->if_snd); 332 ifp->if_capabilities = 0; 333 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 334 335 txp_capabilities(sc); 336 337 callout_init(&sc->sc_tick, 0); 338 callout_setfunc(&sc->sc_tick, txp_tick, sc); 339 340 /* 341 * Attach us everywhere 342 */ 343 if_attach(ifp); 344 if_deferred_start_init(ifp, NULL); 345 ether_ifattach(ifp, enaddr); 346 347 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 348 pmf_class_network_register(self, ifp); 349 else 350 aprint_error_dev(self, "couldn't establish power handler\n"); 351 352 return; 353 354 cleanupintr: 355 pci_intr_disestablish(pc, sc->sc_ih); 356 357 return; 358 359 } 360 361 int 362 txp_chip_init(struct txp_softc *sc) 363 { 364 /* disable interrupts */ 365 WRITE_REG(sc, TXP_IER, 0); 366 WRITE_REG(sc, TXP_IMR, 367 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 368 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 369 TXP_INT_LATCH); 370 371 /* ack all interrupts */ 372 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 373 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 374 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 375 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 376 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 377 378 if (txp_reset_adapter(sc)) 379 return (-1); 380 381 /* disable interrupts */ 382 WRITE_REG(sc, TXP_IER, 0); 383 WRITE_REG(sc, TXP_IMR, 384 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 385 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 386 TXP_INT_LATCH); 387 388 /* ack all interrupts */ 389 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 390 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 391 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 392 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 393 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 394 395 return (0); 396 } 397 398 int 399 txp_reset_adapter(struct txp_softc *sc) 400 { 401 uint32_t r; 402 int i; 403 404 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 405 DELAY(1000); 406 WRITE_REG(sc, TXP_SRR, 0); 407 408 /* Should wait max 6 seconds */ 409 for (i = 0; i < 6000; i++) { 410 r = READ_REG(sc, TXP_A2H_0); 411 if (r == STAT_WAITING_FOR_HOST_REQUEST) 412 break; 413 DELAY(1000); 414 } 415 416 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 417 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 418 return (-1); 419 } 420 421 return (0); 422 } 423 424 int 425 txp_download_fw(struct txp_softc *sc) 426 { 427 const struct txp_fw_file_header *fileheader; 428 const struct txp_fw_section_header *secthead; 429 int sect; 430 uint32_t r, i, ier, imr; 431 432 ier = READ_REG(sc, TXP_IER); 433 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 434 435 imr = READ_REG(sc, TXP_IMR); 436 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 437 438 for (i = 0; i < 10000; i++) { 439 r = READ_REG(sc, TXP_A2H_0); 440 if (r == STAT_WAITING_FOR_HOST_REQUEST) 441 break; 442 DELAY(50); 443 } 444 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 445 printf(": not waiting for host request\n"); 446 return (-1); 447 } 448 449 /* Ack the status */ 450 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 451 452 fileheader = (const struct txp_fw_file_header *)tc990image; 453 if (memcmp("TYPHOON", fileheader->magicid, 454 sizeof(fileheader->magicid))) { 455 printf(": fw invalid magic\n"); 456 return (-1); 457 } 458 459 /* Tell boot firmware to get ready for image */ 460 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 461 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 462 463 if (txp_download_fw_wait(sc)) { 464 printf("%s: fw wait failed, initial\n", 465 device_xname(sc->sc_dev)); 466 return (-1); 467 } 468 469 secthead = (const struct txp_fw_section_header *) 470 (((const uint8_t *)tc990image) + 471 sizeof(struct txp_fw_file_header)); 472 473 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 474 if (txp_download_fw_section(sc, secthead, sect)) 475 return (-1); 476 secthead = (const struct txp_fw_section_header *) 477 (((const uint8_t *)secthead) + le32toh(secthead->nbytes) + 478 sizeof(*secthead)); 479 } 480 481 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 482 483 for (i = 0; i < 10000; i++) { 484 r = READ_REG(sc, TXP_A2H_0); 485 if (r == STAT_WAITING_FOR_BOOT) 486 break; 487 DELAY(50); 488 } 489 if (r != STAT_WAITING_FOR_BOOT) { 490 printf(": not waiting for boot\n"); 491 return (-1); 492 } 493 494 WRITE_REG(sc, TXP_IER, ier); 495 WRITE_REG(sc, TXP_IMR, imr); 496 497 return (0); 498 } 499 500 int 501 txp_download_fw_wait(struct txp_softc *sc) 502 { 503 uint32_t i, r; 504 505 for (i = 0; i < 10000; i++) { 506 r = READ_REG(sc, TXP_ISR); 507 if (r & TXP_INT_A2H_0) 508 break; 509 DELAY(50); 510 } 511 512 if (!(r & TXP_INT_A2H_0)) { 513 printf(": fw wait failed comm0\n"); 514 return (-1); 515 } 516 517 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 518 519 r = READ_REG(sc, TXP_A2H_0); 520 if (r != STAT_WAITING_FOR_SEGMENT) { 521 printf(": fw not waiting for segment\n"); 522 return (-1); 523 } 524 return (0); 525 } 526 527 int 528 txp_download_fw_section(struct txp_softc *sc, 529 const struct txp_fw_section_header *sect, int sectnum) 530 { 531 struct txp_dma_alloc dma; 532 int rseg, err = 0; 533 struct mbuf m; 534 #ifdef INET 535 uint16_t csum; 536 #endif 537 538 /* Skip zero length sections */ 539 if (sect->nbytes == 0) 540 return (0); 541 542 /* Make sure we aren't past the end of the image */ 543 rseg = ((const uint8_t *)sect) - ((const uint8_t *)tc990image); 544 if (rseg >= sizeof(tc990image)) { 545 printf(": fw invalid section address, section %d\n", sectnum); 546 return (-1); 547 } 548 549 /* Make sure this section doesn't go past the end */ 550 rseg += le32toh(sect->nbytes); 551 if (rseg >= sizeof(tc990image)) { 552 printf(": fw truncated section %d\n", sectnum); 553 return (-1); 554 } 555 556 /* map a buffer, copy segment to it, get physaddr */ 557 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 558 printf(": fw dma malloc failed, section %d\n", sectnum); 559 return (-1); 560 } 561 562 memcpy(dma.dma_vaddr, ((const uint8_t *)sect) + sizeof(*sect), 563 le32toh(sect->nbytes)); 564 565 /* 566 * dummy up mbuf and verify section checksum 567 */ 568 m.m_type = MT_DATA; 569 m.m_next = m.m_nextpkt = NULL; 570 m.m_owner = NULL; 571 m.m_len = le32toh(sect->nbytes); 572 m.m_data = dma.dma_vaddr; 573 m.m_flags = 0; 574 #ifdef INET 575 csum = in_cksum(&m, le32toh(sect->nbytes)); 576 if (csum != sect->cksum) { 577 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 578 sectnum, sect->cksum, csum); 579 txp_dma_free(sc, &dma); 580 return -1; 581 } 582 #endif 583 584 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 585 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 586 587 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 588 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 589 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 590 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 591 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 592 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 593 594 if (txp_download_fw_wait(sc)) { 595 printf("%s: fw wait failed, section %d\n", 596 device_xname(sc->sc_dev), sectnum); 597 err = -1; 598 } 599 600 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 601 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 602 603 txp_dma_free(sc, &dma); 604 return (err); 605 } 606 607 int 608 txp_intr(void *vsc) 609 { 610 struct txp_softc *sc = vsc; 611 struct txp_hostvar *hv = sc->sc_hostvar; 612 uint32_t isr; 613 int claimed = 0; 614 615 /* mask all interrupts */ 616 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 617 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 618 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 619 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 620 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 621 622 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 623 sizeof(struct txp_hostvar), 624 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 625 626 isr = READ_REG(sc, TXP_ISR); 627 while (isr) { 628 claimed = 1; 629 WRITE_REG(sc, TXP_ISR, isr); 630 631 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 632 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 633 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 634 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 635 636 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 637 txp_rxbuf_reclaim(sc); 638 639 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 640 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 641 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 642 643 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 644 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 645 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 646 647 isr = READ_REG(sc, TXP_ISR); 648 } 649 650 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 651 sizeof(struct txp_hostvar), 652 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 653 654 /* unmask all interrupts */ 655 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 656 657 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 658 659 return (claimed); 660 } 661 662 void 663 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 664 struct txp_dma_alloc *dma) 665 { 666 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 667 struct txp_rx_desc *rxd; 668 struct mbuf *m; 669 struct txp_swdesc *sd; 670 uint32_t roff, woff; 671 int sumflags = 0; 672 int idx; 673 674 roff = le32toh(*r->r_roff); 675 woff = le32toh(*r->r_woff); 676 idx = roff / sizeof(struct txp_rx_desc); 677 rxd = r->r_desc + idx; 678 679 while (roff != woff) { 680 681 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 682 idx * sizeof(struct txp_rx_desc), 683 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 684 685 if (rxd->rx_flags & RX_FLAGS_ERROR) { 686 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 687 le32toh(rxd->rx_stat)); 688 ifp->if_ierrors++; 689 goto next; 690 } 691 692 /* retrieve stashed pointer */ 693 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 694 695 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 696 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 697 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 698 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 699 m = sd->sd_mbuf; 700 free(sd, M_DEVBUF); 701 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 702 703 #ifdef __STRICT_ALIGNMENT 704 { 705 /* 706 * XXX Nice chip, except it won't accept "off by 2" 707 * buffers, so we're force to copy. Supposedly 708 * this will be fixed in a newer firmware rev 709 * and this will be temporary. 710 */ 711 struct mbuf *mnew; 712 713 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 714 if (mnew == NULL) { 715 m_freem(m); 716 goto next; 717 } 718 if (m->m_len > (MHLEN - 2)) { 719 MCLGET(mnew, M_DONTWAIT); 720 if (!(mnew->m_flags & M_EXT)) { 721 m_freem(mnew); 722 m_freem(m); 723 goto next; 724 } 725 } 726 m_set_rcvif(mnew, ifp); 727 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 728 mnew->m_data += 2; 729 memcpy(mnew->m_data, m->m_data, m->m_len); 730 m_freem(m); 731 m = mnew; 732 } 733 #endif 734 735 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 736 sumflags |= (M_CSUM_IPv4 | M_CSUM_IPv4_BAD); 737 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 738 sumflags |= M_CSUM_IPv4; 739 740 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 741 sumflags |= (M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD); 742 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 743 sumflags |= M_CSUM_TCPv4; 744 745 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 746 sumflags |= (M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD); 747 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 748 sumflags |= M_CSUM_UDPv4; 749 750 m->m_pkthdr.csum_flags = sumflags; 751 752 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 753 vlan_set_tag(m, htons(rxd->rx_vlan >> 16)); 754 } 755 756 if_percpuq_enqueue(ifp->if_percpuq, m); 757 758 next: 759 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 760 idx * sizeof(struct txp_rx_desc), 761 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 762 763 roff += sizeof(struct txp_rx_desc); 764 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 765 idx = 0; 766 roff = 0; 767 rxd = r->r_desc; 768 } else { 769 idx++; 770 rxd++; 771 } 772 woff = le32toh(*r->r_woff); 773 } 774 775 *r->r_roff = htole32(woff); 776 } 777 778 void 779 txp_rxbuf_reclaim(struct txp_softc *sc) 780 { 781 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 782 struct txp_hostvar *hv = sc->sc_hostvar; 783 struct txp_rxbuf_desc *rbd; 784 struct txp_swdesc *sd; 785 uint32_t i, end; 786 787 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 788 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 789 790 if (++i == RXBUF_ENTRIES) 791 i = 0; 792 793 rbd = sc->sc_rxbufs + i; 794 795 while (i != end) { 796 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 797 M_DEVBUF, M_NOWAIT); 798 if (sd == NULL) 799 break; 800 801 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 802 if (sd->sd_mbuf == NULL) 803 goto err_sd; 804 805 MCLGET(sd->sd_mbuf, M_DONTWAIT); 806 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 807 goto err_mbuf; 808 m_set_rcvif(sd->sd_mbuf, ifp); 809 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 810 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 811 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 812 goto err_mbuf; 813 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 814 BUS_DMA_NOWAIT)) { 815 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 816 goto err_mbuf; 817 } 818 819 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 820 i * sizeof(struct txp_rxbuf_desc), 821 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 822 823 /* stash away pointer */ 824 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 825 826 rbd->rb_paddrlo = ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) 827 & 0xffffffff; 828 rbd->rb_paddrhi = ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) 829 >> 32; 830 831 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 832 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 833 834 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 835 i * sizeof(struct txp_rxbuf_desc), 836 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 837 838 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 839 840 if (++i == RXBUF_ENTRIES) { 841 i = 0; 842 rbd = sc->sc_rxbufs; 843 } else 844 rbd++; 845 } 846 return; 847 848 err_mbuf: 849 m_freem(sd->sd_mbuf); 850 err_sd: 851 free(sd, M_DEVBUF); 852 } 853 854 /* 855 * Reclaim mbufs and entries from a transmit ring. 856 */ 857 void 858 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 859 struct txp_dma_alloc *dma) 860 { 861 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 862 uint32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 863 uint32_t cons = r->r_cons, cnt = r->r_cnt; 864 struct txp_tx_desc *txd = r->r_desc + cons; 865 struct txp_swdesc *sd = sc->sc_txd + cons; 866 struct mbuf *m; 867 868 while (cons != idx) { 869 if (cnt == 0) 870 break; 871 872 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 873 cons * sizeof(struct txp_tx_desc), 874 sizeof(struct txp_tx_desc), 875 BUS_DMASYNC_POSTWRITE); 876 877 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 878 TX_FLAGS_TYPE_DATA) { 879 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 880 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 881 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 882 m = sd->sd_mbuf; 883 if (m != NULL) { 884 m_freem(m); 885 txd->tx_addrlo = 0; 886 txd->tx_addrhi = 0; 887 ifp->if_opackets++; 888 } 889 } 890 ifp->if_flags &= ~IFF_OACTIVE; 891 892 if (++cons == TX_ENTRIES) { 893 txd = r->r_desc; 894 cons = 0; 895 sd = sc->sc_txd; 896 } else { 897 txd++; 898 sd++; 899 } 900 901 cnt--; 902 } 903 904 r->r_cons = cons; 905 r->r_cnt = cnt; 906 if (cnt == 0) 907 ifp->if_timer = 0; 908 } 909 910 bool 911 txp_shutdown(device_t self, int howto) 912 { 913 struct txp_softc *sc; 914 915 sc = device_private(self); 916 917 /* mask all interrupts */ 918 WRITE_REG(sc, TXP_IMR, 919 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 920 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 921 TXP_INT_LATCH); 922 923 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 924 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 925 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 926 927 return true; 928 } 929 930 int 931 txp_alloc_rings(struct txp_softc *sc) 932 { 933 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 934 struct txp_boot_record *boot; 935 struct txp_swdesc *sd; 936 uint32_t r; 937 int i, j, nb; 938 939 /* boot record */ 940 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 941 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 942 printf(": can't allocate boot record\n"); 943 return (-1); 944 } 945 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 946 memset(boot, 0, sizeof(*boot)); 947 sc->sc_boot = boot; 948 949 /* host variables */ 950 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 951 BUS_DMA_COHERENT)) { 952 printf(": can't allocate host ring\n"); 953 goto bail_boot; 954 } 955 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 956 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 957 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 958 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 959 960 /* high priority tx ring */ 961 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 962 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 963 printf(": can't allocate high tx ring\n"); 964 goto bail_host; 965 } 966 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 967 sizeof(struct txp_tx_desc) * TX_ENTRIES); 968 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 969 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 970 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 971 sc->sc_txhir.r_reg = TXP_H2A_1; 972 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 973 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 974 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 975 for (i = 0; i < TX_ENTRIES; i++) { 976 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 977 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 978 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 979 for (j = 0; j < i; j++) { 980 bus_dmamap_destroy(sc->sc_dmat, 981 sc->sc_txd[j].sd_map); 982 sc->sc_txd[j].sd_map = NULL; 983 } 984 goto bail_txhiring; 985 } 986 } 987 988 /* low priority tx ring */ 989 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 990 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 991 printf(": can't allocate low tx ring\n"); 992 goto bail_txhiring; 993 } 994 memset(sc->sc_txloring_dma.dma_vaddr, 0, 995 sizeof(struct txp_tx_desc) * TX_ENTRIES); 996 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 997 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 998 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 999 sc->sc_txlor.r_reg = TXP_H2A_3; 1000 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1001 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1002 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1003 1004 /* high priority rx ring */ 1005 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1006 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1007 printf(": can't allocate high rx ring\n"); 1008 goto bail_txloring; 1009 } 1010 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1011 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1012 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1013 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1014 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1015 sc->sc_rxhir.r_desc = 1016 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1017 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1018 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1019 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1020 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1021 1022 /* low priority ring */ 1023 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1024 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1025 printf(": can't allocate low rx ring\n"); 1026 goto bail_rxhiring; 1027 } 1028 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1029 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1030 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1031 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1032 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1033 sc->sc_rxlor.r_desc = 1034 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1035 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1036 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1037 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1038 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1039 1040 /* command ring */ 1041 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1042 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1043 printf(": can't allocate command ring\n"); 1044 goto bail_rxloring; 1045 } 1046 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1047 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1048 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1049 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1050 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1051 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1052 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1053 sc->sc_cmdring.lastwrite = 0; 1054 1055 /* response ring */ 1056 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1057 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1058 printf(": can't allocate response ring\n"); 1059 goto bail_cmdring; 1060 } 1061 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1062 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1063 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1064 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1065 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1066 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1067 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1068 sc->sc_rspring.lastwrite = 0; 1069 1070 /* receive buffer ring */ 1071 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1072 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1073 printf(": can't allocate rx buffer ring\n"); 1074 goto bail_rspring; 1075 } 1076 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1077 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1078 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1079 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1080 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1081 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1082 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1083 sd = malloc(sizeof(struct txp_swdesc), M_DEVBUF, M_WAITOK); 1084 /* stash away pointer */ 1085 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, 1086 sizeof(sd)); 1087 1088 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1089 if (sd->sd_mbuf == NULL) { 1090 goto bail_rxbufring; 1091 } 1092 1093 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1094 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1095 goto bail_rxbufring; 1096 } 1097 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1098 m_set_rcvif(sd->sd_mbuf, ifp); 1099 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1100 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1101 goto bail_rxbufring; 1102 } 1103 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1104 BUS_DMA_NOWAIT)) { 1105 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1106 goto bail_rxbufring; 1107 } 1108 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1109 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1110 1111 1112 sc->sc_rxbufs[nb].rb_paddrlo = 1113 ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1114 sc->sc_rxbufs[nb].rb_paddrhi = 1115 ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1116 } 1117 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1118 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1119 BUS_DMASYNC_PREWRITE); 1120 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1121 sizeof(struct txp_rxbuf_desc)); 1122 1123 /* zero dma */ 1124 if (txp_dma_malloc(sc, sizeof(uint32_t), &sc->sc_zero_dma, 1125 BUS_DMA_COHERENT)) { 1126 printf(": can't allocate response ring\n"); 1127 goto bail_rxbufring; 1128 } 1129 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(uint32_t)); 1130 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1131 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1132 1133 /* See if it's waiting for boot, and try to boot it */ 1134 for (i = 0; i < 10000; i++) { 1135 r = READ_REG(sc, TXP_A2H_0); 1136 if (r == STAT_WAITING_FOR_BOOT) 1137 break; 1138 DELAY(50); 1139 } 1140 if (r != STAT_WAITING_FOR_BOOT) { 1141 printf(": not waiting for boot\n"); 1142 goto bail; 1143 } 1144 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1145 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1146 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1147 1148 /* See if it booted */ 1149 for (i = 0; i < 10000; i++) { 1150 r = READ_REG(sc, TXP_A2H_0); 1151 if (r == STAT_RUNNING) 1152 break; 1153 DELAY(50); 1154 } 1155 if (r != STAT_RUNNING) { 1156 printf(": fw not running\n"); 1157 goto bail; 1158 } 1159 1160 /* Clear TX and CMD ring write registers */ 1161 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1162 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1163 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1164 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1165 1166 return (0); 1167 1168 bail: 1169 txp_dma_free(sc, &sc->sc_zero_dma); 1170 bail_rxbufring: 1171 if (nb == RXBUF_ENTRIES) 1172 nb--; 1173 for (i = 0; i <= nb; i++) { 1174 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1175 sizeof(sd)); 1176 if (sd) 1177 free(sd, M_DEVBUF); 1178 } 1179 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1180 bail_rspring: 1181 txp_dma_free(sc, &sc->sc_rspring_dma); 1182 bail_cmdring: 1183 txp_dma_free(sc, &sc->sc_cmdring_dma); 1184 bail_rxloring: 1185 txp_dma_free(sc, &sc->sc_rxloring_dma); 1186 bail_rxhiring: 1187 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1188 bail_txloring: 1189 txp_dma_free(sc, &sc->sc_txloring_dma); 1190 bail_txhiring: 1191 txp_dma_free(sc, &sc->sc_txhiring_dma); 1192 bail_host: 1193 txp_dma_free(sc, &sc->sc_host_dma); 1194 bail_boot: 1195 txp_dma_free(sc, &sc->sc_boot_dma); 1196 return (-1); 1197 } 1198 1199 int 1200 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1201 struct txp_dma_alloc *dma, int mapflags) 1202 { 1203 int r; 1204 1205 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1206 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1207 goto fail_0; 1208 1209 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1210 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1211 goto fail_1; 1212 1213 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1214 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1215 goto fail_2; 1216 1217 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1218 size, NULL, BUS_DMA_NOWAIT)) != 0) 1219 goto fail_3; 1220 1221 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1222 return (0); 1223 1224 fail_3: 1225 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1226 fail_2: 1227 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1228 fail_1: 1229 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1230 fail_0: 1231 return (r); 1232 } 1233 1234 void 1235 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1236 { 1237 bus_size_t mapsize = dma->dma_map->dm_mapsize; 1238 1239 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1240 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, mapsize); 1241 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1242 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1243 } 1244 1245 int 1246 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1247 { 1248 struct txp_softc *sc = ifp->if_softc; 1249 struct ifaddr *ifa = (struct ifaddr *)data; 1250 int s, error = 0; 1251 1252 s = splnet(); 1253 1254 #if 0 1255 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1256 splx(s); 1257 return error; 1258 } 1259 #endif 1260 1261 switch (command) { 1262 case SIOCINITIFADDR: 1263 ifp->if_flags |= IFF_UP; 1264 txp_init(sc); 1265 switch (ifa->ifa_addr->sa_family) { 1266 #ifdef INET 1267 case AF_INET: 1268 arp_ifinit(ifp, ifa); 1269 break; 1270 #endif /* INET */ 1271 default: 1272 break; 1273 } 1274 break; 1275 case SIOCSIFFLAGS: 1276 if ((error = ifioctl_common(ifp, command, data)) != 0) 1277 break; 1278 if (ifp->if_flags & IFF_UP) { 1279 txp_init(sc); 1280 } else { 1281 if (ifp->if_flags & IFF_RUNNING) 1282 txp_stop(sc); 1283 } 1284 break; 1285 case SIOCADDMULTI: 1286 case SIOCDELMULTI: 1287 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1288 break; 1289 1290 error = 0; 1291 1292 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1293 ; 1294 else if (ifp->if_flags & IFF_RUNNING) { 1295 /* 1296 * Multicast list has changed; set the hardware 1297 * filter accordingly. 1298 */ 1299 txp_set_filter(sc); 1300 } 1301 break; 1302 default: 1303 error = ether_ioctl(ifp, command, data); 1304 break; 1305 } 1306 1307 splx(s); 1308 1309 return (error); 1310 } 1311 1312 void 1313 txp_init(struct txp_softc *sc) 1314 { 1315 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1316 int s; 1317 1318 txp_stop(sc); 1319 1320 s = splnet(); 1321 1322 txp_set_filter(sc); 1323 1324 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1325 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1326 1327 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1328 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1329 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1330 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1331 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1332 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1333 1334 ifp->if_flags |= IFF_RUNNING; 1335 ifp->if_flags &= ~IFF_OACTIVE; 1336 ifp->if_timer = 0; 1337 1338 if (!callout_pending(&sc->sc_tick)) 1339 callout_schedule(&sc->sc_tick, hz); 1340 1341 splx(s); 1342 } 1343 1344 void 1345 txp_tick(void *vsc) 1346 { 1347 struct txp_softc *sc = vsc; 1348 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1349 struct txp_rsp_desc *rsp = NULL; 1350 struct txp_ext_desc *ext; 1351 int s; 1352 1353 s = splnet(); 1354 txp_rxbuf_reclaim(sc); 1355 1356 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1357 &rsp, 1)) 1358 goto out; 1359 if (rsp->rsp_numdesc != 6) 1360 goto out; 1361 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1362 NULL, NULL, NULL, 1)) 1363 goto out; 1364 ext = (struct txp_ext_desc *)(rsp + 1); 1365 1366 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1367 ext[4].ext_1 + ext[4].ext_4; 1368 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1369 ext[2].ext_1; 1370 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1371 ext[1].ext_3; 1372 ifp->if_opackets += rsp->rsp_par2; 1373 1374 out: 1375 if (rsp != NULL) 1376 free(rsp, M_DEVBUF); 1377 1378 splx(s); 1379 callout_schedule(&sc->sc_tick, hz); 1380 } 1381 1382 void 1383 txp_start(struct ifnet *ifp) 1384 { 1385 struct txp_softc *sc = ifp->if_softc; 1386 struct txp_tx_ring *r = &sc->sc_txhir; 1387 struct txp_tx_desc *txd; 1388 int txdidx; 1389 struct txp_frag_desc *fxd; 1390 struct mbuf *m, *mnew; 1391 struct txp_swdesc *sd; 1392 uint32_t firstprod, firstcnt, prod, cnt, i; 1393 1394 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1395 return; 1396 1397 prod = r->r_prod; 1398 cnt = r->r_cnt; 1399 1400 while (1) { 1401 IFQ_POLL(&ifp->if_snd, m); 1402 if (m == NULL) 1403 break; 1404 mnew = NULL; 1405 1406 firstprod = prod; 1407 firstcnt = cnt; 1408 1409 sd = sc->sc_txd + prod; 1410 sd->sd_mbuf = m; 1411 1412 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1413 BUS_DMA_NOWAIT)) { 1414 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1415 if (mnew == NULL) 1416 goto oactive1; 1417 if (m->m_pkthdr.len > MHLEN) { 1418 MCLGET(mnew, M_DONTWAIT); 1419 if ((mnew->m_flags & M_EXT) == 0) { 1420 m_freem(mnew); 1421 goto oactive1; 1422 } 1423 } 1424 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1425 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1426 IFQ_DEQUEUE(&ifp->if_snd, m); 1427 m_freem(m); 1428 m = mnew; 1429 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1430 BUS_DMA_NOWAIT)) 1431 goto oactive1; 1432 } 1433 1434 if ((TX_ENTRIES - cnt) < 4) 1435 goto oactive; 1436 1437 txd = r->r_desc + prod; 1438 txdidx = prod; 1439 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1440 txd->tx_numdesc = 0; 1441 txd->tx_addrlo = 0; 1442 txd->tx_addrhi = 0; 1443 txd->tx_totlen = m->m_pkthdr.len; 1444 txd->tx_pflags = 0; 1445 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1446 1447 if (++prod == TX_ENTRIES) 1448 prod = 0; 1449 1450 if (++cnt >= (TX_ENTRIES - 4)) 1451 goto oactive; 1452 1453 if (vlan_has_tag(m)) 1454 txd->tx_pflags = TX_PFLAGS_VLAN | 1455 (htons(vlan_get_tag(m)) << TX_PFLAGS_VLANTAG_S); 1456 1457 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1458 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1459 #ifdef TRY_TX_TCP_CSUM 1460 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1461 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1462 #endif 1463 #ifdef TRY_TX_UDP_CSUM 1464 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1465 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1466 #endif 1467 1468 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1469 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1470 1471 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1472 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1473 if (++cnt >= (TX_ENTRIES - 4)) { 1474 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1475 0, sd->sd_map->dm_mapsize, 1476 BUS_DMASYNC_POSTWRITE); 1477 goto oactive; 1478 } 1479 1480 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1481 FRAG_FLAGS_VALID; 1482 fxd->frag_rsvd1 = 0; 1483 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1484 fxd->frag_addrlo = 1485 ((uint64_t)sd->sd_map->dm_segs[i].ds_addr) & 1486 0xffffffff; 1487 fxd->frag_addrhi = 1488 ((uint64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1489 32; 1490 fxd->frag_rsvd2 = 0; 1491 1492 bus_dmamap_sync(sc->sc_dmat, 1493 sc->sc_txhiring_dma.dma_map, 1494 prod * sizeof(struct txp_frag_desc), 1495 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1496 1497 if (++prod == TX_ENTRIES) { 1498 fxd = (struct txp_frag_desc *)r->r_desc; 1499 prod = 0; 1500 } else 1501 fxd++; 1502 1503 } 1504 1505 /* 1506 * if mnew isn't NULL, we already dequeued and copied 1507 * the packet. 1508 */ 1509 if (mnew == NULL) 1510 IFQ_DEQUEUE(&ifp->if_snd, m); 1511 1512 ifp->if_timer = 5; 1513 1514 bpf_mtap(ifp, m, BPF_D_OUT); 1515 1516 txd->tx_flags |= TX_FLAGS_VALID; 1517 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1518 txdidx * sizeof(struct txp_tx_desc), 1519 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1520 1521 #if 0 1522 { 1523 struct mbuf *mx; 1524 int i; 1525 1526 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1527 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1528 txd->tx_pflags); 1529 for (mx = m; mx != NULL; mx = mx->m_next) { 1530 for (i = 0; i < mx->m_len; i++) { 1531 printf(":%02x", 1532 (uint8_t)m->m_data[i]); 1533 } 1534 } 1535 printf("\n"); 1536 } 1537 #endif 1538 1539 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1540 } 1541 1542 r->r_prod = prod; 1543 r->r_cnt = cnt; 1544 return; 1545 1546 oactive: 1547 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1548 oactive1: 1549 ifp->if_flags |= IFF_OACTIVE; 1550 r->r_prod = firstprod; 1551 r->r_cnt = firstcnt; 1552 } 1553 1554 /* 1555 * Handle simple commands sent to the typhoon 1556 */ 1557 int 1558 txp_command(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1559 uint32_t in3, uint16_t *out1, uint32_t *out2, uint32_t *out3, int wait) 1560 { 1561 struct txp_rsp_desc *rsp = NULL; 1562 1563 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1564 return (-1); 1565 1566 if (!wait) 1567 return (0); 1568 1569 if (out1 != NULL) 1570 *out1 = le16toh(rsp->rsp_par1); 1571 if (out2 != NULL) 1572 *out2 = le32toh(rsp->rsp_par2); 1573 if (out3 != NULL) 1574 *out3 = le32toh(rsp->rsp_par3); 1575 free(rsp, M_DEVBUF); 1576 return (0); 1577 } 1578 1579 int 1580 txp_command2(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1581 uint32_t in3, struct txp_ext_desc *in_extp, uint8_t in_extn, 1582 struct txp_rsp_desc **rspp, int wait) 1583 { 1584 struct txp_hostvar *hv = sc->sc_hostvar; 1585 struct txp_cmd_desc *cmd; 1586 struct txp_ext_desc *ext; 1587 uint32_t idx, i; 1588 uint16_t seq; 1589 1590 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1591 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1592 return (-1); 1593 } 1594 1595 idx = sc->sc_cmdring.lastwrite; 1596 cmd = (struct txp_cmd_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1597 memset(cmd, 0, sizeof(*cmd)); 1598 1599 cmd->cmd_numdesc = in_extn; 1600 seq = sc->sc_seq++; 1601 cmd->cmd_seq = htole16(seq); 1602 cmd->cmd_id = htole16(id); 1603 cmd->cmd_par1 = htole16(in1); 1604 cmd->cmd_par2 = htole32(in2); 1605 cmd->cmd_par3 = htole32(in3); 1606 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1607 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1608 1609 idx += sizeof(struct txp_cmd_desc); 1610 if (idx == sc->sc_cmdring.size) 1611 idx = 0; 1612 1613 for (i = 0; i < in_extn; i++) { 1614 ext = (struct txp_ext_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1615 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1616 in_extp++; 1617 idx += sizeof(struct txp_cmd_desc); 1618 if (idx == sc->sc_cmdring.size) 1619 idx = 0; 1620 } 1621 1622 sc->sc_cmdring.lastwrite = idx; 1623 1624 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1625 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1626 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1627 1628 if (!wait) 1629 return (0); 1630 1631 for (i = 0; i < 10000; i++) { 1632 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1633 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1634 idx = le32toh(hv->hv_resp_read_idx); 1635 if (idx != le32toh(hv->hv_resp_write_idx)) { 1636 *rspp = NULL; 1637 if (txp_response(sc, idx, id, seq, rspp)) 1638 return (-1); 1639 if (*rspp != NULL) 1640 break; 1641 } 1642 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1643 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1644 DELAY(50); 1645 } 1646 if (i == 1000 || (*rspp) == NULL) { 1647 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1648 return (-1); 1649 } 1650 1651 return (0); 1652 } 1653 1654 int 1655 txp_response(struct txp_softc *sc, uint32_t ridx, uint16_t id, uint16_t seq, 1656 struct txp_rsp_desc **rspp) 1657 { 1658 struct txp_hostvar *hv = sc->sc_hostvar; 1659 struct txp_rsp_desc *rsp; 1660 1661 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1662 rsp = (struct txp_rsp_desc *)(((uint8_t *)sc->sc_rspring.base) + ridx); 1663 1664 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1665 *rspp = (struct txp_rsp_desc *)malloc( 1666 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1667 M_DEVBUF, M_NOWAIT); 1668 if ((*rspp) == NULL) 1669 return (-1); 1670 txp_rsp_fixup(sc, rsp, *rspp); 1671 return (0); 1672 } 1673 1674 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1675 printf("%s: response error: id 0x%x\n", 1676 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1677 txp_rsp_fixup(sc, rsp, NULL); 1678 ridx = le32toh(hv->hv_resp_read_idx); 1679 continue; 1680 } 1681 1682 switch (le16toh(rsp->rsp_id)) { 1683 case TXP_CMD_CYCLE_STATISTICS: 1684 case TXP_CMD_MEDIA_STATUS_READ: 1685 break; 1686 case TXP_CMD_HELLO_RESPONSE: 1687 printf("%s: hello\n", TXP_DEVNAME(sc)); 1688 break; 1689 default: 1690 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1691 le16toh(rsp->rsp_id)); 1692 } 1693 1694 txp_rsp_fixup(sc, rsp, NULL); 1695 ridx = le32toh(hv->hv_resp_read_idx); 1696 hv->hv_resp_read_idx = le32toh(ridx); 1697 } 1698 1699 return (0); 1700 } 1701 1702 void 1703 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1704 struct txp_rsp_desc *dst) 1705 { 1706 struct txp_rsp_desc *src = rsp; 1707 struct txp_hostvar *hv = sc->sc_hostvar; 1708 uint32_t i, ridx; 1709 1710 ridx = le32toh(hv->hv_resp_read_idx); 1711 1712 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1713 if (dst != NULL) 1714 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1715 ridx += sizeof(struct txp_rsp_desc); 1716 if (ridx == sc->sc_rspring.size) { 1717 src = sc->sc_rspring.base; 1718 ridx = 0; 1719 } else 1720 src++; 1721 sc->sc_rspring.lastwrite = ridx; 1722 hv->hv_resp_read_idx = htole32(ridx); 1723 } 1724 1725 hv->hv_resp_read_idx = htole32(ridx); 1726 } 1727 1728 int 1729 txp_cmd_desc_numfree(struct txp_softc *sc) 1730 { 1731 struct txp_hostvar *hv = sc->sc_hostvar; 1732 struct txp_boot_record *br = sc->sc_boot; 1733 uint32_t widx, ridx, nfree; 1734 1735 widx = sc->sc_cmdring.lastwrite; 1736 ridx = le32toh(hv->hv_cmd_read_idx); 1737 1738 if (widx == ridx) { 1739 /* Ring is completely free */ 1740 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1741 } else { 1742 if (widx > ridx) 1743 nfree = le32toh(br->br_cmd_siz) - 1744 (widx - ridx + sizeof(struct txp_cmd_desc)); 1745 else 1746 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1747 } 1748 1749 return (nfree / sizeof(struct txp_cmd_desc)); 1750 } 1751 1752 void 1753 txp_stop(struct txp_softc *sc) 1754 { 1755 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1756 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1757 1758 if (callout_pending(&sc->sc_tick)) 1759 callout_stop(&sc->sc_tick); 1760 } 1761 1762 void 1763 txp_watchdog(struct ifnet *ifp) 1764 { 1765 } 1766 1767 int 1768 txp_ifmedia_upd(struct ifnet *ifp) 1769 { 1770 struct txp_softc *sc = ifp->if_softc; 1771 struct ifmedia *ifm = &sc->sc_ifmedia; 1772 uint16_t new_xcvr; 1773 1774 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1775 return (EINVAL); 1776 1777 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1778 if ((ifm->ifm_media & IFM_FDX) != 0) 1779 new_xcvr = TXP_XCVR_10_FDX; 1780 else 1781 new_xcvr = TXP_XCVR_10_HDX; 1782 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1783 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1784 if ((ifm->ifm_media & IFM_FDX) != 0) 1785 new_xcvr = TXP_XCVR_100_FDX; 1786 else 1787 new_xcvr = TXP_XCVR_100_HDX; 1788 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1789 new_xcvr = TXP_XCVR_AUTO; 1790 } else 1791 return (EINVAL); 1792 1793 /* nothing to do */ 1794 if (sc->sc_xcvr == new_xcvr) 1795 return (0); 1796 1797 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1798 NULL, NULL, NULL, 0); 1799 sc->sc_xcvr = new_xcvr; 1800 1801 return (0); 1802 } 1803 1804 void 1805 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1806 { 1807 struct txp_softc *sc = ifp->if_softc; 1808 struct ifmedia *ifm = &sc->sc_ifmedia; 1809 uint16_t bmsr, bmcr, anlpar; 1810 1811 ifmr->ifm_status = IFM_AVALID; 1812 ifmr->ifm_active = IFM_ETHER; 1813 1814 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1815 &bmsr, NULL, NULL, 1)) 1816 goto bail; 1817 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1818 &bmsr, NULL, NULL, 1)) 1819 goto bail; 1820 1821 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1822 &bmcr, NULL, NULL, 1)) 1823 goto bail; 1824 1825 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1826 &anlpar, NULL, NULL, 1)) 1827 goto bail; 1828 1829 if (bmsr & BMSR_LINK) 1830 ifmr->ifm_status |= IFM_ACTIVE; 1831 1832 if (bmcr & BMCR_ISO) { 1833 ifmr->ifm_active |= IFM_NONE; 1834 ifmr->ifm_status = 0; 1835 return; 1836 } 1837 1838 if (bmcr & BMCR_LOOP) 1839 ifmr->ifm_active |= IFM_LOOP; 1840 1841 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1842 if ((bmsr & BMSR_ACOMP) == 0) { 1843 ifmr->ifm_active |= IFM_NONE; 1844 return; 1845 } 1846 1847 if (anlpar & ANLPAR_TX_FD) 1848 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 1849 else if (anlpar & ANLPAR_T4) 1850 ifmr->ifm_active |= IFM_100_T4 | IFM_HDX; 1851 else if (anlpar & ANLPAR_TX) 1852 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 1853 else if (anlpar & ANLPAR_10_FD) 1854 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 1855 else if (anlpar & ANLPAR_10) 1856 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 1857 else 1858 ifmr->ifm_active |= IFM_NONE; 1859 } else 1860 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1861 return; 1862 1863 bail: 1864 ifmr->ifm_active |= IFM_NONE; 1865 ifmr->ifm_status &= ~IFM_AVALID; 1866 } 1867 1868 void 1869 txp_show_descriptor(void *d) 1870 { 1871 struct txp_cmd_desc *cmd = d; 1872 struct txp_rsp_desc *rsp = d; 1873 struct txp_tx_desc *txd = d; 1874 struct txp_frag_desc *frgd = d; 1875 1876 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1877 case CMD_FLAGS_TYPE_CMD: 1878 /* command descriptor */ 1879 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1880 "0x%x par3 0x%x]\n", 1881 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1882 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1883 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1884 break; 1885 case CMD_FLAGS_TYPE_RESP: 1886 /* response descriptor */ 1887 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1888 "0x%x par3 0x%x]\n", 1889 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1890 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1891 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1892 break; 1893 case CMD_FLAGS_TYPE_DATA: 1894 /* data header (assuming tx for now) */ 1895 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x " 1896 "pflags 0x%x]", 1897 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1898 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1899 break; 1900 case CMD_FLAGS_TYPE_FRAG: 1901 /* fragment descriptor */ 1902 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x " 1903 "rsvd2 0x%x]", 1904 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1905 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1906 break; 1907 default: 1908 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 " 1909 "0x%x par2 0x%x par3 0x%x]\n", 1910 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1911 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1912 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1913 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1914 break; 1915 } 1916 } 1917 1918 void 1919 txp_set_filter(struct txp_softc *sc) 1920 { 1921 struct ethercom *ec = &sc->sc_arpcom; 1922 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1923 uint32_t crc, carry, hashbit, hash[2]; 1924 uint16_t filter; 1925 uint8_t octet; 1926 int i, j, mcnt = 0; 1927 struct ether_multi *enm; 1928 struct ether_multistep step; 1929 1930 if (ifp->if_flags & IFF_PROMISC) { 1931 filter = TXP_RXFILT_PROMISC; 1932 goto setit; 1933 } 1934 1935 again: 1936 filter = TXP_RXFILT_DIRECT; 1937 1938 if (ifp->if_flags & IFF_BROADCAST) 1939 filter |= TXP_RXFILT_BROADCAST; 1940 1941 if (ifp->if_flags & IFF_ALLMULTI) 1942 filter |= TXP_RXFILT_ALLMULTI; 1943 else { 1944 hash[0] = hash[1] = 0; 1945 1946 ETHER_LOCK(ec); 1947 ETHER_FIRST_MULTI(step, ec, enm); 1948 while (enm != NULL) { 1949 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1950 ETHER_ADDR_LEN)) { 1951 /* 1952 * We must listen to a range of multicast 1953 * addresses. For now, just accept all 1954 * multicasts, rather than trying to set only 1955 * those filter bits needed to match the range. 1956 * (At this time, the only use of address 1957 * ranges is for IP multicast routing, for 1958 * which the range is big enough to require 1959 * all bits set.) 1960 */ 1961 ifp->if_flags |= IFF_ALLMULTI; 1962 ETHER_UNLOCK(ec); 1963 goto again; 1964 } 1965 1966 mcnt++; 1967 crc = 0xffffffff; 1968 1969 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1970 octet = enm->enm_addrlo[i]; 1971 for (j = 0; j < 8; j++) { 1972 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1973 (octet & 1); 1974 crc <<= 1; 1975 octet >>= 1; 1976 if (carry) 1977 crc = (crc ^ TXP_POLYNOMIAL) | 1978 carry; 1979 } 1980 } 1981 hashbit = (uint16_t)(crc & (64 - 1)); 1982 hash[hashbit / 32] |= (1 << hashbit % 32); 1983 ETHER_NEXT_MULTI(step, enm); 1984 } 1985 ETHER_UNLOCK(ec); 1986 1987 if (mcnt > 0) { 1988 filter |= TXP_RXFILT_HASHMULTI; 1989 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1990 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1991 } 1992 } 1993 1994 setit: 1995 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1996 NULL, NULL, NULL, 1); 1997 } 1998 1999 void 2000 txp_capabilities(struct txp_softc *sc) 2001 { 2002 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2003 struct txp_rsp_desc *rsp = NULL; 2004 struct txp_ext_desc *ext; 2005 2006 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2007 goto out; 2008 2009 if (rsp->rsp_numdesc != 1) 2010 goto out; 2011 ext = (struct txp_ext_desc *)(rsp + 1); 2012 2013 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2014 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2015 2016 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2017 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2018 sc->sc_tx_capability |= OFFLOAD_VLAN; 2019 sc->sc_rx_capability |= OFFLOAD_VLAN; 2020 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2021 sc->sc_arpcom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 2022 } 2023 2024 #if 0 2025 /* not ready yet */ 2026 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2027 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2028 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2029 ifp->if_capabilities |= IFCAP_IPSEC; 2030 } 2031 #endif 2032 2033 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2034 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2035 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2036 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2037 } 2038 2039 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2040 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2041 #ifdef TRY_TX_TCP_CSUM 2042 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2043 ifp->if_capabilities |= 2044 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2045 #endif 2046 } 2047 2048 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2049 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2050 #ifdef TRY_TX_UDP_CSUM 2051 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2052 ifp->if_capabilities |= 2053 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2054 #endif 2055 } 2056 2057 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2058 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2059 goto out; 2060 2061 out: 2062 if (rsp != NULL) 2063 free(rsp, M_DEVBUF); 2064 } 2065
Indexes created Tue Sep 30 20:09:53 GMT 2025