if_txp.c revision 1.62.2.1
1 /* $NetBSD: if_txp.c,v 1.62.2.1 2020/02/29 20:19:11 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.62.2.1 2020/02/29 20:19:11 ad Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 #include <net/if_media.h> 56 #include <net/bpf.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/pci/if_txpreg.h> 73 74 #include <dev/microcode/typhoon/3c990img.h> 75 76 /* 77 * These currently break the 3c990 firmware, hopefully will be resolved 78 * at some point. 79 */ 80 #undef TRY_TX_UDP_CSUM 81 #undef TRY_TX_TCP_CSUM 82 83 static int txp_probe(device_t, cfdata_t, void *); 84 static void txp_attach(device_t, device_t, void *); 85 static int txp_intr(void *); 86 static void txp_tick(void *); 87 static bool txp_shutdown(device_t, int); 88 static int txp_ioctl(struct ifnet *, u_long, void *); 89 static void txp_start(struct ifnet *); 90 static void txp_stop(struct txp_softc *); 91 static void txp_init(struct txp_softc *); 92 static void txp_watchdog(struct ifnet *); 93 94 static int txp_chip_init(struct txp_softc *); 95 static int txp_reset_adapter(struct txp_softc *); 96 static int txp_download_fw(struct txp_softc *); 97 static int txp_download_fw_wait(struct txp_softc *); 98 static int txp_download_fw_section(struct txp_softc *, 99 const struct txp_fw_section_header *, int); 100 static int txp_alloc_rings(struct txp_softc *); 101 static void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 102 static int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 103 static void txp_set_filter(struct txp_softc *); 104 105 static int txp_cmd_desc_numfree(struct txp_softc *); 106 static int txp_command(struct txp_softc *, uint16_t, uint16_t, uint32_t, 107 uint32_t, uint16_t *, uint32_t *, uint32_t *, int); 108 static int txp_command2(struct txp_softc *, uint16_t, uint16_t, 109 uint32_t, uint32_t, struct txp_ext_desc *, uint8_t, 110 struct txp_rsp_desc **, int); 111 static int txp_response(struct txp_softc *, uint32_t, uint16_t, uint16_t, 112 struct txp_rsp_desc **); 113 static void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 114 struct txp_rsp_desc *); 115 static void txp_capabilities(struct txp_softc *); 116 117 static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 static int txp_ifmedia_upd(struct ifnet *); 119 static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 120 struct txp_dma_alloc *); 121 static void txp_rxbuf_reclaim(struct txp_softc *); 122 static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 123 struct txp_dma_alloc *); 124 125 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 126 NULL, NULL); 127 128 static const struct txp_pci_match { 129 int vid, did, flags; 130 } txp_devices[] = { 131 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 139 }; 140 141 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 142 143 static const struct { 144 uint16_t mask, value; 145 int flags; 146 } txp_subsysinfo[] = { 147 {0xf000, 0x2000, TXP_SERVERVERSION}, 148 {0x0100, 0x0100, TXP_FIBER}, 149 #if 0 /* information from 3com header, unused */ 150 {0x0010, 0x0010, /* secured firmware */}, 151 {0x0003, 0x0000, /* variable DES */}, 152 {0x0003, 0x0001, /* single DES - "95" */}, 153 {0x0003, 0x0002, /* triple DES - "97" */}, 154 #endif 155 }; 156 157 static const struct txp_pci_match * 158 txp_pcilookup(pcireg_t id) 159 { 160 int i; 161 162 for (i = 0; i < __arraycount(txp_devices); i++) 163 if (PCI_VENDOR(id) == txp_devices[i].vid && 164 PCI_PRODUCT(id) == txp_devices[i].did) 165 return &txp_devices[i]; 166 return (0); 167 } 168 169 static int 170 txp_probe(device_t parent, cfdata_t match, void *aux) 171 { 172 struct pci_attach_args *pa = aux; 173 174 if (txp_pcilookup(pa->pa_id)) 175 return (1); 176 return (0); 177 } 178 179 static void 180 txp_attach(device_t parent, device_t self, void *aux) 181 { 182 struct txp_softc *sc = device_private(self); 183 struct pci_attach_args *pa = aux; 184 pci_chipset_tag_t pc = pa->pa_pc; 185 pci_intr_handle_t ih; 186 const char *intrstr = NULL; 187 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 188 uint32_t command; 189 uint16_t p1; 190 uint32_t p2; 191 u_char enaddr[6]; 192 const struct txp_pci_match *match; 193 uint16_t subsys; 194 int i, flags; 195 char devinfo[256]; 196 char intrbuf[PCI_INTRSTR_LEN]; 197 198 sc->sc_dev = self; 199 sc->sc_cold = 1; 200 201 match = txp_pcilookup(pa->pa_id); 202 flags = match->flags; 203 if (match->flags & TXP_USESUBSYSTEM) { 204 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 205 PCI_SUBSYS_ID_REG)); 206 for (i = 0; 207 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 208 i++) 209 if ((subsys & txp_subsysinfo[i].mask) == 210 txp_subsysinfo[i].value) 211 flags |= txp_subsysinfo[i].flags; 212 } 213 sc->sc_flags = flags; 214 215 aprint_naive("\n"); 216 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 217 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM | TXP_SERVERVERSION)) == \ 218 (TXP_USESUBSYSTEM | TXP_SERVERVERSION) ? " (SVR)" : "") 219 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 220 device_xname(sc->sc_dev)); 221 222 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 223 224 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 225 aprint_error(": failed to enable bus mastering\n"); 226 return; 227 } 228 229 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 230 aprint_error(": failed to enable memory mapping\n"); 231 return; 232 } 233 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 234 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 235 aprint_error(": can't map mem space %d\n", 0); 236 return; 237 } 238 239 sc->sc_dmat = pa->pa_dmat; 240 241 /* 242 * Allocate our interrupt. 243 */ 244 if (pci_intr_map(pa, &ih)) { 245 aprint_error(": couldn't map interrupt\n"); 246 return; 247 } 248 249 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 250 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, txp_intr, sc, 251 device_xname(self)); 252 if (sc->sc_ih == NULL) { 253 aprint_error(": couldn't establish interrupt"); 254 if (intrstr != NULL) 255 aprint_normal(" at %s", intrstr); 256 aprint_normal("\n"); 257 return; 258 } 259 aprint_normal(": interrupting at %s\n", intrstr); 260 261 if (txp_chip_init(sc)) 262 goto cleanupintr; 263 264 if (txp_download_fw(sc)) 265 goto cleanupintr; 266 267 if (txp_alloc_rings(sc)) 268 goto cleanupintr; 269 270 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 271 NULL, NULL, NULL, 1)) 272 goto cleanupintr; 273 274 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 275 &p1, &p2, NULL, 1)) 276 goto cleanupintr; 277 278 p1 = htole16(p1); 279 enaddr[0] = ((uint8_t *)&p1)[1]; 280 enaddr[1] = ((uint8_t *)&p1)[0]; 281 p2 = htole32(p2); 282 enaddr[2] = ((uint8_t *)&p2)[3]; 283 enaddr[3] = ((uint8_t *)&p2)[2]; 284 enaddr[4] = ((uint8_t *)&p2)[1]; 285 enaddr[5] = ((uint8_t *)&p2)[0]; 286 287 aprint_normal_dev(self, "Ethernet address %s\n", 288 ether_sprintf(enaddr)); 289 sc->sc_cold = 0; 290 291 /* Initialize ifmedia structures. */ 292 sc->sc_arpcom.ec_ifmedia = &sc->sc_ifmedia; 293 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 294 if (flags & TXP_FIBER) { 295 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX, 296 0, NULL); 297 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_HDX, 298 0, NULL); 299 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_FDX, 300 0, NULL); 301 } else { 302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 303 0, NULL); 304 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 305 0, NULL); 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 309 0, NULL); 310 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 311 0, NULL); 312 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 313 0, NULL); 314 } 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 316 317 sc->sc_xcvr = TXP_XCVR_AUTO; 318 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 319 NULL, NULL, NULL, 0); 320 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 321 322 ifp->if_softc = sc; 323 ifp->if_mtu = ETHERMTU; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 325 ifp->if_ioctl = txp_ioctl; 326 ifp->if_start = txp_start; 327 ifp->if_watchdog = txp_watchdog; 328 ifp->if_baudrate = 10000000; 329 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 330 IFQ_SET_READY(&ifp->if_snd); 331 ifp->if_capabilities = 0; 332 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 333 334 txp_capabilities(sc); 335 336 callout_init(&sc->sc_tick, 0); 337 callout_setfunc(&sc->sc_tick, txp_tick, sc); 338 339 /* 340 * Attach us everywhere 341 */ 342 if_attach(ifp); 343 if_deferred_start_init(ifp, NULL); 344 ether_ifattach(ifp, enaddr); 345 346 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 347 pmf_class_network_register(self, ifp); 348 else 349 aprint_error_dev(self, "couldn't establish power handler\n"); 350 351 return; 352 353 cleanupintr: 354 pci_intr_disestablish(pc, sc->sc_ih); 355 356 return; 357 358 } 359 360 static int 361 txp_chip_init(struct txp_softc *sc) 362 { 363 /* disable interrupts */ 364 WRITE_REG(sc, TXP_IER, 0); 365 WRITE_REG(sc, TXP_IMR, 366 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 367 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 368 TXP_INT_LATCH); 369 370 /* ack all interrupts */ 371 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 372 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 373 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 374 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 375 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 376 377 if (txp_reset_adapter(sc)) 378 return (-1); 379 380 /* disable interrupts */ 381 WRITE_REG(sc, TXP_IER, 0); 382 WRITE_REG(sc, TXP_IMR, 383 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 384 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 385 TXP_INT_LATCH); 386 387 /* ack all interrupts */ 388 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 389 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 392 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 393 394 return (0); 395 } 396 397 static int 398 txp_reset_adapter(struct txp_softc *sc) 399 { 400 uint32_t r; 401 int i; 402 403 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 404 DELAY(1000); 405 WRITE_REG(sc, TXP_SRR, 0); 406 407 /* Should wait max 6 seconds */ 408 for (i = 0; i < 6000; i++) { 409 r = READ_REG(sc, TXP_A2H_0); 410 if (r == STAT_WAITING_FOR_HOST_REQUEST) 411 break; 412 DELAY(1000); 413 } 414 415 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 416 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 417 return (-1); 418 } 419 420 return (0); 421 } 422 423 static int 424 txp_download_fw(struct txp_softc *sc) 425 { 426 const struct txp_fw_file_header *fileheader; 427 const struct txp_fw_section_header *secthead; 428 int sect; 429 uint32_t r, i, ier, imr; 430 431 ier = READ_REG(sc, TXP_IER); 432 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 433 434 imr = READ_REG(sc, TXP_IMR); 435 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 436 437 for (i = 0; i < 10000; i++) { 438 r = READ_REG(sc, TXP_A2H_0); 439 if (r == STAT_WAITING_FOR_HOST_REQUEST) 440 break; 441 DELAY(50); 442 } 443 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 444 printf(": not waiting for host request\n"); 445 return (-1); 446 } 447 448 /* Ack the status */ 449 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 450 451 fileheader = (const struct txp_fw_file_header *)tc990image; 452 if (memcmp("TYPHOON", fileheader->magicid, 453 sizeof(fileheader->magicid))) { 454 printf(": fw invalid magic\n"); 455 return (-1); 456 } 457 458 /* Tell boot firmware to get ready for image */ 459 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 460 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 461 462 if (txp_download_fw_wait(sc)) { 463 printf("%s: fw wait failed, initial\n", 464 device_xname(sc->sc_dev)); 465 return (-1); 466 } 467 468 secthead = (const struct txp_fw_section_header *) 469 (((const uint8_t *)tc990image) + 470 sizeof(struct txp_fw_file_header)); 471 472 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 473 if (txp_download_fw_section(sc, secthead, sect)) 474 return (-1); 475 secthead = (const struct txp_fw_section_header *) 476 (((const uint8_t *)secthead) + le32toh(secthead->nbytes) + 477 sizeof(*secthead)); 478 } 479 480 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 481 482 for (i = 0; i < 10000; i++) { 483 r = READ_REG(sc, TXP_A2H_0); 484 if (r == STAT_WAITING_FOR_BOOT) 485 break; 486 DELAY(50); 487 } 488 if (r != STAT_WAITING_FOR_BOOT) { 489 printf(": not waiting for boot\n"); 490 return (-1); 491 } 492 493 WRITE_REG(sc, TXP_IER, ier); 494 WRITE_REG(sc, TXP_IMR, imr); 495 496 return (0); 497 } 498 499 static int 500 txp_download_fw_wait(struct txp_softc *sc) 501 { 502 uint32_t i, r; 503 504 for (i = 0; i < 10000; i++) { 505 r = READ_REG(sc, TXP_ISR); 506 if (r & TXP_INT_A2H_0) 507 break; 508 DELAY(50); 509 } 510 511 if (!(r & TXP_INT_A2H_0)) { 512 printf(": fw wait failed comm0\n"); 513 return (-1); 514 } 515 516 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 517 518 r = READ_REG(sc, TXP_A2H_0); 519 if (r != STAT_WAITING_FOR_SEGMENT) { 520 printf(": fw not waiting for segment\n"); 521 return (-1); 522 } 523 return (0); 524 } 525 526 static int 527 txp_download_fw_section(struct txp_softc *sc, 528 const struct txp_fw_section_header *sect, int sectnum) 529 { 530 struct txp_dma_alloc dma; 531 int rseg, err = 0; 532 struct mbuf m; 533 #ifdef INET 534 uint16_t csum; 535 #endif 536 537 /* Skip zero length sections */ 538 if (sect->nbytes == 0) 539 return (0); 540 541 /* Make sure we aren't past the end of the image */ 542 rseg = ((const uint8_t *)sect) - ((const uint8_t *)tc990image); 543 if (rseg >= sizeof(tc990image)) { 544 printf(": fw invalid section address, section %d\n", sectnum); 545 return (-1); 546 } 547 548 /* Make sure this section doesn't go past the end */ 549 rseg += le32toh(sect->nbytes); 550 if (rseg >= sizeof(tc990image)) { 551 printf(": fw truncated section %d\n", sectnum); 552 return (-1); 553 } 554 555 /* map a buffer, copy segment to it, get physaddr */ 556 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 557 printf(": fw dma malloc failed, section %d\n", sectnum); 558 return (-1); 559 } 560 561 memcpy(dma.dma_vaddr, ((const uint8_t *)sect) + sizeof(*sect), 562 le32toh(sect->nbytes)); 563 564 /* 565 * dummy up mbuf and verify section checksum 566 */ 567 m.m_type = MT_DATA; 568 m.m_next = m.m_nextpkt = NULL; 569 m.m_owner = NULL; 570 m.m_len = le32toh(sect->nbytes); 571 m.m_data = dma.dma_vaddr; 572 m.m_flags = 0; 573 #ifdef INET 574 csum = in_cksum(&m, le32toh(sect->nbytes)); 575 if (csum != sect->cksum) { 576 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 577 sectnum, sect->cksum, csum); 578 txp_dma_free(sc, &dma); 579 return -1; 580 } 581 #endif 582 583 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 584 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 585 586 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 587 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 588 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 589 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 590 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 591 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 592 593 if (txp_download_fw_wait(sc)) { 594 printf("%s: fw wait failed, section %d\n", 595 device_xname(sc->sc_dev), sectnum); 596 err = -1; 597 } 598 599 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 600 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 601 602 txp_dma_free(sc, &dma); 603 return (err); 604 } 605 606 static int 607 txp_intr(void *vsc) 608 { 609 struct txp_softc *sc = vsc; 610 struct txp_hostvar *hv = sc->sc_hostvar; 611 uint32_t isr; 612 int claimed = 0; 613 614 /* mask all interrupts */ 615 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 616 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 617 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 618 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 619 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 620 621 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 622 sizeof(struct txp_hostvar), 623 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 624 625 isr = READ_REG(sc, TXP_ISR); 626 while (isr) { 627 claimed = 1; 628 WRITE_REG(sc, TXP_ISR, isr); 629 630 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 631 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 632 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 633 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 634 635 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 636 txp_rxbuf_reclaim(sc); 637 638 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 639 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 640 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 641 642 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 643 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 644 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 645 646 isr = READ_REG(sc, TXP_ISR); 647 } 648 649 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 650 sizeof(struct txp_hostvar), 651 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 652 653 /* unmask all interrupts */ 654 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 655 656 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 657 658 return (claimed); 659 } 660 661 static void 662 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 663 struct txp_dma_alloc *dma) 664 { 665 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 666 struct txp_rx_desc *rxd; 667 struct mbuf *m; 668 struct txp_swdesc *sd; 669 uint32_t roff, woff; 670 int sumflags = 0; 671 int idx; 672 673 roff = le32toh(*r->r_roff); 674 woff = le32toh(*r->r_woff); 675 idx = roff / sizeof(struct txp_rx_desc); 676 rxd = r->r_desc + idx; 677 678 while (roff != woff) { 679 680 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 681 idx * sizeof(struct txp_rx_desc), 682 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 683 684 if (rxd->rx_flags & RX_FLAGS_ERROR) { 685 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 686 le32toh(rxd->rx_stat)); 687 if_statinc(ifp, if_ierrors); 688 goto next; 689 } 690 691 /* retrieve stashed pointer */ 692 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 693 694 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 695 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 696 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 697 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 698 m = sd->sd_mbuf; 699 free(sd, M_DEVBUF); 700 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 701 702 #ifdef __STRICT_ALIGNMENT 703 { 704 /* 705 * XXX Nice chip, except it won't accept "off by 2" 706 * buffers, so we're force to copy. Supposedly 707 * this will be fixed in a newer firmware rev 708 * and this will be temporary. 709 */ 710 struct mbuf *mnew; 711 712 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 713 if (mnew == NULL) { 714 m_freem(m); 715 goto next; 716 } 717 if (m->m_len > (MHLEN - 2)) { 718 MCLGET(mnew, M_DONTWAIT); 719 if (!(mnew->m_flags & M_EXT)) { 720 m_freem(mnew); 721 m_freem(m); 722 goto next; 723 } 724 } 725 m_set_rcvif(mnew, ifp); 726 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 727 mnew->m_data += 2; 728 memcpy(mnew->m_data, m->m_data, m->m_len); 729 m_freem(m); 730 m = mnew; 731 } 732 #endif 733 734 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 735 sumflags |= (M_CSUM_IPv4 | M_CSUM_IPv4_BAD); 736 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 737 sumflags |= M_CSUM_IPv4; 738 739 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 740 sumflags |= (M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD); 741 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 742 sumflags |= M_CSUM_TCPv4; 743 744 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 745 sumflags |= (M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD); 746 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 747 sumflags |= M_CSUM_UDPv4; 748 749 m->m_pkthdr.csum_flags = sumflags; 750 751 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 752 vlan_set_tag(m, htons(rxd->rx_vlan >> 16)); 753 } 754 755 if_percpuq_enqueue(ifp->if_percpuq, m); 756 757 next: 758 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 759 idx * sizeof(struct txp_rx_desc), 760 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 761 762 roff += sizeof(struct txp_rx_desc); 763 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 764 idx = 0; 765 roff = 0; 766 rxd = r->r_desc; 767 } else { 768 idx++; 769 rxd++; 770 } 771 woff = le32toh(*r->r_woff); 772 } 773 774 *r->r_roff = htole32(woff); 775 } 776 777 static void 778 txp_rxbuf_reclaim(struct txp_softc *sc) 779 { 780 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 781 struct txp_hostvar *hv = sc->sc_hostvar; 782 struct txp_rxbuf_desc *rbd; 783 struct txp_swdesc *sd; 784 uint32_t i, end; 785 786 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 787 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 788 789 if (++i == RXBUF_ENTRIES) 790 i = 0; 791 792 rbd = sc->sc_rxbufs + i; 793 794 while (i != end) { 795 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 796 M_DEVBUF, M_NOWAIT); 797 if (sd == NULL) 798 break; 799 800 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 801 if (sd->sd_mbuf == NULL) 802 goto err_sd; 803 804 MCLGET(sd->sd_mbuf, M_DONTWAIT); 805 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 806 goto err_mbuf; 807 m_set_rcvif(sd->sd_mbuf, ifp); 808 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 809 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 810 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 811 goto err_mbuf; 812 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 813 BUS_DMA_NOWAIT)) { 814 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 815 goto err_mbuf; 816 } 817 818 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 819 i * sizeof(struct txp_rxbuf_desc), 820 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 821 822 /* stash away pointer */ 823 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 824 825 rbd->rb_paddrlo = ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) 826 & 0xffffffff; 827 rbd->rb_paddrhi = ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) 828 >> 32; 829 830 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 831 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 832 833 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 834 i * sizeof(struct txp_rxbuf_desc), 835 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 836 837 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 838 839 if (++i == RXBUF_ENTRIES) { 840 i = 0; 841 rbd = sc->sc_rxbufs; 842 } else 843 rbd++; 844 } 845 return; 846 847 err_mbuf: 848 m_freem(sd->sd_mbuf); 849 err_sd: 850 free(sd, M_DEVBUF); 851 } 852 853 /* 854 * Reclaim mbufs and entries from a transmit ring. 855 */ 856 static void 857 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 858 struct txp_dma_alloc *dma) 859 { 860 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 861 uint32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 862 uint32_t cons = r->r_cons, cnt = r->r_cnt; 863 struct txp_tx_desc *txd = r->r_desc + cons; 864 struct txp_swdesc *sd = sc->sc_txd + cons; 865 struct mbuf *m; 866 867 while (cons != idx) { 868 if (cnt == 0) 869 break; 870 871 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 872 cons * sizeof(struct txp_tx_desc), 873 sizeof(struct txp_tx_desc), 874 BUS_DMASYNC_POSTWRITE); 875 876 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 877 TX_FLAGS_TYPE_DATA) { 878 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 879 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 880 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 881 m = sd->sd_mbuf; 882 if (m != NULL) { 883 m_freem(m); 884 txd->tx_addrlo = 0; 885 txd->tx_addrhi = 0; 886 if_statinc(ifp, if_opackets); 887 } 888 } 889 ifp->if_flags &= ~IFF_OACTIVE; 890 891 if (++cons == TX_ENTRIES) { 892 txd = r->r_desc; 893 cons = 0; 894 sd = sc->sc_txd; 895 } else { 896 txd++; 897 sd++; 898 } 899 900 cnt--; 901 } 902 903 r->r_cons = cons; 904 r->r_cnt = cnt; 905 if (cnt == 0) 906 ifp->if_timer = 0; 907 } 908 909 static bool 910 txp_shutdown(device_t self, int howto) 911 { 912 struct txp_softc *sc; 913 914 sc = device_private(self); 915 916 /* mask all interrupts */ 917 WRITE_REG(sc, TXP_IMR, 918 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 919 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 920 TXP_INT_LATCH); 921 922 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 923 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 924 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 925 926 return true; 927 } 928 929 static int 930 txp_alloc_rings(struct txp_softc *sc) 931 { 932 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 933 struct txp_boot_record *boot; 934 struct txp_swdesc *sd; 935 uint32_t r; 936 int i, j, nb; 937 938 /* boot record */ 939 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 940 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 941 printf(": can't allocate boot record\n"); 942 return (-1); 943 } 944 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 945 memset(boot, 0, sizeof(*boot)); 946 sc->sc_boot = boot; 947 948 /* host variables */ 949 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 950 BUS_DMA_COHERENT)) { 951 printf(": can't allocate host ring\n"); 952 goto bail_boot; 953 } 954 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 955 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 956 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 957 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 958 959 /* high priority tx ring */ 960 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 961 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 962 printf(": can't allocate high tx ring\n"); 963 goto bail_host; 964 } 965 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 966 sizeof(struct txp_tx_desc) * TX_ENTRIES); 967 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 968 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 969 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 970 sc->sc_txhir.r_reg = TXP_H2A_1; 971 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 972 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 973 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 974 for (i = 0; i < TX_ENTRIES; i++) { 975 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 976 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 977 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 978 for (j = 0; j < i; j++) { 979 bus_dmamap_destroy(sc->sc_dmat, 980 sc->sc_txd[j].sd_map); 981 sc->sc_txd[j].sd_map = NULL; 982 } 983 goto bail_txhiring; 984 } 985 } 986 987 /* low priority tx ring */ 988 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 989 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 990 printf(": can't allocate low tx ring\n"); 991 goto bail_txhiring; 992 } 993 memset(sc->sc_txloring_dma.dma_vaddr, 0, 994 sizeof(struct txp_tx_desc) * TX_ENTRIES); 995 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 996 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 997 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 998 sc->sc_txlor.r_reg = TXP_H2A_3; 999 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1000 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1001 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1002 1003 /* high priority rx ring */ 1004 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1005 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1006 printf(": can't allocate high rx ring\n"); 1007 goto bail_txloring; 1008 } 1009 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1010 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1011 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1012 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1013 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1014 sc->sc_rxhir.r_desc = 1015 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1016 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1017 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1018 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1019 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1020 1021 /* low priority ring */ 1022 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1023 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1024 printf(": can't allocate low rx ring\n"); 1025 goto bail_rxhiring; 1026 } 1027 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1028 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1029 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1030 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1031 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1032 sc->sc_rxlor.r_desc = 1033 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1034 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1035 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1036 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1037 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1038 1039 /* command ring */ 1040 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1041 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1042 printf(": can't allocate command ring\n"); 1043 goto bail_rxloring; 1044 } 1045 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1046 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1047 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1048 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1049 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1050 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1051 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1052 sc->sc_cmdring.lastwrite = 0; 1053 1054 /* response ring */ 1055 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1056 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1057 printf(": can't allocate response ring\n"); 1058 goto bail_cmdring; 1059 } 1060 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1061 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1062 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1063 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1064 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1065 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1066 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1067 sc->sc_rspring.lastwrite = 0; 1068 1069 /* receive buffer ring */ 1070 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1071 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1072 printf(": can't allocate rx buffer ring\n"); 1073 goto bail_rspring; 1074 } 1075 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1076 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1077 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1078 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1079 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1080 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1081 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1082 sd = malloc(sizeof(struct txp_swdesc), M_DEVBUF, M_WAITOK); 1083 /* stash away pointer */ 1084 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, 1085 sizeof(sd)); 1086 1087 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1088 if (sd->sd_mbuf == NULL) { 1089 goto bail_rxbufring; 1090 } 1091 1092 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1093 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1094 goto bail_rxbufring; 1095 } 1096 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1097 m_set_rcvif(sd->sd_mbuf, ifp); 1098 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1099 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1100 goto bail_rxbufring; 1101 } 1102 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1103 BUS_DMA_NOWAIT)) { 1104 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1105 goto bail_rxbufring; 1106 } 1107 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1108 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1109 1110 1111 sc->sc_rxbufs[nb].rb_paddrlo = 1112 ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1113 sc->sc_rxbufs[nb].rb_paddrhi = 1114 ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1115 } 1116 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1117 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1118 BUS_DMASYNC_PREWRITE); 1119 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1120 sizeof(struct txp_rxbuf_desc)); 1121 1122 /* zero dma */ 1123 if (txp_dma_malloc(sc, sizeof(uint32_t), &sc->sc_zero_dma, 1124 BUS_DMA_COHERENT)) { 1125 printf(": can't allocate response ring\n"); 1126 goto bail_rxbufring; 1127 } 1128 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(uint32_t)); 1129 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1130 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1131 1132 /* See if it's waiting for boot, and try to boot it */ 1133 for (i = 0; i < 10000; i++) { 1134 r = READ_REG(sc, TXP_A2H_0); 1135 if (r == STAT_WAITING_FOR_BOOT) 1136 break; 1137 DELAY(50); 1138 } 1139 if (r != STAT_WAITING_FOR_BOOT) { 1140 printf(": not waiting for boot\n"); 1141 goto bail; 1142 } 1143 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1144 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1145 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1146 1147 /* See if it booted */ 1148 for (i = 0; i < 10000; i++) { 1149 r = READ_REG(sc, TXP_A2H_0); 1150 if (r == STAT_RUNNING) 1151 break; 1152 DELAY(50); 1153 } 1154 if (r != STAT_RUNNING) { 1155 printf(": fw not running\n"); 1156 goto bail; 1157 } 1158 1159 /* Clear TX and CMD ring write registers */ 1160 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1161 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1162 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1163 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1164 1165 return (0); 1166 1167 bail: 1168 txp_dma_free(sc, &sc->sc_zero_dma); 1169 bail_rxbufring: 1170 if (nb == RXBUF_ENTRIES) 1171 nb--; 1172 for (i = 0; i <= nb; i++) { 1173 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1174 sizeof(sd)); 1175 if (sd) 1176 free(sd, M_DEVBUF); 1177 } 1178 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1179 bail_rspring: 1180 txp_dma_free(sc, &sc->sc_rspring_dma); 1181 bail_cmdring: 1182 txp_dma_free(sc, &sc->sc_cmdring_dma); 1183 bail_rxloring: 1184 txp_dma_free(sc, &sc->sc_rxloring_dma); 1185 bail_rxhiring: 1186 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1187 bail_txloring: 1188 txp_dma_free(sc, &sc->sc_txloring_dma); 1189 bail_txhiring: 1190 txp_dma_free(sc, &sc->sc_txhiring_dma); 1191 bail_host: 1192 txp_dma_free(sc, &sc->sc_host_dma); 1193 bail_boot: 1194 txp_dma_free(sc, &sc->sc_boot_dma); 1195 return (-1); 1196 } 1197 1198 static int 1199 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1200 struct txp_dma_alloc *dma, int mapflags) 1201 { 1202 int r; 1203 1204 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1205 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1206 goto fail_0; 1207 1208 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1209 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1210 goto fail_1; 1211 1212 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1213 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1214 goto fail_2; 1215 1216 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1217 size, NULL, BUS_DMA_NOWAIT)) != 0) 1218 goto fail_3; 1219 1220 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1221 return (0); 1222 1223 fail_3: 1224 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1225 fail_2: 1226 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1227 fail_1: 1228 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1229 fail_0: 1230 return (r); 1231 } 1232 1233 static void 1234 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1235 { 1236 bus_size_t mapsize = dma->dma_map->dm_mapsize; 1237 1238 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1239 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, mapsize); 1240 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1241 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1242 } 1243 1244 static int 1245 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1246 { 1247 struct txp_softc *sc = ifp->if_softc; 1248 struct ifaddr *ifa = (struct ifaddr *)data; 1249 int s, error = 0; 1250 1251 s = splnet(); 1252 1253 #if 0 1254 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1255 splx(s); 1256 return error; 1257 } 1258 #endif 1259 1260 switch (command) { 1261 case SIOCINITIFADDR: 1262 ifp->if_flags |= IFF_UP; 1263 txp_init(sc); 1264 switch (ifa->ifa_addr->sa_family) { 1265 #ifdef INET 1266 case AF_INET: 1267 arp_ifinit(ifp, ifa); 1268 break; 1269 #endif /* INET */ 1270 default: 1271 break; 1272 } 1273 break; 1274 case SIOCSIFFLAGS: 1275 if ((error = ifioctl_common(ifp, command, data)) != 0) 1276 break; 1277 if (ifp->if_flags & IFF_UP) { 1278 txp_init(sc); 1279 } else { 1280 if (ifp->if_flags & IFF_RUNNING) 1281 txp_stop(sc); 1282 } 1283 break; 1284 case SIOCADDMULTI: 1285 case SIOCDELMULTI: 1286 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1287 break; 1288 1289 error = 0; 1290 1291 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1292 ; 1293 else if (ifp->if_flags & IFF_RUNNING) { 1294 /* 1295 * Multicast list has changed; set the hardware 1296 * filter accordingly. 1297 */ 1298 txp_set_filter(sc); 1299 } 1300 break; 1301 default: 1302 error = ether_ioctl(ifp, command, data); 1303 break; 1304 } 1305 1306 splx(s); 1307 1308 return (error); 1309 } 1310 1311 static void 1312 txp_init(struct txp_softc *sc) 1313 { 1314 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1315 int s; 1316 1317 txp_stop(sc); 1318 1319 s = splnet(); 1320 1321 txp_set_filter(sc); 1322 1323 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1324 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1325 1326 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1327 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1328 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1329 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1330 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1331 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1332 1333 ifp->if_flags |= IFF_RUNNING; 1334 ifp->if_flags &= ~IFF_OACTIVE; 1335 ifp->if_timer = 0; 1336 1337 if (!callout_pending(&sc->sc_tick)) 1338 callout_schedule(&sc->sc_tick, hz); 1339 1340 splx(s); 1341 } 1342 1343 static void 1344 txp_tick(void *vsc) 1345 { 1346 struct txp_softc *sc = vsc; 1347 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1348 struct txp_rsp_desc *rsp = NULL; 1349 struct txp_ext_desc *ext; 1350 int s; 1351 1352 s = splnet(); 1353 txp_rxbuf_reclaim(sc); 1354 1355 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1356 &rsp, 1)) 1357 goto out; 1358 if (rsp->rsp_numdesc != 6) 1359 goto out; 1360 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1361 NULL, NULL, NULL, 1)) 1362 goto out; 1363 ext = (struct txp_ext_desc *)(rsp + 1); 1364 1365 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1366 if_statadd_ref(nsr, if_ierrors, 1367 ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1368 ext[4].ext_1 + ext[4].ext_4); 1369 if_statadd_ref(nsr, if_oerrors, 1370 ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + ext[2].ext_1); 1371 if_statadd_ref(nsr, if_collisions, 1372 ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + ext[1].ext_3); 1373 if_statadd_ref(nsr, if_opackets, rsp->rsp_par2); 1374 IF_STAT_PUTREF(ifp); 1375 1376 out: 1377 if (rsp != NULL) 1378 free(rsp, M_DEVBUF); 1379 1380 splx(s); 1381 callout_schedule(&sc->sc_tick, hz); 1382 } 1383 1384 static void 1385 txp_start(struct ifnet *ifp) 1386 { 1387 struct txp_softc *sc = ifp->if_softc; 1388 struct txp_tx_ring *r = &sc->sc_txhir; 1389 struct txp_tx_desc *txd; 1390 int txdidx; 1391 struct txp_frag_desc *fxd; 1392 struct mbuf *m, *mnew; 1393 struct txp_swdesc *sd; 1394 uint32_t firstprod, firstcnt, prod, cnt, i; 1395 1396 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1397 return; 1398 1399 prod = r->r_prod; 1400 cnt = r->r_cnt; 1401 1402 while (1) { 1403 IFQ_POLL(&ifp->if_snd, m); 1404 if (m == NULL) 1405 break; 1406 mnew = NULL; 1407 1408 firstprod = prod; 1409 firstcnt = cnt; 1410 1411 sd = sc->sc_txd + prod; 1412 sd->sd_mbuf = m; 1413 1414 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1415 BUS_DMA_NOWAIT)) { 1416 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1417 if (mnew == NULL) 1418 goto oactive1; 1419 if (m->m_pkthdr.len > MHLEN) { 1420 MCLGET(mnew, M_DONTWAIT); 1421 if ((mnew->m_flags & M_EXT) == 0) { 1422 m_freem(mnew); 1423 goto oactive1; 1424 } 1425 } 1426 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1427 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1428 IFQ_DEQUEUE(&ifp->if_snd, m); 1429 m_freem(m); 1430 m = mnew; 1431 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1432 BUS_DMA_NOWAIT)) 1433 goto oactive1; 1434 } 1435 1436 if ((TX_ENTRIES - cnt) < 4) 1437 goto oactive; 1438 1439 txd = r->r_desc + prod; 1440 txdidx = prod; 1441 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1442 txd->tx_numdesc = 0; 1443 txd->tx_addrlo = 0; 1444 txd->tx_addrhi = 0; 1445 txd->tx_totlen = m->m_pkthdr.len; 1446 txd->tx_pflags = 0; 1447 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1448 1449 if (++prod == TX_ENTRIES) 1450 prod = 0; 1451 1452 if (++cnt >= (TX_ENTRIES - 4)) 1453 goto oactive; 1454 1455 if (vlan_has_tag(m)) 1456 txd->tx_pflags = TX_PFLAGS_VLAN | 1457 (htons(vlan_get_tag(m)) << TX_PFLAGS_VLANTAG_S); 1458 1459 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1460 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1461 #ifdef TRY_TX_TCP_CSUM 1462 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1463 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1464 #endif 1465 #ifdef TRY_TX_UDP_CSUM 1466 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1467 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1468 #endif 1469 1470 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1471 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1472 1473 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1474 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1475 if (++cnt >= (TX_ENTRIES - 4)) { 1476 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1477 0, sd->sd_map->dm_mapsize, 1478 BUS_DMASYNC_POSTWRITE); 1479 goto oactive; 1480 } 1481 1482 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1483 FRAG_FLAGS_VALID; 1484 fxd->frag_rsvd1 = 0; 1485 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1486 fxd->frag_addrlo = 1487 ((uint64_t)sd->sd_map->dm_segs[i].ds_addr) & 1488 0xffffffff; 1489 fxd->frag_addrhi = 1490 ((uint64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1491 32; 1492 fxd->frag_rsvd2 = 0; 1493 1494 bus_dmamap_sync(sc->sc_dmat, 1495 sc->sc_txhiring_dma.dma_map, 1496 prod * sizeof(struct txp_frag_desc), 1497 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1498 1499 if (++prod == TX_ENTRIES) { 1500 fxd = (struct txp_frag_desc *)r->r_desc; 1501 prod = 0; 1502 } else 1503 fxd++; 1504 1505 } 1506 1507 /* 1508 * if mnew isn't NULL, we already dequeued and copied 1509 * the packet. 1510 */ 1511 if (mnew == NULL) 1512 IFQ_DEQUEUE(&ifp->if_snd, m); 1513 1514 ifp->if_timer = 5; 1515 1516 bpf_mtap(ifp, m, BPF_D_OUT); 1517 1518 txd->tx_flags |= TX_FLAGS_VALID; 1519 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1520 txdidx * sizeof(struct txp_tx_desc), 1521 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1522 1523 #if 0 1524 { 1525 struct mbuf *mx; 1526 int i; 1527 1528 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1529 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1530 txd->tx_pflags); 1531 for (mx = m; mx != NULL; mx = mx->m_next) { 1532 for (i = 0; i < mx->m_len; i++) { 1533 printf(":%02x", 1534 (uint8_t)m->m_data[i]); 1535 } 1536 } 1537 printf("\n"); 1538 } 1539 #endif 1540 1541 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1542 } 1543 1544 r->r_prod = prod; 1545 r->r_cnt = cnt; 1546 return; 1547 1548 oactive: 1549 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1550 oactive1: 1551 ifp->if_flags |= IFF_OACTIVE; 1552 r->r_prod = firstprod; 1553 r->r_cnt = firstcnt; 1554 } 1555 1556 /* 1557 * Handle simple commands sent to the typhoon 1558 */ 1559 static int 1560 txp_command(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1561 uint32_t in3, uint16_t *out1, uint32_t *out2, uint32_t *out3, int wait) 1562 { 1563 struct txp_rsp_desc *rsp = NULL; 1564 1565 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1566 return (-1); 1567 1568 if (!wait) 1569 return (0); 1570 1571 if (out1 != NULL) 1572 *out1 = le16toh(rsp->rsp_par1); 1573 if (out2 != NULL) 1574 *out2 = le32toh(rsp->rsp_par2); 1575 if (out3 != NULL) 1576 *out3 = le32toh(rsp->rsp_par3); 1577 free(rsp, M_DEVBUF); 1578 return (0); 1579 } 1580 1581 static int 1582 txp_command2(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1583 uint32_t in3, struct txp_ext_desc *in_extp, uint8_t in_extn, 1584 struct txp_rsp_desc **rspp, int wait) 1585 { 1586 struct txp_hostvar *hv = sc->sc_hostvar; 1587 struct txp_cmd_desc *cmd; 1588 struct txp_ext_desc *ext; 1589 uint32_t idx, i; 1590 uint16_t seq; 1591 1592 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1593 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1594 return (-1); 1595 } 1596 1597 idx = sc->sc_cmdring.lastwrite; 1598 cmd = (struct txp_cmd_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1599 memset(cmd, 0, sizeof(*cmd)); 1600 1601 cmd->cmd_numdesc = in_extn; 1602 seq = sc->sc_seq++; 1603 cmd->cmd_seq = htole16(seq); 1604 cmd->cmd_id = htole16(id); 1605 cmd->cmd_par1 = htole16(in1); 1606 cmd->cmd_par2 = htole32(in2); 1607 cmd->cmd_par3 = htole32(in3); 1608 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1609 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1610 1611 idx += sizeof(struct txp_cmd_desc); 1612 if (idx == sc->sc_cmdring.size) 1613 idx = 0; 1614 1615 for (i = 0; i < in_extn; i++) { 1616 ext = (struct txp_ext_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1617 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1618 in_extp++; 1619 idx += sizeof(struct txp_cmd_desc); 1620 if (idx == sc->sc_cmdring.size) 1621 idx = 0; 1622 } 1623 1624 sc->sc_cmdring.lastwrite = idx; 1625 1626 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1627 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1628 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1629 1630 if (!wait) 1631 return (0); 1632 1633 for (i = 0; i < 10000; i++) { 1634 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1635 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1636 idx = le32toh(hv->hv_resp_read_idx); 1637 if (idx != le32toh(hv->hv_resp_write_idx)) { 1638 *rspp = NULL; 1639 if (txp_response(sc, idx, id, seq, rspp)) 1640 return (-1); 1641 if (*rspp != NULL) 1642 break; 1643 } 1644 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1645 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1646 DELAY(50); 1647 } 1648 if (i == 1000 || (*rspp) == NULL) { 1649 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1650 return (-1); 1651 } 1652 1653 return (0); 1654 } 1655 1656 static int 1657 txp_response(struct txp_softc *sc, uint32_t ridx, uint16_t id, uint16_t seq, 1658 struct txp_rsp_desc **rspp) 1659 { 1660 struct txp_hostvar *hv = sc->sc_hostvar; 1661 struct txp_rsp_desc *rsp; 1662 1663 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1664 rsp = (struct txp_rsp_desc *)(((uint8_t *)sc->sc_rspring.base) + ridx); 1665 1666 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1667 *rspp = (struct txp_rsp_desc *)malloc( 1668 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1669 M_DEVBUF, M_NOWAIT); 1670 if ((*rspp) == NULL) 1671 return (-1); 1672 txp_rsp_fixup(sc, rsp, *rspp); 1673 return (0); 1674 } 1675 1676 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1677 printf("%s: response error: id 0x%x\n", 1678 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1679 txp_rsp_fixup(sc, rsp, NULL); 1680 ridx = le32toh(hv->hv_resp_read_idx); 1681 continue; 1682 } 1683 1684 switch (le16toh(rsp->rsp_id)) { 1685 case TXP_CMD_CYCLE_STATISTICS: 1686 case TXP_CMD_MEDIA_STATUS_READ: 1687 break; 1688 case TXP_CMD_HELLO_RESPONSE: 1689 printf("%s: hello\n", TXP_DEVNAME(sc)); 1690 break; 1691 default: 1692 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1693 le16toh(rsp->rsp_id)); 1694 } 1695 1696 txp_rsp_fixup(sc, rsp, NULL); 1697 ridx = le32toh(hv->hv_resp_read_idx); 1698 hv->hv_resp_read_idx = le32toh(ridx); 1699 } 1700 1701 return (0); 1702 } 1703 1704 static void 1705 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1706 struct txp_rsp_desc *dst) 1707 { 1708 struct txp_rsp_desc *src = rsp; 1709 struct txp_hostvar *hv = sc->sc_hostvar; 1710 uint32_t i, ridx; 1711 1712 ridx = le32toh(hv->hv_resp_read_idx); 1713 1714 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1715 if (dst != NULL) 1716 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1717 ridx += sizeof(struct txp_rsp_desc); 1718 if (ridx == sc->sc_rspring.size) { 1719 src = sc->sc_rspring.base; 1720 ridx = 0; 1721 } else 1722 src++; 1723 sc->sc_rspring.lastwrite = ridx; 1724 hv->hv_resp_read_idx = htole32(ridx); 1725 } 1726 1727 hv->hv_resp_read_idx = htole32(ridx); 1728 } 1729 1730 static int 1731 txp_cmd_desc_numfree(struct txp_softc *sc) 1732 { 1733 struct txp_hostvar *hv = sc->sc_hostvar; 1734 struct txp_boot_record *br = sc->sc_boot; 1735 uint32_t widx, ridx, nfree; 1736 1737 widx = sc->sc_cmdring.lastwrite; 1738 ridx = le32toh(hv->hv_cmd_read_idx); 1739 1740 if (widx == ridx) { 1741 /* Ring is completely free */ 1742 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1743 } else { 1744 if (widx > ridx) 1745 nfree = le32toh(br->br_cmd_siz) - 1746 (widx - ridx + sizeof(struct txp_cmd_desc)); 1747 else 1748 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1749 } 1750 1751 return (nfree / sizeof(struct txp_cmd_desc)); 1752 } 1753 1754 static void 1755 txp_stop(struct txp_softc *sc) 1756 { 1757 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1758 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1759 1760 if (callout_pending(&sc->sc_tick)) 1761 callout_stop(&sc->sc_tick); 1762 } 1763 1764 static void 1765 txp_watchdog(struct ifnet *ifp) 1766 { 1767 } 1768 1769 static int 1770 txp_ifmedia_upd(struct ifnet *ifp) 1771 { 1772 struct txp_softc *sc = ifp->if_softc; 1773 struct ifmedia *ifm = &sc->sc_ifmedia; 1774 uint16_t new_xcvr; 1775 1776 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1777 return (EINVAL); 1778 1779 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1780 if ((ifm->ifm_media & IFM_FDX) != 0) 1781 new_xcvr = TXP_XCVR_10_FDX; 1782 else 1783 new_xcvr = TXP_XCVR_10_HDX; 1784 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1785 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1786 if ((ifm->ifm_media & IFM_FDX) != 0) 1787 new_xcvr = TXP_XCVR_100_FDX; 1788 else 1789 new_xcvr = TXP_XCVR_100_HDX; 1790 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1791 new_xcvr = TXP_XCVR_AUTO; 1792 } else 1793 return (EINVAL); 1794 1795 /* nothing to do */ 1796 if (sc->sc_xcvr == new_xcvr) 1797 return (0); 1798 1799 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1800 NULL, NULL, NULL, 0); 1801 sc->sc_xcvr = new_xcvr; 1802 1803 return (0); 1804 } 1805 1806 static void 1807 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1808 { 1809 struct txp_softc *sc = ifp->if_softc; 1810 struct ifmedia *ifm = &sc->sc_ifmedia; 1811 uint16_t bmsr, bmcr, anlpar; 1812 1813 ifmr->ifm_status = IFM_AVALID; 1814 ifmr->ifm_active = IFM_ETHER; 1815 1816 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1817 &bmsr, NULL, NULL, 1)) 1818 goto bail; 1819 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1820 &bmsr, NULL, NULL, 1)) 1821 goto bail; 1822 1823 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1824 &bmcr, NULL, NULL, 1)) 1825 goto bail; 1826 1827 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1828 &anlpar, NULL, NULL, 1)) 1829 goto bail; 1830 1831 if (bmsr & BMSR_LINK) 1832 ifmr->ifm_status |= IFM_ACTIVE; 1833 1834 if (bmcr & BMCR_ISO) { 1835 ifmr->ifm_active |= IFM_NONE; 1836 ifmr->ifm_status = 0; 1837 return; 1838 } 1839 1840 if (bmcr & BMCR_LOOP) 1841 ifmr->ifm_active |= IFM_LOOP; 1842 1843 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1844 if ((bmsr & BMSR_ACOMP) == 0) { 1845 ifmr->ifm_active |= IFM_NONE; 1846 return; 1847 } 1848 1849 if (anlpar & ANLPAR_TX_FD) 1850 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 1851 else if (anlpar & ANLPAR_T4) 1852 ifmr->ifm_active |= IFM_100_T4 | IFM_HDX; 1853 else if (anlpar & ANLPAR_TX) 1854 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 1855 else if (anlpar & ANLPAR_10_FD) 1856 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 1857 else if (anlpar & ANLPAR_10) 1858 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 1859 else 1860 ifmr->ifm_active |= IFM_NONE; 1861 } else 1862 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1863 return; 1864 1865 bail: 1866 ifmr->ifm_active |= IFM_NONE; 1867 ifmr->ifm_status &= ~IFM_AVALID; 1868 } 1869 1870 #if 0 /* XXX XXX XXX UNUSED */ 1871 static void 1872 txp_show_descriptor(void *d) 1873 { 1874 struct txp_cmd_desc *cmd = d; 1875 struct txp_rsp_desc *rsp = d; 1876 struct txp_tx_desc *txd = d; 1877 struct txp_frag_desc *frgd = d; 1878 1879 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1880 case CMD_FLAGS_TYPE_CMD: 1881 /* command descriptor */ 1882 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1883 "0x%x par3 0x%x]\n", 1884 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1885 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1886 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1887 break; 1888 case CMD_FLAGS_TYPE_RESP: 1889 /* response descriptor */ 1890 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1891 "0x%x par3 0x%x]\n", 1892 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1893 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1894 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1895 break; 1896 case CMD_FLAGS_TYPE_DATA: 1897 /* data header (assuming tx for now) */ 1898 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x " 1899 "pflags 0x%x]", 1900 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1901 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1902 break; 1903 case CMD_FLAGS_TYPE_FRAG: 1904 /* fragment descriptor */ 1905 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x " 1906 "rsvd2 0x%x]", 1907 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1908 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1909 break; 1910 default: 1911 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 " 1912 "0x%x par2 0x%x par3 0x%x]\n", 1913 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1914 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1915 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1916 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1917 break; 1918 } 1919 } 1920 #endif 1921 1922 static void 1923 txp_set_filter(struct txp_softc *sc) 1924 { 1925 struct ethercom *ec = &sc->sc_arpcom; 1926 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1927 uint32_t crc, carry, hashbit, hash[2]; 1928 uint16_t filter; 1929 uint8_t octet; 1930 int i, j, mcnt = 0; 1931 struct ether_multi *enm; 1932 struct ether_multistep step; 1933 1934 if (ifp->if_flags & IFF_PROMISC) { 1935 filter = TXP_RXFILT_PROMISC; 1936 goto setit; 1937 } 1938 1939 again: 1940 filter = TXP_RXFILT_DIRECT; 1941 1942 if (ifp->if_flags & IFF_BROADCAST) 1943 filter |= TXP_RXFILT_BROADCAST; 1944 1945 if (ifp->if_flags & IFF_ALLMULTI) 1946 filter |= TXP_RXFILT_ALLMULTI; 1947 else { 1948 hash[0] = hash[1] = 0; 1949 1950 ETHER_LOCK(ec); 1951 ETHER_FIRST_MULTI(step, ec, enm); 1952 while (enm != NULL) { 1953 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1954 ETHER_ADDR_LEN)) { 1955 /* 1956 * We must listen to a range of multicast 1957 * addresses. For now, just accept all 1958 * multicasts, rather than trying to set only 1959 * those filter bits needed to match the range. 1960 * (At this time, the only use of address 1961 * ranges is for IP multicast routing, for 1962 * which the range is big enough to require 1963 * all bits set.) 1964 */ 1965 ifp->if_flags |= IFF_ALLMULTI; 1966 ETHER_UNLOCK(ec); 1967 goto again; 1968 } 1969 1970 mcnt++; 1971 crc = 0xffffffff; 1972 1973 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1974 octet = enm->enm_addrlo[i]; 1975 for (j = 0; j < 8; j++) { 1976 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1977 (octet & 1); 1978 crc <<= 1; 1979 octet >>= 1; 1980 if (carry) 1981 crc = (crc ^ TXP_POLYNOMIAL) | 1982 carry; 1983 } 1984 } 1985 hashbit = (uint16_t)(crc & (64 - 1)); 1986 hash[hashbit / 32] |= (1 << hashbit % 32); 1987 ETHER_NEXT_MULTI(step, enm); 1988 } 1989 ETHER_UNLOCK(ec); 1990 1991 if (mcnt > 0) { 1992 filter |= TXP_RXFILT_HASHMULTI; 1993 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1994 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1995 } 1996 } 1997 1998 setit: 1999 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2000 NULL, NULL, NULL, 1); 2001 } 2002 2003 static void 2004 txp_capabilities(struct txp_softc *sc) 2005 { 2006 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2007 struct txp_rsp_desc *rsp = NULL; 2008 struct txp_ext_desc *ext; 2009 2010 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2011 goto out; 2012 2013 if (rsp->rsp_numdesc != 1) 2014 goto out; 2015 ext = (struct txp_ext_desc *)(rsp + 1); 2016 2017 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2018 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2019 2020 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2021 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2022 sc->sc_tx_capability |= OFFLOAD_VLAN; 2023 sc->sc_rx_capability |= OFFLOAD_VLAN; 2024 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2025 sc->sc_arpcom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 2026 } 2027 2028 #if 0 2029 /* not ready yet */ 2030 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2031 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2032 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2033 ifp->if_capabilities |= IFCAP_IPSEC; 2034 } 2035 #endif 2036 2037 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2038 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2039 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2040 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2041 } 2042 2043 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2044 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2045 #ifdef TRY_TX_TCP_CSUM 2046 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2047 ifp->if_capabilities |= 2048 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2049 #endif 2050 } 2051 2052 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2053 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2054 #ifdef TRY_TX_UDP_CSUM 2055 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2056 ifp->if_capabilities |= 2057 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2058 #endif 2059 } 2060 2061 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2062 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2063 goto out; 2064 2065 out: 2066 if (rsp != NULL) 2067 free(rsp, M_DEVBUF); 2068 } 2069
Indexes created Tue Sep 30 20:09:53 GMT 2025