if_txp.c revision 1.66
1 /* $NetBSD: if_txp.c,v 1.66 2020/03/08 19:24:40 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.66 2020/03/08 19:24:40 thorpej Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 #include <net/if_media.h> 56 #include <net/bpf.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/pci/if_txpreg.h> 73 74 #include <dev/microcode/typhoon/3c990img.h> 75 76 /* 77 * These currently break the 3c990 firmware, hopefully will be resolved 78 * at some point. 79 */ 80 #undef TRY_TX_UDP_CSUM 81 #undef TRY_TX_TCP_CSUM 82 83 static int txp_probe(device_t, cfdata_t, void *); 84 static void txp_attach(device_t, device_t, void *); 85 static int txp_intr(void *); 86 static void txp_tick(void *); 87 static bool txp_shutdown(device_t, int); 88 static int txp_ioctl(struct ifnet *, u_long, void *); 89 static void txp_start(struct ifnet *); 90 static void txp_stop(struct txp_softc *); 91 static void txp_init(struct txp_softc *); 92 static void txp_watchdog(struct ifnet *); 93 94 static int txp_chip_init(struct txp_softc *); 95 static int txp_reset_adapter(struct txp_softc *); 96 static int txp_download_fw(struct txp_softc *); 97 static int txp_download_fw_wait(struct txp_softc *); 98 static int txp_download_fw_section(struct txp_softc *, 99 const struct txp_fw_section_header *, int); 100 static int txp_alloc_rings(struct txp_softc *); 101 static void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 102 static int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 103 static void txp_set_filter(struct txp_softc *); 104 105 static int txp_cmd_desc_numfree(struct txp_softc *); 106 static int txp_command(struct txp_softc *, uint16_t, uint16_t, uint32_t, 107 uint32_t, uint16_t *, uint32_t *, uint32_t *, int); 108 static int txp_command2(struct txp_softc *, uint16_t, uint16_t, 109 uint32_t, uint32_t, struct txp_ext_desc *, uint8_t, 110 struct txp_rsp_desc **, int); 111 static int txp_response(struct txp_softc *, uint32_t, uint16_t, uint16_t, 112 struct txp_rsp_desc **); 113 static void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 114 struct txp_rsp_desc *); 115 static void txp_capabilities(struct txp_softc *); 116 117 static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 static int txp_ifmedia_upd(struct ifnet *); 119 static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 120 struct txp_dma_alloc *); 121 static void txp_rxbuf_reclaim(struct txp_softc *); 122 static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 123 struct txp_dma_alloc *); 124 125 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 126 NULL, NULL); 127 128 static const struct txp_pci_match { 129 int vid, did, flags; 130 } txp_devices[] = { 131 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 139 }; 140 141 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 142 143 static const struct { 144 uint16_t mask, value; 145 int flags; 146 } txp_subsysinfo[] = { 147 {0xf000, 0x2000, TXP_SERVERVERSION}, 148 {0x0100, 0x0100, TXP_FIBER}, 149 #if 0 /* information from 3com header, unused */ 150 {0x0010, 0x0010, /* secured firmware */}, 151 {0x0003, 0x0000, /* variable DES */}, 152 {0x0003, 0x0001, /* single DES - "95" */}, 153 {0x0003, 0x0002, /* triple DES - "97" */}, 154 #endif 155 }; 156 157 static const struct txp_pci_match * 158 txp_pcilookup(pcireg_t id) 159 { 160 int i; 161 162 for (i = 0; i < __arraycount(txp_devices); i++) 163 if (PCI_VENDOR(id) == txp_devices[i].vid && 164 PCI_PRODUCT(id) == txp_devices[i].did) 165 return &txp_devices[i]; 166 return (0); 167 } 168 169 static int 170 txp_probe(device_t parent, cfdata_t match, void *aux) 171 { 172 struct pci_attach_args *pa = aux; 173 174 if (txp_pcilookup(pa->pa_id)) 175 return (1); 176 return (0); 177 } 178 179 static void 180 txp_attach(device_t parent, device_t self, void *aux) 181 { 182 struct txp_softc *sc = device_private(self); 183 struct pci_attach_args *pa = aux; 184 pci_chipset_tag_t pc = pa->pa_pc; 185 pci_intr_handle_t ih; 186 const char *intrstr = NULL; 187 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 188 uint32_t command; 189 uint16_t p1; 190 uint32_t p2; 191 u_char enaddr[6]; 192 const struct txp_pci_match *match; 193 uint16_t subsys; 194 int i, flags; 195 char devinfo[256]; 196 char intrbuf[PCI_INTRSTR_LEN]; 197 198 sc->sc_dev = self; 199 sc->sc_cold = 1; 200 201 match = txp_pcilookup(pa->pa_id); 202 flags = match->flags; 203 if (match->flags & TXP_USESUBSYSTEM) { 204 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 205 PCI_SUBSYS_ID_REG)); 206 for (i = 0; 207 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 208 i++) 209 if ((subsys & txp_subsysinfo[i].mask) == 210 txp_subsysinfo[i].value) 211 flags |= txp_subsysinfo[i].flags; 212 } 213 sc->sc_flags = flags; 214 215 aprint_naive("\n"); 216 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 217 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM | TXP_SERVERVERSION)) == \ 218 (TXP_USESUBSYSTEM | TXP_SERVERVERSION) ? " (SVR)" : "") 219 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 220 device_xname(sc->sc_dev)); 221 222 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 223 224 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 225 aprint_error(": failed to enable bus mastering\n"); 226 return; 227 } 228 229 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 230 aprint_error(": failed to enable memory mapping\n"); 231 return; 232 } 233 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 234 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 235 aprint_error(": can't map mem space %d\n", 0); 236 return; 237 } 238 239 if (pci_dma64_available(pa)) 240 sc->sc_dmat = pa->pa_dmat64; 241 else 242 sc->sc_dmat = pa->pa_dmat; 243 244 /* 245 * Allocate our interrupt. 246 */ 247 if (pci_intr_map(pa, &ih)) { 248 aprint_error(": couldn't map interrupt\n"); 249 return; 250 } 251 252 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 253 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, txp_intr, sc, 254 device_xname(self)); 255 if (sc->sc_ih == NULL) { 256 aprint_error(": couldn't establish interrupt"); 257 if (intrstr != NULL) 258 aprint_normal(" at %s", intrstr); 259 aprint_normal("\n"); 260 return; 261 } 262 aprint_normal(": interrupting at %s\n", intrstr); 263 264 if (txp_chip_init(sc)) 265 goto cleanupintr; 266 267 if (txp_download_fw(sc)) 268 goto cleanupintr; 269 270 if (txp_alloc_rings(sc)) 271 goto cleanupintr; 272 273 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 274 NULL, NULL, NULL, 1)) 275 goto cleanupintr; 276 277 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 278 &p1, &p2, NULL, 1)) 279 goto cleanupintr; 280 281 p1 = htole16(p1); 282 enaddr[0] = ((uint8_t *)&p1)[1]; 283 enaddr[1] = ((uint8_t *)&p1)[0]; 284 p2 = htole32(p2); 285 enaddr[2] = ((uint8_t *)&p2)[3]; 286 enaddr[3] = ((uint8_t *)&p2)[2]; 287 enaddr[4] = ((uint8_t *)&p2)[1]; 288 enaddr[5] = ((uint8_t *)&p2)[0]; 289 290 aprint_normal_dev(self, "Ethernet address %s\n", 291 ether_sprintf(enaddr)); 292 sc->sc_cold = 0; 293 294 /* Initialize ifmedia structures. */ 295 sc->sc_arpcom.ec_ifmedia = &sc->sc_ifmedia; 296 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 297 if (flags & TXP_FIBER) { 298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX, 299 0, NULL); 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_FDX, 301 0, NULL); 302 } else { 303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 304 0, NULL); 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 310 0, NULL); 311 } 312 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 313 314 sc->sc_xcvr = TXP_XCVR_AUTO; 315 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 316 NULL, NULL, NULL, 0); 317 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 318 319 ifp->if_softc = sc; 320 ifp->if_mtu = ETHERMTU; 321 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 322 ifp->if_ioctl = txp_ioctl; 323 ifp->if_start = txp_start; 324 ifp->if_watchdog = txp_watchdog; 325 ifp->if_baudrate = 10000000; 326 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 327 IFQ_SET_READY(&ifp->if_snd); 328 ifp->if_capabilities = 0; 329 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 330 331 txp_capabilities(sc); 332 333 callout_init(&sc->sc_tick, 0); 334 callout_setfunc(&sc->sc_tick, txp_tick, sc); 335 336 /* 337 * Attach us everywhere 338 */ 339 if_attach(ifp); 340 if_deferred_start_init(ifp, NULL); 341 ether_ifattach(ifp, enaddr); 342 343 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 344 pmf_class_network_register(self, ifp); 345 else 346 aprint_error_dev(self, "couldn't establish power handler\n"); 347 348 return; 349 350 cleanupintr: 351 pci_intr_disestablish(pc, sc->sc_ih); 352 353 return; 354 355 } 356 357 static int 358 txp_chip_init(struct txp_softc *sc) 359 { 360 /* disable interrupts */ 361 WRITE_REG(sc, TXP_IER, 0); 362 WRITE_REG(sc, TXP_IMR, 363 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 364 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 365 TXP_INT_LATCH); 366 367 /* ack all interrupts */ 368 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 369 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 370 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 371 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 372 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 373 374 if (txp_reset_adapter(sc)) 375 return (-1); 376 377 /* disable interrupts */ 378 WRITE_REG(sc, TXP_IER, 0); 379 WRITE_REG(sc, TXP_IMR, 380 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 381 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 382 TXP_INT_LATCH); 383 384 /* ack all interrupts */ 385 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 386 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 387 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 388 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 389 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 390 391 return (0); 392 } 393 394 static int 395 txp_reset_adapter(struct txp_softc *sc) 396 { 397 uint32_t r; 398 int i; 399 400 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 401 DELAY(1000); 402 WRITE_REG(sc, TXP_SRR, 0); 403 404 /* Should wait max 6 seconds */ 405 for (i = 0; i < 6000; i++) { 406 r = READ_REG(sc, TXP_A2H_0); 407 if (r == STAT_WAITING_FOR_HOST_REQUEST) 408 break; 409 DELAY(1000); 410 } 411 412 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 413 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 414 return (-1); 415 } 416 417 return (0); 418 } 419 420 static int 421 txp_download_fw(struct txp_softc *sc) 422 { 423 const struct txp_fw_file_header *fileheader; 424 const struct txp_fw_section_header *secthead; 425 int sect; 426 uint32_t r, i, ier, imr; 427 428 ier = READ_REG(sc, TXP_IER); 429 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 430 431 imr = READ_REG(sc, TXP_IMR); 432 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 433 434 for (i = 0; i < 10000; i++) { 435 r = READ_REG(sc, TXP_A2H_0); 436 if (r == STAT_WAITING_FOR_HOST_REQUEST) 437 break; 438 DELAY(50); 439 } 440 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 441 printf(": not waiting for host request\n"); 442 return (-1); 443 } 444 445 /* Ack the status */ 446 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 447 448 fileheader = (const struct txp_fw_file_header *)tc990image; 449 if (memcmp("TYPHOON", fileheader->magicid, 450 sizeof(fileheader->magicid))) { 451 printf(": fw invalid magic\n"); 452 return (-1); 453 } 454 455 /* Tell boot firmware to get ready for image */ 456 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 457 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 458 459 if (txp_download_fw_wait(sc)) { 460 printf("%s: fw wait failed, initial\n", 461 device_xname(sc->sc_dev)); 462 return (-1); 463 } 464 465 secthead = (const struct txp_fw_section_header *) 466 (((const uint8_t *)tc990image) + 467 sizeof(struct txp_fw_file_header)); 468 469 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 470 if (txp_download_fw_section(sc, secthead, sect)) 471 return (-1); 472 secthead = (const struct txp_fw_section_header *) 473 (((const uint8_t *)secthead) + le32toh(secthead->nbytes) + 474 sizeof(*secthead)); 475 } 476 477 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 478 479 for (i = 0; i < 10000; i++) { 480 r = READ_REG(sc, TXP_A2H_0); 481 if (r == STAT_WAITING_FOR_BOOT) 482 break; 483 DELAY(50); 484 } 485 if (r != STAT_WAITING_FOR_BOOT) { 486 printf(": not waiting for boot\n"); 487 return (-1); 488 } 489 490 WRITE_REG(sc, TXP_IER, ier); 491 WRITE_REG(sc, TXP_IMR, imr); 492 493 return (0); 494 } 495 496 static int 497 txp_download_fw_wait(struct txp_softc *sc) 498 { 499 uint32_t i, r; 500 501 for (i = 0; i < 10000; i++) { 502 r = READ_REG(sc, TXP_ISR); 503 if (r & TXP_INT_A2H_0) 504 break; 505 DELAY(50); 506 } 507 508 if (!(r & TXP_INT_A2H_0)) { 509 printf(": fw wait failed comm0\n"); 510 return (-1); 511 } 512 513 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 514 515 r = READ_REG(sc, TXP_A2H_0); 516 if (r != STAT_WAITING_FOR_SEGMENT) { 517 printf(": fw not waiting for segment\n"); 518 return (-1); 519 } 520 return (0); 521 } 522 523 static int 524 txp_download_fw_section(struct txp_softc *sc, 525 const struct txp_fw_section_header *sect, int sectnum) 526 { 527 struct txp_dma_alloc dma; 528 int rseg, err = 0; 529 struct mbuf m; 530 #ifdef INET 531 uint16_t csum; 532 #endif 533 534 /* Skip zero length sections */ 535 if (sect->nbytes == 0) 536 return (0); 537 538 /* Make sure we aren't past the end of the image */ 539 rseg = ((const uint8_t *)sect) - ((const uint8_t *)tc990image); 540 if (rseg >= sizeof(tc990image)) { 541 printf(": fw invalid section address, section %d\n", sectnum); 542 return (-1); 543 } 544 545 /* Make sure this section doesn't go past the end */ 546 rseg += le32toh(sect->nbytes); 547 if (rseg >= sizeof(tc990image)) { 548 printf(": fw truncated section %d\n", sectnum); 549 return (-1); 550 } 551 552 /* map a buffer, copy segment to it, get physaddr */ 553 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 554 printf(": fw dma malloc failed, section %d\n", sectnum); 555 return (-1); 556 } 557 558 memcpy(dma.dma_vaddr, ((const uint8_t *)sect) + sizeof(*sect), 559 le32toh(sect->nbytes)); 560 561 /* 562 * dummy up mbuf and verify section checksum 563 */ 564 m.m_type = MT_DATA; 565 m.m_next = m.m_nextpkt = NULL; 566 m.m_owner = NULL; 567 m.m_len = le32toh(sect->nbytes); 568 m.m_data = dma.dma_vaddr; 569 m.m_flags = 0; 570 #ifdef INET 571 csum = in_cksum(&m, le32toh(sect->nbytes)); 572 if (csum != sect->cksum) { 573 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 574 sectnum, sect->cksum, csum); 575 txp_dma_free(sc, &dma); 576 return -1; 577 } 578 #endif 579 580 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 581 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 582 583 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 584 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 585 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 586 WRITE_REG(sc, TXP_H2A_4, BUS_ADDR_HI32(dma.dma_paddr)); 587 WRITE_REG(sc, TXP_H2A_5, BUS_ADDR_LO32(dma.dma_paddr)); 588 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 589 590 if (txp_download_fw_wait(sc)) { 591 printf("%s: fw wait failed, section %d\n", 592 device_xname(sc->sc_dev), sectnum); 593 err = -1; 594 } 595 596 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 597 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 598 599 txp_dma_free(sc, &dma); 600 return (err); 601 } 602 603 static int 604 txp_intr(void *vsc) 605 { 606 struct txp_softc *sc = vsc; 607 struct txp_hostvar *hv = sc->sc_hostvar; 608 uint32_t isr; 609 int claimed = 0; 610 611 /* mask all interrupts */ 612 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 613 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 614 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 615 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 616 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 617 618 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 619 sizeof(struct txp_hostvar), 620 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 621 622 isr = READ_REG(sc, TXP_ISR); 623 while (isr) { 624 claimed = 1; 625 WRITE_REG(sc, TXP_ISR, isr); 626 627 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 628 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 629 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 630 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 631 632 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 633 txp_rxbuf_reclaim(sc); 634 635 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 636 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 637 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 638 639 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 640 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 641 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 642 643 isr = READ_REG(sc, TXP_ISR); 644 } 645 646 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 647 sizeof(struct txp_hostvar), 648 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 649 650 /* unmask all interrupts */ 651 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 652 653 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 654 655 return (claimed); 656 } 657 658 static void 659 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 660 struct txp_dma_alloc *dma) 661 { 662 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 663 struct txp_rx_desc *rxd; 664 struct mbuf *m; 665 struct txp_swdesc *sd; 666 uint32_t roff, woff; 667 int sumflags = 0; 668 int idx; 669 670 roff = le32toh(*r->r_roff); 671 woff = le32toh(*r->r_woff); 672 idx = roff / sizeof(struct txp_rx_desc); 673 rxd = r->r_desc + idx; 674 675 while (roff != woff) { 676 677 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 678 idx * sizeof(struct txp_rx_desc), 679 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 680 681 if (rxd->rx_flags & RX_FLAGS_ERROR) { 682 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 683 le32toh(rxd->rx_stat)); 684 if_statinc(ifp, if_ierrors); 685 goto next; 686 } 687 688 /* retrieve stashed pointer */ 689 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 690 691 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 692 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 693 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 694 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 695 m = sd->sd_mbuf; 696 free(sd, M_DEVBUF); 697 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 698 699 #ifdef __STRICT_ALIGNMENT 700 { 701 /* 702 * XXX Nice chip, except it won't accept "off by 2" 703 * buffers, so we're force to copy. Supposedly 704 * this will be fixed in a newer firmware rev 705 * and this will be temporary. 706 */ 707 struct mbuf *mnew; 708 709 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 710 if (mnew == NULL) { 711 m_freem(m); 712 goto next; 713 } 714 if (m->m_len > (MHLEN - 2)) { 715 MCLGET(mnew, M_DONTWAIT); 716 if (!(mnew->m_flags & M_EXT)) { 717 m_freem(mnew); 718 m_freem(m); 719 goto next; 720 } 721 } 722 m_set_rcvif(mnew, ifp); 723 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 724 mnew->m_data += 2; 725 memcpy(mnew->m_data, m->m_data, m->m_len); 726 m_freem(m); 727 m = mnew; 728 } 729 #endif 730 731 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 732 sumflags |= (M_CSUM_IPv4 | M_CSUM_IPv4_BAD); 733 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 734 sumflags |= M_CSUM_IPv4; 735 736 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 737 sumflags |= (M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD); 738 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 739 sumflags |= M_CSUM_TCPv4; 740 741 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 742 sumflags |= (M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD); 743 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 744 sumflags |= M_CSUM_UDPv4; 745 746 m->m_pkthdr.csum_flags = sumflags; 747 748 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 749 vlan_set_tag(m, htons(rxd->rx_vlan >> 16)); 750 } 751 752 if_percpuq_enqueue(ifp->if_percpuq, m); 753 754 next: 755 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 756 idx * sizeof(struct txp_rx_desc), 757 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 758 759 roff += sizeof(struct txp_rx_desc); 760 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 761 idx = 0; 762 roff = 0; 763 rxd = r->r_desc; 764 } else { 765 idx++; 766 rxd++; 767 } 768 woff = le32toh(*r->r_woff); 769 } 770 771 *r->r_roff = htole32(woff); 772 } 773 774 static void 775 txp_rxbuf_reclaim(struct txp_softc *sc) 776 { 777 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 778 struct txp_hostvar *hv = sc->sc_hostvar; 779 struct txp_rxbuf_desc *rbd; 780 struct txp_swdesc *sd; 781 uint32_t i, end; 782 783 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 784 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 785 786 if (++i == RXBUF_ENTRIES) 787 i = 0; 788 789 rbd = sc->sc_rxbufs + i; 790 791 while (i != end) { 792 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 793 M_DEVBUF, M_NOWAIT); 794 if (sd == NULL) 795 break; 796 797 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 798 if (sd->sd_mbuf == NULL) 799 goto err_sd; 800 801 MCLGET(sd->sd_mbuf, M_DONTWAIT); 802 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 803 goto err_mbuf; 804 m_set_rcvif(sd->sd_mbuf, ifp); 805 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 806 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 807 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 808 goto err_mbuf; 809 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 810 BUS_DMA_NOWAIT)) { 811 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 812 goto err_mbuf; 813 } 814 815 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 816 i * sizeof(struct txp_rxbuf_desc), 817 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 818 819 /* stash away pointer */ 820 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 821 822 rbd->rb_paddrlo = 823 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr)); 824 rbd->rb_paddrhi = 825 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr)); 826 827 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 828 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 829 830 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 831 i * sizeof(struct txp_rxbuf_desc), 832 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 833 834 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 835 836 if (++i == RXBUF_ENTRIES) { 837 i = 0; 838 rbd = sc->sc_rxbufs; 839 } else 840 rbd++; 841 } 842 return; 843 844 err_mbuf: 845 m_freem(sd->sd_mbuf); 846 err_sd: 847 free(sd, M_DEVBUF); 848 } 849 850 /* 851 * Reclaim mbufs and entries from a transmit ring. 852 */ 853 static void 854 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 855 struct txp_dma_alloc *dma) 856 { 857 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 858 uint32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 859 uint32_t cons = r->r_cons, cnt = r->r_cnt; 860 struct txp_tx_desc *txd = r->r_desc + cons; 861 struct txp_swdesc *sd = sc->sc_txd + cons; 862 struct mbuf *m; 863 864 while (cons != idx) { 865 if (cnt == 0) 866 break; 867 868 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 869 cons * sizeof(struct txp_tx_desc), 870 sizeof(struct txp_tx_desc), 871 BUS_DMASYNC_POSTWRITE); 872 873 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 874 TX_FLAGS_TYPE_DATA) { 875 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 876 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 877 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 878 m = sd->sd_mbuf; 879 if (m != NULL) { 880 m_freem(m); 881 txd->tx_addrlo = 0; 882 txd->tx_addrhi = 0; 883 if_statinc(ifp, if_opackets); 884 } 885 } 886 ifp->if_flags &= ~IFF_OACTIVE; 887 888 if (++cons == TX_ENTRIES) { 889 txd = r->r_desc; 890 cons = 0; 891 sd = sc->sc_txd; 892 } else { 893 txd++; 894 sd++; 895 } 896 897 cnt--; 898 } 899 900 r->r_cons = cons; 901 r->r_cnt = cnt; 902 if (cnt == 0) 903 ifp->if_timer = 0; 904 } 905 906 static bool 907 txp_shutdown(device_t self, int howto) 908 { 909 struct txp_softc *sc; 910 911 sc = device_private(self); 912 913 /* mask all interrupts */ 914 WRITE_REG(sc, TXP_IMR, 915 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 916 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 917 TXP_INT_LATCH); 918 919 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 920 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 921 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 922 923 return true; 924 } 925 926 static int 927 txp_alloc_rings(struct txp_softc *sc) 928 { 929 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 930 struct txp_boot_record *boot; 931 struct txp_swdesc *sd; 932 uint32_t r; 933 int i, j, nb; 934 935 /* boot record */ 936 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 937 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 938 printf(": can't allocate boot record\n"); 939 return (-1); 940 } 941 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 942 memset(boot, 0, sizeof(*boot)); 943 sc->sc_boot = boot; 944 945 /* host variables */ 946 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 947 BUS_DMA_COHERENT)) { 948 printf(": can't allocate host ring\n"); 949 goto bail_boot; 950 } 951 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 952 boot->br_hostvar_lo = htole32(BUS_ADDR_LO32(sc->sc_host_dma.dma_paddr)); 953 boot->br_hostvar_hi = htole32(BUS_ADDR_HI32(sc->sc_host_dma.dma_paddr)); 954 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 955 956 /* high priority tx ring */ 957 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 958 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 959 printf(": can't allocate high tx ring\n"); 960 goto bail_host; 961 } 962 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 963 sizeof(struct txp_tx_desc) * TX_ENTRIES); 964 boot->br_txhipri_lo = 965 htole32(BUS_ADDR_LO32(sc->sc_txhiring_dma.dma_paddr)); 966 boot->br_txhipri_hi = 967 htole32(BUS_ADDR_HI32(sc->sc_txhiring_dma.dma_paddr)); 968 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 969 sc->sc_txhir.r_reg = TXP_H2A_1; 970 sc->sc_txhir.r_desc = 971 (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 972 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 973 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 974 for (i = 0; i < TX_ENTRIES; i++) { 975 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 976 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 977 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 978 for (j = 0; j < i; j++) { 979 bus_dmamap_destroy(sc->sc_dmat, 980 sc->sc_txd[j].sd_map); 981 sc->sc_txd[j].sd_map = NULL; 982 } 983 goto bail_txhiring; 984 } 985 } 986 987 /* low priority tx ring */ 988 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 989 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 990 printf(": can't allocate low tx ring\n"); 991 goto bail_txhiring; 992 } 993 memset(sc->sc_txloring_dma.dma_vaddr, 0, 994 sizeof(struct txp_tx_desc) * TX_ENTRIES); 995 boot->br_txlopri_lo = 996 htole32(BUS_ADDR_LO32(sc->sc_txloring_dma.dma_paddr)); 997 boot->br_txlopri_hi = 998 htole32(BUS_ADDR_HI32(sc->sc_txloring_dma.dma_paddr)); 999 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1000 sc->sc_txlor.r_reg = TXP_H2A_3; 1001 sc->sc_txlor.r_desc = 1002 (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1003 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1004 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1005 1006 /* high priority rx ring */ 1007 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1008 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1009 printf(": can't allocate high rx ring\n"); 1010 goto bail_txloring; 1011 } 1012 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1013 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1014 boot->br_rxhipri_lo = 1015 htole32(BUS_ADDR_LO32(sc->sc_rxhiring_dma.dma_paddr)); 1016 boot->br_rxhipri_hi = 1017 htole32(BUS_ADDR_HI32(sc->sc_rxhiring_dma.dma_paddr)); 1018 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1019 sc->sc_rxhir.r_desc = 1020 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1021 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1022 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1023 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1024 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1025 1026 /* low priority ring */ 1027 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1028 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1029 printf(": can't allocate low rx ring\n"); 1030 goto bail_rxhiring; 1031 } 1032 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1033 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1034 boot->br_rxlopri_lo = 1035 htole32(BUS_ADDR_LO32(sc->sc_rxloring_dma.dma_paddr)); 1036 boot->br_rxlopri_hi = 1037 htole32(BUS_ADDR_HI32(sc->sc_rxloring_dma.dma_paddr)); 1038 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1039 sc->sc_rxlor.r_desc = 1040 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1041 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1042 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1043 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1044 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1045 1046 /* command ring */ 1047 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1048 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1049 printf(": can't allocate command ring\n"); 1050 goto bail_rxloring; 1051 } 1052 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1053 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1054 boot->br_cmd_lo = htole32(BUS_ADDR_LO32(sc->sc_cmdring_dma.dma_paddr)); 1055 boot->br_cmd_hi = htole32(BUS_ADDR_HI32(sc->sc_cmdring_dma.dma_paddr)); 1056 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1057 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1058 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1059 sc->sc_cmdring.lastwrite = 0; 1060 1061 /* response ring */ 1062 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1063 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1064 printf(": can't allocate response ring\n"); 1065 goto bail_cmdring; 1066 } 1067 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1068 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1069 boot->br_resp_lo = htole32(BUS_ADDR_LO32(sc->sc_rspring_dma.dma_paddr)); 1070 boot->br_resp_hi = htole32(BUS_ADDR_HI32(sc->sc_rspring_dma.dma_paddr)); 1071 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1072 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1073 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1074 sc->sc_rspring.lastwrite = 0; 1075 1076 /* receive buffer ring */ 1077 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1078 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1079 printf(": can't allocate rx buffer ring\n"); 1080 goto bail_rspring; 1081 } 1082 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1083 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1084 boot->br_rxbuf_lo = htole32(BUS_ADDR_LO32(sc->sc_rxbufring_dma.dma_paddr)); 1085 boot->br_rxbuf_hi = htole32(BUS_ADDR_HI32(sc->sc_rxbufring_dma.dma_paddr)); 1086 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1087 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1088 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1089 sd = malloc(sizeof(struct txp_swdesc), M_DEVBUF, M_WAITOK); 1090 /* stash away pointer */ 1091 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, 1092 sizeof(sd)); 1093 1094 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1095 if (sd->sd_mbuf == NULL) { 1096 goto bail_rxbufring; 1097 } 1098 1099 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1100 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1101 goto bail_rxbufring; 1102 } 1103 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1104 m_set_rcvif(sd->sd_mbuf, ifp); 1105 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1106 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1107 goto bail_rxbufring; 1108 } 1109 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1110 BUS_DMA_NOWAIT)) { 1111 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1112 goto bail_rxbufring; 1113 } 1114 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1115 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1116 1117 1118 sc->sc_rxbufs[nb].rb_paddrlo = 1119 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr)); 1120 sc->sc_rxbufs[nb].rb_paddrhi = 1121 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr)); 1122 } 1123 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1124 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1125 BUS_DMASYNC_PREWRITE); 1126 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1127 sizeof(struct txp_rxbuf_desc)); 1128 1129 /* zero dma */ 1130 if (txp_dma_malloc(sc, sizeof(uint32_t), &sc->sc_zero_dma, 1131 BUS_DMA_COHERENT)) { 1132 printf(": can't allocate response ring\n"); 1133 goto bail_rxbufring; 1134 } 1135 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(uint32_t)); 1136 boot->br_zero_lo = htole32(BUS_ADDR_LO32(sc->sc_zero_dma.dma_paddr)); 1137 boot->br_zero_hi = htole32(BUS_ADDR_HI32(sc->sc_zero_dma.dma_paddr)); 1138 1139 /* See if it's waiting for boot, and try to boot it */ 1140 for (i = 0; i < 10000; i++) { 1141 r = READ_REG(sc, TXP_A2H_0); 1142 if (r == STAT_WAITING_FOR_BOOT) 1143 break; 1144 DELAY(50); 1145 } 1146 if (r != STAT_WAITING_FOR_BOOT) { 1147 printf(": not waiting for boot\n"); 1148 goto bail; 1149 } 1150 WRITE_REG(sc, TXP_H2A_2, BUS_ADDR_HI32(sc->sc_boot_dma.dma_paddr)); 1151 WRITE_REG(sc, TXP_H2A_1, BUS_ADDR_LO32(sc->sc_boot_dma.dma_paddr)); 1152 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1153 1154 /* See if it booted */ 1155 for (i = 0; i < 10000; i++) { 1156 r = READ_REG(sc, TXP_A2H_0); 1157 if (r == STAT_RUNNING) 1158 break; 1159 DELAY(50); 1160 } 1161 if (r != STAT_RUNNING) { 1162 printf(": fw not running\n"); 1163 goto bail; 1164 } 1165 1166 /* Clear TX and CMD ring write registers */ 1167 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1168 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1169 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1170 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1171 1172 return (0); 1173 1174 bail: 1175 txp_dma_free(sc, &sc->sc_zero_dma); 1176 bail_rxbufring: 1177 if (nb == RXBUF_ENTRIES) 1178 nb--; 1179 for (i = 0; i <= nb; i++) { 1180 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1181 sizeof(sd)); 1182 if (sd) 1183 free(sd, M_DEVBUF); 1184 } 1185 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1186 bail_rspring: 1187 txp_dma_free(sc, &sc->sc_rspring_dma); 1188 bail_cmdring: 1189 txp_dma_free(sc, &sc->sc_cmdring_dma); 1190 bail_rxloring: 1191 txp_dma_free(sc, &sc->sc_rxloring_dma); 1192 bail_rxhiring: 1193 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1194 bail_txloring: 1195 txp_dma_free(sc, &sc->sc_txloring_dma); 1196 bail_txhiring: 1197 txp_dma_free(sc, &sc->sc_txhiring_dma); 1198 bail_host: 1199 txp_dma_free(sc, &sc->sc_host_dma); 1200 bail_boot: 1201 txp_dma_free(sc, &sc->sc_boot_dma); 1202 return (-1); 1203 } 1204 1205 static int 1206 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1207 struct txp_dma_alloc *dma, int mapflags) 1208 { 1209 int r; 1210 1211 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1212 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1213 goto fail_0; 1214 1215 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1216 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1217 goto fail_1; 1218 1219 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1220 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1221 goto fail_2; 1222 1223 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1224 size, NULL, BUS_DMA_NOWAIT)) != 0) 1225 goto fail_3; 1226 1227 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1228 return (0); 1229 1230 fail_3: 1231 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1232 fail_2: 1233 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1234 fail_1: 1235 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1236 fail_0: 1237 return (r); 1238 } 1239 1240 static void 1241 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1242 { 1243 bus_size_t mapsize = dma->dma_map->dm_mapsize; 1244 1245 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1246 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, mapsize); 1247 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1248 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1249 } 1250 1251 static int 1252 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1253 { 1254 struct txp_softc *sc = ifp->if_softc; 1255 struct ifaddr *ifa = (struct ifaddr *)data; 1256 int s, error = 0; 1257 1258 s = splnet(); 1259 1260 #if 0 1261 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1262 splx(s); 1263 return error; 1264 } 1265 #endif 1266 1267 switch (command) { 1268 case SIOCINITIFADDR: 1269 ifp->if_flags |= IFF_UP; 1270 txp_init(sc); 1271 switch (ifa->ifa_addr->sa_family) { 1272 #ifdef INET 1273 case AF_INET: 1274 arp_ifinit(ifp, ifa); 1275 break; 1276 #endif /* INET */ 1277 default: 1278 break; 1279 } 1280 break; 1281 case SIOCSIFFLAGS: 1282 if ((error = ifioctl_common(ifp, command, data)) != 0) 1283 break; 1284 if (ifp->if_flags & IFF_UP) { 1285 txp_init(sc); 1286 } else { 1287 if (ifp->if_flags & IFF_RUNNING) 1288 txp_stop(sc); 1289 } 1290 break; 1291 case SIOCADDMULTI: 1292 case SIOCDELMULTI: 1293 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1294 break; 1295 1296 error = 0; 1297 1298 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1299 ; 1300 else if (ifp->if_flags & IFF_RUNNING) { 1301 /* 1302 * Multicast list has changed; set the hardware 1303 * filter accordingly. 1304 */ 1305 txp_set_filter(sc); 1306 } 1307 break; 1308 default: 1309 error = ether_ioctl(ifp, command, data); 1310 break; 1311 } 1312 1313 splx(s); 1314 1315 return (error); 1316 } 1317 1318 static void 1319 txp_init(struct txp_softc *sc) 1320 { 1321 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1322 int s; 1323 1324 txp_stop(sc); 1325 1326 s = splnet(); 1327 1328 txp_set_filter(sc); 1329 1330 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1331 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1332 1333 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1334 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1335 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1336 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1337 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1338 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1339 1340 ifp->if_flags |= IFF_RUNNING; 1341 ifp->if_flags &= ~IFF_OACTIVE; 1342 ifp->if_timer = 0; 1343 1344 if (!callout_pending(&sc->sc_tick)) 1345 callout_schedule(&sc->sc_tick, hz); 1346 1347 splx(s); 1348 } 1349 1350 static void 1351 txp_tick(void *vsc) 1352 { 1353 struct txp_softc *sc = vsc; 1354 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1355 struct txp_rsp_desc *rsp = NULL; 1356 struct txp_ext_desc *ext; 1357 int s; 1358 1359 s = splnet(); 1360 txp_rxbuf_reclaim(sc); 1361 1362 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1363 &rsp, 1)) 1364 goto out; 1365 if (rsp->rsp_numdesc != 6) 1366 goto out; 1367 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1368 NULL, NULL, NULL, 1)) 1369 goto out; 1370 ext = (struct txp_ext_desc *)(rsp + 1); 1371 1372 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1373 if_statadd_ref(nsr, if_ierrors, 1374 ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1375 ext[4].ext_1 + ext[4].ext_4); 1376 if_statadd_ref(nsr, if_oerrors, 1377 ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + ext[2].ext_1); 1378 if_statadd_ref(nsr, if_collisions, 1379 ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + ext[1].ext_3); 1380 if_statadd_ref(nsr, if_opackets, rsp->rsp_par2); 1381 IF_STAT_PUTREF(ifp); 1382 1383 out: 1384 if (rsp != NULL) 1385 free(rsp, M_DEVBUF); 1386 1387 splx(s); 1388 callout_schedule(&sc->sc_tick, hz); 1389 } 1390 1391 static void 1392 txp_start(struct ifnet *ifp) 1393 { 1394 struct txp_softc *sc = ifp->if_softc; 1395 struct txp_tx_ring *r = &sc->sc_txhir; 1396 struct txp_tx_desc *txd; 1397 int txdidx; 1398 struct txp_frag_desc *fxd; 1399 struct mbuf *m, *mnew; 1400 struct txp_swdesc *sd; 1401 uint32_t firstprod, firstcnt, prod, cnt, i; 1402 1403 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1404 return; 1405 1406 prod = r->r_prod; 1407 cnt = r->r_cnt; 1408 1409 while (1) { 1410 IFQ_POLL(&ifp->if_snd, m); 1411 if (m == NULL) 1412 break; 1413 mnew = NULL; 1414 1415 firstprod = prod; 1416 firstcnt = cnt; 1417 1418 sd = sc->sc_txd + prod; 1419 sd->sd_mbuf = m; 1420 1421 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1422 BUS_DMA_NOWAIT)) { 1423 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1424 if (mnew == NULL) 1425 goto oactive1; 1426 if (m->m_pkthdr.len > MHLEN) { 1427 MCLGET(mnew, M_DONTWAIT); 1428 if ((mnew->m_flags & M_EXT) == 0) { 1429 m_freem(mnew); 1430 goto oactive1; 1431 } 1432 } 1433 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1434 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1435 IFQ_DEQUEUE(&ifp->if_snd, m); 1436 m_freem(m); 1437 m = mnew; 1438 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1439 BUS_DMA_NOWAIT)) 1440 goto oactive1; 1441 } 1442 1443 if ((TX_ENTRIES - cnt) < 4) 1444 goto oactive; 1445 1446 txd = r->r_desc + prod; 1447 txdidx = prod; 1448 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1449 txd->tx_numdesc = 0; 1450 txd->tx_addrlo = 0; 1451 txd->tx_addrhi = 0; 1452 txd->tx_totlen = m->m_pkthdr.len; 1453 txd->tx_pflags = 0; 1454 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1455 1456 if (++prod == TX_ENTRIES) 1457 prod = 0; 1458 1459 if (++cnt >= (TX_ENTRIES - 4)) 1460 goto oactive; 1461 1462 if (vlan_has_tag(m)) 1463 txd->tx_pflags = TX_PFLAGS_VLAN | 1464 (htons(vlan_get_tag(m)) << TX_PFLAGS_VLANTAG_S); 1465 1466 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1467 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1468 #ifdef TRY_TX_TCP_CSUM 1469 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1470 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1471 #endif 1472 #ifdef TRY_TX_UDP_CSUM 1473 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1474 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1475 #endif 1476 1477 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1478 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1479 1480 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1481 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1482 if (++cnt >= (TX_ENTRIES - 4)) { 1483 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1484 0, sd->sd_map->dm_mapsize, 1485 BUS_DMASYNC_POSTWRITE); 1486 goto oactive; 1487 } 1488 1489 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1490 FRAG_FLAGS_VALID; 1491 fxd->frag_rsvd1 = 0; 1492 fxd->frag_len = htole16(sd->sd_map->dm_segs[i].ds_len); 1493 fxd->frag_addrlo = 1494 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[i].ds_addr)); 1495 fxd->frag_addrhi = 1496 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[i].ds_addr)); 1497 fxd->frag_rsvd2 = 0; 1498 1499 bus_dmamap_sync(sc->sc_dmat, 1500 sc->sc_txhiring_dma.dma_map, 1501 prod * sizeof(struct txp_frag_desc), 1502 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1503 1504 if (++prod == TX_ENTRIES) { 1505 fxd = (struct txp_frag_desc *)r->r_desc; 1506 prod = 0; 1507 } else 1508 fxd++; 1509 1510 } 1511 1512 /* 1513 * if mnew isn't NULL, we already dequeued and copied 1514 * the packet. 1515 */ 1516 if (mnew == NULL) 1517 IFQ_DEQUEUE(&ifp->if_snd, m); 1518 1519 ifp->if_timer = 5; 1520 1521 bpf_mtap(ifp, m, BPF_D_OUT); 1522 1523 txd->tx_flags |= TX_FLAGS_VALID; 1524 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1525 txdidx * sizeof(struct txp_tx_desc), 1526 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1527 1528 #if 0 1529 { 1530 struct mbuf *mx; 1531 int i; 1532 1533 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1534 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1535 txd->tx_pflags); 1536 for (mx = m; mx != NULL; mx = mx->m_next) { 1537 for (i = 0; i < mx->m_len; i++) { 1538 printf(":%02x", 1539 (uint8_t)m->m_data[i]); 1540 } 1541 } 1542 printf("\n"); 1543 } 1544 #endif 1545 1546 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1547 } 1548 1549 r->r_prod = prod; 1550 r->r_cnt = cnt; 1551 return; 1552 1553 oactive: 1554 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1555 oactive1: 1556 ifp->if_flags |= IFF_OACTIVE; 1557 r->r_prod = firstprod; 1558 r->r_cnt = firstcnt; 1559 } 1560 1561 /* 1562 * Handle simple commands sent to the typhoon 1563 */ 1564 static int 1565 txp_command(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1566 uint32_t in3, uint16_t *out1, uint32_t *out2, uint32_t *out3, int wait) 1567 { 1568 struct txp_rsp_desc *rsp = NULL; 1569 1570 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1571 return (-1); 1572 1573 if (!wait) 1574 return (0); 1575 1576 if (out1 != NULL) 1577 *out1 = le16toh(rsp->rsp_par1); 1578 if (out2 != NULL) 1579 *out2 = le32toh(rsp->rsp_par2); 1580 if (out3 != NULL) 1581 *out3 = le32toh(rsp->rsp_par3); 1582 free(rsp, M_DEVBUF); 1583 return (0); 1584 } 1585 1586 static int 1587 txp_command2(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1588 uint32_t in3, struct txp_ext_desc *in_extp, uint8_t in_extn, 1589 struct txp_rsp_desc **rspp, int wait) 1590 { 1591 struct txp_hostvar *hv = sc->sc_hostvar; 1592 struct txp_cmd_desc *cmd; 1593 struct txp_ext_desc *ext; 1594 uint32_t idx, i; 1595 uint16_t seq; 1596 1597 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1598 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1599 return (-1); 1600 } 1601 1602 idx = sc->sc_cmdring.lastwrite; 1603 cmd = (struct txp_cmd_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1604 memset(cmd, 0, sizeof(*cmd)); 1605 1606 cmd->cmd_numdesc = in_extn; 1607 seq = sc->sc_seq++; 1608 cmd->cmd_seq = htole16(seq); 1609 cmd->cmd_id = htole16(id); 1610 cmd->cmd_par1 = htole16(in1); 1611 cmd->cmd_par2 = htole32(in2); 1612 cmd->cmd_par3 = htole32(in3); 1613 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1614 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1615 1616 idx += sizeof(struct txp_cmd_desc); 1617 if (idx == sc->sc_cmdring.size) 1618 idx = 0; 1619 1620 for (i = 0; i < in_extn; i++) { 1621 ext = (struct txp_ext_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1622 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1623 in_extp++; 1624 idx += sizeof(struct txp_cmd_desc); 1625 if (idx == sc->sc_cmdring.size) 1626 idx = 0; 1627 } 1628 1629 sc->sc_cmdring.lastwrite = idx; 1630 1631 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1632 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1633 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1634 1635 if (!wait) 1636 return (0); 1637 1638 for (i = 0; i < 10000; i++) { 1639 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1640 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1641 idx = le32toh(hv->hv_resp_read_idx); 1642 if (idx != le32toh(hv->hv_resp_write_idx)) { 1643 *rspp = NULL; 1644 if (txp_response(sc, idx, id, seq, rspp)) 1645 return (-1); 1646 if (*rspp != NULL) 1647 break; 1648 } 1649 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1650 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1651 DELAY(50); 1652 } 1653 if (i == 1000 || (*rspp) == NULL) { 1654 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1655 return (-1); 1656 } 1657 1658 return (0); 1659 } 1660 1661 static int 1662 txp_response(struct txp_softc *sc, uint32_t ridx, uint16_t id, uint16_t seq, 1663 struct txp_rsp_desc **rspp) 1664 { 1665 struct txp_hostvar *hv = sc->sc_hostvar; 1666 struct txp_rsp_desc *rsp; 1667 1668 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1669 rsp = (struct txp_rsp_desc *)(((uint8_t *)sc->sc_rspring.base) + ridx); 1670 1671 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1672 *rspp = (struct txp_rsp_desc *)malloc( 1673 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1674 M_DEVBUF, M_NOWAIT); 1675 if ((*rspp) == NULL) 1676 return (-1); 1677 txp_rsp_fixup(sc, rsp, *rspp); 1678 return (0); 1679 } 1680 1681 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1682 printf("%s: response error: id 0x%x\n", 1683 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1684 txp_rsp_fixup(sc, rsp, NULL); 1685 ridx = le32toh(hv->hv_resp_read_idx); 1686 continue; 1687 } 1688 1689 switch (le16toh(rsp->rsp_id)) { 1690 case TXP_CMD_CYCLE_STATISTICS: 1691 case TXP_CMD_MEDIA_STATUS_READ: 1692 break; 1693 case TXP_CMD_HELLO_RESPONSE: 1694 printf("%s: hello\n", TXP_DEVNAME(sc)); 1695 break; 1696 default: 1697 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1698 le16toh(rsp->rsp_id)); 1699 } 1700 1701 txp_rsp_fixup(sc, rsp, NULL); 1702 ridx = le32toh(hv->hv_resp_read_idx); 1703 hv->hv_resp_read_idx = le32toh(ridx); 1704 } 1705 1706 return (0); 1707 } 1708 1709 static void 1710 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1711 struct txp_rsp_desc *dst) 1712 { 1713 struct txp_rsp_desc *src = rsp; 1714 struct txp_hostvar *hv = sc->sc_hostvar; 1715 uint32_t i, ridx; 1716 1717 ridx = le32toh(hv->hv_resp_read_idx); 1718 1719 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1720 if (dst != NULL) 1721 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1722 ridx += sizeof(struct txp_rsp_desc); 1723 if (ridx == sc->sc_rspring.size) { 1724 src = sc->sc_rspring.base; 1725 ridx = 0; 1726 } else 1727 src++; 1728 sc->sc_rspring.lastwrite = ridx; 1729 hv->hv_resp_read_idx = htole32(ridx); 1730 } 1731 1732 hv->hv_resp_read_idx = htole32(ridx); 1733 } 1734 1735 static int 1736 txp_cmd_desc_numfree(struct txp_softc *sc) 1737 { 1738 struct txp_hostvar *hv = sc->sc_hostvar; 1739 struct txp_boot_record *br = sc->sc_boot; 1740 uint32_t widx, ridx, nfree; 1741 1742 widx = sc->sc_cmdring.lastwrite; 1743 ridx = le32toh(hv->hv_cmd_read_idx); 1744 1745 if (widx == ridx) { 1746 /* Ring is completely free */ 1747 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1748 } else { 1749 if (widx > ridx) 1750 nfree = le32toh(br->br_cmd_siz) - 1751 (widx - ridx + sizeof(struct txp_cmd_desc)); 1752 else 1753 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1754 } 1755 1756 return (nfree / sizeof(struct txp_cmd_desc)); 1757 } 1758 1759 static void 1760 txp_stop(struct txp_softc *sc) 1761 { 1762 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1763 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1764 1765 if (callout_pending(&sc->sc_tick)) 1766 callout_stop(&sc->sc_tick); 1767 } 1768 1769 static void 1770 txp_watchdog(struct ifnet *ifp) 1771 { 1772 } 1773 1774 static int 1775 txp_ifmedia_upd(struct ifnet *ifp) 1776 { 1777 struct txp_softc *sc = ifp->if_softc; 1778 struct ifmedia *ifm = &sc->sc_ifmedia; 1779 uint16_t new_xcvr; 1780 1781 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1782 return (EINVAL); 1783 1784 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1785 if ((ifm->ifm_media & IFM_FDX) != 0) 1786 new_xcvr = TXP_XCVR_10_FDX; 1787 else 1788 new_xcvr = TXP_XCVR_10_HDX; 1789 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1790 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1791 if ((ifm->ifm_media & IFM_FDX) != 0) 1792 new_xcvr = TXP_XCVR_100_FDX; 1793 else 1794 new_xcvr = TXP_XCVR_100_HDX; 1795 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1796 new_xcvr = TXP_XCVR_AUTO; 1797 } else 1798 return (EINVAL); 1799 1800 /* nothing to do */ 1801 if (sc->sc_xcvr == new_xcvr) 1802 return (0); 1803 1804 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1805 NULL, NULL, NULL, 0); 1806 sc->sc_xcvr = new_xcvr; 1807 1808 return (0); 1809 } 1810 1811 static void 1812 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1813 { 1814 struct txp_softc *sc = ifp->if_softc; 1815 struct ifmedia *ifm = &sc->sc_ifmedia; 1816 uint16_t bmsr, bmcr, anlpar; 1817 1818 ifmr->ifm_status = IFM_AVALID; 1819 ifmr->ifm_active = IFM_ETHER; 1820 1821 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1822 &bmsr, NULL, NULL, 1)) 1823 goto bail; 1824 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1825 &bmsr, NULL, NULL, 1)) 1826 goto bail; 1827 1828 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1829 &bmcr, NULL, NULL, 1)) 1830 goto bail; 1831 1832 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1833 &anlpar, NULL, NULL, 1)) 1834 goto bail; 1835 1836 if (bmsr & BMSR_LINK) 1837 ifmr->ifm_status |= IFM_ACTIVE; 1838 1839 if (bmcr & BMCR_ISO) { 1840 ifmr->ifm_active |= IFM_NONE; 1841 ifmr->ifm_status = 0; 1842 return; 1843 } 1844 1845 if (bmcr & BMCR_LOOP) 1846 ifmr->ifm_active |= IFM_LOOP; 1847 1848 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1849 if ((bmsr & BMSR_ACOMP) == 0) { 1850 ifmr->ifm_active |= IFM_NONE; 1851 return; 1852 } 1853 1854 if (anlpar & ANLPAR_TX_FD) 1855 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 1856 else if (anlpar & ANLPAR_T4) 1857 ifmr->ifm_active |= IFM_100_T4 | IFM_HDX; 1858 else if (anlpar & ANLPAR_TX) 1859 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 1860 else if (anlpar & ANLPAR_10_FD) 1861 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 1862 else if (anlpar & ANLPAR_10) 1863 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 1864 else 1865 ifmr->ifm_active |= IFM_NONE; 1866 } else 1867 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1868 return; 1869 1870 bail: 1871 ifmr->ifm_active |= IFM_NONE; 1872 ifmr->ifm_status &= ~IFM_AVALID; 1873 } 1874 1875 #if 0 /* XXX XXX XXX UNUSED */ 1876 static void 1877 txp_show_descriptor(void *d) 1878 { 1879 struct txp_cmd_desc *cmd = d; 1880 struct txp_rsp_desc *rsp = d; 1881 struct txp_tx_desc *txd = d; 1882 struct txp_frag_desc *frgd = d; 1883 1884 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1885 case CMD_FLAGS_TYPE_CMD: 1886 /* command descriptor */ 1887 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1888 "0x%x par3 0x%x]\n", 1889 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1890 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1891 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1892 break; 1893 case CMD_FLAGS_TYPE_RESP: 1894 /* response descriptor */ 1895 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1896 "0x%x par3 0x%x]\n", 1897 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1898 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1899 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1900 break; 1901 case CMD_FLAGS_TYPE_DATA: 1902 /* data header (assuming tx for now) */ 1903 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x " 1904 "pflags 0x%x]", 1905 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1906 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1907 break; 1908 case CMD_FLAGS_TYPE_FRAG: 1909 /* fragment descriptor */ 1910 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x " 1911 "rsvd2 0x%x]", 1912 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1913 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1914 break; 1915 default: 1916 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 " 1917 "0x%x par2 0x%x par3 0x%x]\n", 1918 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1919 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1920 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1921 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1922 break; 1923 } 1924 } 1925 #endif 1926 1927 static void 1928 txp_set_filter(struct txp_softc *sc) 1929 { 1930 struct ethercom *ec = &sc->sc_arpcom; 1931 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1932 uint32_t crc, carry, hashbit, hash[2]; 1933 uint16_t filter; 1934 uint8_t octet; 1935 int i, j, mcnt = 0; 1936 struct ether_multi *enm; 1937 struct ether_multistep step; 1938 1939 if (ifp->if_flags & IFF_PROMISC) { 1940 filter = TXP_RXFILT_PROMISC; 1941 goto setit; 1942 } 1943 1944 again: 1945 filter = TXP_RXFILT_DIRECT; 1946 1947 if (ifp->if_flags & IFF_BROADCAST) 1948 filter |= TXP_RXFILT_BROADCAST; 1949 1950 if (ifp->if_flags & IFF_ALLMULTI) 1951 filter |= TXP_RXFILT_ALLMULTI; 1952 else { 1953 hash[0] = hash[1] = 0; 1954 1955 ETHER_LOCK(ec); 1956 ETHER_FIRST_MULTI(step, ec, enm); 1957 while (enm != NULL) { 1958 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1959 ETHER_ADDR_LEN)) { 1960 /* 1961 * We must listen to a range of multicast 1962 * addresses. For now, just accept all 1963 * multicasts, rather than trying to set only 1964 * those filter bits needed to match the range. 1965 * (At this time, the only use of address 1966 * ranges is for IP multicast routing, for 1967 * which the range is big enough to require 1968 * all bits set.) 1969 */ 1970 ifp->if_flags |= IFF_ALLMULTI; 1971 ETHER_UNLOCK(ec); 1972 goto again; 1973 } 1974 1975 mcnt++; 1976 crc = 0xffffffff; 1977 1978 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1979 octet = enm->enm_addrlo[i]; 1980 for (j = 0; j < 8; j++) { 1981 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1982 (octet & 1); 1983 crc <<= 1; 1984 octet >>= 1; 1985 if (carry) 1986 crc = (crc ^ TXP_POLYNOMIAL) | 1987 carry; 1988 } 1989 } 1990 hashbit = (uint16_t)(crc & (64 - 1)); 1991 hash[hashbit / 32] |= (1 << hashbit % 32); 1992 ETHER_NEXT_MULTI(step, enm); 1993 } 1994 ETHER_UNLOCK(ec); 1995 1996 if (mcnt > 0) { 1997 filter |= TXP_RXFILT_HASHMULTI; 1998 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1999 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2000 } 2001 } 2002 2003 setit: 2004 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2005 NULL, NULL, NULL, 1); 2006 } 2007 2008 static void 2009 txp_capabilities(struct txp_softc *sc) 2010 { 2011 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2012 struct txp_rsp_desc *rsp = NULL; 2013 struct txp_ext_desc *ext; 2014 2015 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2016 goto out; 2017 2018 if (rsp->rsp_numdesc != 1) 2019 goto out; 2020 ext = (struct txp_ext_desc *)(rsp + 1); 2021 2022 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2023 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2024 2025 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2026 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2027 sc->sc_tx_capability |= OFFLOAD_VLAN; 2028 sc->sc_rx_capability |= OFFLOAD_VLAN; 2029 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2030 sc->sc_arpcom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 2031 } 2032 2033 #if 0 2034 /* not ready yet */ 2035 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2036 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2037 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2038 ifp->if_capabilities |= IFCAP_IPSEC; 2039 } 2040 #endif 2041 2042 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2043 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2044 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2045 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2046 } 2047 2048 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2049 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2050 #ifdef TRY_TX_TCP_CSUM 2051 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2052 ifp->if_capabilities |= 2053 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2054 #endif 2055 } 2056 2057 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2058 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2059 #ifdef TRY_TX_UDP_CSUM 2060 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2061 ifp->if_capabilities |= 2062 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2063 #endif 2064 } 2065 2066 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2067 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2068 goto out; 2069 2070 out: 2071 if (rsp != NULL) 2072 free(rsp, M_DEVBUF); 2073 } 2074
Indexes created Tue Sep 30 20:09:53 GMT 2025