if_txp.c revision 1.76
1 /* $NetBSD: if_txp.c,v 1.76 2024/06/29 12:11:12 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.76 2024/06/29 12:11:12 riastradh Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/device.h> 46 #include <sys/callout.h> 47 #include <sys/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_types.h> 52 #include <net/if_ether.h> 53 #include <net/if_arp.h> 54 #include <net/if_media.h> 55 #include <net/bpf.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_inarp.h> 63 #endif 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcidevs.h> 70 71 #include <dev/pci/if_txpreg.h> 72 73 #include <dev/microcode/typhoon/3c990img.h> 74 75 /* 76 * These currently break the 3c990 firmware, hopefully will be resolved 77 * at some point. 78 */ 79 #undef TRY_TX_UDP_CSUM 80 #undef TRY_TX_TCP_CSUM 81 82 static int txp_probe(device_t, cfdata_t, void *); 83 static void txp_attach(device_t, device_t, void *); 84 static int txp_intr(void *); 85 static void txp_tick(void *); 86 static bool txp_shutdown(device_t, int); 87 static int txp_ioctl(struct ifnet *, u_long, void *); 88 static void txp_start(struct ifnet *); 89 static void txp_stop(struct txp_softc *); 90 static void txp_init(struct txp_softc *); 91 static void txp_watchdog(struct ifnet *); 92 93 static int txp_chip_init(struct txp_softc *); 94 static int txp_reset_adapter(struct txp_softc *); 95 static int txp_download_fw(struct txp_softc *); 96 static int txp_download_fw_wait(struct txp_softc *); 97 static int txp_download_fw_section(struct txp_softc *, 98 const struct txp_fw_section_header *, int); 99 static int txp_alloc_rings(struct txp_softc *); 100 static void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 101 static int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 102 static void txp_set_filter(struct txp_softc *); 103 104 static int txp_cmd_desc_numfree(struct txp_softc *); 105 static int txp_command(struct txp_softc *, uint16_t, uint16_t, uint32_t, 106 uint32_t, uint16_t *, uint32_t *, uint32_t *, int); 107 static int txp_command2(struct txp_softc *, uint16_t, uint16_t, 108 uint32_t, uint32_t, struct txp_ext_desc *, uint8_t, 109 struct txp_rsp_desc **, int); 110 static int txp_response(struct txp_softc *, uint32_t, uint16_t, uint16_t, 111 struct txp_rsp_desc **); 112 static void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 113 struct txp_rsp_desc *); 114 static void txp_capabilities(struct txp_softc *); 115 116 static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 117 static int txp_ifmedia_upd(struct ifnet *); 118 static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 119 struct txp_dma_alloc *); 120 static void txp_rxbuf_reclaim(struct txp_softc *); 121 static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 122 struct txp_dma_alloc *); 123 124 static void txp_rxd_free(struct txp_softc *, struct txp_swdesc *); 125 static struct txp_swdesc *txp_rxd_alloc(struct txp_softc *); 126 127 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 128 NULL, NULL); 129 130 static const struct txp_pci_match { 131 int vid, did, flags; 132 } txp_devices[] = { 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 141 }; 142 143 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 144 145 static const struct { 146 uint16_t mask, value; 147 int flags; 148 } txp_subsysinfo[] = { 149 {0xf000, 0x2000, TXP_SERVERVERSION}, 150 {0x0100, 0x0100, TXP_FIBER}, 151 #if 0 /* information from 3com header, unused */ 152 {0x0010, 0x0010, /* secured firmware */}, 153 {0x0003, 0x0000, /* variable DES */}, 154 {0x0003, 0x0001, /* single DES - "95" */}, 155 {0x0003, 0x0002, /* triple DES - "97" */}, 156 #endif 157 }; 158 159 static const struct txp_pci_match * 160 txp_pcilookup(pcireg_t id) 161 { 162 int i; 163 164 for (i = 0; i < __arraycount(txp_devices); i++) 165 if (PCI_VENDOR(id) == txp_devices[i].vid && 166 PCI_PRODUCT(id) == txp_devices[i].did) 167 return &txp_devices[i]; 168 return (0); 169 } 170 171 static int 172 txp_probe(device_t parent, cfdata_t match, void *aux) 173 { 174 struct pci_attach_args *pa = aux; 175 176 if (txp_pcilookup(pa->pa_id)) 177 return (1); 178 return (0); 179 } 180 181 static void 182 txp_attach(device_t parent, device_t self, void *aux) 183 { 184 struct txp_softc *sc = device_private(self); 185 struct pci_attach_args *pa = aux; 186 pci_chipset_tag_t pc = pa->pa_pc; 187 pci_intr_handle_t ih; 188 const char *intrstr = NULL; 189 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 190 uint32_t command; 191 uint16_t p1; 192 uint32_t p2; 193 u_char enaddr[6]; 194 const struct txp_pci_match *match; 195 uint16_t subsys; 196 int i, flags; 197 char devinfo[256]; 198 char intrbuf[PCI_INTRSTR_LEN]; 199 200 sc->sc_dev = self; 201 sc->sc_cold = 1; 202 203 match = txp_pcilookup(pa->pa_id); 204 flags = match->flags; 205 if (match->flags & TXP_USESUBSYSTEM) { 206 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 207 PCI_SUBSYS_ID_REG)); 208 for (i = 0; 209 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 210 i++) 211 if ((subsys & txp_subsysinfo[i].mask) == 212 txp_subsysinfo[i].value) 213 flags |= txp_subsysinfo[i].flags; 214 } 215 sc->sc_flags = flags; 216 217 aprint_naive("\n"); 218 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 219 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM | TXP_SERVERVERSION)) == \ 220 (TXP_USESUBSYSTEM | TXP_SERVERVERSION) ? " (SVR)" : "") 221 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 222 device_xname(sc->sc_dev)); 223 224 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 225 226 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 227 aprint_error(": failed to enable bus mastering\n"); 228 return; 229 } 230 231 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 232 aprint_error(": failed to enable memory mapping\n"); 233 return; 234 } 235 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 236 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 237 aprint_error(": can't map mem space %d\n", 0); 238 return; 239 } 240 241 if (pci_dma64_available(pa)) 242 sc->sc_dmat = pa->pa_dmat64; 243 else 244 sc->sc_dmat = pa->pa_dmat; 245 246 /* 247 * Allocate our interrupt. 248 */ 249 if (pci_intr_map(pa, &ih)) { 250 aprint_error(": couldn't map interrupt\n"); 251 return; 252 } 253 254 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 255 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, txp_intr, sc, 256 device_xname(self)); 257 if (sc->sc_ih == NULL) { 258 aprint_error(": couldn't establish interrupt"); 259 if (intrstr != NULL) 260 aprint_normal(" at %s", intrstr); 261 aprint_normal("\n"); 262 return; 263 } 264 aprint_normal(": interrupting at %s\n", intrstr); 265 266 if (txp_chip_init(sc)) 267 goto cleanupintr; 268 269 if (txp_download_fw(sc)) 270 goto cleanupintr; 271 272 if (txp_alloc_rings(sc)) 273 goto cleanupintr; 274 275 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 276 NULL, NULL, NULL, 1)) 277 goto cleanupintr; 278 279 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 280 &p1, &p2, NULL, 1)) 281 goto cleanupintr; 282 283 p1 = htole16(p1); 284 enaddr[0] = ((uint8_t *)&p1)[1]; 285 enaddr[1] = ((uint8_t *)&p1)[0]; 286 p2 = htole32(p2); 287 enaddr[2] = ((uint8_t *)&p2)[3]; 288 enaddr[3] = ((uint8_t *)&p2)[2]; 289 enaddr[4] = ((uint8_t *)&p2)[1]; 290 enaddr[5] = ((uint8_t *)&p2)[0]; 291 292 aprint_normal_dev(self, "Ethernet address %s\n", 293 ether_sprintf(enaddr)); 294 sc->sc_cold = 0; 295 296 /* Initialize ifmedia structures. */ 297 sc->sc_arpcom.ec_ifmedia = &sc->sc_ifmedia; 298 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 299 if (flags & TXP_FIBER) { 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX, 301 0, NULL); 302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_FDX, 303 0, NULL); 304 } else { 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 312 0, NULL); 313 } 314 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 315 316 sc->sc_xcvr = TXP_XCVR_AUTO; 317 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 318 NULL, NULL, NULL, 0); 319 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 320 321 ifp->if_softc = sc; 322 ifp->if_mtu = ETHERMTU; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_ioctl = txp_ioctl; 325 ifp->if_start = txp_start; 326 ifp->if_watchdog = txp_watchdog; 327 ifp->if_baudrate = 10000000; 328 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 329 IFQ_SET_READY(&ifp->if_snd); 330 ifp->if_capabilities = 0; 331 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 332 333 txp_capabilities(sc); 334 335 callout_init(&sc->sc_tick, 0); 336 callout_setfunc(&sc->sc_tick, txp_tick, sc); 337 338 /* 339 * Attach us everywhere 340 */ 341 if_attach(ifp); 342 if_deferred_start_init(ifp, NULL); 343 ether_ifattach(ifp, enaddr); 344 345 /* 346 * XXX Because we allocate Rx buffers in txp_alloc_rings(), 347 * XXX we have to go back and claim them now that our mowners 348 * XXX have been initialized (in ether_ifattach()). 349 * 350 * XXX FIXME by allocating Rx buffers only when interface is 351 * XXX running, like other drivers do. 352 */ 353 for (i = 0; i < RXBUF_ENTRIES; i++) { 354 KASSERT(sc->sc_rxd[i].sd_mbuf != NULL); 355 MCLAIM(sc->sc_rxd[i].sd_mbuf, &sc->sc_arpcom.ec_rx_mowner); 356 } 357 358 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 359 pmf_class_network_register(self, ifp); 360 else 361 aprint_error_dev(self, "couldn't establish power handler\n"); 362 363 return; 364 365 cleanupintr: 366 pci_intr_disestablish(pc, sc->sc_ih); 367 368 return; 369 370 } 371 372 static int 373 txp_chip_init(struct txp_softc *sc) 374 { 375 /* disable interrupts */ 376 WRITE_REG(sc, TXP_IER, 0); 377 WRITE_REG(sc, TXP_IMR, 378 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 379 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 380 TXP_INT_LATCH); 381 382 /* ack all interrupts */ 383 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 384 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 385 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 386 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 387 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 388 389 if (txp_reset_adapter(sc)) 390 return (-1); 391 392 /* disable interrupts */ 393 WRITE_REG(sc, TXP_IER, 0); 394 WRITE_REG(sc, TXP_IMR, 395 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 396 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 397 TXP_INT_LATCH); 398 399 /* ack all interrupts */ 400 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 401 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 402 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 403 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 404 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 405 406 return (0); 407 } 408 409 static int 410 txp_reset_adapter(struct txp_softc *sc) 411 { 412 uint32_t r; 413 int i; 414 415 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 416 DELAY(1000); 417 WRITE_REG(sc, TXP_SRR, 0); 418 419 /* Should wait max 6 seconds */ 420 for (i = 0; i < 6000; i++) { 421 r = READ_REG(sc, TXP_A2H_0); 422 if (r == STAT_WAITING_FOR_HOST_REQUEST) 423 break; 424 DELAY(1000); 425 } 426 427 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 428 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 429 return (-1); 430 } 431 432 return (0); 433 } 434 435 static int 436 txp_download_fw(struct txp_softc *sc) 437 { 438 const struct txp_fw_file_header *fileheader; 439 const struct txp_fw_section_header *secthead; 440 int sect; 441 uint32_t r, i, ier, imr; 442 443 ier = READ_REG(sc, TXP_IER); 444 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 445 446 imr = READ_REG(sc, TXP_IMR); 447 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 448 449 for (i = 0; i < 10000; i++) { 450 r = READ_REG(sc, TXP_A2H_0); 451 if (r == STAT_WAITING_FOR_HOST_REQUEST) 452 break; 453 DELAY(50); 454 } 455 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 456 printf(": not waiting for host request\n"); 457 return (-1); 458 } 459 460 /* Ack the status */ 461 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 462 463 fileheader = (const struct txp_fw_file_header *)tc990image; 464 if (memcmp("TYPHOON", fileheader->magicid, 465 sizeof(fileheader->magicid))) { 466 printf(": fw invalid magic\n"); 467 return (-1); 468 } 469 470 /* Tell boot firmware to get ready for image */ 471 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 472 WRITE_REG(sc, TXP_H2A_2, le32toh(fileheader->hmac[0])); 473 WRITE_REG(sc, TXP_H2A_3, le32toh(fileheader->hmac[1])); 474 WRITE_REG(sc, TXP_H2A_4, le32toh(fileheader->hmac[2])); 475 WRITE_REG(sc, TXP_H2A_5, le32toh(fileheader->hmac[3])); 476 WRITE_REG(sc, TXP_H2A_6, le32toh(fileheader->hmac[4])); 477 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 478 479 if (txp_download_fw_wait(sc)) { 480 printf("%s: fw wait failed, initial\n", 481 device_xname(sc->sc_dev)); 482 return (-1); 483 } 484 485 secthead = (const struct txp_fw_section_header *) 486 (((const uint8_t *)tc990image) + 487 sizeof(struct txp_fw_file_header)); 488 489 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 490 if (txp_download_fw_section(sc, secthead, sect)) 491 return (-1); 492 secthead = (const struct txp_fw_section_header *) 493 (((const uint8_t *)secthead) + le32toh(secthead->nbytes) + 494 sizeof(*secthead)); 495 } 496 497 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 498 499 for (i = 0; i < 10000; i++) { 500 r = READ_REG(sc, TXP_A2H_0); 501 if (r == STAT_WAITING_FOR_BOOT) 502 break; 503 DELAY(50); 504 } 505 if (r != STAT_WAITING_FOR_BOOT) { 506 printf(": not waiting for boot\n"); 507 return (-1); 508 } 509 510 WRITE_REG(sc, TXP_IER, ier); 511 WRITE_REG(sc, TXP_IMR, imr); 512 513 return (0); 514 } 515 516 static int 517 txp_download_fw_wait(struct txp_softc *sc) 518 { 519 uint32_t i, r; 520 521 for (i = 0; i < 10000; i++) { 522 r = READ_REG(sc, TXP_ISR); 523 if (r & TXP_INT_A2H_0) 524 break; 525 DELAY(50); 526 } 527 528 if (!(r & TXP_INT_A2H_0)) { 529 printf(": fw wait failed comm0\n"); 530 return (-1); 531 } 532 533 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 534 535 r = READ_REG(sc, TXP_A2H_0); 536 if (r != STAT_WAITING_FOR_SEGMENT) { 537 printf(": fw not waiting for segment\n"); 538 return (-1); 539 } 540 return (0); 541 } 542 543 static int 544 txp_download_fw_section(struct txp_softc *sc, 545 const struct txp_fw_section_header *sect, int sectnum) 546 { 547 struct txp_dma_alloc dma; 548 int rseg, err = 0; 549 struct mbuf m; 550 #ifdef INET 551 uint16_t csum; 552 #endif 553 554 /* Skip zero length sections */ 555 if (sect->nbytes == 0) 556 return (0); 557 558 /* Make sure we aren't past the end of the image */ 559 rseg = ((const uint8_t *)sect) - ((const uint8_t *)tc990image); 560 if (rseg >= sizeof(tc990image)) { 561 printf(": fw invalid section address, section %d\n", sectnum); 562 return (-1); 563 } 564 565 /* Make sure this section doesn't go past the end */ 566 rseg += le32toh(sect->nbytes); 567 if (rseg >= sizeof(tc990image)) { 568 printf(": fw truncated section %d\n", sectnum); 569 return (-1); 570 } 571 572 /* map a buffer, copy segment to it, get physaddr */ 573 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 574 printf(": fw dma malloc failed, section %d\n", sectnum); 575 return (-1); 576 } 577 578 memcpy(dma.dma_vaddr, ((const uint8_t *)sect) + sizeof(*sect), 579 le32toh(sect->nbytes)); 580 581 /* 582 * dummy up mbuf and verify section checksum 583 */ 584 m.m_type = MT_DATA; 585 m.m_next = m.m_nextpkt = NULL; 586 m.m_owner = NULL; 587 m.m_len = le32toh(sect->nbytes); 588 m.m_data = dma.dma_vaddr; 589 m.m_flags = 0; 590 #ifdef INET 591 csum = in_cksum(&m, le32toh(sect->nbytes)); 592 if (csum != sect->cksum) { 593 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 594 sectnum, sect->cksum, csum); 595 txp_dma_free(sc, &dma); 596 return -1; 597 } 598 #endif 599 600 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 601 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 602 603 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 604 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 605 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 606 WRITE_REG(sc, TXP_H2A_4, BUS_ADDR_HI32(dma.dma_paddr)); 607 WRITE_REG(sc, TXP_H2A_5, BUS_ADDR_LO32(dma.dma_paddr)); 608 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 609 610 if (txp_download_fw_wait(sc)) { 611 printf("%s: fw wait failed, section %d\n", 612 device_xname(sc->sc_dev), sectnum); 613 err = -1; 614 } 615 616 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 617 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 618 619 txp_dma_free(sc, &dma); 620 return (err); 621 } 622 623 static int 624 txp_intr(void *vsc) 625 { 626 struct txp_softc *sc = vsc; 627 struct txp_hostvar *hv = sc->sc_hostvar; 628 uint32_t isr; 629 int claimed = 0; 630 631 /* mask all interrupts */ 632 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 633 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 634 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 635 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 636 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 637 638 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 639 sizeof(struct txp_hostvar), 640 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 641 642 isr = READ_REG(sc, TXP_ISR); 643 while (isr) { 644 claimed = 1; 645 WRITE_REG(sc, TXP_ISR, isr); 646 647 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 648 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 649 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 650 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 651 652 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 653 txp_rxbuf_reclaim(sc); 654 655 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 656 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 657 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 658 659 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 660 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 661 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 662 663 isr = READ_REG(sc, TXP_ISR); 664 } 665 666 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 667 sizeof(struct txp_hostvar), 668 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 669 670 /* unmask all interrupts */ 671 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 672 673 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 674 675 return (claimed); 676 } 677 678 static struct txp_swdesc * 679 txp_rxd_alloc(struct txp_softc *sc) 680 { 681 if (sc->sc_txd_pool_ptr == 0) 682 return NULL; 683 return sc->sc_rxd_pool[--sc->sc_txd_pool_ptr]; 684 } 685 686 static void 687 txp_rxd_free(struct txp_softc *sc, struct txp_swdesc *sd) 688 { 689 KASSERT(sc->sc_txd_pool_ptr < RXBUF_ENTRIES); 690 sc->sc_rxd_pool[sc->sc_txd_pool_ptr++] = sd; 691 } 692 693 static inline uint32_t 694 txp_rxd_idx(struct txp_softc *sc, struct txp_swdesc *sd) 695 { 696 KASSERT(sd >= &sc->sc_rxd[0] && sd < &sc->sc_rxd[RXBUF_ENTRIES]); 697 return (uint32_t)(sd - &sc->sc_rxd[0]); 698 } 699 700 static inline uint32_t 701 txp_txd_idx(struct txp_softc *sc, struct txp_swdesc *sd) 702 { 703 KASSERT(sd >= &sc->sc_txd[0] && sd < &sc->sc_txd[TX_ENTRIES]); 704 return (uint32_t)(sd - &sc->sc_txd[0]); 705 } 706 707 static void 708 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 709 struct txp_dma_alloc *dma) 710 { 711 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 712 struct txp_rx_desc *rxd; 713 struct mbuf *m; 714 struct txp_swdesc *sd; 715 uint32_t roff, woff; 716 uint16_t len; 717 int sumflags = 0; 718 int idx; 719 720 roff = le32toh(*r->r_roff); 721 woff = le32toh(*r->r_woff); 722 idx = roff / sizeof(struct txp_rx_desc); 723 rxd = r->r_desc + idx; 724 725 while (roff != woff) { 726 727 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 728 idx * sizeof(struct txp_rx_desc), 729 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 730 731 if (rxd->rx_flags & RX_FLAGS_ERROR) { 732 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 733 le32toh(rxd->rx_stat)); 734 if_statinc(ifp, if_ierrors); 735 goto next; 736 } 737 738 /* retrieve stashed pointer */ 739 KASSERT(rxd->rx_vaddrlo < RXBUF_ENTRIES); 740 sd = &sc->sc_rxd[rxd->rx_vaddrlo]; 741 742 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 743 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 744 745 len = le16toh(rxd->rx_len); 746 747 #ifdef __NO_STRICT_ALIGNMENT 748 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 749 m = sd->sd_mbuf; 750 sd->sd_mbuf = NULL; 751 txp_rxd_free(sc, sd); 752 #else 753 /* 754 * The Typhoon's receive buffers must be 4-byte aligned. 755 * But this means the data after the Ethernet header 756 * is misaligned. We must allocate a new buffer and 757 * copy the data, shifted forward 2 bytes. 758 */ 759 MGETHDR(m, M_DONTWAIT, MT_DATA); 760 if (m == NULL) { 761 dropit: 762 if_statinc(ifp, if_ierrors); 763 txp_rxd_free(sc, sd); 764 goto next; 765 } 766 MCLAIM(m, &sc->sc_arpcom.ec_rx_mowner); 767 if (len > (MHLEN - ETHER_ALIGN)) { 768 MCLGET(m, M_DONTWAIT); 769 if ((m->m_flags & M_EXT) == 0) { 770 m_freem(m); 771 goto dropit; 772 } 773 } 774 m_set_rcvif(m, ifp); 775 m->m_data += ETHER_ALIGN; 776 memcpy(mtod(m, void *), mtod(sd->sd_mbuf, void *), len); 777 txp_rxd_free(sc, sd); 778 #endif /* __NO_STRICT_ALIGNMENT */ 779 780 m->m_pkthdr.len = m->m_len = len; 781 782 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 783 sumflags |= (M_CSUM_IPv4 | M_CSUM_IPv4_BAD); 784 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 785 sumflags |= M_CSUM_IPv4; 786 787 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 788 sumflags |= (M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD); 789 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 790 sumflags |= M_CSUM_TCPv4; 791 792 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 793 sumflags |= (M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD); 794 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 795 sumflags |= M_CSUM_UDPv4; 796 797 m->m_pkthdr.csum_flags = sumflags; 798 799 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 800 vlan_set_tag(m, htons(rxd->rx_vlan >> 16)); 801 } 802 803 if_percpuq_enqueue(ifp->if_percpuq, m); 804 805 next: 806 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 807 idx * sizeof(struct txp_rx_desc), 808 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 809 810 roff += sizeof(struct txp_rx_desc); 811 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 812 idx = 0; 813 roff = 0; 814 rxd = r->r_desc; 815 } else { 816 idx++; 817 rxd++; 818 } 819 woff = le32toh(*r->r_woff); 820 } 821 822 *r->r_roff = htole32(woff); 823 } 824 825 static void 826 txp_rxbuf_reclaim(struct txp_softc *sc) 827 { 828 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 829 struct txp_hostvar *hv = sc->sc_hostvar; 830 struct txp_rxbuf_desc *rbd; 831 struct txp_swdesc *sd; 832 uint32_t i, end; 833 834 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 835 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 836 837 if (++i == RXBUF_ENTRIES) 838 i = 0; 839 840 rbd = sc->sc_rxbufs + i; 841 842 while (i != end) { 843 sd = txp_rxd_alloc(sc); 844 if (sd == NULL) 845 break; 846 847 /* We might already have a buffer allocated. */ 848 if (sd->sd_mbuf == NULL) { 849 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 850 if (sd->sd_mbuf == NULL) 851 goto err_sd; 852 MCLAIM(sd->sd_mbuf, &sc->sc_arpcom.ec_rx_mowner); 853 854 MCLGET(sd->sd_mbuf, M_DONTWAIT); 855 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 856 goto err_mbuf; 857 m_set_rcvif(sd->sd_mbuf, ifp); 858 sd->sd_mbuf->m_pkthdr.len = 859 sd->sd_mbuf->m_len = MCLBYTES; 860 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, 861 sd->sd_mbuf, BUS_DMA_NOWAIT)) { 862 goto err_mbuf; 863 } 864 } 865 866 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 867 i * sizeof(struct txp_rxbuf_desc), 868 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 869 870 /* stash away pointer */ 871 rbd->rb_vaddrlo = txp_rxd_idx(sc, sd); 872 873 rbd->rb_paddrlo = 874 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr)); 875 rbd->rb_paddrhi = 876 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr)); 877 878 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 879 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 880 881 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 882 i * sizeof(struct txp_rxbuf_desc), 883 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 884 885 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 886 887 if (++i == RXBUF_ENTRIES) { 888 i = 0; 889 rbd = sc->sc_rxbufs; 890 } else 891 rbd++; 892 } 893 return; 894 895 err_mbuf: 896 m_freem(sd->sd_mbuf); 897 sd->sd_mbuf = NULL; 898 err_sd: 899 txp_rxd_free(sc, sd); 900 } 901 902 /* 903 * Reclaim mbufs and entries from a transmit ring. 904 */ 905 static void 906 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 907 struct txp_dma_alloc *dma) 908 { 909 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 910 uint32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 911 uint32_t cons = r->r_cons, cnt = r->r_cnt; 912 struct txp_tx_desc *txd = r->r_desc + cons; 913 struct txp_swdesc *sd; 914 struct mbuf *m; 915 916 while (cons != idx) { 917 if (cnt == 0) 918 break; 919 920 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 921 cons * sizeof(struct txp_tx_desc), 922 sizeof(struct txp_tx_desc), 923 BUS_DMASYNC_POSTWRITE); 924 925 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 926 TX_FLAGS_TYPE_DATA) { 927 KASSERT(txd->tx_addrlo < TX_ENTRIES); 928 sd = &sc->sc_txd[txd->tx_addrlo]; 929 m = sd->sd_mbuf; 930 sd->sd_mbuf = NULL; 931 if (m != NULL) { 932 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 933 sd->sd_map->dm_mapsize, 934 BUS_DMASYNC_POSTWRITE); 935 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 936 m_freem(m); 937 txd->tx_addrlo = 0; 938 txd->tx_addrhi = 0; 939 if_statinc(ifp, if_opackets); 940 } 941 } 942 ifp->if_flags &= ~IFF_OACTIVE; 943 944 if (++cons == TX_ENTRIES) { 945 txd = r->r_desc; 946 cons = 0; 947 } else 948 txd++; 949 950 cnt--; 951 } 952 953 r->r_cons = cons; 954 r->r_cnt = cnt; 955 if (cnt == 0) 956 ifp->if_timer = 0; 957 } 958 959 static bool 960 txp_shutdown(device_t self, int howto) 961 { 962 struct txp_softc *sc; 963 964 sc = device_private(self); 965 966 /* mask all interrupts */ 967 WRITE_REG(sc, TXP_IMR, 968 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 969 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 970 TXP_INT_LATCH); 971 972 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 973 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 974 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 975 976 return true; 977 } 978 979 static int 980 txp_alloc_rings(struct txp_softc *sc) 981 { 982 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 983 struct txp_boot_record *boot; 984 struct txp_swdesc *sd; 985 uint32_t r; 986 int i, j, nb; 987 988 /* boot record */ 989 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 990 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 991 printf(": can't allocate boot record\n"); 992 return (-1); 993 } 994 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 995 memset(boot, 0, sizeof(*boot)); 996 sc->sc_boot = boot; 997 998 /* host variables */ 999 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 1000 BUS_DMA_COHERENT)) { 1001 printf(": can't allocate host ring\n"); 1002 goto bail_boot; 1003 } 1004 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 1005 boot->br_hostvar_lo = htole32(BUS_ADDR_LO32(sc->sc_host_dma.dma_paddr)); 1006 boot->br_hostvar_hi = htole32(BUS_ADDR_HI32(sc->sc_host_dma.dma_paddr)); 1007 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 1008 1009 /* high priority tx ring */ 1010 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1011 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 1012 printf(": can't allocate high tx ring\n"); 1013 goto bail_host; 1014 } 1015 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 1016 sizeof(struct txp_tx_desc) * TX_ENTRIES); 1017 boot->br_txhipri_lo = 1018 htole32(BUS_ADDR_LO32(sc->sc_txhiring_dma.dma_paddr)); 1019 boot->br_txhipri_hi = 1020 htole32(BUS_ADDR_HI32(sc->sc_txhiring_dma.dma_paddr)); 1021 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1022 sc->sc_txhir.r_reg = TXP_H2A_1; 1023 sc->sc_txhir.r_desc = 1024 (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 1025 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 1026 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 1027 for (i = 0; i < TX_ENTRIES; i++) { 1028 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1029 TXP_MAXTXSEGS, TXP_MAX_SEGLEN, 0, BUS_DMA_NOWAIT, 1030 &sc->sc_txd[i].sd_map) != 0) { 1031 for (j = 0; j < i; j++) { 1032 bus_dmamap_destroy(sc->sc_dmat, 1033 sc->sc_txd[j].sd_map); 1034 sc->sc_txd[j].sd_map = NULL; 1035 } 1036 goto bail_txhiring; 1037 } 1038 } 1039 1040 /* low priority tx ring */ 1041 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1042 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1043 printf(": can't allocate low tx ring\n"); 1044 goto bail_txhiring; 1045 } 1046 memset(sc->sc_txloring_dma.dma_vaddr, 0, 1047 sizeof(struct txp_tx_desc) * TX_ENTRIES); 1048 boot->br_txlopri_lo = 1049 htole32(BUS_ADDR_LO32(sc->sc_txloring_dma.dma_paddr)); 1050 boot->br_txlopri_hi = 1051 htole32(BUS_ADDR_HI32(sc->sc_txloring_dma.dma_paddr)); 1052 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1053 sc->sc_txlor.r_reg = TXP_H2A_3; 1054 sc->sc_txlor.r_desc = 1055 (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1056 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1057 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1058 1059 /* high priority rx ring */ 1060 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1061 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1062 printf(": can't allocate high rx ring\n"); 1063 goto bail_txloring; 1064 } 1065 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1066 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1067 boot->br_rxhipri_lo = 1068 htole32(BUS_ADDR_LO32(sc->sc_rxhiring_dma.dma_paddr)); 1069 boot->br_rxhipri_hi = 1070 htole32(BUS_ADDR_HI32(sc->sc_rxhiring_dma.dma_paddr)); 1071 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1072 sc->sc_rxhir.r_desc = 1073 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1074 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1075 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1076 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1077 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1078 1079 /* low priority ring */ 1080 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1081 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1082 printf(": can't allocate low rx ring\n"); 1083 goto bail_rxhiring; 1084 } 1085 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1086 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1087 boot->br_rxlopri_lo = 1088 htole32(BUS_ADDR_LO32(sc->sc_rxloring_dma.dma_paddr)); 1089 boot->br_rxlopri_hi = 1090 htole32(BUS_ADDR_HI32(sc->sc_rxloring_dma.dma_paddr)); 1091 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1092 sc->sc_rxlor.r_desc = 1093 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1094 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1095 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1096 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1097 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1098 1099 /* command ring */ 1100 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1101 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1102 printf(": can't allocate command ring\n"); 1103 goto bail_rxloring; 1104 } 1105 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1106 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1107 boot->br_cmd_lo = htole32(BUS_ADDR_LO32(sc->sc_cmdring_dma.dma_paddr)); 1108 boot->br_cmd_hi = htole32(BUS_ADDR_HI32(sc->sc_cmdring_dma.dma_paddr)); 1109 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1110 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1111 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1112 sc->sc_cmdring.lastwrite = 0; 1113 1114 /* response ring */ 1115 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1116 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1117 printf(": can't allocate response ring\n"); 1118 goto bail_cmdring; 1119 } 1120 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1121 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1122 boot->br_resp_lo = htole32(BUS_ADDR_LO32(sc->sc_rspring_dma.dma_paddr)); 1123 boot->br_resp_hi = htole32(BUS_ADDR_HI32(sc->sc_rspring_dma.dma_paddr)); 1124 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1125 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1126 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1127 sc->sc_rspring.lastwrite = 0; 1128 1129 /* receive buffer ring */ 1130 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1131 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1132 printf(": can't allocate rx buffer ring\n"); 1133 goto bail_rspring; 1134 } 1135 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1136 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1137 boot->br_rxbuf_lo = htole32(BUS_ADDR_LO32(sc->sc_rxbufring_dma.dma_paddr)); 1138 boot->br_rxbuf_hi = htole32(BUS_ADDR_HI32(sc->sc_rxbufring_dma.dma_paddr)); 1139 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1140 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1141 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1142 sd = &sc->sc_rxd[nb]; 1143 1144 /* stash away pointer */ 1145 sc->sc_rxbufs[nb].rb_vaddrlo = txp_rxd_idx(sc, sd); 1146 1147 MGETHDR(sd->sd_mbuf, M_WAIT, MT_DATA); 1148 if (sd->sd_mbuf == NULL) { 1149 goto bail_rxbufring; 1150 } 1151 1152 MCLGET(sd->sd_mbuf, M_WAIT); 1153 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1154 goto bail_rxbufring; 1155 } 1156 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1157 m_set_rcvif(sd->sd_mbuf, ifp); 1158 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1159 TXP_MAX_PKTLEN, 0, BUS_DMA_WAITOK, &sd->sd_map)) { 1160 goto bail_rxbufring; 1161 } 1162 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1163 BUS_DMA_WAITOK)) { 1164 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1165 goto bail_rxbufring; 1166 } 1167 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1168 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1169 1170 sc->sc_rxbufs[nb].rb_paddrlo = 1171 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr)); 1172 sc->sc_rxbufs[nb].rb_paddrhi = 1173 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr)); 1174 } 1175 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1176 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1177 BUS_DMASYNC_PREWRITE); 1178 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1179 sizeof(struct txp_rxbuf_desc)); 1180 1181 /* zero dma */ 1182 if (txp_dma_malloc(sc, sizeof(uint32_t), &sc->sc_zero_dma, 1183 BUS_DMA_COHERENT)) { 1184 printf(": can't allocate response ring\n"); 1185 goto bail_rxbufring; 1186 } 1187 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(uint32_t)); 1188 boot->br_zero_lo = htole32(BUS_ADDR_LO32(sc->sc_zero_dma.dma_paddr)); 1189 boot->br_zero_hi = htole32(BUS_ADDR_HI32(sc->sc_zero_dma.dma_paddr)); 1190 1191 /* See if it's waiting for boot, and try to boot it */ 1192 for (i = 0; i < 10000; i++) { 1193 r = READ_REG(sc, TXP_A2H_0); 1194 if (r == STAT_WAITING_FOR_BOOT) 1195 break; 1196 DELAY(50); 1197 } 1198 if (r != STAT_WAITING_FOR_BOOT) { 1199 printf(": not waiting for boot\n"); 1200 goto bail; 1201 } 1202 WRITE_REG(sc, TXP_H2A_2, BUS_ADDR_HI32(sc->sc_boot_dma.dma_paddr)); 1203 WRITE_REG(sc, TXP_H2A_1, BUS_ADDR_LO32(sc->sc_boot_dma.dma_paddr)); 1204 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1205 1206 /* See if it booted */ 1207 for (i = 0; i < 10000; i++) { 1208 r = READ_REG(sc, TXP_A2H_0); 1209 if (r == STAT_RUNNING) 1210 break; 1211 DELAY(50); 1212 } 1213 if (r != STAT_RUNNING) { 1214 printf(": fw not running\n"); 1215 goto bail; 1216 } 1217 1218 /* Clear TX and CMD ring write registers */ 1219 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1220 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1221 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1222 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1223 1224 return (0); 1225 1226 bail: 1227 txp_dma_free(sc, &sc->sc_zero_dma); 1228 bail_rxbufring: 1229 if (nb == RXBUF_ENTRIES) 1230 nb--; 1231 for (i = 0; i <= nb; i++) { 1232 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1233 sizeof(sd)); 1234 /* XXXJRT */ 1235 } 1236 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1237 bail_rspring: 1238 txp_dma_free(sc, &sc->sc_rspring_dma); 1239 bail_cmdring: 1240 txp_dma_free(sc, &sc->sc_cmdring_dma); 1241 bail_rxloring: 1242 txp_dma_free(sc, &sc->sc_rxloring_dma); 1243 bail_rxhiring: 1244 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1245 bail_txloring: 1246 txp_dma_free(sc, &sc->sc_txloring_dma); 1247 bail_txhiring: 1248 txp_dma_free(sc, &sc->sc_txhiring_dma); 1249 bail_host: 1250 txp_dma_free(sc, &sc->sc_host_dma); 1251 bail_boot: 1252 txp_dma_free(sc, &sc->sc_boot_dma); 1253 return (-1); 1254 } 1255 1256 static int 1257 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1258 struct txp_dma_alloc *dma, int mapflags) 1259 { 1260 int r; 1261 1262 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1263 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1264 goto fail_0; 1265 1266 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1267 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1268 goto fail_1; 1269 1270 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1271 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1272 goto fail_2; 1273 1274 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1275 size, NULL, BUS_DMA_NOWAIT)) != 0) 1276 goto fail_3; 1277 1278 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1279 return (0); 1280 1281 fail_3: 1282 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1283 fail_2: 1284 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1285 fail_1: 1286 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1287 fail_0: 1288 return (r); 1289 } 1290 1291 static void 1292 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1293 { 1294 bus_size_t mapsize = dma->dma_map->dm_mapsize; 1295 1296 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1297 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, mapsize); 1298 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1299 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1300 } 1301 1302 static int 1303 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1304 { 1305 struct txp_softc *sc = ifp->if_softc; 1306 struct ifaddr *ifa = (struct ifaddr *)data; 1307 int s, error = 0; 1308 1309 s = splnet(); 1310 1311 #if 0 1312 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1313 splx(s); 1314 return error; 1315 } 1316 #endif 1317 1318 switch (command) { 1319 case SIOCINITIFADDR: 1320 ifp->if_flags |= IFF_UP; 1321 txp_init(sc); 1322 switch (ifa->ifa_addr->sa_family) { 1323 #ifdef INET 1324 case AF_INET: 1325 arp_ifinit(ifp, ifa); 1326 break; 1327 #endif /* INET */ 1328 default: 1329 break; 1330 } 1331 break; 1332 case SIOCSIFFLAGS: 1333 if ((error = ifioctl_common(ifp, command, data)) != 0) 1334 break; 1335 if (ifp->if_flags & IFF_UP) { 1336 txp_init(sc); 1337 } else { 1338 if (ifp->if_flags & IFF_RUNNING) 1339 txp_stop(sc); 1340 } 1341 break; 1342 case SIOCADDMULTI: 1343 case SIOCDELMULTI: 1344 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1345 break; 1346 1347 error = 0; 1348 1349 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1350 ; 1351 else if (ifp->if_flags & IFF_RUNNING) { 1352 /* 1353 * Multicast list has changed; set the hardware 1354 * filter accordingly. 1355 */ 1356 txp_set_filter(sc); 1357 } 1358 break; 1359 default: 1360 error = ether_ioctl(ifp, command, data); 1361 break; 1362 } 1363 1364 splx(s); 1365 1366 return (error); 1367 } 1368 1369 static void 1370 txp_init(struct txp_softc *sc) 1371 { 1372 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1373 int s; 1374 1375 txp_stop(sc); 1376 1377 s = splnet(); 1378 1379 txp_set_filter(sc); 1380 1381 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1382 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1383 1384 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1385 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1386 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1387 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1388 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1389 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1390 1391 ifp->if_flags |= IFF_RUNNING; 1392 ifp->if_flags &= ~IFF_OACTIVE; 1393 ifp->if_timer = 0; 1394 1395 if (!callout_pending(&sc->sc_tick)) 1396 callout_schedule(&sc->sc_tick, hz); 1397 1398 splx(s); 1399 } 1400 1401 static void 1402 txp_tick(void *vsc) 1403 { 1404 struct txp_softc *sc = vsc; 1405 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1406 struct txp_rsp_desc *rsp = NULL; 1407 struct txp_ext_desc *ext; 1408 int s; 1409 1410 s = splnet(); 1411 txp_rxbuf_reclaim(sc); 1412 1413 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1414 &rsp, 1)) 1415 goto out; 1416 if (rsp->rsp_numdesc != 6) 1417 goto out; 1418 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1419 NULL, NULL, NULL, 1)) 1420 goto out; 1421 ext = (struct txp_ext_desc *)(rsp + 1); 1422 1423 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1424 if_statadd_ref(ifp, nsr, if_ierrors, 1425 ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1426 ext[4].ext_1 + ext[4].ext_4); 1427 if_statadd_ref(ifp, nsr, if_oerrors, 1428 ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + ext[2].ext_1); 1429 if_statadd_ref(ifp, nsr, if_collisions, 1430 ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + ext[1].ext_3); 1431 if_statadd_ref(ifp, nsr, if_opackets, rsp->rsp_par2); 1432 IF_STAT_PUTREF(ifp); 1433 1434 out: 1435 if (rsp != NULL) 1436 free(rsp, M_DEVBUF); 1437 1438 splx(s); 1439 callout_schedule(&sc->sc_tick, hz); 1440 } 1441 1442 static void 1443 txp_start(struct ifnet *ifp) 1444 { 1445 struct txp_softc *sc = ifp->if_softc; 1446 struct txp_tx_ring *r = &sc->sc_txhir; 1447 struct txp_tx_desc *txd; 1448 int txdidx; 1449 struct txp_frag_desc *fxd; 1450 struct mbuf *m, *mnew; 1451 struct txp_swdesc *sd; 1452 uint32_t prod, cnt, i; 1453 int error; 1454 1455 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1456 return; 1457 1458 prod = r->r_prod; 1459 cnt = r->r_cnt; 1460 1461 while (1) { 1462 if (cnt >= TX_ENTRIES - TXP_MAXTXSEGS - 4) { 1463 ifp->if_flags |= IFF_OACTIVE; 1464 break; 1465 } 1466 1467 IFQ_POLL(&ifp->if_snd, m); 1468 if (m == NULL) 1469 break; 1470 mnew = NULL; 1471 1472 sd = sc->sc_txd + prod; 1473 1474 /* 1475 * Load the DMA map. If this fails, the packet either 1476 * didn't fit in the allotted number of segments, or we 1477 * were short on resources. In this case, we'll copy 1478 * and try again. 1479 */ 1480 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1481 BUS_DMA_NOWAIT) != 0) { 1482 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1483 if (mnew == NULL) { 1484 printf("%s: unable to allocate Tx mbuf\n", 1485 device_xname(sc->sc_dev)); 1486 break; 1487 } 1488 MCLAIM(mnew, &sc->sc_arpcom.ec_tx_mowner); 1489 if (m->m_pkthdr.len > MHLEN) { 1490 MCLGET(mnew, M_DONTWAIT); 1491 if ((mnew->m_flags & M_EXT) == 0) { 1492 printf("%s: unable to allocate Tx " 1493 "cluster\n", 1494 device_xname(sc->sc_dev)); 1495 m_freem(mnew); 1496 break; 1497 } 1498 } 1499 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1500 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1501 error = bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, 1502 mnew, BUS_DMA_NOWAIT); 1503 if (error) { 1504 printf("%s: unable to load Tx buffer, " 1505 "error = %d\n", device_xname(sc->sc_dev), 1506 error); 1507 m_freem(mnew); 1508 break; 1509 } 1510 } 1511 1512 IFQ_DEQUEUE(&ifp->if_snd, m); 1513 if (mnew != NULL) { 1514 m_freem(m); 1515 m = mnew; 1516 } 1517 1518 /* 1519 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1520 */ 1521 1522 sd->sd_mbuf = m; 1523 1524 txd = r->r_desc + prod; 1525 txdidx = prod; 1526 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1527 txd->tx_numdesc = 0; 1528 txd->tx_addrlo = txp_txd_idx(sc, sd); 1529 txd->tx_addrhi = 0; 1530 txd->tx_totlen = m->m_pkthdr.len; 1531 txd->tx_pflags = 0; 1532 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1533 1534 if (++prod == TX_ENTRIES) 1535 prod = 0; 1536 cnt++; 1537 1538 if (vlan_has_tag(m)) 1539 txd->tx_pflags = TX_PFLAGS_VLAN | 1540 (htons(vlan_get_tag(m)) << TX_PFLAGS_VLANTAG_S); 1541 1542 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1543 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1544 #ifdef TRY_TX_TCP_CSUM 1545 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1546 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1547 #endif 1548 #ifdef TRY_TX_UDP_CSUM 1549 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1550 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1551 #endif 1552 1553 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1554 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1555 1556 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1557 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1558 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1559 FRAG_FLAGS_VALID; 1560 fxd->frag_rsvd1 = 0; 1561 fxd->frag_len = htole16(sd->sd_map->dm_segs[i].ds_len); 1562 fxd->frag_addrlo = 1563 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[i].ds_addr)); 1564 fxd->frag_addrhi = 1565 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[i].ds_addr)); 1566 fxd->frag_rsvd2 = 0; 1567 1568 bus_dmamap_sync(sc->sc_dmat, 1569 sc->sc_txhiring_dma.dma_map, 1570 prod * sizeof(struct txp_frag_desc), 1571 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1572 1573 if (++prod == TX_ENTRIES) { 1574 fxd = (struct txp_frag_desc *)r->r_desc; 1575 prod = 0; 1576 } else 1577 fxd++; 1578 cnt++; 1579 } 1580 1581 ifp->if_timer = 5; 1582 1583 bpf_mtap(ifp, m, BPF_D_OUT); 1584 1585 txd->tx_flags |= TX_FLAGS_VALID; 1586 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1587 txdidx * sizeof(struct txp_tx_desc), 1588 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1589 1590 #if 0 1591 { 1592 struct mbuf *mx; 1593 int i; 1594 1595 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1596 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1597 txd->tx_pflags); 1598 for (mx = m; mx != NULL; mx = mx->m_next) { 1599 for (i = 0; i < mx->m_len; i++) { 1600 printf(":%02x", 1601 (uint8_t)m->m_data[i]); 1602 } 1603 } 1604 printf("\n"); 1605 } 1606 #endif 1607 1608 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1609 } 1610 1611 r->r_prod = prod; 1612 r->r_cnt = cnt; 1613 } 1614 1615 /* 1616 * Handle simple commands sent to the typhoon 1617 */ 1618 static int 1619 txp_command(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1620 uint32_t in3, uint16_t *out1, uint32_t *out2, uint32_t *out3, int wait) 1621 { 1622 struct txp_rsp_desc *rsp = NULL; 1623 1624 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1625 return (-1); 1626 1627 if (!wait) 1628 return (0); 1629 1630 if (out1 != NULL) 1631 *out1 = le16toh(rsp->rsp_par1); 1632 if (out2 != NULL) 1633 *out2 = le32toh(rsp->rsp_par2); 1634 if (out3 != NULL) 1635 *out3 = le32toh(rsp->rsp_par3); 1636 free(rsp, M_DEVBUF); 1637 return (0); 1638 } 1639 1640 static int 1641 txp_command2(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1642 uint32_t in3, struct txp_ext_desc *in_extp, uint8_t in_extn, 1643 struct txp_rsp_desc **rspp, int wait) 1644 { 1645 struct txp_hostvar *hv = sc->sc_hostvar; 1646 struct txp_cmd_desc *cmd; 1647 struct txp_ext_desc *ext; 1648 uint32_t idx, i; 1649 uint16_t seq; 1650 1651 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1652 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1653 return (-1); 1654 } 1655 1656 idx = sc->sc_cmdring.lastwrite; 1657 cmd = (struct txp_cmd_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1658 memset(cmd, 0, sizeof(*cmd)); 1659 1660 cmd->cmd_numdesc = in_extn; 1661 seq = sc->sc_seq++; 1662 cmd->cmd_seq = htole16(seq); 1663 cmd->cmd_id = htole16(id); 1664 cmd->cmd_par1 = htole16(in1); 1665 cmd->cmd_par2 = htole32(in2); 1666 cmd->cmd_par3 = htole32(in3); 1667 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1668 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1669 1670 idx += sizeof(struct txp_cmd_desc); 1671 if (idx == sc->sc_cmdring.size) 1672 idx = 0; 1673 1674 for (i = 0; i < in_extn; i++) { 1675 ext = (struct txp_ext_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1676 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1677 in_extp++; 1678 idx += sizeof(struct txp_cmd_desc); 1679 if (idx == sc->sc_cmdring.size) 1680 idx = 0; 1681 } 1682 1683 sc->sc_cmdring.lastwrite = idx; 1684 1685 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1686 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1687 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1688 1689 if (!wait) 1690 return (0); 1691 1692 for (i = 0; i < 10000; i++) { 1693 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1694 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1695 idx = le32toh(hv->hv_resp_read_idx); 1696 if (idx != le32toh(hv->hv_resp_write_idx)) { 1697 *rspp = NULL; 1698 if (txp_response(sc, idx, id, seq, rspp)) 1699 return (-1); 1700 if (*rspp != NULL) 1701 break; 1702 } 1703 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1704 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1705 DELAY(50); 1706 } 1707 if (i == 1000 || (*rspp) == NULL) { 1708 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1709 return (-1); 1710 } 1711 1712 return (0); 1713 } 1714 1715 static int 1716 txp_response(struct txp_softc *sc, uint32_t ridx, uint16_t id, uint16_t seq, 1717 struct txp_rsp_desc **rspp) 1718 { 1719 struct txp_hostvar *hv = sc->sc_hostvar; 1720 struct txp_rsp_desc *rsp; 1721 1722 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1723 rsp = (struct txp_rsp_desc *)(((uint8_t *)sc->sc_rspring.base) + ridx); 1724 1725 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1726 *rspp = (struct txp_rsp_desc *)malloc( 1727 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1728 M_DEVBUF, M_NOWAIT); 1729 if ((*rspp) == NULL) 1730 return (-1); 1731 txp_rsp_fixup(sc, rsp, *rspp); 1732 return (0); 1733 } 1734 1735 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1736 printf("%s: response error: id 0x%x\n", 1737 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1738 txp_rsp_fixup(sc, rsp, NULL); 1739 ridx = le32toh(hv->hv_resp_read_idx); 1740 continue; 1741 } 1742 1743 switch (le16toh(rsp->rsp_id)) { 1744 case TXP_CMD_CYCLE_STATISTICS: 1745 case TXP_CMD_MEDIA_STATUS_READ: 1746 break; 1747 case TXP_CMD_HELLO_RESPONSE: 1748 printf("%s: hello\n", TXP_DEVNAME(sc)); 1749 break; 1750 default: 1751 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1752 le16toh(rsp->rsp_id)); 1753 } 1754 1755 txp_rsp_fixup(sc, rsp, NULL); 1756 ridx = le32toh(hv->hv_resp_read_idx); 1757 hv->hv_resp_read_idx = le32toh(ridx); 1758 } 1759 1760 return (0); 1761 } 1762 1763 static void 1764 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1765 struct txp_rsp_desc *dst) 1766 { 1767 struct txp_rsp_desc *src = rsp; 1768 struct txp_hostvar *hv = sc->sc_hostvar; 1769 uint32_t i, ridx; 1770 1771 ridx = le32toh(hv->hv_resp_read_idx); 1772 1773 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1774 if (dst != NULL) 1775 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1776 ridx += sizeof(struct txp_rsp_desc); 1777 if (ridx == sc->sc_rspring.size) { 1778 src = sc->sc_rspring.base; 1779 ridx = 0; 1780 } else 1781 src++; 1782 sc->sc_rspring.lastwrite = ridx; 1783 hv->hv_resp_read_idx = htole32(ridx); 1784 } 1785 1786 hv->hv_resp_read_idx = htole32(ridx); 1787 } 1788 1789 static int 1790 txp_cmd_desc_numfree(struct txp_softc *sc) 1791 { 1792 struct txp_hostvar *hv = sc->sc_hostvar; 1793 struct txp_boot_record *br = sc->sc_boot; 1794 uint32_t widx, ridx, nfree; 1795 1796 widx = sc->sc_cmdring.lastwrite; 1797 ridx = le32toh(hv->hv_cmd_read_idx); 1798 1799 if (widx == ridx) { 1800 /* Ring is completely free */ 1801 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1802 } else { 1803 if (widx > ridx) 1804 nfree = le32toh(br->br_cmd_siz) - 1805 (widx - ridx + sizeof(struct txp_cmd_desc)); 1806 else 1807 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1808 } 1809 1810 return (nfree / sizeof(struct txp_cmd_desc)); 1811 } 1812 1813 static void 1814 txp_stop(struct txp_softc *sc) 1815 { 1816 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1817 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1818 1819 if (callout_pending(&sc->sc_tick)) 1820 callout_stop(&sc->sc_tick); 1821 } 1822 1823 static void 1824 txp_watchdog(struct ifnet *ifp) 1825 { 1826 } 1827 1828 static int 1829 txp_ifmedia_upd(struct ifnet *ifp) 1830 { 1831 struct txp_softc *sc = ifp->if_softc; 1832 struct ifmedia *ifm = &sc->sc_ifmedia; 1833 uint16_t new_xcvr; 1834 1835 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1836 return (EINVAL); 1837 1838 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1839 if ((ifm->ifm_media & IFM_FDX) != 0) 1840 new_xcvr = TXP_XCVR_10_FDX; 1841 else 1842 new_xcvr = TXP_XCVR_10_HDX; 1843 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1844 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1845 if ((ifm->ifm_media & IFM_FDX) != 0) 1846 new_xcvr = TXP_XCVR_100_FDX; 1847 else 1848 new_xcvr = TXP_XCVR_100_HDX; 1849 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1850 new_xcvr = TXP_XCVR_AUTO; 1851 } else 1852 return (EINVAL); 1853 1854 /* nothing to do */ 1855 if (sc->sc_xcvr == new_xcvr) 1856 return (0); 1857 1858 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1859 NULL, NULL, NULL, 0); 1860 sc->sc_xcvr = new_xcvr; 1861 1862 return (0); 1863 } 1864 1865 static void 1866 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1867 { 1868 struct txp_softc *sc = ifp->if_softc; 1869 struct ifmedia *ifm = &sc->sc_ifmedia; 1870 uint16_t bmsr, bmcr, anlpar; 1871 1872 ifmr->ifm_status = IFM_AVALID; 1873 ifmr->ifm_active = IFM_ETHER; 1874 1875 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1876 &bmsr, NULL, NULL, 1)) 1877 goto bail; 1878 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1879 &bmsr, NULL, NULL, 1)) 1880 goto bail; 1881 1882 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1883 &bmcr, NULL, NULL, 1)) 1884 goto bail; 1885 1886 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1887 &anlpar, NULL, NULL, 1)) 1888 goto bail; 1889 1890 if (bmsr & BMSR_LINK) 1891 ifmr->ifm_status |= IFM_ACTIVE; 1892 1893 if (bmcr & BMCR_ISO) { 1894 ifmr->ifm_active |= IFM_NONE; 1895 ifmr->ifm_status = 0; 1896 return; 1897 } 1898 1899 if (bmcr & BMCR_LOOP) 1900 ifmr->ifm_active |= IFM_LOOP; 1901 1902 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1903 if ((bmsr & BMSR_ACOMP) == 0) { 1904 ifmr->ifm_active |= IFM_NONE; 1905 return; 1906 } 1907 1908 if (anlpar & ANLPAR_TX_FD) 1909 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 1910 else if (anlpar & ANLPAR_T4) 1911 ifmr->ifm_active |= IFM_100_T4 | IFM_HDX; 1912 else if (anlpar & ANLPAR_TX) 1913 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 1914 else if (anlpar & ANLPAR_10_FD) 1915 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 1916 else if (anlpar & ANLPAR_10) 1917 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 1918 else 1919 ifmr->ifm_active |= IFM_NONE; 1920 } else 1921 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1922 return; 1923 1924 bail: 1925 ifmr->ifm_active |= IFM_NONE; 1926 ifmr->ifm_status &= ~IFM_AVALID; 1927 } 1928 1929 #if 0 /* XXX XXX XXX UNUSED */ 1930 static void 1931 txp_show_descriptor(void *d) 1932 { 1933 struct txp_cmd_desc *cmd = d; 1934 struct txp_rsp_desc *rsp = d; 1935 struct txp_tx_desc *txd = d; 1936 struct txp_frag_desc *frgd = d; 1937 1938 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1939 case CMD_FLAGS_TYPE_CMD: 1940 /* command descriptor */ 1941 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1942 "0x%x par3 0x%x]\n", 1943 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1944 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1945 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1946 break; 1947 case CMD_FLAGS_TYPE_RESP: 1948 /* response descriptor */ 1949 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1950 "0x%x par3 0x%x]\n", 1951 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1952 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1953 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1954 break; 1955 case CMD_FLAGS_TYPE_DATA: 1956 /* data header (assuming tx for now) */ 1957 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x " 1958 "pflags 0x%x]", 1959 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1960 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1961 break; 1962 case CMD_FLAGS_TYPE_FRAG: 1963 /* fragment descriptor */ 1964 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x " 1965 "rsvd2 0x%x]", 1966 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1967 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1968 break; 1969 default: 1970 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 " 1971 "0x%x par2 0x%x par3 0x%x]\n", 1972 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1973 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1974 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1975 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1976 break; 1977 } 1978 } 1979 #endif 1980 1981 static void 1982 txp_set_filter(struct txp_softc *sc) 1983 { 1984 struct ethercom *ec = &sc->sc_arpcom; 1985 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1986 uint32_t crc, carry, hashbit, hash[2]; 1987 uint16_t filter; 1988 uint8_t octet; 1989 int i, j, mcnt = 0; 1990 struct ether_multi *enm; 1991 struct ether_multistep step; 1992 1993 if (ifp->if_flags & IFF_PROMISC) { 1994 filter = TXP_RXFILT_PROMISC; 1995 goto setit; 1996 } 1997 1998 again: 1999 filter = TXP_RXFILT_DIRECT; 2000 2001 if (ifp->if_flags & IFF_BROADCAST) 2002 filter |= TXP_RXFILT_BROADCAST; 2003 2004 if (ifp->if_flags & IFF_ALLMULTI) 2005 filter |= TXP_RXFILT_ALLMULTI; 2006 else { 2007 hash[0] = hash[1] = 0; 2008 2009 ETHER_LOCK(ec); 2010 ETHER_FIRST_MULTI(step, ec, enm); 2011 while (enm != NULL) { 2012 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2013 ETHER_ADDR_LEN)) { 2014 /* 2015 * We must listen to a range of multicast 2016 * addresses. For now, just accept all 2017 * multicasts, rather than trying to set only 2018 * those filter bits needed to match the range. 2019 * (At this time, the only use of address 2020 * ranges is for IP multicast routing, for 2021 * which the range is big enough to require 2022 * all bits set.) 2023 */ 2024 ifp->if_flags |= IFF_ALLMULTI; 2025 ETHER_UNLOCK(ec); 2026 goto again; 2027 } 2028 2029 mcnt++; 2030 crc = 0xffffffff; 2031 2032 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2033 octet = enm->enm_addrlo[i]; 2034 for (j = 0; j < 8; j++) { 2035 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2036 (octet & 1); 2037 crc <<= 1; 2038 octet >>= 1; 2039 if (carry) 2040 crc = (crc ^ TXP_POLYNOMIAL) | 2041 carry; 2042 } 2043 } 2044 hashbit = (uint16_t)(crc & (64 - 1)); 2045 hash[hashbit / 32] |= (1 << hashbit % 32); 2046 ETHER_NEXT_MULTI(step, enm); 2047 } 2048 ETHER_UNLOCK(ec); 2049 2050 if (mcnt > 0) { 2051 filter |= TXP_RXFILT_HASHMULTI; 2052 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2053 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2054 } 2055 } 2056 2057 setit: 2058 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2059 NULL, NULL, NULL, 1); 2060 } 2061 2062 static void 2063 txp_capabilities(struct txp_softc *sc) 2064 { 2065 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2066 struct txp_rsp_desc *rsp = NULL; 2067 struct txp_ext_desc *ext; 2068 2069 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2070 goto out; 2071 2072 if (rsp->rsp_numdesc != 1) 2073 goto out; 2074 ext = (struct txp_ext_desc *)(rsp + 1); 2075 2076 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2077 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2078 2079 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2080 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2081 sc->sc_tx_capability |= OFFLOAD_VLAN; 2082 sc->sc_rx_capability |= OFFLOAD_VLAN; 2083 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2084 sc->sc_arpcom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 2085 } 2086 2087 #if 0 2088 /* not ready yet */ 2089 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2090 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2091 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2092 ifp->if_capabilities |= IFCAP_IPSEC; 2093 } 2094 #endif 2095 2096 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2097 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2098 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2099 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2100 } 2101 2102 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2103 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2104 #ifdef TRY_TX_TCP_CSUM 2105 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2106 ifp->if_capabilities |= 2107 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2108 #endif 2109 } 2110 2111 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2112 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2113 #ifdef TRY_TX_UDP_CSUM 2114 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2115 ifp->if_capabilities |= 2116 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2117 #endif 2118 } 2119 2120 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2121 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2122 goto out; 2123 2124 out: 2125 if (rsp != NULL) 2126 free(rsp, M_DEVBUF); 2127 } 2128
Indexes created Tue Sep 30 20:09:53 GMT 2025