if_vge.c revision 1.2.2.4
1 1.2.2.4 skrll /* $NetBSD: if_vge.c,v 1.2.2.4 2005/11/10 14:06:02 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /*- 4 1.2.2.2 skrll * Copyright (c) 2004 5 1.2.2.2 skrll * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 1.2.2.2 skrll * 7 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 skrll * modification, are permitted provided that the following conditions 9 1.2.2.2 skrll * are met: 10 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll * 3. All advertising materials mentioning features or use of this software 16 1.2.2.2 skrll * must display the following acknowledgement: 17 1.2.2.2 skrll * This product includes software developed by Bill Paul. 18 1.2.2.2 skrll * 4. Neither the name of the author nor the names of any co-contributors 19 1.2.2.2 skrll * may be used to endorse or promote products derived from this software 20 1.2.2.2 skrll * without specific prior written permission. 21 1.2.2.2 skrll * 22 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 1.2.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 1.2.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 1.2.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 1.2.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 1.2.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 1.2.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 1.2.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 1.2.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 1.2.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 1.2.2.2 skrll * THE POSSIBILITY OF SUCH DAMAGE. 33 1.2.2.2 skrll * 34 1.2.2.2 skrll * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 1.2.2.2 skrll */ 36 1.2.2.2 skrll 37 1.2.2.2 skrll #include <sys/cdefs.h> 38 1.2.2.4 skrll __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.2.2.4 2005/11/10 14:06:02 skrll Exp $"); 39 1.2.2.2 skrll 40 1.2.2.2 skrll /* 41 1.2.2.2 skrll * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 1.2.2.2 skrll * 43 1.2.2.2 skrll * Written by Bill Paul <wpaul (at) windriver.com> 44 1.2.2.2 skrll * Senior Networking Software Engineer 45 1.2.2.2 skrll * Wind River Systems 46 1.2.2.2 skrll */ 47 1.2.2.2 skrll 48 1.2.2.2 skrll /* 49 1.2.2.2 skrll * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 50 1.2.2.2 skrll * combines a tri-speed ethernet MAC and PHY, with the following 51 1.2.2.2 skrll * features: 52 1.2.2.2 skrll * 53 1.2.2.2 skrll * o Jumbo frame support up to 16K 54 1.2.2.2 skrll * o Transmit and receive flow control 55 1.2.2.2 skrll * o IPv4 checksum offload 56 1.2.2.2 skrll * o VLAN tag insertion and stripping 57 1.2.2.2 skrll * o TCP large send 58 1.2.2.2 skrll * o 64-bit multicast hash table filter 59 1.2.2.2 skrll * o 64 entry CAM filter 60 1.2.2.2 skrll * o 16K RX FIFO and 48K TX FIFO memory 61 1.2.2.2 skrll * o Interrupt moderation 62 1.2.2.2 skrll * 63 1.2.2.2 skrll * The VT6122 supports up to four transmit DMA queues. The descriptors 64 1.2.2.2 skrll * in the transmit ring can address up to 7 data fragments; frames which 65 1.2.2.2 skrll * span more than 7 data buffers must be coalesced, but in general the 66 1.2.2.2 skrll * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 1.2.2.2 skrll * long. The receive descriptors address only a single buffer. 68 1.2.2.2 skrll * 69 1.2.2.2 skrll * There are two peculiar design issues with the VT6122. One is that 70 1.2.2.2 skrll * receive data buffers must be aligned on a 32-bit boundary. This is 71 1.2.2.2 skrll * not a problem where the VT6122 is used as a LOM device in x86-based 72 1.2.2.2 skrll * systems, but on architectures that generate unaligned access traps, we 73 1.2.2.2 skrll * have to do some copying. 74 1.2.2.2 skrll * 75 1.2.2.2 skrll * The other issue has to do with the way 64-bit addresses are handled. 76 1.2.2.2 skrll * The DMA descriptors only allow you to specify 48 bits of addressing 77 1.2.2.2 skrll * information. The remaining 16 bits are specified using one of the 78 1.2.2.2 skrll * I/O registers. If you only have a 32-bit system, then this isn't 79 1.2.2.2 skrll * an issue, but if you have a 64-bit system and more than 4GB of 80 1.2.2.2 skrll * memory, you must have to make sure your network data buffers reside 81 1.2.2.2 skrll * in the same 48-bit 'segment.' 82 1.2.2.2 skrll * 83 1.2.2.2 skrll * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 1.2.2.2 skrll * and sample NICs for testing. 85 1.2.2.2 skrll */ 86 1.2.2.2 skrll 87 1.2.2.2 skrll #include "bpfilter.h" 88 1.2.2.2 skrll 89 1.2.2.2 skrll #include <sys/param.h> 90 1.2.2.2 skrll #include <sys/endian.h> 91 1.2.2.2 skrll #include <sys/systm.h> 92 1.2.2.2 skrll #include <sys/sockio.h> 93 1.2.2.2 skrll #include <sys/mbuf.h> 94 1.2.2.2 skrll #include <sys/malloc.h> 95 1.2.2.2 skrll #include <sys/kernel.h> 96 1.2.2.2 skrll #include <sys/socket.h> 97 1.2.2.2 skrll 98 1.2.2.2 skrll #include <net/if.h> 99 1.2.2.2 skrll #include <net/if_arp.h> 100 1.2.2.2 skrll #include <net/if_ether.h> 101 1.2.2.2 skrll #include <net/if_dl.h> 102 1.2.2.2 skrll #include <net/if_media.h> 103 1.2.2.2 skrll 104 1.2.2.2 skrll #include <net/bpf.h> 105 1.2.2.2 skrll 106 1.2.2.2 skrll #include <machine/bus.h> 107 1.2.2.2 skrll 108 1.2.2.2 skrll #include <dev/mii/mii.h> 109 1.2.2.2 skrll #include <dev/mii/miivar.h> 110 1.2.2.2 skrll 111 1.2.2.2 skrll #include <dev/pci/pcireg.h> 112 1.2.2.2 skrll #include <dev/pci/pcivar.h> 113 1.2.2.2 skrll #include <dev/pci/pcidevs.h> 114 1.2.2.2 skrll 115 1.2.2.2 skrll #include <dev/pci/if_vgereg.h> 116 1.2.2.2 skrll #include <dev/pci/if_vgevar.h> 117 1.2.2.2 skrll 118 1.2.2.2 skrll static int vge_probe (struct device *, struct cfdata *, void *); 119 1.2.2.2 skrll static void vge_attach (struct device *, struct device *, void *); 120 1.2.2.2 skrll 121 1.2.2.2 skrll static int vge_encap (struct vge_softc *, struct mbuf *, int); 122 1.2.2.2 skrll 123 1.2.2.2 skrll static int vge_dma_map_rx_desc (struct vge_softc *, int); 124 1.2.2.3 skrll static void vge_dma_map_tx_desc (struct vge_softc *, struct mbuf *, int, int); 125 1.2.2.2 skrll static int vge_allocmem (struct vge_softc *); 126 1.2.2.2 skrll static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 127 1.2.2.2 skrll static int vge_rx_list_init (struct vge_softc *); 128 1.2.2.2 skrll static int vge_tx_list_init (struct vge_softc *); 129 1.2.2.2 skrll #ifdef VGE_FIXUP_RX 130 1.2.2.2 skrll static __inline void vge_fixup_rx 131 1.2.2.2 skrll (struct mbuf *); 132 1.2.2.2 skrll #endif 133 1.2.2.2 skrll static void vge_rxeof (struct vge_softc *); 134 1.2.2.2 skrll static void vge_txeof (struct vge_softc *); 135 1.2.2.2 skrll static int vge_intr (void *); 136 1.2.2.2 skrll static void vge_tick (void *); 137 1.2.2.2 skrll static void vge_start (struct ifnet *); 138 1.2.2.2 skrll static int vge_ioctl (struct ifnet *, u_long, caddr_t); 139 1.2.2.2 skrll static int vge_init (struct ifnet *); 140 1.2.2.2 skrll static void vge_stop (struct vge_softc *); 141 1.2.2.2 skrll static void vge_watchdog (struct ifnet *); 142 1.2.2.2 skrll #if VGE_POWER_MANAGEMENT 143 1.2.2.2 skrll static int vge_suspend (struct device *); 144 1.2.2.2 skrll static int vge_resume (struct device *); 145 1.2.2.2 skrll #endif 146 1.2.2.2 skrll static void vge_shutdown (void *); 147 1.2.2.2 skrll static int vge_ifmedia_upd (struct ifnet *); 148 1.2.2.2 skrll static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 1.2.2.2 skrll 150 1.2.2.2 skrll static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 151 1.2.2.2 skrll static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 152 1.2.2.2 skrll 153 1.2.2.2 skrll static void vge_miipoll_start (struct vge_softc *); 154 1.2.2.2 skrll static void vge_miipoll_stop (struct vge_softc *); 155 1.2.2.2 skrll static int vge_miibus_readreg (struct device *, int, int); 156 1.2.2.2 skrll static void vge_miibus_writereg (struct device *, int, int, int); 157 1.2.2.2 skrll static void vge_miibus_statchg (struct device *); 158 1.2.2.2 skrll 159 1.2.2.2 skrll static void vge_cam_clear (struct vge_softc *); 160 1.2.2.2 skrll static int vge_cam_set (struct vge_softc *, uint8_t *); 161 1.2.2.2 skrll static void vge_setmulti (struct vge_softc *); 162 1.2.2.2 skrll static void vge_reset (struct vge_softc *); 163 1.2.2.2 skrll 164 1.2.2.2 skrll #define VGE_PCI_LOIO 0x10 165 1.2.2.2 skrll #define VGE_PCI_LOMEM 0x14 166 1.2.2.2 skrll 167 1.2.2.2 skrll CFATTACH_DECL(vge, sizeof(struct vge_softc), 168 1.2.2.2 skrll vge_probe, vge_attach, NULL, NULL); 169 1.2.2.2 skrll 170 1.2.2.2 skrll /* 171 1.2.2.2 skrll * Defragment mbuf chain contents to be as linear as possible. 172 1.2.2.2 skrll * Returns new mbuf chain on success, NULL on failure. Old mbuf 173 1.2.2.2 skrll * chain is always freed. 174 1.2.2.2 skrll * XXX temporary until there would be generic function doing this. 175 1.2.2.2 skrll */ 176 1.2.2.2 skrll #define m_defrag vge_m_defrag 177 1.2.2.2 skrll struct mbuf * vge_m_defrag(struct mbuf *, int); 178 1.2.2.2 skrll 179 1.2.2.2 skrll struct mbuf * 180 1.2.2.3 skrll vge_m_defrag(struct mbuf *mold, int flags) 181 1.2.2.2 skrll { 182 1.2.2.3 skrll struct mbuf *m0, *mn, *n; 183 1.2.2.3 skrll size_t sz = mold->m_pkthdr.len; 184 1.2.2.2 skrll 185 1.2.2.2 skrll #ifdef DIAGNOSTIC 186 1.2.2.3 skrll if ((mold->m_flags & M_PKTHDR) == 0) 187 1.2.2.2 skrll panic("m_defrag: not a mbuf chain header"); 188 1.2.2.2 skrll #endif 189 1.2.2.2 skrll 190 1.2.2.3 skrll MGETHDR(m0, flags, MT_DATA); 191 1.2.2.3 skrll if (m0 == NULL) 192 1.2.2.3 skrll return NULL; 193 1.2.2.3 skrll m0->m_pkthdr.len = mold->m_pkthdr.len; 194 1.2.2.3 skrll mn = m0; 195 1.2.2.3 skrll 196 1.2.2.3 skrll do { 197 1.2.2.3 skrll if (sz > MHLEN) { 198 1.2.2.3 skrll MCLGET(mn, M_DONTWAIT); 199 1.2.2.3 skrll if ((mn->m_flags & M_EXT) == 0) { 200 1.2.2.3 skrll m_freem(m0); 201 1.2.2.3 skrll return NULL; 202 1.2.2.3 skrll } 203 1.2.2.3 skrll } 204 1.2.2.2 skrll 205 1.2.2.3 skrll mn->m_len = MIN(sz, MCLBYTES); 206 1.2.2.2 skrll 207 1.2.2.3 skrll m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 208 1.2.2.3 skrll mtod(mn, caddr_t)); 209 1.2.2.2 skrll 210 1.2.2.3 skrll sz -= mn->m_len; 211 1.2.2.3 skrll 212 1.2.2.3 skrll if (sz > 0) { 213 1.2.2.3 skrll /* need more mbufs */ 214 1.2.2.3 skrll MGET(n, M_NOWAIT, MT_DATA); 215 1.2.2.3 skrll if (n == NULL) { 216 1.2.2.3 skrll m_freem(m0); 217 1.2.2.3 skrll return NULL; 218 1.2.2.3 skrll } 219 1.2.2.3 skrll 220 1.2.2.3 skrll mn->m_next = n; 221 1.2.2.3 skrll mn = n; 222 1.2.2.3 skrll } 223 1.2.2.3 skrll } while (sz > 0); 224 1.2.2.2 skrll 225 1.2.2.3 skrll return m0; 226 1.2.2.2 skrll } 227 1.2.2.2 skrll 228 1.2.2.2 skrll /* 229 1.2.2.2 skrll * Read a word of data stored in the EEPROM at address 'addr.' 230 1.2.2.2 skrll */ 231 1.2.2.2 skrll static void 232 1.2.2.2 skrll vge_eeprom_getword(sc, addr, dest) 233 1.2.2.2 skrll struct vge_softc *sc; 234 1.2.2.2 skrll int addr; 235 1.2.2.2 skrll u_int16_t *dest; 236 1.2.2.2 skrll { 237 1.2.2.2 skrll register int i; 238 1.2.2.2 skrll u_int16_t word = 0; 239 1.2.2.2 skrll 240 1.2.2.2 skrll /* 241 1.2.2.2 skrll * Enter EEPROM embedded programming mode. In order to 242 1.2.2.2 skrll * access the EEPROM at all, we first have to set the 243 1.2.2.2 skrll * EELOAD bit in the CHIPCFG2 register. 244 1.2.2.2 skrll */ 245 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 246 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 247 1.2.2.2 skrll 248 1.2.2.2 skrll /* Select the address of the word we want to read */ 249 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_EEADDR, addr); 250 1.2.2.2 skrll 251 1.2.2.2 skrll /* Issue read command */ 252 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 253 1.2.2.2 skrll 254 1.2.2.2 skrll /* Wait for the done bit to be set. */ 255 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 256 1.2.2.2 skrll if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 257 1.2.2.2 skrll break; 258 1.2.2.2 skrll } 259 1.2.2.2 skrll 260 1.2.2.2 skrll if (i == VGE_TIMEOUT) { 261 1.2.2.2 skrll printf("%s: EEPROM read timed out\n", sc->sc_dev.dv_xname); 262 1.2.2.2 skrll *dest = 0; 263 1.2.2.2 skrll return; 264 1.2.2.2 skrll } 265 1.2.2.2 skrll 266 1.2.2.2 skrll /* Read the result */ 267 1.2.2.2 skrll word = CSR_READ_2(sc, VGE_EERDDAT); 268 1.2.2.2 skrll 269 1.2.2.2 skrll /* Turn off EEPROM access mode. */ 270 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 271 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 272 1.2.2.2 skrll 273 1.2.2.2 skrll *dest = word; 274 1.2.2.2 skrll 275 1.2.2.2 skrll return; 276 1.2.2.2 skrll } 277 1.2.2.2 skrll 278 1.2.2.2 skrll /* 279 1.2.2.2 skrll * Read a sequence of words from the EEPROM. 280 1.2.2.2 skrll */ 281 1.2.2.2 skrll static void 282 1.2.2.2 skrll vge_read_eeprom(sc, dest, off, cnt, swap) 283 1.2.2.2 skrll struct vge_softc *sc; 284 1.2.2.2 skrll caddr_t dest; 285 1.2.2.2 skrll int off; 286 1.2.2.2 skrll int cnt; 287 1.2.2.2 skrll int swap; 288 1.2.2.2 skrll { 289 1.2.2.2 skrll int i; 290 1.2.2.2 skrll u_int16_t word = 0, *ptr; 291 1.2.2.2 skrll 292 1.2.2.2 skrll for (i = 0; i < cnt; i++) { 293 1.2.2.2 skrll vge_eeprom_getword(sc, off + i, &word); 294 1.2.2.2 skrll ptr = (u_int16_t *)(dest + (i * 2)); 295 1.2.2.2 skrll if (swap) 296 1.2.2.2 skrll *ptr = ntohs(word); 297 1.2.2.2 skrll else 298 1.2.2.2 skrll *ptr = word; 299 1.2.2.2 skrll } 300 1.2.2.2 skrll } 301 1.2.2.2 skrll 302 1.2.2.2 skrll static void 303 1.2.2.2 skrll vge_miipoll_stop(sc) 304 1.2.2.2 skrll struct vge_softc *sc; 305 1.2.2.2 skrll { 306 1.2.2.2 skrll int i; 307 1.2.2.2 skrll 308 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_MIICMD, 0); 309 1.2.2.2 skrll 310 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 311 1.2.2.2 skrll DELAY(1); 312 1.2.2.2 skrll if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 313 1.2.2.2 skrll break; 314 1.2.2.2 skrll } 315 1.2.2.2 skrll 316 1.2.2.2 skrll if (i == VGE_TIMEOUT) { 317 1.2.2.2 skrll printf("%s: failed to idle MII autopoll\n", 318 1.2.2.2 skrll sc->sc_dev.dv_xname); 319 1.2.2.2 skrll } 320 1.2.2.2 skrll 321 1.2.2.2 skrll return; 322 1.2.2.2 skrll } 323 1.2.2.2 skrll 324 1.2.2.2 skrll static void 325 1.2.2.2 skrll vge_miipoll_start(sc) 326 1.2.2.2 skrll struct vge_softc *sc; 327 1.2.2.2 skrll { 328 1.2.2.2 skrll int i; 329 1.2.2.2 skrll 330 1.2.2.2 skrll /* First, make sure we're idle. */ 331 1.2.2.2 skrll 332 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_MIICMD, 0); 333 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 334 1.2.2.2 skrll 335 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 336 1.2.2.2 skrll DELAY(1); 337 1.2.2.2 skrll if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 338 1.2.2.2 skrll break; 339 1.2.2.2 skrll } 340 1.2.2.2 skrll 341 1.2.2.2 skrll if (i == VGE_TIMEOUT) { 342 1.2.2.2 skrll printf("%s: failed to idle MII autopoll\n", 343 1.2.2.2 skrll sc->sc_dev.dv_xname); 344 1.2.2.2 skrll return; 345 1.2.2.2 skrll } 346 1.2.2.2 skrll 347 1.2.2.2 skrll /* Now enable auto poll mode. */ 348 1.2.2.2 skrll 349 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 350 1.2.2.2 skrll 351 1.2.2.2 skrll /* And make sure it started. */ 352 1.2.2.2 skrll 353 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 354 1.2.2.2 skrll DELAY(1); 355 1.2.2.2 skrll if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 356 1.2.2.2 skrll break; 357 1.2.2.2 skrll } 358 1.2.2.2 skrll 359 1.2.2.2 skrll if (i == VGE_TIMEOUT) { 360 1.2.2.2 skrll printf("%s: failed to start MII autopoll\n", 361 1.2.2.2 skrll sc->sc_dev.dv_xname); 362 1.2.2.2 skrll } 363 1.2.2.2 skrll } 364 1.2.2.2 skrll 365 1.2.2.2 skrll static int 366 1.2.2.2 skrll vge_miibus_readreg(dev, phy, reg) 367 1.2.2.2 skrll struct device *dev; 368 1.2.2.2 skrll int phy, reg; 369 1.2.2.2 skrll { 370 1.2.2.2 skrll struct vge_softc *sc = (struct vge_softc *)dev; 371 1.2.2.2 skrll int i; 372 1.2.2.2 skrll u_int16_t rval = 0; 373 1.2.2.2 skrll 374 1.2.2.2 skrll if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 375 1.2.2.2 skrll return(0); 376 1.2.2.2 skrll 377 1.2.2.2 skrll VGE_LOCK(sc); 378 1.2.2.2 skrll vge_miipoll_stop(sc); 379 1.2.2.2 skrll 380 1.2.2.2 skrll /* Specify the register we want to read. */ 381 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_MIIADDR, reg); 382 1.2.2.2 skrll 383 1.2.2.2 skrll /* Issue read command. */ 384 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 385 1.2.2.2 skrll 386 1.2.2.2 skrll /* Wait for the read command bit to self-clear. */ 387 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 388 1.2.2.2 skrll DELAY(1); 389 1.2.2.2 skrll if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 390 1.2.2.2 skrll break; 391 1.2.2.2 skrll } 392 1.2.2.2 skrll 393 1.2.2.2 skrll if (i == VGE_TIMEOUT) 394 1.2.2.2 skrll printf("%s: MII read timed out\n", sc->sc_dev.dv_xname); 395 1.2.2.2 skrll else 396 1.2.2.2 skrll rval = CSR_READ_2(sc, VGE_MIIDATA); 397 1.2.2.2 skrll 398 1.2.2.2 skrll vge_miipoll_start(sc); 399 1.2.2.2 skrll VGE_UNLOCK(sc); 400 1.2.2.2 skrll 401 1.2.2.2 skrll return (rval); 402 1.2.2.2 skrll } 403 1.2.2.2 skrll 404 1.2.2.2 skrll static void 405 1.2.2.2 skrll vge_miibus_writereg(dev, phy, reg, data) 406 1.2.2.2 skrll struct device *dev; 407 1.2.2.2 skrll int phy, reg, data; 408 1.2.2.2 skrll { 409 1.2.2.2 skrll struct vge_softc *sc = (struct vge_softc *)dev; 410 1.2.2.2 skrll int i; 411 1.2.2.2 skrll 412 1.2.2.2 skrll if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 413 1.2.2.2 skrll return; 414 1.2.2.2 skrll 415 1.2.2.2 skrll VGE_LOCK(sc); 416 1.2.2.2 skrll vge_miipoll_stop(sc); 417 1.2.2.2 skrll 418 1.2.2.2 skrll /* Specify the register we want to write. */ 419 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_MIIADDR, reg); 420 1.2.2.2 skrll 421 1.2.2.2 skrll /* Specify the data we want to write. */ 422 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_MIIDATA, data); 423 1.2.2.2 skrll 424 1.2.2.2 skrll /* Issue write command. */ 425 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 426 1.2.2.2 skrll 427 1.2.2.2 skrll /* Wait for the write command bit to self-clear. */ 428 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 429 1.2.2.2 skrll DELAY(1); 430 1.2.2.2 skrll if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 431 1.2.2.2 skrll break; 432 1.2.2.2 skrll } 433 1.2.2.2 skrll 434 1.2.2.2 skrll if (i == VGE_TIMEOUT) { 435 1.2.2.2 skrll printf("%s: MII write timed out\n", sc->sc_dev.dv_xname); 436 1.2.2.2 skrll } 437 1.2.2.2 skrll 438 1.2.2.2 skrll vge_miipoll_start(sc); 439 1.2.2.2 skrll VGE_UNLOCK(sc); 440 1.2.2.2 skrll } 441 1.2.2.2 skrll 442 1.2.2.2 skrll static void 443 1.2.2.2 skrll vge_cam_clear(sc) 444 1.2.2.2 skrll struct vge_softc *sc; 445 1.2.2.2 skrll { 446 1.2.2.2 skrll int i; 447 1.2.2.2 skrll 448 1.2.2.2 skrll /* 449 1.2.2.2 skrll * Turn off all the mask bits. This tells the chip 450 1.2.2.2 skrll * that none of the entries in the CAM filter are valid. 451 1.2.2.2 skrll * desired entries will be enabled as we fill the filter in. 452 1.2.2.2 skrll */ 453 1.2.2.2 skrll 454 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 455 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 456 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 457 1.2.2.2 skrll for (i = 0; i < 8; i++) 458 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 459 1.2.2.2 skrll 460 1.2.2.2 skrll /* Clear the VLAN filter too. */ 461 1.2.2.2 skrll 462 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 463 1.2.2.2 skrll for (i = 0; i < 8; i++) 464 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 465 1.2.2.2 skrll 466 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CAMADDR, 0); 467 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 468 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 469 1.2.2.2 skrll 470 1.2.2.2 skrll sc->vge_camidx = 0; 471 1.2.2.2 skrll 472 1.2.2.2 skrll return; 473 1.2.2.2 skrll } 474 1.2.2.2 skrll 475 1.2.2.2 skrll static int 476 1.2.2.2 skrll vge_cam_set(sc, addr) 477 1.2.2.2 skrll struct vge_softc *sc; 478 1.2.2.2 skrll uint8_t *addr; 479 1.2.2.2 skrll { 480 1.2.2.2 skrll int i, error = 0; 481 1.2.2.2 skrll 482 1.2.2.2 skrll if (sc->vge_camidx == VGE_CAM_MAXADDRS) 483 1.2.2.2 skrll return(ENOSPC); 484 1.2.2.2 skrll 485 1.2.2.2 skrll /* Select the CAM data page. */ 486 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 487 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 488 1.2.2.2 skrll 489 1.2.2.2 skrll /* Set the filter entry we want to update and enable writing. */ 490 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 491 1.2.2.2 skrll 492 1.2.2.2 skrll /* Write the address to the CAM registers */ 493 1.2.2.2 skrll for (i = 0; i < ETHER_ADDR_LEN; i++) 494 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 495 1.2.2.2 skrll 496 1.2.2.2 skrll /* Issue a write command. */ 497 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 498 1.2.2.2 skrll 499 1.2.2.2 skrll /* Wake for it to clear. */ 500 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 501 1.2.2.2 skrll DELAY(1); 502 1.2.2.2 skrll if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 503 1.2.2.2 skrll break; 504 1.2.2.2 skrll } 505 1.2.2.2 skrll 506 1.2.2.2 skrll if (i == VGE_TIMEOUT) { 507 1.2.2.2 skrll printf("%s: setting CAM filter failed\n", sc->sc_dev.dv_xname); 508 1.2.2.2 skrll error = EIO; 509 1.2.2.2 skrll goto fail; 510 1.2.2.2 skrll } 511 1.2.2.2 skrll 512 1.2.2.2 skrll /* Select the CAM mask page. */ 513 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 514 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 515 1.2.2.2 skrll 516 1.2.2.2 skrll /* Set the mask bit that enables this filter. */ 517 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 518 1.2.2.2 skrll 1<<(sc->vge_camidx & 7)); 519 1.2.2.2 skrll 520 1.2.2.2 skrll sc->vge_camidx++; 521 1.2.2.2 skrll 522 1.2.2.2 skrll fail: 523 1.2.2.2 skrll /* Turn off access to CAM. */ 524 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CAMADDR, 0); 525 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 526 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 527 1.2.2.2 skrll 528 1.2.2.2 skrll return (error); 529 1.2.2.2 skrll } 530 1.2.2.2 skrll 531 1.2.2.2 skrll /* 532 1.2.2.2 skrll * Program the multicast filter. We use the 64-entry CAM filter 533 1.2.2.2 skrll * for perfect filtering. If there's more than 64 multicast addresses, 534 1.2.2.2 skrll * we use the hash filter insted. 535 1.2.2.2 skrll */ 536 1.2.2.2 skrll static void 537 1.2.2.2 skrll vge_setmulti(sc) 538 1.2.2.2 skrll struct vge_softc *sc; 539 1.2.2.2 skrll { 540 1.2.2.2 skrll struct ifnet *ifp; 541 1.2.2.2 skrll int error = 0; 542 1.2.2.2 skrll u_int32_t h, hashes[2] = { 0, 0 }; 543 1.2.2.2 skrll struct ether_multi *enm; 544 1.2.2.2 skrll struct ether_multistep step; 545 1.2.2.2 skrll 546 1.2.2.2 skrll ifp = &sc->sc_ethercom.ec_if; 547 1.2.2.2 skrll 548 1.2.2.2 skrll /* First, zot all the multicast entries. */ 549 1.2.2.2 skrll vge_cam_clear(sc); 550 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_MAR0, 0); 551 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_MAR1, 0); 552 1.2.2.4 skrll ifp->if_flags &= ~IFF_ALLMULTI; 553 1.2.2.2 skrll 554 1.2.2.2 skrll /* 555 1.2.2.2 skrll * If the user wants allmulti or promisc mode, enable reception 556 1.2.2.2 skrll * of all multicast frames. 557 1.2.2.2 skrll */ 558 1.2.2.4 skrll if (ifp->if_flags & IFF_PROMISC) { 559 1.2.2.2 skrll allmulti: 560 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 561 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 562 1.2.2.4 skrll ifp->if_flags |= IFF_ALLMULTI; 563 1.2.2.2 skrll return; 564 1.2.2.2 skrll } 565 1.2.2.2 skrll 566 1.2.2.2 skrll /* Now program new ones */ 567 1.2.2.2 skrll ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 568 1.2.2.2 skrll while(enm != NULL) { 569 1.2.2.2 skrll /* 570 1.2.2.2 skrll * If multicast range, fall back to ALLMULTI. 571 1.2.2.2 skrll */ 572 1.2.2.2 skrll if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 573 1.2.2.2 skrll ETHER_ADDR_LEN) != 0) 574 1.2.2.2 skrll goto allmulti; 575 1.2.2.2 skrll 576 1.2.2.4 skrll error = vge_cam_set(sc, enm->enm_addrlo); 577 1.2.2.2 skrll if (error) 578 1.2.2.2 skrll break; 579 1.2.2.2 skrll 580 1.2.2.2 skrll ETHER_NEXT_MULTI(step, enm); 581 1.2.2.2 skrll } 582 1.2.2.2 skrll 583 1.2.2.2 skrll /* If there were too many addresses, use the hash filter. */ 584 1.2.2.2 skrll if (error) { 585 1.2.2.2 skrll vge_cam_clear(sc); 586 1.2.2.2 skrll 587 1.2.2.2 skrll ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 588 1.2.2.2 skrll while(enm != NULL) { 589 1.2.2.4 skrll /* 590 1.2.2.4 skrll * If multicast range, fall back to ALLMULTI. 591 1.2.2.4 skrll */ 592 1.2.2.4 skrll if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 593 1.2.2.4 skrll ETHER_ADDR_LEN) != 0) 594 1.2.2.4 skrll goto allmulti; 595 1.2.2.4 skrll 596 1.2.2.4 skrll h = ether_crc32_be(enm->enm_addrlo, 597 1.2.2.4 skrll ETHER_ADDR_LEN) >> 26; 598 1.2.2.4 skrll hashes[h >> 5] |= 1 << (h & 0x1f); 599 1.2.2.4 skrll 600 1.2.2.4 skrll ETHER_NEXT_MULTI(step, enm); 601 1.2.2.2 skrll } 602 1.2.2.2 skrll 603 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 604 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 605 1.2.2.2 skrll } 606 1.2.2.2 skrll 607 1.2.2.2 skrll return; 608 1.2.2.2 skrll } 609 1.2.2.2 skrll 610 1.2.2.2 skrll static void 611 1.2.2.2 skrll vge_reset(sc) 612 1.2.2.2 skrll struct vge_softc *sc; 613 1.2.2.2 skrll { 614 1.2.2.2 skrll register int i; 615 1.2.2.2 skrll 616 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 617 1.2.2.2 skrll 618 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 619 1.2.2.2 skrll DELAY(5); 620 1.2.2.2 skrll if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 621 1.2.2.2 skrll break; 622 1.2.2.2 skrll } 623 1.2.2.2 skrll 624 1.2.2.2 skrll if (i == VGE_TIMEOUT) { 625 1.2.2.2 skrll printf("%s: soft reset timed out", sc->sc_dev.dv_xname); 626 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 627 1.2.2.2 skrll DELAY(2000); 628 1.2.2.2 skrll } 629 1.2.2.2 skrll 630 1.2.2.2 skrll DELAY(5000); 631 1.2.2.2 skrll 632 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 633 1.2.2.2 skrll 634 1.2.2.2 skrll for (i = 0; i < VGE_TIMEOUT; i++) { 635 1.2.2.2 skrll DELAY(5); 636 1.2.2.2 skrll if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 637 1.2.2.2 skrll break; 638 1.2.2.2 skrll } 639 1.2.2.2 skrll 640 1.2.2.2 skrll if (i == VGE_TIMEOUT) { 641 1.2.2.2 skrll printf("%s: EEPROM reload timed out\n", sc->sc_dev.dv_xname); 642 1.2.2.2 skrll return; 643 1.2.2.2 skrll } 644 1.2.2.2 skrll 645 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 646 1.2.2.2 skrll 647 1.2.2.2 skrll return; 648 1.2.2.2 skrll } 649 1.2.2.2 skrll 650 1.2.2.2 skrll /* 651 1.2.2.2 skrll * Probe for a VIA gigabit chip. Check the PCI vendor and device 652 1.2.2.2 skrll * IDs against our list and return a device name if we find a match. 653 1.2.2.2 skrll */ 654 1.2.2.2 skrll static int 655 1.2.2.2 skrll vge_probe(struct device *parent, struct cfdata *match, void *aux) 656 1.2.2.2 skrll { 657 1.2.2.2 skrll struct pci_attach_args *pa = aux; 658 1.2.2.2 skrll 659 1.2.2.2 skrll if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 660 1.2.2.2 skrll && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 661 1.2.2.2 skrll return 1; 662 1.2.2.2 skrll 663 1.2.2.2 skrll return (0); 664 1.2.2.2 skrll } 665 1.2.2.2 skrll 666 1.2.2.2 skrll static int 667 1.2.2.2 skrll vge_dma_map_rx_desc(sc, idx) 668 1.2.2.2 skrll struct vge_softc *sc; 669 1.2.2.2 skrll int idx; 670 1.2.2.2 skrll { 671 1.2.2.2 skrll struct vge_rx_desc *d = NULL; 672 1.2.2.2 skrll bus_dma_segment_t *segs; 673 1.2.2.2 skrll 674 1.2.2.2 skrll /* 675 1.2.2.2 skrll * Map the segment array into descriptors. 676 1.2.2.2 skrll */ 677 1.2.2.2 skrll 678 1.2.2.2 skrll d = &sc->vge_ldata.vge_rx_list[idx]; 679 1.2.2.2 skrll 680 1.2.2.2 skrll /* If this descriptor is still owned by the chip, bail. */ 681 1.2.2.2 skrll 682 1.2.2.2 skrll if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 683 1.2.2.2 skrll printf("%s: tried to map busy descriptor\n", 684 1.2.2.2 skrll sc->sc_dev.dv_xname); 685 1.2.2.2 skrll return (EBUSY); 686 1.2.2.2 skrll } 687 1.2.2.2 skrll 688 1.2.2.2 skrll segs = sc->vge_ldata.vge_rx_dmamap[idx]->dm_segs; 689 1.2.2.2 skrll 690 1.2.2.2 skrll d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 691 1.2.2.2 skrll d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 692 1.2.2.2 skrll d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 693 1.2.2.2 skrll d->vge_sts = 0; 694 1.2.2.2 skrll d->vge_ctl = 0; 695 1.2.2.2 skrll 696 1.2.2.2 skrll return (0); 697 1.2.2.2 skrll } 698 1.2.2.2 skrll 699 1.2.2.3 skrll static void 700 1.2.2.2 skrll vge_dma_map_tx_desc(sc, m0, idx, flags) 701 1.2.2.2 skrll struct vge_softc *sc; 702 1.2.2.2 skrll struct mbuf *m0; 703 1.2.2.2 skrll int idx, flags; 704 1.2.2.2 skrll { 705 1.2.2.3 skrll struct vge_tx_desc *d = &sc->vge_ldata.vge_tx_list[idx]; 706 1.2.2.2 skrll struct vge_tx_frag *f; 707 1.2.2.2 skrll int i = 0; 708 1.2.2.2 skrll bus_dma_segment_t *segs; 709 1.2.2.2 skrll size_t sz; 710 1.2.2.2 skrll bus_dmamap_t map = sc->vge_ldata.vge_tx_dmamap[idx]; 711 1.2.2.2 skrll 712 1.2.2.2 skrll /* Map the segment array into descriptors. */ 713 1.2.2.2 skrll 714 1.2.2.2 skrll segs = map->dm_segs; 715 1.2.2.2 skrll for (i = 0; i < map->dm_nsegs; i++) { 716 1.2.2.2 skrll f = &d->vge_frag[i]; 717 1.2.2.2 skrll f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 718 1.2.2.2 skrll f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 719 1.2.2.2 skrll f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 720 1.2.2.2 skrll } 721 1.2.2.2 skrll 722 1.2.2.2 skrll /* Argh. This chip does not autopad short frames */ 723 1.2.2.2 skrll 724 1.2.2.2 skrll sz = m0->m_pkthdr.len; 725 1.2.2.2 skrll if (m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 726 1.2.2.2 skrll f = &d->vge_frag[i]; 727 1.2.2.2 skrll f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - sz)); 728 1.2.2.2 skrll f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 729 1.2.2.2 skrll f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 730 1.2.2.2 skrll sz = VGE_MIN_FRAMELEN; 731 1.2.2.2 skrll i++; 732 1.2.2.2 skrll } 733 1.2.2.2 skrll 734 1.2.2.2 skrll /* 735 1.2.2.2 skrll * When telling the chip how many segments there are, we 736 1.2.2.2 skrll * must use nsegs + 1 instead of just nsegs. Darned if I 737 1.2.2.2 skrll * know why. 738 1.2.2.2 skrll */ 739 1.2.2.2 skrll i++; 740 1.2.2.2 skrll 741 1.2.2.2 skrll d->vge_sts = sz << 16; 742 1.2.2.2 skrll d->vge_ctl = flags|(i << 28)|VGE_TD_LS_NORM; 743 1.2.2.2 skrll 744 1.2.2.2 skrll if (sz > ETHERMTU + ETHER_HDR_LEN) 745 1.2.2.2 skrll d->vge_ctl |= VGE_TDCTL_JUMBO; 746 1.2.2.2 skrll } 747 1.2.2.2 skrll 748 1.2.2.2 skrll static int 749 1.2.2.2 skrll vge_allocmem(sc) 750 1.2.2.2 skrll struct vge_softc *sc; 751 1.2.2.2 skrll { 752 1.2.2.2 skrll int error; 753 1.2.2.2 skrll int nseg; 754 1.2.2.2 skrll int i; 755 1.2.2.2 skrll bus_dma_segment_t seg; 756 1.2.2.2 skrll 757 1.2.2.2 skrll /* 758 1.2.2.2 skrll * Allocate map for TX descriptor list. 759 1.2.2.2 skrll */ 760 1.2.2.2 skrll error = bus_dmamap_create(sc->vge_dmat, 761 1.2.2.2 skrll round_page(VGE_TX_LIST_SZ), 1, round_page(VGE_TX_LIST_SZ), 762 1.2.2.2 skrll 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 763 1.2.2.2 skrll &sc->vge_ldata.vge_tx_list_map); 764 1.2.2.2 skrll if (error) { 765 1.2.2.2 skrll printf("%s: could not allocate TX dma list map\n", 766 1.2.2.2 skrll sc->sc_dev.dv_xname); 767 1.2.2.2 skrll return (ENOMEM); 768 1.2.2.2 skrll } 769 1.2.2.2 skrll 770 1.2.2.2 skrll /* 771 1.2.2.2 skrll * Allocate memory for TX descriptor list. 772 1.2.2.2 skrll */ 773 1.2.2.2 skrll 774 1.2.2.2 skrll error = bus_dmamem_alloc(sc->vge_dmat, VGE_TX_LIST_SZ, VGE_RING_ALIGN, 775 1.2.2.2 skrll 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 776 1.2.2.2 skrll if (error) { 777 1.2.2.2 skrll printf("%s: could not allocate TX ring dma memory\n", 778 1.2.2.2 skrll sc->sc_dev.dv_xname); 779 1.2.2.2 skrll return (ENOMEM); 780 1.2.2.2 skrll } 781 1.2.2.2 skrll 782 1.2.2.2 skrll /* Map the memory to kernel VA space */ 783 1.2.2.2 skrll 784 1.2.2.2 skrll error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 785 1.2.2.2 skrll (caddr_t *) &sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 786 1.2.2.2 skrll if (error) { 787 1.2.2.2 skrll printf("%s: could not map TX ring dma memory\n", 788 1.2.2.2 skrll sc->sc_dev.dv_xname); 789 1.2.2.2 skrll return (ENOMEM); 790 1.2.2.2 skrll } 791 1.2.2.2 skrll 792 1.2.2.2 skrll /* Load the map for the TX ring. */ 793 1.2.2.2 skrll error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_tx_list_map, 794 1.2.2.2 skrll sc->vge_ldata.vge_tx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 795 1.2.2.2 skrll if (error) { 796 1.2.2.2 skrll printf("%s: could not load TX ring dma memory\n", 797 1.2.2.2 skrll sc->sc_dev.dv_xname); 798 1.2.2.2 skrll return (ENOMEM); 799 1.2.2.2 skrll } 800 1.2.2.2 skrll 801 1.2.2.2 skrll sc->vge_ldata.vge_tx_list_addr = 802 1.2.2.2 skrll sc->vge_ldata.vge_tx_list_map->dm_segs[0].ds_addr; 803 1.2.2.2 skrll 804 1.2.2.2 skrll /* Create DMA maps for TX buffers */ 805 1.2.2.2 skrll 806 1.2.2.2 skrll for (i = 0; i < VGE_TX_DESC_CNT; i++) { 807 1.2.2.2 skrll error = bus_dmamap_create(sc->vge_dmat, VGE_TX_MAXLEN, 808 1.2.2.2 skrll VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, 809 1.2.2.2 skrll BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 810 1.2.2.2 skrll &sc->vge_ldata.vge_tx_dmamap[i]); 811 1.2.2.2 skrll if (error) { 812 1.2.2.2 skrll printf("%s: can't create DMA map for TX\n", 813 1.2.2.2 skrll sc->sc_dev.dv_xname); 814 1.2.2.2 skrll return (ENOMEM); 815 1.2.2.2 skrll } 816 1.2.2.2 skrll } 817 1.2.2.2 skrll 818 1.2.2.2 skrll /* 819 1.2.2.2 skrll * Allocate map for RX descriptor list. 820 1.2.2.2 skrll */ 821 1.2.2.2 skrll error = bus_dmamap_create(sc->vge_dmat, 822 1.2.2.2 skrll round_page(VGE_RX_LIST_SZ), 1, round_page(VGE_RX_LIST_SZ), 823 1.2.2.2 skrll 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 824 1.2.2.2 skrll &sc->vge_ldata.vge_rx_list_map); 825 1.2.2.2 skrll if (error) { 826 1.2.2.2 skrll printf("%s: could not allocate RX dma list map\n", 827 1.2.2.2 skrll sc->sc_dev.dv_xname); 828 1.2.2.2 skrll return (ENOMEM); 829 1.2.2.2 skrll } 830 1.2.2.2 skrll 831 1.2.2.2 skrll /* Allocate DMA'able memory for the RX ring */ 832 1.2.2.2 skrll 833 1.2.2.2 skrll error = bus_dmamem_alloc(sc->vge_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 834 1.2.2.2 skrll 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 835 1.2.2.2 skrll if (error) 836 1.2.2.2 skrll return (ENOMEM); 837 1.2.2.2 skrll 838 1.2.2.2 skrll /* Map the memory to kernel VA space */ 839 1.2.2.2 skrll 840 1.2.2.2 skrll error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 841 1.2.2.2 skrll (caddr_t *) &sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 842 1.2.2.2 skrll if (error) 843 1.2.2.2 skrll return (ENOMEM); 844 1.2.2.2 skrll 845 1.2.2.2 skrll /* Load the map for the RX ring. */ 846 1.2.2.2 skrll error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_rx_list_map, 847 1.2.2.2 skrll sc->vge_ldata.vge_rx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 848 1.2.2.2 skrll if (error) { 849 1.2.2.2 skrll printf("%s: could not load RX ring dma memory\n", 850 1.2.2.2 skrll sc->sc_dev.dv_xname); 851 1.2.2.2 skrll return (ENOMEM); 852 1.2.2.2 skrll } 853 1.2.2.2 skrll 854 1.2.2.2 skrll sc->vge_ldata.vge_rx_list_addr = 855 1.2.2.2 skrll sc->vge_ldata.vge_rx_list_map->dm_segs[0].ds_addr; 856 1.2.2.2 skrll 857 1.2.2.2 skrll /* Create DMA maps for RX buffers */ 858 1.2.2.2 skrll 859 1.2.2.2 skrll for (i = 0; i < VGE_RX_DESC_CNT; i++) { 860 1.2.2.2 skrll error = bus_dmamap_create(sc->vge_dmat, MCLBYTES, 861 1.2.2.2 skrll 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 862 1.2.2.2 skrll &sc->vge_ldata.vge_rx_dmamap[i]); 863 1.2.2.2 skrll if (error) { 864 1.2.2.2 skrll printf("%s: can't create DMA map for RX\n", 865 1.2.2.2 skrll sc->sc_dev.dv_xname); 866 1.2.2.2 skrll return (ENOMEM); 867 1.2.2.2 skrll } 868 1.2.2.2 skrll } 869 1.2.2.2 skrll 870 1.2.2.2 skrll return (0); 871 1.2.2.2 skrll } 872 1.2.2.2 skrll 873 1.2.2.2 skrll /* 874 1.2.2.2 skrll * Attach the interface. Allocate softc structures, do ifmedia 875 1.2.2.2 skrll * setup and ethernet/BPF attach. 876 1.2.2.2 skrll */ 877 1.2.2.2 skrll static void 878 1.2.2.2 skrll vge_attach(struct device *parent, struct device *self, void *aux) 879 1.2.2.2 skrll { 880 1.2.2.2 skrll u_char eaddr[ETHER_ADDR_LEN]; 881 1.2.2.2 skrll struct vge_softc *sc = (struct vge_softc *)self; 882 1.2.2.2 skrll struct ifnet *ifp; 883 1.2.2.2 skrll struct pci_attach_args *pa = aux; 884 1.2.2.2 skrll pci_chipset_tag_t pc = pa->pa_pc; 885 1.2.2.2 skrll const char *intrstr; 886 1.2.2.2 skrll pci_intr_handle_t ih; 887 1.2.2.2 skrll 888 1.2.2.2 skrll aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 889 1.2.2.2 skrll PCI_REVISION(pa->pa_class)); 890 1.2.2.2 skrll 891 1.2.2.2 skrll /* Make sure bus-mastering is enabled */ 892 1.2.2.2 skrll pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 893 1.2.2.2 skrll pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 894 1.2.2.2 skrll PCI_COMMAND_MASTER_ENABLE); 895 1.2.2.2 skrll 896 1.2.2.2 skrll /* 897 1.2.2.2 skrll * Map control/status registers. 898 1.2.2.2 skrll */ 899 1.2.2.2 skrll if (0 != pci_mapreg_map(pa, VGE_PCI_LOMEM, 900 1.2.2.2 skrll PCI_MAPREG_TYPE_MEM, BUS_SPACE_MAP_LINEAR, 901 1.2.2.2 skrll &sc->vge_btag, &sc->vge_bhandle, NULL, NULL)) { 902 1.2.2.2 skrll aprint_error("%s: couldn't map memory\n", 903 1.2.2.2 skrll sc->sc_dev.dv_xname); 904 1.2.2.2 skrll return; 905 1.2.2.2 skrll } 906 1.2.2.2 skrll 907 1.2.2.2 skrll /* 908 1.2.2.2 skrll * Map and establish our interrupt. 909 1.2.2.2 skrll */ 910 1.2.2.2 skrll if (pci_intr_map(pa, &ih)) { 911 1.2.2.2 skrll aprint_error("%s: unable to map interrupt\n", 912 1.2.2.2 skrll sc->sc_dev.dv_xname); 913 1.2.2.2 skrll return; 914 1.2.2.2 skrll } 915 1.2.2.2 skrll intrstr = pci_intr_string(pc, ih); 916 1.2.2.2 skrll sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 917 1.2.2.2 skrll if (sc->vge_intrhand == NULL) { 918 1.2.2.2 skrll printf("%s: unable to establish interrupt", 919 1.2.2.2 skrll sc->sc_dev.dv_xname); 920 1.2.2.2 skrll if (intrstr != NULL) 921 1.2.2.2 skrll printf(" at %s", intrstr); 922 1.2.2.2 skrll printf("\n"); 923 1.2.2.2 skrll return; 924 1.2.2.2 skrll } 925 1.2.2.2 skrll aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 926 1.2.2.2 skrll 927 1.2.2.2 skrll /* Reset the adapter. */ 928 1.2.2.2 skrll vge_reset(sc); 929 1.2.2.2 skrll 930 1.2.2.2 skrll /* 931 1.2.2.2 skrll * Get station address from the EEPROM. 932 1.2.2.2 skrll */ 933 1.2.2.2 skrll vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 934 1.2.2.2 skrll bcopy(eaddr, (char *)&sc->vge_eaddr, ETHER_ADDR_LEN); 935 1.2.2.2 skrll 936 1.2.2.2 skrll printf("%s: Ethernet address: %s\n", sc->sc_dev.dv_xname, 937 1.2.2.2 skrll ether_sprintf(eaddr)); 938 1.2.2.2 skrll 939 1.2.2.2 skrll /* 940 1.2.2.2 skrll * Use the 32bit tag. Hardware supports 48bit physical addresses, 941 1.2.2.2 skrll * but we don't use that for now. 942 1.2.2.2 skrll */ 943 1.2.2.2 skrll sc->vge_dmat = pa->pa_dmat; 944 1.2.2.2 skrll 945 1.2.2.3 skrll if (vge_allocmem(sc)) 946 1.2.2.2 skrll return; 947 1.2.2.2 skrll 948 1.2.2.2 skrll ifp = &sc->sc_ethercom.ec_if; 949 1.2.2.2 skrll ifp->if_softc = sc; 950 1.2.2.2 skrll strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 951 1.2.2.2 skrll ifp->if_mtu = ETHERMTU; 952 1.2.2.2 skrll ifp->if_baudrate = IF_Gbps(1); 953 1.2.2.2 skrll ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 954 1.2.2.2 skrll ifp->if_ioctl = vge_ioctl; 955 1.2.2.2 skrll ifp->if_start = vge_start; 956 1.2.2.2 skrll 957 1.2.2.2 skrll /* 958 1.2.2.2 skrll * We can support 802.1Q VLAN-sized frames and jumbo 959 1.2.2.2 skrll * Ethernet frames. 960 1.2.2.2 skrll */ 961 1.2.2.2 skrll sc->sc_ethercom.ec_capabilities |= 962 1.2.2.2 skrll ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 963 1.2.2.2 skrll ETHERCAP_VLAN_HWTAGGING; 964 1.2.2.2 skrll 965 1.2.2.2 skrll /* 966 1.2.2.2 skrll * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 967 1.2.2.2 skrll */ 968 1.2.2.4 skrll ifp->if_capabilities |= 969 1.2.2.4 skrll IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 970 1.2.2.4 skrll IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 971 1.2.2.4 skrll IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 972 1.2.2.2 skrll 973 1.2.2.2 skrll #ifdef DEVICE_POLLING 974 1.2.2.2 skrll #ifdef IFCAP_POLLING 975 1.2.2.2 skrll ifp->if_capabilities |= IFCAP_POLLING; 976 1.2.2.2 skrll #endif 977 1.2.2.2 skrll #endif 978 1.2.2.2 skrll ifp->if_watchdog = vge_watchdog; 979 1.2.2.2 skrll ifp->if_init = vge_init; 980 1.2.2.2 skrll IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 981 1.2.2.2 skrll 982 1.2.2.2 skrll /* 983 1.2.2.2 skrll * Initialize our media structures and probe the MII. 984 1.2.2.2 skrll */ 985 1.2.2.2 skrll sc->sc_mii.mii_ifp = ifp; 986 1.2.2.2 skrll sc->sc_mii.mii_readreg = vge_miibus_readreg; 987 1.2.2.2 skrll sc->sc_mii.mii_writereg = vge_miibus_writereg; 988 1.2.2.2 skrll sc->sc_mii.mii_statchg = vge_miibus_statchg; 989 1.2.2.2 skrll ifmedia_init(&sc->sc_mii.mii_media, 0, vge_ifmedia_upd, 990 1.2.2.2 skrll vge_ifmedia_sts); 991 1.2.2.2 skrll mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 992 1.2.2.2 skrll MII_OFFSET_ANY, MIIF_DOPAUSE); 993 1.2.2.2 skrll if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 994 1.2.2.2 skrll ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 995 1.2.2.2 skrll ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 996 1.2.2.2 skrll } else 997 1.2.2.2 skrll ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 998 1.2.2.2 skrll 999 1.2.2.2 skrll /* 1000 1.2.2.2 skrll * Attach the interface. 1001 1.2.2.2 skrll */ 1002 1.2.2.2 skrll if_attach(ifp); 1003 1.2.2.2 skrll ether_ifattach(ifp, eaddr); 1004 1.2.2.2 skrll 1005 1.2.2.2 skrll callout_init(&sc->vge_timeout); 1006 1.2.2.2 skrll callout_setfunc(&sc->vge_timeout, vge_tick, sc); 1007 1.2.2.2 skrll 1008 1.2.2.2 skrll /* 1009 1.2.2.2 skrll * Make sure the interface is shutdown during reboot. 1010 1.2.2.2 skrll */ 1011 1.2.2.2 skrll if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1012 1.2.2.2 skrll printf("%s: WARNING: unable to establish shutdown hook\n", 1013 1.2.2.2 skrll sc->sc_dev.dv_xname); 1014 1.2.2.2 skrll } 1015 1.2.2.2 skrll } 1016 1.2.2.2 skrll 1017 1.2.2.2 skrll static int 1018 1.2.2.2 skrll vge_newbuf(sc, idx, m) 1019 1.2.2.2 skrll struct vge_softc *sc; 1020 1.2.2.2 skrll int idx; 1021 1.2.2.2 skrll struct mbuf *m; 1022 1.2.2.2 skrll { 1023 1.2.2.2 skrll struct mbuf *n = NULL; 1024 1.2.2.2 skrll int i, error; 1025 1.2.2.2 skrll 1026 1.2.2.2 skrll if (m == NULL) { 1027 1.2.2.2 skrll n = m_gethdr(M_DONTWAIT, MT_DATA); 1028 1.2.2.2 skrll if (n == NULL) 1029 1.2.2.2 skrll return (ENOBUFS); 1030 1.2.2.2 skrll 1031 1.2.2.2 skrll m_clget(n, M_DONTWAIT); 1032 1.2.2.2 skrll if ((n->m_flags & M_EXT) == 0) { 1033 1.2.2.2 skrll m_freem(n); 1034 1.2.2.2 skrll return (ENOBUFS); 1035 1.2.2.2 skrll } 1036 1.2.2.2 skrll 1037 1.2.2.2 skrll m = n; 1038 1.2.2.2 skrll } else 1039 1.2.2.2 skrll m->m_data = m->m_ext.ext_buf; 1040 1.2.2.2 skrll 1041 1.2.2.2 skrll 1042 1.2.2.2 skrll #ifdef VGE_FIXUP_RX 1043 1.2.2.2 skrll /* 1044 1.2.2.2 skrll * This is part of an evil trick to deal with non-x86 platforms. 1045 1.2.2.2 skrll * The VIA chip requires RX buffers to be aligned on 32-bit 1046 1.2.2.2 skrll * boundaries, but that will hose non-x86 machines. To get around 1047 1.2.2.2 skrll * this, we leave some empty space at the start of each buffer 1048 1.2.2.2 skrll * and for non-x86 hosts, we copy the buffer back two bytes 1049 1.2.2.2 skrll * to achieve word alignment. This is slightly more efficient 1050 1.2.2.2 skrll * than allocating a new buffer, copying the contents, and 1051 1.2.2.2 skrll * discarding the old buffer. 1052 1.2.2.2 skrll */ 1053 1.2.2.2 skrll m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1054 1.2.2.2 skrll m_adj(m, VGE_ETHER_ALIGN); 1055 1.2.2.2 skrll #else 1056 1.2.2.2 skrll m->m_len = m->m_pkthdr.len = MCLBYTES; 1057 1.2.2.2 skrll #endif 1058 1.2.2.2 skrll 1059 1.2.2.2 skrll error = bus_dmamap_load_mbuf(sc->vge_dmat, 1060 1.2.2.2 skrll sc->vge_ldata.vge_rx_dmamap[idx], m, BUS_DMA_NOWAIT); 1061 1.2.2.2 skrll if (error || vge_dma_map_rx_desc(sc, idx)) { 1062 1.2.2.2 skrll if (n != NULL) 1063 1.2.2.2 skrll m_freem(n); 1064 1.2.2.2 skrll return (ENOMEM); 1065 1.2.2.2 skrll } 1066 1.2.2.2 skrll 1067 1.2.2.2 skrll /* 1068 1.2.2.2 skrll * Note: the manual fails to document the fact that for 1069 1.2.2.2 skrll * proper opration, the driver needs to replentish the RX 1070 1.2.2.2 skrll * DMA ring 4 descriptors at a time (rather than one at a 1071 1.2.2.2 skrll * time, like most chips). We can allocate the new buffers 1072 1.2.2.2 skrll * but we should not set the OWN bits until we're ready 1073 1.2.2.2 skrll * to hand back 4 of them in one shot. 1074 1.2.2.2 skrll */ 1075 1.2.2.2 skrll 1076 1.2.2.2 skrll #define VGE_RXCHUNK 4 1077 1.2.2.2 skrll sc->vge_rx_consumed++; 1078 1.2.2.2 skrll if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1079 1.2.2.2 skrll for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1080 1.2.2.2 skrll sc->vge_ldata.vge_rx_list[i].vge_sts |= 1081 1.2.2.2 skrll htole32(VGE_RDSTS_OWN); 1082 1.2.2.2 skrll sc->vge_rx_consumed = 0; 1083 1.2.2.2 skrll } 1084 1.2.2.2 skrll 1085 1.2.2.2 skrll sc->vge_ldata.vge_rx_mbuf[idx] = m; 1086 1.2.2.2 skrll 1087 1.2.2.2 skrll bus_dmamap_sync(sc->vge_dmat, 1088 1.2.2.2 skrll sc->vge_ldata.vge_rx_dmamap[idx], 1089 1.2.2.2 skrll 0, sc->vge_ldata.vge_rx_dmamap[idx]->dm_mapsize, 1090 1.2.2.2 skrll BUS_DMASYNC_PREREAD); 1091 1.2.2.2 skrll 1092 1.2.2.2 skrll return (0); 1093 1.2.2.2 skrll } 1094 1.2.2.2 skrll 1095 1.2.2.2 skrll static int 1096 1.2.2.2 skrll vge_tx_list_init(sc) 1097 1.2.2.2 skrll struct vge_softc *sc; 1098 1.2.2.2 skrll { 1099 1.2.2.2 skrll bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1100 1.2.2.2 skrll bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1101 1.2.2.2 skrll (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1102 1.2.2.2 skrll 1103 1.2.2.2 skrll bus_dmamap_sync(sc->vge_dmat, 1104 1.2.2.2 skrll sc->vge_ldata.vge_tx_list_map, 1105 1.2.2.2 skrll 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1106 1.2.2.2 skrll BUS_DMASYNC_PREWRITE); 1107 1.2.2.2 skrll 1108 1.2.2.2 skrll sc->vge_ldata.vge_tx_prodidx = 0; 1109 1.2.2.2 skrll sc->vge_ldata.vge_tx_considx = 0; 1110 1.2.2.2 skrll sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1111 1.2.2.2 skrll 1112 1.2.2.2 skrll return (0); 1113 1.2.2.2 skrll } 1114 1.2.2.2 skrll 1115 1.2.2.2 skrll static int 1116 1.2.2.2 skrll vge_rx_list_init(sc) 1117 1.2.2.2 skrll struct vge_softc *sc; 1118 1.2.2.2 skrll { 1119 1.2.2.2 skrll int i; 1120 1.2.2.2 skrll 1121 1.2.2.2 skrll bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1122 1.2.2.2 skrll bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1123 1.2.2.2 skrll (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1124 1.2.2.2 skrll 1125 1.2.2.2 skrll sc->vge_rx_consumed = 0; 1126 1.2.2.2 skrll 1127 1.2.2.2 skrll for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1128 1.2.2.2 skrll if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1129 1.2.2.2 skrll return (ENOBUFS); 1130 1.2.2.2 skrll } 1131 1.2.2.2 skrll 1132 1.2.2.2 skrll /* Flush the RX descriptors */ 1133 1.2.2.2 skrll 1134 1.2.2.2 skrll bus_dmamap_sync(sc->vge_dmat, 1135 1.2.2.2 skrll sc->vge_ldata.vge_rx_list_map, 1136 1.2.2.2 skrll 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1137 1.2.2.2 skrll BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1138 1.2.2.2 skrll 1139 1.2.2.2 skrll sc->vge_ldata.vge_rx_prodidx = 0; 1140 1.2.2.2 skrll sc->vge_rx_consumed = 0; 1141 1.2.2.2 skrll sc->vge_head = sc->vge_tail = NULL; 1142 1.2.2.2 skrll 1143 1.2.2.2 skrll return (0); 1144 1.2.2.2 skrll } 1145 1.2.2.2 skrll 1146 1.2.2.2 skrll #ifdef VGE_FIXUP_RX 1147 1.2.2.2 skrll static __inline void 1148 1.2.2.2 skrll vge_fixup_rx(m) 1149 1.2.2.2 skrll struct mbuf *m; 1150 1.2.2.2 skrll { 1151 1.2.2.2 skrll int i; 1152 1.2.2.2 skrll uint16_t *src, *dst; 1153 1.2.2.2 skrll 1154 1.2.2.2 skrll src = mtod(m, uint16_t *); 1155 1.2.2.2 skrll dst = src - 1; 1156 1.2.2.2 skrll 1157 1.2.2.2 skrll for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1158 1.2.2.2 skrll *dst++ = *src++; 1159 1.2.2.2 skrll 1160 1.2.2.2 skrll m->m_data -= ETHER_ALIGN; 1161 1.2.2.2 skrll 1162 1.2.2.2 skrll return; 1163 1.2.2.2 skrll } 1164 1.2.2.2 skrll #endif 1165 1.2.2.2 skrll 1166 1.2.2.2 skrll /* 1167 1.2.2.2 skrll * RX handler. We support the reception of jumbo frames that have 1168 1.2.2.2 skrll * been fragmented across multiple 2K mbuf cluster buffers. 1169 1.2.2.2 skrll */ 1170 1.2.2.2 skrll static void 1171 1.2.2.2 skrll vge_rxeof(sc) 1172 1.2.2.2 skrll struct vge_softc *sc; 1173 1.2.2.2 skrll { 1174 1.2.2.2 skrll struct mbuf *m; 1175 1.2.2.2 skrll struct ifnet *ifp; 1176 1.2.2.2 skrll int i, total_len; 1177 1.2.2.2 skrll int lim = 0; 1178 1.2.2.2 skrll struct vge_rx_desc *cur_rx; 1179 1.2.2.2 skrll u_int32_t rxstat, rxctl; 1180 1.2.2.2 skrll 1181 1.2.2.2 skrll VGE_LOCK_ASSERT(sc); 1182 1.2.2.2 skrll ifp = &sc->sc_ethercom.ec_if; 1183 1.2.2.2 skrll i = sc->vge_ldata.vge_rx_prodidx; 1184 1.2.2.2 skrll 1185 1.2.2.2 skrll /* Invalidate the descriptor memory */ 1186 1.2.2.2 skrll 1187 1.2.2.2 skrll bus_dmamap_sync(sc->vge_dmat, 1188 1.2.2.2 skrll sc->vge_ldata.vge_rx_list_map, 1189 1.2.2.2 skrll 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1190 1.2.2.2 skrll BUS_DMASYNC_POSTREAD); 1191 1.2.2.2 skrll 1192 1.2.2.2 skrll while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1193 1.2.2.2 skrll 1194 1.2.2.2 skrll #ifdef DEVICE_POLLING 1195 1.2.2.2 skrll if (ifp->if_flags & IFF_POLLING) { 1196 1.2.2.2 skrll if (sc->rxcycles <= 0) 1197 1.2.2.2 skrll break; 1198 1.2.2.2 skrll sc->rxcycles--; 1199 1.2.2.2 skrll } 1200 1.2.2.2 skrll #endif /* DEVICE_POLLING */ 1201 1.2.2.2 skrll 1202 1.2.2.2 skrll cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1203 1.2.2.2 skrll m = sc->vge_ldata.vge_rx_mbuf[i]; 1204 1.2.2.2 skrll total_len = VGE_RXBYTES(cur_rx); 1205 1.2.2.2 skrll rxstat = le32toh(cur_rx->vge_sts); 1206 1.2.2.2 skrll rxctl = le32toh(cur_rx->vge_ctl); 1207 1.2.2.2 skrll 1208 1.2.2.2 skrll /* Invalidate the RX mbuf and unload its map */ 1209 1.2.2.2 skrll 1210 1.2.2.2 skrll bus_dmamap_sync(sc->vge_dmat, 1211 1.2.2.2 skrll sc->vge_ldata.vge_rx_dmamap[i], 1212 1.2.2.2 skrll 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1213 1.2.2.2 skrll BUS_DMASYNC_POSTWRITE); 1214 1.2.2.2 skrll bus_dmamap_unload(sc->vge_dmat, 1215 1.2.2.2 skrll sc->vge_ldata.vge_rx_dmamap[i]); 1216 1.2.2.2 skrll 1217 1.2.2.2 skrll /* 1218 1.2.2.2 skrll * If the 'start of frame' bit is set, this indicates 1219 1.2.2.2 skrll * either the first fragment in a multi-fragment receive, 1220 1.2.2.2 skrll * or an intermediate fragment. Either way, we want to 1221 1.2.2.2 skrll * accumulate the buffers. 1222 1.2.2.2 skrll */ 1223 1.2.2.2 skrll if (rxstat & VGE_RXPKT_SOF) { 1224 1.2.2.2 skrll m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1225 1.2.2.2 skrll if (sc->vge_head == NULL) 1226 1.2.2.2 skrll sc->vge_head = sc->vge_tail = m; 1227 1.2.2.2 skrll else { 1228 1.2.2.2 skrll m->m_flags &= ~M_PKTHDR; 1229 1.2.2.2 skrll sc->vge_tail->m_next = m; 1230 1.2.2.2 skrll sc->vge_tail = m; 1231 1.2.2.2 skrll } 1232 1.2.2.2 skrll vge_newbuf(sc, i, NULL); 1233 1.2.2.2 skrll VGE_RX_DESC_INC(i); 1234 1.2.2.2 skrll continue; 1235 1.2.2.2 skrll } 1236 1.2.2.2 skrll 1237 1.2.2.2 skrll /* 1238 1.2.2.2 skrll * Bad/error frames will have the RXOK bit cleared. 1239 1.2.2.2 skrll * However, there's one error case we want to allow: 1240 1.2.2.2 skrll * if a VLAN tagged frame arrives and the chip can't 1241 1.2.2.2 skrll * match it against the CAM filter, it considers this 1242 1.2.2.2 skrll * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1243 1.2.2.2 skrll * We don't want to drop the frame though: our VLAN 1244 1.2.2.2 skrll * filtering is done in software. 1245 1.2.2.2 skrll */ 1246 1.2.2.2 skrll if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1247 1.2.2.2 skrll && !(rxstat & VGE_RDSTS_CSUMERR)) { 1248 1.2.2.2 skrll ifp->if_ierrors++; 1249 1.2.2.2 skrll /* 1250 1.2.2.2 skrll * If this is part of a multi-fragment packet, 1251 1.2.2.2 skrll * discard all the pieces. 1252 1.2.2.2 skrll */ 1253 1.2.2.2 skrll if (sc->vge_head != NULL) { 1254 1.2.2.2 skrll m_freem(sc->vge_head); 1255 1.2.2.2 skrll sc->vge_head = sc->vge_tail = NULL; 1256 1.2.2.2 skrll } 1257 1.2.2.2 skrll vge_newbuf(sc, i, m); 1258 1.2.2.2 skrll VGE_RX_DESC_INC(i); 1259 1.2.2.2 skrll continue; 1260 1.2.2.2 skrll } 1261 1.2.2.2 skrll 1262 1.2.2.2 skrll /* 1263 1.2.2.2 skrll * If allocating a replacement mbuf fails, 1264 1.2.2.2 skrll * reload the current one. 1265 1.2.2.2 skrll */ 1266 1.2.2.2 skrll 1267 1.2.2.2 skrll if (vge_newbuf(sc, i, NULL)) { 1268 1.2.2.2 skrll ifp->if_ierrors++; 1269 1.2.2.2 skrll if (sc->vge_head != NULL) { 1270 1.2.2.2 skrll m_freem(sc->vge_head); 1271 1.2.2.2 skrll sc->vge_head = sc->vge_tail = NULL; 1272 1.2.2.2 skrll } 1273 1.2.2.2 skrll vge_newbuf(sc, i, m); 1274 1.2.2.2 skrll VGE_RX_DESC_INC(i); 1275 1.2.2.2 skrll continue; 1276 1.2.2.2 skrll } 1277 1.2.2.2 skrll 1278 1.2.2.2 skrll VGE_RX_DESC_INC(i); 1279 1.2.2.2 skrll 1280 1.2.2.2 skrll if (sc->vge_head != NULL) { 1281 1.2.2.2 skrll m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1282 1.2.2.2 skrll /* 1283 1.2.2.2 skrll * Special case: if there's 4 bytes or less 1284 1.2.2.2 skrll * in this buffer, the mbuf can be discarded: 1285 1.2.2.2 skrll * the last 4 bytes is the CRC, which we don't 1286 1.2.2.2 skrll * care about anyway. 1287 1.2.2.2 skrll */ 1288 1.2.2.2 skrll if (m->m_len <= ETHER_CRC_LEN) { 1289 1.2.2.2 skrll sc->vge_tail->m_len -= 1290 1.2.2.2 skrll (ETHER_CRC_LEN - m->m_len); 1291 1.2.2.2 skrll m_freem(m); 1292 1.2.2.2 skrll } else { 1293 1.2.2.2 skrll m->m_len -= ETHER_CRC_LEN; 1294 1.2.2.2 skrll m->m_flags &= ~M_PKTHDR; 1295 1.2.2.2 skrll sc->vge_tail->m_next = m; 1296 1.2.2.2 skrll } 1297 1.2.2.2 skrll m = sc->vge_head; 1298 1.2.2.2 skrll sc->vge_head = sc->vge_tail = NULL; 1299 1.2.2.2 skrll m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1300 1.2.2.2 skrll } else 1301 1.2.2.2 skrll m->m_pkthdr.len = m->m_len = 1302 1.2.2.2 skrll (total_len - ETHER_CRC_LEN); 1303 1.2.2.2 skrll 1304 1.2.2.2 skrll #ifdef VGE_FIXUP_RX 1305 1.2.2.2 skrll vge_fixup_rx(m); 1306 1.2.2.2 skrll #endif 1307 1.2.2.2 skrll ifp->if_ipackets++; 1308 1.2.2.2 skrll m->m_pkthdr.rcvif = ifp; 1309 1.2.2.2 skrll 1310 1.2.2.2 skrll /* Do RX checksumming if enabled */ 1311 1.2.2.2 skrll if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1312 1.2.2.2 skrll 1313 1.2.2.2 skrll /* Check IP header checksum */ 1314 1.2.2.2 skrll if (rxctl & VGE_RDCTL_IPPKT) 1315 1.2.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1316 1.2.2.2 skrll if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1317 1.2.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1318 1.2.2.2 skrll } 1319 1.2.2.2 skrll 1320 1.2.2.2 skrll if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1321 1.2.2.2 skrll /* Check UDP checksum */ 1322 1.2.2.2 skrll if (rxctl & VGE_RDCTL_TCPPKT) 1323 1.2.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1324 1.2.2.2 skrll 1325 1.2.2.2 skrll if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1326 1.2.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1327 1.2.2.2 skrll } 1328 1.2.2.2 skrll 1329 1.2.2.2 skrll if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1330 1.2.2.2 skrll /* Check UDP checksum */ 1331 1.2.2.2 skrll if (rxctl & VGE_RDCTL_UDPPKT) 1332 1.2.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1333 1.2.2.2 skrll 1334 1.2.2.2 skrll if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1335 1.2.2.2 skrll m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1336 1.2.2.2 skrll } 1337 1.2.2.2 skrll 1338 1.2.2.2 skrll if (rxstat & VGE_RDSTS_VTAG) 1339 1.2.2.2 skrll VLAN_INPUT_TAG(ifp, m, 1340 1.2.2.2 skrll ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1341 1.2.2.2 skrll 1342 1.2.2.2 skrll #if NBPFILTER > 0 1343 1.2.2.2 skrll /* 1344 1.2.2.2 skrll * Handle BPF listeners. 1345 1.2.2.2 skrll */ 1346 1.2.2.2 skrll if (ifp->if_bpf) 1347 1.2.2.2 skrll bpf_mtap(ifp->if_bpf, m); 1348 1.2.2.2 skrll #endif 1349 1.2.2.2 skrll 1350 1.2.2.2 skrll VGE_UNLOCK(sc); 1351 1.2.2.2 skrll (*ifp->if_input)(ifp, m); 1352 1.2.2.2 skrll VGE_LOCK(sc); 1353 1.2.2.2 skrll 1354 1.2.2.2 skrll lim++; 1355 1.2.2.2 skrll if (lim == VGE_RX_DESC_CNT) 1356 1.2.2.2 skrll break; 1357 1.2.2.2 skrll 1358 1.2.2.2 skrll } 1359 1.2.2.2 skrll 1360 1.2.2.2 skrll /* Flush the RX DMA ring */ 1361 1.2.2.2 skrll 1362 1.2.2.2 skrll bus_dmamap_sync(sc->vge_dmat, 1363 1.2.2.2 skrll sc->vge_ldata.vge_rx_list_map, 1364 1.2.2.2 skrll 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1365 1.2.2.2 skrll BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1366 1.2.2.2 skrll 1367 1.2.2.2 skrll sc->vge_ldata.vge_rx_prodidx = i; 1368 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1369 1.2.2.2 skrll 1370 1.2.2.2 skrll 1371 1.2.2.2 skrll return; 1372 1.2.2.2 skrll } 1373 1.2.2.2 skrll 1374 1.2.2.2 skrll static void 1375 1.2.2.2 skrll vge_txeof(sc) 1376 1.2.2.2 skrll struct vge_softc *sc; 1377 1.2.2.2 skrll { 1378 1.2.2.2 skrll struct ifnet *ifp; 1379 1.2.2.2 skrll u_int32_t txstat; 1380 1.2.2.2 skrll int idx; 1381 1.2.2.2 skrll 1382 1.2.2.2 skrll ifp = &sc->sc_ethercom.ec_if; 1383 1.2.2.2 skrll idx = sc->vge_ldata.vge_tx_considx; 1384 1.2.2.2 skrll 1385 1.2.2.2 skrll /* Invalidate the TX descriptor list */ 1386 1.2.2.2 skrll 1387 1.2.2.2 skrll bus_dmamap_sync(sc->vge_dmat, 1388 1.2.2.2 skrll sc->vge_ldata.vge_tx_list_map, 1389 1.2.2.2 skrll 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1390 1.2.2.2 skrll BUS_DMASYNC_POSTREAD); 1391 1.2.2.2 skrll 1392 1.2.2.2 skrll while (idx != sc->vge_ldata.vge_tx_prodidx) { 1393 1.2.2.2 skrll 1394 1.2.2.2 skrll txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1395 1.2.2.2 skrll if (txstat & VGE_TDSTS_OWN) 1396 1.2.2.2 skrll break; 1397 1.2.2.2 skrll 1398 1.2.2.2 skrll m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1399 1.2.2.2 skrll sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1400 1.2.2.2 skrll bus_dmamap_unload(sc->vge_dmat, 1401 1.2.2.2 skrll sc->vge_ldata.vge_tx_dmamap[idx]); 1402 1.2.2.2 skrll if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1403 1.2.2.2 skrll ifp->if_collisions++; 1404 1.2.2.2 skrll if (txstat & VGE_TDSTS_TXERR) 1405 1.2.2.2 skrll ifp->if_oerrors++; 1406 1.2.2.2 skrll else 1407 1.2.2.2 skrll ifp->if_opackets++; 1408 1.2.2.2 skrll 1409 1.2.2.2 skrll sc->vge_ldata.vge_tx_free++; 1410 1.2.2.2 skrll VGE_TX_DESC_INC(idx); 1411 1.2.2.2 skrll } 1412 1.2.2.2 skrll 1413 1.2.2.2 skrll /* No changes made to the TX ring, so no flush needed */ 1414 1.2.2.2 skrll 1415 1.2.2.2 skrll if (idx != sc->vge_ldata.vge_tx_considx) { 1416 1.2.2.2 skrll sc->vge_ldata.vge_tx_considx = idx; 1417 1.2.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 1418 1.2.2.2 skrll ifp->if_timer = 0; 1419 1.2.2.2 skrll } 1420 1.2.2.2 skrll 1421 1.2.2.2 skrll /* 1422 1.2.2.2 skrll * If not all descriptors have been released reaped yet, 1423 1.2.2.2 skrll * reload the timer so that we will eventually get another 1424 1.2.2.2 skrll * interrupt that will cause us to re-enter this routine. 1425 1.2.2.2 skrll * This is done in case the transmitter has gone idle. 1426 1.2.2.2 skrll */ 1427 1.2.2.2 skrll if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1428 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1429 1.2.2.2 skrll } 1430 1.2.2.2 skrll 1431 1.2.2.2 skrll return; 1432 1.2.2.2 skrll } 1433 1.2.2.2 skrll 1434 1.2.2.2 skrll static void 1435 1.2.2.2 skrll vge_tick(xsc) 1436 1.2.2.2 skrll void *xsc; 1437 1.2.2.2 skrll { 1438 1.2.2.2 skrll struct vge_softc *sc = xsc; 1439 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1440 1.2.2.2 skrll struct mii_data *mii = &sc->sc_mii; 1441 1.2.2.2 skrll int s; 1442 1.2.2.2 skrll 1443 1.2.2.2 skrll s = splnet(); 1444 1.2.2.2 skrll 1445 1.2.2.2 skrll VGE_LOCK(sc); 1446 1.2.2.2 skrll 1447 1.2.2.2 skrll callout_schedule(&sc->vge_timeout, hz); 1448 1.2.2.2 skrll 1449 1.2.2.2 skrll mii_tick(mii); 1450 1.2.2.2 skrll if (sc->vge_link) { 1451 1.2.2.2 skrll if (!(mii->mii_media_status & IFM_ACTIVE)) 1452 1.2.2.2 skrll sc->vge_link = 0; 1453 1.2.2.2 skrll } else { 1454 1.2.2.2 skrll if (mii->mii_media_status & IFM_ACTIVE && 1455 1.2.2.2 skrll IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1456 1.2.2.2 skrll sc->vge_link = 1; 1457 1.2.2.2 skrll if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1458 1.2.2.2 skrll vge_start(ifp); 1459 1.2.2.2 skrll } 1460 1.2.2.2 skrll } 1461 1.2.2.2 skrll 1462 1.2.2.2 skrll VGE_UNLOCK(sc); 1463 1.2.2.2 skrll 1464 1.2.2.2 skrll splx(s); 1465 1.2.2.2 skrll } 1466 1.2.2.2 skrll 1467 1.2.2.2 skrll #ifdef DEVICE_POLLING 1468 1.2.2.2 skrll static void 1469 1.2.2.2 skrll vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1470 1.2.2.2 skrll { 1471 1.2.2.2 skrll struct vge_softc *sc = ifp->if_softc; 1472 1.2.2.2 skrll 1473 1.2.2.2 skrll VGE_LOCK(sc); 1474 1.2.2.2 skrll #ifdef IFCAP_POLLING 1475 1.2.2.2 skrll if (!(ifp->if_capenable & IFCAP_POLLING)) { 1476 1.2.2.2 skrll ether_poll_deregister(ifp); 1477 1.2.2.2 skrll cmd = POLL_DEREGISTER; 1478 1.2.2.2 skrll } 1479 1.2.2.2 skrll #endif 1480 1.2.2.2 skrll if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1481 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1482 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1483 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1484 1.2.2.2 skrll goto done; 1485 1.2.2.2 skrll } 1486 1.2.2.2 skrll 1487 1.2.2.2 skrll sc->rxcycles = count; 1488 1.2.2.2 skrll vge_rxeof(sc); 1489 1.2.2.2 skrll vge_txeof(sc); 1490 1.2.2.2 skrll 1491 1.2.2.2 skrll #if __FreeBSD_version < 502114 1492 1.2.2.2 skrll if (ifp->if_snd.ifq_head != NULL) 1493 1.2.2.2 skrll #else 1494 1.2.2.2 skrll if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1495 1.2.2.2 skrll #endif 1496 1.2.2.2 skrll taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1497 1.2.2.2 skrll 1498 1.2.2.2 skrll if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1499 1.2.2.2 skrll u_int32_t status; 1500 1.2.2.2 skrll status = CSR_READ_4(sc, VGE_ISR); 1501 1.2.2.2 skrll if (status == 0xFFFFFFFF) 1502 1.2.2.2 skrll goto done; 1503 1.2.2.2 skrll if (status) 1504 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_ISR, status); 1505 1.2.2.2 skrll 1506 1.2.2.2 skrll /* 1507 1.2.2.2 skrll * XXX check behaviour on receiver stalls. 1508 1.2.2.2 skrll */ 1509 1.2.2.2 skrll 1510 1.2.2.2 skrll if (status & VGE_ISR_TXDMA_STALL || 1511 1.2.2.2 skrll status & VGE_ISR_RXDMA_STALL) 1512 1.2.2.2 skrll vge_init(sc); 1513 1.2.2.2 skrll 1514 1.2.2.2 skrll if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1515 1.2.2.2 skrll vge_rxeof(sc); 1516 1.2.2.2 skrll ifp->if_ierrors++; 1517 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1518 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1519 1.2.2.2 skrll } 1520 1.2.2.2 skrll } 1521 1.2.2.2 skrll done: 1522 1.2.2.2 skrll VGE_UNLOCK(sc); 1523 1.2.2.2 skrll } 1524 1.2.2.2 skrll #endif /* DEVICE_POLLING */ 1525 1.2.2.2 skrll 1526 1.2.2.2 skrll static int 1527 1.2.2.2 skrll vge_intr(arg) 1528 1.2.2.2 skrll void *arg; 1529 1.2.2.2 skrll { 1530 1.2.2.2 skrll struct vge_softc *sc = arg; 1531 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1532 1.2.2.2 skrll u_int32_t status; 1533 1.2.2.2 skrll int claim = 0; 1534 1.2.2.2 skrll 1535 1.2.2.2 skrll if (sc->suspended) { 1536 1.2.2.2 skrll return claim; 1537 1.2.2.2 skrll } 1538 1.2.2.2 skrll 1539 1.2.2.2 skrll VGE_LOCK(sc); 1540 1.2.2.2 skrll 1541 1.2.2.2 skrll if (!(ifp->if_flags & IFF_UP)) { 1542 1.2.2.2 skrll VGE_UNLOCK(sc); 1543 1.2.2.2 skrll return claim; 1544 1.2.2.2 skrll } 1545 1.2.2.2 skrll 1546 1.2.2.2 skrll #ifdef DEVICE_POLLING 1547 1.2.2.2 skrll if (ifp->if_flags & IFF_POLLING) 1548 1.2.2.2 skrll goto done; 1549 1.2.2.2 skrll if ( 1550 1.2.2.2 skrll #ifdef IFCAP_POLLING 1551 1.2.2.2 skrll (ifp->if_capenable & IFCAP_POLLING) && 1552 1.2.2.2 skrll #endif 1553 1.2.2.2 skrll ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1554 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_IMR, 0); 1555 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1556 1.2.2.2 skrll vge_poll(ifp, 0, 1); 1557 1.2.2.2 skrll goto done; 1558 1.2.2.2 skrll } 1559 1.2.2.2 skrll 1560 1.2.2.2 skrll #endif /* DEVICE_POLLING */ 1561 1.2.2.2 skrll 1562 1.2.2.2 skrll /* Disable interrupts */ 1563 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1564 1.2.2.2 skrll 1565 1.2.2.2 skrll for (;;) { 1566 1.2.2.2 skrll 1567 1.2.2.2 skrll status = CSR_READ_4(sc, VGE_ISR); 1568 1.2.2.2 skrll /* If the card has gone away the read returns 0xffff. */ 1569 1.2.2.2 skrll if (status == 0xFFFFFFFF) 1570 1.2.2.2 skrll break; 1571 1.2.2.2 skrll 1572 1.2.2.2 skrll if (status) { 1573 1.2.2.2 skrll claim = 1; 1574 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_ISR, status); 1575 1.2.2.2 skrll } 1576 1.2.2.2 skrll 1577 1.2.2.2 skrll if ((status & VGE_INTRS) == 0) 1578 1.2.2.2 skrll break; 1579 1.2.2.2 skrll 1580 1.2.2.2 skrll if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1581 1.2.2.2 skrll vge_rxeof(sc); 1582 1.2.2.2 skrll 1583 1.2.2.2 skrll if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1584 1.2.2.2 skrll vge_rxeof(sc); 1585 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1586 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1587 1.2.2.2 skrll } 1588 1.2.2.2 skrll 1589 1.2.2.2 skrll if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1590 1.2.2.2 skrll vge_txeof(sc); 1591 1.2.2.2 skrll 1592 1.2.2.2 skrll if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1593 1.2.2.2 skrll vge_init(ifp); 1594 1.2.2.2 skrll 1595 1.2.2.2 skrll if (status & VGE_ISR_LINKSTS) 1596 1.2.2.2 skrll vge_tick(sc); 1597 1.2.2.2 skrll } 1598 1.2.2.2 skrll 1599 1.2.2.2 skrll /* Re-enable interrupts */ 1600 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1601 1.2.2.2 skrll 1602 1.2.2.2 skrll #ifdef DEVICE_POLLING 1603 1.2.2.2 skrll done: 1604 1.2.2.2 skrll #endif 1605 1.2.2.2 skrll VGE_UNLOCK(sc); 1606 1.2.2.2 skrll 1607 1.2.2.2 skrll if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1608 1.2.2.2 skrll vge_start(ifp); 1609 1.2.2.2 skrll 1610 1.2.2.2 skrll return claim; 1611 1.2.2.2 skrll } 1612 1.2.2.2 skrll 1613 1.2.2.2 skrll static int 1614 1.2.2.2 skrll vge_encap(sc, m_head, idx) 1615 1.2.2.2 skrll struct vge_softc *sc; 1616 1.2.2.2 skrll struct mbuf *m_head; 1617 1.2.2.2 skrll int idx; 1618 1.2.2.2 skrll { 1619 1.2.2.2 skrll struct mbuf *m_new = NULL; 1620 1.2.2.2 skrll bus_dmamap_t map; 1621 1.2.2.2 skrll int error, flags; 1622 1.2.2.2 skrll struct m_tag *mtag; 1623 1.2.2.2 skrll 1624 1.2.2.3 skrll /* If this descriptor is still owned by the chip, bail. */ 1625 1.2.2.3 skrll if (sc->vge_ldata.vge_tx_free <= 2 1626 1.2.2.3 skrll || le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts) & VGE_TDSTS_OWN) 1627 1.2.2.3 skrll return (ENOBUFS); 1628 1.2.2.2 skrll 1629 1.2.2.2 skrll flags = 0; 1630 1.2.2.2 skrll 1631 1.2.2.2 skrll if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1632 1.2.2.2 skrll flags |= VGE_TDCTL_IPCSUM; 1633 1.2.2.2 skrll if (m_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1634 1.2.2.2 skrll flags |= VGE_TDCTL_TCPCSUM; 1635 1.2.2.2 skrll if (m_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1636 1.2.2.2 skrll flags |= VGE_TDCTL_UDPCSUM; 1637 1.2.2.2 skrll 1638 1.2.2.2 skrll map = sc->vge_ldata.vge_tx_dmamap[idx]; 1639 1.2.2.2 skrll error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1640 1.2.2.2 skrll m_head, BUS_DMA_NOWAIT); 1641 1.2.2.2 skrll 1642 1.2.2.3 skrll /* If too many segments to map, coalesce */ 1643 1.2.2.3 skrll if (error == EFBIG) { 1644 1.2.2.2 skrll m_new = m_defrag(m_head, M_DONTWAIT); 1645 1.2.2.2 skrll if (m_new == NULL) 1646 1.2.2.3 skrll return (error); 1647 1.2.2.2 skrll 1648 1.2.2.2 skrll error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1649 1.2.2.3 skrll m_new, BUS_DMA_NOWAIT); 1650 1.2.2.3 skrll if (error) { 1651 1.2.2.3 skrll m_freem(m_new); 1652 1.2.2.3 skrll return (error); 1653 1.2.2.2 skrll } 1654 1.2.2.3 skrll 1655 1.2.2.3 skrll m_head = m_new; 1656 1.2.2.3 skrll } else if (error) 1657 1.2.2.3 skrll return (error); 1658 1.2.2.3 skrll 1659 1.2.2.3 skrll vge_dma_map_tx_desc(sc, m_head, idx, flags); 1660 1.2.2.2 skrll 1661 1.2.2.2 skrll sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1662 1.2.2.2 skrll sc->vge_ldata.vge_tx_free--; 1663 1.2.2.2 skrll 1664 1.2.2.2 skrll /* 1665 1.2.2.2 skrll * Set up hardware VLAN tagging. 1666 1.2.2.2 skrll */ 1667 1.2.2.2 skrll 1668 1.2.2.2 skrll mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1669 1.2.2.2 skrll if (mtag != NULL) 1670 1.2.2.2 skrll sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1671 1.2.2.2 skrll htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1672 1.2.2.2 skrll 1673 1.2.2.2 skrll sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1674 1.2.2.2 skrll 1675 1.2.2.2 skrll return (0); 1676 1.2.2.2 skrll } 1677 1.2.2.2 skrll 1678 1.2.2.2 skrll /* 1679 1.2.2.2 skrll * Main transmit routine. 1680 1.2.2.2 skrll */ 1681 1.2.2.2 skrll 1682 1.2.2.2 skrll static void 1683 1.2.2.2 skrll vge_start(ifp) 1684 1.2.2.2 skrll struct ifnet *ifp; 1685 1.2.2.2 skrll { 1686 1.2.2.2 skrll struct vge_softc *sc; 1687 1.2.2.2 skrll struct mbuf *m_head = NULL; 1688 1.2.2.3 skrll int idx, pidx = 0, error; 1689 1.2.2.2 skrll 1690 1.2.2.2 skrll sc = ifp->if_softc; 1691 1.2.2.2 skrll VGE_LOCK(sc); 1692 1.2.2.2 skrll 1693 1.2.2.3 skrll if (!sc->vge_link 1694 1.2.2.3 skrll || (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1695 1.2.2.2 skrll VGE_UNLOCK(sc); 1696 1.2.2.2 skrll return; 1697 1.2.2.2 skrll } 1698 1.2.2.2 skrll 1699 1.2.2.2 skrll idx = sc->vge_ldata.vge_tx_prodidx; 1700 1.2.2.2 skrll 1701 1.2.2.2 skrll pidx = idx - 1; 1702 1.2.2.2 skrll if (pidx < 0) 1703 1.2.2.2 skrll pidx = VGE_TX_DESC_CNT - 1; 1704 1.2.2.2 skrll 1705 1.2.2.3 skrll /* 1706 1.2.2.3 skrll * Loop through the send queue, setting up transmit descriptors 1707 1.2.2.3 skrll * until we drain the queue, or use up all available transmit 1708 1.2.2.3 skrll * descriptors. 1709 1.2.2.3 skrll */ 1710 1.2.2.3 skrll for(;;) { 1711 1.2.2.3 skrll /* Grab a packet off the queue. */ 1712 1.2.2.3 skrll IFQ_POLL(&ifp->if_snd, m_head); 1713 1.2.2.2 skrll if (m_head == NULL) 1714 1.2.2.2 skrll break; 1715 1.2.2.2 skrll 1716 1.2.2.3 skrll if (sc->vge_ldata.vge_tx_mbuf[idx] != NULL) { 1717 1.2.2.3 skrll /* 1718 1.2.2.3 skrll * Slot already used, stop for now. 1719 1.2.2.3 skrll */ 1720 1.2.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 1721 1.2.2.2 skrll break; 1722 1.2.2.2 skrll } 1723 1.2.2.2 skrll 1724 1.2.2.3 skrll if ((error = vge_encap(sc, m_head, idx))) { 1725 1.2.2.3 skrll if (error == EFBIG) { 1726 1.2.2.3 skrll printf("%s: Tx packet consumes too many " 1727 1.2.2.3 skrll "DMA segments, dropping...\n", 1728 1.2.2.3 skrll sc->sc_dev.dv_xname); 1729 1.2.2.3 skrll IFQ_DEQUEUE(&ifp->if_snd, m_head); 1730 1.2.2.3 skrll m_freem(m_head); 1731 1.2.2.3 skrll continue; 1732 1.2.2.3 skrll } 1733 1.2.2.3 skrll 1734 1.2.2.3 skrll /* 1735 1.2.2.3 skrll * Short on resources, just stop for now. 1736 1.2.2.3 skrll */ 1737 1.2.2.3 skrll if (error == ENOBUFS) 1738 1.2.2.3 skrll ifp->if_flags |= IFF_OACTIVE; 1739 1.2.2.3 skrll break; 1740 1.2.2.3 skrll } 1741 1.2.2.3 skrll 1742 1.2.2.3 skrll IFQ_DEQUEUE(&ifp->if_snd, m_head); 1743 1.2.2.3 skrll 1744 1.2.2.3 skrll /* 1745 1.2.2.3 skrll * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1746 1.2.2.3 skrll */ 1747 1.2.2.3 skrll 1748 1.2.2.2 skrll sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1749 1.2.2.2 skrll htole16(VGE_TXDESC_Q); 1750 1.2.2.2 skrll 1751 1.2.2.3 skrll if (sc->vge_ldata.vge_tx_mbuf[idx] != m_head) { 1752 1.2.2.3 skrll m_freem(m_head); 1753 1.2.2.3 skrll m_head = sc->vge_ldata.vge_tx_mbuf[idx]; 1754 1.2.2.3 skrll } 1755 1.2.2.3 skrll 1756 1.2.2.2 skrll pidx = idx; 1757 1.2.2.2 skrll VGE_TX_DESC_INC(idx); 1758 1.2.2.2 skrll 1759 1.2.2.2 skrll /* 1760 1.2.2.2 skrll * If there's a BPF listener, bounce a copy of this frame 1761 1.2.2.2 skrll * to him. 1762 1.2.2.2 skrll */ 1763 1.2.2.2 skrll #if NBPFILTER > 0 1764 1.2.2.2 skrll if (ifp->if_bpf) 1765 1.2.2.2 skrll bpf_mtap(ifp->if_bpf, m_head); 1766 1.2.2.2 skrll #endif 1767 1.2.2.2 skrll } 1768 1.2.2.2 skrll 1769 1.2.2.2 skrll if (idx == sc->vge_ldata.vge_tx_prodidx) { 1770 1.2.2.2 skrll VGE_UNLOCK(sc); 1771 1.2.2.2 skrll return; 1772 1.2.2.2 skrll } 1773 1.2.2.2 skrll 1774 1.2.2.2 skrll /* Flush the TX descriptors */ 1775 1.2.2.2 skrll 1776 1.2.2.2 skrll bus_dmamap_sync(sc->vge_dmat, 1777 1.2.2.2 skrll sc->vge_ldata.vge_tx_list_map, 1778 1.2.2.2 skrll 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1779 1.2.2.2 skrll BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1780 1.2.2.2 skrll 1781 1.2.2.2 skrll /* Issue a transmit command. */ 1782 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1783 1.2.2.2 skrll 1784 1.2.2.2 skrll sc->vge_ldata.vge_tx_prodidx = idx; 1785 1.2.2.2 skrll 1786 1.2.2.2 skrll /* 1787 1.2.2.2 skrll * Use the countdown timer for interrupt moderation. 1788 1.2.2.2 skrll * 'TX done' interrupts are disabled. Instead, we reset the 1789 1.2.2.2 skrll * countdown timer, which will begin counting until it hits 1790 1.2.2.2 skrll * the value in the SSTIMER register, and then trigger an 1791 1.2.2.2 skrll * interrupt. Each time we set the TIMER0_ENABLE bit, the 1792 1.2.2.2 skrll * the timer count is reloaded. Only when the transmitter 1793 1.2.2.2 skrll * is idle will the timer hit 0 and an interrupt fire. 1794 1.2.2.2 skrll */ 1795 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1796 1.2.2.2 skrll 1797 1.2.2.2 skrll VGE_UNLOCK(sc); 1798 1.2.2.2 skrll 1799 1.2.2.2 skrll /* 1800 1.2.2.2 skrll * Set a timeout in case the chip goes out to lunch. 1801 1.2.2.2 skrll */ 1802 1.2.2.2 skrll ifp->if_timer = 5; 1803 1.2.2.2 skrll 1804 1.2.2.2 skrll return; 1805 1.2.2.2 skrll } 1806 1.2.2.2 skrll 1807 1.2.2.2 skrll static int 1808 1.2.2.2 skrll vge_init(ifp) 1809 1.2.2.2 skrll struct ifnet *ifp; 1810 1.2.2.2 skrll { 1811 1.2.2.2 skrll struct vge_softc *sc = ifp->if_softc; 1812 1.2.2.2 skrll struct mii_data *mii = &sc->sc_mii; 1813 1.2.2.2 skrll int i; 1814 1.2.2.2 skrll 1815 1.2.2.2 skrll VGE_LOCK(sc); 1816 1.2.2.2 skrll 1817 1.2.2.2 skrll /* 1818 1.2.2.2 skrll * Cancel pending I/O and free all RX/TX buffers. 1819 1.2.2.2 skrll */ 1820 1.2.2.2 skrll vge_stop(sc); 1821 1.2.2.2 skrll vge_reset(sc); 1822 1.2.2.2 skrll 1823 1.2.2.2 skrll /* 1824 1.2.2.2 skrll * Initialize the RX and TX descriptors and mbufs. 1825 1.2.2.2 skrll */ 1826 1.2.2.2 skrll 1827 1.2.2.2 skrll vge_rx_list_init(sc); 1828 1.2.2.2 skrll vge_tx_list_init(sc); 1829 1.2.2.2 skrll 1830 1.2.2.2 skrll /* Set our station address */ 1831 1.2.2.2 skrll for (i = 0; i < ETHER_ADDR_LEN; i++) 1832 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_PAR0 + i, sc->vge_eaddr[i]); 1833 1.2.2.2 skrll 1834 1.2.2.2 skrll /* 1835 1.2.2.2 skrll * Set receive FIFO threshold. Also allow transmission and 1836 1.2.2.2 skrll * reception of VLAN tagged frames. 1837 1.2.2.2 skrll */ 1838 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1839 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1840 1.2.2.2 skrll 1841 1.2.2.2 skrll /* Set DMA burst length */ 1842 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1843 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1844 1.2.2.2 skrll 1845 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1846 1.2.2.2 skrll 1847 1.2.2.2 skrll /* Set collision backoff algorithm */ 1848 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1849 1.2.2.2 skrll VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1850 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1851 1.2.2.2 skrll 1852 1.2.2.2 skrll /* Disable LPSEL field in priority resolution */ 1853 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1854 1.2.2.2 skrll 1855 1.2.2.2 skrll /* 1856 1.2.2.2 skrll * Load the addresses of the DMA queues into the chip. 1857 1.2.2.2 skrll * Note that we only use one transmit queue. 1858 1.2.2.2 skrll */ 1859 1.2.2.2 skrll 1860 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1861 1.2.2.2 skrll VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1862 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1863 1.2.2.2 skrll 1864 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1865 1.2.2.2 skrll VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1866 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1867 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1868 1.2.2.2 skrll 1869 1.2.2.2 skrll /* Enable and wake up the RX descriptor queue */ 1870 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1871 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1872 1.2.2.2 skrll 1873 1.2.2.2 skrll /* Enable the TX descriptor queue */ 1874 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1875 1.2.2.2 skrll 1876 1.2.2.2 skrll /* Set up the receive filter -- allow large frames for VLANs. */ 1877 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1878 1.2.2.2 skrll 1879 1.2.2.2 skrll /* If we want promiscuous mode, set the allframes bit. */ 1880 1.2.2.2 skrll if (ifp->if_flags & IFF_PROMISC) { 1881 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1882 1.2.2.2 skrll } 1883 1.2.2.2 skrll 1884 1.2.2.2 skrll /* Set capture broadcast bit to capture broadcast frames. */ 1885 1.2.2.2 skrll if (ifp->if_flags & IFF_BROADCAST) { 1886 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1887 1.2.2.2 skrll } 1888 1.2.2.2 skrll 1889 1.2.2.2 skrll /* Set multicast bit to capture multicast frames. */ 1890 1.2.2.2 skrll if (ifp->if_flags & IFF_MULTICAST) { 1891 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1892 1.2.2.2 skrll } 1893 1.2.2.2 skrll 1894 1.2.2.2 skrll /* Init the cam filter. */ 1895 1.2.2.2 skrll vge_cam_clear(sc); 1896 1.2.2.2 skrll 1897 1.2.2.2 skrll /* Init the multicast filter. */ 1898 1.2.2.2 skrll vge_setmulti(sc); 1899 1.2.2.2 skrll 1900 1.2.2.2 skrll /* Enable flow control */ 1901 1.2.2.2 skrll 1902 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1903 1.2.2.2 skrll 1904 1.2.2.2 skrll /* Enable jumbo frame reception (if desired) */ 1905 1.2.2.2 skrll 1906 1.2.2.2 skrll /* Start the MAC. */ 1907 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1908 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1909 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS0, 1910 1.2.2.2 skrll VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1911 1.2.2.2 skrll 1912 1.2.2.2 skrll /* 1913 1.2.2.2 skrll * Configure one-shot timer for microsecond 1914 1.2.2.2 skrll * resulution and load it for 500 usecs. 1915 1.2.2.2 skrll */ 1916 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1917 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1918 1.2.2.2 skrll 1919 1.2.2.2 skrll /* 1920 1.2.2.2 skrll * Configure interrupt moderation for receive. Enable 1921 1.2.2.2 skrll * the holdoff counter and load it, and set the RX 1922 1.2.2.2 skrll * suppression count to the number of descriptors we 1923 1.2.2.2 skrll * want to allow before triggering an interrupt. 1924 1.2.2.2 skrll * The holdoff timer is in units of 20 usecs. 1925 1.2.2.2 skrll */ 1926 1.2.2.2 skrll 1927 1.2.2.2 skrll #ifdef notyet 1928 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1929 1.2.2.2 skrll /* Select the interrupt holdoff timer page. */ 1930 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1931 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1932 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1933 1.2.2.2 skrll 1934 1.2.2.2 skrll /* Enable use of the holdoff timer. */ 1935 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1936 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1937 1.2.2.2 skrll 1938 1.2.2.2 skrll /* Select the RX suppression threshold page. */ 1939 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1940 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1941 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1942 1.2.2.2 skrll 1943 1.2.2.2 skrll /* Restore the page select bits. */ 1944 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1945 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1946 1.2.2.2 skrll #endif 1947 1.2.2.2 skrll 1948 1.2.2.2 skrll #ifdef DEVICE_POLLING 1949 1.2.2.2 skrll /* 1950 1.2.2.2 skrll * Disable interrupts if we are polling. 1951 1.2.2.2 skrll */ 1952 1.2.2.2 skrll if (ifp->if_flags & IFF_POLLING) { 1953 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_IMR, 0); 1954 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1955 1.2.2.2 skrll } else /* otherwise ... */ 1956 1.2.2.2 skrll #endif /* DEVICE_POLLING */ 1957 1.2.2.2 skrll { 1958 1.2.2.2 skrll /* 1959 1.2.2.2 skrll * Enable interrupts. 1960 1.2.2.2 skrll */ 1961 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1962 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_ISR, 0); 1963 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1964 1.2.2.2 skrll } 1965 1.2.2.2 skrll 1966 1.2.2.2 skrll mii_mediachg(mii); 1967 1.2.2.2 skrll 1968 1.2.2.2 skrll ifp->if_flags |= IFF_RUNNING; 1969 1.2.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 1970 1.2.2.2 skrll 1971 1.2.2.2 skrll sc->vge_if_flags = 0; 1972 1.2.2.2 skrll sc->vge_link = 0; 1973 1.2.2.2 skrll 1974 1.2.2.2 skrll VGE_UNLOCK(sc); 1975 1.2.2.2 skrll 1976 1.2.2.2 skrll callout_schedule(&sc->vge_timeout, hz); 1977 1.2.2.2 skrll 1978 1.2.2.2 skrll return (0); 1979 1.2.2.2 skrll } 1980 1.2.2.2 skrll 1981 1.2.2.2 skrll /* 1982 1.2.2.2 skrll * Set media options. 1983 1.2.2.2 skrll */ 1984 1.2.2.2 skrll static int 1985 1.2.2.2 skrll vge_ifmedia_upd(ifp) 1986 1.2.2.2 skrll struct ifnet *ifp; 1987 1.2.2.2 skrll { 1988 1.2.2.2 skrll struct vge_softc *sc = ifp->if_softc; 1989 1.2.2.2 skrll struct mii_data *mii = &sc->sc_mii; 1990 1.2.2.2 skrll 1991 1.2.2.2 skrll mii_mediachg(mii); 1992 1.2.2.2 skrll 1993 1.2.2.2 skrll return (0); 1994 1.2.2.2 skrll } 1995 1.2.2.2 skrll 1996 1.2.2.2 skrll /* 1997 1.2.2.2 skrll * Report current media status. 1998 1.2.2.2 skrll */ 1999 1.2.2.2 skrll static void 2000 1.2.2.2 skrll vge_ifmedia_sts(ifp, ifmr) 2001 1.2.2.2 skrll struct ifnet *ifp; 2002 1.2.2.2 skrll struct ifmediareq *ifmr; 2003 1.2.2.2 skrll { 2004 1.2.2.2 skrll struct vge_softc *sc = ifp->if_softc; 2005 1.2.2.2 skrll struct mii_data *mii = &sc->sc_mii; 2006 1.2.2.2 skrll 2007 1.2.2.2 skrll mii_pollstat(mii); 2008 1.2.2.2 skrll ifmr->ifm_active = mii->mii_media_active; 2009 1.2.2.2 skrll ifmr->ifm_status = mii->mii_media_status; 2010 1.2.2.2 skrll 2011 1.2.2.2 skrll return; 2012 1.2.2.2 skrll } 2013 1.2.2.2 skrll 2014 1.2.2.2 skrll static void 2015 1.2.2.2 skrll vge_miibus_statchg(self) 2016 1.2.2.2 skrll struct device *self; 2017 1.2.2.2 skrll { 2018 1.2.2.2 skrll struct vge_softc *sc = (struct vge_softc *) self; 2019 1.2.2.2 skrll struct mii_data *mii = &sc->sc_mii; 2020 1.2.2.2 skrll struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 2021 1.2.2.2 skrll 2022 1.2.2.2 skrll /* 2023 1.2.2.2 skrll * If the user manually selects a media mode, we need to turn 2024 1.2.2.2 skrll * on the forced MAC mode bit in the DIAGCTL register. If the 2025 1.2.2.2 skrll * user happens to choose a full duplex mode, we also need to 2026 1.2.2.2 skrll * set the 'force full duplex' bit. This applies only to 2027 1.2.2.2 skrll * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2028 1.2.2.2 skrll * mode is disabled, and in 1000baseT mode, full duplex is 2029 1.2.2.2 skrll * always implied, so we turn on the forced mode bit but leave 2030 1.2.2.2 skrll * the FDX bit cleared. 2031 1.2.2.2 skrll */ 2032 1.2.2.2 skrll 2033 1.2.2.2 skrll switch (IFM_SUBTYPE(ife->ifm_media)) { 2034 1.2.2.2 skrll case IFM_AUTO: 2035 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2036 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2037 1.2.2.2 skrll break; 2038 1.2.2.2 skrll case IFM_1000_T: 2039 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2040 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2041 1.2.2.2 skrll break; 2042 1.2.2.2 skrll case IFM_100_TX: 2043 1.2.2.2 skrll case IFM_10_T: 2044 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2045 1.2.2.2 skrll if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2046 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2047 1.2.2.2 skrll } else { 2048 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2049 1.2.2.2 skrll } 2050 1.2.2.2 skrll break; 2051 1.2.2.2 skrll default: 2052 1.2.2.2 skrll printf("%s: unknown media type: %x\n", 2053 1.2.2.2 skrll sc->sc_dev.dv_xname, 2054 1.2.2.2 skrll IFM_SUBTYPE(ife->ifm_media)); 2055 1.2.2.2 skrll break; 2056 1.2.2.2 skrll } 2057 1.2.2.2 skrll 2058 1.2.2.2 skrll return; 2059 1.2.2.2 skrll } 2060 1.2.2.2 skrll 2061 1.2.2.2 skrll static int 2062 1.2.2.2 skrll vge_ioctl(ifp, command, data) 2063 1.2.2.2 skrll struct ifnet *ifp; 2064 1.2.2.2 skrll u_long command; 2065 1.2.2.2 skrll caddr_t data; 2066 1.2.2.2 skrll { 2067 1.2.2.2 skrll struct vge_softc *sc = ifp->if_softc; 2068 1.2.2.2 skrll struct ifreq *ifr = (struct ifreq *) data; 2069 1.2.2.2 skrll struct mii_data *mii; 2070 1.2.2.4 skrll int s, error = 0; 2071 1.2.2.4 skrll 2072 1.2.2.4 skrll s = splnet(); 2073 1.2.2.2 skrll 2074 1.2.2.2 skrll switch (command) { 2075 1.2.2.2 skrll case SIOCSIFMTU: 2076 1.2.2.2 skrll if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2077 1.2.2.2 skrll error = EINVAL; 2078 1.2.2.2 skrll ifp->if_mtu = ifr->ifr_mtu; 2079 1.2.2.2 skrll break; 2080 1.2.2.2 skrll case SIOCSIFFLAGS: 2081 1.2.2.2 skrll if (ifp->if_flags & IFF_UP) { 2082 1.2.2.2 skrll if (ifp->if_flags & IFF_RUNNING && 2083 1.2.2.2 skrll ifp->if_flags & IFF_PROMISC && 2084 1.2.2.2 skrll !(sc->vge_if_flags & IFF_PROMISC)) { 2085 1.2.2.2 skrll CSR_SETBIT_1(sc, VGE_RXCTL, 2086 1.2.2.2 skrll VGE_RXCTL_RX_PROMISC); 2087 1.2.2.2 skrll vge_setmulti(sc); 2088 1.2.2.2 skrll } else if (ifp->if_flags & IFF_RUNNING && 2089 1.2.2.2 skrll !(ifp->if_flags & IFF_PROMISC) && 2090 1.2.2.2 skrll sc->vge_if_flags & IFF_PROMISC) { 2091 1.2.2.2 skrll CSR_CLRBIT_1(sc, VGE_RXCTL, 2092 1.2.2.2 skrll VGE_RXCTL_RX_PROMISC); 2093 1.2.2.2 skrll vge_setmulti(sc); 2094 1.2.2.2 skrll } else 2095 1.2.2.2 skrll vge_init(ifp); 2096 1.2.2.2 skrll } else { 2097 1.2.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 2098 1.2.2.2 skrll vge_stop(sc); 2099 1.2.2.2 skrll } 2100 1.2.2.2 skrll sc->vge_if_flags = ifp->if_flags; 2101 1.2.2.2 skrll break; 2102 1.2.2.2 skrll case SIOCADDMULTI: 2103 1.2.2.2 skrll case SIOCDELMULTI: 2104 1.2.2.4 skrll error = (command == SIOCADDMULTI) ? 2105 1.2.2.4 skrll ether_addmulti(ifr, &sc->sc_ethercom) : 2106 1.2.2.4 skrll ether_delmulti(ifr, &sc->sc_ethercom); 2107 1.2.2.4 skrll 2108 1.2.2.4 skrll if (error == ENETRESET) { 2109 1.2.2.4 skrll /* 2110 1.2.2.4 skrll * Multicast list has changed; set the hardware filter 2111 1.2.2.4 skrll * accordingly. 2112 1.2.2.4 skrll */ 2113 1.2.2.4 skrll if (ifp->if_flags & IFF_RUNNING) 2114 1.2.2.4 skrll vge_setmulti(sc); 2115 1.2.2.4 skrll error = 0; 2116 1.2.2.4 skrll } 2117 1.2.2.2 skrll break; 2118 1.2.2.2 skrll case SIOCGIFMEDIA: 2119 1.2.2.2 skrll case SIOCSIFMEDIA: 2120 1.2.2.2 skrll mii = &sc->sc_mii; 2121 1.2.2.2 skrll error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2122 1.2.2.2 skrll break; 2123 1.2.2.2 skrll default: 2124 1.2.2.2 skrll error = ether_ioctl(ifp, command, data); 2125 1.2.2.2 skrll break; 2126 1.2.2.2 skrll } 2127 1.2.2.2 skrll 2128 1.2.2.4 skrll splx(s); 2129 1.2.2.2 skrll return (error); 2130 1.2.2.2 skrll } 2131 1.2.2.2 skrll 2132 1.2.2.2 skrll static void 2133 1.2.2.2 skrll vge_watchdog(ifp) 2134 1.2.2.2 skrll struct ifnet *ifp; 2135 1.2.2.2 skrll { 2136 1.2.2.2 skrll struct vge_softc *sc; 2137 1.2.2.2 skrll 2138 1.2.2.2 skrll sc = ifp->if_softc; 2139 1.2.2.2 skrll VGE_LOCK(sc); 2140 1.2.2.2 skrll printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2141 1.2.2.2 skrll ifp->if_oerrors++; 2142 1.2.2.2 skrll 2143 1.2.2.2 skrll vge_txeof(sc); 2144 1.2.2.2 skrll vge_rxeof(sc); 2145 1.2.2.2 skrll 2146 1.2.2.2 skrll vge_init(ifp); 2147 1.2.2.2 skrll 2148 1.2.2.2 skrll VGE_UNLOCK(sc); 2149 1.2.2.2 skrll 2150 1.2.2.2 skrll return; 2151 1.2.2.2 skrll } 2152 1.2.2.2 skrll 2153 1.2.2.2 skrll /* 2154 1.2.2.2 skrll * Stop the adapter and free any mbufs allocated to the 2155 1.2.2.2 skrll * RX and TX lists. 2156 1.2.2.2 skrll */ 2157 1.2.2.2 skrll static void 2158 1.2.2.2 skrll vge_stop(sc) 2159 1.2.2.2 skrll struct vge_softc *sc; 2160 1.2.2.2 skrll { 2161 1.2.2.2 skrll register int i; 2162 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2163 1.2.2.2 skrll 2164 1.2.2.2 skrll VGE_LOCK(sc); 2165 1.2.2.2 skrll ifp->if_timer = 0; 2166 1.2.2.2 skrll 2167 1.2.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2168 1.2.2.2 skrll #ifdef DEVICE_POLLING 2169 1.2.2.2 skrll ether_poll_deregister(ifp); 2170 1.2.2.2 skrll #endif /* DEVICE_POLLING */ 2171 1.2.2.2 skrll 2172 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2173 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2174 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2175 1.2.2.2 skrll CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2176 1.2.2.2 skrll CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2177 1.2.2.2 skrll CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2178 1.2.2.2 skrll 2179 1.2.2.2 skrll if (sc->vge_head != NULL) { 2180 1.2.2.2 skrll m_freem(sc->vge_head); 2181 1.2.2.2 skrll sc->vge_head = sc->vge_tail = NULL; 2182 1.2.2.2 skrll } 2183 1.2.2.2 skrll 2184 1.2.2.2 skrll /* Free the TX list buffers. */ 2185 1.2.2.2 skrll 2186 1.2.2.2 skrll for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2187 1.2.2.2 skrll if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2188 1.2.2.2 skrll bus_dmamap_unload(sc->vge_dmat, 2189 1.2.2.2 skrll sc->vge_ldata.vge_tx_dmamap[i]); 2190 1.2.2.2 skrll m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2191 1.2.2.2 skrll sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2192 1.2.2.2 skrll } 2193 1.2.2.2 skrll } 2194 1.2.2.2 skrll 2195 1.2.2.2 skrll /* Free the RX list buffers. */ 2196 1.2.2.2 skrll 2197 1.2.2.2 skrll for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2198 1.2.2.2 skrll if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2199 1.2.2.2 skrll bus_dmamap_unload(sc->vge_dmat, 2200 1.2.2.2 skrll sc->vge_ldata.vge_rx_dmamap[i]); 2201 1.2.2.2 skrll m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2202 1.2.2.2 skrll sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2203 1.2.2.2 skrll } 2204 1.2.2.2 skrll } 2205 1.2.2.2 skrll 2206 1.2.2.2 skrll VGE_UNLOCK(sc); 2207 1.2.2.2 skrll 2208 1.2.2.2 skrll return; 2209 1.2.2.2 skrll } 2210 1.2.2.2 skrll 2211 1.2.2.2 skrll #if VGE_POWER_MANAGEMENT 2212 1.2.2.2 skrll /* 2213 1.2.2.2 skrll * Device suspend routine. Stop the interface and save some PCI 2214 1.2.2.2 skrll * settings in case the BIOS doesn't restore them properly on 2215 1.2.2.2 skrll * resume. 2216 1.2.2.2 skrll */ 2217 1.2.2.2 skrll static int 2218 1.2.2.2 skrll vge_suspend(dev) 2219 1.2.2.2 skrll struct device * dev; 2220 1.2.2.2 skrll { 2221 1.2.2.2 skrll struct vge_softc *sc; 2222 1.2.2.2 skrll int i; 2223 1.2.2.2 skrll 2224 1.2.2.2 skrll sc = device_get_softc(dev); 2225 1.2.2.2 skrll 2226 1.2.2.2 skrll vge_stop(sc); 2227 1.2.2.2 skrll 2228 1.2.2.2 skrll for (i = 0; i < 5; i++) 2229 1.2.2.2 skrll sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2230 1.2.2.2 skrll sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2231 1.2.2.2 skrll sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2232 1.2.2.2 skrll sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2233 1.2.2.2 skrll sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2234 1.2.2.2 skrll 2235 1.2.2.2 skrll sc->suspended = 1; 2236 1.2.2.2 skrll 2237 1.2.2.2 skrll return (0); 2238 1.2.2.2 skrll } 2239 1.2.2.2 skrll 2240 1.2.2.2 skrll /* 2241 1.2.2.2 skrll * Device resume routine. Restore some PCI settings in case the BIOS 2242 1.2.2.2 skrll * doesn't, re-enable busmastering, and restart the interface if 2243 1.2.2.2 skrll * appropriate. 2244 1.2.2.2 skrll */ 2245 1.2.2.2 skrll static int 2246 1.2.2.2 skrll vge_resume(dev) 2247 1.2.2.2 skrll struct device * dev; 2248 1.2.2.2 skrll { 2249 1.2.2.2 skrll struct vge_softc *sc = (struct vge_softc *)dev; 2250 1.2.2.2 skrll struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2251 1.2.2.2 skrll int i; 2252 1.2.2.2 skrll 2253 1.2.2.2 skrll /* better way to do this? */ 2254 1.2.2.2 skrll for (i = 0; i < 5; i++) 2255 1.2.2.2 skrll pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2256 1.2.2.2 skrll pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2257 1.2.2.2 skrll pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2258 1.2.2.2 skrll pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2259 1.2.2.2 skrll pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2260 1.2.2.2 skrll 2261 1.2.2.2 skrll /* reenable busmastering */ 2262 1.2.2.2 skrll pci_enable_busmaster(dev); 2263 1.2.2.2 skrll pci_enable_io(dev, SYS_RES_MEMORY); 2264 1.2.2.2 skrll 2265 1.2.2.2 skrll /* reinitialize interface if necessary */ 2266 1.2.2.2 skrll if (ifp->if_flags & IFF_UP) 2267 1.2.2.2 skrll vge_init(sc); 2268 1.2.2.2 skrll 2269 1.2.2.2 skrll sc->suspended = 0; 2270 1.2.2.2 skrll 2271 1.2.2.2 skrll return (0); 2272 1.2.2.2 skrll } 2273 1.2.2.2 skrll #endif 2274 1.2.2.2 skrll 2275 1.2.2.2 skrll /* 2276 1.2.2.2 skrll * Stop all chip I/O so that the kernel's probe routines don't 2277 1.2.2.2 skrll * get confused by errant DMAs when rebooting. 2278 1.2.2.2 skrll */ 2279 1.2.2.2 skrll static void 2280 1.2.2.2 skrll vge_shutdown(arg) 2281 1.2.2.2 skrll void *arg; 2282 1.2.2.2 skrll { 2283 1.2.2.2 skrll struct vge_softc *sc = (struct vge_softc *)arg; 2284 1.2.2.2 skrll 2285 1.2.2.2 skrll vge_stop(sc); 2286 1.2.2.2 skrll } 2287
Indexes created Thu Oct 16 14:10:15 GMT 2025