if_vge.c revision 1.27
1 /* $NetBSD: if_vge.c,v 1.27 2006/11/16 01:33:09 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.27 2006/11/16 01:33:09 christos Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul (at) windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/if_ether.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <machine/bus.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #include <dev/pci/if_vgereg.h> 116 117 #define VGE_JUMBO_MTU 9000 118 119 #define VGE_IFQ_MAXLEN 64 120 121 #define VGE_RING_ALIGN 256 122 123 #define VGE_NTXDESC 256 124 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1) 125 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK) 126 127 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */ 128 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1) 129 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK) 130 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK) 131 132 #define VGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 133 #define VGE_ADDR_HI(y) ((uint64_t)(y) >> 32) 134 #define VGE_BUFLEN(y) ((y) & 0x7FFF) 135 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 136 137 #ifdef __NO_STRICT_ALIGNMENT 138 #define VGE_RX_PAD sizeof(uint32_t) 139 #else 140 #define VGE_RX_PAD 0 141 #endif 142 143 /* 144 * Control structures are DMA'd to the vge chip. We allocate them in 145 * a single clump that maps to a single DMA segment to make several things 146 * easier. 147 */ 148 struct vge_control_data { 149 /* TX descriptors */ 150 struct vge_txdesc vcd_txdescs[VGE_NTXDESC]; 151 /* RX descriptors */ 152 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC]; 153 /* dummy data for TX padding */ 154 uint8_t vcd_pad[ETHER_PAD_LEN]; 155 }; 156 157 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x) 158 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)]) 159 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)]) 160 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0]) 161 162 /* 163 * Software state for TX jobs. 164 */ 165 struct vge_txsoft { 166 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 167 bus_dmamap_t txs_dmamap; /* our DMA map */ 168 }; 169 170 /* 171 * Software state for RX jobs. 172 */ 173 struct vge_rxsoft { 174 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t rxs_dmamap; /* our DMA map */ 176 }; 177 178 179 struct vge_softc { 180 struct device sc_dev; 181 182 bus_space_tag_t sc_bst; /* bus space tag */ 183 bus_space_handle_t sc_bsh; /* bus space handle */ 184 bus_dma_tag_t sc_dmat; 185 186 struct ethercom sc_ethercom; /* interface info */ 187 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 188 189 void *sc_intrhand; 190 struct mii_data sc_mii; 191 uint8_t sc_type; 192 int sc_if_flags; 193 int sc_link; 194 int sc_camidx; 195 struct callout sc_timeout; 196 197 bus_dmamap_t sc_cddmamap; 198 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 199 200 struct vge_txsoft sc_txsoft[VGE_NTXDESC]; 201 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC]; 202 struct vge_control_data *sc_control_data; 203 #define sc_txdescs sc_control_data->vcd_txdescs 204 #define sc_rxdescs sc_control_data->vcd_rxdescs 205 206 int sc_tx_prodidx; 207 int sc_tx_considx; 208 int sc_tx_free; 209 210 struct mbuf *sc_rx_mhead; 211 struct mbuf *sc_rx_mtail; 212 int sc_rx_prodidx; 213 int sc_rx_consumed; 214 215 int sc_suspended; /* 0 = normal 1 = suspended */ 216 uint32_t sc_saved_maps[5]; /* pci data */ 217 uint32_t sc_saved_biosaddr; 218 uint8_t sc_saved_intline; 219 uint8_t sc_saved_cachelnsz; 220 uint8_t sc_saved_lattimer; 221 }; 222 223 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x)) 224 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x)) 225 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF()) 226 227 #define VGE_TXDESCSYNC(sc, idx, ops) \ 228 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \ 229 VGE_CDTXOFF(idx), \ 230 offsetof(struct vge_txdesc, td_frag[0]), \ 231 (ops)) 232 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \ 233 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 234 VGE_CDTXOFF(idx) + \ 235 offsetof(struct vge_txdesc, td_frag[0]), \ 236 sizeof(struct vge_txfrag) * (nsegs), \ 237 (ops)) 238 #define VGE_RXDESCSYNC(sc, idx, ops) \ 239 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 240 VGE_CDRXOFF(idx), \ 241 sizeof(struct vge_rxdesc), \ 242 (ops)) 243 244 /* 245 * Mbuf adjust factor to force 32-bit alignment of IP header. 246 * Drivers should do m_adj(m, ETHER_ALIGN) when setting up a 247 * receive so the upper layers get the IP header properly aligned 248 * past the 14-byte Ethernet header. 249 */ 250 #define ETHER_ALIGN 2 251 252 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */ 253 254 /* 255 * register space access macros 256 */ 257 #define CSR_WRITE_4(sc, reg, val) \ 258 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 259 #define CSR_WRITE_2(sc, reg, val) \ 260 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 261 #define CSR_WRITE_1(sc, reg, val) \ 262 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 263 264 #define CSR_READ_4(sc, reg) \ 265 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 266 #define CSR_READ_2(sc, reg) \ 267 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg)) 268 #define CSR_READ_1(sc, reg) \ 269 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 270 271 #define CSR_SETBIT_1(sc, reg, x) \ 272 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x)) 273 #define CSR_SETBIT_2(sc, reg, x) \ 274 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x)) 275 #define CSR_SETBIT_4(sc, reg, x) \ 276 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x)) 277 278 #define CSR_CLRBIT_1(sc, reg, x) \ 279 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x)) 280 #define CSR_CLRBIT_2(sc, reg, x) \ 281 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x)) 282 #define CSR_CLRBIT_4(sc, reg, x) \ 283 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x)) 284 285 #define VGE_TIMEOUT 10000 286 287 #define VGE_PCI_LOIO 0x10 288 #define VGE_PCI_LOMEM 0x14 289 290 static int vge_probe(struct device *, struct cfdata *, void *); 291 static void vge_attach(struct device *, struct device *, void *); 292 293 static int vge_encap(struct vge_softc *, struct mbuf *, int); 294 295 static int vge_allocmem(struct vge_softc *); 296 static int vge_newbuf(struct vge_softc *, int, struct mbuf *); 297 #ifndef __NO_STRICT_ALIGNMENT 298 static inline void vge_fixup_rx(struct mbuf *); 299 #endif 300 static void vge_rxeof(struct vge_softc *); 301 static void vge_txeof(struct vge_softc *); 302 static int vge_intr(void *); 303 static void vge_tick(void *); 304 static void vge_start(struct ifnet *); 305 static int vge_ioctl(struct ifnet *, u_long, caddr_t); 306 static int vge_init(struct ifnet *); 307 static void vge_stop(struct vge_softc *); 308 static void vge_watchdog(struct ifnet *); 309 #if VGE_POWER_MANAGEMENT 310 static int vge_suspend(struct device *); 311 static int vge_resume(struct device *); 312 #endif 313 static void vge_shutdown(void *); 314 static int vge_ifmedia_upd(struct ifnet *); 315 static void vge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 316 317 static uint16_t vge_read_eeprom(struct vge_softc *, int); 318 319 static void vge_miipoll_start(struct vge_softc *); 320 static void vge_miipoll_stop(struct vge_softc *); 321 static int vge_miibus_readreg(struct device *, int, int); 322 static void vge_miibus_writereg(struct device *, int, int, int); 323 static void vge_miibus_statchg(struct device *); 324 325 static void vge_cam_clear(struct vge_softc *); 326 static int vge_cam_set(struct vge_softc *, uint8_t *); 327 static void vge_setmulti(struct vge_softc *); 328 static void vge_reset(struct vge_softc *); 329 330 CFATTACH_DECL(vge, sizeof(struct vge_softc), 331 vge_probe, vge_attach, NULL, NULL); 332 333 /* 334 * Defragment mbuf chain contents to be as linear as possible. 335 * Returns new mbuf chain on success, NULL on failure. Old mbuf 336 * chain is always freed. 337 * XXX temporary until there would be generic function doing this. 338 */ 339 #define m_defrag vge_m_defrag 340 struct mbuf * vge_m_defrag(struct mbuf *, int); 341 342 struct mbuf * 343 vge_m_defrag(struct mbuf *mold, int flags) 344 { 345 struct mbuf *m0, *mn, *n; 346 size_t sz = mold->m_pkthdr.len; 347 348 #ifdef DIAGNOSTIC 349 if ((mold->m_flags & M_PKTHDR) == 0) 350 panic("m_defrag: not a mbuf chain header"); 351 #endif 352 353 MGETHDR(m0, flags, MT_DATA); 354 if (m0 == NULL) 355 return NULL; 356 m0->m_pkthdr.len = mold->m_pkthdr.len; 357 mn = m0; 358 359 do { 360 if (sz > MHLEN) { 361 MCLGET(mn, M_DONTWAIT); 362 if ((mn->m_flags & M_EXT) == 0) { 363 m_freem(m0); 364 return NULL; 365 } 366 } 367 368 mn->m_len = MIN(sz, MCLBYTES); 369 370 m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 371 mtod(mn, caddr_t)); 372 373 sz -= mn->m_len; 374 375 if (sz > 0) { 376 /* need more mbufs */ 377 MGET(n, M_NOWAIT, MT_DATA); 378 if (n == NULL) { 379 m_freem(m0); 380 return NULL; 381 } 382 383 mn->m_next = n; 384 mn = n; 385 } 386 } while (sz > 0); 387 388 return m0; 389 } 390 391 /* 392 * Read a word of data stored in the EEPROM at address 'addr.' 393 */ 394 static uint16_t 395 vge_read_eeprom(struct vge_softc *sc, int addr) 396 { 397 int i; 398 uint16_t word = 0; 399 400 /* 401 * Enter EEPROM embedded programming mode. In order to 402 * access the EEPROM at all, we first have to set the 403 * EELOAD bit in the CHIPCFG2 register. 404 */ 405 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 406 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 407 408 /* Select the address of the word we want to read */ 409 CSR_WRITE_1(sc, VGE_EEADDR, addr); 410 411 /* Issue read command */ 412 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 413 414 /* Wait for the done bit to be set. */ 415 for (i = 0; i < VGE_TIMEOUT; i++) { 416 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 417 break; 418 } 419 420 if (i == VGE_TIMEOUT) { 421 aprint_error("%s: EEPROM read timed out\n", 422 sc->sc_dev.dv_xname); 423 return 0; 424 } 425 426 /* Read the result */ 427 word = CSR_READ_2(sc, VGE_EERDDAT); 428 429 /* Turn off EEPROM access mode. */ 430 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 431 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 432 433 return word; 434 } 435 436 static void 437 vge_miipoll_stop(struct vge_softc *sc) 438 { 439 int i; 440 441 CSR_WRITE_1(sc, VGE_MIICMD, 0); 442 443 for (i = 0; i < VGE_TIMEOUT; i++) { 444 DELAY(1); 445 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 446 break; 447 } 448 449 if (i == VGE_TIMEOUT) { 450 aprint_error("%s: failed to idle MII autopoll\n", 451 sc->sc_dev.dv_xname); 452 } 453 } 454 455 static void 456 vge_miipoll_start(struct vge_softc *sc) 457 { 458 int i; 459 460 /* First, make sure we're idle. */ 461 462 CSR_WRITE_1(sc, VGE_MIICMD, 0); 463 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 464 465 for (i = 0; i < VGE_TIMEOUT; i++) { 466 DELAY(1); 467 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 468 break; 469 } 470 471 if (i == VGE_TIMEOUT) { 472 aprint_error("%s: failed to idle MII autopoll\n", 473 sc->sc_dev.dv_xname); 474 return; 475 } 476 477 /* Now enable auto poll mode. */ 478 479 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 480 481 /* And make sure it started. */ 482 483 for (i = 0; i < VGE_TIMEOUT; i++) { 484 DELAY(1); 485 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 486 break; 487 } 488 489 if (i == VGE_TIMEOUT) { 490 aprint_error("%s: failed to start MII autopoll\n", 491 sc->sc_dev.dv_xname); 492 } 493 } 494 495 static int 496 vge_miibus_readreg(struct device *dev, int phy, int reg) 497 { 498 struct vge_softc *sc; 499 int i, s; 500 uint16_t rval; 501 502 sc = (void *)dev; 503 rval = 0; 504 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 505 return 0; 506 507 s = splnet(); 508 vge_miipoll_stop(sc); 509 510 /* Specify the register we want to read. */ 511 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 512 513 /* Issue read command. */ 514 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 515 516 /* Wait for the read command bit to self-clear. */ 517 for (i = 0; i < VGE_TIMEOUT; i++) { 518 DELAY(1); 519 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 520 break; 521 } 522 523 if (i == VGE_TIMEOUT) 524 aprint_error("%s: MII read timed out\n", sc->sc_dev.dv_xname); 525 else 526 rval = CSR_READ_2(sc, VGE_MIIDATA); 527 528 vge_miipoll_start(sc); 529 splx(s); 530 531 return rval; 532 } 533 534 static void 535 vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 536 { 537 struct vge_softc *sc; 538 int i, s; 539 540 sc = (void *)dev; 541 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 542 return; 543 544 s = splnet(); 545 vge_miipoll_stop(sc); 546 547 /* Specify the register we want to write. */ 548 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 549 550 /* Specify the data we want to write. */ 551 CSR_WRITE_2(sc, VGE_MIIDATA, data); 552 553 /* Issue write command. */ 554 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 555 556 /* Wait for the write command bit to self-clear. */ 557 for (i = 0; i < VGE_TIMEOUT; i++) { 558 DELAY(1); 559 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 560 break; 561 } 562 563 if (i == VGE_TIMEOUT) { 564 aprint_error("%s: MII write timed out\n", sc->sc_dev.dv_xname); 565 } 566 567 vge_miipoll_start(sc); 568 splx(s); 569 } 570 571 static void 572 vge_cam_clear(struct vge_softc *sc) 573 { 574 int i; 575 576 /* 577 * Turn off all the mask bits. This tells the chip 578 * that none of the entries in the CAM filter are valid. 579 * desired entries will be enabled as we fill the filter in. 580 */ 581 582 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 583 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 584 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 585 for (i = 0; i < 8; i++) 586 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 587 588 /* Clear the VLAN filter too. */ 589 590 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 591 for (i = 0; i < 8; i++) 592 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 593 594 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 595 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 596 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 597 598 sc->sc_camidx = 0; 599 } 600 601 static int 602 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 603 { 604 int i, error; 605 606 error = 0; 607 608 if (sc->sc_camidx == VGE_CAM_MAXADDRS) 609 return ENOSPC; 610 611 /* Select the CAM data page. */ 612 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 613 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 614 615 /* Set the filter entry we want to update and enable writing. */ 616 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx); 617 618 /* Write the address to the CAM registers */ 619 for (i = 0; i < ETHER_ADDR_LEN; i++) 620 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 621 622 /* Issue a write command. */ 623 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 624 625 /* Wake for it to clear. */ 626 for (i = 0; i < VGE_TIMEOUT; i++) { 627 DELAY(1); 628 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 629 break; 630 } 631 632 if (i == VGE_TIMEOUT) { 633 aprint_error("%s: setting CAM filter failed\n", 634 sc->sc_dev.dv_xname); 635 error = EIO; 636 goto fail; 637 } 638 639 /* Select the CAM mask page. */ 640 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 641 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 642 643 /* Set the mask bit that enables this filter. */ 644 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8), 645 1 << (sc->sc_camidx & 7)); 646 647 sc->sc_camidx++; 648 649 fail: 650 /* Turn off access to CAM. */ 651 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 652 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 653 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 654 655 return error; 656 } 657 658 /* 659 * Program the multicast filter. We use the 64-entry CAM filter 660 * for perfect filtering. If there's more than 64 multicast addresses, 661 * we use the hash filter instead. 662 */ 663 static void 664 vge_setmulti(struct vge_softc *sc) 665 { 666 struct ifnet *ifp; 667 int error; 668 uint32_t h, hashes[2] = { 0, 0 }; 669 struct ether_multi *enm; 670 struct ether_multistep step; 671 672 error = 0; 673 ifp = &sc->sc_ethercom.ec_if; 674 675 /* First, zot all the multicast entries. */ 676 vge_cam_clear(sc); 677 CSR_WRITE_4(sc, VGE_MAR0, 0); 678 CSR_WRITE_4(sc, VGE_MAR1, 0); 679 ifp->if_flags &= ~IFF_ALLMULTI; 680 681 /* 682 * If the user wants allmulti or promisc mode, enable reception 683 * of all multicast frames. 684 */ 685 if (ifp->if_flags & IFF_PROMISC) { 686 allmulti: 687 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 688 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 689 ifp->if_flags |= IFF_ALLMULTI; 690 return; 691 } 692 693 /* Now program new ones */ 694 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 695 while (enm != NULL) { 696 /* 697 * If multicast range, fall back to ALLMULTI. 698 */ 699 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 700 ETHER_ADDR_LEN) != 0) 701 goto allmulti; 702 703 error = vge_cam_set(sc, enm->enm_addrlo); 704 if (error) 705 break; 706 707 ETHER_NEXT_MULTI(step, enm); 708 } 709 710 /* If there were too many addresses, use the hash filter. */ 711 if (error) { 712 vge_cam_clear(sc); 713 714 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 715 while (enm != NULL) { 716 /* 717 * If multicast range, fall back to ALLMULTI. 718 */ 719 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 720 ETHER_ADDR_LEN) != 0) 721 goto allmulti; 722 723 h = ether_crc32_be(enm->enm_addrlo, 724 ETHER_ADDR_LEN) >> 26; 725 hashes[h >> 5] |= 1 << (h & 0x1f); 726 727 ETHER_NEXT_MULTI(step, enm); 728 } 729 730 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 731 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 732 } 733 } 734 735 static void 736 vge_reset(struct vge_softc *sc) 737 { 738 int i; 739 740 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 741 742 for (i = 0; i < VGE_TIMEOUT; i++) { 743 DELAY(5); 744 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 745 break; 746 } 747 748 if (i == VGE_TIMEOUT) { 749 aprint_error("%s: soft reset timed out", sc->sc_dev.dv_xname); 750 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 751 DELAY(2000); 752 } 753 754 DELAY(5000); 755 756 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 757 758 for (i = 0; i < VGE_TIMEOUT; i++) { 759 DELAY(5); 760 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 761 break; 762 } 763 764 if (i == VGE_TIMEOUT) { 765 aprint_error("%s: EEPROM reload timed out\n", 766 sc->sc_dev.dv_xname); 767 return; 768 } 769 770 /* 771 * On some machine, the first read data from EEPROM could be 772 * messed up, so read one dummy data here to avoid the mess. 773 */ 774 (void)vge_read_eeprom(sc, 0); 775 776 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 777 } 778 779 /* 780 * Probe for a VIA gigabit chip. Check the PCI vendor and device 781 * IDs against our list and return a device name if we find a match. 782 */ 783 static int 784 vge_probe(struct device *parent, struct cfdata *match, 785 void *aux) 786 { 787 struct pci_attach_args *pa = aux; 788 789 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 790 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 791 return 1; 792 793 return 0; 794 } 795 796 static int 797 vge_allocmem(struct vge_softc *sc) 798 { 799 int error; 800 int nseg; 801 int i; 802 bus_dma_segment_t seg; 803 804 /* 805 * Allocate memory for control data. 806 */ 807 808 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data), 809 VGE_RING_ALIGN, 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 810 if (error) { 811 aprint_error("%s: could not allocate control data dma memory\n", 812 sc->sc_dev.dv_xname); 813 return ENOMEM; 814 } 815 816 /* Map the memory to kernel VA space */ 817 818 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 819 sizeof(struct vge_control_data), (caddr_t *)&sc->sc_control_data, 820 BUS_DMA_NOWAIT); 821 if (error) { 822 aprint_error("%s: could not map control data dma memory\n", 823 sc->sc_dev.dv_xname); 824 return ENOMEM; 825 } 826 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data)); 827 828 /* 829 * Create map for control data. 830 */ 831 error = bus_dmamap_create(sc->sc_dmat, 832 sizeof(struct vge_control_data), 1, 833 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT, 834 &sc->sc_cddmamap); 835 if (error) { 836 aprint_error("%s: could not create control data dmamap\n", 837 sc->sc_dev.dv_xname); 838 return ENOMEM; 839 } 840 841 /* Load the map for the control data. */ 842 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 843 sc->sc_control_data, sizeof(struct vge_control_data), NULL, 844 BUS_DMA_NOWAIT); 845 if (error) { 846 aprint_error("%s: could not load control data dma memory\n", 847 sc->sc_dev.dv_xname); 848 return ENOMEM; 849 } 850 851 /* Create DMA maps for TX buffers */ 852 853 for (i = 0; i < VGE_NTXDESC; i++) { 854 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN, 855 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT, 856 &sc->sc_txsoft[i].txs_dmamap); 857 if (error) { 858 aprint_error("%s: can't create DMA map for TX descs\n", 859 sc->sc_dev.dv_xname); 860 return ENOMEM; 861 } 862 } 863 864 /* Create DMA maps for RX buffers */ 865 866 for (i = 0; i < VGE_NRXDESC; i++) { 867 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 868 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 869 &sc->sc_rxsoft[i].rxs_dmamap); 870 if (error) { 871 aprint_error("%s: can't create DMA map for RX descs\n", 872 sc->sc_dev.dv_xname); 873 return ENOMEM; 874 } 875 sc->sc_rxsoft[i].rxs_mbuf = NULL; 876 } 877 878 return 0; 879 } 880 881 /* 882 * Attach the interface. Allocate softc structures, do ifmedia 883 * setup and ethernet/BPF attach. 884 */ 885 static void 886 vge_attach(struct device *parent, struct device *self, void *aux) 887 { 888 uint8_t *eaddr; 889 struct vge_softc *sc = (void *)self; 890 struct ifnet *ifp; 891 struct pci_attach_args *pa = aux; 892 pci_chipset_tag_t pc = pa->pa_pc; 893 const char *intrstr; 894 pci_intr_handle_t ih; 895 uint16_t val; 896 897 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 898 PCI_REVISION(pa->pa_class)); 899 900 /* Make sure bus-mastering is enabled */ 901 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 902 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 903 PCI_COMMAND_MASTER_ENABLE); 904 905 /* 906 * Map control/status registers. 907 */ 908 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 909 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) { 910 aprint_error("%s: couldn't map memory\n", sc->sc_dev.dv_xname); 911 return; 912 } 913 914 /* 915 * Map and establish our interrupt. 916 */ 917 if (pci_intr_map(pa, &ih)) { 918 aprint_error("%s: unable to map interrupt\n", 919 sc->sc_dev.dv_xname); 920 return; 921 } 922 intrstr = pci_intr_string(pc, ih); 923 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 924 if (sc->sc_intrhand == NULL) { 925 aprint_error("%s: unable to establish interrupt", 926 sc->sc_dev.dv_xname); 927 if (intrstr != NULL) 928 aprint_error(" at %s", intrstr); 929 aprint_error("\n"); 930 return; 931 } 932 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 933 934 /* Reset the adapter. */ 935 vge_reset(sc); 936 937 /* 938 * Get station address from the EEPROM. 939 */ 940 eaddr = sc->sc_eaddr; 941 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0); 942 eaddr[0] = val & 0xff; 943 eaddr[1] = val >> 8; 944 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1); 945 eaddr[2] = val & 0xff; 946 eaddr[3] = val >> 8; 947 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2); 948 eaddr[4] = val & 0xff; 949 eaddr[5] = val >> 8; 950 951 aprint_normal("%s: Ethernet address: %s\n", sc->sc_dev.dv_xname, 952 ether_sprintf(eaddr)); 953 954 /* 955 * Use the 32bit tag. Hardware supports 48bit physical addresses, 956 * but we don't use that for now. 957 */ 958 sc->sc_dmat = pa->pa_dmat; 959 960 if (vge_allocmem(sc)) 961 return; 962 963 ifp = &sc->sc_ethercom.ec_if; 964 ifp->if_softc = sc; 965 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 966 ifp->if_mtu = ETHERMTU; 967 ifp->if_baudrate = IF_Gbps(1); 968 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 969 ifp->if_ioctl = vge_ioctl; 970 ifp->if_start = vge_start; 971 972 /* 973 * We can support 802.1Q VLAN-sized frames and jumbo 974 * Ethernet frames. 975 */ 976 sc->sc_ethercom.ec_capabilities |= 977 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 978 ETHERCAP_VLAN_HWTAGGING; 979 980 /* 981 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 982 */ 983 ifp->if_capabilities |= 984 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 985 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 986 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 987 988 #ifdef DEVICE_POLLING 989 #ifdef IFCAP_POLLING 990 ifp->if_capabilities |= IFCAP_POLLING; 991 #endif 992 #endif 993 ifp->if_watchdog = vge_watchdog; 994 ifp->if_init = vge_init; 995 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 996 997 /* 998 * Initialize our media structures and probe the MII. 999 */ 1000 sc->sc_mii.mii_ifp = ifp; 1001 sc->sc_mii.mii_readreg = vge_miibus_readreg; 1002 sc->sc_mii.mii_writereg = vge_miibus_writereg; 1003 sc->sc_mii.mii_statchg = vge_miibus_statchg; 1004 ifmedia_init(&sc->sc_mii.mii_media, 0, vge_ifmedia_upd, 1005 vge_ifmedia_sts); 1006 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1007 MII_OFFSET_ANY, MIIF_DOPAUSE); 1008 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1009 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1010 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1011 } else 1012 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1013 1014 /* 1015 * Attach the interface. 1016 */ 1017 if_attach(ifp); 1018 ether_ifattach(ifp, eaddr); 1019 1020 callout_init(&sc->sc_timeout); 1021 callout_setfunc(&sc->sc_timeout, vge_tick, sc); 1022 1023 /* 1024 * Make sure the interface is shutdown during reboot. 1025 */ 1026 if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1027 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1028 sc->sc_dev.dv_xname); 1029 } 1030 } 1031 1032 static int 1033 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 1034 { 1035 struct mbuf *m_new; 1036 struct vge_rxdesc *rxd; 1037 struct vge_rxsoft *rxs; 1038 bus_dmamap_t map; 1039 int i; 1040 1041 m_new = NULL; 1042 if (m == NULL) { 1043 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1044 if (m_new == NULL) 1045 return ENOBUFS; 1046 1047 MCLGET(m_new, M_DONTWAIT); 1048 if ((m_new->m_flags & M_EXT) == 0) { 1049 m_freem(m_new); 1050 return ENOBUFS; 1051 } 1052 1053 m = m_new; 1054 } else 1055 m->m_data = m->m_ext.ext_buf; 1056 1057 1058 #ifndef __NO_STRICT_ALIGNMENT 1059 /* 1060 * This is part of an evil trick to deal with non-x86 platforms. 1061 * The VIA chip requires RX buffers to be aligned on 32-bit 1062 * boundaries, but that will hose non-x86 machines. To get around 1063 * this, we leave some empty space at the start of each buffer 1064 * and for non-x86 hosts, we copy the buffer back two bytes 1065 * to achieve word alignment. This is slightly more efficient 1066 * than allocating a new buffer, copying the contents, and 1067 * discarding the old buffer. 1068 */ 1069 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_RX_PAD; 1070 m->m_data += VGE_RX_PAD; 1071 #else 1072 m->m_len = m->m_pkthdr.len = MCLBYTES; 1073 #endif 1074 rxs = &sc->sc_rxsoft[idx]; 1075 map = rxs->rxs_dmamap; 1076 1077 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) 1078 goto out; 1079 1080 rxd = &sc->sc_rxdescs[idx]; 1081 1082 /* If this descriptor is still owned by the chip, bail. */ 1083 1084 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1085 if (le32toh(rxd->rd_sts) & VGE_RDSTS_OWN) { 1086 aprint_error("%s: tried to map busy RX descriptor\n", 1087 sc->sc_dev.dv_xname); 1088 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1089 goto out; 1090 } 1091 1092 rxs->rxs_mbuf = m; 1093 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1094 BUS_DMASYNC_PREREAD); 1095 1096 rxd->rd_buflen = 1097 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I); 1098 rxd->rd_addrlo = htole32(VGE_ADDR_LO(map->dm_segs[0].ds_addr)); 1099 rxd->rd_addrhi = htole16(VGE_ADDR_HI(map->dm_segs[0].ds_addr) & 0xFFFF); 1100 rxd->rd_sts = 0; 1101 rxd->rd_ctl = 0; 1102 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1103 1104 /* 1105 * Note: the manual fails to document the fact that for 1106 * proper opration, the driver needs to replentish the RX 1107 * DMA ring 4 descriptors at a time (rather than one at a 1108 * time, like most chips). We can allocate the new buffers 1109 * but we should not set the OWN bits until we're ready 1110 * to hand back 4 of them in one shot. 1111 */ 1112 1113 #define VGE_RXCHUNK 4 1114 sc->sc_rx_consumed++; 1115 if (sc->sc_rx_consumed == VGE_RXCHUNK) { 1116 for (i = idx; i != idx - VGE_RXCHUNK; i--) { 1117 KASSERT(i >= 0); 1118 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN); 1119 VGE_RXDESCSYNC(sc, i, 1120 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1121 } 1122 sc->sc_rx_consumed = 0; 1123 } 1124 1125 return 0; 1126 out: 1127 if (m_new != NULL) 1128 m_freem(m_new); 1129 return ENOMEM; 1130 } 1131 1132 #ifndef __NO_STRICT_ALIGNMENT 1133 static inline void 1134 vge_fixup_rx(struct mbuf *m) 1135 { 1136 int i; 1137 uint16_t *src, *dst; 1138 1139 src = mtod(m, uint16_t *); 1140 dst = src - 1; 1141 1142 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1143 *dst++ = *src++; 1144 1145 m->m_data -= ETHER_ALIGN; 1146 } 1147 #endif 1148 1149 /* 1150 * RX handler. We support the reception of jumbo frames that have 1151 * been fragmented across multiple 2K mbuf cluster buffers. 1152 */ 1153 static void 1154 vge_rxeof(struct vge_softc *sc) 1155 { 1156 struct mbuf *m; 1157 struct ifnet *ifp; 1158 int idx, total_len, lim; 1159 struct vge_rxdesc *cur_rxd; 1160 struct vge_rxsoft *rxs; 1161 uint32_t rxstat, rxctl; 1162 1163 ifp = &sc->sc_ethercom.ec_if; 1164 lim = 0; 1165 1166 /* Invalidate the descriptor memory */ 1167 1168 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) { 1169 cur_rxd = &sc->sc_rxdescs[idx]; 1170 1171 VGE_RXDESCSYNC(sc, idx, 1172 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1173 rxstat = le32toh(cur_rxd->rd_sts); 1174 if ((rxstat & VGE_RDSTS_OWN) != 0) { 1175 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1176 break; 1177 } 1178 1179 rxctl = le32toh(cur_rxd->rd_ctl); 1180 rxs = &sc->sc_rxsoft[idx]; 1181 m = rxs->rxs_mbuf; 1182 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16; 1183 1184 /* Invalidate the RX mbuf and unload its map */ 1185 1186 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 1187 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1188 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1189 1190 /* 1191 * If the 'start of frame' bit is set, this indicates 1192 * either the first fragment in a multi-fragment receive, 1193 * or an intermediate fragment. Either way, we want to 1194 * accumulate the buffers. 1195 */ 1196 if (rxstat & VGE_RXPKT_SOF) { 1197 m->m_len = MCLBYTES - VGE_RX_PAD; 1198 if (sc->sc_rx_mhead == NULL) 1199 sc->sc_rx_mhead = sc->sc_rx_mtail = m; 1200 else { 1201 m->m_flags &= ~M_PKTHDR; 1202 sc->sc_rx_mtail->m_next = m; 1203 sc->sc_rx_mtail = m; 1204 } 1205 vge_newbuf(sc, idx, NULL); 1206 continue; 1207 } 1208 1209 /* 1210 * Bad/error frames will have the RXOK bit cleared. 1211 * However, there's one error case we want to allow: 1212 * if a VLAN tagged frame arrives and the chip can't 1213 * match it against the CAM filter, it considers this 1214 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1215 * We don't want to drop the frame though: our VLAN 1216 * filtering is done in software. 1217 */ 1218 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1219 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1220 ifp->if_ierrors++; 1221 /* 1222 * If this is part of a multi-fragment packet, 1223 * discard all the pieces. 1224 */ 1225 if (sc->sc_rx_mhead != NULL) { 1226 m_freem(sc->sc_rx_mhead); 1227 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1228 } 1229 vge_newbuf(sc, idx, m); 1230 continue; 1231 } 1232 1233 /* 1234 * If allocating a replacement mbuf fails, 1235 * reload the current one. 1236 */ 1237 1238 if (vge_newbuf(sc, idx, NULL)) { 1239 ifp->if_ierrors++; 1240 if (sc->sc_rx_mhead != NULL) { 1241 m_freem(sc->sc_rx_mhead); 1242 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1243 } 1244 vge_newbuf(sc, idx, m); 1245 continue; 1246 } 1247 1248 if (sc->sc_rx_mhead != NULL) { 1249 m->m_len = total_len % (MCLBYTES - VGE_RX_PAD); 1250 /* 1251 * Special case: if there's 4 bytes or less 1252 * in this buffer, the mbuf can be discarded: 1253 * the last 4 bytes is the CRC, which we don't 1254 * care about anyway. 1255 */ 1256 if (m->m_len <= ETHER_CRC_LEN) { 1257 sc->sc_rx_mtail->m_len -= 1258 (ETHER_CRC_LEN - m->m_len); 1259 m_freem(m); 1260 } else { 1261 m->m_len -= ETHER_CRC_LEN; 1262 m->m_flags &= ~M_PKTHDR; 1263 sc->sc_rx_mtail->m_next = m; 1264 } 1265 m = sc->sc_rx_mhead; 1266 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1267 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1268 } else 1269 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1270 1271 #ifndef __NO_STRICT_ALIGNMENT 1272 vge_fixup_rx(m); 1273 #endif 1274 ifp->if_ipackets++; 1275 m->m_pkthdr.rcvif = ifp; 1276 1277 /* Do RX checksumming if enabled */ 1278 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1279 1280 /* Check IP header checksum */ 1281 if (rxctl & VGE_RDCTL_IPPKT) 1282 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1283 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1284 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1285 } 1286 1287 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1288 /* Check UDP checksum */ 1289 if (rxctl & VGE_RDCTL_TCPPKT) 1290 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1291 1292 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1293 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1294 } 1295 1296 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1297 /* Check UDP checksum */ 1298 if (rxctl & VGE_RDCTL_UDPPKT) 1299 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1300 1301 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1302 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1303 } 1304 1305 if (rxstat & VGE_RDSTS_VTAG) { 1306 /* 1307 * We use bswap16() here because: 1308 * On LE machines, tag is stored in BE as stream data. 1309 * On BE machines, tag is stored in BE as stream data 1310 * but it was already swapped by le32toh() above. 1311 */ 1312 VLAN_INPUT_TAG(ifp, m, 1313 bswap16(rxctl & VGE_RDCTL_VLANID), continue); 1314 } 1315 1316 #if NBPFILTER > 0 1317 /* 1318 * Handle BPF listeners. 1319 */ 1320 if (ifp->if_bpf) 1321 bpf_mtap(ifp->if_bpf, m); 1322 #endif 1323 1324 (*ifp->if_input)(ifp, m); 1325 1326 lim++; 1327 if (lim == VGE_NRXDESC) 1328 break; 1329 1330 } 1331 1332 sc->sc_rx_prodidx = idx; 1333 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1334 } 1335 1336 static void 1337 vge_txeof(struct vge_softc *sc) 1338 { 1339 struct ifnet *ifp; 1340 struct vge_txsoft *txs; 1341 uint32_t txstat; 1342 int idx; 1343 1344 ifp = &sc->sc_ethercom.ec_if; 1345 idx = sc->sc_tx_considx; 1346 1347 for (idx = sc->sc_tx_considx; 1348 idx != sc->sc_tx_prodidx; 1349 idx = VGE_NEXT_TXDESC(idx)) { 1350 VGE_TXDESCSYNC(sc, idx, 1351 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1352 txstat = le32toh(sc->sc_txdescs[idx].td_sts); 1353 if (txstat & VGE_TDSTS_OWN) { 1354 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1355 break; 1356 } 1357 1358 txs = &sc->sc_txsoft[idx]; 1359 m_freem(txs->txs_mbuf); 1360 txs->txs_mbuf = NULL; 1361 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0, 1362 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1363 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1364 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1365 ifp->if_collisions++; 1366 if (txstat & VGE_TDSTS_TXERR) 1367 ifp->if_oerrors++; 1368 else 1369 ifp->if_opackets++; 1370 1371 sc->sc_tx_free++; 1372 } 1373 1374 /* No changes made to the TX ring, so no flush needed */ 1375 1376 if (idx != sc->sc_tx_considx) { 1377 sc->sc_tx_considx = idx; 1378 ifp->if_flags &= ~IFF_OACTIVE; 1379 } 1380 1381 /* 1382 * If not all descriptors have been released reaped yet, 1383 * reload the timer so that we will eventually get another 1384 * interrupt that will cause us to re-enter this routine. 1385 * This is done in case the transmitter has gone idle. 1386 */ 1387 if (sc->sc_tx_free != VGE_NTXDESC) 1388 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1389 else 1390 ifp->if_timer = 0; 1391 } 1392 1393 static void 1394 vge_tick(void *xsc) 1395 { 1396 struct vge_softc *sc; 1397 struct ifnet *ifp; 1398 struct mii_data *mii; 1399 int s; 1400 1401 sc = xsc; 1402 ifp = &sc->sc_ethercom.ec_if; 1403 mii = &sc->sc_mii; 1404 1405 s = splnet(); 1406 1407 callout_schedule(&sc->sc_timeout, hz); 1408 1409 mii_tick(mii); 1410 if (sc->sc_link) { 1411 if (!(mii->mii_media_status & IFM_ACTIVE)) 1412 sc->sc_link = 0; 1413 } else { 1414 if (mii->mii_media_status & IFM_ACTIVE && 1415 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1416 sc->sc_link = 1; 1417 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1418 vge_start(ifp); 1419 } 1420 } 1421 1422 splx(s); 1423 } 1424 1425 static int 1426 vge_intr(void *arg) 1427 { 1428 struct vge_softc *sc; 1429 struct ifnet *ifp; 1430 uint32_t status; 1431 int claim; 1432 1433 sc = arg; 1434 claim = 0; 1435 if (sc->sc_suspended) { 1436 return claim; 1437 } 1438 1439 ifp = &sc->sc_ethercom.ec_if; 1440 1441 if (!(ifp->if_flags & IFF_UP)) { 1442 return claim; 1443 } 1444 1445 /* Disable interrupts */ 1446 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1447 1448 for (;;) { 1449 1450 status = CSR_READ_4(sc, VGE_ISR); 1451 /* If the card has gone away the read returns 0xffff. */ 1452 if (status == 0xFFFFFFFF) 1453 break; 1454 1455 if (status) { 1456 claim = 1; 1457 CSR_WRITE_4(sc, VGE_ISR, status); 1458 } 1459 1460 if ((status & VGE_INTRS) == 0) 1461 break; 1462 1463 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1464 vge_rxeof(sc); 1465 1466 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1467 vge_rxeof(sc); 1468 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1469 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1470 } 1471 1472 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1473 vge_txeof(sc); 1474 1475 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1476 vge_init(ifp); 1477 1478 if (status & VGE_ISR_LINKSTS) 1479 vge_tick(sc); 1480 } 1481 1482 /* Re-enable interrupts */ 1483 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1484 1485 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1486 vge_start(ifp); 1487 1488 return claim; 1489 } 1490 1491 static int 1492 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1493 { 1494 struct vge_txsoft *txs; 1495 struct vge_txdesc *txd; 1496 struct vge_txfrag *f; 1497 struct mbuf *m_new; 1498 bus_dmamap_t map; 1499 int m_csumflags, seg, error, flags; 1500 struct m_tag *mtag; 1501 size_t sz; 1502 1503 KASSERT(sc->sc_tx_free > 0); 1504 1505 txd = &sc->sc_txdescs[idx]; 1506 1507 #ifdef DIAGNOSTIC 1508 /* If this descriptor is still owned by the chip, bail. */ 1509 VGE_TXDESCSYNC(sc, idx, 1510 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1511 if (le32toh(txd->td_sts) & VGE_TDSTS_OWN) { 1512 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1513 return ENOBUFS; 1514 } 1515 #endif 1516 1517 /* 1518 * Preserve m_pkthdr.csum_flags here since m_head might be 1519 * updated by m_defrag() 1520 */ 1521 m_csumflags = m_head->m_pkthdr.csum_flags; 1522 1523 txs = &sc->sc_txsoft[idx]; 1524 map = txs->txs_dmamap; 1525 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT); 1526 1527 /* If too many segments to map, coalesce */ 1528 if (error == EFBIG || 1529 (m_head->m_pkthdr.len < ETHER_PAD_LEN && 1530 map->dm_nsegs == VGE_TX_FRAGS)) { 1531 m_new = m_defrag(m_head, M_DONTWAIT); 1532 if (m_new == NULL) 1533 return EFBIG; 1534 1535 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1536 m_new, BUS_DMA_NOWAIT); 1537 if (error) { 1538 m_freem(m_new); 1539 return error; 1540 } 1541 1542 m_head = m_new; 1543 } else if (error) 1544 return error; 1545 1546 txs->txs_mbuf = m_head; 1547 1548 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1549 BUS_DMASYNC_PREWRITE); 1550 1551 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) { 1552 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len)); 1553 f->tf_addrlo = htole32(VGE_ADDR_LO(map->dm_segs[seg].ds_addr)); 1554 f->tf_addrhi = htole16(VGE_ADDR_HI(map->dm_segs[seg].ds_addr)); 1555 } 1556 1557 /* Argh. This chip does not autopad short frames */ 1558 sz = m_head->m_pkthdr.len; 1559 if (sz < ETHER_PAD_LEN) { 1560 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz)); 1561 f->tf_addrlo = htole32(VGE_ADDR_LO(VGE_CDPADADDR(sc))); 1562 f->tf_addrhi = htole16(VGE_ADDR_HI(VGE_CDPADADDR(sc)) & 0xFFFF); 1563 sz = ETHER_PAD_LEN; 1564 seg++; 1565 } 1566 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE); 1567 1568 /* 1569 * When telling the chip how many segments there are, we 1570 * must use nsegs + 1 instead of just nsegs. Darned if I 1571 * know why. 1572 */ 1573 seg++; 1574 1575 flags = 0; 1576 if (m_csumflags & M_CSUM_IPv4) 1577 flags |= VGE_TDCTL_IPCSUM; 1578 if (m_csumflags & M_CSUM_TCPv4) 1579 flags |= VGE_TDCTL_TCPCSUM; 1580 if (m_csumflags & M_CSUM_UDPv4) 1581 flags |= VGE_TDCTL_UDPCSUM; 1582 txd->td_sts = htole32(sz << 16); 1583 txd->td_ctl = htole32(flags | (seg << 28) | VGE_TD_LS_NORM); 1584 1585 if (sz > ETHERMTU + ETHER_HDR_LEN) 1586 txd->td_ctl |= htole32(VGE_TDCTL_JUMBO); 1587 1588 /* 1589 * Set up hardware VLAN tagging. 1590 */ 1591 1592 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1593 if (mtag != NULL) { 1594 /* 1595 * No need htons() here since vge(4) chip assumes 1596 * that tags are written in little endian and 1597 * we already use htole32() here. 1598 */ 1599 txd->td_ctl |= htole32(VLAN_TAG_VALUE(mtag) | VGE_TDCTL_VTAG); 1600 } 1601 1602 txd->td_sts |= htole32(VGE_TDSTS_OWN); 1603 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1604 1605 sc->sc_tx_free--; 1606 1607 return 0; 1608 } 1609 1610 /* 1611 * Main transmit routine. 1612 */ 1613 1614 static void 1615 vge_start(struct ifnet *ifp) 1616 { 1617 struct vge_softc *sc; 1618 struct vge_txsoft *txs; 1619 struct mbuf *m_head; 1620 int idx, pidx, error; 1621 1622 sc = ifp->if_softc; 1623 1624 if (!sc->sc_link || 1625 (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1626 return; 1627 } 1628 1629 m_head = NULL; 1630 idx = sc->sc_tx_prodidx; 1631 1632 pidx = (idx - 1) & VGE_NTXDESC_MASK; 1633 1634 /* 1635 * Loop through the send queue, setting up transmit descriptors 1636 * until we drain the queue, or use up all available transmit 1637 * descriptors. 1638 */ 1639 for (;;) { 1640 /* Grab a packet off the queue. */ 1641 IFQ_POLL(&ifp->if_snd, m_head); 1642 if (m_head == NULL) 1643 break; 1644 1645 txs = &sc->sc_txsoft[idx]; 1646 1647 if (txs->txs_mbuf != NULL) { 1648 /* 1649 * Slot already used, stop for now. 1650 */ 1651 ifp->if_flags |= IFF_OACTIVE; 1652 break; 1653 } 1654 1655 if ((error = vge_encap(sc, m_head, idx))) { 1656 if (error == EFBIG) { 1657 aprint_error("%s: Tx packet consumes too many " 1658 "DMA segments, dropping...\n", 1659 sc->sc_dev.dv_xname); 1660 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1661 m_freem(m_head); 1662 continue; 1663 } 1664 1665 /* 1666 * Short on resources, just stop for now. 1667 */ 1668 if (error == ENOBUFS) 1669 ifp->if_flags |= IFF_OACTIVE; 1670 break; 1671 } 1672 1673 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1674 1675 /* 1676 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1677 */ 1678 1679 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |= 1680 htole16(VGE_TXDESC_Q); 1681 VGE_TXFRAGSYNC(sc, pidx, 1, 1682 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1683 1684 if (txs->txs_mbuf != m_head) { 1685 m_freem(m_head); 1686 m_head = txs->txs_mbuf; 1687 } 1688 1689 pidx = idx; 1690 idx = VGE_NEXT_TXDESC(idx); 1691 1692 /* 1693 * If there's a BPF listener, bounce a copy of this frame 1694 * to him. 1695 */ 1696 #if NBPFILTER > 0 1697 if (ifp->if_bpf) 1698 bpf_mtap(ifp->if_bpf, m_head); 1699 #endif 1700 } 1701 1702 if (idx == sc->sc_tx_prodidx) { 1703 return; 1704 } 1705 1706 /* Issue a transmit command. */ 1707 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1708 1709 sc->sc_tx_prodidx = idx; 1710 1711 /* 1712 * Use the countdown timer for interrupt moderation. 1713 * 'TX done' interrupts are disabled. Instead, we reset the 1714 * countdown timer, which will begin counting until it hits 1715 * the value in the SSTIMER register, and then trigger an 1716 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1717 * the timer count is reloaded. Only when the transmitter 1718 * is idle will the timer hit 0 and an interrupt fire. 1719 */ 1720 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1721 1722 /* 1723 * Set a timeout in case the chip goes out to lunch. 1724 */ 1725 ifp->if_timer = 5; 1726 } 1727 1728 static int 1729 vge_init(struct ifnet *ifp) 1730 { 1731 struct vge_softc *sc; 1732 struct vge_rxsoft *rxs; 1733 int i; 1734 1735 sc = ifp->if_softc; 1736 1737 /* 1738 * Cancel pending I/O and free all RX/TX buffers. 1739 */ 1740 vge_stop(sc); 1741 vge_reset(sc); 1742 1743 /* Initialize the RX descriptors and mbufs. */ 1744 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 1745 for (i = 0; i < VGE_NRXDESC; i++) { 1746 rxs = &sc->sc_rxsoft[i]; 1747 if (rxs->rxs_mbuf) { 1748 m_freem(rxs->rxs_mbuf); 1749 rxs->rxs_mbuf = NULL; 1750 } 1751 if (rxs->rxs_dmamap) 1752 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1753 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1754 aprint_error("%s: unable to allocate or map " 1755 "rx buffer\n", sc->sc_dev.dv_xname); 1756 return 1; /* XXX */ 1757 } 1758 } 1759 sc->sc_rx_prodidx = 0; 1760 sc->sc_rx_consumed = 0; 1761 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1762 1763 /* Initialize the TX descriptors and mbufs. */ 1764 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1765 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 1766 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs), 1767 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1768 for (i = 0; i < VGE_NTXDESC; i++) 1769 sc->sc_txsoft[i].txs_mbuf = NULL; 1770 1771 sc->sc_tx_prodidx = 0; 1772 sc->sc_tx_considx = 0; 1773 sc->sc_tx_free = VGE_NTXDESC; 1774 1775 /* Set our station address */ 1776 for (i = 0; i < ETHER_ADDR_LEN; i++) 1777 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]); 1778 1779 /* 1780 * Set receive FIFO threshold. Also allow transmission and 1781 * reception of VLAN tagged frames. 1782 */ 1783 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1784 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1785 1786 /* Set DMA burst length */ 1787 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1788 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1789 1790 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1791 1792 /* Set collision backoff algorithm */ 1793 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1794 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1795 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1796 1797 /* Disable LPSEL field in priority resolution */ 1798 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1799 1800 /* 1801 * Load the addresses of the DMA queues into the chip. 1802 * Note that we only use one transmit queue. 1803 */ 1804 1805 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0))); 1806 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1); 1807 1808 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0))); 1809 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1); 1810 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC); 1811 1812 /* Enable and wake up the RX descriptor queue */ 1813 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1814 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1815 1816 /* Enable the TX descriptor queue */ 1817 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1818 1819 /* Set up the receive filter -- allow large frames for VLANs. */ 1820 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1821 1822 /* If we want promiscuous mode, set the allframes bit. */ 1823 if (ifp->if_flags & IFF_PROMISC) { 1824 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1825 } 1826 1827 /* Set capture broadcast bit to capture broadcast frames. */ 1828 if (ifp->if_flags & IFF_BROADCAST) { 1829 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1830 } 1831 1832 /* Set multicast bit to capture multicast frames. */ 1833 if (ifp->if_flags & IFF_MULTICAST) { 1834 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1835 } 1836 1837 /* Init the cam filter. */ 1838 vge_cam_clear(sc); 1839 1840 /* Init the multicast filter. */ 1841 vge_setmulti(sc); 1842 1843 /* Enable flow control */ 1844 1845 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1846 1847 /* Enable jumbo frame reception (if desired) */ 1848 1849 /* Start the MAC. */ 1850 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1851 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1852 CSR_WRITE_1(sc, VGE_CRS0, 1853 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1854 1855 /* 1856 * Configure one-shot timer for microsecond 1857 * resulution and load it for 500 usecs. 1858 */ 1859 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1860 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1861 1862 /* 1863 * Configure interrupt moderation for receive. Enable 1864 * the holdoff counter and load it, and set the RX 1865 * suppression count to the number of descriptors we 1866 * want to allow before triggering an interrupt. 1867 * The holdoff timer is in units of 20 usecs. 1868 */ 1869 1870 #ifdef notyet 1871 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1872 /* Select the interrupt holdoff timer page. */ 1873 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1874 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1875 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1876 1877 /* Enable use of the holdoff timer. */ 1878 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1879 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1880 1881 /* Select the RX suppression threshold page. */ 1882 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1883 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1884 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1885 1886 /* Restore the page select bits. */ 1887 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1888 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1889 #endif 1890 1891 #ifdef DEVICE_POLLING 1892 /* 1893 * Disable interrupts if we are polling. 1894 */ 1895 if (ifp->if_flags & IFF_POLLING) { 1896 CSR_WRITE_4(sc, VGE_IMR, 0); 1897 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1898 } else /* otherwise ... */ 1899 #endif /* DEVICE_POLLING */ 1900 { 1901 /* 1902 * Enable interrupts. 1903 */ 1904 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1905 CSR_WRITE_4(sc, VGE_ISR, 0); 1906 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1907 } 1908 1909 mii_mediachg(&sc->sc_mii); 1910 1911 ifp->if_flags |= IFF_RUNNING; 1912 ifp->if_flags &= ~IFF_OACTIVE; 1913 1914 sc->sc_if_flags = 0; 1915 sc->sc_link = 0; 1916 1917 callout_schedule(&sc->sc_timeout, hz); 1918 1919 return 0; 1920 } 1921 1922 /* 1923 * Set media options. 1924 */ 1925 static int 1926 vge_ifmedia_upd(struct ifnet *ifp) 1927 { 1928 struct vge_softc *sc; 1929 1930 sc = ifp->if_softc; 1931 mii_mediachg(&sc->sc_mii); 1932 1933 return 0; 1934 } 1935 1936 /* 1937 * Report current media status. 1938 */ 1939 static void 1940 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1941 { 1942 struct vge_softc *sc; 1943 struct mii_data *mii; 1944 1945 sc = ifp->if_softc; 1946 mii = &sc->sc_mii; 1947 1948 mii_pollstat(mii); 1949 ifmr->ifm_active = mii->mii_media_active; 1950 ifmr->ifm_status = mii->mii_media_status; 1951 } 1952 1953 static void 1954 vge_miibus_statchg(struct device *self) 1955 { 1956 struct vge_softc *sc; 1957 struct mii_data *mii; 1958 struct ifmedia_entry *ife; 1959 1960 sc = (void *)self; 1961 mii = &sc->sc_mii; 1962 ife = mii->mii_media.ifm_cur; 1963 /* 1964 * If the user manually selects a media mode, we need to turn 1965 * on the forced MAC mode bit in the DIAGCTL register. If the 1966 * user happens to choose a full duplex mode, we also need to 1967 * set the 'force full duplex' bit. This applies only to 1968 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1969 * mode is disabled, and in 1000baseT mode, full duplex is 1970 * always implied, so we turn on the forced mode bit but leave 1971 * the FDX bit cleared. 1972 */ 1973 1974 switch (IFM_SUBTYPE(ife->ifm_media)) { 1975 case IFM_AUTO: 1976 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1977 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1978 break; 1979 case IFM_1000_T: 1980 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1981 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1982 break; 1983 case IFM_100_TX: 1984 case IFM_10_T: 1985 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1986 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1987 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1988 } else { 1989 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1990 } 1991 break; 1992 default: 1993 aprint_error("%s: unknown media type: %x\n", 1994 sc->sc_dev.dv_xname, 1995 IFM_SUBTYPE(ife->ifm_media)); 1996 break; 1997 } 1998 } 1999 2000 static int 2001 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2002 { 2003 struct vge_softc *sc; 2004 struct ifreq *ifr; 2005 struct mii_data *mii; 2006 int s, error; 2007 2008 sc = ifp->if_softc; 2009 ifr = (struct ifreq *)data; 2010 error = 0; 2011 2012 s = splnet(); 2013 2014 switch (command) { 2015 case SIOCSIFMTU: 2016 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2017 error = EINVAL; 2018 ifp->if_mtu = ifr->ifr_mtu; 2019 break; 2020 case SIOCSIFFLAGS: 2021 if (ifp->if_flags & IFF_UP) { 2022 if (ifp->if_flags & IFF_RUNNING && 2023 ifp->if_flags & IFF_PROMISC && 2024 !(sc->sc_if_flags & IFF_PROMISC)) { 2025 CSR_SETBIT_1(sc, VGE_RXCTL, 2026 VGE_RXCTL_RX_PROMISC); 2027 vge_setmulti(sc); 2028 } else if (ifp->if_flags & IFF_RUNNING && 2029 !(ifp->if_flags & IFF_PROMISC) && 2030 sc->sc_if_flags & IFF_PROMISC) { 2031 CSR_CLRBIT_1(sc, VGE_RXCTL, 2032 VGE_RXCTL_RX_PROMISC); 2033 vge_setmulti(sc); 2034 } else 2035 vge_init(ifp); 2036 } else { 2037 if (ifp->if_flags & IFF_RUNNING) 2038 vge_stop(sc); 2039 } 2040 sc->sc_if_flags = ifp->if_flags; 2041 break; 2042 case SIOCADDMULTI: 2043 case SIOCDELMULTI: 2044 error = (command == SIOCADDMULTI) ? 2045 ether_addmulti(ifr, &sc->sc_ethercom) : 2046 ether_delmulti(ifr, &sc->sc_ethercom); 2047 2048 if (error == ENETRESET) { 2049 /* 2050 * Multicast list has changed; set the hardware filter 2051 * accordingly. 2052 */ 2053 if (ifp->if_flags & IFF_RUNNING) 2054 vge_setmulti(sc); 2055 error = 0; 2056 } 2057 break; 2058 case SIOCGIFMEDIA: 2059 case SIOCSIFMEDIA: 2060 mii = &sc->sc_mii; 2061 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2062 break; 2063 default: 2064 error = ether_ioctl(ifp, command, data); 2065 break; 2066 } 2067 2068 splx(s); 2069 return error; 2070 } 2071 2072 static void 2073 vge_watchdog(struct ifnet *ifp) 2074 { 2075 struct vge_softc *sc; 2076 int s; 2077 2078 sc = ifp->if_softc; 2079 s = splnet(); 2080 aprint_error("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2081 ifp->if_oerrors++; 2082 2083 vge_txeof(sc); 2084 vge_rxeof(sc); 2085 2086 vge_init(ifp); 2087 2088 splx(s); 2089 } 2090 2091 /* 2092 * Stop the adapter and free any mbufs allocated to the 2093 * RX and TX lists. 2094 */ 2095 static void 2096 vge_stop(struct vge_softc *sc) 2097 { 2098 struct ifnet *ifp; 2099 struct vge_txsoft *txs; 2100 struct vge_rxsoft *rxs; 2101 int i, s; 2102 2103 ifp = &sc->sc_ethercom.ec_if; 2104 2105 s = splnet(); 2106 ifp->if_timer = 0; 2107 2108 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2109 #ifdef DEVICE_POLLING 2110 ether_poll_deregister(ifp); 2111 #endif /* DEVICE_POLLING */ 2112 2113 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2114 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2115 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2116 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2117 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2118 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2119 2120 if (sc->sc_rx_mhead != NULL) { 2121 m_freem(sc->sc_rx_mhead); 2122 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 2123 } 2124 2125 /* Free the TX list buffers. */ 2126 2127 for (i = 0; i < VGE_NTXDESC; i++) { 2128 txs = &sc->sc_txsoft[i]; 2129 if (txs->txs_mbuf != NULL) { 2130 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2131 m_freem(txs->txs_mbuf); 2132 txs->txs_mbuf = NULL; 2133 } 2134 } 2135 2136 /* Free the RX list buffers. */ 2137 2138 for (i = 0; i < VGE_NRXDESC; i++) { 2139 rxs = &sc->sc_rxsoft[i]; 2140 if (rxs->rxs_mbuf != NULL) { 2141 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2142 m_freem(rxs->rxs_mbuf); 2143 rxs->rxs_mbuf = NULL; 2144 } 2145 } 2146 2147 splx(s); 2148 } 2149 2150 #if VGE_POWER_MANAGEMENT 2151 /* 2152 * Device suspend routine. Stop the interface and save some PCI 2153 * settings in case the BIOS doesn't restore them properly on 2154 * resume. 2155 */ 2156 static int 2157 vge_suspend(struct device *dev) 2158 { 2159 struct vge_softc *sc; 2160 int i; 2161 2162 sc = device_get_softc(dev); 2163 2164 vge_stop(sc); 2165 2166 for (i = 0; i < 5; i++) 2167 sc->sc_saved_maps[i] = 2168 pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2169 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2170 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2171 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2172 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2173 2174 sc->suspended = 1; 2175 2176 return 0; 2177 } 2178 2179 /* 2180 * Device resume routine. Restore some PCI settings in case the BIOS 2181 * doesn't, re-enable busmastering, and restart the interface if 2182 * appropriate. 2183 */ 2184 static int 2185 vge_resume(struct device *dev) 2186 { 2187 struct vge_softc *sc; 2188 struct ifnet *ifp; 2189 int i; 2190 2191 sc = (void *)dev; 2192 ifp = &sc->sc_ethercom.ec_if; 2193 2194 /* better way to do this? */ 2195 for (i = 0; i < 5; i++) 2196 pci_write_config(dev, PCIR_MAPS + i * 4, 2197 sc->sc_saved_maps[i], 4); 2198 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4); 2199 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1); 2200 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1); 2201 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1); 2202 2203 /* reenable busmastering */ 2204 pci_enable_busmaster(dev); 2205 pci_enable_io(dev, SYS_RES_MEMORY); 2206 2207 /* reinitialize interface if necessary */ 2208 if (ifp->if_flags & IFF_UP) 2209 vge_init(sc); 2210 2211 sc->suspended = 0; 2212 2213 return 0; 2214 } 2215 #endif 2216 2217 /* 2218 * Stop all chip I/O so that the kernel's probe routines don't 2219 * get confused by errant DMAs when rebooting. 2220 */ 2221 static void 2222 vge_shutdown(void *arg) 2223 { 2224 struct vge_softc *sc; 2225 2226 sc = arg; 2227 vge_stop(sc); 2228 } 2229
Indexes created Mon Sep 29 21:09:56 GMT 2025