if_vge.c revision 1.28
1 /* $NetBSD: if_vge.c,v 1.28 2006/11/26 13:09:32 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.28 2006/11/26 13:09:32 tsutsui Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul (at) windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/if_ether.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <machine/bus.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #include <dev/pci/if_vgereg.h> 116 117 #define VGE_JUMBO_MTU 9000 118 119 #define VGE_IFQ_MAXLEN 64 120 121 #define VGE_RING_ALIGN 256 122 123 #define VGE_NTXDESC 256 124 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1) 125 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK) 126 127 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */ 128 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1) 129 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK) 130 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK) 131 132 #define VGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 133 #define VGE_ADDR_HI(y) ((uint64_t)(y) >> 32) 134 #define VGE_BUFLEN(y) ((y) & 0x7FFF) 135 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 136 137 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */ 138 139 /* 140 * Mbuf adjust factor to force 32-bit alignment of IP header. 141 * Drivers should pad ETHER_ALIGN bytes when setting up a 142 * RX mbuf so the upper layers get the IP header properly aligned 143 * past the 14-byte Ethernet header. 144 * 145 * See also comment in vge_encap(). 146 */ 147 #define ETHER_ALIGN 2 148 149 #ifdef __NO_STRICT_ALIGNMENT 150 #define VGE_RX_BUFSIZE MCLBYTES 151 #else 152 #define VGE_RX_PAD sizeof(uint32_t) 153 #define VGE_RX_BUFSIZE (MCLBYTES - VGE_RX_PAD) 154 #endif 155 156 /* 157 * Control structures are DMA'd to the vge chip. We allocate them in 158 * a single clump that maps to a single DMA segment to make several things 159 * easier. 160 */ 161 struct vge_control_data { 162 /* TX descriptors */ 163 struct vge_txdesc vcd_txdescs[VGE_NTXDESC]; 164 /* RX descriptors */ 165 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC]; 166 /* dummy data for TX padding */ 167 uint8_t vcd_pad[ETHER_PAD_LEN]; 168 }; 169 170 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x) 171 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)]) 172 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)]) 173 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0]) 174 175 /* 176 * Software state for TX jobs. 177 */ 178 struct vge_txsoft { 179 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 180 bus_dmamap_t txs_dmamap; /* our DMA map */ 181 }; 182 183 /* 184 * Software state for RX jobs. 185 */ 186 struct vge_rxsoft { 187 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 188 bus_dmamap_t rxs_dmamap; /* our DMA map */ 189 }; 190 191 192 struct vge_softc { 193 struct device sc_dev; 194 195 bus_space_tag_t sc_bst; /* bus space tag */ 196 bus_space_handle_t sc_bsh; /* bus space handle */ 197 bus_dma_tag_t sc_dmat; 198 199 struct ethercom sc_ethercom; /* interface info */ 200 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 201 202 void *sc_intrhand; 203 struct mii_data sc_mii; 204 uint8_t sc_type; 205 int sc_if_flags; 206 int sc_link; 207 int sc_camidx; 208 struct callout sc_timeout; 209 210 bus_dmamap_t sc_cddmamap; 211 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 212 213 struct vge_txsoft sc_txsoft[VGE_NTXDESC]; 214 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC]; 215 struct vge_control_data *sc_control_data; 216 #define sc_txdescs sc_control_data->vcd_txdescs 217 #define sc_rxdescs sc_control_data->vcd_rxdescs 218 219 int sc_tx_prodidx; 220 int sc_tx_considx; 221 int sc_tx_free; 222 223 struct mbuf *sc_rx_mhead; 224 struct mbuf *sc_rx_mtail; 225 int sc_rx_prodidx; 226 int sc_rx_consumed; 227 228 int sc_suspended; /* 0 = normal 1 = suspended */ 229 uint32_t sc_saved_maps[5]; /* pci data */ 230 uint32_t sc_saved_biosaddr; 231 uint8_t sc_saved_intline; 232 uint8_t sc_saved_cachelnsz; 233 uint8_t sc_saved_lattimer; 234 }; 235 236 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x)) 237 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x)) 238 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF()) 239 240 #define VGE_TXDESCSYNC(sc, idx, ops) \ 241 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \ 242 VGE_CDTXOFF(idx), \ 243 offsetof(struct vge_txdesc, td_frag[0]), \ 244 (ops)) 245 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \ 246 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 247 VGE_CDTXOFF(idx) + \ 248 offsetof(struct vge_txdesc, td_frag[0]), \ 249 sizeof(struct vge_txfrag) * (nsegs), \ 250 (ops)) 251 #define VGE_RXDESCSYNC(sc, idx, ops) \ 252 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 253 VGE_CDRXOFF(idx), \ 254 sizeof(struct vge_rxdesc), \ 255 (ops)) 256 257 /* 258 * register space access macros 259 */ 260 #define CSR_WRITE_4(sc, reg, val) \ 261 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 262 #define CSR_WRITE_2(sc, reg, val) \ 263 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 264 #define CSR_WRITE_1(sc, reg, val) \ 265 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 266 267 #define CSR_READ_4(sc, reg) \ 268 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 269 #define CSR_READ_2(sc, reg) \ 270 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg)) 271 #define CSR_READ_1(sc, reg) \ 272 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 273 274 #define CSR_SETBIT_1(sc, reg, x) \ 275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x)) 276 #define CSR_SETBIT_2(sc, reg, x) \ 277 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x)) 278 #define CSR_SETBIT_4(sc, reg, x) \ 279 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x)) 280 281 #define CSR_CLRBIT_1(sc, reg, x) \ 282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x)) 283 #define CSR_CLRBIT_2(sc, reg, x) \ 284 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x)) 285 #define CSR_CLRBIT_4(sc, reg, x) \ 286 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x)) 287 288 #define VGE_TIMEOUT 10000 289 290 #define VGE_PCI_LOIO 0x10 291 #define VGE_PCI_LOMEM 0x14 292 293 static int vge_probe(struct device *, struct cfdata *, void *); 294 static void vge_attach(struct device *, struct device *, void *); 295 296 static int vge_encap(struct vge_softc *, struct mbuf *, int); 297 298 static int vge_allocmem(struct vge_softc *); 299 static int vge_newbuf(struct vge_softc *, int, struct mbuf *); 300 #ifndef __NO_STRICT_ALIGNMENT 301 static inline void vge_fixup_rx(struct mbuf *); 302 #endif 303 static void vge_rxeof(struct vge_softc *); 304 static void vge_txeof(struct vge_softc *); 305 static int vge_intr(void *); 306 static void vge_tick(void *); 307 static void vge_start(struct ifnet *); 308 static int vge_ioctl(struct ifnet *, u_long, caddr_t); 309 static int vge_init(struct ifnet *); 310 static void vge_stop(struct vge_softc *); 311 static void vge_watchdog(struct ifnet *); 312 #if VGE_POWER_MANAGEMENT 313 static int vge_suspend(struct device *); 314 static int vge_resume(struct device *); 315 #endif 316 static void vge_shutdown(void *); 317 static int vge_ifmedia_upd(struct ifnet *); 318 static void vge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 319 320 static uint16_t vge_read_eeprom(struct vge_softc *, int); 321 322 static void vge_miipoll_start(struct vge_softc *); 323 static void vge_miipoll_stop(struct vge_softc *); 324 static int vge_miibus_readreg(struct device *, int, int); 325 static void vge_miibus_writereg(struct device *, int, int, int); 326 static void vge_miibus_statchg(struct device *); 327 328 static void vge_cam_clear(struct vge_softc *); 329 static int vge_cam_set(struct vge_softc *, uint8_t *); 330 static void vge_setmulti(struct vge_softc *); 331 static void vge_reset(struct vge_softc *); 332 333 CFATTACH_DECL(vge, sizeof(struct vge_softc), 334 vge_probe, vge_attach, NULL, NULL); 335 336 /* 337 * Defragment mbuf chain contents to be as linear as possible. 338 * Returns new mbuf chain on success, NULL on failure. Old mbuf 339 * chain is always freed. 340 * XXX temporary until there would be generic function doing this. 341 */ 342 #define m_defrag vge_m_defrag 343 struct mbuf * vge_m_defrag(struct mbuf *, int); 344 345 struct mbuf * 346 vge_m_defrag(struct mbuf *mold, int flags) 347 { 348 struct mbuf *m0, *mn, *n; 349 size_t sz = mold->m_pkthdr.len; 350 351 #ifdef DIAGNOSTIC 352 if ((mold->m_flags & M_PKTHDR) == 0) 353 panic("m_defrag: not a mbuf chain header"); 354 #endif 355 356 MGETHDR(m0, flags, MT_DATA); 357 if (m0 == NULL) 358 return NULL; 359 m0->m_pkthdr.len = mold->m_pkthdr.len; 360 mn = m0; 361 362 do { 363 if (sz > MHLEN) { 364 MCLGET(mn, M_DONTWAIT); 365 if ((mn->m_flags & M_EXT) == 0) { 366 m_freem(m0); 367 return NULL; 368 } 369 } 370 371 mn->m_len = MIN(sz, MCLBYTES); 372 373 m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 374 mtod(mn, caddr_t)); 375 376 sz -= mn->m_len; 377 378 if (sz > 0) { 379 /* need more mbufs */ 380 MGET(n, M_NOWAIT, MT_DATA); 381 if (n == NULL) { 382 m_freem(m0); 383 return NULL; 384 } 385 386 mn->m_next = n; 387 mn = n; 388 } 389 } while (sz > 0); 390 391 return m0; 392 } 393 394 /* 395 * Read a word of data stored in the EEPROM at address 'addr.' 396 */ 397 static uint16_t 398 vge_read_eeprom(struct vge_softc *sc, int addr) 399 { 400 int i; 401 uint16_t word = 0; 402 403 /* 404 * Enter EEPROM embedded programming mode. In order to 405 * access the EEPROM at all, we first have to set the 406 * EELOAD bit in the CHIPCFG2 register. 407 */ 408 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 409 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 410 411 /* Select the address of the word we want to read */ 412 CSR_WRITE_1(sc, VGE_EEADDR, addr); 413 414 /* Issue read command */ 415 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 416 417 /* Wait for the done bit to be set. */ 418 for (i = 0; i < VGE_TIMEOUT; i++) { 419 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 420 break; 421 } 422 423 if (i == VGE_TIMEOUT) { 424 aprint_error("%s: EEPROM read timed out\n", 425 sc->sc_dev.dv_xname); 426 return 0; 427 } 428 429 /* Read the result */ 430 word = CSR_READ_2(sc, VGE_EERDDAT); 431 432 /* Turn off EEPROM access mode. */ 433 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 434 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 435 436 return word; 437 } 438 439 static void 440 vge_miipoll_stop(struct vge_softc *sc) 441 { 442 int i; 443 444 CSR_WRITE_1(sc, VGE_MIICMD, 0); 445 446 for (i = 0; i < VGE_TIMEOUT; i++) { 447 DELAY(1); 448 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 449 break; 450 } 451 452 if (i == VGE_TIMEOUT) { 453 aprint_error("%s: failed to idle MII autopoll\n", 454 sc->sc_dev.dv_xname); 455 } 456 } 457 458 static void 459 vge_miipoll_start(struct vge_softc *sc) 460 { 461 int i; 462 463 /* First, make sure we're idle. */ 464 465 CSR_WRITE_1(sc, VGE_MIICMD, 0); 466 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 467 468 for (i = 0; i < VGE_TIMEOUT; i++) { 469 DELAY(1); 470 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 471 break; 472 } 473 474 if (i == VGE_TIMEOUT) { 475 aprint_error("%s: failed to idle MII autopoll\n", 476 sc->sc_dev.dv_xname); 477 return; 478 } 479 480 /* Now enable auto poll mode. */ 481 482 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 483 484 /* And make sure it started. */ 485 486 for (i = 0; i < VGE_TIMEOUT; i++) { 487 DELAY(1); 488 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 489 break; 490 } 491 492 if (i == VGE_TIMEOUT) { 493 aprint_error("%s: failed to start MII autopoll\n", 494 sc->sc_dev.dv_xname); 495 } 496 } 497 498 static int 499 vge_miibus_readreg(struct device *dev, int phy, int reg) 500 { 501 struct vge_softc *sc; 502 int i, s; 503 uint16_t rval; 504 505 sc = (void *)dev; 506 rval = 0; 507 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 508 return 0; 509 510 s = splnet(); 511 vge_miipoll_stop(sc); 512 513 /* Specify the register we want to read. */ 514 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 515 516 /* Issue read command. */ 517 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 518 519 /* Wait for the read command bit to self-clear. */ 520 for (i = 0; i < VGE_TIMEOUT; i++) { 521 DELAY(1); 522 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 523 break; 524 } 525 526 if (i == VGE_TIMEOUT) 527 aprint_error("%s: MII read timed out\n", sc->sc_dev.dv_xname); 528 else 529 rval = CSR_READ_2(sc, VGE_MIIDATA); 530 531 vge_miipoll_start(sc); 532 splx(s); 533 534 return rval; 535 } 536 537 static void 538 vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 539 { 540 struct vge_softc *sc; 541 int i, s; 542 543 sc = (void *)dev; 544 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 545 return; 546 547 s = splnet(); 548 vge_miipoll_stop(sc); 549 550 /* Specify the register we want to write. */ 551 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 552 553 /* Specify the data we want to write. */ 554 CSR_WRITE_2(sc, VGE_MIIDATA, data); 555 556 /* Issue write command. */ 557 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 558 559 /* Wait for the write command bit to self-clear. */ 560 for (i = 0; i < VGE_TIMEOUT; i++) { 561 DELAY(1); 562 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 563 break; 564 } 565 566 if (i == VGE_TIMEOUT) { 567 aprint_error("%s: MII write timed out\n", sc->sc_dev.dv_xname); 568 } 569 570 vge_miipoll_start(sc); 571 splx(s); 572 } 573 574 static void 575 vge_cam_clear(struct vge_softc *sc) 576 { 577 int i; 578 579 /* 580 * Turn off all the mask bits. This tells the chip 581 * that none of the entries in the CAM filter are valid. 582 * desired entries will be enabled as we fill the filter in. 583 */ 584 585 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 586 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 587 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 588 for (i = 0; i < 8; i++) 589 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 590 591 /* Clear the VLAN filter too. */ 592 593 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 594 for (i = 0; i < 8; i++) 595 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 596 597 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 598 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 599 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 600 601 sc->sc_camidx = 0; 602 } 603 604 static int 605 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 606 { 607 int i, error; 608 609 error = 0; 610 611 if (sc->sc_camidx == VGE_CAM_MAXADDRS) 612 return ENOSPC; 613 614 /* Select the CAM data page. */ 615 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 616 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 617 618 /* Set the filter entry we want to update and enable writing. */ 619 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx); 620 621 /* Write the address to the CAM registers */ 622 for (i = 0; i < ETHER_ADDR_LEN; i++) 623 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 624 625 /* Issue a write command. */ 626 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 627 628 /* Wake for it to clear. */ 629 for (i = 0; i < VGE_TIMEOUT; i++) { 630 DELAY(1); 631 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 632 break; 633 } 634 635 if (i == VGE_TIMEOUT) { 636 aprint_error("%s: setting CAM filter failed\n", 637 sc->sc_dev.dv_xname); 638 error = EIO; 639 goto fail; 640 } 641 642 /* Select the CAM mask page. */ 643 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 644 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 645 646 /* Set the mask bit that enables this filter. */ 647 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8), 648 1 << (sc->sc_camidx & 7)); 649 650 sc->sc_camidx++; 651 652 fail: 653 /* Turn off access to CAM. */ 654 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 655 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 656 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 657 658 return error; 659 } 660 661 /* 662 * Program the multicast filter. We use the 64-entry CAM filter 663 * for perfect filtering. If there's more than 64 multicast addresses, 664 * we use the hash filter instead. 665 */ 666 static void 667 vge_setmulti(struct vge_softc *sc) 668 { 669 struct ifnet *ifp; 670 int error; 671 uint32_t h, hashes[2] = { 0, 0 }; 672 struct ether_multi *enm; 673 struct ether_multistep step; 674 675 error = 0; 676 ifp = &sc->sc_ethercom.ec_if; 677 678 /* First, zot all the multicast entries. */ 679 vge_cam_clear(sc); 680 CSR_WRITE_4(sc, VGE_MAR0, 0); 681 CSR_WRITE_4(sc, VGE_MAR1, 0); 682 ifp->if_flags &= ~IFF_ALLMULTI; 683 684 /* 685 * If the user wants allmulti or promisc mode, enable reception 686 * of all multicast frames. 687 */ 688 if (ifp->if_flags & IFF_PROMISC) { 689 allmulti: 690 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 691 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 692 ifp->if_flags |= IFF_ALLMULTI; 693 return; 694 } 695 696 /* Now program new ones */ 697 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 698 while (enm != NULL) { 699 /* 700 * If multicast range, fall back to ALLMULTI. 701 */ 702 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 703 ETHER_ADDR_LEN) != 0) 704 goto allmulti; 705 706 error = vge_cam_set(sc, enm->enm_addrlo); 707 if (error) 708 break; 709 710 ETHER_NEXT_MULTI(step, enm); 711 } 712 713 /* If there were too many addresses, use the hash filter. */ 714 if (error) { 715 vge_cam_clear(sc); 716 717 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 718 while (enm != NULL) { 719 /* 720 * If multicast range, fall back to ALLMULTI. 721 */ 722 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 723 ETHER_ADDR_LEN) != 0) 724 goto allmulti; 725 726 h = ether_crc32_be(enm->enm_addrlo, 727 ETHER_ADDR_LEN) >> 26; 728 hashes[h >> 5] |= 1 << (h & 0x1f); 729 730 ETHER_NEXT_MULTI(step, enm); 731 } 732 733 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 734 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 735 } 736 } 737 738 static void 739 vge_reset(struct vge_softc *sc) 740 { 741 int i; 742 743 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 744 745 for (i = 0; i < VGE_TIMEOUT; i++) { 746 DELAY(5); 747 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 748 break; 749 } 750 751 if (i == VGE_TIMEOUT) { 752 aprint_error("%s: soft reset timed out", sc->sc_dev.dv_xname); 753 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 754 DELAY(2000); 755 } 756 757 DELAY(5000); 758 759 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 760 761 for (i = 0; i < VGE_TIMEOUT; i++) { 762 DELAY(5); 763 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 764 break; 765 } 766 767 if (i == VGE_TIMEOUT) { 768 aprint_error("%s: EEPROM reload timed out\n", 769 sc->sc_dev.dv_xname); 770 return; 771 } 772 773 /* 774 * On some machine, the first read data from EEPROM could be 775 * messed up, so read one dummy data here to avoid the mess. 776 */ 777 (void)vge_read_eeprom(sc, 0); 778 779 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 780 } 781 782 /* 783 * Probe for a VIA gigabit chip. Check the PCI vendor and device 784 * IDs against our list and return a device name if we find a match. 785 */ 786 static int 787 vge_probe(struct device *parent, struct cfdata *match, 788 void *aux) 789 { 790 struct pci_attach_args *pa = aux; 791 792 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 793 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 794 return 1; 795 796 return 0; 797 } 798 799 static int 800 vge_allocmem(struct vge_softc *sc) 801 { 802 int error; 803 int nseg; 804 int i; 805 bus_dma_segment_t seg; 806 807 /* 808 * Allocate memory for control data. 809 */ 810 811 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data), 812 VGE_RING_ALIGN, 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 813 if (error) { 814 aprint_error("%s: could not allocate control data dma memory\n", 815 sc->sc_dev.dv_xname); 816 return ENOMEM; 817 } 818 819 /* Map the memory to kernel VA space */ 820 821 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 822 sizeof(struct vge_control_data), (caddr_t *)&sc->sc_control_data, 823 BUS_DMA_NOWAIT); 824 if (error) { 825 aprint_error("%s: could not map control data dma memory\n", 826 sc->sc_dev.dv_xname); 827 return ENOMEM; 828 } 829 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data)); 830 831 /* 832 * Create map for control data. 833 */ 834 error = bus_dmamap_create(sc->sc_dmat, 835 sizeof(struct vge_control_data), 1, 836 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT, 837 &sc->sc_cddmamap); 838 if (error) { 839 aprint_error("%s: could not create control data dmamap\n", 840 sc->sc_dev.dv_xname); 841 return ENOMEM; 842 } 843 844 /* Load the map for the control data. */ 845 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 846 sc->sc_control_data, sizeof(struct vge_control_data), NULL, 847 BUS_DMA_NOWAIT); 848 if (error) { 849 aprint_error("%s: could not load control data dma memory\n", 850 sc->sc_dev.dv_xname); 851 return ENOMEM; 852 } 853 854 /* Create DMA maps for TX buffers */ 855 856 for (i = 0; i < VGE_NTXDESC; i++) { 857 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN, 858 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT, 859 &sc->sc_txsoft[i].txs_dmamap); 860 if (error) { 861 aprint_error("%s: can't create DMA map for TX descs\n", 862 sc->sc_dev.dv_xname); 863 return ENOMEM; 864 } 865 } 866 867 /* Create DMA maps for RX buffers */ 868 869 for (i = 0; i < VGE_NRXDESC; i++) { 870 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 871 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 872 &sc->sc_rxsoft[i].rxs_dmamap); 873 if (error) { 874 aprint_error("%s: can't create DMA map for RX descs\n", 875 sc->sc_dev.dv_xname); 876 return ENOMEM; 877 } 878 sc->sc_rxsoft[i].rxs_mbuf = NULL; 879 } 880 881 return 0; 882 } 883 884 /* 885 * Attach the interface. Allocate softc structures, do ifmedia 886 * setup and ethernet/BPF attach. 887 */ 888 static void 889 vge_attach(struct device *parent, struct device *self, void *aux) 890 { 891 uint8_t *eaddr; 892 struct vge_softc *sc = (void *)self; 893 struct ifnet *ifp; 894 struct pci_attach_args *pa = aux; 895 pci_chipset_tag_t pc = pa->pa_pc; 896 const char *intrstr; 897 pci_intr_handle_t ih; 898 uint16_t val; 899 900 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 901 PCI_REVISION(pa->pa_class)); 902 903 /* Make sure bus-mastering is enabled */ 904 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 905 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 906 PCI_COMMAND_MASTER_ENABLE); 907 908 /* 909 * Map control/status registers. 910 */ 911 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 912 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) { 913 aprint_error("%s: couldn't map memory\n", sc->sc_dev.dv_xname); 914 return; 915 } 916 917 /* 918 * Map and establish our interrupt. 919 */ 920 if (pci_intr_map(pa, &ih)) { 921 aprint_error("%s: unable to map interrupt\n", 922 sc->sc_dev.dv_xname); 923 return; 924 } 925 intrstr = pci_intr_string(pc, ih); 926 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 927 if (sc->sc_intrhand == NULL) { 928 aprint_error("%s: unable to establish interrupt", 929 sc->sc_dev.dv_xname); 930 if (intrstr != NULL) 931 aprint_error(" at %s", intrstr); 932 aprint_error("\n"); 933 return; 934 } 935 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 936 937 /* Reset the adapter. */ 938 vge_reset(sc); 939 940 /* 941 * Get station address from the EEPROM. 942 */ 943 eaddr = sc->sc_eaddr; 944 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0); 945 eaddr[0] = val & 0xff; 946 eaddr[1] = val >> 8; 947 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1); 948 eaddr[2] = val & 0xff; 949 eaddr[3] = val >> 8; 950 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2); 951 eaddr[4] = val & 0xff; 952 eaddr[5] = val >> 8; 953 954 aprint_normal("%s: Ethernet address: %s\n", sc->sc_dev.dv_xname, 955 ether_sprintf(eaddr)); 956 957 /* 958 * Use the 32bit tag. Hardware supports 48bit physical addresses, 959 * but we don't use that for now. 960 */ 961 sc->sc_dmat = pa->pa_dmat; 962 963 if (vge_allocmem(sc)) 964 return; 965 966 ifp = &sc->sc_ethercom.ec_if; 967 ifp->if_softc = sc; 968 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 969 ifp->if_mtu = ETHERMTU; 970 ifp->if_baudrate = IF_Gbps(1); 971 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 972 ifp->if_ioctl = vge_ioctl; 973 ifp->if_start = vge_start; 974 975 /* 976 * We can support 802.1Q VLAN-sized frames and jumbo 977 * Ethernet frames. 978 */ 979 sc->sc_ethercom.ec_capabilities |= 980 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 981 ETHERCAP_VLAN_HWTAGGING; 982 983 /* 984 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 985 */ 986 ifp->if_capabilities |= 987 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 988 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 989 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 990 991 #ifdef DEVICE_POLLING 992 #ifdef IFCAP_POLLING 993 ifp->if_capabilities |= IFCAP_POLLING; 994 #endif 995 #endif 996 ifp->if_watchdog = vge_watchdog; 997 ifp->if_init = vge_init; 998 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 999 1000 /* 1001 * Initialize our media structures and probe the MII. 1002 */ 1003 sc->sc_mii.mii_ifp = ifp; 1004 sc->sc_mii.mii_readreg = vge_miibus_readreg; 1005 sc->sc_mii.mii_writereg = vge_miibus_writereg; 1006 sc->sc_mii.mii_statchg = vge_miibus_statchg; 1007 ifmedia_init(&sc->sc_mii.mii_media, 0, vge_ifmedia_upd, 1008 vge_ifmedia_sts); 1009 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1010 MII_OFFSET_ANY, MIIF_DOPAUSE); 1011 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1012 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1013 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1014 } else 1015 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1016 1017 /* 1018 * Attach the interface. 1019 */ 1020 if_attach(ifp); 1021 ether_ifattach(ifp, eaddr); 1022 1023 callout_init(&sc->sc_timeout); 1024 callout_setfunc(&sc->sc_timeout, vge_tick, sc); 1025 1026 /* 1027 * Make sure the interface is shutdown during reboot. 1028 */ 1029 if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1030 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1031 sc->sc_dev.dv_xname); 1032 } 1033 } 1034 1035 static int 1036 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 1037 { 1038 struct mbuf *m_new; 1039 struct vge_rxdesc *rxd; 1040 struct vge_rxsoft *rxs; 1041 bus_dmamap_t map; 1042 int i; 1043 1044 m_new = NULL; 1045 if (m == NULL) { 1046 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1047 if (m_new == NULL) 1048 return ENOBUFS; 1049 1050 MCLGET(m_new, M_DONTWAIT); 1051 if ((m_new->m_flags & M_EXT) == 0) { 1052 m_freem(m_new); 1053 return ENOBUFS; 1054 } 1055 1056 m = m_new; 1057 } else 1058 m->m_data = m->m_ext.ext_buf; 1059 1060 1061 /* 1062 * This is part of an evil trick to deal with non-x86 platforms. 1063 * The VIA chip requires RX buffers to be aligned on 32-bit 1064 * boundaries, but that will hose non-x86 machines. To get around 1065 * this, we leave some empty space at the start of each buffer 1066 * and for non-x86 hosts, we copy the buffer back two bytes 1067 * to achieve word alignment. This is slightly more efficient 1068 * than allocating a new buffer, copying the contents, and 1069 * discarding the old buffer. 1070 */ 1071 m->m_len = m->m_pkthdr.len = VGE_RX_BUFSIZE; 1072 #ifndef __NO_STRICT_ALIGNMENT 1073 m->m_data += VGE_RX_PAD; 1074 #endif 1075 rxs = &sc->sc_rxsoft[idx]; 1076 map = rxs->rxs_dmamap; 1077 1078 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) 1079 goto out; 1080 1081 rxd = &sc->sc_rxdescs[idx]; 1082 1083 /* If this descriptor is still owned by the chip, bail. */ 1084 1085 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1086 if (le32toh(rxd->rd_sts) & VGE_RDSTS_OWN) { 1087 aprint_error("%s: tried to map busy RX descriptor\n", 1088 sc->sc_dev.dv_xname); 1089 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1090 goto out; 1091 } 1092 1093 rxs->rxs_mbuf = m; 1094 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1095 BUS_DMASYNC_PREREAD); 1096 1097 rxd->rd_buflen = 1098 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I); 1099 rxd->rd_addrlo = htole32(VGE_ADDR_LO(map->dm_segs[0].ds_addr)); 1100 rxd->rd_addrhi = htole16(VGE_ADDR_HI(map->dm_segs[0].ds_addr) & 0xFFFF); 1101 rxd->rd_sts = 0; 1102 rxd->rd_ctl = 0; 1103 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1104 1105 /* 1106 * Note: the manual fails to document the fact that for 1107 * proper opration, the driver needs to replentish the RX 1108 * DMA ring 4 descriptors at a time (rather than one at a 1109 * time, like most chips). We can allocate the new buffers 1110 * but we should not set the OWN bits until we're ready 1111 * to hand back 4 of them in one shot. 1112 */ 1113 1114 #define VGE_RXCHUNK 4 1115 sc->sc_rx_consumed++; 1116 if (sc->sc_rx_consumed == VGE_RXCHUNK) { 1117 for (i = idx; i != idx - VGE_RXCHUNK; i--) { 1118 KASSERT(i >= 0); 1119 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN); 1120 VGE_RXDESCSYNC(sc, i, 1121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1122 } 1123 sc->sc_rx_consumed = 0; 1124 } 1125 1126 return 0; 1127 out: 1128 if (m_new != NULL) 1129 m_freem(m_new); 1130 return ENOMEM; 1131 } 1132 1133 #ifndef __NO_STRICT_ALIGNMENT 1134 static inline void 1135 vge_fixup_rx(struct mbuf *m) 1136 { 1137 int i; 1138 uint16_t *src, *dst; 1139 1140 src = mtod(m, uint16_t *); 1141 dst = src - 1; 1142 1143 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1144 *dst++ = *src++; 1145 1146 m->m_data -= ETHER_ALIGN; 1147 } 1148 #endif 1149 1150 /* 1151 * RX handler. We support the reception of jumbo frames that have 1152 * been fragmented across multiple 2K mbuf cluster buffers. 1153 */ 1154 static void 1155 vge_rxeof(struct vge_softc *sc) 1156 { 1157 struct mbuf *m; 1158 struct ifnet *ifp; 1159 int idx, total_len, lim; 1160 struct vge_rxdesc *cur_rxd; 1161 struct vge_rxsoft *rxs; 1162 uint32_t rxstat, rxctl; 1163 1164 ifp = &sc->sc_ethercom.ec_if; 1165 lim = 0; 1166 1167 /* Invalidate the descriptor memory */ 1168 1169 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) { 1170 cur_rxd = &sc->sc_rxdescs[idx]; 1171 1172 VGE_RXDESCSYNC(sc, idx, 1173 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1174 rxstat = le32toh(cur_rxd->rd_sts); 1175 if ((rxstat & VGE_RDSTS_OWN) != 0) { 1176 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1177 break; 1178 } 1179 1180 rxctl = le32toh(cur_rxd->rd_ctl); 1181 rxs = &sc->sc_rxsoft[idx]; 1182 m = rxs->rxs_mbuf; 1183 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16; 1184 1185 /* Invalidate the RX mbuf and unload its map */ 1186 1187 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 1188 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1189 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1190 1191 /* 1192 * If the 'start of frame' bit is set, this indicates 1193 * either the first fragment in a multi-fragment receive, 1194 * or an intermediate fragment. Either way, we want to 1195 * accumulate the buffers. 1196 */ 1197 if (rxstat & VGE_RXPKT_SOF) { 1198 m->m_len = VGE_RX_BUFSIZE; 1199 if (sc->sc_rx_mhead == NULL) 1200 sc->sc_rx_mhead = sc->sc_rx_mtail = m; 1201 else { 1202 m->m_flags &= ~M_PKTHDR; 1203 sc->sc_rx_mtail->m_next = m; 1204 sc->sc_rx_mtail = m; 1205 } 1206 vge_newbuf(sc, idx, NULL); 1207 continue; 1208 } 1209 1210 /* 1211 * Bad/error frames will have the RXOK bit cleared. 1212 * However, there's one error case we want to allow: 1213 * if a VLAN tagged frame arrives and the chip can't 1214 * match it against the CAM filter, it considers this 1215 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1216 * We don't want to drop the frame though: our VLAN 1217 * filtering is done in software. 1218 */ 1219 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1220 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1221 ifp->if_ierrors++; 1222 /* 1223 * If this is part of a multi-fragment packet, 1224 * discard all the pieces. 1225 */ 1226 if (sc->sc_rx_mhead != NULL) { 1227 m_freem(sc->sc_rx_mhead); 1228 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1229 } 1230 vge_newbuf(sc, idx, m); 1231 continue; 1232 } 1233 1234 /* 1235 * If allocating a replacement mbuf fails, 1236 * reload the current one. 1237 */ 1238 1239 if (vge_newbuf(sc, idx, NULL)) { 1240 ifp->if_ierrors++; 1241 if (sc->sc_rx_mhead != NULL) { 1242 m_freem(sc->sc_rx_mhead); 1243 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1244 } 1245 vge_newbuf(sc, idx, m); 1246 continue; 1247 } 1248 1249 if (sc->sc_rx_mhead != NULL) { 1250 m->m_len = total_len % VGE_RX_BUFSIZE; 1251 /* 1252 * Special case: if there's 4 bytes or less 1253 * in this buffer, the mbuf can be discarded: 1254 * the last 4 bytes is the CRC, which we don't 1255 * care about anyway. 1256 */ 1257 if (m->m_len <= ETHER_CRC_LEN) { 1258 sc->sc_rx_mtail->m_len -= 1259 (ETHER_CRC_LEN - m->m_len); 1260 m_freem(m); 1261 } else { 1262 m->m_len -= ETHER_CRC_LEN; 1263 m->m_flags &= ~M_PKTHDR; 1264 sc->sc_rx_mtail->m_next = m; 1265 } 1266 m = sc->sc_rx_mhead; 1267 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1268 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1269 } else 1270 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1271 1272 #ifndef __NO_STRICT_ALIGNMENT 1273 vge_fixup_rx(m); 1274 #endif 1275 ifp->if_ipackets++; 1276 m->m_pkthdr.rcvif = ifp; 1277 1278 /* Do RX checksumming if enabled */ 1279 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1280 1281 /* Check IP header checksum */ 1282 if (rxctl & VGE_RDCTL_IPPKT) 1283 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1284 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1285 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1286 } 1287 1288 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1289 /* Check UDP checksum */ 1290 if (rxctl & VGE_RDCTL_TCPPKT) 1291 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1292 1293 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1294 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1295 } 1296 1297 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1298 /* Check UDP checksum */ 1299 if (rxctl & VGE_RDCTL_UDPPKT) 1300 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1301 1302 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1303 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1304 } 1305 1306 if (rxstat & VGE_RDSTS_VTAG) { 1307 /* 1308 * We use bswap16() here because: 1309 * On LE machines, tag is stored in BE as stream data. 1310 * On BE machines, tag is stored in BE as stream data 1311 * but it was already swapped by le32toh() above. 1312 */ 1313 VLAN_INPUT_TAG(ifp, m, 1314 bswap16(rxctl & VGE_RDCTL_VLANID), continue); 1315 } 1316 1317 #if NBPFILTER > 0 1318 /* 1319 * Handle BPF listeners. 1320 */ 1321 if (ifp->if_bpf) 1322 bpf_mtap(ifp->if_bpf, m); 1323 #endif 1324 1325 (*ifp->if_input)(ifp, m); 1326 1327 lim++; 1328 if (lim == VGE_NRXDESC) 1329 break; 1330 1331 } 1332 1333 sc->sc_rx_prodidx = idx; 1334 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1335 } 1336 1337 static void 1338 vge_txeof(struct vge_softc *sc) 1339 { 1340 struct ifnet *ifp; 1341 struct vge_txsoft *txs; 1342 uint32_t txstat; 1343 int idx; 1344 1345 ifp = &sc->sc_ethercom.ec_if; 1346 idx = sc->sc_tx_considx; 1347 1348 for (idx = sc->sc_tx_considx; 1349 idx != sc->sc_tx_prodidx; 1350 idx = VGE_NEXT_TXDESC(idx)) { 1351 VGE_TXDESCSYNC(sc, idx, 1352 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1353 txstat = le32toh(sc->sc_txdescs[idx].td_sts); 1354 if (txstat & VGE_TDSTS_OWN) { 1355 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1356 break; 1357 } 1358 1359 txs = &sc->sc_txsoft[idx]; 1360 m_freem(txs->txs_mbuf); 1361 txs->txs_mbuf = NULL; 1362 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0, 1363 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1364 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1365 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1366 ifp->if_collisions++; 1367 if (txstat & VGE_TDSTS_TXERR) 1368 ifp->if_oerrors++; 1369 else 1370 ifp->if_opackets++; 1371 1372 sc->sc_tx_free++; 1373 } 1374 1375 /* No changes made to the TX ring, so no flush needed */ 1376 1377 if (idx != sc->sc_tx_considx) { 1378 sc->sc_tx_considx = idx; 1379 ifp->if_flags &= ~IFF_OACTIVE; 1380 } 1381 1382 /* 1383 * If not all descriptors have been released reaped yet, 1384 * reload the timer so that we will eventually get another 1385 * interrupt that will cause us to re-enter this routine. 1386 * This is done in case the transmitter has gone idle. 1387 */ 1388 if (sc->sc_tx_free != VGE_NTXDESC) 1389 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1390 else 1391 ifp->if_timer = 0; 1392 } 1393 1394 static void 1395 vge_tick(void *xsc) 1396 { 1397 struct vge_softc *sc; 1398 struct ifnet *ifp; 1399 struct mii_data *mii; 1400 int s; 1401 1402 sc = xsc; 1403 ifp = &sc->sc_ethercom.ec_if; 1404 mii = &sc->sc_mii; 1405 1406 s = splnet(); 1407 1408 callout_schedule(&sc->sc_timeout, hz); 1409 1410 mii_tick(mii); 1411 if (sc->sc_link) { 1412 if (!(mii->mii_media_status & IFM_ACTIVE)) 1413 sc->sc_link = 0; 1414 } else { 1415 if (mii->mii_media_status & IFM_ACTIVE && 1416 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1417 sc->sc_link = 1; 1418 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1419 vge_start(ifp); 1420 } 1421 } 1422 1423 splx(s); 1424 } 1425 1426 static int 1427 vge_intr(void *arg) 1428 { 1429 struct vge_softc *sc; 1430 struct ifnet *ifp; 1431 uint32_t status; 1432 int claim; 1433 1434 sc = arg; 1435 claim = 0; 1436 if (sc->sc_suspended) { 1437 return claim; 1438 } 1439 1440 ifp = &sc->sc_ethercom.ec_if; 1441 1442 if (!(ifp->if_flags & IFF_UP)) { 1443 return claim; 1444 } 1445 1446 /* Disable interrupts */ 1447 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1448 1449 for (;;) { 1450 1451 status = CSR_READ_4(sc, VGE_ISR); 1452 /* If the card has gone away the read returns 0xffff. */ 1453 if (status == 0xFFFFFFFF) 1454 break; 1455 1456 if (status) { 1457 claim = 1; 1458 CSR_WRITE_4(sc, VGE_ISR, status); 1459 } 1460 1461 if ((status & VGE_INTRS) == 0) 1462 break; 1463 1464 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1465 vge_rxeof(sc); 1466 1467 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1468 vge_rxeof(sc); 1469 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1470 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1471 } 1472 1473 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1474 vge_txeof(sc); 1475 1476 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1477 vge_init(ifp); 1478 1479 if (status & VGE_ISR_LINKSTS) 1480 vge_tick(sc); 1481 } 1482 1483 /* Re-enable interrupts */ 1484 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1485 1486 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1487 vge_start(ifp); 1488 1489 return claim; 1490 } 1491 1492 static int 1493 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1494 { 1495 struct vge_txsoft *txs; 1496 struct vge_txdesc *txd; 1497 struct vge_txfrag *f; 1498 struct mbuf *m_new; 1499 bus_dmamap_t map; 1500 int m_csumflags, seg, error, flags; 1501 struct m_tag *mtag; 1502 size_t sz; 1503 1504 KASSERT(sc->sc_tx_free > 0); 1505 1506 txd = &sc->sc_txdescs[idx]; 1507 1508 #ifdef DIAGNOSTIC 1509 /* If this descriptor is still owned by the chip, bail. */ 1510 VGE_TXDESCSYNC(sc, idx, 1511 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1512 if (le32toh(txd->td_sts) & VGE_TDSTS_OWN) { 1513 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1514 return ENOBUFS; 1515 } 1516 #endif 1517 1518 /* 1519 * Preserve m_pkthdr.csum_flags here since m_head might be 1520 * updated by m_defrag() 1521 */ 1522 m_csumflags = m_head->m_pkthdr.csum_flags; 1523 1524 txs = &sc->sc_txsoft[idx]; 1525 map = txs->txs_dmamap; 1526 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT); 1527 1528 /* If too many segments to map, coalesce */ 1529 if (error == EFBIG || 1530 (m_head->m_pkthdr.len < ETHER_PAD_LEN && 1531 map->dm_nsegs == VGE_TX_FRAGS)) { 1532 m_new = m_defrag(m_head, M_DONTWAIT); 1533 if (m_new == NULL) 1534 return EFBIG; 1535 1536 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1537 m_new, BUS_DMA_NOWAIT); 1538 if (error) { 1539 m_freem(m_new); 1540 return error; 1541 } 1542 1543 m_head = m_new; 1544 } else if (error) 1545 return error; 1546 1547 txs->txs_mbuf = m_head; 1548 1549 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1550 BUS_DMASYNC_PREWRITE); 1551 1552 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) { 1553 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len)); 1554 f->tf_addrlo = htole32(VGE_ADDR_LO(map->dm_segs[seg].ds_addr)); 1555 f->tf_addrhi = htole16(VGE_ADDR_HI(map->dm_segs[seg].ds_addr)); 1556 } 1557 1558 /* Argh. This chip does not autopad short frames */ 1559 sz = m_head->m_pkthdr.len; 1560 if (sz < ETHER_PAD_LEN) { 1561 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz)); 1562 f->tf_addrlo = htole32(VGE_ADDR_LO(VGE_CDPADADDR(sc))); 1563 f->tf_addrhi = htole16(VGE_ADDR_HI(VGE_CDPADADDR(sc)) & 0xFFFF); 1564 sz = ETHER_PAD_LEN; 1565 seg++; 1566 } 1567 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE); 1568 1569 /* 1570 * When telling the chip how many segments there are, we 1571 * must use nsegs + 1 instead of just nsegs. Darned if I 1572 * know why. 1573 */ 1574 seg++; 1575 1576 flags = 0; 1577 if (m_csumflags & M_CSUM_IPv4) 1578 flags |= VGE_TDCTL_IPCSUM; 1579 if (m_csumflags & M_CSUM_TCPv4) 1580 flags |= VGE_TDCTL_TCPCSUM; 1581 if (m_csumflags & M_CSUM_UDPv4) 1582 flags |= VGE_TDCTL_UDPCSUM; 1583 txd->td_sts = htole32(sz << 16); 1584 txd->td_ctl = htole32(flags | (seg << 28) | VGE_TD_LS_NORM); 1585 1586 if (sz > ETHERMTU + ETHER_HDR_LEN) 1587 txd->td_ctl |= htole32(VGE_TDCTL_JUMBO); 1588 1589 /* 1590 * Set up hardware VLAN tagging. 1591 */ 1592 1593 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1594 if (mtag != NULL) { 1595 /* 1596 * No need htons() here since vge(4) chip assumes 1597 * that tags are written in little endian and 1598 * we already use htole32() here. 1599 */ 1600 txd->td_ctl |= htole32(VLAN_TAG_VALUE(mtag) | VGE_TDCTL_VTAG); 1601 } 1602 1603 txd->td_sts |= htole32(VGE_TDSTS_OWN); 1604 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1605 1606 sc->sc_tx_free--; 1607 1608 return 0; 1609 } 1610 1611 /* 1612 * Main transmit routine. 1613 */ 1614 1615 static void 1616 vge_start(struct ifnet *ifp) 1617 { 1618 struct vge_softc *sc; 1619 struct vge_txsoft *txs; 1620 struct mbuf *m_head; 1621 int idx, pidx, error; 1622 1623 sc = ifp->if_softc; 1624 1625 if (!sc->sc_link || 1626 (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1627 return; 1628 } 1629 1630 m_head = NULL; 1631 idx = sc->sc_tx_prodidx; 1632 1633 pidx = (idx - 1) & VGE_NTXDESC_MASK; 1634 1635 /* 1636 * Loop through the send queue, setting up transmit descriptors 1637 * until we drain the queue, or use up all available transmit 1638 * descriptors. 1639 */ 1640 for (;;) { 1641 /* Grab a packet off the queue. */ 1642 IFQ_POLL(&ifp->if_snd, m_head); 1643 if (m_head == NULL) 1644 break; 1645 1646 txs = &sc->sc_txsoft[idx]; 1647 1648 if (txs->txs_mbuf != NULL) { 1649 /* 1650 * Slot already used, stop for now. 1651 */ 1652 ifp->if_flags |= IFF_OACTIVE; 1653 break; 1654 } 1655 1656 if ((error = vge_encap(sc, m_head, idx))) { 1657 if (error == EFBIG) { 1658 aprint_error("%s: Tx packet consumes too many " 1659 "DMA segments, dropping...\n", 1660 sc->sc_dev.dv_xname); 1661 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1662 m_freem(m_head); 1663 continue; 1664 } 1665 1666 /* 1667 * Short on resources, just stop for now. 1668 */ 1669 if (error == ENOBUFS) 1670 ifp->if_flags |= IFF_OACTIVE; 1671 break; 1672 } 1673 1674 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1675 1676 /* 1677 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1678 */ 1679 1680 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |= 1681 htole16(VGE_TXDESC_Q); 1682 VGE_TXFRAGSYNC(sc, pidx, 1, 1683 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1684 1685 if (txs->txs_mbuf != m_head) { 1686 m_freem(m_head); 1687 m_head = txs->txs_mbuf; 1688 } 1689 1690 pidx = idx; 1691 idx = VGE_NEXT_TXDESC(idx); 1692 1693 /* 1694 * If there's a BPF listener, bounce a copy of this frame 1695 * to him. 1696 */ 1697 #if NBPFILTER > 0 1698 if (ifp->if_bpf) 1699 bpf_mtap(ifp->if_bpf, m_head); 1700 #endif 1701 } 1702 1703 if (idx == sc->sc_tx_prodidx) { 1704 return; 1705 } 1706 1707 /* Issue a transmit command. */ 1708 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1709 1710 sc->sc_tx_prodidx = idx; 1711 1712 /* 1713 * Use the countdown timer for interrupt moderation. 1714 * 'TX done' interrupts are disabled. Instead, we reset the 1715 * countdown timer, which will begin counting until it hits 1716 * the value in the SSTIMER register, and then trigger an 1717 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1718 * the timer count is reloaded. Only when the transmitter 1719 * is idle will the timer hit 0 and an interrupt fire. 1720 */ 1721 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1722 1723 /* 1724 * Set a timeout in case the chip goes out to lunch. 1725 */ 1726 ifp->if_timer = 5; 1727 } 1728 1729 static int 1730 vge_init(struct ifnet *ifp) 1731 { 1732 struct vge_softc *sc; 1733 struct vge_rxsoft *rxs; 1734 int i; 1735 1736 sc = ifp->if_softc; 1737 1738 /* 1739 * Cancel pending I/O and free all RX/TX buffers. 1740 */ 1741 vge_stop(sc); 1742 vge_reset(sc); 1743 1744 /* Initialize the RX descriptors and mbufs. */ 1745 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 1746 for (i = 0; i < VGE_NRXDESC; i++) { 1747 rxs = &sc->sc_rxsoft[i]; 1748 if (rxs->rxs_mbuf) { 1749 m_freem(rxs->rxs_mbuf); 1750 rxs->rxs_mbuf = NULL; 1751 } 1752 if (rxs->rxs_dmamap) 1753 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1754 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1755 aprint_error("%s: unable to allocate or map " 1756 "rx buffer\n", sc->sc_dev.dv_xname); 1757 return 1; /* XXX */ 1758 } 1759 } 1760 sc->sc_rx_prodidx = 0; 1761 sc->sc_rx_consumed = 0; 1762 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1763 1764 /* Initialize the TX descriptors and mbufs. */ 1765 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1766 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 1767 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs), 1768 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1769 for (i = 0; i < VGE_NTXDESC; i++) 1770 sc->sc_txsoft[i].txs_mbuf = NULL; 1771 1772 sc->sc_tx_prodidx = 0; 1773 sc->sc_tx_considx = 0; 1774 sc->sc_tx_free = VGE_NTXDESC; 1775 1776 /* Set our station address */ 1777 for (i = 0; i < ETHER_ADDR_LEN; i++) 1778 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]); 1779 1780 /* 1781 * Set receive FIFO threshold. Also allow transmission and 1782 * reception of VLAN tagged frames. 1783 */ 1784 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1785 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1786 1787 /* Set DMA burst length */ 1788 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1789 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1790 1791 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1792 1793 /* Set collision backoff algorithm */ 1794 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1795 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1796 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1797 1798 /* Disable LPSEL field in priority resolution */ 1799 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1800 1801 /* 1802 * Load the addresses of the DMA queues into the chip. 1803 * Note that we only use one transmit queue. 1804 */ 1805 1806 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0))); 1807 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1); 1808 1809 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0))); 1810 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1); 1811 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC); 1812 1813 /* Enable and wake up the RX descriptor queue */ 1814 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1815 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1816 1817 /* Enable the TX descriptor queue */ 1818 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1819 1820 /* Set up the receive filter -- allow large frames for VLANs. */ 1821 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1822 1823 /* If we want promiscuous mode, set the allframes bit. */ 1824 if (ifp->if_flags & IFF_PROMISC) { 1825 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1826 } 1827 1828 /* Set capture broadcast bit to capture broadcast frames. */ 1829 if (ifp->if_flags & IFF_BROADCAST) { 1830 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1831 } 1832 1833 /* Set multicast bit to capture multicast frames. */ 1834 if (ifp->if_flags & IFF_MULTICAST) { 1835 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1836 } 1837 1838 /* Init the cam filter. */ 1839 vge_cam_clear(sc); 1840 1841 /* Init the multicast filter. */ 1842 vge_setmulti(sc); 1843 1844 /* Enable flow control */ 1845 1846 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1847 1848 /* Enable jumbo frame reception (if desired) */ 1849 1850 /* Start the MAC. */ 1851 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1852 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1853 CSR_WRITE_1(sc, VGE_CRS0, 1854 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1855 1856 /* 1857 * Configure one-shot timer for microsecond 1858 * resulution and load it for 500 usecs. 1859 */ 1860 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1861 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1862 1863 /* 1864 * Configure interrupt moderation for receive. Enable 1865 * the holdoff counter and load it, and set the RX 1866 * suppression count to the number of descriptors we 1867 * want to allow before triggering an interrupt. 1868 * The holdoff timer is in units of 20 usecs. 1869 */ 1870 1871 #ifdef notyet 1872 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1873 /* Select the interrupt holdoff timer page. */ 1874 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1875 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1876 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1877 1878 /* Enable use of the holdoff timer. */ 1879 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1880 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1881 1882 /* Select the RX suppression threshold page. */ 1883 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1884 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1885 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1886 1887 /* Restore the page select bits. */ 1888 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1889 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1890 #endif 1891 1892 #ifdef DEVICE_POLLING 1893 /* 1894 * Disable interrupts if we are polling. 1895 */ 1896 if (ifp->if_flags & IFF_POLLING) { 1897 CSR_WRITE_4(sc, VGE_IMR, 0); 1898 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1899 } else /* otherwise ... */ 1900 #endif /* DEVICE_POLLING */ 1901 { 1902 /* 1903 * Enable interrupts. 1904 */ 1905 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1906 CSR_WRITE_4(sc, VGE_ISR, 0); 1907 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1908 } 1909 1910 mii_mediachg(&sc->sc_mii); 1911 1912 ifp->if_flags |= IFF_RUNNING; 1913 ifp->if_flags &= ~IFF_OACTIVE; 1914 1915 sc->sc_if_flags = 0; 1916 sc->sc_link = 0; 1917 1918 callout_schedule(&sc->sc_timeout, hz); 1919 1920 return 0; 1921 } 1922 1923 /* 1924 * Set media options. 1925 */ 1926 static int 1927 vge_ifmedia_upd(struct ifnet *ifp) 1928 { 1929 struct vge_softc *sc; 1930 1931 sc = ifp->if_softc; 1932 mii_mediachg(&sc->sc_mii); 1933 1934 return 0; 1935 } 1936 1937 /* 1938 * Report current media status. 1939 */ 1940 static void 1941 vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1942 { 1943 struct vge_softc *sc; 1944 struct mii_data *mii; 1945 1946 sc = ifp->if_softc; 1947 mii = &sc->sc_mii; 1948 1949 mii_pollstat(mii); 1950 ifmr->ifm_active = mii->mii_media_active; 1951 ifmr->ifm_status = mii->mii_media_status; 1952 } 1953 1954 static void 1955 vge_miibus_statchg(struct device *self) 1956 { 1957 struct vge_softc *sc; 1958 struct mii_data *mii; 1959 struct ifmedia_entry *ife; 1960 1961 sc = (void *)self; 1962 mii = &sc->sc_mii; 1963 ife = mii->mii_media.ifm_cur; 1964 /* 1965 * If the user manually selects a media mode, we need to turn 1966 * on the forced MAC mode bit in the DIAGCTL register. If the 1967 * user happens to choose a full duplex mode, we also need to 1968 * set the 'force full duplex' bit. This applies only to 1969 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1970 * mode is disabled, and in 1000baseT mode, full duplex is 1971 * always implied, so we turn on the forced mode bit but leave 1972 * the FDX bit cleared. 1973 */ 1974 1975 switch (IFM_SUBTYPE(ife->ifm_media)) { 1976 case IFM_AUTO: 1977 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1978 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1979 break; 1980 case IFM_1000_T: 1981 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1982 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1983 break; 1984 case IFM_100_TX: 1985 case IFM_10_T: 1986 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1987 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1988 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1989 } else { 1990 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1991 } 1992 break; 1993 default: 1994 aprint_error("%s: unknown media type: %x\n", 1995 sc->sc_dev.dv_xname, 1996 IFM_SUBTYPE(ife->ifm_media)); 1997 break; 1998 } 1999 } 2000 2001 static int 2002 vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2003 { 2004 struct vge_softc *sc; 2005 struct ifreq *ifr; 2006 struct mii_data *mii; 2007 int s, error; 2008 2009 sc = ifp->if_softc; 2010 ifr = (struct ifreq *)data; 2011 error = 0; 2012 2013 s = splnet(); 2014 2015 switch (command) { 2016 case SIOCSIFMTU: 2017 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2018 error = EINVAL; 2019 ifp->if_mtu = ifr->ifr_mtu; 2020 break; 2021 case SIOCSIFFLAGS: 2022 if (ifp->if_flags & IFF_UP) { 2023 if (ifp->if_flags & IFF_RUNNING && 2024 ifp->if_flags & IFF_PROMISC && 2025 !(sc->sc_if_flags & IFF_PROMISC)) { 2026 CSR_SETBIT_1(sc, VGE_RXCTL, 2027 VGE_RXCTL_RX_PROMISC); 2028 vge_setmulti(sc); 2029 } else if (ifp->if_flags & IFF_RUNNING && 2030 !(ifp->if_flags & IFF_PROMISC) && 2031 sc->sc_if_flags & IFF_PROMISC) { 2032 CSR_CLRBIT_1(sc, VGE_RXCTL, 2033 VGE_RXCTL_RX_PROMISC); 2034 vge_setmulti(sc); 2035 } else 2036 vge_init(ifp); 2037 } else { 2038 if (ifp->if_flags & IFF_RUNNING) 2039 vge_stop(sc); 2040 } 2041 sc->sc_if_flags = ifp->if_flags; 2042 break; 2043 case SIOCADDMULTI: 2044 case SIOCDELMULTI: 2045 error = (command == SIOCADDMULTI) ? 2046 ether_addmulti(ifr, &sc->sc_ethercom) : 2047 ether_delmulti(ifr, &sc->sc_ethercom); 2048 2049 if (error == ENETRESET) { 2050 /* 2051 * Multicast list has changed; set the hardware filter 2052 * accordingly. 2053 */ 2054 if (ifp->if_flags & IFF_RUNNING) 2055 vge_setmulti(sc); 2056 error = 0; 2057 } 2058 break; 2059 case SIOCGIFMEDIA: 2060 case SIOCSIFMEDIA: 2061 mii = &sc->sc_mii; 2062 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2063 break; 2064 default: 2065 error = ether_ioctl(ifp, command, data); 2066 break; 2067 } 2068 2069 splx(s); 2070 return error; 2071 } 2072 2073 static void 2074 vge_watchdog(struct ifnet *ifp) 2075 { 2076 struct vge_softc *sc; 2077 int s; 2078 2079 sc = ifp->if_softc; 2080 s = splnet(); 2081 aprint_error("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2082 ifp->if_oerrors++; 2083 2084 vge_txeof(sc); 2085 vge_rxeof(sc); 2086 2087 vge_init(ifp); 2088 2089 splx(s); 2090 } 2091 2092 /* 2093 * Stop the adapter and free any mbufs allocated to the 2094 * RX and TX lists. 2095 */ 2096 static void 2097 vge_stop(struct vge_softc *sc) 2098 { 2099 struct ifnet *ifp; 2100 struct vge_txsoft *txs; 2101 struct vge_rxsoft *rxs; 2102 int i, s; 2103 2104 ifp = &sc->sc_ethercom.ec_if; 2105 2106 s = splnet(); 2107 ifp->if_timer = 0; 2108 2109 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2110 #ifdef DEVICE_POLLING 2111 ether_poll_deregister(ifp); 2112 #endif /* DEVICE_POLLING */ 2113 2114 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2115 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2116 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2117 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2118 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2119 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2120 2121 if (sc->sc_rx_mhead != NULL) { 2122 m_freem(sc->sc_rx_mhead); 2123 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 2124 } 2125 2126 /* Free the TX list buffers. */ 2127 2128 for (i = 0; i < VGE_NTXDESC; i++) { 2129 txs = &sc->sc_txsoft[i]; 2130 if (txs->txs_mbuf != NULL) { 2131 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2132 m_freem(txs->txs_mbuf); 2133 txs->txs_mbuf = NULL; 2134 } 2135 } 2136 2137 /* Free the RX list buffers. */ 2138 2139 for (i = 0; i < VGE_NRXDESC; i++) { 2140 rxs = &sc->sc_rxsoft[i]; 2141 if (rxs->rxs_mbuf != NULL) { 2142 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2143 m_freem(rxs->rxs_mbuf); 2144 rxs->rxs_mbuf = NULL; 2145 } 2146 } 2147 2148 splx(s); 2149 } 2150 2151 #if VGE_POWER_MANAGEMENT 2152 /* 2153 * Device suspend routine. Stop the interface and save some PCI 2154 * settings in case the BIOS doesn't restore them properly on 2155 * resume. 2156 */ 2157 static int 2158 vge_suspend(struct device *dev) 2159 { 2160 struct vge_softc *sc; 2161 int i; 2162 2163 sc = device_get_softc(dev); 2164 2165 vge_stop(sc); 2166 2167 for (i = 0; i < 5; i++) 2168 sc->sc_saved_maps[i] = 2169 pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2170 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2171 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2172 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2173 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2174 2175 sc->suspended = 1; 2176 2177 return 0; 2178 } 2179 2180 /* 2181 * Device resume routine. Restore some PCI settings in case the BIOS 2182 * doesn't, re-enable busmastering, and restart the interface if 2183 * appropriate. 2184 */ 2185 static int 2186 vge_resume(struct device *dev) 2187 { 2188 struct vge_softc *sc; 2189 struct ifnet *ifp; 2190 int i; 2191 2192 sc = (void *)dev; 2193 ifp = &sc->sc_ethercom.ec_if; 2194 2195 /* better way to do this? */ 2196 for (i = 0; i < 5; i++) 2197 pci_write_config(dev, PCIR_MAPS + i * 4, 2198 sc->sc_saved_maps[i], 4); 2199 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4); 2200 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1); 2201 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1); 2202 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1); 2203 2204 /* reenable busmastering */ 2205 pci_enable_busmaster(dev); 2206 pci_enable_io(dev, SYS_RES_MEMORY); 2207 2208 /* reinitialize interface if necessary */ 2209 if (ifp->if_flags & IFF_UP) 2210 vge_init(sc); 2211 2212 sc->suspended = 0; 2213 2214 return 0; 2215 } 2216 #endif 2217 2218 /* 2219 * Stop all chip I/O so that the kernel's probe routines don't 2220 * get confused by errant DMAs when rebooting. 2221 */ 2222 static void 2223 vge_shutdown(void *arg) 2224 { 2225 struct vge_softc *sc; 2226 2227 sc = arg; 2228 vge_stop(sc); 2229 } 2230
Indexes created Mon Sep 29 21:09:56 GMT 2025