if_vge.c revision 1.4.2.1
1 /* $NetBSD: if_vge.c,v 1.4.2.1 2005/09/11 22:06:32 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.4.2.1 2005/09/11 22:06:32 tron Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul (at) windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/if_ether.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <machine/bus.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #include <dev/pci/if_vgereg.h> 116 #include <dev/pci/if_vgevar.h> 117 118 static int vge_probe (struct device *, struct cfdata *, void *); 119 static void vge_attach (struct device *, struct device *, void *); 120 121 static int vge_encap (struct vge_softc *, struct mbuf *, int); 122 123 static int vge_dma_map_rx_desc (struct vge_softc *, int); 124 static void vge_dma_map_tx_desc (struct vge_softc *, struct mbuf *, int, int); 125 static int vge_allocmem (struct vge_softc *); 126 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 127 static int vge_rx_list_init (struct vge_softc *); 128 static int vge_tx_list_init (struct vge_softc *); 129 #ifdef VGE_FIXUP_RX 130 static __inline void vge_fixup_rx 131 (struct mbuf *); 132 #endif 133 static void vge_rxeof (struct vge_softc *); 134 static void vge_txeof (struct vge_softc *); 135 static int vge_intr (void *); 136 static void vge_tick (void *); 137 static void vge_start (struct ifnet *); 138 static int vge_ioctl (struct ifnet *, u_long, caddr_t); 139 static int vge_init (struct ifnet *); 140 static void vge_stop (struct vge_softc *); 141 static void vge_watchdog (struct ifnet *); 142 #if VGE_POWER_MANAGEMENT 143 static int vge_suspend (struct device *); 144 static int vge_resume (struct device *); 145 #endif 146 static void vge_shutdown (void *); 147 static int vge_ifmedia_upd (struct ifnet *); 148 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 150 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 151 static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 152 153 static void vge_miipoll_start (struct vge_softc *); 154 static void vge_miipoll_stop (struct vge_softc *); 155 static int vge_miibus_readreg (struct device *, int, int); 156 static void vge_miibus_writereg (struct device *, int, int, int); 157 static void vge_miibus_statchg (struct device *); 158 159 static void vge_cam_clear (struct vge_softc *); 160 static int vge_cam_set (struct vge_softc *, uint8_t *); 161 static void vge_setmulti (struct vge_softc *); 162 static void vge_reset (struct vge_softc *); 163 164 #define VGE_PCI_LOIO 0x10 165 #define VGE_PCI_LOMEM 0x14 166 167 CFATTACH_DECL(vge, sizeof(struct vge_softc), 168 vge_probe, vge_attach, NULL, NULL); 169 170 /* 171 * Defragment mbuf chain contents to be as linear as possible. 172 * Returns new mbuf chain on success, NULL on failure. Old mbuf 173 * chain is always freed. 174 * XXX temporary until there would be generic function doing this. 175 */ 176 #define m_defrag vge_m_defrag 177 struct mbuf * vge_m_defrag(struct mbuf *, int); 178 179 struct mbuf * 180 vge_m_defrag(struct mbuf *mold, int flags) 181 { 182 struct mbuf *m0, *mn, *n; 183 size_t sz = mold->m_pkthdr.len; 184 185 #ifdef DIAGNOSTIC 186 if ((mold->m_flags & M_PKTHDR) == 0) 187 panic("m_defrag: not a mbuf chain header"); 188 #endif 189 190 MGETHDR(m0, flags, MT_DATA); 191 if (m0 == NULL) 192 return NULL; 193 m0->m_pkthdr.len = mold->m_pkthdr.len; 194 mn = m0; 195 196 do { 197 if (sz > MHLEN) { 198 MCLGET(mn, M_DONTWAIT); 199 if ((mn->m_flags & M_EXT) == 0) { 200 m_freem(m0); 201 return NULL; 202 } 203 } 204 205 mn->m_len = MIN(sz, MCLBYTES); 206 207 m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 208 mtod(mn, caddr_t)); 209 210 sz -= mn->m_len; 211 212 if (sz > 0) { 213 /* need more mbufs */ 214 MGET(n, M_NOWAIT, MT_DATA); 215 if (n == NULL) { 216 m_freem(m0); 217 return NULL; 218 } 219 220 mn->m_next = n; 221 mn = n; 222 } 223 } while (sz > 0); 224 225 return m0; 226 } 227 228 /* 229 * Read a word of data stored in the EEPROM at address 'addr.' 230 */ 231 static void 232 vge_eeprom_getword(sc, addr, dest) 233 struct vge_softc *sc; 234 int addr; 235 u_int16_t *dest; 236 { 237 register int i; 238 u_int16_t word = 0; 239 240 /* 241 * Enter EEPROM embedded programming mode. In order to 242 * access the EEPROM at all, we first have to set the 243 * EELOAD bit in the CHIPCFG2 register. 244 */ 245 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 246 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 247 248 /* Select the address of the word we want to read */ 249 CSR_WRITE_1(sc, VGE_EEADDR, addr); 250 251 /* Issue read command */ 252 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 253 254 /* Wait for the done bit to be set. */ 255 for (i = 0; i < VGE_TIMEOUT; i++) { 256 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) { 261 printf("%s: EEPROM read timed out\n", sc->sc_dev.dv_xname); 262 *dest = 0; 263 return; 264 } 265 266 /* Read the result */ 267 word = CSR_READ_2(sc, VGE_EERDDAT); 268 269 /* Turn off EEPROM access mode. */ 270 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 271 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 272 273 *dest = word; 274 275 return; 276 } 277 278 /* 279 * Read a sequence of words from the EEPROM. 280 */ 281 static void 282 vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288 { 289 int i; 290 u_int16_t word = 0, *ptr; 291 292 for (i = 0; i < cnt; i++) { 293 vge_eeprom_getword(sc, off + i, &word); 294 ptr = (u_int16_t *)(dest + (i * 2)); 295 if (swap) 296 *ptr = ntohs(word); 297 else 298 *ptr = word; 299 } 300 } 301 302 static void 303 vge_miipoll_stop(sc) 304 struct vge_softc *sc; 305 { 306 int i; 307 308 CSR_WRITE_1(sc, VGE_MIICMD, 0); 309 310 for (i = 0; i < VGE_TIMEOUT; i++) { 311 DELAY(1); 312 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 313 break; 314 } 315 316 if (i == VGE_TIMEOUT) { 317 printf("%s: failed to idle MII autopoll\n", 318 sc->sc_dev.dv_xname); 319 } 320 321 return; 322 } 323 324 static void 325 vge_miipoll_start(sc) 326 struct vge_softc *sc; 327 { 328 int i; 329 330 /* First, make sure we're idle. */ 331 332 CSR_WRITE_1(sc, VGE_MIICMD, 0); 333 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 334 335 for (i = 0; i < VGE_TIMEOUT; i++) { 336 DELAY(1); 337 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 338 break; 339 } 340 341 if (i == VGE_TIMEOUT) { 342 printf("%s: failed to idle MII autopoll\n", 343 sc->sc_dev.dv_xname); 344 return; 345 } 346 347 /* Now enable auto poll mode. */ 348 349 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 350 351 /* And make sure it started. */ 352 353 for (i = 0; i < VGE_TIMEOUT; i++) { 354 DELAY(1); 355 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 356 break; 357 } 358 359 if (i == VGE_TIMEOUT) { 360 printf("%s: failed to start MII autopoll\n", 361 sc->sc_dev.dv_xname); 362 } 363 } 364 365 static int 366 vge_miibus_readreg(dev, phy, reg) 367 struct device *dev; 368 int phy, reg; 369 { 370 struct vge_softc *sc = (struct vge_softc *)dev; 371 int i; 372 u_int16_t rval = 0; 373 374 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 375 return(0); 376 377 VGE_LOCK(sc); 378 vge_miipoll_stop(sc); 379 380 /* Specify the register we want to read. */ 381 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 382 383 /* Issue read command. */ 384 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 385 386 /* Wait for the read command bit to self-clear. */ 387 for (i = 0; i < VGE_TIMEOUT; i++) { 388 DELAY(1); 389 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 390 break; 391 } 392 393 if (i == VGE_TIMEOUT) 394 printf("%s: MII read timed out\n", sc->sc_dev.dv_xname); 395 else 396 rval = CSR_READ_2(sc, VGE_MIIDATA); 397 398 vge_miipoll_start(sc); 399 VGE_UNLOCK(sc); 400 401 return (rval); 402 } 403 404 static void 405 vge_miibus_writereg(dev, phy, reg, data) 406 struct device *dev; 407 int phy, reg, data; 408 { 409 struct vge_softc *sc = (struct vge_softc *)dev; 410 int i; 411 412 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 413 return; 414 415 VGE_LOCK(sc); 416 vge_miipoll_stop(sc); 417 418 /* Specify the register we want to write. */ 419 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 420 421 /* Specify the data we want to write. */ 422 CSR_WRITE_2(sc, VGE_MIIDATA, data); 423 424 /* Issue write command. */ 425 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 426 427 /* Wait for the write command bit to self-clear. */ 428 for (i = 0; i < VGE_TIMEOUT; i++) { 429 DELAY(1); 430 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 431 break; 432 } 433 434 if (i == VGE_TIMEOUT) { 435 printf("%s: MII write timed out\n", sc->sc_dev.dv_xname); 436 } 437 438 vge_miipoll_start(sc); 439 VGE_UNLOCK(sc); 440 } 441 442 static void 443 vge_cam_clear(sc) 444 struct vge_softc *sc; 445 { 446 int i; 447 448 /* 449 * Turn off all the mask bits. This tells the chip 450 * that none of the entries in the CAM filter are valid. 451 * desired entries will be enabled as we fill the filter in. 452 */ 453 454 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 455 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 456 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 457 for (i = 0; i < 8; i++) 458 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 459 460 /* Clear the VLAN filter too. */ 461 462 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 463 for (i = 0; i < 8; i++) 464 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 465 466 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 467 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 468 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 469 470 sc->vge_camidx = 0; 471 472 return; 473 } 474 475 static int 476 vge_cam_set(sc, addr) 477 struct vge_softc *sc; 478 uint8_t *addr; 479 { 480 int i, error = 0; 481 482 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 483 return(ENOSPC); 484 485 /* Select the CAM data page. */ 486 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 487 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 488 489 /* Set the filter entry we want to update and enable writing. */ 490 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 491 492 /* Write the address to the CAM registers */ 493 for (i = 0; i < ETHER_ADDR_LEN; i++) 494 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 495 496 /* Issue a write command. */ 497 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 498 499 /* Wake for it to clear. */ 500 for (i = 0; i < VGE_TIMEOUT; i++) { 501 DELAY(1); 502 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 503 break; 504 } 505 506 if (i == VGE_TIMEOUT) { 507 printf("%s: setting CAM filter failed\n", sc->sc_dev.dv_xname); 508 error = EIO; 509 goto fail; 510 } 511 512 /* Select the CAM mask page. */ 513 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 514 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 515 516 /* Set the mask bit that enables this filter. */ 517 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 518 1<<(sc->vge_camidx & 7)); 519 520 sc->vge_camidx++; 521 522 fail: 523 /* Turn off access to CAM. */ 524 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 525 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 526 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 527 528 return (error); 529 } 530 531 /* 532 * Program the multicast filter. We use the 64-entry CAM filter 533 * for perfect filtering. If there's more than 64 multicast addresses, 534 * we use the hash filter insted. 535 */ 536 static void 537 vge_setmulti(sc) 538 struct vge_softc *sc; 539 { 540 struct ifnet *ifp; 541 int error = 0; 542 u_int32_t h, hashes[2] = { 0, 0 }; 543 struct ether_multi *enm; 544 struct ether_multistep step; 545 546 ifp = &sc->sc_ethercom.ec_if; 547 548 /* First, zot all the multicast entries. */ 549 vge_cam_clear(sc); 550 CSR_WRITE_4(sc, VGE_MAR0, 0); 551 CSR_WRITE_4(sc, VGE_MAR1, 0); 552 ifp->if_flags &= ~IFF_ALLMULTI; 553 554 /* 555 * If the user wants allmulti or promisc mode, enable reception 556 * of all multicast frames. 557 */ 558 if (ifp->if_flags & IFF_PROMISC) { 559 allmulti: 560 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 561 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 562 ifp->if_flags |= IFF_ALLMULTI; 563 return; 564 } 565 566 /* Now program new ones */ 567 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 568 while(enm != NULL) { 569 /* 570 * If multicast range, fall back to ALLMULTI. 571 */ 572 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 573 ETHER_ADDR_LEN) != 0) 574 goto allmulti; 575 576 error = vge_cam_set(sc, enm->enm_addrlo); 577 if (error) 578 break; 579 580 ETHER_NEXT_MULTI(step, enm); 581 } 582 583 /* If there were too many addresses, use the hash filter. */ 584 if (error) { 585 vge_cam_clear(sc); 586 587 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 588 while(enm != NULL) { 589 /* 590 * If multicast range, fall back to ALLMULTI. 591 */ 592 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 593 ETHER_ADDR_LEN) != 0) 594 goto allmulti; 595 596 h = ether_crc32_be(enm->enm_addrlo, 597 ETHER_ADDR_LEN) >> 26; 598 hashes[h >> 5] |= 1 << (h & 0x1f); 599 600 ETHER_NEXT_MULTI(step, enm); 601 } 602 603 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 604 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 605 } 606 607 return; 608 } 609 610 static void 611 vge_reset(sc) 612 struct vge_softc *sc; 613 { 614 register int i; 615 616 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 617 618 for (i = 0; i < VGE_TIMEOUT; i++) { 619 DELAY(5); 620 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 621 break; 622 } 623 624 if (i == VGE_TIMEOUT) { 625 printf("%s: soft reset timed out", sc->sc_dev.dv_xname); 626 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 627 DELAY(2000); 628 } 629 630 DELAY(5000); 631 632 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 633 634 for (i = 0; i < VGE_TIMEOUT; i++) { 635 DELAY(5); 636 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 637 break; 638 } 639 640 if (i == VGE_TIMEOUT) { 641 printf("%s: EEPROM reload timed out\n", sc->sc_dev.dv_xname); 642 return; 643 } 644 645 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 646 647 return; 648 } 649 650 /* 651 * Probe for a VIA gigabit chip. Check the PCI vendor and device 652 * IDs against our list and return a device name if we find a match. 653 */ 654 static int 655 vge_probe(struct device *parent, struct cfdata *match, void *aux) 656 { 657 struct pci_attach_args *pa = aux; 658 659 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 660 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 661 return 1; 662 663 return (0); 664 } 665 666 static int 667 vge_dma_map_rx_desc(sc, idx) 668 struct vge_softc *sc; 669 int idx; 670 { 671 struct vge_rx_desc *d = NULL; 672 bus_dma_segment_t *segs; 673 674 /* 675 * Map the segment array into descriptors. 676 */ 677 678 d = &sc->vge_ldata.vge_rx_list[idx]; 679 680 /* If this descriptor is still owned by the chip, bail. */ 681 682 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 683 printf("%s: tried to map busy descriptor\n", 684 sc->sc_dev.dv_xname); 685 return (EBUSY); 686 } 687 688 segs = sc->vge_ldata.vge_rx_dmamap[idx]->dm_segs; 689 690 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 691 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 692 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 693 d->vge_sts = 0; 694 d->vge_ctl = 0; 695 696 return (0); 697 } 698 699 static void 700 vge_dma_map_tx_desc(sc, m0, idx, flags) 701 struct vge_softc *sc; 702 struct mbuf *m0; 703 int idx, flags; 704 { 705 struct vge_tx_desc *d = &sc->vge_ldata.vge_tx_list[idx]; 706 struct vge_tx_frag *f; 707 int i = 0; 708 bus_dma_segment_t *segs; 709 size_t sz; 710 bus_dmamap_t map = sc->vge_ldata.vge_tx_dmamap[idx]; 711 712 /* Map the segment array into descriptors. */ 713 714 segs = map->dm_segs; 715 for (i = 0; i < map->dm_nsegs; i++) { 716 f = &d->vge_frag[i]; 717 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 718 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 719 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 720 } 721 722 /* Argh. This chip does not autopad short frames */ 723 724 sz = m0->m_pkthdr.len; 725 if (m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 726 f = &d->vge_frag[i]; 727 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - sz)); 728 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 729 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 730 sz = VGE_MIN_FRAMELEN; 731 i++; 732 } 733 734 /* 735 * When telling the chip how many segments there are, we 736 * must use nsegs + 1 instead of just nsegs. Darned if I 737 * know why. 738 */ 739 i++; 740 741 d->vge_sts = sz << 16; 742 d->vge_ctl = flags|(i << 28)|VGE_TD_LS_NORM; 743 744 if (sz > ETHERMTU + ETHER_HDR_LEN) 745 d->vge_ctl |= VGE_TDCTL_JUMBO; 746 } 747 748 static int 749 vge_allocmem(sc) 750 struct vge_softc *sc; 751 { 752 int error; 753 int nseg; 754 int i; 755 bus_dma_segment_t seg; 756 757 /* 758 * Allocate map for TX descriptor list. 759 */ 760 error = bus_dmamap_create(sc->vge_dmat, 761 round_page(VGE_TX_LIST_SZ), 1, round_page(VGE_TX_LIST_SZ), 762 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 763 &sc->vge_ldata.vge_tx_list_map); 764 if (error) { 765 printf("%s: could not allocate TX dma list map\n", 766 sc->sc_dev.dv_xname); 767 return (ENOMEM); 768 } 769 770 /* 771 * Allocate memory for TX descriptor list. 772 */ 773 774 error = bus_dmamem_alloc(sc->vge_dmat, VGE_TX_LIST_SZ, VGE_RING_ALIGN, 775 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 776 if (error) { 777 printf("%s: could not allocate TX ring dma memory\n", 778 sc->sc_dev.dv_xname); 779 return (ENOMEM); 780 } 781 782 /* Map the memory to kernel VA space */ 783 784 error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 785 (caddr_t *) &sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 786 if (error) { 787 printf("%s: could not map TX ring dma memory\n", 788 sc->sc_dev.dv_xname); 789 return (ENOMEM); 790 } 791 792 /* Load the map for the TX ring. */ 793 error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_tx_list_map, 794 sc->vge_ldata.vge_tx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 795 if (error) { 796 printf("%s: could not load TX ring dma memory\n", 797 sc->sc_dev.dv_xname); 798 return (ENOMEM); 799 } 800 801 sc->vge_ldata.vge_tx_list_addr = 802 sc->vge_ldata.vge_tx_list_map->dm_segs[0].ds_addr; 803 804 /* Create DMA maps for TX buffers */ 805 806 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 807 error = bus_dmamap_create(sc->vge_dmat, VGE_TX_MAXLEN, 808 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, 809 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 810 &sc->vge_ldata.vge_tx_dmamap[i]); 811 if (error) { 812 printf("%s: can't create DMA map for TX\n", 813 sc->sc_dev.dv_xname); 814 return (ENOMEM); 815 } 816 } 817 818 /* 819 * Allocate map for RX descriptor list. 820 */ 821 error = bus_dmamap_create(sc->vge_dmat, 822 round_page(VGE_RX_LIST_SZ), 1, round_page(VGE_RX_LIST_SZ), 823 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 824 &sc->vge_ldata.vge_rx_list_map); 825 if (error) { 826 printf("%s: could not allocate RX dma list map\n", 827 sc->sc_dev.dv_xname); 828 return (ENOMEM); 829 } 830 831 /* Allocate DMA'able memory for the RX ring */ 832 833 error = bus_dmamem_alloc(sc->vge_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 834 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 835 if (error) 836 return (ENOMEM); 837 838 /* Map the memory to kernel VA space */ 839 840 error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 841 (caddr_t *) &sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 842 if (error) 843 return (ENOMEM); 844 845 /* Load the map for the RX ring. */ 846 error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_rx_list_map, 847 sc->vge_ldata.vge_rx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 848 if (error) { 849 printf("%s: could not load RX ring dma memory\n", 850 sc->sc_dev.dv_xname); 851 return (ENOMEM); 852 } 853 854 sc->vge_ldata.vge_rx_list_addr = 855 sc->vge_ldata.vge_rx_list_map->dm_segs[0].ds_addr; 856 857 /* Create DMA maps for RX buffers */ 858 859 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 860 error = bus_dmamap_create(sc->vge_dmat, MCLBYTES, 861 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 862 &sc->vge_ldata.vge_rx_dmamap[i]); 863 if (error) { 864 printf("%s: can't create DMA map for RX\n", 865 sc->sc_dev.dv_xname); 866 return (ENOMEM); 867 } 868 } 869 870 return (0); 871 } 872 873 /* 874 * Attach the interface. Allocate softc structures, do ifmedia 875 * setup and ethernet/BPF attach. 876 */ 877 static void 878 vge_attach(struct device *parent, struct device *self, void *aux) 879 { 880 u_char eaddr[ETHER_ADDR_LEN]; 881 struct vge_softc *sc = (struct vge_softc *)self; 882 struct ifnet *ifp; 883 struct pci_attach_args *pa = aux; 884 pci_chipset_tag_t pc = pa->pa_pc; 885 const char *intrstr; 886 pci_intr_handle_t ih; 887 888 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 889 PCI_REVISION(pa->pa_class)); 890 891 /* Make sure bus-mastering is enabled */ 892 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 893 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 894 PCI_COMMAND_MASTER_ENABLE); 895 896 /* 897 * Map control/status registers. 898 */ 899 if (0 != pci_mapreg_map(pa, VGE_PCI_LOMEM, 900 PCI_MAPREG_TYPE_MEM, BUS_SPACE_MAP_LINEAR, 901 &sc->vge_btag, &sc->vge_bhandle, NULL, NULL)) { 902 aprint_error("%s: couldn't map memory\n", 903 sc->sc_dev.dv_xname); 904 return; 905 } 906 907 /* 908 * Map and establish our interrupt. 909 */ 910 if (pci_intr_map(pa, &ih)) { 911 aprint_error("%s: unable to map interrupt\n", 912 sc->sc_dev.dv_xname); 913 return; 914 } 915 intrstr = pci_intr_string(pc, ih); 916 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 917 if (sc->vge_intrhand == NULL) { 918 printf("%s: unable to establish interrupt", 919 sc->sc_dev.dv_xname); 920 if (intrstr != NULL) 921 printf(" at %s", intrstr); 922 printf("\n"); 923 return; 924 } 925 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 926 927 /* Reset the adapter. */ 928 vge_reset(sc); 929 930 /* 931 * Get station address from the EEPROM. 932 */ 933 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 934 bcopy(eaddr, (char *)&sc->vge_eaddr, ETHER_ADDR_LEN); 935 936 printf("%s: Ethernet address: %s\n", sc->sc_dev.dv_xname, 937 ether_sprintf(eaddr)); 938 939 /* 940 * Use the 32bit tag. Hardware supports 48bit physical addresses, 941 * but we don't use that for now. 942 */ 943 sc->vge_dmat = pa->pa_dmat; 944 945 if (vge_allocmem(sc)) 946 return; 947 948 ifp = &sc->sc_ethercom.ec_if; 949 ifp->if_softc = sc; 950 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 951 ifp->if_mtu = ETHERMTU; 952 ifp->if_baudrate = IF_Gbps(1); 953 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 954 ifp->if_ioctl = vge_ioctl; 955 ifp->if_start = vge_start; 956 957 /* 958 * We can support 802.1Q VLAN-sized frames and jumbo 959 * Ethernet frames. 960 */ 961 sc->sc_ethercom.ec_capabilities |= 962 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 963 ETHERCAP_VLAN_HWTAGGING; 964 965 /* 966 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 967 */ 968 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | 969 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 970 971 #ifdef DEVICE_POLLING 972 #ifdef IFCAP_POLLING 973 ifp->if_capabilities |= IFCAP_POLLING; 974 #endif 975 #endif 976 ifp->if_watchdog = vge_watchdog; 977 ifp->if_init = vge_init; 978 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 979 980 /* 981 * Initialize our media structures and probe the MII. 982 */ 983 sc->sc_mii.mii_ifp = ifp; 984 sc->sc_mii.mii_readreg = vge_miibus_readreg; 985 sc->sc_mii.mii_writereg = vge_miibus_writereg; 986 sc->sc_mii.mii_statchg = vge_miibus_statchg; 987 ifmedia_init(&sc->sc_mii.mii_media, 0, vge_ifmedia_upd, 988 vge_ifmedia_sts); 989 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 990 MII_OFFSET_ANY, MIIF_DOPAUSE); 991 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 992 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 993 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 994 } else 995 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 996 997 /* 998 * Attach the interface. 999 */ 1000 if_attach(ifp); 1001 ether_ifattach(ifp, eaddr); 1002 1003 callout_init(&sc->vge_timeout); 1004 callout_setfunc(&sc->vge_timeout, vge_tick, sc); 1005 1006 /* 1007 * Make sure the interface is shutdown during reboot. 1008 */ 1009 if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1010 printf("%s: WARNING: unable to establish shutdown hook\n", 1011 sc->sc_dev.dv_xname); 1012 } 1013 } 1014 1015 static int 1016 vge_newbuf(sc, idx, m) 1017 struct vge_softc *sc; 1018 int idx; 1019 struct mbuf *m; 1020 { 1021 struct mbuf *n = NULL; 1022 int i, error; 1023 1024 if (m == NULL) { 1025 n = m_gethdr(M_DONTWAIT, MT_DATA); 1026 if (n == NULL) 1027 return (ENOBUFS); 1028 1029 m_clget(n, M_DONTWAIT); 1030 if ((n->m_flags & M_EXT) == 0) { 1031 m_freem(n); 1032 return (ENOBUFS); 1033 } 1034 1035 m = n; 1036 } else 1037 m->m_data = m->m_ext.ext_buf; 1038 1039 1040 #ifdef VGE_FIXUP_RX 1041 /* 1042 * This is part of an evil trick to deal with non-x86 platforms. 1043 * The VIA chip requires RX buffers to be aligned on 32-bit 1044 * boundaries, but that will hose non-x86 machines. To get around 1045 * this, we leave some empty space at the start of each buffer 1046 * and for non-x86 hosts, we copy the buffer back two bytes 1047 * to achieve word alignment. This is slightly more efficient 1048 * than allocating a new buffer, copying the contents, and 1049 * discarding the old buffer. 1050 */ 1051 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1052 m_adj(m, VGE_ETHER_ALIGN); 1053 #else 1054 m->m_len = m->m_pkthdr.len = MCLBYTES; 1055 #endif 1056 1057 error = bus_dmamap_load_mbuf(sc->vge_dmat, 1058 sc->vge_ldata.vge_rx_dmamap[idx], m, BUS_DMA_NOWAIT); 1059 if (error || vge_dma_map_rx_desc(sc, idx)) { 1060 if (n != NULL) 1061 m_freem(n); 1062 return (ENOMEM); 1063 } 1064 1065 /* 1066 * Note: the manual fails to document the fact that for 1067 * proper opration, the driver needs to replentish the RX 1068 * DMA ring 4 descriptors at a time (rather than one at a 1069 * time, like most chips). We can allocate the new buffers 1070 * but we should not set the OWN bits until we're ready 1071 * to hand back 4 of them in one shot. 1072 */ 1073 1074 #define VGE_RXCHUNK 4 1075 sc->vge_rx_consumed++; 1076 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1077 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1078 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1079 htole32(VGE_RDSTS_OWN); 1080 sc->vge_rx_consumed = 0; 1081 } 1082 1083 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1084 1085 bus_dmamap_sync(sc->vge_dmat, 1086 sc->vge_ldata.vge_rx_dmamap[idx], 1087 0, sc->vge_ldata.vge_rx_dmamap[idx]->dm_mapsize, 1088 BUS_DMASYNC_PREREAD); 1089 1090 return (0); 1091 } 1092 1093 static int 1094 vge_tx_list_init(sc) 1095 struct vge_softc *sc; 1096 { 1097 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1098 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1099 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1100 1101 bus_dmamap_sync(sc->vge_dmat, 1102 sc->vge_ldata.vge_tx_list_map, 1103 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1104 BUS_DMASYNC_PREWRITE); 1105 1106 sc->vge_ldata.vge_tx_prodidx = 0; 1107 sc->vge_ldata.vge_tx_considx = 0; 1108 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1109 1110 return (0); 1111 } 1112 1113 static int 1114 vge_rx_list_init(sc) 1115 struct vge_softc *sc; 1116 { 1117 int i; 1118 1119 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1120 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1121 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1122 1123 sc->vge_rx_consumed = 0; 1124 1125 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1126 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1127 return (ENOBUFS); 1128 } 1129 1130 /* Flush the RX descriptors */ 1131 1132 bus_dmamap_sync(sc->vge_dmat, 1133 sc->vge_ldata.vge_rx_list_map, 1134 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1135 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1136 1137 sc->vge_ldata.vge_rx_prodidx = 0; 1138 sc->vge_rx_consumed = 0; 1139 sc->vge_head = sc->vge_tail = NULL; 1140 1141 return (0); 1142 } 1143 1144 #ifdef VGE_FIXUP_RX 1145 static __inline void 1146 vge_fixup_rx(m) 1147 struct mbuf *m; 1148 { 1149 int i; 1150 uint16_t *src, *dst; 1151 1152 src = mtod(m, uint16_t *); 1153 dst = src - 1; 1154 1155 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1156 *dst++ = *src++; 1157 1158 m->m_data -= ETHER_ALIGN; 1159 1160 return; 1161 } 1162 #endif 1163 1164 /* 1165 * RX handler. We support the reception of jumbo frames that have 1166 * been fragmented across multiple 2K mbuf cluster buffers. 1167 */ 1168 static void 1169 vge_rxeof(sc) 1170 struct vge_softc *sc; 1171 { 1172 struct mbuf *m; 1173 struct ifnet *ifp; 1174 int i, total_len; 1175 int lim = 0; 1176 struct vge_rx_desc *cur_rx; 1177 u_int32_t rxstat, rxctl; 1178 1179 VGE_LOCK_ASSERT(sc); 1180 ifp = &sc->sc_ethercom.ec_if; 1181 i = sc->vge_ldata.vge_rx_prodidx; 1182 1183 /* Invalidate the descriptor memory */ 1184 1185 bus_dmamap_sync(sc->vge_dmat, 1186 sc->vge_ldata.vge_rx_list_map, 1187 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1188 BUS_DMASYNC_POSTREAD); 1189 1190 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1191 1192 #ifdef DEVICE_POLLING 1193 if (ifp->if_flags & IFF_POLLING) { 1194 if (sc->rxcycles <= 0) 1195 break; 1196 sc->rxcycles--; 1197 } 1198 #endif /* DEVICE_POLLING */ 1199 1200 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1201 m = sc->vge_ldata.vge_rx_mbuf[i]; 1202 total_len = VGE_RXBYTES(cur_rx); 1203 rxstat = le32toh(cur_rx->vge_sts); 1204 rxctl = le32toh(cur_rx->vge_ctl); 1205 1206 /* Invalidate the RX mbuf and unload its map */ 1207 1208 bus_dmamap_sync(sc->vge_dmat, 1209 sc->vge_ldata.vge_rx_dmamap[i], 1210 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1211 BUS_DMASYNC_POSTWRITE); 1212 bus_dmamap_unload(sc->vge_dmat, 1213 sc->vge_ldata.vge_rx_dmamap[i]); 1214 1215 /* 1216 * If the 'start of frame' bit is set, this indicates 1217 * either the first fragment in a multi-fragment receive, 1218 * or an intermediate fragment. Either way, we want to 1219 * accumulate the buffers. 1220 */ 1221 if (rxstat & VGE_RXPKT_SOF) { 1222 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1223 if (sc->vge_head == NULL) 1224 sc->vge_head = sc->vge_tail = m; 1225 else { 1226 m->m_flags &= ~M_PKTHDR; 1227 sc->vge_tail->m_next = m; 1228 sc->vge_tail = m; 1229 } 1230 vge_newbuf(sc, i, NULL); 1231 VGE_RX_DESC_INC(i); 1232 continue; 1233 } 1234 1235 /* 1236 * Bad/error frames will have the RXOK bit cleared. 1237 * However, there's one error case we want to allow: 1238 * if a VLAN tagged frame arrives and the chip can't 1239 * match it against the CAM filter, it considers this 1240 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1241 * We don't want to drop the frame though: our VLAN 1242 * filtering is done in software. 1243 */ 1244 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1245 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1246 ifp->if_ierrors++; 1247 /* 1248 * If this is part of a multi-fragment packet, 1249 * discard all the pieces. 1250 */ 1251 if (sc->vge_head != NULL) { 1252 m_freem(sc->vge_head); 1253 sc->vge_head = sc->vge_tail = NULL; 1254 } 1255 vge_newbuf(sc, i, m); 1256 VGE_RX_DESC_INC(i); 1257 continue; 1258 } 1259 1260 /* 1261 * If allocating a replacement mbuf fails, 1262 * reload the current one. 1263 */ 1264 1265 if (vge_newbuf(sc, i, NULL)) { 1266 ifp->if_ierrors++; 1267 if (sc->vge_head != NULL) { 1268 m_freem(sc->vge_head); 1269 sc->vge_head = sc->vge_tail = NULL; 1270 } 1271 vge_newbuf(sc, i, m); 1272 VGE_RX_DESC_INC(i); 1273 continue; 1274 } 1275 1276 VGE_RX_DESC_INC(i); 1277 1278 if (sc->vge_head != NULL) { 1279 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1280 /* 1281 * Special case: if there's 4 bytes or less 1282 * in this buffer, the mbuf can be discarded: 1283 * the last 4 bytes is the CRC, which we don't 1284 * care about anyway. 1285 */ 1286 if (m->m_len <= ETHER_CRC_LEN) { 1287 sc->vge_tail->m_len -= 1288 (ETHER_CRC_LEN - m->m_len); 1289 m_freem(m); 1290 } else { 1291 m->m_len -= ETHER_CRC_LEN; 1292 m->m_flags &= ~M_PKTHDR; 1293 sc->vge_tail->m_next = m; 1294 } 1295 m = sc->vge_head; 1296 sc->vge_head = sc->vge_tail = NULL; 1297 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1298 } else 1299 m->m_pkthdr.len = m->m_len = 1300 (total_len - ETHER_CRC_LEN); 1301 1302 #ifdef VGE_FIXUP_RX 1303 vge_fixup_rx(m); 1304 #endif 1305 ifp->if_ipackets++; 1306 m->m_pkthdr.rcvif = ifp; 1307 1308 /* Do RX checksumming if enabled */ 1309 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1310 1311 /* Check IP header checksum */ 1312 if (rxctl & VGE_RDCTL_IPPKT) 1313 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1314 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1315 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1316 } 1317 1318 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1319 /* Check UDP checksum */ 1320 if (rxctl & VGE_RDCTL_TCPPKT) 1321 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1322 1323 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1324 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1325 } 1326 1327 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1328 /* Check UDP checksum */ 1329 if (rxctl & VGE_RDCTL_UDPPKT) 1330 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1331 1332 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1333 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1334 } 1335 1336 if (rxstat & VGE_RDSTS_VTAG) 1337 VLAN_INPUT_TAG(ifp, m, 1338 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1339 1340 #if NBPFILTER > 0 1341 /* 1342 * Handle BPF listeners. 1343 */ 1344 if (ifp->if_bpf) 1345 bpf_mtap(ifp->if_bpf, m); 1346 #endif 1347 1348 VGE_UNLOCK(sc); 1349 (*ifp->if_input)(ifp, m); 1350 VGE_LOCK(sc); 1351 1352 lim++; 1353 if (lim == VGE_RX_DESC_CNT) 1354 break; 1355 1356 } 1357 1358 /* Flush the RX DMA ring */ 1359 1360 bus_dmamap_sync(sc->vge_dmat, 1361 sc->vge_ldata.vge_rx_list_map, 1362 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1363 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1364 1365 sc->vge_ldata.vge_rx_prodidx = i; 1366 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1367 1368 1369 return; 1370 } 1371 1372 static void 1373 vge_txeof(sc) 1374 struct vge_softc *sc; 1375 { 1376 struct ifnet *ifp; 1377 u_int32_t txstat; 1378 int idx; 1379 1380 ifp = &sc->sc_ethercom.ec_if; 1381 idx = sc->vge_ldata.vge_tx_considx; 1382 1383 /* Invalidate the TX descriptor list */ 1384 1385 bus_dmamap_sync(sc->vge_dmat, 1386 sc->vge_ldata.vge_tx_list_map, 1387 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1388 BUS_DMASYNC_POSTREAD); 1389 1390 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1391 1392 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1393 if (txstat & VGE_TDSTS_OWN) 1394 break; 1395 1396 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1397 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1398 bus_dmamap_unload(sc->vge_dmat, 1399 sc->vge_ldata.vge_tx_dmamap[idx]); 1400 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1401 ifp->if_collisions++; 1402 if (txstat & VGE_TDSTS_TXERR) 1403 ifp->if_oerrors++; 1404 else 1405 ifp->if_opackets++; 1406 1407 sc->vge_ldata.vge_tx_free++; 1408 VGE_TX_DESC_INC(idx); 1409 } 1410 1411 /* No changes made to the TX ring, so no flush needed */ 1412 1413 if (idx != sc->vge_ldata.vge_tx_considx) { 1414 sc->vge_ldata.vge_tx_considx = idx; 1415 ifp->if_flags &= ~IFF_OACTIVE; 1416 ifp->if_timer = 0; 1417 } 1418 1419 /* 1420 * If not all descriptors have been released reaped yet, 1421 * reload the timer so that we will eventually get another 1422 * interrupt that will cause us to re-enter this routine. 1423 * This is done in case the transmitter has gone idle. 1424 */ 1425 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1426 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1427 } 1428 1429 return; 1430 } 1431 1432 static void 1433 vge_tick(xsc) 1434 void *xsc; 1435 { 1436 struct vge_softc *sc = xsc; 1437 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1438 struct mii_data *mii = &sc->sc_mii; 1439 int s; 1440 1441 s = splnet(); 1442 1443 VGE_LOCK(sc); 1444 1445 callout_schedule(&sc->vge_timeout, hz); 1446 1447 mii_tick(mii); 1448 if (sc->vge_link) { 1449 if (!(mii->mii_media_status & IFM_ACTIVE)) 1450 sc->vge_link = 0; 1451 } else { 1452 if (mii->mii_media_status & IFM_ACTIVE && 1453 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1454 sc->vge_link = 1; 1455 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1456 vge_start(ifp); 1457 } 1458 } 1459 1460 VGE_UNLOCK(sc); 1461 1462 splx(s); 1463 } 1464 1465 #ifdef DEVICE_POLLING 1466 static void 1467 vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1468 { 1469 struct vge_softc *sc = ifp->if_softc; 1470 1471 VGE_LOCK(sc); 1472 #ifdef IFCAP_POLLING 1473 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1474 ether_poll_deregister(ifp); 1475 cmd = POLL_DEREGISTER; 1476 } 1477 #endif 1478 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1479 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1480 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1481 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1482 goto done; 1483 } 1484 1485 sc->rxcycles = count; 1486 vge_rxeof(sc); 1487 vge_txeof(sc); 1488 1489 #if __FreeBSD_version < 502114 1490 if (ifp->if_snd.ifq_head != NULL) 1491 #else 1492 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1493 #endif 1494 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1495 1496 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1497 u_int32_t status; 1498 status = CSR_READ_4(sc, VGE_ISR); 1499 if (status == 0xFFFFFFFF) 1500 goto done; 1501 if (status) 1502 CSR_WRITE_4(sc, VGE_ISR, status); 1503 1504 /* 1505 * XXX check behaviour on receiver stalls. 1506 */ 1507 1508 if (status & VGE_ISR_TXDMA_STALL || 1509 status & VGE_ISR_RXDMA_STALL) 1510 vge_init(sc); 1511 1512 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1513 vge_rxeof(sc); 1514 ifp->if_ierrors++; 1515 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1516 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1517 } 1518 } 1519 done: 1520 VGE_UNLOCK(sc); 1521 } 1522 #endif /* DEVICE_POLLING */ 1523 1524 static int 1525 vge_intr(arg) 1526 void *arg; 1527 { 1528 struct vge_softc *sc = arg; 1529 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1530 u_int32_t status; 1531 int claim = 0; 1532 1533 if (sc->suspended) { 1534 return claim; 1535 } 1536 1537 VGE_LOCK(sc); 1538 1539 if (!(ifp->if_flags & IFF_UP)) { 1540 VGE_UNLOCK(sc); 1541 return claim; 1542 } 1543 1544 #ifdef DEVICE_POLLING 1545 if (ifp->if_flags & IFF_POLLING) 1546 goto done; 1547 if ( 1548 #ifdef IFCAP_POLLING 1549 (ifp->if_capenable & IFCAP_POLLING) && 1550 #endif 1551 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1552 CSR_WRITE_4(sc, VGE_IMR, 0); 1553 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1554 vge_poll(ifp, 0, 1); 1555 goto done; 1556 } 1557 1558 #endif /* DEVICE_POLLING */ 1559 1560 /* Disable interrupts */ 1561 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1562 1563 for (;;) { 1564 1565 status = CSR_READ_4(sc, VGE_ISR); 1566 /* If the card has gone away the read returns 0xffff. */ 1567 if (status == 0xFFFFFFFF) 1568 break; 1569 1570 if (status) { 1571 claim = 1; 1572 CSR_WRITE_4(sc, VGE_ISR, status); 1573 } 1574 1575 if ((status & VGE_INTRS) == 0) 1576 break; 1577 1578 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1579 vge_rxeof(sc); 1580 1581 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1582 vge_rxeof(sc); 1583 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1584 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1585 } 1586 1587 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1588 vge_txeof(sc); 1589 1590 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1591 vge_init(ifp); 1592 1593 if (status & VGE_ISR_LINKSTS) 1594 vge_tick(sc); 1595 } 1596 1597 /* Re-enable interrupts */ 1598 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1599 1600 #ifdef DEVICE_POLLING 1601 done: 1602 #endif 1603 VGE_UNLOCK(sc); 1604 1605 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1606 vge_start(ifp); 1607 1608 return claim; 1609 } 1610 1611 static int 1612 vge_encap(sc, m_head, idx) 1613 struct vge_softc *sc; 1614 struct mbuf *m_head; 1615 int idx; 1616 { 1617 struct mbuf *m_new = NULL; 1618 bus_dmamap_t map; 1619 int error, flags; 1620 struct m_tag *mtag; 1621 1622 /* If this descriptor is still owned by the chip, bail. */ 1623 if (sc->vge_ldata.vge_tx_free <= 2 1624 || le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts) & VGE_TDSTS_OWN) 1625 return (ENOBUFS); 1626 1627 flags = 0; 1628 1629 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1630 flags |= VGE_TDCTL_IPCSUM; 1631 if (m_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1632 flags |= VGE_TDCTL_TCPCSUM; 1633 if (m_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1634 flags |= VGE_TDCTL_UDPCSUM; 1635 1636 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1637 error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1638 m_head, BUS_DMA_NOWAIT); 1639 1640 /* If too many segments to map, coalesce */ 1641 if (error == EFBIG) { 1642 m_new = m_defrag(m_head, M_DONTWAIT); 1643 if (m_new == NULL) 1644 return (error); 1645 1646 error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1647 m_new, BUS_DMA_NOWAIT); 1648 if (error) { 1649 m_freem(m_new); 1650 return (error); 1651 } 1652 1653 m_head = m_new; 1654 } else if (error) 1655 return (error); 1656 1657 vge_dma_map_tx_desc(sc, m_head, idx, flags); 1658 1659 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1660 sc->vge_ldata.vge_tx_free--; 1661 1662 /* 1663 * Set up hardware VLAN tagging. 1664 */ 1665 1666 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1667 if (mtag != NULL) 1668 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1669 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1670 1671 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1672 1673 return (0); 1674 } 1675 1676 /* 1677 * Main transmit routine. 1678 */ 1679 1680 static void 1681 vge_start(ifp) 1682 struct ifnet *ifp; 1683 { 1684 struct vge_softc *sc; 1685 struct mbuf *m_head = NULL; 1686 int idx, pidx = 0, error; 1687 1688 sc = ifp->if_softc; 1689 VGE_LOCK(sc); 1690 1691 if (!sc->vge_link 1692 || (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1693 VGE_UNLOCK(sc); 1694 return; 1695 } 1696 1697 idx = sc->vge_ldata.vge_tx_prodidx; 1698 1699 pidx = idx - 1; 1700 if (pidx < 0) 1701 pidx = VGE_TX_DESC_CNT - 1; 1702 1703 /* 1704 * Loop through the send queue, setting up transmit descriptors 1705 * until we drain the queue, or use up all available transmit 1706 * descriptors. 1707 */ 1708 for(;;) { 1709 /* Grab a packet off the queue. */ 1710 IFQ_POLL(&ifp->if_snd, m_head); 1711 if (m_head == NULL) 1712 break; 1713 1714 if (sc->vge_ldata.vge_tx_mbuf[idx] != NULL) { 1715 /* 1716 * Slot already used, stop for now. 1717 */ 1718 ifp->if_flags |= IFF_OACTIVE; 1719 break; 1720 } 1721 1722 if ((error = vge_encap(sc, m_head, idx))) { 1723 if (error == EFBIG) { 1724 printf("%s: Tx packet consumes too many " 1725 "DMA segments, dropping...\n", 1726 sc->sc_dev.dv_xname); 1727 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1728 m_freem(m_head); 1729 continue; 1730 } 1731 1732 /* 1733 * Short on resources, just stop for now. 1734 */ 1735 if (error == ENOBUFS) 1736 ifp->if_flags |= IFF_OACTIVE; 1737 break; 1738 } 1739 1740 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1741 1742 /* 1743 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1744 */ 1745 1746 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1747 htole16(VGE_TXDESC_Q); 1748 1749 if (sc->vge_ldata.vge_tx_mbuf[idx] != m_head) { 1750 m_freem(m_head); 1751 m_head = sc->vge_ldata.vge_tx_mbuf[idx]; 1752 } 1753 1754 pidx = idx; 1755 VGE_TX_DESC_INC(idx); 1756 1757 /* 1758 * If there's a BPF listener, bounce a copy of this frame 1759 * to him. 1760 */ 1761 #if NBPFILTER > 0 1762 if (ifp->if_bpf) 1763 bpf_mtap(ifp->if_bpf, m_head); 1764 #endif 1765 } 1766 1767 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1768 VGE_UNLOCK(sc); 1769 return; 1770 } 1771 1772 /* Flush the TX descriptors */ 1773 1774 bus_dmamap_sync(sc->vge_dmat, 1775 sc->vge_ldata.vge_tx_list_map, 1776 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1777 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1778 1779 /* Issue a transmit command. */ 1780 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1781 1782 sc->vge_ldata.vge_tx_prodidx = idx; 1783 1784 /* 1785 * Use the countdown timer for interrupt moderation. 1786 * 'TX done' interrupts are disabled. Instead, we reset the 1787 * countdown timer, which will begin counting until it hits 1788 * the value in the SSTIMER register, and then trigger an 1789 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1790 * the timer count is reloaded. Only when the transmitter 1791 * is idle will the timer hit 0 and an interrupt fire. 1792 */ 1793 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1794 1795 VGE_UNLOCK(sc); 1796 1797 /* 1798 * Set a timeout in case the chip goes out to lunch. 1799 */ 1800 ifp->if_timer = 5; 1801 1802 return; 1803 } 1804 1805 static int 1806 vge_init(ifp) 1807 struct ifnet *ifp; 1808 { 1809 struct vge_softc *sc = ifp->if_softc; 1810 struct mii_data *mii = &sc->sc_mii; 1811 int i; 1812 1813 VGE_LOCK(sc); 1814 1815 /* 1816 * Cancel pending I/O and free all RX/TX buffers. 1817 */ 1818 vge_stop(sc); 1819 vge_reset(sc); 1820 1821 /* 1822 * Initialize the RX and TX descriptors and mbufs. 1823 */ 1824 1825 vge_rx_list_init(sc); 1826 vge_tx_list_init(sc); 1827 1828 /* Set our station address */ 1829 for (i = 0; i < ETHER_ADDR_LEN; i++) 1830 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->vge_eaddr[i]); 1831 1832 /* 1833 * Set receive FIFO threshold. Also allow transmission and 1834 * reception of VLAN tagged frames. 1835 */ 1836 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1837 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1838 1839 /* Set DMA burst length */ 1840 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1841 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1842 1843 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1844 1845 /* Set collision backoff algorithm */ 1846 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1847 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1848 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1849 1850 /* Disable LPSEL field in priority resolution */ 1851 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1852 1853 /* 1854 * Load the addresses of the DMA queues into the chip. 1855 * Note that we only use one transmit queue. 1856 */ 1857 1858 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1859 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1860 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1861 1862 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1863 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1864 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1865 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1866 1867 /* Enable and wake up the RX descriptor queue */ 1868 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1869 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1870 1871 /* Enable the TX descriptor queue */ 1872 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1873 1874 /* Set up the receive filter -- allow large frames for VLANs. */ 1875 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1876 1877 /* If we want promiscuous mode, set the allframes bit. */ 1878 if (ifp->if_flags & IFF_PROMISC) { 1879 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1880 } 1881 1882 /* Set capture broadcast bit to capture broadcast frames. */ 1883 if (ifp->if_flags & IFF_BROADCAST) { 1884 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1885 } 1886 1887 /* Set multicast bit to capture multicast frames. */ 1888 if (ifp->if_flags & IFF_MULTICAST) { 1889 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1890 } 1891 1892 /* Init the cam filter. */ 1893 vge_cam_clear(sc); 1894 1895 /* Init the multicast filter. */ 1896 vge_setmulti(sc); 1897 1898 /* Enable flow control */ 1899 1900 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1901 1902 /* Enable jumbo frame reception (if desired) */ 1903 1904 /* Start the MAC. */ 1905 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1906 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1907 CSR_WRITE_1(sc, VGE_CRS0, 1908 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1909 1910 /* 1911 * Configure one-shot timer for microsecond 1912 * resulution and load it for 500 usecs. 1913 */ 1914 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1915 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1916 1917 /* 1918 * Configure interrupt moderation for receive. Enable 1919 * the holdoff counter and load it, and set the RX 1920 * suppression count to the number of descriptors we 1921 * want to allow before triggering an interrupt. 1922 * The holdoff timer is in units of 20 usecs. 1923 */ 1924 1925 #ifdef notyet 1926 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1927 /* Select the interrupt holdoff timer page. */ 1928 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1929 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1930 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1931 1932 /* Enable use of the holdoff timer. */ 1933 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1934 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1935 1936 /* Select the RX suppression threshold page. */ 1937 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1938 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1939 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1940 1941 /* Restore the page select bits. */ 1942 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1943 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1944 #endif 1945 1946 #ifdef DEVICE_POLLING 1947 /* 1948 * Disable interrupts if we are polling. 1949 */ 1950 if (ifp->if_flags & IFF_POLLING) { 1951 CSR_WRITE_4(sc, VGE_IMR, 0); 1952 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1953 } else /* otherwise ... */ 1954 #endif /* DEVICE_POLLING */ 1955 { 1956 /* 1957 * Enable interrupts. 1958 */ 1959 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1960 CSR_WRITE_4(sc, VGE_ISR, 0); 1961 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1962 } 1963 1964 mii_mediachg(mii); 1965 1966 ifp->if_flags |= IFF_RUNNING; 1967 ifp->if_flags &= ~IFF_OACTIVE; 1968 1969 sc->vge_if_flags = 0; 1970 sc->vge_link = 0; 1971 1972 VGE_UNLOCK(sc); 1973 1974 callout_schedule(&sc->vge_timeout, hz); 1975 1976 return (0); 1977 } 1978 1979 /* 1980 * Set media options. 1981 */ 1982 static int 1983 vge_ifmedia_upd(ifp) 1984 struct ifnet *ifp; 1985 { 1986 struct vge_softc *sc = ifp->if_softc; 1987 struct mii_data *mii = &sc->sc_mii; 1988 1989 mii_mediachg(mii); 1990 1991 return (0); 1992 } 1993 1994 /* 1995 * Report current media status. 1996 */ 1997 static void 1998 vge_ifmedia_sts(ifp, ifmr) 1999 struct ifnet *ifp; 2000 struct ifmediareq *ifmr; 2001 { 2002 struct vge_softc *sc = ifp->if_softc; 2003 struct mii_data *mii = &sc->sc_mii; 2004 2005 mii_pollstat(mii); 2006 ifmr->ifm_active = mii->mii_media_active; 2007 ifmr->ifm_status = mii->mii_media_status; 2008 2009 return; 2010 } 2011 2012 static void 2013 vge_miibus_statchg(self) 2014 struct device *self; 2015 { 2016 struct vge_softc *sc = (struct vge_softc *) self; 2017 struct mii_data *mii = &sc->sc_mii; 2018 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 2019 2020 /* 2021 * If the user manually selects a media mode, we need to turn 2022 * on the forced MAC mode bit in the DIAGCTL register. If the 2023 * user happens to choose a full duplex mode, we also need to 2024 * set the 'force full duplex' bit. This applies only to 2025 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2026 * mode is disabled, and in 1000baseT mode, full duplex is 2027 * always implied, so we turn on the forced mode bit but leave 2028 * the FDX bit cleared. 2029 */ 2030 2031 switch (IFM_SUBTYPE(ife->ifm_media)) { 2032 case IFM_AUTO: 2033 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2034 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2035 break; 2036 case IFM_1000_T: 2037 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2038 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2039 break; 2040 case IFM_100_TX: 2041 case IFM_10_T: 2042 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2043 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2044 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2045 } else { 2046 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2047 } 2048 break; 2049 default: 2050 printf("%s: unknown media type: %x\n", 2051 sc->sc_dev.dv_xname, 2052 IFM_SUBTYPE(ife->ifm_media)); 2053 break; 2054 } 2055 2056 return; 2057 } 2058 2059 static int 2060 vge_ioctl(ifp, command, data) 2061 struct ifnet *ifp; 2062 u_long command; 2063 caddr_t data; 2064 { 2065 struct vge_softc *sc = ifp->if_softc; 2066 struct ifreq *ifr = (struct ifreq *) data; 2067 struct mii_data *mii; 2068 int s, error = 0; 2069 2070 s = splnet(); 2071 2072 switch (command) { 2073 case SIOCSIFMTU: 2074 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2075 error = EINVAL; 2076 ifp->if_mtu = ifr->ifr_mtu; 2077 break; 2078 case SIOCSIFFLAGS: 2079 if (ifp->if_flags & IFF_UP) { 2080 if (ifp->if_flags & IFF_RUNNING && 2081 ifp->if_flags & IFF_PROMISC && 2082 !(sc->vge_if_flags & IFF_PROMISC)) { 2083 CSR_SETBIT_1(sc, VGE_RXCTL, 2084 VGE_RXCTL_RX_PROMISC); 2085 vge_setmulti(sc); 2086 } else if (ifp->if_flags & IFF_RUNNING && 2087 !(ifp->if_flags & IFF_PROMISC) && 2088 sc->vge_if_flags & IFF_PROMISC) { 2089 CSR_CLRBIT_1(sc, VGE_RXCTL, 2090 VGE_RXCTL_RX_PROMISC); 2091 vge_setmulti(sc); 2092 } else 2093 vge_init(ifp); 2094 } else { 2095 if (ifp->if_flags & IFF_RUNNING) 2096 vge_stop(sc); 2097 } 2098 sc->vge_if_flags = ifp->if_flags; 2099 break; 2100 case SIOCADDMULTI: 2101 case SIOCDELMULTI: 2102 error = (command == SIOCADDMULTI) ? 2103 ether_addmulti(ifr, &sc->sc_ethercom) : 2104 ether_delmulti(ifr, &sc->sc_ethercom); 2105 2106 if (error == ENETRESET) { 2107 /* 2108 * Multicast list has changed; set the hardware filter 2109 * accordingly. 2110 */ 2111 if (ifp->if_flags & IFF_RUNNING) 2112 vge_setmulti(sc); 2113 error = 0; 2114 } 2115 break; 2116 case SIOCGIFMEDIA: 2117 case SIOCSIFMEDIA: 2118 mii = &sc->sc_mii; 2119 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2120 break; 2121 default: 2122 error = ether_ioctl(ifp, command, data); 2123 break; 2124 } 2125 2126 splx(s); 2127 return (error); 2128 } 2129 2130 static void 2131 vge_watchdog(ifp) 2132 struct ifnet *ifp; 2133 { 2134 struct vge_softc *sc; 2135 2136 sc = ifp->if_softc; 2137 VGE_LOCK(sc); 2138 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2139 ifp->if_oerrors++; 2140 2141 vge_txeof(sc); 2142 vge_rxeof(sc); 2143 2144 vge_init(ifp); 2145 2146 VGE_UNLOCK(sc); 2147 2148 return; 2149 } 2150 2151 /* 2152 * Stop the adapter and free any mbufs allocated to the 2153 * RX and TX lists. 2154 */ 2155 static void 2156 vge_stop(sc) 2157 struct vge_softc *sc; 2158 { 2159 register int i; 2160 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2161 2162 VGE_LOCK(sc); 2163 ifp->if_timer = 0; 2164 2165 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2166 #ifdef DEVICE_POLLING 2167 ether_poll_deregister(ifp); 2168 #endif /* DEVICE_POLLING */ 2169 2170 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2171 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2172 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2173 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2174 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2175 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2176 2177 if (sc->vge_head != NULL) { 2178 m_freem(sc->vge_head); 2179 sc->vge_head = sc->vge_tail = NULL; 2180 } 2181 2182 /* Free the TX list buffers. */ 2183 2184 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2185 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2186 bus_dmamap_unload(sc->vge_dmat, 2187 sc->vge_ldata.vge_tx_dmamap[i]); 2188 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2189 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2190 } 2191 } 2192 2193 /* Free the RX list buffers. */ 2194 2195 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2196 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2197 bus_dmamap_unload(sc->vge_dmat, 2198 sc->vge_ldata.vge_rx_dmamap[i]); 2199 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2200 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2201 } 2202 } 2203 2204 VGE_UNLOCK(sc); 2205 2206 return; 2207 } 2208 2209 #if VGE_POWER_MANAGEMENT 2210 /* 2211 * Device suspend routine. Stop the interface and save some PCI 2212 * settings in case the BIOS doesn't restore them properly on 2213 * resume. 2214 */ 2215 static int 2216 vge_suspend(dev) 2217 struct device * dev; 2218 { 2219 struct vge_softc *sc; 2220 int i; 2221 2222 sc = device_get_softc(dev); 2223 2224 vge_stop(sc); 2225 2226 for (i = 0; i < 5; i++) 2227 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2228 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2229 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2230 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2231 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2232 2233 sc->suspended = 1; 2234 2235 return (0); 2236 } 2237 2238 /* 2239 * Device resume routine. Restore some PCI settings in case the BIOS 2240 * doesn't, re-enable busmastering, and restart the interface if 2241 * appropriate. 2242 */ 2243 static int 2244 vge_resume(dev) 2245 struct device * dev; 2246 { 2247 struct vge_softc *sc = (struct vge_softc *)dev; 2248 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2249 int i; 2250 2251 /* better way to do this? */ 2252 for (i = 0; i < 5; i++) 2253 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2254 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2255 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2256 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2257 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2258 2259 /* reenable busmastering */ 2260 pci_enable_busmaster(dev); 2261 pci_enable_io(dev, SYS_RES_MEMORY); 2262 2263 /* reinitialize interface if necessary */ 2264 if (ifp->if_flags & IFF_UP) 2265 vge_init(sc); 2266 2267 sc->suspended = 0; 2268 2269 return (0); 2270 } 2271 #endif 2272 2273 /* 2274 * Stop all chip I/O so that the kernel's probe routines don't 2275 * get confused by errant DMAs when rebooting. 2276 */ 2277 static void 2278 vge_shutdown(arg) 2279 void *arg; 2280 { 2281 struct vge_softc *sc = (struct vge_softc *)arg; 2282 2283 vge_stop(sc); 2284 } 2285
Indexes created Tue Oct 14 11:09:46 GMT 2025