if_vge.c revision 1.85
1 /* $NetBSD: if_vge.c,v 1.85 2022/09/17 15:44:15 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.85 2022/09/17 15:44:15 thorpej Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul (at) windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers (VGE_DATABUF_HIADDR). If you only have a 32-bit system, 79 * then this isn't an issue, but if you have a 64-bit system and more than 80 * 4GB of memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Furthermore, the descriptors must also all reside within the same 32-bit 84 * 'segment' (see VGE_TXDESC_HIADDR). 85 * 86 * Special thanks to Ryan Fu at VIA Networking for providing documentation 87 * and sample NICs for testing. 88 */ 89 90 91 #include <sys/param.h> 92 #include <sys/endian.h> 93 #include <sys/systm.h> 94 #include <sys/device.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/if_ether.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #include <sys/bus.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 #include <dev/pci/pcireg.h> 115 #include <dev/pci/pcivar.h> 116 #include <dev/pci/pcidevs.h> 117 118 #include <dev/pci/if_vgereg.h> 119 120 #define VGE_IFQ_MAXLEN 64 121 122 #define VGE_RING_ALIGN 256 123 124 #define VGE_NTXDESC 256 125 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1) 126 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK) 127 #define VGE_PREV_TXDESC(x) ((x - 1) & VGE_NTXDESC_MASK) 128 129 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */ 130 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1) 131 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK) 132 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK) 133 134 #define VGE_ADDR_LO(y) BUS_ADDR_LO32(y) 135 #define VGE_ADDR_HI(y) BUS_ADDR_HI32(y) 136 #define VGE_BUFLEN(y) ((y) & 0x7FFF) 137 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 138 139 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */ 140 141 /* 142 * Mbuf adjust factor to force 32-bit alignment of IP header. 143 * Drivers should pad ETHER_ALIGN bytes when setting up a 144 * RX mbuf so the upper layers get the IP header properly aligned 145 * past the 14-byte Ethernet header. 146 * 147 * See also comment in vge_encap(). 148 */ 149 150 #ifdef __NO_STRICT_ALIGNMENT 151 #define VGE_RX_BUFSIZE MCLBYTES 152 #else 153 #define VGE_RX_PAD sizeof(uint32_t) 154 #define VGE_RX_BUFSIZE (MCLBYTES - VGE_RX_PAD) 155 #endif 156 157 /* 158 * Control structures are DMA'd to the vge chip. We allocate them in 159 * a single clump that maps to a single DMA segment to make several things 160 * easier. 161 */ 162 struct vge_control_data { 163 /* TX descriptors */ 164 struct vge_txdesc vcd_txdescs[VGE_NTXDESC]; 165 /* RX descriptors */ 166 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC]; 167 /* dummy data for TX padding */ 168 uint8_t vcd_pad[ETHER_PAD_LEN]; 169 }; 170 171 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x) 172 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)]) 173 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)]) 174 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0]) 175 176 /* 177 * Software state for TX jobs. 178 */ 179 struct vge_txsoft { 180 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 181 bus_dmamap_t txs_dmamap; /* our DMA map */ 182 }; 183 184 /* 185 * Software state for RX jobs. 186 */ 187 struct vge_rxsoft { 188 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 189 bus_dmamap_t rxs_dmamap; /* our DMA map */ 190 }; 191 192 193 struct vge_softc { 194 device_t sc_dev; 195 196 bus_space_tag_t sc_bst; /* bus space tag */ 197 bus_space_handle_t sc_bsh; /* bus space handle */ 198 bus_dma_tag_t sc_dmat; 199 200 struct ethercom sc_ethercom; /* interface info */ 201 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 202 203 void *sc_intrhand; 204 struct mii_data sc_mii; 205 uint8_t sc_type; 206 u_short sc_if_flags; 207 int sc_link; 208 int sc_camidx; 209 callout_t sc_timeout; 210 211 bus_dmamap_t sc_cddmamap; 212 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 213 214 struct vge_txsoft sc_txsoft[VGE_NTXDESC]; 215 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC]; 216 struct vge_control_data *sc_control_data; 217 #define sc_txdescs sc_control_data->vcd_txdescs 218 #define sc_rxdescs sc_control_data->vcd_rxdescs 219 220 int sc_tx_prodidx; 221 int sc_tx_considx; 222 int sc_tx_free; 223 224 struct mbuf *sc_rx_mhead; 225 struct mbuf *sc_rx_mtail; 226 int sc_rx_prodidx; 227 int sc_rx_consumed; 228 229 int sc_suspended; /* 0 = normal 1 = suspended */ 230 uint32_t sc_saved_maps[5]; /* pci data */ 231 uint32_t sc_saved_biosaddr; 232 uint8_t sc_saved_intline; 233 uint8_t sc_saved_cachelnsz; 234 uint8_t sc_saved_lattimer; 235 }; 236 237 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x)) 238 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x)) 239 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF()) 240 241 #define VGE_TXDESCSYNC(sc, idx, ops) \ 242 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \ 243 VGE_CDTXOFF(idx), \ 244 offsetof(struct vge_txdesc, td_frag[0]), \ 245 (ops)) 246 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \ 247 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 248 VGE_CDTXOFF(idx) + \ 249 offsetof(struct vge_txdesc, td_frag[0]), \ 250 sizeof(struct vge_txfrag) * (nsegs), \ 251 (ops)) 252 #define VGE_RXDESCSYNC(sc, idx, ops) \ 253 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 254 VGE_CDRXOFF(idx), \ 255 sizeof(struct vge_rxdesc), \ 256 (ops)) 257 258 /* 259 * register space access macros 260 */ 261 #define CSR_WRITE_4(sc, reg, val) \ 262 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 263 #define CSR_WRITE_2(sc, reg, val) \ 264 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 265 #define CSR_WRITE_1(sc, reg, val) \ 266 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 267 268 #define CSR_READ_4(sc, reg) \ 269 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 270 #define CSR_READ_2(sc, reg) \ 271 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg)) 272 #define CSR_READ_1(sc, reg) \ 273 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 274 275 #define CSR_SETBIT_1(sc, reg, x) \ 276 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x)) 277 #define CSR_SETBIT_2(sc, reg, x) \ 278 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x)) 279 #define CSR_SETBIT_4(sc, reg, x) \ 280 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x)) 281 282 #define CSR_CLRBIT_1(sc, reg, x) \ 283 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x)) 284 #define CSR_CLRBIT_2(sc, reg, x) \ 285 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x)) 286 #define CSR_CLRBIT_4(sc, reg, x) \ 287 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x)) 288 289 #define VGE_TIMEOUT 10000 290 291 #define VGE_PCI_LOIO 0x10 292 #define VGE_PCI_LOMEM 0x14 293 294 static inline void vge_set_txaddr(struct vge_txfrag *, bus_addr_t); 295 static inline void vge_set_rxaddr(struct vge_rxdesc *, bus_addr_t); 296 297 static int vge_ifflags_cb(struct ethercom *); 298 299 static int vge_match(device_t, cfdata_t, void *); 300 static void vge_attach(device_t, device_t, void *); 301 302 static int vge_encap(struct vge_softc *, struct mbuf *, int); 303 304 static int vge_allocmem(struct vge_softc *); 305 static int vge_newbuf(struct vge_softc *, int, struct mbuf *); 306 #ifndef __NO_STRICT_ALIGNMENT 307 static inline void vge_fixup_rx(struct mbuf *); 308 #endif 309 static void vge_rxeof(struct vge_softc *); 310 static void vge_txeof(struct vge_softc *); 311 static int vge_intr(void *); 312 static void vge_tick(void *); 313 static void vge_start(struct ifnet *); 314 static int vge_ioctl(struct ifnet *, u_long, void *); 315 static int vge_init(struct ifnet *); 316 static void vge_stop(struct ifnet *, int); 317 static void vge_watchdog(struct ifnet *); 318 #if VGE_POWER_MANAGEMENT 319 static int vge_suspend(device_t); 320 static int vge_resume(device_t); 321 #endif 322 static bool vge_shutdown(device_t, int); 323 324 static uint16_t vge_read_eeprom(struct vge_softc *, int); 325 326 static void vge_miipoll_start(struct vge_softc *); 327 static void vge_miipoll_stop(struct vge_softc *); 328 static int vge_miibus_readreg(device_t, int, int, uint16_t *); 329 static int vge_miibus_writereg(device_t, int, int, uint16_t); 330 static void vge_miibus_statchg(struct ifnet *); 331 332 static void vge_cam_clear(struct vge_softc *); 333 static int vge_cam_set(struct vge_softc *, uint8_t *); 334 static void vge_clrwol(struct vge_softc *); 335 static void vge_setmulti(struct vge_softc *); 336 static void vge_reset(struct vge_softc *); 337 338 CFATTACH_DECL_NEW(vge, sizeof(struct vge_softc), 339 vge_match, vge_attach, NULL, NULL); 340 341 static inline void 342 vge_set_txaddr(struct vge_txfrag *f, bus_addr_t daddr) 343 { 344 345 f->tf_addrlo = htole32((uint32_t)daddr); 346 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 347 f->tf_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 348 else 349 f->tf_addrhi = 0; 350 } 351 352 static inline void 353 vge_set_rxaddr(struct vge_rxdesc *rxd, bus_addr_t daddr) 354 { 355 356 rxd->rd_addrlo = htole32((uint32_t)daddr); 357 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 358 rxd->rd_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 359 else 360 rxd->rd_addrhi = 0; 361 } 362 363 /* 364 * Read a word of data stored in the EEPROM at address 'addr.' 365 */ 366 static uint16_t 367 vge_read_eeprom(struct vge_softc *sc, int addr) 368 { 369 int i; 370 uint16_t word = 0; 371 372 /* 373 * Enter EEPROM embedded programming mode. In order to 374 * access the EEPROM at all, we first have to set the 375 * EELOAD bit in the CHIPCFG2 register. 376 */ 377 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 378 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*| VGE_EECSR_ECS*/); 379 380 /* Select the address of the word we want to read */ 381 CSR_WRITE_1(sc, VGE_EEADDR, addr); 382 383 /* Issue read command */ 384 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 385 386 /* Wait for the done bit to be set. */ 387 for (i = 0; i < VGE_TIMEOUT; i++) { 388 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 389 break; 390 } 391 392 if (i == VGE_TIMEOUT) { 393 printf("%s: EEPROM read timed out\n", device_xname(sc->sc_dev)); 394 return 0; 395 } 396 397 /* Read the result */ 398 word = CSR_READ_2(sc, VGE_EERDDAT); 399 400 /* Turn off EEPROM access mode. */ 401 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*| VGE_EECSR_ECS*/); 402 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 403 404 return word; 405 } 406 407 static void 408 vge_miipoll_stop(struct vge_softc *sc) 409 { 410 int i; 411 412 CSR_WRITE_1(sc, VGE_MIICMD, 0); 413 414 for (i = 0; i < VGE_TIMEOUT; i++) { 415 DELAY(1); 416 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 417 break; 418 } 419 420 if (i == VGE_TIMEOUT) { 421 printf("%s: failed to idle MII autopoll\n", 422 device_xname(sc->sc_dev)); 423 } 424 } 425 426 static void 427 vge_miipoll_start(struct vge_softc *sc) 428 { 429 int i; 430 431 /* First, make sure we're idle. */ 432 433 CSR_WRITE_1(sc, VGE_MIICMD, 0); 434 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 435 436 for (i = 0; i < VGE_TIMEOUT; i++) { 437 DELAY(1); 438 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 439 break; 440 } 441 442 if (i == VGE_TIMEOUT) { 443 printf("%s: failed to idle MII autopoll\n", 444 device_xname(sc->sc_dev)); 445 return; 446 } 447 448 /* Now enable auto poll mode. */ 449 450 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 451 452 /* And make sure it started. */ 453 454 for (i = 0; i < VGE_TIMEOUT; i++) { 455 DELAY(1); 456 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 457 break; 458 } 459 460 if (i == VGE_TIMEOUT) { 461 printf("%s: failed to start MII autopoll\n", 462 device_xname(sc->sc_dev)); 463 } 464 } 465 466 static int 467 vge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 468 { 469 struct vge_softc *sc; 470 int i, s; 471 int rv = 0; 472 473 sc = device_private(dev); 474 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 475 return -1; 476 477 s = splnet(); 478 vge_miipoll_stop(sc); 479 480 /* Specify the register we want to read. */ 481 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 482 483 /* Issue read command. */ 484 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 485 486 /* Wait for the read command bit to self-clear. */ 487 for (i = 0; i < VGE_TIMEOUT; i++) { 488 DELAY(1); 489 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 490 break; 491 } 492 493 if (i == VGE_TIMEOUT) { 494 printf("%s: MII read timed out\n", device_xname(sc->sc_dev)); 495 rv = ETIMEDOUT; 496 } else 497 *val = CSR_READ_2(sc, VGE_MIIDATA); 498 499 vge_miipoll_start(sc); 500 splx(s); 501 502 return rv; 503 } 504 505 static int 506 vge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 507 { 508 struct vge_softc *sc; 509 int i, s, rv = 0; 510 511 sc = device_private(dev); 512 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 513 return -1; 514 515 s = splnet(); 516 vge_miipoll_stop(sc); 517 518 /* Specify the register we want to write. */ 519 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 520 521 /* Specify the data we want to write. */ 522 CSR_WRITE_2(sc, VGE_MIIDATA, val); 523 524 /* Issue write command. */ 525 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 526 527 /* Wait for the write command bit to self-clear. */ 528 for (i = 0; i < VGE_TIMEOUT; i++) { 529 DELAY(1); 530 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 531 break; 532 } 533 534 if (i == VGE_TIMEOUT) { 535 printf("%s: MII write timed out\n", device_xname(sc->sc_dev)); 536 rv = ETIMEDOUT; 537 } 538 539 vge_miipoll_start(sc); 540 splx(s); 541 542 return rv; 543 } 544 545 static void 546 vge_cam_clear(struct vge_softc *sc) 547 { 548 int i; 549 550 /* 551 * Turn off all the mask bits. This tells the chip 552 * that none of the entries in the CAM filter are valid. 553 * desired entries will be enabled as we fill the filter in. 554 */ 555 556 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 557 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 558 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 559 for (i = 0; i < 8; i++) 560 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 561 562 /* Clear the VLAN filter too. */ 563 564 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | VGE_CAMADDR_AVSEL); 565 for (i = 0; i < 8; i++) 566 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 567 568 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 569 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 570 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 571 572 sc->sc_camidx = 0; 573 } 574 575 static int 576 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 577 { 578 int i, error; 579 580 error = 0; 581 582 if (sc->sc_camidx == VGE_CAM_MAXADDRS) 583 return ENOSPC; 584 585 /* Select the CAM data page. */ 586 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 587 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 588 589 /* Set the filter entry we want to update and enable writing. */ 590 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx); 591 592 /* Write the address to the CAM registers */ 593 for (i = 0; i < ETHER_ADDR_LEN; i++) 594 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 595 596 /* Issue a write command. */ 597 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 598 599 /* Wake for it to clear. */ 600 for (i = 0; i < VGE_TIMEOUT; i++) { 601 DELAY(1); 602 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 603 break; 604 } 605 606 if (i == VGE_TIMEOUT) { 607 printf("%s: setting CAM filter failed\n", 608 device_xname(sc->sc_dev)); 609 error = EIO; 610 goto fail; 611 } 612 613 /* Select the CAM mask page. */ 614 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 615 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 616 617 /* Set the mask bit that enables this filter. */ 618 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8), 619 1 << (sc->sc_camidx & 7)); 620 621 sc->sc_camidx++; 622 623 fail: 624 /* Turn off access to CAM. */ 625 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 626 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 627 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 628 629 return error; 630 } 631 632 /* 633 * Program the multicast filter. We use the 64-entry CAM filter 634 * for perfect filtering. If there's more than 64 multicast addresses, 635 * we use the hash filter instead. 636 */ 637 static void 638 vge_setmulti(struct vge_softc *sc) 639 { 640 struct ethercom *ec = &sc->sc_ethercom; 641 struct ifnet *ifp = &ec->ec_if; 642 int error; 643 uint32_t h, hashes[2] = { 0, 0 }; 644 struct ether_multi *enm; 645 struct ether_multistep step; 646 647 error = 0; 648 649 /* First, zot all the multicast entries. */ 650 vge_cam_clear(sc); 651 CSR_WRITE_4(sc, VGE_MAR0, 0); 652 CSR_WRITE_4(sc, VGE_MAR1, 0); 653 ifp->if_flags &= ~IFF_ALLMULTI; 654 655 /* 656 * If the user wants allmulti or promisc mode, enable reception 657 * of all multicast frames. 658 */ 659 if (ifp->if_flags & IFF_PROMISC) { 660 allmulti: 661 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 662 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 663 ifp->if_flags |= IFF_ALLMULTI; 664 return; 665 } 666 667 /* Now program new ones */ 668 ETHER_LOCK(ec); 669 ETHER_FIRST_MULTI(step, ec, enm); 670 while (enm != NULL) { 671 /* 672 * If multicast range, fall back to ALLMULTI. 673 */ 674 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 675 ETHER_ADDR_LEN) != 0) { 676 ETHER_UNLOCK(ec); 677 goto allmulti; 678 } 679 680 error = vge_cam_set(sc, enm->enm_addrlo); 681 if (error) 682 break; 683 684 ETHER_NEXT_MULTI(step, enm); 685 } 686 ETHER_UNLOCK(ec); 687 688 /* If there were too many addresses, use the hash filter. */ 689 if (error) { 690 vge_cam_clear(sc); 691 692 ETHER_LOCK(ec); 693 ETHER_FIRST_MULTI(step, ec, enm); 694 while (enm != NULL) { 695 /* 696 * If multicast range, fall back to ALLMULTI. 697 */ 698 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 699 ETHER_ADDR_LEN) != 0) { 700 ETHER_UNLOCK(ec); 701 goto allmulti; 702 } 703 704 h = ether_crc32_be(enm->enm_addrlo, 705 ETHER_ADDR_LEN) >> 26; 706 hashes[h >> 5] |= 1 << (h & 0x1f); 707 708 ETHER_NEXT_MULTI(step, enm); 709 } 710 ETHER_UNLOCK(ec); 711 712 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 713 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 714 } 715 } 716 717 static void 718 vge_reset(struct vge_softc *sc) 719 { 720 int i; 721 722 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 723 724 for (i = 0; i < VGE_TIMEOUT; i++) { 725 DELAY(5); 726 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 727 break; 728 } 729 730 if (i == VGE_TIMEOUT) { 731 printf("%s: soft reset timed out", device_xname(sc->sc_dev)); 732 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 733 DELAY(2000); 734 } 735 736 DELAY(5000); 737 738 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 739 740 for (i = 0; i < VGE_TIMEOUT; i++) { 741 DELAY(5); 742 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 743 break; 744 } 745 746 if (i == VGE_TIMEOUT) { 747 printf("%s: EEPROM reload timed out\n", 748 device_xname(sc->sc_dev)); 749 return; 750 } 751 752 /* 753 * On some machine, the first read data from EEPROM could be 754 * messed up, so read one dummy data here to avoid the mess. 755 */ 756 (void)vge_read_eeprom(sc, 0); 757 758 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 759 } 760 761 /* 762 * Probe for a VIA gigabit chip. Check the PCI vendor and device 763 * IDs against our list and return a device name if we find a match. 764 */ 765 static int 766 vge_match(device_t parent, cfdata_t match, void *aux) 767 { 768 struct pci_attach_args *pa = aux; 769 770 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 771 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 772 return 1; 773 774 return 0; 775 } 776 777 static int 778 vge_allocmem(struct vge_softc *sc) 779 { 780 int error; 781 int nseg; 782 int i; 783 bus_dma_segment_t seg; 784 785 /* 786 * Allocate memory for control data. 787 * 788 * NOTE: This must all fit within the same 4GB segment. The 789 * "boundary" argument to bus_dmamem_alloc() will end up as 790 * 4GB on 64-bit platforms and 0 ("no boundary constraint") on 791 * 32-bit platformds. 792 */ 793 794 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data), 795 VGE_RING_ALIGN, 796 (bus_size_t)(1ULL << 32), 797 &seg, 1, &nseg, BUS_DMA_NOWAIT); 798 if (error) { 799 aprint_error_dev(sc->sc_dev, 800 "could not allocate control data dma memory\n"); 801 goto fail_1; 802 } 803 804 /* Map the memory to kernel VA space */ 805 806 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 807 sizeof(struct vge_control_data), (void **)&sc->sc_control_data, 808 BUS_DMA_NOWAIT); 809 if (error) { 810 aprint_error_dev(sc->sc_dev, 811 "could not map control data dma memory\n"); 812 goto fail_2; 813 } 814 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data)); 815 816 /* 817 * Create map for control data. 818 */ 819 error = bus_dmamap_create(sc->sc_dmat, 820 sizeof(struct vge_control_data), 1, 821 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT, 822 &sc->sc_cddmamap); 823 if (error) { 824 aprint_error_dev(sc->sc_dev, 825 "could not create control data dmamap\n"); 826 goto fail_3; 827 } 828 829 /* Load the map for the control data. */ 830 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 831 sc->sc_control_data, sizeof(struct vge_control_data), NULL, 832 BUS_DMA_NOWAIT); 833 if (error) { 834 aprint_error_dev(sc->sc_dev, 835 "could not load control data dma memory\n"); 836 goto fail_4; 837 } 838 839 /* Create DMA maps for TX buffers */ 840 841 for (i = 0; i < VGE_NTXDESC; i++) { 842 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN, 843 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT, 844 &sc->sc_txsoft[i].txs_dmamap); 845 if (error) { 846 aprint_error_dev(sc->sc_dev, 847 "can't create DMA map for TX descs\n"); 848 goto fail_5; 849 } 850 } 851 852 /* Create DMA maps for RX buffers */ 853 854 for (i = 0; i < VGE_NRXDESC; i++) { 855 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 856 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 857 &sc->sc_rxsoft[i].rxs_dmamap); 858 if (error) { 859 aprint_error_dev(sc->sc_dev, 860 "can't create DMA map for RX descs\n"); 861 goto fail_6; 862 } 863 sc->sc_rxsoft[i].rxs_mbuf = NULL; 864 } 865 866 return 0; 867 868 fail_6: 869 for (i = 0; i < VGE_NRXDESC; i++) { 870 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 871 bus_dmamap_destroy(sc->sc_dmat, 872 sc->sc_rxsoft[i].rxs_dmamap); 873 } 874 fail_5: 875 for (i = 0; i < VGE_NTXDESC; i++) { 876 if (sc->sc_txsoft[i].txs_dmamap != NULL) 877 bus_dmamap_destroy(sc->sc_dmat, 878 sc->sc_txsoft[i].txs_dmamap); 879 } 880 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 881 fail_4: 882 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 883 fail_3: 884 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 885 sizeof(struct vge_control_data)); 886 fail_2: 887 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 888 fail_1: 889 return ENOMEM; 890 } 891 892 /* 893 * Attach the interface. Allocate softc structures, do ifmedia 894 * setup and ethernet/BPF attach. 895 */ 896 static void 897 vge_attach(device_t parent, device_t self, void *aux) 898 { 899 uint8_t *eaddr; 900 struct vge_softc *sc = device_private(self); 901 struct ifnet *ifp; 902 struct mii_data * const mii = &sc->sc_mii; 903 struct pci_attach_args *pa = aux; 904 pci_chipset_tag_t pc = pa->pa_pc; 905 const char *intrstr; 906 pci_intr_handle_t ih; 907 uint16_t val; 908 char intrbuf[PCI_INTRSTR_LEN]; 909 910 sc->sc_dev = self; 911 912 pci_aprint_devinfo_fancy(pa, NULL, "VIA VT612X Gigabit Ethernet", 1); 913 914 /* Make sure bus-mastering is enabled */ 915 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 916 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 917 PCI_COMMAND_MASTER_ENABLE); 918 919 /* 920 * Map control/status registers. 921 */ 922 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 923 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) { 924 aprint_error_dev(self, "couldn't map memory\n"); 925 return; 926 } 927 928 /* 929 * Map and establish our interrupt. 930 */ 931 if (pci_intr_map(pa, &ih)) { 932 aprint_error_dev(self, "unable to map interrupt\n"); 933 return; 934 } 935 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 936 sc->sc_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, vge_intr, 937 sc, device_xname(self)); 938 if (sc->sc_intrhand == NULL) { 939 aprint_error_dev(self, "unable to establish interrupt"); 940 if (intrstr != NULL) 941 aprint_error(" at %s", intrstr); 942 aprint_error("\n"); 943 return; 944 } 945 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 946 947 /* Reset the adapter. */ 948 vge_reset(sc); 949 950 /* 951 * Get station address from the EEPROM. 952 */ 953 eaddr = sc->sc_eaddr; 954 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0); 955 eaddr[0] = val & 0xff; 956 eaddr[1] = val >> 8; 957 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1); 958 eaddr[2] = val & 0xff; 959 eaddr[3] = val >> 8; 960 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2); 961 eaddr[4] = val & 0xff; 962 eaddr[5] = val >> 8; 963 964 aprint_normal_dev(self, "Ethernet address %s\n", 965 ether_sprintf(eaddr)); 966 967 /* Clear WOL and take hardware from powerdown. */ 968 vge_clrwol(sc); 969 970 /* 971 * The hardware supports 64-bit DMA addresses, but it's a little 972 * complicated (see large comment about the hardware near the top 973 * of the file). TL;DR -- restrict ourselves to 48-bit. 974 */ 975 if (pci_dma64_available(pa)) { 976 if (bus_dmatag_subregion(pa->pa_dmat64, 977 0, 978 (bus_addr_t)__MASK(48), 979 &sc->sc_dmat, 980 BUS_DMA_WAITOK) != 0) { 981 aprint_error_dev(self, 982 "WARNING: failed to restrict dma range," 983 " falling back to parent bus dma range\n"); 984 sc->sc_dmat = pa->pa_dmat64; 985 } 986 } else { 987 sc->sc_dmat = pa->pa_dmat; 988 } 989 990 if (vge_allocmem(sc) != 0) 991 return; 992 993 ifp = &sc->sc_ethercom.ec_if; 994 ifp->if_softc = sc; 995 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 996 ifp->if_mtu = ETHERMTU; 997 ifp->if_baudrate = IF_Gbps(1); 998 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 999 ifp->if_ioctl = vge_ioctl; 1000 ifp->if_start = vge_start; 1001 ifp->if_init = vge_init; 1002 ifp->if_stop = vge_stop; 1003 1004 /* 1005 * We can support 802.1Q VLAN-sized frames and jumbo 1006 * Ethernet frames. 1007 */ 1008 sc->sc_ethercom.ec_capabilities |= 1009 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 1010 ETHERCAP_VLAN_HWTAGGING; 1011 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1012 1013 /* 1014 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 1015 */ 1016 ifp->if_capabilities |= 1017 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1018 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1019 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1020 1021 #ifdef DEVICE_POLLING 1022 #ifdef IFCAP_POLLING 1023 ifp->if_capabilities |= IFCAP_POLLING; 1024 #endif 1025 #endif 1026 ifp->if_watchdog = vge_watchdog; 1027 IFQ_SET_MAXLEN(&ifp->if_snd, uimax(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 1028 IFQ_SET_READY(&ifp->if_snd); 1029 1030 /* 1031 * Initialize our media structures and probe the MII. 1032 */ 1033 mii->mii_ifp = ifp; 1034 mii->mii_readreg = vge_miibus_readreg; 1035 mii->mii_writereg = vge_miibus_writereg; 1036 mii->mii_statchg = vge_miibus_statchg; 1037 1038 sc->sc_ethercom.ec_mii = mii; 1039 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1040 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1041 MII_OFFSET_ANY, MIIF_DOPAUSE); 1042 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1043 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1044 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1045 } else 1046 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1047 1048 /* 1049 * Attach the interface. 1050 */ 1051 if_attach(ifp); 1052 if_deferred_start_init(ifp, NULL); 1053 ether_ifattach(ifp, eaddr); 1054 ether_set_ifflags_cb(&sc->sc_ethercom, vge_ifflags_cb); 1055 1056 callout_init(&sc->sc_timeout, 0); 1057 callout_setfunc(&sc->sc_timeout, vge_tick, sc); 1058 1059 /* 1060 * Make sure the interface is shutdown during reboot. 1061 */ 1062 if (pmf_device_register1(self, NULL, NULL, vge_shutdown)) 1063 pmf_class_network_register(self, ifp); 1064 else 1065 aprint_error_dev(self, "couldn't establish power handler\n"); 1066 } 1067 1068 static int 1069 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 1070 { 1071 struct mbuf *m_new; 1072 struct vge_rxdesc *rxd; 1073 struct vge_rxsoft *rxs; 1074 bus_dmamap_t map; 1075 int i; 1076 #ifdef DIAGNOSTIC 1077 uint32_t rd_sts; 1078 #endif 1079 1080 m_new = NULL; 1081 if (m == NULL) { 1082 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1083 if (m_new == NULL) 1084 return ENOBUFS; 1085 1086 MCLGET(m_new, M_DONTWAIT); 1087 if ((m_new->m_flags & M_EXT) == 0) { 1088 m_freem(m_new); 1089 return ENOBUFS; 1090 } 1091 1092 m = m_new; 1093 } else 1094 m->m_data = m->m_ext.ext_buf; 1095 1096 1097 /* 1098 * This is part of an evil trick to deal with non-x86 platforms. 1099 * The VIA chip requires RX buffers to be aligned on 32-bit 1100 * boundaries, but that will hose non-x86 machines. To get around 1101 * this, we leave some empty space at the start of each buffer 1102 * and for non-x86 hosts, we copy the buffer back two bytes 1103 * to achieve word alignment. This is slightly more efficient 1104 * than allocating a new buffer, copying the contents, and 1105 * discarding the old buffer. 1106 */ 1107 m->m_len = m->m_pkthdr.len = VGE_RX_BUFSIZE; 1108 #ifndef __NO_STRICT_ALIGNMENT 1109 m->m_data += VGE_RX_PAD; 1110 #endif 1111 rxs = &sc->sc_rxsoft[idx]; 1112 map = rxs->rxs_dmamap; 1113 1114 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) 1115 goto out; 1116 1117 rxd = &sc->sc_rxdescs[idx]; 1118 1119 #ifdef DIAGNOSTIC 1120 /* If this descriptor is still owned by the chip, bail. */ 1121 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1122 rd_sts = le32toh(rxd->rd_sts); 1123 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1124 if (rd_sts & VGE_RDSTS_OWN) { 1125 panic("%s: tried to map busy RX descriptor", 1126 device_xname(sc->sc_dev)); 1127 } 1128 #endif 1129 1130 rxs->rxs_mbuf = m; 1131 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1132 BUS_DMASYNC_PREREAD); 1133 1134 rxd->rd_buflen = 1135 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I); 1136 vge_set_rxaddr(rxd, map->dm_segs[0].ds_addr); 1137 rxd->rd_sts = 0; 1138 rxd->rd_ctl = 0; 1139 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1140 1141 /* 1142 * Note: the manual fails to document the fact that for 1143 * proper operation, the driver needs to replentish the RX 1144 * DMA ring 4 descriptors at a time (rather than one at a 1145 * time, like most chips). We can allocate the new buffers 1146 * but we should not set the OWN bits until we're ready 1147 * to hand back 4 of them in one shot. 1148 */ 1149 1150 #define VGE_RXCHUNK 4 1151 sc->sc_rx_consumed++; 1152 if (sc->sc_rx_consumed == VGE_RXCHUNK) { 1153 for (i = idx; i != idx - VGE_RXCHUNK; i--) { 1154 KASSERT(i >= 0); 1155 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN); 1156 VGE_RXDESCSYNC(sc, i, 1157 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1158 } 1159 sc->sc_rx_consumed = 0; 1160 } 1161 1162 return 0; 1163 out: 1164 if (m_new != NULL) 1165 m_freem(m_new); 1166 return ENOMEM; 1167 } 1168 1169 #ifndef __NO_STRICT_ALIGNMENT 1170 static inline void 1171 vge_fixup_rx(struct mbuf *m) 1172 { 1173 int i; 1174 uint16_t *src, *dst; 1175 1176 src = mtod(m, uint16_t *); 1177 dst = src - 1; 1178 1179 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1180 *dst++ = *src++; 1181 1182 m->m_data -= ETHER_ALIGN; 1183 } 1184 #endif 1185 1186 /* 1187 * RX handler. We support the reception of jumbo frames that have 1188 * been fragmented across multiple 2K mbuf cluster buffers. 1189 */ 1190 static void 1191 vge_rxeof(struct vge_softc *sc) 1192 { 1193 struct mbuf *m; 1194 struct ifnet *ifp; 1195 int idx, total_len, lim; 1196 struct vge_rxdesc *cur_rxd; 1197 struct vge_rxsoft *rxs; 1198 uint32_t rxstat, rxctl; 1199 1200 ifp = &sc->sc_ethercom.ec_if; 1201 lim = 0; 1202 1203 /* Invalidate the descriptor memory */ 1204 1205 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) { 1206 cur_rxd = &sc->sc_rxdescs[idx]; 1207 1208 VGE_RXDESCSYNC(sc, idx, 1209 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1210 rxstat = le32toh(cur_rxd->rd_sts); 1211 if ((rxstat & VGE_RDSTS_OWN) != 0) { 1212 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1213 break; 1214 } 1215 1216 rxctl = le32toh(cur_rxd->rd_ctl); 1217 rxs = &sc->sc_rxsoft[idx]; 1218 m = rxs->rxs_mbuf; 1219 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16; 1220 1221 /* Invalidate the RX mbuf and unload its map */ 1222 1223 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 1224 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1225 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1226 1227 /* 1228 * If the 'start of frame' bit is set, this indicates 1229 * either the first fragment in a multi-fragment receive, 1230 * or an intermediate fragment. Either way, we want to 1231 * accumulate the buffers. 1232 */ 1233 if (rxstat & VGE_RXPKT_SOF) { 1234 m->m_len = VGE_RX_BUFSIZE; 1235 if (sc->sc_rx_mhead == NULL) 1236 sc->sc_rx_mhead = sc->sc_rx_mtail = m; 1237 else { 1238 m->m_flags &= ~M_PKTHDR; 1239 sc->sc_rx_mtail->m_next = m; 1240 sc->sc_rx_mtail = m; 1241 } 1242 vge_newbuf(sc, idx, NULL); 1243 continue; 1244 } 1245 1246 /* 1247 * Bad/error frames will have the RXOK bit cleared. 1248 * However, there's one error case we want to allow: 1249 * if a VLAN tagged frame arrives and the chip can't 1250 * match it against the CAM filter, it considers this 1251 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1252 * We don't want to drop the frame though: our VLAN 1253 * filtering is done in software. 1254 */ 1255 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1256 (rxstat & VGE_RDSTS_VIDM) == 0 && 1257 (rxstat & VGE_RDSTS_CSUMERR) == 0) { 1258 if_statinc(ifp, if_ierrors); 1259 /* 1260 * If this is part of a multi-fragment packet, 1261 * discard all the pieces. 1262 */ 1263 if (sc->sc_rx_mhead != NULL) { 1264 m_freem(sc->sc_rx_mhead); 1265 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1266 } 1267 vge_newbuf(sc, idx, m); 1268 continue; 1269 } 1270 1271 /* 1272 * If allocating a replacement mbuf fails, 1273 * reload the current one. 1274 */ 1275 1276 if (vge_newbuf(sc, idx, NULL)) { 1277 if_statinc(ifp, if_ierrors); 1278 if (sc->sc_rx_mhead != NULL) { 1279 m_freem(sc->sc_rx_mhead); 1280 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1281 } 1282 vge_newbuf(sc, idx, m); 1283 continue; 1284 } 1285 1286 if (sc->sc_rx_mhead != NULL) { 1287 m->m_len = total_len % VGE_RX_BUFSIZE; 1288 /* 1289 * Special case: if there's 4 bytes or less 1290 * in this buffer, the mbuf can be discarded: 1291 * the last 4 bytes is the CRC, which we don't 1292 * care about anyway. 1293 */ 1294 if (m->m_len <= ETHER_CRC_LEN) { 1295 sc->sc_rx_mtail->m_len -= 1296 (ETHER_CRC_LEN - m->m_len); 1297 m_freem(m); 1298 } else { 1299 m->m_len -= ETHER_CRC_LEN; 1300 m->m_flags &= ~M_PKTHDR; 1301 sc->sc_rx_mtail->m_next = m; 1302 } 1303 m = sc->sc_rx_mhead; 1304 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1305 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1306 } else 1307 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1308 1309 #ifndef __NO_STRICT_ALIGNMENT 1310 vge_fixup_rx(m); 1311 #endif 1312 m_set_rcvif(m, ifp); 1313 1314 /* Do RX checksumming if enabled */ 1315 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1316 1317 /* Check IP header checksum */ 1318 if (rxctl & VGE_RDCTL_IPPKT) 1319 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1320 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1321 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1322 } 1323 1324 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1325 /* Check UDP checksum */ 1326 if (rxctl & VGE_RDCTL_TCPPKT) 1327 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1328 1329 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1330 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1331 } 1332 1333 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1334 /* Check UDP checksum */ 1335 if (rxctl & VGE_RDCTL_UDPPKT) 1336 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1337 1338 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1339 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1340 } 1341 1342 if (rxstat & VGE_RDSTS_VTAG) { 1343 /* 1344 * We use bswap16() here because: 1345 * On LE machines, tag is stored in BE as stream data. 1346 * On BE machines, tag is stored in BE as stream data 1347 * but it was already swapped by le32toh() above. 1348 */ 1349 vlan_set_tag(m, bswap16(rxctl & VGE_RDCTL_VLANID)); 1350 } 1351 1352 if_percpuq_enqueue(ifp->if_percpuq, m); 1353 1354 lim++; 1355 if (lim == VGE_NRXDESC) 1356 break; 1357 } 1358 1359 sc->sc_rx_prodidx = idx; 1360 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1361 } 1362 1363 static void 1364 vge_txeof(struct vge_softc *sc) 1365 { 1366 struct ifnet *ifp; 1367 struct vge_txsoft *txs; 1368 uint32_t txstat; 1369 int idx; 1370 1371 ifp = &sc->sc_ethercom.ec_if; 1372 1373 for (idx = sc->sc_tx_considx; 1374 sc->sc_tx_free < VGE_NTXDESC; 1375 idx = VGE_NEXT_TXDESC(idx), sc->sc_tx_free++) { 1376 VGE_TXDESCSYNC(sc, idx, 1377 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1378 txstat = le32toh(sc->sc_txdescs[idx].td_sts); 1379 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1380 if (txstat & VGE_TDSTS_OWN) { 1381 break; 1382 } 1383 1384 txs = &sc->sc_txsoft[idx]; 1385 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0, 1386 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1387 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1388 m_freem(txs->txs_mbuf); 1389 txs->txs_mbuf = NULL; 1390 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1391 if (txstat & (VGE_TDSTS_EXCESSCOLL | VGE_TDSTS_COLL)) 1392 if_statinc_ref(nsr, if_collisions); 1393 if (txstat & VGE_TDSTS_TXERR) 1394 if_statinc_ref(nsr, if_oerrors); 1395 else 1396 if_statinc_ref(nsr, if_opackets); 1397 IF_STAT_PUTREF(ifp); 1398 } 1399 1400 sc->sc_tx_considx = idx; 1401 1402 /* 1403 * If not all descriptors have been released reaped yet, 1404 * reload the timer so that we will eventually get another 1405 * interrupt that will cause us to re-enter this routine. 1406 * This is done in case the transmitter has gone idle. 1407 */ 1408 if (sc->sc_tx_free < VGE_NTXDESC) 1409 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1410 else 1411 ifp->if_timer = 0; 1412 } 1413 1414 static void 1415 vge_tick(void *arg) 1416 { 1417 struct vge_softc *sc; 1418 struct ifnet *ifp; 1419 struct mii_data *mii; 1420 int s; 1421 1422 sc = arg; 1423 ifp = &sc->sc_ethercom.ec_if; 1424 mii = &sc->sc_mii; 1425 1426 s = splnet(); 1427 1428 callout_schedule(&sc->sc_timeout, hz); 1429 1430 mii_tick(mii); 1431 if (sc->sc_link) { 1432 if ((mii->mii_media_status & IFM_ACTIVE) == 0) 1433 sc->sc_link = 0; 1434 } else { 1435 if (mii->mii_media_status & IFM_ACTIVE && 1436 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1437 sc->sc_link = 1; 1438 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1439 vge_start(ifp); 1440 } 1441 } 1442 1443 splx(s); 1444 } 1445 1446 static int 1447 vge_intr(void *arg) 1448 { 1449 struct vge_softc *sc; 1450 struct ifnet *ifp; 1451 uint32_t status; 1452 int claim; 1453 1454 sc = arg; 1455 claim = 0; 1456 if (sc->sc_suspended) { 1457 return claim; 1458 } 1459 1460 ifp = &sc->sc_ethercom.ec_if; 1461 1462 if ((ifp->if_flags & IFF_UP) == 0) { 1463 return claim; 1464 } 1465 1466 /* Disable interrupts */ 1467 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1468 1469 for (;;) { 1470 1471 status = CSR_READ_4(sc, VGE_ISR); 1472 /* If the card has gone away the read returns 0xffffffff. */ 1473 if (status == 0xFFFFFFFF) 1474 break; 1475 1476 if (status) { 1477 claim = 1; 1478 CSR_WRITE_4(sc, VGE_ISR, status); 1479 } 1480 1481 if ((status & VGE_INTRS) == 0) 1482 break; 1483 1484 if (status & (VGE_ISR_RXOK | VGE_ISR_RXOK_HIPRIO)) 1485 vge_rxeof(sc); 1486 1487 if (status & (VGE_ISR_RXOFLOW | VGE_ISR_RXNODESC)) { 1488 vge_rxeof(sc); 1489 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1490 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1491 } 1492 1493 if (status & (VGE_ISR_TXOK0 | VGE_ISR_TIMER0)) 1494 vge_txeof(sc); 1495 1496 if (status & (VGE_ISR_TXDMA_STALL | VGE_ISR_RXDMA_STALL)) 1497 vge_init(ifp); 1498 1499 if (status & VGE_ISR_LINKSTS) 1500 vge_tick(sc); 1501 } 1502 1503 /* Re-enable interrupts */ 1504 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1505 1506 if (claim) 1507 if_schedule_deferred_start(ifp); 1508 1509 return claim; 1510 } 1511 1512 static int 1513 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1514 { 1515 struct vge_txsoft *txs; 1516 struct vge_txdesc *txd; 1517 struct vge_txfrag *f; 1518 struct mbuf *m_new; 1519 bus_dmamap_t map; 1520 int m_csumflags, seg, error, flags; 1521 size_t sz; 1522 uint32_t td_sts, td_ctl; 1523 1524 KASSERT(sc->sc_tx_free > 0); 1525 1526 txd = &sc->sc_txdescs[idx]; 1527 1528 #ifdef DIAGNOSTIC 1529 /* If this descriptor is still owned by the chip, bail. */ 1530 VGE_TXDESCSYNC(sc, idx, 1531 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1532 td_sts = le32toh(txd->td_sts); 1533 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1534 if (td_sts & VGE_TDSTS_OWN) { 1535 return ENOBUFS; 1536 } 1537 #endif 1538 1539 /* 1540 * Preserve m_pkthdr.csum_flags here since m_head might be 1541 * updated by m_defrag() 1542 */ 1543 m_csumflags = m_head->m_pkthdr.csum_flags; 1544 1545 txs = &sc->sc_txsoft[idx]; 1546 map = txs->txs_dmamap; 1547 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT); 1548 1549 /* If too many segments to map, coalesce */ 1550 if (error == EFBIG || 1551 (m_head->m_pkthdr.len < ETHER_PAD_LEN && 1552 map->dm_nsegs == VGE_TX_FRAGS)) { 1553 m_new = m_defrag(m_head, M_DONTWAIT); 1554 if (m_new == NULL) 1555 return EFBIG; 1556 1557 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1558 m_new, BUS_DMA_NOWAIT); 1559 if (error) { 1560 m_freem(m_new); 1561 return error; 1562 } 1563 1564 m_head = m_new; 1565 } else if (error) 1566 return error; 1567 1568 txs->txs_mbuf = m_head; 1569 1570 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1571 BUS_DMASYNC_PREWRITE); 1572 1573 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) { 1574 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len)); 1575 vge_set_txaddr(f, map->dm_segs[seg].ds_addr); 1576 } 1577 1578 /* Argh. This chip does not autopad short frames */ 1579 sz = m_head->m_pkthdr.len; 1580 if (sz < ETHER_PAD_LEN) { 1581 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz)); 1582 vge_set_txaddr(f, VGE_CDPADADDR(sc)); 1583 sz = ETHER_PAD_LEN; 1584 seg++; 1585 } 1586 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE); 1587 1588 /* 1589 * When telling the chip how many segments there are, we 1590 * must use nsegs + 1 instead of just nsegs. Darned if I 1591 * know why. 1592 */ 1593 seg++; 1594 1595 flags = 0; 1596 if (m_csumflags & M_CSUM_IPv4) 1597 flags |= VGE_TDCTL_IPCSUM; 1598 if (m_csumflags & M_CSUM_TCPv4) 1599 flags |= VGE_TDCTL_TCPCSUM; 1600 if (m_csumflags & M_CSUM_UDPv4) 1601 flags |= VGE_TDCTL_UDPCSUM; 1602 td_sts = sz << 16; 1603 td_ctl = flags | (seg << 28) | VGE_TD_LS_NORM; 1604 1605 if (sz > ETHERMTU + ETHER_HDR_LEN) 1606 td_ctl |= VGE_TDCTL_JUMBO; 1607 1608 /* 1609 * Set up hardware VLAN tagging. 1610 */ 1611 if (vlan_has_tag(m_head)) { 1612 /* 1613 * No need htons() here since vge(4) chip assumes 1614 * that tags are written in little endian and 1615 * we already use htole32() here. 1616 */ 1617 td_ctl |= vlan_get_tag(m_head) | VGE_TDCTL_VTAG; 1618 } 1619 txd->td_ctl = htole32(td_ctl); 1620 txd->td_sts = htole32(td_sts); 1621 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1622 1623 txd->td_sts = htole32(VGE_TDSTS_OWN | td_sts); 1624 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1625 1626 sc->sc_tx_free--; 1627 1628 return 0; 1629 } 1630 1631 /* 1632 * Main transmit routine. 1633 */ 1634 1635 static void 1636 vge_start(struct ifnet *ifp) 1637 { 1638 struct vge_softc *sc; 1639 struct vge_txsoft *txs; 1640 struct mbuf *m_head; 1641 int idx, pidx, ofree, error; 1642 1643 sc = ifp->if_softc; 1644 1645 if (!sc->sc_link || 1646 (ifp->if_flags & IFF_RUNNING) == 0) { 1647 return; 1648 } 1649 1650 m_head = NULL; 1651 idx = sc->sc_tx_prodidx; 1652 pidx = VGE_PREV_TXDESC(idx); 1653 ofree = sc->sc_tx_free; 1654 1655 /* 1656 * Loop through the send queue, setting up transmit descriptors 1657 * until we drain the queue, or use up all available transmit 1658 * descriptors. 1659 */ 1660 while (sc->sc_tx_free != 0) { 1661 /* Grab a packet off the queue. */ 1662 IFQ_POLL(&ifp->if_snd, m_head); 1663 if (m_head == NULL) 1664 break; 1665 1666 txs = &sc->sc_txsoft[idx]; 1667 KASSERT(txs->txs_mbuf == NULL); 1668 1669 if ((error = vge_encap(sc, m_head, idx))) { 1670 if (error == EFBIG) { 1671 printf("%s: Tx packet consumes too many " 1672 "DMA segments, dropping...\n", 1673 device_xname(sc->sc_dev)); 1674 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1675 m_freem(m_head); 1676 continue; 1677 } 1678 1679 /* 1680 * Short on resources, just stop for now. 1681 */ 1682 break; 1683 } 1684 1685 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1686 1687 /* 1688 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1689 */ 1690 1691 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |= 1692 htole16(VGE_TXDESC_Q); 1693 VGE_TXFRAGSYNC(sc, pidx, 1, 1694 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1695 1696 if (txs->txs_mbuf != m_head) { 1697 m_freem(m_head); 1698 m_head = txs->txs_mbuf; 1699 } 1700 1701 pidx = idx; 1702 idx = VGE_NEXT_TXDESC(idx); 1703 1704 /* 1705 * If there's a BPF listener, bounce a copy of this frame 1706 * to him. 1707 */ 1708 bpf_mtap(ifp, m_head, BPF_D_OUT); 1709 } 1710 1711 if (sc->sc_tx_free < ofree) { 1712 /* TX packet queued */ 1713 1714 sc->sc_tx_prodidx = idx; 1715 1716 /* Issue a transmit command. */ 1717 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1718 1719 /* 1720 * Use the countdown timer for interrupt moderation. 1721 * 'TX done' interrupts are disabled. Instead, we reset the 1722 * countdown timer, which will begin counting until it hits 1723 * the value in the SSTIMER register, and then trigger an 1724 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1725 * the timer count is reloaded. Only when the transmitter 1726 * is idle will the timer hit 0 and an interrupt fire. 1727 */ 1728 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1729 1730 /* 1731 * Set a timeout in case the chip goes out to lunch. 1732 */ 1733 ifp->if_timer = 5; 1734 } 1735 } 1736 1737 static int 1738 vge_init(struct ifnet *ifp) 1739 { 1740 struct vge_softc *sc; 1741 int i, rc = 0; 1742 1743 sc = ifp->if_softc; 1744 1745 /* 1746 * Cancel pending I/O and free all RX/TX buffers. 1747 */ 1748 vge_stop(ifp, 0); 1749 vge_reset(sc); 1750 1751 /* Initialize the RX descriptors and mbufs. */ 1752 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 1753 sc->sc_rx_consumed = 0; 1754 for (i = 0; i < VGE_NRXDESC; i++) { 1755 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1756 printf("%s: unable to allocate or map rx buffer\n", 1757 device_xname(sc->sc_dev)); 1758 return 1; /* XXX */ 1759 } 1760 } 1761 sc->sc_rx_prodidx = 0; 1762 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1763 1764 /* Initialize the TX descriptors and mbufs. */ 1765 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1766 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 1767 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs), 1768 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1769 for (i = 0; i < VGE_NTXDESC; i++) 1770 sc->sc_txsoft[i].txs_mbuf = NULL; 1771 1772 sc->sc_tx_prodidx = 0; 1773 sc->sc_tx_considx = 0; 1774 sc->sc_tx_free = VGE_NTXDESC; 1775 1776 /* Set our station address */ 1777 for (i = 0; i < ETHER_ADDR_LEN; i++) 1778 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]); 1779 1780 /* 1781 * Set receive FIFO threshold. Also allow transmission and 1782 * reception of VLAN tagged frames. 1783 */ 1784 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR | VGE_RXCFG_VTAGOPT); 1785 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES | VGE_VTAG_OPT2); 1786 1787 /* Set DMA burst length */ 1788 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1789 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1790 1791 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO | VGE_TXCFG_NONBLK); 1792 1793 /* Set collision backoff algorithm */ 1794 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM | 1795 VGE_CHIPCFG1_CAP | VGE_CHIPCFG1_MBA | VGE_CHIPCFG1_BAKOPT); 1796 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFFSET); 1797 1798 /* Disable LPSEL field in priority resolution */ 1799 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1800 1801 /* 1802 * Load the addresses of the DMA queues into the chip. 1803 * Note that we only use one transmit queue. 1804 */ 1805 1806 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, VGE_ADDR_HI(VGE_CDTXADDR(sc, 0))); 1807 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0))); 1808 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1); 1809 1810 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0))); 1811 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1); 1812 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC); 1813 1814 /* Enable and wake up the RX descriptor queue */ 1815 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1816 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1817 1818 /* Enable the TX descriptor queue */ 1819 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1820 1821 /* Set up the receive filter -- allow large frames for VLANs. */ 1822 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST | VGE_RXCTL_RX_GIANT); 1823 1824 /* If we want promiscuous mode, set the allframes bit. */ 1825 if (ifp->if_flags & IFF_PROMISC) { 1826 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1827 } 1828 1829 /* Set capture broadcast bit to capture broadcast frames. */ 1830 if (ifp->if_flags & IFF_BROADCAST) { 1831 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1832 } 1833 1834 /* Set multicast bit to capture multicast frames. */ 1835 if (ifp->if_flags & IFF_MULTICAST) { 1836 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1837 } 1838 1839 /* Init the cam filter. */ 1840 vge_cam_clear(sc); 1841 1842 /* Init the multicast filter. */ 1843 vge_setmulti(sc); 1844 1845 /* Enable flow control */ 1846 1847 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1848 1849 /* Enable jumbo frame reception (if desired) */ 1850 1851 /* Start the MAC. */ 1852 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1853 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1854 CSR_WRITE_1(sc, VGE_CRS0, 1855 VGE_CR0_TX_ENABLE | VGE_CR0_RX_ENABLE | VGE_CR0_START); 1856 1857 /* 1858 * Configure one-shot timer for microsecond 1859 * resulution and load it for 500 usecs. 1860 */ 1861 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1862 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1863 1864 /* 1865 * Configure interrupt moderation for receive. Enable 1866 * the holdoff counter and load it, and set the RX 1867 * suppression count to the number of descriptors we 1868 * want to allow before triggering an interrupt. 1869 * The holdoff timer is in units of 20 usecs. 1870 */ 1871 1872 #ifdef notyet 1873 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1874 /* Select the interrupt holdoff timer page. */ 1875 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1876 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1877 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1878 1879 /* Enable use of the holdoff timer. */ 1880 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1881 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1882 1883 /* Select the RX suppression threshold page. */ 1884 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1885 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1886 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1887 1888 /* Restore the page select bits. */ 1889 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1890 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1891 #endif 1892 1893 #ifdef DEVICE_POLLING 1894 /* 1895 * Disable interrupts if we are polling. 1896 */ 1897 if (ifp->if_flags & IFF_POLLING) { 1898 CSR_WRITE_4(sc, VGE_IMR, 0); 1899 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1900 } else /* otherwise ... */ 1901 #endif /* DEVICE_POLLING */ 1902 { 1903 /* 1904 * Enable interrupts. 1905 */ 1906 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1907 CSR_WRITE_4(sc, VGE_ISR, 0); 1908 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1909 } 1910 1911 if ((rc = ether_mediachange(ifp)) != 0) 1912 goto out; 1913 1914 ifp->if_flags |= IFF_RUNNING; 1915 1916 sc->sc_if_flags = 0; 1917 sc->sc_link = 0; 1918 1919 callout_schedule(&sc->sc_timeout, hz); 1920 1921 out: 1922 return rc; 1923 } 1924 1925 static void 1926 vge_miibus_statchg(struct ifnet *ifp) 1927 { 1928 struct vge_softc *sc = ifp->if_softc; 1929 struct mii_data *mii = &sc->sc_mii; 1930 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1931 uint8_t dctl; 1932 1933 /* 1934 * If the user manually selects a media mode, we need to turn 1935 * on the forced MAC mode bit in the DIAGCTL register. If the 1936 * user happens to choose a full duplex mode, we also need to 1937 * set the 'force full duplex' bit. This applies only to 1938 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1939 * mode is disabled, and in 1000baseT mode, full duplex is 1940 * always implied, so we turn on the forced mode bit but leave 1941 * the FDX bit cleared. 1942 */ 1943 dctl = CSR_READ_1(sc, VGE_DIAGCTL); 1944 1945 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1946 dctl &= ~VGE_DIAGCTL_MACFORCE; 1947 dctl &= ~VGE_DIAGCTL_FDXFORCE; 1948 } else { 1949 u_int ifmword; 1950 1951 /* If the link is up, use the current active media. */ 1952 if ((mii->mii_media_status & IFM_ACTIVE) != 0) 1953 ifmword = mii->mii_media_active; 1954 else 1955 ifmword = ife->ifm_media; 1956 1957 dctl |= VGE_DIAGCTL_MACFORCE; 1958 if ((ifmword & IFM_FDX) != 0) 1959 dctl |= VGE_DIAGCTL_FDXFORCE; 1960 else 1961 dctl &= ~VGE_DIAGCTL_FDXFORCE; 1962 1963 if (IFM_SUBTYPE(ifmword) == IFM_1000_T) { 1964 /* 1965 * It means the user setting is not auto but it's 1966 * 1000baseT-FDX or 1000baseT. 1967 */ 1968 dctl |= VGE_DIAGCTL_GMII; 1969 } else 1970 dctl &= ~VGE_DIAGCTL_GMII; 1971 } 1972 1973 CSR_WRITE_1(sc, VGE_DIAGCTL, dctl); 1974 } 1975 1976 static int 1977 vge_ifflags_cb(struct ethercom *ec) 1978 { 1979 struct ifnet *ifp = &ec->ec_if; 1980 struct vge_softc *sc = ifp->if_softc; 1981 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1982 1983 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 1984 return ENETRESET; 1985 else if ((change & IFF_PROMISC) == 0) 1986 return 0; 1987 1988 if ((ifp->if_flags & IFF_PROMISC) == 0) 1989 CSR_CLRBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1990 else 1991 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1992 vge_setmulti(sc); 1993 return 0; 1994 } 1995 1996 static int 1997 vge_ioctl(struct ifnet *ifp, u_long command, void *data) 1998 { 1999 struct vge_softc *sc; 2000 int s, error; 2001 2002 sc = ifp->if_softc; 2003 error = 0; 2004 2005 s = splnet(); 2006 2007 if ((error = ether_ioctl(ifp, command, data)) == ENETRESET) { 2008 error = 0; 2009 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2010 ; 2011 else if (ifp->if_flags & IFF_RUNNING) { 2012 /* 2013 * Multicast list has changed; set the hardware filter 2014 * accordingly. 2015 */ 2016 vge_setmulti(sc); 2017 } 2018 } 2019 sc->sc_if_flags = ifp->if_flags; 2020 2021 splx(s); 2022 return error; 2023 } 2024 2025 static void 2026 vge_watchdog(struct ifnet *ifp) 2027 { 2028 struct vge_softc *sc; 2029 int s; 2030 2031 sc = ifp->if_softc; 2032 s = splnet(); 2033 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2034 if_statinc(ifp, if_oerrors); 2035 2036 vge_txeof(sc); 2037 vge_rxeof(sc); 2038 2039 vge_init(ifp); 2040 2041 splx(s); 2042 } 2043 2044 /* 2045 * Stop the adapter and free any mbufs allocated to the 2046 * RX and TX lists. 2047 */ 2048 static void 2049 vge_stop(struct ifnet *ifp, int disable) 2050 { 2051 struct vge_softc *sc = ifp->if_softc; 2052 struct vge_txsoft *txs; 2053 struct vge_rxsoft *rxs; 2054 int i, s; 2055 2056 s = splnet(); 2057 ifp->if_timer = 0; 2058 2059 ifp->if_flags &= ~IFF_RUNNING; 2060 #ifdef DEVICE_POLLING 2061 ether_poll_deregister(ifp); 2062 #endif /* DEVICE_POLLING */ 2063 2064 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2065 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2066 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2067 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2068 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2069 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2070 2071 if (sc->sc_rx_mhead != NULL) { 2072 m_freem(sc->sc_rx_mhead); 2073 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 2074 } 2075 2076 /* Free the TX list buffers. */ 2077 2078 for (i = 0; i < VGE_NTXDESC; i++) { 2079 txs = &sc->sc_txsoft[i]; 2080 if (txs->txs_mbuf != NULL) { 2081 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2082 m_freem(txs->txs_mbuf); 2083 txs->txs_mbuf = NULL; 2084 } 2085 } 2086 2087 /* Free the RX list buffers. */ 2088 2089 for (i = 0; i < VGE_NRXDESC; i++) { 2090 rxs = &sc->sc_rxsoft[i]; 2091 if (rxs->rxs_mbuf != NULL) { 2092 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2093 m_freem(rxs->rxs_mbuf); 2094 rxs->rxs_mbuf = NULL; 2095 } 2096 } 2097 2098 splx(s); 2099 } 2100 2101 #if VGE_POWER_MANAGEMENT 2102 /* 2103 * Device suspend routine. Stop the interface and save some PCI 2104 * settings in case the BIOS doesn't restore them properly on 2105 * resume. 2106 */ 2107 static int 2108 vge_suspend(device_t dev) 2109 { 2110 struct vge_softc *sc; 2111 int i; 2112 2113 sc = device_get_softc(dev); 2114 2115 vge_stop(sc); 2116 2117 for (i = 0; i < 5; i++) 2118 sc->sc_saved_maps[i] = 2119 pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2120 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2121 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2122 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2123 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2124 2125 sc->suspended = 1; 2126 2127 return 0; 2128 } 2129 2130 /* 2131 * Device resume routine. Restore some PCI settings in case the BIOS 2132 * doesn't, re-enable busmastering, and restart the interface if 2133 * appropriate. 2134 */ 2135 static int 2136 vge_resume(device_t dev) 2137 { 2138 struct vge_softc *sc; 2139 struct ifnet *ifp; 2140 int i; 2141 2142 sc = device_private(dev); 2143 ifp = &sc->sc_ethercom.ec_if; 2144 2145 /* better way to do this? */ 2146 for (i = 0; i < 5; i++) 2147 pci_write_config(dev, PCIR_MAPS + i * 4, 2148 sc->sc_saved_maps[i], 4); 2149 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4); 2150 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1); 2151 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1); 2152 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1); 2153 2154 /* reenable busmastering */ 2155 pci_enable_busmaster(dev); 2156 pci_enable_io(dev, SYS_RES_MEMORY); 2157 2158 /* reinitialize interface if necessary */ 2159 if (ifp->if_flags & IFF_UP) 2160 vge_init(sc); 2161 2162 sc->suspended = 0; 2163 2164 return 0; 2165 } 2166 #endif 2167 2168 /* 2169 * Stop all chip I/O so that the kernel's probe routines don't 2170 * get confused by errant DMAs when rebooting. 2171 */ 2172 static bool 2173 vge_shutdown(device_t self, int howto) 2174 { 2175 struct vge_softc *sc; 2176 2177 sc = device_private(self); 2178 vge_stop(&sc->sc_ethercom.ec_if, 1); 2179 2180 return true; 2181 } 2182 2183 static void 2184 vge_clrwol(struct vge_softc *sc) 2185 { 2186 uint8_t val; 2187 2188 val = CSR_READ_1(sc, VGE_PWRSTAT); 2189 val &= ~VGE_STICKHW_SWPTAG; 2190 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2191 /* Disable WOL and clear power state indicator. */ 2192 val = CSR_READ_1(sc, VGE_PWRSTAT); 2193 val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1); 2194 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2195 2196 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); 2197 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2198 2199 /* Clear WOL on pattern match. */ 2200 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); 2201 /* Disable WOL on magic/unicast packet. */ 2202 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); 2203 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | 2204 VGE_WOLCFG_PMEOVR); 2205 /* Clear WOL status on pattern match. */ 2206 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); 2207 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); 2208 } 2209
Indexes created Mon Sep 29 21:09:56 GMT 2025