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if_vr.c revision 1.36
      1 /*	$NetBSD: if_vr.c,v 1.36 2000/09/13 14:00:48 tron Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9  * NASA Ames Research Center.
     10  *
     11  * Redistribution and use in source and binary forms, with or without
     12  * modification, are permitted provided that the following conditions
     13  * are met:
     14  * 1. Redistributions of source code must retain the above copyright
     15  *    notice, this list of conditions and the following disclaimer.
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  * 3. All advertising materials mentioning features or use of this software
     20  *    must display the following acknowledgement:
     21  *	This product includes software developed by the NetBSD
     22  *	Foundation, Inc. and its contributors.
     23  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24  *    contributors may be used to endorse or promote products derived
     25  *    from this software without specific prior written permission.
     26  *
     27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37  * POSSIBILITY OF SUCH DAMAGE.
     38  */
     39 
     40 /*
     41  * Copyright (c) 1997, 1998
     42  *	Bill Paul <wpaul (at) ctr.columbia.edu>.  All rights reserved.
     43  *
     44  * Redistribution and use in source and binary forms, with or without
     45  * modification, are permitted provided that the following conditions
     46  * are met:
     47  * 1. Redistributions of source code must retain the above copyright
     48  *    notice, this list of conditions and the following disclaimer.
     49  * 2. Redistributions in binary form must reproduce the above copyright
     50  *    notice, this list of conditions and the following disclaimer in the
     51  *    documentation and/or other materials provided with the distribution.
     52  * 3. All advertising materials mentioning features or use of this software
     53  *    must display the following acknowledgement:
     54  *	This product includes software developed by Bill Paul.
     55  * 4. Neither the name of the author nor the names of any co-contributors
     56  *    may be used to endorse or promote products derived from this software
     57  *    without specific prior written permission.
     58  *
     59  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
     60  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     61  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     62  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
     63  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     64  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     65  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     66  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     67  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     68  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
     69  * THE POSSIBILITY OF SUCH DAMAGE.
     70  *
     71  *	$FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $
     72  */
     73 
     74 /*
     75  * VIA Rhine fast ethernet PCI NIC driver
     76  *
     77  * Supports various network adapters based on the VIA Rhine
     78  * and Rhine II PCI controllers, including the D-Link DFE530TX.
     79  * Datasheets are available at http://www.via.com.tw.
     80  *
     81  * Written by Bill Paul <wpaul (at) ctr.columbia.edu>
     82  * Electrical Engineering Department
     83  * Columbia University, New York City
     84  */
     85 
     86 /*
     87  * The VIA Rhine controllers are similar in some respects to the
     88  * the DEC tulip chips, except less complicated. The controller
     89  * uses an MII bus and an external physical layer interface. The
     90  * receiver has a one entry perfect filter and a 64-bit hash table
     91  * multicast filter. Transmit and receive descriptors are similar
     92  * to the tulip.
     93  *
     94  * The Rhine has a serious flaw in its transmit DMA mechanism:
     95  * transmit buffers must be longword aligned. Unfortunately,
     96  * the kernel doesn't guarantee that mbufs will be filled in starting
     97  * at longword boundaries, so we have to do a buffer copy before
     98  * transmission.
     99  *
    100  * Apparently, the receive DMA mechanism also has the same flaw.  This
    101  * means that on systems with struct alignment requirements, incoming
    102  * frames must be copied to a new buffer which shifts the data forward
    103  * 2 bytes so that the payload is aligned on a 4-byte boundary.
    104  */
    105 
    106 #include "opt_inet.h"
    107 
    108 #include <sys/param.h>
    109 #include <sys/systm.h>
    110 #include <sys/callout.h>
    111 #include <sys/sockio.h>
    112 #include <sys/mbuf.h>
    113 #include <sys/malloc.h>
    114 #include <sys/kernel.h>
    115 #include <sys/socket.h>
    116 #include <sys/device.h>
    117 
    118 #include <uvm/uvm_extern.h>		/* for PAGE_SIZE */
    119 
    120 #include <net/if.h>
    121 #include <net/if_arp.h>
    122 #include <net/if_dl.h>
    123 #include <net/if_media.h>
    124 #include <net/if_ether.h>
    125 
    126 #if defined(INET)
    127 #include <netinet/in.h>
    128 #include <netinet/if_inarp.h>
    129 #endif
    130 
    131 #include "bpfilter.h"
    132 #if NBPFILTER > 0
    133 #include <net/bpf.h>
    134 #endif
    135 
    136 #include <machine/bus.h>
    137 #include <machine/intr.h>
    138 #include <machine/endian.h>
    139 
    140 #include <dev/mii/mii.h>
    141 #include <dev/mii/miivar.h>
    142 #include <dev/mii/mii_bitbang.h>
    143 
    144 #include <dev/pci/pcireg.h>
    145 #include <dev/pci/pcivar.h>
    146 #include <dev/pci/pcidevs.h>
    147 
    148 #include <dev/pci/if_vrreg.h>
    149 
    150 #define	VR_USEIOSPACE
    151 
    152 /*
    153  * Various supported device vendors/types and their names.
    154  */
    155 static struct vr_type {
    156 	pci_vendor_id_t		vr_vid;
    157 	pci_product_id_t	vr_did;
    158 	const char		*vr_name;
    159 } vr_devs[] = {
    160 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043,
    161 		"VIA VT3043 (Rhine) 10/100" },
    162 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A,
    163 		"VIA VT6102 (Rhine II) 10/100" },
    164 	{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A,
    165 		"VIA VT86C100A (Rhine-II) 10/100" },
    166 	{ 0, 0, NULL }
    167 };
    168 
    169 /*
    170  * Transmit descriptor list size.
    171  */
    172 #define	VR_NTXDESC		64
    173 #define	VR_NTXDESC_MASK		(VR_NTXDESC - 1)
    174 #define	VR_NEXTTX(x)		(((x) + 1) & VR_NTXDESC_MASK)
    175 
    176 /*
    177  * Receive descriptor list size.
    178  */
    179 #define	VR_NRXDESC		64
    180 #define	VR_NRXDESC_MASK		(VR_NRXDESC - 1)
    181 #define	VR_NEXTRX(x)		(((x) + 1) & VR_NRXDESC_MASK)
    182 
    183 /*
    184  * Control data structres that are DMA'd to the Rhine chip.  We allocate
    185  * them in a single clump that maps to a single DMA segment to make several
    186  * things easier.
    187  *
    188  * Note that since we always copy outgoing packets to aligned transmit
    189  * buffers, we can reduce the transmit descriptors to one per packet.
    190  */
    191 struct vr_control_data {
    192 	struct vr_desc		vr_txdescs[VR_NTXDESC];
    193 	struct vr_desc		vr_rxdescs[VR_NRXDESC];
    194 };
    195 
    196 #define	VR_CDOFF(x)		offsetof(struct vr_control_data, x)
    197 #define	VR_CDTXOFF(x)		VR_CDOFF(vr_txdescs[(x)])
    198 #define	VR_CDRXOFF(x)		VR_CDOFF(vr_rxdescs[(x)])
    199 
    200 /*
    201  * Software state of transmit and receive descriptors.
    202  */
    203 struct vr_descsoft {
    204 	struct mbuf		*ds_mbuf;	/* head of mbuf chain */
    205 	bus_dmamap_t		ds_dmamap;	/* our DMA map */
    206 };
    207 
    208 struct vr_softc {
    209 	struct device		vr_dev;		/* generic device glue */
    210 	void			*vr_ih;		/* interrupt cookie */
    211 	void			*vr_ats;	/* shutdown hook */
    212 	bus_space_tag_t		vr_bst;		/* bus space tag */
    213 	bus_space_handle_t	vr_bsh;		/* bus space handle */
    214 	bus_dma_tag_t		vr_dmat;	/* bus DMA tag */
    215 	pci_chipset_tag_t	vr_pc;		/* PCI chipset info */
    216 	struct ethercom		vr_ec;		/* Ethernet common info */
    217 	u_int8_t 		vr_enaddr[ETHER_ADDR_LEN];
    218 	struct mii_data		vr_mii;		/* MII/media info */
    219 
    220 	struct callout		vr_tick_ch;	/* tick callout */
    221 
    222 	bus_dmamap_t		vr_cddmamap;	/* control data DMA map */
    223 #define	vr_cddma	vr_cddmamap->dm_segs[0].ds_addr
    224 
    225 	/*
    226 	 * Software state for transmit and receive descriptors.
    227 	 */
    228 	struct vr_descsoft	vr_txsoft[VR_NTXDESC];
    229 	struct vr_descsoft	vr_rxsoft[VR_NRXDESC];
    230 
    231 	/*
    232 	 * Control data structures.
    233 	 */
    234 	struct vr_control_data	*vr_control_data;
    235 
    236 	int	vr_txpending;		/* number of TX requests pending */
    237 	int	vr_txdirty;		/* first dirty TX descriptor */
    238 	int	vr_txlast;		/* last used TX descriptor */
    239 
    240 	int	vr_rxptr;		/* next ready RX descriptor */
    241 };
    242 
    243 #define	VR_CDTXADDR(sc, x)	((sc)->vr_cddma + VR_CDTXOFF((x)))
    244 #define	VR_CDRXADDR(sc, x)	((sc)->vr_cddma + VR_CDRXOFF((x)))
    245 
    246 #define	VR_CDTX(sc, x)		(&(sc)->vr_control_data->vr_txdescs[(x)])
    247 #define	VR_CDRX(sc, x)		(&(sc)->vr_control_data->vr_rxdescs[(x)])
    248 
    249 #define	VR_DSTX(sc, x)		(&(sc)->vr_txsoft[(x)])
    250 #define	VR_DSRX(sc, x)		(&(sc)->vr_rxsoft[(x)])
    251 
    252 #define	VR_CDTXSYNC(sc, x, ops)						\
    253 	bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap,		\
    254 	    VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops))
    255 
    256 #define	VR_CDRXSYNC(sc, x, ops)						\
    257 	bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap,		\
    258 	    VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops))
    259 
    260 /*
    261  * Note we rely on MCLBYTES being a power of two below.
    262  */
    263 #define	VR_INIT_RXDESC(sc, i)						\
    264 do {									\
    265 	struct vr_desc *__d = VR_CDRX((sc), (i));			\
    266 	struct vr_descsoft *__ds = VR_DSRX((sc), (i));			\
    267 									\
    268 	__d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i))));	\
    269 	__d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG |			\
    270 	    VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN);			\
    271 	__d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr);	\
    272 	__d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR |	\
    273 	    ((MCLBYTES - 1) & VR_RXCTL_BUFLEN));			\
    274 	VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
    275 } while (0)
    276 
    277 /*
    278  * register space access macros
    279  */
    280 #define	CSR_WRITE_4(sc, reg, val)					\
    281 	bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val)
    282 #define	CSR_WRITE_2(sc, reg, val)					\
    283 	bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val)
    284 #define	CSR_WRITE_1(sc, reg, val)					\
    285 	bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val)
    286 
    287 #define	CSR_READ_4(sc, reg)						\
    288 	bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg)
    289 #define	CSR_READ_2(sc, reg)						\
    290 	bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg)
    291 #define	CSR_READ_1(sc, reg)						\
    292 	bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg)
    293 
    294 #define	VR_TIMEOUT		1000
    295 
    296 static int vr_add_rxbuf		__P((struct vr_softc *, int));
    297 
    298 static void vr_rxeof		__P((struct vr_softc *));
    299 static void vr_rxeoc		__P((struct vr_softc *));
    300 static void vr_txeof		__P((struct vr_softc *));
    301 static int vr_intr		__P((void *));
    302 static void vr_start		__P((struct ifnet *));
    303 static int vr_ioctl		__P((struct ifnet *, u_long, caddr_t));
    304 static int vr_init		__P((struct vr_softc *));
    305 static void vr_stop		__P((struct vr_softc *, int));
    306 static void vr_rxdrain		__P((struct vr_softc *));
    307 static void vr_watchdog		__P((struct ifnet *));
    308 static void vr_tick		__P((void *));
    309 
    310 static int vr_ifmedia_upd	__P((struct ifnet *));
    311 static void vr_ifmedia_sts	__P((struct ifnet *, struct ifmediareq *));
    312 
    313 static int vr_mii_readreg	__P((struct device *, int, int));
    314 static void vr_mii_writereg	__P((struct device *, int, int, int));
    315 static void vr_mii_statchg	__P((struct device *));
    316 
    317 static u_int8_t vr_calchash	__P((u_int8_t *));
    318 static void vr_setmulti		__P((struct vr_softc *));
    319 static void vr_reset		__P((struct vr_softc *));
    320 
    321 int	vr_copy_small = 0;
    322 
    323 #define	VR_SETBIT(sc, reg, x)				\
    324 	CSR_WRITE_1(sc, reg,				\
    325 		CSR_READ_1(sc, reg) | x)
    326 
    327 #define	VR_CLRBIT(sc, reg, x)				\
    328 	CSR_WRITE_1(sc, reg,				\
    329 		CSR_READ_1(sc, reg) & ~x)
    330 
    331 #define	VR_SETBIT16(sc, reg, x)				\
    332 	CSR_WRITE_2(sc, reg,				\
    333 		CSR_READ_2(sc, reg) | x)
    334 
    335 #define	VR_CLRBIT16(sc, reg, x)				\
    336 	CSR_WRITE_2(sc, reg,				\
    337 		CSR_READ_2(sc, reg) & ~x)
    338 
    339 #define	VR_SETBIT32(sc, reg, x)				\
    340 	CSR_WRITE_4(sc, reg,				\
    341 		CSR_READ_4(sc, reg) | x)
    342 
    343 #define	VR_CLRBIT32(sc, reg, x)				\
    344 	CSR_WRITE_4(sc, reg,				\
    345 		CSR_READ_4(sc, reg) & ~x)
    346 
    347 /*
    348  * MII bit-bang glue.
    349  */
    350 u_int32_t vr_mii_bitbang_read __P((struct device *));
    351 void vr_mii_bitbang_write __P((struct device *, u_int32_t));
    352 
    353 const struct mii_bitbang_ops vr_mii_bitbang_ops = {
    354 	vr_mii_bitbang_read,
    355 	vr_mii_bitbang_write,
    356 	{
    357 		VR_MIICMD_DATAOUT,	/* MII_BIT_MDO */
    358 		VR_MIICMD_DATAIN,	/* MII_BIT_MDI */
    359 		VR_MIICMD_CLK,		/* MII_BIT_MDC */
    360 		VR_MIICMD_DIR,		/* MII_BIT_DIR_HOST_PHY */
    361 		0,			/* MII_BIT_DIR_PHY_HOST */
    362 	}
    363 };
    364 
    365 u_int32_t
    366 vr_mii_bitbang_read(self)
    367 	struct device *self;
    368 {
    369 	struct vr_softc *sc = (void *) self;
    370 
    371 	return (CSR_READ_1(sc, VR_MIICMD));
    372 }
    373 
    374 void
    375 vr_mii_bitbang_write(self, val)
    376 	struct device *self;
    377 	u_int32_t val;
    378 {
    379 	struct vr_softc *sc = (void *) self;
    380 
    381 	CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM);
    382 }
    383 
    384 /*
    385  * Read an PHY register through the MII.
    386  */
    387 static int
    388 vr_mii_readreg(self, phy, reg)
    389 	struct device *self;
    390 	int phy, reg;
    391 {
    392 	struct vr_softc *sc = (void *) self;
    393 
    394 	CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
    395 	return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg));
    396 }
    397 
    398 /*
    399  * Write to a PHY register through the MII.
    400  */
    401 static void
    402 vr_mii_writereg(self, phy, reg, val)
    403 	struct device *self;
    404 	int phy, reg, val;
    405 {
    406 	struct vr_softc *sc = (void *) self;
    407 
    408 	CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
    409 	mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val);
    410 }
    411 
    412 static void
    413 vr_mii_statchg(self)
    414 	struct device *self;
    415 {
    416 	struct vr_softc *sc = (struct vr_softc *)self;
    417 
    418 	/*
    419 	 * In order to fiddle with the 'full-duplex' bit in the netconfig
    420 	 * register, we first have to put the transmit and/or receive logic
    421 	 * in the idle state.
    422 	 */
    423 	VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
    424 
    425 	if (sc->vr_mii.mii_media_active & IFM_FDX)
    426 		VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
    427 	else
    428 		VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
    429 
    430 	if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING)
    431 		VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
    432 }
    433 
    434 /*
    435  * Calculate CRC of a multicast group address, return the lower 6 bits.
    436  */
    437 static u_int8_t
    438 vr_calchash(addr)
    439 	u_int8_t *addr;
    440 {
    441 	u_int32_t crc, carry;
    442 	int i, j;
    443 	u_int8_t c;
    444 
    445 	/* Compute CRC for the address value. */
    446 	crc = 0xFFFFFFFF; /* initial value */
    447 
    448 	for (i = 0; i < 6; i++) {
    449 		c = *(addr + i);
    450 		for (j = 0; j < 8; j++) {
    451 			carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
    452 			crc <<= 1;
    453 			c >>= 1;
    454 			if (carry)
    455 				crc = (crc ^ 0x04c11db6) | carry;
    456 		}
    457 	}
    458 
    459 	/* return the filter bit position */
    460 	return ((crc >> 26) & 0x0000003F);
    461 }
    462 
    463 /*
    464  * Program the 64-bit multicast hash filter.
    465  */
    466 static void
    467 vr_setmulti(sc)
    468 	struct vr_softc *sc;
    469 {
    470 	struct ifnet *ifp;
    471 	int h = 0;
    472 	u_int32_t hashes[2] = { 0, 0 };
    473 	struct ether_multistep step;
    474 	struct ether_multi *enm;
    475 	int mcnt = 0;
    476 	u_int8_t rxfilt;
    477 
    478 	ifp = &sc->vr_ec.ec_if;
    479 
    480 	rxfilt = CSR_READ_1(sc, VR_RXCFG);
    481 
    482 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
    483 		rxfilt |= VR_RXCFG_RX_MULTI;
    484 		CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
    485 		CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
    486 		CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
    487 		return;
    488 	}
    489 
    490 	/* first, zot all the existing hash bits */
    491 	CSR_WRITE_4(sc, VR_MAR0, 0);
    492 	CSR_WRITE_4(sc, VR_MAR1, 0);
    493 
    494 	/* now program new ones */
    495 	ETHER_FIRST_MULTI(step, &sc->vr_ec, enm);
    496 	while (enm != NULL) {
    497 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0)
    498 			continue;
    499 
    500 		h = vr_calchash(enm->enm_addrlo);
    501 
    502 		if (h < 32)
    503 			hashes[0] |= (1 << h);
    504 		else
    505 			hashes[1] |= (1 << (h - 32));
    506 		ETHER_NEXT_MULTI(step, enm);
    507 		mcnt++;
    508 	}
    509 
    510 	if (mcnt)
    511 		rxfilt |= VR_RXCFG_RX_MULTI;
    512 	else
    513 		rxfilt &= ~VR_RXCFG_RX_MULTI;
    514 
    515 	CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
    516 	CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
    517 	CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
    518 }
    519 
    520 static void
    521 vr_reset(sc)
    522 	struct vr_softc *sc;
    523 {
    524 	int i;
    525 
    526 	VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
    527 
    528 	for (i = 0; i < VR_TIMEOUT; i++) {
    529 		DELAY(10);
    530 		if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
    531 			break;
    532 	}
    533 	if (i == VR_TIMEOUT)
    534 		printf("%s: reset never completed!\n",
    535 			sc->vr_dev.dv_xname);
    536 
    537 	/* Wait a little while for the chip to get its brains in order. */
    538 	DELAY(1000);
    539 }
    540 
    541 /*
    542  * Initialize an RX descriptor and attach an MBUF cluster.
    543  * Note: the length fields are only 11 bits wide, which means the
    544  * largest size we can specify is 2047. This is important because
    545  * MCLBYTES is 2048, so we have to subtract one otherwise we'll
    546  * overflow the field and make a mess.
    547  */
    548 static int
    549 vr_add_rxbuf(sc, i)
    550 	struct vr_softc *sc;
    551 	int i;
    552 {
    553 	struct vr_descsoft *ds = VR_DSRX(sc, i);
    554 	struct mbuf *m_new;
    555 	int error;
    556 
    557 	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
    558 	if (m_new == NULL)
    559 		return (ENOBUFS);
    560 
    561 	MCLGET(m_new, M_DONTWAIT);
    562 	if ((m_new->m_flags & M_EXT) == 0) {
    563 		m_freem(m_new);
    564 		return (ENOBUFS);
    565 	}
    566 
    567 	if (ds->ds_mbuf != NULL)
    568 		bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap);
    569 
    570 	ds->ds_mbuf = m_new;
    571 
    572 	error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap,
    573 	    m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
    574 	if (error) {
    575 		printf("%s: unable to load rx DMA map %d, error = %d\n",
    576 		    sc->vr_dev.dv_xname, i, error);
    577 		panic("vr_add_rxbuf");		/* XXX */
    578 	}
    579 
    580 	bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
    581 	    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
    582 
    583 	VR_INIT_RXDESC(sc, i);
    584 
    585 	return (0);
    586 }
    587 
    588 /*
    589  * A frame has been uploaded: pass the resulting mbuf chain up to
    590  * the higher level protocols.
    591  */
    592 static void
    593 vr_rxeof(sc)
    594 	struct vr_softc *sc;
    595 {
    596 	struct ether_header *eh;
    597 	struct mbuf *m;
    598 	struct ifnet *ifp;
    599 	struct vr_desc *d;
    600 	struct vr_descsoft *ds;
    601 	int i, total_len;
    602 	u_int32_t rxstat;
    603 
    604 	ifp = &sc->vr_ec.ec_if;
    605 
    606 	for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) {
    607 		d = VR_CDRX(sc, i);
    608 		ds = VR_DSRX(sc, i);
    609 
    610 		VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
    611 
    612 		rxstat = le32toh(d->vr_status);
    613 
    614 		if (rxstat & VR_RXSTAT_OWN) {
    615 			/*
    616 			 * We have processed all of the receive buffers.
    617 			 */
    618 			break;
    619 		}
    620 
    621 		/*
    622 		 * If an error occurs, update stats, clear the
    623 		 * status word and leave the mbuf cluster in place:
    624 		 * it should simply get re-used next time this descriptor
    625 		 * comes up in the ring.
    626 		 */
    627 		if (rxstat & VR_RXSTAT_RXERR) {
    628 			const char *errstr;
    629 
    630 			ifp->if_ierrors++;
    631 			switch (rxstat & 0x000000FF) {
    632 			case VR_RXSTAT_CRCERR:
    633 				errstr = "crc error";
    634 				break;
    635 			case VR_RXSTAT_FRAMEALIGNERR:
    636 				errstr = "frame alignment error";
    637 				break;
    638 			case VR_RXSTAT_FIFOOFLOW:
    639 				errstr = "FIFO overflow";
    640 				break;
    641 			case VR_RXSTAT_GIANT:
    642 				errstr = "received giant packet";
    643 				break;
    644 			case VR_RXSTAT_RUNT:
    645 				errstr = "received runt packet";
    646 				break;
    647 			case VR_RXSTAT_BUSERR:
    648 				errstr = "system bus error";
    649 				break;
    650 			case VR_RXSTAT_BUFFERR:
    651 				errstr = "rx buffer error";
    652 				break;
    653 			default:
    654 				errstr = "unknown rx error";
    655 				break;
    656 			}
    657 			printf("%s: receive error: %s\n", sc->vr_dev.dv_xname,
    658 			    errstr);
    659 
    660 			VR_INIT_RXDESC(sc, i);
    661 
    662 			continue;
    663 		}
    664 
    665 		bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
    666 		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
    667 
    668 		/* No errors; receive the packet. */
    669 		total_len = VR_RXBYTES(le32toh(d->vr_status));
    670 
    671 		/*
    672 		 * XXX The VIA Rhine chip includes the CRC with every
    673 		 * received frame, and there's no way to turn this
    674 		 * behavior off (at least, I can't find anything in
    675 		 * the manual that explains how to do it) so we have
    676 		 * to trim off the CRC manually.
    677 		 */
    678 		total_len -= ETHER_CRC_LEN;
    679 
    680 #ifdef __NO_STRICT_ALIGNMENT
    681 		/*
    682 		 * If the packet is small enough to fit in a
    683 		 * single header mbuf, allocate one and copy
    684 		 * the data into it.  This greatly reduces
    685 		 * memory consumption when we receive lots
    686 		 * of small packets.
    687 		 *
    688 		 * Otherwise, we add a new buffer to the receive
    689 		 * chain.  If this fails, we drop the packet and
    690 		 * recycle the old buffer.
    691 		 */
    692 		if (vr_copy_small != 0 && total_len <= MHLEN) {
    693 			MGETHDR(m, M_DONTWAIT, MT_DATA);
    694 			if (m == NULL)
    695 				goto dropit;
    696 			memcpy(mtod(m, caddr_t),
    697 			    mtod(ds->ds_mbuf, caddr_t), total_len);
    698 			VR_INIT_RXDESC(sc, i);
    699 			bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
    700 			    ds->ds_dmamap->dm_mapsize,
    701 			    BUS_DMASYNC_PREREAD);
    702 		} else {
    703 			m = ds->ds_mbuf;
    704 			if (vr_add_rxbuf(sc, i) == ENOBUFS) {
    705  dropit:
    706 				ifp->if_ierrors++;
    707 				VR_INIT_RXDESC(sc, i);
    708 				bus_dmamap_sync(sc->vr_dmat,
    709 				    ds->ds_dmamap, 0,
    710 				    ds->ds_dmamap->dm_mapsize,
    711 				    BUS_DMASYNC_PREREAD);
    712 				continue;
    713 			}
    714 		}
    715 #else
    716 		/*
    717 		 * The Rhine's packet buffers must be 4-byte aligned.
    718 		 * But this means that the data after the Ethernet header
    719 		 * is misaligned.  We must allocate a new buffer and
    720 		 * copy the data, shifted forward 2 bytes.
    721 		 */
    722 		MGETHDR(m, M_DONTWAIT, MT_DATA);
    723 		if (m == NULL) {
    724  dropit:
    725 			ifp->if_ierrors++;
    726 			VR_INIT_RXDESC(sc, i);
    727 			bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
    728 			    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
    729 			continue;
    730 		}
    731 		if (total_len > (MHLEN - 2)) {
    732 			MCLGET(m, M_DONTWAIT);
    733 			if ((m->m_flags & M_EXT) == 0) {
    734 				m_freem(m);
    735 				goto dropit;
    736 			}
    737 		}
    738 		m->m_data += 2;
    739 
    740 		/*
    741 		 * Note that we use clusters for incoming frames, so the
    742 		 * buffer is virtually contiguous.
    743 		 */
    744 		memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t),
    745 		    total_len);
    746 
    747 		/* Allow the recieve descriptor to continue using its mbuf. */
    748 		VR_INIT_RXDESC(sc, i);
    749 		bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
    750 		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
    751 #endif /* __NO_STRICT_ALIGNMENT */
    752 
    753 		ifp->if_ipackets++;
    754 		eh = mtod(m, struct ether_header *);
    755 		m->m_pkthdr.rcvif = ifp;
    756 		m->m_pkthdr.len = m->m_len = total_len;
    757 #if NBPFILTER > 0
    758 		/*
    759 		 * Handle BPF listeners. Let the BPF user see the packet, but
    760 		 * don't pass it up to the ether_input() layer unless it's
    761 		 * a broadcast packet, multicast packet, matches our ethernet
    762 		 * address or the interface is in promiscuous mode.
    763 		 */
    764 		if (ifp->if_bpf) {
    765 			bpf_mtap(ifp->if_bpf, m);
    766 			if ((ifp->if_flags & IFF_PROMISC) != 0 &&
    767 			    ETHER_IS_MULTICAST(eh->ether_dhost) == 0 &&
    768 			    memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl),
    769 				   ETHER_ADDR_LEN) != 0) {
    770 				m_freem(m);
    771 				continue;
    772 			}
    773 		}
    774 #endif
    775 		/* Pass it on. */
    776 		(*ifp->if_input)(ifp, m);
    777 	}
    778 
    779 	/* Update the receive pointer. */
    780 	sc->vr_rxptr = i;
    781 }
    782 
    783 void
    784 vr_rxeoc(sc)
    785 	struct vr_softc *sc;
    786 {
    787 
    788 	vr_rxeof(sc);
    789 	VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
    790 	CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr));
    791 	VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
    792 	VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
    793 }
    794 
    795 /*
    796  * A frame was downloaded to the chip. It's safe for us to clean up
    797  * the list buffers.
    798  */
    799 static void
    800 vr_txeof(sc)
    801 	struct vr_softc *sc;
    802 {
    803 	struct ifnet *ifp = &sc->vr_ec.ec_if;
    804 	struct vr_desc *d;
    805 	struct vr_descsoft *ds;
    806 	u_int32_t txstat;
    807 	int i;
    808 
    809 	ifp->if_flags &= ~IFF_OACTIVE;
    810 
    811 	/*
    812 	 * Go through our tx list and free mbufs for those
    813 	 * frames that have been transmitted.
    814 	 */
    815 	for (i = sc->vr_txdirty; sc->vr_txpending != 0;
    816 	     i = VR_NEXTTX(i), sc->vr_txpending--) {
    817 		d = VR_CDTX(sc, i);
    818 		ds = VR_DSTX(sc, i);
    819 
    820 		VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
    821 
    822 		txstat = le32toh(d->vr_status);
    823 		if (txstat & VR_TXSTAT_OWN)
    824 			break;
    825 
    826 		bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap,
    827 		    0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
    828 		bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap);
    829 		m_freem(ds->ds_mbuf);
    830 		ds->ds_mbuf = NULL;
    831 
    832 		if (txstat & VR_TXSTAT_ERRSUM) {
    833 			ifp->if_oerrors++;
    834 			if (txstat & VR_TXSTAT_DEFER)
    835 				ifp->if_collisions++;
    836 			if (txstat & VR_TXSTAT_LATECOLL)
    837 				ifp->if_collisions++;
    838 		}
    839 
    840 		ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3;
    841 		ifp->if_opackets++;
    842 	}
    843 
    844 	/* Update the dirty transmit buffer pointer. */
    845 	sc->vr_txdirty = i;
    846 
    847 	/*
    848 	 * Cancel the watchdog timer if there are no pending
    849 	 * transmissions.
    850 	 */
    851 	if (sc->vr_txpending == 0)
    852 		ifp->if_timer = 0;
    853 }
    854 
    855 static int
    856 vr_intr(arg)
    857 	void *arg;
    858 {
    859 	struct vr_softc *sc;
    860 	struct ifnet *ifp;
    861 	u_int16_t status;
    862 	int handled = 0, dotx = 0;
    863 
    864 	sc = arg;
    865 	ifp = &sc->vr_ec.ec_if;
    866 
    867 	/* Suppress unwanted interrupts. */
    868 	if ((ifp->if_flags & IFF_UP) == 0) {
    869 		vr_stop(sc, 1);
    870 		return (0);
    871 	}
    872 
    873 	/* Disable interrupts. */
    874 	CSR_WRITE_2(sc, VR_IMR, 0x0000);
    875 
    876 	for (;;) {
    877 		status = CSR_READ_2(sc, VR_ISR);
    878 		if (status)
    879 			CSR_WRITE_2(sc, VR_ISR, status);
    880 
    881 		if ((status & VR_INTRS) == 0)
    882 			break;
    883 
    884 		handled = 1;
    885 
    886 		if (status & VR_ISR_RX_OK)
    887 			vr_rxeof(sc);
    888 
    889 		if (status &
    890 		    (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW |
    891 		     VR_ISR_RX_DROPPED))
    892 			vr_rxeoc(sc);
    893 
    894 		if (status & VR_ISR_TX_OK) {
    895 			dotx = 1;
    896 			vr_txeof(sc);
    897 		}
    898 
    899 		if (status & (VR_ISR_TX_UNDERRUN | VR_ISR_TX_ABRT)) {
    900 			if (status & VR_ISR_TX_UNDERRUN)
    901 				printf("%s: transmit underrun\n",
    902 				    sc->vr_dev.dv_xname);
    903 			if (status & VR_ISR_TX_ABRT)
    904 				printf("%s: transmit aborted\n",
    905 				    sc->vr_dev.dv_xname);
    906 			ifp->if_oerrors++;
    907 			dotx = 1;
    908 			vr_txeof(sc);
    909 			if (sc->vr_txpending) {
    910 				VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
    911 				VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
    912 			}
    913 		}
    914 
    915 		if (status & VR_ISR_BUSERR) {
    916 			printf("%s: PCI bus error\n", sc->vr_dev.dv_xname);
    917 			/* vr_init() calls vr_start() */
    918 			dotx = 0;
    919 			(void) vr_init(sc);
    920 		}
    921 	}
    922 
    923 	/* Re-enable interrupts. */
    924 	CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
    925 
    926 	if (dotx)
    927 		vr_start(ifp);
    928 
    929 	return (handled);
    930 }
    931 
    932 /*
    933  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
    934  * to the mbuf data regions directly in the transmit lists. We also save a
    935  * copy of the pointers since the transmit list fragment pointers are
    936  * physical addresses.
    937  */
    938 static void
    939 vr_start(ifp)
    940 	struct ifnet *ifp;
    941 {
    942 	struct vr_softc *sc = ifp->if_softc;
    943 	struct mbuf *m0, *m;
    944 	struct vr_desc *d;
    945 	struct vr_descsoft *ds;
    946 	int error, firsttx, nexttx, opending;
    947 
    948 	/*
    949 	 * Remember the previous txpending and the first transmit
    950 	 * descriptor we use.
    951 	 */
    952 	opending = sc->vr_txpending;
    953 	firsttx = VR_NEXTTX(sc->vr_txlast);
    954 
    955 	/*
    956 	 * Loop through the send queue, setting up transmit descriptors
    957 	 * until we drain the queue, or use up all available transmit
    958 	 * descriptors.
    959 	 */
    960 	while (sc->vr_txpending < VR_NTXDESC) {
    961 		/*
    962 		 * Grab a packet off the queue.
    963 		 */
    964 		IF_DEQUEUE(&ifp->if_snd, m0);
    965 		if (m0 == NULL)
    966 			break;
    967 
    968 		/*
    969 		 * Get the next available transmit descriptor.
    970 		 */
    971 		nexttx = VR_NEXTTX(sc->vr_txlast);
    972 		d = VR_CDTX(sc, nexttx);
    973 		ds = VR_DSTX(sc, nexttx);
    974 
    975 		/*
    976 		 * Load the DMA map.  If this fails, the packet didn't
    977 		 * fit in one DMA segment, and we need to copy.  Note,
    978 		 * the packet must also be aligned.
    979 		 */
    980 		if ((mtod(m0, bus_addr_t) & 3) != 0 ||
    981 		    bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0,
    982 		     BUS_DMA_NOWAIT) != 0) {
    983 			MGETHDR(m, M_DONTWAIT, MT_DATA);
    984 			if (m == NULL) {
    985 				printf("%s: unable to allocate Tx mbuf\n",
    986 				    sc->vr_dev.dv_xname);
    987 				IF_PREPEND(&ifp->if_snd, m0);
    988 				break;
    989 			}
    990 			if (m0->m_pkthdr.len > MHLEN) {
    991 				MCLGET(m, M_DONTWAIT);
    992 				if ((m->m_flags & M_EXT) == 0) {
    993 					printf("%s: unable to allocate Tx "
    994 					    "cluster\n", sc->vr_dev.dv_xname);
    995 					m_freem(m);
    996 					IF_PREPEND(&ifp->if_snd, m0);
    997 					break;
    998 				}
    999 			}
   1000 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
   1001 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
   1002 			m_freem(m0);
   1003 			m0 = m;
   1004 			error = bus_dmamap_load_mbuf(sc->vr_dmat,
   1005 			    ds->ds_dmamap, m0, BUS_DMA_NOWAIT);
   1006 			if (error) {
   1007 				printf("%s: unable to load Tx buffer, "
   1008 				    "error = %d\n", sc->vr_dev.dv_xname, error);
   1009 				IF_PREPEND(&ifp->if_snd, m0);
   1010 				break;
   1011 			}
   1012 		}
   1013 
   1014 		/* Sync the DMA map. */
   1015 		bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
   1016 		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE);
   1017 
   1018 		/*
   1019 		 * Store a pointer to the packet so we can free it later.
   1020 		 */
   1021 		ds->ds_mbuf = m0;
   1022 
   1023 #if NBPFILTER > 0
   1024 		/*
   1025 		 * If there's a BPF listener, bounce a copy of this frame
   1026 		 * to him.
   1027 		 */
   1028 		if (ifp->if_bpf)
   1029 			bpf_mtap(ifp->if_bpf, m0);
   1030 #endif
   1031 
   1032 		/*
   1033 		 * Fill in the transmit descriptor.  The Rhine
   1034 		 * doesn't auto-pad, so we have to do this ourselves.
   1035 		 */
   1036 		d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr);
   1037 		d->vr_ctl = htole32(m0->m_pkthdr.len < VR_MIN_FRAMELEN ?
   1038 		    VR_MIN_FRAMELEN : m0->m_pkthdr.len);
   1039 		d->vr_ctl |=
   1040 		    htole32(VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG|
   1041 		    VR_TXCTL_LASTFRAG);
   1042 
   1043 		/*
   1044 		 * If this is the first descriptor we're enqueuing,
   1045 		 * don't give it to the Rhine yet.  That could cause
   1046 		 * a race condition.  We'll do it below.
   1047 		 */
   1048 		if (nexttx == firsttx)
   1049 			d->vr_status = 0;
   1050 		else
   1051 			d->vr_status = htole32(VR_TXSTAT_OWN);
   1052 
   1053 		VR_CDTXSYNC(sc, nexttx,
   1054 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1055 
   1056 		/* Advance the tx pointer. */
   1057 		sc->vr_txpending++;
   1058 		sc->vr_txlast = nexttx;
   1059 	}
   1060 
   1061 	if (sc->vr_txpending == VR_NTXDESC) {
   1062 		/* No more slots left; notify upper layer. */
   1063 		ifp->if_flags |= IFF_OACTIVE;
   1064 	}
   1065 
   1066 	if (sc->vr_txpending != opending) {
   1067 		/*
   1068 		 * We enqueued packets.  If the transmitter was idle,
   1069 		 * reset the txdirty pointer.
   1070 		 */
   1071 		if (opending == 0)
   1072 			sc->vr_txdirty = firsttx;
   1073 
   1074 		/*
   1075 		 * Cause a transmit interrupt to happen on the
   1076 		 * last packet we enqueued.
   1077 		 */
   1078 		VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT);
   1079 		VR_CDTXSYNC(sc, sc->vr_txlast,
   1080 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1081 
   1082 		/*
   1083 		 * The entire packet chain is set up.  Give the
   1084 		 * first descriptor to the Rhine now.
   1085 		 */
   1086 		VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN);
   1087 		VR_CDTXSYNC(sc, firsttx,
   1088 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1089 
   1090 		/* Start the transmitter. */
   1091 		VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_TX_GO);
   1092 
   1093 		/* Set the watchdog timer in case the chip flakes out. */
   1094 		ifp->if_timer = 5;
   1095 	}
   1096 }
   1097 
   1098 /*
   1099  * Initialize the interface.  Must be called at splnet.
   1100  */
   1101 static int
   1102 vr_init(sc)
   1103 	struct vr_softc *sc;
   1104 {
   1105 	struct ifnet *ifp = &sc->vr_ec.ec_if;
   1106 	struct vr_desc *d;
   1107 	struct vr_descsoft *ds;
   1108 	int i, error = 0;
   1109 
   1110 	/* Cancel pending I/O. */
   1111 	vr_stop(sc, 0);
   1112 
   1113 	/* Reset the Rhine to a known state. */
   1114 	vr_reset(sc);
   1115 
   1116 	VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
   1117 	VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD);
   1118 
   1119 	VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
   1120 	VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
   1121 
   1122 	/*
   1123 	 * Initialize the transmit desciptor ring.  txlast is initialized
   1124 	 * to the end of the list so that it will wrap around to the first
   1125 	 * descriptor when the first packet is transmitted.
   1126 	 */
   1127 	for (i = 0; i < VR_NTXDESC; i++) {
   1128 		d = VR_CDTX(sc, i);
   1129 		memset(d, 0, sizeof(struct vr_desc));
   1130 		d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i)));
   1131 		VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1132 	}
   1133 	sc->vr_txpending = 0;
   1134 	sc->vr_txdirty = 0;
   1135 	sc->vr_txlast = VR_NTXDESC - 1;
   1136 
   1137 	/*
   1138 	 * Initialize the receive descriptor ring.
   1139 	 */
   1140 	for (i = 0; i < VR_NRXDESC; i++) {
   1141 		ds = VR_DSRX(sc, i);
   1142 		if (ds->ds_mbuf == NULL) {
   1143 			if ((error = vr_add_rxbuf(sc, i)) != 0) {
   1144 				printf("%s: unable to allocate or map rx "
   1145 				    "buffer %d, error = %d\n",
   1146 				    sc->vr_dev.dv_xname, i, error);
   1147 				/*
   1148 				 * XXX Should attempt to run with fewer receive
   1149 				 * XXX buffers instead of just failing.
   1150 				 */
   1151 				vr_rxdrain(sc);
   1152 				goto out;
   1153 			}
   1154 		}
   1155 	}
   1156 	sc->vr_rxptr = 0;
   1157 
   1158 	/* If we want promiscuous mode, set the allframes bit. */
   1159 	if (ifp->if_flags & IFF_PROMISC)
   1160 		VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
   1161 	else
   1162 		VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
   1163 
   1164 	/* Set capture broadcast bit to capture broadcast frames. */
   1165 	if (ifp->if_flags & IFF_BROADCAST)
   1166 		VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
   1167 	else
   1168 		VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
   1169 
   1170 	/* Program the multicast filter, if necessary. */
   1171 	vr_setmulti(sc);
   1172 
   1173 	/* Give the transmit and recieve rings to the Rhine. */
   1174 	CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr));
   1175 	CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast)));
   1176 
   1177 	/* Set current media. */
   1178 	mii_mediachg(&sc->vr_mii);
   1179 
   1180 	/* Enable receiver and transmitter. */
   1181 	CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
   1182 				    VR_CMD_TX_ON|VR_CMD_RX_ON|
   1183 				    VR_CMD_RX_GO);
   1184 
   1185 	/* Enable interrupts. */
   1186 	CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
   1187 	CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
   1188 
   1189 	ifp->if_flags |= IFF_RUNNING;
   1190 	ifp->if_flags &= ~IFF_OACTIVE;
   1191 
   1192 	/* Start one second timer. */
   1193 	callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc);
   1194 
   1195 	/* Attempt to start output on the interface. */
   1196 	vr_start(ifp);
   1197 
   1198  out:
   1199 	if (error)
   1200 		printf("%s: interface not running\n", sc->vr_dev.dv_xname);
   1201 	return (error);
   1202 }
   1203 
   1204 /*
   1205  * Set media options.
   1206  */
   1207 static int
   1208 vr_ifmedia_upd(ifp)
   1209 	struct ifnet *ifp;
   1210 {
   1211 	struct vr_softc *sc = ifp->if_softc;
   1212 
   1213 	if (ifp->if_flags & IFF_UP)
   1214 		mii_mediachg(&sc->vr_mii);
   1215 	return (0);
   1216 }
   1217 
   1218 /*
   1219  * Report current media status.
   1220  */
   1221 static void
   1222 vr_ifmedia_sts(ifp, ifmr)
   1223 	struct ifnet *ifp;
   1224 	struct ifmediareq *ifmr;
   1225 {
   1226 	struct vr_softc *sc = ifp->if_softc;
   1227 
   1228 	mii_pollstat(&sc->vr_mii);
   1229 	ifmr->ifm_status = sc->vr_mii.mii_media_status;
   1230 	ifmr->ifm_active = sc->vr_mii.mii_media_active;
   1231 }
   1232 
   1233 static int
   1234 vr_ioctl(ifp, command, data)
   1235 	struct ifnet *ifp;
   1236 	u_long command;
   1237 	caddr_t data;
   1238 {
   1239 	struct vr_softc *sc = ifp->if_softc;
   1240 	struct ifreq *ifr = (struct ifreq *)data;
   1241 	struct ifaddr *ifa = (struct ifaddr *)data;
   1242 	int s, error = 0;
   1243 
   1244 	s = splnet();
   1245 
   1246 	switch (command) {
   1247 	case SIOCSIFADDR:
   1248 		ifp->if_flags |= IFF_UP;
   1249 
   1250 		switch (ifa->ifa_addr->sa_family) {
   1251 #ifdef INET
   1252 		case AF_INET:
   1253 			if ((error = vr_init(sc)) != 0)
   1254 				break;
   1255 			arp_ifinit(ifp, ifa);
   1256 			break;
   1257 #endif /* INET */
   1258 		default:
   1259 			error = vr_init(sc);
   1260 			break;
   1261 		}
   1262 		break;
   1263 
   1264 	case SIOCGIFADDR:
   1265 		bcopy((caddr_t) sc->vr_enaddr,
   1266 			(caddr_t) ((struct sockaddr *)&ifr->ifr_data)->sa_data,
   1267 			ETHER_ADDR_LEN);
   1268 		break;
   1269 
   1270 	case SIOCSIFMTU:
   1271 		if (ifr->ifr_mtu > ETHERMTU)
   1272 			error = EINVAL;
   1273 		else
   1274 			ifp->if_mtu = ifr->ifr_mtu;
   1275 		break;
   1276 
   1277 	case SIOCSIFFLAGS:
   1278 		if ((ifp->if_flags & IFF_UP) == 0 &&
   1279 		    (ifp->if_flags & IFF_RUNNING) != 0) {
   1280 			/*
   1281 			 * If interface is marked down and it is running, then
   1282 			 * stop it.
   1283 			 */
   1284 			vr_stop(sc, 1);
   1285 		} else if ((ifp->if_flags & IFF_UP) != 0 &&
   1286 			   (ifp->if_flags & IFF_RUNNING) == 0) {
   1287 			/*
   1288 			 * If interface is marked up and it is stopped, then
   1289 			 * start it.
   1290 			 */
   1291 			error = vr_init(sc);
   1292 		} else if ((ifp->if_flags & IFF_UP) != 0) {
   1293 			/*
   1294 			 * Reset the interface to pick up changes in any other
   1295 			 * flags that affect the hardware state.
   1296 			 */
   1297 			error = vr_init(sc);
   1298 		}
   1299 		break;
   1300 
   1301 	case SIOCADDMULTI:
   1302 	case SIOCDELMULTI:
   1303 		if (command == SIOCADDMULTI)
   1304 			error = ether_addmulti(ifr, &sc->vr_ec);
   1305 		else
   1306 			error = ether_delmulti(ifr, &sc->vr_ec);
   1307 
   1308 		if (error == ENETRESET) {
   1309 			/*
   1310 			 * Multicast list has changed; set the hardware filter
   1311 			 * accordingly.
   1312 			 */
   1313 			vr_setmulti(sc);
   1314 			error = 0;
   1315 		}
   1316 		break;
   1317 
   1318 	case SIOCGIFMEDIA:
   1319 	case SIOCSIFMEDIA:
   1320 		error = ifmedia_ioctl(ifp, ifr, &sc->vr_mii.mii_media, command);
   1321 		break;
   1322 
   1323 	default:
   1324 		error = EINVAL;
   1325 		break;
   1326 	}
   1327 
   1328 	splx(s);
   1329 	return (error);
   1330 }
   1331 
   1332 static void
   1333 vr_watchdog(ifp)
   1334 	struct ifnet *ifp;
   1335 {
   1336 	struct vr_softc *sc = ifp->if_softc;
   1337 
   1338 	printf("%s: device timeout\n", sc->vr_dev.dv_xname);
   1339 	ifp->if_oerrors++;
   1340 
   1341 	(void) vr_init(sc);
   1342 }
   1343 
   1344 /*
   1345  * One second timer, used to tick MII.
   1346  */
   1347 static void
   1348 vr_tick(arg)
   1349 	void *arg;
   1350 {
   1351 	struct vr_softc *sc = arg;
   1352 	int s;
   1353 
   1354 	s = splnet();
   1355 	mii_tick(&sc->vr_mii);
   1356 	splx(s);
   1357 
   1358 	callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc);
   1359 }
   1360 
   1361 /*
   1362  * Drain the receive queue.
   1363  */
   1364 static void
   1365 vr_rxdrain(sc)
   1366 	struct vr_softc *sc;
   1367 {
   1368 	struct vr_descsoft *ds;
   1369 	int i;
   1370 
   1371 	for (i = 0; i < VR_NRXDESC; i++) {
   1372 		ds = VR_DSRX(sc, i);
   1373 		if (ds->ds_mbuf != NULL) {
   1374 			bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap);
   1375 			m_freem(ds->ds_mbuf);
   1376 			ds->ds_mbuf = NULL;
   1377 		}
   1378 	}
   1379 }
   1380 
   1381 /*
   1382  * Stop the adapter and free any mbufs allocated to the
   1383  * transmit lists.
   1384  */
   1385 static void
   1386 vr_stop(sc, drain)
   1387 	struct vr_softc *sc;
   1388 	int drain;
   1389 {
   1390 	struct vr_descsoft *ds;
   1391 	struct ifnet *ifp;
   1392 	int i;
   1393 
   1394 	/* Cancel one second timer. */
   1395 	callout_stop(&sc->vr_tick_ch);
   1396 
   1397 	/* Down the MII. */
   1398 	mii_down(&sc->vr_mii);
   1399 
   1400 	ifp = &sc->vr_ec.ec_if;
   1401 	ifp->if_timer = 0;
   1402 
   1403 	VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
   1404 	VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
   1405 	CSR_WRITE_2(sc, VR_IMR, 0x0000);
   1406 	CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
   1407 	CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
   1408 
   1409 	/*
   1410 	 * Release any queued transmit buffers.
   1411 	 */
   1412 	for (i = 0; i < VR_NTXDESC; i++) {
   1413 		ds = VR_DSTX(sc, i);
   1414 		if (ds->ds_mbuf != NULL) {
   1415 			bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap);
   1416 			m_freem(ds->ds_mbuf);
   1417 			ds->ds_mbuf = NULL;
   1418 		}
   1419 	}
   1420 
   1421 	if (drain) {
   1422 		/*
   1423 		 * Release the receive buffers.
   1424 		 */
   1425 		vr_rxdrain(sc);
   1426 	}
   1427 
   1428 	/*
   1429 	 * Mark the interface down and cancel the watchdog timer.
   1430 	 */
   1431 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   1432 	ifp->if_timer = 0;
   1433 }
   1434 
   1435 static struct vr_type *vr_lookup __P((struct pci_attach_args *));
   1436 static int vr_probe __P((struct device *, struct cfdata *, void *));
   1437 static void vr_attach __P((struct device *, struct device *, void *));
   1438 static void vr_shutdown __P((void *));
   1439 
   1440 struct cfattach vr_ca = {
   1441 	sizeof (struct vr_softc), vr_probe, vr_attach
   1442 };
   1443 
   1444 static struct vr_type *
   1445 vr_lookup(pa)
   1446 	struct pci_attach_args *pa;
   1447 {
   1448 	struct vr_type *vrt;
   1449 
   1450 	for (vrt = vr_devs; vrt->vr_name != NULL; vrt++) {
   1451 		if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid &&
   1452 		    PCI_PRODUCT(pa->pa_id) == vrt->vr_did)
   1453 			return (vrt);
   1454 	}
   1455 	return (NULL);
   1456 }
   1457 
   1458 static int
   1459 vr_probe(parent, match, aux)
   1460 	struct device *parent;
   1461 	struct cfdata *match;
   1462 	void *aux;
   1463 {
   1464 	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
   1465 
   1466 	if (vr_lookup(pa) != NULL)
   1467 		return (1);
   1468 
   1469 	return (0);
   1470 }
   1471 
   1472 /*
   1473  * Stop all chip I/O so that the kernel's probe routines don't
   1474  * get confused by errant DMAs when rebooting.
   1475  */
   1476 static void
   1477 vr_shutdown(arg)
   1478 	void *arg;
   1479 {
   1480 	struct vr_softc *sc = (struct vr_softc *)arg;
   1481 
   1482 	vr_stop(sc, 1);
   1483 }
   1484 
   1485 /*
   1486  * Attach the interface. Allocate softc structures, do ifmedia
   1487  * setup and ethernet/BPF attach.
   1488  */
   1489 static void
   1490 vr_attach(parent, self, aux)
   1491 	struct device *parent;
   1492 	struct device *self;
   1493 	void *aux;
   1494 {
   1495 	struct vr_softc *sc = (struct vr_softc *) self;
   1496 	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
   1497 	bus_dma_segment_t seg;
   1498 	struct vr_type *vrt;
   1499 	u_int32_t command;
   1500 	struct ifnet *ifp;
   1501 	u_char eaddr[ETHER_ADDR_LEN];
   1502 	int i, rseg, error;
   1503 
   1504 #define	PCI_CONF_WRITE(r, v)	pci_conf_write(pa->pa_pc, pa->pa_tag, (r), (v))
   1505 #define	PCI_CONF_READ(r)	pci_conf_read(pa->pa_pc, pa->pa_tag, (r))
   1506 
   1507 	callout_init(&sc->vr_tick_ch);
   1508 
   1509 	vrt = vr_lookup(pa);
   1510 	if (vrt == NULL) {
   1511 		printf("\n");
   1512 		panic("vr_attach: impossible");
   1513 	}
   1514 
   1515 	printf(": %s Ethernet\n", vrt->vr_name);
   1516 
   1517 	/*
   1518 	 * Handle power management nonsense.
   1519 	 */
   1520 
   1521 	command = PCI_CONF_READ(VR_PCI_CAPID) & 0x000000FF;
   1522 	if (command == 0x01) {
   1523 		command = PCI_CONF_READ(VR_PCI_PWRMGMTCTRL);
   1524 		if (command & VR_PSTATE_MASK) {
   1525 			u_int32_t iobase, membase, irq;
   1526 
   1527 			/* Save important PCI config data. */
   1528 			iobase = PCI_CONF_READ(VR_PCI_LOIO);
   1529 			membase = PCI_CONF_READ(VR_PCI_LOMEM);
   1530 			irq = PCI_CONF_READ(VR_PCI_INTLINE);
   1531 
   1532 			/* Reset the power state. */
   1533 			printf("%s: chip is in D%d power mode "
   1534 				"-- setting to D0\n",
   1535 				sc->vr_dev.dv_xname, command & VR_PSTATE_MASK);
   1536 			command &= 0xFFFFFFFC;
   1537 			PCI_CONF_WRITE(VR_PCI_PWRMGMTCTRL, command);
   1538 
   1539 			/* Restore PCI config data. */
   1540 			PCI_CONF_WRITE(VR_PCI_LOIO, iobase);
   1541 			PCI_CONF_WRITE(VR_PCI_LOMEM, membase);
   1542 			PCI_CONF_WRITE(VR_PCI_INTLINE, irq);
   1543 		}
   1544 	}
   1545 
   1546 	/* Make sure bus mastering is enabled. */
   1547 	command = PCI_CONF_READ(PCI_COMMAND_STATUS_REG);
   1548 	command |= PCI_COMMAND_MASTER_ENABLE;
   1549 	PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, command);
   1550 
   1551 	/*
   1552 	 * Map control/status registers.
   1553 	 */
   1554 	{
   1555 		bus_space_tag_t iot, memt;
   1556 		bus_space_handle_t ioh, memh;
   1557 		int ioh_valid, memh_valid;
   1558 		pci_intr_handle_t intrhandle;
   1559 		const char *intrstr;
   1560 
   1561 		ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO,
   1562 			PCI_MAPREG_TYPE_IO, 0,
   1563 			&iot, &ioh, NULL, NULL) == 0);
   1564 		memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM,
   1565 			PCI_MAPREG_TYPE_MEM |
   1566 			PCI_MAPREG_MEM_TYPE_32BIT,
   1567 			0, &memt, &memh, NULL, NULL) == 0);
   1568 #if defined(VR_USEIOSPACE)
   1569 		if (ioh_valid) {
   1570 			sc->vr_bst = iot;
   1571 			sc->vr_bsh = ioh;
   1572 		} else if (memh_valid) {
   1573 			sc->vr_bst = memt;
   1574 			sc->vr_bsh = memh;
   1575 		}
   1576 #else
   1577 		if (memh_valid) {
   1578 			sc->vr_bst = memt;
   1579 			sc->vr_bsh = memh;
   1580 		} else if (ioh_valid) {
   1581 			sc->vr_bst = iot;
   1582 			sc->vr_bsh = ioh;
   1583 		}
   1584 #endif
   1585 		else {
   1586 			printf(": unable to map device registers\n");
   1587 			return;
   1588 		}
   1589 
   1590 		/* Allocate interrupt */
   1591 		if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
   1592 				pa->pa_intrline, &intrhandle)) {
   1593 			printf("%s: couldn't map interrupt\n",
   1594 				sc->vr_dev.dv_xname);
   1595 			return;
   1596 		}
   1597 		intrstr = pci_intr_string(pa->pa_pc, intrhandle);
   1598 		sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET,
   1599 						vr_intr, sc);
   1600 		if (sc->vr_ih == NULL) {
   1601 			printf("%s: couldn't establish interrupt",
   1602 				sc->vr_dev.dv_xname);
   1603 			if (intrstr != NULL)
   1604 				printf(" at %s", intrstr);
   1605 			printf("\n");
   1606 		}
   1607 		printf("%s: interrupting at %s\n",
   1608 			sc->vr_dev.dv_xname, intrstr);
   1609 	}
   1610 
   1611 	/* Reset the adapter. */
   1612 	vr_reset(sc);
   1613 
   1614 	/*
   1615 	 * Get station address. The way the Rhine chips work,
   1616 	 * you're not allowed to directly access the EEPROM once
   1617 	 * they've been programmed a special way. Consequently,
   1618 	 * we need to read the node address from the PAR0 and PAR1
   1619 	 * registers.
   1620 	 */
   1621 	VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
   1622 	DELAY(200);
   1623 	for (i = 0; i < ETHER_ADDR_LEN; i++)
   1624 		eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
   1625 
   1626 	/*
   1627 	 * A Rhine chip was detected. Inform the world.
   1628 	 */
   1629 	printf("%s: Ethernet address: %s\n",
   1630 		sc->vr_dev.dv_xname, ether_sprintf(eaddr));
   1631 
   1632 	bcopy(eaddr, sc->vr_enaddr, ETHER_ADDR_LEN);
   1633 
   1634 	sc->vr_dmat = pa->pa_dmat;
   1635 
   1636 	/*
   1637 	 * Allocate the control data structures, and create and load
   1638 	 * the DMA map for it.
   1639 	 */
   1640 	if ((error = bus_dmamem_alloc(sc->vr_dmat,
   1641 	    sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
   1642 	    0)) != 0) {
   1643 		printf("%s: unable to allocate control data, error = %d\n",
   1644 		    sc->vr_dev.dv_xname, error);
   1645 		goto fail_0;
   1646 	}
   1647 
   1648 	if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg,
   1649 	    sizeof(struct vr_control_data), (caddr_t *)&sc->vr_control_data,
   1650 	    BUS_DMA_COHERENT)) != 0) {
   1651 		printf("%s: unable to map control data, error = %d\n",
   1652 		    sc->vr_dev.dv_xname, error);
   1653 		goto fail_1;
   1654 	}
   1655 
   1656 	if ((error = bus_dmamap_create(sc->vr_dmat,
   1657 	    sizeof(struct vr_control_data), 1,
   1658 	    sizeof(struct vr_control_data), 0, 0,
   1659 	    &sc->vr_cddmamap)) != 0) {
   1660 		printf("%s: unable to create control data DMA map, "
   1661 		    "error = %d\n", sc->vr_dev.dv_xname, error);
   1662 		goto fail_2;
   1663 	}
   1664 
   1665 	if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap,
   1666 	    sc->vr_control_data, sizeof(struct vr_control_data), NULL,
   1667 	    0)) != 0) {
   1668 		printf("%s: unable to load control data DMA map, error = %d\n",
   1669 		    sc->vr_dev.dv_xname, error);
   1670 		goto fail_3;
   1671 	}
   1672 
   1673 	/*
   1674 	 * Create the transmit buffer DMA maps.
   1675 	 */
   1676 	for (i = 0; i < VR_NTXDESC; i++) {
   1677 		if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES,
   1678 		    1, MCLBYTES, 0, 0,
   1679 		    &VR_DSTX(sc, i)->ds_dmamap)) != 0) {
   1680 			printf("%s: unable to create tx DMA map %d, "
   1681 			    "error = %d\n", sc->vr_dev.dv_xname, i, error);
   1682 			goto fail_4;
   1683 		}
   1684 	}
   1685 
   1686 	/*
   1687 	 * Create the receive buffer DMA maps.
   1688 	 */
   1689 	for (i = 0; i < VR_NRXDESC; i++) {
   1690 		if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1,
   1691 		    MCLBYTES, 0, 0,
   1692 		    &VR_DSRX(sc, i)->ds_dmamap)) != 0) {
   1693 			printf("%s: unable to create rx DMA map %d, "
   1694 			    "error = %d\n", sc->vr_dev.dv_xname, i, error);
   1695 			goto fail_5;
   1696 		}
   1697 		VR_DSRX(sc, i)->ds_mbuf = NULL;
   1698 	}
   1699 
   1700 	ifp = &sc->vr_ec.ec_if;
   1701 	ifp->if_softc = sc;
   1702 	ifp->if_mtu = ETHERMTU;
   1703 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   1704 	ifp->if_ioctl = vr_ioctl;
   1705 	ifp->if_start = vr_start;
   1706 	ifp->if_watchdog = vr_watchdog;
   1707 	bcopy(sc->vr_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
   1708 
   1709 	/*
   1710 	 * Initialize MII/media info.
   1711 	 */
   1712 	sc->vr_mii.mii_ifp = ifp;
   1713 	sc->vr_mii.mii_readreg = vr_mii_readreg;
   1714 	sc->vr_mii.mii_writereg = vr_mii_writereg;
   1715 	sc->vr_mii.mii_statchg = vr_mii_statchg;
   1716 	ifmedia_init(&sc->vr_mii.mii_media, 0, vr_ifmedia_upd, vr_ifmedia_sts);
   1717 	mii_attach(&sc->vr_dev, &sc->vr_mii, 0xffffffff, MII_PHY_ANY,
   1718 	    MII_OFFSET_ANY, 0);
   1719 	if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) {
   1720 		ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
   1721 		ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE);
   1722 	} else
   1723 		ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO);
   1724 
   1725 	/*
   1726 	 * Call MI attach routines.
   1727 	 */
   1728 	if_attach(ifp);
   1729 	ether_ifattach(ifp, sc->vr_enaddr);
   1730 
   1731 #if NBPFILTER > 0
   1732 	bpfattach(&sc->vr_ec.ec_if.if_bpf,
   1733 		ifp, DLT_EN10MB, sizeof (struct ether_header));
   1734 #endif
   1735 
   1736 	sc->vr_ats = shutdownhook_establish(vr_shutdown, sc);
   1737 	if (sc->vr_ats == NULL)
   1738 		printf("%s: warning: couldn't establish shutdown hook\n",
   1739 			sc->vr_dev.dv_xname);
   1740 	return;
   1741 
   1742  fail_5:
   1743 	for (i = 0; i < VR_NRXDESC; i++) {
   1744 		if (sc->vr_rxsoft[i].ds_dmamap != NULL)
   1745 			bus_dmamap_destroy(sc->vr_dmat,
   1746 			    sc->vr_rxsoft[i].ds_dmamap);
   1747 	}
   1748  fail_4:
   1749 	for (i = 0; i < VR_NTXDESC; i++) {
   1750 		if (sc->vr_txsoft[i].ds_dmamap != NULL)
   1751 			bus_dmamap_destroy(sc->vr_dmat,
   1752 			    sc->vr_txsoft[i].ds_dmamap);
   1753 	}
   1754 	bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap);
   1755  fail_3:
   1756 	bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap);
   1757  fail_2:
   1758 	bus_dmamem_unmap(sc->vr_dmat, (caddr_t)sc->vr_control_data,
   1759 	    sizeof(struct vr_control_data));
   1760  fail_1:
   1761 	bus_dmamem_free(sc->vr_dmat, &seg, rseg);
   1762  fail_0:
   1763 	return;
   1764 }
   1765