if_vrreg.h revision 1.8
1 /* $NetBSD: if_vrreg.h,v 1.8 1999/02/05 01:10:30 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_vrreg.h,v 1.2 1999/01/10 18:51:49 wpaul Exp $ 35 */ 36 37 /* 38 * Rhine register definitions. 39 */ 40 41 #define VR_PAR0 0x00 /* node address 0 to 4 */ 42 #define VR_PAR1 0x04 /* node address 2 to 6 */ 43 #define VR_RXCFG 0x06 /* receiver config register */ 44 #define VR_TXCFG 0x07 /* transmit config register */ 45 #define VR_COMMAND 0x08 /* command register */ 46 #define VR_ISR 0x0C /* interrupt/status register */ 47 #define VR_IMR 0x0E /* interrupt mask register */ 48 #define VR_MAR0 0x10 /* multicast hash 0 */ 49 #define VR_MAR1 0x14 /* multicast hash 1 */ 50 #define VR_RXADDR 0x18 /* rx descriptor list start addr */ 51 #define VR_TXADDR 0x1C /* tx descriptor list start addr */ 52 #define VR_CURRXDESC0 0x20 53 #define VR_CURRXDESC1 0x24 54 #define VR_CURRXDESC2 0x28 55 #define VR_CURRXDESC3 0x2C 56 #define VR_NEXTRXDESC0 0x30 57 #define VR_NEXTRXDESC1 0x34 58 #define VR_NEXTRXDESC2 0x38 59 #define VR_NEXTRXDESC3 0x3C 60 #define VR_CURTXDESC0 0x40 61 #define VR_CURTXDESC1 0x44 62 #define VR_CURTXDESC2 0x48 63 #define VR_CURTXDESC3 0x4C 64 #define VR_NEXTTXDESC0 0x50 65 #define VR_NEXTTXDESC1 0x54 66 #define VR_NEXTTXDESC2 0x58 67 #define VR_NEXTTXDESC3 0x5C 68 #define VR_CURRXDMA 0x60 /* current RX DMA address */ 69 #define VR_CURTXDMA 0x64 /* current TX DMA address */ 70 #define VR_TALLYCNT 0x68 /* tally counter test register */ 71 #define VR_PHYADDR 0x6C 72 #define VR_MIISTAT 0x6D 73 #define VR_BCR0 0x6E 74 #define VR_BCR1 0x6F 75 #define VR_MIICMD 0x70 76 #define VR_MIIADDR 0x71 77 #define VR_MIIDATA 0x72 78 #define VR_EECSR 0x74 79 #define VR_TEST 0x75 80 #define VR_GPIO 0x76 81 #define VR_CONFIG 0x78 82 #define VR_MPA_CNT 0x7C 83 #define VR_CRC_CNT 0x7E 84 85 /* 86 * RX config bits. 87 */ 88 #define VR_RXCFG_RX_ERRPKTS 0x01 89 #define VR_RXCFG_RX_RUNT 0x02 90 #define VR_RXCFG_RX_MULTI 0x04 91 #define VR_RXCFG_RX_BROAD 0x08 92 #define VR_RXCFG_RX_PROMISC 0x10 93 #define VR_RXCFG_RX_THRESH 0xE0 94 95 #define VR_RXTHRESH_32BYTES 0x00 96 #define VR_RXTHRESH_64BYTES 0x20 97 #define VR_RXTHRESH_128BYTES 0x40 98 #define VR_RXTHRESH_256BYTES 0x60 99 #define VR_RXTHRESH_512BYTES 0x80 100 #define VR_RXTHRESH_768BYTES 0xA0 101 #define VR_RXTHRESH_1024BYTES 0xC0 102 #define VR_RXTHRESH_STORENFWD 0xE0 103 104 /* 105 * TX config bits. 106 */ 107 #define VR_TXCFG_RSVD0 0x01 108 #define VR_TXCFG_LOOPBKMODE 0x06 109 #define VR_TXCFG_BACKOFF 0x08 110 #define VR_TXCFG_RSVD1 0x10 111 #define VR_TXCFG_TX_THRESH 0xE0 112 113 #define VR_TXTHRESH_32BYTES 0x00 114 #define VR_TXTHRESH_64BYTES 0x20 115 #define VR_TXTHRESH_128BYTES 0x40 116 #define VR_TXTHRESH_256BYTES 0x60 117 #define VR_TXTHRESH_512BYTES 0x80 118 #define VR_TXTHRESH_768BYTES 0xA0 119 #define VR_TXTHRESH_1024BYTES 0xC0 120 #define VR_TXTHRESH_STORENFWD 0xE0 121 122 /* 123 * Command register bits. 124 */ 125 #define VR_CMD_INIT 0x0001 126 #define VR_CMD_START 0x0002 127 #define VR_CMD_STOP 0x0004 128 #define VR_CMD_RX_ON 0x0008 129 #define VR_CMD_TX_ON 0x0010 130 #define VR_CMD_TX_GO 0x0020 131 #define VR_CMD_RX_GO 0x0040 132 #define VR_CMD_RSVD 0x0080 133 #define VR_CMD_RX_EARLY 0x0100 134 #define VR_CMD_TX_EARLY 0x0200 135 #define VR_CMD_FULLDUPLEX 0x0400 136 #define VR_CMD_TX_NOPOLL 0x0800 137 138 #define VR_CMD_RESET 0x8000 139 140 /* 141 * Interrupt status bits. 142 */ 143 #define VR_ISR_RX_OK 0x0001 /* packet rx ok */ 144 #define VR_ISR_TX_OK 0x0002 /* packet tx ok */ 145 #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ 146 #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 147 #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 148 #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ 149 #define VR_ISR_BUSERR 0x0040 /* PCI bus error */ 150 #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ 151 #define VR_ISR_RX_EARLY 0x0100 /* rx early */ 152 #define VR_ISR_LINKSTAT 0x0200 /* MII status change */ 153 #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 154 #define VR_ISR_RX_DROPPED 0x0800 155 #define VR_ISR_RX_NOBUF2 0x1000 156 #define VR_ISR_TX_ABRT2 0x2000 157 #define VR_ISR_LINKSTAT2 0x4000 158 #define VR_ISR_MAGICPACKET 0x8000 159 160 /* 161 * Interrupt mask bits. 162 */ 163 #define VR_IMR_RX_OK 0x0001 /* packet rx ok */ 164 #define VR_IMR_TX_OK 0x0002 /* packet tx ok */ 165 #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ 166 #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 167 #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 168 #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ 169 #define VR_IMR_BUSERR 0x0040 /* PCI bus error */ 170 #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ 171 #define VR_IMR_RX_EARLY 0x0100 /* rx early */ 172 #define VR_IMR_LINKSTAT 0x0200 /* MII status change */ 173 #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 174 #define VR_IMR_RX_DROPPED 0x0800 175 #define VR_IMR_RX_NOBUF2 0x1000 176 #define VR_IMR_TX_ABRT2 0x2000 177 #define VR_IMR_LINKSTAT2 0x4000 178 #define VR_IMR_MAGICPACKET 0x8000 179 180 #define VR_INTRS \ 181 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ 182 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ 183 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) 184 185 /* 186 * MII status register. 187 */ 188 189 #define VR_MIISTAT_SPEED 0x01 190 #define VR_MIISTAT_LINKFAULT 0x02 191 #define VR_MIISTAT_MGTREADERR 0x04 192 #define VR_MIISTAT_MIIERR 0x08 193 #define VR_MIISTAT_PHYOPT 0x10 194 #define VR_MIISTAT_MDC_SPEED 0x20 195 #define VR_MIISTAT_RSVD 0x40 196 #define VR_MIISTAT_GPIO1POLL 0x80 197 198 /* 199 * MII command register bits. 200 */ 201 #define VR_MIICMD_CLK 0x01 202 #define VR_MIICMD_DATAIN 0x02 203 #define VR_MIICMD_DATAOUT 0x04 204 #define VR_MIICMD_DIR 0x08 205 #define VR_MIICMD_DIRECTPGM 0x10 206 #define VR_MIICMD_WRITE_ENB 0x20 207 #define VR_MIICMD_READ_ENB 0x40 208 #define VR_MIICMD_AUTOPOLL 0x80 209 210 /* 211 * EEPROM control bits. 212 */ 213 #define VR_EECSR_DATAIN 0x01 /* data out */ 214 #define VR_EECSR_DATAOUT 0x02 /* data in */ 215 #define VR_EECSR_CLK 0x04 /* clock */ 216 #define VR_EECSR_CS 0x08 /* chip select */ 217 #define VR_EECSR_DPM 0x10 218 #define VR_EECSR_LOAD 0x20 219 #define VR_EECSR_EMBP 0x40 220 #define VR_EECSR_EEPR 0x80 221 222 #define VR_EECMD_WRITE 0x140 223 #define VR_EECMD_READ 0x180 224 #define VR_EECMD_ERASE 0x1c0 225 226 /* 227 * Test register bits. 228 */ 229 #define VR_TEST_TEST0 0x01 230 #define VR_TEST_TEST1 0x02 231 #define VR_TEST_TEST2 0x04 232 #define VR_TEST_TSTUD 0x08 233 #define VR_TEST_TSTOV 0x10 234 #define VR_TEST_BKOFF 0x20 235 #define VR_TEST_FCOL 0x40 236 #define VR_TEST_HBDES 0x80 237 238 /* 239 * Config register bits. 240 */ 241 #define VR_CFG_GPIO2OUTENB 0x00000001 242 #define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */ 243 #define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */ 244 #define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */ 245 #define VR_CFG_MIIOPT 0x00000010 246 #define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */ 247 #define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */ 248 #define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */ 249 #define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */ 250 #define VR_CFG_MRREADWAIT 0x00000200 251 #define VR_CFG_MRWRITEWAIT 0x00000400 252 #define VR_CFG_RX_ARB 0x00000800 253 #define VR_CFG_TX_ARB 0x00001000 254 #define VR_CFG_READMULTI 0x00002000 255 #define VR_CFG_TX_PACE 0x00004000 256 #define VR_CFG_TX_QDIS 0x00008000 257 #define VR_CFG_ROMSEL0 0x00010000 258 #define VR_CFG_ROMSEL1 0x00020000 259 #define VR_CFG_ROMSEL2 0x00040000 260 #define VR_CFG_ROMTIMESEL 0x00080000 261 #define VR_CFG_RSVD0 0x00100000 262 #define VR_CFG_ROMDLY 0x00200000 263 #define VR_CFG_ROMOPT 0x00400000 264 #define VR_CFG_RSVD1 0x00800000 265 #define VR_CFG_BACKOFFOPT 0x01000000 266 #define VR_CFG_BACKOFFMOD 0x02000000 267 #define VR_CFG_CAPEFFECT 0x04000000 268 #define VR_CFG_BACKOFFRAND 0x08000000 269 #define VR_CFG_MAGICKPACKET 0x10000000 270 #define VR_CFG_PCIREADLINE 0x20000000 271 #define VR_CFG_DIAG 0x40000000 272 #define VR_CFG_GPIOEN 0x80000000 273 274 /* 275 * Rhine TX/RX list structure. 276 */ 277 278 struct vr_desc { 279 u_int32_t vr_status; 280 u_int32_t vr_ctl; 281 u_int32_t vr_ptr1; 282 u_int32_t vr_ptr2; 283 }; 284 285 #define vr_data vr_ptr1 286 #define vr_next vr_ptr2 287 288 289 #define VR_RXSTAT_RXERR 0x00000001 290 #define VR_RXSTAT_CRCERR 0x00000002 291 #define VR_RXSTAT_FRAMEALIGNERR 0x00000004 292 #define VR_RXSTAT_FIFOOFLOW 0x00000008 293 #define VR_RXSTAT_GIANT 0x00000010 294 #define VR_RXSTAT_RUNT 0x00000020 295 #define VR_RXSTAT_BUSERR 0x00000040 296 #define VR_RXSTAT_BUFFERR 0x00000080 297 #define VR_RXSTAT_LASTFRAG 0x00000100 298 #define VR_RXSTAT_FIRSTFRAG 0x00000200 299 #define VR_RXSTAT_RLINK 0x00000400 300 #define VR_RXSTAT_RX_PHYS 0x00000800 301 #define VR_RXSTAT_RX_BROAD 0x00001000 302 #define VR_RXSTAT_RX_MULTI 0x00002000 303 #define VR_RXSTAT_RX_OK 0x00004000 304 #define VR_RXSTAT_RXLEN 0x07FF0000 305 #define VR_RXSTAT_RXLEN_EXT 0x78000000 306 #define VR_RXSTAT_OWN 0x80000000 307 308 #define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) 309 #define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN) 310 311 #define VR_RXCTL_BUFLEN 0x000007FF 312 #define VR_RXCTL_BUFLEN_EXT 0x00007800 313 #define VR_RXCTL_CHAIN 0x00008000 314 #define VR_RXCTL_RX_INTR 0x00800000 315 316 #define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR) 317 318 #define VR_TXSTAT_DEFER 0x00000001 319 #define VR_TXSTAT_UNDERRUN 0x00000002 320 #define VR_TXSTAT_COLLCNT 0x00000078 321 #define VR_TXSTAT_SQE 0x00000080 322 #define VR_TXSTAT_ABRT 0x00000100 323 #define VR_TXSTAT_LATECOLL 0x00000200 324 #define VR_TXSTAT_CARRLOST 0x00000400 325 #define VR_TXSTAT_BUSERR 0x00002000 326 #define VR_TXSTAT_JABTIMEO 0x00004000 327 #define VR_TXSTAT_ERRSUM 0x00008000 328 #define VR_TXSTAT_OWN 0x80000000 329 330 #define VR_TXCTL_BUFLEN 0x000007FF 331 #define VR_TXCTL_BUFLEN_EXT 0x00007800 332 #define VR_TXCTL_TLINK 0x00008000 333 #define VR_TXCTL_FIRSTFRAG 0x00200000 334 #define VR_TXCTL_LASTFRAG 0x00400000 335 #define VR_TXCTL_FINT 0x00800000 336 337 338 #define VR_MAXFRAGS 16 339 #define VR_RX_LIST_CNT 64 340 #define VR_TX_LIST_CNT 64 341 #define VR_MIN_FRAMELEN 60 342 #define VR_FRAMELEN 1536 343 #define VR_RXLEN 1520 344 345 #define VR_TXOWN(x) x->vr_ptr->vr_status 346 347 /* 348 * Texas Instruments PHY identifiers 349 */ 350 #define TI_PHY_VENDORID 0x4000 351 #define TI_PHY_10BT 0x501F 352 #define TI_PHY_100VGPMI 0x502F 353 354 /* 355 * These ID values are for the NS DP83840A 10/100 PHY 356 */ 357 #define NS_PHY_VENDORID 0x2000 358 #define NS_PHY_83840A 0x5C0F 359 360 /* 361 * Level 1 10/100 PHY 362 */ 363 #define LEVEL1_PHY_VENDORID 0x7810 364 #define LEVEL1_PHY_LXT970 0x000F 365 366 /* 367 * Intel 82555 10/100 PHY 368 */ 369 #define INTEL_PHY_VENDORID 0x0A28 370 #define INTEL_PHY_82555 0x015F 371 372 /* 373 * SEEQ 80220 10/100 PHY 374 */ 375 #define SEEQ_PHY_VENDORID 0x0016 376 #define SEEQ_PHY_80220 0xF83F 377 378 379 /* 380 * PCI low memory base and low I/O base register, and 381 * other PCI registers. 382 */ 383 384 #define VR_PCI_VENDOR_ID 0x00 385 #define VR_PCI_DEVICE_ID 0x02 386 #define VR_PCI_COMMAND 0x04 387 #define VR_PCI_STATUS 0x06 388 #define VR_PCI_CLASSCODE 0x09 389 #define VR_PCI_LATENCY_TIMER 0x0D 390 #define VR_PCI_HEADER_TYPE 0x0E 391 #define VR_PCI_LOIO 0x10 392 #define VR_PCI_LOMEM 0x14 393 #define VR_PCI_BIOSROM 0x30 394 #define VR_PCI_INTLINE 0x3C 395 #define VR_PCI_INTPIN 0x3D 396 #define VR_PCI_MINGNT 0x3E 397 #define VR_PCI_MINLAT 0x0F 398 #define VR_PCI_RESETOPT 0x48 399 #define VR_PCI_EEPROM_DATA 0x4C 400 401 /* power management registers */ 402 #define VR_PCI_CAPID 0xDC /* 8 bits */ 403 #define VR_PCI_NEXTPTR 0xDD /* 8 bits */ 404 #define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 405 #define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 406 407 #define VR_PSTATE_MASK 0x0003 408 #define VR_PSTATE_D0 0x0000 409 #define VR_PSTATE_D1 0x0002 410 #define VR_PSTATE_D2 0x0002 411 #define VR_PSTATE_D3 0x0003 412 #define VR_PME_EN 0x0010 413 #define VR_PME_STATUS 0x8000 414 415 #define PHY_UNKNOWN 6 416 417 #define VR_PHYADDR_MIN 0x00 418 #define VR_PHYADDR_MAX 0x1F 419 420 #define PHY_BMCR 0x00 421 #define PHY_BMSR 0x01 422 #define PHY_VENID 0x02 423 #define PHY_DEVID 0x03 424 #define PHY_ANAR 0x04 425 #define PHY_LPAR 0x05 426 #define PHY_ANEXP 0x06 427 428 #define PHY_ANAR_NEXTPAGE 0x8000 429 #define PHY_ANAR_RSVD0 0x4000 430 #define PHY_ANAR_TLRFLT 0x2000 431 #define PHY_ANAR_RSVD1 0x1000 432 #define PHY_ANAR_RSVD2 0x0800 433 #define PHY_ANAR_RSVD3 0x0400 434 #define PHY_ANAR_100BT4 0x0200 435 #define PHY_ANAR_100BTXFULL 0x0100 436 #define PHY_ANAR_100BTXHALF 0x0080 437 #define PHY_ANAR_10BTFULL 0x0040 438 #define PHY_ANAR_10BTHALF 0x0020 439 #define PHY_ANAR_PROTO4 0x0010 440 #define PHY_ANAR_PROTO3 0x0008 441 #define PHY_ANAR_PROTO2 0x0004 442 #define PHY_ANAR_PROTO1 0x0002 443 #define PHY_ANAR_PROTO0 0x0001 444 445 /* 446 * These are the register definitions for the PHY (physical layer 447 * interface chip). 448 */ 449 /* 450 * PHY BMCR Basic Mode Control Register 451 */ 452 #define PHY_BMCR_RESET 0x8000 453 #define PHY_BMCR_LOOPBK 0x4000 454 #define PHY_BMCR_SPEEDSEL 0x2000 455 #define PHY_BMCR_AUTONEGENBL 0x1000 456 #define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 457 #define PHY_BMCR_ISOLATE 0x0400 458 #define PHY_BMCR_AUTONEGRSTR 0x0200 459 #define PHY_BMCR_DUPLEX 0x0100 460 #define PHY_BMCR_COLLTEST 0x0080 461 #define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 462 #define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 463 #define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 464 #define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 465 #define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 466 #define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 467 #define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 468 /* 469 * RESET: 1 == software reset, 0 == normal operation 470 * Resets status and control registers to default values. 471 * Relatches all hardware config values. 472 * 473 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 474 * 475 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 476 * Link speed is selected byt his bit or if auto-negotiation if bit 477 * 12 (AUTONEGENBL) is set (in which case the value of this register 478 * is ignored). 479 * 480 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 481 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 482 * determine speed and mode. Should be cleared and then set if PHY configured 483 * for no autoneg on startup. 484 * 485 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 486 * 487 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 488 * 489 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 490 * 491 * COLLTEST: 1 == collision test enabled, 0 == normal operation 492 */ 493 494 /* 495 * PHY, BMSR Basic Mode Status Register 496 */ 497 #define PHY_BMSR_100BT4 0x8000 498 #define PHY_BMSR_100BTXFULL 0x4000 499 #define PHY_BMSR_100BTXHALF 0x2000 500 #define PHY_BMSR_10BTFULL 0x1000 501 #define PHY_BMSR_10BTHALF 0x0800 502 #define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 503 #define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 504 #define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 505 #define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 506 #define PHY_BMSR_MFPRESUP 0x0040 507 #define PHY_BMSR_AUTONEGCOMP 0x0020 508 #define PHY_BMSR_REMFAULT 0x0010 509 #define PHY_BMSR_CANAUTONEG 0x0008 510 #define PHY_BMSR_LINKSTAT 0x0004 511 #define PHY_BMSR_JABBER 0x0002 512 #define PHY_BMSR_EXTENDED 0x0001 513
Indexes created Sat Sep 27 14:09:57 GMT 2025