if_vte.c revision 1.1.2.2
1 /* $NetBSD: if_vte.c,v 1.1.2.2 2011/02/08 16:19:50 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2010, Pyun YongHyeon <yongari (at) FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 54 55 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.1.2.2 2011/02/08 16:19:50 bouyer Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/mbuf.h> 63 #include <sys/protosw.h> 64 #include <sys/socket.h> 65 #include <sys/ioctl.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_dl.h> 76 #include <net/route.h> 77 #include <net/netisr.h> 78 79 #include <net/bpf.h> 80 #include <net/bpfdesc.h> 81 82 #include "rnd.h" 83 #if NRND > 0 84 #include <sys/rnd.h> 85 #endif 86 87 #include "opt_inet.h" 88 #include <net/if_ether.h> 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/in_systm.h> 92 #include <netinet/in_var.h> 93 #include <netinet/ip.h> 94 #include <netinet/if_inarp.h> 95 #endif 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 100 #include <dev/pci/pcireg.h> 101 #include <dev/pci/pcivar.h> 102 #include <dev/pci/pcidevs.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 107 #include <dev/pci/if_vtereg.h> 108 #include <dev/pci/if_vtevar.h> 109 110 static int vte_match(device_t, cfdata_t, void *); 111 static void vte_attach(device_t, device_t, void *); 112 static int vte_detach(device_t, int); 113 static int vte_dma_alloc(struct vte_softc *); 114 static void vte_dma_free(struct vte_softc *); 115 static struct vte_txdesc * 116 vte_encap(struct vte_softc *, struct mbuf **); 117 static void vte_get_macaddr(struct vte_softc *); 118 static int vte_init(struct ifnet *); 119 static int vte_init_rx_ring(struct vte_softc *); 120 static int vte_init_tx_ring(struct vte_softc *); 121 static int vte_intr(void *); 122 static int vte_ifioctl(struct ifnet *, u_long, void *); 123 static void vte_mac_config(struct vte_softc *); 124 static int vte_miibus_readreg(device_t, int, int); 125 static void vte_miibus_statchg(device_t); 126 static void vte_miibus_writereg(device_t, int, int, int); 127 static int vte_mediachange(struct ifnet *); 128 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 129 static void vte_reset(struct vte_softc *); 130 static void vte_rxeof(struct vte_softc *); 131 static void vte_rxfilter(struct vte_softc *); 132 static bool vte_shutdown(device_t, int); 133 static bool vte_suspend(device_t, const pmf_qual_t *); 134 static bool vte_resume(device_t, const pmf_qual_t *); 135 static void vte_ifstart(struct ifnet *); 136 static void vte_start_mac(struct vte_softc *); 137 static void vte_stats_clear(struct vte_softc *); 138 static void vte_stats_update(struct vte_softc *); 139 static void vte_stop(struct ifnet *, int); 140 static void vte_stop_mac(struct vte_softc *); 141 static void vte_tick(void *); 142 static void vte_txeof(struct vte_softc *); 143 static void vte_ifwatchdog(struct ifnet *); 144 145 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 146 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 147 static int vte_root_num; 148 149 #define DPRINTF(a) 150 151 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 152 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 153 154 155 static int 156 vte_match(device_t parent, cfdata_t cf, void *aux) 157 { 158 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 159 160 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 161 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 162 return 1; 163 164 return 0; 165 } 166 167 static void 168 vte_attach(device_t parent, device_t self, void *aux) 169 { 170 struct vte_softc *sc = device_private(self); 171 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 172 struct ifnet * const ifp = &sc->vte_if; 173 int h_valid; 174 pcireg_t reg, csr; 175 pci_intr_handle_t intrhandle; 176 const char *intrstr; 177 int error; 178 char devinfo[256]; 179 const struct sysctlnode *node; 180 int vte_nodenum; 181 182 sc->vte_dev = self; 183 aprint_normal("\n"); 184 185 callout_init(&sc->vte_tick_ch, 0); 186 187 /* Map the device. */ 188 h_valid = 0; 189 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 190 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 191 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 192 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 193 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 194 } 195 if (h_valid == 0) { 196 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 197 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 198 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 199 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 200 &sc->vte_bushandle, NULL, NULL) == 0); 201 } 202 } 203 if (h_valid == 0) { 204 aprint_error_dev(self, "unable to map device registers\n"); 205 return; 206 } 207 sc->vte_dmatag = pa->pa_dmat; 208 /* Enable the device. */ 209 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 210 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 211 csr | PCI_COMMAND_MASTER_ENABLE); 212 213 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 214 aprint_normal_dev(self, "%s\n", devinfo); 215 216 /* Reset the ethernet controller. */ 217 vte_reset(sc); 218 219 if ((error = vte_dma_alloc(sc) != 0)) 220 return; 221 222 /* Load station address. */ 223 vte_get_macaddr(sc); 224 225 aprint_normal_dev(self, "Ethernet address %s\n", 226 ether_sprintf(sc->vte_eaddr)); 227 228 /* Map and establish interrupts */ 229 if (pci_intr_map(pa, &intrhandle)) { 230 aprint_error_dev(self, "couldn't map interrupt\n"); 231 return; 232 } 233 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 234 sc->vte_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 235 vte_intr, sc); 236 if (sc->vte_ih == NULL) { 237 aprint_error_dev(self, "couldn't establish interrupt"); 238 if (intrstr != NULL) 239 aprint_error(" at %s", intrstr); 240 aprint_error("\n"); 241 return; 242 } 243 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 244 245 sc->vte_if.if_softc = sc; 246 sc->vte_mii.mii_ifp = ifp; 247 sc->vte_mii.mii_readreg = vte_miibus_readreg; 248 sc->vte_mii.mii_writereg = vte_miibus_writereg; 249 sc->vte_mii.mii_statchg = vte_miibus_statchg; 250 sc->vte_ec.ec_mii = &sc->vte_mii; 251 ifmedia_init(&sc->vte_mii.mii_media, IFM_IMASK, vte_mediachange, 252 ether_mediastatus); 253 mii_attach(self, &sc->vte_mii, 0xffffffff, MII_PHY_ANY, 254 MII_OFFSET_ANY, 0); 255 if (LIST_FIRST(&sc->vte_mii.mii_phys) == NULL) { 256 ifmedia_add(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 257 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE); 258 } else 259 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_AUTO); 260 261 /* 262 * We can support 802.1Q VLAN-sized frames. 263 */ 264 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 265 266 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 267 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 268 ifp->if_ioctl = vte_ifioctl; 269 ifp->if_start = vte_ifstart; 270 ifp->if_watchdog = vte_ifwatchdog; 271 ifp->if_init = vte_init; 272 ifp->if_stop = vte_stop; 273 ifp->if_timer = 0; 274 IFQ_SET_READY(&ifp->if_snd); 275 if_attach(ifp); 276 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 277 278 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 279 pmf_class_network_register(self, ifp); 280 else 281 aprint_error_dev(self, "couldn't establish power handler\n"); 282 283 #if NRND > 0 284 rnd_attach_source(&sc->rnd_source, device_xname(self), 285 RND_TYPE_NET, 0); 286 #endif 287 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 288 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 289 SYSCTL_DESCR("vte per-controller controls"), 290 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 291 CTL_EOL) != 0) { 292 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 293 return; 294 } 295 vte_nodenum = node->sysctl_num; 296 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 297 CTLFLAG_READWRITE, 298 CTLTYPE_INT, "int_rxct", 299 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 300 vte_sysctl_intrxct, 0, sc, 301 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 302 CTL_EOL) != 0) { 303 aprint_normal_dev(sc->vte_dev, 304 "couldn't create int_rxct sysctl node\n"); 305 } 306 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 307 CTLFLAG_READWRITE, 308 CTLTYPE_INT, "int_txct", 309 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 310 vte_sysctl_inttxct, 0, sc, 311 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 312 CTL_EOL) != 0) { 313 aprint_normal_dev(sc->vte_dev, 314 "couldn't create int_txct sysctl node\n"); 315 } 316 } 317 318 static int 319 vte_detach(device_t dev, int flags __unused) 320 { 321 struct vte_softc *sc = device_private(dev); 322 struct ifnet *ifp = &sc->vte_if; 323 int s; 324 325 s = splnet(); 326 /* Stop the interface. Callouts are stopped in it. */ 327 vte_stop(ifp, 1); 328 splx(s); 329 330 pmf_device_deregister(dev); 331 332 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 333 ifmedia_delete_instance(&sc->vte_mii.mii_media, IFM_INST_ANY); 334 335 ether_ifdetach(ifp); 336 if_detach(ifp); 337 338 vte_dma_free(sc); 339 340 return (0); 341 } 342 343 static int 344 vte_miibus_readreg(device_t dev, int phy, int reg) 345 { 346 struct vte_softc *sc = device_private(dev); 347 int i; 348 349 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 350 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 351 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 352 DELAY(5); 353 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 354 break; 355 } 356 357 if (i == 0) { 358 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 359 return (0); 360 } 361 362 return (CSR_READ_2(sc, VTE_MMRD)); 363 } 364 365 static void 366 vte_miibus_writereg(device_t dev, int phy, int reg, int val) 367 { 368 struct vte_softc *sc = device_private(dev); 369 int i; 370 371 CSR_WRITE_2(sc, VTE_MMWD, val); 372 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 373 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 374 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 375 DELAY(5); 376 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 377 break; 378 } 379 380 if (i == 0) 381 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 382 383 } 384 385 static void 386 vte_miibus_statchg(device_t dev) 387 { 388 struct vte_softc *sc = device_private(dev); 389 struct ifnet *ifp; 390 uint16_t val; 391 392 ifp = &sc->vte_if; 393 394 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 395 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 396 397 sc->vte_flags &= ~VTE_FLAG_LINK; 398 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 399 (IFM_ACTIVE | IFM_AVALID)) { 400 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 401 case IFM_10_T: 402 case IFM_100_TX: 403 sc->vte_flags |= VTE_FLAG_LINK; 404 break; 405 default: 406 break; 407 } 408 } 409 410 /* Stop RX/TX MACs. */ 411 vte_stop_mac(sc); 412 /* Program MACs with resolved duplex and flow control. */ 413 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 414 /* 415 * Timer waiting time : (63 + TIMER * 64) MII clock. 416 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 417 */ 418 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 419 val = 18 << VTE_IM_TIMER_SHIFT; 420 else 421 val = 1 << VTE_IM_TIMER_SHIFT; 422 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 423 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 424 CSR_WRITE_2(sc, VTE_MRICR, val); 425 426 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 427 val = 18 << VTE_IM_TIMER_SHIFT; 428 else 429 val = 1 << VTE_IM_TIMER_SHIFT; 430 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 431 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 432 CSR_WRITE_2(sc, VTE_MTICR, val); 433 434 vte_mac_config(sc); 435 vte_start_mac(sc); 436 DPRINTF(("vte_miibus_statchg: link\n")); 437 } 438 } 439 440 static void 441 vte_get_macaddr(struct vte_softc *sc) 442 { 443 uint16_t mid; 444 445 /* 446 * It seems there is no way to reload station address and 447 * it is supposed to be set by BIOS. 448 */ 449 mid = CSR_READ_2(sc, VTE_MID0L); 450 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 451 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 452 mid = CSR_READ_2(sc, VTE_MID0M); 453 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 454 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 455 mid = CSR_READ_2(sc, VTE_MID0H); 456 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 457 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 458 } 459 460 461 static int 462 vte_dma_alloc(struct vte_softc *sc) 463 { 464 struct vte_txdesc *txd; 465 struct vte_rxdesc *rxd; 466 int error, i, rseg; 467 468 /* create DMA map for TX ring */ 469 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 470 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 471 &sc->vte_cdata.vte_tx_ring_map); 472 if (error) { 473 aprint_error_dev(sc->vte_dev, 474 "could not create dma map for TX ring (%d)\n", 475 error); 476 goto fail; 477 } 478 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 479 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 480 VTE_TX_RING_ALIGN, 0, 481 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 482 BUS_DMA_NOWAIT); 483 if (error != 0) { 484 aprint_error_dev(sc->vte_dev, 485 "could not allocate DMA'able memory for TX ring (%d).\n", 486 error); 487 goto fail; 488 } 489 KASSERT(rseg == 1); 490 error = bus_dmamem_map(sc->vte_dmatag, 491 sc->vte_cdata.vte_tx_ring_seg, 1, 492 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 493 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 494 if (error != 0) { 495 aprint_error_dev(sc->vte_dev, 496 "could not map DMA'able memory for TX ring (%d).\n", 497 error); 498 goto fail; 499 } 500 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 501 error = bus_dmamap_load(sc->vte_dmatag, 502 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 503 VTE_TX_RING_SZ, NULL, 504 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 505 if (error != 0) { 506 aprint_error_dev(sc->vte_dev, 507 "could not load DMA'able memory for TX ring.\n"); 508 goto fail; 509 } 510 511 /* create DMA map for RX ring */ 512 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 513 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 514 &sc->vte_cdata.vte_rx_ring_map); 515 if (error) { 516 aprint_error_dev(sc->vte_dev, 517 "could not create dma map for RX ring (%d)\n", 518 error); 519 goto fail; 520 } 521 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 522 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 523 VTE_RX_RING_ALIGN, 0, 524 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 525 BUS_DMA_NOWAIT); 526 if (error != 0) { 527 aprint_error_dev(sc->vte_dev, 528 "could not allocate DMA'able memory for RX ring (%d).\n", 529 error); 530 goto fail; 531 } 532 KASSERT(rseg == 1); 533 error = bus_dmamem_map(sc->vte_dmatag, 534 sc->vte_cdata.vte_rx_ring_seg, 1, 535 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 536 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 537 if (error != 0) { 538 aprint_error_dev(sc->vte_dev, 539 "could not map DMA'able memory for RX ring (%d).\n", 540 error); 541 goto fail; 542 } 543 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 544 error = bus_dmamap_load(sc->vte_dmatag, 545 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 546 VTE_RX_RING_SZ, NULL, 547 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 548 if (error != 0) { 549 aprint_error_dev(sc->vte_dev, 550 "could not load DMA'able memory for RX ring (%d).\n", 551 error); 552 goto fail; 553 } 554 555 /* Create DMA maps for TX buffers. */ 556 for (i = 0; i < VTE_TX_RING_CNT; i++) { 557 txd = &sc->vte_cdata.vte_txdesc[i]; 558 txd->tx_m = NULL; 559 txd->tx_dmamap = NULL; 560 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 561 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 562 &txd->tx_dmamap); 563 if (error != 0) { 564 aprint_error_dev(sc->vte_dev, 565 "could not create TX DMA map %d (%d).\n", i, error); 566 goto fail; 567 } 568 } 569 /* Create DMA maps for RX buffers. */ 570 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 571 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 572 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 573 aprint_error_dev(sc->vte_dev, 574 "could not create spare RX dmamap (%d).\n", error); 575 goto fail; 576 } 577 for (i = 0; i < VTE_RX_RING_CNT; i++) { 578 rxd = &sc->vte_cdata.vte_rxdesc[i]; 579 rxd->rx_m = NULL; 580 rxd->rx_dmamap = NULL; 581 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 582 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 583 &rxd->rx_dmamap); 584 if (error != 0) { 585 aprint_error_dev(sc->vte_dev, 586 "could not create RX dmamap %d (%d).\n", i, error); 587 goto fail; 588 } 589 } 590 return 0; 591 592 fail: 593 vte_dma_free(sc); 594 return (error); 595 } 596 597 static void 598 vte_dma_free(struct vte_softc *sc) 599 { 600 struct vte_txdesc *txd; 601 struct vte_rxdesc *rxd; 602 int i; 603 604 /* TX buffers. */ 605 for (i = 0; i < VTE_TX_RING_CNT; i++) { 606 txd = &sc->vte_cdata.vte_txdesc[i]; 607 if (txd->tx_dmamap != NULL) { 608 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 609 txd->tx_dmamap = NULL; 610 } 611 } 612 /* RX buffers */ 613 for (i = 0; i < VTE_RX_RING_CNT; i++) { 614 rxd = &sc->vte_cdata.vte_rxdesc[i]; 615 if (rxd->rx_dmamap != NULL) { 616 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 617 rxd->rx_dmamap = NULL; 618 } 619 } 620 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 621 bus_dmamap_destroy(sc->vte_dmatag, 622 sc->vte_cdata.vte_rx_sparemap); 623 sc->vte_cdata.vte_rx_sparemap = NULL; 624 } 625 /* TX descriptor ring. */ 626 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 627 bus_dmamap_unload(sc->vte_dmatag, 628 sc->vte_cdata.vte_tx_ring_map); 629 bus_dmamap_destroy(sc->vte_dmatag, 630 sc->vte_cdata.vte_tx_ring_map); 631 } 632 if (sc->vte_cdata.vte_tx_ring != NULL) { 633 bus_dmamem_unmap(sc->vte_dmatag, 634 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 635 bus_dmamem_free(sc->vte_dmatag, 636 sc->vte_cdata.vte_tx_ring_seg, 1); 637 } 638 sc->vte_cdata.vte_tx_ring = NULL; 639 sc->vte_cdata.vte_tx_ring_map = NULL; 640 /* RX ring. */ 641 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 642 bus_dmamap_unload(sc->vte_dmatag, 643 sc->vte_cdata.vte_rx_ring_map); 644 bus_dmamap_destroy(sc->vte_dmatag, 645 sc->vte_cdata.vte_rx_ring_map); 646 } 647 if (sc->vte_cdata.vte_rx_ring != NULL) { 648 bus_dmamem_unmap(sc->vte_dmatag, 649 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 650 bus_dmamem_free(sc->vte_dmatag, 651 sc->vte_cdata.vte_rx_ring_seg, 1); 652 } 653 sc->vte_cdata.vte_rx_ring = NULL; 654 sc->vte_cdata.vte_rx_ring_map = NULL; 655 } 656 657 static bool 658 vte_shutdown(device_t dev, int howto) 659 { 660 661 return (vte_suspend(dev, NULL)); 662 } 663 664 static bool 665 vte_suspend(device_t dev, const pmf_qual_t *qual) 666 { 667 struct vte_softc *sc = device_private(dev); 668 struct ifnet *ifp = &sc->vte_if; 669 670 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 671 if ((ifp->if_flags & IFF_RUNNING) != 0) 672 vte_stop(ifp, 1); 673 return (0); 674 } 675 676 static bool 677 vte_resume(device_t dev, const pmf_qual_t *qual) 678 { 679 struct vte_softc *sc = device_private(dev); 680 struct ifnet *ifp; 681 682 ifp = &sc->vte_if; 683 if ((ifp->if_flags & IFF_UP) != 0) { 684 ifp->if_flags &= ~IFF_RUNNING; 685 vte_init(ifp); 686 } 687 688 return (0); 689 } 690 691 static struct vte_txdesc * 692 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 693 { 694 struct vte_txdesc *txd; 695 struct mbuf *m, *n; 696 int copy, error, padlen; 697 698 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 699 m = *m_head; 700 /* 701 * Controller doesn't auto-pad, so we have to make sure pad 702 * short frames out to the minimum frame length. 703 */ 704 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 705 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 706 else 707 padlen = 0; 708 709 /* 710 * Controller does not support multi-fragmented TX buffers. 711 * Controller spends most of its TX processing time in 712 * de-fragmenting TX buffers. Either faster CPU or more 713 * advanced controller DMA engine is required to speed up 714 * TX path processing. 715 * To mitigate the de-fragmenting issue, perform deep copy 716 * from fragmented mbuf chains to a pre-allocated mbuf 717 * cluster with extra cost of kernel memory. For frames 718 * that is composed of single TX buffer, the deep copy is 719 * bypassed. 720 */ 721 copy = 0; 722 if (m->m_next != NULL) 723 copy++; 724 if (padlen > 0 && (M_READONLY(m) || 725 padlen > M_TRAILINGSPACE(m))) 726 copy++; 727 if (copy != 0) { 728 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 729 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 730 n->m_pkthdr.len = m->m_pkthdr.len; 731 n->m_len = m->m_pkthdr.len; 732 m = n; 733 txd->tx_flags |= VTE_TXMBUF; 734 } 735 736 if (padlen > 0) { 737 /* Zero out the bytes in the pad area. */ 738 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 739 m->m_pkthdr.len += padlen; 740 m->m_len = m->m_pkthdr.len; 741 } 742 743 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 0); 744 if (error != 0) { 745 txd->tx_flags &= ~VTE_TXMBUF; 746 return (NULL); 747 } 748 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 749 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 750 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 751 752 txd->tx_desc->dtlen = 753 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 754 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 755 sc->vte_cdata.vte_tx_cnt++; 756 /* Update producer index. */ 757 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 758 759 /* Finally hand over ownership to controller. */ 760 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 761 txd->tx_m = m; 762 763 return (txd); 764 } 765 766 static void 767 vte_ifstart(struct ifnet *ifp) 768 { 769 struct vte_softc *sc = ifp->if_softc; 770 struct vte_txdesc *txd; 771 struct mbuf *m_head, *m; 772 int enq; 773 774 ifp = &sc->vte_if; 775 776 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 777 778 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 779 IFF_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 780 return; 781 782 for (enq = 0; !IFQ_IS_EMPTY(&ifp->if_snd); ) { 783 /* Reserve one free TX descriptor. */ 784 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 785 ifp->if_flags |= IFF_OACTIVE; 786 break; 787 } 788 IFQ_POLL(&ifp->if_snd, m_head); 789 if (m_head == NULL) 790 break; 791 /* 792 * Pack the data into the transmit ring. If we 793 * don't have room, set the OACTIVE flag and wait 794 * for the NIC to drain the ring. 795 */ 796 DPRINTF(("vte_encap:")); 797 if ((txd = vte_encap(sc, &m_head)) == NULL) { 798 DPRINTF((" failed\n")); 799 break; 800 } 801 DPRINTF((" ok\n")); 802 IFQ_DEQUEUE(&ifp->if_snd, m); 803 KASSERT(m == m_head); 804 805 enq++; 806 /* 807 * If there's a BPF listener, bounce a copy of this frame 808 * to him. 809 */ 810 bpf_mtap(ifp, m_head); 811 /* Free consumed TX frame. */ 812 if ((txd->tx_flags & VTE_TXMBUF) != 0) 813 m_freem(m_head); 814 } 815 816 if (enq > 0) { 817 bus_dmamap_sync(sc->vte_dmatag, 818 sc->vte_cdata.vte_tx_ring_map, 0, 819 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 820 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 821 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 822 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 823 } 824 } 825 826 static void 827 vte_ifwatchdog(struct ifnet *ifp) 828 { 829 struct vte_softc *sc = ifp->if_softc; 830 831 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 832 return; 833 834 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 835 ifp->if_oerrors++; 836 vte_init(ifp); 837 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 838 vte_ifstart(ifp); 839 } 840 841 static int 842 vte_mediachange(struct ifnet *ifp) 843 { 844 int error; 845 struct vte_softc *sc = ifp->if_softc; 846 847 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 848 error = 0; 849 else if (error != 0) { 850 aprint_error_dev(sc->vte_dev, "could not set media\n"); 851 return error; 852 } 853 return 0; 854 855 } 856 857 static int 858 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 859 { 860 struct vte_softc *sc = ifp->if_softc; 861 int error, s; 862 863 s = splnet(); 864 error = ether_ioctl(ifp, cmd, data); 865 if (error == ENETRESET) { 866 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 867 if (ifp->if_flags & IFF_RUNNING) 868 vte_rxfilter(sc); 869 error = 0; 870 } 871 splx(s); 872 return error; 873 } 874 875 static void 876 vte_mac_config(struct vte_softc *sc) 877 { 878 uint16_t mcr; 879 880 mcr = CSR_READ_2(sc, VTE_MCR0); 881 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 882 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 883 mcr |= MCR0_FULL_DUPLEX; 884 #ifdef notyet 885 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 886 mcr |= MCR0_FC_ENB; 887 /* 888 * The data sheet is not clear whether the controller 889 * honors received pause frames or not. The is no 890 * separate control bit for RX pause frame so just 891 * enable MCR0_FC_ENB bit. 892 */ 893 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 894 mcr |= MCR0_FC_ENB; 895 #endif 896 } 897 CSR_WRITE_2(sc, VTE_MCR0, mcr); 898 } 899 900 static void 901 vte_stats_clear(struct vte_softc *sc) 902 { 903 904 /* Reading counter registers clears its contents. */ 905 CSR_READ_2(sc, VTE_CNT_RX_DONE); 906 CSR_READ_2(sc, VTE_CNT_MECNT0); 907 CSR_READ_2(sc, VTE_CNT_MECNT1); 908 CSR_READ_2(sc, VTE_CNT_MECNT2); 909 CSR_READ_2(sc, VTE_CNT_MECNT3); 910 CSR_READ_2(sc, VTE_CNT_TX_DONE); 911 CSR_READ_2(sc, VTE_CNT_MECNT4); 912 CSR_READ_2(sc, VTE_CNT_PAUSE); 913 } 914 915 static void 916 vte_stats_update(struct vte_softc *sc) 917 { 918 struct vte_hw_stats *stat; 919 struct ifnet *ifp = &sc->vte_if; 920 uint16_t value; 921 922 stat = &sc->vte_stats; 923 924 CSR_READ_2(sc, VTE_MECISR); 925 /* RX stats. */ 926 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 927 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 928 stat->rx_bcast_frames += (value >> 8); 929 stat->rx_mcast_frames += (value & 0xFF); 930 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 931 stat->rx_runts += (value >> 8); 932 stat->rx_crcerrs += (value & 0xFF); 933 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 934 stat->rx_long_frames += (value & 0xFF); 935 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 936 stat->rx_fifo_full += (value >> 8); 937 stat->rx_desc_unavail += (value & 0xFF); 938 939 /* TX stats. */ 940 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 941 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 942 stat->tx_underruns += (value >> 8); 943 stat->tx_late_colls += (value & 0xFF); 944 945 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 946 stat->tx_pause_frames += (value >> 8); 947 stat->rx_pause_frames += (value & 0xFF); 948 949 /* Update ifp counters. */ 950 ifp->if_opackets = stat->tx_frames; 951 ifp->if_collisions = stat->tx_late_colls; 952 ifp->if_oerrors = stat->tx_late_colls + stat->tx_underruns; 953 ifp->if_ipackets = stat->rx_frames; 954 ifp->if_ierrors = stat->rx_crcerrs + stat->rx_runts + 955 stat->rx_long_frames + stat->rx_fifo_full; 956 } 957 958 static int 959 vte_intr(void *arg) 960 { 961 struct vte_softc *sc = (struct vte_softc *)arg; 962 struct ifnet *ifp = &sc->vte_if; 963 uint16_t status; 964 int n; 965 966 /* Reading VTE_MISR acknowledges interrupts. */ 967 status = CSR_READ_2(sc, VTE_MISR); 968 DPRINTF(("vte_intr status 0x%x\n", status)); 969 if ((status & VTE_INTRS) == 0) { 970 /* Not ours. */ 971 return 0; 972 } 973 974 /* Disable interrupts. */ 975 CSR_WRITE_2(sc, VTE_MIER, 0); 976 for (n = 8; (status & VTE_INTRS) != 0;) { 977 if ((ifp->if_flags & IFF_RUNNING) == 0) 978 break; 979 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 980 MISR_RX_FIFO_FULL)) != 0) 981 vte_rxeof(sc); 982 if ((status & MISR_TX_DONE) != 0) 983 vte_txeof(sc); 984 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 985 vte_stats_update(sc); 986 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 987 vte_ifstart(ifp); 988 if (--n > 0) 989 status = CSR_READ_2(sc, VTE_MISR); 990 else 991 break; 992 } 993 994 if ((ifp->if_flags & IFF_RUNNING) != 0) { 995 /* Re-enable interrupts. */ 996 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 997 } 998 return 1; 999 } 1000 1001 static void 1002 vte_txeof(struct vte_softc *sc) 1003 { 1004 struct ifnet *ifp; 1005 struct vte_txdesc *txd; 1006 uint16_t status; 1007 int cons, prog; 1008 1009 ifp = &sc->vte_if; 1010 1011 if (sc->vte_cdata.vte_tx_cnt == 0) 1012 return; 1013 bus_dmamap_sync(sc->vte_dmatag, 1014 sc->vte_cdata.vte_tx_ring_map, 0, 1015 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1016 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1017 cons = sc->vte_cdata.vte_tx_cons; 1018 /* 1019 * Go through our TX list and free mbufs for those 1020 * frames which have been transmitted. 1021 */ 1022 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1023 txd = &sc->vte_cdata.vte_txdesc[cons]; 1024 status = le16toh(txd->tx_desc->dtst); 1025 if ((status & VTE_DTST_TX_OWN) != 0) 1026 break; 1027 sc->vte_cdata.vte_tx_cnt--; 1028 /* Reclaim transmitted mbufs. */ 1029 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1030 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1031 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1032 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1033 m_freem(txd->tx_m); 1034 txd->tx_flags &= ~VTE_TXMBUF; 1035 txd->tx_m = NULL; 1036 prog++; 1037 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1038 } 1039 1040 if (prog > 0) { 1041 ifp->if_flags &= ~IFF_OACTIVE; 1042 sc->vte_cdata.vte_tx_cons = cons; 1043 /* 1044 * Unarm watchdog timer only when there is no pending 1045 * frames in TX queue. 1046 */ 1047 if (sc->vte_cdata.vte_tx_cnt == 0) 1048 sc->vte_watchdog_timer = 0; 1049 } 1050 } 1051 1052 static int 1053 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1054 { 1055 struct mbuf *m; 1056 bus_dmamap_t map; 1057 1058 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1059 if (m == NULL) 1060 return (ENOBUFS); 1061 m->m_len = m->m_pkthdr.len = MCLBYTES; 1062 m_adj(m, sizeof(uint32_t)); 1063 1064 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1065 sc->vte_cdata.vte_rx_sparemap, m, 0) != 0) { 1066 m_freem(m); 1067 return (ENOBUFS); 1068 } 1069 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1070 1071 if (rxd->rx_m != NULL) { 1072 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1073 0, rxd->rx_dmamap->dm_mapsize, 1074 BUS_DMASYNC_POSTREAD); 1075 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1076 } 1077 map = rxd->rx_dmamap; 1078 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1079 sc->vte_cdata.vte_rx_sparemap = map; 1080 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1081 0, rxd->rx_dmamap->dm_mapsize, 1082 BUS_DMASYNC_PREREAD); 1083 rxd->rx_m = m; 1084 rxd->rx_desc->drbp = 1085 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1086 rxd->rx_desc->drlen = htole16( 1087 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1088 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, rxd->rx_dmamap->dm_segs[0].ds_len)); 1089 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1090 1091 return (0); 1092 } 1093 1094 static void 1095 vte_rxeof(struct vte_softc *sc) 1096 { 1097 struct ifnet *ifp; 1098 struct vte_rxdesc *rxd; 1099 struct mbuf *m; 1100 uint16_t status, total_len; 1101 int cons, prog; 1102 1103 bus_dmamap_sync(sc->vte_dmatag, 1104 sc->vte_cdata.vte_rx_ring_map, 0, 1105 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1106 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1107 cons = sc->vte_cdata.vte_rx_cons; 1108 ifp = &sc->vte_if; 1109 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1110 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1111 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1112 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1113 status = le16toh(rxd->rx_desc->drst); 1114 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", cons, rxd, rxd->rx_m, status, VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1115 if ((status & VTE_DRST_RX_OWN) != 0) 1116 break; 1117 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1118 m = rxd->rx_m; 1119 if ((status & VTE_DRST_RX_OK) == 0) { 1120 /* Discard errored frame. */ 1121 rxd->rx_desc->drlen = 1122 htole16(MCLBYTES - sizeof(uint32_t)); 1123 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1124 continue; 1125 } 1126 if (vte_newbuf(sc, rxd) != 0) { 1127 DPRINTF(("vte_rxeof newbuf failed\n")); 1128 ifp->if_ierrors++; 1129 rxd->rx_desc->drlen = 1130 htole16(MCLBYTES - sizeof(uint32_t)); 1131 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1132 continue; 1133 } 1134 1135 /* 1136 * It seems there is no way to strip FCS bytes. 1137 */ 1138 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1139 m->m_pkthdr.rcvif = ifp; 1140 ifp->if_ipackets++; 1141 bpf_mtap(ifp, m); 1142 (*ifp->if_input)(ifp, m); 1143 } 1144 1145 if (prog > 0) { 1146 /* Update the consumer index. */ 1147 sc->vte_cdata.vte_rx_cons = cons; 1148 /* 1149 * Sync updated RX descriptors such that controller see 1150 * modified RX buffer addresses. 1151 */ 1152 bus_dmamap_sync(sc->vte_dmatag, 1153 sc->vte_cdata.vte_rx_ring_map, 0, 1154 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1155 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1156 #ifdef notyet 1157 /* 1158 * Update residue counter. Controller does not 1159 * keep track of number of available RX descriptors 1160 * such that driver should have to update VTE_MRDCR 1161 * to make controller know how many free RX 1162 * descriptors were added to controller. This is 1163 * a similar mechanism used in VIA velocity 1164 * controllers and it indicates controller just 1165 * polls OWN bit of current RX descriptor pointer. 1166 * A couple of severe issues were seen on sample 1167 * board where the controller continuously emits TX 1168 * pause frames once RX pause threshold crossed. 1169 * Once triggered it never recovered form that 1170 * state, I couldn't find a way to make it back to 1171 * work at least. This issue effectively 1172 * disconnected the system from network. Also, the 1173 * controller used 00:00:00:00:00:00 as source 1174 * station address of TX pause frame. Probably this 1175 * is one of reason why vendor recommends not to 1176 * enable flow control on R6040 controller. 1177 */ 1178 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1179 (((VTE_RX_RING_CNT * 2) / 10) << 1180 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1181 #endif 1182 #if NRND > 0 1183 if (RND_ENABLED(&sc->rnd_source)) 1184 rnd_add_uint32(&sc->rnd_source, prog); 1185 #endif /* NRND > 0 */ 1186 } 1187 } 1188 1189 static void 1190 vte_tick(void *arg) 1191 { 1192 struct vte_softc *sc; 1193 int s = splnet(); 1194 1195 sc = (struct vte_softc *)arg; 1196 1197 mii_tick(&sc->vte_mii); 1198 vte_stats_update(sc); 1199 vte_txeof(sc); 1200 vte_ifwatchdog(&sc->vte_if); 1201 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1202 splx(s); 1203 } 1204 1205 static void 1206 vte_reset(struct vte_softc *sc) 1207 { 1208 uint16_t mcr; 1209 int i; 1210 1211 mcr = CSR_READ_2(sc, VTE_MCR1); 1212 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1213 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1214 DELAY(10); 1215 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1216 break; 1217 } 1218 if (i == 0) 1219 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1220 /* 1221 * Follow the guide of vendor recommended way to reset MAC. 1222 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1223 * not reliable so manually reset internal state machine. 1224 */ 1225 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1226 CSR_WRITE_2(sc, VTE_MACSM, 0); 1227 DELAY(5000); 1228 } 1229 1230 1231 static int 1232 vte_init(struct ifnet *ifp) 1233 { 1234 struct vte_softc *sc = ifp->if_softc; 1235 bus_addr_t paddr; 1236 uint8_t eaddr[ETHER_ADDR_LEN]; 1237 int s, error; 1238 1239 s = splnet(); 1240 /* 1241 * Cancel any pending I/O. 1242 */ 1243 vte_stop(ifp, 1); 1244 /* 1245 * Reset the chip to a known state. 1246 */ 1247 vte_reset(sc); 1248 1249 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1250 splx(s); 1251 return 0; 1252 } 1253 1254 /* Initialize RX descriptors. */ 1255 if (vte_init_rx_ring(sc) != 0) { 1256 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1257 vte_stop(ifp, 1); 1258 splx(s); 1259 return ENOMEM; 1260 } 1261 if (vte_init_tx_ring(sc) != 0) { 1262 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1263 vte_stop(ifp, 1); 1264 splx(s); 1265 return ENOMEM; 1266 } 1267 1268 /* 1269 * Reprogram the station address. Controller supports up 1270 * to 4 different station addresses so driver programs the 1271 * first station address as its own ethernet address and 1272 * configure the remaining three addresses as perfect 1273 * multicast addresses. 1274 */ 1275 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1276 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1277 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1278 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1279 1280 /* Set TX descriptor base addresses. */ 1281 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1282 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1283 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1284 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1285 1286 /* Set RX descriptor base addresses. */ 1287 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1288 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1289 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1290 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1291 /* 1292 * Initialize RX descriptor residue counter and set RX 1293 * pause threshold to 20% of available RX descriptors. 1294 * See comments on vte_rxeof() for details on flow control 1295 * issues. 1296 */ 1297 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1298 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1299 1300 /* 1301 * Always use maximum frame size that controller can 1302 * support. Otherwise received frames that has longer 1303 * frame length than vte(4) MTU would be silently dropped 1304 * in controller. This would break path-MTU discovery as 1305 * sender wouldn't get any responses from receiver. The 1306 * RX buffer size should be multiple of 4. 1307 * Note, jumbo frames are silently ignored by controller 1308 * and even MAC counters do not detect them. 1309 */ 1310 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1311 1312 /* Configure FIFO. */ 1313 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1314 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1315 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1316 1317 /* 1318 * Configure TX/RX MACs. Actual resolved duplex and flow 1319 * control configuration is done after detecting a valid 1320 * link. Note, we don't generate early interrupt here 1321 * as well since FreeBSD does not have interrupt latency 1322 * problems like Windows. 1323 */ 1324 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1325 /* 1326 * We manually keep track of PHY status changes to 1327 * configure resolved duplex and flow control since only 1328 * duplex configuration can be automatically reflected to 1329 * MCR0. 1330 */ 1331 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1332 MCR1_EXCESS_COL_RETRY_16); 1333 1334 /* Initialize RX filter. */ 1335 vte_rxfilter(sc); 1336 1337 /* Disable TX/RX interrupt moderation control. */ 1338 CSR_WRITE_2(sc, VTE_MRICR, 0); 1339 CSR_WRITE_2(sc, VTE_MTICR, 0); 1340 1341 /* Enable MAC event counter interrupts. */ 1342 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1343 /* Clear MAC statistics. */ 1344 vte_stats_clear(sc); 1345 1346 /* Acknowledge all pending interrupts and clear it. */ 1347 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1348 CSR_WRITE_2(sc, VTE_MISR, 0); 1349 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), CSR_READ_2(sc, VTE_MISR))); 1350 1351 sc->vte_flags &= ~VTE_FLAG_LINK; 1352 ifp->if_flags |= IFF_RUNNING; 1353 ifp->if_flags &= ~IFF_OACTIVE; 1354 1355 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1356 error = 0; 1357 else if (error != 0) { 1358 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1359 splx(s); 1360 return error; 1361 } 1362 1363 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1364 1365 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), CSR_READ_2(sc, VTE_MISR))); 1366 splx(s); 1367 return 0; 1368 } 1369 1370 static void 1371 vte_stop(struct ifnet *ifp, int disable) 1372 { 1373 struct vte_softc *sc = ifp->if_softc; 1374 struct vte_txdesc *txd; 1375 struct vte_rxdesc *rxd; 1376 int i; 1377 1378 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1379 if ((ifp->if_flags & IFF_RUNNING) == 0) 1380 return; 1381 /* 1382 * Mark the interface down and cancel the watchdog timer. 1383 */ 1384 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1385 sc->vte_flags &= ~VTE_FLAG_LINK; 1386 callout_stop(&sc->vte_tick_ch); 1387 sc->vte_watchdog_timer = 0; 1388 vte_stats_update(sc); 1389 /* Disable interrupts. */ 1390 CSR_WRITE_2(sc, VTE_MIER, 0); 1391 CSR_WRITE_2(sc, VTE_MECIER, 0); 1392 /* Stop RX/TX MACs. */ 1393 vte_stop_mac(sc); 1394 /* Clear interrupts. */ 1395 CSR_READ_2(sc, VTE_MISR); 1396 /* 1397 * Free TX/RX mbufs still in the queues. 1398 */ 1399 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1400 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1401 if (rxd->rx_m != NULL) { 1402 bus_dmamap_sync(sc->vte_dmatag, 1403 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1404 BUS_DMASYNC_POSTREAD); 1405 bus_dmamap_unload(sc->vte_dmatag, 1406 rxd->rx_dmamap); 1407 m_freem(rxd->rx_m); 1408 rxd->rx_m = NULL; 1409 } 1410 } 1411 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1412 txd = &sc->vte_cdata.vte_txdesc[i]; 1413 if (txd->tx_m != NULL) { 1414 bus_dmamap_sync(sc->vte_dmatag, 1415 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1416 BUS_DMASYNC_POSTWRITE); 1417 bus_dmamap_unload(sc->vte_dmatag, 1418 txd->tx_dmamap); 1419 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1420 m_freem(txd->tx_m); 1421 txd->tx_m = NULL; 1422 txd->tx_flags &= ~VTE_TXMBUF; 1423 } 1424 } 1425 /* Free TX mbuf pools used for deep copy. */ 1426 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1427 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1428 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1429 sc->vte_cdata.vte_txmbufs[i] = NULL; 1430 } 1431 } 1432 } 1433 1434 static void 1435 vte_start_mac(struct vte_softc *sc) 1436 { 1437 struct ifnet *ifp = &sc->vte_if; 1438 uint16_t mcr; 1439 int i; 1440 1441 /* Enable RX/TX MACs. */ 1442 mcr = CSR_READ_2(sc, VTE_MCR0); 1443 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1444 (MCR0_RX_ENB | MCR0_TX_ENB) && 1445 (ifp->if_flags & IFF_RUNNING) != 0) { 1446 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1447 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1448 for (i = VTE_TIMEOUT; i > 0; i--) { 1449 mcr = CSR_READ_2(sc, VTE_MCR0); 1450 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1451 (MCR0_RX_ENB | MCR0_TX_ENB)) 1452 break; 1453 DELAY(10); 1454 } 1455 if (i == 0) 1456 aprint_error_dev(sc->vte_dev, 1457 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1458 } 1459 } 1460 1461 static void 1462 vte_stop_mac(struct vte_softc *sc) 1463 { 1464 uint16_t mcr; 1465 int i; 1466 1467 /* Disable RX/TX MACs. */ 1468 mcr = CSR_READ_2(sc, VTE_MCR0); 1469 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1470 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1471 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1472 for (i = VTE_TIMEOUT; i > 0; i--) { 1473 mcr = CSR_READ_2(sc, VTE_MCR0); 1474 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1475 break; 1476 DELAY(10); 1477 } 1478 if (i == 0) 1479 aprint_error_dev(sc->vte_dev, 1480 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1481 } 1482 } 1483 1484 static int 1485 vte_init_tx_ring(struct vte_softc *sc) 1486 { 1487 struct vte_tx_desc *desc; 1488 struct vte_txdesc *txd; 1489 bus_addr_t addr; 1490 int i; 1491 1492 sc->vte_cdata.vte_tx_prod = 0; 1493 sc->vte_cdata.vte_tx_cons = 0; 1494 sc->vte_cdata.vte_tx_cnt = 0; 1495 1496 /* Pre-allocate TX mbufs for deep copy. */ 1497 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1498 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1499 MT_DATA, M_PKTHDR); 1500 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1501 return (ENOBUFS); 1502 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1503 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1504 } 1505 desc = sc->vte_cdata.vte_tx_ring; 1506 bzero(desc, VTE_TX_RING_SZ); 1507 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1508 txd = &sc->vte_cdata.vte_txdesc[i]; 1509 txd->tx_m = NULL; 1510 if (i != VTE_TX_RING_CNT - 1) 1511 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1512 sizeof(struct vte_tx_desc) * (i + 1); 1513 else 1514 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1515 sizeof(struct vte_tx_desc) * 0; 1516 desc = &sc->vte_cdata.vte_tx_ring[i]; 1517 desc->dtnp = htole32(addr); 1518 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1519 txd->tx_desc = desc; 1520 } 1521 1522 bus_dmamap_sync(sc->vte_dmatag, 1523 sc->vte_cdata.vte_tx_ring_map, 0, 1524 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1525 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1526 return (0); 1527 } 1528 1529 static int 1530 vte_init_rx_ring(struct vte_softc *sc) 1531 { 1532 struct vte_rx_desc *desc; 1533 struct vte_rxdesc *rxd; 1534 bus_addr_t addr; 1535 int i; 1536 1537 sc->vte_cdata.vte_rx_cons = 0; 1538 desc = sc->vte_cdata.vte_rx_ring; 1539 bzero(desc, VTE_RX_RING_SZ); 1540 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1541 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1542 rxd->rx_m = NULL; 1543 if (i != VTE_RX_RING_CNT - 1) 1544 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1545 + sizeof(struct vte_rx_desc) * (i + 1); 1546 else 1547 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1548 + sizeof(struct vte_rx_desc) * 0; 1549 desc = &sc->vte_cdata.vte_rx_ring[i]; 1550 desc->drnp = htole32(addr); 1551 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1552 rxd->rx_desc = desc; 1553 if (vte_newbuf(sc, rxd) != 0) 1554 return (ENOBUFS); 1555 } 1556 1557 bus_dmamap_sync(sc->vte_dmatag, 1558 sc->vte_cdata.vte_rx_ring_map, 0, 1559 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1561 1562 return (0); 1563 } 1564 1565 static void 1566 vte_rxfilter(struct vte_softc *sc) 1567 { 1568 struct ether_multistep step; 1569 struct ether_multi *enm; 1570 struct ifnet *ifp; 1571 uint8_t *eaddr; 1572 uint32_t crc; 1573 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1574 uint16_t mchash[4], mcr; 1575 int i, nperf; 1576 1577 ifp = &sc->vte_if; 1578 1579 DPRINTF(("vte_rxfilter\n")); 1580 bzero(mchash, sizeof(mchash)); 1581 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1582 rxfilt_perf[i][0] = 0xFFFF; 1583 rxfilt_perf[i][1] = 0xFFFF; 1584 rxfilt_perf[i][2] = 0xFFFF; 1585 } 1586 1587 mcr = CSR_READ_2(sc, VTE_MCR0); 1588 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1589 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST | MCR0_MULTICAST); 1590 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1591 mcr |= MCR0_BROADCAST; 1592 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1593 if ((ifp->if_flags & IFF_PROMISC) != 0) 1594 mcr |= MCR0_PROMISC; 1595 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1596 mcr |= MCR0_MULTICAST; 1597 mchash[0] = 0xFFFF; 1598 mchash[1] = 0xFFFF; 1599 mchash[2] = 0xFFFF; 1600 mchash[3] = 0xFFFF; 1601 goto chipit; 1602 } 1603 1604 ETHER_FIRST_MULTI(step, &sc->vte_ec, enm); 1605 nperf = 0; 1606 while (enm != NULL) { 1607 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1608 sc->vte_if.if_flags |= IFF_ALLMULTI; 1609 mcr |= MCR0_MULTICAST; 1610 mchash[0] = 0xFFFF; 1611 mchash[1] = 0xFFFF; 1612 mchash[2] = 0xFFFF; 1613 mchash[3] = 0xFFFF; 1614 goto chipit; 1615 } 1616 /* 1617 * Program the first 3 multicast groups into 1618 * the perfect filter. For all others, use the 1619 * hash table. 1620 */ 1621 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1622 eaddr = enm->enm_addrlo; 1623 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1624 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1625 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1626 nperf++; 1627 continue; 1628 } 1629 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1630 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1631 ETHER_NEXT_MULTI(step, enm); 1632 } 1633 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1634 mchash[3] != 0) 1635 mcr |= MCR0_MULTICAST; 1636 1637 chipit: 1638 /* Program multicast hash table. */ 1639 DPRINTF(("chipit write multicast\n")); 1640 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1641 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1642 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1643 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1644 /* Program perfect filter table. */ 1645 DPRINTF(("chipit write perfect filter\n")); 1646 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1647 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1648 rxfilt_perf[i][0]); 1649 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1650 rxfilt_perf[i][1]); 1651 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1652 rxfilt_perf[i][2]); 1653 } 1654 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1655 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1656 DPRINTF(("chipit read mcro\n")); 1657 CSR_READ_2(sc, VTE_MCR0); 1658 DPRINTF(("chipit done\n")); 1659 } 1660 1661 /* 1662 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1663 * set up in vte_pci_attach() 1664 */ 1665 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1666 { 1667 int rc; 1668 const struct sysctlnode *node; 1669 1670 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 1671 0, CTLTYPE_NODE, "hw", NULL, 1672 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 1673 goto err; 1674 } 1675 1676 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1677 0, CTLTYPE_NODE, "vte", 1678 SYSCTL_DESCR("vte interface controls"), 1679 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1680 goto err; 1681 } 1682 1683 vte_root_num = node->sysctl_num; 1684 return; 1685 1686 err: 1687 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1688 } 1689 1690 static int 1691 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1692 { 1693 int error, t; 1694 struct sysctlnode node; 1695 struct vte_softc *sc; 1696 1697 node = *rnode; 1698 sc = node.sysctl_data; 1699 t = sc->vte_int_rx_mod; 1700 node.sysctl_data = &t; 1701 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1702 if (error || newp == NULL) 1703 return error; 1704 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1705 return EINVAL; 1706 1707 sc->vte_int_rx_mod = t; 1708 vte_miibus_statchg(sc->vte_dev); 1709 return 0; 1710 } 1711 1712 static int 1713 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1714 { 1715 int error, t; 1716 struct sysctlnode node; 1717 struct vte_softc *sc; 1718 1719 node = *rnode; 1720 sc = node.sysctl_data; 1721 t = sc->vte_int_tx_mod; 1722 node.sysctl_data = &t; 1723 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1724 if (error || newp == NULL) 1725 return error; 1726 1727 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1728 return EINVAL; 1729 sc->vte_int_tx_mod = t; 1730 vte_miibus_statchg(sc->vte_dev); 1731 return 0; 1732 } 1733
Indexes created Thu Oct 02 01:09:59 GMT 2025