if_vte.c revision 1.11.4.3
1 /* $NetBSD: if_vte.c,v 1.11.4.3 2016/07/09 20:25:04 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2010, Pyun YongHyeon <yongari (at) FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 54 55 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.11.4.3 2016/07/09 20:25:04 skrll Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/mbuf.h> 63 #include <sys/protosw.h> 64 #include <sys/socket.h> 65 #include <sys/ioctl.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_dl.h> 76 #include <net/route.h> 77 #include <net/netisr.h> 78 79 #include <net/bpf.h> 80 #include <net/bpfdesc.h> 81 82 #include <sys/rndsource.h> 83 84 #include "opt_inet.h" 85 #include <net/if_ether.h> 86 #ifdef INET 87 #include <netinet/in.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #include <netinet/if_inarp.h> 92 #endif 93 94 #include <sys/bus.h> 95 #include <sys/intr.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcidevs.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 104 #include <dev/pci/if_vtereg.h> 105 #include <dev/pci/if_vtevar.h> 106 107 static int vte_match(device_t, cfdata_t, void *); 108 static void vte_attach(device_t, device_t, void *); 109 static int vte_detach(device_t, int); 110 static int vte_dma_alloc(struct vte_softc *); 111 static void vte_dma_free(struct vte_softc *); 112 static struct vte_txdesc * 113 vte_encap(struct vte_softc *, struct mbuf **); 114 static void vte_get_macaddr(struct vte_softc *); 115 static int vte_init(struct ifnet *); 116 static int vte_init_rx_ring(struct vte_softc *); 117 static int vte_init_tx_ring(struct vte_softc *); 118 static int vte_intr(void *); 119 static int vte_ifioctl(struct ifnet *, u_long, void *); 120 static void vte_mac_config(struct vte_softc *); 121 static int vte_miibus_readreg(device_t, int, int); 122 static void vte_miibus_statchg(struct ifnet *); 123 static void vte_miibus_writereg(device_t, int, int, int); 124 static int vte_mediachange(struct ifnet *); 125 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 126 static void vte_reset(struct vte_softc *); 127 static void vte_rxeof(struct vte_softc *); 128 static void vte_rxfilter(struct vte_softc *); 129 static bool vte_shutdown(device_t, int); 130 static bool vte_suspend(device_t, const pmf_qual_t *); 131 static bool vte_resume(device_t, const pmf_qual_t *); 132 static void vte_ifstart(struct ifnet *); 133 static void vte_start_mac(struct vte_softc *); 134 static void vte_stats_clear(struct vte_softc *); 135 static void vte_stats_update(struct vte_softc *); 136 static void vte_stop(struct ifnet *, int); 137 static void vte_stop_mac(struct vte_softc *); 138 static void vte_tick(void *); 139 static void vte_txeof(struct vte_softc *); 140 static void vte_ifwatchdog(struct ifnet *); 141 142 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 143 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 144 static int vte_root_num; 145 146 #define DPRINTF(a) 147 148 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 149 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 150 151 152 static int 153 vte_match(device_t parent, cfdata_t cf, void *aux) 154 { 155 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 156 157 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 158 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 159 return 1; 160 161 return 0; 162 } 163 164 static void 165 vte_attach(device_t parent, device_t self, void *aux) 166 { 167 struct vte_softc *sc = device_private(self); 168 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 169 struct ifnet * const ifp = &sc->vte_if; 170 int h_valid; 171 pcireg_t reg, csr; 172 pci_intr_handle_t intrhandle; 173 const char *intrstr; 174 int error; 175 const struct sysctlnode *node; 176 int vte_nodenum; 177 char intrbuf[PCI_INTRSTR_LEN]; 178 179 sc->vte_dev = self; 180 181 callout_init(&sc->vte_tick_ch, 0); 182 183 /* Map the device. */ 184 h_valid = 0; 185 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 186 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 187 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 188 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 189 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 190 } 191 if (h_valid == 0) { 192 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 193 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 194 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 195 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 196 &sc->vte_bushandle, NULL, NULL) == 0); 197 } 198 } 199 if (h_valid == 0) { 200 aprint_error_dev(self, "unable to map device registers\n"); 201 return; 202 } 203 sc->vte_dmatag = pa->pa_dmat; 204 /* Enable the device. */ 205 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 206 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 207 csr | PCI_COMMAND_MASTER_ENABLE); 208 209 pci_aprint_devinfo(pa, NULL); 210 211 /* Reset the ethernet controller. */ 212 vte_reset(sc); 213 214 if ((error = vte_dma_alloc(sc)) != 0) 215 return; 216 217 /* Load station address. */ 218 vte_get_macaddr(sc); 219 220 aprint_normal_dev(self, "Ethernet address %s\n", 221 ether_sprintf(sc->vte_eaddr)); 222 223 /* Map and establish interrupts */ 224 if (pci_intr_map(pa, &intrhandle)) { 225 aprint_error_dev(self, "couldn't map interrupt\n"); 226 return; 227 } 228 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 229 sc->vte_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 230 vte_intr, sc); 231 if (sc->vte_ih == NULL) { 232 aprint_error_dev(self, "couldn't establish interrupt"); 233 if (intrstr != NULL) 234 aprint_error(" at %s", intrstr); 235 aprint_error("\n"); 236 return; 237 } 238 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 239 240 sc->vte_if.if_softc = sc; 241 sc->vte_mii.mii_ifp = ifp; 242 sc->vte_mii.mii_readreg = vte_miibus_readreg; 243 sc->vte_mii.mii_writereg = vte_miibus_writereg; 244 sc->vte_mii.mii_statchg = vte_miibus_statchg; 245 sc->vte_ec.ec_mii = &sc->vte_mii; 246 ifmedia_init(&sc->vte_mii.mii_media, IFM_IMASK, vte_mediachange, 247 ether_mediastatus); 248 mii_attach(self, &sc->vte_mii, 0xffffffff, MII_PHY_ANY, 249 MII_OFFSET_ANY, 0); 250 if (LIST_FIRST(&sc->vte_mii.mii_phys) == NULL) { 251 ifmedia_add(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 252 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE); 253 } else 254 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_AUTO); 255 256 /* 257 * We can support 802.1Q VLAN-sized frames. 258 */ 259 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 260 261 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 262 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 263 ifp->if_ioctl = vte_ifioctl; 264 ifp->if_start = vte_ifstart; 265 ifp->if_watchdog = vte_ifwatchdog; 266 ifp->if_init = vte_init; 267 ifp->if_stop = vte_stop; 268 ifp->if_timer = 0; 269 IFQ_SET_READY(&ifp->if_snd); 270 if_attach(ifp); 271 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 272 273 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 274 pmf_class_network_register(self, ifp); 275 else 276 aprint_error_dev(self, "couldn't establish power handler\n"); 277 278 rnd_attach_source(&sc->rnd_source, device_xname(self), 279 RND_TYPE_NET, RND_FLAG_DEFAULT); 280 281 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 282 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 283 SYSCTL_DESCR("vte per-controller controls"), 284 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 285 CTL_EOL) != 0) { 286 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 287 return; 288 } 289 vte_nodenum = node->sysctl_num; 290 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 291 CTLFLAG_READWRITE, 292 CTLTYPE_INT, "int_rxct", 293 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 294 vte_sysctl_intrxct, 0, (void *)sc, 295 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 296 CTL_EOL) != 0) { 297 aprint_normal_dev(sc->vte_dev, 298 "couldn't create int_rxct sysctl node\n"); 299 } 300 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 301 CTLFLAG_READWRITE, 302 CTLTYPE_INT, "int_txct", 303 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 304 vte_sysctl_inttxct, 0, (void *)sc, 305 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 306 CTL_EOL) != 0) { 307 aprint_normal_dev(sc->vte_dev, 308 "couldn't create int_txct sysctl node\n"); 309 } 310 } 311 312 static int 313 vte_detach(device_t dev, int flags __unused) 314 { 315 struct vte_softc *sc = device_private(dev); 316 struct ifnet *ifp = &sc->vte_if; 317 int s; 318 319 s = splnet(); 320 /* Stop the interface. Callouts are stopped in it. */ 321 vte_stop(ifp, 1); 322 splx(s); 323 324 pmf_device_deregister(dev); 325 326 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 327 ifmedia_delete_instance(&sc->vte_mii.mii_media, IFM_INST_ANY); 328 329 ether_ifdetach(ifp); 330 if_detach(ifp); 331 332 vte_dma_free(sc); 333 334 return (0); 335 } 336 337 static int 338 vte_miibus_readreg(device_t dev, int phy, int reg) 339 { 340 struct vte_softc *sc = device_private(dev); 341 int i; 342 343 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 344 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 345 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 346 DELAY(5); 347 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 348 break; 349 } 350 351 if (i == 0) { 352 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 353 return (0); 354 } 355 356 return (CSR_READ_2(sc, VTE_MMRD)); 357 } 358 359 static void 360 vte_miibus_writereg(device_t dev, int phy, int reg, int val) 361 { 362 struct vte_softc *sc = device_private(dev); 363 int i; 364 365 CSR_WRITE_2(sc, VTE_MMWD, val); 366 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 367 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 368 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 369 DELAY(5); 370 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 371 break; 372 } 373 374 if (i == 0) 375 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 376 377 } 378 379 static void 380 vte_miibus_statchg(struct ifnet *ifp) 381 { 382 struct vte_softc *sc = ifp->if_softc; 383 uint16_t val; 384 385 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 386 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 387 388 sc->vte_flags &= ~VTE_FLAG_LINK; 389 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 390 (IFM_ACTIVE | IFM_AVALID)) { 391 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 392 case IFM_10_T: 393 case IFM_100_TX: 394 sc->vte_flags |= VTE_FLAG_LINK; 395 break; 396 default: 397 break; 398 } 399 } 400 401 /* Stop RX/TX MACs. */ 402 vte_stop_mac(sc); 403 /* Program MACs with resolved duplex and flow control. */ 404 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 405 /* 406 * Timer waiting time : (63 + TIMER * 64) MII clock. 407 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 408 */ 409 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 410 val = 18 << VTE_IM_TIMER_SHIFT; 411 else 412 val = 1 << VTE_IM_TIMER_SHIFT; 413 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 414 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 415 CSR_WRITE_2(sc, VTE_MRICR, val); 416 417 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 418 val = 18 << VTE_IM_TIMER_SHIFT; 419 else 420 val = 1 << VTE_IM_TIMER_SHIFT; 421 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 422 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 423 CSR_WRITE_2(sc, VTE_MTICR, val); 424 425 vte_mac_config(sc); 426 vte_start_mac(sc); 427 DPRINTF(("vte_miibus_statchg: link\n")); 428 } 429 } 430 431 static void 432 vte_get_macaddr(struct vte_softc *sc) 433 { 434 uint16_t mid; 435 436 /* 437 * It seems there is no way to reload station address and 438 * it is supposed to be set by BIOS. 439 */ 440 mid = CSR_READ_2(sc, VTE_MID0L); 441 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 442 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 443 mid = CSR_READ_2(sc, VTE_MID0M); 444 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 445 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 446 mid = CSR_READ_2(sc, VTE_MID0H); 447 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 448 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 449 } 450 451 452 static int 453 vte_dma_alloc(struct vte_softc *sc) 454 { 455 struct vte_txdesc *txd; 456 struct vte_rxdesc *rxd; 457 int error, i, rseg; 458 459 /* create DMA map for TX ring */ 460 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 461 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 462 &sc->vte_cdata.vte_tx_ring_map); 463 if (error) { 464 aprint_error_dev(sc->vte_dev, 465 "could not create dma map for TX ring (%d)\n", 466 error); 467 goto fail; 468 } 469 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 470 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 471 VTE_TX_RING_ALIGN, 0, 472 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 473 BUS_DMA_NOWAIT); 474 if (error != 0) { 475 aprint_error_dev(sc->vte_dev, 476 "could not allocate DMA'able memory for TX ring (%d).\n", 477 error); 478 goto fail; 479 } 480 KASSERT(rseg == 1); 481 error = bus_dmamem_map(sc->vte_dmatag, 482 sc->vte_cdata.vte_tx_ring_seg, 1, 483 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 484 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 485 if (error != 0) { 486 aprint_error_dev(sc->vte_dev, 487 "could not map DMA'able memory for TX ring (%d).\n", 488 error); 489 goto fail; 490 } 491 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 492 error = bus_dmamap_load(sc->vte_dmatag, 493 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 494 VTE_TX_RING_SZ, NULL, 495 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 496 if (error != 0) { 497 aprint_error_dev(sc->vte_dev, 498 "could not load DMA'able memory for TX ring.\n"); 499 goto fail; 500 } 501 502 /* create DMA map for RX ring */ 503 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 504 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 505 &sc->vte_cdata.vte_rx_ring_map); 506 if (error) { 507 aprint_error_dev(sc->vte_dev, 508 "could not create dma map for RX ring (%d)\n", 509 error); 510 goto fail; 511 } 512 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 513 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 514 VTE_RX_RING_ALIGN, 0, 515 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 516 BUS_DMA_NOWAIT); 517 if (error != 0) { 518 aprint_error_dev(sc->vte_dev, 519 "could not allocate DMA'able memory for RX ring (%d).\n", 520 error); 521 goto fail; 522 } 523 KASSERT(rseg == 1); 524 error = bus_dmamem_map(sc->vte_dmatag, 525 sc->vte_cdata.vte_rx_ring_seg, 1, 526 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 527 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 528 if (error != 0) { 529 aprint_error_dev(sc->vte_dev, 530 "could not map DMA'able memory for RX ring (%d).\n", 531 error); 532 goto fail; 533 } 534 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 535 error = bus_dmamap_load(sc->vte_dmatag, 536 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 537 VTE_RX_RING_SZ, NULL, 538 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 539 if (error != 0) { 540 aprint_error_dev(sc->vte_dev, 541 "could not load DMA'able memory for RX ring (%d).\n", 542 error); 543 goto fail; 544 } 545 546 /* Create DMA maps for TX buffers. */ 547 for (i = 0; i < VTE_TX_RING_CNT; i++) { 548 txd = &sc->vte_cdata.vte_txdesc[i]; 549 txd->tx_m = NULL; 550 txd->tx_dmamap = NULL; 551 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 552 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 553 &txd->tx_dmamap); 554 if (error != 0) { 555 aprint_error_dev(sc->vte_dev, 556 "could not create TX DMA map %d (%d).\n", i, error); 557 goto fail; 558 } 559 } 560 /* Create DMA maps for RX buffers. */ 561 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 562 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 563 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 564 aprint_error_dev(sc->vte_dev, 565 "could not create spare RX dmamap (%d).\n", error); 566 goto fail; 567 } 568 for (i = 0; i < VTE_RX_RING_CNT; i++) { 569 rxd = &sc->vte_cdata.vte_rxdesc[i]; 570 rxd->rx_m = NULL; 571 rxd->rx_dmamap = NULL; 572 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 573 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 574 &rxd->rx_dmamap); 575 if (error != 0) { 576 aprint_error_dev(sc->vte_dev, 577 "could not create RX dmamap %d (%d).\n", i, error); 578 goto fail; 579 } 580 } 581 return 0; 582 583 fail: 584 vte_dma_free(sc); 585 return (error); 586 } 587 588 static void 589 vte_dma_free(struct vte_softc *sc) 590 { 591 struct vte_txdesc *txd; 592 struct vte_rxdesc *rxd; 593 int i; 594 595 /* TX buffers. */ 596 for (i = 0; i < VTE_TX_RING_CNT; i++) { 597 txd = &sc->vte_cdata.vte_txdesc[i]; 598 if (txd->tx_dmamap != NULL) { 599 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 600 txd->tx_dmamap = NULL; 601 } 602 } 603 /* RX buffers */ 604 for (i = 0; i < VTE_RX_RING_CNT; i++) { 605 rxd = &sc->vte_cdata.vte_rxdesc[i]; 606 if (rxd->rx_dmamap != NULL) { 607 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 608 rxd->rx_dmamap = NULL; 609 } 610 } 611 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 612 bus_dmamap_destroy(sc->vte_dmatag, 613 sc->vte_cdata.vte_rx_sparemap); 614 sc->vte_cdata.vte_rx_sparemap = NULL; 615 } 616 /* TX descriptor ring. */ 617 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 618 bus_dmamap_unload(sc->vte_dmatag, 619 sc->vte_cdata.vte_tx_ring_map); 620 bus_dmamap_destroy(sc->vte_dmatag, 621 sc->vte_cdata.vte_tx_ring_map); 622 } 623 if (sc->vte_cdata.vte_tx_ring != NULL) { 624 bus_dmamem_unmap(sc->vte_dmatag, 625 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 626 bus_dmamem_free(sc->vte_dmatag, 627 sc->vte_cdata.vte_tx_ring_seg, 1); 628 } 629 sc->vte_cdata.vte_tx_ring = NULL; 630 sc->vte_cdata.vte_tx_ring_map = NULL; 631 /* RX ring. */ 632 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 633 bus_dmamap_unload(sc->vte_dmatag, 634 sc->vte_cdata.vte_rx_ring_map); 635 bus_dmamap_destroy(sc->vte_dmatag, 636 sc->vte_cdata.vte_rx_ring_map); 637 } 638 if (sc->vte_cdata.vte_rx_ring != NULL) { 639 bus_dmamem_unmap(sc->vte_dmatag, 640 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 641 bus_dmamem_free(sc->vte_dmatag, 642 sc->vte_cdata.vte_rx_ring_seg, 1); 643 } 644 sc->vte_cdata.vte_rx_ring = NULL; 645 sc->vte_cdata.vte_rx_ring_map = NULL; 646 } 647 648 static bool 649 vte_shutdown(device_t dev, int howto) 650 { 651 652 return (vte_suspend(dev, NULL)); 653 } 654 655 static bool 656 vte_suspend(device_t dev, const pmf_qual_t *qual) 657 { 658 struct vte_softc *sc = device_private(dev); 659 struct ifnet *ifp = &sc->vte_if; 660 661 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 662 if ((ifp->if_flags & IFF_RUNNING) != 0) 663 vte_stop(ifp, 1); 664 return (0); 665 } 666 667 static bool 668 vte_resume(device_t dev, const pmf_qual_t *qual) 669 { 670 struct vte_softc *sc = device_private(dev); 671 struct ifnet *ifp; 672 673 ifp = &sc->vte_if; 674 if ((ifp->if_flags & IFF_UP) != 0) { 675 ifp->if_flags &= ~IFF_RUNNING; 676 vte_init(ifp); 677 } 678 679 return (0); 680 } 681 682 static struct vte_txdesc * 683 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 684 { 685 struct vte_txdesc *txd; 686 struct mbuf *m, *n; 687 int copy, error, padlen; 688 689 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 690 m = *m_head; 691 /* 692 * Controller doesn't auto-pad, so we have to make sure pad 693 * short frames out to the minimum frame length. 694 */ 695 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 696 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 697 else 698 padlen = 0; 699 700 /* 701 * Controller does not support multi-fragmented TX buffers. 702 * Controller spends most of its TX processing time in 703 * de-fragmenting TX buffers. Either faster CPU or more 704 * advanced controller DMA engine is required to speed up 705 * TX path processing. 706 * To mitigate the de-fragmenting issue, perform deep copy 707 * from fragmented mbuf chains to a pre-allocated mbuf 708 * cluster with extra cost of kernel memory. For frames 709 * that is composed of single TX buffer, the deep copy is 710 * bypassed. 711 */ 712 copy = 0; 713 if (m->m_next != NULL) 714 copy++; 715 if (padlen > 0 && (M_READONLY(m) || 716 padlen > M_TRAILINGSPACE(m))) 717 copy++; 718 if (copy != 0) { 719 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 720 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 721 n->m_pkthdr.len = m->m_pkthdr.len; 722 n->m_len = m->m_pkthdr.len; 723 m = n; 724 txd->tx_flags |= VTE_TXMBUF; 725 } 726 727 if (padlen > 0) { 728 /* Zero out the bytes in the pad area. */ 729 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 730 m->m_pkthdr.len += padlen; 731 m->m_len = m->m_pkthdr.len; 732 } 733 734 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 0); 735 if (error != 0) { 736 txd->tx_flags &= ~VTE_TXMBUF; 737 return (NULL); 738 } 739 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 740 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 741 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 742 743 txd->tx_desc->dtlen = 744 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 745 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 746 sc->vte_cdata.vte_tx_cnt++; 747 /* Update producer index. */ 748 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 749 750 /* Finally hand over ownership to controller. */ 751 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 752 txd->tx_m = m; 753 754 return (txd); 755 } 756 757 static void 758 vte_ifstart(struct ifnet *ifp) 759 { 760 struct vte_softc *sc = ifp->if_softc; 761 struct vte_txdesc *txd; 762 struct mbuf *m_head, *m; 763 int enq; 764 765 ifp = &sc->vte_if; 766 767 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 768 769 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 770 IFF_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 771 return; 772 773 for (enq = 0; !IFQ_IS_EMPTY(&ifp->if_snd); ) { 774 /* Reserve one free TX descriptor. */ 775 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 776 ifp->if_flags |= IFF_OACTIVE; 777 break; 778 } 779 IFQ_POLL(&ifp->if_snd, m_head); 780 if (m_head == NULL) 781 break; 782 /* 783 * Pack the data into the transmit ring. If we 784 * don't have room, set the OACTIVE flag and wait 785 * for the NIC to drain the ring. 786 */ 787 DPRINTF(("vte_encap:")); 788 if ((txd = vte_encap(sc, &m_head)) == NULL) { 789 DPRINTF((" failed\n")); 790 break; 791 } 792 DPRINTF((" ok\n")); 793 IFQ_DEQUEUE(&ifp->if_snd, m); 794 KASSERT(m == m_head); 795 796 enq++; 797 /* 798 * If there's a BPF listener, bounce a copy of this frame 799 * to him. 800 */ 801 bpf_mtap(ifp, m_head); 802 /* Free consumed TX frame. */ 803 if ((txd->tx_flags & VTE_TXMBUF) != 0) 804 m_freem(m_head); 805 } 806 807 if (enq > 0) { 808 bus_dmamap_sync(sc->vte_dmatag, 809 sc->vte_cdata.vte_tx_ring_map, 0, 810 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 811 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 812 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 813 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 814 } 815 } 816 817 static void 818 vte_ifwatchdog(struct ifnet *ifp) 819 { 820 struct vte_softc *sc = ifp->if_softc; 821 822 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 823 return; 824 825 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 826 ifp->if_oerrors++; 827 vte_init(ifp); 828 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 829 vte_ifstart(ifp); 830 } 831 832 static int 833 vte_mediachange(struct ifnet *ifp) 834 { 835 int error; 836 struct vte_softc *sc = ifp->if_softc; 837 838 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 839 error = 0; 840 else if (error != 0) { 841 aprint_error_dev(sc->vte_dev, "could not set media\n"); 842 return error; 843 } 844 return 0; 845 846 } 847 848 static int 849 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 850 { 851 struct vte_softc *sc = ifp->if_softc; 852 int error, s; 853 854 s = splnet(); 855 error = ether_ioctl(ifp, cmd, data); 856 if (error == ENETRESET) { 857 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 858 if (ifp->if_flags & IFF_RUNNING) 859 vte_rxfilter(sc); 860 error = 0; 861 } 862 splx(s); 863 return error; 864 } 865 866 static void 867 vte_mac_config(struct vte_softc *sc) 868 { 869 uint16_t mcr; 870 871 mcr = CSR_READ_2(sc, VTE_MCR0); 872 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 873 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 874 mcr |= MCR0_FULL_DUPLEX; 875 #ifdef notyet 876 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 877 mcr |= MCR0_FC_ENB; 878 /* 879 * The data sheet is not clear whether the controller 880 * honors received pause frames or not. The is no 881 * separate control bit for RX pause frame so just 882 * enable MCR0_FC_ENB bit. 883 */ 884 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 885 mcr |= MCR0_FC_ENB; 886 #endif 887 } 888 CSR_WRITE_2(sc, VTE_MCR0, mcr); 889 } 890 891 static void 892 vte_stats_clear(struct vte_softc *sc) 893 { 894 895 /* Reading counter registers clears its contents. */ 896 CSR_READ_2(sc, VTE_CNT_RX_DONE); 897 CSR_READ_2(sc, VTE_CNT_MECNT0); 898 CSR_READ_2(sc, VTE_CNT_MECNT1); 899 CSR_READ_2(sc, VTE_CNT_MECNT2); 900 CSR_READ_2(sc, VTE_CNT_MECNT3); 901 CSR_READ_2(sc, VTE_CNT_TX_DONE); 902 CSR_READ_2(sc, VTE_CNT_MECNT4); 903 CSR_READ_2(sc, VTE_CNT_PAUSE); 904 } 905 906 static void 907 vte_stats_update(struct vte_softc *sc) 908 { 909 struct vte_hw_stats *stat; 910 struct ifnet *ifp = &sc->vte_if; 911 uint16_t value; 912 913 stat = &sc->vte_stats; 914 915 CSR_READ_2(sc, VTE_MECISR); 916 /* RX stats. */ 917 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 918 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 919 stat->rx_bcast_frames += (value >> 8); 920 stat->rx_mcast_frames += (value & 0xFF); 921 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 922 stat->rx_runts += (value >> 8); 923 stat->rx_crcerrs += (value & 0xFF); 924 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 925 stat->rx_long_frames += (value & 0xFF); 926 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 927 stat->rx_fifo_full += (value >> 8); 928 stat->rx_desc_unavail += (value & 0xFF); 929 930 /* TX stats. */ 931 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 932 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 933 stat->tx_underruns += (value >> 8); 934 stat->tx_late_colls += (value & 0xFF); 935 936 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 937 stat->tx_pause_frames += (value >> 8); 938 stat->rx_pause_frames += (value & 0xFF); 939 940 /* Update ifp counters. */ 941 ifp->if_opackets = stat->tx_frames; 942 ifp->if_oerrors = stat->tx_late_colls + stat->tx_underruns; 943 ifp->if_ipackets = stat->rx_frames; 944 ifp->if_ierrors = stat->rx_crcerrs + stat->rx_runts + 945 stat->rx_long_frames + stat->rx_fifo_full; 946 } 947 948 static int 949 vte_intr(void *arg) 950 { 951 struct vte_softc *sc = (struct vte_softc *)arg; 952 struct ifnet *ifp = &sc->vte_if; 953 uint16_t status; 954 int n; 955 956 /* Reading VTE_MISR acknowledges interrupts. */ 957 status = CSR_READ_2(sc, VTE_MISR); 958 DPRINTF(("vte_intr status 0x%x\n", status)); 959 if ((status & VTE_INTRS) == 0) { 960 /* Not ours. */ 961 return 0; 962 } 963 964 /* Disable interrupts. */ 965 CSR_WRITE_2(sc, VTE_MIER, 0); 966 for (n = 8; (status & VTE_INTRS) != 0;) { 967 if ((ifp->if_flags & IFF_RUNNING) == 0) 968 break; 969 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 970 MISR_RX_FIFO_FULL)) != 0) 971 vte_rxeof(sc); 972 if ((status & MISR_TX_DONE) != 0) 973 vte_txeof(sc); 974 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 975 vte_stats_update(sc); 976 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 977 vte_ifstart(ifp); 978 if (--n > 0) 979 status = CSR_READ_2(sc, VTE_MISR); 980 else 981 break; 982 } 983 984 if ((ifp->if_flags & IFF_RUNNING) != 0) { 985 /* Re-enable interrupts. */ 986 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 987 } 988 return 1; 989 } 990 991 static void 992 vte_txeof(struct vte_softc *sc) 993 { 994 struct ifnet *ifp; 995 struct vte_txdesc *txd; 996 uint16_t status; 997 int cons, prog; 998 999 ifp = &sc->vte_if; 1000 1001 if (sc->vte_cdata.vte_tx_cnt == 0) 1002 return; 1003 bus_dmamap_sync(sc->vte_dmatag, 1004 sc->vte_cdata.vte_tx_ring_map, 0, 1005 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1006 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1007 cons = sc->vte_cdata.vte_tx_cons; 1008 /* 1009 * Go through our TX list and free mbufs for those 1010 * frames which have been transmitted. 1011 */ 1012 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1013 txd = &sc->vte_cdata.vte_txdesc[cons]; 1014 status = le16toh(txd->tx_desc->dtst); 1015 if ((status & VTE_DTST_TX_OWN) != 0) 1016 break; 1017 if ((status & VTE_DTST_TX_OK) != 0) 1018 ifp->if_collisions += (status & 0xf); 1019 sc->vte_cdata.vte_tx_cnt--; 1020 /* Reclaim transmitted mbufs. */ 1021 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1022 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1023 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1024 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1025 m_freem(txd->tx_m); 1026 txd->tx_flags &= ~VTE_TXMBUF; 1027 txd->tx_m = NULL; 1028 prog++; 1029 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1030 } 1031 1032 if (prog > 0) { 1033 ifp->if_flags &= ~IFF_OACTIVE; 1034 sc->vte_cdata.vte_tx_cons = cons; 1035 /* 1036 * Unarm watchdog timer only when there is no pending 1037 * frames in TX queue. 1038 */ 1039 if (sc->vte_cdata.vte_tx_cnt == 0) 1040 sc->vte_watchdog_timer = 0; 1041 } 1042 } 1043 1044 static int 1045 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1046 { 1047 struct mbuf *m; 1048 bus_dmamap_t map; 1049 1050 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1051 if (m == NULL) 1052 return (ENOBUFS); 1053 m->m_len = m->m_pkthdr.len = MCLBYTES; 1054 m_adj(m, sizeof(uint32_t)); 1055 1056 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1057 sc->vte_cdata.vte_rx_sparemap, m, 0) != 0) { 1058 m_freem(m); 1059 return (ENOBUFS); 1060 } 1061 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1062 1063 if (rxd->rx_m != NULL) { 1064 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1065 0, rxd->rx_dmamap->dm_mapsize, 1066 BUS_DMASYNC_POSTREAD); 1067 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1068 } 1069 map = rxd->rx_dmamap; 1070 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1071 sc->vte_cdata.vte_rx_sparemap = map; 1072 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1073 0, rxd->rx_dmamap->dm_mapsize, 1074 BUS_DMASYNC_PREREAD); 1075 rxd->rx_m = m; 1076 rxd->rx_desc->drbp = 1077 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1078 rxd->rx_desc->drlen = htole16( 1079 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1080 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, rxd->rx_dmamap->dm_segs[0].ds_len)); 1081 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1082 1083 return (0); 1084 } 1085 1086 static void 1087 vte_rxeof(struct vte_softc *sc) 1088 { 1089 struct ifnet *ifp; 1090 struct vte_rxdesc *rxd; 1091 struct mbuf *m; 1092 uint16_t status, total_len; 1093 int cons, prog; 1094 1095 bus_dmamap_sync(sc->vte_dmatag, 1096 sc->vte_cdata.vte_rx_ring_map, 0, 1097 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1098 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1099 cons = sc->vte_cdata.vte_rx_cons; 1100 ifp = &sc->vte_if; 1101 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1102 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1103 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1104 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1105 status = le16toh(rxd->rx_desc->drst); 1106 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", cons, rxd, rxd->rx_m, status, VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1107 if ((status & VTE_DRST_RX_OWN) != 0) 1108 break; 1109 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1110 m = rxd->rx_m; 1111 if ((status & VTE_DRST_RX_OK) == 0) { 1112 /* Discard errored frame. */ 1113 rxd->rx_desc->drlen = 1114 htole16(MCLBYTES - sizeof(uint32_t)); 1115 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1116 continue; 1117 } 1118 if (vte_newbuf(sc, rxd) != 0) { 1119 DPRINTF(("vte_rxeof newbuf failed\n")); 1120 ifp->if_ierrors++; 1121 rxd->rx_desc->drlen = 1122 htole16(MCLBYTES - sizeof(uint32_t)); 1123 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1124 continue; 1125 } 1126 1127 /* 1128 * It seems there is no way to strip FCS bytes. 1129 */ 1130 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1131 m_set_rcvif(m, ifp); 1132 ifp->if_ipackets++; 1133 bpf_mtap(ifp, m); 1134 if_percpuq_enqueue(ifp->if_percpuq, m); 1135 } 1136 1137 if (prog > 0) { 1138 /* Update the consumer index. */ 1139 sc->vte_cdata.vte_rx_cons = cons; 1140 /* 1141 * Sync updated RX descriptors such that controller see 1142 * modified RX buffer addresses. 1143 */ 1144 bus_dmamap_sync(sc->vte_dmatag, 1145 sc->vte_cdata.vte_rx_ring_map, 0, 1146 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1147 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1148 #ifdef notyet 1149 /* 1150 * Update residue counter. Controller does not 1151 * keep track of number of available RX descriptors 1152 * such that driver should have to update VTE_MRDCR 1153 * to make controller know how many free RX 1154 * descriptors were added to controller. This is 1155 * a similar mechanism used in VIA velocity 1156 * controllers and it indicates controller just 1157 * polls OWN bit of current RX descriptor pointer. 1158 * A couple of severe issues were seen on sample 1159 * board where the controller continuously emits TX 1160 * pause frames once RX pause threshold crossed. 1161 * Once triggered it never recovered form that 1162 * state, I couldn't find a way to make it back to 1163 * work at least. This issue effectively 1164 * disconnected the system from network. Also, the 1165 * controller used 00:00:00:00:00:00 as source 1166 * station address of TX pause frame. Probably this 1167 * is one of reason why vendor recommends not to 1168 * enable flow control on R6040 controller. 1169 */ 1170 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1171 (((VTE_RX_RING_CNT * 2) / 10) << 1172 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1173 #endif 1174 rnd_add_uint32(&sc->rnd_source, prog); 1175 } 1176 } 1177 1178 static void 1179 vte_tick(void *arg) 1180 { 1181 struct vte_softc *sc; 1182 int s = splnet(); 1183 1184 sc = (struct vte_softc *)arg; 1185 1186 mii_tick(&sc->vte_mii); 1187 vte_stats_update(sc); 1188 vte_txeof(sc); 1189 vte_ifwatchdog(&sc->vte_if); 1190 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1191 splx(s); 1192 } 1193 1194 static void 1195 vte_reset(struct vte_softc *sc) 1196 { 1197 uint16_t mcr; 1198 int i; 1199 1200 mcr = CSR_READ_2(sc, VTE_MCR1); 1201 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1202 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1203 DELAY(10); 1204 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1205 break; 1206 } 1207 if (i == 0) 1208 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1209 /* 1210 * Follow the guide of vendor recommended way to reset MAC. 1211 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1212 * not reliable so manually reset internal state machine. 1213 */ 1214 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1215 CSR_WRITE_2(sc, VTE_MACSM, 0); 1216 DELAY(5000); 1217 } 1218 1219 1220 static int 1221 vte_init(struct ifnet *ifp) 1222 { 1223 struct vte_softc *sc = ifp->if_softc; 1224 bus_addr_t paddr; 1225 uint8_t eaddr[ETHER_ADDR_LEN]; 1226 int s, error; 1227 1228 s = splnet(); 1229 /* 1230 * Cancel any pending I/O. 1231 */ 1232 vte_stop(ifp, 1); 1233 /* 1234 * Reset the chip to a known state. 1235 */ 1236 vte_reset(sc); 1237 1238 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1239 splx(s); 1240 return 0; 1241 } 1242 1243 /* Initialize RX descriptors. */ 1244 if (vte_init_rx_ring(sc) != 0) { 1245 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1246 vte_stop(ifp, 1); 1247 splx(s); 1248 return ENOMEM; 1249 } 1250 if (vte_init_tx_ring(sc) != 0) { 1251 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1252 vte_stop(ifp, 1); 1253 splx(s); 1254 return ENOMEM; 1255 } 1256 1257 /* 1258 * Reprogram the station address. Controller supports up 1259 * to 4 different station addresses so driver programs the 1260 * first station address as its own ethernet address and 1261 * configure the remaining three addresses as perfect 1262 * multicast addresses. 1263 */ 1264 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1265 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1266 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1267 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1268 1269 /* Set TX descriptor base addresses. */ 1270 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1271 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1272 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1273 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1274 1275 /* Set RX descriptor base addresses. */ 1276 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1277 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1278 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1279 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1280 /* 1281 * Initialize RX descriptor residue counter and set RX 1282 * pause threshold to 20% of available RX descriptors. 1283 * See comments on vte_rxeof() for details on flow control 1284 * issues. 1285 */ 1286 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1287 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1288 1289 /* 1290 * Always use maximum frame size that controller can 1291 * support. Otherwise received frames that has longer 1292 * frame length than vte(4) MTU would be silently dropped 1293 * in controller. This would break path-MTU discovery as 1294 * sender wouldn't get any responses from receiver. The 1295 * RX buffer size should be multiple of 4. 1296 * Note, jumbo frames are silently ignored by controller 1297 * and even MAC counters do not detect them. 1298 */ 1299 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1300 1301 /* Configure FIFO. */ 1302 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1303 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1304 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1305 1306 /* 1307 * Configure TX/RX MACs. Actual resolved duplex and flow 1308 * control configuration is done after detecting a valid 1309 * link. Note, we don't generate early interrupt here 1310 * as well since FreeBSD does not have interrupt latency 1311 * problems like Windows. 1312 */ 1313 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1314 /* 1315 * We manually keep track of PHY status changes to 1316 * configure resolved duplex and flow control since only 1317 * duplex configuration can be automatically reflected to 1318 * MCR0. 1319 */ 1320 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1321 MCR1_EXCESS_COL_RETRY_16); 1322 1323 /* Initialize RX filter. */ 1324 vte_rxfilter(sc); 1325 1326 /* Disable TX/RX interrupt moderation control. */ 1327 CSR_WRITE_2(sc, VTE_MRICR, 0); 1328 CSR_WRITE_2(sc, VTE_MTICR, 0); 1329 1330 /* Enable MAC event counter interrupts. */ 1331 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1332 /* Clear MAC statistics. */ 1333 vte_stats_clear(sc); 1334 1335 /* Acknowledge all pending interrupts and clear it. */ 1336 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1337 CSR_WRITE_2(sc, VTE_MISR, 0); 1338 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), CSR_READ_2(sc, VTE_MISR))); 1339 1340 sc->vte_flags &= ~VTE_FLAG_LINK; 1341 ifp->if_flags |= IFF_RUNNING; 1342 ifp->if_flags &= ~IFF_OACTIVE; 1343 1344 /* calling mii_mediachg will call back vte_start_mac() */ 1345 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1346 error = 0; 1347 else if (error != 0) { 1348 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1349 splx(s); 1350 return error; 1351 } 1352 1353 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1354 1355 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), CSR_READ_2(sc, VTE_MISR))); 1356 splx(s); 1357 return 0; 1358 } 1359 1360 static void 1361 vte_stop(struct ifnet *ifp, int disable) 1362 { 1363 struct vte_softc *sc = ifp->if_softc; 1364 struct vte_txdesc *txd; 1365 struct vte_rxdesc *rxd; 1366 int i; 1367 1368 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1369 if ((ifp->if_flags & IFF_RUNNING) == 0) 1370 return; 1371 /* 1372 * Mark the interface down and cancel the watchdog timer. 1373 */ 1374 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1375 sc->vte_flags &= ~VTE_FLAG_LINK; 1376 callout_stop(&sc->vte_tick_ch); 1377 sc->vte_watchdog_timer = 0; 1378 vte_stats_update(sc); 1379 /* Disable interrupts. */ 1380 CSR_WRITE_2(sc, VTE_MIER, 0); 1381 CSR_WRITE_2(sc, VTE_MECIER, 0); 1382 /* Stop RX/TX MACs. */ 1383 vte_stop_mac(sc); 1384 /* Clear interrupts. */ 1385 CSR_READ_2(sc, VTE_MISR); 1386 /* 1387 * Free TX/RX mbufs still in the queues. 1388 */ 1389 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1390 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1391 if (rxd->rx_m != NULL) { 1392 bus_dmamap_sync(sc->vte_dmatag, 1393 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1394 BUS_DMASYNC_POSTREAD); 1395 bus_dmamap_unload(sc->vte_dmatag, 1396 rxd->rx_dmamap); 1397 m_freem(rxd->rx_m); 1398 rxd->rx_m = NULL; 1399 } 1400 } 1401 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1402 txd = &sc->vte_cdata.vte_txdesc[i]; 1403 if (txd->tx_m != NULL) { 1404 bus_dmamap_sync(sc->vte_dmatag, 1405 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1406 BUS_DMASYNC_POSTWRITE); 1407 bus_dmamap_unload(sc->vte_dmatag, 1408 txd->tx_dmamap); 1409 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1410 m_freem(txd->tx_m); 1411 txd->tx_m = NULL; 1412 txd->tx_flags &= ~VTE_TXMBUF; 1413 } 1414 } 1415 /* Free TX mbuf pools used for deep copy. */ 1416 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1417 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1418 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1419 sc->vte_cdata.vte_txmbufs[i] = NULL; 1420 } 1421 } 1422 } 1423 1424 static void 1425 vte_start_mac(struct vte_softc *sc) 1426 { 1427 struct ifnet *ifp = &sc->vte_if; 1428 uint16_t mcr; 1429 int i; 1430 1431 /* Enable RX/TX MACs. */ 1432 mcr = CSR_READ_2(sc, VTE_MCR0); 1433 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1434 (MCR0_RX_ENB | MCR0_TX_ENB) && 1435 (ifp->if_flags & IFF_RUNNING) != 0) { 1436 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1437 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1438 for (i = VTE_TIMEOUT; i > 0; i--) { 1439 mcr = CSR_READ_2(sc, VTE_MCR0); 1440 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1441 (MCR0_RX_ENB | MCR0_TX_ENB)) 1442 break; 1443 DELAY(10); 1444 } 1445 if (i == 0) 1446 aprint_error_dev(sc->vte_dev, 1447 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1448 } 1449 vte_rxfilter(sc); 1450 } 1451 1452 static void 1453 vte_stop_mac(struct vte_softc *sc) 1454 { 1455 uint16_t mcr; 1456 int i; 1457 1458 /* Disable RX/TX MACs. */ 1459 mcr = CSR_READ_2(sc, VTE_MCR0); 1460 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1461 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1462 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1463 for (i = VTE_TIMEOUT; i > 0; i--) { 1464 mcr = CSR_READ_2(sc, VTE_MCR0); 1465 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1466 break; 1467 DELAY(10); 1468 } 1469 if (i == 0) 1470 aprint_error_dev(sc->vte_dev, 1471 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1472 } 1473 } 1474 1475 static int 1476 vte_init_tx_ring(struct vte_softc *sc) 1477 { 1478 struct vte_tx_desc *desc; 1479 struct vte_txdesc *txd; 1480 bus_addr_t addr; 1481 int i; 1482 1483 sc->vte_cdata.vte_tx_prod = 0; 1484 sc->vte_cdata.vte_tx_cons = 0; 1485 sc->vte_cdata.vte_tx_cnt = 0; 1486 1487 /* Pre-allocate TX mbufs for deep copy. */ 1488 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1489 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1490 MT_DATA, M_PKTHDR); 1491 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1492 return (ENOBUFS); 1493 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1494 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1495 } 1496 desc = sc->vte_cdata.vte_tx_ring; 1497 bzero(desc, VTE_TX_RING_SZ); 1498 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1499 txd = &sc->vte_cdata.vte_txdesc[i]; 1500 txd->tx_m = NULL; 1501 if (i != VTE_TX_RING_CNT - 1) 1502 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1503 sizeof(struct vte_tx_desc) * (i + 1); 1504 else 1505 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1506 sizeof(struct vte_tx_desc) * 0; 1507 desc = &sc->vte_cdata.vte_tx_ring[i]; 1508 desc->dtnp = htole32(addr); 1509 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1510 txd->tx_desc = desc; 1511 } 1512 1513 bus_dmamap_sync(sc->vte_dmatag, 1514 sc->vte_cdata.vte_tx_ring_map, 0, 1515 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1516 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1517 return (0); 1518 } 1519 1520 static int 1521 vte_init_rx_ring(struct vte_softc *sc) 1522 { 1523 struct vte_rx_desc *desc; 1524 struct vte_rxdesc *rxd; 1525 bus_addr_t addr; 1526 int i; 1527 1528 sc->vte_cdata.vte_rx_cons = 0; 1529 desc = sc->vte_cdata.vte_rx_ring; 1530 bzero(desc, VTE_RX_RING_SZ); 1531 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1532 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1533 rxd->rx_m = NULL; 1534 if (i != VTE_RX_RING_CNT - 1) 1535 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1536 + sizeof(struct vte_rx_desc) * (i + 1); 1537 else 1538 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1539 + sizeof(struct vte_rx_desc) * 0; 1540 desc = &sc->vte_cdata.vte_rx_ring[i]; 1541 desc->drnp = htole32(addr); 1542 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1543 rxd->rx_desc = desc; 1544 if (vte_newbuf(sc, rxd) != 0) 1545 return (ENOBUFS); 1546 } 1547 1548 bus_dmamap_sync(sc->vte_dmatag, 1549 sc->vte_cdata.vte_rx_ring_map, 0, 1550 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1551 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1552 1553 return (0); 1554 } 1555 1556 static void 1557 vte_rxfilter(struct vte_softc *sc) 1558 { 1559 struct ether_multistep step; 1560 struct ether_multi *enm; 1561 struct ifnet *ifp; 1562 uint8_t *eaddr; 1563 uint32_t crc; 1564 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1565 uint16_t mchash[4], mcr; 1566 int i, nperf; 1567 1568 ifp = &sc->vte_if; 1569 1570 DPRINTF(("vte_rxfilter\n")); 1571 memset(mchash, 0, sizeof(mchash)); 1572 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1573 rxfilt_perf[i][0] = 0xFFFF; 1574 rxfilt_perf[i][1] = 0xFFFF; 1575 rxfilt_perf[i][2] = 0xFFFF; 1576 } 1577 1578 mcr = CSR_READ_2(sc, VTE_MCR0); 1579 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1580 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST); 1581 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1582 mcr |= MCR0_BROADCAST_DIS; 1583 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1584 if ((ifp->if_flags & IFF_PROMISC) != 0) 1585 mcr |= MCR0_PROMISC; 1586 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1587 mcr |= MCR0_MULTICAST; 1588 mchash[0] = 0xFFFF; 1589 mchash[1] = 0xFFFF; 1590 mchash[2] = 0xFFFF; 1591 mchash[3] = 0xFFFF; 1592 goto chipit; 1593 } 1594 1595 ETHER_FIRST_MULTI(step, &sc->vte_ec, enm); 1596 nperf = 0; 1597 while (enm != NULL) { 1598 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1599 sc->vte_if.if_flags |= IFF_ALLMULTI; 1600 mcr |= MCR0_MULTICAST; 1601 mchash[0] = 0xFFFF; 1602 mchash[1] = 0xFFFF; 1603 mchash[2] = 0xFFFF; 1604 mchash[3] = 0xFFFF; 1605 goto chipit; 1606 } 1607 /* 1608 * Program the first 3 multicast groups into 1609 * the perfect filter. For all others, use the 1610 * hash table. 1611 */ 1612 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1613 eaddr = enm->enm_addrlo; 1614 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1615 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1616 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1617 nperf++; 1618 } else { 1619 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1620 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1621 } 1622 ETHER_NEXT_MULTI(step, enm); 1623 } 1624 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1625 mchash[3] != 0) 1626 mcr |= MCR0_MULTICAST; 1627 1628 chipit: 1629 /* Program multicast hash table. */ 1630 DPRINTF(("chipit write multicast\n")); 1631 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1632 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1633 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1634 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1635 /* Program perfect filter table. */ 1636 DPRINTF(("chipit write perfect filter\n")); 1637 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1638 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1639 rxfilt_perf[i][0]); 1640 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1641 rxfilt_perf[i][1]); 1642 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1643 rxfilt_perf[i][2]); 1644 } 1645 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1646 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1647 DPRINTF(("chipit read mcro\n")); 1648 CSR_READ_2(sc, VTE_MCR0); 1649 DPRINTF(("chipit done\n")); 1650 } 1651 1652 /* 1653 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1654 * set up in vte_pci_attach() 1655 */ 1656 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1657 { 1658 int rc; 1659 const struct sysctlnode *node; 1660 1661 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1662 0, CTLTYPE_NODE, "vte", 1663 SYSCTL_DESCR("vte interface controls"), 1664 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1665 goto err; 1666 } 1667 1668 vte_root_num = node->sysctl_num; 1669 return; 1670 1671 err: 1672 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1673 } 1674 1675 static int 1676 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1677 { 1678 int error, t; 1679 struct sysctlnode node; 1680 struct vte_softc *sc; 1681 1682 node = *rnode; 1683 sc = node.sysctl_data; 1684 t = sc->vte_int_rx_mod; 1685 node.sysctl_data = &t; 1686 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1687 if (error || newp == NULL) 1688 return error; 1689 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1690 return EINVAL; 1691 1692 sc->vte_int_rx_mod = t; 1693 vte_miibus_statchg(&sc->vte_if); 1694 return 0; 1695 } 1696 1697 static int 1698 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1699 { 1700 int error, t; 1701 struct sysctlnode node; 1702 struct vte_softc *sc; 1703 1704 node = *rnode; 1705 sc = node.sysctl_data; 1706 t = sc->vte_int_tx_mod; 1707 node.sysctl_data = &t; 1708 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1709 if (error || newp == NULL) 1710 return error; 1711 1712 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1713 return EINVAL; 1714 sc->vte_int_tx_mod = t; 1715 vte_miibus_statchg(&sc->vte_if); 1716 return 0; 1717 } 1718
Indexes created Thu Oct 02 01:09:59 GMT 2025