if_vte.c revision 1.11.4.4
1 2 /* 3 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 /*- 27 * Copyright (c) 2010, Pyun YongHyeon <yongari (at) FreeBSD.org> 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice unmodified, this list of conditions, and the following 35 * disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 53 54 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.11.4.4 2016/10/05 20:55:43 skrll Exp $"); 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/mbuf.h> 62 #include <sys/protosw.h> 63 #include <sys/socket.h> 64 #include <sys/ioctl.h> 65 #include <sys/errno.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/device.h> 69 #include <sys/sysctl.h> 70 71 #include <net/if.h> 72 #include <net/if_media.h> 73 #include <net/if_types.h> 74 #include <net/if_dl.h> 75 #include <net/route.h> 76 #include <net/netisr.h> 77 78 #include <net/bpf.h> 79 #include <net/bpfdesc.h> 80 81 #include <sys/rndsource.h> 82 83 #include "opt_inet.h" 84 #include <net/if_ether.h> 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/in_systm.h> 88 #include <netinet/in_var.h> 89 #include <netinet/ip.h> 90 #include <netinet/if_inarp.h> 91 #endif 92 93 #include <sys/bus.h> 94 #include <sys/intr.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/mii/mii.h> 101 #include <dev/mii/miivar.h> 102 103 #include <dev/pci/if_vtereg.h> 104 #include <dev/pci/if_vtevar.h> 105 106 static int vte_match(device_t, cfdata_t, void *); 107 static void vte_attach(device_t, device_t, void *); 108 static int vte_detach(device_t, int); 109 static int vte_dma_alloc(struct vte_softc *); 110 static void vte_dma_free(struct vte_softc *); 111 static struct vte_txdesc * 112 vte_encap(struct vte_softc *, struct mbuf **); 113 static void vte_get_macaddr(struct vte_softc *); 114 static int vte_init(struct ifnet *); 115 static int vte_init_rx_ring(struct vte_softc *); 116 static int vte_init_tx_ring(struct vte_softc *); 117 static int vte_intr(void *); 118 static int vte_ifioctl(struct ifnet *, u_long, void *); 119 static void vte_mac_config(struct vte_softc *); 120 static int vte_miibus_readreg(device_t, int, int); 121 static void vte_miibus_statchg(struct ifnet *); 122 static void vte_miibus_writereg(device_t, int, int, int); 123 static int vte_mediachange(struct ifnet *); 124 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 125 static void vte_reset(struct vte_softc *); 126 static void vte_rxeof(struct vte_softc *); 127 static void vte_rxfilter(struct vte_softc *); 128 static bool vte_shutdown(device_t, int); 129 static bool vte_suspend(device_t, const pmf_qual_t *); 130 static bool vte_resume(device_t, const pmf_qual_t *); 131 static void vte_ifstart(struct ifnet *); 132 static void vte_start_mac(struct vte_softc *); 133 static void vte_stats_clear(struct vte_softc *); 134 static void vte_stats_update(struct vte_softc *); 135 static void vte_stop(struct ifnet *, int); 136 static void vte_stop_mac(struct vte_softc *); 137 static void vte_tick(void *); 138 static void vte_txeof(struct vte_softc *); 139 static void vte_ifwatchdog(struct ifnet *); 140 141 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 142 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 143 static int vte_root_num; 144 145 #define DPRINTF(a) 146 147 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 148 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 149 150 151 static int 152 vte_match(device_t parent, cfdata_t cf, void *aux) 153 { 154 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 155 156 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 157 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 158 return 1; 159 160 return 0; 161 } 162 163 static void 164 vte_attach(device_t parent, device_t self, void *aux) 165 { 166 struct vte_softc *sc = device_private(self); 167 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 168 struct ifnet * const ifp = &sc->vte_if; 169 int h_valid; 170 pcireg_t reg, csr; 171 pci_intr_handle_t intrhandle; 172 const char *intrstr; 173 int error; 174 const struct sysctlnode *node; 175 int vte_nodenum; 176 char intrbuf[PCI_INTRSTR_LEN]; 177 178 sc->vte_dev = self; 179 180 callout_init(&sc->vte_tick_ch, 0); 181 182 /* Map the device. */ 183 h_valid = 0; 184 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 185 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 186 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 187 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 188 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 189 } 190 if (h_valid == 0) { 191 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 192 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 193 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 194 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 195 &sc->vte_bushandle, NULL, NULL) == 0); 196 } 197 } 198 if (h_valid == 0) { 199 aprint_error_dev(self, "unable to map device registers\n"); 200 return; 201 } 202 sc->vte_dmatag = pa->pa_dmat; 203 /* Enable the device. */ 204 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 205 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 206 csr | PCI_COMMAND_MASTER_ENABLE); 207 208 pci_aprint_devinfo(pa, NULL); 209 210 /* Reset the ethernet controller. */ 211 vte_reset(sc); 212 213 if ((error = vte_dma_alloc(sc)) != 0) 214 return; 215 216 /* Load station address. */ 217 vte_get_macaddr(sc); 218 219 aprint_normal_dev(self, "Ethernet address %s\n", 220 ether_sprintf(sc->vte_eaddr)); 221 222 /* Map and establish interrupts */ 223 if (pci_intr_map(pa, &intrhandle)) { 224 aprint_error_dev(self, "couldn't map interrupt\n"); 225 return; 226 } 227 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 228 sizeof(intrbuf)); 229 sc->vte_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 230 vte_intr, sc); 231 if (sc->vte_ih == NULL) { 232 aprint_error_dev(self, "couldn't establish interrupt"); 233 if (intrstr != NULL) 234 aprint_error(" at %s", intrstr); 235 aprint_error("\n"); 236 return; 237 } 238 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 239 240 sc->vte_if.if_softc = sc; 241 sc->vte_mii.mii_ifp = ifp; 242 sc->vte_mii.mii_readreg = vte_miibus_readreg; 243 sc->vte_mii.mii_writereg = vte_miibus_writereg; 244 sc->vte_mii.mii_statchg = vte_miibus_statchg; 245 sc->vte_ec.ec_mii = &sc->vte_mii; 246 ifmedia_init(&sc->vte_mii.mii_media, IFM_IMASK, vte_mediachange, 247 ether_mediastatus); 248 mii_attach(self, &sc->vte_mii, 0xffffffff, MII_PHY_ANY, 249 MII_OFFSET_ANY, 0); 250 if (LIST_FIRST(&sc->vte_mii.mii_phys) == NULL) { 251 ifmedia_add(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 252 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE); 253 } else 254 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_AUTO); 255 256 /* 257 * We can support 802.1Q VLAN-sized frames. 258 */ 259 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 260 261 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 262 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 263 ifp->if_ioctl = vte_ifioctl; 264 ifp->if_start = vte_ifstart; 265 ifp->if_watchdog = vte_ifwatchdog; 266 ifp->if_init = vte_init; 267 ifp->if_stop = vte_stop; 268 ifp->if_timer = 0; 269 IFQ_SET_READY(&ifp->if_snd); 270 if_attach(ifp); 271 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 272 273 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 274 pmf_class_network_register(self, ifp); 275 else 276 aprint_error_dev(self, "couldn't establish power handler\n"); 277 278 rnd_attach_source(&sc->rnd_source, device_xname(self), 279 RND_TYPE_NET, RND_FLAG_DEFAULT); 280 281 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 282 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 283 SYSCTL_DESCR("vte per-controller controls"), 284 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 285 CTL_EOL) != 0) { 286 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 287 return; 288 } 289 vte_nodenum = node->sysctl_num; 290 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 291 CTLFLAG_READWRITE, 292 CTLTYPE_INT, "int_rxct", 293 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 294 vte_sysctl_intrxct, 0, (void *)sc, 295 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 296 CTL_EOL) != 0) { 297 aprint_normal_dev(sc->vte_dev, 298 "couldn't create int_rxct sysctl node\n"); 299 } 300 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 301 CTLFLAG_READWRITE, 302 CTLTYPE_INT, "int_txct", 303 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 304 vte_sysctl_inttxct, 0, (void *)sc, 305 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 306 CTL_EOL) != 0) { 307 aprint_normal_dev(sc->vte_dev, 308 "couldn't create int_txct sysctl node\n"); 309 } 310 } 311 312 static int 313 vte_detach(device_t dev, int flags __unused) 314 { 315 struct vte_softc *sc = device_private(dev); 316 struct ifnet *ifp = &sc->vte_if; 317 int s; 318 319 s = splnet(); 320 /* Stop the interface. Callouts are stopped in it. */ 321 vte_stop(ifp, 1); 322 splx(s); 323 324 pmf_device_deregister(dev); 325 326 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 327 ifmedia_delete_instance(&sc->vte_mii.mii_media, IFM_INST_ANY); 328 329 ether_ifdetach(ifp); 330 if_detach(ifp); 331 332 vte_dma_free(sc); 333 334 return (0); 335 } 336 337 static int 338 vte_miibus_readreg(device_t dev, int phy, int reg) 339 { 340 struct vte_softc *sc = device_private(dev); 341 int i; 342 343 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 344 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 345 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 346 DELAY(5); 347 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 348 break; 349 } 350 351 if (i == 0) { 352 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 353 return (0); 354 } 355 356 return (CSR_READ_2(sc, VTE_MMRD)); 357 } 358 359 static void 360 vte_miibus_writereg(device_t dev, int phy, int reg, int val) 361 { 362 struct vte_softc *sc = device_private(dev); 363 int i; 364 365 CSR_WRITE_2(sc, VTE_MMWD, val); 366 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 367 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 368 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 369 DELAY(5); 370 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 371 break; 372 } 373 374 if (i == 0) 375 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 376 377 } 378 379 static void 380 vte_miibus_statchg(struct ifnet *ifp) 381 { 382 struct vte_softc *sc = ifp->if_softc; 383 uint16_t val; 384 385 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 386 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 387 388 sc->vte_flags &= ~VTE_FLAG_LINK; 389 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 390 (IFM_ACTIVE | IFM_AVALID)) { 391 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 392 case IFM_10_T: 393 case IFM_100_TX: 394 sc->vte_flags |= VTE_FLAG_LINK; 395 break; 396 default: 397 break; 398 } 399 } 400 401 /* Stop RX/TX MACs. */ 402 vte_stop_mac(sc); 403 /* Program MACs with resolved duplex and flow control. */ 404 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 405 /* 406 * Timer waiting time : (63 + TIMER * 64) MII clock. 407 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 408 */ 409 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 410 val = 18 << VTE_IM_TIMER_SHIFT; 411 else 412 val = 1 << VTE_IM_TIMER_SHIFT; 413 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 414 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 415 CSR_WRITE_2(sc, VTE_MRICR, val); 416 417 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 418 val = 18 << VTE_IM_TIMER_SHIFT; 419 else 420 val = 1 << VTE_IM_TIMER_SHIFT; 421 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 422 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 423 CSR_WRITE_2(sc, VTE_MTICR, val); 424 425 vte_mac_config(sc); 426 vte_start_mac(sc); 427 DPRINTF(("vte_miibus_statchg: link\n")); 428 } 429 } 430 431 static void 432 vte_get_macaddr(struct vte_softc *sc) 433 { 434 uint16_t mid; 435 436 /* 437 * It seems there is no way to reload station address and 438 * it is supposed to be set by BIOS. 439 */ 440 mid = CSR_READ_2(sc, VTE_MID0L); 441 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 442 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 443 mid = CSR_READ_2(sc, VTE_MID0M); 444 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 445 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 446 mid = CSR_READ_2(sc, VTE_MID0H); 447 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 448 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 449 } 450 451 452 static int 453 vte_dma_alloc(struct vte_softc *sc) 454 { 455 struct vte_txdesc *txd; 456 struct vte_rxdesc *rxd; 457 int error, i, rseg; 458 459 /* create DMA map for TX ring */ 460 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 461 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 462 &sc->vte_cdata.vte_tx_ring_map); 463 if (error) { 464 aprint_error_dev(sc->vte_dev, 465 "could not create dma map for TX ring (%d)\n", 466 error); 467 goto fail; 468 } 469 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 470 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 471 VTE_TX_RING_ALIGN, 0, 472 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 473 BUS_DMA_NOWAIT); 474 if (error != 0) { 475 aprint_error_dev(sc->vte_dev, 476 "could not allocate DMA'able memory for TX ring (%d).\n", 477 error); 478 goto fail; 479 } 480 KASSERT(rseg == 1); 481 error = bus_dmamem_map(sc->vte_dmatag, 482 sc->vte_cdata.vte_tx_ring_seg, 1, 483 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 484 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 485 if (error != 0) { 486 aprint_error_dev(sc->vte_dev, 487 "could not map DMA'able memory for TX ring (%d).\n", 488 error); 489 goto fail; 490 } 491 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 492 error = bus_dmamap_load(sc->vte_dmatag, 493 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 494 VTE_TX_RING_SZ, NULL, 495 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 496 if (error != 0) { 497 aprint_error_dev(sc->vte_dev, 498 "could not load DMA'able memory for TX ring.\n"); 499 goto fail; 500 } 501 502 /* create DMA map for RX ring */ 503 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 504 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 505 &sc->vte_cdata.vte_rx_ring_map); 506 if (error) { 507 aprint_error_dev(sc->vte_dev, 508 "could not create dma map for RX ring (%d)\n", 509 error); 510 goto fail; 511 } 512 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 513 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 514 VTE_RX_RING_ALIGN, 0, 515 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 516 BUS_DMA_NOWAIT); 517 if (error != 0) { 518 aprint_error_dev(sc->vte_dev, 519 "could not allocate DMA'able memory for RX ring (%d).\n", 520 error); 521 goto fail; 522 } 523 KASSERT(rseg == 1); 524 error = bus_dmamem_map(sc->vte_dmatag, 525 sc->vte_cdata.vte_rx_ring_seg, 1, 526 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 527 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 528 if (error != 0) { 529 aprint_error_dev(sc->vte_dev, 530 "could not map DMA'able memory for RX ring (%d).\n", 531 error); 532 goto fail; 533 } 534 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 535 error = bus_dmamap_load(sc->vte_dmatag, 536 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 537 VTE_RX_RING_SZ, NULL, 538 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 539 if (error != 0) { 540 aprint_error_dev(sc->vte_dev, 541 "could not load DMA'able memory for RX ring (%d).\n", 542 error); 543 goto fail; 544 } 545 546 /* Create DMA maps for TX buffers. */ 547 for (i = 0; i < VTE_TX_RING_CNT; i++) { 548 txd = &sc->vte_cdata.vte_txdesc[i]; 549 txd->tx_m = NULL; 550 txd->tx_dmamap = NULL; 551 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 552 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 553 &txd->tx_dmamap); 554 if (error != 0) { 555 aprint_error_dev(sc->vte_dev, 556 "could not create TX DMA map %d (%d).\n", i, error); 557 goto fail; 558 } 559 } 560 /* Create DMA maps for RX buffers. */ 561 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 562 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 563 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 564 aprint_error_dev(sc->vte_dev, 565 "could not create spare RX dmamap (%d).\n", error); 566 goto fail; 567 } 568 for (i = 0; i < VTE_RX_RING_CNT; i++) { 569 rxd = &sc->vte_cdata.vte_rxdesc[i]; 570 rxd->rx_m = NULL; 571 rxd->rx_dmamap = NULL; 572 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 573 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 574 &rxd->rx_dmamap); 575 if (error != 0) { 576 aprint_error_dev(sc->vte_dev, 577 "could not create RX dmamap %d (%d).\n", i, error); 578 goto fail; 579 } 580 } 581 return 0; 582 583 fail: 584 vte_dma_free(sc); 585 return (error); 586 } 587 588 static void 589 vte_dma_free(struct vte_softc *sc) 590 { 591 struct vte_txdesc *txd; 592 struct vte_rxdesc *rxd; 593 int i; 594 595 /* TX buffers. */ 596 for (i = 0; i < VTE_TX_RING_CNT; i++) { 597 txd = &sc->vte_cdata.vte_txdesc[i]; 598 if (txd->tx_dmamap != NULL) { 599 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 600 txd->tx_dmamap = NULL; 601 } 602 } 603 /* RX buffers */ 604 for (i = 0; i < VTE_RX_RING_CNT; i++) { 605 rxd = &sc->vte_cdata.vte_rxdesc[i]; 606 if (rxd->rx_dmamap != NULL) { 607 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 608 rxd->rx_dmamap = NULL; 609 } 610 } 611 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 612 bus_dmamap_destroy(sc->vte_dmatag, 613 sc->vte_cdata.vte_rx_sparemap); 614 sc->vte_cdata.vte_rx_sparemap = NULL; 615 } 616 /* TX descriptor ring. */ 617 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 618 bus_dmamap_unload(sc->vte_dmatag, 619 sc->vte_cdata.vte_tx_ring_map); 620 bus_dmamap_destroy(sc->vte_dmatag, 621 sc->vte_cdata.vte_tx_ring_map); 622 } 623 if (sc->vte_cdata.vte_tx_ring != NULL) { 624 bus_dmamem_unmap(sc->vte_dmatag, 625 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 626 bus_dmamem_free(sc->vte_dmatag, 627 sc->vte_cdata.vte_tx_ring_seg, 1); 628 } 629 sc->vte_cdata.vte_tx_ring = NULL; 630 sc->vte_cdata.vte_tx_ring_map = NULL; 631 /* RX ring. */ 632 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 633 bus_dmamap_unload(sc->vte_dmatag, 634 sc->vte_cdata.vte_rx_ring_map); 635 bus_dmamap_destroy(sc->vte_dmatag, 636 sc->vte_cdata.vte_rx_ring_map); 637 } 638 if (sc->vte_cdata.vte_rx_ring != NULL) { 639 bus_dmamem_unmap(sc->vte_dmatag, 640 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 641 bus_dmamem_free(sc->vte_dmatag, 642 sc->vte_cdata.vte_rx_ring_seg, 1); 643 } 644 sc->vte_cdata.vte_rx_ring = NULL; 645 sc->vte_cdata.vte_rx_ring_map = NULL; 646 } 647 648 static bool 649 vte_shutdown(device_t dev, int howto) 650 { 651 652 return (vte_suspend(dev, NULL)); 653 } 654 655 static bool 656 vte_suspend(device_t dev, const pmf_qual_t *qual) 657 { 658 struct vte_softc *sc = device_private(dev); 659 struct ifnet *ifp = &sc->vte_if; 660 661 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 662 if ((ifp->if_flags & IFF_RUNNING) != 0) 663 vte_stop(ifp, 1); 664 return (0); 665 } 666 667 static bool 668 vte_resume(device_t dev, const pmf_qual_t *qual) 669 { 670 struct vte_softc *sc = device_private(dev); 671 struct ifnet *ifp; 672 673 ifp = &sc->vte_if; 674 if ((ifp->if_flags & IFF_UP) != 0) { 675 ifp->if_flags &= ~IFF_RUNNING; 676 vte_init(ifp); 677 } 678 679 return (0); 680 } 681 682 static struct vte_txdesc * 683 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 684 { 685 struct vte_txdesc *txd; 686 struct mbuf *m, *n; 687 int copy, error, padlen; 688 689 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 690 m = *m_head; 691 /* 692 * Controller doesn't auto-pad, so we have to make sure pad 693 * short frames out to the minimum frame length. 694 */ 695 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 696 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 697 else 698 padlen = 0; 699 700 /* 701 * Controller does not support multi-fragmented TX buffers. 702 * Controller spends most of its TX processing time in 703 * de-fragmenting TX buffers. Either faster CPU or more 704 * advanced controller DMA engine is required to speed up 705 * TX path processing. 706 * To mitigate the de-fragmenting issue, perform deep copy 707 * from fragmented mbuf chains to a pre-allocated mbuf 708 * cluster with extra cost of kernel memory. For frames 709 * that is composed of single TX buffer, the deep copy is 710 * bypassed. 711 */ 712 copy = 0; 713 if (m->m_next != NULL) 714 copy++; 715 if (padlen > 0 && (M_READONLY(m) || 716 padlen > M_TRAILINGSPACE(m))) 717 copy++; 718 if (copy != 0) { 719 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 720 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 721 n->m_pkthdr.len = m->m_pkthdr.len; 722 n->m_len = m->m_pkthdr.len; 723 m = n; 724 txd->tx_flags |= VTE_TXMBUF; 725 } 726 727 if (padlen > 0) { 728 /* Zero out the bytes in the pad area. */ 729 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 730 m->m_pkthdr.len += padlen; 731 m->m_len = m->m_pkthdr.len; 732 } 733 734 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 0); 735 if (error != 0) { 736 txd->tx_flags &= ~VTE_TXMBUF; 737 return (NULL); 738 } 739 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 740 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 741 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 742 743 txd->tx_desc->dtlen = 744 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 745 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 746 sc->vte_cdata.vte_tx_cnt++; 747 /* Update producer index. */ 748 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 749 750 /* Finally hand over ownership to controller. */ 751 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 752 txd->tx_m = m; 753 754 return (txd); 755 } 756 757 static void 758 vte_ifstart(struct ifnet *ifp) 759 { 760 struct vte_softc *sc = ifp->if_softc; 761 struct vte_txdesc *txd; 762 struct mbuf *m_head, *m; 763 int enq; 764 765 ifp = &sc->vte_if; 766 767 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 768 769 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 770 IFF_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 771 return; 772 773 for (enq = 0; !IFQ_IS_EMPTY(&ifp->if_snd); ) { 774 /* Reserve one free TX descriptor. */ 775 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 776 ifp->if_flags |= IFF_OACTIVE; 777 break; 778 } 779 IFQ_POLL(&ifp->if_snd, m_head); 780 if (m_head == NULL) 781 break; 782 /* 783 * Pack the data into the transmit ring. If we 784 * don't have room, set the OACTIVE flag and wait 785 * for the NIC to drain the ring. 786 */ 787 DPRINTF(("vte_encap:")); 788 if ((txd = vte_encap(sc, &m_head)) == NULL) { 789 DPRINTF((" failed\n")); 790 break; 791 } 792 DPRINTF((" ok\n")); 793 IFQ_DEQUEUE(&ifp->if_snd, m); 794 KASSERT(m == m_head); 795 796 enq++; 797 /* 798 * If there's a BPF listener, bounce a copy of this frame 799 * to him. 800 */ 801 bpf_mtap(ifp, m_head); 802 /* Free consumed TX frame. */ 803 if ((txd->tx_flags & VTE_TXMBUF) != 0) 804 m_freem(m_head); 805 } 806 807 if (enq > 0) { 808 bus_dmamap_sync(sc->vte_dmatag, 809 sc->vte_cdata.vte_tx_ring_map, 0, 810 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 811 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 812 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 813 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 814 } 815 } 816 817 static void 818 vte_ifwatchdog(struct ifnet *ifp) 819 { 820 struct vte_softc *sc = ifp->if_softc; 821 822 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 823 return; 824 825 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 826 ifp->if_oerrors++; 827 vte_init(ifp); 828 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 829 vte_ifstart(ifp); 830 } 831 832 static int 833 vte_mediachange(struct ifnet *ifp) 834 { 835 int error; 836 struct vte_softc *sc = ifp->if_softc; 837 838 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 839 error = 0; 840 else if (error != 0) { 841 aprint_error_dev(sc->vte_dev, "could not set media\n"); 842 return error; 843 } 844 return 0; 845 846 } 847 848 static int 849 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 850 { 851 struct vte_softc *sc = ifp->if_softc; 852 int error, s; 853 854 s = splnet(); 855 error = ether_ioctl(ifp, cmd, data); 856 if (error == ENETRESET) { 857 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 858 if (ifp->if_flags & IFF_RUNNING) 859 vte_rxfilter(sc); 860 error = 0; 861 } 862 splx(s); 863 return error; 864 } 865 866 static void 867 vte_mac_config(struct vte_softc *sc) 868 { 869 uint16_t mcr; 870 871 mcr = CSR_READ_2(sc, VTE_MCR0); 872 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 873 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 874 mcr |= MCR0_FULL_DUPLEX; 875 #ifdef notyet 876 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 877 mcr |= MCR0_FC_ENB; 878 /* 879 * The data sheet is not clear whether the controller 880 * honors received pause frames or not. The is no 881 * separate control bit for RX pause frame so just 882 * enable MCR0_FC_ENB bit. 883 */ 884 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 885 mcr |= MCR0_FC_ENB; 886 #endif 887 } 888 CSR_WRITE_2(sc, VTE_MCR0, mcr); 889 } 890 891 static void 892 vte_stats_clear(struct vte_softc *sc) 893 { 894 895 /* Reading counter registers clears its contents. */ 896 CSR_READ_2(sc, VTE_CNT_RX_DONE); 897 CSR_READ_2(sc, VTE_CNT_MECNT0); 898 CSR_READ_2(sc, VTE_CNT_MECNT1); 899 CSR_READ_2(sc, VTE_CNT_MECNT2); 900 CSR_READ_2(sc, VTE_CNT_MECNT3); 901 CSR_READ_2(sc, VTE_CNT_TX_DONE); 902 CSR_READ_2(sc, VTE_CNT_MECNT4); 903 CSR_READ_2(sc, VTE_CNT_PAUSE); 904 } 905 906 static void 907 vte_stats_update(struct vte_softc *sc) 908 { 909 struct vte_hw_stats *stat; 910 struct ifnet *ifp = &sc->vte_if; 911 uint16_t value; 912 913 stat = &sc->vte_stats; 914 915 CSR_READ_2(sc, VTE_MECISR); 916 /* RX stats. */ 917 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 918 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 919 stat->rx_bcast_frames += (value >> 8); 920 stat->rx_mcast_frames += (value & 0xFF); 921 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 922 stat->rx_runts += (value >> 8); 923 stat->rx_crcerrs += (value & 0xFF); 924 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 925 stat->rx_long_frames += (value & 0xFF); 926 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 927 stat->rx_fifo_full += (value >> 8); 928 stat->rx_desc_unavail += (value & 0xFF); 929 930 /* TX stats. */ 931 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 932 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 933 stat->tx_underruns += (value >> 8); 934 stat->tx_late_colls += (value & 0xFF); 935 936 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 937 stat->tx_pause_frames += (value >> 8); 938 stat->rx_pause_frames += (value & 0xFF); 939 940 /* Update ifp counters. */ 941 ifp->if_opackets = stat->tx_frames; 942 ifp->if_oerrors = stat->tx_late_colls + stat->tx_underruns; 943 ifp->if_ipackets = stat->rx_frames; 944 ifp->if_ierrors = stat->rx_crcerrs + stat->rx_runts + 945 stat->rx_long_frames + stat->rx_fifo_full; 946 } 947 948 static int 949 vte_intr(void *arg) 950 { 951 struct vte_softc *sc = (struct vte_softc *)arg; 952 struct ifnet *ifp = &sc->vte_if; 953 uint16_t status; 954 int n; 955 956 /* Reading VTE_MISR acknowledges interrupts. */ 957 status = CSR_READ_2(sc, VTE_MISR); 958 DPRINTF(("vte_intr status 0x%x\n", status)); 959 if ((status & VTE_INTRS) == 0) { 960 /* Not ours. */ 961 return 0; 962 } 963 964 /* Disable interrupts. */ 965 CSR_WRITE_2(sc, VTE_MIER, 0); 966 for (n = 8; (status & VTE_INTRS) != 0;) { 967 if ((ifp->if_flags & IFF_RUNNING) == 0) 968 break; 969 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 970 MISR_RX_FIFO_FULL)) != 0) 971 vte_rxeof(sc); 972 if ((status & MISR_TX_DONE) != 0) 973 vte_txeof(sc); 974 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 975 vte_stats_update(sc); 976 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 977 vte_ifstart(ifp); 978 if (--n > 0) 979 status = CSR_READ_2(sc, VTE_MISR); 980 else 981 break; 982 } 983 984 if ((ifp->if_flags & IFF_RUNNING) != 0) { 985 /* Re-enable interrupts. */ 986 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 987 } 988 return 1; 989 } 990 991 static void 992 vte_txeof(struct vte_softc *sc) 993 { 994 struct ifnet *ifp; 995 struct vte_txdesc *txd; 996 uint16_t status; 997 int cons, prog; 998 999 ifp = &sc->vte_if; 1000 1001 if (sc->vte_cdata.vte_tx_cnt == 0) 1002 return; 1003 bus_dmamap_sync(sc->vte_dmatag, 1004 sc->vte_cdata.vte_tx_ring_map, 0, 1005 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1006 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1007 cons = sc->vte_cdata.vte_tx_cons; 1008 /* 1009 * Go through our TX list and free mbufs for those 1010 * frames which have been transmitted. 1011 */ 1012 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1013 txd = &sc->vte_cdata.vte_txdesc[cons]; 1014 status = le16toh(txd->tx_desc->dtst); 1015 if ((status & VTE_DTST_TX_OWN) != 0) 1016 break; 1017 if ((status & VTE_DTST_TX_OK) != 0) 1018 ifp->if_collisions += (status & 0xf); 1019 sc->vte_cdata.vte_tx_cnt--; 1020 /* Reclaim transmitted mbufs. */ 1021 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1022 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1023 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1024 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1025 m_freem(txd->tx_m); 1026 txd->tx_flags &= ~VTE_TXMBUF; 1027 txd->tx_m = NULL; 1028 prog++; 1029 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1030 } 1031 1032 if (prog > 0) { 1033 ifp->if_flags &= ~IFF_OACTIVE; 1034 sc->vte_cdata.vte_tx_cons = cons; 1035 /* 1036 * Unarm watchdog timer only when there is no pending 1037 * frames in TX queue. 1038 */ 1039 if (sc->vte_cdata.vte_tx_cnt == 0) 1040 sc->vte_watchdog_timer = 0; 1041 } 1042 } 1043 1044 static int 1045 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1046 { 1047 struct mbuf *m; 1048 bus_dmamap_t map; 1049 1050 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1051 if (m == NULL) 1052 return (ENOBUFS); 1053 m->m_len = m->m_pkthdr.len = MCLBYTES; 1054 m_adj(m, sizeof(uint32_t)); 1055 1056 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1057 sc->vte_cdata.vte_rx_sparemap, m, 0) != 0) { 1058 m_freem(m); 1059 return (ENOBUFS); 1060 } 1061 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1062 1063 if (rxd->rx_m != NULL) { 1064 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1065 0, rxd->rx_dmamap->dm_mapsize, 1066 BUS_DMASYNC_POSTREAD); 1067 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1068 } 1069 map = rxd->rx_dmamap; 1070 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1071 sc->vte_cdata.vte_rx_sparemap = map; 1072 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1073 0, rxd->rx_dmamap->dm_mapsize, 1074 BUS_DMASYNC_PREREAD); 1075 rxd->rx_m = m; 1076 rxd->rx_desc->drbp = 1077 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1078 rxd->rx_desc->drlen = htole16( 1079 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1080 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, 1081 (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, 1082 rxd->rx_dmamap->dm_segs[0].ds_len)); 1083 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1084 1085 return (0); 1086 } 1087 1088 static void 1089 vte_rxeof(struct vte_softc *sc) 1090 { 1091 struct ifnet *ifp; 1092 struct vte_rxdesc *rxd; 1093 struct mbuf *m; 1094 uint16_t status, total_len; 1095 int cons, prog; 1096 1097 bus_dmamap_sync(sc->vte_dmatag, 1098 sc->vte_cdata.vte_rx_ring_map, 0, 1099 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1100 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1101 cons = sc->vte_cdata.vte_rx_cons; 1102 ifp = &sc->vte_if; 1103 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1104 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1105 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1106 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1107 status = le16toh(rxd->rx_desc->drst); 1108 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", 1109 cons, rxd, rxd->rx_m, status, 1110 VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1111 if ((status & VTE_DRST_RX_OWN) != 0) 1112 break; 1113 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1114 m = rxd->rx_m; 1115 if ((status & VTE_DRST_RX_OK) == 0) { 1116 /* Discard errored frame. */ 1117 rxd->rx_desc->drlen = 1118 htole16(MCLBYTES - sizeof(uint32_t)); 1119 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1120 continue; 1121 } 1122 if (vte_newbuf(sc, rxd) != 0) { 1123 DPRINTF(("vte_rxeof newbuf failed\n")); 1124 ifp->if_ierrors++; 1125 rxd->rx_desc->drlen = 1126 htole16(MCLBYTES - sizeof(uint32_t)); 1127 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1128 continue; 1129 } 1130 1131 /* 1132 * It seems there is no way to strip FCS bytes. 1133 */ 1134 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1135 m_set_rcvif(m, ifp); 1136 ifp->if_ipackets++; 1137 bpf_mtap(ifp, m); 1138 if_percpuq_enqueue(ifp->if_percpuq, m); 1139 } 1140 1141 if (prog > 0) { 1142 /* Update the consumer index. */ 1143 sc->vte_cdata.vte_rx_cons = cons; 1144 /* 1145 * Sync updated RX descriptors such that controller see 1146 * modified RX buffer addresses. 1147 */ 1148 bus_dmamap_sync(sc->vte_dmatag, 1149 sc->vte_cdata.vte_rx_ring_map, 0, 1150 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1151 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1152 #ifdef notyet 1153 /* 1154 * Update residue counter. Controller does not 1155 * keep track of number of available RX descriptors 1156 * such that driver should have to update VTE_MRDCR 1157 * to make controller know how many free RX 1158 * descriptors were added to controller. This is 1159 * a similar mechanism used in VIA velocity 1160 * controllers and it indicates controller just 1161 * polls OWN bit of current RX descriptor pointer. 1162 * A couple of severe issues were seen on sample 1163 * board where the controller continuously emits TX 1164 * pause frames once RX pause threshold crossed. 1165 * Once triggered it never recovered form that 1166 * state, I couldn't find a way to make it back to 1167 * work at least. This issue effectively 1168 * disconnected the system from network. Also, the 1169 * controller used 00:00:00:00:00:00 as source 1170 * station address of TX pause frame. Probably this 1171 * is one of reason why vendor recommends not to 1172 * enable flow control on R6040 controller. 1173 */ 1174 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1175 (((VTE_RX_RING_CNT * 2) / 10) << 1176 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1177 #endif 1178 rnd_add_uint32(&sc->rnd_source, prog); 1179 } 1180 } 1181 1182 static void 1183 vte_tick(void *arg) 1184 { 1185 struct vte_softc *sc; 1186 int s = splnet(); 1187 1188 sc = (struct vte_softc *)arg; 1189 1190 mii_tick(&sc->vte_mii); 1191 vte_stats_update(sc); 1192 vte_txeof(sc); 1193 vte_ifwatchdog(&sc->vte_if); 1194 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1195 splx(s); 1196 } 1197 1198 static void 1199 vte_reset(struct vte_softc *sc) 1200 { 1201 uint16_t mcr; 1202 int i; 1203 1204 mcr = CSR_READ_2(sc, VTE_MCR1); 1205 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1206 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1207 DELAY(10); 1208 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1209 break; 1210 } 1211 if (i == 0) 1212 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1213 /* 1214 * Follow the guide of vendor recommended way to reset MAC. 1215 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1216 * not reliable so manually reset internal state machine. 1217 */ 1218 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1219 CSR_WRITE_2(sc, VTE_MACSM, 0); 1220 DELAY(5000); 1221 } 1222 1223 1224 static int 1225 vte_init(struct ifnet *ifp) 1226 { 1227 struct vte_softc *sc = ifp->if_softc; 1228 bus_addr_t paddr; 1229 uint8_t eaddr[ETHER_ADDR_LEN]; 1230 int s, error; 1231 1232 s = splnet(); 1233 /* 1234 * Cancel any pending I/O. 1235 */ 1236 vte_stop(ifp, 1); 1237 /* 1238 * Reset the chip to a known state. 1239 */ 1240 vte_reset(sc); 1241 1242 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1243 splx(s); 1244 return 0; 1245 } 1246 1247 /* Initialize RX descriptors. */ 1248 if (vte_init_rx_ring(sc) != 0) { 1249 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1250 vte_stop(ifp, 1); 1251 splx(s); 1252 return ENOMEM; 1253 } 1254 if (vte_init_tx_ring(sc) != 0) { 1255 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1256 vte_stop(ifp, 1); 1257 splx(s); 1258 return ENOMEM; 1259 } 1260 1261 /* 1262 * Reprogram the station address. Controller supports up 1263 * to 4 different station addresses so driver programs the 1264 * first station address as its own ethernet address and 1265 * configure the remaining three addresses as perfect 1266 * multicast addresses. 1267 */ 1268 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1269 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1270 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1271 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1272 1273 /* Set TX descriptor base addresses. */ 1274 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1275 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1276 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1277 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1278 1279 /* Set RX descriptor base addresses. */ 1280 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1281 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1282 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1283 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1284 /* 1285 * Initialize RX descriptor residue counter and set RX 1286 * pause threshold to 20% of available RX descriptors. 1287 * See comments on vte_rxeof() for details on flow control 1288 * issues. 1289 */ 1290 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1291 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1292 1293 /* 1294 * Always use maximum frame size that controller can 1295 * support. Otherwise received frames that has longer 1296 * frame length than vte(4) MTU would be silently dropped 1297 * in controller. This would break path-MTU discovery as 1298 * sender wouldn't get any responses from receiver. The 1299 * RX buffer size should be multiple of 4. 1300 * Note, jumbo frames are silently ignored by controller 1301 * and even MAC counters do not detect them. 1302 */ 1303 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1304 1305 /* Configure FIFO. */ 1306 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1307 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1308 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1309 1310 /* 1311 * Configure TX/RX MACs. Actual resolved duplex and flow 1312 * control configuration is done after detecting a valid 1313 * link. Note, we don't generate early interrupt here 1314 * as well since FreeBSD does not have interrupt latency 1315 * problems like Windows. 1316 */ 1317 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1318 /* 1319 * We manually keep track of PHY status changes to 1320 * configure resolved duplex and flow control since only 1321 * duplex configuration can be automatically reflected to 1322 * MCR0. 1323 */ 1324 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1325 MCR1_EXCESS_COL_RETRY_16); 1326 1327 /* Initialize RX filter. */ 1328 vte_rxfilter(sc); 1329 1330 /* Disable TX/RX interrupt moderation control. */ 1331 CSR_WRITE_2(sc, VTE_MRICR, 0); 1332 CSR_WRITE_2(sc, VTE_MTICR, 0); 1333 1334 /* Enable MAC event counter interrupts. */ 1335 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1336 /* Clear MAC statistics. */ 1337 vte_stats_clear(sc); 1338 1339 /* Acknowledge all pending interrupts and clear it. */ 1340 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1341 CSR_WRITE_2(sc, VTE_MISR, 0); 1342 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1343 CSR_READ_2(sc, VTE_MISR))); 1344 1345 sc->vte_flags &= ~VTE_FLAG_LINK; 1346 ifp->if_flags |= IFF_RUNNING; 1347 ifp->if_flags &= ~IFF_OACTIVE; 1348 1349 /* calling mii_mediachg will call back vte_start_mac() */ 1350 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1351 error = 0; 1352 else if (error != 0) { 1353 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1354 splx(s); 1355 return error; 1356 } 1357 1358 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1359 1360 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1361 CSR_READ_2(sc, VTE_MISR))); 1362 splx(s); 1363 return 0; 1364 } 1365 1366 static void 1367 vte_stop(struct ifnet *ifp, int disable) 1368 { 1369 struct vte_softc *sc = ifp->if_softc; 1370 struct vte_txdesc *txd; 1371 struct vte_rxdesc *rxd; 1372 int i; 1373 1374 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1375 if ((ifp->if_flags & IFF_RUNNING) == 0) 1376 return; 1377 /* 1378 * Mark the interface down and cancel the watchdog timer. 1379 */ 1380 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1381 sc->vte_flags &= ~VTE_FLAG_LINK; 1382 callout_stop(&sc->vte_tick_ch); 1383 sc->vte_watchdog_timer = 0; 1384 vte_stats_update(sc); 1385 /* Disable interrupts. */ 1386 CSR_WRITE_2(sc, VTE_MIER, 0); 1387 CSR_WRITE_2(sc, VTE_MECIER, 0); 1388 /* Stop RX/TX MACs. */ 1389 vte_stop_mac(sc); 1390 /* Clear interrupts. */ 1391 CSR_READ_2(sc, VTE_MISR); 1392 /* 1393 * Free TX/RX mbufs still in the queues. 1394 */ 1395 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1396 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1397 if (rxd->rx_m != NULL) { 1398 bus_dmamap_sync(sc->vte_dmatag, 1399 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1400 BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_unload(sc->vte_dmatag, 1402 rxd->rx_dmamap); 1403 m_freem(rxd->rx_m); 1404 rxd->rx_m = NULL; 1405 } 1406 } 1407 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1408 txd = &sc->vte_cdata.vte_txdesc[i]; 1409 if (txd->tx_m != NULL) { 1410 bus_dmamap_sync(sc->vte_dmatag, 1411 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1412 BUS_DMASYNC_POSTWRITE); 1413 bus_dmamap_unload(sc->vte_dmatag, 1414 txd->tx_dmamap); 1415 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1416 m_freem(txd->tx_m); 1417 txd->tx_m = NULL; 1418 txd->tx_flags &= ~VTE_TXMBUF; 1419 } 1420 } 1421 /* Free TX mbuf pools used for deep copy. */ 1422 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1423 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1424 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1425 sc->vte_cdata.vte_txmbufs[i] = NULL; 1426 } 1427 } 1428 } 1429 1430 static void 1431 vte_start_mac(struct vte_softc *sc) 1432 { 1433 struct ifnet *ifp = &sc->vte_if; 1434 uint16_t mcr; 1435 int i; 1436 1437 /* Enable RX/TX MACs. */ 1438 mcr = CSR_READ_2(sc, VTE_MCR0); 1439 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1440 (MCR0_RX_ENB | MCR0_TX_ENB) && 1441 (ifp->if_flags & IFF_RUNNING) != 0) { 1442 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1443 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1444 for (i = VTE_TIMEOUT; i > 0; i--) { 1445 mcr = CSR_READ_2(sc, VTE_MCR0); 1446 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1447 (MCR0_RX_ENB | MCR0_TX_ENB)) 1448 break; 1449 DELAY(10); 1450 } 1451 if (i == 0) 1452 aprint_error_dev(sc->vte_dev, 1453 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1454 } 1455 vte_rxfilter(sc); 1456 } 1457 1458 static void 1459 vte_stop_mac(struct vte_softc *sc) 1460 { 1461 uint16_t mcr; 1462 int i; 1463 1464 /* Disable RX/TX MACs. */ 1465 mcr = CSR_READ_2(sc, VTE_MCR0); 1466 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1467 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1468 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1469 for (i = VTE_TIMEOUT; i > 0; i--) { 1470 mcr = CSR_READ_2(sc, VTE_MCR0); 1471 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1472 break; 1473 DELAY(10); 1474 } 1475 if (i == 0) 1476 aprint_error_dev(sc->vte_dev, 1477 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1478 } 1479 } 1480 1481 static int 1482 vte_init_tx_ring(struct vte_softc *sc) 1483 { 1484 struct vte_tx_desc *desc; 1485 struct vte_txdesc *txd; 1486 bus_addr_t addr; 1487 int i; 1488 1489 sc->vte_cdata.vte_tx_prod = 0; 1490 sc->vte_cdata.vte_tx_cons = 0; 1491 sc->vte_cdata.vte_tx_cnt = 0; 1492 1493 /* Pre-allocate TX mbufs for deep copy. */ 1494 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1495 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1496 MT_DATA, M_PKTHDR); 1497 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1498 return (ENOBUFS); 1499 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1500 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1501 } 1502 desc = sc->vte_cdata.vte_tx_ring; 1503 bzero(desc, VTE_TX_RING_SZ); 1504 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1505 txd = &sc->vte_cdata.vte_txdesc[i]; 1506 txd->tx_m = NULL; 1507 if (i != VTE_TX_RING_CNT - 1) 1508 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1509 sizeof(struct vte_tx_desc) * (i + 1); 1510 else 1511 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1512 sizeof(struct vte_tx_desc) * 0; 1513 desc = &sc->vte_cdata.vte_tx_ring[i]; 1514 desc->dtnp = htole32(addr); 1515 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1516 txd->tx_desc = desc; 1517 } 1518 1519 bus_dmamap_sync(sc->vte_dmatag, 1520 sc->vte_cdata.vte_tx_ring_map, 0, 1521 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1522 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1523 return (0); 1524 } 1525 1526 static int 1527 vte_init_rx_ring(struct vte_softc *sc) 1528 { 1529 struct vte_rx_desc *desc; 1530 struct vte_rxdesc *rxd; 1531 bus_addr_t addr; 1532 int i; 1533 1534 sc->vte_cdata.vte_rx_cons = 0; 1535 desc = sc->vte_cdata.vte_rx_ring; 1536 bzero(desc, VTE_RX_RING_SZ); 1537 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1538 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1539 rxd->rx_m = NULL; 1540 if (i != VTE_RX_RING_CNT - 1) 1541 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1542 + sizeof(struct vte_rx_desc) * (i + 1); 1543 else 1544 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1545 + sizeof(struct vte_rx_desc) * 0; 1546 desc = &sc->vte_cdata.vte_rx_ring[i]; 1547 desc->drnp = htole32(addr); 1548 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1549 rxd->rx_desc = desc; 1550 if (vte_newbuf(sc, rxd) != 0) 1551 return (ENOBUFS); 1552 } 1553 1554 bus_dmamap_sync(sc->vte_dmatag, 1555 sc->vte_cdata.vte_rx_ring_map, 0, 1556 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1558 1559 return (0); 1560 } 1561 1562 static void 1563 vte_rxfilter(struct vte_softc *sc) 1564 { 1565 struct ether_multistep step; 1566 struct ether_multi *enm; 1567 struct ifnet *ifp; 1568 uint8_t *eaddr; 1569 uint32_t crc; 1570 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1571 uint16_t mchash[4], mcr; 1572 int i, nperf; 1573 1574 ifp = &sc->vte_if; 1575 1576 DPRINTF(("vte_rxfilter\n")); 1577 memset(mchash, 0, sizeof(mchash)); 1578 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1579 rxfilt_perf[i][0] = 0xFFFF; 1580 rxfilt_perf[i][1] = 0xFFFF; 1581 rxfilt_perf[i][2] = 0xFFFF; 1582 } 1583 1584 mcr = CSR_READ_2(sc, VTE_MCR0); 1585 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1586 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST); 1587 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1588 mcr |= MCR0_BROADCAST_DIS; 1589 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1590 if ((ifp->if_flags & IFF_PROMISC) != 0) 1591 mcr |= MCR0_PROMISC; 1592 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1593 mcr |= MCR0_MULTICAST; 1594 mchash[0] = 0xFFFF; 1595 mchash[1] = 0xFFFF; 1596 mchash[2] = 0xFFFF; 1597 mchash[3] = 0xFFFF; 1598 goto chipit; 1599 } 1600 1601 ETHER_FIRST_MULTI(step, &sc->vte_ec, enm); 1602 nperf = 0; 1603 while (enm != NULL) { 1604 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1605 sc->vte_if.if_flags |= IFF_ALLMULTI; 1606 mcr |= MCR0_MULTICAST; 1607 mchash[0] = 0xFFFF; 1608 mchash[1] = 0xFFFF; 1609 mchash[2] = 0xFFFF; 1610 mchash[3] = 0xFFFF; 1611 goto chipit; 1612 } 1613 /* 1614 * Program the first 3 multicast groups into 1615 * the perfect filter. For all others, use the 1616 * hash table. 1617 */ 1618 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1619 eaddr = enm->enm_addrlo; 1620 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1621 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1622 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1623 nperf++; 1624 } else { 1625 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1626 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1627 } 1628 ETHER_NEXT_MULTI(step, enm); 1629 } 1630 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1631 mchash[3] != 0) 1632 mcr |= MCR0_MULTICAST; 1633 1634 chipit: 1635 /* Program multicast hash table. */ 1636 DPRINTF(("chipit write multicast\n")); 1637 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1638 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1639 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1640 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1641 /* Program perfect filter table. */ 1642 DPRINTF(("chipit write perfect filter\n")); 1643 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1644 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1645 rxfilt_perf[i][0]); 1646 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1647 rxfilt_perf[i][1]); 1648 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1649 rxfilt_perf[i][2]); 1650 } 1651 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1652 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1653 DPRINTF(("chipit read mcro\n")); 1654 CSR_READ_2(sc, VTE_MCR0); 1655 DPRINTF(("chipit done\n")); 1656 } 1657 1658 /* 1659 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1660 * set up in vte_pci_attach() 1661 */ 1662 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1663 { 1664 int rc; 1665 const struct sysctlnode *node; 1666 1667 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1668 0, CTLTYPE_NODE, "vte", 1669 SYSCTL_DESCR("vte interface controls"), 1670 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1671 goto err; 1672 } 1673 1674 vte_root_num = node->sysctl_num; 1675 return; 1676 1677 err: 1678 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1679 } 1680 1681 static int 1682 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1683 { 1684 int error, t; 1685 struct sysctlnode node; 1686 struct vte_softc *sc; 1687 1688 node = *rnode; 1689 sc = node.sysctl_data; 1690 t = sc->vte_int_rx_mod; 1691 node.sysctl_data = &t; 1692 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1693 if (error || newp == NULL) 1694 return error; 1695 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1696 return EINVAL; 1697 1698 sc->vte_int_rx_mod = t; 1699 vte_miibus_statchg(&sc->vte_if); 1700 return 0; 1701 } 1702 1703 static int 1704 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1705 { 1706 int error, t; 1707 struct sysctlnode node; 1708 struct vte_softc *sc; 1709 1710 node = *rnode; 1711 sc = node.sysctl_data; 1712 t = sc->vte_int_tx_mod; 1713 node.sysctl_data = &t; 1714 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1715 if (error || newp == NULL) 1716 return error; 1717 1718 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1719 return EINVAL; 1720 sc->vte_int_tx_mod = t; 1721 vte_miibus_statchg(&sc->vte_if); 1722 return 0; 1723 } 1724
Indexes created Thu Oct 02 01:09:59 GMT 2025