if_vte.c revision 1.11.4.6
1 /* $NetBSD: if_vte.c,v 1.11.4.6 2017/08/28 17:52:05 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2010, Pyun YongHyeon <yongari (at) FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 54 55 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.11.4.6 2017/08/28 17:52:05 skrll Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/mbuf.h> 63 #include <sys/protosw.h> 64 #include <sys/socket.h> 65 #include <sys/ioctl.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_dl.h> 76 #include <net/route.h> 77 #include <net/netisr.h> 78 79 #include <net/bpf.h> 80 #include <net/bpfdesc.h> 81 82 #include <sys/rndsource.h> 83 84 #include "opt_inet.h" 85 #include <net/if_ether.h> 86 #ifdef INET 87 #include <netinet/in.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #include <netinet/if_inarp.h> 92 #endif 93 94 #include <sys/bus.h> 95 #include <sys/intr.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcidevs.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 104 #include <dev/pci/if_vtereg.h> 105 #include <dev/pci/if_vtevar.h> 106 107 static int vte_match(device_t, cfdata_t, void *); 108 static void vte_attach(device_t, device_t, void *); 109 static int vte_detach(device_t, int); 110 static int vte_dma_alloc(struct vte_softc *); 111 static void vte_dma_free(struct vte_softc *); 112 static struct vte_txdesc * 113 vte_encap(struct vte_softc *, struct mbuf **); 114 static void vte_get_macaddr(struct vte_softc *); 115 static int vte_init(struct ifnet *); 116 static int vte_init_rx_ring(struct vte_softc *); 117 static int vte_init_tx_ring(struct vte_softc *); 118 static int vte_intr(void *); 119 static int vte_ifioctl(struct ifnet *, u_long, void *); 120 static void vte_mac_config(struct vte_softc *); 121 static int vte_miibus_readreg(device_t, int, int); 122 static void vte_miibus_statchg(struct ifnet *); 123 static void vte_miibus_writereg(device_t, int, int, int); 124 static int vte_mediachange(struct ifnet *); 125 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 126 static void vte_reset(struct vte_softc *); 127 static void vte_rxeof(struct vte_softc *); 128 static void vte_rxfilter(struct vte_softc *); 129 static bool vte_shutdown(device_t, int); 130 static bool vte_suspend(device_t, const pmf_qual_t *); 131 static bool vte_resume(device_t, const pmf_qual_t *); 132 static void vte_ifstart(struct ifnet *); 133 static void vte_start_mac(struct vte_softc *); 134 static void vte_stats_clear(struct vte_softc *); 135 static void vte_stats_update(struct vte_softc *); 136 static void vte_stop(struct ifnet *, int); 137 static void vte_stop_mac(struct vte_softc *); 138 static void vte_tick(void *); 139 static void vte_txeof(struct vte_softc *); 140 static void vte_ifwatchdog(struct ifnet *); 141 142 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 143 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 144 static int vte_root_num; 145 146 #define DPRINTF(a) 147 148 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 149 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 150 151 152 static int 153 vte_match(device_t parent, cfdata_t cf, void *aux) 154 { 155 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 156 157 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 158 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 159 return 1; 160 161 return 0; 162 } 163 164 static void 165 vte_attach(device_t parent, device_t self, void *aux) 166 { 167 struct vte_softc *sc = device_private(self); 168 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 169 struct ifnet * const ifp = &sc->vte_if; 170 int h_valid; 171 pcireg_t reg, csr; 172 pci_intr_handle_t intrhandle; 173 const char *intrstr; 174 int error; 175 const struct sysctlnode *node; 176 int vte_nodenum; 177 char intrbuf[PCI_INTRSTR_LEN]; 178 179 sc->vte_dev = self; 180 181 callout_init(&sc->vte_tick_ch, 0); 182 183 /* Map the device. */ 184 h_valid = 0; 185 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 186 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 187 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 188 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 189 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 190 } 191 if (h_valid == 0) { 192 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 193 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 194 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 195 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 196 &sc->vte_bushandle, NULL, NULL) == 0); 197 } 198 } 199 if (h_valid == 0) { 200 aprint_error_dev(self, "unable to map device registers\n"); 201 return; 202 } 203 sc->vte_dmatag = pa->pa_dmat; 204 /* Enable the device. */ 205 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 206 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 207 csr | PCI_COMMAND_MASTER_ENABLE); 208 209 pci_aprint_devinfo(pa, NULL); 210 211 /* Reset the ethernet controller. */ 212 vte_reset(sc); 213 214 if ((error = vte_dma_alloc(sc)) != 0) 215 return; 216 217 /* Load station address. */ 218 vte_get_macaddr(sc); 219 220 aprint_normal_dev(self, "Ethernet address %s\n", 221 ether_sprintf(sc->vte_eaddr)); 222 223 /* Map and establish interrupts */ 224 if (pci_intr_map(pa, &intrhandle)) { 225 aprint_error_dev(self, "couldn't map interrupt\n"); 226 return; 227 } 228 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 229 sizeof(intrbuf)); 230 sc->vte_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 231 vte_intr, sc); 232 if (sc->vte_ih == NULL) { 233 aprint_error_dev(self, "couldn't establish interrupt"); 234 if (intrstr != NULL) 235 aprint_error(" at %s", intrstr); 236 aprint_error("\n"); 237 return; 238 } 239 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 240 241 sc->vte_if.if_softc = sc; 242 sc->vte_mii.mii_ifp = ifp; 243 sc->vte_mii.mii_readreg = vte_miibus_readreg; 244 sc->vte_mii.mii_writereg = vte_miibus_writereg; 245 sc->vte_mii.mii_statchg = vte_miibus_statchg; 246 sc->vte_ec.ec_mii = &sc->vte_mii; 247 ifmedia_init(&sc->vte_mii.mii_media, IFM_IMASK, vte_mediachange, 248 ether_mediastatus); 249 mii_attach(self, &sc->vte_mii, 0xffffffff, MII_PHY_ANY, 250 MII_OFFSET_ANY, 0); 251 if (LIST_FIRST(&sc->vte_mii.mii_phys) == NULL) { 252 ifmedia_add(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 253 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE); 254 } else 255 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_AUTO); 256 257 /* 258 * We can support 802.1Q VLAN-sized frames. 259 */ 260 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 261 262 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 263 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 264 ifp->if_ioctl = vte_ifioctl; 265 ifp->if_start = vte_ifstart; 266 ifp->if_watchdog = vte_ifwatchdog; 267 ifp->if_init = vte_init; 268 ifp->if_stop = vte_stop; 269 ifp->if_timer = 0; 270 IFQ_SET_READY(&ifp->if_snd); 271 if_attach(ifp); 272 if_deferred_start_init(ifp, NULL); 273 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 274 275 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 276 pmf_class_network_register(self, ifp); 277 else 278 aprint_error_dev(self, "couldn't establish power handler\n"); 279 280 rnd_attach_source(&sc->rnd_source, device_xname(self), 281 RND_TYPE_NET, RND_FLAG_DEFAULT); 282 283 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 284 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 285 SYSCTL_DESCR("vte per-controller controls"), 286 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 287 CTL_EOL) != 0) { 288 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 289 return; 290 } 291 vte_nodenum = node->sysctl_num; 292 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 293 CTLFLAG_READWRITE, 294 CTLTYPE_INT, "int_rxct", 295 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 296 vte_sysctl_intrxct, 0, (void *)sc, 297 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 298 CTL_EOL) != 0) { 299 aprint_normal_dev(sc->vte_dev, 300 "couldn't create int_rxct sysctl node\n"); 301 } 302 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 303 CTLFLAG_READWRITE, 304 CTLTYPE_INT, "int_txct", 305 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 306 vte_sysctl_inttxct, 0, (void *)sc, 307 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 308 CTL_EOL) != 0) { 309 aprint_normal_dev(sc->vte_dev, 310 "couldn't create int_txct sysctl node\n"); 311 } 312 } 313 314 static int 315 vte_detach(device_t dev, int flags __unused) 316 { 317 struct vte_softc *sc = device_private(dev); 318 struct ifnet *ifp = &sc->vte_if; 319 int s; 320 321 s = splnet(); 322 /* Stop the interface. Callouts are stopped in it. */ 323 vte_stop(ifp, 1); 324 splx(s); 325 326 pmf_device_deregister(dev); 327 328 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 329 ifmedia_delete_instance(&sc->vte_mii.mii_media, IFM_INST_ANY); 330 331 ether_ifdetach(ifp); 332 if_detach(ifp); 333 334 vte_dma_free(sc); 335 336 return (0); 337 } 338 339 static int 340 vte_miibus_readreg(device_t dev, int phy, int reg) 341 { 342 struct vte_softc *sc = device_private(dev); 343 int i; 344 345 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 346 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 347 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 348 DELAY(5); 349 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 350 break; 351 } 352 353 if (i == 0) { 354 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 355 return (0); 356 } 357 358 return (CSR_READ_2(sc, VTE_MMRD)); 359 } 360 361 static void 362 vte_miibus_writereg(device_t dev, int phy, int reg, int val) 363 { 364 struct vte_softc *sc = device_private(dev); 365 int i; 366 367 CSR_WRITE_2(sc, VTE_MMWD, val); 368 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 369 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 370 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 371 DELAY(5); 372 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 373 break; 374 } 375 376 if (i == 0) 377 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 378 379 } 380 381 static void 382 vte_miibus_statchg(struct ifnet *ifp) 383 { 384 struct vte_softc *sc = ifp->if_softc; 385 uint16_t val; 386 387 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 388 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 389 390 sc->vte_flags &= ~VTE_FLAG_LINK; 391 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 392 (IFM_ACTIVE | IFM_AVALID)) { 393 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 394 case IFM_10_T: 395 case IFM_100_TX: 396 sc->vte_flags |= VTE_FLAG_LINK; 397 break; 398 default: 399 break; 400 } 401 } 402 403 /* Stop RX/TX MACs. */ 404 vte_stop_mac(sc); 405 /* Program MACs with resolved duplex and flow control. */ 406 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 407 /* 408 * Timer waiting time : (63 + TIMER * 64) MII clock. 409 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 410 */ 411 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 412 val = 18 << VTE_IM_TIMER_SHIFT; 413 else 414 val = 1 << VTE_IM_TIMER_SHIFT; 415 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 416 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 417 CSR_WRITE_2(sc, VTE_MRICR, val); 418 419 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 420 val = 18 << VTE_IM_TIMER_SHIFT; 421 else 422 val = 1 << VTE_IM_TIMER_SHIFT; 423 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 424 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 425 CSR_WRITE_2(sc, VTE_MTICR, val); 426 427 vte_mac_config(sc); 428 vte_start_mac(sc); 429 DPRINTF(("vte_miibus_statchg: link\n")); 430 } 431 } 432 433 static void 434 vte_get_macaddr(struct vte_softc *sc) 435 { 436 uint16_t mid; 437 438 /* 439 * It seems there is no way to reload station address and 440 * it is supposed to be set by BIOS. 441 */ 442 mid = CSR_READ_2(sc, VTE_MID0L); 443 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 444 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 445 mid = CSR_READ_2(sc, VTE_MID0M); 446 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 447 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 448 mid = CSR_READ_2(sc, VTE_MID0H); 449 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 450 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 451 } 452 453 454 static int 455 vte_dma_alloc(struct vte_softc *sc) 456 { 457 struct vte_txdesc *txd; 458 struct vte_rxdesc *rxd; 459 int error, i, rseg; 460 461 /* create DMA map for TX ring */ 462 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 463 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 464 &sc->vte_cdata.vte_tx_ring_map); 465 if (error) { 466 aprint_error_dev(sc->vte_dev, 467 "could not create dma map for TX ring (%d)\n", 468 error); 469 goto fail; 470 } 471 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 472 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 473 VTE_TX_RING_ALIGN, 0, 474 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 475 BUS_DMA_NOWAIT); 476 if (error != 0) { 477 aprint_error_dev(sc->vte_dev, 478 "could not allocate DMA'able memory for TX ring (%d).\n", 479 error); 480 goto fail; 481 } 482 KASSERT(rseg == 1); 483 error = bus_dmamem_map(sc->vte_dmatag, 484 sc->vte_cdata.vte_tx_ring_seg, 1, 485 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 486 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 487 if (error != 0) { 488 aprint_error_dev(sc->vte_dev, 489 "could not map DMA'able memory for TX ring (%d).\n", 490 error); 491 goto fail; 492 } 493 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 494 error = bus_dmamap_load(sc->vte_dmatag, 495 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 496 VTE_TX_RING_SZ, NULL, 497 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 498 if (error != 0) { 499 aprint_error_dev(sc->vte_dev, 500 "could not load DMA'able memory for TX ring.\n"); 501 goto fail; 502 } 503 504 /* create DMA map for RX ring */ 505 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 506 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 507 &sc->vte_cdata.vte_rx_ring_map); 508 if (error) { 509 aprint_error_dev(sc->vte_dev, 510 "could not create dma map for RX ring (%d)\n", 511 error); 512 goto fail; 513 } 514 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 515 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 516 VTE_RX_RING_ALIGN, 0, 517 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 518 BUS_DMA_NOWAIT); 519 if (error != 0) { 520 aprint_error_dev(sc->vte_dev, 521 "could not allocate DMA'able memory for RX ring (%d).\n", 522 error); 523 goto fail; 524 } 525 KASSERT(rseg == 1); 526 error = bus_dmamem_map(sc->vte_dmatag, 527 sc->vte_cdata.vte_rx_ring_seg, 1, 528 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 529 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 530 if (error != 0) { 531 aprint_error_dev(sc->vte_dev, 532 "could not map DMA'able memory for RX ring (%d).\n", 533 error); 534 goto fail; 535 } 536 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 537 error = bus_dmamap_load(sc->vte_dmatag, 538 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 539 VTE_RX_RING_SZ, NULL, 540 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 541 if (error != 0) { 542 aprint_error_dev(sc->vte_dev, 543 "could not load DMA'able memory for RX ring (%d).\n", 544 error); 545 goto fail; 546 } 547 548 /* Create DMA maps for TX buffers. */ 549 for (i = 0; i < VTE_TX_RING_CNT; i++) { 550 txd = &sc->vte_cdata.vte_txdesc[i]; 551 txd->tx_m = NULL; 552 txd->tx_dmamap = NULL; 553 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 554 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 555 &txd->tx_dmamap); 556 if (error != 0) { 557 aprint_error_dev(sc->vte_dev, 558 "could not create TX DMA map %d (%d).\n", i, error); 559 goto fail; 560 } 561 } 562 /* Create DMA maps for RX buffers. */ 563 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 564 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 565 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 566 aprint_error_dev(sc->vte_dev, 567 "could not create spare RX dmamap (%d).\n", error); 568 goto fail; 569 } 570 for (i = 0; i < VTE_RX_RING_CNT; i++) { 571 rxd = &sc->vte_cdata.vte_rxdesc[i]; 572 rxd->rx_m = NULL; 573 rxd->rx_dmamap = NULL; 574 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 575 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 576 &rxd->rx_dmamap); 577 if (error != 0) { 578 aprint_error_dev(sc->vte_dev, 579 "could not create RX dmamap %d (%d).\n", i, error); 580 goto fail; 581 } 582 } 583 return 0; 584 585 fail: 586 vte_dma_free(sc); 587 return (error); 588 } 589 590 static void 591 vte_dma_free(struct vte_softc *sc) 592 { 593 struct vte_txdesc *txd; 594 struct vte_rxdesc *rxd; 595 int i; 596 597 /* TX buffers. */ 598 for (i = 0; i < VTE_TX_RING_CNT; i++) { 599 txd = &sc->vte_cdata.vte_txdesc[i]; 600 if (txd->tx_dmamap != NULL) { 601 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 602 txd->tx_dmamap = NULL; 603 } 604 } 605 /* RX buffers */ 606 for (i = 0; i < VTE_RX_RING_CNT; i++) { 607 rxd = &sc->vte_cdata.vte_rxdesc[i]; 608 if (rxd->rx_dmamap != NULL) { 609 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 610 rxd->rx_dmamap = NULL; 611 } 612 } 613 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 614 bus_dmamap_destroy(sc->vte_dmatag, 615 sc->vte_cdata.vte_rx_sparemap); 616 sc->vte_cdata.vte_rx_sparemap = NULL; 617 } 618 /* TX descriptor ring. */ 619 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 620 bus_dmamap_unload(sc->vte_dmatag, 621 sc->vte_cdata.vte_tx_ring_map); 622 bus_dmamap_destroy(sc->vte_dmatag, 623 sc->vte_cdata.vte_tx_ring_map); 624 } 625 if (sc->vte_cdata.vte_tx_ring != NULL) { 626 bus_dmamem_unmap(sc->vte_dmatag, 627 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 628 bus_dmamem_free(sc->vte_dmatag, 629 sc->vte_cdata.vte_tx_ring_seg, 1); 630 } 631 sc->vte_cdata.vte_tx_ring = NULL; 632 sc->vte_cdata.vte_tx_ring_map = NULL; 633 /* RX ring. */ 634 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 635 bus_dmamap_unload(sc->vte_dmatag, 636 sc->vte_cdata.vte_rx_ring_map); 637 bus_dmamap_destroy(sc->vte_dmatag, 638 sc->vte_cdata.vte_rx_ring_map); 639 } 640 if (sc->vte_cdata.vte_rx_ring != NULL) { 641 bus_dmamem_unmap(sc->vte_dmatag, 642 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 643 bus_dmamem_free(sc->vte_dmatag, 644 sc->vte_cdata.vte_rx_ring_seg, 1); 645 } 646 sc->vte_cdata.vte_rx_ring = NULL; 647 sc->vte_cdata.vte_rx_ring_map = NULL; 648 } 649 650 static bool 651 vte_shutdown(device_t dev, int howto) 652 { 653 654 return (vte_suspend(dev, NULL)); 655 } 656 657 static bool 658 vte_suspend(device_t dev, const pmf_qual_t *qual) 659 { 660 struct vte_softc *sc = device_private(dev); 661 struct ifnet *ifp = &sc->vte_if; 662 663 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 664 if ((ifp->if_flags & IFF_RUNNING) != 0) 665 vte_stop(ifp, 1); 666 return (0); 667 } 668 669 static bool 670 vte_resume(device_t dev, const pmf_qual_t *qual) 671 { 672 struct vte_softc *sc = device_private(dev); 673 struct ifnet *ifp; 674 675 ifp = &sc->vte_if; 676 if ((ifp->if_flags & IFF_UP) != 0) { 677 ifp->if_flags &= ~IFF_RUNNING; 678 vte_init(ifp); 679 } 680 681 return (0); 682 } 683 684 static struct vte_txdesc * 685 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 686 { 687 struct vte_txdesc *txd; 688 struct mbuf *m, *n; 689 int copy, error, padlen; 690 691 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 692 m = *m_head; 693 /* 694 * Controller doesn't auto-pad, so we have to make sure pad 695 * short frames out to the minimum frame length. 696 */ 697 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 698 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 699 else 700 padlen = 0; 701 702 /* 703 * Controller does not support multi-fragmented TX buffers. 704 * Controller spends most of its TX processing time in 705 * de-fragmenting TX buffers. Either faster CPU or more 706 * advanced controller DMA engine is required to speed up 707 * TX path processing. 708 * To mitigate the de-fragmenting issue, perform deep copy 709 * from fragmented mbuf chains to a pre-allocated mbuf 710 * cluster with extra cost of kernel memory. For frames 711 * that is composed of single TX buffer, the deep copy is 712 * bypassed. 713 */ 714 copy = 0; 715 if (m->m_next != NULL) 716 copy++; 717 if (padlen > 0 && (M_READONLY(m) || 718 padlen > M_TRAILINGSPACE(m))) 719 copy++; 720 if (copy != 0) { 721 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 722 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 723 n->m_pkthdr.len = m->m_pkthdr.len; 724 n->m_len = m->m_pkthdr.len; 725 m = n; 726 txd->tx_flags |= VTE_TXMBUF; 727 } 728 729 if (padlen > 0) { 730 /* Zero out the bytes in the pad area. */ 731 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 732 m->m_pkthdr.len += padlen; 733 m->m_len = m->m_pkthdr.len; 734 } 735 736 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 737 BUS_DMA_NOWAIT); 738 if (error != 0) { 739 txd->tx_flags &= ~VTE_TXMBUF; 740 return (NULL); 741 } 742 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 743 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 744 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 745 746 txd->tx_desc->dtlen = 747 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 748 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 749 sc->vte_cdata.vte_tx_cnt++; 750 /* Update producer index. */ 751 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 752 753 /* Finally hand over ownership to controller. */ 754 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 755 txd->tx_m = m; 756 757 return (txd); 758 } 759 760 static void 761 vte_ifstart(struct ifnet *ifp) 762 { 763 struct vte_softc *sc = ifp->if_softc; 764 struct vte_txdesc *txd; 765 struct mbuf *m_head, *m; 766 int enq; 767 768 ifp = &sc->vte_if; 769 770 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 771 772 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 773 IFF_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 774 return; 775 776 for (enq = 0; !IFQ_IS_EMPTY(&ifp->if_snd); ) { 777 /* Reserve one free TX descriptor. */ 778 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 779 ifp->if_flags |= IFF_OACTIVE; 780 break; 781 } 782 IFQ_POLL(&ifp->if_snd, m_head); 783 if (m_head == NULL) 784 break; 785 /* 786 * Pack the data into the transmit ring. If we 787 * don't have room, set the OACTIVE flag and wait 788 * for the NIC to drain the ring. 789 */ 790 DPRINTF(("vte_encap:")); 791 if ((txd = vte_encap(sc, &m_head)) == NULL) { 792 DPRINTF((" failed\n")); 793 break; 794 } 795 DPRINTF((" ok\n")); 796 IFQ_DEQUEUE(&ifp->if_snd, m); 797 KASSERT(m == m_head); 798 799 enq++; 800 /* 801 * If there's a BPF listener, bounce a copy of this frame 802 * to him. 803 */ 804 bpf_mtap(ifp, m_head); 805 /* Free consumed TX frame. */ 806 if ((txd->tx_flags & VTE_TXMBUF) != 0) 807 m_freem(m_head); 808 } 809 810 if (enq > 0) { 811 bus_dmamap_sync(sc->vte_dmatag, 812 sc->vte_cdata.vte_tx_ring_map, 0, 813 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 815 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 816 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 817 } 818 } 819 820 static void 821 vte_ifwatchdog(struct ifnet *ifp) 822 { 823 struct vte_softc *sc = ifp->if_softc; 824 825 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 826 return; 827 828 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 829 ifp->if_oerrors++; 830 vte_init(ifp); 831 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 832 vte_ifstart(ifp); 833 } 834 835 static int 836 vte_mediachange(struct ifnet *ifp) 837 { 838 int error; 839 struct vte_softc *sc = ifp->if_softc; 840 841 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 842 error = 0; 843 else if (error != 0) { 844 aprint_error_dev(sc->vte_dev, "could not set media\n"); 845 return error; 846 } 847 return 0; 848 849 } 850 851 static int 852 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 853 { 854 struct vte_softc *sc = ifp->if_softc; 855 int error, s; 856 857 s = splnet(); 858 error = ether_ioctl(ifp, cmd, data); 859 if (error == ENETRESET) { 860 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 861 if (ifp->if_flags & IFF_RUNNING) 862 vte_rxfilter(sc); 863 error = 0; 864 } 865 splx(s); 866 return error; 867 } 868 869 static void 870 vte_mac_config(struct vte_softc *sc) 871 { 872 uint16_t mcr; 873 874 mcr = CSR_READ_2(sc, VTE_MCR0); 875 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 876 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 877 mcr |= MCR0_FULL_DUPLEX; 878 #ifdef notyet 879 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 880 mcr |= MCR0_FC_ENB; 881 /* 882 * The data sheet is not clear whether the controller 883 * honors received pause frames or not. The is no 884 * separate control bit for RX pause frame so just 885 * enable MCR0_FC_ENB bit. 886 */ 887 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 888 mcr |= MCR0_FC_ENB; 889 #endif 890 } 891 CSR_WRITE_2(sc, VTE_MCR0, mcr); 892 } 893 894 static void 895 vte_stats_clear(struct vte_softc *sc) 896 { 897 898 /* Reading counter registers clears its contents. */ 899 CSR_READ_2(sc, VTE_CNT_RX_DONE); 900 CSR_READ_2(sc, VTE_CNT_MECNT0); 901 CSR_READ_2(sc, VTE_CNT_MECNT1); 902 CSR_READ_2(sc, VTE_CNT_MECNT2); 903 CSR_READ_2(sc, VTE_CNT_MECNT3); 904 CSR_READ_2(sc, VTE_CNT_TX_DONE); 905 CSR_READ_2(sc, VTE_CNT_MECNT4); 906 CSR_READ_2(sc, VTE_CNT_PAUSE); 907 } 908 909 static void 910 vte_stats_update(struct vte_softc *sc) 911 { 912 struct vte_hw_stats *stat; 913 struct ifnet *ifp = &sc->vte_if; 914 uint16_t value; 915 916 stat = &sc->vte_stats; 917 918 CSR_READ_2(sc, VTE_MECISR); 919 /* RX stats. */ 920 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 921 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 922 stat->rx_bcast_frames += (value >> 8); 923 stat->rx_mcast_frames += (value & 0xFF); 924 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 925 stat->rx_runts += (value >> 8); 926 stat->rx_crcerrs += (value & 0xFF); 927 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 928 stat->rx_long_frames += (value & 0xFF); 929 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 930 stat->rx_fifo_full += (value >> 8); 931 stat->rx_desc_unavail += (value & 0xFF); 932 933 /* TX stats. */ 934 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 935 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 936 stat->tx_underruns += (value >> 8); 937 stat->tx_late_colls += (value & 0xFF); 938 939 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 940 stat->tx_pause_frames += (value >> 8); 941 stat->rx_pause_frames += (value & 0xFF); 942 943 /* Update ifp counters. */ 944 ifp->if_opackets = stat->tx_frames; 945 ifp->if_oerrors = stat->tx_late_colls + stat->tx_underruns; 946 ifp->if_ipackets = stat->rx_frames; 947 ifp->if_ierrors = stat->rx_crcerrs + stat->rx_runts + 948 stat->rx_long_frames + stat->rx_fifo_full; 949 } 950 951 static int 952 vte_intr(void *arg) 953 { 954 struct vte_softc *sc = (struct vte_softc *)arg; 955 struct ifnet *ifp = &sc->vte_if; 956 uint16_t status; 957 int n; 958 959 /* Reading VTE_MISR acknowledges interrupts. */ 960 status = CSR_READ_2(sc, VTE_MISR); 961 DPRINTF(("vte_intr status 0x%x\n", status)); 962 if ((status & VTE_INTRS) == 0) { 963 /* Not ours. */ 964 return 0; 965 } 966 967 /* Disable interrupts. */ 968 CSR_WRITE_2(sc, VTE_MIER, 0); 969 for (n = 8; (status & VTE_INTRS) != 0;) { 970 if ((ifp->if_flags & IFF_RUNNING) == 0) 971 break; 972 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 973 MISR_RX_FIFO_FULL)) != 0) 974 vte_rxeof(sc); 975 if ((status & MISR_TX_DONE) != 0) 976 vte_txeof(sc); 977 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 978 vte_stats_update(sc); 979 if_schedule_deferred_start(ifp); 980 if (--n > 0) 981 status = CSR_READ_2(sc, VTE_MISR); 982 else 983 break; 984 } 985 986 if ((ifp->if_flags & IFF_RUNNING) != 0) { 987 /* Re-enable interrupts. */ 988 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 989 } 990 return 1; 991 } 992 993 static void 994 vte_txeof(struct vte_softc *sc) 995 { 996 struct ifnet *ifp; 997 struct vte_txdesc *txd; 998 uint16_t status; 999 int cons, prog; 1000 1001 ifp = &sc->vte_if; 1002 1003 if (sc->vte_cdata.vte_tx_cnt == 0) 1004 return; 1005 bus_dmamap_sync(sc->vte_dmatag, 1006 sc->vte_cdata.vte_tx_ring_map, 0, 1007 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1008 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1009 cons = sc->vte_cdata.vte_tx_cons; 1010 /* 1011 * Go through our TX list and free mbufs for those 1012 * frames which have been transmitted. 1013 */ 1014 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1015 txd = &sc->vte_cdata.vte_txdesc[cons]; 1016 status = le16toh(txd->tx_desc->dtst); 1017 if ((status & VTE_DTST_TX_OWN) != 0) 1018 break; 1019 if ((status & VTE_DTST_TX_OK) != 0) 1020 ifp->if_collisions += (status & 0xf); 1021 sc->vte_cdata.vte_tx_cnt--; 1022 /* Reclaim transmitted mbufs. */ 1023 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1024 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1025 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1026 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1027 m_freem(txd->tx_m); 1028 txd->tx_flags &= ~VTE_TXMBUF; 1029 txd->tx_m = NULL; 1030 prog++; 1031 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1032 } 1033 1034 if (prog > 0) { 1035 ifp->if_flags &= ~IFF_OACTIVE; 1036 sc->vte_cdata.vte_tx_cons = cons; 1037 /* 1038 * Unarm watchdog timer only when there is no pending 1039 * frames in TX queue. 1040 */ 1041 if (sc->vte_cdata.vte_tx_cnt == 0) 1042 sc->vte_watchdog_timer = 0; 1043 } 1044 } 1045 1046 static int 1047 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1048 { 1049 struct mbuf *m; 1050 bus_dmamap_t map; 1051 1052 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1053 if (m == NULL) 1054 return (ENOBUFS); 1055 m->m_len = m->m_pkthdr.len = MCLBYTES; 1056 m_adj(m, sizeof(uint32_t)); 1057 1058 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1059 sc->vte_cdata.vte_rx_sparemap, m, BUS_DMA_NOWAIT) != 0) { 1060 m_freem(m); 1061 return (ENOBUFS); 1062 } 1063 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1064 1065 if (rxd->rx_m != NULL) { 1066 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1067 0, rxd->rx_dmamap->dm_mapsize, 1068 BUS_DMASYNC_POSTREAD); 1069 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1070 } 1071 map = rxd->rx_dmamap; 1072 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1073 sc->vte_cdata.vte_rx_sparemap = map; 1074 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1075 0, rxd->rx_dmamap->dm_mapsize, 1076 BUS_DMASYNC_PREREAD); 1077 rxd->rx_m = m; 1078 rxd->rx_desc->drbp = 1079 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1080 rxd->rx_desc->drlen = htole16( 1081 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1082 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, 1083 (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, 1084 rxd->rx_dmamap->dm_segs[0].ds_len)); 1085 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1086 1087 return (0); 1088 } 1089 1090 static void 1091 vte_rxeof(struct vte_softc *sc) 1092 { 1093 struct ifnet *ifp; 1094 struct vte_rxdesc *rxd; 1095 struct mbuf *m; 1096 uint16_t status, total_len; 1097 int cons, prog; 1098 1099 bus_dmamap_sync(sc->vte_dmatag, 1100 sc->vte_cdata.vte_rx_ring_map, 0, 1101 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1102 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1103 cons = sc->vte_cdata.vte_rx_cons; 1104 ifp = &sc->vte_if; 1105 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1106 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1107 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1108 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1109 status = le16toh(rxd->rx_desc->drst); 1110 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", 1111 cons, rxd, rxd->rx_m, status, 1112 VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1113 if ((status & VTE_DRST_RX_OWN) != 0) 1114 break; 1115 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1116 m = rxd->rx_m; 1117 if ((status & VTE_DRST_RX_OK) == 0) { 1118 /* Discard errored frame. */ 1119 rxd->rx_desc->drlen = 1120 htole16(MCLBYTES - sizeof(uint32_t)); 1121 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1122 continue; 1123 } 1124 if (vte_newbuf(sc, rxd) != 0) { 1125 DPRINTF(("vte_rxeof newbuf failed\n")); 1126 ifp->if_ierrors++; 1127 rxd->rx_desc->drlen = 1128 htole16(MCLBYTES - sizeof(uint32_t)); 1129 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1130 continue; 1131 } 1132 1133 /* 1134 * It seems there is no way to strip FCS bytes. 1135 */ 1136 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1137 m_set_rcvif(m, ifp); 1138 if_percpuq_enqueue(ifp->if_percpuq, m); 1139 } 1140 1141 if (prog > 0) { 1142 /* Update the consumer index. */ 1143 sc->vte_cdata.vte_rx_cons = cons; 1144 /* 1145 * Sync updated RX descriptors such that controller see 1146 * modified RX buffer addresses. 1147 */ 1148 bus_dmamap_sync(sc->vte_dmatag, 1149 sc->vte_cdata.vte_rx_ring_map, 0, 1150 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1151 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1152 #ifdef notyet 1153 /* 1154 * Update residue counter. Controller does not 1155 * keep track of number of available RX descriptors 1156 * such that driver should have to update VTE_MRDCR 1157 * to make controller know how many free RX 1158 * descriptors were added to controller. This is 1159 * a similar mechanism used in VIA velocity 1160 * controllers and it indicates controller just 1161 * polls OWN bit of current RX descriptor pointer. 1162 * A couple of severe issues were seen on sample 1163 * board where the controller continuously emits TX 1164 * pause frames once RX pause threshold crossed. 1165 * Once triggered it never recovered form that 1166 * state, I couldn't find a way to make it back to 1167 * work at least. This issue effectively 1168 * disconnected the system from network. Also, the 1169 * controller used 00:00:00:00:00:00 as source 1170 * station address of TX pause frame. Probably this 1171 * is one of reason why vendor recommends not to 1172 * enable flow control on R6040 controller. 1173 */ 1174 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1175 (((VTE_RX_RING_CNT * 2) / 10) << 1176 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1177 #endif 1178 rnd_add_uint32(&sc->rnd_source, prog); 1179 } 1180 } 1181 1182 static void 1183 vte_tick(void *arg) 1184 { 1185 struct vte_softc *sc; 1186 int s = splnet(); 1187 1188 sc = (struct vte_softc *)arg; 1189 1190 mii_tick(&sc->vte_mii); 1191 vte_stats_update(sc); 1192 vte_txeof(sc); 1193 vte_ifwatchdog(&sc->vte_if); 1194 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1195 splx(s); 1196 } 1197 1198 static void 1199 vte_reset(struct vte_softc *sc) 1200 { 1201 uint16_t mcr; 1202 int i; 1203 1204 mcr = CSR_READ_2(sc, VTE_MCR1); 1205 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1206 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1207 DELAY(10); 1208 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1209 break; 1210 } 1211 if (i == 0) 1212 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1213 /* 1214 * Follow the guide of vendor recommended way to reset MAC. 1215 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1216 * not reliable so manually reset internal state machine. 1217 */ 1218 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1219 CSR_WRITE_2(sc, VTE_MACSM, 0); 1220 DELAY(5000); 1221 } 1222 1223 1224 static int 1225 vte_init(struct ifnet *ifp) 1226 { 1227 struct vte_softc *sc = ifp->if_softc; 1228 bus_addr_t paddr; 1229 uint8_t eaddr[ETHER_ADDR_LEN]; 1230 int s, error; 1231 1232 s = splnet(); 1233 /* 1234 * Cancel any pending I/O. 1235 */ 1236 vte_stop(ifp, 1); 1237 /* 1238 * Reset the chip to a known state. 1239 */ 1240 vte_reset(sc); 1241 1242 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1243 splx(s); 1244 return 0; 1245 } 1246 1247 /* Initialize RX descriptors. */ 1248 if (vte_init_rx_ring(sc) != 0) { 1249 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1250 vte_stop(ifp, 1); 1251 splx(s); 1252 return ENOMEM; 1253 } 1254 if (vte_init_tx_ring(sc) != 0) { 1255 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1256 vte_stop(ifp, 1); 1257 splx(s); 1258 return ENOMEM; 1259 } 1260 1261 /* 1262 * Reprogram the station address. Controller supports up 1263 * to 4 different station addresses so driver programs the 1264 * first station address as its own ethernet address and 1265 * configure the remaining three addresses as perfect 1266 * multicast addresses. 1267 */ 1268 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1269 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1270 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1271 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1272 1273 /* Set TX descriptor base addresses. */ 1274 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1275 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1276 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1277 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1278 1279 /* Set RX descriptor base addresses. */ 1280 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1281 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1282 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1283 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1284 /* 1285 * Initialize RX descriptor residue counter and set RX 1286 * pause threshold to 20% of available RX descriptors. 1287 * See comments on vte_rxeof() for details on flow control 1288 * issues. 1289 */ 1290 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1291 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1292 1293 /* 1294 * Always use maximum frame size that controller can 1295 * support. Otherwise received frames that has longer 1296 * frame length than vte(4) MTU would be silently dropped 1297 * in controller. This would break path-MTU discovery as 1298 * sender wouldn't get any responses from receiver. The 1299 * RX buffer size should be multiple of 4. 1300 * Note, jumbo frames are silently ignored by controller 1301 * and even MAC counters do not detect them. 1302 */ 1303 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1304 1305 /* Configure FIFO. */ 1306 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1307 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1308 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1309 1310 /* 1311 * Configure TX/RX MACs. Actual resolved duplex and flow 1312 * control configuration is done after detecting a valid 1313 * link. Note, we don't generate early interrupt here 1314 * as well since FreeBSD does not have interrupt latency 1315 * problems like Windows. 1316 */ 1317 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1318 /* 1319 * We manually keep track of PHY status changes to 1320 * configure resolved duplex and flow control since only 1321 * duplex configuration can be automatically reflected to 1322 * MCR0. 1323 */ 1324 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1325 MCR1_EXCESS_COL_RETRY_16); 1326 1327 /* Initialize RX filter. */ 1328 vte_rxfilter(sc); 1329 1330 /* Disable TX/RX interrupt moderation control. */ 1331 CSR_WRITE_2(sc, VTE_MRICR, 0); 1332 CSR_WRITE_2(sc, VTE_MTICR, 0); 1333 1334 /* Enable MAC event counter interrupts. */ 1335 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1336 /* Clear MAC statistics. */ 1337 vte_stats_clear(sc); 1338 1339 /* Acknowledge all pending interrupts and clear it. */ 1340 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1341 CSR_WRITE_2(sc, VTE_MISR, 0); 1342 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1343 CSR_READ_2(sc, VTE_MISR))); 1344 1345 sc->vte_flags &= ~VTE_FLAG_LINK; 1346 ifp->if_flags |= IFF_RUNNING; 1347 ifp->if_flags &= ~IFF_OACTIVE; 1348 1349 /* calling mii_mediachg will call back vte_start_mac() */ 1350 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1351 error = 0; 1352 else if (error != 0) { 1353 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1354 splx(s); 1355 return error; 1356 } 1357 1358 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1359 1360 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1361 CSR_READ_2(sc, VTE_MISR))); 1362 splx(s); 1363 return 0; 1364 } 1365 1366 static void 1367 vte_stop(struct ifnet *ifp, int disable) 1368 { 1369 struct vte_softc *sc = ifp->if_softc; 1370 struct vte_txdesc *txd; 1371 struct vte_rxdesc *rxd; 1372 int i; 1373 1374 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1375 if ((ifp->if_flags & IFF_RUNNING) == 0) 1376 return; 1377 /* 1378 * Mark the interface down and cancel the watchdog timer. 1379 */ 1380 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1381 sc->vte_flags &= ~VTE_FLAG_LINK; 1382 callout_stop(&sc->vte_tick_ch); 1383 sc->vte_watchdog_timer = 0; 1384 vte_stats_update(sc); 1385 /* Disable interrupts. */ 1386 CSR_WRITE_2(sc, VTE_MIER, 0); 1387 CSR_WRITE_2(sc, VTE_MECIER, 0); 1388 /* Stop RX/TX MACs. */ 1389 vte_stop_mac(sc); 1390 /* Clear interrupts. */ 1391 CSR_READ_2(sc, VTE_MISR); 1392 /* 1393 * Free TX/RX mbufs still in the queues. 1394 */ 1395 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1396 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1397 if (rxd->rx_m != NULL) { 1398 bus_dmamap_sync(sc->vte_dmatag, 1399 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1400 BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_unload(sc->vte_dmatag, 1402 rxd->rx_dmamap); 1403 m_freem(rxd->rx_m); 1404 rxd->rx_m = NULL; 1405 } 1406 } 1407 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1408 txd = &sc->vte_cdata.vte_txdesc[i]; 1409 if (txd->tx_m != NULL) { 1410 bus_dmamap_sync(sc->vte_dmatag, 1411 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1412 BUS_DMASYNC_POSTWRITE); 1413 bus_dmamap_unload(sc->vte_dmatag, 1414 txd->tx_dmamap); 1415 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1416 m_freem(txd->tx_m); 1417 txd->tx_m = NULL; 1418 txd->tx_flags &= ~VTE_TXMBUF; 1419 } 1420 } 1421 /* Free TX mbuf pools used for deep copy. */ 1422 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1423 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1424 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1425 sc->vte_cdata.vte_txmbufs[i] = NULL; 1426 } 1427 } 1428 } 1429 1430 static void 1431 vte_start_mac(struct vte_softc *sc) 1432 { 1433 struct ifnet *ifp = &sc->vte_if; 1434 uint16_t mcr; 1435 int i; 1436 1437 /* Enable RX/TX MACs. */ 1438 mcr = CSR_READ_2(sc, VTE_MCR0); 1439 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1440 (MCR0_RX_ENB | MCR0_TX_ENB) && 1441 (ifp->if_flags & IFF_RUNNING) != 0) { 1442 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1443 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1444 for (i = VTE_TIMEOUT; i > 0; i--) { 1445 mcr = CSR_READ_2(sc, VTE_MCR0); 1446 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1447 (MCR0_RX_ENB | MCR0_TX_ENB)) 1448 break; 1449 DELAY(10); 1450 } 1451 if (i == 0) 1452 aprint_error_dev(sc->vte_dev, 1453 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1454 } 1455 vte_rxfilter(sc); 1456 } 1457 1458 static void 1459 vte_stop_mac(struct vte_softc *sc) 1460 { 1461 uint16_t mcr; 1462 int i; 1463 1464 /* Disable RX/TX MACs. */ 1465 mcr = CSR_READ_2(sc, VTE_MCR0); 1466 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1467 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1468 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1469 for (i = VTE_TIMEOUT; i > 0; i--) { 1470 mcr = CSR_READ_2(sc, VTE_MCR0); 1471 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1472 break; 1473 DELAY(10); 1474 } 1475 if (i == 0) 1476 aprint_error_dev(sc->vte_dev, 1477 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1478 } 1479 } 1480 1481 static int 1482 vte_init_tx_ring(struct vte_softc *sc) 1483 { 1484 struct vte_tx_desc *desc; 1485 struct vte_txdesc *txd; 1486 bus_addr_t addr; 1487 int i; 1488 1489 sc->vte_cdata.vte_tx_prod = 0; 1490 sc->vte_cdata.vte_tx_cons = 0; 1491 sc->vte_cdata.vte_tx_cnt = 0; 1492 1493 /* Pre-allocate TX mbufs for deep copy. */ 1494 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1495 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1496 MT_DATA, M_PKTHDR); 1497 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1498 return (ENOBUFS); 1499 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1500 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1501 } 1502 desc = sc->vte_cdata.vte_tx_ring; 1503 bzero(desc, VTE_TX_RING_SZ); 1504 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1505 txd = &sc->vte_cdata.vte_txdesc[i]; 1506 txd->tx_m = NULL; 1507 if (i != VTE_TX_RING_CNT - 1) 1508 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1509 sizeof(struct vte_tx_desc) * (i + 1); 1510 else 1511 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1512 sizeof(struct vte_tx_desc) * 0; 1513 desc = &sc->vte_cdata.vte_tx_ring[i]; 1514 desc->dtnp = htole32(addr); 1515 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1516 txd->tx_desc = desc; 1517 } 1518 1519 bus_dmamap_sync(sc->vte_dmatag, 1520 sc->vte_cdata.vte_tx_ring_map, 0, 1521 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1522 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1523 return (0); 1524 } 1525 1526 static int 1527 vte_init_rx_ring(struct vte_softc *sc) 1528 { 1529 struct vte_rx_desc *desc; 1530 struct vte_rxdesc *rxd; 1531 bus_addr_t addr; 1532 int i; 1533 1534 sc->vte_cdata.vte_rx_cons = 0; 1535 desc = sc->vte_cdata.vte_rx_ring; 1536 bzero(desc, VTE_RX_RING_SZ); 1537 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1538 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1539 rxd->rx_m = NULL; 1540 if (i != VTE_RX_RING_CNT - 1) 1541 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1542 + sizeof(struct vte_rx_desc) * (i + 1); 1543 else 1544 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1545 + sizeof(struct vte_rx_desc) * 0; 1546 desc = &sc->vte_cdata.vte_rx_ring[i]; 1547 desc->drnp = htole32(addr); 1548 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1549 rxd->rx_desc = desc; 1550 if (vte_newbuf(sc, rxd) != 0) 1551 return (ENOBUFS); 1552 } 1553 1554 bus_dmamap_sync(sc->vte_dmatag, 1555 sc->vte_cdata.vte_rx_ring_map, 0, 1556 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1558 1559 return (0); 1560 } 1561 1562 static void 1563 vte_rxfilter(struct vte_softc *sc) 1564 { 1565 struct ether_multistep step; 1566 struct ether_multi *enm; 1567 struct ifnet *ifp; 1568 uint8_t *eaddr; 1569 uint32_t crc; 1570 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1571 uint16_t mchash[4], mcr; 1572 int i, nperf; 1573 1574 ifp = &sc->vte_if; 1575 1576 DPRINTF(("vte_rxfilter\n")); 1577 memset(mchash, 0, sizeof(mchash)); 1578 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1579 rxfilt_perf[i][0] = 0xFFFF; 1580 rxfilt_perf[i][1] = 0xFFFF; 1581 rxfilt_perf[i][2] = 0xFFFF; 1582 } 1583 1584 mcr = CSR_READ_2(sc, VTE_MCR0); 1585 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1586 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST); 1587 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1588 mcr |= MCR0_BROADCAST_DIS; 1589 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1590 if ((ifp->if_flags & IFF_PROMISC) != 0) 1591 mcr |= MCR0_PROMISC; 1592 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1593 mcr |= MCR0_MULTICAST; 1594 mchash[0] = 0xFFFF; 1595 mchash[1] = 0xFFFF; 1596 mchash[2] = 0xFFFF; 1597 mchash[3] = 0xFFFF; 1598 goto chipit; 1599 } 1600 1601 ETHER_FIRST_MULTI(step, &sc->vte_ec, enm); 1602 nperf = 0; 1603 while (enm != NULL) { 1604 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1605 sc->vte_if.if_flags |= IFF_ALLMULTI; 1606 mcr |= MCR0_MULTICAST; 1607 mchash[0] = 0xFFFF; 1608 mchash[1] = 0xFFFF; 1609 mchash[2] = 0xFFFF; 1610 mchash[3] = 0xFFFF; 1611 goto chipit; 1612 } 1613 /* 1614 * Program the first 3 multicast groups into 1615 * the perfect filter. For all others, use the 1616 * hash table. 1617 */ 1618 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1619 eaddr = enm->enm_addrlo; 1620 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1621 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1622 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1623 nperf++; 1624 } else { 1625 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1626 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1627 } 1628 ETHER_NEXT_MULTI(step, enm); 1629 } 1630 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1631 mchash[3] != 0) 1632 mcr |= MCR0_MULTICAST; 1633 1634 chipit: 1635 /* Program multicast hash table. */ 1636 DPRINTF(("chipit write multicast\n")); 1637 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1638 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1639 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1640 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1641 /* Program perfect filter table. */ 1642 DPRINTF(("chipit write perfect filter\n")); 1643 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1644 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1645 rxfilt_perf[i][0]); 1646 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1647 rxfilt_perf[i][1]); 1648 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1649 rxfilt_perf[i][2]); 1650 } 1651 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1652 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1653 DPRINTF(("chipit read mcro\n")); 1654 CSR_READ_2(sc, VTE_MCR0); 1655 DPRINTF(("chipit done\n")); 1656 } 1657 1658 /* 1659 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1660 * set up in vte_pci_attach() 1661 */ 1662 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1663 { 1664 int rc; 1665 const struct sysctlnode *node; 1666 1667 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1668 0, CTLTYPE_NODE, "vte", 1669 SYSCTL_DESCR("vte interface controls"), 1670 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1671 goto err; 1672 } 1673 1674 vte_root_num = node->sysctl_num; 1675 return; 1676 1677 err: 1678 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1679 } 1680 1681 static int 1682 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1683 { 1684 int error, t; 1685 struct sysctlnode node; 1686 struct vte_softc *sc; 1687 1688 node = *rnode; 1689 sc = node.sysctl_data; 1690 t = sc->vte_int_rx_mod; 1691 node.sysctl_data = &t; 1692 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1693 if (error || newp == NULL) 1694 return error; 1695 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1696 return EINVAL; 1697 1698 sc->vte_int_rx_mod = t; 1699 vte_miibus_statchg(&sc->vte_if); 1700 return 0; 1701 } 1702 1703 static int 1704 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1705 { 1706 int error, t; 1707 struct sysctlnode node; 1708 struct vte_softc *sc; 1709 1710 node = *rnode; 1711 sc = node.sysctl_data; 1712 t = sc->vte_int_tx_mod; 1713 node.sysctl_data = &t; 1714 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1715 if (error || newp == NULL) 1716 return error; 1717 1718 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1719 return EINVAL; 1720 sc->vte_int_tx_mod = t; 1721 vte_miibus_statchg(&sc->vte_if); 1722 return 0; 1723 } 1724
Indexes created Thu Oct 02 01:09:59 GMT 2025