if_vte.c revision 1.22
1 /* $NetBSD: if_vte.c,v 1.22 2019/01/22 03:42:27 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2010, Pyun YongHyeon <yongari (at) FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 54 55 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.22 2019/01/22 03:42:27 msaitoh Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/mbuf.h> 63 #include <sys/protosw.h> 64 #include <sys/socket.h> 65 #include <sys/ioctl.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_dl.h> 76 #include <net/route.h> 77 #include <net/netisr.h> 78 #include <net/bpf.h> 79 80 #include <sys/rndsource.h> 81 82 #include "opt_inet.h" 83 #include <net/if_ether.h> 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/in_systm.h> 87 #include <netinet/in_var.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_inarp.h> 90 #endif 91 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/pci/if_vtereg.h> 103 #include <dev/pci/if_vtevar.h> 104 105 static int vte_match(device_t, cfdata_t, void *); 106 static void vte_attach(device_t, device_t, void *); 107 static int vte_detach(device_t, int); 108 static int vte_dma_alloc(struct vte_softc *); 109 static void vte_dma_free(struct vte_softc *); 110 static struct vte_txdesc * 111 vte_encap(struct vte_softc *, struct mbuf **); 112 static void vte_get_macaddr(struct vte_softc *); 113 static int vte_init(struct ifnet *); 114 static int vte_init_rx_ring(struct vte_softc *); 115 static int vte_init_tx_ring(struct vte_softc *); 116 static int vte_intr(void *); 117 static int vte_ifioctl(struct ifnet *, u_long, void *); 118 static void vte_mac_config(struct vte_softc *); 119 static int vte_miibus_readreg(device_t, int, int, uint16_t *); 120 static void vte_miibus_statchg(struct ifnet *); 121 static int vte_miibus_writereg(device_t, int, int, uint16_t); 122 static int vte_mediachange(struct ifnet *); 123 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 124 static void vte_reset(struct vte_softc *); 125 static void vte_rxeof(struct vte_softc *); 126 static void vte_rxfilter(struct vte_softc *); 127 static bool vte_shutdown(device_t, int); 128 static bool vte_suspend(device_t, const pmf_qual_t *); 129 static bool vte_resume(device_t, const pmf_qual_t *); 130 static void vte_ifstart(struct ifnet *); 131 static void vte_start_mac(struct vte_softc *); 132 static void vte_stats_clear(struct vte_softc *); 133 static void vte_stats_update(struct vte_softc *); 134 static void vte_stop(struct ifnet *, int); 135 static void vte_stop_mac(struct vte_softc *); 136 static void vte_tick(void *); 137 static void vte_txeof(struct vte_softc *); 138 static void vte_ifwatchdog(struct ifnet *); 139 140 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 141 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 142 static int vte_root_num; 143 144 #define DPRINTF(a) 145 146 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 147 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 148 149 150 static int 151 vte_match(device_t parent, cfdata_t cf, void *aux) 152 { 153 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 154 155 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 156 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 157 return 1; 158 159 return 0; 160 } 161 162 static void 163 vte_attach(device_t parent, device_t self, void *aux) 164 { 165 struct vte_softc *sc = device_private(self); 166 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 167 struct ifnet * const ifp = &sc->vte_if; 168 int h_valid; 169 pcireg_t reg, csr; 170 pci_intr_handle_t intrhandle; 171 const char *intrstr; 172 int error; 173 const struct sysctlnode *node; 174 int vte_nodenum; 175 char intrbuf[PCI_INTRSTR_LEN]; 176 177 sc->vte_dev = self; 178 179 callout_init(&sc->vte_tick_ch, 0); 180 181 /* Map the device. */ 182 h_valid = 0; 183 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 184 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 185 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 186 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 187 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 188 } 189 if (h_valid == 0) { 190 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 191 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 192 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 193 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 194 &sc->vte_bushandle, NULL, NULL) == 0); 195 } 196 } 197 if (h_valid == 0) { 198 aprint_error_dev(self, "unable to map device registers\n"); 199 return; 200 } 201 sc->vte_dmatag = pa->pa_dmat; 202 /* Enable the device. */ 203 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 204 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 205 csr | PCI_COMMAND_MASTER_ENABLE); 206 207 pci_aprint_devinfo(pa, NULL); 208 209 /* Reset the ethernet controller. */ 210 vte_reset(sc); 211 212 if ((error = vte_dma_alloc(sc)) != 0) 213 return; 214 215 /* Load station address. */ 216 vte_get_macaddr(sc); 217 218 aprint_normal_dev(self, "Ethernet address %s\n", 219 ether_sprintf(sc->vte_eaddr)); 220 221 /* Map and establish interrupts */ 222 if (pci_intr_map(pa, &intrhandle)) { 223 aprint_error_dev(self, "couldn't map interrupt\n"); 224 return; 225 } 226 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 227 sizeof(intrbuf)); 228 sc->vte_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 229 vte_intr, sc, device_xname(self)); 230 if (sc->vte_ih == NULL) { 231 aprint_error_dev(self, "couldn't establish interrupt"); 232 if (intrstr != NULL) 233 aprint_error(" at %s", intrstr); 234 aprint_error("\n"); 235 return; 236 } 237 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 238 239 sc->vte_if.if_softc = sc; 240 sc->vte_mii.mii_ifp = ifp; 241 sc->vte_mii.mii_readreg = vte_miibus_readreg; 242 sc->vte_mii.mii_writereg = vte_miibus_writereg; 243 sc->vte_mii.mii_statchg = vte_miibus_statchg; 244 sc->vte_ec.ec_mii = &sc->vte_mii; 245 ifmedia_init(&sc->vte_mii.mii_media, IFM_IMASK, vte_mediachange, 246 ether_mediastatus); 247 mii_attach(self, &sc->vte_mii, 0xffffffff, MII_PHY_ANY, 248 MII_OFFSET_ANY, 0); 249 if (LIST_FIRST(&sc->vte_mii.mii_phys) == NULL) { 250 ifmedia_add(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 251 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE); 252 } else 253 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_AUTO); 254 255 /* 256 * We can support 802.1Q VLAN-sized frames. 257 */ 258 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 259 260 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 261 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 262 ifp->if_ioctl = vte_ifioctl; 263 ifp->if_start = vte_ifstart; 264 ifp->if_watchdog = vte_ifwatchdog; 265 ifp->if_init = vte_init; 266 ifp->if_stop = vte_stop; 267 ifp->if_timer = 0; 268 IFQ_SET_READY(&ifp->if_snd); 269 if_attach(ifp); 270 if_deferred_start_init(ifp, NULL); 271 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 272 273 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 274 pmf_class_network_register(self, ifp); 275 else 276 aprint_error_dev(self, "couldn't establish power handler\n"); 277 278 rnd_attach_source(&sc->rnd_source, device_xname(self), 279 RND_TYPE_NET, RND_FLAG_DEFAULT); 280 281 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 282 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 283 SYSCTL_DESCR("vte per-controller controls"), 284 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 285 CTL_EOL) != 0) { 286 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 287 return; 288 } 289 vte_nodenum = node->sysctl_num; 290 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 291 CTLFLAG_READWRITE, 292 CTLTYPE_INT, "int_rxct", 293 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 294 vte_sysctl_intrxct, 0, (void *)sc, 295 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 296 CTL_EOL) != 0) { 297 aprint_normal_dev(sc->vte_dev, 298 "couldn't create int_rxct sysctl node\n"); 299 } 300 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 301 CTLFLAG_READWRITE, 302 CTLTYPE_INT, "int_txct", 303 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 304 vte_sysctl_inttxct, 0, (void *)sc, 305 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 306 CTL_EOL) != 0) { 307 aprint_normal_dev(sc->vte_dev, 308 "couldn't create int_txct sysctl node\n"); 309 } 310 } 311 312 static int 313 vte_detach(device_t dev, int flags __unused) 314 { 315 struct vte_softc *sc = device_private(dev); 316 struct ifnet *ifp = &sc->vte_if; 317 int s; 318 319 s = splnet(); 320 /* Stop the interface. Callouts are stopped in it. */ 321 vte_stop(ifp, 1); 322 splx(s); 323 324 pmf_device_deregister(dev); 325 326 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 327 ifmedia_delete_instance(&sc->vte_mii.mii_media, IFM_INST_ANY); 328 329 ether_ifdetach(ifp); 330 if_detach(ifp); 331 332 vte_dma_free(sc); 333 334 return (0); 335 } 336 337 static int 338 vte_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 339 { 340 struct vte_softc *sc = device_private(dev); 341 int i; 342 343 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 344 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 345 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 346 DELAY(5); 347 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 348 break; 349 } 350 351 if (i == 0) { 352 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 353 return ETIMEDOUT; 354 } 355 356 *val = CSR_READ_2(sc, VTE_MMRD); 357 return 0; 358 } 359 360 static int 361 vte_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 362 { 363 struct vte_softc *sc = device_private(dev); 364 int i; 365 366 CSR_WRITE_2(sc, VTE_MMWD, val); 367 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 368 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 369 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 370 DELAY(5); 371 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 372 break; 373 } 374 375 if (i == 0) { 376 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 377 return ETIMEDOUT; 378 } 379 380 return 0; 381 } 382 383 static void 384 vte_miibus_statchg(struct ifnet *ifp) 385 { 386 struct vte_softc *sc = ifp->if_softc; 387 uint16_t val; 388 389 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 390 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 391 392 sc->vte_flags &= ~VTE_FLAG_LINK; 393 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 394 (IFM_ACTIVE | IFM_AVALID)) { 395 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 396 case IFM_10_T: 397 case IFM_100_TX: 398 sc->vte_flags |= VTE_FLAG_LINK; 399 break; 400 default: 401 break; 402 } 403 } 404 405 /* Stop RX/TX MACs. */ 406 vte_stop_mac(sc); 407 /* Program MACs with resolved duplex and flow control. */ 408 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 409 /* 410 * Timer waiting time : (63 + TIMER * 64) MII clock. 411 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 412 */ 413 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 414 val = 18 << VTE_IM_TIMER_SHIFT; 415 else 416 val = 1 << VTE_IM_TIMER_SHIFT; 417 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 418 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 419 CSR_WRITE_2(sc, VTE_MRICR, val); 420 421 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 422 val = 18 << VTE_IM_TIMER_SHIFT; 423 else 424 val = 1 << VTE_IM_TIMER_SHIFT; 425 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 426 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 427 CSR_WRITE_2(sc, VTE_MTICR, val); 428 429 vte_mac_config(sc); 430 vte_start_mac(sc); 431 DPRINTF(("vte_miibus_statchg: link\n")); 432 } 433 } 434 435 static void 436 vte_get_macaddr(struct vte_softc *sc) 437 { 438 uint16_t mid; 439 440 /* 441 * It seems there is no way to reload station address and 442 * it is supposed to be set by BIOS. 443 */ 444 mid = CSR_READ_2(sc, VTE_MID0L); 445 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 446 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 447 mid = CSR_READ_2(sc, VTE_MID0M); 448 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 449 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 450 mid = CSR_READ_2(sc, VTE_MID0H); 451 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 452 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 453 } 454 455 456 static int 457 vte_dma_alloc(struct vte_softc *sc) 458 { 459 struct vte_txdesc *txd; 460 struct vte_rxdesc *rxd; 461 int error, i, rseg; 462 463 /* create DMA map for TX ring */ 464 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 465 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 466 &sc->vte_cdata.vte_tx_ring_map); 467 if (error) { 468 aprint_error_dev(sc->vte_dev, 469 "could not create dma map for TX ring (%d)\n", 470 error); 471 goto fail; 472 } 473 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 474 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 475 VTE_TX_RING_ALIGN, 0, 476 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 477 BUS_DMA_NOWAIT); 478 if (error != 0) { 479 aprint_error_dev(sc->vte_dev, 480 "could not allocate DMA'able memory for TX ring (%d).\n", 481 error); 482 goto fail; 483 } 484 KASSERT(rseg == 1); 485 error = bus_dmamem_map(sc->vte_dmatag, 486 sc->vte_cdata.vte_tx_ring_seg, 1, 487 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 488 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 489 if (error != 0) { 490 aprint_error_dev(sc->vte_dev, 491 "could not map DMA'able memory for TX ring (%d).\n", 492 error); 493 goto fail; 494 } 495 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 496 error = bus_dmamap_load(sc->vte_dmatag, 497 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 498 VTE_TX_RING_SZ, NULL, 499 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 500 if (error != 0) { 501 aprint_error_dev(sc->vte_dev, 502 "could not load DMA'able memory for TX ring.\n"); 503 goto fail; 504 } 505 506 /* create DMA map for RX ring */ 507 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 508 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 509 &sc->vte_cdata.vte_rx_ring_map); 510 if (error) { 511 aprint_error_dev(sc->vte_dev, 512 "could not create dma map for RX ring (%d)\n", 513 error); 514 goto fail; 515 } 516 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 517 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 518 VTE_RX_RING_ALIGN, 0, 519 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 520 BUS_DMA_NOWAIT); 521 if (error != 0) { 522 aprint_error_dev(sc->vte_dev, 523 "could not allocate DMA'able memory for RX ring (%d).\n", 524 error); 525 goto fail; 526 } 527 KASSERT(rseg == 1); 528 error = bus_dmamem_map(sc->vte_dmatag, 529 sc->vte_cdata.vte_rx_ring_seg, 1, 530 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 531 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 532 if (error != 0) { 533 aprint_error_dev(sc->vte_dev, 534 "could not map DMA'able memory for RX ring (%d).\n", 535 error); 536 goto fail; 537 } 538 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 539 error = bus_dmamap_load(sc->vte_dmatag, 540 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 541 VTE_RX_RING_SZ, NULL, 542 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 543 if (error != 0) { 544 aprint_error_dev(sc->vte_dev, 545 "could not load DMA'able memory for RX ring (%d).\n", 546 error); 547 goto fail; 548 } 549 550 /* Create DMA maps for TX buffers. */ 551 for (i = 0; i < VTE_TX_RING_CNT; i++) { 552 txd = &sc->vte_cdata.vte_txdesc[i]; 553 txd->tx_m = NULL; 554 txd->tx_dmamap = NULL; 555 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 556 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 557 &txd->tx_dmamap); 558 if (error != 0) { 559 aprint_error_dev(sc->vte_dev, 560 "could not create TX DMA map %d (%d).\n", i, error); 561 goto fail; 562 } 563 } 564 /* Create DMA maps for RX buffers. */ 565 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 566 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 567 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 568 aprint_error_dev(sc->vte_dev, 569 "could not create spare RX dmamap (%d).\n", error); 570 goto fail; 571 } 572 for (i = 0; i < VTE_RX_RING_CNT; i++) { 573 rxd = &sc->vte_cdata.vte_rxdesc[i]; 574 rxd->rx_m = NULL; 575 rxd->rx_dmamap = NULL; 576 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 577 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 578 &rxd->rx_dmamap); 579 if (error != 0) { 580 aprint_error_dev(sc->vte_dev, 581 "could not create RX dmamap %d (%d).\n", i, error); 582 goto fail; 583 } 584 } 585 return 0; 586 587 fail: 588 vte_dma_free(sc); 589 return (error); 590 } 591 592 static void 593 vte_dma_free(struct vte_softc *sc) 594 { 595 struct vte_txdesc *txd; 596 struct vte_rxdesc *rxd; 597 int i; 598 599 /* TX buffers. */ 600 for (i = 0; i < VTE_TX_RING_CNT; i++) { 601 txd = &sc->vte_cdata.vte_txdesc[i]; 602 if (txd->tx_dmamap != NULL) { 603 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 604 txd->tx_dmamap = NULL; 605 } 606 } 607 /* RX buffers */ 608 for (i = 0; i < VTE_RX_RING_CNT; i++) { 609 rxd = &sc->vte_cdata.vte_rxdesc[i]; 610 if (rxd->rx_dmamap != NULL) { 611 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 612 rxd->rx_dmamap = NULL; 613 } 614 } 615 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 616 bus_dmamap_destroy(sc->vte_dmatag, 617 sc->vte_cdata.vte_rx_sparemap); 618 sc->vte_cdata.vte_rx_sparemap = NULL; 619 } 620 /* TX descriptor ring. */ 621 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 622 bus_dmamap_unload(sc->vte_dmatag, 623 sc->vte_cdata.vte_tx_ring_map); 624 bus_dmamap_destroy(sc->vte_dmatag, 625 sc->vte_cdata.vte_tx_ring_map); 626 } 627 if (sc->vte_cdata.vte_tx_ring != NULL) { 628 bus_dmamem_unmap(sc->vte_dmatag, 629 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 630 bus_dmamem_free(sc->vte_dmatag, 631 sc->vte_cdata.vte_tx_ring_seg, 1); 632 } 633 sc->vte_cdata.vte_tx_ring = NULL; 634 sc->vte_cdata.vte_tx_ring_map = NULL; 635 /* RX ring. */ 636 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 637 bus_dmamap_unload(sc->vte_dmatag, 638 sc->vte_cdata.vte_rx_ring_map); 639 bus_dmamap_destroy(sc->vte_dmatag, 640 sc->vte_cdata.vte_rx_ring_map); 641 } 642 if (sc->vte_cdata.vte_rx_ring != NULL) { 643 bus_dmamem_unmap(sc->vte_dmatag, 644 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 645 bus_dmamem_free(sc->vte_dmatag, 646 sc->vte_cdata.vte_rx_ring_seg, 1); 647 } 648 sc->vte_cdata.vte_rx_ring = NULL; 649 sc->vte_cdata.vte_rx_ring_map = NULL; 650 } 651 652 static bool 653 vte_shutdown(device_t dev, int howto) 654 { 655 656 return (vte_suspend(dev, NULL)); 657 } 658 659 static bool 660 vte_suspend(device_t dev, const pmf_qual_t *qual) 661 { 662 struct vte_softc *sc = device_private(dev); 663 struct ifnet *ifp = &sc->vte_if; 664 665 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 666 if ((ifp->if_flags & IFF_RUNNING) != 0) 667 vte_stop(ifp, 1); 668 return (0); 669 } 670 671 static bool 672 vte_resume(device_t dev, const pmf_qual_t *qual) 673 { 674 struct vte_softc *sc = device_private(dev); 675 struct ifnet *ifp; 676 677 ifp = &sc->vte_if; 678 if ((ifp->if_flags & IFF_UP) != 0) { 679 ifp->if_flags &= ~IFF_RUNNING; 680 vte_init(ifp); 681 } 682 683 return (0); 684 } 685 686 static struct vte_txdesc * 687 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 688 { 689 struct vte_txdesc *txd; 690 struct mbuf *m, *n; 691 int copy, error, padlen; 692 693 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 694 m = *m_head; 695 /* 696 * Controller doesn't auto-pad, so we have to make sure pad 697 * short frames out to the minimum frame length. 698 */ 699 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 700 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 701 else 702 padlen = 0; 703 704 /* 705 * Controller does not support multi-fragmented TX buffers. 706 * Controller spends most of its TX processing time in 707 * de-fragmenting TX buffers. Either faster CPU or more 708 * advanced controller DMA engine is required to speed up 709 * TX path processing. 710 * To mitigate the de-fragmenting issue, perform deep copy 711 * from fragmented mbuf chains to a pre-allocated mbuf 712 * cluster with extra cost of kernel memory. For frames 713 * that is composed of single TX buffer, the deep copy is 714 * bypassed. 715 */ 716 copy = 0; 717 if (m->m_next != NULL) 718 copy++; 719 if (padlen > 0 && (M_READONLY(m) || 720 padlen > M_TRAILINGSPACE(m))) 721 copy++; 722 if (copy != 0) { 723 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 724 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 725 n->m_pkthdr.len = m->m_pkthdr.len; 726 n->m_len = m->m_pkthdr.len; 727 m = n; 728 txd->tx_flags |= VTE_TXMBUF; 729 } 730 731 if (padlen > 0) { 732 /* Zero out the bytes in the pad area. */ 733 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 734 m->m_pkthdr.len += padlen; 735 m->m_len = m->m_pkthdr.len; 736 } 737 738 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 739 BUS_DMA_NOWAIT); 740 if (error != 0) { 741 txd->tx_flags &= ~VTE_TXMBUF; 742 return (NULL); 743 } 744 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 745 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 746 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 747 748 txd->tx_desc->dtlen = 749 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 750 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 751 sc->vte_cdata.vte_tx_cnt++; 752 /* Update producer index. */ 753 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 754 755 /* Finally hand over ownership to controller. */ 756 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 757 txd->tx_m = m; 758 759 return (txd); 760 } 761 762 static void 763 vte_ifstart(struct ifnet *ifp) 764 { 765 struct vte_softc *sc = ifp->if_softc; 766 struct vte_txdesc *txd; 767 struct mbuf *m_head, *m; 768 int enq; 769 770 ifp = &sc->vte_if; 771 772 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 773 774 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 775 IFF_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 776 return; 777 778 for (enq = 0; !IFQ_IS_EMPTY(&ifp->if_snd); ) { 779 /* Reserve one free TX descriptor. */ 780 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 781 ifp->if_flags |= IFF_OACTIVE; 782 break; 783 } 784 IFQ_POLL(&ifp->if_snd, m_head); 785 if (m_head == NULL) 786 break; 787 /* 788 * Pack the data into the transmit ring. If we 789 * don't have room, set the OACTIVE flag and wait 790 * for the NIC to drain the ring. 791 */ 792 DPRINTF(("vte_encap:")); 793 if ((txd = vte_encap(sc, &m_head)) == NULL) { 794 DPRINTF((" failed\n")); 795 break; 796 } 797 DPRINTF((" ok\n")); 798 IFQ_DEQUEUE(&ifp->if_snd, m); 799 KASSERT(m == m_head); 800 801 enq++; 802 /* 803 * If there's a BPF listener, bounce a copy of this frame 804 * to him. 805 */ 806 bpf_mtap(ifp, m_head, BPF_D_OUT); 807 /* Free consumed TX frame. */ 808 if ((txd->tx_flags & VTE_TXMBUF) != 0) 809 m_freem(m_head); 810 } 811 812 if (enq > 0) { 813 bus_dmamap_sync(sc->vte_dmatag, 814 sc->vte_cdata.vte_tx_ring_map, 0, 815 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 817 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 818 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 819 } 820 } 821 822 static void 823 vte_ifwatchdog(struct ifnet *ifp) 824 { 825 struct vte_softc *sc = ifp->if_softc; 826 827 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 828 return; 829 830 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 831 ifp->if_oerrors++; 832 vte_init(ifp); 833 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 834 vte_ifstart(ifp); 835 } 836 837 static int 838 vte_mediachange(struct ifnet *ifp) 839 { 840 int error; 841 struct vte_softc *sc = ifp->if_softc; 842 843 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 844 error = 0; 845 else if (error != 0) { 846 aprint_error_dev(sc->vte_dev, "could not set media\n"); 847 return error; 848 } 849 return 0; 850 851 } 852 853 static int 854 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 855 { 856 struct vte_softc *sc = ifp->if_softc; 857 int error, s; 858 859 s = splnet(); 860 error = ether_ioctl(ifp, cmd, data); 861 if (error == ENETRESET) { 862 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 863 if (ifp->if_flags & IFF_RUNNING) 864 vte_rxfilter(sc); 865 error = 0; 866 } 867 splx(s); 868 return error; 869 } 870 871 static void 872 vte_mac_config(struct vte_softc *sc) 873 { 874 uint16_t mcr; 875 876 mcr = CSR_READ_2(sc, VTE_MCR0); 877 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 878 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 879 mcr |= MCR0_FULL_DUPLEX; 880 #ifdef notyet 881 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 882 mcr |= MCR0_FC_ENB; 883 /* 884 * The data sheet is not clear whether the controller 885 * honors received pause frames or not. The is no 886 * separate control bit for RX pause frame so just 887 * enable MCR0_FC_ENB bit. 888 */ 889 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 890 mcr |= MCR0_FC_ENB; 891 #endif 892 } 893 CSR_WRITE_2(sc, VTE_MCR0, mcr); 894 } 895 896 static void 897 vte_stats_clear(struct vte_softc *sc) 898 { 899 900 /* Reading counter registers clears its contents. */ 901 CSR_READ_2(sc, VTE_CNT_RX_DONE); 902 CSR_READ_2(sc, VTE_CNT_MECNT0); 903 CSR_READ_2(sc, VTE_CNT_MECNT1); 904 CSR_READ_2(sc, VTE_CNT_MECNT2); 905 CSR_READ_2(sc, VTE_CNT_MECNT3); 906 CSR_READ_2(sc, VTE_CNT_TX_DONE); 907 CSR_READ_2(sc, VTE_CNT_MECNT4); 908 CSR_READ_2(sc, VTE_CNT_PAUSE); 909 } 910 911 static void 912 vte_stats_update(struct vte_softc *sc) 913 { 914 struct vte_hw_stats *stat; 915 struct ifnet *ifp = &sc->vte_if; 916 uint16_t value; 917 918 stat = &sc->vte_stats; 919 920 CSR_READ_2(sc, VTE_MECISR); 921 /* RX stats. */ 922 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 923 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 924 stat->rx_bcast_frames += (value >> 8); 925 stat->rx_mcast_frames += (value & 0xFF); 926 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 927 stat->rx_runts += (value >> 8); 928 stat->rx_crcerrs += (value & 0xFF); 929 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 930 stat->rx_long_frames += (value & 0xFF); 931 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 932 stat->rx_fifo_full += (value >> 8); 933 stat->rx_desc_unavail += (value & 0xFF); 934 935 /* TX stats. */ 936 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 937 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 938 stat->tx_underruns += (value >> 8); 939 stat->tx_late_colls += (value & 0xFF); 940 941 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 942 stat->tx_pause_frames += (value >> 8); 943 stat->rx_pause_frames += (value & 0xFF); 944 945 /* Update ifp counters. */ 946 ifp->if_opackets = stat->tx_frames; 947 ifp->if_oerrors = stat->tx_late_colls + stat->tx_underruns; 948 ifp->if_ipackets = stat->rx_frames; 949 ifp->if_ierrors = stat->rx_crcerrs + stat->rx_runts + 950 stat->rx_long_frames + stat->rx_fifo_full; 951 } 952 953 static int 954 vte_intr(void *arg) 955 { 956 struct vte_softc *sc = (struct vte_softc *)arg; 957 struct ifnet *ifp = &sc->vte_if; 958 uint16_t status; 959 int n; 960 961 /* Reading VTE_MISR acknowledges interrupts. */ 962 status = CSR_READ_2(sc, VTE_MISR); 963 DPRINTF(("vte_intr status 0x%x\n", status)); 964 if ((status & VTE_INTRS) == 0) { 965 /* Not ours. */ 966 return 0; 967 } 968 969 /* Disable interrupts. */ 970 CSR_WRITE_2(sc, VTE_MIER, 0); 971 for (n = 8; (status & VTE_INTRS) != 0;) { 972 if ((ifp->if_flags & IFF_RUNNING) == 0) 973 break; 974 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 975 MISR_RX_FIFO_FULL)) != 0) 976 vte_rxeof(sc); 977 if ((status & MISR_TX_DONE) != 0) 978 vte_txeof(sc); 979 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 980 vte_stats_update(sc); 981 if_schedule_deferred_start(ifp); 982 if (--n > 0) 983 status = CSR_READ_2(sc, VTE_MISR); 984 else 985 break; 986 } 987 988 if ((ifp->if_flags & IFF_RUNNING) != 0) { 989 /* Re-enable interrupts. */ 990 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 991 } 992 return 1; 993 } 994 995 static void 996 vte_txeof(struct vte_softc *sc) 997 { 998 struct ifnet *ifp; 999 struct vte_txdesc *txd; 1000 uint16_t status; 1001 int cons, prog; 1002 1003 ifp = &sc->vte_if; 1004 1005 if (sc->vte_cdata.vte_tx_cnt == 0) 1006 return; 1007 bus_dmamap_sync(sc->vte_dmatag, 1008 sc->vte_cdata.vte_tx_ring_map, 0, 1009 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1010 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1011 cons = sc->vte_cdata.vte_tx_cons; 1012 /* 1013 * Go through our TX list and free mbufs for those 1014 * frames which have been transmitted. 1015 */ 1016 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1017 txd = &sc->vte_cdata.vte_txdesc[cons]; 1018 status = le16toh(txd->tx_desc->dtst); 1019 if ((status & VTE_DTST_TX_OWN) != 0) 1020 break; 1021 if ((status & VTE_DTST_TX_OK) != 0) 1022 ifp->if_collisions += (status & 0xf); 1023 sc->vte_cdata.vte_tx_cnt--; 1024 /* Reclaim transmitted mbufs. */ 1025 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1026 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1027 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1028 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1029 m_freem(txd->tx_m); 1030 txd->tx_flags &= ~VTE_TXMBUF; 1031 txd->tx_m = NULL; 1032 prog++; 1033 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1034 } 1035 1036 if (prog > 0) { 1037 ifp->if_flags &= ~IFF_OACTIVE; 1038 sc->vte_cdata.vte_tx_cons = cons; 1039 /* 1040 * Unarm watchdog timer only when there is no pending 1041 * frames in TX queue. 1042 */ 1043 if (sc->vte_cdata.vte_tx_cnt == 0) 1044 sc->vte_watchdog_timer = 0; 1045 } 1046 } 1047 1048 static int 1049 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1050 { 1051 struct mbuf *m; 1052 bus_dmamap_t map; 1053 1054 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1055 if (m == NULL) 1056 return (ENOBUFS); 1057 m->m_len = m->m_pkthdr.len = MCLBYTES; 1058 m_adj(m, sizeof(uint32_t)); 1059 1060 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1061 sc->vte_cdata.vte_rx_sparemap, m, BUS_DMA_NOWAIT) != 0) { 1062 m_freem(m); 1063 return (ENOBUFS); 1064 } 1065 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1066 1067 if (rxd->rx_m != NULL) { 1068 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1069 0, rxd->rx_dmamap->dm_mapsize, 1070 BUS_DMASYNC_POSTREAD); 1071 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1072 } 1073 map = rxd->rx_dmamap; 1074 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1075 sc->vte_cdata.vte_rx_sparemap = map; 1076 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1077 0, rxd->rx_dmamap->dm_mapsize, 1078 BUS_DMASYNC_PREREAD); 1079 rxd->rx_m = m; 1080 rxd->rx_desc->drbp = 1081 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1082 rxd->rx_desc->drlen = htole16( 1083 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1084 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, 1085 (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, 1086 rxd->rx_dmamap->dm_segs[0].ds_len)); 1087 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1088 1089 return (0); 1090 } 1091 1092 static void 1093 vte_rxeof(struct vte_softc *sc) 1094 { 1095 struct ifnet *ifp; 1096 struct vte_rxdesc *rxd; 1097 struct mbuf *m; 1098 uint16_t status, total_len; 1099 int cons, prog; 1100 1101 bus_dmamap_sync(sc->vte_dmatag, 1102 sc->vte_cdata.vte_rx_ring_map, 0, 1103 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1104 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1105 cons = sc->vte_cdata.vte_rx_cons; 1106 ifp = &sc->vte_if; 1107 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1108 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1109 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1110 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1111 status = le16toh(rxd->rx_desc->drst); 1112 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", 1113 cons, rxd, rxd->rx_m, status, 1114 VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1115 if ((status & VTE_DRST_RX_OWN) != 0) 1116 break; 1117 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1118 m = rxd->rx_m; 1119 if ((status & VTE_DRST_RX_OK) == 0) { 1120 /* Discard errored frame. */ 1121 rxd->rx_desc->drlen = 1122 htole16(MCLBYTES - sizeof(uint32_t)); 1123 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1124 continue; 1125 } 1126 if (vte_newbuf(sc, rxd) != 0) { 1127 DPRINTF(("vte_rxeof newbuf failed\n")); 1128 ifp->if_ierrors++; 1129 rxd->rx_desc->drlen = 1130 htole16(MCLBYTES - sizeof(uint32_t)); 1131 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1132 continue; 1133 } 1134 1135 /* 1136 * It seems there is no way to strip FCS bytes. 1137 */ 1138 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1139 m_set_rcvif(m, ifp); 1140 if_percpuq_enqueue(ifp->if_percpuq, m); 1141 } 1142 1143 if (prog > 0) { 1144 /* Update the consumer index. */ 1145 sc->vte_cdata.vte_rx_cons = cons; 1146 /* 1147 * Sync updated RX descriptors such that controller see 1148 * modified RX buffer addresses. 1149 */ 1150 bus_dmamap_sync(sc->vte_dmatag, 1151 sc->vte_cdata.vte_rx_ring_map, 0, 1152 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1153 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1154 #ifdef notyet 1155 /* 1156 * Update residue counter. Controller does not 1157 * keep track of number of available RX descriptors 1158 * such that driver should have to update VTE_MRDCR 1159 * to make controller know how many free RX 1160 * descriptors were added to controller. This is 1161 * a similar mechanism used in VIA velocity 1162 * controllers and it indicates controller just 1163 * polls OWN bit of current RX descriptor pointer. 1164 * A couple of severe issues were seen on sample 1165 * board where the controller continuously emits TX 1166 * pause frames once RX pause threshold crossed. 1167 * Once triggered it never recovered form that 1168 * state, I couldn't find a way to make it back to 1169 * work at least. This issue effectively 1170 * disconnected the system from network. Also, the 1171 * controller used 00:00:00:00:00:00 as source 1172 * station address of TX pause frame. Probably this 1173 * is one of reason why vendor recommends not to 1174 * enable flow control on R6040 controller. 1175 */ 1176 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1177 (((VTE_RX_RING_CNT * 2) / 10) << 1178 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1179 #endif 1180 rnd_add_uint32(&sc->rnd_source, prog); 1181 } 1182 } 1183 1184 static void 1185 vte_tick(void *arg) 1186 { 1187 struct vte_softc *sc; 1188 int s = splnet(); 1189 1190 sc = (struct vte_softc *)arg; 1191 1192 mii_tick(&sc->vte_mii); 1193 vte_stats_update(sc); 1194 vte_txeof(sc); 1195 vte_ifwatchdog(&sc->vte_if); 1196 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1197 splx(s); 1198 } 1199 1200 static void 1201 vte_reset(struct vte_softc *sc) 1202 { 1203 uint16_t mcr; 1204 int i; 1205 1206 mcr = CSR_READ_2(sc, VTE_MCR1); 1207 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1208 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1209 DELAY(10); 1210 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1211 break; 1212 } 1213 if (i == 0) 1214 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1215 /* 1216 * Follow the guide of vendor recommended way to reset MAC. 1217 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1218 * not reliable so manually reset internal state machine. 1219 */ 1220 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1221 CSR_WRITE_2(sc, VTE_MACSM, 0); 1222 DELAY(5000); 1223 } 1224 1225 1226 static int 1227 vte_init(struct ifnet *ifp) 1228 { 1229 struct vte_softc *sc = ifp->if_softc; 1230 bus_addr_t paddr; 1231 uint8_t eaddr[ETHER_ADDR_LEN]; 1232 int s, error; 1233 1234 s = splnet(); 1235 /* 1236 * Cancel any pending I/O. 1237 */ 1238 vte_stop(ifp, 1); 1239 /* 1240 * Reset the chip to a known state. 1241 */ 1242 vte_reset(sc); 1243 1244 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1245 splx(s); 1246 return 0; 1247 } 1248 1249 /* Initialize RX descriptors. */ 1250 if (vte_init_rx_ring(sc) != 0) { 1251 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1252 vte_stop(ifp, 1); 1253 splx(s); 1254 return ENOMEM; 1255 } 1256 if (vte_init_tx_ring(sc) != 0) { 1257 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1258 vte_stop(ifp, 1); 1259 splx(s); 1260 return ENOMEM; 1261 } 1262 1263 /* 1264 * Reprogram the station address. Controller supports up 1265 * to 4 different station addresses so driver programs the 1266 * first station address as its own ethernet address and 1267 * configure the remaining three addresses as perfect 1268 * multicast addresses. 1269 */ 1270 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1271 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1272 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1273 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1274 1275 /* Set TX descriptor base addresses. */ 1276 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1277 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1278 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1279 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1280 1281 /* Set RX descriptor base addresses. */ 1282 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1283 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1284 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1285 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1286 /* 1287 * Initialize RX descriptor residue counter and set RX 1288 * pause threshold to 20% of available RX descriptors. 1289 * See comments on vte_rxeof() for details on flow control 1290 * issues. 1291 */ 1292 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1293 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1294 1295 /* 1296 * Always use maximum frame size that controller can 1297 * support. Otherwise received frames that has longer 1298 * frame length than vte(4) MTU would be silently dropped 1299 * in controller. This would break path-MTU discovery as 1300 * sender wouldn't get any responses from receiver. The 1301 * RX buffer size should be multiple of 4. 1302 * Note, jumbo frames are silently ignored by controller 1303 * and even MAC counters do not detect them. 1304 */ 1305 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1306 1307 /* Configure FIFO. */ 1308 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1309 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1310 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1311 1312 /* 1313 * Configure TX/RX MACs. Actual resolved duplex and flow 1314 * control configuration is done after detecting a valid 1315 * link. Note, we don't generate early interrupt here 1316 * as well since FreeBSD does not have interrupt latency 1317 * problems like Windows. 1318 */ 1319 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1320 /* 1321 * We manually keep track of PHY status changes to 1322 * configure resolved duplex and flow control since only 1323 * duplex configuration can be automatically reflected to 1324 * MCR0. 1325 */ 1326 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1327 MCR1_EXCESS_COL_RETRY_16); 1328 1329 /* Initialize RX filter. */ 1330 vte_rxfilter(sc); 1331 1332 /* Disable TX/RX interrupt moderation control. */ 1333 CSR_WRITE_2(sc, VTE_MRICR, 0); 1334 CSR_WRITE_2(sc, VTE_MTICR, 0); 1335 1336 /* Enable MAC event counter interrupts. */ 1337 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1338 /* Clear MAC statistics. */ 1339 vte_stats_clear(sc); 1340 1341 /* Acknowledge all pending interrupts and clear it. */ 1342 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1343 CSR_WRITE_2(sc, VTE_MISR, 0); 1344 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1345 CSR_READ_2(sc, VTE_MISR))); 1346 1347 sc->vte_flags &= ~VTE_FLAG_LINK; 1348 ifp->if_flags |= IFF_RUNNING; 1349 ifp->if_flags &= ~IFF_OACTIVE; 1350 1351 /* calling mii_mediachg will call back vte_start_mac() */ 1352 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1353 error = 0; 1354 else if (error != 0) { 1355 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1356 splx(s); 1357 return error; 1358 } 1359 1360 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1361 1362 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1363 CSR_READ_2(sc, VTE_MISR))); 1364 splx(s); 1365 return 0; 1366 } 1367 1368 static void 1369 vte_stop(struct ifnet *ifp, int disable) 1370 { 1371 struct vte_softc *sc = ifp->if_softc; 1372 struct vte_txdesc *txd; 1373 struct vte_rxdesc *rxd; 1374 int i; 1375 1376 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1377 if ((ifp->if_flags & IFF_RUNNING) == 0) 1378 return; 1379 /* 1380 * Mark the interface down and cancel the watchdog timer. 1381 */ 1382 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1383 sc->vte_flags &= ~VTE_FLAG_LINK; 1384 callout_stop(&sc->vte_tick_ch); 1385 sc->vte_watchdog_timer = 0; 1386 vte_stats_update(sc); 1387 /* Disable interrupts. */ 1388 CSR_WRITE_2(sc, VTE_MIER, 0); 1389 CSR_WRITE_2(sc, VTE_MECIER, 0); 1390 /* Stop RX/TX MACs. */ 1391 vte_stop_mac(sc); 1392 /* Clear interrupts. */ 1393 CSR_READ_2(sc, VTE_MISR); 1394 /* 1395 * Free TX/RX mbufs still in the queues. 1396 */ 1397 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1398 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1399 if (rxd->rx_m != NULL) { 1400 bus_dmamap_sync(sc->vte_dmatag, 1401 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1402 BUS_DMASYNC_POSTREAD); 1403 bus_dmamap_unload(sc->vte_dmatag, 1404 rxd->rx_dmamap); 1405 m_freem(rxd->rx_m); 1406 rxd->rx_m = NULL; 1407 } 1408 } 1409 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1410 txd = &sc->vte_cdata.vte_txdesc[i]; 1411 if (txd->tx_m != NULL) { 1412 bus_dmamap_sync(sc->vte_dmatag, 1413 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1414 BUS_DMASYNC_POSTWRITE); 1415 bus_dmamap_unload(sc->vte_dmatag, 1416 txd->tx_dmamap); 1417 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1418 m_freem(txd->tx_m); 1419 txd->tx_m = NULL; 1420 txd->tx_flags &= ~VTE_TXMBUF; 1421 } 1422 } 1423 /* Free TX mbuf pools used for deep copy. */ 1424 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1425 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1426 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1427 sc->vte_cdata.vte_txmbufs[i] = NULL; 1428 } 1429 } 1430 } 1431 1432 static void 1433 vte_start_mac(struct vte_softc *sc) 1434 { 1435 struct ifnet *ifp = &sc->vte_if; 1436 uint16_t mcr; 1437 int i; 1438 1439 /* Enable RX/TX MACs. */ 1440 mcr = CSR_READ_2(sc, VTE_MCR0); 1441 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1442 (MCR0_RX_ENB | MCR0_TX_ENB) && 1443 (ifp->if_flags & IFF_RUNNING) != 0) { 1444 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1445 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1446 for (i = VTE_TIMEOUT; i > 0; i--) { 1447 mcr = CSR_READ_2(sc, VTE_MCR0); 1448 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1449 (MCR0_RX_ENB | MCR0_TX_ENB)) 1450 break; 1451 DELAY(10); 1452 } 1453 if (i == 0) 1454 aprint_error_dev(sc->vte_dev, 1455 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1456 } 1457 vte_rxfilter(sc); 1458 } 1459 1460 static void 1461 vte_stop_mac(struct vte_softc *sc) 1462 { 1463 uint16_t mcr; 1464 int i; 1465 1466 /* Disable RX/TX MACs. */ 1467 mcr = CSR_READ_2(sc, VTE_MCR0); 1468 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1469 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1470 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1471 for (i = VTE_TIMEOUT; i > 0; i--) { 1472 mcr = CSR_READ_2(sc, VTE_MCR0); 1473 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1474 break; 1475 DELAY(10); 1476 } 1477 if (i == 0) 1478 aprint_error_dev(sc->vte_dev, 1479 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1480 } 1481 } 1482 1483 static int 1484 vte_init_tx_ring(struct vte_softc *sc) 1485 { 1486 struct vte_tx_desc *desc; 1487 struct vte_txdesc *txd; 1488 bus_addr_t addr; 1489 int i; 1490 1491 sc->vte_cdata.vte_tx_prod = 0; 1492 sc->vte_cdata.vte_tx_cons = 0; 1493 sc->vte_cdata.vte_tx_cnt = 0; 1494 1495 /* Pre-allocate TX mbufs for deep copy. */ 1496 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1497 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1498 MT_DATA, M_PKTHDR); 1499 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1500 return (ENOBUFS); 1501 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1502 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1503 } 1504 desc = sc->vte_cdata.vte_tx_ring; 1505 bzero(desc, VTE_TX_RING_SZ); 1506 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1507 txd = &sc->vte_cdata.vte_txdesc[i]; 1508 txd->tx_m = NULL; 1509 if (i != VTE_TX_RING_CNT - 1) 1510 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1511 sizeof(struct vte_tx_desc) * (i + 1); 1512 else 1513 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1514 sizeof(struct vte_tx_desc) * 0; 1515 desc = &sc->vte_cdata.vte_tx_ring[i]; 1516 desc->dtnp = htole32(addr); 1517 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1518 txd->tx_desc = desc; 1519 } 1520 1521 bus_dmamap_sync(sc->vte_dmatag, 1522 sc->vte_cdata.vte_tx_ring_map, 0, 1523 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1525 return (0); 1526 } 1527 1528 static int 1529 vte_init_rx_ring(struct vte_softc *sc) 1530 { 1531 struct vte_rx_desc *desc; 1532 struct vte_rxdesc *rxd; 1533 bus_addr_t addr; 1534 int i; 1535 1536 sc->vte_cdata.vte_rx_cons = 0; 1537 desc = sc->vte_cdata.vte_rx_ring; 1538 bzero(desc, VTE_RX_RING_SZ); 1539 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1540 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1541 rxd->rx_m = NULL; 1542 if (i != VTE_RX_RING_CNT - 1) 1543 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1544 + sizeof(struct vte_rx_desc) * (i + 1); 1545 else 1546 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1547 + sizeof(struct vte_rx_desc) * 0; 1548 desc = &sc->vte_cdata.vte_rx_ring[i]; 1549 desc->drnp = htole32(addr); 1550 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1551 rxd->rx_desc = desc; 1552 if (vte_newbuf(sc, rxd) != 0) 1553 return (ENOBUFS); 1554 } 1555 1556 bus_dmamap_sync(sc->vte_dmatag, 1557 sc->vte_cdata.vte_rx_ring_map, 0, 1558 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1559 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1560 1561 return (0); 1562 } 1563 1564 static void 1565 vte_rxfilter(struct vte_softc *sc) 1566 { 1567 struct ether_multistep step; 1568 struct ether_multi *enm; 1569 struct ifnet *ifp; 1570 uint8_t *eaddr; 1571 uint32_t crc; 1572 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1573 uint16_t mchash[4], mcr; 1574 int i, nperf; 1575 1576 ifp = &sc->vte_if; 1577 1578 DPRINTF(("vte_rxfilter\n")); 1579 memset(mchash, 0, sizeof(mchash)); 1580 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1581 rxfilt_perf[i][0] = 0xFFFF; 1582 rxfilt_perf[i][1] = 0xFFFF; 1583 rxfilt_perf[i][2] = 0xFFFF; 1584 } 1585 1586 mcr = CSR_READ_2(sc, VTE_MCR0); 1587 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1588 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST); 1589 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1590 mcr |= MCR0_BROADCAST_DIS; 1591 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1592 if ((ifp->if_flags & IFF_PROMISC) != 0) 1593 mcr |= MCR0_PROMISC; 1594 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1595 mcr |= MCR0_MULTICAST; 1596 mchash[0] = 0xFFFF; 1597 mchash[1] = 0xFFFF; 1598 mchash[2] = 0xFFFF; 1599 mchash[3] = 0xFFFF; 1600 goto chipit; 1601 } 1602 1603 ETHER_FIRST_MULTI(step, &sc->vte_ec, enm); 1604 nperf = 0; 1605 while (enm != NULL) { 1606 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1607 sc->vte_if.if_flags |= IFF_ALLMULTI; 1608 mcr |= MCR0_MULTICAST; 1609 mchash[0] = 0xFFFF; 1610 mchash[1] = 0xFFFF; 1611 mchash[2] = 0xFFFF; 1612 mchash[3] = 0xFFFF; 1613 goto chipit; 1614 } 1615 /* 1616 * Program the first 3 multicast groups into 1617 * the perfect filter. For all others, use the 1618 * hash table. 1619 */ 1620 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1621 eaddr = enm->enm_addrlo; 1622 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1623 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1624 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1625 nperf++; 1626 } else { 1627 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1628 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1629 } 1630 ETHER_NEXT_MULTI(step, enm); 1631 } 1632 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1633 mchash[3] != 0) 1634 mcr |= MCR0_MULTICAST; 1635 1636 chipit: 1637 /* Program multicast hash table. */ 1638 DPRINTF(("chipit write multicast\n")); 1639 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1640 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1641 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1642 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1643 /* Program perfect filter table. */ 1644 DPRINTF(("chipit write perfect filter\n")); 1645 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1646 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1647 rxfilt_perf[i][0]); 1648 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1649 rxfilt_perf[i][1]); 1650 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1651 rxfilt_perf[i][2]); 1652 } 1653 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1654 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1655 DPRINTF(("chipit read mcro\n")); 1656 CSR_READ_2(sc, VTE_MCR0); 1657 DPRINTF(("chipit done\n")); 1658 } 1659 1660 /* 1661 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1662 * set up in vte_pci_attach() 1663 */ 1664 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1665 { 1666 int rc; 1667 const struct sysctlnode *node; 1668 1669 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1670 0, CTLTYPE_NODE, "vte", 1671 SYSCTL_DESCR("vte interface controls"), 1672 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1673 goto err; 1674 } 1675 1676 vte_root_num = node->sysctl_num; 1677 return; 1678 1679 err: 1680 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1681 } 1682 1683 static int 1684 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1685 { 1686 int error, t; 1687 struct sysctlnode node; 1688 struct vte_softc *sc; 1689 1690 node = *rnode; 1691 sc = node.sysctl_data; 1692 t = sc->vte_int_rx_mod; 1693 node.sysctl_data = &t; 1694 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1695 if (error || newp == NULL) 1696 return error; 1697 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1698 return EINVAL; 1699 1700 sc->vte_int_rx_mod = t; 1701 vte_miibus_statchg(&sc->vte_if); 1702 return 0; 1703 } 1704 1705 static int 1706 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1707 { 1708 int error, t; 1709 struct sysctlnode node; 1710 struct vte_softc *sc; 1711 1712 node = *rnode; 1713 sc = node.sysctl_data; 1714 t = sc->vte_int_tx_mod; 1715 node.sysctl_data = &t; 1716 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1717 if (error || newp == NULL) 1718 return error; 1719 1720 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1721 return EINVAL; 1722 sc->vte_int_tx_mod = t; 1723 vte_miibus_statchg(&sc->vte_if); 1724 return 0; 1725 } 1726
Indexes created Thu Oct 02 01:09:59 GMT 2025