if_vte.c revision 1.26
1 /* $NetBSD: if_vte.c,v 1.26 2019/05/28 07:41:49 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2010, Pyun YongHyeon <yongari (at) FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 54 55 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.26 2019/05/28 07:41:49 msaitoh Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/mbuf.h> 63 #include <sys/protosw.h> 64 #include <sys/socket.h> 65 #include <sys/ioctl.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_dl.h> 76 #include <net/route.h> 77 #include <net/netisr.h> 78 #include <net/bpf.h> 79 80 #include <sys/rndsource.h> 81 82 #include "opt_inet.h" 83 #include <net/if_ether.h> 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/in_systm.h> 87 #include <netinet/in_var.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_inarp.h> 90 #endif 91 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/pci/if_vtereg.h> 103 #include <dev/pci/if_vtevar.h> 104 105 static int vte_match(device_t, cfdata_t, void *); 106 static void vte_attach(device_t, device_t, void *); 107 static int vte_detach(device_t, int); 108 static int vte_dma_alloc(struct vte_softc *); 109 static void vte_dma_free(struct vte_softc *); 110 static struct vte_txdesc * 111 vte_encap(struct vte_softc *, struct mbuf **); 112 static void vte_get_macaddr(struct vte_softc *); 113 static int vte_init(struct ifnet *); 114 static int vte_init_rx_ring(struct vte_softc *); 115 static int vte_init_tx_ring(struct vte_softc *); 116 static int vte_intr(void *); 117 static int vte_ifioctl(struct ifnet *, u_long, void *); 118 static void vte_mac_config(struct vte_softc *); 119 static int vte_miibus_readreg(device_t, int, int, uint16_t *); 120 static void vte_miibus_statchg(struct ifnet *); 121 static int vte_miibus_writereg(device_t, int, int, uint16_t); 122 static int vte_mediachange(struct ifnet *); 123 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 124 static void vte_reset(struct vte_softc *); 125 static void vte_rxeof(struct vte_softc *); 126 static void vte_rxfilter(struct vte_softc *); 127 static bool vte_shutdown(device_t, int); 128 static bool vte_suspend(device_t, const pmf_qual_t *); 129 static bool vte_resume(device_t, const pmf_qual_t *); 130 static void vte_ifstart(struct ifnet *); 131 static void vte_start_mac(struct vte_softc *); 132 static void vte_stats_clear(struct vte_softc *); 133 static void vte_stats_update(struct vte_softc *); 134 static void vte_stop(struct ifnet *, int); 135 static void vte_stop_mac(struct vte_softc *); 136 static void vte_tick(void *); 137 static void vte_txeof(struct vte_softc *); 138 static void vte_ifwatchdog(struct ifnet *); 139 140 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 141 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 142 static int vte_root_num; 143 144 #define DPRINTF(a) 145 146 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 147 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 148 149 150 static int 151 vte_match(device_t parent, cfdata_t cf, void *aux) 152 { 153 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 154 155 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 156 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 157 return 1; 158 159 return 0; 160 } 161 162 static void 163 vte_attach(device_t parent, device_t self, void *aux) 164 { 165 struct vte_softc *sc = device_private(self); 166 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 167 struct ifnet * const ifp = &sc->vte_if; 168 struct mii_data * const mii = &sc->vte_mii; 169 int h_valid; 170 pcireg_t reg, csr; 171 pci_intr_handle_t intrhandle; 172 const char *intrstr; 173 int error; 174 const struct sysctlnode *node; 175 int vte_nodenum; 176 char intrbuf[PCI_INTRSTR_LEN]; 177 178 sc->vte_dev = self; 179 180 callout_init(&sc->vte_tick_ch, 0); 181 182 /* Map the device. */ 183 h_valid = 0; 184 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 185 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 186 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 187 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 188 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 189 } 190 if (h_valid == 0) { 191 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 192 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 193 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 194 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 195 &sc->vte_bushandle, NULL, NULL) == 0); 196 } 197 } 198 if (h_valid == 0) { 199 aprint_error_dev(self, "unable to map device registers\n"); 200 return; 201 } 202 sc->vte_dmatag = pa->pa_dmat; 203 /* Enable the device. */ 204 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 205 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 206 csr | PCI_COMMAND_MASTER_ENABLE); 207 208 pci_aprint_devinfo(pa, NULL); 209 210 /* Reset the ethernet controller. */ 211 vte_reset(sc); 212 213 if ((error = vte_dma_alloc(sc)) != 0) 214 return; 215 216 /* Load station address. */ 217 vte_get_macaddr(sc); 218 219 aprint_normal_dev(self, "Ethernet address %s\n", 220 ether_sprintf(sc->vte_eaddr)); 221 222 /* Map and establish interrupts */ 223 if (pci_intr_map(pa, &intrhandle)) { 224 aprint_error_dev(self, "couldn't map interrupt\n"); 225 return; 226 } 227 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 228 sizeof(intrbuf)); 229 sc->vte_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 230 vte_intr, sc, device_xname(self)); 231 if (sc->vte_ih == NULL) { 232 aprint_error_dev(self, "couldn't establish interrupt"); 233 if (intrstr != NULL) 234 aprint_error(" at %s", intrstr); 235 aprint_error("\n"); 236 return; 237 } 238 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 239 240 sc->vte_if.if_softc = sc; 241 mii->mii_ifp = ifp; 242 mii->mii_readreg = vte_miibus_readreg; 243 mii->mii_writereg = vte_miibus_writereg; 244 mii->mii_statchg = vte_miibus_statchg; 245 sc->vte_ec.ec_mii = mii; 246 ifmedia_init(&mii->mii_media, IFM_IMASK, vte_mediachange, 247 ether_mediastatus); 248 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 249 MII_OFFSET_ANY, 0); 250 if (LIST_FIRST(&mii->mii_phys) == NULL) { 251 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 252 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 253 } else 254 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 255 256 /* 257 * We can support 802.1Q VLAN-sized frames. 258 */ 259 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 260 261 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 262 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 263 ifp->if_ioctl = vte_ifioctl; 264 ifp->if_start = vte_ifstart; 265 ifp->if_watchdog = vte_ifwatchdog; 266 ifp->if_init = vte_init; 267 ifp->if_stop = vte_stop; 268 ifp->if_timer = 0; 269 IFQ_SET_READY(&ifp->if_snd); 270 if_attach(ifp); 271 if_deferred_start_init(ifp, NULL); 272 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 273 274 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 275 pmf_class_network_register(self, ifp); 276 else 277 aprint_error_dev(self, "couldn't establish power handler\n"); 278 279 rnd_attach_source(&sc->rnd_source, device_xname(self), 280 RND_TYPE_NET, RND_FLAG_DEFAULT); 281 282 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 283 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 284 SYSCTL_DESCR("vte per-controller controls"), 285 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 286 CTL_EOL) != 0) { 287 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 288 return; 289 } 290 vte_nodenum = node->sysctl_num; 291 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 292 CTLFLAG_READWRITE, 293 CTLTYPE_INT, "int_rxct", 294 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 295 vte_sysctl_intrxct, 0, (void *)sc, 296 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 297 CTL_EOL) != 0) { 298 aprint_normal_dev(sc->vte_dev, 299 "couldn't create int_rxct sysctl node\n"); 300 } 301 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 302 CTLFLAG_READWRITE, 303 CTLTYPE_INT, "int_txct", 304 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 305 vte_sysctl_inttxct, 0, (void *)sc, 306 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 307 CTL_EOL) != 0) { 308 aprint_normal_dev(sc->vte_dev, 309 "couldn't create int_txct sysctl node\n"); 310 } 311 } 312 313 static int 314 vte_detach(device_t dev, int flags __unused) 315 { 316 struct vte_softc *sc = device_private(dev); 317 struct ifnet *ifp = &sc->vte_if; 318 int s; 319 320 s = splnet(); 321 /* Stop the interface. Callouts are stopped in it. */ 322 vte_stop(ifp, 1); 323 splx(s); 324 325 pmf_device_deregister(dev); 326 327 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 328 ifmedia_delete_instance(&sc->vte_mii.mii_media, IFM_INST_ANY); 329 330 ether_ifdetach(ifp); 331 if_detach(ifp); 332 333 vte_dma_free(sc); 334 335 return (0); 336 } 337 338 static int 339 vte_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 340 { 341 struct vte_softc *sc = device_private(dev); 342 int i; 343 344 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 345 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 346 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 347 DELAY(5); 348 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 349 break; 350 } 351 352 if (i == 0) { 353 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 354 return ETIMEDOUT; 355 } 356 357 *val = CSR_READ_2(sc, VTE_MMRD); 358 return 0; 359 } 360 361 static int 362 vte_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 363 { 364 struct vte_softc *sc = device_private(dev); 365 int i; 366 367 CSR_WRITE_2(sc, VTE_MMWD, val); 368 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 369 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 370 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 371 DELAY(5); 372 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 373 break; 374 } 375 376 if (i == 0) { 377 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 378 return ETIMEDOUT; 379 } 380 381 return 0; 382 } 383 384 static void 385 vte_miibus_statchg(struct ifnet *ifp) 386 { 387 struct vte_softc *sc = ifp->if_softc; 388 uint16_t val; 389 390 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 391 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 392 393 sc->vte_flags &= ~VTE_FLAG_LINK; 394 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 395 (IFM_ACTIVE | IFM_AVALID)) { 396 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 397 case IFM_10_T: 398 case IFM_100_TX: 399 sc->vte_flags |= VTE_FLAG_LINK; 400 break; 401 default: 402 break; 403 } 404 } 405 406 /* Stop RX/TX MACs. */ 407 vte_stop_mac(sc); 408 /* Program MACs with resolved duplex and flow control. */ 409 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 410 /* 411 * Timer waiting time : (63 + TIMER * 64) MII clock. 412 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 413 */ 414 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 415 val = 18 << VTE_IM_TIMER_SHIFT; 416 else 417 val = 1 << VTE_IM_TIMER_SHIFT; 418 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 419 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 420 CSR_WRITE_2(sc, VTE_MRICR, val); 421 422 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 423 val = 18 << VTE_IM_TIMER_SHIFT; 424 else 425 val = 1 << VTE_IM_TIMER_SHIFT; 426 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 427 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 428 CSR_WRITE_2(sc, VTE_MTICR, val); 429 430 vte_mac_config(sc); 431 vte_start_mac(sc); 432 DPRINTF(("vte_miibus_statchg: link\n")); 433 } 434 } 435 436 static void 437 vte_get_macaddr(struct vte_softc *sc) 438 { 439 uint16_t mid; 440 441 /* 442 * It seems there is no way to reload station address and 443 * it is supposed to be set by BIOS. 444 */ 445 mid = CSR_READ_2(sc, VTE_MID0L); 446 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 447 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 448 mid = CSR_READ_2(sc, VTE_MID0M); 449 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 450 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 451 mid = CSR_READ_2(sc, VTE_MID0H); 452 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 453 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 454 } 455 456 457 static int 458 vte_dma_alloc(struct vte_softc *sc) 459 { 460 struct vte_txdesc *txd; 461 struct vte_rxdesc *rxd; 462 int error, i, rseg; 463 464 /* create DMA map for TX ring */ 465 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 466 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 467 &sc->vte_cdata.vte_tx_ring_map); 468 if (error) { 469 aprint_error_dev(sc->vte_dev, 470 "could not create dma map for TX ring (%d)\n", 471 error); 472 goto fail; 473 } 474 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 475 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 476 VTE_TX_RING_ALIGN, 0, 477 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 478 BUS_DMA_NOWAIT); 479 if (error != 0) { 480 aprint_error_dev(sc->vte_dev, 481 "could not allocate DMA'able memory for TX ring (%d).\n", 482 error); 483 goto fail; 484 } 485 KASSERT(rseg == 1); 486 error = bus_dmamem_map(sc->vte_dmatag, 487 sc->vte_cdata.vte_tx_ring_seg, 1, 488 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 489 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 490 if (error != 0) { 491 aprint_error_dev(sc->vte_dev, 492 "could not map DMA'able memory for TX ring (%d).\n", 493 error); 494 goto fail; 495 } 496 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 497 error = bus_dmamap_load(sc->vte_dmatag, 498 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 499 VTE_TX_RING_SZ, NULL, 500 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 501 if (error != 0) { 502 aprint_error_dev(sc->vte_dev, 503 "could not load DMA'able memory for TX ring.\n"); 504 goto fail; 505 } 506 507 /* create DMA map for RX ring */ 508 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 509 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 510 &sc->vte_cdata.vte_rx_ring_map); 511 if (error) { 512 aprint_error_dev(sc->vte_dev, 513 "could not create dma map for RX ring (%d)\n", 514 error); 515 goto fail; 516 } 517 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 518 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 519 VTE_RX_RING_ALIGN, 0, 520 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 521 BUS_DMA_NOWAIT); 522 if (error != 0) { 523 aprint_error_dev(sc->vte_dev, 524 "could not allocate DMA'able memory for RX ring (%d).\n", 525 error); 526 goto fail; 527 } 528 KASSERT(rseg == 1); 529 error = bus_dmamem_map(sc->vte_dmatag, 530 sc->vte_cdata.vte_rx_ring_seg, 1, 531 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 532 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 533 if (error != 0) { 534 aprint_error_dev(sc->vte_dev, 535 "could not map DMA'able memory for RX ring (%d).\n", 536 error); 537 goto fail; 538 } 539 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 540 error = bus_dmamap_load(sc->vte_dmatag, 541 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 542 VTE_RX_RING_SZ, NULL, 543 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 544 if (error != 0) { 545 aprint_error_dev(sc->vte_dev, 546 "could not load DMA'able memory for RX ring (%d).\n", 547 error); 548 goto fail; 549 } 550 551 /* Create DMA maps for TX buffers. */ 552 for (i = 0; i < VTE_TX_RING_CNT; i++) { 553 txd = &sc->vte_cdata.vte_txdesc[i]; 554 txd->tx_m = NULL; 555 txd->tx_dmamap = NULL; 556 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 557 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 558 &txd->tx_dmamap); 559 if (error != 0) { 560 aprint_error_dev(sc->vte_dev, 561 "could not create TX DMA map %d (%d).\n", i, error); 562 goto fail; 563 } 564 } 565 /* Create DMA maps for RX buffers. */ 566 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 567 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 568 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 569 aprint_error_dev(sc->vte_dev, 570 "could not create spare RX dmamap (%d).\n", error); 571 goto fail; 572 } 573 for (i = 0; i < VTE_RX_RING_CNT; i++) { 574 rxd = &sc->vte_cdata.vte_rxdesc[i]; 575 rxd->rx_m = NULL; 576 rxd->rx_dmamap = NULL; 577 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 578 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 579 &rxd->rx_dmamap); 580 if (error != 0) { 581 aprint_error_dev(sc->vte_dev, 582 "could not create RX dmamap %d (%d).\n", i, error); 583 goto fail; 584 } 585 } 586 return 0; 587 588 fail: 589 vte_dma_free(sc); 590 return (error); 591 } 592 593 static void 594 vte_dma_free(struct vte_softc *sc) 595 { 596 struct vte_txdesc *txd; 597 struct vte_rxdesc *rxd; 598 int i; 599 600 /* TX buffers. */ 601 for (i = 0; i < VTE_TX_RING_CNT; i++) { 602 txd = &sc->vte_cdata.vte_txdesc[i]; 603 if (txd->tx_dmamap != NULL) { 604 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 605 txd->tx_dmamap = NULL; 606 } 607 } 608 /* RX buffers */ 609 for (i = 0; i < VTE_RX_RING_CNT; i++) { 610 rxd = &sc->vte_cdata.vte_rxdesc[i]; 611 if (rxd->rx_dmamap != NULL) { 612 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 613 rxd->rx_dmamap = NULL; 614 } 615 } 616 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 617 bus_dmamap_destroy(sc->vte_dmatag, 618 sc->vte_cdata.vte_rx_sparemap); 619 sc->vte_cdata.vte_rx_sparemap = NULL; 620 } 621 /* TX descriptor ring. */ 622 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 623 bus_dmamap_unload(sc->vte_dmatag, 624 sc->vte_cdata.vte_tx_ring_map); 625 bus_dmamap_destroy(sc->vte_dmatag, 626 sc->vte_cdata.vte_tx_ring_map); 627 } 628 if (sc->vte_cdata.vte_tx_ring != NULL) { 629 bus_dmamem_unmap(sc->vte_dmatag, 630 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 631 bus_dmamem_free(sc->vte_dmatag, 632 sc->vte_cdata.vte_tx_ring_seg, 1); 633 } 634 sc->vte_cdata.vte_tx_ring = NULL; 635 sc->vte_cdata.vte_tx_ring_map = NULL; 636 /* RX ring. */ 637 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 638 bus_dmamap_unload(sc->vte_dmatag, 639 sc->vte_cdata.vte_rx_ring_map); 640 bus_dmamap_destroy(sc->vte_dmatag, 641 sc->vte_cdata.vte_rx_ring_map); 642 } 643 if (sc->vte_cdata.vte_rx_ring != NULL) { 644 bus_dmamem_unmap(sc->vte_dmatag, 645 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 646 bus_dmamem_free(sc->vte_dmatag, 647 sc->vte_cdata.vte_rx_ring_seg, 1); 648 } 649 sc->vte_cdata.vte_rx_ring = NULL; 650 sc->vte_cdata.vte_rx_ring_map = NULL; 651 } 652 653 static bool 654 vte_shutdown(device_t dev, int howto) 655 { 656 657 return (vte_suspend(dev, NULL)); 658 } 659 660 static bool 661 vte_suspend(device_t dev, const pmf_qual_t *qual) 662 { 663 struct vte_softc *sc = device_private(dev); 664 struct ifnet *ifp = &sc->vte_if; 665 666 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 667 if ((ifp->if_flags & IFF_RUNNING) != 0) 668 vte_stop(ifp, 1); 669 return (0); 670 } 671 672 static bool 673 vte_resume(device_t dev, const pmf_qual_t *qual) 674 { 675 struct vte_softc *sc = device_private(dev); 676 struct ifnet *ifp; 677 678 ifp = &sc->vte_if; 679 if ((ifp->if_flags & IFF_UP) != 0) { 680 ifp->if_flags &= ~IFF_RUNNING; 681 vte_init(ifp); 682 } 683 684 return (0); 685 } 686 687 static struct vte_txdesc * 688 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 689 { 690 struct vte_txdesc *txd; 691 struct mbuf *m, *n; 692 int copy, error, padlen; 693 694 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 695 m = *m_head; 696 /* 697 * Controller doesn't auto-pad, so we have to make sure pad 698 * short frames out to the minimum frame length. 699 */ 700 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 701 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 702 else 703 padlen = 0; 704 705 /* 706 * Controller does not support multi-fragmented TX buffers. 707 * Controller spends most of its TX processing time in 708 * de-fragmenting TX buffers. Either faster CPU or more 709 * advanced controller DMA engine is required to speed up 710 * TX path processing. 711 * To mitigate the de-fragmenting issue, perform deep copy 712 * from fragmented mbuf chains to a pre-allocated mbuf 713 * cluster with extra cost of kernel memory. For frames 714 * that is composed of single TX buffer, the deep copy is 715 * bypassed. 716 */ 717 copy = 0; 718 if (m->m_next != NULL) 719 copy++; 720 if (padlen > 0 && (M_READONLY(m) || 721 padlen > M_TRAILINGSPACE(m))) 722 copy++; 723 if (copy != 0) { 724 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 725 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 726 n->m_pkthdr.len = m->m_pkthdr.len; 727 n->m_len = m->m_pkthdr.len; 728 m = n; 729 txd->tx_flags |= VTE_TXMBUF; 730 } 731 732 if (padlen > 0) { 733 /* Zero out the bytes in the pad area. */ 734 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 735 m->m_pkthdr.len += padlen; 736 m->m_len = m->m_pkthdr.len; 737 } 738 739 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 740 BUS_DMA_NOWAIT); 741 if (error != 0) { 742 txd->tx_flags &= ~VTE_TXMBUF; 743 return (NULL); 744 } 745 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 746 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 747 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 748 749 txd->tx_desc->dtlen = 750 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 751 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 752 sc->vte_cdata.vte_tx_cnt++; 753 /* Update producer index. */ 754 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 755 756 /* Finally hand over ownership to controller. */ 757 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 758 txd->tx_m = m; 759 760 return (txd); 761 } 762 763 static void 764 vte_ifstart(struct ifnet *ifp) 765 { 766 struct vte_softc *sc = ifp->if_softc; 767 struct vte_txdesc *txd; 768 struct mbuf *m_head, *m; 769 int enq; 770 771 ifp = &sc->vte_if; 772 773 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 774 775 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 776 IFF_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 777 return; 778 779 for (enq = 0; !IFQ_IS_EMPTY(&ifp->if_snd); ) { 780 /* Reserve one free TX descriptor. */ 781 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 782 ifp->if_flags |= IFF_OACTIVE; 783 break; 784 } 785 IFQ_POLL(&ifp->if_snd, m_head); 786 if (m_head == NULL) 787 break; 788 /* 789 * Pack the data into the transmit ring. If we 790 * don't have room, set the OACTIVE flag and wait 791 * for the NIC to drain the ring. 792 */ 793 DPRINTF(("vte_encap:")); 794 if ((txd = vte_encap(sc, &m_head)) == NULL) { 795 DPRINTF((" failed\n")); 796 break; 797 } 798 DPRINTF((" ok\n")); 799 IFQ_DEQUEUE(&ifp->if_snd, m); 800 KASSERT(m == m_head); 801 802 enq++; 803 /* 804 * If there's a BPF listener, bounce a copy of this frame 805 * to him. 806 */ 807 bpf_mtap(ifp, m_head, BPF_D_OUT); 808 /* Free consumed TX frame. */ 809 if ((txd->tx_flags & VTE_TXMBUF) != 0) 810 m_freem(m_head); 811 } 812 813 if (enq > 0) { 814 bus_dmamap_sync(sc->vte_dmatag, 815 sc->vte_cdata.vte_tx_ring_map, 0, 816 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 817 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 818 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 819 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 820 } 821 } 822 823 static void 824 vte_ifwatchdog(struct ifnet *ifp) 825 { 826 struct vte_softc *sc = ifp->if_softc; 827 828 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 829 return; 830 831 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 832 ifp->if_oerrors++; 833 vte_init(ifp); 834 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 835 vte_ifstart(ifp); 836 } 837 838 static int 839 vte_mediachange(struct ifnet *ifp) 840 { 841 int error; 842 struct vte_softc *sc = ifp->if_softc; 843 844 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 845 error = 0; 846 else if (error != 0) { 847 aprint_error_dev(sc->vte_dev, "could not set media\n"); 848 return error; 849 } 850 return 0; 851 852 } 853 854 static int 855 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 856 { 857 struct vte_softc *sc = ifp->if_softc; 858 int error, s; 859 860 s = splnet(); 861 error = ether_ioctl(ifp, cmd, data); 862 if (error == ENETRESET) { 863 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 864 if (ifp->if_flags & IFF_RUNNING) 865 vte_rxfilter(sc); 866 error = 0; 867 } 868 splx(s); 869 return error; 870 } 871 872 static void 873 vte_mac_config(struct vte_softc *sc) 874 { 875 uint16_t mcr; 876 877 mcr = CSR_READ_2(sc, VTE_MCR0); 878 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 879 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 880 mcr |= MCR0_FULL_DUPLEX; 881 #ifdef notyet 882 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 883 mcr |= MCR0_FC_ENB; 884 /* 885 * The data sheet is not clear whether the controller 886 * honors received pause frames or not. The is no 887 * separate control bit for RX pause frame so just 888 * enable MCR0_FC_ENB bit. 889 */ 890 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 891 mcr |= MCR0_FC_ENB; 892 #endif 893 } 894 CSR_WRITE_2(sc, VTE_MCR0, mcr); 895 } 896 897 static void 898 vte_stats_clear(struct vte_softc *sc) 899 { 900 901 /* Reading counter registers clears its contents. */ 902 CSR_READ_2(sc, VTE_CNT_RX_DONE); 903 CSR_READ_2(sc, VTE_CNT_MECNT0); 904 CSR_READ_2(sc, VTE_CNT_MECNT1); 905 CSR_READ_2(sc, VTE_CNT_MECNT2); 906 CSR_READ_2(sc, VTE_CNT_MECNT3); 907 CSR_READ_2(sc, VTE_CNT_TX_DONE); 908 CSR_READ_2(sc, VTE_CNT_MECNT4); 909 CSR_READ_2(sc, VTE_CNT_PAUSE); 910 } 911 912 static void 913 vte_stats_update(struct vte_softc *sc) 914 { 915 struct vte_hw_stats *stat; 916 struct ifnet *ifp = &sc->vte_if; 917 uint16_t value; 918 919 stat = &sc->vte_stats; 920 921 CSR_READ_2(sc, VTE_MECISR); 922 /* RX stats. */ 923 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 924 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 925 stat->rx_bcast_frames += (value >> 8); 926 stat->rx_mcast_frames += (value & 0xFF); 927 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 928 stat->rx_runts += (value >> 8); 929 stat->rx_crcerrs += (value & 0xFF); 930 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 931 stat->rx_long_frames += (value & 0xFF); 932 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 933 stat->rx_fifo_full += (value >> 8); 934 stat->rx_desc_unavail += (value & 0xFF); 935 936 /* TX stats. */ 937 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 938 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 939 stat->tx_underruns += (value >> 8); 940 stat->tx_late_colls += (value & 0xFF); 941 942 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 943 stat->tx_pause_frames += (value >> 8); 944 stat->rx_pause_frames += (value & 0xFF); 945 946 /* Update ifp counters. */ 947 ifp->if_opackets = stat->tx_frames; 948 ifp->if_oerrors = stat->tx_late_colls + stat->tx_underruns; 949 ifp->if_ipackets = stat->rx_frames; 950 ifp->if_ierrors = stat->rx_crcerrs + stat->rx_runts + 951 stat->rx_long_frames + stat->rx_fifo_full; 952 } 953 954 static int 955 vte_intr(void *arg) 956 { 957 struct vte_softc *sc = (struct vte_softc *)arg; 958 struct ifnet *ifp = &sc->vte_if; 959 uint16_t status; 960 int n; 961 962 /* Reading VTE_MISR acknowledges interrupts. */ 963 status = CSR_READ_2(sc, VTE_MISR); 964 DPRINTF(("vte_intr status 0x%x\n", status)); 965 if ((status & VTE_INTRS) == 0) { 966 /* Not ours. */ 967 return 0; 968 } 969 970 /* Disable interrupts. */ 971 CSR_WRITE_2(sc, VTE_MIER, 0); 972 for (n = 8; (status & VTE_INTRS) != 0;) { 973 if ((ifp->if_flags & IFF_RUNNING) == 0) 974 break; 975 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 976 MISR_RX_FIFO_FULL)) != 0) 977 vte_rxeof(sc); 978 if ((status & MISR_TX_DONE) != 0) 979 vte_txeof(sc); 980 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 981 vte_stats_update(sc); 982 if_schedule_deferred_start(ifp); 983 if (--n > 0) 984 status = CSR_READ_2(sc, VTE_MISR); 985 else 986 break; 987 } 988 989 if ((ifp->if_flags & IFF_RUNNING) != 0) { 990 /* Re-enable interrupts. */ 991 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 992 } 993 return 1; 994 } 995 996 static void 997 vte_txeof(struct vte_softc *sc) 998 { 999 struct ifnet *ifp; 1000 struct vte_txdesc *txd; 1001 uint16_t status; 1002 int cons, prog; 1003 1004 ifp = &sc->vte_if; 1005 1006 if (sc->vte_cdata.vte_tx_cnt == 0) 1007 return; 1008 bus_dmamap_sync(sc->vte_dmatag, 1009 sc->vte_cdata.vte_tx_ring_map, 0, 1010 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1011 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1012 cons = sc->vte_cdata.vte_tx_cons; 1013 /* 1014 * Go through our TX list and free mbufs for those 1015 * frames which have been transmitted. 1016 */ 1017 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1018 txd = &sc->vte_cdata.vte_txdesc[cons]; 1019 status = le16toh(txd->tx_desc->dtst); 1020 if ((status & VTE_DTST_TX_OWN) != 0) 1021 break; 1022 if ((status & VTE_DTST_TX_OK) != 0) 1023 ifp->if_collisions += (status & 0xf); 1024 sc->vte_cdata.vte_tx_cnt--; 1025 /* Reclaim transmitted mbufs. */ 1026 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1027 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1028 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1029 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1030 m_freem(txd->tx_m); 1031 txd->tx_flags &= ~VTE_TXMBUF; 1032 txd->tx_m = NULL; 1033 prog++; 1034 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1035 } 1036 1037 if (prog > 0) { 1038 ifp->if_flags &= ~IFF_OACTIVE; 1039 sc->vte_cdata.vte_tx_cons = cons; 1040 /* 1041 * Unarm watchdog timer only when there is no pending 1042 * frames in TX queue. 1043 */ 1044 if (sc->vte_cdata.vte_tx_cnt == 0) 1045 sc->vte_watchdog_timer = 0; 1046 } 1047 } 1048 1049 static int 1050 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1051 { 1052 struct mbuf *m; 1053 bus_dmamap_t map; 1054 1055 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1056 if (m == NULL) 1057 return (ENOBUFS); 1058 m->m_len = m->m_pkthdr.len = MCLBYTES; 1059 m_adj(m, sizeof(uint32_t)); 1060 1061 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1062 sc->vte_cdata.vte_rx_sparemap, m, BUS_DMA_NOWAIT) != 0) { 1063 m_freem(m); 1064 return (ENOBUFS); 1065 } 1066 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1067 1068 if (rxd->rx_m != NULL) { 1069 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1070 0, rxd->rx_dmamap->dm_mapsize, 1071 BUS_DMASYNC_POSTREAD); 1072 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1073 } 1074 map = rxd->rx_dmamap; 1075 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1076 sc->vte_cdata.vte_rx_sparemap = map; 1077 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1078 0, rxd->rx_dmamap->dm_mapsize, 1079 BUS_DMASYNC_PREREAD); 1080 rxd->rx_m = m; 1081 rxd->rx_desc->drbp = 1082 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1083 rxd->rx_desc->drlen = htole16( 1084 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1085 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, 1086 (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, 1087 rxd->rx_dmamap->dm_segs[0].ds_len)); 1088 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1089 1090 return (0); 1091 } 1092 1093 static void 1094 vte_rxeof(struct vte_softc *sc) 1095 { 1096 struct ifnet *ifp; 1097 struct vte_rxdesc *rxd; 1098 struct mbuf *m; 1099 uint16_t status, total_len; 1100 int cons, prog; 1101 1102 bus_dmamap_sync(sc->vte_dmatag, 1103 sc->vte_cdata.vte_rx_ring_map, 0, 1104 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1105 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1106 cons = sc->vte_cdata.vte_rx_cons; 1107 ifp = &sc->vte_if; 1108 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1109 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1110 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1111 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1112 status = le16toh(rxd->rx_desc->drst); 1113 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", 1114 cons, rxd, rxd->rx_m, status, 1115 VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1116 if ((status & VTE_DRST_RX_OWN) != 0) 1117 break; 1118 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1119 m = rxd->rx_m; 1120 if ((status & VTE_DRST_RX_OK) == 0) { 1121 /* Discard errored frame. */ 1122 rxd->rx_desc->drlen = 1123 htole16(MCLBYTES - sizeof(uint32_t)); 1124 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1125 continue; 1126 } 1127 if (vte_newbuf(sc, rxd) != 0) { 1128 DPRINTF(("vte_rxeof newbuf failed\n")); 1129 ifp->if_ierrors++; 1130 rxd->rx_desc->drlen = 1131 htole16(MCLBYTES - sizeof(uint32_t)); 1132 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1133 continue; 1134 } 1135 1136 /* 1137 * It seems there is no way to strip FCS bytes. 1138 */ 1139 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1140 m_set_rcvif(m, ifp); 1141 if_percpuq_enqueue(ifp->if_percpuq, m); 1142 } 1143 1144 if (prog > 0) { 1145 /* Update the consumer index. */ 1146 sc->vte_cdata.vte_rx_cons = cons; 1147 /* 1148 * Sync updated RX descriptors such that controller see 1149 * modified RX buffer addresses. 1150 */ 1151 bus_dmamap_sync(sc->vte_dmatag, 1152 sc->vte_cdata.vte_rx_ring_map, 0, 1153 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1154 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1155 #ifdef notyet 1156 /* 1157 * Update residue counter. Controller does not 1158 * keep track of number of available RX descriptors 1159 * such that driver should have to update VTE_MRDCR 1160 * to make controller know how many free RX 1161 * descriptors were added to controller. This is 1162 * a similar mechanism used in VIA velocity 1163 * controllers and it indicates controller just 1164 * polls OWN bit of current RX descriptor pointer. 1165 * A couple of severe issues were seen on sample 1166 * board where the controller continuously emits TX 1167 * pause frames once RX pause threshold crossed. 1168 * Once triggered it never recovered form that 1169 * state, I couldn't find a way to make it back to 1170 * work at least. This issue effectively 1171 * disconnected the system from network. Also, the 1172 * controller used 00:00:00:00:00:00 as source 1173 * station address of TX pause frame. Probably this 1174 * is one of reason why vendor recommends not to 1175 * enable flow control on R6040 controller. 1176 */ 1177 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1178 (((VTE_RX_RING_CNT * 2) / 10) << 1179 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1180 #endif 1181 rnd_add_uint32(&sc->rnd_source, prog); 1182 } 1183 } 1184 1185 static void 1186 vte_tick(void *arg) 1187 { 1188 struct vte_softc *sc; 1189 int s = splnet(); 1190 1191 sc = (struct vte_softc *)arg; 1192 1193 mii_tick(&sc->vte_mii); 1194 vte_stats_update(sc); 1195 vte_txeof(sc); 1196 vte_ifwatchdog(&sc->vte_if); 1197 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1198 splx(s); 1199 } 1200 1201 static void 1202 vte_reset(struct vte_softc *sc) 1203 { 1204 uint16_t mcr; 1205 int i; 1206 1207 mcr = CSR_READ_2(sc, VTE_MCR1); 1208 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1209 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1210 DELAY(10); 1211 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1212 break; 1213 } 1214 if (i == 0) 1215 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1216 /* 1217 * Follow the guide of vendor recommended way to reset MAC. 1218 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1219 * not reliable so manually reset internal state machine. 1220 */ 1221 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1222 CSR_WRITE_2(sc, VTE_MACSM, 0); 1223 DELAY(5000); 1224 } 1225 1226 1227 static int 1228 vte_init(struct ifnet *ifp) 1229 { 1230 struct vte_softc *sc = ifp->if_softc; 1231 bus_addr_t paddr; 1232 uint8_t eaddr[ETHER_ADDR_LEN]; 1233 int s, error; 1234 1235 s = splnet(); 1236 /* 1237 * Cancel any pending I/O. 1238 */ 1239 vte_stop(ifp, 1); 1240 /* 1241 * Reset the chip to a known state. 1242 */ 1243 vte_reset(sc); 1244 1245 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1246 splx(s); 1247 return 0; 1248 } 1249 1250 /* Initialize RX descriptors. */ 1251 if (vte_init_rx_ring(sc) != 0) { 1252 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1253 vte_stop(ifp, 1); 1254 splx(s); 1255 return ENOMEM; 1256 } 1257 if (vte_init_tx_ring(sc) != 0) { 1258 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1259 vte_stop(ifp, 1); 1260 splx(s); 1261 return ENOMEM; 1262 } 1263 1264 /* 1265 * Reprogram the station address. Controller supports up 1266 * to 4 different station addresses so driver programs the 1267 * first station address as its own ethernet address and 1268 * configure the remaining three addresses as perfect 1269 * multicast addresses. 1270 */ 1271 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1272 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1273 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1274 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1275 1276 /* Set TX descriptor base addresses. */ 1277 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1278 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1279 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1280 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1281 1282 /* Set RX descriptor base addresses. */ 1283 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1284 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1285 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1286 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1287 /* 1288 * Initialize RX descriptor residue counter and set RX 1289 * pause threshold to 20% of available RX descriptors. 1290 * See comments on vte_rxeof() for details on flow control 1291 * issues. 1292 */ 1293 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1294 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1295 1296 /* 1297 * Always use maximum frame size that controller can 1298 * support. Otherwise received frames that has longer 1299 * frame length than vte(4) MTU would be silently dropped 1300 * in controller. This would break path-MTU discovery as 1301 * sender wouldn't get any responses from receiver. The 1302 * RX buffer size should be multiple of 4. 1303 * Note, jumbo frames are silently ignored by controller 1304 * and even MAC counters do not detect them. 1305 */ 1306 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1307 1308 /* Configure FIFO. */ 1309 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1310 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1311 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1312 1313 /* 1314 * Configure TX/RX MACs. Actual resolved duplex and flow 1315 * control configuration is done after detecting a valid 1316 * link. Note, we don't generate early interrupt here 1317 * as well since FreeBSD does not have interrupt latency 1318 * problems like Windows. 1319 */ 1320 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1321 /* 1322 * We manually keep track of PHY status changes to 1323 * configure resolved duplex and flow control since only 1324 * duplex configuration can be automatically reflected to 1325 * MCR0. 1326 */ 1327 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1328 MCR1_EXCESS_COL_RETRY_16); 1329 1330 /* Initialize RX filter. */ 1331 vte_rxfilter(sc); 1332 1333 /* Disable TX/RX interrupt moderation control. */ 1334 CSR_WRITE_2(sc, VTE_MRICR, 0); 1335 CSR_WRITE_2(sc, VTE_MTICR, 0); 1336 1337 /* Enable MAC event counter interrupts. */ 1338 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1339 /* Clear MAC statistics. */ 1340 vte_stats_clear(sc); 1341 1342 /* Acknowledge all pending interrupts and clear it. */ 1343 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1344 CSR_WRITE_2(sc, VTE_MISR, 0); 1345 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1346 CSR_READ_2(sc, VTE_MISR))); 1347 1348 sc->vte_flags &= ~VTE_FLAG_LINK; 1349 ifp->if_flags |= IFF_RUNNING; 1350 ifp->if_flags &= ~IFF_OACTIVE; 1351 1352 /* calling mii_mediachg will call back vte_start_mac() */ 1353 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1354 error = 0; 1355 else if (error != 0) { 1356 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1357 splx(s); 1358 return error; 1359 } 1360 1361 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1362 1363 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1364 CSR_READ_2(sc, VTE_MISR))); 1365 splx(s); 1366 return 0; 1367 } 1368 1369 static void 1370 vte_stop(struct ifnet *ifp, int disable) 1371 { 1372 struct vte_softc *sc = ifp->if_softc; 1373 struct vte_txdesc *txd; 1374 struct vte_rxdesc *rxd; 1375 int i; 1376 1377 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1378 if ((ifp->if_flags & IFF_RUNNING) == 0) 1379 return; 1380 /* 1381 * Mark the interface down and cancel the watchdog timer. 1382 */ 1383 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1384 sc->vte_flags &= ~VTE_FLAG_LINK; 1385 callout_stop(&sc->vte_tick_ch); 1386 sc->vte_watchdog_timer = 0; 1387 vte_stats_update(sc); 1388 /* Disable interrupts. */ 1389 CSR_WRITE_2(sc, VTE_MIER, 0); 1390 CSR_WRITE_2(sc, VTE_MECIER, 0); 1391 /* Stop RX/TX MACs. */ 1392 vte_stop_mac(sc); 1393 /* Clear interrupts. */ 1394 CSR_READ_2(sc, VTE_MISR); 1395 /* 1396 * Free TX/RX mbufs still in the queues. 1397 */ 1398 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1399 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1400 if (rxd->rx_m != NULL) { 1401 bus_dmamap_sync(sc->vte_dmatag, 1402 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1403 BUS_DMASYNC_POSTREAD); 1404 bus_dmamap_unload(sc->vte_dmatag, 1405 rxd->rx_dmamap); 1406 m_freem(rxd->rx_m); 1407 rxd->rx_m = NULL; 1408 } 1409 } 1410 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1411 txd = &sc->vte_cdata.vte_txdesc[i]; 1412 if (txd->tx_m != NULL) { 1413 bus_dmamap_sync(sc->vte_dmatag, 1414 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1415 BUS_DMASYNC_POSTWRITE); 1416 bus_dmamap_unload(sc->vte_dmatag, 1417 txd->tx_dmamap); 1418 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1419 m_freem(txd->tx_m); 1420 txd->tx_m = NULL; 1421 txd->tx_flags &= ~VTE_TXMBUF; 1422 } 1423 } 1424 /* Free TX mbuf pools used for deep copy. */ 1425 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1426 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1427 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1428 sc->vte_cdata.vte_txmbufs[i] = NULL; 1429 } 1430 } 1431 } 1432 1433 static void 1434 vte_start_mac(struct vte_softc *sc) 1435 { 1436 struct ifnet *ifp = &sc->vte_if; 1437 uint16_t mcr; 1438 int i; 1439 1440 /* Enable RX/TX MACs. */ 1441 mcr = CSR_READ_2(sc, VTE_MCR0); 1442 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1443 (MCR0_RX_ENB | MCR0_TX_ENB) && 1444 (ifp->if_flags & IFF_RUNNING) != 0) { 1445 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1446 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1447 for (i = VTE_TIMEOUT; i > 0; i--) { 1448 mcr = CSR_READ_2(sc, VTE_MCR0); 1449 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1450 (MCR0_RX_ENB | MCR0_TX_ENB)) 1451 break; 1452 DELAY(10); 1453 } 1454 if (i == 0) 1455 aprint_error_dev(sc->vte_dev, 1456 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1457 } 1458 vte_rxfilter(sc); 1459 } 1460 1461 static void 1462 vte_stop_mac(struct vte_softc *sc) 1463 { 1464 uint16_t mcr; 1465 int i; 1466 1467 /* Disable RX/TX MACs. */ 1468 mcr = CSR_READ_2(sc, VTE_MCR0); 1469 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1470 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1471 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1472 for (i = VTE_TIMEOUT; i > 0; i--) { 1473 mcr = CSR_READ_2(sc, VTE_MCR0); 1474 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1475 break; 1476 DELAY(10); 1477 } 1478 if (i == 0) 1479 aprint_error_dev(sc->vte_dev, 1480 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1481 } 1482 } 1483 1484 static int 1485 vte_init_tx_ring(struct vte_softc *sc) 1486 { 1487 struct vte_tx_desc *desc; 1488 struct vte_txdesc *txd; 1489 bus_addr_t addr; 1490 int i; 1491 1492 sc->vte_cdata.vte_tx_prod = 0; 1493 sc->vte_cdata.vte_tx_cons = 0; 1494 sc->vte_cdata.vte_tx_cnt = 0; 1495 1496 /* Pre-allocate TX mbufs for deep copy. */ 1497 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1498 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1499 MT_DATA, M_PKTHDR); 1500 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1501 return (ENOBUFS); 1502 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1503 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1504 } 1505 desc = sc->vte_cdata.vte_tx_ring; 1506 bzero(desc, VTE_TX_RING_SZ); 1507 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1508 txd = &sc->vte_cdata.vte_txdesc[i]; 1509 txd->tx_m = NULL; 1510 if (i != VTE_TX_RING_CNT - 1) 1511 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1512 sizeof(struct vte_tx_desc) * (i + 1); 1513 else 1514 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1515 sizeof(struct vte_tx_desc) * 0; 1516 desc = &sc->vte_cdata.vte_tx_ring[i]; 1517 desc->dtnp = htole32(addr); 1518 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1519 txd->tx_desc = desc; 1520 } 1521 1522 bus_dmamap_sync(sc->vte_dmatag, 1523 sc->vte_cdata.vte_tx_ring_map, 0, 1524 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1525 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1526 return (0); 1527 } 1528 1529 static int 1530 vte_init_rx_ring(struct vte_softc *sc) 1531 { 1532 struct vte_rx_desc *desc; 1533 struct vte_rxdesc *rxd; 1534 bus_addr_t addr; 1535 int i; 1536 1537 sc->vte_cdata.vte_rx_cons = 0; 1538 desc = sc->vte_cdata.vte_rx_ring; 1539 bzero(desc, VTE_RX_RING_SZ); 1540 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1541 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1542 rxd->rx_m = NULL; 1543 if (i != VTE_RX_RING_CNT - 1) 1544 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1545 + sizeof(struct vte_rx_desc) * (i + 1); 1546 else 1547 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1548 + sizeof(struct vte_rx_desc) * 0; 1549 desc = &sc->vte_cdata.vte_rx_ring[i]; 1550 desc->drnp = htole32(addr); 1551 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1552 rxd->rx_desc = desc; 1553 if (vte_newbuf(sc, rxd) != 0) 1554 return (ENOBUFS); 1555 } 1556 1557 bus_dmamap_sync(sc->vte_dmatag, 1558 sc->vte_cdata.vte_rx_ring_map, 0, 1559 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1561 1562 return (0); 1563 } 1564 1565 static void 1566 vte_rxfilter(struct vte_softc *sc) 1567 { 1568 struct ethercom *ec = &sc->vte_ec; 1569 struct ether_multistep step; 1570 struct ether_multi *enm; 1571 struct ifnet *ifp; 1572 uint8_t *eaddr; 1573 uint32_t crc; 1574 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1575 uint16_t mchash[4], mcr; 1576 int i, nperf; 1577 1578 ifp = &sc->vte_if; 1579 1580 DPRINTF(("vte_rxfilter\n")); 1581 memset(mchash, 0, sizeof(mchash)); 1582 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1583 rxfilt_perf[i][0] = 0xFFFF; 1584 rxfilt_perf[i][1] = 0xFFFF; 1585 rxfilt_perf[i][2] = 0xFFFF; 1586 } 1587 1588 mcr = CSR_READ_2(sc, VTE_MCR0); 1589 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1590 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST); 1591 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1592 mcr |= MCR0_BROADCAST_DIS; 1593 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1594 if ((ifp->if_flags & IFF_PROMISC) != 0) 1595 mcr |= MCR0_PROMISC; 1596 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1597 mcr |= MCR0_MULTICAST; 1598 mchash[0] = 0xFFFF; 1599 mchash[1] = 0xFFFF; 1600 mchash[2] = 0xFFFF; 1601 mchash[3] = 0xFFFF; 1602 goto chipit; 1603 } 1604 1605 ETHER_LOCK(ec); 1606 ETHER_FIRST_MULTI(step, ec, enm); 1607 nperf = 0; 1608 while (enm != NULL) { 1609 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) 1610 != 0) { 1611 sc->vte_if.if_flags |= IFF_ALLMULTI; 1612 mcr |= MCR0_MULTICAST; 1613 mchash[0] = 0xFFFF; 1614 mchash[1] = 0xFFFF; 1615 mchash[2] = 0xFFFF; 1616 mchash[3] = 0xFFFF; 1617 ETHER_UNLOCK(ec); 1618 goto chipit; 1619 } 1620 /* 1621 * Program the first 3 multicast groups into 1622 * the perfect filter. For all others, use the 1623 * hash table. 1624 */ 1625 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1626 eaddr = enm->enm_addrlo; 1627 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1628 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1629 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1630 nperf++; 1631 } else { 1632 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1633 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1634 } 1635 ETHER_NEXT_MULTI(step, enm); 1636 } 1637 ETHER_UNLOCK(ec); 1638 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1639 mchash[3] != 0) 1640 mcr |= MCR0_MULTICAST; 1641 1642 chipit: 1643 /* Program multicast hash table. */ 1644 DPRINTF(("chipit write multicast\n")); 1645 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1646 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1647 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1648 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1649 /* Program perfect filter table. */ 1650 DPRINTF(("chipit write perfect filter\n")); 1651 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1652 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1653 rxfilt_perf[i][0]); 1654 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1655 rxfilt_perf[i][1]); 1656 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1657 rxfilt_perf[i][2]); 1658 } 1659 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1660 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1661 DPRINTF(("chipit read mcro\n")); 1662 CSR_READ_2(sc, VTE_MCR0); 1663 DPRINTF(("chipit done\n")); 1664 } 1665 1666 /* 1667 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1668 * set up in vte_pci_attach() 1669 */ 1670 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1671 { 1672 int rc; 1673 const struct sysctlnode *node; 1674 1675 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1676 0, CTLTYPE_NODE, "vte", 1677 SYSCTL_DESCR("vte interface controls"), 1678 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1679 goto err; 1680 } 1681 1682 vte_root_num = node->sysctl_num; 1683 return; 1684 1685 err: 1686 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1687 } 1688 1689 static int 1690 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1691 { 1692 int error, t; 1693 struct sysctlnode node; 1694 struct vte_softc *sc; 1695 1696 node = *rnode; 1697 sc = node.sysctl_data; 1698 t = sc->vte_int_rx_mod; 1699 node.sysctl_data = &t; 1700 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1701 if (error || newp == NULL) 1702 return error; 1703 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1704 return EINVAL; 1705 1706 sc->vte_int_rx_mod = t; 1707 vte_miibus_statchg(&sc->vte_if); 1708 return 0; 1709 } 1710 1711 static int 1712 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1713 { 1714 int error, t; 1715 struct sysctlnode node; 1716 struct vte_softc *sc; 1717 1718 node = *rnode; 1719 sc = node.sysctl_data; 1720 t = sc->vte_int_tx_mod; 1721 node.sysctl_data = &t; 1722 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1723 if (error || newp == NULL) 1724 return error; 1725 1726 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1727 return EINVAL; 1728 sc->vte_int_tx_mod = t; 1729 vte_miibus_statchg(&sc->vte_if); 1730 return 0; 1731 } 1732
Indexes created Thu Oct 02 01:09:59 GMT 2025