if_vte.c revision 1.34
1 /* $NetBSD: if_vte.c,v 1.34 2022/09/17 15:31:29 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2010, Pyun YongHyeon <yongari (at) FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 54 55 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.34 2022/09/17 15:31:29 thorpej Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/mbuf.h> 63 #include <sys/protosw.h> 64 #include <sys/socket.h> 65 #include <sys/ioctl.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_dl.h> 76 #include <net/route.h> 77 #include <net/bpf.h> 78 79 #include <sys/rndsource.h> 80 81 #include "opt_inet.h" 82 #include <net/if_ether.h> 83 #ifdef INET 84 #include <netinet/in.h> 85 #include <netinet/in_systm.h> 86 #include <netinet/in_var.h> 87 #include <netinet/ip.h> 88 #include <netinet/if_inarp.h> 89 #endif 90 91 #include <sys/bus.h> 92 #include <sys/intr.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcidevs.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <dev/pci/if_vtereg.h> 102 #include <dev/pci/if_vtevar.h> 103 104 static int vte_match(device_t, cfdata_t, void *); 105 static void vte_attach(device_t, device_t, void *); 106 static int vte_detach(device_t, int); 107 static int vte_dma_alloc(struct vte_softc *); 108 static void vte_dma_free(struct vte_softc *); 109 static struct vte_txdesc * 110 vte_encap(struct vte_softc *, struct mbuf **); 111 static void vte_get_macaddr(struct vte_softc *); 112 static int vte_init(struct ifnet *); 113 static int vte_init_rx_ring(struct vte_softc *); 114 static int vte_init_tx_ring(struct vte_softc *); 115 static int vte_intr(void *); 116 static int vte_ifioctl(struct ifnet *, u_long, void *); 117 static void vte_mac_config(struct vte_softc *); 118 static int vte_miibus_readreg(device_t, int, int, uint16_t *); 119 static void vte_miibus_statchg(struct ifnet *); 120 static int vte_miibus_writereg(device_t, int, int, uint16_t); 121 static int vte_mediachange(struct ifnet *); 122 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 123 static void vte_reset(struct vte_softc *); 124 static void vte_rxeof(struct vte_softc *); 125 static void vte_rxfilter(struct vte_softc *); 126 static bool vte_shutdown(device_t, int); 127 static bool vte_suspend(device_t, const pmf_qual_t *); 128 static bool vte_resume(device_t, const pmf_qual_t *); 129 static void vte_ifstart(struct ifnet *); 130 static void vte_start_mac(struct vte_softc *); 131 static void vte_stats_clear(struct vte_softc *); 132 static void vte_stats_update(struct vte_softc *); 133 static void vte_stop(struct ifnet *, int); 134 static void vte_stop_mac(struct vte_softc *); 135 static void vte_tick(void *); 136 static void vte_txeof(struct vte_softc *); 137 static void vte_ifwatchdog(struct ifnet *); 138 139 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 140 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 141 static int vte_root_num; 142 143 #define DPRINTF(a) 144 145 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 146 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 147 148 149 static int 150 vte_match(device_t parent, cfdata_t cf, void *aux) 151 { 152 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 153 154 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 155 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 156 return 1; 157 158 return 0; 159 } 160 161 static void 162 vte_attach(device_t parent, device_t self, void *aux) 163 { 164 struct vte_softc *sc = device_private(self); 165 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 166 struct ifnet * const ifp = &sc->vte_if; 167 struct mii_data * const mii = &sc->vte_mii; 168 int h_valid; 169 pcireg_t reg, csr; 170 pci_intr_handle_t intrhandle; 171 const char *intrstr; 172 int error; 173 const struct sysctlnode *node; 174 int vte_nodenum; 175 char intrbuf[PCI_INTRSTR_LEN]; 176 177 sc->vte_dev = self; 178 179 callout_init(&sc->vte_tick_ch, 0); 180 callout_setfunc(&sc->vte_tick_ch, vte_tick, sc); 181 182 /* Map the device. */ 183 h_valid = 0; 184 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 185 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 186 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 187 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 188 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 189 } 190 if (h_valid == 0) { 191 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 192 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 193 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 194 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 195 &sc->vte_bushandle, NULL, NULL) == 0); 196 } 197 } 198 if (h_valid == 0) { 199 aprint_error_dev(self, "unable to map device registers\n"); 200 return; 201 } 202 sc->vte_dmatag = pa->pa_dmat; 203 /* Enable the device. */ 204 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 205 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 206 csr | PCI_COMMAND_MASTER_ENABLE); 207 208 pci_aprint_devinfo(pa, NULL); 209 210 /* Reset the ethernet controller. */ 211 vte_reset(sc); 212 213 if ((error = vte_dma_alloc(sc)) != 0) 214 return; 215 216 /* Load station address. */ 217 vte_get_macaddr(sc); 218 219 aprint_normal_dev(self, "Ethernet address %s\n", 220 ether_sprintf(sc->vte_eaddr)); 221 222 /* Map and establish interrupts */ 223 if (pci_intr_map(pa, &intrhandle)) { 224 aprint_error_dev(self, "couldn't map interrupt\n"); 225 return; 226 } 227 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 228 sizeof(intrbuf)); 229 sc->vte_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 230 vte_intr, sc, device_xname(self)); 231 if (sc->vte_ih == NULL) { 232 aprint_error_dev(self, "couldn't establish interrupt"); 233 if (intrstr != NULL) 234 aprint_error(" at %s", intrstr); 235 aprint_error("\n"); 236 return; 237 } 238 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 239 240 sc->vte_if.if_softc = sc; 241 mii->mii_ifp = ifp; 242 mii->mii_readreg = vte_miibus_readreg; 243 mii->mii_writereg = vte_miibus_writereg; 244 mii->mii_statchg = vte_miibus_statchg; 245 sc->vte_ec.ec_mii = mii; 246 ifmedia_init(&mii->mii_media, IFM_IMASK, vte_mediachange, 247 ether_mediastatus); 248 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 249 MII_OFFSET_ANY, 0); 250 if (LIST_FIRST(&mii->mii_phys) == NULL) { 251 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 252 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 253 } else 254 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 255 256 /* 257 * We can support 802.1Q VLAN-sized frames. 258 */ 259 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 260 261 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 262 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 263 ifp->if_ioctl = vte_ifioctl; 264 ifp->if_start = vte_ifstart; 265 ifp->if_watchdog = vte_ifwatchdog; 266 ifp->if_init = vte_init; 267 ifp->if_stop = vte_stop; 268 ifp->if_timer = 0; 269 IFQ_SET_READY(&ifp->if_snd); 270 if_attach(ifp); 271 if_deferred_start_init(ifp, NULL); 272 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 273 274 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 275 pmf_class_network_register(self, ifp); 276 else 277 aprint_error_dev(self, "couldn't establish power handler\n"); 278 279 rnd_attach_source(&sc->rnd_source, device_xname(self), 280 RND_TYPE_NET, RND_FLAG_DEFAULT); 281 282 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 283 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 284 SYSCTL_DESCR("vte per-controller controls"), 285 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 286 CTL_EOL) != 0) { 287 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 288 return; 289 } 290 vte_nodenum = node->sysctl_num; 291 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 292 CTLFLAG_READWRITE, 293 CTLTYPE_INT, "int_rxct", 294 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 295 vte_sysctl_intrxct, 0, (void *)sc, 296 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 297 CTL_EOL) != 0) { 298 aprint_normal_dev(sc->vte_dev, 299 "couldn't create int_rxct sysctl node\n"); 300 } 301 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 302 CTLFLAG_READWRITE, 303 CTLTYPE_INT, "int_txct", 304 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 305 vte_sysctl_inttxct, 0, (void *)sc, 306 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 307 CTL_EOL) != 0) { 308 aprint_normal_dev(sc->vte_dev, 309 "couldn't create int_txct sysctl node\n"); 310 } 311 } 312 313 static int 314 vte_detach(device_t dev, int flags __unused) 315 { 316 struct vte_softc *sc = device_private(dev); 317 struct ifnet *ifp = &sc->vte_if; 318 int s; 319 320 s = splnet(); 321 /* Stop the interface. Callouts are stopped in it. */ 322 vte_stop(ifp, 1); 323 splx(s); 324 325 pmf_device_deregister(dev); 326 327 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 328 329 ether_ifdetach(ifp); 330 if_detach(ifp); 331 ifmedia_fini(&sc->vte_mii.mii_media); 332 333 vte_dma_free(sc); 334 335 return (0); 336 } 337 338 static int 339 vte_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 340 { 341 struct vte_softc *sc = device_private(dev); 342 int i; 343 344 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 345 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 346 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 347 DELAY(5); 348 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 349 break; 350 } 351 352 if (i == 0) { 353 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 354 return ETIMEDOUT; 355 } 356 357 *val = CSR_READ_2(sc, VTE_MMRD); 358 return 0; 359 } 360 361 static int 362 vte_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 363 { 364 struct vte_softc *sc = device_private(dev); 365 int i; 366 367 CSR_WRITE_2(sc, VTE_MMWD, val); 368 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 369 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 370 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 371 DELAY(5); 372 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 373 break; 374 } 375 376 if (i == 0) { 377 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 378 return ETIMEDOUT; 379 } 380 381 return 0; 382 } 383 384 static void 385 vte_miibus_statchg(struct ifnet *ifp) 386 { 387 struct vte_softc *sc = ifp->if_softc; 388 uint16_t val; 389 390 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 391 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 392 393 sc->vte_flags &= ~VTE_FLAG_LINK; 394 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 395 (IFM_ACTIVE | IFM_AVALID)) { 396 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 397 case IFM_10_T: 398 case IFM_100_TX: 399 sc->vte_flags |= VTE_FLAG_LINK; 400 break; 401 default: 402 break; 403 } 404 } 405 406 /* Stop RX/TX MACs. */ 407 vte_stop_mac(sc); 408 /* Program MACs with resolved duplex and flow control. */ 409 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 410 /* 411 * Timer waiting time : (63 + TIMER * 64) MII clock. 412 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 413 */ 414 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 415 val = 18 << VTE_IM_TIMER_SHIFT; 416 else 417 val = 1 << VTE_IM_TIMER_SHIFT; 418 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 419 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 420 CSR_WRITE_2(sc, VTE_MRICR, val); 421 422 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 423 val = 18 << VTE_IM_TIMER_SHIFT; 424 else 425 val = 1 << VTE_IM_TIMER_SHIFT; 426 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 427 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 428 CSR_WRITE_2(sc, VTE_MTICR, val); 429 430 vte_mac_config(sc); 431 vte_start_mac(sc); 432 DPRINTF(("vte_miibus_statchg: link\n")); 433 } 434 } 435 436 static void 437 vte_get_macaddr(struct vte_softc *sc) 438 { 439 uint16_t mid; 440 441 /* 442 * It seems there is no way to reload station address and 443 * it is supposed to be set by BIOS. 444 */ 445 mid = CSR_READ_2(sc, VTE_MID0L); 446 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 447 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 448 mid = CSR_READ_2(sc, VTE_MID0M); 449 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 450 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 451 mid = CSR_READ_2(sc, VTE_MID0H); 452 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 453 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 454 } 455 456 457 static int 458 vte_dma_alloc(struct vte_softc *sc) 459 { 460 struct vte_txdesc *txd; 461 struct vte_rxdesc *rxd; 462 int error, i, rseg; 463 464 /* create DMA map for TX ring */ 465 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 466 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 467 &sc->vte_cdata.vte_tx_ring_map); 468 if (error) { 469 aprint_error_dev(sc->vte_dev, 470 "could not create dma map for TX ring (%d)\n", 471 error); 472 goto fail; 473 } 474 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 475 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 476 VTE_TX_RING_ALIGN, 0, 477 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 478 BUS_DMA_NOWAIT); 479 if (error != 0) { 480 aprint_error_dev(sc->vte_dev, 481 "could not allocate DMA'able memory for TX ring (%d).\n", 482 error); 483 goto fail; 484 } 485 KASSERT(rseg == 1); 486 error = bus_dmamem_map(sc->vte_dmatag, 487 sc->vte_cdata.vte_tx_ring_seg, 1, 488 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 489 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 490 if (error != 0) { 491 aprint_error_dev(sc->vte_dev, 492 "could not map DMA'able memory for TX ring (%d).\n", 493 error); 494 goto fail; 495 } 496 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 497 error = bus_dmamap_load(sc->vte_dmatag, 498 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 499 VTE_TX_RING_SZ, NULL, 500 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 501 if (error != 0) { 502 aprint_error_dev(sc->vte_dev, 503 "could not load DMA'able memory for TX ring.\n"); 504 goto fail; 505 } 506 507 /* create DMA map for RX ring */ 508 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 509 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 510 &sc->vte_cdata.vte_rx_ring_map); 511 if (error) { 512 aprint_error_dev(sc->vte_dev, 513 "could not create dma map for RX ring (%d)\n", 514 error); 515 goto fail; 516 } 517 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 518 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 519 VTE_RX_RING_ALIGN, 0, 520 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 521 BUS_DMA_NOWAIT); 522 if (error != 0) { 523 aprint_error_dev(sc->vte_dev, 524 "could not allocate DMA'able memory for RX ring (%d).\n", 525 error); 526 goto fail; 527 } 528 KASSERT(rseg == 1); 529 error = bus_dmamem_map(sc->vte_dmatag, 530 sc->vte_cdata.vte_rx_ring_seg, 1, 531 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 532 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 533 if (error != 0) { 534 aprint_error_dev(sc->vte_dev, 535 "could not map DMA'able memory for RX ring (%d).\n", 536 error); 537 goto fail; 538 } 539 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 540 error = bus_dmamap_load(sc->vte_dmatag, 541 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 542 VTE_RX_RING_SZ, NULL, 543 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 544 if (error != 0) { 545 aprint_error_dev(sc->vte_dev, 546 "could not load DMA'able memory for RX ring (%d).\n", 547 error); 548 goto fail; 549 } 550 551 /* Create DMA maps for TX buffers. */ 552 for (i = 0; i < VTE_TX_RING_CNT; i++) { 553 txd = &sc->vte_cdata.vte_txdesc[i]; 554 txd->tx_m = NULL; 555 txd->tx_dmamap = NULL; 556 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 557 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 558 &txd->tx_dmamap); 559 if (error != 0) { 560 aprint_error_dev(sc->vte_dev, 561 "could not create TX DMA map %d (%d).\n", i, error); 562 goto fail; 563 } 564 } 565 /* Create DMA maps for RX buffers. */ 566 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 567 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 568 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 569 aprint_error_dev(sc->vte_dev, 570 "could not create spare RX dmamap (%d).\n", error); 571 goto fail; 572 } 573 for (i = 0; i < VTE_RX_RING_CNT; i++) { 574 rxd = &sc->vte_cdata.vte_rxdesc[i]; 575 rxd->rx_m = NULL; 576 rxd->rx_dmamap = NULL; 577 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 578 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 579 &rxd->rx_dmamap); 580 if (error != 0) { 581 aprint_error_dev(sc->vte_dev, 582 "could not create RX dmamap %d (%d).\n", i, error); 583 goto fail; 584 } 585 } 586 return 0; 587 588 fail: 589 vte_dma_free(sc); 590 return (error); 591 } 592 593 static void 594 vte_dma_free(struct vte_softc *sc) 595 { 596 struct vte_txdesc *txd; 597 struct vte_rxdesc *rxd; 598 int i; 599 600 /* TX buffers. */ 601 for (i = 0; i < VTE_TX_RING_CNT; i++) { 602 txd = &sc->vte_cdata.vte_txdesc[i]; 603 if (txd->tx_dmamap != NULL) { 604 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 605 txd->tx_dmamap = NULL; 606 } 607 } 608 /* RX buffers */ 609 for (i = 0; i < VTE_RX_RING_CNT; i++) { 610 rxd = &sc->vte_cdata.vte_rxdesc[i]; 611 if (rxd->rx_dmamap != NULL) { 612 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 613 rxd->rx_dmamap = NULL; 614 } 615 } 616 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 617 bus_dmamap_destroy(sc->vte_dmatag, 618 sc->vte_cdata.vte_rx_sparemap); 619 sc->vte_cdata.vte_rx_sparemap = NULL; 620 } 621 /* TX descriptor ring. */ 622 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 623 bus_dmamap_unload(sc->vte_dmatag, 624 sc->vte_cdata.vte_tx_ring_map); 625 bus_dmamap_destroy(sc->vte_dmatag, 626 sc->vte_cdata.vte_tx_ring_map); 627 } 628 if (sc->vte_cdata.vte_tx_ring != NULL) { 629 bus_dmamem_unmap(sc->vte_dmatag, 630 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 631 bus_dmamem_free(sc->vte_dmatag, 632 sc->vte_cdata.vte_tx_ring_seg, 1); 633 } 634 sc->vte_cdata.vte_tx_ring = NULL; 635 sc->vte_cdata.vte_tx_ring_map = NULL; 636 /* RX ring. */ 637 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 638 bus_dmamap_unload(sc->vte_dmatag, 639 sc->vte_cdata.vte_rx_ring_map); 640 bus_dmamap_destroy(sc->vte_dmatag, 641 sc->vte_cdata.vte_rx_ring_map); 642 } 643 if (sc->vte_cdata.vte_rx_ring != NULL) { 644 bus_dmamem_unmap(sc->vte_dmatag, 645 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 646 bus_dmamem_free(sc->vte_dmatag, 647 sc->vte_cdata.vte_rx_ring_seg, 1); 648 } 649 sc->vte_cdata.vte_rx_ring = NULL; 650 sc->vte_cdata.vte_rx_ring_map = NULL; 651 } 652 653 static bool 654 vte_shutdown(device_t dev, int howto) 655 { 656 657 return (vte_suspend(dev, NULL)); 658 } 659 660 static bool 661 vte_suspend(device_t dev, const pmf_qual_t *qual) 662 { 663 struct vte_softc *sc = device_private(dev); 664 struct ifnet *ifp = &sc->vte_if; 665 666 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 667 if ((ifp->if_flags & IFF_RUNNING) != 0) 668 vte_stop(ifp, 1); 669 return (0); 670 } 671 672 static bool 673 vte_resume(device_t dev, const pmf_qual_t *qual) 674 { 675 struct vte_softc *sc = device_private(dev); 676 struct ifnet *ifp; 677 678 ifp = &sc->vte_if; 679 if ((ifp->if_flags & IFF_UP) != 0) { 680 ifp->if_flags &= ~IFF_RUNNING; 681 vte_init(ifp); 682 } 683 684 return (0); 685 } 686 687 static struct vte_txdesc * 688 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 689 { 690 struct vte_txdesc *txd; 691 struct mbuf *m, *n; 692 int copy, error, padlen; 693 694 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 695 m = *m_head; 696 /* 697 * Controller doesn't auto-pad, so we have to make sure pad 698 * short frames out to the minimum frame length. 699 */ 700 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 701 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 702 else 703 padlen = 0; 704 705 /* 706 * Controller does not support multi-fragmented TX buffers. 707 * Controller spends most of its TX processing time in 708 * de-fragmenting TX buffers. Either faster CPU or more 709 * advanced controller DMA engine is required to speed up 710 * TX path processing. 711 * To mitigate the de-fragmenting issue, perform deep copy 712 * from fragmented mbuf chains to a pre-allocated mbuf 713 * cluster with extra cost of kernel memory. For frames 714 * that is composed of single TX buffer, the deep copy is 715 * bypassed. 716 */ 717 copy = 0; 718 if (m->m_next != NULL) 719 copy++; 720 if (padlen > 0 && (M_READONLY(m) || 721 padlen > M_TRAILINGSPACE(m))) 722 copy++; 723 if (copy != 0) { 724 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 725 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 726 n->m_pkthdr.len = m->m_pkthdr.len; 727 n->m_len = m->m_pkthdr.len; 728 m = n; 729 txd->tx_flags |= VTE_TXMBUF; 730 } 731 732 if (padlen > 0) { 733 /* Zero out the bytes in the pad area. */ 734 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 735 m->m_pkthdr.len += padlen; 736 m->m_len = m->m_pkthdr.len; 737 } 738 739 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 740 BUS_DMA_NOWAIT); 741 if (error != 0) { 742 txd->tx_flags &= ~VTE_TXMBUF; 743 return (NULL); 744 } 745 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 746 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 747 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 748 749 txd->tx_desc->dtlen = 750 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 751 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 752 sc->vte_cdata.vte_tx_cnt++; 753 /* Update producer index. */ 754 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 755 756 /* Finally hand over ownership to controller. */ 757 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 758 txd->tx_m = m; 759 760 return (txd); 761 } 762 763 static void 764 vte_ifstart(struct ifnet *ifp) 765 { 766 struct vte_softc *sc = ifp->if_softc; 767 struct vte_txdesc *txd; 768 struct mbuf *m_head, *m; 769 int enq; 770 771 ifp = &sc->vte_if; 772 773 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 774 775 if ((ifp->if_flags & IFF_RUNNING) == 0) { 776 return; 777 } 778 if ((sc->vte_flags & VTE_FLAG_LINK) == 0) { 779 return; 780 } 781 782 /* Reserve one free TX descriptor. */ 783 for (enq = 0; sc->vte_cdata.vte_tx_cnt < VTE_TX_RING_CNT - 1; ) { 784 IFQ_POLL(&ifp->if_snd, m_head); 785 if (m_head == NULL) 786 break; 787 /* 788 * Pack the data into the transmit ring. 789 */ 790 DPRINTF(("vte_encap:")); 791 if ((txd = vte_encap(sc, &m_head)) == NULL) { 792 DPRINTF((" failed\n")); 793 break; 794 } 795 DPRINTF((" ok\n")); 796 IFQ_DEQUEUE(&ifp->if_snd, m); 797 KASSERT(m == m_head); 798 799 enq++; 800 /* 801 * If there's a BPF listener, bounce a copy of this frame 802 * to him. 803 */ 804 bpf_mtap(ifp, m_head, BPF_D_OUT); 805 /* Free consumed TX frame. */ 806 if ((txd->tx_flags & VTE_TXMBUF) != 0) 807 m_freem(m_head); 808 } 809 810 if (enq > 0) { 811 bus_dmamap_sync(sc->vte_dmatag, 812 sc->vte_cdata.vte_tx_ring_map, 0, 813 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 815 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 816 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 817 } 818 } 819 820 static void 821 vte_ifwatchdog(struct ifnet *ifp) 822 { 823 struct vte_softc *sc = ifp->if_softc; 824 825 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 826 return; 827 828 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 829 if_statinc(ifp, if_oerrors); 830 vte_init(ifp); 831 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 832 vte_ifstart(ifp); 833 } 834 835 static int 836 vte_mediachange(struct ifnet *ifp) 837 { 838 int error; 839 struct vte_softc *sc = ifp->if_softc; 840 841 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 842 error = 0; 843 else if (error != 0) { 844 aprint_error_dev(sc->vte_dev, "could not set media\n"); 845 return error; 846 } 847 return 0; 848 849 } 850 851 static int 852 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 853 { 854 struct vte_softc *sc = ifp->if_softc; 855 int error, s; 856 857 s = splnet(); 858 error = ether_ioctl(ifp, cmd, data); 859 if (error == ENETRESET) { 860 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 861 if (ifp->if_flags & IFF_RUNNING) 862 vte_rxfilter(sc); 863 error = 0; 864 } 865 splx(s); 866 return error; 867 } 868 869 static void 870 vte_mac_config(struct vte_softc *sc) 871 { 872 uint16_t mcr; 873 874 mcr = CSR_READ_2(sc, VTE_MCR0); 875 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 876 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 877 mcr |= MCR0_FULL_DUPLEX; 878 #ifdef notyet 879 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 880 mcr |= MCR0_FC_ENB; 881 /* 882 * The data sheet is not clear whether the controller 883 * honors received pause frames or not. The is no 884 * separate control bit for RX pause frame so just 885 * enable MCR0_FC_ENB bit. 886 */ 887 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 888 mcr |= MCR0_FC_ENB; 889 #endif 890 } 891 CSR_WRITE_2(sc, VTE_MCR0, mcr); 892 } 893 894 static void 895 vte_stats_clear(struct vte_softc *sc) 896 { 897 898 /* Reading counter registers clears its contents. */ 899 CSR_READ_2(sc, VTE_CNT_RX_DONE); 900 CSR_READ_2(sc, VTE_CNT_MECNT0); 901 CSR_READ_2(sc, VTE_CNT_MECNT1); 902 CSR_READ_2(sc, VTE_CNT_MECNT2); 903 CSR_READ_2(sc, VTE_CNT_MECNT3); 904 CSR_READ_2(sc, VTE_CNT_TX_DONE); 905 CSR_READ_2(sc, VTE_CNT_MECNT4); 906 CSR_READ_2(sc, VTE_CNT_PAUSE); 907 } 908 909 static void 910 vte_stats_update(struct vte_softc *sc) 911 { 912 struct vte_hw_stats *stat; 913 struct ifnet *ifp = &sc->vte_if; 914 uint16_t value; 915 916 stat = &sc->vte_stats; 917 918 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 919 920 CSR_READ_2(sc, VTE_MECISR); 921 922 /* RX stats. */ 923 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 924 925 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 926 stat->rx_bcast_frames += (value >> 8); 927 stat->rx_mcast_frames += (value & 0xFF); 928 929 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 930 if_statadd_ref(nsr, if_ierrors, 931 (value >> 8) + /* rx_runts */ 932 (value & 0xFF)); /* rx_crcerrs */ 933 934 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 935 if_statadd_ref(nsr, if_ierrors, 936 (value & 0xFF)); /* rx_long_frames */ 937 938 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 939 if_statadd_ref(nsr, if_ierrors, 940 (value >> 8)); /* rx_fifo_full */ 941 stat->rx_desc_unavail += (value & 0xFF); 942 943 /* TX stats. */ 944 if_statadd_ref(nsr, if_opackets, 945 CSR_READ_2(sc, VTE_CNT_TX_DONE)); /* tx_frames */ 946 947 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 948 if_statadd_ref(nsr, if_oerrors, 949 (value >> 8) + /* tx_underruns */ 950 (value & 0xFF)); /* tx_late_colls */ 951 952 /* Pause stats. */ 953 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 954 stat->tx_pause_frames += (value >> 8); 955 stat->rx_pause_frames += (value & 0xFF); 956 957 IF_STAT_PUTREF(ifp); 958 } 959 960 static int 961 vte_intr(void *arg) 962 { 963 struct vte_softc *sc = (struct vte_softc *)arg; 964 struct ifnet *ifp = &sc->vte_if; 965 uint16_t status; 966 int n; 967 968 /* Reading VTE_MISR acknowledges interrupts. */ 969 status = CSR_READ_2(sc, VTE_MISR); 970 DPRINTF(("vte_intr status 0x%x\n", status)); 971 if ((status & VTE_INTRS) == 0) { 972 /* Not ours. */ 973 return 0; 974 } 975 976 /* Disable interrupts. */ 977 CSR_WRITE_2(sc, VTE_MIER, 0); 978 for (n = 8; (status & VTE_INTRS) != 0;) { 979 if ((ifp->if_flags & IFF_RUNNING) == 0) 980 break; 981 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 982 MISR_RX_FIFO_FULL)) != 0) 983 vte_rxeof(sc); 984 if ((status & MISR_TX_DONE) != 0) 985 vte_txeof(sc); 986 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 987 vte_stats_update(sc); 988 if_schedule_deferred_start(ifp); 989 if (--n > 0) 990 status = CSR_READ_2(sc, VTE_MISR); 991 else 992 break; 993 } 994 995 if ((ifp->if_flags & IFF_RUNNING) != 0) { 996 /* Re-enable interrupts. */ 997 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 998 } 999 return 1; 1000 } 1001 1002 static void 1003 vte_txeof(struct vte_softc *sc) 1004 { 1005 struct ifnet *ifp; 1006 struct vte_txdesc *txd; 1007 uint16_t status; 1008 int cons, prog; 1009 1010 ifp = &sc->vte_if; 1011 1012 if (sc->vte_cdata.vte_tx_cnt == 0) 1013 return; 1014 bus_dmamap_sync(sc->vte_dmatag, 1015 sc->vte_cdata.vte_tx_ring_map, 0, 1016 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1017 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1018 cons = sc->vte_cdata.vte_tx_cons; 1019 /* 1020 * Go through our TX list and free mbufs for those 1021 * frames which have been transmitted. 1022 */ 1023 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1024 txd = &sc->vte_cdata.vte_txdesc[cons]; 1025 status = le16toh(txd->tx_desc->dtst); 1026 if ((status & VTE_DTST_TX_OWN) != 0) 1027 break; 1028 if ((status & VTE_DTST_TX_OK) != 0) 1029 if_statadd(ifp, if_collisions, (status & 0xf)); 1030 sc->vte_cdata.vte_tx_cnt--; 1031 /* Reclaim transmitted mbufs. */ 1032 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1033 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1034 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1035 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1036 m_freem(txd->tx_m); 1037 txd->tx_flags &= ~VTE_TXMBUF; 1038 txd->tx_m = NULL; 1039 prog++; 1040 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1041 } 1042 1043 if (prog > 0) { 1044 sc->vte_cdata.vte_tx_cons = cons; 1045 /* 1046 * Unarm watchdog timer only when there is no pending 1047 * frames in TX queue. 1048 */ 1049 if (sc->vte_cdata.vte_tx_cnt == 0) 1050 sc->vte_watchdog_timer = 0; 1051 } 1052 } 1053 1054 static int 1055 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1056 { 1057 struct mbuf *m; 1058 bus_dmamap_t map; 1059 1060 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1061 if (m == NULL) 1062 return (ENOBUFS); 1063 m->m_len = m->m_pkthdr.len = MCLBYTES; 1064 m_adj(m, sizeof(uint32_t)); 1065 1066 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1067 sc->vte_cdata.vte_rx_sparemap, m, BUS_DMA_NOWAIT) != 0) { 1068 m_freem(m); 1069 return (ENOBUFS); 1070 } 1071 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1072 1073 if (rxd->rx_m != NULL) { 1074 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1075 0, rxd->rx_dmamap->dm_mapsize, 1076 BUS_DMASYNC_POSTREAD); 1077 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1078 } 1079 map = rxd->rx_dmamap; 1080 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1081 sc->vte_cdata.vte_rx_sparemap = map; 1082 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1083 0, rxd->rx_dmamap->dm_mapsize, 1084 BUS_DMASYNC_PREREAD); 1085 rxd->rx_m = m; 1086 rxd->rx_desc->drbp = 1087 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1088 rxd->rx_desc->drlen = htole16( 1089 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1090 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, 1091 (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, 1092 rxd->rx_dmamap->dm_segs[0].ds_len)); 1093 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1094 1095 return (0); 1096 } 1097 1098 static void 1099 vte_rxeof(struct vte_softc *sc) 1100 { 1101 struct ifnet *ifp; 1102 struct vte_rxdesc *rxd; 1103 struct mbuf *m; 1104 uint16_t status, total_len; 1105 int cons, prog; 1106 1107 bus_dmamap_sync(sc->vte_dmatag, 1108 sc->vte_cdata.vte_rx_ring_map, 0, 1109 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1110 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1111 cons = sc->vte_cdata.vte_rx_cons; 1112 ifp = &sc->vte_if; 1113 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1114 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1115 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1116 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1117 status = le16toh(rxd->rx_desc->drst); 1118 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", 1119 cons, rxd, rxd->rx_m, status, 1120 VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1121 if ((status & VTE_DRST_RX_OWN) != 0) 1122 break; 1123 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1124 m = rxd->rx_m; 1125 if ((status & VTE_DRST_RX_OK) == 0) { 1126 /* Discard errored frame. */ 1127 rxd->rx_desc->drlen = 1128 htole16(MCLBYTES - sizeof(uint32_t)); 1129 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1130 continue; 1131 } 1132 if (vte_newbuf(sc, rxd) != 0) { 1133 DPRINTF(("vte_rxeof newbuf failed\n")); 1134 if_statinc(ifp, if_ierrors); 1135 rxd->rx_desc->drlen = 1136 htole16(MCLBYTES - sizeof(uint32_t)); 1137 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1138 continue; 1139 } 1140 1141 /* 1142 * It seems there is no way to strip FCS bytes. 1143 */ 1144 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1145 m_set_rcvif(m, ifp); 1146 if_percpuq_enqueue(ifp->if_percpuq, m); 1147 } 1148 1149 if (prog > 0) { 1150 /* Update the consumer index. */ 1151 sc->vte_cdata.vte_rx_cons = cons; 1152 /* 1153 * Sync updated RX descriptors such that controller see 1154 * modified RX buffer addresses. 1155 */ 1156 bus_dmamap_sync(sc->vte_dmatag, 1157 sc->vte_cdata.vte_rx_ring_map, 0, 1158 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1159 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1160 #ifdef notyet 1161 /* 1162 * Update residue counter. Controller does not 1163 * keep track of number of available RX descriptors 1164 * such that driver should have to update VTE_MRDCR 1165 * to make controller know how many free RX 1166 * descriptors were added to controller. This is 1167 * a similar mechanism used in VIA velocity 1168 * controllers and it indicates controller just 1169 * polls OWN bit of current RX descriptor pointer. 1170 * A couple of severe issues were seen on sample 1171 * board where the controller continuously emits TX 1172 * pause frames once RX pause threshold crossed. 1173 * Once triggered it never recovered form that 1174 * state, I couldn't find a way to make it back to 1175 * work at least. This issue effectively 1176 * disconnected the system from network. Also, the 1177 * controller used 00:00:00:00:00:00 as source 1178 * station address of TX pause frame. Probably this 1179 * is one of reason why vendor recommends not to 1180 * enable flow control on R6040 controller. 1181 */ 1182 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1183 (((VTE_RX_RING_CNT * 2) / 10) << 1184 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1185 #endif 1186 rnd_add_uint32(&sc->rnd_source, prog); 1187 } 1188 } 1189 1190 static void 1191 vte_tick(void *arg) 1192 { 1193 struct vte_softc *sc; 1194 int s = splnet(); 1195 1196 sc = (struct vte_softc *)arg; 1197 1198 mii_tick(&sc->vte_mii); 1199 vte_stats_update(sc); 1200 vte_txeof(sc); 1201 vte_ifwatchdog(&sc->vte_if); 1202 callout_schedule(&sc->vte_tick_ch, hz); 1203 splx(s); 1204 } 1205 1206 static void 1207 vte_reset(struct vte_softc *sc) 1208 { 1209 uint16_t mcr, mdcsc; 1210 int i; 1211 1212 mdcsc = CSR_READ_2(sc, VTE_MDCSC); 1213 mcr = CSR_READ_2(sc, VTE_MCR1); 1214 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1215 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1216 DELAY(10); 1217 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1218 break; 1219 } 1220 if (i == 0) 1221 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1222 /* 1223 * Follow the guide of vendor recommended way to reset MAC. 1224 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1225 * not reliable so manually reset internal state machine. 1226 */ 1227 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1228 CSR_WRITE_2(sc, VTE_MACSM, 0); 1229 DELAY(5000); 1230 1231 /* 1232 * On some SoCs (like Vortex86DX3) MDC speed control register value 1233 * needs to be restored to original value instead of default one, 1234 * otherwise some PHY registers may fail to be read. 1235 */ 1236 if (mdcsc != MDCSC_DEFAULT) 1237 CSR_WRITE_2(sc, VTE_MDCSC, mdcsc); 1238 } 1239 1240 1241 static int 1242 vte_init(struct ifnet *ifp) 1243 { 1244 struct vte_softc *sc = ifp->if_softc; 1245 bus_addr_t paddr; 1246 uint8_t eaddr[ETHER_ADDR_LEN]; 1247 int s, error; 1248 1249 s = splnet(); 1250 /* 1251 * Cancel any pending I/O. 1252 */ 1253 vte_stop(ifp, 1); 1254 /* 1255 * Reset the chip to a known state. 1256 */ 1257 vte_reset(sc); 1258 1259 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1260 splx(s); 1261 return 0; 1262 } 1263 1264 /* Initialize RX descriptors. */ 1265 if (vte_init_rx_ring(sc) != 0) { 1266 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1267 vte_stop(ifp, 1); 1268 splx(s); 1269 return ENOMEM; 1270 } 1271 if (vte_init_tx_ring(sc) != 0) { 1272 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1273 vte_stop(ifp, 1); 1274 splx(s); 1275 return ENOMEM; 1276 } 1277 1278 /* 1279 * Reprogram the station address. Controller supports up 1280 * to 4 different station addresses so driver programs the 1281 * first station address as its own ethernet address and 1282 * configure the remaining three addresses as perfect 1283 * multicast addresses. 1284 */ 1285 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1286 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1287 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1288 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1289 1290 /* Set TX descriptor base addresses. */ 1291 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1292 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1293 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1294 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1295 1296 /* Set RX descriptor base addresses. */ 1297 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1298 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1299 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1300 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1301 /* 1302 * Initialize RX descriptor residue counter and set RX 1303 * pause threshold to 20% of available RX descriptors. 1304 * See comments on vte_rxeof() for details on flow control 1305 * issues. 1306 */ 1307 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1308 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1309 1310 /* 1311 * Always use maximum frame size that controller can 1312 * support. Otherwise received frames that has longer 1313 * frame length than vte(4) MTU would be silently dropped 1314 * in controller. This would break path-MTU discovery as 1315 * sender wouldn't get any responses from receiver. The 1316 * RX buffer size should be multiple of 4. 1317 * Note, jumbo frames are silently ignored by controller 1318 * and even MAC counters do not detect them. 1319 */ 1320 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1321 1322 /* Configure FIFO. */ 1323 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1324 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1325 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1326 1327 /* 1328 * Configure TX/RX MACs. Actual resolved duplex and flow 1329 * control configuration is done after detecting a valid 1330 * link. Note, we don't generate early interrupt here 1331 * as well since FreeBSD does not have interrupt latency 1332 * problems like Windows. 1333 */ 1334 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1335 /* 1336 * We manually keep track of PHY status changes to 1337 * configure resolved duplex and flow control since only 1338 * duplex configuration can be automatically reflected to 1339 * MCR0. 1340 */ 1341 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1342 MCR1_EXCESS_COL_RETRY_16); 1343 1344 /* Initialize RX filter. */ 1345 vte_rxfilter(sc); 1346 1347 /* Disable TX/RX interrupt moderation control. */ 1348 CSR_WRITE_2(sc, VTE_MRICR, 0); 1349 CSR_WRITE_2(sc, VTE_MTICR, 0); 1350 1351 /* Enable MAC event counter interrupts. */ 1352 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1353 /* Clear MAC statistics. */ 1354 vte_stats_clear(sc); 1355 1356 /* Acknowledge all pending interrupts and clear it. */ 1357 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1358 CSR_WRITE_2(sc, VTE_MISR, 0); 1359 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1360 CSR_READ_2(sc, VTE_MISR))); 1361 1362 sc->vte_flags &= ~VTE_FLAG_LINK; 1363 ifp->if_flags |= IFF_RUNNING; 1364 1365 /* calling mii_mediachg will call back vte_start_mac() */ 1366 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1367 error = 0; 1368 else if (error != 0) { 1369 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1370 splx(s); 1371 return error; 1372 } 1373 1374 callout_schedule(&sc->vte_tick_ch, hz); 1375 1376 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1377 CSR_READ_2(sc, VTE_MISR))); 1378 splx(s); 1379 return 0; 1380 } 1381 1382 static void 1383 vte_stop(struct ifnet *ifp, int disable) 1384 { 1385 struct vte_softc *sc = ifp->if_softc; 1386 struct vte_txdesc *txd; 1387 struct vte_rxdesc *rxd; 1388 int i; 1389 1390 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1391 if ((ifp->if_flags & IFF_RUNNING) == 0) 1392 return; 1393 /* 1394 * Mark the interface down and cancel the watchdog timer. 1395 */ 1396 ifp->if_flags &= ~IFF_RUNNING; 1397 sc->vte_flags &= ~VTE_FLAG_LINK; 1398 callout_stop(&sc->vte_tick_ch); 1399 sc->vte_watchdog_timer = 0; 1400 vte_stats_update(sc); 1401 /* Disable interrupts. */ 1402 CSR_WRITE_2(sc, VTE_MIER, 0); 1403 CSR_WRITE_2(sc, VTE_MECIER, 0); 1404 /* Stop RX/TX MACs. */ 1405 vte_stop_mac(sc); 1406 /* Clear interrupts. */ 1407 CSR_READ_2(sc, VTE_MISR); 1408 /* 1409 * Free TX/RX mbufs still in the queues. 1410 */ 1411 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1412 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1413 if (rxd->rx_m != NULL) { 1414 bus_dmamap_sync(sc->vte_dmatag, 1415 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1416 BUS_DMASYNC_POSTREAD); 1417 bus_dmamap_unload(sc->vte_dmatag, 1418 rxd->rx_dmamap); 1419 m_freem(rxd->rx_m); 1420 rxd->rx_m = NULL; 1421 } 1422 } 1423 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1424 txd = &sc->vte_cdata.vte_txdesc[i]; 1425 if (txd->tx_m != NULL) { 1426 bus_dmamap_sync(sc->vte_dmatag, 1427 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1428 BUS_DMASYNC_POSTWRITE); 1429 bus_dmamap_unload(sc->vte_dmatag, 1430 txd->tx_dmamap); 1431 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1432 m_freem(txd->tx_m); 1433 txd->tx_m = NULL; 1434 txd->tx_flags &= ~VTE_TXMBUF; 1435 } 1436 } 1437 /* Free TX mbuf pools used for deep copy. */ 1438 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1439 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1440 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1441 sc->vte_cdata.vte_txmbufs[i] = NULL; 1442 } 1443 } 1444 } 1445 1446 static void 1447 vte_start_mac(struct vte_softc *sc) 1448 { 1449 struct ifnet *ifp = &sc->vte_if; 1450 uint16_t mcr; 1451 int i; 1452 1453 /* Enable RX/TX MACs. */ 1454 mcr = CSR_READ_2(sc, VTE_MCR0); 1455 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1456 (MCR0_RX_ENB | MCR0_TX_ENB) && 1457 (ifp->if_flags & IFF_RUNNING) != 0) { 1458 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1459 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1460 for (i = VTE_TIMEOUT; i > 0; i--) { 1461 mcr = CSR_READ_2(sc, VTE_MCR0); 1462 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1463 (MCR0_RX_ENB | MCR0_TX_ENB)) 1464 break; 1465 DELAY(10); 1466 } 1467 if (i == 0) 1468 aprint_error_dev(sc->vte_dev, 1469 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1470 } 1471 vte_rxfilter(sc); 1472 } 1473 1474 static void 1475 vte_stop_mac(struct vte_softc *sc) 1476 { 1477 uint16_t mcr; 1478 int i; 1479 1480 /* Disable RX/TX MACs. */ 1481 mcr = CSR_READ_2(sc, VTE_MCR0); 1482 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1483 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1484 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1485 for (i = VTE_TIMEOUT; i > 0; i--) { 1486 mcr = CSR_READ_2(sc, VTE_MCR0); 1487 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1488 break; 1489 DELAY(10); 1490 } 1491 if (i == 0) 1492 aprint_error_dev(sc->vte_dev, 1493 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1494 } 1495 } 1496 1497 static int 1498 vte_init_tx_ring(struct vte_softc *sc) 1499 { 1500 struct vte_tx_desc *desc; 1501 struct vte_txdesc *txd; 1502 bus_addr_t addr; 1503 int i; 1504 1505 sc->vte_cdata.vte_tx_prod = 0; 1506 sc->vte_cdata.vte_tx_cons = 0; 1507 sc->vte_cdata.vte_tx_cnt = 0; 1508 1509 /* Pre-allocate TX mbufs for deep copy. */ 1510 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1511 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1512 MT_DATA, M_PKTHDR); 1513 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1514 return (ENOBUFS); 1515 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1516 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1517 } 1518 desc = sc->vte_cdata.vte_tx_ring; 1519 bzero(desc, VTE_TX_RING_SZ); 1520 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1521 txd = &sc->vte_cdata.vte_txdesc[i]; 1522 txd->tx_m = NULL; 1523 if (i != VTE_TX_RING_CNT - 1) 1524 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1525 sizeof(struct vte_tx_desc) * (i + 1); 1526 else 1527 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1528 sizeof(struct vte_tx_desc) * 0; 1529 desc = &sc->vte_cdata.vte_tx_ring[i]; 1530 desc->dtnp = htole32(addr); 1531 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1532 txd->tx_desc = desc; 1533 } 1534 1535 bus_dmamap_sync(sc->vte_dmatag, 1536 sc->vte_cdata.vte_tx_ring_map, 0, 1537 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1538 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1539 return (0); 1540 } 1541 1542 static int 1543 vte_init_rx_ring(struct vte_softc *sc) 1544 { 1545 struct vte_rx_desc *desc; 1546 struct vte_rxdesc *rxd; 1547 bus_addr_t addr; 1548 int i; 1549 1550 sc->vte_cdata.vte_rx_cons = 0; 1551 desc = sc->vte_cdata.vte_rx_ring; 1552 bzero(desc, VTE_RX_RING_SZ); 1553 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1554 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1555 rxd->rx_m = NULL; 1556 if (i != VTE_RX_RING_CNT - 1) 1557 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1558 + sizeof(struct vte_rx_desc) * (i + 1); 1559 else 1560 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1561 + sizeof(struct vte_rx_desc) * 0; 1562 desc = &sc->vte_cdata.vte_rx_ring[i]; 1563 desc->drnp = htole32(addr); 1564 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1565 rxd->rx_desc = desc; 1566 if (vte_newbuf(sc, rxd) != 0) 1567 return (ENOBUFS); 1568 } 1569 1570 bus_dmamap_sync(sc->vte_dmatag, 1571 sc->vte_cdata.vte_rx_ring_map, 0, 1572 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1573 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1574 1575 return (0); 1576 } 1577 1578 static void 1579 vte_rxfilter(struct vte_softc *sc) 1580 { 1581 struct ethercom *ec = &sc->vte_ec; 1582 struct ether_multistep step; 1583 struct ether_multi *enm; 1584 struct ifnet *ifp; 1585 uint8_t *eaddr; 1586 uint32_t crc; 1587 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1588 uint16_t mchash[4], mcr; 1589 int i, nperf; 1590 1591 ifp = &sc->vte_if; 1592 1593 DPRINTF(("vte_rxfilter\n")); 1594 memset(mchash, 0, sizeof(mchash)); 1595 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1596 rxfilt_perf[i][0] = 0xFFFF; 1597 rxfilt_perf[i][1] = 0xFFFF; 1598 rxfilt_perf[i][2] = 0xFFFF; 1599 } 1600 1601 mcr = CSR_READ_2(sc, VTE_MCR0); 1602 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1603 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST); 1604 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1605 mcr |= MCR0_BROADCAST_DIS; 1606 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1607 if ((ifp->if_flags & IFF_PROMISC) != 0) 1608 mcr |= MCR0_PROMISC; 1609 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1610 mcr |= MCR0_MULTICAST; 1611 mchash[0] = 0xFFFF; 1612 mchash[1] = 0xFFFF; 1613 mchash[2] = 0xFFFF; 1614 mchash[3] = 0xFFFF; 1615 goto chipit; 1616 } 1617 1618 ETHER_LOCK(ec); 1619 ETHER_FIRST_MULTI(step, ec, enm); 1620 nperf = 0; 1621 while (enm != NULL) { 1622 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) 1623 != 0) { 1624 sc->vte_if.if_flags |= IFF_ALLMULTI; 1625 mcr |= MCR0_MULTICAST; 1626 mchash[0] = 0xFFFF; 1627 mchash[1] = 0xFFFF; 1628 mchash[2] = 0xFFFF; 1629 mchash[3] = 0xFFFF; 1630 ETHER_UNLOCK(ec); 1631 goto chipit; 1632 } 1633 /* 1634 * Program the first 3 multicast groups into 1635 * the perfect filter. For all others, use the 1636 * hash table. 1637 */ 1638 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1639 eaddr = enm->enm_addrlo; 1640 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1641 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1642 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1643 nperf++; 1644 } else { 1645 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1646 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1647 } 1648 ETHER_NEXT_MULTI(step, enm); 1649 } 1650 ETHER_UNLOCK(ec); 1651 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1652 mchash[3] != 0) 1653 mcr |= MCR0_MULTICAST; 1654 1655 chipit: 1656 /* Program multicast hash table. */ 1657 DPRINTF(("chipit write multicast\n")); 1658 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1659 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1660 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1661 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1662 /* Program perfect filter table. */ 1663 DPRINTF(("chipit write perfect filter\n")); 1664 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1665 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1666 rxfilt_perf[i][0]); 1667 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1668 rxfilt_perf[i][1]); 1669 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1670 rxfilt_perf[i][2]); 1671 } 1672 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1673 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1674 DPRINTF(("chipit read mcro\n")); 1675 CSR_READ_2(sc, VTE_MCR0); 1676 DPRINTF(("chipit done\n")); 1677 } 1678 1679 /* 1680 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1681 * set up in vte_pci_attach() 1682 */ 1683 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1684 { 1685 int rc; 1686 const struct sysctlnode *node; 1687 1688 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1689 0, CTLTYPE_NODE, "vte", 1690 SYSCTL_DESCR("vte interface controls"), 1691 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1692 goto err; 1693 } 1694 1695 vte_root_num = node->sysctl_num; 1696 return; 1697 1698 err: 1699 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1700 } 1701 1702 static int 1703 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1704 { 1705 int error, t; 1706 struct sysctlnode node; 1707 struct vte_softc *sc; 1708 1709 node = *rnode; 1710 sc = node.sysctl_data; 1711 t = sc->vte_int_rx_mod; 1712 node.sysctl_data = &t; 1713 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1714 if (error || newp == NULL) 1715 return error; 1716 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1717 return EINVAL; 1718 1719 sc->vte_int_rx_mod = t; 1720 vte_miibus_statchg(&sc->vte_if); 1721 return 0; 1722 } 1723 1724 static int 1725 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1726 { 1727 int error, t; 1728 struct sysctlnode node; 1729 struct vte_softc *sc; 1730 1731 node = *rnode; 1732 sc = node.sysctl_data; 1733 t = sc->vte_int_tx_mod; 1734 node.sysctl_data = &t; 1735 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1736 if (error || newp == NULL) 1737 return error; 1738 1739 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1740 return EINVAL; 1741 sc->vte_int_tx_mod = t; 1742 vte_miibus_statchg(&sc->vte_if); 1743 return 0; 1744 } 1745
Indexes created Thu Oct 02 07:10:07 GMT 2025