if_vte.c revision 1.5
1 /* $NetBSD: if_vte.c,v 1.5 2012/02/02 19:43:05 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2010, Pyun YongHyeon <yongari (at) FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 54 55 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.5 2012/02/02 19:43:05 tls Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/mbuf.h> 63 #include <sys/protosw.h> 64 #include <sys/socket.h> 65 #include <sys/ioctl.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_dl.h> 76 #include <net/route.h> 77 #include <net/netisr.h> 78 79 #include <net/bpf.h> 80 #include <net/bpfdesc.h> 81 82 #include <sys/rnd.h> 83 84 #include "opt_inet.h" 85 #include <net/if_ether.h> 86 #ifdef INET 87 #include <netinet/in.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #include <netinet/if_inarp.h> 92 #endif 93 94 #include <sys/bus.h> 95 #include <sys/intr.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcidevs.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 104 #include <dev/pci/if_vtereg.h> 105 #include <dev/pci/if_vtevar.h> 106 107 static int vte_match(device_t, cfdata_t, void *); 108 static void vte_attach(device_t, device_t, void *); 109 static int vte_detach(device_t, int); 110 static int vte_dma_alloc(struct vte_softc *); 111 static void vte_dma_free(struct vte_softc *); 112 static struct vte_txdesc * 113 vte_encap(struct vte_softc *, struct mbuf **); 114 static void vte_get_macaddr(struct vte_softc *); 115 static int vte_init(struct ifnet *); 116 static int vte_init_rx_ring(struct vte_softc *); 117 static int vte_init_tx_ring(struct vte_softc *); 118 static int vte_intr(void *); 119 static int vte_ifioctl(struct ifnet *, u_long, void *); 120 static void vte_mac_config(struct vte_softc *); 121 static int vte_miibus_readreg(device_t, int, int); 122 static void vte_miibus_statchg(device_t); 123 static void vte_miibus_writereg(device_t, int, int, int); 124 static int vte_mediachange(struct ifnet *); 125 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 126 static void vte_reset(struct vte_softc *); 127 static void vte_rxeof(struct vte_softc *); 128 static void vte_rxfilter(struct vte_softc *); 129 static bool vte_shutdown(device_t, int); 130 static bool vte_suspend(device_t, const pmf_qual_t *); 131 static bool vte_resume(device_t, const pmf_qual_t *); 132 static void vte_ifstart(struct ifnet *); 133 static void vte_start_mac(struct vte_softc *); 134 static void vte_stats_clear(struct vte_softc *); 135 static void vte_stats_update(struct vte_softc *); 136 static void vte_stop(struct ifnet *, int); 137 static void vte_stop_mac(struct vte_softc *); 138 static void vte_tick(void *); 139 static void vte_txeof(struct vte_softc *); 140 static void vte_ifwatchdog(struct ifnet *); 141 142 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 143 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 144 static int vte_root_num; 145 146 #define DPRINTF(a) 147 148 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 149 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 150 151 152 static int 153 vte_match(device_t parent, cfdata_t cf, void *aux) 154 { 155 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 156 157 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 158 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 159 return 1; 160 161 return 0; 162 } 163 164 static void 165 vte_attach(device_t parent, device_t self, void *aux) 166 { 167 struct vte_softc *sc = device_private(self); 168 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 169 struct ifnet * const ifp = &sc->vte_if; 170 int h_valid; 171 pcireg_t reg, csr; 172 pci_intr_handle_t intrhandle; 173 const char *intrstr; 174 int error; 175 const struct sysctlnode *node; 176 int vte_nodenum; 177 178 sc->vte_dev = self; 179 180 callout_init(&sc->vte_tick_ch, 0); 181 182 /* Map the device. */ 183 h_valid = 0; 184 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 185 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 186 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 187 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 188 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 189 } 190 if (h_valid == 0) { 191 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 192 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 193 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 194 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 195 &sc->vte_bushandle, NULL, NULL) == 0); 196 } 197 } 198 if (h_valid == 0) { 199 aprint_error_dev(self, "unable to map device registers\n"); 200 return; 201 } 202 sc->vte_dmatag = pa->pa_dmat; 203 /* Enable the device. */ 204 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 205 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 206 csr | PCI_COMMAND_MASTER_ENABLE); 207 208 pci_aprint_devinfo(pa, NULL); 209 210 /* Reset the ethernet controller. */ 211 vte_reset(sc); 212 213 if ((error = vte_dma_alloc(sc)) != 0) 214 return; 215 216 /* Load station address. */ 217 vte_get_macaddr(sc); 218 219 aprint_normal_dev(self, "Ethernet address %s\n", 220 ether_sprintf(sc->vte_eaddr)); 221 222 /* Map and establish interrupts */ 223 if (pci_intr_map(pa, &intrhandle)) { 224 aprint_error_dev(self, "couldn't map interrupt\n"); 225 return; 226 } 227 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 228 sc->vte_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 229 vte_intr, sc); 230 if (sc->vte_ih == NULL) { 231 aprint_error_dev(self, "couldn't establish interrupt"); 232 if (intrstr != NULL) 233 aprint_error(" at %s", intrstr); 234 aprint_error("\n"); 235 return; 236 } 237 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 238 239 sc->vte_if.if_softc = sc; 240 sc->vte_mii.mii_ifp = ifp; 241 sc->vte_mii.mii_readreg = vte_miibus_readreg; 242 sc->vte_mii.mii_writereg = vte_miibus_writereg; 243 sc->vte_mii.mii_statchg = vte_miibus_statchg; 244 sc->vte_ec.ec_mii = &sc->vte_mii; 245 ifmedia_init(&sc->vte_mii.mii_media, IFM_IMASK, vte_mediachange, 246 ether_mediastatus); 247 mii_attach(self, &sc->vte_mii, 0xffffffff, MII_PHY_ANY, 248 MII_OFFSET_ANY, 0); 249 if (LIST_FIRST(&sc->vte_mii.mii_phys) == NULL) { 250 ifmedia_add(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 251 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_NONE); 252 } else 253 ifmedia_set(&sc->vte_mii.mii_media, IFM_ETHER|IFM_AUTO); 254 255 /* 256 * We can support 802.1Q VLAN-sized frames. 257 */ 258 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 259 260 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 261 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 262 ifp->if_ioctl = vte_ifioctl; 263 ifp->if_start = vte_ifstart; 264 ifp->if_watchdog = vte_ifwatchdog; 265 ifp->if_init = vte_init; 266 ifp->if_stop = vte_stop; 267 ifp->if_timer = 0; 268 IFQ_SET_READY(&ifp->if_snd); 269 if_attach(ifp); 270 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 271 272 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 273 pmf_class_network_register(self, ifp); 274 else 275 aprint_error_dev(self, "couldn't establish power handler\n"); 276 277 rnd_attach_source(&sc->rnd_source, device_xname(self), 278 RND_TYPE_NET, 0); 279 280 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 281 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 282 SYSCTL_DESCR("vte per-controller controls"), 283 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 284 CTL_EOL) != 0) { 285 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 286 return; 287 } 288 vte_nodenum = node->sysctl_num; 289 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 290 CTLFLAG_READWRITE, 291 CTLTYPE_INT, "int_rxct", 292 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 293 vte_sysctl_intrxct, 0, sc, 294 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 295 CTL_EOL) != 0) { 296 aprint_normal_dev(sc->vte_dev, 297 "couldn't create int_rxct sysctl node\n"); 298 } 299 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 300 CTLFLAG_READWRITE, 301 CTLTYPE_INT, "int_txct", 302 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 303 vte_sysctl_inttxct, 0, sc, 304 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 305 CTL_EOL) != 0) { 306 aprint_normal_dev(sc->vte_dev, 307 "couldn't create int_txct sysctl node\n"); 308 } 309 } 310 311 static int 312 vte_detach(device_t dev, int flags __unused) 313 { 314 struct vte_softc *sc = device_private(dev); 315 struct ifnet *ifp = &sc->vte_if; 316 int s; 317 318 s = splnet(); 319 /* Stop the interface. Callouts are stopped in it. */ 320 vte_stop(ifp, 1); 321 splx(s); 322 323 pmf_device_deregister(dev); 324 325 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 326 ifmedia_delete_instance(&sc->vte_mii.mii_media, IFM_INST_ANY); 327 328 ether_ifdetach(ifp); 329 if_detach(ifp); 330 331 vte_dma_free(sc); 332 333 return (0); 334 } 335 336 static int 337 vte_miibus_readreg(device_t dev, int phy, int reg) 338 { 339 struct vte_softc *sc = device_private(dev); 340 int i; 341 342 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 343 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 344 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 345 DELAY(5); 346 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 347 break; 348 } 349 350 if (i == 0) { 351 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 352 return (0); 353 } 354 355 return (CSR_READ_2(sc, VTE_MMRD)); 356 } 357 358 static void 359 vte_miibus_writereg(device_t dev, int phy, int reg, int val) 360 { 361 struct vte_softc *sc = device_private(dev); 362 int i; 363 364 CSR_WRITE_2(sc, VTE_MMWD, val); 365 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 366 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 367 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 368 DELAY(5); 369 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 370 break; 371 } 372 373 if (i == 0) 374 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 375 376 } 377 378 static void 379 vte_miibus_statchg(device_t dev) 380 { 381 struct vte_softc *sc = device_private(dev); 382 struct ifnet *ifp; 383 uint16_t val; 384 385 ifp = &sc->vte_if; 386 387 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 388 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 389 390 sc->vte_flags &= ~VTE_FLAG_LINK; 391 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 392 (IFM_ACTIVE | IFM_AVALID)) { 393 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 394 case IFM_10_T: 395 case IFM_100_TX: 396 sc->vte_flags |= VTE_FLAG_LINK; 397 break; 398 default: 399 break; 400 } 401 } 402 403 /* Stop RX/TX MACs. */ 404 vte_stop_mac(sc); 405 /* Program MACs with resolved duplex and flow control. */ 406 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 407 /* 408 * Timer waiting time : (63 + TIMER * 64) MII clock. 409 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 410 */ 411 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 412 val = 18 << VTE_IM_TIMER_SHIFT; 413 else 414 val = 1 << VTE_IM_TIMER_SHIFT; 415 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 416 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 417 CSR_WRITE_2(sc, VTE_MRICR, val); 418 419 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 420 val = 18 << VTE_IM_TIMER_SHIFT; 421 else 422 val = 1 << VTE_IM_TIMER_SHIFT; 423 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 424 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 425 CSR_WRITE_2(sc, VTE_MTICR, val); 426 427 vte_mac_config(sc); 428 vte_start_mac(sc); 429 DPRINTF(("vte_miibus_statchg: link\n")); 430 } 431 } 432 433 static void 434 vte_get_macaddr(struct vte_softc *sc) 435 { 436 uint16_t mid; 437 438 /* 439 * It seems there is no way to reload station address and 440 * it is supposed to be set by BIOS. 441 */ 442 mid = CSR_READ_2(sc, VTE_MID0L); 443 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 444 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 445 mid = CSR_READ_2(sc, VTE_MID0M); 446 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 447 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 448 mid = CSR_READ_2(sc, VTE_MID0H); 449 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 450 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 451 } 452 453 454 static int 455 vte_dma_alloc(struct vte_softc *sc) 456 { 457 struct vte_txdesc *txd; 458 struct vte_rxdesc *rxd; 459 int error, i, rseg; 460 461 /* create DMA map for TX ring */ 462 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 463 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 464 &sc->vte_cdata.vte_tx_ring_map); 465 if (error) { 466 aprint_error_dev(sc->vte_dev, 467 "could not create dma map for TX ring (%d)\n", 468 error); 469 goto fail; 470 } 471 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 472 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 473 VTE_TX_RING_ALIGN, 0, 474 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 475 BUS_DMA_NOWAIT); 476 if (error != 0) { 477 aprint_error_dev(sc->vte_dev, 478 "could not allocate DMA'able memory for TX ring (%d).\n", 479 error); 480 goto fail; 481 } 482 KASSERT(rseg == 1); 483 error = bus_dmamem_map(sc->vte_dmatag, 484 sc->vte_cdata.vte_tx_ring_seg, 1, 485 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 486 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 487 if (error != 0) { 488 aprint_error_dev(sc->vte_dev, 489 "could not map DMA'able memory for TX ring (%d).\n", 490 error); 491 goto fail; 492 } 493 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 494 error = bus_dmamap_load(sc->vte_dmatag, 495 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 496 VTE_TX_RING_SZ, NULL, 497 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 498 if (error != 0) { 499 aprint_error_dev(sc->vte_dev, 500 "could not load DMA'able memory for TX ring.\n"); 501 goto fail; 502 } 503 504 /* create DMA map for RX ring */ 505 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 506 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 507 &sc->vte_cdata.vte_rx_ring_map); 508 if (error) { 509 aprint_error_dev(sc->vte_dev, 510 "could not create dma map for RX ring (%d)\n", 511 error); 512 goto fail; 513 } 514 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 515 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 516 VTE_RX_RING_ALIGN, 0, 517 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 518 BUS_DMA_NOWAIT); 519 if (error != 0) { 520 aprint_error_dev(sc->vte_dev, 521 "could not allocate DMA'able memory for RX ring (%d).\n", 522 error); 523 goto fail; 524 } 525 KASSERT(rseg == 1); 526 error = bus_dmamem_map(sc->vte_dmatag, 527 sc->vte_cdata.vte_rx_ring_seg, 1, 528 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 529 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 530 if (error != 0) { 531 aprint_error_dev(sc->vte_dev, 532 "could not map DMA'able memory for RX ring (%d).\n", 533 error); 534 goto fail; 535 } 536 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 537 error = bus_dmamap_load(sc->vte_dmatag, 538 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 539 VTE_RX_RING_SZ, NULL, 540 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 541 if (error != 0) { 542 aprint_error_dev(sc->vte_dev, 543 "could not load DMA'able memory for RX ring (%d).\n", 544 error); 545 goto fail; 546 } 547 548 /* Create DMA maps for TX buffers. */ 549 for (i = 0; i < VTE_TX_RING_CNT; i++) { 550 txd = &sc->vte_cdata.vte_txdesc[i]; 551 txd->tx_m = NULL; 552 txd->tx_dmamap = NULL; 553 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 554 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 555 &txd->tx_dmamap); 556 if (error != 0) { 557 aprint_error_dev(sc->vte_dev, 558 "could not create TX DMA map %d (%d).\n", i, error); 559 goto fail; 560 } 561 } 562 /* Create DMA maps for RX buffers. */ 563 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 564 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 565 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 566 aprint_error_dev(sc->vte_dev, 567 "could not create spare RX dmamap (%d).\n", error); 568 goto fail; 569 } 570 for (i = 0; i < VTE_RX_RING_CNT; i++) { 571 rxd = &sc->vte_cdata.vte_rxdesc[i]; 572 rxd->rx_m = NULL; 573 rxd->rx_dmamap = NULL; 574 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 575 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 576 &rxd->rx_dmamap); 577 if (error != 0) { 578 aprint_error_dev(sc->vte_dev, 579 "could not create RX dmamap %d (%d).\n", i, error); 580 goto fail; 581 } 582 } 583 return 0; 584 585 fail: 586 vte_dma_free(sc); 587 return (error); 588 } 589 590 static void 591 vte_dma_free(struct vte_softc *sc) 592 { 593 struct vte_txdesc *txd; 594 struct vte_rxdesc *rxd; 595 int i; 596 597 /* TX buffers. */ 598 for (i = 0; i < VTE_TX_RING_CNT; i++) { 599 txd = &sc->vte_cdata.vte_txdesc[i]; 600 if (txd->tx_dmamap != NULL) { 601 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 602 txd->tx_dmamap = NULL; 603 } 604 } 605 /* RX buffers */ 606 for (i = 0; i < VTE_RX_RING_CNT; i++) { 607 rxd = &sc->vte_cdata.vte_rxdesc[i]; 608 if (rxd->rx_dmamap != NULL) { 609 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 610 rxd->rx_dmamap = NULL; 611 } 612 } 613 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 614 bus_dmamap_destroy(sc->vte_dmatag, 615 sc->vte_cdata.vte_rx_sparemap); 616 sc->vte_cdata.vte_rx_sparemap = NULL; 617 } 618 /* TX descriptor ring. */ 619 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 620 bus_dmamap_unload(sc->vte_dmatag, 621 sc->vte_cdata.vte_tx_ring_map); 622 bus_dmamap_destroy(sc->vte_dmatag, 623 sc->vte_cdata.vte_tx_ring_map); 624 } 625 if (sc->vte_cdata.vte_tx_ring != NULL) { 626 bus_dmamem_unmap(sc->vte_dmatag, 627 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 628 bus_dmamem_free(sc->vte_dmatag, 629 sc->vte_cdata.vte_tx_ring_seg, 1); 630 } 631 sc->vte_cdata.vte_tx_ring = NULL; 632 sc->vte_cdata.vte_tx_ring_map = NULL; 633 /* RX ring. */ 634 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 635 bus_dmamap_unload(sc->vte_dmatag, 636 sc->vte_cdata.vte_rx_ring_map); 637 bus_dmamap_destroy(sc->vte_dmatag, 638 sc->vte_cdata.vte_rx_ring_map); 639 } 640 if (sc->vte_cdata.vte_rx_ring != NULL) { 641 bus_dmamem_unmap(sc->vte_dmatag, 642 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 643 bus_dmamem_free(sc->vte_dmatag, 644 sc->vte_cdata.vte_rx_ring_seg, 1); 645 } 646 sc->vte_cdata.vte_rx_ring = NULL; 647 sc->vte_cdata.vte_rx_ring_map = NULL; 648 } 649 650 static bool 651 vte_shutdown(device_t dev, int howto) 652 { 653 654 return (vte_suspend(dev, NULL)); 655 } 656 657 static bool 658 vte_suspend(device_t dev, const pmf_qual_t *qual) 659 { 660 struct vte_softc *sc = device_private(dev); 661 struct ifnet *ifp = &sc->vte_if; 662 663 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 664 if ((ifp->if_flags & IFF_RUNNING) != 0) 665 vte_stop(ifp, 1); 666 return (0); 667 } 668 669 static bool 670 vte_resume(device_t dev, const pmf_qual_t *qual) 671 { 672 struct vte_softc *sc = device_private(dev); 673 struct ifnet *ifp; 674 675 ifp = &sc->vte_if; 676 if ((ifp->if_flags & IFF_UP) != 0) { 677 ifp->if_flags &= ~IFF_RUNNING; 678 vte_init(ifp); 679 } 680 681 return (0); 682 } 683 684 static struct vte_txdesc * 685 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 686 { 687 struct vte_txdesc *txd; 688 struct mbuf *m, *n; 689 int copy, error, padlen; 690 691 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 692 m = *m_head; 693 /* 694 * Controller doesn't auto-pad, so we have to make sure pad 695 * short frames out to the minimum frame length. 696 */ 697 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 698 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 699 else 700 padlen = 0; 701 702 /* 703 * Controller does not support multi-fragmented TX buffers. 704 * Controller spends most of its TX processing time in 705 * de-fragmenting TX buffers. Either faster CPU or more 706 * advanced controller DMA engine is required to speed up 707 * TX path processing. 708 * To mitigate the de-fragmenting issue, perform deep copy 709 * from fragmented mbuf chains to a pre-allocated mbuf 710 * cluster with extra cost of kernel memory. For frames 711 * that is composed of single TX buffer, the deep copy is 712 * bypassed. 713 */ 714 copy = 0; 715 if (m->m_next != NULL) 716 copy++; 717 if (padlen > 0 && (M_READONLY(m) || 718 padlen > M_TRAILINGSPACE(m))) 719 copy++; 720 if (copy != 0) { 721 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 722 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 723 n->m_pkthdr.len = m->m_pkthdr.len; 724 n->m_len = m->m_pkthdr.len; 725 m = n; 726 txd->tx_flags |= VTE_TXMBUF; 727 } 728 729 if (padlen > 0) { 730 /* Zero out the bytes in the pad area. */ 731 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 732 m->m_pkthdr.len += padlen; 733 m->m_len = m->m_pkthdr.len; 734 } 735 736 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 0); 737 if (error != 0) { 738 txd->tx_flags &= ~VTE_TXMBUF; 739 return (NULL); 740 } 741 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 742 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 743 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 744 745 txd->tx_desc->dtlen = 746 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 747 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 748 sc->vte_cdata.vte_tx_cnt++; 749 /* Update producer index. */ 750 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 751 752 /* Finally hand over ownership to controller. */ 753 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 754 txd->tx_m = m; 755 756 return (txd); 757 } 758 759 static void 760 vte_ifstart(struct ifnet *ifp) 761 { 762 struct vte_softc *sc = ifp->if_softc; 763 struct vte_txdesc *txd; 764 struct mbuf *m_head, *m; 765 int enq; 766 767 ifp = &sc->vte_if; 768 769 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 770 771 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 772 IFF_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 773 return; 774 775 for (enq = 0; !IFQ_IS_EMPTY(&ifp->if_snd); ) { 776 /* Reserve one free TX descriptor. */ 777 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 778 ifp->if_flags |= IFF_OACTIVE; 779 break; 780 } 781 IFQ_POLL(&ifp->if_snd, m_head); 782 if (m_head == NULL) 783 break; 784 /* 785 * Pack the data into the transmit ring. If we 786 * don't have room, set the OACTIVE flag and wait 787 * for the NIC to drain the ring. 788 */ 789 DPRINTF(("vte_encap:")); 790 if ((txd = vte_encap(sc, &m_head)) == NULL) { 791 DPRINTF((" failed\n")); 792 break; 793 } 794 DPRINTF((" ok\n")); 795 IFQ_DEQUEUE(&ifp->if_snd, m); 796 KASSERT(m == m_head); 797 798 enq++; 799 /* 800 * If there's a BPF listener, bounce a copy of this frame 801 * to him. 802 */ 803 bpf_mtap(ifp, m_head); 804 /* Free consumed TX frame. */ 805 if ((txd->tx_flags & VTE_TXMBUF) != 0) 806 m_freem(m_head); 807 } 808 809 if (enq > 0) { 810 bus_dmamap_sync(sc->vte_dmatag, 811 sc->vte_cdata.vte_tx_ring_map, 0, 812 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 813 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 814 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 815 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 816 } 817 } 818 819 static void 820 vte_ifwatchdog(struct ifnet *ifp) 821 { 822 struct vte_softc *sc = ifp->if_softc; 823 824 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 825 return; 826 827 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 828 ifp->if_oerrors++; 829 vte_init(ifp); 830 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 831 vte_ifstart(ifp); 832 } 833 834 static int 835 vte_mediachange(struct ifnet *ifp) 836 { 837 int error; 838 struct vte_softc *sc = ifp->if_softc; 839 840 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 841 error = 0; 842 else if (error != 0) { 843 aprint_error_dev(sc->vte_dev, "could not set media\n"); 844 return error; 845 } 846 return 0; 847 848 } 849 850 static int 851 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 852 { 853 struct vte_softc *sc = ifp->if_softc; 854 int error, s; 855 856 s = splnet(); 857 error = ether_ioctl(ifp, cmd, data); 858 if (error == ENETRESET) { 859 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 860 if (ifp->if_flags & IFF_RUNNING) 861 vte_rxfilter(sc); 862 error = 0; 863 } 864 splx(s); 865 return error; 866 } 867 868 static void 869 vte_mac_config(struct vte_softc *sc) 870 { 871 uint16_t mcr; 872 873 mcr = CSR_READ_2(sc, VTE_MCR0); 874 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 875 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 876 mcr |= MCR0_FULL_DUPLEX; 877 #ifdef notyet 878 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 879 mcr |= MCR0_FC_ENB; 880 /* 881 * The data sheet is not clear whether the controller 882 * honors received pause frames or not. The is no 883 * separate control bit for RX pause frame so just 884 * enable MCR0_FC_ENB bit. 885 */ 886 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 887 mcr |= MCR0_FC_ENB; 888 #endif 889 } 890 CSR_WRITE_2(sc, VTE_MCR0, mcr); 891 } 892 893 static void 894 vte_stats_clear(struct vte_softc *sc) 895 { 896 897 /* Reading counter registers clears its contents. */ 898 CSR_READ_2(sc, VTE_CNT_RX_DONE); 899 CSR_READ_2(sc, VTE_CNT_MECNT0); 900 CSR_READ_2(sc, VTE_CNT_MECNT1); 901 CSR_READ_2(sc, VTE_CNT_MECNT2); 902 CSR_READ_2(sc, VTE_CNT_MECNT3); 903 CSR_READ_2(sc, VTE_CNT_TX_DONE); 904 CSR_READ_2(sc, VTE_CNT_MECNT4); 905 CSR_READ_2(sc, VTE_CNT_PAUSE); 906 } 907 908 static void 909 vte_stats_update(struct vte_softc *sc) 910 { 911 struct vte_hw_stats *stat; 912 struct ifnet *ifp = &sc->vte_if; 913 uint16_t value; 914 915 stat = &sc->vte_stats; 916 917 CSR_READ_2(sc, VTE_MECISR); 918 /* RX stats. */ 919 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 920 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 921 stat->rx_bcast_frames += (value >> 8); 922 stat->rx_mcast_frames += (value & 0xFF); 923 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 924 stat->rx_runts += (value >> 8); 925 stat->rx_crcerrs += (value & 0xFF); 926 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 927 stat->rx_long_frames += (value & 0xFF); 928 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 929 stat->rx_fifo_full += (value >> 8); 930 stat->rx_desc_unavail += (value & 0xFF); 931 932 /* TX stats. */ 933 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 934 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 935 stat->tx_underruns += (value >> 8); 936 stat->tx_late_colls += (value & 0xFF); 937 938 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 939 stat->tx_pause_frames += (value >> 8); 940 stat->rx_pause_frames += (value & 0xFF); 941 942 /* Update ifp counters. */ 943 ifp->if_opackets = stat->tx_frames; 944 ifp->if_oerrors = stat->tx_late_colls + stat->tx_underruns; 945 ifp->if_ipackets = stat->rx_frames; 946 ifp->if_ierrors = stat->rx_crcerrs + stat->rx_runts + 947 stat->rx_long_frames + stat->rx_fifo_full; 948 } 949 950 static int 951 vte_intr(void *arg) 952 { 953 struct vte_softc *sc = (struct vte_softc *)arg; 954 struct ifnet *ifp = &sc->vte_if; 955 uint16_t status; 956 int n; 957 958 /* Reading VTE_MISR acknowledges interrupts. */ 959 status = CSR_READ_2(sc, VTE_MISR); 960 DPRINTF(("vte_intr status 0x%x\n", status)); 961 if ((status & VTE_INTRS) == 0) { 962 /* Not ours. */ 963 return 0; 964 } 965 966 /* Disable interrupts. */ 967 CSR_WRITE_2(sc, VTE_MIER, 0); 968 for (n = 8; (status & VTE_INTRS) != 0;) { 969 if ((ifp->if_flags & IFF_RUNNING) == 0) 970 break; 971 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 972 MISR_RX_FIFO_FULL)) != 0) 973 vte_rxeof(sc); 974 if ((status & MISR_TX_DONE) != 0) 975 vte_txeof(sc); 976 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 977 vte_stats_update(sc); 978 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 979 vte_ifstart(ifp); 980 if (--n > 0) 981 status = CSR_READ_2(sc, VTE_MISR); 982 else 983 break; 984 } 985 986 if ((ifp->if_flags & IFF_RUNNING) != 0) { 987 /* Re-enable interrupts. */ 988 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 989 } 990 return 1; 991 } 992 993 static void 994 vte_txeof(struct vte_softc *sc) 995 { 996 struct ifnet *ifp; 997 struct vte_txdesc *txd; 998 uint16_t status; 999 int cons, prog; 1000 1001 ifp = &sc->vte_if; 1002 1003 if (sc->vte_cdata.vte_tx_cnt == 0) 1004 return; 1005 bus_dmamap_sync(sc->vte_dmatag, 1006 sc->vte_cdata.vte_tx_ring_map, 0, 1007 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1008 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1009 cons = sc->vte_cdata.vte_tx_cons; 1010 /* 1011 * Go through our TX list and free mbufs for those 1012 * frames which have been transmitted. 1013 */ 1014 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1015 txd = &sc->vte_cdata.vte_txdesc[cons]; 1016 status = le16toh(txd->tx_desc->dtst); 1017 if ((status & VTE_DTST_TX_OWN) != 0) 1018 break; 1019 if ((status & VTE_DTST_TX_OK) != 0) 1020 ifp->if_collisions += (status & 0xf); 1021 sc->vte_cdata.vte_tx_cnt--; 1022 /* Reclaim transmitted mbufs. */ 1023 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1024 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1025 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1026 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1027 m_freem(txd->tx_m); 1028 txd->tx_flags &= ~VTE_TXMBUF; 1029 txd->tx_m = NULL; 1030 prog++; 1031 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1032 } 1033 1034 if (prog > 0) { 1035 ifp->if_flags &= ~IFF_OACTIVE; 1036 sc->vte_cdata.vte_tx_cons = cons; 1037 /* 1038 * Unarm watchdog timer only when there is no pending 1039 * frames in TX queue. 1040 */ 1041 if (sc->vte_cdata.vte_tx_cnt == 0) 1042 sc->vte_watchdog_timer = 0; 1043 } 1044 } 1045 1046 static int 1047 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1048 { 1049 struct mbuf *m; 1050 bus_dmamap_t map; 1051 1052 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1053 if (m == NULL) 1054 return (ENOBUFS); 1055 m->m_len = m->m_pkthdr.len = MCLBYTES; 1056 m_adj(m, sizeof(uint32_t)); 1057 1058 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1059 sc->vte_cdata.vte_rx_sparemap, m, 0) != 0) { 1060 m_freem(m); 1061 return (ENOBUFS); 1062 } 1063 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1064 1065 if (rxd->rx_m != NULL) { 1066 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1067 0, rxd->rx_dmamap->dm_mapsize, 1068 BUS_DMASYNC_POSTREAD); 1069 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1070 } 1071 map = rxd->rx_dmamap; 1072 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1073 sc->vte_cdata.vte_rx_sparemap = map; 1074 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1075 0, rxd->rx_dmamap->dm_mapsize, 1076 BUS_DMASYNC_PREREAD); 1077 rxd->rx_m = m; 1078 rxd->rx_desc->drbp = 1079 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1080 rxd->rx_desc->drlen = htole16( 1081 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1082 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, rxd->rx_dmamap->dm_segs[0].ds_len)); 1083 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1084 1085 return (0); 1086 } 1087 1088 static void 1089 vte_rxeof(struct vte_softc *sc) 1090 { 1091 struct ifnet *ifp; 1092 struct vte_rxdesc *rxd; 1093 struct mbuf *m; 1094 uint16_t status, total_len; 1095 int cons, prog; 1096 1097 bus_dmamap_sync(sc->vte_dmatag, 1098 sc->vte_cdata.vte_rx_ring_map, 0, 1099 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1100 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1101 cons = sc->vte_cdata.vte_rx_cons; 1102 ifp = &sc->vte_if; 1103 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1104 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1105 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1106 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1107 status = le16toh(rxd->rx_desc->drst); 1108 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", cons, rxd, rxd->rx_m, status, VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1109 if ((status & VTE_DRST_RX_OWN) != 0) 1110 break; 1111 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1112 m = rxd->rx_m; 1113 if ((status & VTE_DRST_RX_OK) == 0) { 1114 /* Discard errored frame. */ 1115 rxd->rx_desc->drlen = 1116 htole16(MCLBYTES - sizeof(uint32_t)); 1117 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1118 continue; 1119 } 1120 if (vte_newbuf(sc, rxd) != 0) { 1121 DPRINTF(("vte_rxeof newbuf failed\n")); 1122 ifp->if_ierrors++; 1123 rxd->rx_desc->drlen = 1124 htole16(MCLBYTES - sizeof(uint32_t)); 1125 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1126 continue; 1127 } 1128 1129 /* 1130 * It seems there is no way to strip FCS bytes. 1131 */ 1132 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1133 m->m_pkthdr.rcvif = ifp; 1134 ifp->if_ipackets++; 1135 bpf_mtap(ifp, m); 1136 (*ifp->if_input)(ifp, m); 1137 } 1138 1139 if (prog > 0) { 1140 /* Update the consumer index. */ 1141 sc->vte_cdata.vte_rx_cons = cons; 1142 /* 1143 * Sync updated RX descriptors such that controller see 1144 * modified RX buffer addresses. 1145 */ 1146 bus_dmamap_sync(sc->vte_dmatag, 1147 sc->vte_cdata.vte_rx_ring_map, 0, 1148 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1149 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1150 #ifdef notyet 1151 /* 1152 * Update residue counter. Controller does not 1153 * keep track of number of available RX descriptors 1154 * such that driver should have to update VTE_MRDCR 1155 * to make controller know how many free RX 1156 * descriptors were added to controller. This is 1157 * a similar mechanism used in VIA velocity 1158 * controllers and it indicates controller just 1159 * polls OWN bit of current RX descriptor pointer. 1160 * A couple of severe issues were seen on sample 1161 * board where the controller continuously emits TX 1162 * pause frames once RX pause threshold crossed. 1163 * Once triggered it never recovered form that 1164 * state, I couldn't find a way to make it back to 1165 * work at least. This issue effectively 1166 * disconnected the system from network. Also, the 1167 * controller used 00:00:00:00:00:00 as source 1168 * station address of TX pause frame. Probably this 1169 * is one of reason why vendor recommends not to 1170 * enable flow control on R6040 controller. 1171 */ 1172 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1173 (((VTE_RX_RING_CNT * 2) / 10) << 1174 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1175 #endif 1176 rnd_add_uint32(&sc->rnd_source, prog); 1177 } 1178 } 1179 1180 static void 1181 vte_tick(void *arg) 1182 { 1183 struct vte_softc *sc; 1184 int s = splnet(); 1185 1186 sc = (struct vte_softc *)arg; 1187 1188 mii_tick(&sc->vte_mii); 1189 vte_stats_update(sc); 1190 vte_txeof(sc); 1191 vte_ifwatchdog(&sc->vte_if); 1192 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1193 splx(s); 1194 } 1195 1196 static void 1197 vte_reset(struct vte_softc *sc) 1198 { 1199 uint16_t mcr; 1200 int i; 1201 1202 mcr = CSR_READ_2(sc, VTE_MCR1); 1203 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1204 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1205 DELAY(10); 1206 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1207 break; 1208 } 1209 if (i == 0) 1210 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1211 /* 1212 * Follow the guide of vendor recommended way to reset MAC. 1213 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1214 * not reliable so manually reset internal state machine. 1215 */ 1216 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1217 CSR_WRITE_2(sc, VTE_MACSM, 0); 1218 DELAY(5000); 1219 } 1220 1221 1222 static int 1223 vte_init(struct ifnet *ifp) 1224 { 1225 struct vte_softc *sc = ifp->if_softc; 1226 bus_addr_t paddr; 1227 uint8_t eaddr[ETHER_ADDR_LEN]; 1228 int s, error; 1229 1230 s = splnet(); 1231 /* 1232 * Cancel any pending I/O. 1233 */ 1234 vte_stop(ifp, 1); 1235 /* 1236 * Reset the chip to a known state. 1237 */ 1238 vte_reset(sc); 1239 1240 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1241 splx(s); 1242 return 0; 1243 } 1244 1245 /* Initialize RX descriptors. */ 1246 if (vte_init_rx_ring(sc) != 0) { 1247 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1248 vte_stop(ifp, 1); 1249 splx(s); 1250 return ENOMEM; 1251 } 1252 if (vte_init_tx_ring(sc) != 0) { 1253 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1254 vte_stop(ifp, 1); 1255 splx(s); 1256 return ENOMEM; 1257 } 1258 1259 /* 1260 * Reprogram the station address. Controller supports up 1261 * to 4 different station addresses so driver programs the 1262 * first station address as its own ethernet address and 1263 * configure the remaining three addresses as perfect 1264 * multicast addresses. 1265 */ 1266 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1267 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1268 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1269 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1270 1271 /* Set TX descriptor base addresses. */ 1272 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1273 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1274 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1275 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1276 1277 /* Set RX descriptor base addresses. */ 1278 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1279 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1280 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1281 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1282 /* 1283 * Initialize RX descriptor residue counter and set RX 1284 * pause threshold to 20% of available RX descriptors. 1285 * See comments on vte_rxeof() for details on flow control 1286 * issues. 1287 */ 1288 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1289 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1290 1291 /* 1292 * Always use maximum frame size that controller can 1293 * support. Otherwise received frames that has longer 1294 * frame length than vte(4) MTU would be silently dropped 1295 * in controller. This would break path-MTU discovery as 1296 * sender wouldn't get any responses from receiver. The 1297 * RX buffer size should be multiple of 4. 1298 * Note, jumbo frames are silently ignored by controller 1299 * and even MAC counters do not detect them. 1300 */ 1301 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1302 1303 /* Configure FIFO. */ 1304 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1305 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1306 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1307 1308 /* 1309 * Configure TX/RX MACs. Actual resolved duplex and flow 1310 * control configuration is done after detecting a valid 1311 * link. Note, we don't generate early interrupt here 1312 * as well since FreeBSD does not have interrupt latency 1313 * problems like Windows. 1314 */ 1315 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1316 /* 1317 * We manually keep track of PHY status changes to 1318 * configure resolved duplex and flow control since only 1319 * duplex configuration can be automatically reflected to 1320 * MCR0. 1321 */ 1322 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1323 MCR1_EXCESS_COL_RETRY_16); 1324 1325 /* Initialize RX filter. */ 1326 vte_rxfilter(sc); 1327 1328 /* Disable TX/RX interrupt moderation control. */ 1329 CSR_WRITE_2(sc, VTE_MRICR, 0); 1330 CSR_WRITE_2(sc, VTE_MTICR, 0); 1331 1332 /* Enable MAC event counter interrupts. */ 1333 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1334 /* Clear MAC statistics. */ 1335 vte_stats_clear(sc); 1336 1337 /* Acknowledge all pending interrupts and clear it. */ 1338 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1339 CSR_WRITE_2(sc, VTE_MISR, 0); 1340 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), CSR_READ_2(sc, VTE_MISR))); 1341 1342 sc->vte_flags &= ~VTE_FLAG_LINK; 1343 ifp->if_flags |= IFF_RUNNING; 1344 ifp->if_flags &= ~IFF_OACTIVE; 1345 1346 /* calling mii_mediachg will call back vte_start_mac() */ 1347 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1348 error = 0; 1349 else if (error != 0) { 1350 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1351 splx(s); 1352 return error; 1353 } 1354 1355 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1356 1357 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), CSR_READ_2(sc, VTE_MISR))); 1358 splx(s); 1359 return 0; 1360 } 1361 1362 static void 1363 vte_stop(struct ifnet *ifp, int disable) 1364 { 1365 struct vte_softc *sc = ifp->if_softc; 1366 struct vte_txdesc *txd; 1367 struct vte_rxdesc *rxd; 1368 int i; 1369 1370 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1371 if ((ifp->if_flags & IFF_RUNNING) == 0) 1372 return; 1373 /* 1374 * Mark the interface down and cancel the watchdog timer. 1375 */ 1376 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1377 sc->vte_flags &= ~VTE_FLAG_LINK; 1378 callout_stop(&sc->vte_tick_ch); 1379 sc->vte_watchdog_timer = 0; 1380 vte_stats_update(sc); 1381 /* Disable interrupts. */ 1382 CSR_WRITE_2(sc, VTE_MIER, 0); 1383 CSR_WRITE_2(sc, VTE_MECIER, 0); 1384 /* Stop RX/TX MACs. */ 1385 vte_stop_mac(sc); 1386 /* Clear interrupts. */ 1387 CSR_READ_2(sc, VTE_MISR); 1388 /* 1389 * Free TX/RX mbufs still in the queues. 1390 */ 1391 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1392 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1393 if (rxd->rx_m != NULL) { 1394 bus_dmamap_sync(sc->vte_dmatag, 1395 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1396 BUS_DMASYNC_POSTREAD); 1397 bus_dmamap_unload(sc->vte_dmatag, 1398 rxd->rx_dmamap); 1399 m_freem(rxd->rx_m); 1400 rxd->rx_m = NULL; 1401 } 1402 } 1403 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1404 txd = &sc->vte_cdata.vte_txdesc[i]; 1405 if (txd->tx_m != NULL) { 1406 bus_dmamap_sync(sc->vte_dmatag, 1407 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1408 BUS_DMASYNC_POSTWRITE); 1409 bus_dmamap_unload(sc->vte_dmatag, 1410 txd->tx_dmamap); 1411 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1412 m_freem(txd->tx_m); 1413 txd->tx_m = NULL; 1414 txd->tx_flags &= ~VTE_TXMBUF; 1415 } 1416 } 1417 /* Free TX mbuf pools used for deep copy. */ 1418 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1419 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1420 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1421 sc->vte_cdata.vte_txmbufs[i] = NULL; 1422 } 1423 } 1424 } 1425 1426 static void 1427 vte_start_mac(struct vte_softc *sc) 1428 { 1429 struct ifnet *ifp = &sc->vte_if; 1430 uint16_t mcr; 1431 int i; 1432 1433 /* Enable RX/TX MACs. */ 1434 mcr = CSR_READ_2(sc, VTE_MCR0); 1435 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1436 (MCR0_RX_ENB | MCR0_TX_ENB) && 1437 (ifp->if_flags & IFF_RUNNING) != 0) { 1438 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1439 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1440 for (i = VTE_TIMEOUT; i > 0; i--) { 1441 mcr = CSR_READ_2(sc, VTE_MCR0); 1442 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1443 (MCR0_RX_ENB | MCR0_TX_ENB)) 1444 break; 1445 DELAY(10); 1446 } 1447 if (i == 0) 1448 aprint_error_dev(sc->vte_dev, 1449 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1450 } 1451 vte_rxfilter(sc); 1452 } 1453 1454 static void 1455 vte_stop_mac(struct vte_softc *sc) 1456 { 1457 uint16_t mcr; 1458 int i; 1459 1460 /* Disable RX/TX MACs. */ 1461 mcr = CSR_READ_2(sc, VTE_MCR0); 1462 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1463 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1464 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1465 for (i = VTE_TIMEOUT; i > 0; i--) { 1466 mcr = CSR_READ_2(sc, VTE_MCR0); 1467 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1468 break; 1469 DELAY(10); 1470 } 1471 if (i == 0) 1472 aprint_error_dev(sc->vte_dev, 1473 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1474 } 1475 } 1476 1477 static int 1478 vte_init_tx_ring(struct vte_softc *sc) 1479 { 1480 struct vte_tx_desc *desc; 1481 struct vte_txdesc *txd; 1482 bus_addr_t addr; 1483 int i; 1484 1485 sc->vte_cdata.vte_tx_prod = 0; 1486 sc->vte_cdata.vte_tx_cons = 0; 1487 sc->vte_cdata.vte_tx_cnt = 0; 1488 1489 /* Pre-allocate TX mbufs for deep copy. */ 1490 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1491 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1492 MT_DATA, M_PKTHDR); 1493 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1494 return (ENOBUFS); 1495 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1496 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1497 } 1498 desc = sc->vte_cdata.vte_tx_ring; 1499 bzero(desc, VTE_TX_RING_SZ); 1500 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1501 txd = &sc->vte_cdata.vte_txdesc[i]; 1502 txd->tx_m = NULL; 1503 if (i != VTE_TX_RING_CNT - 1) 1504 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1505 sizeof(struct vte_tx_desc) * (i + 1); 1506 else 1507 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1508 sizeof(struct vte_tx_desc) * 0; 1509 desc = &sc->vte_cdata.vte_tx_ring[i]; 1510 desc->dtnp = htole32(addr); 1511 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1512 txd->tx_desc = desc; 1513 } 1514 1515 bus_dmamap_sync(sc->vte_dmatag, 1516 sc->vte_cdata.vte_tx_ring_map, 0, 1517 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1518 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1519 return (0); 1520 } 1521 1522 static int 1523 vte_init_rx_ring(struct vte_softc *sc) 1524 { 1525 struct vte_rx_desc *desc; 1526 struct vte_rxdesc *rxd; 1527 bus_addr_t addr; 1528 int i; 1529 1530 sc->vte_cdata.vte_rx_cons = 0; 1531 desc = sc->vte_cdata.vte_rx_ring; 1532 bzero(desc, VTE_RX_RING_SZ); 1533 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1534 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1535 rxd->rx_m = NULL; 1536 if (i != VTE_RX_RING_CNT - 1) 1537 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1538 + sizeof(struct vte_rx_desc) * (i + 1); 1539 else 1540 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1541 + sizeof(struct vte_rx_desc) * 0; 1542 desc = &sc->vte_cdata.vte_rx_ring[i]; 1543 desc->drnp = htole32(addr); 1544 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1545 rxd->rx_desc = desc; 1546 if (vte_newbuf(sc, rxd) != 0) 1547 return (ENOBUFS); 1548 } 1549 1550 bus_dmamap_sync(sc->vte_dmatag, 1551 sc->vte_cdata.vte_rx_ring_map, 0, 1552 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1554 1555 return (0); 1556 } 1557 1558 static void 1559 vte_rxfilter(struct vte_softc *sc) 1560 { 1561 struct ether_multistep step; 1562 struct ether_multi *enm; 1563 struct ifnet *ifp; 1564 uint8_t *eaddr; 1565 uint32_t crc; 1566 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1567 uint16_t mchash[4], mcr; 1568 int i, nperf; 1569 1570 ifp = &sc->vte_if; 1571 1572 DPRINTF(("vte_rxfilter\n")); 1573 memset(mchash, 0, sizeof(mchash)); 1574 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1575 rxfilt_perf[i][0] = 0xFFFF; 1576 rxfilt_perf[i][1] = 0xFFFF; 1577 rxfilt_perf[i][2] = 0xFFFF; 1578 } 1579 1580 mcr = CSR_READ_2(sc, VTE_MCR0); 1581 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1582 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST); 1583 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1584 mcr |= MCR0_BROADCAST_DIS; 1585 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1586 if ((ifp->if_flags & IFF_PROMISC) != 0) 1587 mcr |= MCR0_PROMISC; 1588 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1589 mcr |= MCR0_MULTICAST; 1590 mchash[0] = 0xFFFF; 1591 mchash[1] = 0xFFFF; 1592 mchash[2] = 0xFFFF; 1593 mchash[3] = 0xFFFF; 1594 goto chipit; 1595 } 1596 1597 ETHER_FIRST_MULTI(step, &sc->vte_ec, enm); 1598 nperf = 0; 1599 while (enm != NULL) { 1600 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1601 sc->vte_if.if_flags |= IFF_ALLMULTI; 1602 mcr |= MCR0_MULTICAST; 1603 mchash[0] = 0xFFFF; 1604 mchash[1] = 0xFFFF; 1605 mchash[2] = 0xFFFF; 1606 mchash[3] = 0xFFFF; 1607 goto chipit; 1608 } 1609 /* 1610 * Program the first 3 multicast groups into 1611 * the perfect filter. For all others, use the 1612 * hash table. 1613 */ 1614 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1615 eaddr = enm->enm_addrlo; 1616 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1617 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1618 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1619 nperf++; 1620 } else { 1621 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1622 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1623 } 1624 ETHER_NEXT_MULTI(step, enm); 1625 } 1626 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1627 mchash[3] != 0) 1628 mcr |= MCR0_MULTICAST; 1629 1630 chipit: 1631 /* Program multicast hash table. */ 1632 DPRINTF(("chipit write multicast\n")); 1633 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1634 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1635 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1636 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1637 /* Program perfect filter table. */ 1638 DPRINTF(("chipit write perfect filter\n")); 1639 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1640 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1641 rxfilt_perf[i][0]); 1642 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1643 rxfilt_perf[i][1]); 1644 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1645 rxfilt_perf[i][2]); 1646 } 1647 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1648 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1649 DPRINTF(("chipit read mcro\n")); 1650 CSR_READ_2(sc, VTE_MCR0); 1651 DPRINTF(("chipit done\n")); 1652 } 1653 1654 /* 1655 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1656 * set up in vte_pci_attach() 1657 */ 1658 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1659 { 1660 int rc; 1661 const struct sysctlnode *node; 1662 1663 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 1664 0, CTLTYPE_NODE, "hw", NULL, 1665 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 1666 goto err; 1667 } 1668 1669 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1670 0, CTLTYPE_NODE, "vte", 1671 SYSCTL_DESCR("vte interface controls"), 1672 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1673 goto err; 1674 } 1675 1676 vte_root_num = node->sysctl_num; 1677 return; 1678 1679 err: 1680 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1681 } 1682 1683 static int 1684 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1685 { 1686 int error, t; 1687 struct sysctlnode node; 1688 struct vte_softc *sc; 1689 1690 node = *rnode; 1691 sc = node.sysctl_data; 1692 t = sc->vte_int_rx_mod; 1693 node.sysctl_data = &t; 1694 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1695 if (error || newp == NULL) 1696 return error; 1697 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1698 return EINVAL; 1699 1700 sc->vte_int_rx_mod = t; 1701 vte_miibus_statchg(sc->vte_dev); 1702 return 0; 1703 } 1704 1705 static int 1706 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1707 { 1708 int error, t; 1709 struct sysctlnode node; 1710 struct vte_softc *sc; 1711 1712 node = *rnode; 1713 sc = node.sysctl_data; 1714 t = sc->vte_int_tx_mod; 1715 node.sysctl_data = &t; 1716 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1717 if (error || newp == NULL) 1718 return error; 1719 1720 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1721 return EINVAL; 1722 sc->vte_int_tx_mod = t; 1723 vte_miibus_statchg(sc->vte_dev); 1724 return 0; 1725 } 1726
Indexes created Thu Oct 02 01:09:59 GMT 2025