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if_wi_pci.c revision 1.25.2.4
      1  1.25.2.4     skrll /*      $NetBSD: if_wi_pci.c,v 1.25.2.4 2004/08/25 06:58:06 skrll Exp $  */
      2       1.1    ichiro 
      3       1.1    ichiro /*-
      4       1.1    ichiro  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5       1.1    ichiro  * All rights reserved.
      6       1.1    ichiro  *
      7       1.1    ichiro  * This code is derived from software contributed to The NetBSD Foundation
      8       1.1    ichiro  * by Hideaki Imaizumi <hiddy (at) sfc.wide.ad.jp>
      9       1.1    ichiro  * and Ichiro FUKUHARA (ichiro (at) ichiro.org).
     10       1.1    ichiro  *
     11       1.1    ichiro  * Redistribution and use in source and binary forms, with or without
     12       1.1    ichiro  * modification, are permitted provided that the following conditions
     13       1.1    ichiro  * are met:
     14       1.1    ichiro  * 1. Redistributions of source code must retain the above copyright
     15       1.1    ichiro  *    notice, this list of conditions and the following disclaimer.
     16       1.1    ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     17       1.1    ichiro  *    notice, this list of conditions and the following disclaimer in the
     18       1.1    ichiro  *    documentation and/or other materials provided with the distribution.
     19       1.1    ichiro  * 3. All advertising materials mentioning features or use of this software
     20       1.1    ichiro  *    must display the following acknowledgement:
     21       1.1    ichiro  *        This product includes software developed by the NetBSD
     22       1.1    ichiro  *        Foundation, Inc. and its contributors.
     23       1.1    ichiro  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24       1.1    ichiro  *    contributors may be used to endorse or promote products derived
     25       1.1    ichiro  *    from this software without specific prior written permission.
     26       1.1    ichiro  *
     27       1.1    ichiro  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28       1.1    ichiro  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29       1.1    ichiro  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30       1.1    ichiro  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31       1.1    ichiro  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32       1.1    ichiro  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33       1.1    ichiro  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34       1.1    ichiro  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35       1.1    ichiro  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36       1.1    ichiro  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37       1.1    ichiro  * POSSIBILITY OF SUCH DAMAGE.
     38       1.1    ichiro  */
     39       1.1    ichiro 
     40       1.1    ichiro /*
     41       1.1    ichiro  * PCI bus front-end for the Intersil PCI WaveLan.
     42       1.1    ichiro  * Works with Prism2.5 Mini-PCI wavelan.
     43       1.1    ichiro  */
     44       1.2     lukem 
     45       1.2     lukem #include <sys/cdefs.h>
     46  1.25.2.4     skrll __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.25.2.4 2004/08/25 06:58:06 skrll Exp $");
     47       1.1    ichiro 
     48       1.1    ichiro #include <sys/param.h>
     49       1.1    ichiro #include <sys/systm.h>
     50       1.1    ichiro #include <sys/mbuf.h>
     51       1.1    ichiro #include <sys/syslog.h>
     52       1.1    ichiro #include <sys/socket.h>
     53       1.1    ichiro #include <sys/device.h>
     54       1.1    ichiro #include <sys/callout.h>
     55       1.1    ichiro 
     56       1.1    ichiro #include <net/if.h>
     57       1.1    ichiro #include <net/if_ether.h>
     58       1.1    ichiro #include <net/if_media.h>
     59  1.25.2.2     skrll 
     60  1.25.2.2     skrll #include <net80211/ieee80211_var.h>
     61  1.25.2.2     skrll #include <net80211/ieee80211_compat.h>
     62  1.25.2.2     skrll #include <net80211/ieee80211_radiotap.h>
     63  1.25.2.2     skrll #include <net80211/ieee80211_rssadapt.h>
     64       1.1    ichiro 
     65       1.1    ichiro #include <machine/bus.h>
     66       1.1    ichiro #include <machine/intr.h>
     67       1.1    ichiro 
     68       1.1    ichiro #include <dev/pci/pcireg.h>
     69       1.1    ichiro #include <dev/pci/pcivar.h>
     70       1.1    ichiro #include <dev/pci/pcidevs.h>
     71       1.1    ichiro 
     72       1.1    ichiro #include <dev/ic/wi_ieee.h>
     73       1.1    ichiro #include <dev/ic/wireg.h>
     74       1.1    ichiro #include <dev/ic/wivar.h>
     75       1.1    ichiro 
     76      1.13     soren #define WI_PCI_CBMA		0x10	/* Configuration Base Memory Address */
     77       1.3  augustss #define WI_PCI_PLX_LOMEM	0x10	/* PLX chip membase */
     78       1.3  augustss #define WI_PCI_PLX_LOIO		0x14	/* PLX chip iobase */
     79       1.3  augustss #define WI_PCI_LOMEM		0x18	/* ISA membase */
     80       1.3  augustss #define WI_PCI_LOIO		0x1C	/* ISA iobase */
     81       1.3  augustss 
     82      1.23  christos #define CHIP_PLX_OTHER		0x01
     83      1.23  christos #define CHIP_PLX_9052		0x02
     84  1.25.2.2     skrll #define CHIP_TMD_7160		0x03
     85      1.23  christos 
     86       1.3  augustss #define WI_PLX_COR_OFFSET       0x3E0
     87       1.3  augustss #define WI_PLX_COR_VALUE        0x41
     88       1.3  augustss 
     89       1.1    ichiro struct wi_pci_softc {
     90       1.1    ichiro 	struct wi_softc psc_wi;		/* real "wi" softc */
     91       1.1    ichiro 
     92       1.1    ichiro 	/* PCI-specific goo */
     93       1.1    ichiro 	pci_intr_handle_t psc_ih;
     94  1.25.2.2     skrll 	pci_chipset_tag_t psc_pc;
     95       1.1    ichiro 
     96       1.1    ichiro 	void *sc_powerhook;		/* power hook descriptor */
     97       1.1    ichiro };
     98       1.1    ichiro 
     99  1.25.2.4     skrll static int	wi_pci_match(struct device *, struct cfdata *, void *);
    100  1.25.2.4     skrll static void	wi_pci_attach(struct device *, struct device *, void *);
    101  1.25.2.4     skrll static int	wi_pci_enable(struct wi_softc *);
    102  1.25.2.4     skrll static void	wi_pci_disable(struct wi_softc *);
    103  1.25.2.4     skrll static void	wi_pci_reset(struct wi_softc *);
    104  1.25.2.4     skrll static void	wi_pci_powerhook(int, void *);
    105       1.1    ichiro 
    106       1.1    ichiro static const struct wi_pci_product
    107  1.25.2.4     skrll 	*wi_pci_lookup(struct pci_attach_args *);
    108       1.1    ichiro 
    109      1.11   thorpej CFATTACH_DECL(wi_pci, sizeof(struct wi_pci_softc),
    110      1.12   thorpej     wi_pci_match, wi_pci_attach, NULL, NULL);
    111       1.1    ichiro 
    112  1.25.2.4     skrll static const struct wi_pci_product {
    113       1.1    ichiro 	pci_vendor_id_t		wpp_vendor;	/* vendor ID */
    114       1.1    ichiro 	pci_product_id_t	wpp_product;	/* product ID */
    115  1.25.2.2     skrll 	int			wpp_chip;	/* uses other chip */
    116       1.1    ichiro } wi_pci_products[] = {
    117       1.3  augustss 	{ PCI_VENDOR_GLOBALSUN,		PCI_PRODUCT_GLOBALSUN_GL24110P,
    118  1.25.2.2     skrll 	  CHIP_PLX_OTHER },
    119       1.3  augustss 	{ PCI_VENDOR_GLOBALSUN,		PCI_PRODUCT_GLOBALSUN_GL24110P02,
    120  1.25.2.2     skrll 	  CHIP_PLX_OTHER },
    121       1.3  augustss 	{ PCI_VENDOR_EUMITCOM,		PCI_PRODUCT_EUMITCOM_WL11000P,
    122  1.25.2.2     skrll 	  CHIP_PLX_OTHER },
    123       1.3  augustss 	{ PCI_VENDOR_3COM,		PCI_PRODUCT_3COM_3CRWE777A,
    124  1.25.2.2     skrll 	  CHIP_PLX_OTHER },
    125       1.3  augustss 	{ PCI_VENDOR_NETGEAR,		PCI_PRODUCT_NETGEAR_MA301,
    126  1.25.2.2     skrll 	  CHIP_PLX_OTHER },
    127       1.1    ichiro 	{ PCI_VENDOR_INTERSIL,		PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN,
    128  1.25.2.2     skrll 	  0 },
    129      1.20     perry 	{ PCI_VENDOR_NDC,		PCI_PRODUCT_NDC_NCP130,
    130  1.25.2.2     skrll 	  CHIP_PLX_9052 },
    131      1.22       jdc 	{ PCI_VENDOR_USR2,		PCI_PRODUCT_USR2_2415,
    132  1.25.2.2     skrll 	  CHIP_PLX_OTHER },
    133  1.25.2.2     skrll 	{ PCI_VENDOR_NDC,		PCI_PRODUCT_NDC_NCP130A2,
    134  1.25.2.2     skrll 	  CHIP_TMD_7160 },
    135       1.1    ichiro 	{ 0,				0,
    136  1.25.2.2     skrll 	  0},
    137       1.1    ichiro };
    138       1.1    ichiro 
    139       1.1    ichiro static int
    140  1.25.2.4     skrll wi_pci_enable(struct wi_softc *sc)
    141       1.1    ichiro {
    142       1.1    ichiro 	struct wi_pci_softc *psc = (struct wi_pci_softc *)sc;
    143       1.1    ichiro 
    144       1.1    ichiro 	/* establish the interrupt. */
    145  1.25.2.2     skrll 	sc->sc_ih = pci_intr_establish(psc->psc_pc,
    146       1.1    ichiro 					psc->psc_ih, IPL_NET, wi_intr, sc);
    147       1.1    ichiro 	if (sc->sc_ih == NULL) {
    148       1.1    ichiro 		printf("%s: couldn't establish interrupt\n",
    149       1.1    ichiro 		    sc->sc_dev.dv_xname);
    150       1.1    ichiro 		return (EIO);
    151       1.1    ichiro 	}
    152       1.1    ichiro 
    153       1.1    ichiro 	/* reset HFA3842 MAC core */
    154  1.25.2.2     skrll 	if (sc->sc_reset != NULL)
    155  1.25.2.2     skrll 		wi_pci_reset(sc);
    156       1.1    ichiro 
    157       1.1    ichiro 	return (0);
    158       1.1    ichiro }
    159       1.1    ichiro 
    160       1.1    ichiro static void
    161  1.25.2.4     skrll wi_pci_disable(struct wi_softc *sc)
    162       1.1    ichiro {
    163       1.1    ichiro 	struct wi_pci_softc *psc = (struct wi_pci_softc *)sc;
    164       1.1    ichiro 
    165  1.25.2.2     skrll 	pci_intr_disestablish(psc->psc_pc, sc->sc_ih);
    166       1.7  jdolecek }
    167       1.7  jdolecek 
    168       1.7  jdolecek static void
    169  1.25.2.4     skrll wi_pci_reset(struct wi_softc *sc)
    170       1.7  jdolecek {
    171       1.8   thorpej 	int i, secs, usecs;
    172       1.7  jdolecek 
    173  1.25.2.3     skrll 	bus_space_write_2(sc->sc_iot, sc->sc_ioh,
    174  1.25.2.3     skrll 	    WI_PCI_COR, WI_COR_SOFT_RESET);
    175       1.8   thorpej 	DELAY(250*1000); /* 1/4 second */
    176       1.8   thorpej 
    177  1.25.2.3     skrll 	bus_space_write_2(sc->sc_iot, sc->sc_ioh,
    178  1.25.2.3     skrll 	    WI_PCI_COR, WI_COR_CLEAR);
    179       1.8   thorpej 	DELAY(500*1000); /* 1/2 second */
    180       1.8   thorpej 
    181       1.8   thorpej 	/* wait 2 seconds for firmware to complete initialization. */
    182       1.8   thorpej 
    183       1.8   thorpej 	for (i = 200000; i--; DELAY(10))
    184       1.8   thorpej 		if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))
    185       1.8   thorpej 			break;
    186       1.8   thorpej 
    187       1.8   thorpej 	if (i < 0) {
    188       1.8   thorpej 		printf("%s: PCI reset timed out\n", sc->sc_dev.dv_xname);
    189      1.10      onoe 	} else if (sc->sc_if.if_flags & IFF_DEBUG) {
    190       1.8   thorpej 		usecs = (200000 - i) * 10;
    191       1.8   thorpej 		secs = usecs / 1000000;
    192       1.8   thorpej 		usecs %= 1000000;
    193       1.8   thorpej 
    194       1.8   thorpej 		printf("%s: PCI reset in %d.%06d seconds\n",
    195       1.8   thorpej                        sc->sc_dev.dv_xname, secs, usecs);
    196       1.8   thorpej 	}
    197       1.7  jdolecek 
    198       1.7  jdolecek 	return;
    199       1.1    ichiro }
    200       1.1    ichiro 
    201       1.1    ichiro static const struct wi_pci_product *
    202  1.25.2.4     skrll wi_pci_lookup(struct pci_attach_args *pa)
    203       1.1    ichiro {
    204       1.1    ichiro 	const struct wi_pci_product *wpp;
    205       1.1    ichiro 
    206       1.3  augustss 	for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) {
    207       1.1    ichiro 		if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor &&
    208       1.1    ichiro 		    PCI_PRODUCT(pa->pa_id) == wpp->wpp_product)
    209       1.1    ichiro 			return (wpp);
    210       1.1    ichiro 	}
    211       1.1    ichiro 	return (NULL);
    212       1.1    ichiro }
    213       1.1    ichiro 
    214       1.1    ichiro static int
    215  1.25.2.4     skrll wi_pci_match(struct device *parent, struct cfdata *match, void *aux)
    216       1.1    ichiro {
    217       1.1    ichiro 	struct pci_attach_args *pa = aux;
    218       1.1    ichiro 
    219       1.1    ichiro 	if (wi_pci_lookup(pa) != NULL)
    220       1.1    ichiro 		return (1);
    221       1.1    ichiro 	return (0);
    222       1.1    ichiro }
    223       1.1    ichiro 
    224       1.1    ichiro static void
    225  1.25.2.4     skrll wi_pci_attach(struct device *parent, struct device *self, void *aux)
    226       1.1    ichiro {
    227       1.1    ichiro 	struct wi_pci_softc *psc = (struct wi_pci_softc *)self;
    228       1.1    ichiro 	struct wi_softc *sc = &psc->psc_wi;
    229       1.1    ichiro 	struct pci_attach_args *pa = aux;
    230       1.1    ichiro 	pci_chipset_tag_t pc = pa->pa_pc;
    231       1.1    ichiro 	const char *intrstr;
    232       1.1    ichiro 	const struct wi_pci_product *wpp;
    233       1.1    ichiro 	pci_intr_handle_t ih;
    234  1.25.2.2     skrll 	bus_space_tag_t memt, iot, plxt, tmdt;
    235  1.25.2.2     skrll 	bus_space_handle_t memh, ioh, plxh, tmdh;
    236       1.1    ichiro 
    237  1.25.2.2     skrll 	psc->psc_pc = pc;
    238       1.1    ichiro 
    239       1.5  augustss 	wpp = wi_pci_lookup(pa);
    240       1.5  augustss #ifdef DIAGNOSTIC
    241       1.5  augustss 	if (wpp == NULL) {
    242       1.5  augustss 		printf("\n");
    243       1.5  augustss 		panic("wi_pci_attach: impossible");
    244       1.5  augustss 	}
    245       1.5  augustss #endif
    246       1.5  augustss 
    247  1.25.2.2     skrll 	switch (wpp->wpp_chip) {
    248  1.25.2.2     skrll 	case CHIP_PLX_OTHER:
    249  1.25.2.2     skrll 	case CHIP_PLX_9052:
    250       1.3  augustss 		/* Map memory and I/O registers. */
    251       1.3  augustss 		if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
    252       1.3  augustss 		    &memt, &memh, NULL, NULL) != 0) {
    253       1.3  augustss 			printf(": can't map mem space\n");
    254       1.3  augustss 			return;
    255       1.3  augustss 		}
    256       1.3  augustss 		if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
    257       1.3  augustss 		    &iot, &ioh, NULL, NULL) != 0) {
    258       1.3  augustss 			printf(": can't map I/O space\n");
    259       1.3  augustss 			return;
    260       1.3  augustss 		}
    261      1.23  christos 
    262  1.25.2.2     skrll 		if (wpp->wpp_chip == CHIP_PLX_OTHER) {
    263      1.23  christos 			/* The PLX 9052 doesn't have IO at 0x14.  Perhaps
    264      1.23  christos 			   other chips have, so we'll make this conditional. */
    265      1.23  christos 			if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO,
    266      1.23  christos 				PCI_MAPREG_TYPE_IO, 0, &plxt,
    267      1.23  christos 				&plxh, NULL, NULL) != 0) {
    268      1.23  christos 					printf(": can't map PLX\n");
    269      1.23  christos 					return;
    270      1.23  christos 				}
    271      1.21    dyoung 		}
    272  1.25.2.2     skrll 		break;
    273  1.25.2.2     skrll 	case CHIP_TMD_7160:
    274  1.25.2.2     skrll 		/* Used instead of PLX on at least one revision of
    275  1.25.2.2     skrll 		 * the National Datacomm Corporation NCP130. Values
    276  1.25.2.2     skrll 		 * for registers acquired from OpenBSD, which in
    277  1.25.2.2     skrll 		 * turn got them from a Linux driver.
    278  1.25.2.2     skrll 		 */
    279  1.25.2.2     skrll 		/* Map COR and I/O registers. */
    280  1.25.2.2     skrll 		if (pci_mapreg_map(pa, WI_TMD_COR, PCI_MAPREG_TYPE_IO, 0,
    281  1.25.2.2     skrll 		    &tmdt, &tmdh, NULL, NULL) != 0) {
    282  1.25.2.2     skrll 			printf(": can't map TMD\n");
    283  1.25.2.2     skrll 			return;
    284  1.25.2.2     skrll 		}
    285  1.25.2.2     skrll 		if (pci_mapreg_map(pa, WI_TMD_IO, PCI_MAPREG_TYPE_IO, 0,
    286  1.25.2.2     skrll 		    &iot, &ioh, NULL, NULL) != 0) {
    287  1.25.2.2     skrll 			printf(": can't map I/O space\n");
    288  1.25.2.2     skrll 			return;
    289  1.25.2.2     skrll 		}
    290  1.25.2.2     skrll 		break;
    291  1.25.2.2     skrll 	default:
    292       1.3  augustss 		if (pci_mapreg_map(pa, WI_PCI_CBMA,
    293       1.3  augustss 		    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
    294       1.3  augustss 		    0, &iot, &ioh, NULL, NULL) != 0) {
    295       1.3  augustss 			printf(": can't map mem space\n");
    296       1.3  augustss 			return;
    297       1.3  augustss 		}
    298       1.3  augustss 
    299       1.3  augustss 		memt = iot;
    300       1.3  augustss 		memh = ioh;
    301       1.3  augustss 		sc->sc_pci = 1;
    302  1.25.2.2     skrll 		break;
    303       1.1    ichiro 	}
    304       1.1    ichiro 
    305  1.25.2.2     skrll 	{
    306       1.3  augustss 		char devinfo[256];
    307       1.3  augustss 
    308  1.25.2.2     skrll 		pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
    309       1.3  augustss 		printf(": %s (rev. 0x%02x)\n", devinfo,
    310       1.3  augustss 		       PCI_REVISION(pa->pa_class));
    311       1.3  augustss 	}
    312       1.1    ichiro 
    313       1.1    ichiro 	sc->sc_enabled = 1;
    314       1.1    ichiro 	sc->sc_enable = wi_pci_enable;
    315       1.1    ichiro 	sc->sc_disable = wi_pci_disable;
    316  1.25.2.1   darrenr 
    317       1.3  augustss 	sc->sc_iot = iot;
    318       1.3  augustss 	sc->sc_ioh = ioh;
    319       1.3  augustss 	/* Make sure interrupts are disabled. */
    320       1.3  augustss 	CSR_WRITE_2(sc, WI_INT_EN, 0);
    321       1.3  augustss 	CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
    322      1.21    dyoung 
    323  1.25.2.2     skrll 	if (wpp->wpp_chip == CHIP_PLX_OTHER) {
    324      1.21    dyoung 		uint32_t command;
    325      1.21    dyoung #define	WI_LOCAL_INTCSR		0x4c
    326      1.21    dyoung #define	WI_LOCAL_INTEN		0x40	/* poke this into INTCSR */
    327      1.21    dyoung 
    328      1.21    dyoung 		command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR);
    329      1.21    dyoung 		command |= WI_LOCAL_INTEN;
    330      1.21    dyoung 		bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command);
    331      1.21    dyoung 	}
    332       1.1    ichiro 
    333       1.1    ichiro 	/* Map and establish the interrupt. */
    334       1.1    ichiro 	if (pci_intr_map(pa, &ih)) {
    335  1.25.2.3     skrll 		printf("%s: couldn't map interrupt\n", self->dv_xname);
    336       1.1    ichiro 		return;
    337       1.1    ichiro 	}
    338       1.1    ichiro 	intrstr = pci_intr_string(pc, ih);
    339       1.1    ichiro 
    340       1.1    ichiro 	psc->psc_ih = ih;
    341       1.1    ichiro 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc);
    342       1.1    ichiro 	if (sc->sc_ih == NULL) {
    343  1.25.2.3     skrll 		printf("%s: couldn't establish interrupt", self->dv_xname);
    344       1.1    ichiro 		if (intrstr != NULL)
    345       1.1    ichiro 			printf(" at %s", intrstr);
    346       1.1    ichiro 		printf("\n");
    347       1.1    ichiro 		return;
    348       1.1    ichiro 	}
    349       1.1    ichiro 
    350  1.25.2.3     skrll 	printf("%s: interrupting at %s\n", self->dv_xname, intrstr);
    351       1.1    ichiro 
    352  1.25.2.2     skrll 	switch (wpp->wpp_chip) {
    353  1.25.2.2     skrll 	case CHIP_PLX_OTHER:
    354  1.25.2.2     skrll 	case CHIP_PLX_9052:
    355       1.3  augustss 		/*
    356       1.3  augustss 		 * Setup the PLX chip for level interrupts and config index 1
    357       1.3  augustss 		 * XXX - should really reset the PLX chip too.
    358       1.3  augustss 		 */
    359       1.3  augustss 		bus_space_write_1(memt, memh,
    360       1.3  augustss 		    WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE);
    361  1.25.2.2     skrll 		break;
    362  1.25.2.2     skrll 	case CHIP_TMD_7160:
    363  1.25.2.2     skrll 		/* Enable I/O mode and level interrupts on the embedded
    364  1.25.2.2     skrll 		 * card. The card's COR is the first byte of BAR 0.
    365  1.25.2.2     skrll 		 */
    366  1.25.2.2     skrll 		bus_space_write_1(tmdt, tmdh, 0, WI_COR_IOMODE);
    367  1.25.2.2     skrll 		break;
    368  1.25.2.2     skrll 	default:
    369       1.3  augustss 		/* reset HFA3842 MAC core */
    370       1.3  augustss 		wi_pci_reset(sc);
    371  1.25.2.2     skrll 		break;
    372       1.3  augustss 	}
    373       1.1    ichiro 
    374  1.25.2.3     skrll 	printf("%s:", self->dv_xname);
    375  1.25.2.3     skrll 
    376  1.25.2.3     skrll 	if (wi_attach(sc, 0) != 0) {
    377  1.25.2.3     skrll 		printf("%s: failed to attach controller\n", self->dv_xname);
    378       1.1    ichiro 		pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
    379       1.1    ichiro 		return;
    380       1.1    ichiro 	}
    381      1.17    dyoung 
    382  1.25.2.2     skrll 	if (!wpp->wpp_chip)
    383  1.25.2.2     skrll 		sc->sc_reset = wi_pci_reset;
    384       1.1    ichiro 
    385       1.1    ichiro 	/* Add a suspend hook to restore PCI config state */
    386       1.1    ichiro 	psc->sc_powerhook = powerhook_establish(wi_pci_powerhook, psc);
    387       1.1    ichiro 	if (psc->sc_powerhook == NULL)
    388  1.25.2.3     skrll 		printf("%s: WARNING: unable to establish pci power hook\n",
    389  1.25.2.3     skrll 		    self->dv_xname);
    390       1.1    ichiro }
    391       1.1    ichiro 
    392       1.1    ichiro static void
    393  1.25.2.4     skrll wi_pci_powerhook(int why, void *arg)
    394       1.1    ichiro {
    395       1.1    ichiro 	struct wi_pci_softc *psc = arg;
    396       1.1    ichiro 	struct wi_softc *sc = &psc->psc_wi;
    397       1.1    ichiro 
    398       1.1    ichiro 	wi_power(sc, why);
    399       1.1    ichiro }
    400