if_wi_pci.c revision 1.27 1 1.27 dyoung /* $NetBSD: if_wi_pci.c,v 1.27 2003/10/13 08:07:22 dyoung Exp $ */
2 1.1 ichiro
3 1.1 ichiro /*-
4 1.1 ichiro * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 1.1 ichiro * All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * This code is derived from software contributed to The NetBSD Foundation
8 1.1 ichiro * by Hideaki Imaizumi <hiddy (at) sfc.wide.ad.jp>
9 1.1 ichiro * and Ichiro FUKUHARA (ichiro (at) ichiro.org).
10 1.1 ichiro *
11 1.1 ichiro * Redistribution and use in source and binary forms, with or without
12 1.1 ichiro * modification, are permitted provided that the following conditions
13 1.1 ichiro * are met:
14 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
15 1.1 ichiro * notice, this list of conditions and the following disclaimer.
16 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
18 1.1 ichiro * documentation and/or other materials provided with the distribution.
19 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
20 1.1 ichiro * must display the following acknowledgement:
21 1.1 ichiro * This product includes software developed by the NetBSD
22 1.1 ichiro * Foundation, Inc. and its contributors.
23 1.1 ichiro * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 ichiro * contributors may be used to endorse or promote products derived
25 1.1 ichiro * from this software without specific prior written permission.
26 1.1 ichiro *
27 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 ichiro * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 ichiro * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 ichiro * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 ichiro * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 ichiro * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 ichiro * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 ichiro * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 ichiro * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 ichiro * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 ichiro * POSSIBILITY OF SUCH DAMAGE.
38 1.1 ichiro */
39 1.1 ichiro
40 1.1 ichiro /*
41 1.1 ichiro * PCI bus front-end for the Intersil PCI WaveLan.
42 1.1 ichiro * Works with Prism2.5 Mini-PCI wavelan.
43 1.1 ichiro */
44 1.2 lukem
45 1.2 lukem #include <sys/cdefs.h>
46 1.27 dyoung __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.27 2003/10/13 08:07:22 dyoung Exp $");
47 1.1 ichiro
48 1.1 ichiro #include <sys/param.h>
49 1.1 ichiro #include <sys/systm.h>
50 1.1 ichiro #include <sys/mbuf.h>
51 1.1 ichiro #include <sys/syslog.h>
52 1.1 ichiro #include <sys/socket.h>
53 1.1 ichiro #include <sys/device.h>
54 1.1 ichiro #include <sys/callout.h>
55 1.1 ichiro
56 1.1 ichiro #include <net/if.h>
57 1.1 ichiro #include <net/if_ether.h>
58 1.1 ichiro #include <net/if_media.h>
59 1.27 dyoung
60 1.27 dyoung #include <net80211/ieee80211_var.h>
61 1.27 dyoung #include <net80211/ieee80211_compat.h>
62 1.1 ichiro
63 1.1 ichiro #include <machine/bus.h>
64 1.1 ichiro #include <machine/intr.h>
65 1.1 ichiro
66 1.1 ichiro #include <dev/pci/pcireg.h>
67 1.1 ichiro #include <dev/pci/pcivar.h>
68 1.1 ichiro #include <dev/pci/pcidevs.h>
69 1.1 ichiro
70 1.1 ichiro #include <dev/ic/wi_ieee.h>
71 1.1 ichiro #include <dev/ic/wireg.h>
72 1.1 ichiro #include <dev/ic/wivar.h>
73 1.1 ichiro
74 1.13 soren #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */
75 1.3 augustss #define WI_PCI_PLX_LOMEM 0x10 /* PLX chip membase */
76 1.3 augustss #define WI_PCI_PLX_LOIO 0x14 /* PLX chip iobase */
77 1.3 augustss #define WI_PCI_LOMEM 0x18 /* ISA membase */
78 1.3 augustss #define WI_PCI_LOIO 0x1C /* ISA iobase */
79 1.3 augustss
80 1.23 christos #define CHIP_PLX_OTHER 0x01
81 1.23 christos #define CHIP_PLX_9052 0x02
82 1.23 christos
83 1.3 augustss #define WI_PLX_COR_OFFSET 0x3E0
84 1.3 augustss #define WI_PLX_COR_VALUE 0x41
85 1.3 augustss
86 1.1 ichiro struct wi_pci_softc {
87 1.1 ichiro struct wi_softc psc_wi; /* real "wi" softc */
88 1.1 ichiro
89 1.1 ichiro /* PCI-specific goo */
90 1.1 ichiro pci_intr_handle_t psc_ih;
91 1.26 scw pci_chipset_tag_t psc_pc;
92 1.1 ichiro
93 1.1 ichiro void *sc_powerhook; /* power hook descriptor */
94 1.1 ichiro };
95 1.1 ichiro
96 1.1 ichiro static int wi_pci_match __P((struct device *, struct cfdata *, void *));
97 1.1 ichiro static void wi_pci_attach __P((struct device *, struct device *, void *));
98 1.1 ichiro static int wi_pci_enable __P((struct wi_softc *));
99 1.1 ichiro static void wi_pci_disable __P((struct wi_softc *));
100 1.7 jdolecek static void wi_pci_reset __P((struct wi_softc *));
101 1.1 ichiro static void wi_pci_powerhook __P((int, void *));
102 1.1 ichiro
103 1.1 ichiro static const struct wi_pci_product
104 1.1 ichiro *wi_pci_lookup __P((struct pci_attach_args *));
105 1.1 ichiro
106 1.11 thorpej CFATTACH_DECL(wi_pci, sizeof(struct wi_pci_softc),
107 1.12 thorpej wi_pci_match, wi_pci_attach, NULL, NULL);
108 1.1 ichiro
109 1.1 ichiro const struct wi_pci_product {
110 1.1 ichiro pci_vendor_id_t wpp_vendor; /* vendor ID */
111 1.1 ichiro pci_product_id_t wpp_product; /* product ID */
112 1.1 ichiro const char *wpp_name; /* product name */
113 1.3 augustss int wpp_plx; /* uses PLX chip */
114 1.1 ichiro } wi_pci_products[] = {
115 1.3 augustss { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P,
116 1.23 christos NULL, CHIP_PLX_OTHER },
117 1.3 augustss { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02,
118 1.23 christos NULL, CHIP_PLX_OTHER },
119 1.3 augustss { PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P,
120 1.23 christos NULL, CHIP_PLX_OTHER },
121 1.3 augustss { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A,
122 1.23 christos NULL, CHIP_PLX_OTHER },
123 1.3 augustss { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301,
124 1.23 christos NULL, CHIP_PLX_OTHER },
125 1.1 ichiro { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN,
126 1.3 augustss "Intersil Prism2.5", 0 },
127 1.20 perry { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130,
128 1.23 christos NULL, CHIP_PLX_9052 },
129 1.22 jdc { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_2415,
130 1.23 christos NULL, CHIP_PLX_OTHER },
131 1.1 ichiro { 0, 0,
132 1.3 augustss NULL, 0},
133 1.1 ichiro };
134 1.1 ichiro
135 1.1 ichiro static int
136 1.1 ichiro wi_pci_enable(sc)
137 1.1 ichiro struct wi_softc *sc;
138 1.1 ichiro {
139 1.1 ichiro struct wi_pci_softc *psc = (struct wi_pci_softc *)sc;
140 1.1 ichiro
141 1.1 ichiro /* establish the interrupt. */
142 1.26 scw sc->sc_ih = pci_intr_establish(psc->psc_pc,
143 1.1 ichiro psc->psc_ih, IPL_NET, wi_intr, sc);
144 1.1 ichiro if (sc->sc_ih == NULL) {
145 1.1 ichiro printf("%s: couldn't establish interrupt\n",
146 1.1 ichiro sc->sc_dev.dv_xname);
147 1.1 ichiro return (EIO);
148 1.1 ichiro }
149 1.1 ichiro
150 1.1 ichiro /* reset HFA3842 MAC core */
151 1.1 ichiro wi_pci_reset(sc);
152 1.1 ichiro
153 1.1 ichiro return (0);
154 1.1 ichiro }
155 1.1 ichiro
156 1.1 ichiro static void
157 1.1 ichiro wi_pci_disable(sc)
158 1.1 ichiro struct wi_softc *sc;
159 1.1 ichiro {
160 1.1 ichiro struct wi_pci_softc *psc = (struct wi_pci_softc *)sc;
161 1.1 ichiro
162 1.26 scw pci_intr_disestablish(psc->psc_pc, sc->sc_ih);
163 1.7 jdolecek }
164 1.7 jdolecek
165 1.7 jdolecek static void
166 1.7 jdolecek wi_pci_reset(sc)
167 1.7 jdolecek struct wi_softc *sc;
168 1.7 jdolecek {
169 1.8 thorpej int i, secs, usecs;
170 1.7 jdolecek
171 1.25 fvdl bus_space_write_2(sc->sc_iot, sc->sc_ioh,
172 1.25 fvdl WI_PCI_COR, WI_COR_SOFT_RESET);
173 1.8 thorpej DELAY(250*1000); /* 1/4 second */
174 1.8 thorpej
175 1.25 fvdl bus_space_write_2(sc->sc_iot, sc->sc_ioh,
176 1.25 fvdl WI_PCI_COR, WI_COR_CLEAR);
177 1.8 thorpej DELAY(500*1000); /* 1/2 second */
178 1.8 thorpej
179 1.8 thorpej /* wait 2 seconds for firmware to complete initialization. */
180 1.8 thorpej
181 1.8 thorpej for (i = 200000; i--; DELAY(10))
182 1.8 thorpej if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))
183 1.8 thorpej break;
184 1.8 thorpej
185 1.8 thorpej if (i < 0) {
186 1.8 thorpej printf("%s: PCI reset timed out\n", sc->sc_dev.dv_xname);
187 1.10 onoe } else if (sc->sc_if.if_flags & IFF_DEBUG) {
188 1.8 thorpej usecs = (200000 - i) * 10;
189 1.8 thorpej secs = usecs / 1000000;
190 1.8 thorpej usecs %= 1000000;
191 1.8 thorpej
192 1.8 thorpej printf("%s: PCI reset in %d.%06d seconds\n",
193 1.8 thorpej sc->sc_dev.dv_xname, secs, usecs);
194 1.8 thorpej }
195 1.7 jdolecek
196 1.7 jdolecek return;
197 1.1 ichiro }
198 1.1 ichiro
199 1.1 ichiro static const struct wi_pci_product *
200 1.1 ichiro wi_pci_lookup(pa)
201 1.1 ichiro struct pci_attach_args *pa;
202 1.1 ichiro {
203 1.1 ichiro const struct wi_pci_product *wpp;
204 1.1 ichiro
205 1.3 augustss for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) {
206 1.1 ichiro if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor &&
207 1.1 ichiro PCI_PRODUCT(pa->pa_id) == wpp->wpp_product)
208 1.1 ichiro return (wpp);
209 1.1 ichiro }
210 1.1 ichiro return (NULL);
211 1.1 ichiro }
212 1.1 ichiro
213 1.1 ichiro static int
214 1.1 ichiro wi_pci_match(parent, match, aux)
215 1.1 ichiro struct device *parent;
216 1.1 ichiro struct cfdata *match;
217 1.1 ichiro void *aux;
218 1.1 ichiro {
219 1.1 ichiro struct pci_attach_args *pa = aux;
220 1.1 ichiro
221 1.1 ichiro if (wi_pci_lookup(pa) != NULL)
222 1.1 ichiro return (1);
223 1.1 ichiro return (0);
224 1.1 ichiro }
225 1.1 ichiro
226 1.1 ichiro static void
227 1.1 ichiro wi_pci_attach(parent, self, aux)
228 1.1 ichiro struct device *parent, *self;
229 1.1 ichiro void *aux;
230 1.1 ichiro {
231 1.1 ichiro struct wi_pci_softc *psc = (struct wi_pci_softc *)self;
232 1.1 ichiro struct wi_softc *sc = &psc->psc_wi;
233 1.1 ichiro struct pci_attach_args *pa = aux;
234 1.1 ichiro pci_chipset_tag_t pc = pa->pa_pc;
235 1.1 ichiro const char *intrstr;
236 1.1 ichiro const struct wi_pci_product *wpp;
237 1.1 ichiro pci_intr_handle_t ih;
238 1.21 dyoung bus_space_tag_t memt, iot, plxt;
239 1.21 dyoung bus_space_handle_t memh, ioh, plxh;
240 1.1 ichiro
241 1.26 scw psc->psc_pc = pc;
242 1.1 ichiro
243 1.5 augustss wpp = wi_pci_lookup(pa);
244 1.5 augustss #ifdef DIAGNOSTIC
245 1.5 augustss if (wpp == NULL) {
246 1.5 augustss printf("\n");
247 1.5 augustss panic("wi_pci_attach: impossible");
248 1.5 augustss }
249 1.5 augustss #endif
250 1.5 augustss
251 1.3 augustss if (wpp->wpp_plx) {
252 1.3 augustss /* Map memory and I/O registers. */
253 1.3 augustss if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
254 1.3 augustss &memt, &memh, NULL, NULL) != 0) {
255 1.3 augustss printf(": can't map mem space\n");
256 1.3 augustss return;
257 1.3 augustss }
258 1.3 augustss if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
259 1.3 augustss &iot, &ioh, NULL, NULL) != 0) {
260 1.3 augustss printf(": can't map I/O space\n");
261 1.3 augustss return;
262 1.3 augustss }
263 1.23 christos
264 1.23 christos if (wpp->wpp_plx == CHIP_PLX_OTHER) {
265 1.23 christos /* The PLX 9052 doesn't have IO at 0x14. Perhaps
266 1.23 christos other chips have, so we'll make this conditional. */
267 1.23 christos if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO,
268 1.23 christos PCI_MAPREG_TYPE_IO, 0, &plxt,
269 1.23 christos &plxh, NULL, NULL) != 0) {
270 1.23 christos printf(": can't map PLX\n");
271 1.23 christos return;
272 1.23 christos }
273 1.21 dyoung }
274 1.3 augustss } else {
275 1.3 augustss if (pci_mapreg_map(pa, WI_PCI_CBMA,
276 1.3 augustss PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
277 1.3 augustss 0, &iot, &ioh, NULL, NULL) != 0) {
278 1.3 augustss printf(": can't map mem space\n");
279 1.3 augustss return;
280 1.3 augustss }
281 1.3 augustss
282 1.3 augustss memt = iot;
283 1.3 augustss memh = ioh;
284 1.3 augustss sc->sc_pci = 1;
285 1.1 ichiro }
286 1.1 ichiro
287 1.3 augustss if (wpp->wpp_name != NULL) {
288 1.3 augustss printf(": %s Wireless Lan\n", wpp->wpp_name);
289 1.3 augustss } else {
290 1.3 augustss char devinfo[256];
291 1.3 augustss
292 1.3 augustss pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
293 1.3 augustss printf(": %s (rev. 0x%02x)\n", devinfo,
294 1.3 augustss PCI_REVISION(pa->pa_class));
295 1.3 augustss }
296 1.1 ichiro
297 1.1 ichiro sc->sc_enabled = 1;
298 1.1 ichiro sc->sc_enable = wi_pci_enable;
299 1.1 ichiro sc->sc_disable = wi_pci_disable;
300 1.1 ichiro
301 1.3 augustss sc->sc_iot = iot;
302 1.3 augustss sc->sc_ioh = ioh;
303 1.3 augustss /* Make sure interrupts are disabled. */
304 1.3 augustss CSR_WRITE_2(sc, WI_INT_EN, 0);
305 1.3 augustss CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
306 1.21 dyoung
307 1.23 christos if (wpp->wpp_plx == CHIP_PLX_OTHER) {
308 1.21 dyoung uint32_t command;
309 1.21 dyoung #define WI_LOCAL_INTCSR 0x4c
310 1.21 dyoung #define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */
311 1.21 dyoung
312 1.21 dyoung command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR);
313 1.21 dyoung command |= WI_LOCAL_INTEN;
314 1.21 dyoung bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command);
315 1.21 dyoung }
316 1.1 ichiro
317 1.1 ichiro /* Map and establish the interrupt. */
318 1.1 ichiro if (pci_intr_map(pa, &ih)) {
319 1.1 ichiro printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
320 1.1 ichiro return;
321 1.1 ichiro }
322 1.1 ichiro intrstr = pci_intr_string(pc, ih);
323 1.1 ichiro
324 1.1 ichiro psc->psc_ih = ih;
325 1.1 ichiro sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc);
326 1.1 ichiro if (sc->sc_ih == NULL) {
327 1.1 ichiro printf("%s: couldn't establish interrupt",
328 1.1 ichiro sc->sc_dev.dv_xname);
329 1.1 ichiro if (intrstr != NULL)
330 1.1 ichiro printf(" at %s", intrstr);
331 1.1 ichiro printf("\n");
332 1.1 ichiro return;
333 1.1 ichiro }
334 1.1 ichiro
335 1.1 ichiro printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
336 1.1 ichiro
337 1.3 augustss if (wpp->wpp_plx) {
338 1.3 augustss /*
339 1.3 augustss * Setup the PLX chip for level interrupts and config index 1
340 1.3 augustss * XXX - should really reset the PLX chip too.
341 1.3 augustss */
342 1.3 augustss bus_space_write_1(memt, memh,
343 1.3 augustss WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE);
344 1.3 augustss } else {
345 1.3 augustss /* reset HFA3842 MAC core */
346 1.3 augustss wi_pci_reset(sc);
347 1.3 augustss }
348 1.1 ichiro
349 1.3 augustss printf("%s:", sc->sc_dev.dv_xname);
350 1.1 ichiro if (wi_attach(sc) != 0) {
351 1.6 jdolecek printf("%s: failed to attach controller\n",
352 1.6 jdolecek sc->sc_dev.dv_xname);
353 1.1 ichiro pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
354 1.1 ichiro return;
355 1.1 ichiro }
356 1.17 dyoung
357 1.17 dyoung sc->sc_reset = wi_pci_reset;
358 1.1 ichiro
359 1.1 ichiro /* Add a suspend hook to restore PCI config state */
360 1.1 ichiro psc->sc_powerhook = powerhook_establish(wi_pci_powerhook, psc);
361 1.1 ichiro if (psc->sc_powerhook == NULL)
362 1.1 ichiro printf ("%s: WARNING: unable to establish pci power hook\n",
363 1.1 ichiro sc->sc_dev.dv_xname);
364 1.1 ichiro }
365 1.1 ichiro
366 1.1 ichiro static void
367 1.1 ichiro wi_pci_powerhook(why, arg)
368 1.1 ichiro int why;
369 1.1 ichiro void *arg;
370 1.1 ichiro {
371 1.1 ichiro struct wi_pci_softc *psc = arg;
372 1.1 ichiro struct wi_softc *sc = &psc->psc_wi;
373 1.1 ichiro
374 1.1 ichiro wi_power(sc, why);
375 1.1 ichiro }
376