if_wi_pci.c revision 1.7.4.1 1 1.7.4.1 he /* $NetBSD: if_wi_pci.c,v 1.7.4.1 2003/07/28 19:06:35 he Exp $ */
2 1.1 ichiro
3 1.1 ichiro /*-
4 1.1 ichiro * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 1.1 ichiro * All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * This code is derived from software contributed to The NetBSD Foundation
8 1.1 ichiro * by Hideaki Imaizumi <hiddy (at) sfc.wide.ad.jp>
9 1.1 ichiro * and Ichiro FUKUHARA (ichiro (at) ichiro.org).
10 1.1 ichiro *
11 1.1 ichiro * Redistribution and use in source and binary forms, with or without
12 1.1 ichiro * modification, are permitted provided that the following conditions
13 1.1 ichiro * are met:
14 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
15 1.1 ichiro * notice, this list of conditions and the following disclaimer.
16 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
18 1.1 ichiro * documentation and/or other materials provided with the distribution.
19 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
20 1.1 ichiro * must display the following acknowledgement:
21 1.1 ichiro * This product includes software developed by the NetBSD
22 1.1 ichiro * Foundation, Inc. and its contributors.
23 1.1 ichiro * 4. Neither the name of The NetBSD Foundation nor the names of its
24 1.1 ichiro * contributors may be used to endorse or promote products derived
25 1.1 ichiro * from this software without specific prior written permission.
26 1.1 ichiro *
27 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 1.1 ichiro * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 1.1 ichiro * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 1.1 ichiro * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 1.1 ichiro * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 ichiro * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 ichiro * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 ichiro * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 ichiro * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 ichiro * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 ichiro * POSSIBILITY OF SUCH DAMAGE.
38 1.1 ichiro */
39 1.1 ichiro
40 1.1 ichiro /*
41 1.1 ichiro * PCI bus front-end for the Intersil PCI WaveLan.
42 1.1 ichiro * Works with Prism2.5 Mini-PCI wavelan.
43 1.1 ichiro */
44 1.2 lukem
45 1.2 lukem #include <sys/cdefs.h>
46 1.7.4.1 he __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.7.4.1 2003/07/28 19:06:35 he Exp $");
47 1.1 ichiro
48 1.1 ichiro #include <sys/param.h>
49 1.1 ichiro #include <sys/systm.h>
50 1.1 ichiro #include <sys/mbuf.h>
51 1.1 ichiro #include <sys/syslog.h>
52 1.1 ichiro #include <sys/socket.h>
53 1.1 ichiro #include <sys/device.h>
54 1.1 ichiro #include <sys/callout.h>
55 1.1 ichiro
56 1.1 ichiro #include <net/if.h>
57 1.1 ichiro #include <net/if_ether.h>
58 1.1 ichiro #include <net/if_media.h>
59 1.1 ichiro #include <net/if_ieee80211.h>
60 1.1 ichiro
61 1.1 ichiro #include <machine/bus.h>
62 1.1 ichiro #include <machine/intr.h>
63 1.1 ichiro
64 1.1 ichiro #include <dev/pci/pcireg.h>
65 1.1 ichiro #include <dev/pci/pcivar.h>
66 1.1 ichiro #include <dev/pci/pcidevs.h>
67 1.1 ichiro
68 1.1 ichiro #include <dev/ic/wi_ieee.h>
69 1.1 ichiro #include <dev/ic/wireg.h>
70 1.1 ichiro #include <dev/ic/wivar.h>
71 1.1 ichiro
72 1.3 augustss #define WI_PCI_PLX_LOMEM 0x10 /* PLX chip membase */
73 1.3 augustss #define WI_PCI_PLX_LOIO 0x14 /* PLX chip iobase */
74 1.3 augustss #define WI_PCI_LOMEM 0x18 /* ISA membase */
75 1.3 augustss #define WI_PCI_LOIO 0x1C /* ISA iobase */
76 1.3 augustss
77 1.7.4.1 he #define CHIP_PLX_OTHER 0x01
78 1.7.4.1 he #define CHIP_PLX_9052 0x02
79 1.7.4.1 he
80 1.3 augustss #define WI_PLX_COR_OFFSET 0x3E0
81 1.3 augustss #define WI_PLX_COR_VALUE 0x41
82 1.3 augustss
83 1.1 ichiro struct wi_pci_softc {
84 1.1 ichiro struct wi_softc psc_wi; /* real "wi" softc */
85 1.1 ichiro
86 1.1 ichiro /* PCI-specific goo */
87 1.1 ichiro pci_intr_handle_t psc_ih;
88 1.1 ichiro struct pci_attach_args *psc_pa;
89 1.1 ichiro
90 1.1 ichiro void *sc_powerhook; /* power hook descriptor */
91 1.1 ichiro };
92 1.1 ichiro
93 1.1 ichiro static int wi_pci_match __P((struct device *, struct cfdata *, void *));
94 1.1 ichiro static void wi_pci_attach __P((struct device *, struct device *, void *));
95 1.1 ichiro static int wi_pci_enable __P((struct wi_softc *));
96 1.1 ichiro static void wi_pci_disable __P((struct wi_softc *));
97 1.7 jdolecek static void wi_pci_reset __P((struct wi_softc *));
98 1.1 ichiro static void wi_pci_powerhook __P((int, void *));
99 1.1 ichiro
100 1.1 ichiro static const struct wi_pci_product
101 1.1 ichiro *wi_pci_lookup __P((struct pci_attach_args *));
102 1.1 ichiro
103 1.1 ichiro struct cfattach wi_pci_ca = {
104 1.1 ichiro sizeof(struct wi_pci_softc), wi_pci_match, wi_pci_attach
105 1.1 ichiro };
106 1.1 ichiro
107 1.1 ichiro const struct wi_pci_product {
108 1.1 ichiro pci_vendor_id_t wpp_vendor; /* vendor ID */
109 1.1 ichiro pci_product_id_t wpp_product; /* product ID */
110 1.1 ichiro const char *wpp_name; /* product name */
111 1.3 augustss int wpp_plx; /* uses PLX chip */
112 1.1 ichiro } wi_pci_products[] = {
113 1.3 augustss { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P,
114 1.7.4.1 he NULL, CHIP_PLX_OTHER },
115 1.3 augustss { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02,
116 1.7.4.1 he NULL, CHIP_PLX_OTHER },
117 1.3 augustss { PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P,
118 1.7.4.1 he NULL, CHIP_PLX_OTHER },
119 1.3 augustss { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A,
120 1.7.4.1 he NULL, CHIP_PLX_OTHER },
121 1.3 augustss { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301,
122 1.7.4.1 he NULL, CHIP_PLX_OTHER },
123 1.1 ichiro { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN,
124 1.3 augustss "Intersil Prism2.5", 0 },
125 1.1 ichiro { 0, 0,
126 1.3 augustss NULL, 0},
127 1.1 ichiro };
128 1.1 ichiro
129 1.1 ichiro static int
130 1.1 ichiro wi_pci_enable(sc)
131 1.1 ichiro struct wi_softc *sc;
132 1.1 ichiro {
133 1.1 ichiro struct wi_pci_softc *psc = (struct wi_pci_softc *)sc;
134 1.1 ichiro
135 1.1 ichiro /* establish the interrupt. */
136 1.1 ichiro sc->sc_ih = pci_intr_establish(psc->psc_pa->pa_pc,
137 1.1 ichiro psc->psc_ih, IPL_NET, wi_intr, sc);
138 1.1 ichiro if (sc->sc_ih == NULL) {
139 1.1 ichiro printf("%s: couldn't establish interrupt\n",
140 1.1 ichiro sc->sc_dev.dv_xname);
141 1.1 ichiro return (EIO);
142 1.1 ichiro }
143 1.1 ichiro
144 1.1 ichiro /* reset HFA3842 MAC core */
145 1.1 ichiro wi_pci_reset(sc);
146 1.1 ichiro
147 1.1 ichiro return (0);
148 1.1 ichiro }
149 1.1 ichiro
150 1.1 ichiro static void
151 1.1 ichiro wi_pci_disable(sc)
152 1.1 ichiro struct wi_softc *sc;
153 1.1 ichiro {
154 1.1 ichiro struct wi_pci_softc *psc = (struct wi_pci_softc *)sc;
155 1.1 ichiro
156 1.1 ichiro pci_intr_disestablish(psc->psc_pa->pa_pc, sc->sc_ih);
157 1.7 jdolecek }
158 1.7 jdolecek
159 1.7 jdolecek static void
160 1.7 jdolecek wi_pci_reset(sc)
161 1.7 jdolecek struct wi_softc *sc;
162 1.7 jdolecek {
163 1.7 jdolecek bus_space_write_2(sc->sc_iot, sc->sc_ioh,
164 1.7 jdolecek WI_PCI_COR, WI_PCI_SOFT_RESET);
165 1.7 jdolecek DELAY(100*1000); /* 100 m sec */
166 1.7 jdolecek
167 1.7 jdolecek bus_space_write_2(sc->sc_iot, sc->sc_ioh, WI_PCI_COR, 0x0);
168 1.7 jdolecek DELAY(100*1000); /* 100 m sec */
169 1.7 jdolecek
170 1.7 jdolecek return;
171 1.1 ichiro }
172 1.1 ichiro
173 1.1 ichiro static const struct wi_pci_product *
174 1.1 ichiro wi_pci_lookup(pa)
175 1.1 ichiro struct pci_attach_args *pa;
176 1.1 ichiro {
177 1.1 ichiro const struct wi_pci_product *wpp;
178 1.1 ichiro
179 1.3 augustss for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) {
180 1.1 ichiro if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor &&
181 1.1 ichiro PCI_PRODUCT(pa->pa_id) == wpp->wpp_product)
182 1.1 ichiro return (wpp);
183 1.1 ichiro }
184 1.1 ichiro return (NULL);
185 1.1 ichiro }
186 1.1 ichiro
187 1.1 ichiro static int
188 1.1 ichiro wi_pci_match(parent, match, aux)
189 1.1 ichiro struct device *parent;
190 1.1 ichiro struct cfdata *match;
191 1.1 ichiro void *aux;
192 1.1 ichiro {
193 1.1 ichiro struct pci_attach_args *pa = aux;
194 1.1 ichiro
195 1.1 ichiro if (wi_pci_lookup(pa) != NULL)
196 1.1 ichiro return (1);
197 1.1 ichiro return (0);
198 1.1 ichiro }
199 1.1 ichiro
200 1.1 ichiro static void
201 1.1 ichiro wi_pci_attach(parent, self, aux)
202 1.1 ichiro struct device *parent, *self;
203 1.1 ichiro void *aux;
204 1.1 ichiro {
205 1.1 ichiro struct wi_pci_softc *psc = (struct wi_pci_softc *)self;
206 1.1 ichiro struct wi_softc *sc = &psc->psc_wi;
207 1.1 ichiro struct pci_attach_args *pa = aux;
208 1.1 ichiro pci_chipset_tag_t pc = pa->pa_pc;
209 1.1 ichiro const char *intrstr;
210 1.1 ichiro const struct wi_pci_product *wpp;
211 1.1 ichiro pci_intr_handle_t ih;
212 1.7.4.1 he bus_space_tag_t memt, iot, plxt;
213 1.7.4.1 he bus_space_handle_t memh, ioh, plxh;
214 1.1 ichiro
215 1.1 ichiro psc->psc_pa = pa;
216 1.1 ichiro
217 1.5 augustss wpp = wi_pci_lookup(pa);
218 1.5 augustss #ifdef DIAGNOSTIC
219 1.5 augustss if (wpp == NULL) {
220 1.5 augustss printf("\n");
221 1.5 augustss panic("wi_pci_attach: impossible");
222 1.5 augustss }
223 1.5 augustss #endif
224 1.5 augustss
225 1.3 augustss if (wpp->wpp_plx) {
226 1.3 augustss /* Map memory and I/O registers. */
227 1.3 augustss if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
228 1.3 augustss &memt, &memh, NULL, NULL) != 0) {
229 1.3 augustss printf(": can't map mem space\n");
230 1.3 augustss return;
231 1.3 augustss }
232 1.3 augustss if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
233 1.3 augustss &iot, &ioh, NULL, NULL) != 0) {
234 1.3 augustss printf(": can't map I/O space\n");
235 1.3 augustss return;
236 1.3 augustss }
237 1.7.4.1 he
238 1.7.4.1 he if (wpp->wpp_plx == CHIP_PLX_OTHER) {
239 1.7.4.1 he /* The PLX 9052 doesn't have IO at 0x14. Perhaps
240 1.7.4.1 he other chips have, so we'll make this conditional. */
241 1.7.4.1 he if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO,
242 1.7.4.1 he PCI_MAPREG_TYPE_IO, 0, &plxt,
243 1.7.4.1 he &plxh, NULL, NULL) != 0) {
244 1.7.4.1 he printf(": can't map PLX\n");
245 1.7.4.1 he return;
246 1.7.4.1 he }
247 1.7.4.1 he }
248 1.3 augustss } else {
249 1.3 augustss if (pci_mapreg_map(pa, WI_PCI_CBMA,
250 1.3 augustss PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
251 1.3 augustss 0, &iot, &ioh, NULL, NULL) != 0) {
252 1.3 augustss printf(": can't map mem space\n");
253 1.3 augustss return;
254 1.3 augustss }
255 1.3 augustss
256 1.3 augustss memt = iot;
257 1.3 augustss memh = ioh;
258 1.3 augustss sc->sc_pci = 1;
259 1.1 ichiro }
260 1.1 ichiro
261 1.3 augustss if (wpp->wpp_name != NULL) {
262 1.3 augustss printf(": %s Wireless Lan\n", wpp->wpp_name);
263 1.3 augustss } else {
264 1.3 augustss char devinfo[256];
265 1.3 augustss
266 1.3 augustss pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
267 1.3 augustss printf(": %s (rev. 0x%02x)\n", devinfo,
268 1.3 augustss PCI_REVISION(pa->pa_class));
269 1.3 augustss }
270 1.1 ichiro
271 1.1 ichiro sc->sc_enabled = 1;
272 1.1 ichiro sc->sc_enable = wi_pci_enable;
273 1.1 ichiro sc->sc_disable = wi_pci_disable;
274 1.1 ichiro
275 1.1 ichiro /* Enable the card. */
276 1.1 ichiro pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
277 1.1 ichiro pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
278 1.1 ichiro PCI_COMMAND_MASTER_ENABLE);
279 1.1 ichiro
280 1.3 augustss sc->sc_iot = iot;
281 1.3 augustss sc->sc_ioh = ioh;
282 1.3 augustss /* Make sure interrupts are disabled. */
283 1.3 augustss CSR_WRITE_2(sc, WI_INT_EN, 0);
284 1.3 augustss CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
285 1.7.4.1 he
286 1.7.4.1 he if (wpp->wpp_plx == CHIP_PLX_OTHER) {
287 1.7.4.1 he uint32_t command;
288 1.7.4.1 he #define WI_LOCAL_INTCSR 0x4c
289 1.7.4.1 he #define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */
290 1.7.4.1 he
291 1.7.4.1 he command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR);
292 1.7.4.1 he command |= WI_LOCAL_INTEN;
293 1.7.4.1 he bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command);
294 1.7.4.1 he }
295 1.1 ichiro
296 1.1 ichiro /* Map and establish the interrupt. */
297 1.1 ichiro if (pci_intr_map(pa, &ih)) {
298 1.1 ichiro printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
299 1.1 ichiro return;
300 1.1 ichiro }
301 1.1 ichiro intrstr = pci_intr_string(pc, ih);
302 1.1 ichiro
303 1.1 ichiro psc->psc_ih = ih;
304 1.1 ichiro sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc);
305 1.1 ichiro if (sc->sc_ih == NULL) {
306 1.1 ichiro printf("%s: couldn't establish interrupt",
307 1.1 ichiro sc->sc_dev.dv_xname);
308 1.1 ichiro if (intrstr != NULL)
309 1.1 ichiro printf(" at %s", intrstr);
310 1.1 ichiro printf("\n");
311 1.1 ichiro return;
312 1.1 ichiro }
313 1.1 ichiro
314 1.1 ichiro printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
315 1.1 ichiro
316 1.3 augustss if (wpp->wpp_plx) {
317 1.3 augustss /*
318 1.3 augustss * Setup the PLX chip for level interrupts and config index 1
319 1.3 augustss * XXX - should really reset the PLX chip too.
320 1.3 augustss */
321 1.3 augustss bus_space_write_1(memt, memh,
322 1.3 augustss WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE);
323 1.3 augustss } else {
324 1.3 augustss /* reset HFA3842 MAC core */
325 1.3 augustss wi_pci_reset(sc);
326 1.3 augustss }
327 1.1 ichiro
328 1.3 augustss printf("%s:", sc->sc_dev.dv_xname);
329 1.1 ichiro sc->sc_ifp = &sc->sc_ethercom.ec_if;
330 1.1 ichiro if (wi_attach(sc) != 0) {
331 1.6 jdolecek printf("%s: failed to attach controller\n",
332 1.6 jdolecek sc->sc_dev.dv_xname);
333 1.1 ichiro pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
334 1.1 ichiro return;
335 1.1 ichiro }
336 1.1 ichiro
337 1.1 ichiro /* Add a suspend hook to restore PCI config state */
338 1.1 ichiro psc->sc_powerhook = powerhook_establish(wi_pci_powerhook, psc);
339 1.1 ichiro if (psc->sc_powerhook == NULL)
340 1.1 ichiro printf ("%s: WARNING: unable to establish pci power hook\n",
341 1.1 ichiro sc->sc_dev.dv_xname);
342 1.1 ichiro }
343 1.1 ichiro
344 1.1 ichiro static void
345 1.1 ichiro wi_pci_powerhook(why, arg)
346 1.1 ichiro int why;
347 1.1 ichiro void *arg;
348 1.1 ichiro {
349 1.1 ichiro struct wi_pci_softc *psc = arg;
350 1.1 ichiro struct wi_softc *sc = &psc->psc_wi;
351 1.1 ichiro
352 1.1 ichiro wi_power(sc, why);
353 1.1 ichiro }
354