if_wi_pci.c revision 1.33
1 /* $NetBSD: if_wi_pci.c,v 1.33 2004/07/17 20:05:39 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Hideaki Imaizumi <hiddy (at) sfc.wide.ad.jp> 9 * and Ichiro FUKUHARA (ichiro (at) ichiro.org). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intersil PCI WaveLan. 42 * Works with Prism2.5 Mini-PCI wavelan. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.33 2004/07/17 20:05:39 mycroft Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/syslog.h> 52 #include <sys/socket.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 56 #include <net/if.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 60 #include <net80211/ieee80211_var.h> 61 #include <net80211/ieee80211_compat.h> 62 #include <net80211/ieee80211_radiotap.h> 63 #include <net80211/ieee80211_rssadapt.h> 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/ic/wi_ieee.h> 73 #include <dev/ic/wireg.h> 74 #include <dev/ic/wivar.h> 75 76 #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */ 77 #define WI_PCI_PLX_LOMEM 0x10 /* PLX chip membase */ 78 #define WI_PCI_PLX_LOIO 0x14 /* PLX chip iobase */ 79 #define WI_PCI_LOMEM 0x18 /* ISA membase */ 80 #define WI_PCI_LOIO 0x1C /* ISA iobase */ 81 82 #define CHIP_PLX_OTHER 0x01 83 #define CHIP_PLX_9052 0x02 84 #define CHIP_TMD_7160 0x03 85 86 #define WI_PLX_COR_OFFSET 0x3E0 87 #define WI_PLX_COR_VALUE 0x41 88 89 struct wi_pci_softc { 90 struct wi_softc psc_wi; /* real "wi" softc */ 91 92 /* PCI-specific goo */ 93 pci_intr_handle_t psc_ih; 94 pci_chipset_tag_t psc_pc; 95 96 void *sc_powerhook; /* power hook descriptor */ 97 }; 98 99 static int wi_pci_match __P((struct device *, struct cfdata *, void *)); 100 static void wi_pci_attach __P((struct device *, struct device *, void *)); 101 static int wi_pci_enable __P((struct wi_softc *)); 102 static void wi_pci_disable __P((struct wi_softc *)); 103 static void wi_pci_reset __P((struct wi_softc *)); 104 static void wi_pci_powerhook __P((int, void *)); 105 106 static const struct wi_pci_product 107 *wi_pci_lookup __P((struct pci_attach_args *)); 108 109 CFATTACH_DECL(wi_pci, sizeof(struct wi_pci_softc), 110 wi_pci_match, wi_pci_attach, NULL, NULL); 111 112 const struct wi_pci_product { 113 pci_vendor_id_t wpp_vendor; /* vendor ID */ 114 pci_product_id_t wpp_product; /* product ID */ 115 int wpp_chip; /* uses other chip */ 116 } wi_pci_products[] = { 117 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P, 118 CHIP_PLX_OTHER }, 119 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02, 120 CHIP_PLX_OTHER }, 121 { PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P, 122 CHIP_PLX_OTHER }, 123 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A, 124 CHIP_PLX_OTHER }, 125 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301, 126 CHIP_PLX_OTHER }, 127 { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN, 128 0 }, 129 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130, 130 CHIP_PLX_9052 }, 131 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_2415, 132 CHIP_PLX_OTHER }, 133 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130A2, 134 CHIP_TMD_7160 }, 135 { 0, 0, 136 0}, 137 }; 138 139 static int 140 wi_pci_enable(sc) 141 struct wi_softc *sc; 142 { 143 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 144 145 /* establish the interrupt. */ 146 sc->sc_ih = pci_intr_establish(psc->psc_pc, 147 psc->psc_ih, IPL_NET, wi_intr, sc); 148 if (sc->sc_ih == NULL) { 149 printf("%s: couldn't establish interrupt\n", 150 sc->sc_dev.dv_xname); 151 return (EIO); 152 } 153 154 /* reset HFA3842 MAC core */ 155 if (sc->sc_reset != NULL) 156 wi_pci_reset(sc); 157 158 return (0); 159 } 160 161 static void 162 wi_pci_disable(sc) 163 struct wi_softc *sc; 164 { 165 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 166 167 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 168 } 169 170 static void 171 wi_pci_reset(sc) 172 struct wi_softc *sc; 173 { 174 int i, secs, usecs; 175 176 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 177 WI_PCI_COR, WI_COR_SOFT_RESET); 178 DELAY(250*1000); /* 1/4 second */ 179 180 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 181 WI_PCI_COR, WI_COR_CLEAR); 182 DELAY(500*1000); /* 1/2 second */ 183 184 /* wait 2 seconds for firmware to complete initialization. */ 185 186 for (i = 200000; i--; DELAY(10)) 187 if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) 188 break; 189 190 if (i < 0) { 191 printf("%s: PCI reset timed out\n", sc->sc_dev.dv_xname); 192 } else if (sc->sc_if.if_flags & IFF_DEBUG) { 193 usecs = (200000 - i) * 10; 194 secs = usecs / 1000000; 195 usecs %= 1000000; 196 197 printf("%s: PCI reset in %d.%06d seconds\n", 198 sc->sc_dev.dv_xname, secs, usecs); 199 } 200 201 return; 202 } 203 204 static const struct wi_pci_product * 205 wi_pci_lookup(pa) 206 struct pci_attach_args *pa; 207 { 208 const struct wi_pci_product *wpp; 209 210 for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) { 211 if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor && 212 PCI_PRODUCT(pa->pa_id) == wpp->wpp_product) 213 return (wpp); 214 } 215 return (NULL); 216 } 217 218 static int 219 wi_pci_match(parent, match, aux) 220 struct device *parent; 221 struct cfdata *match; 222 void *aux; 223 { 224 struct pci_attach_args *pa = aux; 225 226 if (wi_pci_lookup(pa) != NULL) 227 return (1); 228 return (0); 229 } 230 231 static void 232 wi_pci_attach(parent, self, aux) 233 struct device *parent, *self; 234 void *aux; 235 { 236 struct wi_pci_softc *psc = (struct wi_pci_softc *)self; 237 struct wi_softc *sc = &psc->psc_wi; 238 struct pci_attach_args *pa = aux; 239 pci_chipset_tag_t pc = pa->pa_pc; 240 const char *intrstr; 241 const struct wi_pci_product *wpp; 242 pci_intr_handle_t ih; 243 bus_space_tag_t memt, iot, plxt, tmdt; 244 bus_space_handle_t memh, ioh, plxh, tmdh; 245 246 psc->psc_pc = pc; 247 248 wpp = wi_pci_lookup(pa); 249 #ifdef DIAGNOSTIC 250 if (wpp == NULL) { 251 printf("\n"); 252 panic("wi_pci_attach: impossible"); 253 } 254 #endif 255 256 switch (wpp->wpp_chip) { 257 case CHIP_PLX_OTHER: 258 case CHIP_PLX_9052: 259 /* Map memory and I/O registers. */ 260 if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 261 &memt, &memh, NULL, NULL) != 0) { 262 printf(": can't map mem space\n"); 263 return; 264 } 265 if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 266 &iot, &ioh, NULL, NULL) != 0) { 267 printf(": can't map I/O space\n"); 268 return; 269 } 270 271 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 272 /* The PLX 9052 doesn't have IO at 0x14. Perhaps 273 other chips have, so we'll make this conditional. */ 274 if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO, 275 PCI_MAPREG_TYPE_IO, 0, &plxt, 276 &plxh, NULL, NULL) != 0) { 277 printf(": can't map PLX\n"); 278 return; 279 } 280 } 281 break; 282 case CHIP_TMD_7160: 283 /* Used instead of PLX on at least one revision of 284 * the National Datacomm Corporation NCP130. Values 285 * for registers acquired from OpenBSD, which in 286 * turn got them from a Linux driver. 287 */ 288 /* Map COR and I/O registers. */ 289 if (pci_mapreg_map(pa, WI_TMD_COR, PCI_MAPREG_TYPE_IO, 0, 290 &tmdt, &tmdh, NULL, NULL) != 0) { 291 printf(": can't map TMD\n"); 292 return; 293 } 294 if (pci_mapreg_map(pa, WI_TMD_IO, PCI_MAPREG_TYPE_IO, 0, 295 &iot, &ioh, NULL, NULL) != 0) { 296 printf(": can't map I/O space\n"); 297 return; 298 } 299 break; 300 default: 301 if (pci_mapreg_map(pa, WI_PCI_CBMA, 302 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 303 0, &iot, &ioh, NULL, NULL) != 0) { 304 printf(": can't map mem space\n"); 305 return; 306 } 307 308 memt = iot; 309 memh = ioh; 310 sc->sc_pci = 1; 311 break; 312 } 313 314 { 315 char devinfo[256]; 316 317 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 318 printf(": %s (rev. 0x%02x)\n", devinfo, 319 PCI_REVISION(pa->pa_class)); 320 } 321 322 sc->sc_enabled = 1; 323 sc->sc_enable = wi_pci_enable; 324 sc->sc_disable = wi_pci_disable; 325 326 sc->sc_iot = iot; 327 sc->sc_ioh = ioh; 328 /* Make sure interrupts are disabled. */ 329 CSR_WRITE_2(sc, WI_INT_EN, 0); 330 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); 331 332 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 333 uint32_t command; 334 #define WI_LOCAL_INTCSR 0x4c 335 #define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */ 336 337 command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR); 338 command |= WI_LOCAL_INTEN; 339 bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command); 340 } 341 342 /* Map and establish the interrupt. */ 343 if (pci_intr_map(pa, &ih)) { 344 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 345 return; 346 } 347 intrstr = pci_intr_string(pc, ih); 348 349 psc->psc_ih = ih; 350 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc); 351 if (sc->sc_ih == NULL) { 352 printf("%s: couldn't establish interrupt", 353 sc->sc_dev.dv_xname); 354 if (intrstr != NULL) 355 printf(" at %s", intrstr); 356 printf("\n"); 357 return; 358 } 359 360 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 361 362 switch (wpp->wpp_chip) { 363 case CHIP_PLX_OTHER: 364 case CHIP_PLX_9052: 365 /* 366 * Setup the PLX chip for level interrupts and config index 1 367 * XXX - should really reset the PLX chip too. 368 */ 369 bus_space_write_1(memt, memh, 370 WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE); 371 break; 372 case CHIP_TMD_7160: 373 /* Enable I/O mode and level interrupts on the embedded 374 * card. The card's COR is the first byte of BAR 0. 375 */ 376 bus_space_write_1(tmdt, tmdh, 0, WI_COR_IOMODE); 377 break; 378 default: 379 /* reset HFA3842 MAC core */ 380 wi_pci_reset(sc); 381 break; 382 } 383 384 printf("%s:", sc->sc_dev.dv_xname); 385 if (wi_attach(sc) != 0) { 386 printf("%s: failed to attach controller\n", 387 sc->sc_dev.dv_xname); 388 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 389 return; 390 } 391 392 if (!wpp->wpp_chip) 393 sc->sc_reset = wi_pci_reset; 394 395 /* Add a suspend hook to restore PCI config state */ 396 psc->sc_powerhook = powerhook_establish(wi_pci_powerhook, psc); 397 if (psc->sc_powerhook == NULL) 398 printf ("%s: WARNING: unable to establish pci power hook\n", 399 sc->sc_dev.dv_xname); 400 } 401 402 static void 403 wi_pci_powerhook(why, arg) 404 int why; 405 void *arg; 406 { 407 struct wi_pci_softc *psc = arg; 408 struct wi_softc *sc = &psc->psc_wi; 409 410 wi_power(sc, why); 411 } 412
Indexes created Sat Sep 20 22:09:52 GMT 2025