if_wi_pci.c revision 1.41.22.1
1 /* $NetBSD: if_wi_pci.c,v 1.41.22.1 2007/09/04 15:05:48 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Hideaki Imaizumi <hiddy (at) sfc.wide.ad.jp> 9 * and Ichiro FUKUHARA (ichiro (at) ichiro.org). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intersil PCI WaveLan. 42 * Works with Prism2.5 Mini-PCI wavelan. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.41.22.1 2007/09/04 15:05:48 joerg Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/syslog.h> 52 #include <sys/socket.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 56 #include <net/if.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 60 #include <net80211/ieee80211_netbsd.h> 61 #include <net80211/ieee80211_var.h> 62 #include <net80211/ieee80211_radiotap.h> 63 #include <net80211/ieee80211_rssadapt.h> 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/ic/wi_ieee.h> 73 #include <dev/ic/wireg.h> 74 #include <dev/ic/wivar.h> 75 76 #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */ 77 #define WI_PCI_PLX_LOMEM 0x10 /* PLX chip membase */ 78 #define WI_PCI_PLX_LOIO 0x14 /* PLX chip iobase */ 79 #define WI_PCI_LOMEM 0x18 /* ISA membase */ 80 #define WI_PCI_LOIO 0x1C /* ISA iobase */ 81 82 #define CHIP_PLX_OTHER 0x01 83 #define CHIP_PLX_9052 0x02 84 #define CHIP_TMD_7160 0x03 85 86 #define WI_PLX_COR_OFFSET 0x3E0 87 #define WI_PLX_COR_VALUE 0x41 88 89 struct wi_pci_softc { 90 struct wi_softc psc_wi; /* real "wi" softc */ 91 92 /* PCI-specific goo */ 93 pci_intr_handle_t psc_ih; 94 pci_chipset_tag_t psc_pc; 95 pcitag_t psc_pcitag; 96 97 struct pci_conf_state psc_pciconf; 98 }; 99 100 static int wi_pci_match(struct device *, struct cfdata *, void *); 101 static void wi_pci_attach(struct device *, struct device *, void *); 102 static int wi_pci_enable(struct wi_softc *); 103 static void wi_pci_disable(struct wi_softc *); 104 static void wi_pci_reset(struct wi_softc *); 105 static pnp_status_t 106 wi_pci_power(device_t, pnp_request_t, void *); 107 108 static const struct wi_pci_product 109 *wi_pci_lookup(struct pci_attach_args *); 110 111 CFATTACH_DECL(wi_pci, sizeof(struct wi_pci_softc), 112 wi_pci_match, wi_pci_attach, NULL, NULL); 113 114 static const struct wi_pci_product { 115 pci_vendor_id_t wpp_vendor; /* vendor ID */ 116 pci_product_id_t wpp_product; /* product ID */ 117 int wpp_chip; /* uses other chip */ 118 } wi_pci_products[] = { 119 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P, 120 CHIP_PLX_OTHER }, 121 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02, 122 CHIP_PLX_OTHER }, 123 { PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P, 124 CHIP_PLX_OTHER }, 125 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A, 126 CHIP_PLX_OTHER }, 127 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301, 128 CHIP_PLX_OTHER }, 129 { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN, 130 0 }, 131 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130, 132 CHIP_PLX_9052 }, 133 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_2415, 134 CHIP_PLX_OTHER }, 135 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130A2, 136 CHIP_TMD_7160 }, 137 { 0, 0, 138 0}, 139 }; 140 141 static int 142 wi_pci_enable(struct wi_softc *sc) 143 { 144 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 145 146 /* establish the interrupt. */ 147 sc->sc_ih = pci_intr_establish(psc->psc_pc, 148 psc->psc_ih, IPL_NET, wi_intr, sc); 149 if (sc->sc_ih == NULL) { 150 printf("%s: couldn't establish interrupt\n", 151 sc->sc_dev.dv_xname); 152 return (EIO); 153 } 154 155 /* reset HFA3842 MAC core */ 156 if (sc->sc_reset != NULL) 157 wi_pci_reset(sc); 158 159 return (0); 160 } 161 162 static void 163 wi_pci_disable(struct wi_softc *sc) 164 { 165 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 166 167 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 168 } 169 170 static void 171 wi_pci_reset(struct wi_softc *sc) 172 { 173 int i, secs, usecs; 174 175 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 176 WI_PCI_COR, WI_COR_SOFT_RESET); 177 DELAY(250*1000); /* 1/4 second */ 178 179 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 180 WI_PCI_COR, WI_COR_CLEAR); 181 DELAY(500*1000); /* 1/2 second */ 182 183 /* wait 2 seconds for firmware to complete initialization. */ 184 185 for (i = 200000; i--; DELAY(10)) 186 if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) 187 break; 188 189 if (i < 0) { 190 printf("%s: PCI reset timed out\n", sc->sc_dev.dv_xname); 191 } else if (sc->sc_if.if_flags & IFF_DEBUG) { 192 usecs = (200000 - i) * 10; 193 secs = usecs / 1000000; 194 usecs %= 1000000; 195 196 printf("%s: PCI reset in %d.%06d seconds\n", 197 sc->sc_dev.dv_xname, secs, usecs); 198 } 199 200 return; 201 } 202 203 static const struct wi_pci_product * 204 wi_pci_lookup(struct pci_attach_args *pa) 205 { 206 const struct wi_pci_product *wpp; 207 208 for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) { 209 if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor && 210 PCI_PRODUCT(pa->pa_id) == wpp->wpp_product) 211 return (wpp); 212 } 213 return (NULL); 214 } 215 216 static int 217 wi_pci_match(struct device *parent, struct cfdata *match, 218 void *aux) 219 { 220 struct pci_attach_args *pa = aux; 221 222 if (wi_pci_lookup(pa) != NULL) 223 return (1); 224 return (0); 225 } 226 227 static void 228 wi_pci_attach(struct device *parent, struct device *self, void *aux) 229 { 230 struct wi_pci_softc *psc = (struct wi_pci_softc *)self; 231 struct wi_softc *sc = &psc->psc_wi; 232 struct pci_attach_args *pa = aux; 233 pci_chipset_tag_t pc = pa->pa_pc; 234 const char *intrstr; 235 const struct wi_pci_product *wpp; 236 pci_intr_handle_t ih; 237 bus_space_tag_t memt, iot, plxt, tmdt; 238 bus_space_handle_t memh, ioh, plxh, tmdh; 239 240 psc->psc_pc = pc; 241 psc->psc_pcitag = pa->pa_tag; 242 243 wpp = wi_pci_lookup(pa); 244 #ifdef DIAGNOSTIC 245 if (wpp == NULL) { 246 printf("\n"); 247 panic("wi_pci_attach: impossible"); 248 } 249 #endif 250 251 switch (wpp->wpp_chip) { 252 case CHIP_PLX_OTHER: 253 case CHIP_PLX_9052: 254 /* Map memory and I/O registers. */ 255 if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 256 &memt, &memh, NULL, NULL) != 0) { 257 printf(": can't map mem space\n"); 258 return; 259 } 260 if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 261 &iot, &ioh, NULL, NULL) != 0) { 262 printf(": can't map I/O space\n"); 263 return; 264 } 265 266 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 267 /* The PLX 9052 doesn't have IO at 0x14. Perhaps 268 other chips have, so we'll make this conditional. */ 269 if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO, 270 PCI_MAPREG_TYPE_IO, 0, &plxt, 271 &plxh, NULL, NULL) != 0) { 272 printf(": can't map PLX\n"); 273 return; 274 } 275 } 276 break; 277 case CHIP_TMD_7160: 278 /* Used instead of PLX on at least one revision of 279 * the National Datacomm Corporation NCP130. Values 280 * for registers acquired from OpenBSD, which in 281 * turn got them from a Linux driver. 282 */ 283 /* Map COR and I/O registers. */ 284 if (pci_mapreg_map(pa, WI_TMD_COR, PCI_MAPREG_TYPE_IO, 0, 285 &tmdt, &tmdh, NULL, NULL) != 0) { 286 printf(": can't map TMD\n"); 287 return; 288 } 289 if (pci_mapreg_map(pa, WI_TMD_IO, PCI_MAPREG_TYPE_IO, 0, 290 &iot, &ioh, NULL, NULL) != 0) { 291 printf(": can't map I/O space\n"); 292 return; 293 } 294 break; 295 default: 296 if (pci_mapreg_map(pa, WI_PCI_CBMA, 297 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 298 0, &iot, &ioh, NULL, NULL) != 0) { 299 printf(": can't map mem space\n"); 300 return; 301 } 302 303 memt = iot; 304 memh = ioh; 305 sc->sc_pci = 1; 306 break; 307 } 308 309 { 310 char devinfo[256]; 311 312 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 313 printf(": %s (rev. 0x%02x)\n", devinfo, 314 PCI_REVISION(pa->pa_class)); 315 } 316 317 sc->sc_enabled = 1; 318 sc->sc_enable = wi_pci_enable; 319 sc->sc_disable = wi_pci_disable; 320 321 sc->sc_iot = iot; 322 sc->sc_ioh = ioh; 323 /* Make sure interrupts are disabled. */ 324 CSR_WRITE_2(sc, WI_INT_EN, 0); 325 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); 326 327 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 328 uint32_t command; 329 #define WI_LOCAL_INTCSR 0x4c 330 #define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */ 331 332 command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR); 333 command |= WI_LOCAL_INTEN; 334 bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command); 335 } 336 337 /* Map and establish the interrupt. */ 338 if (pci_intr_map(pa, &ih)) { 339 printf("%s: couldn't map interrupt\n", self->dv_xname); 340 return; 341 } 342 intrstr = pci_intr_string(pc, ih); 343 344 psc->psc_ih = ih; 345 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc); 346 if (sc->sc_ih == NULL) { 347 printf("%s: couldn't establish interrupt", self->dv_xname); 348 if (intrstr != NULL) 349 printf(" at %s", intrstr); 350 printf("\n"); 351 return; 352 } 353 354 printf("%s: interrupting at %s\n", self->dv_xname, intrstr); 355 356 switch (wpp->wpp_chip) { 357 case CHIP_PLX_OTHER: 358 case CHIP_PLX_9052: 359 /* 360 * Setup the PLX chip for level interrupts and config index 1 361 * XXX - should really reset the PLX chip too. 362 */ 363 bus_space_write_1(memt, memh, 364 WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE); 365 break; 366 case CHIP_TMD_7160: 367 /* Enable I/O mode and level interrupts on the embedded 368 * card. The card's COR is the first byte of BAR 0. 369 */ 370 bus_space_write_1(tmdt, tmdh, 0, WI_COR_IOMODE); 371 break; 372 default: 373 /* reset HFA3842 MAC core */ 374 wi_pci_reset(sc); 375 break; 376 } 377 378 printf("%s:", self->dv_xname); 379 380 if (wi_attach(sc, 0) != 0) { 381 printf("%s: failed to attach controller\n", self->dv_xname); 382 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 383 return; 384 } 385 386 if (!wpp->wpp_chip) 387 sc->sc_reset = wi_pci_reset; 388 389 if (pnp_register(self, wi_pci_power) != PNP_STATUS_SUCCESS) 390 aprint_error("%s: couldn't establish power handler\n", 391 device_xname(self)); 392 } 393 394 static pnp_status_t 395 wi_pci_power(device_t dv, pnp_request_t req, void *opaque) 396 { 397 struct wi_pci_softc *psc = (struct wi_pci_softc *)dv; 398 399 return pci_net_generic_power(dv, req, opaque, psc->psc_pc, psc->psc_pcitag, 400 &psc->psc_pciconf, &psc->psc_wi.sc_if); 401 } 402
Indexes created Wed Oct 01 18:09:54 GMT 2025