if_wi_pci.c revision 1.48
1 /* $NetBSD: if_wi_pci.c,v 1.48 2009/05/12 08:23:01 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Hideaki Imaizumi <hiddy (at) sfc.wide.ad.jp> 9 * and Ichiro FUKUHARA (ichiro (at) ichiro.org). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus front-end for the Intersil PCI WaveLan. 35 * Works with Prism2.5 Mini-PCI wavelan. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.48 2009/05/12 08:23:01 cegger Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/mbuf.h> 44 #include <sys/syslog.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 49 #include <net/if.h> 50 #include <net/if_ether.h> 51 #include <net/if_media.h> 52 53 #include <net80211/ieee80211_netbsd.h> 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_radiotap.h> 56 #include <net80211/ieee80211_rssadapt.h> 57 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/ic/wi_ieee.h> 66 #include <dev/ic/wireg.h> 67 #include <dev/ic/wivar.h> 68 69 #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */ 70 #define WI_PCI_PLX_LOMEM 0x10 /* PLX chip membase */ 71 #define WI_PCI_PLX_LOIO 0x14 /* PLX chip iobase */ 72 #define WI_PCI_LOMEM 0x18 /* ISA membase */ 73 #define WI_PCI_LOIO 0x1C /* ISA iobase */ 74 75 #define CHIP_PLX_OTHER 0x01 76 #define CHIP_PLX_9052 0x02 77 #define CHIP_TMD_7160 0x03 78 79 #define WI_PLX_COR_OFFSET 0x3E0 80 #define WI_PLX_COR_VALUE 0x41 81 82 struct wi_pci_softc { 83 struct wi_softc psc_wi; /* real "wi" softc */ 84 85 /* PCI-specific goo */ 86 pci_intr_handle_t psc_ih; 87 pci_chipset_tag_t psc_pc; 88 pcitag_t psc_pcitag; 89 }; 90 91 static int wi_pci_match(device_t, cfdata_t, void *); 92 static void wi_pci_attach(device_t, device_t, void *); 93 static int wi_pci_enable(struct wi_softc *); 94 static void wi_pci_disable(struct wi_softc *); 95 static void wi_pci_reset(struct wi_softc *); 96 97 static const struct wi_pci_product 98 *wi_pci_lookup(struct pci_attach_args *); 99 100 CFATTACH_DECL(wi_pci, sizeof(struct wi_pci_softc), 101 wi_pci_match, wi_pci_attach, NULL, NULL); 102 103 static const struct wi_pci_product { 104 pci_vendor_id_t wpp_vendor; /* vendor ID */ 105 pci_product_id_t wpp_product; /* product ID */ 106 int wpp_chip; /* uses other chip */ 107 } wi_pci_products[] = { 108 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P, 109 CHIP_PLX_OTHER }, 110 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02, 111 CHIP_PLX_OTHER }, 112 { PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P, 113 CHIP_PLX_OTHER }, 114 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A, 115 CHIP_PLX_OTHER }, 116 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301, 117 CHIP_PLX_OTHER }, 118 { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN, 119 0 }, 120 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130, 121 CHIP_PLX_9052 }, 122 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_2415, 123 CHIP_PLX_OTHER }, 124 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130A2, 125 CHIP_TMD_7160 }, 126 { 0, 0, 127 0}, 128 }; 129 130 static int 131 wi_pci_enable(struct wi_softc *sc) 132 { 133 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 134 135 /* establish the interrupt. */ 136 sc->sc_ih = pci_intr_establish(psc->psc_pc, 137 psc->psc_ih, IPL_NET, wi_intr, sc); 138 if (sc->sc_ih == NULL) { 139 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt\n"); 140 return (EIO); 141 } 142 143 /* reset HFA3842 MAC core */ 144 if (sc->sc_reset != NULL) 145 wi_pci_reset(sc); 146 147 return (0); 148 } 149 150 static void 151 wi_pci_disable(struct wi_softc *sc) 152 { 153 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 154 155 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 156 } 157 158 static void 159 wi_pci_reset(struct wi_softc *sc) 160 { 161 int i, secs, usecs; 162 163 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 164 WI_PCI_COR, WI_COR_SOFT_RESET); 165 DELAY(250*1000); /* 1/4 second */ 166 167 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 168 WI_PCI_COR, WI_COR_CLEAR); 169 DELAY(500*1000); /* 1/2 second */ 170 171 /* wait 2 seconds for firmware to complete initialization. */ 172 173 for (i = 200000; i--; DELAY(10)) 174 if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) 175 break; 176 177 if (i < 0) { 178 printf("%s: PCI reset timed out\n", device_xname(&sc->sc_dev)); 179 } else if (sc->sc_if.if_flags & IFF_DEBUG) { 180 usecs = (200000 - i) * 10; 181 secs = usecs / 1000000; 182 usecs %= 1000000; 183 184 printf("%s: PCI reset in %d.%06d seconds\n", 185 device_xname(&sc->sc_dev), secs, usecs); 186 } 187 188 return; 189 } 190 191 static const struct wi_pci_product * 192 wi_pci_lookup(struct pci_attach_args *pa) 193 { 194 const struct wi_pci_product *wpp; 195 196 for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) { 197 if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor && 198 PCI_PRODUCT(pa->pa_id) == wpp->wpp_product) 199 return (wpp); 200 } 201 return (NULL); 202 } 203 204 static int 205 wi_pci_match(device_t parent, cfdata_t match, void *aux) 206 { 207 struct pci_attach_args *pa = aux; 208 209 if (wi_pci_lookup(pa) != NULL) 210 return (1); 211 return (0); 212 } 213 214 static void 215 wi_pci_attach(device_t parent, device_t self, void *aux) 216 { 217 struct wi_pci_softc *psc = device_private(self); 218 struct wi_softc *sc = &psc->psc_wi; 219 struct pci_attach_args *pa = aux; 220 pci_chipset_tag_t pc = pa->pa_pc; 221 const char *intrstr; 222 const struct wi_pci_product *wpp; 223 pci_intr_handle_t ih; 224 bus_space_tag_t memt, iot, plxt, tmdt; 225 bus_space_handle_t memh, ioh, plxh, tmdh; 226 227 psc->psc_pc = pc; 228 psc->psc_pcitag = pa->pa_tag; 229 230 wpp = wi_pci_lookup(pa); 231 #ifdef DIAGNOSTIC 232 if (wpp == NULL) { 233 printf("\n"); 234 panic("wi_pci_attach: impossible"); 235 } 236 #endif 237 238 switch (wpp->wpp_chip) { 239 case CHIP_PLX_OTHER: 240 case CHIP_PLX_9052: 241 /* Map memory and I/O registers. */ 242 if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 243 &memt, &memh, NULL, NULL) != 0) { 244 printf(": can't map mem space\n"); 245 return; 246 } 247 if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 248 &iot, &ioh, NULL, NULL) != 0) { 249 printf(": can't map I/O space\n"); 250 return; 251 } 252 253 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 254 /* The PLX 9052 doesn't have IO at 0x14. Perhaps 255 other chips have, so we'll make this conditional. */ 256 if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO, 257 PCI_MAPREG_TYPE_IO, 0, &plxt, 258 &plxh, NULL, NULL) != 0) { 259 printf(": can't map PLX\n"); 260 return; 261 } 262 } 263 break; 264 case CHIP_TMD_7160: 265 /* Used instead of PLX on at least one revision of 266 * the National Datacomm Corporation NCP130. Values 267 * for registers acquired from OpenBSD, which in 268 * turn got them from a Linux driver. 269 */ 270 /* Map COR and I/O registers. */ 271 if (pci_mapreg_map(pa, WI_TMD_COR, PCI_MAPREG_TYPE_IO, 0, 272 &tmdt, &tmdh, NULL, NULL) != 0) { 273 printf(": can't map TMD\n"); 274 return; 275 } 276 if (pci_mapreg_map(pa, WI_TMD_IO, PCI_MAPREG_TYPE_IO, 0, 277 &iot, &ioh, NULL, NULL) != 0) { 278 printf(": can't map I/O space\n"); 279 return; 280 } 281 break; 282 default: 283 if (pci_mapreg_map(pa, WI_PCI_CBMA, 284 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 285 0, &iot, &ioh, NULL, NULL) != 0) { 286 printf(": can't map mem space\n"); 287 return; 288 } 289 290 memt = iot; 291 memh = ioh; 292 sc->sc_pci = 1; 293 break; 294 } 295 296 { 297 char devinfo[256]; 298 299 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 300 printf(": %s (rev. 0x%02x)\n", devinfo, 301 PCI_REVISION(pa->pa_class)); 302 } 303 304 sc->sc_enabled = 1; 305 sc->sc_enable = wi_pci_enable; 306 sc->sc_disable = wi_pci_disable; 307 308 sc->sc_iot = iot; 309 sc->sc_ioh = ioh; 310 /* Make sure interrupts are disabled. */ 311 CSR_WRITE_2(sc, WI_INT_EN, 0); 312 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); 313 314 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 315 uint32_t command; 316 #define WI_LOCAL_INTCSR 0x4c 317 #define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */ 318 319 command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR); 320 command |= WI_LOCAL_INTEN; 321 bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command); 322 } 323 324 /* Map and establish the interrupt. */ 325 if (pci_intr_map(pa, &ih)) { 326 aprint_error_dev(self, "couldn't map interrupt\n"); 327 return; 328 } 329 intrstr = pci_intr_string(pc, ih); 330 331 psc->psc_ih = ih; 332 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc); 333 if (sc->sc_ih == NULL) { 334 aprint_error_dev(self, "couldn't establish interrupt"); 335 if (intrstr != NULL) 336 printf(" at %s", intrstr); 337 printf("\n"); 338 return; 339 } 340 341 printf("%s: interrupting at %s\n", device_xname(self), intrstr); 342 343 switch (wpp->wpp_chip) { 344 case CHIP_PLX_OTHER: 345 case CHIP_PLX_9052: 346 /* 347 * Setup the PLX chip for level interrupts and config index 1 348 * XXX - should really reset the PLX chip too. 349 */ 350 bus_space_write_1(memt, memh, 351 WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE); 352 break; 353 case CHIP_TMD_7160: 354 /* Enable I/O mode and level interrupts on the embedded 355 * card. The card's COR is the first byte of BAR 0. 356 */ 357 bus_space_write_1(tmdt, tmdh, 0, WI_COR_IOMODE); 358 break; 359 default: 360 /* reset HFA3842 MAC core */ 361 wi_pci_reset(sc); 362 break; 363 } 364 365 printf("%s:", device_xname(self)); 366 367 if (wi_attach(sc, 0) != 0) { 368 aprint_error_dev(self, "failed to attach controller\n"); 369 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 370 return; 371 } 372 373 if (!wpp->wpp_chip) 374 sc->sc_reset = wi_pci_reset; 375 376 if (!pmf_device_register(self, NULL, NULL)) 377 aprint_error_dev(self, "couldn't establish power handler\n"); 378 else 379 pmf_class_network_register(self, &sc->sc_if); 380 } 381
Indexes created Sat Sep 20 22:09:52 GMT 2025