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if_wm.c revision 1.182
      1  1.182   msaitoh /*	$NetBSD: if_wm.c,v 1.182 2009/12/16 04:50:35 msaitoh Exp $	*/
      2    1.1   thorpej 
      3    1.1   thorpej /*
      4   1.69   thorpej  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
      5    1.1   thorpej  * All rights reserved.
      6    1.1   thorpej  *
      7    1.1   thorpej  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8    1.1   thorpej  *
      9    1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     10    1.1   thorpej  * modification, are permitted provided that the following conditions
     11    1.1   thorpej  * are met:
     12    1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     13    1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     14    1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     15    1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     16    1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     17    1.1   thorpej  * 3. All advertising materials mentioning features or use of this software
     18    1.1   thorpej  *    must display the following acknowledgement:
     19    1.1   thorpej  *	This product includes software developed for the NetBSD Project by
     20    1.1   thorpej  *	Wasabi Systems, Inc.
     21    1.1   thorpej  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22    1.1   thorpej  *    or promote products derived from this software without specific prior
     23    1.1   thorpej  *    written permission.
     24    1.1   thorpej  *
     25    1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26    1.1   thorpej  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27    1.1   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28    1.1   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29    1.1   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30    1.1   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31    1.1   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32    1.1   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33    1.1   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34    1.1   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35    1.1   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     36    1.1   thorpej  */
     37    1.1   thorpej 
     38  1.139    bouyer /*******************************************************************************
     39  1.139    bouyer 
     40  1.139    bouyer   Copyright (c) 2001-2005, Intel Corporation
     41  1.139    bouyer   All rights reserved.
     42  1.139    bouyer 
     43  1.139    bouyer   Redistribution and use in source and binary forms, with or without
     44  1.139    bouyer   modification, are permitted provided that the following conditions are met:
     45  1.139    bouyer 
     46  1.139    bouyer    1. Redistributions of source code must retain the above copyright notice,
     47  1.139    bouyer       this list of conditions and the following disclaimer.
     48  1.139    bouyer 
     49  1.139    bouyer    2. Redistributions in binary form must reproduce the above copyright
     50  1.139    bouyer       notice, this list of conditions and the following disclaimer in the
     51  1.139    bouyer       documentation and/or other materials provided with the distribution.
     52  1.139    bouyer 
     53  1.139    bouyer    3. Neither the name of the Intel Corporation nor the names of its
     54  1.139    bouyer       contributors may be used to endorse or promote products derived from
     55  1.139    bouyer       this software without specific prior written permission.
     56  1.139    bouyer 
     57  1.139    bouyer   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     58  1.139    bouyer   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     59  1.139    bouyer   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     60  1.139    bouyer   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     61  1.139    bouyer   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     62  1.139    bouyer   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     63  1.139    bouyer   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     64  1.139    bouyer   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     65  1.139    bouyer   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     66  1.139    bouyer   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     67  1.139    bouyer   POSSIBILITY OF SUCH DAMAGE.
     68  1.139    bouyer 
     69  1.139    bouyer *******************************************************************************/
     70    1.1   thorpej /*
     71   1.11   thorpej  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
     72    1.1   thorpej  *
     73    1.1   thorpej  * TODO (in order of importance):
     74    1.1   thorpej  *
     75   1.61   thorpej  *	- Rework how parameters are loaded from the EEPROM.
     76    1.1   thorpej  */
     77   1.38     lukem 
     78   1.38     lukem #include <sys/cdefs.h>
     79  1.182   msaitoh __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.182 2009/12/16 04:50:35 msaitoh Exp $");
     80    1.1   thorpej 
     81    1.1   thorpej #include "bpfilter.h"
     82   1.21    itojun #include "rnd.h"
     83    1.1   thorpej 
     84    1.1   thorpej #include <sys/param.h>
     85    1.1   thorpej #include <sys/systm.h>
     86   1.96     perry #include <sys/callout.h>
     87    1.1   thorpej #include <sys/mbuf.h>
     88    1.1   thorpej #include <sys/malloc.h>
     89    1.1   thorpej #include <sys/kernel.h>
     90    1.1   thorpej #include <sys/socket.h>
     91    1.1   thorpej #include <sys/ioctl.h>
     92    1.1   thorpej #include <sys/errno.h>
     93    1.1   thorpej #include <sys/device.h>
     94    1.1   thorpej #include <sys/queue.h>
     95   1.84   thorpej #include <sys/syslog.h>
     96    1.1   thorpej 
     97    1.1   thorpej #include <uvm/uvm_extern.h>		/* for PAGE_SIZE */
     98    1.1   thorpej 
     99   1.21    itojun #if NRND > 0
    100   1.21    itojun #include <sys/rnd.h>
    101   1.21    itojun #endif
    102   1.21    itojun 
    103    1.1   thorpej #include <net/if.h>
    104   1.96     perry #include <net/if_dl.h>
    105    1.1   thorpej #include <net/if_media.h>
    106    1.1   thorpej #include <net/if_ether.h>
    107    1.1   thorpej 
    108   1.96     perry #if NBPFILTER > 0
    109    1.1   thorpej #include <net/bpf.h>
    110    1.1   thorpej #endif
    111    1.1   thorpej 
    112    1.1   thorpej #include <netinet/in.h>			/* XXX for struct ip */
    113    1.1   thorpej #include <netinet/in_systm.h>		/* XXX for struct ip */
    114    1.1   thorpej #include <netinet/ip.h>			/* XXX for struct ip */
    115  1.131      yamt #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
    116   1.13   thorpej #include <netinet/tcp.h>		/* XXX for struct tcphdr */
    117    1.1   thorpej 
    118  1.147        ad #include <sys/bus.h>
    119  1.147        ad #include <sys/intr.h>
    120    1.1   thorpej #include <machine/endian.h>
    121    1.1   thorpej 
    122    1.1   thorpej #include <dev/mii/mii.h>
    123    1.1   thorpej #include <dev/mii/miivar.h>
    124    1.1   thorpej #include <dev/mii/mii_bitbang.h>
    125  1.127    bouyer #include <dev/mii/ikphyreg.h>
    126    1.1   thorpej 
    127    1.1   thorpej #include <dev/pci/pcireg.h>
    128    1.1   thorpej #include <dev/pci/pcivar.h>
    129    1.1   thorpej #include <dev/pci/pcidevs.h>
    130    1.1   thorpej 
    131    1.1   thorpej #include <dev/pci/if_wmreg.h>
    132  1.182   msaitoh #include <dev/pci/if_wmvar.h>
    133    1.1   thorpej 
    134    1.1   thorpej #ifdef WM_DEBUG
    135    1.1   thorpej #define	WM_DEBUG_LINK		0x01
    136    1.1   thorpej #define	WM_DEBUG_TX		0x02
    137    1.1   thorpej #define	WM_DEBUG_RX		0x04
    138    1.1   thorpej #define	WM_DEBUG_GMII		0x08
    139  1.127    bouyer int	wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK|WM_DEBUG_GMII;
    140    1.1   thorpej 
    141    1.1   thorpej #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
    142    1.1   thorpej #else
    143    1.1   thorpej #define	DPRINTF(x, y)	/* nothing */
    144    1.1   thorpej #endif /* WM_DEBUG */
    145    1.1   thorpej 
    146    1.1   thorpej /*
    147    1.2   thorpej  * Transmit descriptor list size.  Due to errata, we can only have
    148   1.75   thorpej  * 256 hardware descriptors in the ring on < 82544, but we use 4096
    149   1.75   thorpej  * on >= 82544.  We tell the upper layers that they can queue a lot
    150   1.75   thorpej  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
    151   1.75   thorpej  * of them at a time.
    152   1.75   thorpej  *
    153   1.75   thorpej  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
    154   1.75   thorpej  * chains containing many small mbufs have been observed in zero-copy
    155   1.75   thorpej  * situations with jumbo frames.
    156    1.1   thorpej  */
    157   1.75   thorpej #define	WM_NTXSEGS		256
    158    1.2   thorpej #define	WM_IFQUEUELEN		256
    159   1.74      tron #define	WM_TXQUEUELEN_MAX	64
    160   1.74      tron #define	WM_TXQUEUELEN_MAX_82547	16
    161   1.74      tron #define	WM_TXQUEUELEN(sc)	((sc)->sc_txnum)
    162   1.74      tron #define	WM_TXQUEUELEN_MASK(sc)	(WM_TXQUEUELEN(sc) - 1)
    163   1.74      tron #define	WM_TXQUEUE_GC(sc)	(WM_TXQUEUELEN(sc) / 8)
    164   1.75   thorpej #define	WM_NTXDESC_82542	256
    165   1.75   thorpej #define	WM_NTXDESC_82544	4096
    166   1.75   thorpej #define	WM_NTXDESC(sc)		((sc)->sc_ntxdesc)
    167   1.75   thorpej #define	WM_NTXDESC_MASK(sc)	(WM_NTXDESC(sc) - 1)
    168   1.75   thorpej #define	WM_TXDESCSIZE(sc)	(WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t))
    169   1.75   thorpej #define	WM_NEXTTX(sc, x)	(((x) + 1) & WM_NTXDESC_MASK(sc))
    170   1.74      tron #define	WM_NEXTTXS(sc, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(sc))
    171    1.1   thorpej 
    172   1.99      matt #define	WM_MAXTXDMA		round_page(IP_MAXPACKET) /* for TSO */
    173   1.82   thorpej 
    174    1.1   thorpej /*
    175    1.1   thorpej  * Receive descriptor list size.  We have one Rx buffer for normal
    176    1.1   thorpej  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
    177   1.10   thorpej  * packet.  We allocate 256 receive descriptors, each with a 2k
    178   1.10   thorpej  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
    179    1.1   thorpej  */
    180   1.10   thorpej #define	WM_NRXDESC		256
    181    1.1   thorpej #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
    182    1.1   thorpej #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
    183    1.1   thorpej #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
    184    1.1   thorpej 
    185    1.1   thorpej /*
    186    1.1   thorpej  * Control structures are DMA'd to the i82542 chip.  We allocate them in
    187  1.105     skrll  * a single clump that maps to a single DMA segment to make several things
    188    1.1   thorpej  * easier.
    189    1.1   thorpej  */
    190   1.75   thorpej struct wm_control_data_82544 {
    191    1.1   thorpej 	/*
    192   1.75   thorpej 	 * The receive descriptors.
    193    1.1   thorpej 	 */
    194   1.75   thorpej 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
    195    1.1   thorpej 
    196    1.1   thorpej 	/*
    197   1.75   thorpej 	 * The transmit descriptors.  Put these at the end, because
    198   1.75   thorpej 	 * we might use a smaller number of them.
    199    1.1   thorpej 	 */
    200   1.75   thorpej 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544];
    201   1.75   thorpej };
    202   1.75   thorpej 
    203   1.75   thorpej struct wm_control_data_82542 {
    204    1.1   thorpej 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
    205   1.75   thorpej 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542];
    206    1.1   thorpej };
    207    1.1   thorpej 
    208   1.75   thorpej #define	WM_CDOFF(x)	offsetof(struct wm_control_data_82544, x)
    209    1.1   thorpej #define	WM_CDTXOFF(x)	WM_CDOFF(wcd_txdescs[(x)])
    210    1.1   thorpej #define	WM_CDRXOFF(x)	WM_CDOFF(wcd_rxdescs[(x)])
    211    1.1   thorpej 
    212    1.1   thorpej /*
    213    1.1   thorpej  * Software state for transmit jobs.
    214    1.1   thorpej  */
    215    1.1   thorpej struct wm_txsoft {
    216    1.1   thorpej 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
    217    1.1   thorpej 	bus_dmamap_t txs_dmamap;	/* our DMA map */
    218    1.1   thorpej 	int txs_firstdesc;		/* first descriptor in packet */
    219    1.1   thorpej 	int txs_lastdesc;		/* last descriptor in packet */
    220    1.4   thorpej 	int txs_ndesc;			/* # of descriptors used */
    221    1.1   thorpej };
    222    1.1   thorpej 
    223    1.1   thorpej /*
    224    1.1   thorpej  * Software state for receive buffers.  Each descriptor gets a
    225    1.1   thorpej  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
    226    1.1   thorpej  * more than one buffer, we chain them together.
    227    1.1   thorpej  */
    228    1.1   thorpej struct wm_rxsoft {
    229    1.1   thorpej 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
    230    1.1   thorpej 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
    231    1.1   thorpej };
    232    1.1   thorpej 
    233  1.173   msaitoh #define WM_LINKUP_TIMEOUT	50
    234  1.173   msaitoh 
    235    1.1   thorpej /*
    236    1.1   thorpej  * Software state per device.
    237    1.1   thorpej  */
    238    1.1   thorpej struct wm_softc {
    239  1.160  christos 	device_t sc_dev;		/* generic device information */
    240    1.1   thorpej 	bus_space_tag_t sc_st;		/* bus space tag */
    241    1.1   thorpej 	bus_space_handle_t sc_sh;	/* bus space handle */
    242   1.53   thorpej 	bus_space_tag_t sc_iot;		/* I/O space tag */
    243   1.53   thorpej 	bus_space_handle_t sc_ioh;	/* I/O space handle */
    244  1.139    bouyer 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
    245  1.139    bouyer 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
    246    1.1   thorpej 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
    247    1.1   thorpej 	struct ethercom sc_ethercom;	/* ethernet common data */
    248  1.123  jmcneill 	pci_chipset_tag_t sc_pc;
    249  1.123  jmcneill 	pcitag_t sc_pcitag;
    250    1.1   thorpej 
    251   1.43   thorpej 	wm_chip_type sc_type;		/* chip type */
    252    1.1   thorpej 	int sc_flags;			/* flags; see below */
    253  1.179   msaitoh 	int sc_if_flags;		/* last if_flags */
    254   1.52   thorpej 	int sc_bus_speed;		/* PCI/PCIX bus speed */
    255   1.54   thorpej 	int sc_pcix_offset;		/* PCIX capability register offset */
    256   1.71   thorpej 	int sc_flowflags;		/* 802.3x flow control flags */
    257    1.1   thorpej 
    258    1.1   thorpej 	void *sc_ih;			/* interrupt cookie */
    259    1.1   thorpej 
    260   1.44   thorpej 	int sc_ee_addrbits;		/* EEPROM address bits */
    261   1.44   thorpej 
    262    1.1   thorpej 	struct mii_data sc_mii;		/* MII/media information */
    263    1.1   thorpej 
    264  1.142        ad 	callout_t sc_tick_ch;		/* tick callout */
    265    1.1   thorpej 
    266    1.1   thorpej 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
    267    1.1   thorpej #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
    268    1.1   thorpej 
    269   1.42   thorpej 	int		sc_align_tweak;
    270   1.42   thorpej 
    271    1.1   thorpej 	/*
    272    1.1   thorpej 	 * Software state for the transmit and receive descriptors.
    273    1.1   thorpej 	 */
    274   1.74      tron 	int			sc_txnum;	/* must be a power of two */
    275   1.74      tron 	struct wm_txsoft	sc_txsoft[WM_TXQUEUELEN_MAX];
    276   1.74      tron 	struct wm_rxsoft	sc_rxsoft[WM_NRXDESC];
    277    1.1   thorpej 
    278    1.1   thorpej 	/*
    279    1.1   thorpej 	 * Control data structures.
    280    1.1   thorpej 	 */
    281   1.75   thorpej 	int			sc_ntxdesc;	/* must be a power of two */
    282   1.75   thorpej 	struct wm_control_data_82544 *sc_control_data;
    283    1.1   thorpej #define	sc_txdescs	sc_control_data->wcd_txdescs
    284    1.1   thorpej #define	sc_rxdescs	sc_control_data->wcd_rxdescs
    285    1.1   thorpej 
    286    1.1   thorpej #ifdef WM_EVENT_COUNTERS
    287    1.1   thorpej 	/* Event counters. */
    288    1.1   thorpej 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
    289    1.1   thorpej 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
    290   1.78   thorpej 	struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
    291    1.4   thorpej 	struct evcnt sc_ev_txdw;	/* Tx descriptor interrupts */
    292    1.4   thorpej 	struct evcnt sc_ev_txqe;	/* Tx queue empty interrupts */
    293    1.1   thorpej 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
    294    1.1   thorpej 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
    295    1.1   thorpej 
    296    1.1   thorpej 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
    297    1.1   thorpej 	struct evcnt sc_ev_rxtusum;	/* TCP/UDP cksums checked in-bound */
    298    1.1   thorpej 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
    299    1.1   thorpej 	struct evcnt sc_ev_txtusum;	/* TCP/UDP cksums comp. out-bound */
    300  1.107      yamt 	struct evcnt sc_ev_txtusum6;	/* TCP/UDP v6 cksums comp. out-bound */
    301  1.131      yamt 	struct evcnt sc_ev_txtso;	/* TCP seg offload out-bound (IPv4) */
    302  1.131      yamt 	struct evcnt sc_ev_txtso6;	/* TCP seg offload out-bound (IPv6) */
    303   1.99      matt 	struct evcnt sc_ev_txtsopain;	/* painful header manip. for TSO */
    304    1.1   thorpej 
    305    1.2   thorpej 	struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
    306    1.1   thorpej 	struct evcnt sc_ev_txdrop;	/* Tx packets dropped (too many segs) */
    307    1.1   thorpej 
    308    1.1   thorpej 	struct evcnt sc_ev_tu;		/* Tx underrun */
    309   1.71   thorpej 
    310   1.71   thorpej 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
    311   1.71   thorpej 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
    312   1.71   thorpej 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
    313   1.71   thorpej 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
    314   1.71   thorpej 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
    315    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
    316    1.1   thorpej 
    317    1.1   thorpej 	bus_addr_t sc_tdt_reg;		/* offset of TDT register */
    318    1.1   thorpej 
    319    1.1   thorpej 	int	sc_txfree;		/* number of free Tx descriptors */
    320    1.1   thorpej 	int	sc_txnext;		/* next ready Tx descriptor */
    321    1.1   thorpej 
    322    1.1   thorpej 	int	sc_txsfree;		/* number of free Tx jobs */
    323    1.1   thorpej 	int	sc_txsnext;		/* next free Tx job */
    324    1.1   thorpej 	int	sc_txsdirty;		/* dirty Tx jobs */
    325    1.1   thorpej 
    326   1.78   thorpej 	/* These 5 variables are used only on the 82547. */
    327   1.78   thorpej 	int	sc_txfifo_size;		/* Tx FIFO size */
    328   1.78   thorpej 	int	sc_txfifo_head;		/* current head of FIFO */
    329   1.78   thorpej 	uint32_t sc_txfifo_addr;	/* internal address of start of FIFO */
    330   1.78   thorpej 	int	sc_txfifo_stall;	/* Tx FIFO is stalled */
    331  1.142        ad 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
    332   1.78   thorpej 
    333    1.1   thorpej 	bus_addr_t sc_rdt_reg;		/* offset of RDT register */
    334    1.1   thorpej 
    335    1.1   thorpej 	int	sc_rxptr;		/* next ready Rx descriptor/queue ent */
    336    1.1   thorpej 	int	sc_rxdiscard;
    337    1.1   thorpej 	int	sc_rxlen;
    338    1.1   thorpej 	struct mbuf *sc_rxhead;
    339    1.1   thorpej 	struct mbuf *sc_rxtail;
    340    1.1   thorpej 	struct mbuf **sc_rxtailp;
    341    1.1   thorpej 
    342    1.1   thorpej 	uint32_t sc_ctrl;		/* prototype CTRL register */
    343    1.1   thorpej #if 0
    344    1.1   thorpej 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
    345    1.1   thorpej #endif
    346    1.1   thorpej 	uint32_t sc_icr;		/* prototype interrupt bits */
    347   1.92    briggs 	uint32_t sc_itr;		/* prototype intr throttling reg */
    348    1.1   thorpej 	uint32_t sc_tctl;		/* prototype TCTL register */
    349    1.1   thorpej 	uint32_t sc_rctl;		/* prototype RCTL register */
    350    1.1   thorpej 	uint32_t sc_txcw;		/* prototype TXCW register */
    351    1.1   thorpej 	uint32_t sc_tipg;		/* prototype TIPG register */
    352   1.71   thorpej 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
    353   1.78   thorpej 	uint32_t sc_pba;		/* prototype PBA register */
    354    1.1   thorpej 
    355    1.1   thorpej 	int sc_tbi_linkup;		/* TBI link status */
    356  1.173   msaitoh 	int sc_tbi_anegticks;		/* autonegotiation ticks */
    357  1.173   msaitoh 	int sc_tbi_ticks;		/* tbi ticks */
    358  1.173   msaitoh 	int sc_tbi_nrxcfg;		/* count of ICR_RXCFG */
    359  1.173   msaitoh 	int sc_tbi_lastnrxcfg;		/* count of ICR_RXCFG (on last tick) */
    360    1.1   thorpej 
    361    1.1   thorpej 	int sc_mchash_type;		/* multicast filter offset */
    362   1.21    itojun 
    363   1.21    itojun #if NRND > 0
    364   1.21    itojun 	rndsource_element_t rnd_source;	/* random source */
    365   1.21    itojun #endif
    366  1.139    bouyer 	int sc_ich8_flash_base;
    367  1.139    bouyer 	int sc_ich8_flash_bank_size;
    368    1.1   thorpej };
    369    1.1   thorpej 
    370    1.1   thorpej #define	WM_RXCHAIN_RESET(sc)						\
    371    1.1   thorpej do {									\
    372    1.1   thorpej 	(sc)->sc_rxtailp = &(sc)->sc_rxhead;				\
    373    1.1   thorpej 	*(sc)->sc_rxtailp = NULL;					\
    374    1.1   thorpej 	(sc)->sc_rxlen = 0;						\
    375    1.1   thorpej } while (/*CONSTCOND*/0)
    376    1.1   thorpej 
    377    1.1   thorpej #define	WM_RXCHAIN_LINK(sc, m)						\
    378    1.1   thorpej do {									\
    379    1.1   thorpej 	*(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);			\
    380    1.1   thorpej 	(sc)->sc_rxtailp = &(m)->m_next;				\
    381    1.1   thorpej } while (/*CONSTCOND*/0)
    382    1.1   thorpej 
    383    1.1   thorpej /* sc_flags */
    384  1.127    bouyer #define	WM_F_HAS_MII		0x0001	/* has MII */
    385  1.127    bouyer #define	WM_F_EEPROM_HANDSHAKE	0x0002	/* requires EEPROM handshake */
    386  1.127    bouyer #define	WM_F_EEPROM_SEMAPHORE	0x0004	/* EEPROM with semaphore */
    387  1.127    bouyer #define	WM_F_EEPROM_EERDEEWR	0x0008	/* EEPROM access via EERD/EEWR */
    388  1.127    bouyer #define	WM_F_EEPROM_SPI		0x0010	/* EEPROM is SPI */
    389  1.127    bouyer #define	WM_F_EEPROM_FLASH	0x0020	/* EEPROM is FLASH */
    390  1.127    bouyer #define	WM_F_EEPROM_INVALID	0x0040	/* EEPROM not present (bad checksum) */
    391  1.127    bouyer #define	WM_F_IOH_VALID		0x0080	/* I/O handle is valid */
    392  1.127    bouyer #define	WM_F_BUS64		0x0100	/* bus is 64-bit */
    393  1.127    bouyer #define	WM_F_PCIX		0x0200	/* bus is PCI-X */
    394  1.127    bouyer #define	WM_F_CSA		0x0400	/* bus is CSA */
    395  1.127    bouyer #define	WM_F_PCIE		0x0800	/* bus is PCI-Express */
    396  1.127    bouyer #define WM_F_SWFW_SYNC		0x1000  /* Software-Firmware synchronisation */
    397  1.139    bouyer #define WM_F_SWFWHW_SYNC	0x2000  /* Software-Firmware synchronisation */
    398    1.1   thorpej 
    399    1.1   thorpej #ifdef WM_EVENT_COUNTERS
    400    1.1   thorpej #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
    401   1.71   thorpej #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
    402    1.1   thorpej #else
    403    1.1   thorpej #define	WM_EVCNT_INCR(ev)	/* nothing */
    404   1.71   thorpej #define	WM_EVCNT_ADD(ev, val)	/* nothing */
    405    1.1   thorpej #endif
    406    1.1   thorpej 
    407    1.1   thorpej #define	CSR_READ(sc, reg)						\
    408    1.1   thorpej 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
    409    1.1   thorpej #define	CSR_WRITE(sc, reg, val)						\
    410    1.1   thorpej 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
    411   1.78   thorpej #define	CSR_WRITE_FLUSH(sc)						\
    412   1.78   thorpej 	(void) CSR_READ((sc), WMREG_STATUS)
    413    1.1   thorpej 
    414  1.139    bouyer #define ICH8_FLASH_READ32(sc, reg) \
    415  1.139    bouyer 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg))
    416  1.139    bouyer #define ICH8_FLASH_WRITE32(sc, reg, data) \
    417  1.139    bouyer 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
    418  1.139    bouyer 
    419  1.139    bouyer #define ICH8_FLASH_READ16(sc, reg) \
    420  1.139    bouyer 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg))
    421  1.139    bouyer #define ICH8_FLASH_WRITE16(sc, reg, data) \
    422  1.139    bouyer 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
    423  1.139    bouyer 
    424    1.1   thorpej #define	WM_CDTXADDR(sc, x)	((sc)->sc_cddma + WM_CDTXOFF((x)))
    425    1.1   thorpej #define	WM_CDRXADDR(sc, x)	((sc)->sc_cddma + WM_CDRXOFF((x)))
    426    1.1   thorpej 
    427   1.69   thorpej #define	WM_CDTXADDR_LO(sc, x)	(WM_CDTXADDR((sc), (x)) & 0xffffffffU)
    428   1.69   thorpej #define	WM_CDTXADDR_HI(sc, x)						\
    429   1.69   thorpej 	(sizeof(bus_addr_t) == 8 ?					\
    430   1.69   thorpej 	 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
    431   1.69   thorpej 
    432   1.69   thorpej #define	WM_CDRXADDR_LO(sc, x)	(WM_CDRXADDR((sc), (x)) & 0xffffffffU)
    433   1.69   thorpej #define	WM_CDRXADDR_HI(sc, x)						\
    434   1.69   thorpej 	(sizeof(bus_addr_t) == 8 ?					\
    435   1.69   thorpej 	 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
    436   1.69   thorpej 
    437    1.1   thorpej #define	WM_CDTXSYNC(sc, x, n, ops)					\
    438    1.1   thorpej do {									\
    439    1.1   thorpej 	int __x, __n;							\
    440    1.1   thorpej 									\
    441    1.1   thorpej 	__x = (x);							\
    442    1.1   thorpej 	__n = (n);							\
    443    1.1   thorpej 									\
    444    1.1   thorpej 	/* If it will wrap around, sync to the end of the ring. */	\
    445   1.75   thorpej 	if ((__x + __n) > WM_NTXDESC(sc)) {				\
    446    1.1   thorpej 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
    447    1.1   thorpej 		    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) *		\
    448   1.75   thorpej 		    (WM_NTXDESC(sc) - __x), (ops));			\
    449   1.75   thorpej 		__n -= (WM_NTXDESC(sc) - __x);				\
    450    1.1   thorpej 		__x = 0;						\
    451    1.1   thorpej 	}								\
    452    1.1   thorpej 									\
    453    1.1   thorpej 	/* Now sync whatever is left. */				\
    454    1.1   thorpej 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    455    1.1   thorpej 	    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops));	\
    456    1.1   thorpej } while (/*CONSTCOND*/0)
    457    1.1   thorpej 
    458    1.1   thorpej #define	WM_CDRXSYNC(sc, x, ops)						\
    459    1.1   thorpej do {									\
    460    1.1   thorpej 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    461    1.1   thorpej 	   WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops));		\
    462    1.1   thorpej } while (/*CONSTCOND*/0)
    463    1.1   thorpej 
    464    1.1   thorpej #define	WM_INIT_RXDESC(sc, x)						\
    465    1.1   thorpej do {									\
    466    1.1   thorpej 	struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
    467    1.1   thorpej 	wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];		\
    468    1.1   thorpej 	struct mbuf *__m = __rxs->rxs_mbuf;				\
    469    1.1   thorpej 									\
    470    1.1   thorpej 	/*								\
    471    1.1   thorpej 	 * Note: We scoot the packet forward 2 bytes in the buffer	\
    472    1.1   thorpej 	 * so that the payload after the Ethernet header is aligned	\
    473    1.1   thorpej 	 * to a 4-byte boundary.					\
    474    1.1   thorpej 	 *								\
    475    1.1   thorpej 	 * XXX BRAINDAMAGE ALERT!					\
    476    1.1   thorpej 	 * The stupid chip uses the same size for every buffer, which	\
    477    1.1   thorpej 	 * is set in the Receive Control register.  We are using the 2K	\
    478    1.1   thorpej 	 * size option, but what we REALLY want is (2K - 2)!  For this	\
    479   1.41       tls 	 * reason, we can't "scoot" packets longer than the standard	\
    480   1.41       tls 	 * Ethernet MTU.  On strict-alignment platforms, if the total	\
    481   1.42   thorpej 	 * size exceeds (2K - 2) we set align_tweak to 0 and let	\
    482   1.41       tls 	 * the upper layer copy the headers.				\
    483    1.1   thorpej 	 */								\
    484   1.42   thorpej 	__m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak;	\
    485    1.1   thorpej 									\
    486   1.69   thorpej 	wm_set_dma_addr(&__rxd->wrx_addr,				\
    487   1.69   thorpej 	    __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \
    488    1.1   thorpej 	__rxd->wrx_len = 0;						\
    489    1.1   thorpej 	__rxd->wrx_cksum = 0;						\
    490    1.1   thorpej 	__rxd->wrx_status = 0;						\
    491    1.1   thorpej 	__rxd->wrx_errors = 0;						\
    492    1.1   thorpej 	__rxd->wrx_special = 0;						\
    493    1.1   thorpej 	WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
    494    1.1   thorpej 									\
    495    1.1   thorpej 	CSR_WRITE((sc), (sc)->sc_rdt_reg, (x));				\
    496    1.1   thorpej } while (/*CONSTCOND*/0)
    497    1.1   thorpej 
    498   1.47   thorpej static void	wm_start(struct ifnet *);
    499   1.47   thorpej static void	wm_watchdog(struct ifnet *);
    500  1.135  christos static int	wm_ioctl(struct ifnet *, u_long, void *);
    501   1.47   thorpej static int	wm_init(struct ifnet *);
    502   1.47   thorpej static void	wm_stop(struct ifnet *, int);
    503    1.1   thorpej 
    504   1.47   thorpej static void	wm_reset(struct wm_softc *);
    505   1.47   thorpej static void	wm_rxdrain(struct wm_softc *);
    506   1.47   thorpej static int	wm_add_rxbuf(struct wm_softc *, int);
    507   1.51   thorpej static int	wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *);
    508  1.117   msaitoh static int	wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *);
    509  1.112     gavan static int	wm_validate_eeprom_checksum(struct wm_softc *);
    510   1.47   thorpej static void	wm_tick(void *);
    511    1.1   thorpej 
    512   1.47   thorpej static void	wm_set_filter(struct wm_softc *);
    513    1.1   thorpej 
    514   1.47   thorpej static int	wm_intr(void *);
    515   1.47   thorpej static void	wm_txintr(struct wm_softc *);
    516   1.47   thorpej static void	wm_rxintr(struct wm_softc *);
    517   1.47   thorpej static void	wm_linkintr(struct wm_softc *, uint32_t);
    518    1.1   thorpej 
    519   1.47   thorpej static void	wm_tbi_mediainit(struct wm_softc *);
    520   1.47   thorpej static int	wm_tbi_mediachange(struct ifnet *);
    521   1.47   thorpej static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
    522    1.1   thorpej 
    523   1.47   thorpej static void	wm_tbi_set_linkled(struct wm_softc *);
    524   1.47   thorpej static void	wm_tbi_check_link(struct wm_softc *);
    525    1.1   thorpej 
    526   1.47   thorpej static void	wm_gmii_reset(struct wm_softc *);
    527    1.1   thorpej 
    528  1.157    dyoung static int	wm_gmii_i82543_readreg(device_t, int, int);
    529  1.157    dyoung static void	wm_gmii_i82543_writereg(device_t, int, int, int);
    530    1.1   thorpej 
    531  1.157    dyoung static int	wm_gmii_i82544_readreg(device_t, int, int);
    532  1.157    dyoung static void	wm_gmii_i82544_writereg(device_t, int, int, int);
    533    1.1   thorpej 
    534  1.157    dyoung static int	wm_gmii_i80003_readreg(device_t, int, int);
    535  1.157    dyoung static void	wm_gmii_i80003_writereg(device_t, int, int, int);
    536  1.127    bouyer 
    537  1.167   msaitoh static int	wm_gmii_bm_readreg(device_t, int, int);
    538  1.167   msaitoh static void	wm_gmii_bm_writereg(device_t, int, int, int);
    539  1.167   msaitoh 
    540  1.157    dyoung static void	wm_gmii_statchg(device_t);
    541    1.1   thorpej 
    542   1.47   thorpej static void	wm_gmii_mediainit(struct wm_softc *);
    543   1.47   thorpej static int	wm_gmii_mediachange(struct ifnet *);
    544   1.47   thorpej static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
    545    1.1   thorpej 
    546  1.178   msaitoh static int	wm_kmrn_readreg(struct wm_softc *, int);
    547  1.178   msaitoh static void	wm_kmrn_writereg(struct wm_softc *, int, int);
    548  1.127    bouyer 
    549  1.160  christos static int	wm_match(device_t, cfdata_t, void *);
    550  1.157    dyoung static void	wm_attach(device_t, device_t, void *);
    551  1.117   msaitoh static int	wm_is_onboard_nvm_eeprom(struct wm_softc *);
    552  1.146   msaitoh static void	wm_get_auto_rd_done(struct wm_softc *);
    553  1.127    bouyer static int	wm_get_swsm_semaphore(struct wm_softc *);
    554  1.127    bouyer static void	wm_put_swsm_semaphore(struct wm_softc *);
    555  1.117   msaitoh static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
    556  1.127    bouyer static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
    557  1.127    bouyer static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
    558  1.139    bouyer static int	wm_get_swfwhw_semaphore(struct wm_softc *);
    559  1.139    bouyer static void	wm_put_swfwhw_semaphore(struct wm_softc *);
    560  1.139    bouyer 
    561  1.139    bouyer static int	wm_read_eeprom_ich8(struct wm_softc *, int, int, uint16_t *);
    562  1.139    bouyer static int32_t	wm_ich8_cycle_init(struct wm_softc *);
    563  1.139    bouyer static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
    564  1.139    bouyer static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t,
    565  1.148    simonb 		     uint32_t, uint16_t *);
    566  1.167   msaitoh static int32_t	wm_read_ich8_byte(struct wm_softc *sc, uint32_t, uint8_t *);
    567  1.139    bouyer static int32_t	wm_read_ich8_word(struct wm_softc *sc, uint32_t, uint16_t *);
    568  1.169   msaitoh static void	wm_82547_txfifo_stall(void *);
    569  1.169   msaitoh static int	wm_check_mng_mode(struct wm_softc *);
    570  1.169   msaitoh static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
    571  1.169   msaitoh #if 0
    572  1.169   msaitoh static int	wm_check_mng_mode_82574(struct wm_softc *);
    573  1.169   msaitoh #endif
    574  1.169   msaitoh static int	wm_check_mng_mode_generic(struct wm_softc *);
    575  1.169   msaitoh static void	wm_get_hw_control(struct wm_softc *);
    576  1.173   msaitoh static int	wm_check_for_link(struct wm_softc *);
    577    1.1   thorpej 
    578  1.160  christos CFATTACH_DECL_NEW(wm, sizeof(struct wm_softc),
    579   1.25   thorpej     wm_match, wm_attach, NULL, NULL);
    580    1.1   thorpej 
    581   1.78   thorpej 
    582    1.1   thorpej /*
    583    1.1   thorpej  * Devices supported by this driver.
    584    1.1   thorpej  */
    585   1.76   thorpej static const struct wm_product {
    586    1.1   thorpej 	pci_vendor_id_t		wmp_vendor;
    587    1.1   thorpej 	pci_product_id_t	wmp_product;
    588    1.1   thorpej 	const char		*wmp_name;
    589   1.43   thorpej 	wm_chip_type		wmp_type;
    590    1.1   thorpej 	int			wmp_flags;
    591    1.1   thorpej #define	WMP_F_1000X		0x01
    592    1.1   thorpej #define	WMP_F_1000T		0x02
    593    1.1   thorpej } wm_products[] = {
    594    1.1   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
    595    1.1   thorpej 	  "Intel i82542 1000BASE-X Ethernet",
    596   1.11   thorpej 	  WM_T_82542_2_1,	WMP_F_1000X },
    597    1.1   thorpej 
    598   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
    599   1.11   thorpej 	  "Intel i82543GC 1000BASE-X Ethernet",
    600   1.11   thorpej 	  WM_T_82543,		WMP_F_1000X },
    601    1.1   thorpej 
    602   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
    603   1.11   thorpej 	  "Intel i82543GC 1000BASE-T Ethernet",
    604   1.11   thorpej 	  WM_T_82543,		WMP_F_1000T },
    605    1.1   thorpej 
    606   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
    607   1.11   thorpej 	  "Intel i82544EI 1000BASE-T Ethernet",
    608   1.11   thorpej 	  WM_T_82544,		WMP_F_1000T },
    609    1.1   thorpej 
    610   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
    611   1.11   thorpej 	  "Intel i82544EI 1000BASE-X Ethernet",
    612   1.11   thorpej 	  WM_T_82544,		WMP_F_1000X },
    613    1.1   thorpej 
    614   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
    615    1.1   thorpej 	  "Intel i82544GC 1000BASE-T Ethernet",
    616   1.11   thorpej 	  WM_T_82544,		WMP_F_1000T },
    617    1.1   thorpej 
    618   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
    619   1.11   thorpej 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
    620   1.11   thorpej 	  WM_T_82544,		WMP_F_1000T },
    621    1.1   thorpej 
    622   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
    623   1.17   thorpej 	  "Intel i82540EM 1000BASE-T Ethernet",
    624   1.34      kent 	  WM_T_82540,		WMP_F_1000T },
    625   1.34      kent 
    626   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
    627   1.55   thorpej 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
    628   1.55   thorpej 	  WM_T_82540,		WMP_F_1000T },
    629   1.55   thorpej 
    630   1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
    631   1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    632   1.34      kent 	  WM_T_82540,		WMP_F_1000T },
    633   1.34      kent 
    634   1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
    635   1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    636   1.33      kent 	  WM_T_82540,		WMP_F_1000T },
    637   1.33      kent 
    638   1.33      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
    639   1.33      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    640   1.17   thorpej 	  WM_T_82540,		WMP_F_1000T },
    641   1.17   thorpej 
    642   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
    643   1.17   thorpej 	  "Intel i82545EM 1000BASE-T Ethernet",
    644   1.17   thorpej 	  WM_T_82545,		WMP_F_1000T },
    645   1.17   thorpej 
    646   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
    647   1.55   thorpej 	  "Intel i82545GM 1000BASE-T Ethernet",
    648   1.55   thorpej 	  WM_T_82545_3,		WMP_F_1000T },
    649   1.55   thorpej 
    650   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
    651   1.55   thorpej 	  "Intel i82545GM 1000BASE-X Ethernet",
    652   1.55   thorpej 	  WM_T_82545_3,		WMP_F_1000X },
    653   1.55   thorpej #if 0
    654   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
    655   1.55   thorpej 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
    656   1.55   thorpej 	  WM_T_82545_3,		WMP_F_SERDES },
    657   1.55   thorpej #endif
    658   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
    659   1.39   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
    660   1.39   thorpej 	  WM_T_82546,		WMP_F_1000T },
    661   1.39   thorpej 
    662   1.39   thorpej 	{ PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82546EB_QUAD,
    663   1.17   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
    664   1.17   thorpej 	  WM_T_82546,		WMP_F_1000T },
    665   1.17   thorpej 
    666   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
    667   1.17   thorpej 	  "Intel i82545EM 1000BASE-X Ethernet",
    668   1.17   thorpej 	  WM_T_82545,		WMP_F_1000X },
    669   1.17   thorpej 
    670   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
    671   1.17   thorpej 	  "Intel i82546EB 1000BASE-X Ethernet",
    672   1.17   thorpej 	  WM_T_82546,		WMP_F_1000X },
    673   1.17   thorpej 
    674   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
    675   1.55   thorpej 	  "Intel i82546GB 1000BASE-T Ethernet",
    676   1.55   thorpej 	  WM_T_82546_3,		WMP_F_1000T },
    677   1.55   thorpej 
    678   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
    679   1.55   thorpej 	  "Intel i82546GB 1000BASE-X Ethernet",
    680   1.55   thorpej 	  WM_T_82546_3,		WMP_F_1000X },
    681   1.55   thorpej #if 0
    682   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
    683   1.55   thorpej 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
    684   1.55   thorpej 	  WM_T_82546_3,		WMP_F_SERDES },
    685   1.55   thorpej #endif
    686  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
    687  1.127    bouyer 	  "i82546GB quad-port Gigabit Ethernet",
    688  1.127    bouyer 	  WM_T_82546_3,		WMP_F_1000T },
    689  1.127    bouyer 
    690  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
    691  1.127    bouyer 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
    692  1.127    bouyer 	  WM_T_82546_3,		WMP_F_1000T },
    693  1.127    bouyer 
    694  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
    695  1.116   msaitoh 	  "Intel PRO/1000MT (82546GB)",
    696  1.116   msaitoh 	  WM_T_82546_3,		WMP_F_1000T },
    697  1.116   msaitoh 
    698   1.63   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
    699   1.63   thorpej 	  "Intel i82541EI 1000BASE-T Ethernet",
    700   1.63   thorpej 	  WM_T_82541,		WMP_F_1000T },
    701   1.63   thorpej 
    702  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
    703  1.116   msaitoh 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
    704  1.116   msaitoh 	  WM_T_82541,		WMP_F_1000T },
    705  1.116   msaitoh 
    706   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
    707   1.57   thorpej 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
    708   1.57   thorpej 	  WM_T_82541,		WMP_F_1000T },
    709   1.57   thorpej 
    710   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
    711   1.57   thorpej 	  "Intel i82541ER 1000BASE-T Ethernet",
    712   1.57   thorpej 	  WM_T_82541_2,		WMP_F_1000T },
    713   1.57   thorpej 
    714   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
    715   1.57   thorpej 	  "Intel i82541GI 1000BASE-T Ethernet",
    716   1.57   thorpej 	  WM_T_82541_2,		WMP_F_1000T },
    717   1.57   thorpej 
    718   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
    719   1.57   thorpej 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
    720   1.57   thorpej 	  WM_T_82541_2,		WMP_F_1000T },
    721   1.57   thorpej 
    722  1.101      tron 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
    723  1.101      tron 	  "Intel i82541PI 1000BASE-T Ethernet",
    724  1.101      tron 	  WM_T_82541_2,		WMP_F_1000T },
    725  1.101      tron 
    726   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
    727   1.57   thorpej 	  "Intel i82547EI 1000BASE-T Ethernet",
    728   1.57   thorpej 	  WM_T_82547,		WMP_F_1000T },
    729   1.57   thorpej 
    730  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
    731  1.141    simonb 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
    732  1.116   msaitoh 	  WM_T_82547,		WMP_F_1000T },
    733  1.116   msaitoh 
    734   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
    735   1.57   thorpej 	  "Intel i82547GI 1000BASE-T Ethernet",
    736   1.57   thorpej 	  WM_T_82547_2,		WMP_F_1000T },
    737  1.116   msaitoh 
    738  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
    739  1.116   msaitoh 	  "Intel PRO/1000 PT (82571EB)",
    740  1.116   msaitoh 	  WM_T_82571,		WMP_F_1000T },
    741  1.116   msaitoh 
    742  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
    743  1.116   msaitoh 	  "Intel PRO/1000 PF (82571EB)",
    744  1.116   msaitoh 	  WM_T_82571,		WMP_F_1000X },
    745  1.116   msaitoh #if 0
    746  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
    747  1.116   msaitoh 	  "Intel PRO/1000 PB (82571EB)",
    748  1.116   msaitoh 	  WM_T_82571,		WMP_F_SERDES },
    749  1.116   msaitoh #endif
    750  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
    751  1.127    bouyer 	  "Intel PRO/1000 QT (82571EB)",
    752  1.127    bouyer 	  WM_T_82571,		WMP_F_1000T },
    753  1.127    bouyer 
    754  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
    755  1.116   msaitoh 	  "Intel i82572EI 1000baseT Ethernet",
    756  1.116   msaitoh 	  WM_T_82572,		WMP_F_1000T },
    757  1.116   msaitoh 
    758  1.151     ragge 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
    759  1.151     ragge 	  "Intel PRO/1000 PT Quad Port Server Adapter",
    760  1.151     ragge 	  WM_T_82571,		WMP_F_1000T, },
    761  1.151     ragge 
    762  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
    763  1.116   msaitoh 	  "Intel i82572EI 1000baseX Ethernet",
    764  1.116   msaitoh 	  WM_T_82572,		WMP_F_1000X },
    765  1.116   msaitoh #if 0
    766  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
    767  1.116   msaitoh 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
    768  1.116   msaitoh 	  WM_T_82572,		WMP_F_SERDES },
    769  1.116   msaitoh #endif
    770  1.116   msaitoh 
    771  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
    772  1.116   msaitoh 	  "Intel i82572EI 1000baseT Ethernet",
    773  1.116   msaitoh 	  WM_T_82572,		WMP_F_1000T },
    774  1.116   msaitoh 
    775  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
    776  1.116   msaitoh 	  "Intel i82573E",
    777  1.116   msaitoh 	  WM_T_82573,		WMP_F_1000T },
    778  1.116   msaitoh 
    779  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
    780  1.117   msaitoh 	  "Intel i82573E IAMT",
    781  1.116   msaitoh 	  WM_T_82573,		WMP_F_1000T },
    782  1.116   msaitoh 
    783  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
    784  1.116   msaitoh 	  "Intel i82573L Gigabit Ethernet",
    785  1.116   msaitoh 	  WM_T_82573,		WMP_F_1000T },
    786  1.116   msaitoh 
    787  1.165  sborrill 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
    788  1.165  sborrill 	  "Intel i82574L",
    789  1.165  sborrill 	  WM_T_82574,		WMP_F_1000T },
    790  1.165  sborrill 
    791  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
    792  1.127    bouyer 	  "i80003 dual 1000baseT Ethernet",
    793  1.127    bouyer 	  WM_T_80003,		WMP_F_1000T },
    794  1.127    bouyer 
    795  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
    796  1.127    bouyer 	  "i80003 dual 1000baseX Ethernet",
    797  1.127    bouyer 	  WM_T_80003,		WMP_F_1000T },
    798  1.127    bouyer #if 0
    799  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
    800  1.127    bouyer 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
    801  1.127    bouyer 	  WM_T_80003,		WMP_F_SERDES },
    802  1.127    bouyer #endif
    803  1.127    bouyer 
    804  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
    805  1.127    bouyer 	  "Intel i80003 1000baseT Ethernet",
    806  1.127    bouyer 	  WM_T_80003,		WMP_F_1000T },
    807  1.127    bouyer #if 0
    808  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
    809  1.127    bouyer 	  "Intel i80003 Gigabit Ethernet (SERDES)",
    810  1.127    bouyer 	  WM_T_80003,		WMP_F_SERDES },
    811  1.127    bouyer #endif
    812  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
    813  1.139    bouyer 	  "Intel i82801H (M_AMT) LAN Controller",
    814  1.139    bouyer 	  WM_T_ICH8,		WMP_F_1000T },
    815  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
    816  1.139    bouyer 	  "Intel i82801H (AMT) LAN Controller",
    817  1.139    bouyer 	  WM_T_ICH8,		WMP_F_1000T },
    818  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
    819  1.139    bouyer 	  "Intel i82801H LAN Controller",
    820  1.139    bouyer 	  WM_T_ICH8,		WMP_F_1000T },
    821  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
    822  1.139    bouyer 	  "Intel i82801H (IFE) LAN Controller",
    823  1.139    bouyer 	  WM_T_ICH8,		WMP_F_1000T },
    824  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
    825  1.139    bouyer 	  "Intel i82801H (M) LAN Controller",
    826  1.139    bouyer 	  WM_T_ICH8,		WMP_F_1000T },
    827  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
    828  1.139    bouyer 	  "Intel i82801H IFE (GT) LAN Controller",
    829  1.139    bouyer 	  WM_T_ICH8,		WMP_F_1000T },
    830  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
    831  1.139    bouyer 	  "Intel i82801H IFE (G) LAN Controller",
    832  1.139    bouyer 	  WM_T_ICH8,		WMP_F_1000T },
    833  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
    834  1.144   msaitoh 	  "82801I (AMT) LAN Controller",
    835  1.144   msaitoh 	  WM_T_ICH9,		WMP_F_1000T },
    836  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
    837  1.144   msaitoh 	  "82801I LAN Controller",
    838  1.144   msaitoh 	  WM_T_ICH9,		WMP_F_1000T },
    839  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
    840  1.144   msaitoh 	  "82801I (G) LAN Controller",
    841  1.144   msaitoh 	  WM_T_ICH9,		WMP_F_1000T },
    842  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
    843  1.144   msaitoh 	  "82801I (GT) LAN Controller",
    844  1.144   msaitoh 	  WM_T_ICH9,		WMP_F_1000T },
    845  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
    846  1.144   msaitoh 	  "82801I (C) LAN Controller",
    847  1.144   msaitoh 	  WM_T_ICH9,		WMP_F_1000T },
    848  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
    849  1.162    bouyer 	  "82801I mobile LAN Controller",
    850  1.162    bouyer 	  WM_T_ICH9,		WMP_F_1000T },
    851  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IGP_M_V,
    852  1.162    bouyer 	  "82801I mobile (V) LAN Controller",
    853  1.162    bouyer 	  WM_T_ICH9,		WMP_F_1000T },
    854  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
    855  1.162    bouyer 	  "82801I mobile (AMT) LAN Controller",
    856  1.162    bouyer 	  WM_T_ICH9,		WMP_F_1000T },
    857  1.164     markd 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82567LM_3,
    858  1.164     markd 	  "82567LM-3 LAN Controller",
    859  1.167   msaitoh 	  WM_T_ICH10,		WMP_F_1000T },
    860  1.167   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82567LF_3,
    861  1.167   msaitoh 	  "82567LF-3 LAN Controller",
    862  1.167   msaitoh 	  WM_T_ICH10,		WMP_F_1000T },
    863  1.174   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LF,
    864  1.174   msaitoh 	  "i82801J (LF) LAN Controller",
    865  1.174   msaitoh 	  WM_T_ICH10,		WMP_F_1000T },
    866    1.1   thorpej 	{ 0,			0,
    867    1.1   thorpej 	  NULL,
    868    1.1   thorpej 	  0,			0 },
    869    1.1   thorpej };
    870    1.1   thorpej 
    871    1.2   thorpej #ifdef WM_EVENT_COUNTERS
    872   1.75   thorpej static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")];
    873    1.2   thorpej #endif /* WM_EVENT_COUNTERS */
    874    1.2   thorpej 
    875   1.53   thorpej #if 0 /* Not currently used */
    876  1.110     perry static inline uint32_t
    877   1.53   thorpej wm_io_read(struct wm_softc *sc, int reg)
    878   1.53   thorpej {
    879   1.53   thorpej 
    880   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
    881   1.53   thorpej 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
    882   1.53   thorpej }
    883   1.53   thorpej #endif
    884   1.53   thorpej 
    885  1.110     perry static inline void
    886   1.53   thorpej wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
    887   1.53   thorpej {
    888   1.53   thorpej 
    889   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
    890   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
    891   1.53   thorpej }
    892   1.53   thorpej 
    893  1.110     perry static inline void
    894  1.110     perry wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
    895   1.69   thorpej {
    896   1.69   thorpej 	wa->wa_low = htole32(v & 0xffffffffU);
    897   1.69   thorpej 	if (sizeof(bus_addr_t) == 8)
    898   1.69   thorpej 		wa->wa_high = htole32((uint64_t) v >> 32);
    899   1.69   thorpej 	else
    900   1.69   thorpej 		wa->wa_high = 0;
    901   1.69   thorpej }
    902   1.69   thorpej 
    903    1.1   thorpej static const struct wm_product *
    904    1.1   thorpej wm_lookup(const struct pci_attach_args *pa)
    905    1.1   thorpej {
    906    1.1   thorpej 	const struct wm_product *wmp;
    907    1.1   thorpej 
    908    1.1   thorpej 	for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
    909    1.1   thorpej 		if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
    910    1.1   thorpej 		    PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
    911    1.1   thorpej 			return (wmp);
    912    1.1   thorpej 	}
    913    1.1   thorpej 	return (NULL);
    914    1.1   thorpej }
    915    1.1   thorpej 
    916   1.47   thorpej static int
    917  1.160  christos wm_match(device_t parent, cfdata_t cf, void *aux)
    918    1.1   thorpej {
    919    1.1   thorpej 	struct pci_attach_args *pa = aux;
    920    1.1   thorpej 
    921    1.1   thorpej 	if (wm_lookup(pa) != NULL)
    922    1.1   thorpej 		return (1);
    923    1.1   thorpej 
    924    1.1   thorpej 	return (0);
    925    1.1   thorpej }
    926    1.1   thorpej 
    927   1.47   thorpej static void
    928  1.157    dyoung wm_attach(device_t parent, device_t self, void *aux)
    929    1.1   thorpej {
    930  1.157    dyoung 	struct wm_softc *sc = device_private(self);
    931    1.1   thorpej 	struct pci_attach_args *pa = aux;
    932  1.182   msaitoh 	prop_dictionary_t dict;
    933    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    934    1.1   thorpej 	pci_chipset_tag_t pc = pa->pa_pc;
    935    1.1   thorpej 	pci_intr_handle_t ih;
    936   1.75   thorpej 	size_t cdata_size;
    937    1.1   thorpej 	const char *intrstr = NULL;
    938  1.160  christos 	const char *eetype, *xname;
    939    1.1   thorpej 	bus_space_tag_t memt;
    940    1.1   thorpej 	bus_space_handle_t memh;
    941    1.1   thorpej 	bus_dma_segment_t seg;
    942    1.1   thorpej 	int memh_valid;
    943    1.1   thorpej 	int i, rseg, error;
    944    1.1   thorpej 	const struct wm_product *wmp;
    945  1.115   thorpej 	prop_data_t ea;
    946  1.115   thorpej 	prop_number_t pn;
    947    1.1   thorpej 	uint8_t enaddr[ETHER_ADDR_LEN];
    948    1.1   thorpej 	uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
    949    1.1   thorpej 	pcireg_t preg, memtype;
    950   1.44   thorpej 	uint32_t reg;
    951    1.1   thorpej 
    952  1.160  christos 	sc->sc_dev = self;
    953  1.142        ad 	callout_init(&sc->sc_tick_ch, 0);
    954    1.1   thorpej 
    955    1.1   thorpej 	wmp = wm_lookup(pa);
    956    1.1   thorpej 	if (wmp == NULL) {
    957    1.1   thorpej 		printf("\n");
    958    1.1   thorpej 		panic("wm_attach: impossible");
    959    1.1   thorpej 	}
    960    1.1   thorpej 
    961  1.123  jmcneill 	sc->sc_pc = pa->pa_pc;
    962  1.123  jmcneill 	sc->sc_pcitag = pa->pa_tag;
    963  1.123  jmcneill 
    964   1.69   thorpej 	if (pci_dma64_available(pa))
    965   1.69   thorpej 		sc->sc_dmat = pa->pa_dmat64;
    966   1.69   thorpej 	else
    967   1.69   thorpej 		sc->sc_dmat = pa->pa_dmat;
    968    1.1   thorpej 
    969    1.1   thorpej 	preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG));
    970   1.37   thorpej 	aprint_naive(": Ethernet controller\n");
    971   1.37   thorpej 	aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg);
    972    1.1   thorpej 
    973    1.1   thorpej 	sc->sc_type = wmp->wmp_type;
    974   1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
    975    1.1   thorpej 		if (preg < 2) {
    976  1.160  christos 			aprint_error_dev(sc->sc_dev,
    977  1.160  christos 			    "i82542 must be at least rev. 2\n");
    978    1.1   thorpej 			return;
    979    1.1   thorpej 		}
    980    1.1   thorpej 		if (preg < 3)
    981   1.11   thorpej 			sc->sc_type = WM_T_82542_2_0;
    982    1.1   thorpej 	}
    983    1.1   thorpej 
    984  1.182   msaitoh 	/* Set device properties */
    985  1.182   msaitoh 	dict = device_properties(sc->sc_dev);
    986  1.182   msaitoh 	prop_dictionary_set_uint32(dict, "mactype", sc->sc_type);
    987  1.182   msaitoh 
    988    1.1   thorpej 	/*
    989   1.53   thorpej 	 * Map the device.  All devices support memory-mapped acccess,
    990   1.53   thorpej 	 * and it is really required for normal operation.
    991    1.1   thorpej 	 */
    992    1.1   thorpej 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
    993    1.1   thorpej 	switch (memtype) {
    994    1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
    995    1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
    996    1.1   thorpej 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
    997    1.1   thorpej 		    memtype, 0, &memt, &memh, NULL, NULL) == 0);
    998    1.1   thorpej 		break;
    999    1.1   thorpej 	default:
   1000    1.1   thorpej 		memh_valid = 0;
   1001    1.1   thorpej 	}
   1002    1.1   thorpej 
   1003    1.1   thorpej 	if (memh_valid) {
   1004    1.1   thorpej 		sc->sc_st = memt;
   1005    1.1   thorpej 		sc->sc_sh = memh;
   1006    1.1   thorpej 	} else {
   1007  1.160  christos 		aprint_error_dev(sc->sc_dev,
   1008  1.160  christos 		    "unable to map device registers\n");
   1009    1.1   thorpej 		return;
   1010    1.1   thorpej 	}
   1011    1.1   thorpej 
   1012   1.53   thorpej 	/*
   1013   1.53   thorpej 	 * In addition, i82544 and later support I/O mapped indirect
   1014   1.53   thorpej 	 * register access.  It is not desirable (nor supported in
   1015   1.53   thorpej 	 * this driver) to use it for normal operation, though it is
   1016   1.53   thorpej 	 * required to work around bugs in some chip versions.
   1017   1.53   thorpej 	 */
   1018   1.53   thorpej 	if (sc->sc_type >= WM_T_82544) {
   1019   1.53   thorpej 		/* First we have to find the I/O BAR. */
   1020   1.53   thorpej 		for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
   1021   1.53   thorpej 			if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) ==
   1022   1.53   thorpej 			    PCI_MAPREG_TYPE_IO)
   1023   1.53   thorpej 				break;
   1024   1.53   thorpej 		}
   1025   1.53   thorpej 		if (i == PCI_MAPREG_END)
   1026  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1027  1.160  christos 			    "WARNING: unable to find I/O BAR\n");
   1028   1.88    briggs 		else {
   1029   1.88    briggs 			/*
   1030   1.88    briggs 			 * The i8254x doesn't apparently respond when the
   1031   1.88    briggs 			 * I/O BAR is 0, which looks somewhat like it's not
   1032   1.88    briggs 			 * been configured.
   1033   1.88    briggs 			 */
   1034   1.88    briggs 			preg = pci_conf_read(pc, pa->pa_tag, i);
   1035   1.88    briggs 			if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
   1036  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1037  1.160  christos 				    "WARNING: I/O BAR at zero.\n");
   1038   1.88    briggs 			} else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
   1039   1.53   thorpej 					0, &sc->sc_iot, &sc->sc_ioh,
   1040   1.88    briggs 					NULL, NULL) == 0) {
   1041   1.88    briggs 				sc->sc_flags |= WM_F_IOH_VALID;
   1042   1.88    briggs 			} else {
   1043  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1044  1.160  christos 				    "WARNING: unable to map I/O space\n");
   1045   1.88    briggs 			}
   1046   1.88    briggs 		}
   1047   1.88    briggs 
   1048   1.53   thorpej 	}
   1049   1.53   thorpej 
   1050   1.11   thorpej 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
   1051    1.1   thorpej 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
   1052    1.1   thorpej 	preg |= PCI_COMMAND_MASTER_ENABLE;
   1053   1.11   thorpej 	if (sc->sc_type < WM_T_82542_2_1)
   1054    1.1   thorpej 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
   1055    1.1   thorpej 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
   1056    1.1   thorpej 
   1057  1.122  christos 	/* power up chip */
   1058  1.157    dyoung 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
   1059  1.122  christos 	    NULL)) && error != EOPNOTSUPP) {
   1060  1.160  christos 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
   1061  1.122  christos 		return;
   1062    1.1   thorpej 	}
   1063    1.1   thorpej 
   1064    1.1   thorpej 	/*
   1065    1.1   thorpej 	 * Map and establish our interrupt.
   1066    1.1   thorpej 	 */
   1067    1.1   thorpej 	if (pci_intr_map(pa, &ih)) {
   1068  1.160  christos 		aprint_error_dev(sc->sc_dev, "unable to map interrupt\n");
   1069    1.1   thorpej 		return;
   1070    1.1   thorpej 	}
   1071    1.1   thorpej 	intrstr = pci_intr_string(pc, ih);
   1072    1.1   thorpej 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc);
   1073    1.1   thorpej 	if (sc->sc_ih == NULL) {
   1074  1.160  christos 		aprint_error_dev(sc->sc_dev, "unable to establish interrupt");
   1075    1.1   thorpej 		if (intrstr != NULL)
   1076  1.181     njoly 			aprint_error(" at %s", intrstr);
   1077  1.181     njoly 		aprint_error("\n");
   1078    1.1   thorpej 		return;
   1079    1.1   thorpej 	}
   1080  1.160  christos 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
   1081   1.52   thorpej 
   1082   1.52   thorpej 	/*
   1083   1.52   thorpej 	 * Determine a few things about the bus we're connected to.
   1084   1.52   thorpej 	 */
   1085   1.52   thorpej 	if (sc->sc_type < WM_T_82543) {
   1086   1.52   thorpej 		/* We don't really know the bus characteristics here. */
   1087   1.52   thorpej 		sc->sc_bus_speed = 33;
   1088   1.73      tron 	} else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
   1089   1.73      tron 		/*
   1090   1.73      tron 		 * CSA (Communication Streaming Architecture) is about as fast
   1091   1.73      tron 		 * a 32-bit 66MHz PCI Bus.
   1092   1.73      tron 		 */
   1093   1.73      tron 		sc->sc_flags |= WM_F_CSA;
   1094   1.73      tron 		sc->sc_bus_speed = 66;
   1095  1.160  christos 		aprint_verbose_dev(sc->sc_dev,
   1096  1.160  christos 		    "Communication Streaming Architecture\n");
   1097   1.78   thorpej 		if (sc->sc_type == WM_T_82547) {
   1098  1.142        ad 			callout_init(&sc->sc_txfifo_ch, 0);
   1099   1.78   thorpej 			callout_setfunc(&sc->sc_txfifo_ch,
   1100   1.78   thorpej 					wm_82547_txfifo_stall, sc);
   1101  1.160  christos 			aprint_verbose_dev(sc->sc_dev,
   1102  1.160  christos 			    "using 82547 Tx FIFO stall work-around\n");
   1103   1.78   thorpej 		}
   1104  1.116   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   1105  1.139    bouyer 		sc->sc_flags |= WM_F_PCIE;
   1106  1.167   msaitoh 		if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
   1107  1.167   msaitoh 			&& (sc->sc_type != WM_T_ICH10))
   1108  1.139    bouyer 			sc->sc_flags |= WM_F_EEPROM_SEMAPHORE;
   1109  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
   1110   1.73      tron 	} else {
   1111   1.52   thorpej 		reg = CSR_READ(sc, WMREG_STATUS);
   1112   1.52   thorpej 		if (reg & STATUS_BUS64)
   1113   1.52   thorpej 			sc->sc_flags |= WM_F_BUS64;
   1114  1.176   msaitoh 		if ((reg & STATUS_PCIX_MODE) != 0) {
   1115   1.54   thorpej 			pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
   1116   1.54   thorpej 
   1117   1.52   thorpej 			sc->sc_flags |= WM_F_PCIX;
   1118   1.54   thorpej 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
   1119   1.54   thorpej 					       PCI_CAP_PCIX,
   1120   1.54   thorpej 					       &sc->sc_pcix_offset, NULL) == 0)
   1121  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1122  1.160  christos 				    "unable to find PCIX capability\n");
   1123   1.54   thorpej 			else if (sc->sc_type != WM_T_82545_3 &&
   1124   1.54   thorpej 				 sc->sc_type != WM_T_82546_3) {
   1125   1.54   thorpej 				/*
   1126   1.54   thorpej 				 * Work around a problem caused by the BIOS
   1127   1.54   thorpej 				 * setting the max memory read byte count
   1128   1.54   thorpej 				 * incorrectly.
   1129   1.54   thorpej 				 */
   1130   1.54   thorpej 				pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
   1131   1.54   thorpej 				    sc->sc_pcix_offset + PCI_PCIX_CMD);
   1132   1.54   thorpej 				pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
   1133   1.54   thorpej 				    sc->sc_pcix_offset + PCI_PCIX_STATUS);
   1134   1.54   thorpej 
   1135   1.54   thorpej 				bytecnt =
   1136   1.54   thorpej 				    (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >>
   1137   1.54   thorpej 				    PCI_PCIX_CMD_BYTECNT_SHIFT;
   1138   1.54   thorpej 				maxb =
   1139   1.54   thorpej 				    (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >>
   1140   1.54   thorpej 				    PCI_PCIX_STATUS_MAXB_SHIFT;
   1141   1.54   thorpej 				if (bytecnt > maxb) {
   1142  1.160  christos 					aprint_verbose_dev(sc->sc_dev,
   1143  1.160  christos 					    "resetting PCI-X MMRBC: %d -> %d\n",
   1144   1.54   thorpej 					    512 << bytecnt, 512 << maxb);
   1145   1.54   thorpej 					pcix_cmd = (pcix_cmd &
   1146   1.54   thorpej 					    ~PCI_PCIX_CMD_BYTECNT_MASK) |
   1147   1.54   thorpej 					   (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT);
   1148   1.54   thorpej 					pci_conf_write(pa->pa_pc, pa->pa_tag,
   1149   1.54   thorpej 					    sc->sc_pcix_offset + PCI_PCIX_CMD,
   1150   1.54   thorpej 					    pcix_cmd);
   1151   1.54   thorpej 				}
   1152   1.54   thorpej 			}
   1153   1.54   thorpej 		}
   1154   1.52   thorpej 		/*
   1155   1.52   thorpej 		 * The quad port adapter is special; it has a PCIX-PCIX
   1156   1.52   thorpej 		 * bridge on the board, and can run the secondary bus at
   1157   1.52   thorpej 		 * a higher speed.
   1158   1.52   thorpej 		 */
   1159   1.52   thorpej 		if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
   1160   1.52   thorpej 			sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
   1161   1.52   thorpej 								      : 66;
   1162   1.52   thorpej 		} else if (sc->sc_flags & WM_F_PCIX) {
   1163   1.62   thorpej 			switch (reg & STATUS_PCIXSPD_MASK) {
   1164   1.52   thorpej 			case STATUS_PCIXSPD_50_66:
   1165   1.52   thorpej 				sc->sc_bus_speed = 66;
   1166   1.52   thorpej 				break;
   1167   1.52   thorpej 			case STATUS_PCIXSPD_66_100:
   1168   1.52   thorpej 				sc->sc_bus_speed = 100;
   1169   1.52   thorpej 				break;
   1170   1.52   thorpej 			case STATUS_PCIXSPD_100_133:
   1171   1.52   thorpej 				sc->sc_bus_speed = 133;
   1172   1.52   thorpej 				break;
   1173   1.52   thorpej 			default:
   1174  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1175  1.158    cegger 				    "unknown PCIXSPD %d; assuming 66MHz\n",
   1176   1.62   thorpej 				    reg & STATUS_PCIXSPD_MASK);
   1177   1.52   thorpej 				sc->sc_bus_speed = 66;
   1178   1.52   thorpej 			}
   1179   1.52   thorpej 		} else
   1180   1.52   thorpej 			sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
   1181  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n",
   1182   1.52   thorpej 		    (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
   1183   1.52   thorpej 		    (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
   1184   1.52   thorpej 	}
   1185    1.1   thorpej 
   1186    1.1   thorpej 	/*
   1187    1.1   thorpej 	 * Allocate the control data structures, and create and load the
   1188    1.1   thorpej 	 * DMA map for it.
   1189   1.69   thorpej 	 *
   1190   1.69   thorpej 	 * NOTE: All Tx descriptors must be in the same 4G segment of
   1191   1.69   thorpej 	 * memory.  So must Rx descriptors.  We simplify by allocating
   1192   1.69   thorpej 	 * both sets within the same 4G segment.
   1193    1.1   thorpej 	 */
   1194   1.75   thorpej 	WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ?
   1195   1.75   thorpej 	    WM_NTXDESC_82542 : WM_NTXDESC_82544;
   1196   1.75   thorpej 	cdata_size = sc->sc_type < WM_T_82544 ?
   1197   1.75   thorpej 	    sizeof(struct wm_control_data_82542) :
   1198   1.75   thorpej 	    sizeof(struct wm_control_data_82544);
   1199   1.75   thorpej 	if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE,
   1200   1.75   thorpej 				      (bus_size_t) 0x100000000ULL,
   1201   1.69   thorpej 				      &seg, 1, &rseg, 0)) != 0) {
   1202  1.160  christos 		aprint_error_dev(sc->sc_dev,
   1203  1.158    cegger 		    "unable to allocate control data, error = %d\n",
   1204  1.158    cegger 		    error);
   1205    1.1   thorpej 		goto fail_0;
   1206    1.1   thorpej 	}
   1207    1.1   thorpej 
   1208   1.75   thorpej 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size,
   1209  1.155     rafal 				    (void **)&sc->sc_control_data,
   1210  1.155     rafal 				    BUS_DMA_COHERENT)) != 0) {
   1211  1.160  christos 		aprint_error_dev(sc->sc_dev,
   1212  1.160  christos 		    "unable to map control data, error = %d\n", error);
   1213    1.1   thorpej 		goto fail_1;
   1214    1.1   thorpej 	}
   1215    1.1   thorpej 
   1216   1.75   thorpej 	if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size,
   1217   1.75   thorpej 				       0, 0, &sc->sc_cddmamap)) != 0) {
   1218  1.160  christos 		aprint_error_dev(sc->sc_dev,
   1219  1.160  christos 		    "unable to create control data DMA map, error = %d\n",
   1220  1.160  christos 		    error);
   1221    1.1   thorpej 		goto fail_2;
   1222    1.1   thorpej 	}
   1223    1.1   thorpej 
   1224    1.1   thorpej 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
   1225   1.75   thorpej 				     sc->sc_control_data, cdata_size, NULL,
   1226   1.69   thorpej 				     0)) != 0) {
   1227  1.160  christos 		aprint_error_dev(sc->sc_dev,
   1228  1.158    cegger 		    "unable to load control data DMA map, error = %d\n",
   1229  1.158    cegger 		    error);
   1230    1.1   thorpej 		goto fail_3;
   1231    1.1   thorpej 	}
   1232    1.1   thorpej 
   1233   1.74      tron 
   1234    1.1   thorpej 	/*
   1235    1.1   thorpej 	 * Create the transmit buffer DMA maps.
   1236    1.1   thorpej 	 */
   1237   1.74      tron 	WM_TXQUEUELEN(sc) =
   1238   1.74      tron 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
   1239   1.74      tron 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
   1240   1.74      tron 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
   1241   1.82   thorpej 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
   1242   1.79   thorpej 					       WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
   1243   1.69   thorpej 					  &sc->sc_txsoft[i].txs_dmamap)) != 0) {
   1244  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1245  1.160  christos 			    "unable to create Tx DMA map %d, error = %d\n",
   1246  1.160  christos 			    i, error);
   1247    1.1   thorpej 			goto fail_4;
   1248    1.1   thorpej 		}
   1249    1.1   thorpej 	}
   1250    1.1   thorpej 
   1251    1.1   thorpej 	/*
   1252    1.1   thorpej 	 * Create the receive buffer DMA maps.
   1253    1.1   thorpej 	 */
   1254    1.1   thorpej 	for (i = 0; i < WM_NRXDESC; i++) {
   1255    1.1   thorpej 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
   1256   1.69   thorpej 					       MCLBYTES, 0, 0,
   1257   1.69   thorpej 					  &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
   1258  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1259  1.160  christos 			    "unable to create Rx DMA map %d error = %d\n",
   1260  1.160  christos 			    i, error);
   1261    1.1   thorpej 			goto fail_5;
   1262    1.1   thorpej 		}
   1263    1.1   thorpej 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
   1264    1.1   thorpej 	}
   1265    1.1   thorpej 
   1266  1.127    bouyer 	/* clear interesting stat counters */
   1267  1.127    bouyer 	CSR_READ(sc, WMREG_COLC);
   1268  1.127    bouyer 	CSR_READ(sc, WMREG_RXERRC);
   1269  1.127    bouyer 
   1270    1.1   thorpej 	/*
   1271    1.1   thorpej 	 * Reset the chip to a known state.
   1272    1.1   thorpej 	 */
   1273    1.1   thorpej 	wm_reset(sc);
   1274    1.1   thorpej 
   1275  1.169   msaitoh 	switch (sc->sc_type) {
   1276  1.169   msaitoh 	case WM_T_82571:
   1277  1.169   msaitoh 	case WM_T_82572:
   1278  1.169   msaitoh 	case WM_T_82573:
   1279  1.169   msaitoh 	case WM_T_82574:
   1280  1.169   msaitoh 	case WM_T_80003:
   1281  1.169   msaitoh 	case WM_T_ICH8:
   1282  1.169   msaitoh 	case WM_T_ICH9:
   1283  1.169   msaitoh 	case WM_T_ICH10:
   1284  1.169   msaitoh 		if (wm_check_mng_mode(sc) != 0)
   1285  1.169   msaitoh 			wm_get_hw_control(sc);
   1286  1.169   msaitoh 		break;
   1287  1.169   msaitoh 	default:
   1288  1.169   msaitoh 		break;
   1289  1.169   msaitoh 	}
   1290  1.169   msaitoh 
   1291    1.1   thorpej 	/*
   1292   1.44   thorpej 	 * Get some information about the EEPROM.
   1293   1.44   thorpej 	 */
   1294  1.167   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   1295  1.167   msaitoh 	    || (sc->sc_type == WM_T_ICH10)) {
   1296  1.139    bouyer 		uint32_t flash_size;
   1297  1.139    bouyer 		sc->sc_flags |= WM_F_SWFWHW_SYNC | WM_F_EEPROM_FLASH;
   1298  1.139    bouyer 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH);
   1299  1.139    bouyer 		if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
   1300  1.139    bouyer 		    &sc->sc_flasht, &sc->sc_flashh, NULL, NULL)) {
   1301  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1302  1.160  christos 			    "can't map FLASH registers\n");
   1303  1.139    bouyer 			return;
   1304  1.139    bouyer 		}
   1305  1.139    bouyer 		flash_size = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
   1306  1.139    bouyer 		sc->sc_ich8_flash_base = (flash_size & ICH_GFPREG_BASE_MASK) *
   1307  1.139    bouyer 						ICH_FLASH_SECTOR_SIZE;
   1308  1.139    bouyer 		sc->sc_ich8_flash_bank_size =
   1309  1.139    bouyer 			((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
   1310  1.139    bouyer 		sc->sc_ich8_flash_bank_size -=
   1311  1.139    bouyer 			(flash_size & ICH_GFPREG_BASE_MASK);
   1312  1.139    bouyer 		sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
   1313  1.139    bouyer 		sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
   1314  1.139    bouyer 	} else if (sc->sc_type == WM_T_80003)
   1315  1.136   msaitoh 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR |  WM_F_SWFW_SYNC;
   1316  1.127    bouyer 	else if (sc->sc_type == WM_T_82573)
   1317  1.136   msaitoh 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
   1318  1.165  sborrill 	else if (sc->sc_type == WM_T_82574)
   1319  1.165  sborrill 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
   1320  1.117   msaitoh 	else if (sc->sc_type > WM_T_82544)
   1321   1.44   thorpej 		sc->sc_flags |= WM_F_EEPROM_HANDSHAKE;
   1322  1.117   msaitoh 
   1323   1.44   thorpej 	if (sc->sc_type <= WM_T_82544)
   1324   1.44   thorpej 		sc->sc_ee_addrbits = 6;
   1325   1.44   thorpej 	else if (sc->sc_type <= WM_T_82546_3) {
   1326   1.44   thorpej 		reg = CSR_READ(sc, WMREG_EECD);
   1327   1.44   thorpej 		if (reg & EECD_EE_SIZE)
   1328   1.44   thorpej 			sc->sc_ee_addrbits = 8;
   1329   1.44   thorpej 		else
   1330   1.44   thorpej 			sc->sc_ee_addrbits = 6;
   1331   1.57   thorpej 	} else if (sc->sc_type <= WM_T_82547_2) {
   1332   1.57   thorpej 		reg = CSR_READ(sc, WMREG_EECD);
   1333   1.57   thorpej 		if (reg & EECD_EE_TYPE) {
   1334   1.57   thorpej 			sc->sc_flags |= WM_F_EEPROM_SPI;
   1335   1.57   thorpej 			sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
   1336   1.57   thorpej 		} else
   1337   1.57   thorpej 			sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6;
   1338  1.165  sborrill 	} else if ((sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574) &&
   1339  1.117   msaitoh 	    (wm_is_onboard_nvm_eeprom(sc) == 0)) {
   1340  1.117   msaitoh 		sc->sc_flags |= WM_F_EEPROM_FLASH;
   1341   1.57   thorpej 	} else {
   1342   1.57   thorpej 		/* Assume everything else is SPI. */
   1343   1.57   thorpej 		reg = CSR_READ(sc, WMREG_EECD);
   1344   1.57   thorpej 		sc->sc_flags |= WM_F_EEPROM_SPI;
   1345   1.57   thorpej 		sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
   1346   1.44   thorpej 	}
   1347  1.112     gavan 
   1348  1.112     gavan 	/*
   1349  1.112     gavan 	 * Defer printing the EEPROM type until after verifying the checksum
   1350  1.112     gavan 	 * This allows the EEPROM type to be printed correctly in the case
   1351  1.112     gavan 	 * that no EEPROM is attached.
   1352  1.112     gavan 	 */
   1353  1.112     gavan 
   1354  1.112     gavan 	/*
   1355  1.113     gavan 	 * Validate the EEPROM checksum. If the checksum fails, flag this for
   1356  1.113     gavan 	 * later, so we can fail future reads from the EEPROM.
   1357    1.1   thorpej 	 */
   1358  1.169   msaitoh 	if (wm_validate_eeprom_checksum(sc)) {
   1359  1.169   msaitoh 		/*
   1360  1.169   msaitoh 		 * Read twice again because some PCI-e parts fail the first
   1361  1.169   msaitoh 		 * check due to the link being in sleep state.
   1362  1.169   msaitoh 		 */
   1363  1.169   msaitoh 		if (wm_validate_eeprom_checksum(sc))
   1364  1.169   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVALID;
   1365  1.169   msaitoh 	}
   1366  1.112     gavan 
   1367  1.113     gavan 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   1368  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "No EEPROM\n");
   1369  1.117   msaitoh 	else if (sc->sc_flags & WM_F_EEPROM_FLASH) {
   1370  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "FLASH\n");
   1371  1.117   msaitoh 	} else {
   1372  1.112     gavan 		if (sc->sc_flags & WM_F_EEPROM_SPI)
   1373  1.112     gavan 			eetype = "SPI";
   1374  1.112     gavan 		else
   1375  1.112     gavan 			eetype = "MicroWire";
   1376  1.160  christos 		aprint_verbose_dev(sc->sc_dev,
   1377  1.160  christos 		    "%u word (%d address bits) %s EEPROM\n",
   1378  1.158    cegger 		    1U << sc->sc_ee_addrbits,
   1379  1.112     gavan 		    sc->sc_ee_addrbits, eetype);
   1380  1.112     gavan 	}
   1381  1.112     gavan 
   1382  1.113     gavan 	/*
   1383  1.113     gavan 	 * Read the Ethernet address from the EEPROM, if not first found
   1384  1.113     gavan 	 * in device properties.
   1385  1.113     gavan 	 */
   1386  1.182   msaitoh 	ea = prop_dictionary_get(dict, "mac-addr");
   1387  1.115   thorpej 	if (ea != NULL) {
   1388  1.115   thorpej 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
   1389  1.115   thorpej 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
   1390  1.115   thorpej 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
   1391  1.115   thorpej 	} else {
   1392  1.113     gavan 		if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
   1393  1.113     gavan 		    sizeof(myea) / sizeof(myea[0]), myea)) {
   1394  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1395  1.160  christos 			    "unable to read Ethernet address\n");
   1396  1.113     gavan 			return;
   1397  1.113     gavan 		}
   1398  1.113     gavan 		enaddr[0] = myea[0] & 0xff;
   1399  1.113     gavan 		enaddr[1] = myea[0] >> 8;
   1400  1.113     gavan 		enaddr[2] = myea[1] & 0xff;
   1401  1.113     gavan 		enaddr[3] = myea[1] >> 8;
   1402  1.113     gavan 		enaddr[4] = myea[2] & 0xff;
   1403  1.113     gavan 		enaddr[5] = myea[2] >> 8;
   1404  1.113     gavan 	}
   1405    1.1   thorpej 
   1406   1.17   thorpej 	/*
   1407   1.17   thorpej 	 * Toggle the LSB of the MAC address on the second port
   1408  1.121   msaitoh 	 * of the dual port controller.
   1409   1.17   thorpej 	 */
   1410  1.121   msaitoh 	if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3
   1411  1.127    bouyer 	    || sc->sc_type ==  WM_T_82571 || sc->sc_type == WM_T_80003) {
   1412   1.17   thorpej 		if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1)
   1413   1.17   thorpej 			enaddr[5] ^= 1;
   1414   1.17   thorpej 	}
   1415   1.17   thorpej 
   1416  1.160  christos 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
   1417    1.1   thorpej 	    ether_sprintf(enaddr));
   1418    1.1   thorpej 
   1419    1.1   thorpej 	/*
   1420    1.1   thorpej 	 * Read the config info from the EEPROM, and set up various
   1421    1.1   thorpej 	 * bits in the control registers based on their contents.
   1422    1.1   thorpej 	 */
   1423  1.182   msaitoh 	pn = prop_dictionary_get(dict, "i82543-cfg1");
   1424  1.115   thorpej 	if (pn != NULL) {
   1425  1.115   thorpej 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   1426  1.115   thorpej 		cfg1 = (uint16_t) prop_number_integer_value(pn);
   1427  1.115   thorpej 	} else {
   1428  1.113     gavan 		if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
   1429  1.160  christos 			aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
   1430  1.113     gavan 			return;
   1431  1.113     gavan 		}
   1432   1.51   thorpej 	}
   1433  1.115   thorpej 
   1434  1.182   msaitoh 	pn = prop_dictionary_get(dict, "i82543-cfg2");
   1435  1.115   thorpej 	if (pn != NULL) {
   1436  1.115   thorpej 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   1437  1.115   thorpej 		cfg2 = (uint16_t) prop_number_integer_value(pn);
   1438  1.115   thorpej 	} else {
   1439  1.113     gavan 		if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
   1440  1.160  christos 			aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
   1441  1.113     gavan 			return;
   1442  1.113     gavan 		}
   1443   1.51   thorpej 	}
   1444  1.115   thorpej 
   1445   1.51   thorpej 	if (sc->sc_type >= WM_T_82544) {
   1446  1.182   msaitoh 		pn = prop_dictionary_get(dict, "i82543-swdpin");
   1447  1.115   thorpej 		if (pn != NULL) {
   1448  1.115   thorpej 			KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   1449  1.115   thorpej 			swdpin = (uint16_t) prop_number_integer_value(pn);
   1450  1.115   thorpej 		} else {
   1451  1.113     gavan 			if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
   1452  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1453  1.160  christos 				    "unable to read SWDPIN\n");
   1454  1.113     gavan 				return;
   1455  1.113     gavan 			}
   1456   1.51   thorpej 		}
   1457   1.51   thorpej 	}
   1458    1.1   thorpej 
   1459    1.1   thorpej 	if (cfg1 & EEPROM_CFG1_ILOS)
   1460    1.1   thorpej 		sc->sc_ctrl |= CTRL_ILOS;
   1461   1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   1462    1.1   thorpej 		sc->sc_ctrl |=
   1463    1.1   thorpej 		    ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
   1464    1.1   thorpej 		    CTRL_SWDPIO_SHIFT;
   1465    1.1   thorpej 		sc->sc_ctrl |=
   1466    1.1   thorpej 		    ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
   1467    1.1   thorpej 		    CTRL_SWDPINS_SHIFT;
   1468    1.1   thorpej 	} else {
   1469    1.1   thorpej 		sc->sc_ctrl |=
   1470    1.1   thorpej 		    ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) <<
   1471    1.1   thorpej 		    CTRL_SWDPIO_SHIFT;
   1472    1.1   thorpej 	}
   1473    1.1   thorpej 
   1474    1.1   thorpej #if 0
   1475   1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   1476    1.1   thorpej 		if (cfg1 & EEPROM_CFG1_IPS0)
   1477    1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
   1478    1.1   thorpej 		if (cfg1 & EEPROM_CFG1_IPS1)
   1479    1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
   1480    1.1   thorpej 		sc->sc_ctrl_ext |=
   1481    1.1   thorpej 		    ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
   1482    1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
   1483    1.1   thorpej 		sc->sc_ctrl_ext |=
   1484    1.1   thorpej 		    ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
   1485    1.1   thorpej 		    CTRL_EXT_SWDPINS_SHIFT;
   1486    1.1   thorpej 	} else {
   1487    1.1   thorpej 		sc->sc_ctrl_ext |=
   1488    1.1   thorpej 		    ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) <<
   1489    1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
   1490    1.1   thorpej 	}
   1491    1.1   thorpej #endif
   1492    1.1   thorpej 
   1493    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   1494    1.1   thorpej #if 0
   1495    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   1496    1.1   thorpej #endif
   1497    1.1   thorpej 
   1498    1.1   thorpej 	/*
   1499    1.1   thorpej 	 * Set up some register offsets that are different between
   1500   1.11   thorpej 	 * the i82542 and the i82543 and later chips.
   1501    1.1   thorpej 	 */
   1502   1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
   1503    1.1   thorpej 		sc->sc_rdt_reg = WMREG_OLD_RDT0;
   1504    1.1   thorpej 		sc->sc_tdt_reg = WMREG_OLD_TDT;
   1505    1.1   thorpej 	} else {
   1506    1.1   thorpej 		sc->sc_rdt_reg = WMREG_RDT;
   1507    1.1   thorpej 		sc->sc_tdt_reg = WMREG_TDT;
   1508    1.1   thorpej 	}
   1509    1.1   thorpej 
   1510    1.1   thorpej 	/*
   1511    1.1   thorpej 	 * Determine if we're TBI or GMII mode, and initialize the
   1512    1.1   thorpej 	 * media structures accordingly.
   1513    1.1   thorpej 	 */
   1514  1.144   msaitoh 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
   1515  1.167   msaitoh 	    || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_82573
   1516  1.167   msaitoh 	    || sc->sc_type == WM_T_82574) {
   1517  1.139    bouyer 		/* STATUS_TBIMODE reserved/reused, can't rely on it */
   1518  1.139    bouyer 		wm_gmii_mediainit(sc);
   1519  1.139    bouyer 	} else if (sc->sc_type < WM_T_82543 ||
   1520    1.1   thorpej 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
   1521    1.1   thorpej 		if (wmp->wmp_flags & WMP_F_1000T)
   1522  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1523  1.160  christos 			    "WARNING: TBIMODE set on 1000BASE-T product!\n");
   1524    1.1   thorpej 		wm_tbi_mediainit(sc);
   1525    1.1   thorpej 	} else {
   1526    1.1   thorpej 		if (wmp->wmp_flags & WMP_F_1000X)
   1527  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1528  1.160  christos 			    "WARNING: TBIMODE clear on 1000BASE-X product!\n");
   1529    1.1   thorpej 		wm_gmii_mediainit(sc);
   1530    1.1   thorpej 	}
   1531    1.1   thorpej 
   1532    1.1   thorpej 	ifp = &sc->sc_ethercom.ec_if;
   1533  1.160  christos 	xname = device_xname(sc->sc_dev);
   1534  1.160  christos 	strlcpy(ifp->if_xname, xname, IFNAMSIZ);
   1535    1.1   thorpej 	ifp->if_softc = sc;
   1536    1.1   thorpej 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   1537    1.1   thorpej 	ifp->if_ioctl = wm_ioctl;
   1538    1.1   thorpej 	ifp->if_start = wm_start;
   1539    1.1   thorpej 	ifp->if_watchdog = wm_watchdog;
   1540    1.1   thorpej 	ifp->if_init = wm_init;
   1541    1.1   thorpej 	ifp->if_stop = wm_stop;
   1542   1.58     ragge 	IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
   1543    1.1   thorpej 	IFQ_SET_READY(&ifp->if_snd);
   1544    1.1   thorpej 
   1545  1.165  sborrill 	if (sc->sc_type != WM_T_82573 && sc->sc_type != WM_T_82574 &&
   1546  1.165  sborrill 	    sc->sc_type != WM_T_ICH8)
   1547  1.120   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   1548   1.41       tls 
   1549    1.1   thorpej 	/*
   1550   1.11   thorpej 	 * If we're a i82543 or greater, we can support VLANs.
   1551    1.1   thorpej 	 */
   1552   1.11   thorpej 	if (sc->sc_type >= WM_T_82543)
   1553    1.1   thorpej 		sc->sc_ethercom.ec_capabilities |=
   1554  1.172    darran 		    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
   1555    1.1   thorpej 
   1556    1.1   thorpej 	/*
   1557    1.1   thorpej 	 * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
   1558   1.11   thorpej 	 * on i82543 and later.
   1559    1.1   thorpej 	 */
   1560  1.130      yamt 	if (sc->sc_type >= WM_T_82543) {
   1561    1.1   thorpej 		ifp->if_capabilities |=
   1562  1.103      yamt 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
   1563  1.103      yamt 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   1564  1.107      yamt 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
   1565  1.107      yamt 		    IFCAP_CSUM_TCPv6_Tx |
   1566  1.107      yamt 		    IFCAP_CSUM_UDPv6_Tx;
   1567  1.130      yamt 	}
   1568  1.130      yamt 
   1569  1.130      yamt 	/*
   1570  1.130      yamt 	 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL.
   1571  1.130      yamt 	 *
   1572  1.130      yamt 	 *	82541GI (8086:1076) ... no
   1573  1.130      yamt 	 *	82572EI (8086:10b9) ... yes
   1574  1.130      yamt 	 */
   1575  1.130      yamt 	if (sc->sc_type >= WM_T_82571) {
   1576  1.130      yamt 		ifp->if_capabilities |=
   1577  1.130      yamt 		    IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
   1578  1.130      yamt 	}
   1579    1.1   thorpej 
   1580   1.99      matt 	/*
   1581   1.99      matt 	 * If we're a i82544 or greater (except i82547), we can do
   1582   1.99      matt 	 * TCP segmentation offload.
   1583   1.99      matt 	 */
   1584  1.131      yamt 	if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) {
   1585   1.99      matt 		ifp->if_capabilities |= IFCAP_TSOv4;
   1586  1.131      yamt 	}
   1587  1.131      yamt 
   1588  1.131      yamt 	if (sc->sc_type >= WM_T_82571) {
   1589  1.131      yamt 		ifp->if_capabilities |= IFCAP_TSOv6;
   1590  1.131      yamt 	}
   1591   1.99      matt 
   1592    1.1   thorpej 	/*
   1593    1.1   thorpej 	 * Attach the interface.
   1594    1.1   thorpej 	 */
   1595    1.1   thorpej 	if_attach(ifp);
   1596    1.1   thorpej 	ether_ifattach(ifp, enaddr);
   1597   1.21    itojun #if NRND > 0
   1598  1.160  christos 	rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 0);
   1599   1.21    itojun #endif
   1600    1.1   thorpej 
   1601    1.1   thorpej #ifdef WM_EVENT_COUNTERS
   1602    1.1   thorpej 	/* Attach event counters. */
   1603    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
   1604  1.160  christos 	    NULL, xname, "txsstall");
   1605    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
   1606  1.160  christos 	    NULL, xname, "txdstall");
   1607   1.78   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC,
   1608  1.160  christos 	    NULL, xname, "txfifo_stall");
   1609    1.4   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR,
   1610  1.160  christos 	    NULL, xname, "txdw");
   1611    1.4   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR,
   1612  1.160  christos 	    NULL, xname, "txqe");
   1613    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
   1614  1.160  christos 	    NULL, xname, "rxintr");
   1615    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
   1616  1.160  christos 	    NULL, xname, "linkintr");
   1617    1.1   thorpej 
   1618    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
   1619  1.160  christos 	    NULL, xname, "rxipsum");
   1620    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC,
   1621  1.160  christos 	    NULL, xname, "rxtusum");
   1622    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
   1623  1.160  christos 	    NULL, xname, "txipsum");
   1624    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC,
   1625  1.160  christos 	    NULL, xname, "txtusum");
   1626  1.107      yamt 	evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC,
   1627  1.160  christos 	    NULL, xname, "txtusum6");
   1628    1.1   thorpej 
   1629   1.99      matt 	evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC,
   1630  1.160  christos 	    NULL, xname, "txtso");
   1631  1.131      yamt 	evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC,
   1632  1.160  christos 	    NULL, xname, "txtso6");
   1633   1.99      matt 	evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC,
   1634  1.160  christos 	    NULL, xname, "txtsopain");
   1635   1.99      matt 
   1636   1.75   thorpej 	for (i = 0; i < WM_NTXSEGS; i++) {
   1637   1.75   thorpej 		sprintf(wm_txseg_evcnt_names[i], "txseg%d", i);
   1638    1.2   thorpej 		evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC,
   1639  1.160  christos 		    NULL, xname, wm_txseg_evcnt_names[i]);
   1640   1.75   thorpej 	}
   1641    1.2   thorpej 
   1642    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC,
   1643  1.160  christos 	    NULL, xname, "txdrop");
   1644    1.1   thorpej 
   1645    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC,
   1646  1.160  christos 	    NULL, xname, "tu");
   1647   1.71   thorpej 
   1648   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
   1649  1.160  christos 	    NULL, xname, "tx_xoff");
   1650   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
   1651  1.160  christos 	    NULL, xname, "tx_xon");
   1652   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
   1653  1.160  christos 	    NULL, xname, "rx_xoff");
   1654   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
   1655  1.160  christos 	    NULL, xname, "rx_xon");
   1656   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
   1657  1.160  christos 	    NULL, xname, "rx_macctl");
   1658    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
   1659    1.1   thorpej 
   1660  1.180   tsutsui 	if (pmf_device_register(self, NULL, NULL))
   1661  1.180   tsutsui 		pmf_class_network_register(self, ifp);
   1662  1.180   tsutsui 	else
   1663  1.149  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
   1664  1.123  jmcneill 
   1665    1.1   thorpej 	return;
   1666    1.1   thorpej 
   1667    1.1   thorpej 	/*
   1668    1.1   thorpej 	 * Free any resources we've allocated during the failed attach
   1669    1.1   thorpej 	 * attempt.  Do this in reverse order and fall through.
   1670    1.1   thorpej 	 */
   1671    1.1   thorpej  fail_5:
   1672    1.1   thorpej 	for (i = 0; i < WM_NRXDESC; i++) {
   1673    1.1   thorpej 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
   1674    1.1   thorpej 			bus_dmamap_destroy(sc->sc_dmat,
   1675    1.1   thorpej 			    sc->sc_rxsoft[i].rxs_dmamap);
   1676    1.1   thorpej 	}
   1677    1.1   thorpej  fail_4:
   1678   1.74      tron 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
   1679    1.1   thorpej 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
   1680    1.1   thorpej 			bus_dmamap_destroy(sc->sc_dmat,
   1681    1.1   thorpej 			    sc->sc_txsoft[i].txs_dmamap);
   1682    1.1   thorpej 	}
   1683    1.1   thorpej 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
   1684    1.1   thorpej  fail_3:
   1685    1.1   thorpej 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
   1686    1.1   thorpej  fail_2:
   1687  1.135  christos 	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
   1688   1.75   thorpej 	    cdata_size);
   1689    1.1   thorpej  fail_1:
   1690    1.1   thorpej 	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
   1691    1.1   thorpej  fail_0:
   1692    1.1   thorpej 	return;
   1693    1.1   thorpej }
   1694    1.1   thorpej 
   1695    1.1   thorpej /*
   1696   1.86   thorpej  * wm_tx_offload:
   1697    1.1   thorpej  *
   1698    1.1   thorpej  *	Set up TCP/IP checksumming parameters for the
   1699    1.1   thorpej  *	specified packet.
   1700    1.1   thorpej  */
   1701    1.1   thorpej static int
   1702   1.86   thorpej wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp,
   1703   1.65   tsutsui     uint8_t *fieldsp)
   1704    1.1   thorpej {
   1705    1.4   thorpej 	struct mbuf *m0 = txs->txs_mbuf;
   1706    1.1   thorpej 	struct livengood_tcpip_ctxdesc *t;
   1707   1.98   thorpej 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
   1708  1.131      yamt 	uint32_t ipcse;
   1709   1.13   thorpej 	struct ether_header *eh;
   1710    1.1   thorpej 	int offset, iphl;
   1711   1.98   thorpej 	uint8_t fields;
   1712    1.1   thorpej 
   1713    1.1   thorpej 	/*
   1714    1.1   thorpej 	 * XXX It would be nice if the mbuf pkthdr had offset
   1715    1.1   thorpej 	 * fields for the protocol headers.
   1716    1.1   thorpej 	 */
   1717    1.1   thorpej 
   1718   1.13   thorpej 	eh = mtod(m0, struct ether_header *);
   1719   1.13   thorpej 	switch (htons(eh->ether_type)) {
   1720   1.13   thorpej 	case ETHERTYPE_IP:
   1721  1.107      yamt 	case ETHERTYPE_IPV6:
   1722   1.13   thorpej 		offset = ETHER_HDR_LEN;
   1723   1.35   thorpej 		break;
   1724   1.35   thorpej 
   1725   1.35   thorpej 	case ETHERTYPE_VLAN:
   1726   1.35   thorpej 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   1727   1.13   thorpej 		break;
   1728   1.13   thorpej 
   1729   1.13   thorpej 	default:
   1730   1.13   thorpej 		/*
   1731   1.13   thorpej 		 * Don't support this protocol or encapsulation.
   1732   1.13   thorpej 		 */
   1733   1.13   thorpej 		*fieldsp = 0;
   1734   1.13   thorpej 		*cmdp = 0;
   1735   1.13   thorpej 		return (0);
   1736   1.13   thorpej 	}
   1737    1.1   thorpej 
   1738  1.107      yamt 	if ((m0->m_pkthdr.csum_flags &
   1739  1.107      yamt 	    (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) {
   1740  1.107      yamt 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   1741  1.107      yamt 	} else {
   1742  1.107      yamt 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
   1743  1.107      yamt 	}
   1744  1.131      yamt 	ipcse = offset + iphl - 1;
   1745    1.1   thorpej 
   1746   1.98   thorpej 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
   1747   1.98   thorpej 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
   1748   1.98   thorpej 	seg = 0;
   1749   1.98   thorpej 	fields = 0;
   1750   1.98   thorpej 
   1751  1.131      yamt 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
   1752   1.99      matt 		int hlen = offset + iphl;
   1753  1.132   thorpej 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   1754  1.131      yamt 
   1755   1.99      matt 		if (__predict_false(m0->m_len <
   1756   1.99      matt 				    (hlen + sizeof(struct tcphdr)))) {
   1757   1.99      matt 			/*
   1758   1.99      matt 			 * TCP/IP headers are not in the first mbuf; we need
   1759   1.99      matt 			 * to do this the slow and painful way.  Let's just
   1760   1.99      matt 			 * hope this doesn't happen very often.
   1761   1.99      matt 			 */
   1762   1.99      matt 			struct tcphdr th;
   1763   1.99      matt 
   1764   1.99      matt 			WM_EVCNT_INCR(&sc->sc_ev_txtsopain);
   1765   1.99      matt 
   1766   1.99      matt 			m_copydata(m0, hlen, sizeof(th), &th);
   1767  1.131      yamt 			if (v4) {
   1768  1.131      yamt 				struct ip ip;
   1769   1.99      matt 
   1770  1.131      yamt 				m_copydata(m0, offset, sizeof(ip), &ip);
   1771  1.131      yamt 				ip.ip_len = 0;
   1772  1.131      yamt 				m_copyback(m0,
   1773  1.131      yamt 				    offset + offsetof(struct ip, ip_len),
   1774  1.131      yamt 				    sizeof(ip.ip_len), &ip.ip_len);
   1775  1.131      yamt 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   1776  1.131      yamt 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   1777  1.131      yamt 			} else {
   1778  1.131      yamt 				struct ip6_hdr ip6;
   1779   1.99      matt 
   1780  1.131      yamt 				m_copydata(m0, offset, sizeof(ip6), &ip6);
   1781  1.131      yamt 				ip6.ip6_plen = 0;
   1782  1.131      yamt 				m_copyback(m0,
   1783  1.131      yamt 				    offset + offsetof(struct ip6_hdr, ip6_plen),
   1784  1.131      yamt 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
   1785  1.131      yamt 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
   1786  1.131      yamt 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
   1787  1.131      yamt 			}
   1788   1.99      matt 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   1789   1.99      matt 			    sizeof(th.th_sum), &th.th_sum);
   1790   1.99      matt 
   1791   1.99      matt 			hlen += th.th_off << 2;
   1792   1.99      matt 		} else {
   1793   1.99      matt 			/*
   1794   1.99      matt 			 * TCP/IP headers are in the first mbuf; we can do
   1795   1.99      matt 			 * this the easy way.
   1796   1.99      matt 			 */
   1797  1.131      yamt 			struct tcphdr *th;
   1798   1.99      matt 
   1799  1.131      yamt 			if (v4) {
   1800  1.131      yamt 				struct ip *ip =
   1801  1.135  christos 				    (void *)(mtod(m0, char *) + offset);
   1802  1.135  christos 				th = (void *)(mtod(m0, char *) + hlen);
   1803  1.131      yamt 
   1804  1.131      yamt 				ip->ip_len = 0;
   1805  1.131      yamt 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   1806  1.131      yamt 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   1807  1.131      yamt 			} else {
   1808  1.131      yamt 				struct ip6_hdr *ip6 =
   1809  1.131      yamt 				    (void *)(mtod(m0, char *) + offset);
   1810  1.131      yamt 				th = (void *)(mtod(m0, char *) + hlen);
   1811  1.131      yamt 
   1812  1.131      yamt 				ip6->ip6_plen = 0;
   1813  1.131      yamt 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
   1814  1.131      yamt 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
   1815  1.131      yamt 			}
   1816   1.99      matt 			hlen += th->th_off << 2;
   1817   1.99      matt 		}
   1818   1.99      matt 
   1819  1.131      yamt 		if (v4) {
   1820  1.131      yamt 			WM_EVCNT_INCR(&sc->sc_ev_txtso);
   1821  1.131      yamt 			cmdlen |= WTX_TCPIP_CMD_IP;
   1822  1.131      yamt 		} else {
   1823  1.131      yamt 			WM_EVCNT_INCR(&sc->sc_ev_txtso6);
   1824  1.131      yamt 			ipcse = 0;
   1825  1.131      yamt 		}
   1826   1.99      matt 		cmd |= WTX_TCPIP_CMD_TSE;
   1827  1.131      yamt 		cmdlen |= WTX_TCPIP_CMD_TSE |
   1828   1.99      matt 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
   1829   1.99      matt 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
   1830   1.99      matt 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
   1831   1.99      matt 	}
   1832   1.99      matt 
   1833   1.13   thorpej 	/*
   1834   1.13   thorpej 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
   1835   1.13   thorpej 	 * offload feature, if we load the context descriptor, we
   1836   1.13   thorpej 	 * MUST provide valid values for IPCSS and TUCSS fields.
   1837   1.13   thorpej 	 */
   1838   1.13   thorpej 
   1839   1.87   thorpej 	ipcs = WTX_TCPIP_IPCSS(offset) |
   1840   1.87   thorpej 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
   1841  1.131      yamt 	    WTX_TCPIP_IPCSE(ipcse);
   1842   1.99      matt 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) {
   1843    1.1   thorpej 		WM_EVCNT_INCR(&sc->sc_ev_txipsum);
   1844   1.65   tsutsui 		fields |= WTX_IXSM;
   1845   1.13   thorpej 	}
   1846    1.1   thorpej 
   1847    1.1   thorpej 	offset += iphl;
   1848    1.1   thorpej 
   1849   1.99      matt 	if (m0->m_pkthdr.csum_flags &
   1850   1.99      matt 	    (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) {
   1851    1.1   thorpej 		WM_EVCNT_INCR(&sc->sc_ev_txtusum);
   1852   1.65   tsutsui 		fields |= WTX_TXSM;
   1853   1.65   tsutsui 		tucs = WTX_TCPIP_TUCSS(offset) |
   1854  1.107      yamt 		    WTX_TCPIP_TUCSO(offset +
   1855  1.107      yamt 		    M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
   1856  1.107      yamt 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   1857  1.107      yamt 	} else if ((m0->m_pkthdr.csum_flags &
   1858  1.131      yamt 	    (M_CSUM_TCPv6|M_CSUM_UDPv6|M_CSUM_TSOv6)) != 0) {
   1859  1.107      yamt 		WM_EVCNT_INCR(&sc->sc_ev_txtusum6);
   1860  1.107      yamt 		fields |= WTX_TXSM;
   1861  1.107      yamt 		tucs = WTX_TCPIP_TUCSS(offset) |
   1862  1.107      yamt 		    WTX_TCPIP_TUCSO(offset +
   1863  1.107      yamt 		    M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
   1864  1.107      yamt 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   1865   1.13   thorpej 	} else {
   1866   1.13   thorpej 		/* Just initialize it to a valid TCP context. */
   1867   1.65   tsutsui 		tucs = WTX_TCPIP_TUCSS(offset) |
   1868   1.13   thorpej 		    WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
   1869   1.65   tsutsui 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   1870   1.13   thorpej 	}
   1871    1.1   thorpej 
   1872   1.87   thorpej 	/* Fill in the context descriptor. */
   1873   1.87   thorpej 	t = (struct livengood_tcpip_ctxdesc *)
   1874   1.87   thorpej 	    &sc->sc_txdescs[sc->sc_txnext];
   1875   1.87   thorpej 	t->tcpip_ipcs = htole32(ipcs);
   1876   1.87   thorpej 	t->tcpip_tucs = htole32(tucs);
   1877   1.98   thorpej 	t->tcpip_cmdlen = htole32(cmdlen);
   1878   1.98   thorpej 	t->tcpip_seg = htole32(seg);
   1879   1.87   thorpej 	WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE);
   1880    1.5   thorpej 
   1881   1.87   thorpej 	sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext);
   1882   1.87   thorpej 	txs->txs_ndesc++;
   1883    1.1   thorpej 
   1884   1.98   thorpej 	*cmdp = cmd;
   1885    1.1   thorpej 	*fieldsp = fields;
   1886    1.1   thorpej 
   1887    1.1   thorpej 	return (0);
   1888    1.1   thorpej }
   1889    1.1   thorpej 
   1890   1.75   thorpej static void
   1891   1.75   thorpej wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
   1892   1.75   thorpej {
   1893   1.75   thorpej 	struct mbuf *m;
   1894   1.75   thorpej 	int i;
   1895   1.75   thorpej 
   1896  1.160  christos 	log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev));
   1897   1.75   thorpej 	for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
   1898   1.84   thorpej 		log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
   1899  1.160  christos 		    "m_flags = 0x%08x\n", device_xname(sc->sc_dev),
   1900   1.75   thorpej 		    m->m_data, m->m_len, m->m_flags);
   1901  1.160  christos 	log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev),
   1902   1.84   thorpej 	    i, i == 1 ? "" : "s");
   1903   1.75   thorpej }
   1904   1.75   thorpej 
   1905    1.1   thorpej /*
   1906   1.78   thorpej  * wm_82547_txfifo_stall:
   1907   1.78   thorpej  *
   1908   1.78   thorpej  *	Callout used to wait for the 82547 Tx FIFO to drain,
   1909   1.78   thorpej  *	reset the FIFO pointers, and restart packet transmission.
   1910   1.78   thorpej  */
   1911   1.78   thorpej static void
   1912   1.78   thorpej wm_82547_txfifo_stall(void *arg)
   1913   1.78   thorpej {
   1914   1.78   thorpej 	struct wm_softc *sc = arg;
   1915   1.78   thorpej 	int s;
   1916   1.78   thorpej 
   1917   1.78   thorpej 	s = splnet();
   1918   1.78   thorpej 
   1919   1.78   thorpej 	if (sc->sc_txfifo_stall) {
   1920   1.78   thorpej 		if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) &&
   1921   1.78   thorpej 		    CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
   1922   1.78   thorpej 		    CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
   1923   1.78   thorpej 			/*
   1924   1.78   thorpej 			 * Packets have drained.  Stop transmitter, reset
   1925   1.78   thorpej 			 * FIFO pointers, restart transmitter, and kick
   1926   1.78   thorpej 			 * the packet queue.
   1927   1.78   thorpej 			 */
   1928   1.78   thorpej 			uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
   1929   1.78   thorpej 			CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
   1930   1.78   thorpej 			CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr);
   1931   1.78   thorpej 			CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr);
   1932   1.78   thorpej 			CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr);
   1933   1.78   thorpej 			CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr);
   1934   1.78   thorpej 			CSR_WRITE(sc, WMREG_TCTL, tctl);
   1935   1.78   thorpej 			CSR_WRITE_FLUSH(sc);
   1936   1.78   thorpej 
   1937   1.78   thorpej 			sc->sc_txfifo_head = 0;
   1938   1.78   thorpej 			sc->sc_txfifo_stall = 0;
   1939   1.78   thorpej 			wm_start(&sc->sc_ethercom.ec_if);
   1940   1.78   thorpej 		} else {
   1941   1.78   thorpej 			/*
   1942   1.78   thorpej 			 * Still waiting for packets to drain; try again in
   1943   1.78   thorpej 			 * another tick.
   1944   1.78   thorpej 			 */
   1945   1.78   thorpej 			callout_schedule(&sc->sc_txfifo_ch, 1);
   1946   1.78   thorpej 		}
   1947   1.78   thorpej 	}
   1948   1.78   thorpej 
   1949   1.78   thorpej 	splx(s);
   1950   1.78   thorpej }
   1951   1.78   thorpej 
   1952   1.78   thorpej /*
   1953   1.78   thorpej  * wm_82547_txfifo_bugchk:
   1954   1.78   thorpej  *
   1955   1.78   thorpej  *	Check for bug condition in the 82547 Tx FIFO.  We need to
   1956   1.78   thorpej  *	prevent enqueueing a packet that would wrap around the end
   1957   1.78   thorpej  *	if the Tx FIFO ring buffer, otherwise the chip will croak.
   1958   1.78   thorpej  *
   1959   1.78   thorpej  *	We do this by checking the amount of space before the end
   1960   1.78   thorpej  *	of the Tx FIFO buffer.  If the packet will not fit, we "stall"
   1961   1.78   thorpej  *	the Tx FIFO, wait for all remaining packets to drain, reset
   1962   1.78   thorpej  *	the internal FIFO pointers to the beginning, and restart
   1963   1.78   thorpej  *	transmission on the interface.
   1964   1.78   thorpej  */
   1965   1.78   thorpej #define	WM_FIFO_HDR		0x10
   1966   1.78   thorpej #define	WM_82547_PAD_LEN	0x3e0
   1967   1.78   thorpej static int
   1968   1.78   thorpej wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
   1969   1.78   thorpej {
   1970   1.78   thorpej 	int space = sc->sc_txfifo_size - sc->sc_txfifo_head;
   1971   1.78   thorpej 	int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
   1972   1.78   thorpej 
   1973   1.78   thorpej 	/* Just return if already stalled. */
   1974   1.78   thorpej 	if (sc->sc_txfifo_stall)
   1975   1.78   thorpej 		return (1);
   1976   1.78   thorpej 
   1977   1.78   thorpej 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   1978   1.78   thorpej 		/* Stall only occurs in half-duplex mode. */
   1979   1.78   thorpej 		goto send_packet;
   1980   1.78   thorpej 	}
   1981   1.78   thorpej 
   1982   1.78   thorpej 	if (len >= WM_82547_PAD_LEN + space) {
   1983   1.78   thorpej 		sc->sc_txfifo_stall = 1;
   1984   1.78   thorpej 		callout_schedule(&sc->sc_txfifo_ch, 1);
   1985   1.78   thorpej 		return (1);
   1986   1.78   thorpej 	}
   1987   1.78   thorpej 
   1988   1.78   thorpej  send_packet:
   1989   1.78   thorpej 	sc->sc_txfifo_head += len;
   1990   1.78   thorpej 	if (sc->sc_txfifo_head >= sc->sc_txfifo_size)
   1991   1.78   thorpej 		sc->sc_txfifo_head -= sc->sc_txfifo_size;
   1992   1.78   thorpej 
   1993   1.78   thorpej 	return (0);
   1994   1.78   thorpej }
   1995   1.78   thorpej 
   1996   1.78   thorpej /*
   1997    1.1   thorpej  * wm_start:		[ifnet interface function]
   1998    1.1   thorpej  *
   1999    1.1   thorpej  *	Start packet transmission on the interface.
   2000    1.1   thorpej  */
   2001   1.47   thorpej static void
   2002    1.1   thorpej wm_start(struct ifnet *ifp)
   2003    1.1   thorpej {
   2004    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   2005   1.30    itojun 	struct mbuf *m0;
   2006   1.30    itojun 	struct m_tag *mtag;
   2007    1.1   thorpej 	struct wm_txsoft *txs;
   2008    1.1   thorpej 	bus_dmamap_t dmamap;
   2009   1.99      matt 	int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
   2010   1.80   thorpej 	bus_addr_t curaddr;
   2011   1.80   thorpej 	bus_size_t seglen, curlen;
   2012   1.65   tsutsui 	uint32_t cksumcmd;
   2013   1.65   tsutsui 	uint8_t cksumfields;
   2014    1.1   thorpej 
   2015    1.1   thorpej 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
   2016    1.1   thorpej 		return;
   2017    1.1   thorpej 
   2018    1.1   thorpej 	/*
   2019    1.1   thorpej 	 * Remember the previous number of free descriptors.
   2020    1.1   thorpej 	 */
   2021    1.1   thorpej 	ofree = sc->sc_txfree;
   2022    1.1   thorpej 
   2023    1.1   thorpej 	/*
   2024    1.1   thorpej 	 * Loop through the send queue, setting up transmit descriptors
   2025    1.1   thorpej 	 * until we drain the queue, or use up all available transmit
   2026    1.1   thorpej 	 * descriptors.
   2027    1.1   thorpej 	 */
   2028    1.1   thorpej 	for (;;) {
   2029    1.1   thorpej 		/* Grab a packet off the queue. */
   2030    1.1   thorpej 		IFQ_POLL(&ifp->if_snd, m0);
   2031    1.1   thorpej 		if (m0 == NULL)
   2032    1.1   thorpej 			break;
   2033    1.1   thorpej 
   2034    1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   2035    1.1   thorpej 		    ("%s: TX: have packet to transmit: %p\n",
   2036  1.160  christos 		    device_xname(sc->sc_dev), m0));
   2037    1.1   thorpej 
   2038    1.1   thorpej 		/* Get a work queue entry. */
   2039   1.74      tron 		if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) {
   2040   1.10   thorpej 			wm_txintr(sc);
   2041   1.10   thorpej 			if (sc->sc_txsfree == 0) {
   2042   1.10   thorpej 				DPRINTF(WM_DEBUG_TX,
   2043   1.10   thorpej 				    ("%s: TX: no free job descriptors\n",
   2044  1.160  christos 					device_xname(sc->sc_dev)));
   2045   1.10   thorpej 				WM_EVCNT_INCR(&sc->sc_ev_txsstall);
   2046   1.10   thorpej 				break;
   2047   1.10   thorpej 			}
   2048    1.1   thorpej 		}
   2049    1.1   thorpej 
   2050    1.1   thorpej 		txs = &sc->sc_txsoft[sc->sc_txsnext];
   2051    1.1   thorpej 		dmamap = txs->txs_dmamap;
   2052    1.1   thorpej 
   2053  1.131      yamt 		use_tso = (m0->m_pkthdr.csum_flags &
   2054  1.131      yamt 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0;
   2055   1.99      matt 
   2056   1.99      matt 		/*
   2057   1.99      matt 		 * So says the Linux driver:
   2058   1.99      matt 		 * The controller does a simple calculation to make sure
   2059   1.99      matt 		 * there is enough room in the FIFO before initiating the
   2060   1.99      matt 		 * DMA for each buffer.  The calc is:
   2061   1.99      matt 		 *	4 = ceil(buffer len / MSS)
   2062   1.99      matt 		 * To make sure we don't overrun the FIFO, adjust the max
   2063   1.99      matt 		 * buffer len if the MSS drops.
   2064   1.99      matt 		 */
   2065   1.99      matt 		dmamap->dm_maxsegsz =
   2066   1.99      matt 		    (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
   2067   1.99      matt 		    ? m0->m_pkthdr.segsz << 2
   2068   1.99      matt 		    : WTX_MAX_LEN;
   2069   1.99      matt 
   2070    1.1   thorpej 		/*
   2071    1.1   thorpej 		 * Load the DMA map.  If this fails, the packet either
   2072    1.1   thorpej 		 * didn't fit in the allotted number of segments, or we
   2073    1.1   thorpej 		 * were short on resources.  For the too-many-segments
   2074    1.1   thorpej 		 * case, we simply report an error and drop the packet,
   2075    1.1   thorpej 		 * since we can't sanely copy a jumbo packet to a single
   2076    1.1   thorpej 		 * buffer.
   2077    1.1   thorpej 		 */
   2078    1.1   thorpej 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   2079    1.1   thorpej 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT);
   2080    1.1   thorpej 		if (error) {
   2081    1.1   thorpej 			if (error == EFBIG) {
   2082    1.1   thorpej 				WM_EVCNT_INCR(&sc->sc_ev_txdrop);
   2083   1.84   thorpej 				log(LOG_ERR, "%s: Tx packet consumes too many "
   2084    1.1   thorpej 				    "DMA segments, dropping...\n",
   2085  1.160  christos 				    device_xname(sc->sc_dev));
   2086    1.1   thorpej 				IFQ_DEQUEUE(&ifp->if_snd, m0);
   2087   1.75   thorpej 				wm_dump_mbuf_chain(sc, m0);
   2088    1.1   thorpej 				m_freem(m0);
   2089    1.1   thorpej 				continue;
   2090    1.1   thorpej 			}
   2091    1.1   thorpej 			/*
   2092    1.1   thorpej 			 * Short on resources, just stop for now.
   2093    1.1   thorpej 			 */
   2094    1.1   thorpej 			DPRINTF(WM_DEBUG_TX,
   2095    1.1   thorpej 			    ("%s: TX: dmamap load failed: %d\n",
   2096  1.160  christos 			    device_xname(sc->sc_dev), error));
   2097    1.1   thorpej 			break;
   2098    1.1   thorpej 		}
   2099    1.1   thorpej 
   2100   1.80   thorpej 		segs_needed = dmamap->dm_nsegs;
   2101   1.99      matt 		if (use_tso) {
   2102   1.99      matt 			/* For sentinel descriptor; see below. */
   2103   1.99      matt 			segs_needed++;
   2104   1.99      matt 		}
   2105   1.80   thorpej 
   2106    1.1   thorpej 		/*
   2107    1.1   thorpej 		 * Ensure we have enough descriptors free to describe
   2108    1.1   thorpej 		 * the packet.  Note, we always reserve one descriptor
   2109    1.1   thorpej 		 * at the end of the ring due to the semantics of the
   2110    1.1   thorpej 		 * TDT register, plus one more in the event we need
   2111   1.87   thorpej 		 * to load offload context.
   2112    1.1   thorpej 		 */
   2113   1.80   thorpej 		if (segs_needed > sc->sc_txfree - 2) {
   2114    1.1   thorpej 			/*
   2115    1.1   thorpej 			 * Not enough free descriptors to transmit this
   2116    1.1   thorpej 			 * packet.  We haven't committed anything yet,
   2117    1.1   thorpej 			 * so just unload the DMA map, put the packet
   2118    1.1   thorpej 			 * pack on the queue, and punt.  Notify the upper
   2119    1.1   thorpej 			 * layer that there are no more slots left.
   2120    1.1   thorpej 			 */
   2121    1.1   thorpej 			DPRINTF(WM_DEBUG_TX,
   2122  1.104      ross 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
   2123  1.160  christos 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
   2124  1.160  christos 			    segs_needed, sc->sc_txfree - 1));
   2125    1.1   thorpej 			ifp->if_flags |= IFF_OACTIVE;
   2126    1.1   thorpej 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   2127    1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_txdstall);
   2128    1.1   thorpej 			break;
   2129    1.1   thorpej 		}
   2130    1.1   thorpej 
   2131   1.78   thorpej 		/*
   2132   1.78   thorpej 		 * Check for 82547 Tx FIFO bug.  We need to do this
   2133   1.78   thorpej 		 * once we know we can transmit the packet, since we
   2134   1.78   thorpej 		 * do some internal FIFO space accounting here.
   2135   1.78   thorpej 		 */
   2136   1.78   thorpej 		if (sc->sc_type == WM_T_82547 &&
   2137   1.78   thorpej 		    wm_82547_txfifo_bugchk(sc, m0)) {
   2138   1.78   thorpej 			DPRINTF(WM_DEBUG_TX,
   2139   1.78   thorpej 			    ("%s: TX: 82547 Tx FIFO bug detected\n",
   2140  1.160  christos 			    device_xname(sc->sc_dev)));
   2141   1.78   thorpej 			ifp->if_flags |= IFF_OACTIVE;
   2142   1.78   thorpej 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   2143   1.78   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall);
   2144   1.78   thorpej 			break;
   2145   1.78   thorpej 		}
   2146   1.78   thorpej 
   2147    1.1   thorpej 		IFQ_DEQUEUE(&ifp->if_snd, m0);
   2148    1.1   thorpej 
   2149    1.1   thorpej 		/*
   2150    1.1   thorpej 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
   2151    1.1   thorpej 		 */
   2152    1.1   thorpej 
   2153    1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   2154   1.80   thorpej 		    ("%s: TX: packet has %d (%d) DMA segments\n",
   2155  1.160  christos 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
   2156    1.1   thorpej 
   2157    1.2   thorpej 		WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]);
   2158    1.1   thorpej 
   2159    1.1   thorpej 		/*
   2160    1.4   thorpej 		 * Store a pointer to the packet so that we can free it
   2161    1.4   thorpej 		 * later.
   2162    1.4   thorpej 		 *
   2163    1.4   thorpej 		 * Initially, we consider the number of descriptors the
   2164    1.4   thorpej 		 * packet uses the number of DMA segments.  This may be
   2165    1.4   thorpej 		 * incremented by 1 if we do checksum offload (a descriptor
   2166    1.4   thorpej 		 * is used to set the checksum context).
   2167    1.4   thorpej 		 */
   2168    1.4   thorpej 		txs->txs_mbuf = m0;
   2169    1.6   thorpej 		txs->txs_firstdesc = sc->sc_txnext;
   2170   1.80   thorpej 		txs->txs_ndesc = segs_needed;
   2171    1.4   thorpej 
   2172   1.86   thorpej 		/* Set up offload parameters for this packet. */
   2173    1.1   thorpej 		if (m0->m_pkthdr.csum_flags &
   2174  1.131      yamt 		    (M_CSUM_TSOv4|M_CSUM_TSOv6|
   2175  1.131      yamt 		    M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
   2176  1.107      yamt 		    M_CSUM_TCPv6|M_CSUM_UDPv6)) {
   2177   1.86   thorpej 			if (wm_tx_offload(sc, txs, &cksumcmd,
   2178   1.86   thorpej 					  &cksumfields) != 0) {
   2179    1.1   thorpej 				/* Error message already displayed. */
   2180    1.1   thorpej 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   2181    1.1   thorpej 				continue;
   2182    1.1   thorpej 			}
   2183    1.1   thorpej 		} else {
   2184    1.1   thorpej 			cksumcmd = 0;
   2185    1.1   thorpej 			cksumfields = 0;
   2186    1.1   thorpej 		}
   2187    1.1   thorpej 
   2188   1.98   thorpej 		cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
   2189    1.6   thorpej 
   2190   1.81   thorpej 		/* Sync the DMA map. */
   2191   1.81   thorpej 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   2192   1.81   thorpej 		    BUS_DMASYNC_PREWRITE);
   2193   1.81   thorpej 
   2194    1.1   thorpej 		/*
   2195    1.1   thorpej 		 * Initialize the transmit descriptor.
   2196    1.1   thorpej 		 */
   2197    1.1   thorpej 		for (nexttx = sc->sc_txnext, seg = 0;
   2198   1.80   thorpej 		     seg < dmamap->dm_nsegs; seg++) {
   2199   1.80   thorpej 			for (seglen = dmamap->dm_segs[seg].ds_len,
   2200   1.80   thorpej 			     curaddr = dmamap->dm_segs[seg].ds_addr;
   2201   1.80   thorpej 			     seglen != 0;
   2202   1.80   thorpej 			     curaddr += curlen, seglen -= curlen,
   2203   1.80   thorpej 			     nexttx = WM_NEXTTX(sc, nexttx)) {
   2204   1.80   thorpej 				curlen = seglen;
   2205   1.80   thorpej 
   2206   1.99      matt 				/*
   2207   1.99      matt 				 * So says the Linux driver:
   2208   1.99      matt 				 * Work around for premature descriptor
   2209   1.99      matt 				 * write-backs in TSO mode.  Append a
   2210   1.99      matt 				 * 4-byte sentinel descriptor.
   2211   1.99      matt 				 */
   2212   1.99      matt 				if (use_tso &&
   2213   1.99      matt 				    seg == dmamap->dm_nsegs - 1 &&
   2214   1.99      matt 				    curlen > 8)
   2215   1.99      matt 					curlen -= 4;
   2216   1.99      matt 
   2217   1.80   thorpej 				wm_set_dma_addr(
   2218   1.80   thorpej 				    &sc->sc_txdescs[nexttx].wtx_addr,
   2219   1.80   thorpej 				    curaddr);
   2220   1.80   thorpej 				sc->sc_txdescs[nexttx].wtx_cmdlen =
   2221   1.80   thorpej 				    htole32(cksumcmd | curlen);
   2222   1.80   thorpej 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_status =
   2223   1.80   thorpej 				    0;
   2224   1.80   thorpej 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_options =
   2225   1.80   thorpej 				    cksumfields;
   2226   1.80   thorpej 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0;
   2227   1.80   thorpej 				lasttx = nexttx;
   2228    1.1   thorpej 
   2229   1.80   thorpej 				DPRINTF(WM_DEBUG_TX,
   2230  1.104      ross 				    ("%s: TX: desc %d: low 0x%08lx, "
   2231   1.80   thorpej 				     "len 0x%04x\n",
   2232  1.160  christos 				    device_xname(sc->sc_dev), nexttx,
   2233  1.104      ross 				    curaddr & 0xffffffffUL, (unsigned)curlen));
   2234   1.80   thorpej 			}
   2235    1.1   thorpej 		}
   2236   1.59  christos 
   2237   1.59  christos 		KASSERT(lasttx != -1);
   2238    1.1   thorpej 
   2239    1.1   thorpej 		/*
   2240    1.1   thorpej 		 * Set up the command byte on the last descriptor of
   2241    1.1   thorpej 		 * the packet.  If we're in the interrupt delay window,
   2242    1.1   thorpej 		 * delay the interrupt.
   2243    1.1   thorpej 		 */
   2244    1.1   thorpej 		sc->sc_txdescs[lasttx].wtx_cmdlen |=
   2245   1.98   thorpej 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
   2246    1.1   thorpej 
   2247    1.1   thorpej 		/*
   2248    1.1   thorpej 		 * If VLANs are enabled and the packet has a VLAN tag, set
   2249    1.1   thorpej 		 * up the descriptor to encapsulate the packet for us.
   2250    1.1   thorpej 		 *
   2251    1.1   thorpej 		 * This is only valid on the last descriptor of the packet.
   2252    1.1   thorpej 		 */
   2253   1.94  jdolecek 		if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
   2254    1.1   thorpej 			sc->sc_txdescs[lasttx].wtx_cmdlen |=
   2255    1.1   thorpej 			    htole32(WTX_CMD_VLE);
   2256   1.65   tsutsui 			sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan
   2257   1.94  jdolecek 			    = htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
   2258    1.1   thorpej 		}
   2259    1.1   thorpej 
   2260    1.6   thorpej 		txs->txs_lastdesc = lasttx;
   2261    1.6   thorpej 
   2262    1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   2263  1.160  christos 		    ("%s: TX: desc %d: cmdlen 0x%08x\n",
   2264  1.160  christos 		    device_xname(sc->sc_dev),
   2265   1.65   tsutsui 		    lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen)));
   2266    1.1   thorpej 
   2267    1.1   thorpej 		/* Sync the descriptors we're using. */
   2268   1.80   thorpej 		WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc,
   2269    1.1   thorpej 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   2270    1.1   thorpej 
   2271    1.1   thorpej 		/* Give the packet to the chip. */
   2272    1.1   thorpej 		CSR_WRITE(sc, sc->sc_tdt_reg, nexttx);
   2273    1.1   thorpej 
   2274    1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   2275  1.160  christos 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
   2276    1.1   thorpej 
   2277    1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   2278    1.1   thorpej 		    ("%s: TX: finished transmitting packet, job %d\n",
   2279  1.160  christos 		    device_xname(sc->sc_dev), sc->sc_txsnext));
   2280    1.1   thorpej 
   2281    1.1   thorpej 		/* Advance the tx pointer. */
   2282    1.4   thorpej 		sc->sc_txfree -= txs->txs_ndesc;
   2283    1.1   thorpej 		sc->sc_txnext = nexttx;
   2284    1.1   thorpej 
   2285    1.1   thorpej 		sc->sc_txsfree--;
   2286   1.74      tron 		sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext);
   2287    1.1   thorpej 
   2288    1.1   thorpej #if NBPFILTER > 0
   2289    1.1   thorpej 		/* Pass the packet to any BPF listeners. */
   2290    1.1   thorpej 		if (ifp->if_bpf)
   2291    1.1   thorpej 			bpf_mtap(ifp->if_bpf, m0);
   2292    1.1   thorpej #endif /* NBPFILTER > 0 */
   2293    1.1   thorpej 	}
   2294    1.1   thorpej 
   2295    1.6   thorpej 	if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) {
   2296    1.1   thorpej 		/* No more slots; notify upper layer. */
   2297    1.1   thorpej 		ifp->if_flags |= IFF_OACTIVE;
   2298    1.1   thorpej 	}
   2299    1.1   thorpej 
   2300    1.1   thorpej 	if (sc->sc_txfree != ofree) {
   2301    1.1   thorpej 		/* Set a watchdog timer in case the chip flakes out. */
   2302    1.1   thorpej 		ifp->if_timer = 5;
   2303    1.1   thorpej 	}
   2304    1.1   thorpej }
   2305    1.1   thorpej 
   2306    1.1   thorpej /*
   2307    1.1   thorpej  * wm_watchdog:		[ifnet interface function]
   2308    1.1   thorpej  *
   2309    1.1   thorpej  *	Watchdog timer handler.
   2310    1.1   thorpej  */
   2311   1.47   thorpej static void
   2312    1.1   thorpej wm_watchdog(struct ifnet *ifp)
   2313    1.1   thorpej {
   2314    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   2315    1.1   thorpej 
   2316    1.1   thorpej 	/*
   2317    1.1   thorpej 	 * Since we're using delayed interrupts, sweep up
   2318    1.1   thorpej 	 * before we report an error.
   2319    1.1   thorpej 	 */
   2320    1.1   thorpej 	wm_txintr(sc);
   2321    1.1   thorpej 
   2322   1.75   thorpej 	if (sc->sc_txfree != WM_NTXDESC(sc)) {
   2323   1.84   thorpej 		log(LOG_ERR,
   2324   1.84   thorpej 		    "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
   2325  1.160  christos 		    device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree,
   2326    1.2   thorpej 		    sc->sc_txnext);
   2327    1.1   thorpej 		ifp->if_oerrors++;
   2328    1.1   thorpej 
   2329    1.1   thorpej 		/* Reset the interface. */
   2330    1.1   thorpej 		(void) wm_init(ifp);
   2331    1.1   thorpej 	}
   2332    1.1   thorpej 
   2333    1.1   thorpej 	/* Try to get more packets going. */
   2334    1.1   thorpej 	wm_start(ifp);
   2335    1.1   thorpej }
   2336    1.1   thorpej 
   2337    1.1   thorpej /*
   2338    1.1   thorpej  * wm_ioctl:		[ifnet interface function]
   2339    1.1   thorpej  *
   2340    1.1   thorpej  *	Handle control requests from the operator.
   2341    1.1   thorpej  */
   2342   1.47   thorpej static int
   2343  1.135  christos wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
   2344    1.1   thorpej {
   2345    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   2346    1.1   thorpej 	struct ifreq *ifr = (struct ifreq *) data;
   2347  1.175    darran 	struct ifaddr *ifa = (struct ifaddr *)data;
   2348  1.175    darran 	struct sockaddr_dl *sdl;
   2349  1.179   msaitoh 	int diff, s, error;
   2350    1.1   thorpej 
   2351    1.1   thorpej 	s = splnet();
   2352    1.1   thorpej 
   2353    1.1   thorpej 	switch (cmd) {
   2354  1.179   msaitoh 	case SIOCSIFFLAGS:
   2355  1.179   msaitoh 		if ((error = ifioctl_common(ifp, cmd, data)) != 0)
   2356  1.179   msaitoh 			break;
   2357  1.179   msaitoh 		if (ifp->if_flags & IFF_UP) {
   2358  1.179   msaitoh 			diff = (ifp->if_flags ^ sc->sc_if_flags)
   2359  1.179   msaitoh 			    & (IFF_PROMISC | IFF_ALLMULTI);
   2360  1.179   msaitoh 			if ((diff & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
   2361  1.179   msaitoh 				/*
   2362  1.179   msaitoh 				 * If the difference bettween last flag and
   2363  1.179   msaitoh 				 * new flag is only IFF_PROMISC or
   2364  1.179   msaitoh 				 * IFF_ALLMULTI, set multicast filter only
   2365  1.179   msaitoh 				 * (don't reset to prevent link down).
   2366  1.179   msaitoh 				 */
   2367  1.179   msaitoh 				wm_set_filter(sc);
   2368  1.179   msaitoh 			} else {
   2369  1.179   msaitoh 				/*
   2370  1.179   msaitoh 				 * Reset the interface to pick up changes in
   2371  1.179   msaitoh 				 * any other flags that affect the hardware
   2372  1.179   msaitoh 				 * state.
   2373  1.179   msaitoh 				 */
   2374  1.179   msaitoh 				wm_init(ifp);
   2375  1.179   msaitoh 			}
   2376  1.179   msaitoh 		} else {
   2377  1.179   msaitoh 			if (ifp->if_flags & IFF_RUNNING)
   2378  1.179   msaitoh 				wm_stop(ifp, 1);
   2379  1.179   msaitoh 		}
   2380  1.179   msaitoh 		sc->sc_if_flags = ifp->if_flags;
   2381  1.179   msaitoh 		error = 0;
   2382  1.179   msaitoh 		break;
   2383    1.1   thorpej 	case SIOCSIFMEDIA:
   2384    1.1   thorpej 	case SIOCGIFMEDIA:
   2385   1.71   thorpej 		/* Flow control requires full-duplex mode. */
   2386   1.71   thorpej 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
   2387   1.71   thorpej 		    (ifr->ifr_media & IFM_FDX) == 0)
   2388   1.71   thorpej 			ifr->ifr_media &= ~IFM_ETH_FMASK;
   2389   1.71   thorpej 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
   2390   1.71   thorpej 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
   2391   1.71   thorpej 				/* We can do both TXPAUSE and RXPAUSE. */
   2392   1.71   thorpej 				ifr->ifr_media |=
   2393   1.71   thorpej 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   2394   1.71   thorpej 			}
   2395   1.71   thorpej 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
   2396   1.71   thorpej 		}
   2397    1.1   thorpej 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
   2398    1.1   thorpej 		break;
   2399  1.175    darran 	case SIOCINITIFADDR:
   2400  1.175    darran 		if (ifa->ifa_addr->sa_family == AF_LINK) {
   2401  1.175    darran 			sdl = satosdl(ifp->if_dl->ifa_addr);
   2402  1.175    darran 			(void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
   2403  1.175    darran 					LLADDR(satosdl(ifa->ifa_addr)),
   2404  1.175    darran 					ifp->if_addrlen);
   2405  1.175    darran 			/* unicast address is first multicast entry */
   2406  1.175    darran 			wm_set_filter(sc);
   2407  1.175    darran 			error = 0;
   2408  1.175    darran 			break;
   2409  1.175    darran 		}
   2410  1.175    darran 		/* Fall through for rest */
   2411    1.1   thorpej 	default:
   2412  1.154    dyoung 		if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
   2413  1.154    dyoung 			break;
   2414  1.154    dyoung 
   2415  1.154    dyoung 		error = 0;
   2416  1.154    dyoung 
   2417  1.154    dyoung 		if (cmd == SIOCSIFCAP)
   2418  1.154    dyoung 			error = (*ifp->if_init)(ifp);
   2419  1.154    dyoung 		else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
   2420  1.154    dyoung 			;
   2421  1.154    dyoung 		else if (ifp->if_flags & IFF_RUNNING) {
   2422    1.1   thorpej 			/*
   2423    1.1   thorpej 			 * Multicast list has changed; set the hardware filter
   2424    1.1   thorpej 			 * accordingly.
   2425    1.1   thorpej 			 */
   2426  1.154    dyoung 			wm_set_filter(sc);
   2427    1.1   thorpej 		}
   2428    1.1   thorpej 		break;
   2429    1.1   thorpej 	}
   2430    1.1   thorpej 
   2431    1.1   thorpej 	/* Try to get more packets going. */
   2432    1.1   thorpej 	wm_start(ifp);
   2433    1.1   thorpej 
   2434    1.1   thorpej 	splx(s);
   2435    1.1   thorpej 	return (error);
   2436    1.1   thorpej }
   2437    1.1   thorpej 
   2438    1.1   thorpej /*
   2439    1.1   thorpej  * wm_intr:
   2440    1.1   thorpej  *
   2441    1.1   thorpej  *	Interrupt service routine.
   2442    1.1   thorpej  */
   2443   1.47   thorpej static int
   2444    1.1   thorpej wm_intr(void *arg)
   2445    1.1   thorpej {
   2446    1.1   thorpej 	struct wm_softc *sc = arg;
   2447    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2448    1.1   thorpej 	uint32_t icr;
   2449  1.108      yamt 	int handled = 0;
   2450    1.1   thorpej 
   2451  1.108      yamt 	while (1 /* CONSTCOND */) {
   2452    1.1   thorpej 		icr = CSR_READ(sc, WMREG_ICR);
   2453    1.1   thorpej 		if ((icr & sc->sc_icr) == 0)
   2454    1.1   thorpej 			break;
   2455   1.22    itojun #if 0 /*NRND > 0*/
   2456   1.21    itojun 		if (RND_ENABLED(&sc->rnd_source))
   2457   1.21    itojun 			rnd_add_uint32(&sc->rnd_source, icr);
   2458   1.21    itojun #endif
   2459    1.1   thorpej 
   2460    1.1   thorpej 		handled = 1;
   2461    1.1   thorpej 
   2462   1.10   thorpej #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   2463    1.1   thorpej 		if (icr & (ICR_RXDMT0|ICR_RXT0)) {
   2464    1.1   thorpej 			DPRINTF(WM_DEBUG_RX,
   2465    1.1   thorpej 			    ("%s: RX: got Rx intr 0x%08x\n",
   2466  1.160  christos 			    device_xname(sc->sc_dev),
   2467    1.1   thorpej 			    icr & (ICR_RXDMT0|ICR_RXT0)));
   2468    1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_rxintr);
   2469    1.1   thorpej 		}
   2470   1.10   thorpej #endif
   2471   1.10   thorpej 		wm_rxintr(sc);
   2472    1.1   thorpej 
   2473   1.10   thorpej #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   2474   1.10   thorpej 		if (icr & ICR_TXDW) {
   2475    1.1   thorpej 			DPRINTF(WM_DEBUG_TX,
   2476   1.67   thorpej 			    ("%s: TX: got TXDW interrupt\n",
   2477  1.160  christos 			    device_xname(sc->sc_dev)));
   2478   1.10   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_txdw);
   2479   1.10   thorpej 		}
   2480    1.4   thorpej #endif
   2481   1.10   thorpej 		wm_txintr(sc);
   2482    1.1   thorpej 
   2483    1.1   thorpej 		if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) {
   2484    1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   2485    1.1   thorpej 			wm_linkintr(sc, icr);
   2486    1.1   thorpej 		}
   2487    1.1   thorpej 
   2488    1.1   thorpej 		if (icr & ICR_RXO) {
   2489  1.108      yamt 			ifp->if_ierrors++;
   2490  1.108      yamt #if defined(WM_DEBUG)
   2491   1.84   thorpej 			log(LOG_WARNING, "%s: Receive overrun\n",
   2492  1.160  christos 			    device_xname(sc->sc_dev));
   2493  1.108      yamt #endif /* defined(WM_DEBUG) */
   2494    1.1   thorpej 		}
   2495    1.1   thorpej 	}
   2496    1.1   thorpej 
   2497    1.1   thorpej 	if (handled) {
   2498    1.1   thorpej 		/* Try to get more packets going. */
   2499    1.1   thorpej 		wm_start(ifp);
   2500    1.1   thorpej 	}
   2501    1.1   thorpej 
   2502    1.1   thorpej 	return (handled);
   2503    1.1   thorpej }
   2504    1.1   thorpej 
   2505    1.1   thorpej /*
   2506    1.1   thorpej  * wm_txintr:
   2507    1.1   thorpej  *
   2508    1.1   thorpej  *	Helper; handle transmit interrupts.
   2509    1.1   thorpej  */
   2510   1.47   thorpej static void
   2511    1.1   thorpej wm_txintr(struct wm_softc *sc)
   2512    1.1   thorpej {
   2513    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2514    1.1   thorpej 	struct wm_txsoft *txs;
   2515    1.1   thorpej 	uint8_t status;
   2516    1.1   thorpej 	int i;
   2517    1.1   thorpej 
   2518    1.1   thorpej 	ifp->if_flags &= ~IFF_OACTIVE;
   2519    1.1   thorpej 
   2520    1.1   thorpej 	/*
   2521    1.1   thorpej 	 * Go through the Tx list and free mbufs for those
   2522   1.16    simonb 	 * frames which have been transmitted.
   2523    1.1   thorpej 	 */
   2524   1.74      tron 	for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc);
   2525   1.74      tron 	     i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) {
   2526    1.1   thorpej 		txs = &sc->sc_txsoft[i];
   2527    1.1   thorpej 
   2528    1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   2529  1.160  christos 		    ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i));
   2530    1.1   thorpej 
   2531   1.80   thorpej 		WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc,
   2532    1.1   thorpej 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   2533    1.1   thorpej 
   2534   1.65   tsutsui 		status =
   2535   1.65   tsutsui 		    sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status;
   2536   1.20   thorpej 		if ((status & WTX_ST_DD) == 0) {
   2537   1.20   thorpej 			WM_CDTXSYNC(sc, txs->txs_lastdesc, 1,
   2538   1.20   thorpej 			    BUS_DMASYNC_PREREAD);
   2539    1.1   thorpej 			break;
   2540   1.20   thorpej 		}
   2541    1.1   thorpej 
   2542    1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   2543    1.1   thorpej 		    ("%s: TX: job %d done: descs %d..%d\n",
   2544  1.160  christos 		    device_xname(sc->sc_dev), i, txs->txs_firstdesc,
   2545    1.1   thorpej 		    txs->txs_lastdesc));
   2546    1.1   thorpej 
   2547    1.1   thorpej 		/*
   2548    1.1   thorpej 		 * XXX We should probably be using the statistics
   2549    1.1   thorpej 		 * XXX registers, but I don't know if they exist
   2550   1.11   thorpej 		 * XXX on chips before the i82544.
   2551    1.1   thorpej 		 */
   2552    1.1   thorpej 
   2553    1.1   thorpej #ifdef WM_EVENT_COUNTERS
   2554    1.1   thorpej 		if (status & WTX_ST_TU)
   2555    1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_tu);
   2556    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
   2557    1.1   thorpej 
   2558    1.1   thorpej 		if (status & (WTX_ST_EC|WTX_ST_LC)) {
   2559    1.1   thorpej 			ifp->if_oerrors++;
   2560    1.1   thorpej 			if (status & WTX_ST_LC)
   2561   1.84   thorpej 				log(LOG_WARNING, "%s: late collision\n",
   2562  1.160  christos 				    device_xname(sc->sc_dev));
   2563    1.1   thorpej 			else if (status & WTX_ST_EC) {
   2564    1.1   thorpej 				ifp->if_collisions += 16;
   2565   1.84   thorpej 				log(LOG_WARNING, "%s: excessive collisions\n",
   2566  1.160  christos 				    device_xname(sc->sc_dev));
   2567    1.1   thorpej 			}
   2568    1.1   thorpej 		} else
   2569    1.1   thorpej 			ifp->if_opackets++;
   2570    1.1   thorpej 
   2571    1.4   thorpej 		sc->sc_txfree += txs->txs_ndesc;
   2572    1.1   thorpej 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
   2573    1.1   thorpej 		    0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   2574    1.1   thorpej 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   2575    1.1   thorpej 		m_freem(txs->txs_mbuf);
   2576    1.1   thorpej 		txs->txs_mbuf = NULL;
   2577    1.1   thorpej 	}
   2578    1.1   thorpej 
   2579    1.1   thorpej 	/* Update the dirty transmit buffer pointer. */
   2580    1.1   thorpej 	sc->sc_txsdirty = i;
   2581    1.1   thorpej 	DPRINTF(WM_DEBUG_TX,
   2582  1.160  christos 	    ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i));
   2583    1.1   thorpej 
   2584    1.1   thorpej 	/*
   2585    1.1   thorpej 	 * If there are no more pending transmissions, cancel the watchdog
   2586    1.1   thorpej 	 * timer.
   2587    1.1   thorpej 	 */
   2588   1.74      tron 	if (sc->sc_txsfree == WM_TXQUEUELEN(sc))
   2589    1.1   thorpej 		ifp->if_timer = 0;
   2590    1.1   thorpej }
   2591    1.1   thorpej 
   2592    1.1   thorpej /*
   2593    1.1   thorpej  * wm_rxintr:
   2594    1.1   thorpej  *
   2595    1.1   thorpej  *	Helper; handle receive interrupts.
   2596    1.1   thorpej  */
   2597   1.47   thorpej static void
   2598    1.1   thorpej wm_rxintr(struct wm_softc *sc)
   2599    1.1   thorpej {
   2600    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2601    1.1   thorpej 	struct wm_rxsoft *rxs;
   2602    1.1   thorpej 	struct mbuf *m;
   2603    1.1   thorpej 	int i, len;
   2604    1.1   thorpej 	uint8_t status, errors;
   2605  1.171    darran 	uint16_t vlantag;
   2606    1.1   thorpej 
   2607    1.1   thorpej 	for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
   2608    1.1   thorpej 		rxs = &sc->sc_rxsoft[i];
   2609    1.1   thorpej 
   2610    1.1   thorpej 		DPRINTF(WM_DEBUG_RX,
   2611    1.1   thorpej 		    ("%s: RX: checking descriptor %d\n",
   2612  1.160  christos 		    device_xname(sc->sc_dev), i));
   2613    1.1   thorpej 
   2614    1.1   thorpej 		WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   2615    1.1   thorpej 
   2616    1.1   thorpej 		status = sc->sc_rxdescs[i].wrx_status;
   2617    1.1   thorpej 		errors = sc->sc_rxdescs[i].wrx_errors;
   2618    1.1   thorpej 		len = le16toh(sc->sc_rxdescs[i].wrx_len);
   2619  1.171    darran 		vlantag = sc->sc_rxdescs[i].wrx_special;
   2620    1.1   thorpej 
   2621    1.1   thorpej 		if ((status & WRX_ST_DD) == 0) {
   2622    1.1   thorpej 			/*
   2623    1.1   thorpej 			 * We have processed all of the receive descriptors.
   2624    1.1   thorpej 			 */
   2625   1.20   thorpej 			WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
   2626    1.1   thorpej 			break;
   2627    1.1   thorpej 		}
   2628    1.1   thorpej 
   2629    1.1   thorpej 		if (__predict_false(sc->sc_rxdiscard)) {
   2630    1.1   thorpej 			DPRINTF(WM_DEBUG_RX,
   2631    1.1   thorpej 			    ("%s: RX: discarding contents of descriptor %d\n",
   2632  1.160  christos 			    device_xname(sc->sc_dev), i));
   2633    1.1   thorpej 			WM_INIT_RXDESC(sc, i);
   2634    1.1   thorpej 			if (status & WRX_ST_EOP) {
   2635    1.1   thorpej 				/* Reset our state. */
   2636    1.1   thorpej 				DPRINTF(WM_DEBUG_RX,
   2637    1.1   thorpej 				    ("%s: RX: resetting rxdiscard -> 0\n",
   2638  1.160  christos 				    device_xname(sc->sc_dev)));
   2639    1.1   thorpej 				sc->sc_rxdiscard = 0;
   2640    1.1   thorpej 			}
   2641    1.1   thorpej 			continue;
   2642    1.1   thorpej 		}
   2643    1.1   thorpej 
   2644    1.1   thorpej 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   2645    1.1   thorpej 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   2646    1.1   thorpej 
   2647    1.1   thorpej 		m = rxs->rxs_mbuf;
   2648    1.1   thorpej 
   2649    1.1   thorpej 		/*
   2650  1.124  wrstuden 		 * Add a new receive buffer to the ring, unless of
   2651  1.124  wrstuden 		 * course the length is zero. Treat the latter as a
   2652  1.124  wrstuden 		 * failed mapping.
   2653    1.1   thorpej 		 */
   2654  1.124  wrstuden 		if ((len == 0) || (wm_add_rxbuf(sc, i) != 0)) {
   2655    1.1   thorpej 			/*
   2656    1.1   thorpej 			 * Failed, throw away what we've done so
   2657    1.1   thorpej 			 * far, and discard the rest of the packet.
   2658    1.1   thorpej 			 */
   2659    1.1   thorpej 			ifp->if_ierrors++;
   2660    1.1   thorpej 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   2661    1.1   thorpej 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   2662    1.1   thorpej 			WM_INIT_RXDESC(sc, i);
   2663    1.1   thorpej 			if ((status & WRX_ST_EOP) == 0)
   2664    1.1   thorpej 				sc->sc_rxdiscard = 1;
   2665    1.1   thorpej 			if (sc->sc_rxhead != NULL)
   2666    1.1   thorpej 				m_freem(sc->sc_rxhead);
   2667    1.1   thorpej 			WM_RXCHAIN_RESET(sc);
   2668    1.1   thorpej 			DPRINTF(WM_DEBUG_RX,
   2669    1.1   thorpej 			    ("%s: RX: Rx buffer allocation failed, "
   2670  1.160  christos 			    "dropping packet%s\n", device_xname(sc->sc_dev),
   2671    1.1   thorpej 			    sc->sc_rxdiscard ? " (discard)" : ""));
   2672    1.1   thorpej 			continue;
   2673    1.1   thorpej 		}
   2674    1.1   thorpej 
   2675    1.1   thorpej 		m->m_len = len;
   2676  1.159    simonb 		sc->sc_rxlen += len;
   2677    1.1   thorpej 		DPRINTF(WM_DEBUG_RX,
   2678    1.1   thorpej 		    ("%s: RX: buffer at %p len %d\n",
   2679  1.160  christos 		    device_xname(sc->sc_dev), m->m_data, len));
   2680    1.1   thorpej 
   2681    1.1   thorpej 		/*
   2682    1.1   thorpej 		 * If this is not the end of the packet, keep
   2683    1.1   thorpej 		 * looking.
   2684    1.1   thorpej 		 */
   2685    1.1   thorpej 		if ((status & WRX_ST_EOP) == 0) {
   2686  1.159    simonb 			WM_RXCHAIN_LINK(sc, m);
   2687    1.1   thorpej 			DPRINTF(WM_DEBUG_RX,
   2688    1.1   thorpej 			    ("%s: RX: not yet EOP, rxlen -> %d\n",
   2689  1.160  christos 			    device_xname(sc->sc_dev), sc->sc_rxlen));
   2690    1.1   thorpej 			continue;
   2691    1.1   thorpej 		}
   2692    1.1   thorpej 
   2693    1.1   thorpej 		/*
   2694   1.93   thorpej 		 * Okay, we have the entire packet now.  The chip is
   2695   1.93   thorpej 		 * configured to include the FCS (not all chips can
   2696   1.93   thorpej 		 * be configured to strip it), so we need to trim it.
   2697  1.159    simonb 		 * May need to adjust length of previous mbuf in the
   2698  1.159    simonb 		 * chain if the current mbuf is too short.
   2699    1.1   thorpej 		 */
   2700  1.159    simonb 		if (m->m_len < ETHER_CRC_LEN) {
   2701  1.159    simonb 			sc->sc_rxtail->m_len -= (ETHER_CRC_LEN - m->m_len);
   2702  1.159    simonb 			m->m_len = 0;
   2703  1.159    simonb 		} else {
   2704  1.159    simonb 			m->m_len -= ETHER_CRC_LEN;
   2705  1.159    simonb 		}
   2706  1.159    simonb 		len = sc->sc_rxlen - ETHER_CRC_LEN;
   2707  1.159    simonb 
   2708  1.159    simonb 		WM_RXCHAIN_LINK(sc, m);
   2709   1.93   thorpej 
   2710    1.1   thorpej 		*sc->sc_rxtailp = NULL;
   2711    1.1   thorpej 		m = sc->sc_rxhead;
   2712    1.1   thorpej 
   2713    1.1   thorpej 		WM_RXCHAIN_RESET(sc);
   2714    1.1   thorpej 
   2715    1.1   thorpej 		DPRINTF(WM_DEBUG_RX,
   2716    1.1   thorpej 		    ("%s: RX: have entire packet, len -> %d\n",
   2717  1.160  christos 		    device_xname(sc->sc_dev), len));
   2718    1.1   thorpej 
   2719    1.1   thorpej 		/*
   2720    1.1   thorpej 		 * If an error occurred, update stats and drop the packet.
   2721    1.1   thorpej 		 */
   2722    1.1   thorpej 		if (errors &
   2723    1.1   thorpej 		     (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
   2724    1.1   thorpej 			ifp->if_ierrors++;
   2725    1.1   thorpej 			if (errors & WRX_ER_SE)
   2726   1.84   thorpej 				log(LOG_WARNING, "%s: symbol error\n",
   2727  1.160  christos 				    device_xname(sc->sc_dev));
   2728    1.1   thorpej 			else if (errors & WRX_ER_SEQ)
   2729   1.84   thorpej 				log(LOG_WARNING, "%s: receive sequence error\n",
   2730  1.160  christos 				    device_xname(sc->sc_dev));
   2731    1.1   thorpej 			else if (errors & WRX_ER_CE)
   2732   1.84   thorpej 				log(LOG_WARNING, "%s: CRC error\n",
   2733  1.160  christos 				    device_xname(sc->sc_dev));
   2734    1.1   thorpej 			m_freem(m);
   2735    1.1   thorpej 			continue;
   2736    1.1   thorpej 		}
   2737    1.1   thorpej 
   2738    1.1   thorpej 		/*
   2739    1.1   thorpej 		 * No errors.  Receive the packet.
   2740    1.1   thorpej 		 */
   2741    1.1   thorpej 		m->m_pkthdr.rcvif = ifp;
   2742    1.1   thorpej 		m->m_pkthdr.len = len;
   2743    1.1   thorpej 
   2744    1.1   thorpej 		/*
   2745    1.1   thorpej 		 * If VLANs are enabled, VLAN packets have been unwrapped
   2746    1.1   thorpej 		 * for us.  Associate the tag with the packet.
   2747    1.1   thorpej 		 */
   2748   1.94  jdolecek 		if ((status & WRX_ST_VP) != 0) {
   2749   1.94  jdolecek 			VLAN_INPUT_TAG(ifp, m,
   2750  1.171    darran 			    le16toh(vlantag),
   2751   1.94  jdolecek 			    continue);
   2752    1.1   thorpej 		}
   2753    1.1   thorpej 
   2754    1.1   thorpej 		/*
   2755    1.1   thorpej 		 * Set up checksum info for this packet.
   2756    1.1   thorpej 		 */
   2757  1.106      yamt 		if ((status & WRX_ST_IXSM) == 0) {
   2758  1.106      yamt 			if (status & WRX_ST_IPCS) {
   2759  1.106      yamt 				WM_EVCNT_INCR(&sc->sc_ev_rxipsum);
   2760  1.106      yamt 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
   2761  1.106      yamt 				if (errors & WRX_ER_IPE)
   2762  1.106      yamt 					m->m_pkthdr.csum_flags |=
   2763  1.106      yamt 					    M_CSUM_IPv4_BAD;
   2764  1.106      yamt 			}
   2765  1.106      yamt 			if (status & WRX_ST_TCPCS) {
   2766  1.106      yamt 				/*
   2767  1.106      yamt 				 * Note: we don't know if this was TCP or UDP,
   2768  1.106      yamt 				 * so we just set both bits, and expect the
   2769  1.106      yamt 				 * upper layers to deal.
   2770  1.106      yamt 				 */
   2771  1.106      yamt 				WM_EVCNT_INCR(&sc->sc_ev_rxtusum);
   2772  1.106      yamt 				m->m_pkthdr.csum_flags |=
   2773  1.130      yamt 				    M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   2774  1.130      yamt 				    M_CSUM_TCPv6 | M_CSUM_UDPv6;
   2775  1.106      yamt 				if (errors & WRX_ER_TCPE)
   2776  1.106      yamt 					m->m_pkthdr.csum_flags |=
   2777  1.106      yamt 					    M_CSUM_TCP_UDP_BAD;
   2778  1.106      yamt 			}
   2779    1.1   thorpej 		}
   2780    1.1   thorpej 
   2781    1.1   thorpej 		ifp->if_ipackets++;
   2782    1.1   thorpej 
   2783    1.1   thorpej #if NBPFILTER > 0
   2784    1.1   thorpej 		/* Pass this up to any BPF listeners. */
   2785    1.1   thorpej 		if (ifp->if_bpf)
   2786    1.1   thorpej 			bpf_mtap(ifp->if_bpf, m);
   2787    1.1   thorpej #endif /* NBPFILTER > 0 */
   2788    1.1   thorpej 
   2789    1.1   thorpej 		/* Pass it on. */
   2790    1.1   thorpej 		(*ifp->if_input)(ifp, m);
   2791    1.1   thorpej 	}
   2792    1.1   thorpej 
   2793    1.1   thorpej 	/* Update the receive pointer. */
   2794    1.1   thorpej 	sc->sc_rxptr = i;
   2795    1.1   thorpej 
   2796    1.1   thorpej 	DPRINTF(WM_DEBUG_RX,
   2797  1.160  christos 	    ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i));
   2798    1.1   thorpej }
   2799    1.1   thorpej 
   2800    1.1   thorpej /*
   2801    1.1   thorpej  * wm_linkintr:
   2802    1.1   thorpej  *
   2803    1.1   thorpej  *	Helper; handle link interrupts.
   2804    1.1   thorpej  */
   2805   1.47   thorpej static void
   2806    1.1   thorpej wm_linkintr(struct wm_softc *sc, uint32_t icr)
   2807    1.1   thorpej {
   2808    1.1   thorpej 	uint32_t status;
   2809    1.1   thorpej 
   2810  1.173   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   2811  1.173   msaitoh 		__func__));
   2812    1.1   thorpej 	/*
   2813    1.1   thorpej 	 * If we get a link status interrupt on a 1000BASE-T
   2814    1.1   thorpej 	 * device, just fall into the normal MII tick path.
   2815    1.1   thorpej 	 */
   2816    1.1   thorpej 	if (sc->sc_flags & WM_F_HAS_MII) {
   2817    1.1   thorpej 		if (icr & ICR_LSC) {
   2818    1.1   thorpej 			DPRINTF(WM_DEBUG_LINK,
   2819    1.1   thorpej 			    ("%s: LINK: LSC -> mii_tick\n",
   2820  1.160  christos 			    device_xname(sc->sc_dev)));
   2821    1.1   thorpej 			mii_tick(&sc->sc_mii);
   2822  1.170   msaitoh 			if (sc->sc_type == WM_T_82543) {
   2823  1.170   msaitoh 				int miistatus, active;
   2824  1.170   msaitoh 
   2825  1.170   msaitoh 				/*
   2826  1.170   msaitoh 				 * With 82543, we need to force speed and
   2827  1.170   msaitoh 				 * duplex on the MAC equal to what the PHY
   2828  1.170   msaitoh 				 * speed and duplex configuration is.
   2829  1.170   msaitoh 				 */
   2830  1.170   msaitoh 				miistatus = sc->sc_mii.mii_media_status;
   2831  1.170   msaitoh 
   2832  1.170   msaitoh 				if (miistatus & IFM_ACTIVE) {
   2833  1.170   msaitoh 					active = sc->sc_mii.mii_media_active;
   2834  1.170   msaitoh 					sc->sc_ctrl &= ~(CTRL_SPEED_MASK
   2835  1.170   msaitoh 					    | CTRL_FD);
   2836  1.170   msaitoh 					switch (IFM_SUBTYPE(active)) {
   2837  1.170   msaitoh 					case IFM_10_T:
   2838  1.170   msaitoh 						sc->sc_ctrl |= CTRL_SPEED_10;
   2839  1.170   msaitoh 						break;
   2840  1.170   msaitoh 					case IFM_100_TX:
   2841  1.170   msaitoh 						sc->sc_ctrl |= CTRL_SPEED_100;
   2842  1.170   msaitoh 						break;
   2843  1.170   msaitoh 					case IFM_1000_T:
   2844  1.170   msaitoh 						sc->sc_ctrl |= CTRL_SPEED_1000;
   2845  1.170   msaitoh 						break;
   2846  1.170   msaitoh 					default:
   2847  1.170   msaitoh 						/*
   2848  1.170   msaitoh 						 * fiber?
   2849  1.170   msaitoh 						 * Shoud not enter here.
   2850  1.170   msaitoh 						 */
   2851  1.170   msaitoh 						printf("unknown media (%x)\n",
   2852  1.170   msaitoh 						    active);
   2853  1.170   msaitoh 						break;
   2854  1.170   msaitoh 					}
   2855  1.170   msaitoh 					if (active & IFM_FDX)
   2856  1.170   msaitoh 						sc->sc_ctrl |= CTRL_FD;
   2857  1.170   msaitoh 					CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2858  1.170   msaitoh 				}
   2859  1.170   msaitoh 			}
   2860    1.1   thorpej 		} else if (icr & ICR_RXSEQ) {
   2861    1.1   thorpej 			DPRINTF(WM_DEBUG_LINK,
   2862    1.1   thorpej 			    ("%s: LINK Receive sequence error\n",
   2863  1.160  christos 			    device_xname(sc->sc_dev)));
   2864    1.1   thorpej 		}
   2865    1.1   thorpej 		return;
   2866    1.1   thorpej 	}
   2867    1.1   thorpej 
   2868  1.173   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   2869    1.1   thorpej 	if (icr & ICR_LSC) {
   2870    1.1   thorpej 		if (status & STATUS_LU) {
   2871    1.1   thorpej 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
   2872  1.160  christos 			    device_xname(sc->sc_dev),
   2873    1.1   thorpej 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   2874  1.173   msaitoh 			/*
   2875  1.173   msaitoh 			 * NOTE: CTRL will update TFCE and RFCE automatically,
   2876  1.173   msaitoh 			 * so we should update sc->sc_ctrl
   2877  1.173   msaitoh 			 */
   2878  1.173   msaitoh 
   2879  1.173   msaitoh 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   2880    1.1   thorpej 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   2881   1.71   thorpej 			sc->sc_fcrtl &= ~FCRTL_XONE;
   2882    1.1   thorpej 			if (status & STATUS_FD)
   2883    1.1   thorpej 				sc->sc_tctl |=
   2884    1.1   thorpej 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   2885    1.1   thorpej 			else
   2886    1.1   thorpej 				sc->sc_tctl |=
   2887    1.1   thorpej 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   2888  1.173   msaitoh 			if (sc->sc_ctrl & CTRL_TFCE)
   2889   1.71   thorpej 				sc->sc_fcrtl |= FCRTL_XONE;
   2890    1.1   thorpej 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   2891   1.71   thorpej 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   2892   1.71   thorpej 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   2893   1.71   thorpej 				      sc->sc_fcrtl);
   2894    1.1   thorpej 			sc->sc_tbi_linkup = 1;
   2895    1.1   thorpej 		} else {
   2896    1.1   thorpej 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   2897  1.161    cegger 			    device_xname(sc->sc_dev)));
   2898    1.1   thorpej 			sc->sc_tbi_linkup = 0;
   2899    1.1   thorpej 		}
   2900    1.1   thorpej 		wm_tbi_set_linkled(sc);
   2901  1.173   msaitoh 	} else if (icr & ICR_RXCFG) {
   2902  1.173   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n",
   2903  1.173   msaitoh 		    device_xname(sc->sc_dev)));
   2904  1.173   msaitoh 		sc->sc_tbi_nrxcfg++;
   2905  1.173   msaitoh 		wm_check_for_link(sc);
   2906    1.1   thorpej 	} else if (icr & ICR_RXSEQ) {
   2907    1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   2908    1.1   thorpej 		    ("%s: LINK: Receive sequence error\n",
   2909  1.160  christos 		    device_xname(sc->sc_dev)));
   2910    1.1   thorpej 	}
   2911    1.1   thorpej }
   2912    1.1   thorpej 
   2913    1.1   thorpej /*
   2914    1.1   thorpej  * wm_tick:
   2915    1.1   thorpej  *
   2916    1.1   thorpej  *	One second timer, used to check link status, sweep up
   2917    1.1   thorpej  *	completed transmit jobs, etc.
   2918    1.1   thorpej  */
   2919   1.47   thorpej static void
   2920    1.1   thorpej wm_tick(void *arg)
   2921    1.1   thorpej {
   2922    1.1   thorpej 	struct wm_softc *sc = arg;
   2923  1.127    bouyer 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2924    1.1   thorpej 	int s;
   2925    1.1   thorpej 
   2926    1.1   thorpej 	s = splnet();
   2927    1.1   thorpej 
   2928   1.71   thorpej 	if (sc->sc_type >= WM_T_82542_2_1) {
   2929   1.71   thorpej 		WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
   2930   1.71   thorpej 		WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
   2931   1.71   thorpej 		WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
   2932   1.71   thorpej 		WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
   2933   1.71   thorpej 		WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
   2934   1.71   thorpej 	}
   2935   1.71   thorpej 
   2936  1.127    bouyer 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
   2937  1.127    bouyer 	ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
   2938  1.127    bouyer 
   2939  1.127    bouyer 
   2940    1.1   thorpej 	if (sc->sc_flags & WM_F_HAS_MII)
   2941    1.1   thorpej 		mii_tick(&sc->sc_mii);
   2942    1.1   thorpej 	else
   2943    1.1   thorpej 		wm_tbi_check_link(sc);
   2944    1.1   thorpej 
   2945    1.1   thorpej 	splx(s);
   2946    1.1   thorpej 
   2947    1.1   thorpej 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   2948    1.1   thorpej }
   2949    1.1   thorpej 
   2950    1.1   thorpej /*
   2951    1.1   thorpej  * wm_reset:
   2952    1.1   thorpej  *
   2953    1.1   thorpej  *	Reset the i82542 chip.
   2954    1.1   thorpej  */
   2955   1.47   thorpej static void
   2956    1.1   thorpej wm_reset(struct wm_softc *sc)
   2957    1.1   thorpej {
   2958  1.146   msaitoh 	uint32_t reg;
   2959    1.1   thorpej 
   2960   1.78   thorpej 	/*
   2961   1.78   thorpej 	 * Allocate on-chip memory according to the MTU size.
   2962   1.78   thorpej 	 * The Packet Buffer Allocation register must be written
   2963   1.78   thorpej 	 * before the chip is reset.
   2964   1.78   thorpej 	 */
   2965  1.120   msaitoh 	switch (sc->sc_type) {
   2966  1.120   msaitoh 	case WM_T_82547:
   2967  1.120   msaitoh 	case WM_T_82547_2:
   2968   1.78   thorpej 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   2969   1.78   thorpej 		    PBA_22K : PBA_30K;
   2970   1.78   thorpej 		sc->sc_txfifo_head = 0;
   2971   1.78   thorpej 		sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
   2972   1.78   thorpej 		sc->sc_txfifo_size =
   2973   1.78   thorpej 		    (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
   2974   1.78   thorpej 		sc->sc_txfifo_stall = 0;
   2975  1.120   msaitoh 		break;
   2976  1.120   msaitoh 	case WM_T_82571:
   2977  1.120   msaitoh 	case WM_T_82572:
   2978  1.127    bouyer 	case WM_T_80003:
   2979  1.120   msaitoh 		sc->sc_pba = PBA_32K;
   2980  1.120   msaitoh 		break;
   2981  1.120   msaitoh 	case WM_T_82573:
   2982  1.165  sborrill 	case WM_T_82574:
   2983  1.120   msaitoh 		sc->sc_pba = PBA_12K;
   2984  1.120   msaitoh 		break;
   2985  1.139    bouyer 	case WM_T_ICH8:
   2986  1.139    bouyer 		sc->sc_pba = PBA_8K;
   2987  1.139    bouyer 		CSR_WRITE(sc, WMREG_PBS, PBA_16K);
   2988  1.139    bouyer 		break;
   2989  1.144   msaitoh 	case WM_T_ICH9:
   2990  1.167   msaitoh 	case WM_T_ICH10:
   2991  1.144   msaitoh 		sc->sc_pba = PBA_10K;
   2992  1.144   msaitoh 		break;
   2993  1.120   msaitoh 	default:
   2994  1.120   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   2995  1.120   msaitoh 		    PBA_40K : PBA_48K;
   2996  1.120   msaitoh 		break;
   2997   1.78   thorpej 	}
   2998   1.78   thorpej 	CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
   2999   1.78   thorpej 
   3000  1.144   msaitoh 	if (sc->sc_flags & WM_F_PCIE) {
   3001  1.144   msaitoh 		int timeout = 800;
   3002  1.144   msaitoh 
   3003  1.144   msaitoh 		sc->sc_ctrl |= CTRL_GIO_M_DIS;
   3004  1.144   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3005  1.144   msaitoh 
   3006  1.144   msaitoh 		while (timeout) {
   3007  1.144   msaitoh 			if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA) == 0)
   3008  1.144   msaitoh 				break;
   3009  1.144   msaitoh 			delay(100);
   3010  1.144   msaitoh 		}
   3011  1.144   msaitoh 	}
   3012  1.144   msaitoh 
   3013  1.144   msaitoh 	/* clear interrupt */
   3014  1.144   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   3015  1.144   msaitoh 
   3016  1.137   msaitoh 	/*
   3017  1.138      salo 	 * 82541 Errata 29? & 82547 Errata 28?
   3018  1.137   msaitoh 	 * See also the description about PHY_RST bit in CTRL register
   3019  1.137   msaitoh 	 * in 8254x_GBe_SDM.pdf.
   3020  1.137   msaitoh 	 */
   3021  1.137   msaitoh 	if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) {
   3022  1.137   msaitoh 		CSR_WRITE(sc, WMREG_CTRL,
   3023  1.137   msaitoh 		    CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
   3024  1.137   msaitoh 		delay(5000);
   3025  1.137   msaitoh 	}
   3026  1.137   msaitoh 
   3027   1.53   thorpej 	switch (sc->sc_type) {
   3028   1.53   thorpej 	case WM_T_82544:
   3029   1.53   thorpej 	case WM_T_82540:
   3030   1.53   thorpej 	case WM_T_82545:
   3031   1.53   thorpej 	case WM_T_82546:
   3032   1.53   thorpej 	case WM_T_82541:
   3033   1.53   thorpej 	case WM_T_82541_2:
   3034   1.53   thorpej 		/*
   3035   1.88    briggs 		 * On some chipsets, a reset through a memory-mapped write
   3036   1.88    briggs 		 * cycle can cause the chip to reset before completing the
   3037   1.88    briggs 		 * write cycle.  This causes major headache that can be
   3038   1.88    briggs 		 * avoided by issuing the reset via indirect register writes
   3039   1.88    briggs 		 * through I/O space.
   3040   1.88    briggs 		 *
   3041   1.88    briggs 		 * So, if we successfully mapped the I/O BAR at attach time,
   3042   1.88    briggs 		 * use that.  Otherwise, try our luck with a memory-mapped
   3043   1.88    briggs 		 * reset.
   3044   1.53   thorpej 		 */
   3045   1.53   thorpej 		if (sc->sc_flags & WM_F_IOH_VALID)
   3046   1.53   thorpej 			wm_io_write(sc, WMREG_CTRL, CTRL_RST);
   3047   1.53   thorpej 		else
   3048   1.53   thorpej 			CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
   3049   1.53   thorpej 		break;
   3050   1.53   thorpej 
   3051   1.53   thorpej 	case WM_T_82545_3:
   3052   1.53   thorpej 	case WM_T_82546_3:
   3053   1.53   thorpej 		/* Use the shadow control register on these chips. */
   3054   1.53   thorpej 		CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
   3055   1.53   thorpej 		break;
   3056   1.53   thorpej 
   3057  1.139    bouyer 	case WM_T_ICH8:
   3058  1.144   msaitoh 	case WM_T_ICH9:
   3059  1.167   msaitoh 	case WM_T_ICH10:
   3060  1.139    bouyer 		wm_get_swfwhw_semaphore(sc);
   3061  1.139    bouyer 		CSR_WRITE(sc, WMREG_CTRL, CTRL_RST | CTRL_PHY_RESET);
   3062  1.144   msaitoh 		delay(10000);
   3063  1.139    bouyer 
   3064   1.53   thorpej 	default:
   3065   1.53   thorpej 		/* Everything else can safely use the documented method. */
   3066   1.53   thorpej 		CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
   3067   1.53   thorpej 		break;
   3068   1.53   thorpej 	}
   3069    1.1   thorpej 	delay(10000);
   3070    1.1   thorpej 
   3071  1.146   msaitoh 	/* reload EEPROM */
   3072  1.144   msaitoh 	switch(sc->sc_type) {
   3073  1.144   msaitoh 	case WM_T_82542_2_0:
   3074  1.144   msaitoh 	case WM_T_82542_2_1:
   3075  1.144   msaitoh 	case WM_T_82543:
   3076  1.144   msaitoh 	case WM_T_82544:
   3077  1.144   msaitoh 		delay(10);
   3078  1.146   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
   3079  1.146   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   3080  1.144   msaitoh 		delay(2000);
   3081  1.144   msaitoh 		break;
   3082  1.144   msaitoh 	case WM_T_82541:
   3083  1.144   msaitoh 	case WM_T_82541_2:
   3084  1.144   msaitoh 	case WM_T_82547:
   3085  1.144   msaitoh 	case WM_T_82547_2:
   3086  1.144   msaitoh 		delay(20000);
   3087  1.144   msaitoh 		break;
   3088  1.144   msaitoh 	case WM_T_82573:
   3089  1.165  sborrill 	case WM_T_82574:
   3090  1.146   msaitoh 		if (sc->sc_flags & WM_F_EEPROM_FLASH) {
   3091  1.146   msaitoh 			delay(10);
   3092  1.146   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
   3093  1.146   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   3094  1.146   msaitoh 		}
   3095  1.144   msaitoh 		/* FALLTHROUGH */
   3096  1.144   msaitoh 	default:
   3097  1.145   msaitoh 		/* check EECD_EE_AUTORD */
   3098  1.146   msaitoh 		wm_get_auto_rd_done(sc);
   3099  1.127    bouyer 	}
   3100  1.144   msaitoh 
   3101  1.174   msaitoh 	/* reload sc_ctrl */
   3102  1.174   msaitoh 	sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   3103  1.174   msaitoh 
   3104  1.144   msaitoh #if 0
   3105  1.144   msaitoh 	for (i = 0; i < 1000; i++) {
   3106  1.144   msaitoh 		if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) {
   3107  1.144   msaitoh 			return;
   3108  1.144   msaitoh 		}
   3109  1.144   msaitoh 		delay(20);
   3110  1.144   msaitoh 	}
   3111  1.144   msaitoh 
   3112  1.144   msaitoh 	if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
   3113  1.144   msaitoh 		log(LOG_ERR, "%s: reset failed to complete\n",
   3114  1.160  christos 		    device_xname(sc->sc_dev));
   3115  1.144   msaitoh #endif
   3116    1.1   thorpej }
   3117    1.1   thorpej 
   3118    1.1   thorpej /*
   3119    1.1   thorpej  * wm_init:		[ifnet interface function]
   3120    1.1   thorpej  *
   3121    1.1   thorpej  *	Initialize the interface.  Must be called at splnet().
   3122    1.1   thorpej  */
   3123   1.47   thorpej static int
   3124    1.1   thorpej wm_init(struct ifnet *ifp)
   3125    1.1   thorpej {
   3126    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   3127    1.1   thorpej 	struct wm_rxsoft *rxs;
   3128    1.1   thorpej 	int i, error = 0;
   3129    1.1   thorpej 	uint32_t reg;
   3130    1.1   thorpej 
   3131   1.42   thorpej 	/*
   3132   1.42   thorpej 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
   3133   1.42   thorpej 	 * There is a small but measurable benefit to avoiding the adjusment
   3134   1.42   thorpej 	 * of the descriptor so that the headers are aligned, for normal mtu,
   3135   1.42   thorpej 	 * on such platforms.  One possibility is that the DMA itself is
   3136   1.42   thorpej 	 * slightly more efficient if the front of the entire packet (instead
   3137   1.42   thorpej 	 * of the front of the headers) is aligned.
   3138   1.42   thorpej 	 *
   3139   1.42   thorpej 	 * Note we must always set align_tweak to 0 if we are using
   3140   1.42   thorpej 	 * jumbo frames.
   3141   1.42   thorpej 	 */
   3142   1.42   thorpej #ifdef __NO_STRICT_ALIGNMENT
   3143   1.42   thorpej 	sc->sc_align_tweak = 0;
   3144   1.41       tls #else
   3145   1.42   thorpej 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
   3146   1.42   thorpej 		sc->sc_align_tweak = 0;
   3147   1.42   thorpej 	else
   3148   1.42   thorpej 		sc->sc_align_tweak = 2;
   3149   1.42   thorpej #endif /* __NO_STRICT_ALIGNMENT */
   3150   1.41       tls 
   3151    1.1   thorpej 	/* Cancel any pending I/O. */
   3152    1.1   thorpej 	wm_stop(ifp, 0);
   3153    1.1   thorpej 
   3154  1.127    bouyer 	/* update statistics before reset */
   3155  1.127    bouyer 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
   3156  1.127    bouyer 	ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
   3157  1.127    bouyer 
   3158    1.1   thorpej 	/* Reset the chip to a known state. */
   3159    1.1   thorpej 	wm_reset(sc);
   3160    1.1   thorpej 
   3161  1.169   msaitoh 	switch (sc->sc_type) {
   3162  1.169   msaitoh 	case WM_T_82571:
   3163  1.169   msaitoh 	case WM_T_82572:
   3164  1.169   msaitoh 	case WM_T_82573:
   3165  1.169   msaitoh 	case WM_T_82574:
   3166  1.169   msaitoh 	case WM_T_80003:
   3167  1.169   msaitoh 	case WM_T_ICH8:
   3168  1.169   msaitoh 	case WM_T_ICH9:
   3169  1.169   msaitoh 	case WM_T_ICH10:
   3170  1.169   msaitoh 		if (wm_check_mng_mode(sc) != 0)
   3171  1.169   msaitoh 			wm_get_hw_control(sc);
   3172  1.169   msaitoh 		break;
   3173  1.169   msaitoh 	default:
   3174  1.169   msaitoh 		break;
   3175  1.169   msaitoh 	}
   3176  1.169   msaitoh 
   3177    1.1   thorpej 	/* Initialize the transmit descriptor ring. */
   3178   1.75   thorpej 	memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc));
   3179   1.75   thorpej 	WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc),
   3180    1.1   thorpej 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   3181   1.75   thorpej 	sc->sc_txfree = WM_NTXDESC(sc);
   3182    1.1   thorpej 	sc->sc_txnext = 0;
   3183    1.5   thorpej 
   3184   1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
   3185   1.69   thorpej 		CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0));
   3186   1.69   thorpej 		CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0));
   3187   1.75   thorpej 		CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc));
   3188    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
   3189    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
   3190   1.10   thorpej 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
   3191    1.1   thorpej 	} else {
   3192   1.69   thorpej 		CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0));
   3193   1.69   thorpej 		CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0));
   3194   1.75   thorpej 		CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc));
   3195    1.1   thorpej 		CSR_WRITE(sc, WMREG_TDH, 0);
   3196    1.1   thorpej 		CSR_WRITE(sc, WMREG_TDT, 0);
   3197  1.150       tls 		CSR_WRITE(sc, WMREG_TIDV, 375);		/* ITR / 4 */
   3198  1.150       tls 		CSR_WRITE(sc, WMREG_TADV, 375);		/* should be same */
   3199    1.1   thorpej 
   3200    1.1   thorpej 		CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
   3201    1.1   thorpej 		    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
   3202    1.1   thorpej 		CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
   3203    1.1   thorpej 		    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
   3204    1.1   thorpej 	}
   3205    1.1   thorpej 	CSR_WRITE(sc, WMREG_TQSA_LO, 0);
   3206    1.1   thorpej 	CSR_WRITE(sc, WMREG_TQSA_HI, 0);
   3207    1.1   thorpej 
   3208    1.1   thorpej 	/* Initialize the transmit job descriptors. */
   3209   1.74      tron 	for (i = 0; i < WM_TXQUEUELEN(sc); i++)
   3210    1.1   thorpej 		sc->sc_txsoft[i].txs_mbuf = NULL;
   3211   1.74      tron 	sc->sc_txsfree = WM_TXQUEUELEN(sc);
   3212    1.1   thorpej 	sc->sc_txsnext = 0;
   3213    1.1   thorpej 	sc->sc_txsdirty = 0;
   3214    1.1   thorpej 
   3215    1.1   thorpej 	/*
   3216    1.1   thorpej 	 * Initialize the receive descriptor and receive job
   3217    1.1   thorpej 	 * descriptor rings.
   3218    1.1   thorpej 	 */
   3219   1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
   3220   1.69   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0));
   3221   1.69   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0));
   3222    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs));
   3223    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
   3224    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
   3225   1.10   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
   3226    1.1   thorpej 
   3227    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
   3228    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
   3229    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
   3230    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
   3231    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
   3232    1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
   3233    1.1   thorpej 	} else {
   3234   1.69   thorpej 		CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0));
   3235   1.69   thorpej 		CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0));
   3236    1.1   thorpej 		CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs));
   3237    1.1   thorpej 		CSR_WRITE(sc, WMREG_RDH, 0);
   3238    1.1   thorpej 		CSR_WRITE(sc, WMREG_RDT, 0);
   3239  1.150       tls 		CSR_WRITE(sc, WMREG_RDTR, 375 | RDTR_FPD);	/* ITR/4 */
   3240  1.150       tls 		CSR_WRITE(sc, WMREG_RADV, 375);		/* MUST be same */
   3241    1.1   thorpej 	}
   3242    1.1   thorpej 	for (i = 0; i < WM_NRXDESC; i++) {
   3243    1.1   thorpej 		rxs = &sc->sc_rxsoft[i];
   3244    1.1   thorpej 		if (rxs->rxs_mbuf == NULL) {
   3245    1.1   thorpej 			if ((error = wm_add_rxbuf(sc, i)) != 0) {
   3246   1.84   thorpej 				log(LOG_ERR, "%s: unable to allocate or map rx "
   3247    1.1   thorpej 				    "buffer %d, error = %d\n",
   3248  1.160  christos 				    device_xname(sc->sc_dev), i, error);
   3249    1.1   thorpej 				/*
   3250    1.1   thorpej 				 * XXX Should attempt to run with fewer receive
   3251    1.1   thorpej 				 * XXX buffers instead of just failing.
   3252    1.1   thorpej 				 */
   3253    1.1   thorpej 				wm_rxdrain(sc);
   3254    1.1   thorpej 				goto out;
   3255    1.1   thorpej 			}
   3256    1.1   thorpej 		} else
   3257    1.1   thorpej 			WM_INIT_RXDESC(sc, i);
   3258    1.1   thorpej 	}
   3259    1.1   thorpej 	sc->sc_rxptr = 0;
   3260    1.1   thorpej 	sc->sc_rxdiscard = 0;
   3261    1.1   thorpej 	WM_RXCHAIN_RESET(sc);
   3262    1.1   thorpej 
   3263    1.1   thorpej 	/*
   3264    1.1   thorpej 	 * Clear out the VLAN table -- we don't use it (yet).
   3265    1.1   thorpej 	 */
   3266    1.1   thorpej 	CSR_WRITE(sc, WMREG_VET, 0);
   3267    1.1   thorpej 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
   3268    1.1   thorpej 		CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
   3269    1.1   thorpej 
   3270    1.1   thorpej 	/*
   3271    1.1   thorpej 	 * Set up flow-control parameters.
   3272    1.1   thorpej 	 *
   3273    1.1   thorpej 	 * XXX Values could probably stand some tuning.
   3274    1.1   thorpej 	 */
   3275  1.177   msaitoh 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
   3276  1.177   msaitoh 	    && (sc->sc_type != WM_T_ICH10)) {
   3277  1.139    bouyer 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
   3278  1.139    bouyer 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
   3279  1.139    bouyer 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
   3280  1.139    bouyer 	}
   3281   1.71   thorpej 
   3282   1.71   thorpej 	sc->sc_fcrtl = FCRTL_DFLT;
   3283   1.71   thorpej 	if (sc->sc_type < WM_T_82543) {
   3284   1.71   thorpej 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
   3285   1.71   thorpej 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
   3286   1.71   thorpej 	} else {
   3287   1.71   thorpej 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
   3288   1.71   thorpej 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
   3289    1.1   thorpej 	}
   3290  1.177   msaitoh 
   3291  1.177   msaitoh 	if (sc->sc_type == WM_T_80003)
   3292  1.177   msaitoh 		CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
   3293  1.177   msaitoh 	else
   3294  1.177   msaitoh 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
   3295    1.1   thorpej 
   3296    1.1   thorpej 	/* Deal with VLAN enables. */
   3297   1.94  jdolecek 	if (VLAN_ATTACHED(&sc->sc_ethercom))
   3298    1.1   thorpej 		sc->sc_ctrl |= CTRL_VME;
   3299    1.1   thorpej 	else
   3300    1.1   thorpej 		sc->sc_ctrl &= ~CTRL_VME;
   3301    1.1   thorpej 
   3302    1.1   thorpej 	/* Write the control registers. */
   3303    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3304  1.177   msaitoh 
   3305  1.177   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII) {
   3306  1.127    bouyer 		int val;
   3307  1.177   msaitoh 
   3308  1.177   msaitoh 		switch (sc->sc_type) {
   3309  1.177   msaitoh 		case WM_T_80003:
   3310  1.177   msaitoh 		case WM_T_ICH8:
   3311  1.177   msaitoh 		case WM_T_ICH9:
   3312  1.177   msaitoh 		case WM_T_ICH10:
   3313  1.177   msaitoh 			/*
   3314  1.177   msaitoh 			 * Set the mac to wait the maximum time between each
   3315  1.177   msaitoh 			 * iteration and increase the max iterations when
   3316  1.177   msaitoh 			 * polling the phy; this fixes erroneous timeouts at
   3317  1.177   msaitoh 			 * 10Mbps.
   3318  1.177   msaitoh 			 */
   3319  1.178   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
   3320  1.177   msaitoh 			    0xFFFF);
   3321  1.178   msaitoh 			val = wm_kmrn_readreg(sc,
   3322  1.177   msaitoh 			    KUMCTRLSTA_OFFSET_INB_PARAM);
   3323  1.177   msaitoh 			val |= 0x3F;
   3324  1.178   msaitoh 			wm_kmrn_writereg(sc,
   3325  1.177   msaitoh 			    KUMCTRLSTA_OFFSET_INB_PARAM, val);
   3326  1.177   msaitoh 			break;
   3327  1.177   msaitoh 		default:
   3328  1.177   msaitoh 			break;
   3329  1.177   msaitoh 		}
   3330  1.177   msaitoh 
   3331  1.177   msaitoh 		if (sc->sc_type == WM_T_80003) {
   3332  1.177   msaitoh 			val = CSR_READ(sc, WMREG_CTRL_EXT);
   3333  1.177   msaitoh 			val &= ~CTRL_EXT_LINK_MODE_MASK;
   3334  1.177   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, val);
   3335  1.177   msaitoh 
   3336  1.177   msaitoh 			/* Bypass RX and TX FIFO's */
   3337  1.178   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
   3338  1.177   msaitoh 			    KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
   3339  1.177   msaitoh 			    KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
   3340  1.127    bouyer 
   3341  1.178   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
   3342  1.177   msaitoh 			    KUMCTRLSTA_INB_CTRL_DIS_PADDING |
   3343  1.177   msaitoh 			    KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
   3344  1.177   msaitoh 		}
   3345  1.127    bouyer 	}
   3346    1.1   thorpej #if 0
   3347    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   3348    1.1   thorpej #endif
   3349    1.1   thorpej 
   3350    1.1   thorpej 	/*
   3351    1.1   thorpej 	 * Set up checksum offload parameters.
   3352    1.1   thorpej 	 */
   3353    1.1   thorpej 	reg = CSR_READ(sc, WMREG_RXCSUM);
   3354  1.130      yamt 	reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
   3355  1.103      yamt 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
   3356    1.1   thorpej 		reg |= RXCSUM_IPOFL;
   3357  1.103      yamt 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
   3358   1.12   thorpej 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
   3359  1.130      yamt 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
   3360  1.130      yamt 		reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
   3361    1.1   thorpej 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
   3362    1.1   thorpej 
   3363  1.173   msaitoh 	/* Reset TBI's RXCFG count */
   3364  1.173   msaitoh 	sc->sc_tbi_nrxcfg = sc->sc_tbi_lastnrxcfg = 0;
   3365  1.173   msaitoh 
   3366    1.1   thorpej 	/*
   3367    1.1   thorpej 	 * Set up the interrupt registers.
   3368    1.1   thorpej 	 */
   3369    1.1   thorpej 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   3370   1.10   thorpej 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
   3371    1.1   thorpej 	    ICR_RXO | ICR_RXT0;
   3372    1.1   thorpej 	if ((sc->sc_flags & WM_F_HAS_MII) == 0)
   3373    1.1   thorpej 		sc->sc_icr |= ICR_RXCFG;
   3374    1.1   thorpej 	CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
   3375    1.1   thorpej 
   3376  1.177   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3377  1.177   msaitoh 	    || (sc->sc_type == WM_T_ICH10)) {
   3378  1.177   msaitoh 		reg = CSR_READ(sc, WMREG_KABGTXD);
   3379  1.177   msaitoh 		reg |= KABGTXD_BGSQLBIAS;
   3380  1.177   msaitoh 		CSR_WRITE(sc, WMREG_KABGTXD, reg);
   3381  1.177   msaitoh 	}
   3382  1.177   msaitoh 
   3383    1.1   thorpej 	/* Set up the inter-packet gap. */
   3384    1.1   thorpej 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   3385    1.1   thorpej 
   3386   1.92    briggs 	if (sc->sc_type >= WM_T_82543) {
   3387  1.150       tls 		/*
   3388  1.150       tls 		 * Set up the interrupt throttling register (units of 256ns)
   3389  1.150       tls 		 * Note that a footnote in Intel's documentation says this
   3390  1.150       tls 		 * ticker runs at 1/4 the rate when the chip is in 100Mbit
   3391  1.150       tls 		 * or 10Mbit mode.  Empirically, it appears to be the case
   3392  1.150       tls 		 * that that is also true for the 1024ns units of the other
   3393  1.150       tls 		 * interrupt-related timer registers -- so, really, we ought
   3394  1.150       tls 		 * to divide this value by 4 when the link speed is low.
   3395  1.150       tls 		 *
   3396  1.150       tls 		 * XXX implement this division at link speed change!
   3397  1.150       tls 		 */
   3398  1.153       tls 
   3399  1.153       tls 		 /*
   3400  1.153       tls 		  * For N interrupts/sec, set this value to:
   3401  1.153       tls 		  * 1000000000 / (N * 256).  Note that we set the
   3402  1.153       tls 		  * absolute and packet timer values to this value
   3403  1.153       tls 		  * divided by 4 to get "simple timer" behavior.
   3404  1.153       tls 		  */
   3405  1.153       tls 
   3406  1.153       tls 		sc->sc_itr = 1500;		/* 2604 ints/sec */
   3407   1.92    briggs 		CSR_WRITE(sc, WMREG_ITR, sc->sc_itr);
   3408   1.92    briggs 	}
   3409   1.92    briggs 
   3410    1.1   thorpej 	/* Set the VLAN ethernetype. */
   3411    1.1   thorpej 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
   3412    1.1   thorpej 
   3413    1.1   thorpej 	/*
   3414    1.1   thorpej 	 * Set up the transmit control register; we start out with
   3415    1.1   thorpej 	 * a collision distance suitable for FDX, but update it whe
   3416    1.1   thorpej 	 * we resolve the media type.
   3417    1.1   thorpej 	 */
   3418  1.178   msaitoh 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
   3419  1.178   msaitoh 	    | TCTL_CT(TX_COLLISION_THRESHOLD)
   3420  1.178   msaitoh 	    | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   3421  1.120   msaitoh 	if (sc->sc_type >= WM_T_82571)
   3422  1.120   msaitoh 		sc->sc_tctl |= TCTL_MULR;
   3423    1.1   thorpej 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   3424    1.1   thorpej 
   3425  1.177   msaitoh 	if (sc->sc_type == WM_T_80003) {
   3426  1.177   msaitoh 		reg = CSR_READ(sc, WMREG_TCTL_EXT);
   3427  1.177   msaitoh 		reg &= ~TCTL_EXT_GCEX_MASK;
   3428  1.177   msaitoh 		reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
   3429  1.177   msaitoh 		CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
   3430  1.177   msaitoh 	}
   3431  1.177   msaitoh 
   3432    1.1   thorpej 	/* Set the media. */
   3433  1.152    dyoung 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
   3434  1.152    dyoung 		goto out;
   3435    1.1   thorpej 
   3436    1.1   thorpej 	/*
   3437    1.1   thorpej 	 * Set up the receive control register; we actually program
   3438    1.1   thorpej 	 * the register when we set the receive filter.  Use multicast
   3439    1.1   thorpej 	 * address offset type 0.
   3440    1.1   thorpej 	 *
   3441   1.11   thorpej 	 * Only the i82544 has the ability to strip the incoming
   3442    1.1   thorpej 	 * CRC, so we don't enable that feature.
   3443    1.1   thorpej 	 */
   3444    1.1   thorpej 	sc->sc_mchash_type = 0;
   3445  1.120   msaitoh 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
   3446  1.120   msaitoh 	    | RCTL_MO(sc->sc_mchash_type);
   3447  1.120   msaitoh 
   3448  1.120   msaitoh 	/* 82573 doesn't support jumbo frame */
   3449  1.165  sborrill 	if (sc->sc_type != WM_T_82573 && sc->sc_type != WM_T_82574 &&
   3450  1.165  sborrill 	    sc->sc_type != WM_T_ICH8)
   3451  1.120   msaitoh 		sc->sc_rctl |= RCTL_LPE;
   3452   1.41       tls 
   3453  1.119  uebayasi 	if (MCLBYTES == 2048) {
   3454   1.41       tls 		sc->sc_rctl |= RCTL_2k;
   3455   1.41       tls 	} else {
   3456  1.119  uebayasi 		if (sc->sc_type >= WM_T_82543) {
   3457   1.41       tls 			switch(MCLBYTES) {
   3458   1.41       tls 			case 4096:
   3459   1.41       tls 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
   3460   1.41       tls 				break;
   3461   1.41       tls 			case 8192:
   3462   1.41       tls 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
   3463   1.41       tls 				break;
   3464   1.41       tls 			case 16384:
   3465   1.41       tls 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
   3466   1.41       tls 				break;
   3467   1.41       tls 			default:
   3468   1.41       tls 				panic("wm_init: MCLBYTES %d unsupported",
   3469   1.41       tls 				    MCLBYTES);
   3470   1.41       tls 				break;
   3471   1.41       tls 			}
   3472   1.41       tls 		} else panic("wm_init: i82542 requires MCLBYTES = 2048");
   3473   1.41       tls 	}
   3474    1.1   thorpej 
   3475    1.1   thorpej 	/* Set the receive filter. */
   3476    1.1   thorpej 	wm_set_filter(sc);
   3477    1.1   thorpej 
   3478    1.1   thorpej 	/* Start the one second link check clock. */
   3479    1.1   thorpej 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   3480    1.1   thorpej 
   3481    1.1   thorpej 	/* ...all done! */
   3482   1.96     perry 	ifp->if_flags |= IFF_RUNNING;
   3483    1.1   thorpej 	ifp->if_flags &= ~IFF_OACTIVE;
   3484    1.1   thorpej 
   3485    1.1   thorpej  out:
   3486    1.1   thorpej 	if (error)
   3487   1.84   thorpej 		log(LOG_ERR, "%s: interface not running\n",
   3488  1.160  christos 		    device_xname(sc->sc_dev));
   3489    1.1   thorpej 	return (error);
   3490    1.1   thorpej }
   3491    1.1   thorpej 
   3492    1.1   thorpej /*
   3493    1.1   thorpej  * wm_rxdrain:
   3494    1.1   thorpej  *
   3495    1.1   thorpej  *	Drain the receive queue.
   3496    1.1   thorpej  */
   3497   1.47   thorpej static void
   3498    1.1   thorpej wm_rxdrain(struct wm_softc *sc)
   3499    1.1   thorpej {
   3500    1.1   thorpej 	struct wm_rxsoft *rxs;
   3501    1.1   thorpej 	int i;
   3502    1.1   thorpej 
   3503    1.1   thorpej 	for (i = 0; i < WM_NRXDESC; i++) {
   3504    1.1   thorpej 		rxs = &sc->sc_rxsoft[i];
   3505    1.1   thorpej 		if (rxs->rxs_mbuf != NULL) {
   3506    1.1   thorpej 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   3507    1.1   thorpej 			m_freem(rxs->rxs_mbuf);
   3508    1.1   thorpej 			rxs->rxs_mbuf = NULL;
   3509    1.1   thorpej 		}
   3510    1.1   thorpej 	}
   3511    1.1   thorpej }
   3512    1.1   thorpej 
   3513    1.1   thorpej /*
   3514    1.1   thorpej  * wm_stop:		[ifnet interface function]
   3515    1.1   thorpej  *
   3516    1.1   thorpej  *	Stop transmission on the interface.
   3517    1.1   thorpej  */
   3518   1.47   thorpej static void
   3519    1.1   thorpej wm_stop(struct ifnet *ifp, int disable)
   3520    1.1   thorpej {
   3521    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   3522    1.1   thorpej 	struct wm_txsoft *txs;
   3523    1.1   thorpej 	int i;
   3524    1.1   thorpej 
   3525    1.1   thorpej 	/* Stop the one second clock. */
   3526    1.1   thorpej 	callout_stop(&sc->sc_tick_ch);
   3527    1.1   thorpej 
   3528   1.78   thorpej 	/* Stop the 82547 Tx FIFO stall check timer. */
   3529   1.78   thorpej 	if (sc->sc_type == WM_T_82547)
   3530   1.78   thorpej 		callout_stop(&sc->sc_txfifo_ch);
   3531   1.78   thorpej 
   3532    1.1   thorpej 	if (sc->sc_flags & WM_F_HAS_MII) {
   3533    1.1   thorpej 		/* Down the MII. */
   3534    1.1   thorpej 		mii_down(&sc->sc_mii);
   3535  1.173   msaitoh 	} else {
   3536  1.173   msaitoh #if 0
   3537  1.173   msaitoh 		/* Should we clear PHY's status properly? */
   3538  1.173   msaitoh 		wm_reset(sc);
   3539  1.173   msaitoh #endif
   3540    1.1   thorpej 	}
   3541    1.1   thorpej 
   3542    1.1   thorpej 	/* Stop the transmit and receive processes. */
   3543    1.1   thorpej 	CSR_WRITE(sc, WMREG_TCTL, 0);
   3544    1.1   thorpej 	CSR_WRITE(sc, WMREG_RCTL, 0);
   3545    1.1   thorpej 
   3546  1.102       scw 	/*
   3547  1.102       scw 	 * Clear the interrupt mask to ensure the device cannot assert its
   3548  1.102       scw 	 * interrupt line.
   3549  1.102       scw 	 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service
   3550  1.102       scw 	 * any currently pending or shared interrupt.
   3551  1.102       scw 	 */
   3552  1.102       scw 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   3553  1.102       scw 	sc->sc_icr = 0;
   3554  1.102       scw 
   3555    1.1   thorpej 	/* Release any queued transmit buffers. */
   3556   1.74      tron 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
   3557    1.1   thorpej 		txs = &sc->sc_txsoft[i];
   3558    1.1   thorpej 		if (txs->txs_mbuf != NULL) {
   3559    1.1   thorpej 			bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   3560    1.1   thorpej 			m_freem(txs->txs_mbuf);
   3561    1.1   thorpej 			txs->txs_mbuf = NULL;
   3562    1.1   thorpej 		}
   3563    1.1   thorpej 	}
   3564    1.1   thorpej 
   3565    1.1   thorpej 	/* Mark the interface as down and cancel the watchdog timer. */
   3566    1.1   thorpej 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   3567    1.1   thorpej 	ifp->if_timer = 0;
   3568  1.156    dyoung 
   3569  1.156    dyoung 	if (disable)
   3570  1.156    dyoung 		wm_rxdrain(sc);
   3571    1.1   thorpej }
   3572    1.1   thorpej 
   3573  1.145   msaitoh void
   3574  1.146   msaitoh wm_get_auto_rd_done(struct wm_softc *sc)
   3575  1.145   msaitoh {
   3576  1.145   msaitoh 	int i;
   3577  1.145   msaitoh 
   3578  1.145   msaitoh 	/* wait for eeprom to reload */
   3579  1.145   msaitoh 	switch (sc->sc_type) {
   3580  1.145   msaitoh 	case WM_T_82571:
   3581  1.145   msaitoh 	case WM_T_82572:
   3582  1.145   msaitoh 	case WM_T_82573:
   3583  1.165  sborrill 	case WM_T_82574:
   3584  1.145   msaitoh 	case WM_T_80003:
   3585  1.145   msaitoh 	case WM_T_ICH8:
   3586  1.145   msaitoh 	case WM_T_ICH9:
   3587  1.167   msaitoh 	case WM_T_ICH10:
   3588  1.145   msaitoh 		for (i = 10; i > 0; i--) {
   3589  1.145   msaitoh 			if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
   3590  1.145   msaitoh 				break;
   3591  1.145   msaitoh 			delay(1000);
   3592  1.145   msaitoh 		}
   3593  1.145   msaitoh 		if (i == 0) {
   3594  1.145   msaitoh 			log(LOG_ERR, "%s: auto read from eeprom failed to "
   3595  1.160  christos 			    "complete\n", device_xname(sc->sc_dev));
   3596  1.145   msaitoh 		}
   3597  1.145   msaitoh 		break;
   3598  1.145   msaitoh 	default:
   3599  1.145   msaitoh 		delay(5000);
   3600  1.145   msaitoh 		break;
   3601  1.145   msaitoh 	}
   3602  1.145   msaitoh 
   3603  1.145   msaitoh 	/* Phy configuration starts after EECD_AUTO_RD is set */
   3604  1.165  sborrill 	if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574)
   3605  1.145   msaitoh 		delay(25000);
   3606  1.145   msaitoh }
   3607  1.145   msaitoh 
   3608    1.1   thorpej /*
   3609   1.45   thorpej  * wm_acquire_eeprom:
   3610   1.45   thorpej  *
   3611   1.45   thorpej  *	Perform the EEPROM handshake required on some chips.
   3612   1.45   thorpej  */
   3613   1.45   thorpej static int
   3614   1.45   thorpej wm_acquire_eeprom(struct wm_softc *sc)
   3615   1.45   thorpej {
   3616   1.45   thorpej 	uint32_t reg;
   3617   1.45   thorpej 	int x;
   3618  1.127    bouyer 	int ret = 0;
   3619   1.45   thorpej 
   3620  1.117   msaitoh 	/* always success */
   3621  1.117   msaitoh 	if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0)
   3622  1.117   msaitoh 		return 0;
   3623  1.117   msaitoh 
   3624  1.139    bouyer 	if (sc->sc_flags & WM_F_SWFWHW_SYNC) {
   3625  1.139    bouyer 		ret = wm_get_swfwhw_semaphore(sc);
   3626  1.139    bouyer 	} else if (sc->sc_flags & WM_F_SWFW_SYNC) {
   3627  1.127    bouyer 		/* this will also do wm_get_swsm_semaphore() if needed */
   3628  1.127    bouyer 		ret = wm_get_swfw_semaphore(sc, SWFW_EEP_SM);
   3629  1.127    bouyer 	} else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) {
   3630  1.127    bouyer 		ret = wm_get_swsm_semaphore(sc);
   3631  1.127    bouyer 	}
   3632  1.127    bouyer 
   3633  1.169   msaitoh 	if (ret) {
   3634  1.169   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   3635  1.169   msaitoh 			__func__);
   3636  1.117   msaitoh 		return 1;
   3637  1.169   msaitoh 	}
   3638  1.117   msaitoh 
   3639   1.45   thorpej 	if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE)  {
   3640   1.45   thorpej 		reg = CSR_READ(sc, WMREG_EECD);
   3641   1.45   thorpej 
   3642   1.45   thorpej 		/* Request EEPROM access. */
   3643   1.45   thorpej 		reg |= EECD_EE_REQ;
   3644   1.45   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   3645   1.45   thorpej 
   3646   1.45   thorpej 		/* ..and wait for it to be granted. */
   3647  1.117   msaitoh 		for (x = 0; x < 1000; x++) {
   3648   1.45   thorpej 			reg = CSR_READ(sc, WMREG_EECD);
   3649   1.45   thorpej 			if (reg & EECD_EE_GNT)
   3650   1.45   thorpej 				break;
   3651   1.45   thorpej 			delay(5);
   3652   1.45   thorpej 		}
   3653   1.45   thorpej 		if ((reg & EECD_EE_GNT) == 0) {
   3654  1.160  christos 			aprint_error_dev(sc->sc_dev,
   3655  1.160  christos 			    "could not acquire EEPROM GNT\n");
   3656   1.45   thorpej 			reg &= ~EECD_EE_REQ;
   3657   1.45   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg);
   3658  1.139    bouyer 			if (sc->sc_flags & WM_F_SWFWHW_SYNC)
   3659  1.139    bouyer 				wm_put_swfwhw_semaphore(sc);
   3660  1.127    bouyer 			if (sc->sc_flags & WM_F_SWFW_SYNC)
   3661  1.127    bouyer 				wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
   3662  1.127    bouyer 			else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE)
   3663  1.127    bouyer 				wm_put_swsm_semaphore(sc);
   3664   1.45   thorpej 			return (1);
   3665   1.45   thorpej 		}
   3666   1.45   thorpej 	}
   3667   1.45   thorpej 
   3668   1.45   thorpej 	return (0);
   3669   1.45   thorpej }
   3670   1.45   thorpej 
   3671   1.45   thorpej /*
   3672   1.45   thorpej  * wm_release_eeprom:
   3673   1.45   thorpej  *
   3674   1.45   thorpej  *	Release the EEPROM mutex.
   3675   1.45   thorpej  */
   3676   1.45   thorpej static void
   3677   1.45   thorpej wm_release_eeprom(struct wm_softc *sc)
   3678   1.45   thorpej {
   3679   1.45   thorpej 	uint32_t reg;
   3680   1.45   thorpej 
   3681  1.117   msaitoh 	/* always success */
   3682  1.117   msaitoh 	if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0)
   3683  1.117   msaitoh 		return;
   3684  1.117   msaitoh 
   3685   1.45   thorpej 	if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) {
   3686   1.45   thorpej 		reg = CSR_READ(sc, WMREG_EECD);
   3687   1.45   thorpej 		reg &= ~EECD_EE_REQ;
   3688   1.45   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   3689   1.45   thorpej 	}
   3690  1.117   msaitoh 
   3691  1.139    bouyer 	if (sc->sc_flags & WM_F_SWFWHW_SYNC)
   3692  1.139    bouyer 		wm_put_swfwhw_semaphore(sc);
   3693  1.127    bouyer 	if (sc->sc_flags & WM_F_SWFW_SYNC)
   3694  1.127    bouyer 		wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
   3695  1.127    bouyer 	else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE)
   3696  1.127    bouyer 		wm_put_swsm_semaphore(sc);
   3697   1.45   thorpej }
   3698   1.45   thorpej 
   3699   1.45   thorpej /*
   3700   1.46   thorpej  * wm_eeprom_sendbits:
   3701   1.46   thorpej  *
   3702   1.46   thorpej  *	Send a series of bits to the EEPROM.
   3703   1.46   thorpej  */
   3704   1.46   thorpej static void
   3705   1.46   thorpej wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
   3706   1.46   thorpej {
   3707   1.46   thorpej 	uint32_t reg;
   3708   1.46   thorpej 	int x;
   3709   1.46   thorpej 
   3710   1.46   thorpej 	reg = CSR_READ(sc, WMREG_EECD);
   3711   1.46   thorpej 
   3712   1.46   thorpej 	for (x = nbits; x > 0; x--) {
   3713   1.46   thorpej 		if (bits & (1U << (x - 1)))
   3714   1.46   thorpej 			reg |= EECD_DI;
   3715   1.46   thorpej 		else
   3716   1.46   thorpej 			reg &= ~EECD_DI;
   3717   1.46   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   3718   1.46   thorpej 		delay(2);
   3719   1.46   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   3720   1.46   thorpej 		delay(2);
   3721   1.46   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   3722   1.46   thorpej 		delay(2);
   3723   1.46   thorpej 	}
   3724   1.46   thorpej }
   3725   1.46   thorpej 
   3726   1.46   thorpej /*
   3727   1.48   thorpej  * wm_eeprom_recvbits:
   3728   1.48   thorpej  *
   3729   1.48   thorpej  *	Receive a series of bits from the EEPROM.
   3730   1.48   thorpej  */
   3731   1.48   thorpej static void
   3732   1.48   thorpej wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
   3733   1.48   thorpej {
   3734   1.48   thorpej 	uint32_t reg, val;
   3735   1.48   thorpej 	int x;
   3736   1.48   thorpej 
   3737   1.48   thorpej 	reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
   3738   1.48   thorpej 
   3739   1.48   thorpej 	val = 0;
   3740   1.48   thorpej 	for (x = nbits; x > 0; x--) {
   3741   1.48   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   3742   1.48   thorpej 		delay(2);
   3743   1.48   thorpej 		if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
   3744   1.48   thorpej 			val |= (1U << (x - 1));
   3745   1.48   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   3746   1.48   thorpej 		delay(2);
   3747   1.48   thorpej 	}
   3748   1.48   thorpej 	*valp = val;
   3749   1.48   thorpej }
   3750   1.48   thorpej 
   3751   1.48   thorpej /*
   3752   1.50   thorpej  * wm_read_eeprom_uwire:
   3753   1.50   thorpej  *
   3754   1.50   thorpej  *	Read a word from the EEPROM using the MicroWire protocol.
   3755   1.50   thorpej  */
   3756   1.51   thorpej static int
   3757   1.51   thorpej wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   3758   1.50   thorpej {
   3759   1.50   thorpej 	uint32_t reg, val;
   3760   1.51   thorpej 	int i;
   3761   1.51   thorpej 
   3762   1.51   thorpej 	for (i = 0; i < wordcnt; i++) {
   3763   1.51   thorpej 		/* Clear SK and DI. */
   3764   1.51   thorpej 		reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
   3765   1.51   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   3766   1.50   thorpej 
   3767   1.51   thorpej 		/* Set CHIP SELECT. */
   3768   1.51   thorpej 		reg |= EECD_CS;
   3769   1.51   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   3770   1.51   thorpej 		delay(2);
   3771   1.51   thorpej 
   3772   1.51   thorpej 		/* Shift in the READ command. */
   3773   1.51   thorpej 		wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
   3774   1.51   thorpej 
   3775   1.51   thorpej 		/* Shift in address. */
   3776   1.51   thorpej 		wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);
   3777   1.51   thorpej 
   3778   1.51   thorpej 		/* Shift out the data. */
   3779   1.51   thorpej 		wm_eeprom_recvbits(sc, &val, 16);
   3780   1.51   thorpej 		data[i] = val & 0xffff;
   3781   1.51   thorpej 
   3782   1.51   thorpej 		/* Clear CHIP SELECT. */
   3783   1.51   thorpej 		reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
   3784   1.51   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   3785   1.51   thorpej 		delay(2);
   3786   1.51   thorpej 	}
   3787   1.51   thorpej 
   3788   1.51   thorpej 	return (0);
   3789   1.50   thorpej }
   3790   1.50   thorpej 
   3791   1.50   thorpej /*
   3792   1.57   thorpej  * wm_spi_eeprom_ready:
   3793   1.57   thorpej  *
   3794   1.57   thorpej  *	Wait for a SPI EEPROM to be ready for commands.
   3795   1.57   thorpej  */
   3796   1.57   thorpej static int
   3797   1.57   thorpej wm_spi_eeprom_ready(struct wm_softc *sc)
   3798   1.57   thorpej {
   3799   1.57   thorpej 	uint32_t val;
   3800   1.57   thorpej 	int usec;
   3801   1.57   thorpej 
   3802   1.57   thorpej 	for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) {
   3803   1.57   thorpej 		wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8);
   3804   1.57   thorpej 		wm_eeprom_recvbits(sc, &val, 8);
   3805   1.57   thorpej 		if ((val & SPI_SR_RDY) == 0)
   3806   1.57   thorpej 			break;
   3807   1.57   thorpej 	}
   3808   1.57   thorpej 	if (usec >= SPI_MAX_RETRIES) {
   3809  1.160  christos 		aprint_error_dev(sc->sc_dev, "EEPROM failed to become ready\n");
   3810   1.57   thorpej 		return (1);
   3811   1.57   thorpej 	}
   3812   1.57   thorpej 	return (0);
   3813   1.57   thorpej }
   3814   1.57   thorpej 
   3815   1.57   thorpej /*
   3816   1.57   thorpej  * wm_read_eeprom_spi:
   3817   1.57   thorpej  *
   3818   1.57   thorpej  *	Read a work from the EEPROM using the SPI protocol.
   3819   1.57   thorpej  */
   3820   1.57   thorpej static int
   3821   1.57   thorpej wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   3822   1.57   thorpej {
   3823   1.57   thorpej 	uint32_t reg, val;
   3824   1.57   thorpej 	int i;
   3825   1.57   thorpej 	uint8_t opc;
   3826   1.57   thorpej 
   3827   1.57   thorpej 	/* Clear SK and CS. */
   3828   1.57   thorpej 	reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
   3829   1.57   thorpej 	CSR_WRITE(sc, WMREG_EECD, reg);
   3830   1.57   thorpej 	delay(2);
   3831   1.57   thorpej 
   3832   1.57   thorpej 	if (wm_spi_eeprom_ready(sc))
   3833   1.57   thorpej 		return (1);
   3834   1.57   thorpej 
   3835   1.57   thorpej 	/* Toggle CS to flush commands. */
   3836   1.57   thorpej 	CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
   3837   1.57   thorpej 	delay(2);
   3838   1.57   thorpej 	CSR_WRITE(sc, WMREG_EECD, reg);
   3839   1.57   thorpej 	delay(2);
   3840   1.57   thorpej 
   3841   1.57   thorpej 	opc = SPI_OPC_READ;
   3842   1.57   thorpej 	if (sc->sc_ee_addrbits == 8 && word >= 128)
   3843   1.57   thorpej 		opc |= SPI_OPC_A8;
   3844   1.57   thorpej 
   3845   1.57   thorpej 	wm_eeprom_sendbits(sc, opc, 8);
   3846   1.57   thorpej 	wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits);
   3847   1.57   thorpej 
   3848   1.57   thorpej 	for (i = 0; i < wordcnt; i++) {
   3849   1.57   thorpej 		wm_eeprom_recvbits(sc, &val, 16);
   3850   1.57   thorpej 		data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
   3851   1.57   thorpej 	}
   3852   1.57   thorpej 
   3853   1.57   thorpej 	/* Raise CS and clear SK. */
   3854   1.57   thorpej 	reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
   3855   1.57   thorpej 	CSR_WRITE(sc, WMREG_EECD, reg);
   3856   1.57   thorpej 	delay(2);
   3857   1.57   thorpej 
   3858   1.57   thorpej 	return (0);
   3859   1.57   thorpej }
   3860   1.57   thorpej 
   3861  1.112     gavan #define EEPROM_CHECKSUM		0xBABA
   3862  1.112     gavan #define EEPROM_SIZE		0x0040
   3863  1.112     gavan 
   3864  1.112     gavan /*
   3865  1.112     gavan  * wm_validate_eeprom_checksum
   3866  1.112     gavan  *
   3867  1.112     gavan  * The checksum is defined as the sum of the first 64 (16 bit) words.
   3868  1.112     gavan  */
   3869  1.112     gavan static int
   3870  1.112     gavan wm_validate_eeprom_checksum(struct wm_softc *sc)
   3871  1.112     gavan {
   3872  1.112     gavan 	uint16_t checksum;
   3873  1.112     gavan 	uint16_t eeprom_data;
   3874  1.112     gavan 	int i;
   3875  1.112     gavan 
   3876  1.112     gavan 	checksum = 0;
   3877  1.112     gavan 
   3878  1.112     gavan 	for (i = 0; i < EEPROM_SIZE; i++) {
   3879  1.119  uebayasi 		if (wm_read_eeprom(sc, i, 1, &eeprom_data))
   3880  1.112     gavan 			return 1;
   3881  1.112     gavan 		checksum += eeprom_data;
   3882  1.112     gavan 	}
   3883  1.112     gavan 
   3884  1.112     gavan 	if (checksum != (uint16_t) EEPROM_CHECKSUM)
   3885  1.112     gavan 		return 1;
   3886  1.112     gavan 
   3887  1.112     gavan 	return 0;
   3888  1.112     gavan }
   3889  1.112     gavan 
   3890   1.57   thorpej /*
   3891    1.1   thorpej  * wm_read_eeprom:
   3892    1.1   thorpej  *
   3893    1.1   thorpej  *	Read data from the serial EEPROM.
   3894    1.1   thorpej  */
   3895   1.51   thorpej static int
   3896    1.1   thorpej wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   3897    1.1   thorpej {
   3898   1.51   thorpej 	int rv;
   3899    1.1   thorpej 
   3900  1.113     gavan 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   3901  1.113     gavan 		return 1;
   3902  1.112     gavan 
   3903   1.51   thorpej 	if (wm_acquire_eeprom(sc))
   3904  1.113     gavan 		return 1;
   3905   1.17   thorpej 
   3906  1.167   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3907  1.167   msaitoh 	    || (sc->sc_type == WM_T_ICH10))
   3908  1.139    bouyer 		rv = wm_read_eeprom_ich8(sc, word, wordcnt, data);
   3909  1.139    bouyer 	else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR)
   3910  1.117   msaitoh 		rv = wm_read_eeprom_eerd(sc, word, wordcnt, data);
   3911  1.117   msaitoh 	else if (sc->sc_flags & WM_F_EEPROM_SPI)
   3912   1.57   thorpej 		rv = wm_read_eeprom_spi(sc, word, wordcnt, data);
   3913   1.57   thorpej 	else
   3914   1.57   thorpej 		rv = wm_read_eeprom_uwire(sc, word, wordcnt, data);
   3915   1.17   thorpej 
   3916   1.51   thorpej 	wm_release_eeprom(sc);
   3917  1.113     gavan 	return rv;
   3918    1.1   thorpej }
   3919    1.1   thorpej 
   3920  1.117   msaitoh static int
   3921  1.117   msaitoh wm_read_eeprom_eerd(struct wm_softc *sc, int offset, int wordcnt,
   3922  1.117   msaitoh     uint16_t *data)
   3923  1.117   msaitoh {
   3924  1.117   msaitoh 	int i, eerd = 0;
   3925  1.117   msaitoh 	int error = 0;
   3926  1.117   msaitoh 
   3927  1.117   msaitoh 	for (i = 0; i < wordcnt; i++) {
   3928  1.117   msaitoh 		eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
   3929  1.117   msaitoh 
   3930  1.117   msaitoh 		CSR_WRITE(sc, WMREG_EERD, eerd);
   3931  1.117   msaitoh 		error = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
   3932  1.117   msaitoh 		if (error != 0)
   3933  1.117   msaitoh 			break;
   3934  1.117   msaitoh 
   3935  1.117   msaitoh 		data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
   3936  1.117   msaitoh 	}
   3937  1.119  uebayasi 
   3938  1.117   msaitoh 	return error;
   3939  1.117   msaitoh }
   3940  1.117   msaitoh 
   3941  1.117   msaitoh static int
   3942  1.117   msaitoh wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
   3943  1.117   msaitoh {
   3944  1.117   msaitoh 	uint32_t attempts = 100000;
   3945  1.117   msaitoh 	uint32_t i, reg = 0;
   3946  1.117   msaitoh 	int32_t done = -1;
   3947  1.117   msaitoh 
   3948  1.119  uebayasi 	for (i = 0; i < attempts; i++) {
   3949  1.117   msaitoh 		reg = CSR_READ(sc, rw);
   3950  1.117   msaitoh 
   3951  1.119  uebayasi 		if (reg & EERD_DONE) {
   3952  1.117   msaitoh 			done = 0;
   3953  1.117   msaitoh 			break;
   3954  1.117   msaitoh 		}
   3955  1.117   msaitoh 		delay(5);
   3956  1.117   msaitoh 	}
   3957  1.117   msaitoh 
   3958  1.117   msaitoh 	return done;
   3959  1.117   msaitoh }
   3960  1.117   msaitoh 
   3961    1.1   thorpej /*
   3962    1.1   thorpej  * wm_add_rxbuf:
   3963    1.1   thorpej  *
   3964    1.1   thorpej  *	Add a receive buffer to the indiciated descriptor.
   3965    1.1   thorpej  */
   3966   1.47   thorpej static int
   3967    1.1   thorpej wm_add_rxbuf(struct wm_softc *sc, int idx)
   3968    1.1   thorpej {
   3969    1.1   thorpej 	struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx];
   3970    1.1   thorpej 	struct mbuf *m;
   3971    1.1   thorpej 	int error;
   3972    1.1   thorpej 
   3973    1.1   thorpej 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   3974    1.1   thorpej 	if (m == NULL)
   3975    1.1   thorpej 		return (ENOBUFS);
   3976    1.1   thorpej 
   3977    1.1   thorpej 	MCLGET(m, M_DONTWAIT);
   3978    1.1   thorpej 	if ((m->m_flags & M_EXT) == 0) {
   3979    1.1   thorpej 		m_freem(m);
   3980    1.1   thorpej 		return (ENOBUFS);
   3981    1.1   thorpej 	}
   3982    1.1   thorpej 
   3983    1.1   thorpej 	if (rxs->rxs_mbuf != NULL)
   3984    1.1   thorpej 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   3985    1.1   thorpej 
   3986    1.1   thorpej 	rxs->rxs_mbuf = m;
   3987    1.1   thorpej 
   3988   1.32   thorpej 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
   3989   1.32   thorpej 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
   3990    1.1   thorpej 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
   3991    1.1   thorpej 	if (error) {
   3992   1.84   thorpej 		/* XXX XXX XXX */
   3993  1.160  christos 		aprint_error_dev(sc->sc_dev,
   3994  1.160  christos 		    "unable to load rx DMA map %d, error = %d\n",
   3995  1.158    cegger 		    idx, error);
   3996   1.84   thorpej 		panic("wm_add_rxbuf");
   3997    1.1   thorpej 	}
   3998    1.1   thorpej 
   3999    1.1   thorpej 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   4000    1.1   thorpej 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   4001    1.1   thorpej 
   4002    1.1   thorpej 	WM_INIT_RXDESC(sc, idx);
   4003    1.1   thorpej 
   4004    1.1   thorpej 	return (0);
   4005    1.1   thorpej }
   4006    1.1   thorpej 
   4007    1.1   thorpej /*
   4008    1.1   thorpej  * wm_set_ral:
   4009    1.1   thorpej  *
   4010    1.1   thorpej  *	Set an entery in the receive address list.
   4011    1.1   thorpej  */
   4012    1.1   thorpej static void
   4013    1.1   thorpej wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
   4014    1.1   thorpej {
   4015    1.1   thorpej 	uint32_t ral_lo, ral_hi;
   4016    1.1   thorpej 
   4017    1.1   thorpej 	if (enaddr != NULL) {
   4018    1.1   thorpej 		ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
   4019    1.1   thorpej 		    (enaddr[3] << 24);
   4020    1.1   thorpej 		ral_hi = enaddr[4] | (enaddr[5] << 8);
   4021    1.1   thorpej 		ral_hi |= RAL_AV;
   4022    1.1   thorpej 	} else {
   4023    1.1   thorpej 		ral_lo = 0;
   4024    1.1   thorpej 		ral_hi = 0;
   4025    1.1   thorpej 	}
   4026    1.1   thorpej 
   4027   1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   4028    1.1   thorpej 		CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),
   4029    1.1   thorpej 		    ral_lo);
   4030    1.1   thorpej 		CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),
   4031    1.1   thorpej 		    ral_hi);
   4032    1.1   thorpej 	} else {
   4033    1.1   thorpej 		CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo);
   4034    1.1   thorpej 		CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi);
   4035    1.1   thorpej 	}
   4036    1.1   thorpej }
   4037    1.1   thorpej 
   4038    1.1   thorpej /*
   4039    1.1   thorpej  * wm_mchash:
   4040    1.1   thorpej  *
   4041    1.1   thorpej  *	Compute the hash of the multicast address for the 4096-bit
   4042    1.1   thorpej  *	multicast filter.
   4043    1.1   thorpej  */
   4044    1.1   thorpej static uint32_t
   4045    1.1   thorpej wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
   4046    1.1   thorpej {
   4047    1.1   thorpej 	static const int lo_shift[4] = { 4, 3, 2, 0 };
   4048    1.1   thorpej 	static const int hi_shift[4] = { 4, 5, 6, 8 };
   4049  1.139    bouyer 	static const int ich8_lo_shift[4] = { 6, 5, 4, 2 };
   4050  1.139    bouyer 	static const int ich8_hi_shift[4] = { 2, 3, 4, 6 };
   4051    1.1   thorpej 	uint32_t hash;
   4052    1.1   thorpej 
   4053  1.167   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4054  1.167   msaitoh 	    || (sc->sc_type == WM_T_ICH10)) {
   4055  1.139    bouyer 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
   4056  1.139    bouyer 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
   4057  1.139    bouyer 		return (hash & 0x3ff);
   4058  1.139    bouyer 	}
   4059    1.1   thorpej 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
   4060    1.1   thorpej 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
   4061    1.1   thorpej 
   4062    1.1   thorpej 	return (hash & 0xfff);
   4063    1.1   thorpej }
   4064    1.1   thorpej 
   4065    1.1   thorpej /*
   4066    1.1   thorpej  * wm_set_filter:
   4067    1.1   thorpej  *
   4068    1.1   thorpej  *	Set up the receive filter.
   4069    1.1   thorpej  */
   4070   1.47   thorpej static void
   4071    1.1   thorpej wm_set_filter(struct wm_softc *sc)
   4072    1.1   thorpej {
   4073    1.1   thorpej 	struct ethercom *ec = &sc->sc_ethercom;
   4074    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   4075    1.1   thorpej 	struct ether_multi *enm;
   4076    1.1   thorpej 	struct ether_multistep step;
   4077    1.1   thorpej 	bus_addr_t mta_reg;
   4078    1.1   thorpej 	uint32_t hash, reg, bit;
   4079  1.139    bouyer 	int i, size;
   4080    1.1   thorpej 
   4081   1.11   thorpej 	if (sc->sc_type >= WM_T_82544)
   4082    1.1   thorpej 		mta_reg = WMREG_CORDOVA_MTA;
   4083    1.1   thorpej 	else
   4084    1.1   thorpej 		mta_reg = WMREG_MTA;
   4085    1.1   thorpej 
   4086    1.1   thorpej 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
   4087    1.1   thorpej 
   4088    1.1   thorpej 	if (ifp->if_flags & IFF_BROADCAST)
   4089    1.1   thorpej 		sc->sc_rctl |= RCTL_BAM;
   4090    1.1   thorpej 	if (ifp->if_flags & IFF_PROMISC) {
   4091    1.1   thorpej 		sc->sc_rctl |= RCTL_UPE;
   4092    1.1   thorpej 		goto allmulti;
   4093    1.1   thorpej 	}
   4094    1.1   thorpej 
   4095    1.1   thorpej 	/*
   4096    1.1   thorpej 	 * Set the station address in the first RAL slot, and
   4097    1.1   thorpej 	 * clear the remaining slots.
   4098    1.1   thorpej 	 */
   4099  1.167   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4100  1.167   msaitoh 		 || (sc->sc_type == WM_T_ICH10))
   4101  1.139    bouyer 		size = WM_ICH8_RAL_TABSIZE;
   4102  1.139    bouyer 	else
   4103  1.139    bouyer 		size = WM_RAL_TABSIZE;
   4104  1.143    dyoung 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
   4105  1.139    bouyer 	for (i = 1; i < size; i++)
   4106    1.1   thorpej 		wm_set_ral(sc, NULL, i);
   4107    1.1   thorpej 
   4108  1.167   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4109  1.167   msaitoh 	    || (sc->sc_type == WM_T_ICH10))
   4110  1.139    bouyer 		size = WM_ICH8_MC_TABSIZE;
   4111  1.139    bouyer 	else
   4112  1.139    bouyer 		size = WM_MC_TABSIZE;
   4113    1.1   thorpej 	/* Clear out the multicast table. */
   4114  1.139    bouyer 	for (i = 0; i < size; i++)
   4115    1.1   thorpej 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
   4116    1.1   thorpej 
   4117    1.1   thorpej 	ETHER_FIRST_MULTI(step, ec, enm);
   4118    1.1   thorpej 	while (enm != NULL) {
   4119    1.1   thorpej 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   4120    1.1   thorpej 			/*
   4121    1.1   thorpej 			 * We must listen to a range of multicast addresses.
   4122    1.1   thorpej 			 * For now, just accept all multicasts, rather than
   4123    1.1   thorpej 			 * trying to set only those filter bits needed to match
   4124    1.1   thorpej 			 * the range.  (At this time, the only use of address
   4125    1.1   thorpej 			 * ranges is for IP multicast routing, for which the
   4126    1.1   thorpej 			 * range is big enough to require all bits set.)
   4127    1.1   thorpej 			 */
   4128    1.1   thorpej 			goto allmulti;
   4129    1.1   thorpej 		}
   4130    1.1   thorpej 
   4131    1.1   thorpej 		hash = wm_mchash(sc, enm->enm_addrlo);
   4132    1.1   thorpej 
   4133  1.139    bouyer 		reg = (hash >> 5);
   4134  1.167   msaitoh 		if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4135  1.167   msaitoh 		    || (sc->sc_type == WM_T_ICH10))
   4136  1.139    bouyer 			reg &= 0x1f;
   4137  1.139    bouyer 		else
   4138  1.139    bouyer 			reg &= 0x7f;
   4139    1.1   thorpej 		bit = hash & 0x1f;
   4140    1.1   thorpej 
   4141    1.1   thorpej 		hash = CSR_READ(sc, mta_reg + (reg << 2));
   4142    1.1   thorpej 		hash |= 1U << bit;
   4143    1.1   thorpej 
   4144    1.1   thorpej 		/* XXX Hardware bug?? */
   4145   1.11   thorpej 		if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
   4146    1.1   thorpej 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
   4147    1.1   thorpej 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   4148    1.1   thorpej 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
   4149    1.1   thorpej 		} else
   4150    1.1   thorpej 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   4151    1.1   thorpej 
   4152    1.1   thorpej 		ETHER_NEXT_MULTI(step, enm);
   4153    1.1   thorpej 	}
   4154    1.1   thorpej 
   4155    1.1   thorpej 	ifp->if_flags &= ~IFF_ALLMULTI;
   4156    1.1   thorpej 	goto setit;
   4157    1.1   thorpej 
   4158    1.1   thorpej  allmulti:
   4159    1.1   thorpej 	ifp->if_flags |= IFF_ALLMULTI;
   4160    1.1   thorpej 	sc->sc_rctl |= RCTL_MPE;
   4161    1.1   thorpej 
   4162    1.1   thorpej  setit:
   4163    1.1   thorpej 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
   4164    1.1   thorpej }
   4165    1.1   thorpej 
   4166    1.1   thorpej /*
   4167    1.1   thorpej  * wm_tbi_mediainit:
   4168    1.1   thorpej  *
   4169    1.1   thorpej  *	Initialize media for use on 1000BASE-X devices.
   4170    1.1   thorpej  */
   4171   1.47   thorpej static void
   4172    1.1   thorpej wm_tbi_mediainit(struct wm_softc *sc)
   4173    1.1   thorpej {
   4174  1.173   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   4175    1.1   thorpej 	const char *sep = "";
   4176    1.1   thorpej 
   4177   1.11   thorpej 	if (sc->sc_type < WM_T_82543)
   4178    1.1   thorpej 		sc->sc_tipg = TIPG_WM_DFLT;
   4179    1.1   thorpej 	else
   4180    1.1   thorpej 		sc->sc_tipg = TIPG_LG_DFLT;
   4181    1.1   thorpej 
   4182  1.173   msaitoh 	sc->sc_tbi_anegticks = 5;
   4183  1.173   msaitoh 
   4184  1.173   msaitoh 	/* Initialize our media structures */
   4185  1.173   msaitoh 	sc->sc_mii.mii_ifp = ifp;
   4186  1.173   msaitoh 
   4187  1.173   msaitoh 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   4188   1.26      fair 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange,
   4189    1.1   thorpej 	    wm_tbi_mediastatus);
   4190    1.1   thorpej 
   4191    1.1   thorpej 	/*
   4192    1.1   thorpej 	 * SWD Pins:
   4193    1.1   thorpej 	 *
   4194    1.1   thorpej 	 *	0 = Link LED (output)
   4195    1.1   thorpej 	 *	1 = Loss Of Signal (input)
   4196    1.1   thorpej 	 */
   4197    1.1   thorpej 	sc->sc_ctrl |= CTRL_SWDPIO(0);
   4198    1.1   thorpej 	sc->sc_ctrl &= ~CTRL_SWDPIO(1);
   4199    1.1   thorpej 
   4200    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4201    1.1   thorpej 
   4202   1.27  christos #define	ADD(ss, mm, dd)							\
   4203    1.1   thorpej do {									\
   4204   1.84   thorpej 	aprint_normal("%s%s", sep, ss);					\
   4205   1.27  christos 	ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL);	\
   4206    1.1   thorpej 	sep = ", ";							\
   4207    1.1   thorpej } while (/*CONSTCOND*/0)
   4208    1.1   thorpej 
   4209  1.160  christos 	aprint_normal_dev(sc->sc_dev, "");
   4210    1.1   thorpej 	ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
   4211    1.1   thorpej 	ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD);
   4212    1.1   thorpej 	ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD);
   4213   1.84   thorpej 	aprint_normal("\n");
   4214    1.1   thorpej 
   4215    1.1   thorpej #undef ADD
   4216    1.1   thorpej 
   4217    1.1   thorpej 	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
   4218    1.1   thorpej }
   4219    1.1   thorpej 
   4220    1.1   thorpej /*
   4221    1.1   thorpej  * wm_tbi_mediastatus:	[ifmedia interface function]
   4222    1.1   thorpej  *
   4223    1.1   thorpej  *	Get the current interface media status on a 1000BASE-X device.
   4224    1.1   thorpej  */
   4225   1.47   thorpej static void
   4226    1.1   thorpej wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   4227    1.1   thorpej {
   4228    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   4229  1.173   msaitoh 	uint32_t ctrl, status;
   4230    1.1   thorpej 
   4231    1.1   thorpej 	ifmr->ifm_status = IFM_AVALID;
   4232    1.1   thorpej 	ifmr->ifm_active = IFM_ETHER;
   4233    1.1   thorpej 
   4234  1.173   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   4235  1.173   msaitoh 	if ((status & STATUS_LU) == 0) {
   4236    1.1   thorpej 		ifmr->ifm_active |= IFM_NONE;
   4237    1.1   thorpej 		return;
   4238    1.1   thorpej 	}
   4239    1.1   thorpej 
   4240    1.1   thorpej 	ifmr->ifm_status |= IFM_ACTIVE;
   4241    1.1   thorpej 	ifmr->ifm_active |= IFM_1000_SX;
   4242    1.1   thorpej 	if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
   4243    1.1   thorpej 		ifmr->ifm_active |= IFM_FDX;
   4244   1.71   thorpej 	ctrl = CSR_READ(sc, WMREG_CTRL);
   4245   1.71   thorpej 	if (ctrl & CTRL_RFCE)
   4246   1.71   thorpej 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE;
   4247   1.71   thorpej 	if (ctrl & CTRL_TFCE)
   4248   1.71   thorpej 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE;
   4249    1.1   thorpej }
   4250    1.1   thorpej 
   4251    1.1   thorpej /*
   4252    1.1   thorpej  * wm_tbi_mediachange:	[ifmedia interface function]
   4253    1.1   thorpej  *
   4254    1.1   thorpej  *	Set hardware to newly-selected media on a 1000BASE-X device.
   4255    1.1   thorpej  */
   4256   1.47   thorpej static int
   4257    1.1   thorpej wm_tbi_mediachange(struct ifnet *ifp)
   4258    1.1   thorpej {
   4259    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   4260    1.1   thorpej 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   4261    1.1   thorpej 	uint32_t status;
   4262    1.1   thorpej 	int i;
   4263    1.1   thorpej 
   4264  1.173   msaitoh 	sc->sc_txcw = 0;
   4265   1.71   thorpej 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
   4266   1.71   thorpej 	    (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
   4267  1.173   msaitoh 		sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE;
   4268  1.134   msaitoh 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   4269  1.173   msaitoh 		sc->sc_txcw |= TXCW_ANE;
   4270  1.134   msaitoh 	} else {
   4271  1.173   msaitoh 		/*
   4272  1.173   msaitoh 		 * If autonegotiation is turned off, force link up and turn on
   4273  1.173   msaitoh 		 * full duplex
   4274  1.173   msaitoh 		 */
   4275  1.134   msaitoh 		sc->sc_txcw &= ~TXCW_ANE;
   4276  1.134   msaitoh 		sc->sc_ctrl |= CTRL_SLU | CTRL_FD;
   4277  1.173   msaitoh 		sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
   4278  1.134   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4279  1.134   msaitoh 		delay(1000);
   4280  1.134   msaitoh 	}
   4281    1.1   thorpej 
   4282  1.134   msaitoh 	DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n",
   4283  1.160  christos 		    device_xname(sc->sc_dev),sc->sc_txcw));
   4284    1.1   thorpej 	CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   4285    1.1   thorpej 	delay(10000);
   4286    1.1   thorpej 
   4287  1.134   msaitoh 	i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1);
   4288  1.160  christos 	DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i));
   4289  1.134   msaitoh 
   4290  1.134   msaitoh 	/*
   4291  1.134   msaitoh 	 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the
   4292  1.134   msaitoh 	 * optics detect a signal, 0 if they don't.
   4293  1.134   msaitoh 	 */
   4294  1.173   msaitoh 	if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) {
   4295    1.1   thorpej 		/* Have signal; wait for the link to come up. */
   4296  1.134   msaitoh 
   4297  1.134   msaitoh 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   4298  1.134   msaitoh 			/*
   4299  1.134   msaitoh 			 * Reset the link, and let autonegotiation do its thing
   4300  1.134   msaitoh 			 */
   4301  1.134   msaitoh 			sc->sc_ctrl |= CTRL_LRST;
   4302  1.134   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4303  1.134   msaitoh 			delay(1000);
   4304  1.134   msaitoh 			sc->sc_ctrl &= ~CTRL_LRST;
   4305  1.134   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4306  1.134   msaitoh 			delay(1000);
   4307  1.134   msaitoh 		}
   4308  1.134   msaitoh 
   4309  1.173   msaitoh 		for (i = 0; i < WM_LINKUP_TIMEOUT; i++) {
   4310    1.1   thorpej 			delay(10000);
   4311    1.1   thorpej 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
   4312    1.1   thorpej 				break;
   4313    1.1   thorpej 		}
   4314    1.1   thorpej 
   4315  1.134   msaitoh 		DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n",
   4316  1.160  christos 			    device_xname(sc->sc_dev),i));
   4317  1.134   msaitoh 
   4318    1.1   thorpej 		status = CSR_READ(sc, WMREG_STATUS);
   4319  1.134   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   4320  1.134   msaitoh 		    ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n",
   4321  1.160  christos 			device_xname(sc->sc_dev),status, STATUS_LU));
   4322    1.1   thorpej 		if (status & STATUS_LU) {
   4323    1.1   thorpej 			/* Link is up. */
   4324    1.1   thorpej 			DPRINTF(WM_DEBUG_LINK,
   4325    1.1   thorpej 			    ("%s: LINK: set media -> link up %s\n",
   4326  1.160  christos 			    device_xname(sc->sc_dev),
   4327    1.1   thorpej 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   4328  1.173   msaitoh 
   4329  1.173   msaitoh 			/*
   4330  1.173   msaitoh 			 * NOTE: CTRL will update TFCE and RFCE automatically,
   4331  1.173   msaitoh 			 * so we should update sc->sc_ctrl
   4332  1.173   msaitoh 			 */
   4333  1.173   msaitoh 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   4334    1.1   thorpej 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   4335   1.71   thorpej 			sc->sc_fcrtl &= ~FCRTL_XONE;
   4336    1.1   thorpej 			if (status & STATUS_FD)
   4337    1.1   thorpej 				sc->sc_tctl |=
   4338    1.1   thorpej 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   4339    1.1   thorpej 			else
   4340    1.1   thorpej 				sc->sc_tctl |=
   4341    1.1   thorpej 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   4342   1.71   thorpej 			if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
   4343   1.71   thorpej 				sc->sc_fcrtl |= FCRTL_XONE;
   4344    1.1   thorpej 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   4345   1.71   thorpej 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   4346   1.71   thorpej 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   4347   1.71   thorpej 				      sc->sc_fcrtl);
   4348    1.1   thorpej 			sc->sc_tbi_linkup = 1;
   4349    1.1   thorpej 		} else {
   4350  1.173   msaitoh 			if (i == WM_LINKUP_TIMEOUT)
   4351  1.173   msaitoh 				wm_check_for_link(sc);
   4352    1.1   thorpej 			/* Link is down. */
   4353    1.1   thorpej 			DPRINTF(WM_DEBUG_LINK,
   4354    1.1   thorpej 			    ("%s: LINK: set media -> link down\n",
   4355  1.160  christos 			    device_xname(sc->sc_dev)));
   4356    1.1   thorpej 			sc->sc_tbi_linkup = 0;
   4357    1.1   thorpej 		}
   4358    1.1   thorpej 	} else {
   4359    1.1   thorpej 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
   4360  1.160  christos 		    device_xname(sc->sc_dev)));
   4361    1.1   thorpej 		sc->sc_tbi_linkup = 0;
   4362    1.1   thorpej 	}
   4363    1.1   thorpej 
   4364    1.1   thorpej 	wm_tbi_set_linkled(sc);
   4365    1.1   thorpej 
   4366    1.1   thorpej 	return (0);
   4367    1.1   thorpej }
   4368    1.1   thorpej 
   4369    1.1   thorpej /*
   4370    1.1   thorpej  * wm_tbi_set_linkled:
   4371    1.1   thorpej  *
   4372    1.1   thorpej  *	Update the link LED on 1000BASE-X devices.
   4373    1.1   thorpej  */
   4374   1.47   thorpej static void
   4375    1.1   thorpej wm_tbi_set_linkled(struct wm_softc *sc)
   4376    1.1   thorpej {
   4377    1.1   thorpej 
   4378    1.1   thorpej 	if (sc->sc_tbi_linkup)
   4379    1.1   thorpej 		sc->sc_ctrl |= CTRL_SWDPIN(0);
   4380    1.1   thorpej 	else
   4381    1.1   thorpej 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
   4382    1.1   thorpej 
   4383  1.173   msaitoh 	/* 82540 or newer devices are active low */
   4384  1.173   msaitoh 	sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0;
   4385  1.173   msaitoh 
   4386    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4387    1.1   thorpej }
   4388    1.1   thorpej 
   4389    1.1   thorpej /*
   4390    1.1   thorpej  * wm_tbi_check_link:
   4391    1.1   thorpej  *
   4392    1.1   thorpej  *	Check the link on 1000BASE-X devices.
   4393    1.1   thorpej  */
   4394   1.47   thorpej static void
   4395    1.1   thorpej wm_tbi_check_link(struct wm_softc *sc)
   4396    1.1   thorpej {
   4397  1.173   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   4398  1.173   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   4399    1.1   thorpej 	uint32_t rxcw, ctrl, status;
   4400    1.1   thorpej 
   4401  1.173   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   4402    1.1   thorpej 
   4403    1.1   thorpej 	rxcw = CSR_READ(sc, WMREG_RXCW);
   4404    1.1   thorpej 	ctrl = CSR_READ(sc, WMREG_CTRL);
   4405    1.1   thorpej 
   4406  1.173   msaitoh 	/* set link status */
   4407    1.1   thorpej 	if ((status & STATUS_LU) == 0) {
   4408    1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   4409  1.160  christos 		    ("%s: LINK: checklink -> down\n", device_xname(sc->sc_dev)));
   4410    1.1   thorpej 		sc->sc_tbi_linkup = 0;
   4411  1.173   msaitoh 	} else if (sc->sc_tbi_linkup == 0) {
   4412    1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   4413  1.160  christos 		    ("%s: LINK: checklink -> up %s\n", device_xname(sc->sc_dev),
   4414    1.1   thorpej 		    (status & STATUS_FD) ? "FDX" : "HDX"));
   4415    1.1   thorpej 		sc->sc_tbi_linkup = 1;
   4416    1.1   thorpej 	}
   4417    1.1   thorpej 
   4418  1.173   msaitoh 	if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP)
   4419  1.173   msaitoh 	    && ((status & STATUS_LU) == 0)) {
   4420  1.173   msaitoh 		sc->sc_tbi_linkup = 0;
   4421  1.173   msaitoh 		if (sc->sc_tbi_nrxcfg - sc->sc_tbi_lastnrxcfg > 100) {
   4422  1.173   msaitoh 			/* RXCFG storm! */
   4423  1.173   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("RXCFG storm! (%d)\n",
   4424  1.173   msaitoh 				sc->sc_tbi_nrxcfg - sc->sc_tbi_lastnrxcfg));
   4425  1.173   msaitoh 			wm_init(ifp);
   4426  1.173   msaitoh 			wm_start(ifp);
   4427  1.173   msaitoh 		} else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   4428  1.173   msaitoh 			/* If the timer expired, retry autonegotiation */
   4429  1.173   msaitoh 			if (++sc->sc_tbi_ticks >= sc->sc_tbi_anegticks) {
   4430  1.173   msaitoh 				DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
   4431  1.173   msaitoh 				sc->sc_tbi_ticks = 0;
   4432  1.173   msaitoh 				/*
   4433  1.173   msaitoh 				 * Reset the link, and let autonegotiation do
   4434  1.173   msaitoh 				 * its thing
   4435  1.173   msaitoh 				 */
   4436  1.173   msaitoh 				sc->sc_ctrl |= CTRL_LRST;
   4437  1.173   msaitoh 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4438  1.173   msaitoh 				delay(1000);
   4439  1.173   msaitoh 				sc->sc_ctrl &= ~CTRL_LRST;
   4440  1.173   msaitoh 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4441  1.173   msaitoh 				delay(1000);
   4442  1.173   msaitoh 				CSR_WRITE(sc, WMREG_TXCW,
   4443  1.173   msaitoh 				    sc->sc_txcw & ~TXCW_ANE);
   4444  1.173   msaitoh 				CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   4445  1.173   msaitoh 			}
   4446  1.173   msaitoh 		}
   4447  1.173   msaitoh 	}
   4448  1.173   msaitoh 
   4449    1.1   thorpej 	wm_tbi_set_linkled(sc);
   4450    1.1   thorpej }
   4451    1.1   thorpej 
   4452    1.1   thorpej /*
   4453    1.1   thorpej  * wm_gmii_reset:
   4454    1.1   thorpej  *
   4455    1.1   thorpej  *	Reset the PHY.
   4456    1.1   thorpej  */
   4457   1.47   thorpej static void
   4458    1.1   thorpej wm_gmii_reset(struct wm_softc *sc)
   4459    1.1   thorpej {
   4460    1.1   thorpej 	uint32_t reg;
   4461  1.127    bouyer 	int func = 0; /* XXX gcc */
   4462    1.1   thorpej 
   4463  1.167   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4464  1.167   msaitoh 	    || (sc->sc_type == WM_T_ICH10)) {
   4465  1.169   msaitoh 		if (wm_get_swfwhw_semaphore(sc)) {
   4466  1.169   msaitoh 			aprint_error_dev(sc->sc_dev,
   4467  1.169   msaitoh 			    "%s: failed to get semaphore\n", __func__);
   4468  1.139    bouyer 			return;
   4469  1.169   msaitoh 		}
   4470  1.139    bouyer 	}
   4471  1.139    bouyer 	if (sc->sc_type == WM_T_80003) {
   4472  1.127    bouyer 		func = (CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1;
   4473  1.127    bouyer 		if (wm_get_swfw_semaphore(sc,
   4474  1.169   msaitoh 			func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) {
   4475  1.169   msaitoh 			aprint_error_dev(sc->sc_dev,
   4476  1.169   msaitoh 			    "%s: failed to get semaphore\n", __func__);
   4477  1.127    bouyer 			return;
   4478  1.169   msaitoh 		}
   4479  1.127    bouyer 	}
   4480   1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   4481    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   4482    1.1   thorpej 		delay(20000);
   4483    1.1   thorpej 
   4484    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4485    1.1   thorpej 		delay(20000);
   4486    1.1   thorpej 	} else {
   4487  1.148    simonb 		/*
   4488  1.148    simonb 		 * With 82543, we need to force speed and duplex on the MAC
   4489  1.148    simonb 		 * equal to what the PHY speed and duplex configuration is.
   4490  1.148    simonb 		 * In addition, we need to perform a hardware reset on the PHY
   4491  1.148    simonb 		 * to take it out of reset.
   4492  1.148    simonb 		 */
   4493  1.148    simonb 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
   4494  1.148    simonb 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4495  1.133   msaitoh 
   4496    1.1   thorpej 		/* The PHY reset pin is active-low. */
   4497    1.1   thorpej 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   4498    1.1   thorpej 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
   4499    1.1   thorpej 		    CTRL_EXT_SWDPIN(4));
   4500    1.1   thorpej 		reg |= CTRL_EXT_SWDPIO(4);
   4501    1.1   thorpej 
   4502    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   4503    1.1   thorpej 		delay(10);
   4504    1.1   thorpej 
   4505    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4506  1.133   msaitoh 		delay(10000);
   4507    1.1   thorpej 
   4508    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   4509    1.1   thorpej 		delay(10);
   4510    1.1   thorpej #if 0
   4511    1.1   thorpej 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
   4512    1.1   thorpej #endif
   4513    1.1   thorpej 	}
   4514  1.167   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4515  1.167   msaitoh 	    || (sc->sc_type == WM_T_ICH10))
   4516  1.139    bouyer 		wm_put_swfwhw_semaphore(sc);
   4517  1.139    bouyer 	if (sc->sc_type == WM_T_80003)
   4518  1.127    bouyer 		wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM);
   4519    1.1   thorpej }
   4520    1.1   thorpej 
   4521    1.1   thorpej /*
   4522    1.1   thorpej  * wm_gmii_mediainit:
   4523    1.1   thorpej  *
   4524    1.1   thorpej  *	Initialize media for use on 1000BASE-T devices.
   4525    1.1   thorpej  */
   4526   1.47   thorpej static void
   4527    1.1   thorpej wm_gmii_mediainit(struct wm_softc *sc)
   4528    1.1   thorpej {
   4529    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   4530    1.1   thorpej 
   4531    1.1   thorpej 	/* We have MII. */
   4532    1.1   thorpej 	sc->sc_flags |= WM_F_HAS_MII;
   4533    1.1   thorpej 
   4534  1.177   msaitoh 	if (sc->sc_type == WM_T_80003)
   4535  1.127    bouyer 		sc->sc_tipg =  TIPG_1000T_80003_DFLT;
   4536  1.127    bouyer 	else
   4537  1.127    bouyer 		sc->sc_tipg = TIPG_1000T_DFLT;
   4538    1.1   thorpej 
   4539    1.1   thorpej 	/*
   4540    1.1   thorpej 	 * Let the chip set speed/duplex on its own based on
   4541    1.1   thorpej 	 * signals from the PHY.
   4542  1.127    bouyer 	 * XXXbouyer - I'm not sure this is right for the 80003,
   4543  1.127    bouyer 	 * the em driver only sets CTRL_SLU here - but it seems to work.
   4544    1.1   thorpej 	 */
   4545  1.133   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   4546    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4547    1.1   thorpej 
   4548    1.1   thorpej 	/* Initialize our media structures and probe the GMII. */
   4549    1.1   thorpej 	sc->sc_mii.mii_ifp = ifp;
   4550    1.1   thorpej 
   4551  1.167   msaitoh 	if (sc->sc_type == WM_T_ICH10) {
   4552  1.167   msaitoh 		sc->sc_mii.mii_readreg = wm_gmii_bm_readreg;
   4553  1.167   msaitoh 		sc->sc_mii.mii_writereg = wm_gmii_bm_writereg;
   4554  1.167   msaitoh 	} else if (sc->sc_type >= WM_T_80003) {
   4555  1.127    bouyer 		sc->sc_mii.mii_readreg = wm_gmii_i80003_readreg;
   4556  1.127    bouyer 		sc->sc_mii.mii_writereg = wm_gmii_i80003_writereg;
   4557  1.127    bouyer 	} else if (sc->sc_type >= WM_T_82544) {
   4558   1.11   thorpej 		sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
   4559   1.11   thorpej 		sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
   4560    1.1   thorpej 	} else {
   4561   1.11   thorpej 		sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg;
   4562   1.11   thorpej 		sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg;
   4563    1.1   thorpej 	}
   4564    1.1   thorpej 	sc->sc_mii.mii_statchg = wm_gmii_statchg;
   4565    1.1   thorpej 
   4566    1.1   thorpej 	wm_gmii_reset(sc);
   4567    1.1   thorpej 
   4568  1.152    dyoung 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   4569   1.26      fair 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
   4570    1.1   thorpej 	    wm_gmii_mediastatus);
   4571    1.1   thorpej 
   4572  1.160  christos 	mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   4573   1.71   thorpej 	    MII_OFFSET_ANY, MIIF_DOPAUSE);
   4574    1.1   thorpej 	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
   4575    1.1   thorpej 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
   4576    1.1   thorpej 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
   4577    1.1   thorpej 	} else
   4578    1.1   thorpej 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
   4579    1.1   thorpej }
   4580    1.1   thorpej 
   4581    1.1   thorpej /*
   4582    1.1   thorpej  * wm_gmii_mediastatus:	[ifmedia interface function]
   4583    1.1   thorpej  *
   4584    1.1   thorpej  *	Get the current interface media status on a 1000BASE-T device.
   4585    1.1   thorpej  */
   4586   1.47   thorpej static void
   4587    1.1   thorpej wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   4588    1.1   thorpej {
   4589    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   4590    1.1   thorpej 
   4591  1.152    dyoung 	ether_mediastatus(ifp, ifmr);
   4592  1.152    dyoung 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) |
   4593   1.71   thorpej 			   sc->sc_flowflags;
   4594    1.1   thorpej }
   4595    1.1   thorpej 
   4596    1.1   thorpej /*
   4597    1.1   thorpej  * wm_gmii_mediachange:	[ifmedia interface function]
   4598    1.1   thorpej  *
   4599    1.1   thorpej  *	Set hardware to newly-selected media on a 1000BASE-T device.
   4600    1.1   thorpej  */
   4601   1.47   thorpej static int
   4602    1.1   thorpej wm_gmii_mediachange(struct ifnet *ifp)
   4603    1.1   thorpej {
   4604    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   4605  1.127    bouyer 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   4606  1.152    dyoung 	int rc;
   4607    1.1   thorpej 
   4608  1.152    dyoung 	if ((ifp->if_flags & IFF_UP) == 0)
   4609  1.152    dyoung 		return 0;
   4610  1.152    dyoung 
   4611  1.152    dyoung 	sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
   4612  1.152    dyoung 	sc->sc_ctrl |= CTRL_SLU;
   4613  1.152    dyoung 	if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   4614  1.152    dyoung 	    || (sc->sc_type > WM_T_82543)) {
   4615  1.152    dyoung 		sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX);
   4616  1.152    dyoung 	} else {
   4617  1.152    dyoung 		sc->sc_ctrl &= ~CTRL_ASDE;
   4618  1.152    dyoung 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
   4619  1.152    dyoung 		if (ife->ifm_media & IFM_FDX)
   4620  1.152    dyoung 			sc->sc_ctrl |= CTRL_FD;
   4621  1.152    dyoung 		switch(IFM_SUBTYPE(ife->ifm_media)) {
   4622  1.152    dyoung 		case IFM_10_T:
   4623  1.152    dyoung 			sc->sc_ctrl |= CTRL_SPEED_10;
   4624  1.152    dyoung 			break;
   4625  1.152    dyoung 		case IFM_100_TX:
   4626  1.152    dyoung 			sc->sc_ctrl |= CTRL_SPEED_100;
   4627  1.152    dyoung 			break;
   4628  1.152    dyoung 		case IFM_1000_T:
   4629  1.152    dyoung 			sc->sc_ctrl |= CTRL_SPEED_1000;
   4630  1.152    dyoung 			break;
   4631  1.152    dyoung 		default:
   4632  1.152    dyoung 			panic("wm_gmii_mediachange: bad media 0x%x",
   4633  1.152    dyoung 			    ife->ifm_media);
   4634  1.127    bouyer 		}
   4635  1.127    bouyer 	}
   4636  1.152    dyoung 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4637  1.152    dyoung 	if (sc->sc_type <= WM_T_82543)
   4638  1.152    dyoung 		wm_gmii_reset(sc);
   4639  1.152    dyoung 
   4640  1.152    dyoung 	if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
   4641  1.152    dyoung 		return 0;
   4642  1.152    dyoung 	return rc;
   4643    1.1   thorpej }
   4644    1.1   thorpej 
   4645    1.1   thorpej #define	MDI_IO		CTRL_SWDPIN(2)
   4646    1.1   thorpej #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
   4647    1.1   thorpej #define	MDI_CLK		CTRL_SWDPIN(3)
   4648    1.1   thorpej 
   4649    1.1   thorpej static void
   4650   1.11   thorpej i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
   4651    1.1   thorpej {
   4652    1.1   thorpej 	uint32_t i, v;
   4653    1.1   thorpej 
   4654    1.1   thorpej 	v = CSR_READ(sc, WMREG_CTRL);
   4655    1.1   thorpej 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   4656    1.1   thorpej 	v |= MDI_DIR | CTRL_SWDPIO(3);
   4657    1.1   thorpej 
   4658    1.1   thorpej 	for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
   4659    1.1   thorpej 		if (data & i)
   4660    1.1   thorpej 			v |= MDI_IO;
   4661    1.1   thorpej 		else
   4662    1.1   thorpej 			v &= ~MDI_IO;
   4663    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v);
   4664    1.1   thorpej 		delay(10);
   4665    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   4666    1.1   thorpej 		delay(10);
   4667    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v);
   4668    1.1   thorpej 		delay(10);
   4669    1.1   thorpej 	}
   4670    1.1   thorpej }
   4671    1.1   thorpej 
   4672    1.1   thorpej static uint32_t
   4673   1.11   thorpej i82543_mii_recvbits(struct wm_softc *sc)
   4674    1.1   thorpej {
   4675    1.1   thorpej 	uint32_t v, i, data = 0;
   4676    1.1   thorpej 
   4677    1.1   thorpej 	v = CSR_READ(sc, WMREG_CTRL);
   4678    1.1   thorpej 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   4679    1.1   thorpej 	v |= CTRL_SWDPIO(3);
   4680    1.1   thorpej 
   4681    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v);
   4682    1.1   thorpej 	delay(10);
   4683    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   4684    1.1   thorpej 	delay(10);
   4685    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v);
   4686    1.1   thorpej 	delay(10);
   4687    1.1   thorpej 
   4688    1.1   thorpej 	for (i = 0; i < 16; i++) {
   4689    1.1   thorpej 		data <<= 1;
   4690    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   4691    1.1   thorpej 		delay(10);
   4692    1.1   thorpej 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
   4693    1.1   thorpej 			data |= 1;
   4694    1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v);
   4695    1.1   thorpej 		delay(10);
   4696    1.1   thorpej 	}
   4697    1.1   thorpej 
   4698    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   4699    1.1   thorpej 	delay(10);
   4700    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v);
   4701    1.1   thorpej 	delay(10);
   4702    1.1   thorpej 
   4703    1.1   thorpej 	return (data);
   4704    1.1   thorpej }
   4705    1.1   thorpej 
   4706    1.1   thorpej #undef MDI_IO
   4707    1.1   thorpej #undef MDI_DIR
   4708    1.1   thorpej #undef MDI_CLK
   4709    1.1   thorpej 
   4710    1.1   thorpej /*
   4711   1.11   thorpej  * wm_gmii_i82543_readreg:	[mii interface function]
   4712    1.1   thorpej  *
   4713   1.11   thorpej  *	Read a PHY register on the GMII (i82543 version).
   4714    1.1   thorpej  */
   4715   1.47   thorpej static int
   4716  1.157    dyoung wm_gmii_i82543_readreg(device_t self, int phy, int reg)
   4717    1.1   thorpej {
   4718  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   4719    1.1   thorpej 	int rv;
   4720    1.1   thorpej 
   4721   1.11   thorpej 	i82543_mii_sendbits(sc, 0xffffffffU, 32);
   4722   1.11   thorpej 	i82543_mii_sendbits(sc, reg | (phy << 5) |
   4723    1.1   thorpej 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
   4724   1.11   thorpej 	rv = i82543_mii_recvbits(sc) & 0xffff;
   4725    1.1   thorpej 
   4726    1.1   thorpej 	DPRINTF(WM_DEBUG_GMII,
   4727    1.1   thorpej 	    ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
   4728  1.160  christos 	    device_xname(sc->sc_dev), phy, reg, rv));
   4729    1.1   thorpej 
   4730    1.1   thorpej 	return (rv);
   4731    1.1   thorpej }
   4732    1.1   thorpej 
   4733    1.1   thorpej /*
   4734   1.11   thorpej  * wm_gmii_i82543_writereg:	[mii interface function]
   4735    1.1   thorpej  *
   4736   1.11   thorpej  *	Write a PHY register on the GMII (i82543 version).
   4737    1.1   thorpej  */
   4738   1.47   thorpej static void
   4739  1.157    dyoung wm_gmii_i82543_writereg(device_t self, int phy, int reg, int val)
   4740    1.1   thorpej {
   4741  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   4742    1.1   thorpej 
   4743   1.11   thorpej 	i82543_mii_sendbits(sc, 0xffffffffU, 32);
   4744   1.11   thorpej 	i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
   4745    1.1   thorpej 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
   4746    1.1   thorpej 	    (MII_COMMAND_START << 30), 32);
   4747    1.1   thorpej }
   4748    1.1   thorpej 
   4749    1.1   thorpej /*
   4750   1.11   thorpej  * wm_gmii_i82544_readreg:	[mii interface function]
   4751    1.1   thorpej  *
   4752    1.1   thorpej  *	Read a PHY register on the GMII.
   4753    1.1   thorpej  */
   4754   1.47   thorpej static int
   4755  1.157    dyoung wm_gmii_i82544_readreg(device_t self, int phy, int reg)
   4756    1.1   thorpej {
   4757  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   4758   1.60    ichiro 	uint32_t mdic = 0;
   4759    1.1   thorpej 	int i, rv;
   4760    1.1   thorpej 
   4761    1.1   thorpej 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
   4762    1.1   thorpej 	    MDIC_REGADD(reg));
   4763    1.1   thorpej 
   4764  1.127    bouyer 	for (i = 0; i < 320; i++) {
   4765    1.1   thorpej 		mdic = CSR_READ(sc, WMREG_MDIC);
   4766    1.1   thorpej 		if (mdic & MDIC_READY)
   4767    1.1   thorpej 			break;
   4768    1.1   thorpej 		delay(10);
   4769    1.1   thorpej 	}
   4770    1.1   thorpej 
   4771    1.1   thorpej 	if ((mdic & MDIC_READY) == 0) {
   4772   1.84   thorpej 		log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
   4773  1.160  christos 		    device_xname(sc->sc_dev), phy, reg);
   4774    1.1   thorpej 		rv = 0;
   4775    1.1   thorpej 	} else if (mdic & MDIC_E) {
   4776    1.1   thorpej #if 0 /* This is normal if no PHY is present. */
   4777   1.84   thorpej 		log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
   4778  1.160  christos 		    device_xname(sc->sc_dev), phy, reg);
   4779    1.1   thorpej #endif
   4780    1.1   thorpej 		rv = 0;
   4781    1.1   thorpej 	} else {
   4782    1.1   thorpej 		rv = MDIC_DATA(mdic);
   4783    1.1   thorpej 		if (rv == 0xffff)
   4784    1.1   thorpej 			rv = 0;
   4785    1.1   thorpej 	}
   4786    1.1   thorpej 
   4787    1.1   thorpej 	return (rv);
   4788    1.1   thorpej }
   4789    1.1   thorpej 
   4790    1.1   thorpej /*
   4791   1.11   thorpej  * wm_gmii_i82544_writereg:	[mii interface function]
   4792    1.1   thorpej  *
   4793    1.1   thorpej  *	Write a PHY register on the GMII.
   4794    1.1   thorpej  */
   4795   1.47   thorpej static void
   4796  1.157    dyoung wm_gmii_i82544_writereg(device_t self, int phy, int reg, int val)
   4797    1.1   thorpej {
   4798  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   4799   1.60    ichiro 	uint32_t mdic = 0;
   4800    1.1   thorpej 	int i;
   4801    1.1   thorpej 
   4802    1.1   thorpej 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
   4803    1.1   thorpej 	    MDIC_REGADD(reg) | MDIC_DATA(val));
   4804    1.1   thorpej 
   4805  1.127    bouyer 	for (i = 0; i < 320; i++) {
   4806    1.1   thorpej 		mdic = CSR_READ(sc, WMREG_MDIC);
   4807    1.1   thorpej 		if (mdic & MDIC_READY)
   4808    1.1   thorpej 			break;
   4809    1.1   thorpej 		delay(10);
   4810    1.1   thorpej 	}
   4811    1.1   thorpej 
   4812    1.1   thorpej 	if ((mdic & MDIC_READY) == 0)
   4813   1.84   thorpej 		log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n",
   4814  1.160  christos 		    device_xname(sc->sc_dev), phy, reg);
   4815    1.1   thorpej 	else if (mdic & MDIC_E)
   4816   1.84   thorpej 		log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n",
   4817  1.160  christos 		    device_xname(sc->sc_dev), phy, reg);
   4818    1.1   thorpej }
   4819    1.1   thorpej 
   4820    1.1   thorpej /*
   4821  1.127    bouyer  * wm_gmii_i80003_readreg:	[mii interface function]
   4822  1.127    bouyer  *
   4823  1.127    bouyer  *	Read a PHY register on the kumeran
   4824  1.127    bouyer  * This could be handled by the PHY layer if we didn't have to lock the
   4825  1.127    bouyer  * ressource ...
   4826  1.127    bouyer  */
   4827  1.127    bouyer static int
   4828  1.157    dyoung wm_gmii_i80003_readreg(device_t self, int phy, int reg)
   4829  1.127    bouyer {
   4830  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   4831  1.127    bouyer 	int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1);
   4832  1.127    bouyer 	int rv;
   4833  1.127    bouyer 
   4834  1.127    bouyer 	if (phy != 1) /* only one PHY on kumeran bus */
   4835  1.127    bouyer 		return 0;
   4836  1.127    bouyer 
   4837  1.169   msaitoh 	if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) {
   4838  1.169   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   4839  1.169   msaitoh 		    __func__);
   4840  1.127    bouyer 		return 0;
   4841  1.169   msaitoh 	}
   4842  1.127    bouyer 
   4843  1.127    bouyer 	if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
   4844  1.127    bouyer 		wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
   4845  1.127    bouyer 		    reg >> GG82563_PAGE_SHIFT);
   4846  1.127    bouyer 	} else {
   4847  1.127    bouyer 		wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT,
   4848  1.127    bouyer 		    reg >> GG82563_PAGE_SHIFT);
   4849  1.127    bouyer 	}
   4850  1.168   msaitoh 	/* Wait more 200us for a bug of the ready bit in the MDIC register */
   4851  1.168   msaitoh 	delay(200);
   4852  1.168   msaitoh 	rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS);
   4853  1.168   msaitoh 	delay(200);
   4854  1.127    bouyer 
   4855  1.127    bouyer 	wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM);
   4856  1.127    bouyer 	return (rv);
   4857  1.127    bouyer }
   4858  1.127    bouyer 
   4859  1.127    bouyer /*
   4860  1.127    bouyer  * wm_gmii_i80003_writereg:	[mii interface function]
   4861  1.127    bouyer  *
   4862  1.127    bouyer  *	Write a PHY register on the kumeran.
   4863  1.127    bouyer  * This could be handled by the PHY layer if we didn't have to lock the
   4864  1.127    bouyer  * ressource ...
   4865  1.127    bouyer  */
   4866  1.127    bouyer static void
   4867  1.157    dyoung wm_gmii_i80003_writereg(device_t self, int phy, int reg, int val)
   4868  1.127    bouyer {
   4869  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   4870  1.127    bouyer 	int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1);
   4871  1.127    bouyer 
   4872  1.127    bouyer 	if (phy != 1) /* only one PHY on kumeran bus */
   4873  1.127    bouyer 		return;
   4874  1.127    bouyer 
   4875  1.169   msaitoh 	if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) {
   4876  1.169   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   4877  1.169   msaitoh 		    __func__);
   4878  1.127    bouyer 		return;
   4879  1.169   msaitoh 	}
   4880  1.127    bouyer 
   4881  1.127    bouyer 	if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
   4882  1.127    bouyer 		wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
   4883  1.127    bouyer 		    reg >> GG82563_PAGE_SHIFT);
   4884  1.127    bouyer 	} else {
   4885  1.127    bouyer 		wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT,
   4886  1.127    bouyer 		    reg >> GG82563_PAGE_SHIFT);
   4887  1.127    bouyer 	}
   4888  1.168   msaitoh 	/* Wait more 200us for a bug of the ready bit in the MDIC register */
   4889  1.168   msaitoh 	delay(200);
   4890  1.168   msaitoh 	wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val);
   4891  1.168   msaitoh 	delay(200);
   4892  1.127    bouyer 
   4893  1.127    bouyer 	wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM);
   4894  1.127    bouyer }
   4895  1.127    bouyer 
   4896  1.127    bouyer /*
   4897  1.167   msaitoh  * wm_gmii_bm_readreg:	[mii interface function]
   4898  1.167   msaitoh  *
   4899  1.167   msaitoh  *	Read a PHY register on the kumeran
   4900  1.167   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   4901  1.167   msaitoh  * ressource ...
   4902  1.167   msaitoh  */
   4903  1.167   msaitoh static int
   4904  1.167   msaitoh wm_gmii_bm_readreg(device_t self, int phy, int reg)
   4905  1.167   msaitoh {
   4906  1.167   msaitoh 	struct wm_softc *sc = device_private(self);
   4907  1.167   msaitoh 	int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1);
   4908  1.167   msaitoh 	int rv;
   4909  1.167   msaitoh 
   4910  1.169   msaitoh 	if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) {
   4911  1.169   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   4912  1.169   msaitoh 		    __func__);
   4913  1.167   msaitoh 		return 0;
   4914  1.169   msaitoh 	}
   4915  1.167   msaitoh 
   4916  1.167   msaitoh 	if (reg > GG82563_MAX_REG_ADDRESS) {
   4917  1.167   msaitoh 		if (phy == 1)
   4918  1.167   msaitoh 			wm_gmii_i82544_writereg(self, phy, 0x1f,
   4919  1.167   msaitoh 			    reg);
   4920  1.167   msaitoh 		else
   4921  1.167   msaitoh 			wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
   4922  1.167   msaitoh 			    reg >> GG82563_PAGE_SHIFT);
   4923  1.167   msaitoh 
   4924  1.167   msaitoh 	}
   4925  1.167   msaitoh 
   4926  1.167   msaitoh 	rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS);
   4927  1.167   msaitoh 	wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM);
   4928  1.167   msaitoh 	return (rv);
   4929  1.167   msaitoh }
   4930  1.167   msaitoh 
   4931  1.167   msaitoh /*
   4932  1.167   msaitoh  * wm_gmii_bm_writereg:	[mii interface function]
   4933  1.167   msaitoh  *
   4934  1.167   msaitoh  *	Write a PHY register on the kumeran.
   4935  1.167   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   4936  1.167   msaitoh  * ressource ...
   4937  1.167   msaitoh  */
   4938  1.167   msaitoh static void
   4939  1.167   msaitoh wm_gmii_bm_writereg(device_t self, int phy, int reg, int val)
   4940  1.167   msaitoh {
   4941  1.167   msaitoh 	struct wm_softc *sc = device_private(self);
   4942  1.167   msaitoh 	int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1);
   4943  1.167   msaitoh 
   4944  1.169   msaitoh 	if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) {
   4945  1.169   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   4946  1.169   msaitoh 		    __func__);
   4947  1.167   msaitoh 		return;
   4948  1.169   msaitoh 	}
   4949  1.167   msaitoh 
   4950  1.167   msaitoh 	if (reg > GG82563_MAX_REG_ADDRESS) {
   4951  1.167   msaitoh 		if (phy == 1)
   4952  1.167   msaitoh 			wm_gmii_i82544_writereg(self, phy, 0x1f,
   4953  1.167   msaitoh 			    reg);
   4954  1.167   msaitoh 		else
   4955  1.167   msaitoh 			wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
   4956  1.167   msaitoh 			    reg >> GG82563_PAGE_SHIFT);
   4957  1.167   msaitoh 
   4958  1.167   msaitoh 	}
   4959  1.167   msaitoh 
   4960  1.167   msaitoh 	wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val);
   4961  1.167   msaitoh 	wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM);
   4962  1.167   msaitoh }
   4963  1.167   msaitoh 
   4964  1.167   msaitoh /*
   4965    1.1   thorpej  * wm_gmii_statchg:	[mii interface function]
   4966    1.1   thorpej  *
   4967    1.1   thorpej  *	Callback from MII layer when media changes.
   4968    1.1   thorpej  */
   4969   1.47   thorpej static void
   4970  1.157    dyoung wm_gmii_statchg(device_t self)
   4971    1.1   thorpej {
   4972  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   4973   1.71   thorpej 	struct mii_data *mii = &sc->sc_mii;
   4974    1.1   thorpej 
   4975   1.71   thorpej 	sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
   4976    1.1   thorpej 	sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   4977   1.71   thorpej 	sc->sc_fcrtl &= ~FCRTL_XONE;
   4978   1.71   thorpej 
   4979   1.71   thorpej 	/*
   4980   1.71   thorpej 	 * Get flow control negotiation result.
   4981   1.71   thorpej 	 */
   4982   1.71   thorpej 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
   4983   1.71   thorpej 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
   4984   1.71   thorpej 		sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
   4985   1.71   thorpej 		mii->mii_media_active &= ~IFM_ETH_FMASK;
   4986   1.71   thorpej 	}
   4987   1.71   thorpej 
   4988   1.71   thorpej 	if (sc->sc_flowflags & IFM_FLOW) {
   4989   1.71   thorpej 		if (sc->sc_flowflags & IFM_ETH_TXPAUSE) {
   4990   1.71   thorpej 			sc->sc_ctrl |= CTRL_TFCE;
   4991   1.71   thorpej 			sc->sc_fcrtl |= FCRTL_XONE;
   4992   1.71   thorpej 		}
   4993   1.71   thorpej 		if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
   4994   1.71   thorpej 			sc->sc_ctrl |= CTRL_RFCE;
   4995   1.71   thorpej 	}
   4996    1.1   thorpej 
   4997    1.1   thorpej 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   4998    1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   4999  1.160  christos 		    ("%s: LINK: statchg: FDX\n", device_xname(sc->sc_dev)));
   5000    1.1   thorpej 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   5001    1.1   thorpej 	} else  {
   5002    1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   5003  1.160  christos 		    ("%s: LINK: statchg: HDX\n", device_xname(sc->sc_dev)));
   5004    1.1   thorpej 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   5005    1.1   thorpej 	}
   5006    1.1   thorpej 
   5007   1.71   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   5008    1.1   thorpej 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   5009   1.71   thorpej 	CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
   5010   1.71   thorpej 						 : WMREG_FCRTL, sc->sc_fcrtl);
   5011  1.178   msaitoh 	if (sc->sc_type == WM_T_80003) {
   5012  1.127    bouyer 		switch(IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
   5013  1.127    bouyer 		case IFM_1000_T:
   5014  1.178   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
   5015  1.127    bouyer 			    KUMCTRLSTA_HD_CTRL_1000_DEFAULT);
   5016  1.127    bouyer 			sc->sc_tipg =  TIPG_1000T_80003_DFLT;
   5017  1.127    bouyer 			break;
   5018  1.127    bouyer 		default:
   5019  1.178   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
   5020  1.127    bouyer 			    KUMCTRLSTA_HD_CTRL_10_100_DEFAULT);
   5021  1.127    bouyer 			sc->sc_tipg =  TIPG_10_100_80003_DFLT;
   5022  1.127    bouyer 			break;
   5023  1.127    bouyer 		}
   5024  1.127    bouyer 		CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   5025  1.127    bouyer 	}
   5026  1.127    bouyer }
   5027  1.127    bouyer 
   5028  1.127    bouyer /*
   5029  1.178   msaitoh  * wm_kmrn_readreg:
   5030  1.127    bouyer  *
   5031  1.127    bouyer  *	Read a kumeran register
   5032  1.127    bouyer  */
   5033  1.127    bouyer static int
   5034  1.178   msaitoh wm_kmrn_readreg(struct wm_softc *sc, int reg)
   5035  1.127    bouyer {
   5036  1.127    bouyer 	int rv;
   5037  1.127    bouyer 
   5038  1.178   msaitoh 	if (sc->sc_flags == WM_F_SWFW_SYNC) {
   5039  1.178   msaitoh 		if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) {
   5040  1.178   msaitoh 			aprint_error_dev(sc->sc_dev,
   5041  1.178   msaitoh 			    "%s: failed to get semaphore\n", __func__);
   5042  1.178   msaitoh 			return 0;
   5043  1.178   msaitoh 		}
   5044  1.178   msaitoh 	} else 	if (sc->sc_flags == WM_F_SWFWHW_SYNC) {
   5045  1.178   msaitoh 		if (wm_get_swfwhw_semaphore(sc)) {
   5046  1.178   msaitoh 			aprint_error_dev(sc->sc_dev,
   5047  1.178   msaitoh 			    "%s: failed to get semaphore\n", __func__);
   5048  1.178   msaitoh 			return 0;
   5049  1.178   msaitoh 		}
   5050  1.169   msaitoh 	}
   5051  1.127    bouyer 
   5052  1.127    bouyer 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
   5053  1.127    bouyer 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
   5054  1.127    bouyer 	    KUMCTRLSTA_REN);
   5055  1.127    bouyer 	delay(2);
   5056  1.127    bouyer 
   5057  1.127    bouyer 	rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
   5058  1.178   msaitoh 
   5059  1.178   msaitoh 	if (sc->sc_flags == WM_F_SWFW_SYNC)
   5060  1.178   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   5061  1.178   msaitoh 	else if (sc->sc_flags == WM_F_SWFWHW_SYNC)
   5062  1.178   msaitoh 		wm_put_swfwhw_semaphore(sc);
   5063  1.178   msaitoh 
   5064  1.127    bouyer 	return (rv);
   5065  1.127    bouyer }
   5066  1.127    bouyer 
   5067  1.127    bouyer /*
   5068  1.178   msaitoh  * wm_kmrn_writereg:
   5069  1.127    bouyer  *
   5070  1.127    bouyer  *	Write a kumeran register
   5071  1.127    bouyer  */
   5072  1.127    bouyer static void
   5073  1.178   msaitoh wm_kmrn_writereg(struct wm_softc *sc, int reg, int val)
   5074  1.127    bouyer {
   5075  1.127    bouyer 
   5076  1.178   msaitoh 	if (sc->sc_flags == WM_F_SWFW_SYNC) {
   5077  1.178   msaitoh 		if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) {
   5078  1.178   msaitoh 			aprint_error_dev(sc->sc_dev,
   5079  1.178   msaitoh 			    "%s: failed to get semaphore\n", __func__);
   5080  1.178   msaitoh 			return;
   5081  1.178   msaitoh 		}
   5082  1.178   msaitoh 	} else 	if (sc->sc_flags == WM_F_SWFWHW_SYNC) {
   5083  1.178   msaitoh 		if (wm_get_swfwhw_semaphore(sc)) {
   5084  1.178   msaitoh 			aprint_error_dev(sc->sc_dev,
   5085  1.178   msaitoh 			    "%s: failed to get semaphore\n", __func__);
   5086  1.178   msaitoh 			return;
   5087  1.178   msaitoh 		}
   5088  1.169   msaitoh 	}
   5089  1.127    bouyer 
   5090  1.127    bouyer 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
   5091  1.127    bouyer 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
   5092  1.127    bouyer 	    (val & KUMCTRLSTA_MASK));
   5093  1.178   msaitoh 
   5094  1.178   msaitoh 	if (sc->sc_flags == WM_F_SWFW_SYNC)
   5095  1.178   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   5096  1.178   msaitoh 	else if (sc->sc_flags == WM_F_SWFWHW_SYNC)
   5097  1.178   msaitoh 		wm_put_swfwhw_semaphore(sc);
   5098    1.1   thorpej }
   5099  1.117   msaitoh 
   5100  1.117   msaitoh static int
   5101  1.117   msaitoh wm_is_onboard_nvm_eeprom(struct wm_softc *sc)
   5102  1.117   msaitoh {
   5103  1.117   msaitoh 	uint32_t eecd = 0;
   5104  1.117   msaitoh 
   5105  1.165  sborrill 	if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574) {
   5106  1.117   msaitoh 		eecd = CSR_READ(sc, WMREG_EECD);
   5107  1.117   msaitoh 
   5108  1.117   msaitoh 		/* Isolate bits 15 & 16 */
   5109  1.117   msaitoh 		eecd = ((eecd >> 15) & 0x03);
   5110  1.117   msaitoh 
   5111  1.117   msaitoh 		/* If both bits are set, device is Flash type */
   5112  1.119  uebayasi 		if (eecd == 0x03) {
   5113  1.117   msaitoh 			return 0;
   5114  1.117   msaitoh 		}
   5115  1.117   msaitoh 	}
   5116  1.117   msaitoh 	return 1;
   5117  1.117   msaitoh }
   5118  1.117   msaitoh 
   5119  1.117   msaitoh static int
   5120  1.127    bouyer wm_get_swsm_semaphore(struct wm_softc *sc)
   5121  1.117   msaitoh {
   5122  1.117   msaitoh 	int32_t timeout;
   5123  1.117   msaitoh 	uint32_t swsm;
   5124  1.117   msaitoh 
   5125  1.117   msaitoh 	/* Get the FW semaphore. */
   5126  1.117   msaitoh 	timeout = 1000 + 1; /* XXX */
   5127  1.117   msaitoh 	while (timeout) {
   5128  1.117   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   5129  1.117   msaitoh 		swsm |= SWSM_SWESMBI;
   5130  1.117   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, swsm);
   5131  1.117   msaitoh 		/* if we managed to set the bit we got the semaphore. */
   5132  1.117   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   5133  1.119  uebayasi 		if (swsm & SWSM_SWESMBI)
   5134  1.117   msaitoh 			break;
   5135  1.117   msaitoh 
   5136  1.117   msaitoh 		delay(50);
   5137  1.117   msaitoh 		timeout--;
   5138  1.117   msaitoh 	}
   5139  1.117   msaitoh 
   5140  1.117   msaitoh 	if (timeout == 0) {
   5141  1.160  christos 		aprint_error_dev(sc->sc_dev, "could not acquire EEPROM GNT\n");
   5142  1.117   msaitoh 		/* Release semaphores */
   5143  1.127    bouyer 		wm_put_swsm_semaphore(sc);
   5144  1.117   msaitoh 		return 1;
   5145  1.117   msaitoh 	}
   5146  1.117   msaitoh 	return 0;
   5147  1.117   msaitoh }
   5148  1.117   msaitoh 
   5149  1.117   msaitoh static void
   5150  1.127    bouyer wm_put_swsm_semaphore(struct wm_softc *sc)
   5151  1.117   msaitoh {
   5152  1.117   msaitoh 	uint32_t swsm;
   5153  1.117   msaitoh 
   5154  1.117   msaitoh 	swsm = CSR_READ(sc, WMREG_SWSM);
   5155  1.119  uebayasi 	swsm &= ~(SWSM_SWESMBI);
   5156  1.117   msaitoh 	CSR_WRITE(sc, WMREG_SWSM, swsm);
   5157  1.117   msaitoh }
   5158  1.127    bouyer 
   5159  1.127    bouyer static int
   5160  1.136   msaitoh wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
   5161  1.136   msaitoh {
   5162  1.127    bouyer 	uint32_t swfw_sync;
   5163  1.127    bouyer 	uint32_t swmask = mask << SWFW_SOFT_SHIFT;
   5164  1.127    bouyer 	uint32_t fwmask = mask << SWFW_FIRM_SHIFT;
   5165  1.127    bouyer 	int timeout = 200;
   5166  1.127    bouyer 
   5167  1.127    bouyer 	for(timeout = 0; timeout < 200; timeout++) {
   5168  1.127    bouyer 		if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) {
   5169  1.169   msaitoh 			if (wm_get_swsm_semaphore(sc)) {
   5170  1.169   msaitoh 				aprint_error_dev(sc->sc_dev,
   5171  1.169   msaitoh 				    "%s: failed to get semaphore\n",
   5172  1.169   msaitoh 				    __func__);
   5173  1.127    bouyer 				return 1;
   5174  1.169   msaitoh 			}
   5175  1.127    bouyer 		}
   5176  1.127    bouyer 		swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
   5177  1.127    bouyer 		if ((swfw_sync & (swmask | fwmask)) == 0) {
   5178  1.127    bouyer 			swfw_sync |= swmask;
   5179  1.127    bouyer 			CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
   5180  1.127    bouyer 			if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE)
   5181  1.127    bouyer 				wm_put_swsm_semaphore(sc);
   5182  1.127    bouyer 			return 0;
   5183  1.127    bouyer 		}
   5184  1.127    bouyer 		if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE)
   5185  1.127    bouyer 			wm_put_swsm_semaphore(sc);
   5186  1.127    bouyer 		delay(5000);
   5187  1.127    bouyer 	}
   5188  1.127    bouyer 	printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n",
   5189  1.160  christos 	    device_xname(sc->sc_dev), mask, swfw_sync);
   5190  1.127    bouyer 	return 1;
   5191  1.127    bouyer }
   5192  1.127    bouyer 
   5193  1.127    bouyer static void
   5194  1.136   msaitoh wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
   5195  1.136   msaitoh {
   5196  1.127    bouyer 	uint32_t swfw_sync;
   5197  1.127    bouyer 
   5198  1.127    bouyer 	if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) {
   5199  1.127    bouyer 		while (wm_get_swsm_semaphore(sc) != 0)
   5200  1.127    bouyer 			continue;
   5201  1.127    bouyer 	}
   5202  1.127    bouyer 	swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
   5203  1.127    bouyer 	swfw_sync &= ~(mask << SWFW_SOFT_SHIFT);
   5204  1.127    bouyer 	CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
   5205  1.127    bouyer 	if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE)
   5206  1.127    bouyer 		wm_put_swsm_semaphore(sc);
   5207  1.127    bouyer }
   5208  1.139    bouyer 
   5209  1.139    bouyer static int
   5210  1.139    bouyer wm_get_swfwhw_semaphore(struct wm_softc *sc)
   5211  1.139    bouyer {
   5212  1.139    bouyer 	uint32_t ext_ctrl;
   5213  1.139    bouyer 	int timeout = 200;
   5214  1.139    bouyer 
   5215  1.139    bouyer 	for(timeout = 0; timeout < 200; timeout++) {
   5216  1.139    bouyer 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   5217  1.139    bouyer 		ext_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
   5218  1.139    bouyer 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   5219  1.139    bouyer 
   5220  1.139    bouyer 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   5221  1.139    bouyer 		if (ext_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
   5222  1.139    bouyer 			return 0;
   5223  1.139    bouyer 		delay(5000);
   5224  1.139    bouyer 	}
   5225  1.178   msaitoh 	printf("%s: failed to get swfwhw semaphore ext_ctrl 0x%x\n",
   5226  1.160  christos 	    device_xname(sc->sc_dev), ext_ctrl);
   5227  1.139    bouyer 	return 1;
   5228  1.139    bouyer }
   5229  1.139    bouyer 
   5230  1.139    bouyer static void
   5231  1.139    bouyer wm_put_swfwhw_semaphore(struct wm_softc *sc)
   5232  1.139    bouyer {
   5233  1.139    bouyer 	uint32_t ext_ctrl;
   5234  1.139    bouyer 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   5235  1.139    bouyer 	ext_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
   5236  1.139    bouyer 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   5237  1.139    bouyer }
   5238  1.139    bouyer 
   5239  1.169   msaitoh static int
   5240  1.169   msaitoh wm_valid_nvm_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank)
   5241  1.169   msaitoh {
   5242  1.169   msaitoh 	uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1;
   5243  1.169   msaitoh 	uint8_t bank_high_byte;
   5244  1.169   msaitoh 	uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t);
   5245  1.169   msaitoh 
   5246  1.169   msaitoh 	if (sc->sc_type != WM_T_ICH10) {
   5247  1.169   msaitoh 		/* Value of bit 22 corresponds to the flash bank we're on. */
   5248  1.169   msaitoh 		*bank = (CSR_READ(sc, WMREG_EECD) & EECD_SEC1VAL) ? 1 : 0;
   5249  1.169   msaitoh 	} else {
   5250  1.169   msaitoh 		wm_read_ich8_byte(sc, act_offset, &bank_high_byte);
   5251  1.169   msaitoh 		if ((bank_high_byte & 0xc0) == 0x80)
   5252  1.169   msaitoh 			*bank = 0;
   5253  1.169   msaitoh 		else {
   5254  1.169   msaitoh 			wm_read_ich8_byte(sc, act_offset + bank1_offset,
   5255  1.169   msaitoh 			    &bank_high_byte);
   5256  1.169   msaitoh 			if ((bank_high_byte & 0xc0) == 0x80)
   5257  1.169   msaitoh 				*bank = 1;
   5258  1.169   msaitoh 			else {
   5259  1.169   msaitoh 				aprint_error_dev(sc->sc_dev,
   5260  1.169   msaitoh 				    "EEPROM not present\n");
   5261  1.169   msaitoh 				return -1;
   5262  1.169   msaitoh 			}
   5263  1.169   msaitoh 		}
   5264  1.169   msaitoh 	}
   5265  1.169   msaitoh 
   5266  1.169   msaitoh 	return 0;
   5267  1.169   msaitoh }
   5268  1.169   msaitoh 
   5269  1.139    bouyer /******************************************************************************
   5270  1.139    bouyer  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
   5271  1.139    bouyer  * register.
   5272  1.139    bouyer  *
   5273  1.139    bouyer  * sc - Struct containing variables accessed by shared code
   5274  1.139    bouyer  * offset - offset of word in the EEPROM to read
   5275  1.139    bouyer  * data - word read from the EEPROM
   5276  1.139    bouyer  * words - number of words to read
   5277  1.139    bouyer  *****************************************************************************/
   5278  1.139    bouyer static int
   5279  1.139    bouyer wm_read_eeprom_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data)
   5280  1.139    bouyer {
   5281  1.139    bouyer     int32_t  error = 0;
   5282  1.139    bouyer     uint32_t flash_bank = 0;
   5283  1.139    bouyer     uint32_t act_offset = 0;
   5284  1.139    bouyer     uint32_t bank_offset = 0;
   5285  1.139    bouyer     uint16_t word = 0;
   5286  1.139    bouyer     uint16_t i = 0;
   5287  1.139    bouyer 
   5288  1.139    bouyer     /* We need to know which is the valid flash bank.  In the event
   5289  1.139    bouyer      * that we didn't allocate eeprom_shadow_ram, we may not be
   5290  1.139    bouyer      * managing flash_bank.  So it cannot be trusted and needs
   5291  1.139    bouyer      * to be updated with each read.
   5292  1.139    bouyer      */
   5293  1.169   msaitoh     error = wm_valid_nvm_bank_detect_ich8lan(sc, &flash_bank);
   5294  1.169   msaitoh     if (error) {
   5295  1.169   msaitoh 	    aprint_error_dev(sc->sc_dev, "%s: failed to detect NVM bank\n",
   5296  1.169   msaitoh 		    __func__);
   5297  1.169   msaitoh         return error;
   5298  1.167   msaitoh     }
   5299  1.139    bouyer 
   5300  1.139    bouyer     /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
   5301  1.139    bouyer     bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
   5302  1.139    bouyer 
   5303  1.139    bouyer     error = wm_get_swfwhw_semaphore(sc);
   5304  1.169   msaitoh     if (error) {
   5305  1.169   msaitoh 	    aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   5306  1.169   msaitoh 		__func__);
   5307  1.139    bouyer         return error;
   5308  1.169   msaitoh     }
   5309  1.139    bouyer 
   5310  1.139    bouyer     for (i = 0; i < words; i++) {
   5311  1.139    bouyer             /* The NVM part needs a byte offset, hence * 2 */
   5312  1.139    bouyer             act_offset = bank_offset + ((offset + i) * 2);
   5313  1.139    bouyer             error = wm_read_ich8_word(sc, act_offset, &word);
   5314  1.169   msaitoh             if (error) {
   5315  1.169   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to read NVM\n",
   5316  1.169   msaitoh 		    __func__);
   5317  1.139    bouyer                 break;
   5318  1.169   msaitoh 	    }
   5319  1.139    bouyer             data[i] = word;
   5320  1.139    bouyer     }
   5321  1.139    bouyer 
   5322  1.139    bouyer     wm_put_swfwhw_semaphore(sc);
   5323  1.139    bouyer     return error;
   5324  1.139    bouyer }
   5325  1.139    bouyer 
   5326  1.139    bouyer /******************************************************************************
   5327  1.139    bouyer  * This function does initial flash setup so that a new read/write/erase cycle
   5328  1.139    bouyer  * can be started.
   5329  1.139    bouyer  *
   5330  1.139    bouyer  * sc - The pointer to the hw structure
   5331  1.139    bouyer  ****************************************************************************/
   5332  1.139    bouyer static int32_t
   5333  1.139    bouyer wm_ich8_cycle_init(struct wm_softc *sc)
   5334  1.139    bouyer {
   5335  1.139    bouyer     uint16_t hsfsts;
   5336  1.139    bouyer     int32_t error = 1;
   5337  1.139    bouyer     int32_t i     = 0;
   5338  1.139    bouyer 
   5339  1.139    bouyer     hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   5340  1.139    bouyer 
   5341  1.139    bouyer     /* May be check the Flash Des Valid bit in Hw status */
   5342  1.139    bouyer     if ((hsfsts & HSFSTS_FLDVAL) == 0) {
   5343  1.139    bouyer         return error;
   5344  1.139    bouyer     }
   5345  1.139    bouyer 
   5346  1.139    bouyer     /* Clear FCERR in Hw status by writing 1 */
   5347  1.139    bouyer     /* Clear DAEL in Hw status by writing a 1 */
   5348  1.139    bouyer     hsfsts |= HSFSTS_ERR | HSFSTS_DAEL;
   5349  1.139    bouyer 
   5350  1.139    bouyer     ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   5351  1.139    bouyer 
   5352  1.139    bouyer     /* Either we should have a hardware SPI cycle in progress bit to check
   5353  1.139    bouyer      * against, in order to start a new cycle or FDONE bit should be changed
   5354  1.139    bouyer      * in the hardware so that it is 1 after harware reset, which can then be
   5355  1.139    bouyer      * used as an indication whether a cycle is in progress or has been
   5356  1.139    bouyer      * completed .. we should also have some software semaphore mechanism to
   5357  1.139    bouyer      * guard FDONE or the cycle in progress bit so that two threads access to
   5358  1.139    bouyer      * those bits can be sequentiallized or a way so that 2 threads dont
   5359  1.139    bouyer      * start the cycle at the same time */
   5360  1.139    bouyer 
   5361  1.139    bouyer     if ((hsfsts & HSFSTS_FLINPRO) == 0) {
   5362  1.139    bouyer         /* There is no cycle running at present, so we can start a cycle */
   5363  1.139    bouyer         /* Begin by setting Flash Cycle Done. */
   5364  1.139    bouyer         hsfsts |= HSFSTS_DONE;
   5365  1.139    bouyer         ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   5366  1.139    bouyer         error = 0;
   5367  1.139    bouyer     } else {
   5368  1.139    bouyer         /* otherwise poll for sometime so the current cycle has a chance
   5369  1.139    bouyer          * to end before giving up. */
   5370  1.139    bouyer         for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
   5371  1.139    bouyer             hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   5372  1.139    bouyer             if ((hsfsts & HSFSTS_FLINPRO) == 0) {
   5373  1.139    bouyer                 error = 0;
   5374  1.139    bouyer                 break;
   5375  1.139    bouyer             }
   5376  1.139    bouyer             delay(1);
   5377  1.139    bouyer         }
   5378  1.139    bouyer         if (error == 0) {
   5379  1.139    bouyer             /* Successful in waiting for previous cycle to timeout,
   5380  1.139    bouyer              * now set the Flash Cycle Done. */
   5381  1.139    bouyer             hsfsts |= HSFSTS_DONE;
   5382  1.139    bouyer             ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   5383  1.139    bouyer         }
   5384  1.139    bouyer     }
   5385  1.139    bouyer     return error;
   5386  1.139    bouyer }
   5387  1.139    bouyer 
   5388  1.139    bouyer /******************************************************************************
   5389  1.139    bouyer  * This function starts a flash cycle and waits for its completion
   5390  1.139    bouyer  *
   5391  1.139    bouyer  * sc - The pointer to the hw structure
   5392  1.139    bouyer  ****************************************************************************/
   5393  1.139    bouyer static int32_t
   5394  1.139    bouyer wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout)
   5395  1.139    bouyer {
   5396  1.139    bouyer     uint16_t hsflctl;
   5397  1.139    bouyer     uint16_t hsfsts;
   5398  1.139    bouyer     int32_t error = 1;
   5399  1.139    bouyer     uint32_t i = 0;
   5400  1.139    bouyer 
   5401  1.139    bouyer     /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
   5402  1.139    bouyer     hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
   5403  1.139    bouyer     hsflctl |= HSFCTL_GO;
   5404  1.139    bouyer     ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
   5405  1.139    bouyer 
   5406  1.139    bouyer     /* wait till FDONE bit is set to 1 */
   5407  1.139    bouyer     do {
   5408  1.139    bouyer         hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   5409  1.139    bouyer         if (hsfsts & HSFSTS_DONE)
   5410  1.139    bouyer             break;
   5411  1.139    bouyer         delay(1);
   5412  1.139    bouyer         i++;
   5413  1.139    bouyer     } while (i < timeout);
   5414  1.139    bouyer     if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0) {
   5415  1.139    bouyer         error = 0;
   5416  1.139    bouyer     }
   5417  1.139    bouyer     return error;
   5418  1.139    bouyer }
   5419  1.139    bouyer 
   5420  1.139    bouyer /******************************************************************************
   5421  1.139    bouyer  * Reads a byte or word from the NVM using the ICH8 flash access registers.
   5422  1.139    bouyer  *
   5423  1.139    bouyer  * sc - The pointer to the hw structure
   5424  1.139    bouyer  * index - The index of the byte or word to read.
   5425  1.139    bouyer  * size - Size of data to read, 1=byte 2=word
   5426  1.139    bouyer  * data - Pointer to the word to store the value read.
   5427  1.139    bouyer  *****************************************************************************/
   5428  1.139    bouyer static int32_t
   5429  1.139    bouyer wm_read_ich8_data(struct wm_softc *sc, uint32_t index,
   5430  1.139    bouyer                      uint32_t size, uint16_t* data)
   5431  1.139    bouyer {
   5432  1.139    bouyer     uint16_t hsfsts;
   5433  1.139    bouyer     uint16_t hsflctl;
   5434  1.139    bouyer     uint32_t flash_linear_address;
   5435  1.139    bouyer     uint32_t flash_data = 0;
   5436  1.139    bouyer     int32_t error = 1;
   5437  1.139    bouyer     int32_t count = 0;
   5438  1.139    bouyer 
   5439  1.139    bouyer     if (size < 1  || size > 2 || data == 0x0 ||
   5440  1.139    bouyer         index > ICH_FLASH_LINEAR_ADDR_MASK)
   5441  1.139    bouyer         return error;
   5442  1.139    bouyer 
   5443  1.139    bouyer     flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
   5444  1.139    bouyer                            sc->sc_ich8_flash_base;
   5445  1.139    bouyer 
   5446  1.139    bouyer     do {
   5447  1.139    bouyer         delay(1);
   5448  1.139    bouyer         /* Steps */
   5449  1.139    bouyer         error = wm_ich8_cycle_init(sc);
   5450  1.139    bouyer         if (error)
   5451  1.139    bouyer             break;
   5452  1.139    bouyer 
   5453  1.139    bouyer         hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
   5454  1.139    bouyer         /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
   5455  1.139    bouyer         hsflctl |=  ((size - 1) << HSFCTL_BCOUNT_SHIFT) & HSFCTL_BCOUNT_MASK;
   5456  1.139    bouyer         hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT;
   5457  1.139    bouyer         ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
   5458  1.139    bouyer 
   5459  1.139    bouyer         /* Write the last 24 bits of index into Flash Linear address field in
   5460  1.139    bouyer          * Flash Address */
   5461  1.139    bouyer         /* TODO: TBD maybe check the index against the size of flash */
   5462  1.139    bouyer 
   5463  1.139    bouyer         ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address);
   5464  1.139    bouyer 
   5465  1.139    bouyer         error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT);
   5466  1.139    bouyer 
   5467  1.139    bouyer         /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
   5468  1.139    bouyer          * sequence a few more times, else read in (shift in) the Flash Data0,
   5469  1.139    bouyer          * the order is least significant byte first msb to lsb */
   5470  1.139    bouyer         if (error == 0) {
   5471  1.139    bouyer             flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0);
   5472  1.139    bouyer             if (size == 1) {
   5473  1.139    bouyer                 *data = (uint8_t)(flash_data & 0x000000FF);
   5474  1.139    bouyer             } else if (size == 2) {
   5475  1.139    bouyer                 *data = (uint16_t)(flash_data & 0x0000FFFF);
   5476  1.139    bouyer             }
   5477  1.139    bouyer             break;
   5478  1.139    bouyer         } else {
   5479  1.139    bouyer             /* If we've gotten here, then things are probably completely hosed,
   5480  1.139    bouyer              * but if the error condition is detected, it won't hurt to give
   5481  1.139    bouyer              * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
   5482  1.139    bouyer              */
   5483  1.139    bouyer             hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   5484  1.139    bouyer             if (hsfsts & HSFSTS_ERR) {
   5485  1.139    bouyer                 /* Repeat for some time before giving up. */
   5486  1.139    bouyer                 continue;
   5487  1.139    bouyer             } else if ((hsfsts & HSFSTS_DONE) == 0) {
   5488  1.139    bouyer                 break;
   5489  1.139    bouyer             }
   5490  1.139    bouyer         }
   5491  1.139    bouyer     } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
   5492  1.139    bouyer 
   5493  1.139    bouyer     return error;
   5494  1.139    bouyer }
   5495  1.139    bouyer 
   5496  1.139    bouyer /******************************************************************************
   5497  1.139    bouyer  * Reads a single byte from the NVM using the ICH8 flash access registers.
   5498  1.139    bouyer  *
   5499  1.139    bouyer  * sc - pointer to wm_hw structure
   5500  1.139    bouyer  * index - The index of the byte to read.
   5501  1.139    bouyer  * data - Pointer to a byte to store the value read.
   5502  1.139    bouyer  *****************************************************************************/
   5503  1.139    bouyer static int32_t
   5504  1.139    bouyer wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data)
   5505  1.139    bouyer {
   5506  1.144   msaitoh     int32_t status;
   5507  1.139    bouyer     uint16_t word = 0;
   5508  1.139    bouyer 
   5509  1.139    bouyer     status = wm_read_ich8_data(sc, index, 1, &word);
   5510  1.139    bouyer     if (status == 0) {
   5511  1.139    bouyer         *data = (uint8_t)word;
   5512  1.139    bouyer     }
   5513  1.139    bouyer 
   5514  1.139    bouyer     return status;
   5515  1.139    bouyer }
   5516  1.139    bouyer 
   5517  1.139    bouyer /******************************************************************************
   5518  1.139    bouyer  * Reads a word from the NVM using the ICH8 flash access registers.
   5519  1.139    bouyer  *
   5520  1.139    bouyer  * sc - pointer to wm_hw structure
   5521  1.139    bouyer  * index - The starting byte index of the word to read.
   5522  1.139    bouyer  * data - Pointer to a word to store the value read.
   5523  1.139    bouyer  *****************************************************************************/
   5524  1.139    bouyer static int32_t
   5525  1.139    bouyer wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data)
   5526  1.139    bouyer {
   5527  1.144   msaitoh     int32_t status;
   5528  1.144   msaitoh 
   5529  1.139    bouyer     status = wm_read_ich8_data(sc, index, 2, data);
   5530  1.139    bouyer     return status;
   5531  1.139    bouyer }
   5532  1.169   msaitoh 
   5533  1.169   msaitoh static int
   5534  1.169   msaitoh wm_check_mng_mode(struct wm_softc *sc)
   5535  1.169   msaitoh {
   5536  1.169   msaitoh 	int rv;
   5537  1.169   msaitoh 
   5538  1.169   msaitoh 	switch (sc->sc_type) {
   5539  1.169   msaitoh 	case WM_T_ICH8:
   5540  1.169   msaitoh 	case WM_T_ICH9:
   5541  1.169   msaitoh 	case WM_T_ICH10:
   5542  1.169   msaitoh 		rv = wm_check_mng_mode_ich8lan(sc);
   5543  1.169   msaitoh 		break;
   5544  1.169   msaitoh #if 0
   5545  1.169   msaitoh 	case WM_T_82574:
   5546  1.169   msaitoh 		/*
   5547  1.169   msaitoh 		 * The function is provided in em driver, but it's not
   5548  1.169   msaitoh 		 * used. Why?
   5549  1.169   msaitoh 		 */
   5550  1.169   msaitoh 		rv = wm_check_mng_mode_82574(sc);
   5551  1.169   msaitoh 		break;
   5552  1.169   msaitoh #endif
   5553  1.169   msaitoh 	case WM_T_82571:
   5554  1.169   msaitoh 	case WM_T_82572:
   5555  1.169   msaitoh 	case WM_T_82573:
   5556  1.169   msaitoh 	case WM_T_80003:
   5557  1.169   msaitoh 		rv = wm_check_mng_mode_generic(sc);
   5558  1.169   msaitoh 		break;
   5559  1.169   msaitoh 	default:
   5560  1.169   msaitoh 		/* noting to do */
   5561  1.169   msaitoh 		rv = 0;
   5562  1.169   msaitoh 		break;
   5563  1.169   msaitoh 	}
   5564  1.169   msaitoh 
   5565  1.169   msaitoh 	return rv;
   5566  1.169   msaitoh }
   5567  1.169   msaitoh 
   5568  1.169   msaitoh static int
   5569  1.169   msaitoh wm_check_mng_mode_ich8lan(struct wm_softc *sc)
   5570  1.169   msaitoh {
   5571  1.169   msaitoh 	uint32_t fwsm;
   5572  1.169   msaitoh 
   5573  1.169   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   5574  1.169   msaitoh 
   5575  1.169   msaitoh 	if ((fwsm & FWSM_MODE_MASK) == (MNG_ICH_IAMT_MODE << FWSM_MODE_SHIFT))
   5576  1.169   msaitoh 		return 1;
   5577  1.169   msaitoh 
   5578  1.169   msaitoh 	return 0;
   5579  1.169   msaitoh }
   5580  1.169   msaitoh 
   5581  1.169   msaitoh #if 0
   5582  1.169   msaitoh static int
   5583  1.169   msaitoh wm_check_mng_mode_82574(struct wm_softc *sc)
   5584  1.169   msaitoh {
   5585  1.169   msaitoh 	uint16_t data;
   5586  1.169   msaitoh 
   5587  1.169   msaitoh 	wm_read_eeprom(sc, NVM_INIT_CONTROL2_REG, 1, &data);
   5588  1.169   msaitoh 
   5589  1.169   msaitoh 	if ((data & NVM_INIT_CTRL2_MNGM) != 0)
   5590  1.169   msaitoh 		return 1;
   5591  1.169   msaitoh 
   5592  1.169   msaitoh 	return 0;
   5593  1.169   msaitoh }
   5594  1.169   msaitoh #endif
   5595  1.169   msaitoh 
   5596  1.169   msaitoh static int
   5597  1.169   msaitoh wm_check_mng_mode_generic(struct wm_softc *sc)
   5598  1.169   msaitoh {
   5599  1.169   msaitoh 	uint32_t fwsm;
   5600  1.169   msaitoh 
   5601  1.169   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   5602  1.169   msaitoh 
   5603  1.169   msaitoh 	if ((fwsm & FWSM_MODE_MASK) == (MNG_IAMT_MODE << FWSM_MODE_SHIFT))
   5604  1.169   msaitoh 		return 1;
   5605  1.169   msaitoh 
   5606  1.169   msaitoh 	return 0;
   5607  1.169   msaitoh }
   5608  1.169   msaitoh 
   5609  1.169   msaitoh static void
   5610  1.169   msaitoh wm_get_hw_control(struct wm_softc *sc)
   5611  1.169   msaitoh {
   5612  1.169   msaitoh 	uint32_t reg;
   5613  1.169   msaitoh 
   5614  1.169   msaitoh 	switch (sc->sc_type) {
   5615  1.169   msaitoh 	case WM_T_82573:
   5616  1.169   msaitoh #if 0
   5617  1.169   msaitoh 	case WM_T_82574:
   5618  1.169   msaitoh 		/*
   5619  1.169   msaitoh 		 * FreeBSD's em driver has the function for 82574 to checks
   5620  1.169   msaitoh 		 * the management mode, but it's not used. Why?
   5621  1.169   msaitoh 		 */
   5622  1.169   msaitoh #endif
   5623  1.169   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   5624  1.169   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD);
   5625  1.169   msaitoh 		break;
   5626  1.169   msaitoh 	case WM_T_82571:
   5627  1.169   msaitoh 	case WM_T_82572:
   5628  1.169   msaitoh 	case WM_T_80003:
   5629  1.169   msaitoh 	case WM_T_ICH8:
   5630  1.169   msaitoh 	case WM_T_ICH9:
   5631  1.169   msaitoh 	case WM_T_ICH10:
   5632  1.169   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5633  1.169   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);
   5634  1.169   msaitoh 		break;
   5635  1.169   msaitoh 	default:
   5636  1.169   msaitoh 		break;
   5637  1.169   msaitoh 	}
   5638  1.169   msaitoh }
   5639  1.173   msaitoh 
   5640  1.173   msaitoh /* XXX Currently TBI only */
   5641  1.173   msaitoh static int
   5642  1.173   msaitoh wm_check_for_link(struct wm_softc *sc)
   5643  1.173   msaitoh {
   5644  1.173   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   5645  1.173   msaitoh 	uint32_t rxcw;
   5646  1.173   msaitoh 	uint32_t ctrl;
   5647  1.173   msaitoh 	uint32_t status;
   5648  1.173   msaitoh 	uint32_t sig;
   5649  1.173   msaitoh 
   5650  1.173   msaitoh 	rxcw = CSR_READ(sc, WMREG_RXCW);
   5651  1.173   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   5652  1.173   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   5653  1.173   msaitoh 
   5654  1.173   msaitoh 	sig = (sc->sc_type > WM_T_82544) ? CTRL_SWDPIN(1) : 0;
   5655  1.173   msaitoh 
   5656  1.173   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s: sig = %d, status_lu = %d, rxcw_c = %d\n",
   5657  1.173   msaitoh 		device_xname(sc->sc_dev), __func__,
   5658  1.173   msaitoh 		((ctrl & CTRL_SWDPIN(1)) == sig),
   5659  1.173   msaitoh 		((status & STATUS_LU) != 0),
   5660  1.173   msaitoh 		((rxcw & RXCW_C) != 0)
   5661  1.173   msaitoh 		    ));
   5662  1.173   msaitoh 
   5663  1.173   msaitoh 	/*
   5664  1.173   msaitoh 	 * SWDPIN   LU RXCW
   5665  1.173   msaitoh 	 *      0    0    0
   5666  1.173   msaitoh 	 *      0    0    1	(should not happen)
   5667  1.173   msaitoh 	 *      0    1    0	(should not happen)
   5668  1.173   msaitoh 	 *      0    1    1	(should not happen)
   5669  1.173   msaitoh 	 *      1    0    0	Disable autonego and force linkup
   5670  1.173   msaitoh 	 *      1    0    1	got /C/ but not linkup yet
   5671  1.173   msaitoh 	 *      1    1    0	(linkup)
   5672  1.173   msaitoh 	 *      1    1    1	If IFM_AUTO, back to autonego
   5673  1.173   msaitoh 	 *
   5674  1.173   msaitoh 	 */
   5675  1.173   msaitoh 	if (((ctrl & CTRL_SWDPIN(1)) == sig)
   5676  1.173   msaitoh 	    && ((status & STATUS_LU) == 0)
   5677  1.173   msaitoh 	    && ((rxcw & RXCW_C) == 0)) {
   5678  1.173   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: force linkup and fullduplex\n",
   5679  1.173   msaitoh 			__func__));
   5680  1.173   msaitoh 		sc->sc_tbi_linkup = 0;
   5681  1.173   msaitoh 		/* Disable auto-negotiation in the TXCW register */
   5682  1.173   msaitoh 		CSR_WRITE(sc, WMREG_TXCW, (sc->sc_txcw & ~TXCW_ANE));
   5683  1.173   msaitoh 
   5684  1.173   msaitoh 		/*
   5685  1.173   msaitoh 		 * Force link-up and also force full-duplex.
   5686  1.173   msaitoh 		 *
   5687  1.173   msaitoh 		 * NOTE: CTRL was updated TFCE and RFCE automatically,
   5688  1.173   msaitoh 		 * so we should update sc->sc_ctrl
   5689  1.173   msaitoh 		 */
   5690  1.173   msaitoh 		sc->sc_ctrl = ctrl | CTRL_SLU | CTRL_FD;
   5691  1.173   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   5692  1.173   msaitoh 	} else if(((status & STATUS_LU) != 0)
   5693  1.173   msaitoh 	    && ((rxcw & RXCW_C) != 0)
   5694  1.173   msaitoh 	    && (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)) {
   5695  1.173   msaitoh 		sc->sc_tbi_linkup = 1;
   5696  1.173   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: go back to autonego\n",
   5697  1.173   msaitoh 			__func__));
   5698  1.173   msaitoh 		CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   5699  1.173   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, (ctrl & ~CTRL_SLU));
   5700  1.173   msaitoh 	} else if (((ctrl & CTRL_SWDPIN(1)) == sig)
   5701  1.173   msaitoh 	    && ((rxcw & RXCW_C) != 0)) {
   5702  1.173   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("/C/"));
   5703  1.173   msaitoh 	} else {
   5704  1.173   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: %x,%x,%x\n", __func__, rxcw, ctrl,
   5705  1.173   msaitoh 			status));
   5706  1.173   msaitoh 	}
   5707  1.173   msaitoh 
   5708  1.173   msaitoh 	return 0;
   5709  1.173   msaitoh }
   5710