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if_wm.c revision 1.34
      1  1.34      kent /*	$NetBSD: if_wm.c,v 1.34 2003/04/05 13:23:17 kent Exp $	*/
      2   1.1   thorpej 
      3   1.1   thorpej /*
      4   1.1   thorpej  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
      5   1.1   thorpej  * All rights reserved.
      6   1.1   thorpej  *
      7   1.1   thorpej  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8   1.1   thorpej  *
      9   1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     10   1.1   thorpej  * modification, are permitted provided that the following conditions
     11   1.1   thorpej  * are met:
     12   1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     13   1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     14   1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     15   1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     16   1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     17   1.1   thorpej  * 3. All advertising materials mentioning features or use of this software
     18   1.1   thorpej  *    must display the following acknowledgement:
     19   1.1   thorpej  *	This product includes software developed for the NetBSD Project by
     20   1.1   thorpej  *	Wasabi Systems, Inc.
     21   1.1   thorpej  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22   1.1   thorpej  *    or promote products derived from this software without specific prior
     23   1.1   thorpej  *    written permission.
     24   1.1   thorpej  *
     25   1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26   1.1   thorpej  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27   1.1   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28   1.1   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29   1.1   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30   1.1   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31   1.1   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32   1.1   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33   1.1   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34   1.1   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35   1.1   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     36   1.1   thorpej  */
     37   1.1   thorpej 
     38   1.1   thorpej /*
     39  1.11   thorpej  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
     40   1.1   thorpej  *
     41   1.1   thorpej  * TODO (in order of importance):
     42   1.1   thorpej  *
     43  1.11   thorpej  *	- Make GMII work on the i82543.
     44   1.1   thorpej  *
     45  1.12   thorpej  *	- Fix hw VLAN assist.
     46   1.1   thorpej  *
     47   1.1   thorpej  *	- Jumbo frames -- requires changes to network stack due to
     48   1.1   thorpej  *	  lame buffer length handling on chip.
     49   1.1   thorpej  */
     50   1.1   thorpej 
     51   1.1   thorpej #include "bpfilter.h"
     52  1.21    itojun #include "rnd.h"
     53   1.1   thorpej 
     54   1.1   thorpej #include <sys/param.h>
     55   1.1   thorpej #include <sys/systm.h>
     56   1.1   thorpej #include <sys/callout.h>
     57   1.1   thorpej #include <sys/mbuf.h>
     58   1.1   thorpej #include <sys/malloc.h>
     59   1.1   thorpej #include <sys/kernel.h>
     60   1.1   thorpej #include <sys/socket.h>
     61   1.1   thorpej #include <sys/ioctl.h>
     62   1.1   thorpej #include <sys/errno.h>
     63   1.1   thorpej #include <sys/device.h>
     64   1.1   thorpej #include <sys/queue.h>
     65   1.1   thorpej 
     66   1.1   thorpej #include <uvm/uvm_extern.h>		/* for PAGE_SIZE */
     67   1.1   thorpej 
     68  1.21    itojun #if NRND > 0
     69  1.21    itojun #include <sys/rnd.h>
     70  1.21    itojun #endif
     71  1.21    itojun 
     72   1.1   thorpej #include <net/if.h>
     73   1.1   thorpej #include <net/if_dl.h>
     74   1.1   thorpej #include <net/if_media.h>
     75   1.1   thorpej #include <net/if_ether.h>
     76   1.1   thorpej 
     77   1.1   thorpej #if NBPFILTER > 0
     78   1.1   thorpej #include <net/bpf.h>
     79   1.1   thorpej #endif
     80   1.1   thorpej 
     81   1.1   thorpej #include <netinet/in.h>			/* XXX for struct ip */
     82   1.1   thorpej #include <netinet/in_systm.h>		/* XXX for struct ip */
     83   1.1   thorpej #include <netinet/ip.h>			/* XXX for struct ip */
     84  1.13   thorpej #include <netinet/tcp.h>		/* XXX for struct tcphdr */
     85   1.1   thorpej 
     86   1.1   thorpej #include <machine/bus.h>
     87   1.1   thorpej #include <machine/intr.h>
     88   1.1   thorpej #include <machine/endian.h>
     89   1.1   thorpej 
     90   1.1   thorpej #include <dev/mii/mii.h>
     91   1.1   thorpej #include <dev/mii/miivar.h>
     92   1.1   thorpej #include <dev/mii/mii_bitbang.h>
     93   1.1   thorpej 
     94   1.1   thorpej #include <dev/pci/pcireg.h>
     95   1.1   thorpej #include <dev/pci/pcivar.h>
     96   1.1   thorpej #include <dev/pci/pcidevs.h>
     97   1.1   thorpej 
     98   1.1   thorpej #include <dev/pci/if_wmreg.h>
     99   1.1   thorpej 
    100   1.1   thorpej #ifdef WM_DEBUG
    101   1.1   thorpej #define	WM_DEBUG_LINK		0x01
    102   1.1   thorpej #define	WM_DEBUG_TX		0x02
    103   1.1   thorpej #define	WM_DEBUG_RX		0x04
    104   1.1   thorpej #define	WM_DEBUG_GMII		0x08
    105   1.1   thorpej int	wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;
    106   1.1   thorpej 
    107   1.1   thorpej #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
    108   1.1   thorpej #else
    109   1.1   thorpej #define	DPRINTF(x, y)	/* nothing */
    110   1.1   thorpej #endif /* WM_DEBUG */
    111   1.1   thorpej 
    112   1.1   thorpej /*
    113   1.2   thorpej  * Transmit descriptor list size.  Due to errata, we can only have
    114   1.2   thorpej  * 256 hardware descriptors in the ring.  We tell the upper layers
    115  1.15    simonb  * that they can queue a lot of packets, and we go ahead and manage
    116   1.9   thorpej  * up to 64 of them at a time.  We allow up to 16 DMA segments per
    117   1.2   thorpej  * packet.
    118   1.1   thorpej  */
    119   1.2   thorpej #define	WM_NTXSEGS		16
    120   1.2   thorpej #define	WM_IFQUEUELEN		256
    121   1.9   thorpej #define	WM_TXQUEUELEN		64
    122   1.1   thorpej #define	WM_TXQUEUELEN_MASK	(WM_TXQUEUELEN - 1)
    123  1.10   thorpej #define	WM_TXQUEUE_GC		(WM_TXQUEUELEN / 8)
    124   1.2   thorpej #define	WM_NTXDESC		256
    125   1.1   thorpej #define	WM_NTXDESC_MASK		(WM_NTXDESC - 1)
    126   1.1   thorpej #define	WM_NEXTTX(x)		(((x) + 1) & WM_NTXDESC_MASK)
    127   1.1   thorpej #define	WM_NEXTTXS(x)		(((x) + 1) & WM_TXQUEUELEN_MASK)
    128   1.1   thorpej 
    129   1.1   thorpej /*
    130   1.1   thorpej  * Receive descriptor list size.  We have one Rx buffer for normal
    131   1.1   thorpej  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
    132  1.10   thorpej  * packet.  We allocate 256 receive descriptors, each with a 2k
    133  1.10   thorpej  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
    134   1.1   thorpej  */
    135  1.10   thorpej #define	WM_NRXDESC		256
    136   1.1   thorpej #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
    137   1.1   thorpej #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
    138   1.1   thorpej #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
    139   1.1   thorpej 
    140   1.1   thorpej /*
    141   1.1   thorpej  * Control structures are DMA'd to the i82542 chip.  We allocate them in
    142   1.1   thorpej  * a single clump that maps to a single DMA segment to make serveral things
    143   1.1   thorpej  * easier.
    144   1.1   thorpej  */
    145   1.1   thorpej struct wm_control_data {
    146   1.1   thorpej 	/*
    147   1.1   thorpej 	 * The transmit descriptors.
    148   1.1   thorpej 	 */
    149   1.1   thorpej 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC];
    150   1.1   thorpej 
    151   1.1   thorpej 	/*
    152   1.1   thorpej 	 * The receive descriptors.
    153   1.1   thorpej 	 */
    154   1.1   thorpej 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
    155   1.1   thorpej };
    156   1.1   thorpej 
    157   1.1   thorpej #define	WM_CDOFF(x)	offsetof(struct wm_control_data, x)
    158   1.1   thorpej #define	WM_CDTXOFF(x)	WM_CDOFF(wcd_txdescs[(x)])
    159   1.1   thorpej #define	WM_CDRXOFF(x)	WM_CDOFF(wcd_rxdescs[(x)])
    160   1.1   thorpej 
    161   1.1   thorpej /*
    162   1.1   thorpej  * Software state for transmit jobs.
    163   1.1   thorpej  */
    164   1.1   thorpej struct wm_txsoft {
    165   1.1   thorpej 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
    166   1.1   thorpej 	bus_dmamap_t txs_dmamap;	/* our DMA map */
    167   1.1   thorpej 	int txs_firstdesc;		/* first descriptor in packet */
    168   1.1   thorpej 	int txs_lastdesc;		/* last descriptor in packet */
    169   1.4   thorpej 	int txs_ndesc;			/* # of descriptors used */
    170   1.1   thorpej };
    171   1.1   thorpej 
    172   1.1   thorpej /*
    173   1.1   thorpej  * Software state for receive buffers.  Each descriptor gets a
    174   1.1   thorpej  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
    175   1.1   thorpej  * more than one buffer, we chain them together.
    176   1.1   thorpej  */
    177   1.1   thorpej struct wm_rxsoft {
    178   1.1   thorpej 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
    179   1.1   thorpej 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
    180   1.1   thorpej };
    181   1.1   thorpej 
    182   1.1   thorpej /*
    183   1.1   thorpej  * Software state per device.
    184   1.1   thorpej  */
    185   1.1   thorpej struct wm_softc {
    186   1.1   thorpej 	struct device sc_dev;		/* generic device information */
    187   1.1   thorpej 	bus_space_tag_t sc_st;		/* bus space tag */
    188   1.1   thorpej 	bus_space_handle_t sc_sh;	/* bus space handle */
    189   1.1   thorpej 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
    190   1.1   thorpej 	struct ethercom sc_ethercom;	/* ethernet common data */
    191   1.1   thorpej 	void *sc_sdhook;		/* shutdown hook */
    192   1.1   thorpej 
    193   1.1   thorpej 	int sc_type;			/* chip type; see below */
    194   1.1   thorpej 	int sc_flags;			/* flags; see below */
    195   1.1   thorpej 
    196   1.1   thorpej 	void *sc_ih;			/* interrupt cookie */
    197   1.1   thorpej 
    198   1.1   thorpej 	struct mii_data sc_mii;		/* MII/media information */
    199   1.1   thorpej 
    200   1.1   thorpej 	struct callout sc_tick_ch;	/* tick callout */
    201   1.1   thorpej 
    202   1.1   thorpej 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
    203   1.1   thorpej #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
    204   1.1   thorpej 
    205   1.1   thorpej 	/*
    206   1.1   thorpej 	 * Software state for the transmit and receive descriptors.
    207   1.1   thorpej 	 */
    208   1.1   thorpej 	struct wm_txsoft sc_txsoft[WM_TXQUEUELEN];
    209   1.1   thorpej 	struct wm_rxsoft sc_rxsoft[WM_NRXDESC];
    210   1.1   thorpej 
    211   1.1   thorpej 	/*
    212   1.1   thorpej 	 * Control data structures.
    213   1.1   thorpej 	 */
    214   1.1   thorpej 	struct wm_control_data *sc_control_data;
    215   1.1   thorpej #define	sc_txdescs	sc_control_data->wcd_txdescs
    216   1.1   thorpej #define	sc_rxdescs	sc_control_data->wcd_rxdescs
    217   1.1   thorpej 
    218   1.1   thorpej #ifdef WM_EVENT_COUNTERS
    219   1.1   thorpej 	/* Event counters. */
    220   1.1   thorpej 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
    221   1.1   thorpej 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
    222   1.8   thorpej 	struct evcnt sc_ev_txforceintr;	/* Tx interrupts forced */
    223   1.4   thorpej 	struct evcnt sc_ev_txdw;	/* Tx descriptor interrupts */
    224   1.4   thorpej 	struct evcnt sc_ev_txqe;	/* Tx queue empty interrupts */
    225   1.1   thorpej 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
    226   1.1   thorpej 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
    227   1.1   thorpej 
    228   1.1   thorpej 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
    229   1.1   thorpej 	struct evcnt sc_ev_rxtusum;	/* TCP/UDP cksums checked in-bound */
    230   1.1   thorpej 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
    231   1.1   thorpej 	struct evcnt sc_ev_txtusum;	/* TCP/UDP cksums comp. out-bound */
    232   1.1   thorpej 
    233   1.5   thorpej 	struct evcnt sc_ev_txctx_init;	/* Tx cksum context cache initialized */
    234   1.5   thorpej 	struct evcnt sc_ev_txctx_hit;	/* Tx cksum context cache hit */
    235   1.5   thorpej 	struct evcnt sc_ev_txctx_miss;	/* Tx cksum context cache miss */
    236   1.5   thorpej 
    237   1.2   thorpej 	struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
    238   1.1   thorpej 	struct evcnt sc_ev_txdrop;	/* Tx packets dropped (too many segs) */
    239   1.1   thorpej 
    240   1.1   thorpej 	struct evcnt sc_ev_tu;		/* Tx underrun */
    241   1.1   thorpej #endif /* WM_EVENT_COUNTERS */
    242   1.1   thorpej 
    243   1.1   thorpej 	bus_addr_t sc_tdt_reg;		/* offset of TDT register */
    244   1.1   thorpej 
    245   1.1   thorpej 	int	sc_txfree;		/* number of free Tx descriptors */
    246   1.1   thorpej 	int	sc_txnext;		/* next ready Tx descriptor */
    247   1.1   thorpej 
    248   1.1   thorpej 	int	sc_txsfree;		/* number of free Tx jobs */
    249   1.1   thorpej 	int	sc_txsnext;		/* next free Tx job */
    250   1.1   thorpej 	int	sc_txsdirty;		/* dirty Tx jobs */
    251   1.1   thorpej 
    252   1.7   thorpej 	uint32_t sc_txctx_ipcs;		/* cached Tx IP cksum ctx */
    253   1.7   thorpej 	uint32_t sc_txctx_tucs;		/* cached Tx TCP/UDP cksum ctx */
    254   1.5   thorpej 
    255   1.1   thorpej 	bus_addr_t sc_rdt_reg;		/* offset of RDT register */
    256   1.1   thorpej 
    257   1.1   thorpej 	int	sc_rxptr;		/* next ready Rx descriptor/queue ent */
    258   1.1   thorpej 	int	sc_rxdiscard;
    259   1.1   thorpej 	int	sc_rxlen;
    260   1.1   thorpej 	struct mbuf *sc_rxhead;
    261   1.1   thorpej 	struct mbuf *sc_rxtail;
    262   1.1   thorpej 	struct mbuf **sc_rxtailp;
    263   1.1   thorpej 
    264   1.1   thorpej 	uint32_t sc_ctrl;		/* prototype CTRL register */
    265   1.1   thorpej #if 0
    266   1.1   thorpej 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
    267   1.1   thorpej #endif
    268   1.1   thorpej 	uint32_t sc_icr;		/* prototype interrupt bits */
    269   1.1   thorpej 	uint32_t sc_tctl;		/* prototype TCTL register */
    270   1.1   thorpej 	uint32_t sc_rctl;		/* prototype RCTL register */
    271   1.1   thorpej 	uint32_t sc_txcw;		/* prototype TXCW register */
    272   1.1   thorpej 	uint32_t sc_tipg;		/* prototype TIPG register */
    273   1.1   thorpej 
    274   1.1   thorpej 	int sc_tbi_linkup;		/* TBI link status */
    275   1.1   thorpej 	int sc_tbi_anstate;		/* autonegotiation state */
    276   1.1   thorpej 
    277   1.1   thorpej 	int sc_mchash_type;		/* multicast filter offset */
    278  1.21    itojun 
    279  1.21    itojun #if NRND > 0
    280  1.21    itojun 	rndsource_element_t rnd_source;	/* random source */
    281  1.21    itojun #endif
    282   1.1   thorpej };
    283   1.1   thorpej 
    284   1.1   thorpej #define	WM_RXCHAIN_RESET(sc)						\
    285   1.1   thorpej do {									\
    286   1.1   thorpej 	(sc)->sc_rxtailp = &(sc)->sc_rxhead;				\
    287   1.1   thorpej 	*(sc)->sc_rxtailp = NULL;					\
    288   1.1   thorpej 	(sc)->sc_rxlen = 0;						\
    289   1.1   thorpej } while (/*CONSTCOND*/0)
    290   1.1   thorpej 
    291   1.1   thorpej #define	WM_RXCHAIN_LINK(sc, m)						\
    292   1.1   thorpej do {									\
    293   1.1   thorpej 	*(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);			\
    294   1.1   thorpej 	(sc)->sc_rxtailp = &(m)->m_next;				\
    295   1.1   thorpej } while (/*CONSTCOND*/0)
    296   1.1   thorpej 
    297   1.1   thorpej /* sc_type */
    298  1.11   thorpej #define	WM_T_82542_2_0		0	/* i82542 2.0 (really old) */
    299  1.11   thorpej #define	WM_T_82542_2_1		1	/* i82542 2.1+ (old) */
    300  1.11   thorpej #define	WM_T_82543		2	/* i82543 */
    301  1.11   thorpej #define	WM_T_82544		3	/* i82544 */
    302  1.11   thorpej #define	WM_T_82540		4	/* i82540 */
    303  1.11   thorpej #define	WM_T_82545		5	/* i82545 */
    304  1.11   thorpej #define	WM_T_82546		6	/* i82546 */
    305   1.1   thorpej 
    306   1.1   thorpej /* sc_flags */
    307   1.1   thorpej #define	WM_F_HAS_MII		0x01	/* has MII */
    308  1.17   thorpej #define	WM_F_EEPROM_HANDSHAKE	0x02	/* requires EEPROM handshake */
    309   1.1   thorpej 
    310   1.1   thorpej #ifdef WM_EVENT_COUNTERS
    311   1.1   thorpej #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
    312   1.1   thorpej #else
    313   1.1   thorpej #define	WM_EVCNT_INCR(ev)	/* nothing */
    314   1.1   thorpej #endif
    315   1.1   thorpej 
    316   1.1   thorpej #define	CSR_READ(sc, reg)						\
    317   1.1   thorpej 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
    318   1.1   thorpej #define	CSR_WRITE(sc, reg, val)						\
    319   1.1   thorpej 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
    320   1.1   thorpej 
    321   1.1   thorpej #define	WM_CDTXADDR(sc, x)	((sc)->sc_cddma + WM_CDTXOFF((x)))
    322   1.1   thorpej #define	WM_CDRXADDR(sc, x)	((sc)->sc_cddma + WM_CDRXOFF((x)))
    323   1.1   thorpej 
    324   1.1   thorpej #define	WM_CDTXSYNC(sc, x, n, ops)					\
    325   1.1   thorpej do {									\
    326   1.1   thorpej 	int __x, __n;							\
    327   1.1   thorpej 									\
    328   1.1   thorpej 	__x = (x);							\
    329   1.1   thorpej 	__n = (n);							\
    330   1.1   thorpej 									\
    331   1.1   thorpej 	/* If it will wrap around, sync to the end of the ring. */	\
    332   1.1   thorpej 	if ((__x + __n) > WM_NTXDESC) {					\
    333   1.1   thorpej 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
    334   1.1   thorpej 		    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) *		\
    335   1.1   thorpej 		    (WM_NTXDESC - __x), (ops));				\
    336   1.1   thorpej 		__n -= (WM_NTXDESC - __x);				\
    337   1.1   thorpej 		__x = 0;						\
    338   1.1   thorpej 	}								\
    339   1.1   thorpej 									\
    340   1.1   thorpej 	/* Now sync whatever is left. */				\
    341   1.1   thorpej 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    342   1.1   thorpej 	    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops));	\
    343   1.1   thorpej } while (/*CONSTCOND*/0)
    344   1.1   thorpej 
    345   1.1   thorpej #define	WM_CDRXSYNC(sc, x, ops)						\
    346   1.1   thorpej do {									\
    347   1.1   thorpej 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    348   1.1   thorpej 	   WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops));		\
    349   1.1   thorpej } while (/*CONSTCOND*/0)
    350   1.1   thorpej 
    351   1.1   thorpej #define	WM_INIT_RXDESC(sc, x)						\
    352   1.1   thorpej do {									\
    353   1.1   thorpej 	struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
    354   1.1   thorpej 	wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];		\
    355   1.1   thorpej 	struct mbuf *__m = __rxs->rxs_mbuf;				\
    356   1.1   thorpej 									\
    357   1.1   thorpej 	/*								\
    358   1.1   thorpej 	 * Note: We scoot the packet forward 2 bytes in the buffer	\
    359   1.1   thorpej 	 * so that the payload after the Ethernet header is aligned	\
    360   1.1   thorpej 	 * to a 4-byte boundary.					\
    361   1.1   thorpej 	 *								\
    362   1.1   thorpej 	 * XXX BRAINDAMAGE ALERT!					\
    363   1.1   thorpej 	 * The stupid chip uses the same size for every buffer, which	\
    364   1.1   thorpej 	 * is set in the Receive Control register.  We are using the 2K	\
    365   1.1   thorpej 	 * size option, but what we REALLY want is (2K - 2)!  For this	\
    366   1.1   thorpej 	 * reason, we can't accept packets longer than the standard	\
    367   1.1   thorpej 	 * Ethernet MTU, without incurring a big penalty to copy every	\
    368   1.1   thorpej 	 * incoming packet to a new, suitably aligned buffer.		\
    369   1.1   thorpej 	 *								\
    370   1.1   thorpej 	 * We'll need to make some changes to the layer 3/4 parts of	\
    371   1.1   thorpej 	 * the stack (to copy the headers to a new buffer if not	\
    372   1.1   thorpej 	 * aligned) in order to support large MTU on this chip.  Lame.	\
    373   1.1   thorpej 	 */								\
    374   1.1   thorpej 	__m->m_data = __m->m_ext.ext_buf + 2;				\
    375   1.1   thorpej 									\
    376   1.1   thorpej 	__rxd->wrx_addr.wa_low =					\
    377   1.1   thorpej 	    htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2);		\
    378   1.1   thorpej 	__rxd->wrx_addr.wa_high = 0;					\
    379   1.1   thorpej 	__rxd->wrx_len = 0;						\
    380   1.1   thorpej 	__rxd->wrx_cksum = 0;						\
    381   1.1   thorpej 	__rxd->wrx_status = 0;						\
    382   1.1   thorpej 	__rxd->wrx_errors = 0;						\
    383   1.1   thorpej 	__rxd->wrx_special = 0;						\
    384   1.1   thorpej 	WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
    385   1.1   thorpej 									\
    386   1.1   thorpej 	CSR_WRITE((sc), (sc)->sc_rdt_reg, (x));				\
    387   1.1   thorpej } while (/*CONSTCOND*/0)
    388   1.1   thorpej 
    389   1.1   thorpej void	wm_start(struct ifnet *);
    390   1.1   thorpej void	wm_watchdog(struct ifnet *);
    391   1.1   thorpej int	wm_ioctl(struct ifnet *, u_long, caddr_t);
    392   1.1   thorpej int	wm_init(struct ifnet *);
    393   1.1   thorpej void	wm_stop(struct ifnet *, int);
    394   1.1   thorpej 
    395   1.1   thorpej void	wm_shutdown(void *);
    396   1.1   thorpej 
    397   1.1   thorpej void	wm_reset(struct wm_softc *);
    398   1.1   thorpej void	wm_rxdrain(struct wm_softc *);
    399   1.1   thorpej int	wm_add_rxbuf(struct wm_softc *, int);
    400   1.1   thorpej void	wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *);
    401   1.1   thorpej void	wm_tick(void *);
    402   1.1   thorpej 
    403   1.1   thorpej void	wm_set_filter(struct wm_softc *);
    404   1.1   thorpej 
    405   1.1   thorpej int	wm_intr(void *);
    406   1.1   thorpej void	wm_txintr(struct wm_softc *);
    407   1.1   thorpej void	wm_rxintr(struct wm_softc *);
    408   1.1   thorpej void	wm_linkintr(struct wm_softc *, uint32_t);
    409   1.1   thorpej 
    410   1.1   thorpej void	wm_tbi_mediainit(struct wm_softc *);
    411   1.1   thorpej int	wm_tbi_mediachange(struct ifnet *);
    412   1.1   thorpej void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
    413   1.1   thorpej 
    414   1.1   thorpej void	wm_tbi_set_linkled(struct wm_softc *);
    415   1.1   thorpej void	wm_tbi_check_link(struct wm_softc *);
    416   1.1   thorpej 
    417   1.1   thorpej void	wm_gmii_reset(struct wm_softc *);
    418   1.1   thorpej 
    419  1.11   thorpej int	wm_gmii_i82543_readreg(struct device *, int, int);
    420  1.11   thorpej void	wm_gmii_i82543_writereg(struct device *, int, int, int);
    421   1.1   thorpej 
    422  1.11   thorpej int	wm_gmii_i82544_readreg(struct device *, int, int);
    423  1.11   thorpej void	wm_gmii_i82544_writereg(struct device *, int, int, int);
    424   1.1   thorpej 
    425   1.1   thorpej void	wm_gmii_statchg(struct device *);
    426   1.1   thorpej 
    427   1.1   thorpej void	wm_gmii_mediainit(struct wm_softc *);
    428   1.1   thorpej int	wm_gmii_mediachange(struct ifnet *);
    429   1.1   thorpej void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
    430   1.1   thorpej 
    431   1.1   thorpej int	wm_match(struct device *, struct cfdata *, void *);
    432   1.1   thorpej void	wm_attach(struct device *, struct device *, void *);
    433   1.1   thorpej 
    434  1.24   thorpej CFATTACH_DECL(wm, sizeof(struct wm_softc),
    435  1.25   thorpej     wm_match, wm_attach, NULL, NULL);
    436   1.1   thorpej 
    437   1.1   thorpej /*
    438   1.1   thorpej  * Devices supported by this driver.
    439   1.1   thorpej  */
    440   1.1   thorpej const struct wm_product {
    441   1.1   thorpej 	pci_vendor_id_t		wmp_vendor;
    442   1.1   thorpej 	pci_product_id_t	wmp_product;
    443   1.1   thorpej 	const char		*wmp_name;
    444   1.1   thorpej 	int			wmp_type;
    445   1.1   thorpej 	int			wmp_flags;
    446   1.1   thorpej #define	WMP_F_1000X		0x01
    447   1.1   thorpej #define	WMP_F_1000T		0x02
    448   1.1   thorpej } wm_products[] = {
    449   1.1   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
    450   1.1   thorpej 	  "Intel i82542 1000BASE-X Ethernet",
    451  1.11   thorpej 	  WM_T_82542_2_1,	WMP_F_1000X },
    452   1.1   thorpej 
    453  1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
    454  1.11   thorpej 	  "Intel i82543GC 1000BASE-X Ethernet",
    455  1.11   thorpej 	  WM_T_82543,		WMP_F_1000X },
    456   1.1   thorpej 
    457  1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
    458  1.11   thorpej 	  "Intel i82543GC 1000BASE-T Ethernet",
    459  1.11   thorpej 	  WM_T_82543,		WMP_F_1000T },
    460   1.1   thorpej 
    461  1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
    462  1.11   thorpej 	  "Intel i82544EI 1000BASE-T Ethernet",
    463  1.11   thorpej 	  WM_T_82544,		WMP_F_1000T },
    464   1.1   thorpej 
    465  1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
    466  1.11   thorpej 	  "Intel i82544EI 1000BASE-X Ethernet",
    467  1.11   thorpej 	  WM_T_82544,		WMP_F_1000X },
    468   1.1   thorpej 
    469  1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
    470   1.1   thorpej 	  "Intel i82544GC 1000BASE-T Ethernet",
    471  1.11   thorpej 	  WM_T_82544,		WMP_F_1000T },
    472   1.1   thorpej 
    473  1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
    474  1.11   thorpej 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
    475  1.11   thorpej 	  WM_T_82544,		WMP_F_1000T },
    476   1.1   thorpej 
    477  1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
    478  1.17   thorpej 	  "Intel i82540EM 1000BASE-T Ethernet",
    479  1.34      kent 	  WM_T_82540,		WMP_F_1000T },
    480  1.34      kent 
    481  1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
    482  1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    483  1.34      kent 	  WM_T_82540,		WMP_F_1000T },
    484  1.34      kent 
    485  1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
    486  1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    487  1.33      kent 	  WM_T_82540,		WMP_F_1000T },
    488  1.33      kent 
    489  1.33      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
    490  1.33      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    491  1.17   thorpej 	  WM_T_82540,		WMP_F_1000T },
    492  1.17   thorpej 
    493  1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
    494  1.17   thorpej 	  "Intel i82545EM 1000BASE-T Ethernet",
    495  1.17   thorpej 	  WM_T_82545,		WMP_F_1000T },
    496  1.17   thorpej 
    497  1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
    498  1.17   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
    499  1.17   thorpej 	  WM_T_82546,		WMP_F_1000T },
    500  1.17   thorpej 
    501  1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
    502  1.17   thorpej 	  "Intel i82545EM 1000BASE-X Ethernet",
    503  1.17   thorpej 	  WM_T_82545,		WMP_F_1000X },
    504  1.17   thorpej 
    505  1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
    506  1.17   thorpej 	  "Intel i82546EB 1000BASE-X Ethernet",
    507  1.17   thorpej 	  WM_T_82546,		WMP_F_1000X },
    508  1.17   thorpej 
    509  1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
    510  1.17   thorpej 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
    511  1.17   thorpej 	  WM_T_82540,		WMP_F_1000T },
    512  1.17   thorpej 
    513   1.1   thorpej 	{ 0,			0,
    514   1.1   thorpej 	  NULL,
    515   1.1   thorpej 	  0,			0 },
    516   1.1   thorpej };
    517   1.1   thorpej 
    518   1.2   thorpej #ifdef WM_EVENT_COUNTERS
    519   1.2   thorpej #if WM_NTXSEGS != 16
    520   1.2   thorpej #error Update wm_txseg_evcnt_names
    521   1.2   thorpej #endif
    522   1.2   thorpej static const char *wm_txseg_evcnt_names[WM_NTXSEGS] = {
    523   1.2   thorpej 	"txseg1",
    524   1.2   thorpej 	"txseg2",
    525   1.2   thorpej 	"txseg3",
    526   1.2   thorpej 	"txseg4",
    527   1.2   thorpej 	"txseg5",
    528   1.2   thorpej 	"txseg6",
    529   1.2   thorpej 	"txseg7",
    530   1.2   thorpej 	"txseg8",
    531   1.2   thorpej 	"txseg9",
    532   1.2   thorpej 	"txseg10",
    533   1.2   thorpej 	"txseg11",
    534   1.2   thorpej 	"txseg12",
    535   1.2   thorpej 	"txseg13",
    536   1.2   thorpej 	"txseg14",
    537   1.2   thorpej 	"txseg15",
    538   1.2   thorpej 	"txseg16",
    539   1.2   thorpej };
    540   1.2   thorpej #endif /* WM_EVENT_COUNTERS */
    541   1.2   thorpej 
    542   1.1   thorpej static const struct wm_product *
    543   1.1   thorpej wm_lookup(const struct pci_attach_args *pa)
    544   1.1   thorpej {
    545   1.1   thorpej 	const struct wm_product *wmp;
    546   1.1   thorpej 
    547   1.1   thorpej 	for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
    548   1.1   thorpej 		if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
    549   1.1   thorpej 		    PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
    550   1.1   thorpej 			return (wmp);
    551   1.1   thorpej 	}
    552   1.1   thorpej 	return (NULL);
    553   1.1   thorpej }
    554   1.1   thorpej 
    555   1.1   thorpej int
    556   1.1   thorpej wm_match(struct device *parent, struct cfdata *cf, void *aux)
    557   1.1   thorpej {
    558   1.1   thorpej 	struct pci_attach_args *pa = aux;
    559   1.1   thorpej 
    560   1.1   thorpej 	if (wm_lookup(pa) != NULL)
    561   1.1   thorpej 		return (1);
    562   1.1   thorpej 
    563   1.1   thorpej 	return (0);
    564   1.1   thorpej }
    565   1.1   thorpej 
    566   1.1   thorpej void
    567   1.1   thorpej wm_attach(struct device *parent, struct device *self, void *aux)
    568   1.1   thorpej {
    569   1.1   thorpej 	struct wm_softc *sc = (void *) self;
    570   1.1   thorpej 	struct pci_attach_args *pa = aux;
    571   1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    572   1.1   thorpej 	pci_chipset_tag_t pc = pa->pa_pc;
    573   1.1   thorpej 	pci_intr_handle_t ih;
    574   1.1   thorpej 	const char *intrstr = NULL;
    575   1.1   thorpej 	bus_space_tag_t memt;
    576   1.1   thorpej 	bus_space_handle_t memh;
    577   1.1   thorpej 	bus_dma_segment_t seg;
    578   1.1   thorpej 	int memh_valid;
    579   1.1   thorpej 	int i, rseg, error;
    580   1.1   thorpej 	const struct wm_product *wmp;
    581   1.1   thorpej 	uint8_t enaddr[ETHER_ADDR_LEN];
    582   1.1   thorpej 	uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
    583   1.1   thorpej 	pcireg_t preg, memtype;
    584   1.1   thorpej 	int pmreg;
    585   1.1   thorpej 
    586   1.1   thorpej 	callout_init(&sc->sc_tick_ch);
    587   1.1   thorpej 
    588   1.1   thorpej 	wmp = wm_lookup(pa);
    589   1.1   thorpej 	if (wmp == NULL) {
    590   1.1   thorpej 		printf("\n");
    591   1.1   thorpej 		panic("wm_attach: impossible");
    592   1.1   thorpej 	}
    593   1.1   thorpej 
    594   1.1   thorpej 	sc->sc_dmat = pa->pa_dmat;
    595   1.1   thorpej 
    596   1.1   thorpej 	preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG));
    597   1.1   thorpej 	printf(": %s, rev. %d\n", wmp->wmp_name, preg);
    598   1.1   thorpej 
    599   1.1   thorpej 	sc->sc_type = wmp->wmp_type;
    600  1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
    601   1.1   thorpej 		if (preg < 2) {
    602  1.11   thorpej 			printf("%s: i82542 must be at least rev. 2\n",
    603   1.1   thorpej 			    sc->sc_dev.dv_xname);
    604   1.1   thorpej 			return;
    605   1.1   thorpej 		}
    606   1.1   thorpej 		if (preg < 3)
    607  1.11   thorpej 			sc->sc_type = WM_T_82542_2_0;
    608   1.1   thorpej 	}
    609   1.1   thorpej 
    610   1.1   thorpej 	/*
    611  1.17   thorpej 	 * Some chips require a handshake to access the EEPROM.
    612  1.17   thorpej 	 */
    613  1.17   thorpej 	if (sc->sc_type >= WM_T_82540)
    614  1.17   thorpej 		sc->sc_flags |= WM_F_EEPROM_HANDSHAKE;
    615  1.17   thorpej 
    616  1.17   thorpej 	/*
    617   1.1   thorpej 	 * Map the device.
    618   1.1   thorpej 	 */
    619   1.1   thorpej 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
    620   1.1   thorpej 	switch (memtype) {
    621   1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
    622   1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
    623   1.1   thorpej 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
    624   1.1   thorpej 		    memtype, 0, &memt, &memh, NULL, NULL) == 0);
    625   1.1   thorpej 		break;
    626   1.1   thorpej 	default:
    627   1.1   thorpej 		memh_valid = 0;
    628   1.1   thorpej 	}
    629   1.1   thorpej 
    630   1.1   thorpej 	if (memh_valid) {
    631   1.1   thorpej 		sc->sc_st = memt;
    632   1.1   thorpej 		sc->sc_sh = memh;
    633   1.1   thorpej 	} else {
    634   1.1   thorpej 		printf("%s: unable to map device registers\n",
    635   1.1   thorpej 		    sc->sc_dev.dv_xname);
    636   1.1   thorpej 		return;
    637   1.1   thorpej 	}
    638   1.1   thorpej 
    639  1.11   thorpej 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
    640   1.1   thorpej 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    641   1.1   thorpej 	preg |= PCI_COMMAND_MASTER_ENABLE;
    642  1.11   thorpej 	if (sc->sc_type < WM_T_82542_2_1)
    643   1.1   thorpej 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
    644   1.1   thorpej 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
    645   1.1   thorpej 
    646   1.1   thorpej 	/* Get it out of power save mode, if needed. */
    647   1.1   thorpej 	if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
    648  1.29   tsutsui 		preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) &
    649  1.29   tsutsui 		    PCI_PMCSR_STATE_MASK;
    650  1.29   tsutsui 		if (preg == PCI_PMCSR_STATE_D3) {
    651   1.1   thorpej 			/*
    652   1.1   thorpej 			 * The card has lost all configuration data in
    653   1.1   thorpej 			 * this state, so punt.
    654   1.1   thorpej 			 */
    655   1.1   thorpej 			printf("%s: unable to wake from power state D3\n",
    656   1.1   thorpej 			    sc->sc_dev.dv_xname);
    657   1.1   thorpej 			return;
    658   1.1   thorpej 		}
    659  1.29   tsutsui 		if (preg != PCI_PMCSR_STATE_D0) {
    660   1.1   thorpej 			printf("%s: waking up from power state D%d\n",
    661   1.1   thorpej 			    sc->sc_dev.dv_xname, preg);
    662  1.29   tsutsui 			pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
    663  1.29   tsutsui 			    PCI_PMCSR_STATE_D0);
    664   1.1   thorpej 		}
    665   1.1   thorpej 	}
    666   1.1   thorpej 
    667   1.1   thorpej 	/*
    668   1.1   thorpej 	 * Map and establish our interrupt.
    669   1.1   thorpej 	 */
    670   1.1   thorpej 	if (pci_intr_map(pa, &ih)) {
    671   1.1   thorpej 		printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname);
    672   1.1   thorpej 		return;
    673   1.1   thorpej 	}
    674   1.1   thorpej 	intrstr = pci_intr_string(pc, ih);
    675   1.1   thorpej 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc);
    676   1.1   thorpej 	if (sc->sc_ih == NULL) {
    677   1.1   thorpej 		printf("%s: unable to establish interrupt",
    678   1.1   thorpej 		    sc->sc_dev.dv_xname);
    679   1.1   thorpej 		if (intrstr != NULL)
    680   1.1   thorpej 			printf(" at %s", intrstr);
    681   1.1   thorpej 		printf("\n");
    682   1.1   thorpej 		return;
    683   1.1   thorpej 	}
    684   1.1   thorpej 	printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
    685   1.1   thorpej 
    686   1.1   thorpej 	/*
    687   1.1   thorpej 	 * Allocate the control data structures, and create and load the
    688   1.1   thorpej 	 * DMA map for it.
    689   1.1   thorpej 	 */
    690   1.1   thorpej 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
    691   1.1   thorpej 	    sizeof(struct wm_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
    692   1.1   thorpej 	    0)) != 0) {
    693   1.1   thorpej 		printf("%s: unable to allocate control data, error = %d\n",
    694   1.1   thorpej 		    sc->sc_dev.dv_xname, error);
    695   1.1   thorpej 		goto fail_0;
    696   1.1   thorpej 	}
    697   1.1   thorpej 
    698   1.1   thorpej 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
    699   1.1   thorpej 	    sizeof(struct wm_control_data), (caddr_t *)&sc->sc_control_data,
    700  1.20   thorpej 	    0)) != 0) {
    701   1.1   thorpej 		printf("%s: unable to map control data, error = %d\n",
    702   1.1   thorpej 		    sc->sc_dev.dv_xname, error);
    703   1.1   thorpej 		goto fail_1;
    704   1.1   thorpej 	}
    705   1.1   thorpej 
    706   1.1   thorpej 	if ((error = bus_dmamap_create(sc->sc_dmat,
    707   1.1   thorpej 	    sizeof(struct wm_control_data), 1,
    708   1.1   thorpej 	    sizeof(struct wm_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
    709   1.1   thorpej 		printf("%s: unable to create control data DMA map, "
    710   1.1   thorpej 		    "error = %d\n", sc->sc_dev.dv_xname, error);
    711   1.1   thorpej 		goto fail_2;
    712   1.1   thorpej 	}
    713   1.1   thorpej 
    714   1.1   thorpej 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
    715   1.1   thorpej 	    sc->sc_control_data, sizeof(struct wm_control_data), NULL,
    716   1.1   thorpej 	    0)) != 0) {
    717   1.1   thorpej 		printf("%s: unable to load control data DMA map, error = %d\n",
    718   1.1   thorpej 		    sc->sc_dev.dv_xname, error);
    719   1.1   thorpej 		goto fail_3;
    720   1.1   thorpej 	}
    721   1.1   thorpej 
    722   1.1   thorpej 	/*
    723   1.1   thorpej 	 * Create the transmit buffer DMA maps.
    724   1.1   thorpej 	 */
    725   1.1   thorpej 	for (i = 0; i < WM_TXQUEUELEN; i++) {
    726   1.1   thorpej 		if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO,
    727   1.1   thorpej 		    WM_NTXSEGS, MCLBYTES, 0, 0,
    728   1.1   thorpej 		    &sc->sc_txsoft[i].txs_dmamap)) != 0) {
    729   1.1   thorpej 			printf("%s: unable to create Tx DMA map %d, "
    730   1.1   thorpej 			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
    731   1.1   thorpej 			goto fail_4;
    732   1.1   thorpej 		}
    733   1.1   thorpej 	}
    734   1.1   thorpej 
    735   1.1   thorpej 	/*
    736   1.1   thorpej 	 * Create the receive buffer DMA maps.
    737   1.1   thorpej 	 */
    738   1.1   thorpej 	for (i = 0; i < WM_NRXDESC; i++) {
    739   1.1   thorpej 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
    740   1.1   thorpej 		    MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
    741   1.1   thorpej 			printf("%s: unable to create Rx DMA map %d, "
    742   1.1   thorpej 			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
    743   1.1   thorpej 			goto fail_5;
    744   1.1   thorpej 		}
    745   1.1   thorpej 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
    746   1.1   thorpej 	}
    747   1.1   thorpej 
    748   1.1   thorpej 	/*
    749   1.1   thorpej 	 * Reset the chip to a known state.
    750   1.1   thorpej 	 */
    751   1.1   thorpej 	wm_reset(sc);
    752   1.1   thorpej 
    753   1.1   thorpej 	/*
    754   1.1   thorpej 	 * Read the Ethernet address from the EEPROM.
    755   1.1   thorpej 	 */
    756   1.1   thorpej 	wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
    757   1.1   thorpej 	    sizeof(myea) / sizeof(myea[0]), myea);
    758   1.1   thorpej 	enaddr[0] = myea[0] & 0xff;
    759   1.1   thorpej 	enaddr[1] = myea[0] >> 8;
    760   1.1   thorpej 	enaddr[2] = myea[1] & 0xff;
    761   1.1   thorpej 	enaddr[3] = myea[1] >> 8;
    762   1.1   thorpej 	enaddr[4] = myea[2] & 0xff;
    763   1.1   thorpej 	enaddr[5] = myea[2] >> 8;
    764   1.1   thorpej 
    765  1.17   thorpej 	/*
    766  1.17   thorpej 	 * Toggle the LSB of the MAC address on the second port
    767  1.17   thorpej 	 * of the i82546.
    768  1.17   thorpej 	 */
    769  1.17   thorpej 	if (sc->sc_type == WM_T_82546) {
    770  1.17   thorpej 		if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1)
    771  1.17   thorpej 			enaddr[5] ^= 1;
    772  1.17   thorpej 	}
    773  1.17   thorpej 
    774   1.1   thorpej 	printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
    775   1.1   thorpej 	    ether_sprintf(enaddr));
    776   1.1   thorpej 
    777   1.1   thorpej 	/*
    778   1.1   thorpej 	 * Read the config info from the EEPROM, and set up various
    779   1.1   thorpej 	 * bits in the control registers based on their contents.
    780   1.1   thorpej 	 */
    781   1.1   thorpej 	wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1);
    782   1.1   thorpej 	wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2);
    783  1.11   thorpej 	if (sc->sc_type >= WM_T_82544)
    784   1.1   thorpej 		wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin);
    785   1.1   thorpej 
    786   1.1   thorpej 	if (cfg1 & EEPROM_CFG1_ILOS)
    787   1.1   thorpej 		sc->sc_ctrl |= CTRL_ILOS;
    788  1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
    789   1.1   thorpej 		sc->sc_ctrl |=
    790   1.1   thorpej 		    ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
    791   1.1   thorpej 		    CTRL_SWDPIO_SHIFT;
    792   1.1   thorpej 		sc->sc_ctrl |=
    793   1.1   thorpej 		    ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
    794   1.1   thorpej 		    CTRL_SWDPINS_SHIFT;
    795   1.1   thorpej 	} else {
    796   1.1   thorpej 		sc->sc_ctrl |=
    797   1.1   thorpej 		    ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) <<
    798   1.1   thorpej 		    CTRL_SWDPIO_SHIFT;
    799   1.1   thorpej 	}
    800   1.1   thorpej 
    801   1.1   thorpej #if 0
    802  1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
    803   1.1   thorpej 		if (cfg1 & EEPROM_CFG1_IPS0)
    804   1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
    805   1.1   thorpej 		if (cfg1 & EEPROM_CFG1_IPS1)
    806   1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
    807   1.1   thorpej 		sc->sc_ctrl_ext |=
    808   1.1   thorpej 		    ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
    809   1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
    810   1.1   thorpej 		sc->sc_ctrl_ext |=
    811   1.1   thorpej 		    ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
    812   1.1   thorpej 		    CTRL_EXT_SWDPINS_SHIFT;
    813   1.1   thorpej 	} else {
    814   1.1   thorpej 		sc->sc_ctrl_ext |=
    815   1.1   thorpej 		    ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) <<
    816   1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
    817   1.1   thorpej 	}
    818   1.1   thorpej #endif
    819   1.1   thorpej 
    820   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
    821   1.1   thorpej #if 0
    822   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
    823   1.1   thorpej #endif
    824   1.1   thorpej 
    825   1.1   thorpej 	/*
    826   1.1   thorpej 	 * Set up some register offsets that are different between
    827  1.11   thorpej 	 * the i82542 and the i82543 and later chips.
    828   1.1   thorpej 	 */
    829  1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
    830   1.1   thorpej 		sc->sc_rdt_reg = WMREG_OLD_RDT0;
    831   1.1   thorpej 		sc->sc_tdt_reg = WMREG_OLD_TDT;
    832   1.1   thorpej 	} else {
    833   1.1   thorpej 		sc->sc_rdt_reg = WMREG_RDT;
    834   1.1   thorpej 		sc->sc_tdt_reg = WMREG_TDT;
    835   1.1   thorpej 	}
    836   1.1   thorpej 
    837   1.1   thorpej 	/*
    838   1.1   thorpej 	 * Determine if we should use flow control.  We should
    839  1.11   thorpej 	 * always use it, unless we're on a i82542 < 2.1.
    840   1.1   thorpej 	 */
    841  1.11   thorpej 	if (sc->sc_type >= WM_T_82542_2_1)
    842   1.1   thorpej 		sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;
    843   1.1   thorpej 
    844   1.1   thorpej 	/*
    845   1.1   thorpej 	 * Determine if we're TBI or GMII mode, and initialize the
    846   1.1   thorpej 	 * media structures accordingly.
    847   1.1   thorpej 	 */
    848  1.11   thorpej 	if (sc->sc_type < WM_T_82543 ||
    849   1.1   thorpej 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
    850   1.1   thorpej 		if (wmp->wmp_flags & WMP_F_1000T)
    851   1.1   thorpej 			printf("%s: WARNING: TBIMODE set on 1000BASE-T "
    852   1.1   thorpej 			    "product!\n", sc->sc_dev.dv_xname);
    853   1.1   thorpej 		wm_tbi_mediainit(sc);
    854   1.1   thorpej 	} else {
    855   1.1   thorpej 		if (wmp->wmp_flags & WMP_F_1000X)
    856   1.1   thorpej 			printf("%s: WARNING: TBIMODE clear on 1000BASE-X "
    857   1.1   thorpej 			    "product!\n", sc->sc_dev.dv_xname);
    858   1.1   thorpej 		wm_gmii_mediainit(sc);
    859   1.1   thorpej 	}
    860   1.1   thorpej 
    861   1.1   thorpej 	ifp = &sc->sc_ethercom.ec_if;
    862   1.1   thorpej 	strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
    863   1.1   thorpej 	ifp->if_softc = sc;
    864   1.1   thorpej 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
    865   1.1   thorpej 	ifp->if_ioctl = wm_ioctl;
    866   1.1   thorpej 	ifp->if_start = wm_start;
    867   1.1   thorpej 	ifp->if_watchdog = wm_watchdog;
    868   1.1   thorpej 	ifp->if_init = wm_init;
    869   1.1   thorpej 	ifp->if_stop = wm_stop;
    870   1.2   thorpej 	IFQ_SET_MAXLEN(&ifp->if_snd, WM_IFQUEUELEN);
    871   1.1   thorpej 	IFQ_SET_READY(&ifp->if_snd);
    872   1.1   thorpej 
    873   1.1   thorpej 	/*
    874  1.11   thorpej 	 * If we're a i82543 or greater, we can support VLANs.
    875   1.1   thorpej 	 */
    876  1.11   thorpej 	if (sc->sc_type >= WM_T_82543)
    877   1.1   thorpej 		sc->sc_ethercom.ec_capabilities |=
    878   1.1   thorpej 		    ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */;
    879   1.1   thorpej 
    880   1.1   thorpej 	/*
    881   1.1   thorpej 	 * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
    882  1.11   thorpej 	 * on i82543 and later.
    883   1.1   thorpej 	 */
    884  1.11   thorpej 	if (sc->sc_type >= WM_T_82543)
    885   1.1   thorpej 		ifp->if_capabilities |=
    886   1.1   thorpej 		    IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
    887   1.1   thorpej 
    888   1.1   thorpej 	/*
    889   1.1   thorpej 	 * Attach the interface.
    890   1.1   thorpej 	 */
    891   1.1   thorpej 	if_attach(ifp);
    892   1.1   thorpej 	ether_ifattach(ifp, enaddr);
    893  1.21    itojun #if NRND > 0
    894  1.21    itojun 	rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
    895  1.21    itojun 	    RND_TYPE_NET, 0);
    896  1.21    itojun #endif
    897   1.1   thorpej 
    898   1.1   thorpej #ifdef WM_EVENT_COUNTERS
    899   1.1   thorpej 	/* Attach event counters. */
    900   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
    901   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "txsstall");
    902   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
    903   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "txdstall");
    904   1.8   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_MISC,
    905   1.8   thorpej 	    NULL, sc->sc_dev.dv_xname, "txforceintr");
    906   1.4   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR,
    907   1.4   thorpej 	    NULL, sc->sc_dev.dv_xname, "txdw");
    908   1.4   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR,
    909   1.4   thorpej 	    NULL, sc->sc_dev.dv_xname, "txqe");
    910   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
    911   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "rxintr");
    912   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
    913   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "linkintr");
    914   1.1   thorpej 
    915   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
    916   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "rxipsum");
    917   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC,
    918   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "rxtusum");
    919   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
    920   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "txipsum");
    921   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC,
    922   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "txtusum");
    923   1.1   thorpej 
    924   1.5   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC,
    925   1.5   thorpej 	    NULL, sc->sc_dev.dv_xname, "txctx init");
    926   1.5   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC,
    927   1.5   thorpej 	    NULL, sc->sc_dev.dv_xname, "txctx hit");
    928   1.5   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC,
    929   1.5   thorpej 	    NULL, sc->sc_dev.dv_xname, "txctx miss");
    930   1.5   thorpej 
    931   1.2   thorpej 	for (i = 0; i < WM_NTXSEGS; i++)
    932   1.2   thorpej 		evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC,
    933   1.2   thorpej 		    NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]);
    934   1.2   thorpej 
    935   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC,
    936   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "txdrop");
    937   1.1   thorpej 
    938   1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC,
    939   1.1   thorpej 	    NULL, sc->sc_dev.dv_xname, "tu");
    940   1.1   thorpej #endif /* WM_EVENT_COUNTERS */
    941   1.1   thorpej 
    942   1.1   thorpej 	/*
    943   1.1   thorpej 	 * Make sure the interface is shutdown during reboot.
    944   1.1   thorpej 	 */
    945   1.1   thorpej 	sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc);
    946   1.1   thorpej 	if (sc->sc_sdhook == NULL)
    947   1.1   thorpej 		printf("%s: WARNING: unable to establish shutdown hook\n",
    948   1.1   thorpej 		    sc->sc_dev.dv_xname);
    949   1.1   thorpej 	return;
    950   1.1   thorpej 
    951   1.1   thorpej 	/*
    952   1.1   thorpej 	 * Free any resources we've allocated during the failed attach
    953   1.1   thorpej 	 * attempt.  Do this in reverse order and fall through.
    954   1.1   thorpej 	 */
    955   1.1   thorpej  fail_5:
    956   1.1   thorpej 	for (i = 0; i < WM_NRXDESC; i++) {
    957   1.1   thorpej 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
    958   1.1   thorpej 			bus_dmamap_destroy(sc->sc_dmat,
    959   1.1   thorpej 			    sc->sc_rxsoft[i].rxs_dmamap);
    960   1.1   thorpej 	}
    961   1.1   thorpej  fail_4:
    962   1.1   thorpej 	for (i = 0; i < WM_TXQUEUELEN; i++) {
    963   1.1   thorpej 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
    964   1.1   thorpej 			bus_dmamap_destroy(sc->sc_dmat,
    965   1.1   thorpej 			    sc->sc_txsoft[i].txs_dmamap);
    966   1.1   thorpej 	}
    967   1.1   thorpej 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
    968   1.1   thorpej  fail_3:
    969   1.1   thorpej 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
    970   1.1   thorpej  fail_2:
    971   1.1   thorpej 	bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
    972   1.1   thorpej 	    sizeof(struct wm_control_data));
    973   1.1   thorpej  fail_1:
    974   1.1   thorpej 	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
    975   1.1   thorpej  fail_0:
    976   1.1   thorpej 	return;
    977   1.1   thorpej }
    978   1.1   thorpej 
    979   1.1   thorpej /*
    980   1.1   thorpej  * wm_shutdown:
    981   1.1   thorpej  *
    982   1.1   thorpej  *	Make sure the interface is stopped at reboot time.
    983   1.1   thorpej  */
    984   1.1   thorpej void
    985   1.1   thorpej wm_shutdown(void *arg)
    986   1.1   thorpej {
    987   1.1   thorpej 	struct wm_softc *sc = arg;
    988   1.1   thorpej 
    989   1.1   thorpej 	wm_stop(&sc->sc_ethercom.ec_if, 1);
    990   1.1   thorpej }
    991   1.1   thorpej 
    992   1.1   thorpej /*
    993   1.1   thorpej  * wm_tx_cksum:
    994   1.1   thorpej  *
    995   1.1   thorpej  *	Set up TCP/IP checksumming parameters for the
    996   1.1   thorpej  *	specified packet.
    997   1.1   thorpej  */
    998   1.1   thorpej static int
    999   1.4   thorpej wm_tx_cksum(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp,
   1000   1.1   thorpej     uint32_t *fieldsp)
   1001   1.1   thorpej {
   1002   1.4   thorpej 	struct mbuf *m0 = txs->txs_mbuf;
   1003   1.1   thorpej 	struct livengood_tcpip_ctxdesc *t;
   1004   1.7   thorpej 	uint32_t fields = 0, ipcs, tucs;
   1005   1.1   thorpej 	struct ip *ip;
   1006  1.13   thorpej 	struct ether_header *eh;
   1007   1.1   thorpej 	int offset, iphl;
   1008   1.1   thorpej 
   1009   1.1   thorpej 	/*
   1010   1.1   thorpej 	 * XXX It would be nice if the mbuf pkthdr had offset
   1011   1.1   thorpej 	 * fields for the protocol headers.
   1012   1.1   thorpej 	 */
   1013   1.1   thorpej 
   1014  1.13   thorpej 	eh = mtod(m0, struct ether_header *);
   1015  1.13   thorpej 	switch (htons(eh->ether_type)) {
   1016  1.13   thorpej 	case ETHERTYPE_IP:
   1017  1.13   thorpej 		iphl = sizeof(struct ip);
   1018  1.13   thorpej 		offset = ETHER_HDR_LEN;
   1019  1.13   thorpej 		break;
   1020  1.13   thorpej 
   1021  1.13   thorpej 	default:
   1022  1.13   thorpej 		/*
   1023  1.13   thorpej 		 * Don't support this protocol or encapsulation.
   1024  1.13   thorpej 		 */
   1025  1.13   thorpej 		*fieldsp = 0;
   1026  1.13   thorpej 		*cmdp = 0;
   1027  1.13   thorpej 		return (0);
   1028  1.13   thorpej 	}
   1029   1.1   thorpej 
   1030   1.1   thorpej 	/* XXX */
   1031  1.13   thorpej 	if (m0->m_len < (offset + iphl)) {
   1032   1.1   thorpej 		printf("%s: wm_tx_cksum: need to m_pullup, "
   1033   1.1   thorpej 		    "packet dropped\n", sc->sc_dev.dv_xname);
   1034   1.1   thorpej 		return (EINVAL);
   1035   1.1   thorpej 	}
   1036   1.1   thorpej 
   1037   1.1   thorpej 	ip = (struct ip *) (mtod(m0, caddr_t) + offset);
   1038   1.1   thorpej 	iphl = ip->ip_hl << 2;
   1039   1.1   thorpej 
   1040  1.13   thorpej 	/*
   1041  1.13   thorpej 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
   1042  1.13   thorpej 	 * offload feature, if we load the context descriptor, we
   1043  1.13   thorpej 	 * MUST provide valid values for IPCSS and TUCSS fields.
   1044  1.13   thorpej 	 */
   1045  1.13   thorpej 
   1046   1.1   thorpej 	if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
   1047   1.1   thorpej 		WM_EVCNT_INCR(&sc->sc_ev_txipsum);
   1048   1.1   thorpej 		fields |= htole32(WTX_IXSM);
   1049   1.1   thorpej 		ipcs = htole32(WTX_TCPIP_IPCSS(offset) |
   1050  1.12   thorpej 		    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
   1051   1.1   thorpej 		    WTX_TCPIP_IPCSE(offset + iphl - 1));
   1052  1.13   thorpej 	} else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) {
   1053  1.13   thorpej 		/* Use the cached value. */
   1054  1.13   thorpej 		ipcs = sc->sc_txctx_ipcs;
   1055  1.13   thorpej 	} else {
   1056  1.13   thorpej 		/* Just initialize it to the likely value anyway. */
   1057  1.13   thorpej 		ipcs = htole32(WTX_TCPIP_IPCSS(offset) |
   1058  1.13   thorpej 		    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
   1059  1.13   thorpej 		    WTX_TCPIP_IPCSE(offset + iphl - 1));
   1060  1.13   thorpej 	}
   1061   1.1   thorpej 
   1062   1.1   thorpej 	offset += iphl;
   1063   1.1   thorpej 
   1064   1.1   thorpej 	if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) {
   1065   1.1   thorpej 		WM_EVCNT_INCR(&sc->sc_ev_txtusum);
   1066   1.1   thorpej 		fields |= htole32(WTX_TXSM);
   1067   1.1   thorpej 		tucs = htole32(WTX_TCPIP_TUCSS(offset) |
   1068   1.1   thorpej 		    WTX_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) |
   1069   1.1   thorpej 		    WTX_TCPIP_TUCSE(0) /* rest of packet */);
   1070  1.13   thorpej 	} else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) {
   1071  1.13   thorpej 		/* Use the cached value. */
   1072  1.13   thorpej 		tucs = sc->sc_txctx_tucs;
   1073  1.13   thorpej 	} else {
   1074  1.13   thorpej 		/* Just initialize it to a valid TCP context. */
   1075  1.13   thorpej 		tucs = htole32(WTX_TCPIP_TUCSS(offset) |
   1076  1.13   thorpej 		    WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
   1077  1.13   thorpej 		    WTX_TCPIP_TUCSE(0) /* rest of packet */);
   1078  1.13   thorpej 	}
   1079   1.1   thorpej 
   1080   1.5   thorpej 	if (sc->sc_txctx_ipcs == ipcs &&
   1081   1.7   thorpej 	    sc->sc_txctx_tucs == tucs) {
   1082   1.5   thorpej 		/* Cached context is fine. */
   1083   1.5   thorpej 		WM_EVCNT_INCR(&sc->sc_ev_txctx_hit);
   1084   1.5   thorpej 	} else {
   1085   1.5   thorpej 		/* Fill in the context descriptor. */
   1086   1.5   thorpej #ifdef WM_EVENT_COUNTERS
   1087   1.5   thorpej 		if (sc->sc_txctx_ipcs == 0xffffffff &&
   1088   1.7   thorpej 		    sc->sc_txctx_tucs == 0xffffffff)
   1089   1.5   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_txctx_init);
   1090   1.5   thorpej 		else
   1091   1.5   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_txctx_miss);
   1092   1.5   thorpej #endif
   1093   1.5   thorpej 		t = (struct livengood_tcpip_ctxdesc *)
   1094   1.5   thorpej 		    &sc->sc_txdescs[sc->sc_txnext];
   1095   1.5   thorpej 		t->tcpip_ipcs = ipcs;
   1096   1.5   thorpej 		t->tcpip_tucs = tucs;
   1097   1.5   thorpej 		t->tcpip_cmdlen =
   1098   1.7   thorpej 		    htole32(WTX_CMD_DEXT | WTX_DTYP_C);
   1099   1.5   thorpej 		t->tcpip_seg = 0;
   1100   1.5   thorpej 		WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE);
   1101   1.5   thorpej 
   1102   1.5   thorpej 		sc->sc_txctx_ipcs = ipcs;
   1103   1.5   thorpej 		sc->sc_txctx_tucs = tucs;
   1104   1.5   thorpej 
   1105   1.5   thorpej 		sc->sc_txnext = WM_NEXTTX(sc->sc_txnext);
   1106   1.5   thorpej 		txs->txs_ndesc++;
   1107   1.5   thorpej 	}
   1108   1.1   thorpej 
   1109   1.1   thorpej 	*cmdp = WTX_CMD_DEXT | WTC_DTYP_D;
   1110   1.1   thorpej 	*fieldsp = fields;
   1111   1.1   thorpej 
   1112   1.1   thorpej 	return (0);
   1113   1.1   thorpej }
   1114   1.1   thorpej 
   1115   1.1   thorpej /*
   1116   1.1   thorpej  * wm_start:		[ifnet interface function]
   1117   1.1   thorpej  *
   1118   1.1   thorpej  *	Start packet transmission on the interface.
   1119   1.1   thorpej  */
   1120   1.1   thorpej void
   1121   1.1   thorpej wm_start(struct ifnet *ifp)
   1122   1.1   thorpej {
   1123   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   1124  1.30    itojun 	struct mbuf *m0;
   1125  1.30    itojun #if 0 /* XXXJRT */
   1126  1.30    itojun 	struct m_tag *mtag;
   1127  1.30    itojun #endif
   1128   1.1   thorpej 	struct wm_txsoft *txs;
   1129   1.1   thorpej 	bus_dmamap_t dmamap;
   1130   1.1   thorpej 	int error, nexttx, lasttx, ofree, seg;
   1131   1.1   thorpej 	uint32_t cksumcmd, cksumfields;
   1132   1.1   thorpej 
   1133   1.1   thorpej 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
   1134   1.1   thorpej 		return;
   1135   1.1   thorpej 
   1136   1.1   thorpej 	/*
   1137   1.1   thorpej 	 * Remember the previous number of free descriptors.
   1138   1.1   thorpej 	 */
   1139   1.1   thorpej 	ofree = sc->sc_txfree;
   1140   1.1   thorpej 
   1141   1.1   thorpej 	/*
   1142   1.1   thorpej 	 * Loop through the send queue, setting up transmit descriptors
   1143   1.1   thorpej 	 * until we drain the queue, or use up all available transmit
   1144   1.1   thorpej 	 * descriptors.
   1145   1.1   thorpej 	 */
   1146   1.1   thorpej 	for (;;) {
   1147   1.1   thorpej 		/* Grab a packet off the queue. */
   1148   1.1   thorpej 		IFQ_POLL(&ifp->if_snd, m0);
   1149   1.1   thorpej 		if (m0 == NULL)
   1150   1.1   thorpej 			break;
   1151   1.1   thorpej 
   1152   1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   1153   1.1   thorpej 		    ("%s: TX: have packet to transmit: %p\n",
   1154   1.1   thorpej 		    sc->sc_dev.dv_xname, m0));
   1155   1.1   thorpej 
   1156   1.1   thorpej 		/* Get a work queue entry. */
   1157  1.10   thorpej 		if (sc->sc_txsfree < WM_TXQUEUE_GC) {
   1158  1.10   thorpej 			wm_txintr(sc);
   1159  1.10   thorpej 			if (sc->sc_txsfree == 0) {
   1160  1.10   thorpej 				DPRINTF(WM_DEBUG_TX,
   1161  1.10   thorpej 				    ("%s: TX: no free job descriptors\n",
   1162  1.10   thorpej 					sc->sc_dev.dv_xname));
   1163  1.10   thorpej 				WM_EVCNT_INCR(&sc->sc_ev_txsstall);
   1164  1.10   thorpej 				break;
   1165  1.10   thorpej 			}
   1166   1.1   thorpej 		}
   1167   1.1   thorpej 
   1168   1.1   thorpej 		txs = &sc->sc_txsoft[sc->sc_txsnext];
   1169   1.1   thorpej 		dmamap = txs->txs_dmamap;
   1170   1.1   thorpej 
   1171   1.1   thorpej 		/*
   1172   1.1   thorpej 		 * Load the DMA map.  If this fails, the packet either
   1173   1.1   thorpej 		 * didn't fit in the allotted number of segments, or we
   1174   1.1   thorpej 		 * were short on resources.  For the too-many-segments
   1175   1.1   thorpej 		 * case, we simply report an error and drop the packet,
   1176   1.1   thorpej 		 * since we can't sanely copy a jumbo packet to a single
   1177   1.1   thorpej 		 * buffer.
   1178   1.1   thorpej 		 */
   1179   1.1   thorpej 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   1180   1.1   thorpej 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT);
   1181   1.1   thorpej 		if (error) {
   1182   1.1   thorpej 			if (error == EFBIG) {
   1183   1.1   thorpej 				WM_EVCNT_INCR(&sc->sc_ev_txdrop);
   1184   1.1   thorpej 				printf("%s: Tx packet consumes too many "
   1185   1.1   thorpej 				    "DMA segments, dropping...\n",
   1186   1.1   thorpej 				    sc->sc_dev.dv_xname);
   1187   1.1   thorpej 				IFQ_DEQUEUE(&ifp->if_snd, m0);
   1188   1.1   thorpej 				m_freem(m0);
   1189   1.1   thorpej 				continue;
   1190   1.1   thorpej 			}
   1191   1.1   thorpej 			/*
   1192   1.1   thorpej 			 * Short on resources, just stop for now.
   1193   1.1   thorpej 			 */
   1194   1.1   thorpej 			DPRINTF(WM_DEBUG_TX,
   1195   1.1   thorpej 			    ("%s: TX: dmamap load failed: %d\n",
   1196   1.1   thorpej 			    sc->sc_dev.dv_xname, error));
   1197   1.1   thorpej 			break;
   1198   1.1   thorpej 		}
   1199   1.1   thorpej 
   1200   1.1   thorpej 		/*
   1201   1.1   thorpej 		 * Ensure we have enough descriptors free to describe
   1202   1.1   thorpej 		 * the packet.  Note, we always reserve one descriptor
   1203   1.1   thorpej 		 * at the end of the ring due to the semantics of the
   1204   1.1   thorpej 		 * TDT register, plus one more in the event we need
   1205   1.1   thorpej 		 * to re-load checksum offload context.
   1206   1.1   thorpej 		 */
   1207   1.1   thorpej 		if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) {
   1208   1.1   thorpej 			/*
   1209   1.1   thorpej 			 * Not enough free descriptors to transmit this
   1210   1.1   thorpej 			 * packet.  We haven't committed anything yet,
   1211   1.1   thorpej 			 * so just unload the DMA map, put the packet
   1212   1.1   thorpej 			 * pack on the queue, and punt.  Notify the upper
   1213   1.1   thorpej 			 * layer that there are no more slots left.
   1214   1.1   thorpej 			 */
   1215   1.1   thorpej 			DPRINTF(WM_DEBUG_TX,
   1216   1.1   thorpej 			    ("%s: TX: need %d descriptors, have %d\n",
   1217   1.1   thorpej 			    sc->sc_dev.dv_xname, dmamap->dm_nsegs,
   1218   1.1   thorpej 			    sc->sc_txfree - 1));
   1219   1.1   thorpej 			ifp->if_flags |= IFF_OACTIVE;
   1220   1.1   thorpej 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   1221   1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_txdstall);
   1222   1.1   thorpej 			break;
   1223   1.1   thorpej 		}
   1224   1.1   thorpej 
   1225   1.1   thorpej 		IFQ_DEQUEUE(&ifp->if_snd, m0);
   1226   1.1   thorpej 
   1227   1.1   thorpej 		/*
   1228   1.1   thorpej 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
   1229   1.1   thorpej 		 */
   1230   1.1   thorpej 
   1231   1.1   thorpej 		/* Sync the DMA map. */
   1232   1.1   thorpej 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   1233   1.1   thorpej 		    BUS_DMASYNC_PREWRITE);
   1234   1.1   thorpej 
   1235   1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   1236   1.1   thorpej 		    ("%s: TX: packet has %d DMA segments\n",
   1237   1.1   thorpej 		    sc->sc_dev.dv_xname, dmamap->dm_nsegs));
   1238   1.1   thorpej 
   1239   1.2   thorpej 		WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]);
   1240   1.1   thorpej 
   1241   1.1   thorpej 		/*
   1242   1.4   thorpej 		 * Store a pointer to the packet so that we can free it
   1243   1.4   thorpej 		 * later.
   1244   1.4   thorpej 		 *
   1245   1.4   thorpej 		 * Initially, we consider the number of descriptors the
   1246   1.4   thorpej 		 * packet uses the number of DMA segments.  This may be
   1247   1.4   thorpej 		 * incremented by 1 if we do checksum offload (a descriptor
   1248   1.4   thorpej 		 * is used to set the checksum context).
   1249   1.4   thorpej 		 */
   1250   1.4   thorpej 		txs->txs_mbuf = m0;
   1251   1.6   thorpej 		txs->txs_firstdesc = sc->sc_txnext;
   1252   1.4   thorpej 		txs->txs_ndesc = dmamap->dm_nsegs;
   1253   1.4   thorpej 
   1254   1.4   thorpej 		/*
   1255   1.1   thorpej 		 * Set up checksum offload parameters for
   1256   1.1   thorpej 		 * this packet.
   1257   1.1   thorpej 		 */
   1258   1.1   thorpej 		if (m0->m_pkthdr.csum_flags &
   1259   1.1   thorpej 		    (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) {
   1260   1.4   thorpej 			if (wm_tx_cksum(sc, txs, &cksumcmd,
   1261   1.4   thorpej 					&cksumfields) != 0) {
   1262   1.1   thorpej 				/* Error message already displayed. */
   1263   1.1   thorpej 				m_freem(m0);
   1264   1.1   thorpej 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   1265   1.4   thorpej 				txs->txs_mbuf = NULL;
   1266   1.1   thorpej 				continue;
   1267   1.1   thorpej 			}
   1268   1.1   thorpej 		} else {
   1269   1.1   thorpej 			cksumcmd = 0;
   1270   1.1   thorpej 			cksumfields = 0;
   1271   1.1   thorpej 		}
   1272   1.1   thorpej 
   1273   1.6   thorpej 		cksumcmd |= htole32(WTX_CMD_IDE);
   1274   1.6   thorpej 
   1275   1.1   thorpej 		/*
   1276   1.1   thorpej 		 * Initialize the transmit descriptor.
   1277   1.1   thorpej 		 */
   1278   1.1   thorpej 		for (nexttx = sc->sc_txnext, seg = 0;
   1279   1.1   thorpej 		     seg < dmamap->dm_nsegs;
   1280   1.1   thorpej 		     seg++, nexttx = WM_NEXTTX(nexttx)) {
   1281   1.1   thorpej 			/*
   1282   1.1   thorpej 			 * Note: we currently only use 32-bit DMA
   1283   1.1   thorpej 			 * addresses.
   1284   1.1   thorpej 			 */
   1285  1.18    briggs 			sc->sc_txdescs[nexttx].wtx_addr.wa_high = 0;
   1286   1.1   thorpej 			sc->sc_txdescs[nexttx].wtx_addr.wa_low =
   1287   1.1   thorpej 			    htole32(dmamap->dm_segs[seg].ds_addr);
   1288   1.1   thorpej 			sc->sc_txdescs[nexttx].wtx_cmdlen = cksumcmd |
   1289   1.1   thorpej 			    htole32(dmamap->dm_segs[seg].ds_len);
   1290   1.1   thorpej 			sc->sc_txdescs[nexttx].wtx_fields.wtxu_bits =
   1291   1.1   thorpej 			    cksumfields;
   1292   1.1   thorpej 			lasttx = nexttx;
   1293   1.1   thorpej 
   1294   1.1   thorpej 			DPRINTF(WM_DEBUG_TX,
   1295   1.1   thorpej 			    ("%s: TX: desc %d: low 0x%08x, len 0x%04x\n",
   1296   1.1   thorpej 			    sc->sc_dev.dv_xname, nexttx,
   1297   1.1   thorpej 			    (uint32_t) dmamap->dm_segs[seg].ds_addr,
   1298   1.1   thorpej 			    (uint32_t) dmamap->dm_segs[seg].ds_len));
   1299   1.1   thorpej 		}
   1300   1.1   thorpej 
   1301   1.1   thorpej 		/*
   1302   1.1   thorpej 		 * Set up the command byte on the last descriptor of
   1303   1.1   thorpej 		 * the packet.  If we're in the interrupt delay window,
   1304   1.1   thorpej 		 * delay the interrupt.
   1305   1.1   thorpej 		 */
   1306   1.1   thorpej 		sc->sc_txdescs[lasttx].wtx_cmdlen |=
   1307   1.7   thorpej 		    htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS);
   1308   1.1   thorpej 
   1309   1.1   thorpej #if 0 /* XXXJRT */
   1310   1.1   thorpej 		/*
   1311   1.1   thorpej 		 * If VLANs are enabled and the packet has a VLAN tag, set
   1312   1.1   thorpej 		 * up the descriptor to encapsulate the packet for us.
   1313   1.1   thorpej 		 *
   1314   1.1   thorpej 		 * This is only valid on the last descriptor of the packet.
   1315   1.1   thorpej 		 */
   1316   1.1   thorpej 		if (sc->sc_ethercom.ec_nvlans != 0 &&
   1317  1.30    itojun 		    (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) {
   1318   1.1   thorpej 			sc->sc_txdescs[lasttx].wtx_cmdlen |=
   1319   1.1   thorpej 			    htole32(WTX_CMD_VLE);
   1320   1.1   thorpej 			sc->sc_txdescs[lasttx].wtx_fields.wtxu_fields.wtxu_vlan
   1321  1.31    itojun 			    = htole16(*(u_int *)(mtag + 1) & 0xffff);
   1322   1.1   thorpej 		}
   1323   1.1   thorpej #endif /* XXXJRT */
   1324   1.1   thorpej 
   1325   1.6   thorpej 		txs->txs_lastdesc = lasttx;
   1326   1.6   thorpej 
   1327   1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   1328   1.1   thorpej 		    ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname,
   1329   1.1   thorpej 		    lasttx, sc->sc_txdescs[lasttx].wtx_cmdlen));
   1330   1.1   thorpej 
   1331   1.1   thorpej 		/* Sync the descriptors we're using. */
   1332   1.1   thorpej 		WM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
   1333   1.1   thorpej 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1334   1.1   thorpej 
   1335   1.1   thorpej 		/* Give the packet to the chip. */
   1336   1.1   thorpej 		CSR_WRITE(sc, sc->sc_tdt_reg, nexttx);
   1337   1.1   thorpej 
   1338   1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   1339   1.1   thorpej 		    ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx));
   1340   1.1   thorpej 
   1341   1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   1342   1.1   thorpej 		    ("%s: TX: finished transmitting packet, job %d\n",
   1343   1.1   thorpej 		    sc->sc_dev.dv_xname, sc->sc_txsnext));
   1344   1.1   thorpej 
   1345   1.1   thorpej 		/* Advance the tx pointer. */
   1346   1.4   thorpej 		sc->sc_txfree -= txs->txs_ndesc;
   1347   1.1   thorpej 		sc->sc_txnext = nexttx;
   1348   1.1   thorpej 
   1349   1.1   thorpej 		sc->sc_txsfree--;
   1350   1.1   thorpej 		sc->sc_txsnext = WM_NEXTTXS(sc->sc_txsnext);
   1351   1.1   thorpej 
   1352   1.1   thorpej #if NBPFILTER > 0
   1353   1.1   thorpej 		/* Pass the packet to any BPF listeners. */
   1354   1.1   thorpej 		if (ifp->if_bpf)
   1355   1.1   thorpej 			bpf_mtap(ifp->if_bpf, m0);
   1356   1.1   thorpej #endif /* NBPFILTER > 0 */
   1357   1.1   thorpej 	}
   1358   1.1   thorpej 
   1359   1.6   thorpej 	if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) {
   1360   1.1   thorpej 		/* No more slots; notify upper layer. */
   1361   1.1   thorpej 		ifp->if_flags |= IFF_OACTIVE;
   1362   1.1   thorpej 	}
   1363   1.1   thorpej 
   1364   1.1   thorpej 	if (sc->sc_txfree != ofree) {
   1365   1.1   thorpej 		/* Set a watchdog timer in case the chip flakes out. */
   1366   1.1   thorpej 		ifp->if_timer = 5;
   1367   1.1   thorpej 	}
   1368   1.1   thorpej }
   1369   1.1   thorpej 
   1370   1.1   thorpej /*
   1371   1.1   thorpej  * wm_watchdog:		[ifnet interface function]
   1372   1.1   thorpej  *
   1373   1.1   thorpej  *	Watchdog timer handler.
   1374   1.1   thorpej  */
   1375   1.1   thorpej void
   1376   1.1   thorpej wm_watchdog(struct ifnet *ifp)
   1377   1.1   thorpej {
   1378   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   1379   1.1   thorpej 
   1380   1.1   thorpej 	/*
   1381   1.1   thorpej 	 * Since we're using delayed interrupts, sweep up
   1382   1.1   thorpej 	 * before we report an error.
   1383   1.1   thorpej 	 */
   1384   1.1   thorpej 	wm_txintr(sc);
   1385   1.1   thorpej 
   1386   1.1   thorpej 	if (sc->sc_txfree != WM_NTXDESC) {
   1387   1.2   thorpej 		printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n",
   1388   1.2   thorpej 		    sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree,
   1389   1.2   thorpej 		    sc->sc_txnext);
   1390   1.1   thorpej 		ifp->if_oerrors++;
   1391   1.1   thorpej 
   1392   1.1   thorpej 		/* Reset the interface. */
   1393   1.1   thorpej 		(void) wm_init(ifp);
   1394   1.1   thorpej 	}
   1395   1.1   thorpej 
   1396   1.1   thorpej 	/* Try to get more packets going. */
   1397   1.1   thorpej 	wm_start(ifp);
   1398   1.1   thorpej }
   1399   1.1   thorpej 
   1400   1.1   thorpej /*
   1401   1.1   thorpej  * wm_ioctl:		[ifnet interface function]
   1402   1.1   thorpej  *
   1403   1.1   thorpej  *	Handle control requests from the operator.
   1404   1.1   thorpej  */
   1405   1.1   thorpej int
   1406   1.1   thorpej wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
   1407   1.1   thorpej {
   1408   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   1409   1.1   thorpej 	struct ifreq *ifr = (struct ifreq *) data;
   1410   1.1   thorpej 	int s, error;
   1411   1.1   thorpej 
   1412   1.1   thorpej 	s = splnet();
   1413   1.1   thorpej 
   1414   1.1   thorpej 	switch (cmd) {
   1415   1.1   thorpej 	case SIOCSIFMEDIA:
   1416   1.1   thorpej 	case SIOCGIFMEDIA:
   1417   1.1   thorpej 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
   1418   1.1   thorpej 		break;
   1419   1.1   thorpej 
   1420   1.1   thorpej 	default:
   1421   1.1   thorpej 		error = ether_ioctl(ifp, cmd, data);
   1422   1.1   thorpej 		if (error == ENETRESET) {
   1423   1.1   thorpej 			/*
   1424   1.1   thorpej 			 * Multicast list has changed; set the hardware filter
   1425   1.1   thorpej 			 * accordingly.
   1426   1.1   thorpej 			 */
   1427   1.1   thorpej 			wm_set_filter(sc);
   1428   1.1   thorpej 			error = 0;
   1429   1.1   thorpej 		}
   1430   1.1   thorpej 		break;
   1431   1.1   thorpej 	}
   1432   1.1   thorpej 
   1433   1.1   thorpej 	/* Try to get more packets going. */
   1434   1.1   thorpej 	wm_start(ifp);
   1435   1.1   thorpej 
   1436   1.1   thorpej 	splx(s);
   1437   1.1   thorpej 	return (error);
   1438   1.1   thorpej }
   1439   1.1   thorpej 
   1440   1.1   thorpej /*
   1441   1.1   thorpej  * wm_intr:
   1442   1.1   thorpej  *
   1443   1.1   thorpej  *	Interrupt service routine.
   1444   1.1   thorpej  */
   1445   1.1   thorpej int
   1446   1.1   thorpej wm_intr(void *arg)
   1447   1.1   thorpej {
   1448   1.1   thorpej 	struct wm_softc *sc = arg;
   1449   1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1450   1.1   thorpej 	uint32_t icr;
   1451   1.1   thorpej 	int wantinit, handled = 0;
   1452   1.1   thorpej 
   1453   1.1   thorpej 	for (wantinit = 0; wantinit == 0;) {
   1454   1.1   thorpej 		icr = CSR_READ(sc, WMREG_ICR);
   1455   1.1   thorpej 		if ((icr & sc->sc_icr) == 0)
   1456   1.1   thorpej 			break;
   1457  1.21    itojun 
   1458  1.22    itojun #if 0 /*NRND > 0*/
   1459  1.21    itojun 		if (RND_ENABLED(&sc->rnd_source))
   1460  1.21    itojun 			rnd_add_uint32(&sc->rnd_source, icr);
   1461  1.21    itojun #endif
   1462   1.1   thorpej 
   1463   1.1   thorpej 		handled = 1;
   1464   1.1   thorpej 
   1465  1.10   thorpej #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   1466   1.1   thorpej 		if (icr & (ICR_RXDMT0|ICR_RXT0)) {
   1467   1.1   thorpej 			DPRINTF(WM_DEBUG_RX,
   1468   1.1   thorpej 			    ("%s: RX: got Rx intr 0x%08x\n",
   1469   1.1   thorpej 			    sc->sc_dev.dv_xname,
   1470   1.1   thorpej 			    icr & (ICR_RXDMT0|ICR_RXT0)));
   1471   1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_rxintr);
   1472   1.1   thorpej 		}
   1473  1.10   thorpej #endif
   1474  1.10   thorpej 		wm_rxintr(sc);
   1475   1.1   thorpej 
   1476  1.10   thorpej #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   1477  1.10   thorpej 		if (icr & ICR_TXDW) {
   1478   1.1   thorpej 			DPRINTF(WM_DEBUG_TX,
   1479  1.10   thorpej 			    ("%s: TX: got TDXW interrupt\n",
   1480   1.1   thorpej 			    sc->sc_dev.dv_xname));
   1481  1.10   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_txdw);
   1482  1.10   thorpej 		}
   1483   1.4   thorpej #endif
   1484  1.10   thorpej 		wm_txintr(sc);
   1485   1.1   thorpej 
   1486   1.1   thorpej 		if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) {
   1487   1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   1488   1.1   thorpej 			wm_linkintr(sc, icr);
   1489   1.1   thorpej 		}
   1490   1.1   thorpej 
   1491   1.1   thorpej 		if (icr & ICR_RXO) {
   1492   1.1   thorpej 			printf("%s: Receive overrun\n", sc->sc_dev.dv_xname);
   1493   1.1   thorpej 			wantinit = 1;
   1494   1.1   thorpej 		}
   1495   1.1   thorpej 	}
   1496   1.1   thorpej 
   1497   1.1   thorpej 	if (handled) {
   1498   1.1   thorpej 		if (wantinit)
   1499   1.1   thorpej 			wm_init(ifp);
   1500   1.1   thorpej 
   1501   1.1   thorpej 		/* Try to get more packets going. */
   1502   1.1   thorpej 		wm_start(ifp);
   1503   1.1   thorpej 	}
   1504   1.1   thorpej 
   1505   1.1   thorpej 	return (handled);
   1506   1.1   thorpej }
   1507   1.1   thorpej 
   1508   1.1   thorpej /*
   1509   1.1   thorpej  * wm_txintr:
   1510   1.1   thorpej  *
   1511   1.1   thorpej  *	Helper; handle transmit interrupts.
   1512   1.1   thorpej  */
   1513   1.1   thorpej void
   1514   1.1   thorpej wm_txintr(struct wm_softc *sc)
   1515   1.1   thorpej {
   1516   1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1517   1.1   thorpej 	struct wm_txsoft *txs;
   1518   1.1   thorpej 	uint8_t status;
   1519   1.1   thorpej 	int i;
   1520   1.1   thorpej 
   1521   1.1   thorpej 	ifp->if_flags &= ~IFF_OACTIVE;
   1522   1.1   thorpej 
   1523   1.1   thorpej 	/*
   1524   1.1   thorpej 	 * Go through the Tx list and free mbufs for those
   1525  1.16    simonb 	 * frames which have been transmitted.
   1526   1.1   thorpej 	 */
   1527   1.1   thorpej 	for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN;
   1528   1.1   thorpej 	     i = WM_NEXTTXS(i), sc->sc_txsfree++) {
   1529   1.1   thorpej 		txs = &sc->sc_txsoft[i];
   1530   1.1   thorpej 
   1531   1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   1532   1.1   thorpej 		    ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i));
   1533   1.1   thorpej 
   1534   1.1   thorpej 		WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs,
   1535   1.1   thorpej 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   1536   1.1   thorpej 
   1537   1.1   thorpej 		status = le32toh(sc->sc_txdescs[
   1538   1.1   thorpej 		    txs->txs_lastdesc].wtx_fields.wtxu_bits);
   1539  1.20   thorpej 		if ((status & WTX_ST_DD) == 0) {
   1540  1.20   thorpej 			WM_CDTXSYNC(sc, txs->txs_lastdesc, 1,
   1541  1.20   thorpej 			    BUS_DMASYNC_PREREAD);
   1542   1.1   thorpej 			break;
   1543  1.20   thorpej 		}
   1544   1.1   thorpej 
   1545   1.1   thorpej 		DPRINTF(WM_DEBUG_TX,
   1546   1.1   thorpej 		    ("%s: TX: job %d done: descs %d..%d\n",
   1547   1.1   thorpej 		    sc->sc_dev.dv_xname, i, txs->txs_firstdesc,
   1548   1.1   thorpej 		    txs->txs_lastdesc));
   1549   1.1   thorpej 
   1550   1.1   thorpej 		/*
   1551   1.1   thorpej 		 * XXX We should probably be using the statistics
   1552   1.1   thorpej 		 * XXX registers, but I don't know if they exist
   1553  1.11   thorpej 		 * XXX on chips before the i82544.
   1554   1.1   thorpej 		 */
   1555   1.1   thorpej 
   1556   1.1   thorpej #ifdef WM_EVENT_COUNTERS
   1557   1.1   thorpej 		if (status & WTX_ST_TU)
   1558   1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_tu);
   1559   1.1   thorpej #endif /* WM_EVENT_COUNTERS */
   1560   1.1   thorpej 
   1561   1.1   thorpej 		if (status & (WTX_ST_EC|WTX_ST_LC)) {
   1562   1.1   thorpej 			ifp->if_oerrors++;
   1563   1.1   thorpej 			if (status & WTX_ST_LC)
   1564   1.1   thorpej 				printf("%s: late collision\n",
   1565   1.1   thorpej 				    sc->sc_dev.dv_xname);
   1566   1.1   thorpej 			else if (status & WTX_ST_EC) {
   1567   1.1   thorpej 				ifp->if_collisions += 16;
   1568   1.1   thorpej 				printf("%s: excessive collisions\n",
   1569   1.1   thorpej 				    sc->sc_dev.dv_xname);
   1570   1.1   thorpej 			}
   1571   1.1   thorpej 		} else
   1572   1.1   thorpej 			ifp->if_opackets++;
   1573   1.1   thorpej 
   1574   1.4   thorpej 		sc->sc_txfree += txs->txs_ndesc;
   1575   1.1   thorpej 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
   1576   1.1   thorpej 		    0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   1577   1.1   thorpej 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   1578   1.1   thorpej 		m_freem(txs->txs_mbuf);
   1579   1.1   thorpej 		txs->txs_mbuf = NULL;
   1580   1.1   thorpej 	}
   1581   1.1   thorpej 
   1582   1.1   thorpej 	/* Update the dirty transmit buffer pointer. */
   1583   1.1   thorpej 	sc->sc_txsdirty = i;
   1584   1.1   thorpej 	DPRINTF(WM_DEBUG_TX,
   1585   1.1   thorpej 	    ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i));
   1586   1.1   thorpej 
   1587   1.1   thorpej 	/*
   1588   1.1   thorpej 	 * If there are no more pending transmissions, cancel the watchdog
   1589   1.1   thorpej 	 * timer.
   1590   1.1   thorpej 	 */
   1591  1.10   thorpej 	if (sc->sc_txsfree == WM_TXQUEUELEN)
   1592   1.1   thorpej 		ifp->if_timer = 0;
   1593   1.1   thorpej }
   1594   1.1   thorpej 
   1595   1.1   thorpej /*
   1596   1.1   thorpej  * wm_rxintr:
   1597   1.1   thorpej  *
   1598   1.1   thorpej  *	Helper; handle receive interrupts.
   1599   1.1   thorpej  */
   1600   1.1   thorpej void
   1601   1.1   thorpej wm_rxintr(struct wm_softc *sc)
   1602   1.1   thorpej {
   1603   1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1604   1.1   thorpej 	struct wm_rxsoft *rxs;
   1605   1.1   thorpej 	struct mbuf *m;
   1606   1.1   thorpej 	int i, len;
   1607   1.1   thorpej 	uint8_t status, errors;
   1608   1.1   thorpej 
   1609   1.1   thorpej 	for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
   1610   1.1   thorpej 		rxs = &sc->sc_rxsoft[i];
   1611   1.1   thorpej 
   1612   1.1   thorpej 		DPRINTF(WM_DEBUG_RX,
   1613   1.1   thorpej 		    ("%s: RX: checking descriptor %d\n",
   1614   1.1   thorpej 		    sc->sc_dev.dv_xname, i));
   1615   1.1   thorpej 
   1616   1.1   thorpej 		WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   1617   1.1   thorpej 
   1618   1.1   thorpej 		status = sc->sc_rxdescs[i].wrx_status;
   1619   1.1   thorpej 		errors = sc->sc_rxdescs[i].wrx_errors;
   1620   1.1   thorpej 		len = le16toh(sc->sc_rxdescs[i].wrx_len);
   1621   1.1   thorpej 
   1622   1.1   thorpej 		if ((status & WRX_ST_DD) == 0) {
   1623   1.1   thorpej 			/*
   1624   1.1   thorpej 			 * We have processed all of the receive descriptors.
   1625   1.1   thorpej 			 */
   1626  1.20   thorpej 			WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
   1627   1.1   thorpej 			break;
   1628   1.1   thorpej 		}
   1629   1.1   thorpej 
   1630   1.1   thorpej 		if (__predict_false(sc->sc_rxdiscard)) {
   1631   1.1   thorpej 			DPRINTF(WM_DEBUG_RX,
   1632   1.1   thorpej 			    ("%s: RX: discarding contents of descriptor %d\n",
   1633   1.1   thorpej 			    sc->sc_dev.dv_xname, i));
   1634   1.1   thorpej 			WM_INIT_RXDESC(sc, i);
   1635   1.1   thorpej 			if (status & WRX_ST_EOP) {
   1636   1.1   thorpej 				/* Reset our state. */
   1637   1.1   thorpej 				DPRINTF(WM_DEBUG_RX,
   1638   1.1   thorpej 				    ("%s: RX: resetting rxdiscard -> 0\n",
   1639   1.1   thorpej 				    sc->sc_dev.dv_xname));
   1640   1.1   thorpej 				sc->sc_rxdiscard = 0;
   1641   1.1   thorpej 			}
   1642   1.1   thorpej 			continue;
   1643   1.1   thorpej 		}
   1644   1.1   thorpej 
   1645   1.1   thorpej 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   1646   1.1   thorpej 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   1647   1.1   thorpej 
   1648   1.1   thorpej 		m = rxs->rxs_mbuf;
   1649   1.1   thorpej 
   1650   1.1   thorpej 		/*
   1651   1.1   thorpej 		 * Add a new receive buffer to the ring.
   1652   1.1   thorpej 		 */
   1653   1.1   thorpej 		if (wm_add_rxbuf(sc, i) != 0) {
   1654   1.1   thorpej 			/*
   1655   1.1   thorpej 			 * Failed, throw away what we've done so
   1656   1.1   thorpej 			 * far, and discard the rest of the packet.
   1657   1.1   thorpej 			 */
   1658   1.1   thorpej 			ifp->if_ierrors++;
   1659   1.1   thorpej 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   1660   1.1   thorpej 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   1661   1.1   thorpej 			WM_INIT_RXDESC(sc, i);
   1662   1.1   thorpej 			if ((status & WRX_ST_EOP) == 0)
   1663   1.1   thorpej 				sc->sc_rxdiscard = 1;
   1664   1.1   thorpej 			if (sc->sc_rxhead != NULL)
   1665   1.1   thorpej 				m_freem(sc->sc_rxhead);
   1666   1.1   thorpej 			WM_RXCHAIN_RESET(sc);
   1667   1.1   thorpej 			DPRINTF(WM_DEBUG_RX,
   1668   1.1   thorpej 			    ("%s: RX: Rx buffer allocation failed, "
   1669   1.1   thorpej 			    "dropping packet%s\n", sc->sc_dev.dv_xname,
   1670   1.1   thorpej 			    sc->sc_rxdiscard ? " (discard)" : ""));
   1671   1.1   thorpej 			continue;
   1672   1.1   thorpej 		}
   1673   1.1   thorpej 
   1674   1.1   thorpej 		WM_RXCHAIN_LINK(sc, m);
   1675   1.1   thorpej 
   1676   1.1   thorpej 		m->m_len = len;
   1677   1.1   thorpej 
   1678   1.1   thorpej 		DPRINTF(WM_DEBUG_RX,
   1679   1.1   thorpej 		    ("%s: RX: buffer at %p len %d\n",
   1680   1.1   thorpej 		    sc->sc_dev.dv_xname, m->m_data, len));
   1681   1.1   thorpej 
   1682   1.1   thorpej 		/*
   1683   1.1   thorpej 		 * If this is not the end of the packet, keep
   1684   1.1   thorpej 		 * looking.
   1685   1.1   thorpej 		 */
   1686   1.1   thorpej 		if ((status & WRX_ST_EOP) == 0) {
   1687   1.1   thorpej 			sc->sc_rxlen += len;
   1688   1.1   thorpej 			DPRINTF(WM_DEBUG_RX,
   1689   1.1   thorpej 			    ("%s: RX: not yet EOP, rxlen -> %d\n",
   1690   1.1   thorpej 			    sc->sc_dev.dv_xname, sc->sc_rxlen));
   1691   1.1   thorpej 			continue;
   1692   1.1   thorpej 		}
   1693   1.1   thorpej 
   1694   1.1   thorpej 		/*
   1695   1.1   thorpej 		 * Okay, we have the entire packet now...
   1696   1.1   thorpej 		 */
   1697   1.1   thorpej 		*sc->sc_rxtailp = NULL;
   1698   1.1   thorpej 		m = sc->sc_rxhead;
   1699   1.1   thorpej 		len += sc->sc_rxlen;
   1700   1.1   thorpej 
   1701   1.1   thorpej 		WM_RXCHAIN_RESET(sc);
   1702   1.1   thorpej 
   1703   1.1   thorpej 		DPRINTF(WM_DEBUG_RX,
   1704   1.1   thorpej 		    ("%s: RX: have entire packet, len -> %d\n",
   1705   1.1   thorpej 		    sc->sc_dev.dv_xname, len));
   1706   1.1   thorpej 
   1707   1.1   thorpej 		/*
   1708   1.1   thorpej 		 * If an error occurred, update stats and drop the packet.
   1709   1.1   thorpej 		 */
   1710   1.1   thorpej 		if (errors &
   1711   1.1   thorpej 		     (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
   1712   1.1   thorpej 			ifp->if_ierrors++;
   1713   1.1   thorpej 			if (errors & WRX_ER_SE)
   1714   1.1   thorpej 				printf("%s: symbol error\n",
   1715   1.1   thorpej 				    sc->sc_dev.dv_xname);
   1716   1.1   thorpej 			else if (errors & WRX_ER_SEQ)
   1717   1.1   thorpej 				printf("%s: receive sequence error\n",
   1718   1.1   thorpej 				    sc->sc_dev.dv_xname);
   1719   1.1   thorpej 			else if (errors & WRX_ER_CE)
   1720   1.1   thorpej 				printf("%s: CRC error\n",
   1721   1.1   thorpej 				    sc->sc_dev.dv_xname);
   1722   1.1   thorpej 			m_freem(m);
   1723   1.1   thorpej 			continue;
   1724   1.1   thorpej 		}
   1725   1.1   thorpej 
   1726   1.1   thorpej 		/*
   1727   1.1   thorpej 		 * No errors.  Receive the packet.
   1728   1.1   thorpej 		 *
   1729   1.1   thorpej 		 * Note, we have configured the chip to include the
   1730   1.1   thorpej 		 * CRC with every packet.
   1731   1.1   thorpej 		 */
   1732   1.1   thorpej 		m->m_flags |= M_HASFCS;
   1733   1.1   thorpej 		m->m_pkthdr.rcvif = ifp;
   1734   1.1   thorpej 		m->m_pkthdr.len = len;
   1735   1.1   thorpej 
   1736   1.1   thorpej #if 0 /* XXXJRT */
   1737   1.1   thorpej 		/*
   1738   1.1   thorpej 		 * If VLANs are enabled, VLAN packets have been unwrapped
   1739   1.1   thorpej 		 * for us.  Associate the tag with the packet.
   1740   1.1   thorpej 		 */
   1741   1.1   thorpej 		if (sc->sc_ethercom.ec_nvlans != 0 &&
   1742   1.1   thorpej 		    (status & WRX_ST_VP) != 0) {
   1743  1.30    itojun 			struct m_tag *vtag;
   1744   1.1   thorpej 
   1745  1.30    itojun 			vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int),
   1746  1.30    itojun 			    M_NOWAIT);
   1747   1.1   thorpej 			if (vtag == NULL) {
   1748   1.1   thorpej 				ifp->if_ierrors++;
   1749   1.1   thorpej 				printf("%s: unable to allocate VLAN tag\n",
   1750   1.1   thorpej 				    sc->sc_dev.dv_xname);
   1751   1.1   thorpej 				m_freem(m);
   1752   1.1   thorpej 				continue;
   1753   1.1   thorpej 			}
   1754   1.1   thorpej 
   1755  1.30    itojun 			*(u_int *)(vtag + 1) =
   1756   1.1   thorpej 			    le16toh(sc->sc_rxdescs[i].wrx_special);
   1757   1.1   thorpej 		}
   1758   1.1   thorpej #endif /* XXXJRT */
   1759   1.1   thorpej 
   1760   1.1   thorpej 		/*
   1761   1.1   thorpej 		 * Set up checksum info for this packet.
   1762   1.1   thorpej 		 */
   1763   1.1   thorpej 		if (status & WRX_ST_IPCS) {
   1764   1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_rxipsum);
   1765   1.1   thorpej 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
   1766   1.1   thorpej 			if (errors & WRX_ER_IPE)
   1767   1.1   thorpej 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
   1768   1.1   thorpej 		}
   1769   1.1   thorpej 		if (status & WRX_ST_TCPCS) {
   1770   1.1   thorpej 			/*
   1771   1.1   thorpej 			 * Note: we don't know if this was TCP or UDP,
   1772   1.1   thorpej 			 * so we just set both bits, and expect the
   1773   1.1   thorpej 			 * upper layers to deal.
   1774   1.1   thorpej 			 */
   1775   1.1   thorpej 			WM_EVCNT_INCR(&sc->sc_ev_rxtusum);
   1776   1.1   thorpej 			m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4;
   1777   1.1   thorpej 			if (errors & WRX_ER_TCPE)
   1778   1.1   thorpej 				m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD;
   1779   1.1   thorpej 		}
   1780   1.1   thorpej 
   1781   1.1   thorpej 		ifp->if_ipackets++;
   1782   1.1   thorpej 
   1783   1.1   thorpej #if NBPFILTER > 0
   1784   1.1   thorpej 		/* Pass this up to any BPF listeners. */
   1785   1.1   thorpej 		if (ifp->if_bpf)
   1786   1.1   thorpej 			bpf_mtap(ifp->if_bpf, m);
   1787   1.1   thorpej #endif /* NBPFILTER > 0 */
   1788   1.1   thorpej 
   1789   1.1   thorpej 		/* Pass it on. */
   1790   1.1   thorpej 		(*ifp->if_input)(ifp, m);
   1791   1.1   thorpej 	}
   1792   1.1   thorpej 
   1793   1.1   thorpej 	/* Update the receive pointer. */
   1794   1.1   thorpej 	sc->sc_rxptr = i;
   1795   1.1   thorpej 
   1796   1.1   thorpej 	DPRINTF(WM_DEBUG_RX,
   1797   1.1   thorpej 	    ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i));
   1798   1.1   thorpej }
   1799   1.1   thorpej 
   1800   1.1   thorpej /*
   1801   1.1   thorpej  * wm_linkintr:
   1802   1.1   thorpej  *
   1803   1.1   thorpej  *	Helper; handle link interrupts.
   1804   1.1   thorpej  */
   1805   1.1   thorpej void
   1806   1.1   thorpej wm_linkintr(struct wm_softc *sc, uint32_t icr)
   1807   1.1   thorpej {
   1808   1.1   thorpej 	uint32_t status;
   1809   1.1   thorpej 
   1810   1.1   thorpej 	/*
   1811   1.1   thorpej 	 * If we get a link status interrupt on a 1000BASE-T
   1812   1.1   thorpej 	 * device, just fall into the normal MII tick path.
   1813   1.1   thorpej 	 */
   1814   1.1   thorpej 	if (sc->sc_flags & WM_F_HAS_MII) {
   1815   1.1   thorpej 		if (icr & ICR_LSC) {
   1816   1.1   thorpej 			DPRINTF(WM_DEBUG_LINK,
   1817   1.1   thorpej 			    ("%s: LINK: LSC -> mii_tick\n",
   1818   1.1   thorpej 			    sc->sc_dev.dv_xname));
   1819   1.1   thorpej 			mii_tick(&sc->sc_mii);
   1820   1.1   thorpej 		} else if (icr & ICR_RXSEQ) {
   1821   1.1   thorpej 			DPRINTF(WM_DEBUG_LINK,
   1822   1.1   thorpej 			    ("%s: LINK Receive sequence error\n",
   1823   1.1   thorpej 			    sc->sc_dev.dv_xname));
   1824   1.1   thorpej 		}
   1825   1.1   thorpej 		return;
   1826   1.1   thorpej 	}
   1827   1.1   thorpej 
   1828   1.1   thorpej 	/*
   1829   1.1   thorpej 	 * If we are now receiving /C/, check for link again in
   1830   1.1   thorpej 	 * a couple of link clock ticks.
   1831   1.1   thorpej 	 */
   1832   1.1   thorpej 	if (icr & ICR_RXCFG) {
   1833   1.1   thorpej 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n",
   1834   1.1   thorpej 		    sc->sc_dev.dv_xname));
   1835   1.1   thorpej 		sc->sc_tbi_anstate = 2;
   1836   1.1   thorpej 	}
   1837   1.1   thorpej 
   1838   1.1   thorpej 	if (icr & ICR_LSC) {
   1839   1.1   thorpej 		status = CSR_READ(sc, WMREG_STATUS);
   1840   1.1   thorpej 		if (status & STATUS_LU) {
   1841   1.1   thorpej 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
   1842   1.1   thorpej 			    sc->sc_dev.dv_xname,
   1843   1.1   thorpej 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   1844   1.1   thorpej 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   1845   1.1   thorpej 			if (status & STATUS_FD)
   1846   1.1   thorpej 				sc->sc_tctl |=
   1847   1.1   thorpej 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   1848   1.1   thorpej 			else
   1849   1.1   thorpej 				sc->sc_tctl |=
   1850   1.1   thorpej 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   1851   1.1   thorpej 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   1852   1.1   thorpej 			sc->sc_tbi_linkup = 1;
   1853   1.1   thorpej 		} else {
   1854   1.1   thorpej 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   1855   1.1   thorpej 			    sc->sc_dev.dv_xname));
   1856   1.1   thorpej 			sc->sc_tbi_linkup = 0;
   1857   1.1   thorpej 		}
   1858   1.1   thorpej 		sc->sc_tbi_anstate = 2;
   1859   1.1   thorpej 		wm_tbi_set_linkled(sc);
   1860   1.1   thorpej 	} else if (icr & ICR_RXSEQ) {
   1861   1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   1862   1.1   thorpej 		    ("%s: LINK: Receive sequence error\n",
   1863   1.1   thorpej 		    sc->sc_dev.dv_xname));
   1864   1.1   thorpej 	}
   1865   1.1   thorpej }
   1866   1.1   thorpej 
   1867   1.1   thorpej /*
   1868   1.1   thorpej  * wm_tick:
   1869   1.1   thorpej  *
   1870   1.1   thorpej  *	One second timer, used to check link status, sweep up
   1871   1.1   thorpej  *	completed transmit jobs, etc.
   1872   1.1   thorpej  */
   1873   1.1   thorpej void
   1874   1.1   thorpej wm_tick(void *arg)
   1875   1.1   thorpej {
   1876   1.1   thorpej 	struct wm_softc *sc = arg;
   1877   1.1   thorpej 	int s;
   1878   1.1   thorpej 
   1879   1.1   thorpej 	s = splnet();
   1880   1.1   thorpej 
   1881   1.1   thorpej 	if (sc->sc_flags & WM_F_HAS_MII)
   1882   1.1   thorpej 		mii_tick(&sc->sc_mii);
   1883   1.1   thorpej 	else
   1884   1.1   thorpej 		wm_tbi_check_link(sc);
   1885   1.1   thorpej 
   1886   1.1   thorpej 	splx(s);
   1887   1.1   thorpej 
   1888   1.1   thorpej 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   1889   1.1   thorpej }
   1890   1.1   thorpej 
   1891   1.1   thorpej /*
   1892   1.1   thorpej  * wm_reset:
   1893   1.1   thorpej  *
   1894   1.1   thorpej  *	Reset the i82542 chip.
   1895   1.1   thorpej  */
   1896   1.1   thorpej void
   1897   1.1   thorpej wm_reset(struct wm_softc *sc)
   1898   1.1   thorpej {
   1899   1.1   thorpej 	int i;
   1900   1.1   thorpej 
   1901   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
   1902   1.1   thorpej 	delay(10000);
   1903   1.1   thorpej 
   1904   1.1   thorpej 	for (i = 0; i < 1000; i++) {
   1905   1.1   thorpej 		if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0)
   1906   1.1   thorpej 			return;
   1907   1.1   thorpej 		delay(20);
   1908   1.1   thorpej 	}
   1909   1.1   thorpej 
   1910   1.1   thorpej 	if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
   1911   1.1   thorpej 		printf("%s: WARNING: reset failed to complete\n",
   1912   1.1   thorpej 		    sc->sc_dev.dv_xname);
   1913   1.1   thorpej }
   1914   1.1   thorpej 
   1915   1.1   thorpej /*
   1916   1.1   thorpej  * wm_init:		[ifnet interface function]
   1917   1.1   thorpej  *
   1918   1.1   thorpej  *	Initialize the interface.  Must be called at splnet().
   1919   1.1   thorpej  */
   1920   1.1   thorpej int
   1921   1.1   thorpej wm_init(struct ifnet *ifp)
   1922   1.1   thorpej {
   1923   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   1924   1.1   thorpej 	struct wm_rxsoft *rxs;
   1925   1.1   thorpej 	int i, error = 0;
   1926   1.1   thorpej 	uint32_t reg;
   1927   1.1   thorpej 
   1928   1.1   thorpej 	/* Cancel any pending I/O. */
   1929   1.1   thorpej 	wm_stop(ifp, 0);
   1930   1.1   thorpej 
   1931   1.1   thorpej 	/* Reset the chip to a known state. */
   1932   1.1   thorpej 	wm_reset(sc);
   1933   1.1   thorpej 
   1934   1.1   thorpej 	/* Initialize the transmit descriptor ring. */
   1935   1.1   thorpej 	memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
   1936   1.1   thorpej 	WM_CDTXSYNC(sc, 0, WM_NTXDESC,
   1937   1.1   thorpej 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1938   1.1   thorpej 	sc->sc_txfree = WM_NTXDESC;
   1939   1.1   thorpej 	sc->sc_txnext = 0;
   1940   1.5   thorpej 
   1941   1.5   thorpej 	sc->sc_txctx_ipcs = 0xffffffff;
   1942   1.5   thorpej 	sc->sc_txctx_tucs = 0xffffffff;
   1943   1.1   thorpej 
   1944  1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
   1945   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_TBDAH, 0);
   1946   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR(sc, 0));
   1947   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_TDLEN, sizeof(sc->sc_txdescs));
   1948   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
   1949   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
   1950  1.10   thorpej 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
   1951   1.1   thorpej 	} else {
   1952   1.1   thorpej 		CSR_WRITE(sc, WMREG_TBDAH, 0);
   1953   1.1   thorpej 		CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR(sc, 0));
   1954   1.1   thorpej 		CSR_WRITE(sc, WMREG_TDLEN, sizeof(sc->sc_txdescs));
   1955   1.1   thorpej 		CSR_WRITE(sc, WMREG_TDH, 0);
   1956   1.1   thorpej 		CSR_WRITE(sc, WMREG_TDT, 0);
   1957  1.10   thorpej 		CSR_WRITE(sc, WMREG_TIDV, 128);
   1958   1.1   thorpej 
   1959   1.1   thorpej 		CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
   1960   1.1   thorpej 		    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
   1961   1.1   thorpej 		CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
   1962   1.1   thorpej 		    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
   1963   1.1   thorpej 	}
   1964   1.1   thorpej 	CSR_WRITE(sc, WMREG_TQSA_LO, 0);
   1965   1.1   thorpej 	CSR_WRITE(sc, WMREG_TQSA_HI, 0);
   1966   1.1   thorpej 
   1967   1.1   thorpej 	/* Initialize the transmit job descriptors. */
   1968   1.1   thorpej 	for (i = 0; i < WM_TXQUEUELEN; i++)
   1969   1.1   thorpej 		sc->sc_txsoft[i].txs_mbuf = NULL;
   1970   1.1   thorpej 	sc->sc_txsfree = WM_TXQUEUELEN;
   1971   1.1   thorpej 	sc->sc_txsnext = 0;
   1972   1.1   thorpej 	sc->sc_txsdirty = 0;
   1973   1.1   thorpej 
   1974   1.1   thorpej 	/*
   1975   1.1   thorpej 	 * Initialize the receive descriptor and receive job
   1976   1.1   thorpej 	 * descriptor rings.
   1977   1.1   thorpej 	 */
   1978  1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
   1979   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, 0);
   1980   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR(sc, 0));
   1981   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs));
   1982   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
   1983   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
   1984  1.10   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
   1985   1.1   thorpej 
   1986   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
   1987   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
   1988   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
   1989   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
   1990   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
   1991   1.1   thorpej 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
   1992   1.1   thorpej 	} else {
   1993   1.1   thorpej 		CSR_WRITE(sc, WMREG_RDBAH, 0);
   1994   1.1   thorpej 		CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR(sc, 0));
   1995   1.1   thorpej 		CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs));
   1996   1.1   thorpej 		CSR_WRITE(sc, WMREG_RDH, 0);
   1997   1.1   thorpej 		CSR_WRITE(sc, WMREG_RDT, 0);
   1998  1.10   thorpej 		CSR_WRITE(sc, WMREG_RDTR, 28 | RDTR_FPD);
   1999   1.1   thorpej 	}
   2000   1.1   thorpej 	for (i = 0; i < WM_NRXDESC; i++) {
   2001   1.1   thorpej 		rxs = &sc->sc_rxsoft[i];
   2002   1.1   thorpej 		if (rxs->rxs_mbuf == NULL) {
   2003   1.1   thorpej 			if ((error = wm_add_rxbuf(sc, i)) != 0) {
   2004   1.1   thorpej 				printf("%s: unable to allocate or map rx "
   2005   1.1   thorpej 				    "buffer %d, error = %d\n",
   2006   1.1   thorpej 				    sc->sc_dev.dv_xname, i, error);
   2007   1.1   thorpej 				/*
   2008   1.1   thorpej 				 * XXX Should attempt to run with fewer receive
   2009   1.1   thorpej 				 * XXX buffers instead of just failing.
   2010   1.1   thorpej 				 */
   2011   1.1   thorpej 				wm_rxdrain(sc);
   2012   1.1   thorpej 				goto out;
   2013   1.1   thorpej 			}
   2014   1.1   thorpej 		} else
   2015   1.1   thorpej 			WM_INIT_RXDESC(sc, i);
   2016   1.1   thorpej 	}
   2017   1.1   thorpej 	sc->sc_rxptr = 0;
   2018   1.1   thorpej 	sc->sc_rxdiscard = 0;
   2019   1.1   thorpej 	WM_RXCHAIN_RESET(sc);
   2020   1.1   thorpej 
   2021   1.1   thorpej 	/*
   2022   1.1   thorpej 	 * Clear out the VLAN table -- we don't use it (yet).
   2023   1.1   thorpej 	 */
   2024   1.1   thorpej 	CSR_WRITE(sc, WMREG_VET, 0);
   2025   1.1   thorpej 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
   2026   1.1   thorpej 		CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
   2027   1.1   thorpej 
   2028   1.1   thorpej 	/*
   2029   1.1   thorpej 	 * Set up flow-control parameters.
   2030   1.1   thorpej 	 *
   2031   1.1   thorpej 	 * XXX Values could probably stand some tuning.
   2032   1.1   thorpej 	 */
   2033   1.1   thorpej 	if (sc->sc_ctrl & (CTRL_RFCE|CTRL_TFCE)) {
   2034   1.1   thorpej 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
   2035   1.1   thorpej 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
   2036   1.1   thorpej 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
   2037   1.1   thorpej 
   2038  1.11   thorpej 		if (sc->sc_type < WM_T_82543) {
   2039   1.1   thorpej 			CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
   2040   1.1   thorpej 			CSR_WRITE(sc, WMREG_OLD_FCRTL, FCRTL_DFLT);
   2041   1.1   thorpej 		} else {
   2042   1.1   thorpej 			CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
   2043   1.1   thorpej 			CSR_WRITE(sc, WMREG_FCRTL, FCRTL_DFLT);
   2044   1.1   thorpej 		}
   2045   1.1   thorpej 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
   2046   1.1   thorpej 	}
   2047   1.1   thorpej 
   2048   1.1   thorpej #if 0 /* XXXJRT */
   2049   1.1   thorpej 	/* Deal with VLAN enables. */
   2050   1.1   thorpej 	if (sc->sc_ethercom.ec_nvlans != 0)
   2051   1.1   thorpej 		sc->sc_ctrl |= CTRL_VME;
   2052   1.1   thorpej 	else
   2053   1.1   thorpej #endif /* XXXJRT */
   2054   1.1   thorpej 		sc->sc_ctrl &= ~CTRL_VME;
   2055   1.1   thorpej 
   2056   1.1   thorpej 	/* Write the control registers. */
   2057   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2058   1.1   thorpej #if 0
   2059   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   2060   1.1   thorpej #endif
   2061   1.1   thorpej 
   2062   1.1   thorpej 	/*
   2063   1.1   thorpej 	 * Set up checksum offload parameters.
   2064   1.1   thorpej 	 */
   2065   1.1   thorpej 	reg = CSR_READ(sc, WMREG_RXCSUM);
   2066   1.1   thorpej 	if (ifp->if_capenable & IFCAP_CSUM_IPv4)
   2067   1.1   thorpej 		reg |= RXCSUM_IPOFL;
   2068   1.1   thorpej 	else
   2069   1.1   thorpej 		reg &= ~RXCSUM_IPOFL;
   2070   1.1   thorpej 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4))
   2071  1.12   thorpej 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
   2072  1.12   thorpej 	else {
   2073   1.1   thorpej 		reg &= ~RXCSUM_TUOFL;
   2074  1.12   thorpej 		if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0)
   2075  1.12   thorpej 			reg &= ~RXCSUM_IPOFL;
   2076  1.12   thorpej 	}
   2077   1.1   thorpej 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
   2078   1.1   thorpej 
   2079   1.1   thorpej 	/*
   2080   1.1   thorpej 	 * Set up the interrupt registers.
   2081   1.1   thorpej 	 */
   2082   1.1   thorpej 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   2083  1.10   thorpej 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
   2084   1.1   thorpej 	    ICR_RXO | ICR_RXT0;
   2085   1.1   thorpej 	if ((sc->sc_flags & WM_F_HAS_MII) == 0)
   2086   1.1   thorpej 		sc->sc_icr |= ICR_RXCFG;
   2087   1.1   thorpej 	CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
   2088   1.1   thorpej 
   2089   1.1   thorpej 	/* Set up the inter-packet gap. */
   2090   1.1   thorpej 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   2091   1.1   thorpej 
   2092   1.1   thorpej #if 0 /* XXXJRT */
   2093   1.1   thorpej 	/* Set the VLAN ethernetype. */
   2094   1.1   thorpej 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
   2095   1.1   thorpej #endif
   2096   1.1   thorpej 
   2097   1.1   thorpej 	/*
   2098   1.1   thorpej 	 * Set up the transmit control register; we start out with
   2099   1.1   thorpej 	 * a collision distance suitable for FDX, but update it whe
   2100   1.1   thorpej 	 * we resolve the media type.
   2101   1.1   thorpej 	 */
   2102   1.1   thorpej 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
   2103   1.1   thorpej 	    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   2104   1.1   thorpej 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   2105   1.1   thorpej 
   2106   1.1   thorpej 	/* Set the media. */
   2107   1.1   thorpej 	(void) (*sc->sc_mii.mii_media.ifm_change)(ifp);
   2108   1.1   thorpej 
   2109   1.1   thorpej 	/*
   2110   1.1   thorpej 	 * Set up the receive control register; we actually program
   2111   1.1   thorpej 	 * the register when we set the receive filter.  Use multicast
   2112   1.1   thorpej 	 * address offset type 0.
   2113   1.1   thorpej 	 *
   2114  1.11   thorpej 	 * Only the i82544 has the ability to strip the incoming
   2115   1.1   thorpej 	 * CRC, so we don't enable that feature.
   2116   1.1   thorpej 	 */
   2117   1.1   thorpej 	sc->sc_mchash_type = 0;
   2118   1.1   thorpej 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_2k |
   2119   1.1   thorpej 	    RCTL_DPF | RCTL_MO(sc->sc_mchash_type);
   2120   1.1   thorpej 
   2121   1.1   thorpej 	/* Set the receive filter. */
   2122   1.1   thorpej 	wm_set_filter(sc);
   2123   1.1   thorpej 
   2124   1.1   thorpej 	/* Start the one second link check clock. */
   2125   1.1   thorpej 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   2126   1.1   thorpej 
   2127   1.1   thorpej 	/* ...all done! */
   2128   1.1   thorpej 	ifp->if_flags |= IFF_RUNNING;
   2129   1.1   thorpej 	ifp->if_flags &= ~IFF_OACTIVE;
   2130   1.1   thorpej 
   2131   1.1   thorpej  out:
   2132   1.1   thorpej 	if (error)
   2133   1.1   thorpej 		printf("%s: interface not running\n", sc->sc_dev.dv_xname);
   2134   1.1   thorpej 	return (error);
   2135   1.1   thorpej }
   2136   1.1   thorpej 
   2137   1.1   thorpej /*
   2138   1.1   thorpej  * wm_rxdrain:
   2139   1.1   thorpej  *
   2140   1.1   thorpej  *	Drain the receive queue.
   2141   1.1   thorpej  */
   2142   1.1   thorpej void
   2143   1.1   thorpej wm_rxdrain(struct wm_softc *sc)
   2144   1.1   thorpej {
   2145   1.1   thorpej 	struct wm_rxsoft *rxs;
   2146   1.1   thorpej 	int i;
   2147   1.1   thorpej 
   2148   1.1   thorpej 	for (i = 0; i < WM_NRXDESC; i++) {
   2149   1.1   thorpej 		rxs = &sc->sc_rxsoft[i];
   2150   1.1   thorpej 		if (rxs->rxs_mbuf != NULL) {
   2151   1.1   thorpej 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   2152   1.1   thorpej 			m_freem(rxs->rxs_mbuf);
   2153   1.1   thorpej 			rxs->rxs_mbuf = NULL;
   2154   1.1   thorpej 		}
   2155   1.1   thorpej 	}
   2156   1.1   thorpej }
   2157   1.1   thorpej 
   2158   1.1   thorpej /*
   2159   1.1   thorpej  * wm_stop:		[ifnet interface function]
   2160   1.1   thorpej  *
   2161   1.1   thorpej  *	Stop transmission on the interface.
   2162   1.1   thorpej  */
   2163   1.1   thorpej void
   2164   1.1   thorpej wm_stop(struct ifnet *ifp, int disable)
   2165   1.1   thorpej {
   2166   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   2167   1.1   thorpej 	struct wm_txsoft *txs;
   2168   1.1   thorpej 	int i;
   2169   1.1   thorpej 
   2170   1.1   thorpej 	/* Stop the one second clock. */
   2171   1.1   thorpej 	callout_stop(&sc->sc_tick_ch);
   2172   1.1   thorpej 
   2173   1.1   thorpej 	if (sc->sc_flags & WM_F_HAS_MII) {
   2174   1.1   thorpej 		/* Down the MII. */
   2175   1.1   thorpej 		mii_down(&sc->sc_mii);
   2176   1.1   thorpej 	}
   2177   1.1   thorpej 
   2178   1.1   thorpej 	/* Stop the transmit and receive processes. */
   2179   1.1   thorpej 	CSR_WRITE(sc, WMREG_TCTL, 0);
   2180   1.1   thorpej 	CSR_WRITE(sc, WMREG_RCTL, 0);
   2181   1.1   thorpej 
   2182   1.1   thorpej 	/* Release any queued transmit buffers. */
   2183   1.1   thorpej 	for (i = 0; i < WM_TXQUEUELEN; i++) {
   2184   1.1   thorpej 		txs = &sc->sc_txsoft[i];
   2185   1.1   thorpej 		if (txs->txs_mbuf != NULL) {
   2186   1.1   thorpej 			bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   2187   1.1   thorpej 			m_freem(txs->txs_mbuf);
   2188   1.1   thorpej 			txs->txs_mbuf = NULL;
   2189   1.1   thorpej 		}
   2190   1.1   thorpej 	}
   2191   1.1   thorpej 
   2192   1.1   thorpej 	if (disable)
   2193   1.1   thorpej 		wm_rxdrain(sc);
   2194   1.1   thorpej 
   2195   1.1   thorpej 	/* Mark the interface as down and cancel the watchdog timer. */
   2196   1.1   thorpej 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   2197   1.1   thorpej 	ifp->if_timer = 0;
   2198   1.1   thorpej }
   2199   1.1   thorpej 
   2200   1.1   thorpej /*
   2201   1.1   thorpej  * wm_read_eeprom:
   2202   1.1   thorpej  *
   2203   1.1   thorpej  *	Read data from the serial EEPROM.
   2204   1.1   thorpej  */
   2205   1.1   thorpej void
   2206   1.1   thorpej wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   2207   1.1   thorpej {
   2208   1.1   thorpej 	uint32_t reg;
   2209  1.17   thorpej 	int i, x, addrbits = 6;
   2210   1.1   thorpej 
   2211   1.1   thorpej 	for (i = 0; i < wordcnt; i++) {
   2212  1.17   thorpej 		if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) {
   2213  1.17   thorpej 			reg = CSR_READ(sc, WMREG_EECD);
   2214  1.17   thorpej 
   2215  1.17   thorpej 			/* Get number of address bits. */
   2216  1.17   thorpej 			if (reg & EECD_EE_SIZE)
   2217  1.17   thorpej 				addrbits = 8;
   2218  1.17   thorpej 
   2219  1.17   thorpej 			/* Request EEPROM access. */
   2220  1.17   thorpej 			reg |= EECD_EE_REQ;
   2221  1.17   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg);
   2222  1.17   thorpej 
   2223  1.17   thorpej 			/* ..and wait for it to be granted. */
   2224  1.17   thorpej 			for (x = 0; x < 100; x++) {
   2225  1.17   thorpej 				reg = CSR_READ(sc, WMREG_EECD);
   2226  1.17   thorpej 				if (reg & EECD_EE_GNT)
   2227  1.17   thorpej 					break;
   2228  1.17   thorpej 				delay(5);
   2229  1.17   thorpej 			}
   2230  1.17   thorpej 			if ((reg & EECD_EE_GNT) == 0) {
   2231  1.17   thorpej 				printf("%s: could not acquire EEPROM GNT\n",
   2232  1.17   thorpej 				    sc->sc_dev.dv_xname);
   2233  1.17   thorpej 				*data = 0xffff;
   2234  1.17   thorpej 				reg &= ~EECD_EE_REQ;
   2235  1.17   thorpej 				CSR_WRITE(sc, WMREG_EECD, reg);
   2236  1.17   thorpej 				continue;
   2237  1.17   thorpej 			}
   2238  1.17   thorpej 		} else
   2239  1.17   thorpej 			reg = 0;
   2240  1.17   thorpej 
   2241  1.17   thorpej 		/* Clear SK and DI. */
   2242  1.17   thorpej 		reg &= ~(EECD_SK | EECD_DI);
   2243  1.17   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   2244  1.17   thorpej 
   2245  1.17   thorpej 		/* Set CHIP SELECT. */
   2246  1.17   thorpej 		reg |= EECD_CS;
   2247  1.17   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   2248   1.1   thorpej 		delay(2);
   2249   1.1   thorpej 
   2250   1.1   thorpej 		/* Shift in the READ command. */
   2251   1.1   thorpej 		for (x = 3; x > 0; x--) {
   2252   1.1   thorpej 			if (UWIRE_OPC_READ & (1 << (x - 1)))
   2253   1.1   thorpej 				reg |= EECD_DI;
   2254  1.17   thorpej 			else
   2255  1.17   thorpej 				reg &= ~EECD_DI;
   2256   1.1   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg);
   2257   1.1   thorpej 			delay(2);
   2258   1.1   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   2259   1.1   thorpej 			delay(2);
   2260   1.1   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg);
   2261   1.1   thorpej 			delay(2);
   2262   1.1   thorpej 		}
   2263   1.1   thorpej 
   2264   1.1   thorpej 		/* Shift in address. */
   2265  1.17   thorpej 		for (x = addrbits; x > 0; x--) {
   2266   1.1   thorpej 			if ((word + i) & (1 << (x - 1)))
   2267   1.1   thorpej 				reg |= EECD_DI;
   2268  1.17   thorpej 			else
   2269  1.17   thorpej 				reg &= ~EECD_DI;
   2270   1.1   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg);
   2271   1.1   thorpej 			delay(2);
   2272   1.1   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   2273   1.1   thorpej 			delay(2);
   2274   1.1   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg);
   2275   1.1   thorpej 			delay(2);
   2276   1.1   thorpej 		}
   2277   1.1   thorpej 
   2278   1.1   thorpej 		/* Shift out the data. */
   2279  1.17   thorpej 		reg &= ~EECD_DI;
   2280   1.1   thorpej 		data[i] = 0;
   2281   1.1   thorpej 		for (x = 16; x > 0; x--) {
   2282   1.1   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   2283   1.1   thorpej 			delay(2);
   2284   1.1   thorpej 			if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
   2285   1.1   thorpej 				data[i] |= (1 << (x - 1));
   2286   1.1   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg);
   2287   1.1   thorpej 			delay(2);
   2288   1.1   thorpej 		}
   2289   1.1   thorpej 
   2290   1.1   thorpej 		/* Clear CHIP SELECT. */
   2291  1.17   thorpej 		reg &= ~EECD_CS;
   2292  1.17   thorpej 		CSR_WRITE(sc, WMREG_EECD, reg);
   2293  1.17   thorpej 		delay(2);
   2294  1.17   thorpej 
   2295  1.17   thorpej 		if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) {
   2296  1.17   thorpej 			/* Release the EEPROM. */
   2297  1.17   thorpej 			reg &= ~EECD_EE_REQ;
   2298  1.17   thorpej 			CSR_WRITE(sc, WMREG_EECD, reg);
   2299  1.17   thorpej 		}
   2300   1.1   thorpej 	}
   2301   1.1   thorpej }
   2302   1.1   thorpej 
   2303   1.1   thorpej /*
   2304   1.1   thorpej  * wm_add_rxbuf:
   2305   1.1   thorpej  *
   2306   1.1   thorpej  *	Add a receive buffer to the indiciated descriptor.
   2307   1.1   thorpej  */
   2308   1.1   thorpej int
   2309   1.1   thorpej wm_add_rxbuf(struct wm_softc *sc, int idx)
   2310   1.1   thorpej {
   2311   1.1   thorpej 	struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx];
   2312   1.1   thorpej 	struct mbuf *m;
   2313   1.1   thorpej 	int error;
   2314   1.1   thorpej 
   2315   1.1   thorpej 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   2316   1.1   thorpej 	if (m == NULL)
   2317   1.1   thorpej 		return (ENOBUFS);
   2318   1.1   thorpej 
   2319   1.1   thorpej 	MCLGET(m, M_DONTWAIT);
   2320   1.1   thorpej 	if ((m->m_flags & M_EXT) == 0) {
   2321   1.1   thorpej 		m_freem(m);
   2322   1.1   thorpej 		return (ENOBUFS);
   2323   1.1   thorpej 	}
   2324   1.1   thorpej 
   2325   1.1   thorpej 	if (rxs->rxs_mbuf != NULL)
   2326   1.1   thorpej 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   2327   1.1   thorpej 
   2328   1.1   thorpej 	rxs->rxs_mbuf = m;
   2329   1.1   thorpej 
   2330  1.32   thorpej 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
   2331  1.32   thorpej 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
   2332   1.1   thorpej 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
   2333   1.1   thorpej 	if (error) {
   2334   1.1   thorpej 		printf("%s: unable to load rx DMA map %d, error = %d\n",
   2335   1.1   thorpej 		    sc->sc_dev.dv_xname, idx, error);
   2336   1.1   thorpej 		panic("wm_add_rxbuf");	/* XXX XXX XXX */
   2337   1.1   thorpej 	}
   2338   1.1   thorpej 
   2339   1.1   thorpej 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   2340   1.1   thorpej 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   2341   1.1   thorpej 
   2342   1.1   thorpej 	WM_INIT_RXDESC(sc, idx);
   2343   1.1   thorpej 
   2344   1.1   thorpej 	return (0);
   2345   1.1   thorpej }
   2346   1.1   thorpej 
   2347   1.1   thorpej /*
   2348   1.1   thorpej  * wm_set_ral:
   2349   1.1   thorpej  *
   2350   1.1   thorpej  *	Set an entery in the receive address list.
   2351   1.1   thorpej  */
   2352   1.1   thorpej static void
   2353   1.1   thorpej wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
   2354   1.1   thorpej {
   2355   1.1   thorpej 	uint32_t ral_lo, ral_hi;
   2356   1.1   thorpej 
   2357   1.1   thorpej 	if (enaddr != NULL) {
   2358   1.1   thorpej 		ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
   2359   1.1   thorpej 		    (enaddr[3] << 24);
   2360   1.1   thorpej 		ral_hi = enaddr[4] | (enaddr[5] << 8);
   2361   1.1   thorpej 		ral_hi |= RAL_AV;
   2362   1.1   thorpej 	} else {
   2363   1.1   thorpej 		ral_lo = 0;
   2364   1.1   thorpej 		ral_hi = 0;
   2365   1.1   thorpej 	}
   2366   1.1   thorpej 
   2367  1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2368   1.1   thorpej 		CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),
   2369   1.1   thorpej 		    ral_lo);
   2370   1.1   thorpej 		CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),
   2371   1.1   thorpej 		    ral_hi);
   2372   1.1   thorpej 	} else {
   2373   1.1   thorpej 		CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo);
   2374   1.1   thorpej 		CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi);
   2375   1.1   thorpej 	}
   2376   1.1   thorpej }
   2377   1.1   thorpej 
   2378   1.1   thorpej /*
   2379   1.1   thorpej  * wm_mchash:
   2380   1.1   thorpej  *
   2381   1.1   thorpej  *	Compute the hash of the multicast address for the 4096-bit
   2382   1.1   thorpej  *	multicast filter.
   2383   1.1   thorpej  */
   2384   1.1   thorpej static uint32_t
   2385   1.1   thorpej wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
   2386   1.1   thorpej {
   2387   1.1   thorpej 	static const int lo_shift[4] = { 4, 3, 2, 0 };
   2388   1.1   thorpej 	static const int hi_shift[4] = { 4, 5, 6, 8 };
   2389   1.1   thorpej 	uint32_t hash;
   2390   1.1   thorpej 
   2391   1.1   thorpej 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
   2392   1.1   thorpej 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
   2393   1.1   thorpej 
   2394   1.1   thorpej 	return (hash & 0xfff);
   2395   1.1   thorpej }
   2396   1.1   thorpej 
   2397   1.1   thorpej /*
   2398   1.1   thorpej  * wm_set_filter:
   2399   1.1   thorpej  *
   2400   1.1   thorpej  *	Set up the receive filter.
   2401   1.1   thorpej  */
   2402   1.1   thorpej void
   2403   1.1   thorpej wm_set_filter(struct wm_softc *sc)
   2404   1.1   thorpej {
   2405   1.1   thorpej 	struct ethercom *ec = &sc->sc_ethercom;
   2406   1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2407   1.1   thorpej 	struct ether_multi *enm;
   2408   1.1   thorpej 	struct ether_multistep step;
   2409   1.1   thorpej 	bus_addr_t mta_reg;
   2410   1.1   thorpej 	uint32_t hash, reg, bit;
   2411   1.1   thorpej 	int i;
   2412   1.1   thorpej 
   2413  1.11   thorpej 	if (sc->sc_type >= WM_T_82544)
   2414   1.1   thorpej 		mta_reg = WMREG_CORDOVA_MTA;
   2415   1.1   thorpej 	else
   2416   1.1   thorpej 		mta_reg = WMREG_MTA;
   2417   1.1   thorpej 
   2418   1.1   thorpej 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
   2419   1.1   thorpej 
   2420   1.1   thorpej 	if (ifp->if_flags & IFF_BROADCAST)
   2421   1.1   thorpej 		sc->sc_rctl |= RCTL_BAM;
   2422   1.1   thorpej 	if (ifp->if_flags & IFF_PROMISC) {
   2423   1.1   thorpej 		sc->sc_rctl |= RCTL_UPE;
   2424   1.1   thorpej 		goto allmulti;
   2425   1.1   thorpej 	}
   2426   1.1   thorpej 
   2427   1.1   thorpej 	/*
   2428   1.1   thorpej 	 * Set the station address in the first RAL slot, and
   2429   1.1   thorpej 	 * clear the remaining slots.
   2430   1.1   thorpej 	 */
   2431   1.1   thorpej 	wm_set_ral(sc, LLADDR(ifp->if_sadl), 0);
   2432   1.1   thorpej 	for (i = 1; i < WM_RAL_TABSIZE; i++)
   2433   1.1   thorpej 		wm_set_ral(sc, NULL, i);
   2434   1.1   thorpej 
   2435   1.1   thorpej 	/* Clear out the multicast table. */
   2436   1.1   thorpej 	for (i = 0; i < WM_MC_TABSIZE; i++)
   2437   1.1   thorpej 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
   2438   1.1   thorpej 
   2439   1.1   thorpej 	ETHER_FIRST_MULTI(step, ec, enm);
   2440   1.1   thorpej 	while (enm != NULL) {
   2441   1.1   thorpej 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   2442   1.1   thorpej 			/*
   2443   1.1   thorpej 			 * We must listen to a range of multicast addresses.
   2444   1.1   thorpej 			 * For now, just accept all multicasts, rather than
   2445   1.1   thorpej 			 * trying to set only those filter bits needed to match
   2446   1.1   thorpej 			 * the range.  (At this time, the only use of address
   2447   1.1   thorpej 			 * ranges is for IP multicast routing, for which the
   2448   1.1   thorpej 			 * range is big enough to require all bits set.)
   2449   1.1   thorpej 			 */
   2450   1.1   thorpej 			goto allmulti;
   2451   1.1   thorpej 		}
   2452   1.1   thorpej 
   2453   1.1   thorpej 		hash = wm_mchash(sc, enm->enm_addrlo);
   2454   1.1   thorpej 
   2455   1.1   thorpej 		reg = (hash >> 5) & 0x7f;
   2456   1.1   thorpej 		bit = hash & 0x1f;
   2457   1.1   thorpej 
   2458   1.1   thorpej 		hash = CSR_READ(sc, mta_reg + (reg << 2));
   2459   1.1   thorpej 		hash |= 1U << bit;
   2460   1.1   thorpej 
   2461   1.1   thorpej 		/* XXX Hardware bug?? */
   2462  1.11   thorpej 		if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
   2463   1.1   thorpej 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
   2464   1.1   thorpej 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   2465   1.1   thorpej 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
   2466   1.1   thorpej 		} else
   2467   1.1   thorpej 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   2468   1.1   thorpej 
   2469   1.1   thorpej 		ETHER_NEXT_MULTI(step, enm);
   2470   1.1   thorpej 	}
   2471   1.1   thorpej 
   2472   1.1   thorpej 	ifp->if_flags &= ~IFF_ALLMULTI;
   2473   1.1   thorpej 	goto setit;
   2474   1.1   thorpej 
   2475   1.1   thorpej  allmulti:
   2476   1.1   thorpej 	ifp->if_flags |= IFF_ALLMULTI;
   2477   1.1   thorpej 	sc->sc_rctl |= RCTL_MPE;
   2478   1.1   thorpej 
   2479   1.1   thorpej  setit:
   2480   1.1   thorpej 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
   2481   1.1   thorpej }
   2482   1.1   thorpej 
   2483   1.1   thorpej /*
   2484   1.1   thorpej  * wm_tbi_mediainit:
   2485   1.1   thorpej  *
   2486   1.1   thorpej  *	Initialize media for use on 1000BASE-X devices.
   2487   1.1   thorpej  */
   2488   1.1   thorpej void
   2489   1.1   thorpej wm_tbi_mediainit(struct wm_softc *sc)
   2490   1.1   thorpej {
   2491   1.1   thorpej 	const char *sep = "";
   2492   1.1   thorpej 
   2493  1.11   thorpej 	if (sc->sc_type < WM_T_82543)
   2494   1.1   thorpej 		sc->sc_tipg = TIPG_WM_DFLT;
   2495   1.1   thorpej 	else
   2496   1.1   thorpej 		sc->sc_tipg = TIPG_LG_DFLT;
   2497   1.1   thorpej 
   2498  1.26      fair 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange,
   2499   1.1   thorpej 	    wm_tbi_mediastatus);
   2500   1.1   thorpej 
   2501   1.1   thorpej 	/*
   2502   1.1   thorpej 	 * SWD Pins:
   2503   1.1   thorpej 	 *
   2504   1.1   thorpej 	 *	0 = Link LED (output)
   2505   1.1   thorpej 	 *	1 = Loss Of Signal (input)
   2506   1.1   thorpej 	 */
   2507   1.1   thorpej 	sc->sc_ctrl |= CTRL_SWDPIO(0);
   2508   1.1   thorpej 	sc->sc_ctrl &= ~CTRL_SWDPIO(1);
   2509   1.1   thorpej 
   2510   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2511   1.1   thorpej 
   2512  1.27  christos #define	ADD(ss, mm, dd)							\
   2513   1.1   thorpej do {									\
   2514  1.27  christos 	printf("%s%s", sep, ss);					\
   2515  1.27  christos 	ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL);	\
   2516   1.1   thorpej 	sep = ", ";							\
   2517   1.1   thorpej } while (/*CONSTCOND*/0)
   2518   1.1   thorpej 
   2519   1.1   thorpej 	printf("%s: ", sc->sc_dev.dv_xname);
   2520   1.1   thorpej 	ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
   2521   1.1   thorpej 	ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD);
   2522   1.1   thorpej 	ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD);
   2523   1.1   thorpej 	printf("\n");
   2524   1.1   thorpej 
   2525   1.1   thorpej #undef ADD
   2526   1.1   thorpej 
   2527   1.1   thorpej 	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
   2528   1.1   thorpej }
   2529   1.1   thorpej 
   2530   1.1   thorpej /*
   2531   1.1   thorpej  * wm_tbi_mediastatus:	[ifmedia interface function]
   2532   1.1   thorpej  *
   2533   1.1   thorpej  *	Get the current interface media status on a 1000BASE-X device.
   2534   1.1   thorpej  */
   2535   1.1   thorpej void
   2536   1.1   thorpej wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   2537   1.1   thorpej {
   2538   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   2539   1.1   thorpej 
   2540   1.1   thorpej 	ifmr->ifm_status = IFM_AVALID;
   2541   1.1   thorpej 	ifmr->ifm_active = IFM_ETHER;
   2542   1.1   thorpej 
   2543   1.1   thorpej 	if (sc->sc_tbi_linkup == 0) {
   2544   1.1   thorpej 		ifmr->ifm_active |= IFM_NONE;
   2545   1.1   thorpej 		return;
   2546   1.1   thorpej 	}
   2547   1.1   thorpej 
   2548   1.1   thorpej 	ifmr->ifm_status |= IFM_ACTIVE;
   2549   1.1   thorpej 	ifmr->ifm_active |= IFM_1000_SX;
   2550   1.1   thorpej 	if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
   2551   1.1   thorpej 		ifmr->ifm_active |= IFM_FDX;
   2552   1.1   thorpej }
   2553   1.1   thorpej 
   2554   1.1   thorpej /*
   2555   1.1   thorpej  * wm_tbi_mediachange:	[ifmedia interface function]
   2556   1.1   thorpej  *
   2557   1.1   thorpej  *	Set hardware to newly-selected media on a 1000BASE-X device.
   2558   1.1   thorpej  */
   2559   1.1   thorpej int
   2560   1.1   thorpej wm_tbi_mediachange(struct ifnet *ifp)
   2561   1.1   thorpej {
   2562   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   2563   1.1   thorpej 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   2564   1.1   thorpej 	uint32_t status;
   2565   1.1   thorpej 	int i;
   2566   1.1   thorpej 
   2567   1.1   thorpej 	sc->sc_txcw = ife->ifm_data;
   2568   1.1   thorpej 	if (sc->sc_ctrl & CTRL_RFCE)
   2569   1.1   thorpej 		sc->sc_txcw |= ANAR_X_PAUSE_TOWARDS;
   2570   1.1   thorpej 	if (sc->sc_ctrl & CTRL_TFCE)
   2571   1.1   thorpej 		sc->sc_txcw |= ANAR_X_PAUSE_ASYM;
   2572   1.1   thorpej 	sc->sc_txcw |= TXCW_ANE;
   2573   1.1   thorpej 
   2574   1.1   thorpej 	CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   2575   1.1   thorpej 	delay(10000);
   2576   1.1   thorpej 
   2577   1.1   thorpej 	sc->sc_tbi_anstate = 0;
   2578   1.1   thorpej 
   2579   1.1   thorpej 	if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) {
   2580   1.1   thorpej 		/* Have signal; wait for the link to come up. */
   2581   1.1   thorpej 		for (i = 0; i < 50; i++) {
   2582   1.1   thorpej 			delay(10000);
   2583   1.1   thorpej 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
   2584   1.1   thorpej 				break;
   2585   1.1   thorpej 		}
   2586   1.1   thorpej 
   2587   1.1   thorpej 		status = CSR_READ(sc, WMREG_STATUS);
   2588   1.1   thorpej 		if (status & STATUS_LU) {
   2589   1.1   thorpej 			/* Link is up. */
   2590   1.1   thorpej 			DPRINTF(WM_DEBUG_LINK,
   2591   1.1   thorpej 			    ("%s: LINK: set media -> link up %s\n",
   2592   1.1   thorpej 			    sc->sc_dev.dv_xname,
   2593   1.1   thorpej 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   2594   1.1   thorpej 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   2595   1.1   thorpej 			if (status & STATUS_FD)
   2596   1.1   thorpej 				sc->sc_tctl |=
   2597   1.1   thorpej 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   2598   1.1   thorpej 			else
   2599   1.1   thorpej 				sc->sc_tctl |=
   2600   1.1   thorpej 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   2601   1.1   thorpej 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   2602   1.1   thorpej 			sc->sc_tbi_linkup = 1;
   2603   1.1   thorpej 		} else {
   2604   1.1   thorpej 			/* Link is down. */
   2605   1.1   thorpej 			DPRINTF(WM_DEBUG_LINK,
   2606   1.1   thorpej 			    ("%s: LINK: set media -> link down\n",
   2607   1.1   thorpej 			    sc->sc_dev.dv_xname));
   2608   1.1   thorpej 			sc->sc_tbi_linkup = 0;
   2609   1.1   thorpej 		}
   2610   1.1   thorpej 	} else {
   2611   1.1   thorpej 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
   2612   1.1   thorpej 		    sc->sc_dev.dv_xname));
   2613   1.1   thorpej 		sc->sc_tbi_linkup = 0;
   2614   1.1   thorpej 	}
   2615   1.1   thorpej 
   2616   1.1   thorpej 	wm_tbi_set_linkled(sc);
   2617   1.1   thorpej 
   2618   1.1   thorpej 	return (0);
   2619   1.1   thorpej }
   2620   1.1   thorpej 
   2621   1.1   thorpej /*
   2622   1.1   thorpej  * wm_tbi_set_linkled:
   2623   1.1   thorpej  *
   2624   1.1   thorpej  *	Update the link LED on 1000BASE-X devices.
   2625   1.1   thorpej  */
   2626   1.1   thorpej void
   2627   1.1   thorpej wm_tbi_set_linkled(struct wm_softc *sc)
   2628   1.1   thorpej {
   2629   1.1   thorpej 
   2630   1.1   thorpej 	if (sc->sc_tbi_linkup)
   2631   1.1   thorpej 		sc->sc_ctrl |= CTRL_SWDPIN(0);
   2632   1.1   thorpej 	else
   2633   1.1   thorpej 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
   2634   1.1   thorpej 
   2635   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2636   1.1   thorpej }
   2637   1.1   thorpej 
   2638   1.1   thorpej /*
   2639   1.1   thorpej  * wm_tbi_check_link:
   2640   1.1   thorpej  *
   2641   1.1   thorpej  *	Check the link on 1000BASE-X devices.
   2642   1.1   thorpej  */
   2643   1.1   thorpej void
   2644   1.1   thorpej wm_tbi_check_link(struct wm_softc *sc)
   2645   1.1   thorpej {
   2646   1.1   thorpej 	uint32_t rxcw, ctrl, status;
   2647   1.1   thorpej 
   2648   1.1   thorpej 	if (sc->sc_tbi_anstate == 0)
   2649   1.1   thorpej 		return;
   2650   1.1   thorpej 	else if (sc->sc_tbi_anstate > 1) {
   2651   1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   2652   1.1   thorpej 		    ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname,
   2653   1.1   thorpej 		    sc->sc_tbi_anstate));
   2654   1.1   thorpej 		sc->sc_tbi_anstate--;
   2655   1.1   thorpej 		return;
   2656   1.1   thorpej 	}
   2657   1.1   thorpej 
   2658   1.1   thorpej 	sc->sc_tbi_anstate = 0;
   2659   1.1   thorpej 
   2660   1.1   thorpej 	rxcw = CSR_READ(sc, WMREG_RXCW);
   2661   1.1   thorpej 	ctrl = CSR_READ(sc, WMREG_CTRL);
   2662   1.1   thorpej 	status = CSR_READ(sc, WMREG_STATUS);
   2663   1.1   thorpej 
   2664   1.1   thorpej 	if ((status & STATUS_LU) == 0) {
   2665   1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   2666   1.1   thorpej 		    ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname));
   2667   1.1   thorpej 		sc->sc_tbi_linkup = 0;
   2668   1.1   thorpej 	} else {
   2669   1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   2670   1.1   thorpej 		    ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname,
   2671   1.1   thorpej 		    (status & STATUS_FD) ? "FDX" : "HDX"));
   2672   1.1   thorpej 		sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   2673   1.1   thorpej 		if (status & STATUS_FD)
   2674   1.1   thorpej 			sc->sc_tctl |=
   2675   1.1   thorpej 			    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   2676   1.1   thorpej 		else
   2677   1.1   thorpej 			sc->sc_tctl |=
   2678   1.1   thorpej 			    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   2679   1.1   thorpej 		CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   2680   1.1   thorpej 		sc->sc_tbi_linkup = 1;
   2681   1.1   thorpej 	}
   2682   1.1   thorpej 
   2683   1.1   thorpej 	wm_tbi_set_linkled(sc);
   2684   1.1   thorpej }
   2685   1.1   thorpej 
   2686   1.1   thorpej /*
   2687   1.1   thorpej  * wm_gmii_reset:
   2688   1.1   thorpej  *
   2689   1.1   thorpej  *	Reset the PHY.
   2690   1.1   thorpej  */
   2691   1.1   thorpej void
   2692   1.1   thorpej wm_gmii_reset(struct wm_softc *sc)
   2693   1.1   thorpej {
   2694   1.1   thorpej 	uint32_t reg;
   2695   1.1   thorpej 
   2696  1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2697   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   2698   1.1   thorpej 		delay(20000);
   2699   1.1   thorpej 
   2700   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2701   1.1   thorpej 		delay(20000);
   2702   1.1   thorpej 	} else {
   2703   1.1   thorpej 		/* The PHY reset pin is active-low. */
   2704   1.1   thorpej 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   2705   1.1   thorpej 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
   2706   1.1   thorpej 		    CTRL_EXT_SWDPIN(4));
   2707   1.1   thorpej 		reg |= CTRL_EXT_SWDPIO(4);
   2708   1.1   thorpej 
   2709   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   2710   1.1   thorpej 		delay(10);
   2711   1.1   thorpej 
   2712   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   2713   1.1   thorpej 		delay(10);
   2714   1.1   thorpej 
   2715   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   2716   1.1   thorpej 		delay(10);
   2717   1.1   thorpej #if 0
   2718   1.1   thorpej 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
   2719   1.1   thorpej #endif
   2720   1.1   thorpej 	}
   2721   1.1   thorpej }
   2722   1.1   thorpej 
   2723   1.1   thorpej /*
   2724   1.1   thorpej  * wm_gmii_mediainit:
   2725   1.1   thorpej  *
   2726   1.1   thorpej  *	Initialize media for use on 1000BASE-T devices.
   2727   1.1   thorpej  */
   2728   1.1   thorpej void
   2729   1.1   thorpej wm_gmii_mediainit(struct wm_softc *sc)
   2730   1.1   thorpej {
   2731   1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2732   1.1   thorpej 
   2733   1.1   thorpej 	/* We have MII. */
   2734   1.1   thorpej 	sc->sc_flags |= WM_F_HAS_MII;
   2735   1.1   thorpej 
   2736   1.1   thorpej 	sc->sc_tipg = TIPG_1000T_DFLT;
   2737   1.1   thorpej 
   2738   1.1   thorpej 	/*
   2739   1.1   thorpej 	 * Let the chip set speed/duplex on its own based on
   2740   1.1   thorpej 	 * signals from the PHY.
   2741   1.1   thorpej 	 */
   2742   1.1   thorpej 	sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE;
   2743   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2744   1.1   thorpej 
   2745   1.1   thorpej 	/* Initialize our media structures and probe the GMII. */
   2746   1.1   thorpej 	sc->sc_mii.mii_ifp = ifp;
   2747   1.1   thorpej 
   2748  1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2749  1.11   thorpej 		sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
   2750  1.11   thorpej 		sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
   2751   1.1   thorpej 	} else {
   2752  1.11   thorpej 		sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg;
   2753  1.11   thorpej 		sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg;
   2754   1.1   thorpej 	}
   2755   1.1   thorpej 	sc->sc_mii.mii_statchg = wm_gmii_statchg;
   2756   1.1   thorpej 
   2757   1.1   thorpej 	wm_gmii_reset(sc);
   2758   1.1   thorpej 
   2759  1.26      fair 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
   2760   1.1   thorpej 	    wm_gmii_mediastatus);
   2761   1.1   thorpej 
   2762   1.1   thorpej 	mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   2763   1.1   thorpej 	    MII_OFFSET_ANY, 0);
   2764   1.1   thorpej 	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
   2765   1.1   thorpej 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
   2766   1.1   thorpej 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
   2767   1.1   thorpej 	} else
   2768   1.1   thorpej 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
   2769   1.1   thorpej }
   2770   1.1   thorpej 
   2771   1.1   thorpej /*
   2772   1.1   thorpej  * wm_gmii_mediastatus:	[ifmedia interface function]
   2773   1.1   thorpej  *
   2774   1.1   thorpej  *	Get the current interface media status on a 1000BASE-T device.
   2775   1.1   thorpej  */
   2776   1.1   thorpej void
   2777   1.1   thorpej wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   2778   1.1   thorpej {
   2779   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   2780   1.1   thorpej 
   2781   1.1   thorpej 	mii_pollstat(&sc->sc_mii);
   2782   1.1   thorpej 	ifmr->ifm_status = sc->sc_mii.mii_media_status;
   2783   1.1   thorpej 	ifmr->ifm_active = sc->sc_mii.mii_media_active;
   2784   1.1   thorpej }
   2785   1.1   thorpej 
   2786   1.1   thorpej /*
   2787   1.1   thorpej  * wm_gmii_mediachange:	[ifmedia interface function]
   2788   1.1   thorpej  *
   2789   1.1   thorpej  *	Set hardware to newly-selected media on a 1000BASE-T device.
   2790   1.1   thorpej  */
   2791   1.1   thorpej int
   2792   1.1   thorpej wm_gmii_mediachange(struct ifnet *ifp)
   2793   1.1   thorpej {
   2794   1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   2795   1.1   thorpej 
   2796   1.1   thorpej 	if (ifp->if_flags & IFF_UP)
   2797   1.1   thorpej 		mii_mediachg(&sc->sc_mii);
   2798   1.1   thorpej 	return (0);
   2799   1.1   thorpej }
   2800   1.1   thorpej 
   2801   1.1   thorpej #define	MDI_IO		CTRL_SWDPIN(2)
   2802   1.1   thorpej #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
   2803   1.1   thorpej #define	MDI_CLK		CTRL_SWDPIN(3)
   2804   1.1   thorpej 
   2805   1.1   thorpej static void
   2806  1.11   thorpej i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
   2807   1.1   thorpej {
   2808   1.1   thorpej 	uint32_t i, v;
   2809   1.1   thorpej 
   2810   1.1   thorpej 	v = CSR_READ(sc, WMREG_CTRL);
   2811   1.1   thorpej 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   2812   1.1   thorpej 	v |= MDI_DIR | CTRL_SWDPIO(3);
   2813   1.1   thorpej 
   2814   1.1   thorpej 	for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
   2815   1.1   thorpej 		if (data & i)
   2816   1.1   thorpej 			v |= MDI_IO;
   2817   1.1   thorpej 		else
   2818   1.1   thorpej 			v &= ~MDI_IO;
   2819   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v);
   2820   1.1   thorpej 		delay(10);
   2821   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   2822   1.1   thorpej 		delay(10);
   2823   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v);
   2824   1.1   thorpej 		delay(10);
   2825   1.1   thorpej 	}
   2826   1.1   thorpej }
   2827   1.1   thorpej 
   2828   1.1   thorpej static uint32_t
   2829  1.11   thorpej i82543_mii_recvbits(struct wm_softc *sc)
   2830   1.1   thorpej {
   2831   1.1   thorpej 	uint32_t v, i, data = 0;
   2832   1.1   thorpej 
   2833   1.1   thorpej 	v = CSR_READ(sc, WMREG_CTRL);
   2834   1.1   thorpej 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   2835   1.1   thorpej 	v |= CTRL_SWDPIO(3);
   2836   1.1   thorpej 
   2837   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v);
   2838   1.1   thorpej 	delay(10);
   2839   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   2840   1.1   thorpej 	delay(10);
   2841   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v);
   2842   1.1   thorpej 	delay(10);
   2843   1.1   thorpej 
   2844   1.1   thorpej 	for (i = 0; i < 16; i++) {
   2845   1.1   thorpej 		data <<= 1;
   2846   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   2847   1.1   thorpej 		delay(10);
   2848   1.1   thorpej 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
   2849   1.1   thorpej 			data |= 1;
   2850   1.1   thorpej 		CSR_WRITE(sc, WMREG_CTRL, v);
   2851   1.1   thorpej 		delay(10);
   2852   1.1   thorpej 	}
   2853   1.1   thorpej 
   2854   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   2855   1.1   thorpej 	delay(10);
   2856   1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, v);
   2857   1.1   thorpej 	delay(10);
   2858   1.1   thorpej 
   2859   1.1   thorpej 	return (data);
   2860   1.1   thorpej }
   2861   1.1   thorpej 
   2862   1.1   thorpej #undef MDI_IO
   2863   1.1   thorpej #undef MDI_DIR
   2864   1.1   thorpej #undef MDI_CLK
   2865   1.1   thorpej 
   2866   1.1   thorpej /*
   2867  1.11   thorpej  * wm_gmii_i82543_readreg:	[mii interface function]
   2868   1.1   thorpej  *
   2869  1.11   thorpej  *	Read a PHY register on the GMII (i82543 version).
   2870   1.1   thorpej  */
   2871   1.1   thorpej int
   2872  1.11   thorpej wm_gmii_i82543_readreg(struct device *self, int phy, int reg)
   2873   1.1   thorpej {
   2874   1.1   thorpej 	struct wm_softc *sc = (void *) self;
   2875   1.1   thorpej 	int rv;
   2876   1.1   thorpej 
   2877  1.11   thorpej 	i82543_mii_sendbits(sc, 0xffffffffU, 32);
   2878  1.11   thorpej 	i82543_mii_sendbits(sc, reg | (phy << 5) |
   2879   1.1   thorpej 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
   2880  1.11   thorpej 	rv = i82543_mii_recvbits(sc) & 0xffff;
   2881   1.1   thorpej 
   2882   1.1   thorpej 	DPRINTF(WM_DEBUG_GMII,
   2883   1.1   thorpej 	    ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
   2884   1.1   thorpej 	    sc->sc_dev.dv_xname, phy, reg, rv));
   2885   1.1   thorpej 
   2886   1.1   thorpej 	return (rv);
   2887   1.1   thorpej }
   2888   1.1   thorpej 
   2889   1.1   thorpej /*
   2890  1.11   thorpej  * wm_gmii_i82543_writereg:	[mii interface function]
   2891   1.1   thorpej  *
   2892  1.11   thorpej  *	Write a PHY register on the GMII (i82543 version).
   2893   1.1   thorpej  */
   2894   1.1   thorpej void
   2895  1.11   thorpej wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val)
   2896   1.1   thorpej {
   2897   1.1   thorpej 	struct wm_softc *sc = (void *) self;
   2898   1.1   thorpej 
   2899  1.11   thorpej 	i82543_mii_sendbits(sc, 0xffffffffU, 32);
   2900  1.11   thorpej 	i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
   2901   1.1   thorpej 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
   2902   1.1   thorpej 	    (MII_COMMAND_START << 30), 32);
   2903   1.1   thorpej }
   2904   1.1   thorpej 
   2905   1.1   thorpej /*
   2906  1.11   thorpej  * wm_gmii_i82544_readreg:	[mii interface function]
   2907   1.1   thorpej  *
   2908   1.1   thorpej  *	Read a PHY register on the GMII.
   2909   1.1   thorpej  */
   2910   1.1   thorpej int
   2911  1.11   thorpej wm_gmii_i82544_readreg(struct device *self, int phy, int reg)
   2912   1.1   thorpej {
   2913   1.1   thorpej 	struct wm_softc *sc = (void *) self;
   2914   1.1   thorpej 	uint32_t mdic;
   2915   1.1   thorpej 	int i, rv;
   2916   1.1   thorpej 
   2917   1.1   thorpej 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
   2918   1.1   thorpej 	    MDIC_REGADD(reg));
   2919   1.1   thorpej 
   2920   1.1   thorpej 	for (i = 0; i < 100; i++) {
   2921   1.1   thorpej 		mdic = CSR_READ(sc, WMREG_MDIC);
   2922   1.1   thorpej 		if (mdic & MDIC_READY)
   2923   1.1   thorpej 			break;
   2924   1.1   thorpej 		delay(10);
   2925   1.1   thorpej 	}
   2926   1.1   thorpej 
   2927   1.1   thorpej 	if ((mdic & MDIC_READY) == 0) {
   2928   1.1   thorpej 		printf("%s: MDIC read timed out: phy %d reg %d\n",
   2929   1.1   thorpej 		    sc->sc_dev.dv_xname, phy, reg);
   2930   1.1   thorpej 		rv = 0;
   2931   1.1   thorpej 	} else if (mdic & MDIC_E) {
   2932   1.1   thorpej #if 0 /* This is normal if no PHY is present. */
   2933   1.1   thorpej 		printf("%s: MDIC read error: phy %d reg %d\n",
   2934   1.1   thorpej 		    sc->sc_dev.dv_xname, phy, reg);
   2935   1.1   thorpej #endif
   2936   1.1   thorpej 		rv = 0;
   2937   1.1   thorpej 	} else {
   2938   1.1   thorpej 		rv = MDIC_DATA(mdic);
   2939   1.1   thorpej 		if (rv == 0xffff)
   2940   1.1   thorpej 			rv = 0;
   2941   1.1   thorpej 	}
   2942   1.1   thorpej 
   2943   1.1   thorpej 	return (rv);
   2944   1.1   thorpej }
   2945   1.1   thorpej 
   2946   1.1   thorpej /*
   2947  1.11   thorpej  * wm_gmii_i82544_writereg:	[mii interface function]
   2948   1.1   thorpej  *
   2949   1.1   thorpej  *	Write a PHY register on the GMII.
   2950   1.1   thorpej  */
   2951   1.1   thorpej void
   2952  1.11   thorpej wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val)
   2953   1.1   thorpej {
   2954   1.1   thorpej 	struct wm_softc *sc = (void *) self;
   2955   1.1   thorpej 	uint32_t mdic;
   2956   1.1   thorpej 	int i;
   2957   1.1   thorpej 
   2958   1.1   thorpej 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
   2959   1.1   thorpej 	    MDIC_REGADD(reg) | MDIC_DATA(val));
   2960   1.1   thorpej 
   2961   1.1   thorpej 	for (i = 0; i < 100; i++) {
   2962   1.1   thorpej 		mdic = CSR_READ(sc, WMREG_MDIC);
   2963   1.1   thorpej 		if (mdic & MDIC_READY)
   2964   1.1   thorpej 			break;
   2965   1.1   thorpej 		delay(10);
   2966   1.1   thorpej 	}
   2967   1.1   thorpej 
   2968   1.1   thorpej 	if ((mdic & MDIC_READY) == 0)
   2969   1.1   thorpej 		printf("%s: MDIC write timed out: phy %d reg %d\n",
   2970   1.1   thorpej 		    sc->sc_dev.dv_xname, phy, reg);
   2971   1.1   thorpej 	else if (mdic & MDIC_E)
   2972   1.1   thorpej 		printf("%s: MDIC write error: phy %d reg %d\n",
   2973   1.1   thorpej 		    sc->sc_dev.dv_xname, phy, reg);
   2974   1.1   thorpej }
   2975   1.1   thorpej 
   2976   1.1   thorpej /*
   2977   1.1   thorpej  * wm_gmii_statchg:	[mii interface function]
   2978   1.1   thorpej  *
   2979   1.1   thorpej  *	Callback from MII layer when media changes.
   2980   1.1   thorpej  */
   2981   1.1   thorpej void
   2982   1.1   thorpej wm_gmii_statchg(struct device *self)
   2983   1.1   thorpej {
   2984   1.1   thorpej 	struct wm_softc *sc = (void *) self;
   2985   1.1   thorpej 
   2986   1.1   thorpej 	sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   2987   1.1   thorpej 
   2988   1.1   thorpej 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   2989   1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   2990   1.1   thorpej 		    ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname));
   2991   1.1   thorpej 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   2992   1.1   thorpej 	} else  {
   2993   1.1   thorpej 		DPRINTF(WM_DEBUG_LINK,
   2994   1.1   thorpej 		    ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname));
   2995   1.1   thorpej 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   2996   1.1   thorpej 	}
   2997   1.1   thorpej 
   2998   1.1   thorpej 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   2999   1.1   thorpej }
   3000