if_wm.c revision 1.349 1 1.349 knakahar /* $NetBSD: if_wm.c,v 1.349 2015/09/28 07:02:57 knakahara Exp $ */
2 1.1 thorpej
3 1.1 thorpej /*
4 1.69 thorpej * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
5 1.1 thorpej * All rights reserved.
6 1.1 thorpej *
7 1.1 thorpej * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 1.1 thorpej *
9 1.1 thorpej * Redistribution and use in source and binary forms, with or without
10 1.1 thorpej * modification, are permitted provided that the following conditions
11 1.1 thorpej * are met:
12 1.1 thorpej * 1. Redistributions of source code must retain the above copyright
13 1.1 thorpej * notice, this list of conditions and the following disclaimer.
14 1.1 thorpej * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 thorpej * notice, this list of conditions and the following disclaimer in the
16 1.1 thorpej * documentation and/or other materials provided with the distribution.
17 1.1 thorpej * 3. All advertising materials mentioning features or use of this software
18 1.1 thorpej * must display the following acknowledgement:
19 1.1 thorpej * This product includes software developed for the NetBSD Project by
20 1.1 thorpej * Wasabi Systems, Inc.
21 1.1 thorpej * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 thorpej * or promote products derived from this software without specific prior
23 1.1 thorpej * written permission.
24 1.1 thorpej *
25 1.1 thorpej * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 thorpej * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 thorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 thorpej * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 thorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 thorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 thorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 thorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 thorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 thorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 thorpej * POSSIBILITY OF SUCH DAMAGE.
36 1.1 thorpej */
37 1.1 thorpej
38 1.139 bouyer /*******************************************************************************
39 1.139 bouyer
40 1.246 christos Copyright (c) 2001-2005, Intel Corporation
41 1.139 bouyer All rights reserved.
42 1.246 christos
43 1.246 christos Redistribution and use in source and binary forms, with or without
44 1.139 bouyer modification, are permitted provided that the following conditions are met:
45 1.246 christos
46 1.246 christos 1. Redistributions of source code must retain the above copyright notice,
47 1.139 bouyer this list of conditions and the following disclaimer.
48 1.246 christos
49 1.246 christos 2. Redistributions in binary form must reproduce the above copyright
50 1.246 christos notice, this list of conditions and the following disclaimer in the
51 1.139 bouyer documentation and/or other materials provided with the distribution.
52 1.246 christos
53 1.246 christos 3. Neither the name of the Intel Corporation nor the names of its
54 1.246 christos contributors may be used to endorse or promote products derived from
55 1.139 bouyer this software without specific prior written permission.
56 1.246 christos
57 1.139 bouyer THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
58 1.246 christos AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59 1.246 christos IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
60 1.246 christos ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
61 1.246 christos LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
62 1.246 christos CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
63 1.246 christos SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
64 1.246 christos INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
65 1.246 christos CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
66 1.139 bouyer ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
67 1.139 bouyer POSSIBILITY OF SUCH DAMAGE.
68 1.139 bouyer
69 1.139 bouyer *******************************************************************************/
70 1.1 thorpej /*
71 1.11 thorpej * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
72 1.1 thorpej *
73 1.1 thorpej * TODO (in order of importance):
74 1.1 thorpej *
75 1.288 msaitoh * - Check XXX'ed comments
76 1.286 msaitoh * - EEE (Energy Efficiency Ethernet)
77 1.347 msaitoh * - Multi queue
78 1.347 msaitoh * - Image Unique ID
79 1.347 msaitoh * - LPLU other than PCH*
80 1.286 msaitoh * - Virtual Function
81 1.286 msaitoh * - Set LED correctly (based on contents in EEPROM)
82 1.61 thorpej * - Rework how parameters are loaded from the EEPROM.
83 1.1 thorpej */
84 1.38 lukem
85 1.38 lukem #include <sys/cdefs.h>
86 1.349 knakahar __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.349 2015/09/28 07:02:57 knakahara Exp $");
87 1.309 ozaki
88 1.309 ozaki #ifdef _KERNEL_OPT
89 1.309 ozaki #include "opt_net_mpsafe.h"
90 1.309 ozaki #endif
91 1.1 thorpej
92 1.1 thorpej #include <sys/param.h>
93 1.1 thorpej #include <sys/systm.h>
94 1.96 perry #include <sys/callout.h>
95 1.1 thorpej #include <sys/mbuf.h>
96 1.1 thorpej #include <sys/malloc.h>
97 1.1 thorpej #include <sys/kernel.h>
98 1.1 thorpej #include <sys/socket.h>
99 1.1 thorpej #include <sys/ioctl.h>
100 1.1 thorpej #include <sys/errno.h>
101 1.1 thorpej #include <sys/device.h>
102 1.1 thorpej #include <sys/queue.h>
103 1.84 thorpej #include <sys/syslog.h>
104 1.346 knakahar #include <sys/interrupt.h>
105 1.1 thorpej
106 1.315 riastrad #include <sys/rndsource.h>
107 1.21 itojun
108 1.1 thorpej #include <net/if.h>
109 1.96 perry #include <net/if_dl.h>
110 1.1 thorpej #include <net/if_media.h>
111 1.1 thorpej #include <net/if_ether.h>
112 1.1 thorpej
113 1.1 thorpej #include <net/bpf.h>
114 1.1 thorpej
115 1.1 thorpej #include <netinet/in.h> /* XXX for struct ip */
116 1.1 thorpej #include <netinet/in_systm.h> /* XXX for struct ip */
117 1.1 thorpej #include <netinet/ip.h> /* XXX for struct ip */
118 1.131 yamt #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
119 1.13 thorpej #include <netinet/tcp.h> /* XXX for struct tcphdr */
120 1.1 thorpej
121 1.147 ad #include <sys/bus.h>
122 1.147 ad #include <sys/intr.h>
123 1.1 thorpej #include <machine/endian.h>
124 1.1 thorpej
125 1.1 thorpej #include <dev/mii/mii.h>
126 1.1 thorpej #include <dev/mii/miivar.h>
127 1.202 msaitoh #include <dev/mii/miidevs.h>
128 1.1 thorpej #include <dev/mii/mii_bitbang.h>
129 1.127 bouyer #include <dev/mii/ikphyreg.h>
130 1.191 msaitoh #include <dev/mii/igphyreg.h>
131 1.202 msaitoh #include <dev/mii/igphyvar.h>
132 1.192 msaitoh #include <dev/mii/inbmphyreg.h>
133 1.1 thorpej
134 1.1 thorpej #include <dev/pci/pcireg.h>
135 1.1 thorpej #include <dev/pci/pcivar.h>
136 1.1 thorpej #include <dev/pci/pcidevs.h>
137 1.1 thorpej
138 1.1 thorpej #include <dev/pci/if_wmreg.h>
139 1.182 msaitoh #include <dev/pci/if_wmvar.h>
140 1.1 thorpej
141 1.1 thorpej #ifdef WM_DEBUG
142 1.1 thorpej #define WM_DEBUG_LINK 0x01
143 1.1 thorpej #define WM_DEBUG_TX 0x02
144 1.1 thorpej #define WM_DEBUG_RX 0x04
145 1.1 thorpej #define WM_DEBUG_GMII 0x08
146 1.203 msaitoh #define WM_DEBUG_MANAGE 0x10
147 1.240 msaitoh #define WM_DEBUG_NVM 0x20
148 1.203 msaitoh int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
149 1.240 msaitoh | WM_DEBUG_MANAGE | WM_DEBUG_NVM;
150 1.1 thorpej
151 1.1 thorpej #define DPRINTF(x, y) if (wm_debug & (x)) printf y
152 1.1 thorpej #else
153 1.1 thorpej #define DPRINTF(x, y) /* nothing */
154 1.1 thorpej #endif /* WM_DEBUG */
155 1.1 thorpej
156 1.272 ozaki #ifdef NET_MPSAFE
157 1.272 ozaki #define WM_MPSAFE 1
158 1.272 ozaki #endif
159 1.272 ozaki
160 1.335 msaitoh #ifdef __HAVE_PCI_MSI_MSIX
161 1.341 knakahar #define WM_MSI_MSIX 1 /* Enable by default */
162 1.335 msaitoh #endif
163 1.335 msaitoh
164 1.335 msaitoh /*
165 1.335 msaitoh * This device driver divides interrupt to TX, RX and link state.
166 1.335 msaitoh * Each MSI-X vector indexes are below.
167 1.335 msaitoh */
168 1.340 knakahar #define WM_MSIX_NINTR 3
169 1.340 knakahar #define WM_MSIX_TXINTR_IDX 0
170 1.340 knakahar #define WM_MSIX_RXINTR_IDX 1
171 1.340 knakahar #define WM_MSIX_LINKINTR_IDX 2
172 1.340 knakahar #define WM_MAX_NINTR WM_MSIX_NINTR
173 1.335 msaitoh
174 1.335 msaitoh /*
175 1.335 msaitoh * This device driver set affinity to each interrupts like below (round-robin).
176 1.335 msaitoh * If the number CPUs is less than the number of interrupts, this driver usase
177 1.335 msaitoh * the same CPU for multiple interrupts.
178 1.335 msaitoh */
179 1.340 knakahar #define WM_MSIX_TXINTR_CPUID 0
180 1.340 knakahar #define WM_MSIX_RXINTR_CPUID 1
181 1.340 knakahar #define WM_MSIX_LINKINTR_CPUID 2
182 1.335 msaitoh
183 1.1 thorpej /*
184 1.2 thorpej * Transmit descriptor list size. Due to errata, we can only have
185 1.75 thorpej * 256 hardware descriptors in the ring on < 82544, but we use 4096
186 1.75 thorpej * on >= 82544. We tell the upper layers that they can queue a lot
187 1.75 thorpej * of packets, and we go ahead and manage up to 64 (16 for the i82547)
188 1.75 thorpej * of them at a time.
189 1.75 thorpej *
190 1.75 thorpej * We allow up to 256 (!) DMA segments per packet. Pathological packet
191 1.75 thorpej * chains containing many small mbufs have been observed in zero-copy
192 1.75 thorpej * situations with jumbo frames.
193 1.1 thorpej */
194 1.75 thorpej #define WM_NTXSEGS 256
195 1.2 thorpej #define WM_IFQUEUELEN 256
196 1.74 tron #define WM_TXQUEUELEN_MAX 64
197 1.74 tron #define WM_TXQUEUELEN_MAX_82547 16
198 1.74 tron #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum)
199 1.74 tron #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1)
200 1.74 tron #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8)
201 1.75 thorpej #define WM_NTXDESC_82542 256
202 1.75 thorpej #define WM_NTXDESC_82544 4096
203 1.75 thorpej #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc)
204 1.75 thorpej #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1)
205 1.75 thorpej #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t))
206 1.75 thorpej #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc))
207 1.74 tron #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc))
208 1.1 thorpej
209 1.269 tls #define WM_MAXTXDMA (2 * round_page(IP_MAXPACKET)) /* for TSO */
210 1.82 thorpej
211 1.1 thorpej /*
212 1.1 thorpej * Receive descriptor list size. We have one Rx buffer for normal
213 1.1 thorpej * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized
214 1.10 thorpej * packet. We allocate 256 receive descriptors, each with a 2k
215 1.10 thorpej * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
216 1.1 thorpej */
217 1.10 thorpej #define WM_NRXDESC 256
218 1.1 thorpej #define WM_NRXDESC_MASK (WM_NRXDESC - 1)
219 1.1 thorpej #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK)
220 1.1 thorpej #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK)
221 1.1 thorpej
222 1.1 thorpej /*
223 1.1 thorpej * Control structures are DMA'd to the i82542 chip. We allocate them in
224 1.105 skrll * a single clump that maps to a single DMA segment to make several things
225 1.1 thorpej * easier.
226 1.1 thorpej */
227 1.75 thorpej struct wm_control_data_82544 {
228 1.1 thorpej /*
229 1.75 thorpej * The receive descriptors.
230 1.1 thorpej */
231 1.75 thorpej wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
232 1.1 thorpej
233 1.1 thorpej /*
234 1.75 thorpej * The transmit descriptors. Put these at the end, because
235 1.75 thorpej * we might use a smaller number of them.
236 1.1 thorpej */
237 1.232 bouyer union {
238 1.232 bouyer wiseman_txdesc_t wcdu_txdescs[WM_NTXDESC_82544];
239 1.232 bouyer nq_txdesc_t wcdu_nq_txdescs[WM_NTXDESC_82544];
240 1.232 bouyer } wdc_u;
241 1.75 thorpej };
242 1.75 thorpej
243 1.75 thorpej struct wm_control_data_82542 {
244 1.1 thorpej wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
245 1.75 thorpej wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542];
246 1.1 thorpej };
247 1.1 thorpej
248 1.75 thorpej #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x)
249 1.232 bouyer #define WM_CDTXOFF(x) WM_CDOFF(wdc_u.wcdu_txdescs[(x)])
250 1.1 thorpej #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)])
251 1.1 thorpej
252 1.1 thorpej /*
253 1.1 thorpej * Software state for transmit jobs.
254 1.1 thorpej */
255 1.1 thorpej struct wm_txsoft {
256 1.1 thorpej struct mbuf *txs_mbuf; /* head of our mbuf chain */
257 1.1 thorpej bus_dmamap_t txs_dmamap; /* our DMA map */
258 1.1 thorpej int txs_firstdesc; /* first descriptor in packet */
259 1.1 thorpej int txs_lastdesc; /* last descriptor in packet */
260 1.4 thorpej int txs_ndesc; /* # of descriptors used */
261 1.1 thorpej };
262 1.1 thorpej
263 1.1 thorpej /*
264 1.1 thorpej * Software state for receive buffers. Each descriptor gets a
265 1.1 thorpej * 2k (MCLBYTES) buffer and a DMA map. For packets which fill
266 1.1 thorpej * more than one buffer, we chain them together.
267 1.1 thorpej */
268 1.1 thorpej struct wm_rxsoft {
269 1.1 thorpej struct mbuf *rxs_mbuf; /* head of our mbuf chain */
270 1.1 thorpej bus_dmamap_t rxs_dmamap; /* our DMA map */
271 1.1 thorpej };
272 1.1 thorpej
273 1.173 msaitoh #define WM_LINKUP_TIMEOUT 50
274 1.173 msaitoh
275 1.199 msaitoh static uint16_t swfwphysem[] = {
276 1.199 msaitoh SWFW_PHY0_SM,
277 1.199 msaitoh SWFW_PHY1_SM,
278 1.199 msaitoh SWFW_PHY2_SM,
279 1.199 msaitoh SWFW_PHY3_SM
280 1.199 msaitoh };
281 1.199 msaitoh
282 1.320 msaitoh static const uint32_t wm_82580_rxpbs_table[] = {
283 1.320 msaitoh 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
284 1.320 msaitoh };
285 1.320 msaitoh
286 1.1 thorpej /*
287 1.1 thorpej * Software state per device.
288 1.1 thorpej */
289 1.1 thorpej struct wm_softc {
290 1.160 christos device_t sc_dev; /* generic device information */
291 1.1 thorpej bus_space_tag_t sc_st; /* bus space tag */
292 1.1 thorpej bus_space_handle_t sc_sh; /* bus space handle */
293 1.204 msaitoh bus_size_t sc_ss; /* bus space size */
294 1.53 thorpej bus_space_tag_t sc_iot; /* I/O space tag */
295 1.53 thorpej bus_space_handle_t sc_ioh; /* I/O space handle */
296 1.212 jakllsch bus_size_t sc_ios; /* I/O space size */
297 1.139 bouyer bus_space_tag_t sc_flasht; /* flash registers space tag */
298 1.139 bouyer bus_space_handle_t sc_flashh; /* flash registers space handle */
299 1.336 msaitoh bus_size_t sc_flashs; /* flash registers space size */
300 1.1 thorpej bus_dma_tag_t sc_dmat; /* bus DMA tag */
301 1.199 msaitoh
302 1.1 thorpej struct ethercom sc_ethercom; /* ethernet common data */
303 1.199 msaitoh struct mii_data sc_mii; /* MII/media information */
304 1.199 msaitoh
305 1.123 jmcneill pci_chipset_tag_t sc_pc;
306 1.123 jmcneill pcitag_t sc_pcitag;
307 1.199 msaitoh int sc_bus_speed; /* PCI/PCIX bus speed */
308 1.281 msaitoh int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */
309 1.1 thorpej
310 1.304 msaitoh uint16_t sc_pcidevid; /* PCI device ID */
311 1.192 msaitoh wm_chip_type sc_type; /* MAC type */
312 1.192 msaitoh int sc_rev; /* MAC revision */
313 1.192 msaitoh wm_phy_type sc_phytype; /* PHY type */
314 1.292 msaitoh uint32_t sc_mediatype; /* Media type (Copper, Fiber, SERDES)*/
315 1.311 msaitoh #define WM_MEDIATYPE_UNKNOWN 0x00
316 1.311 msaitoh #define WM_MEDIATYPE_FIBER 0x01
317 1.311 msaitoh #define WM_MEDIATYPE_COPPER 0x02
318 1.311 msaitoh #define WM_MEDIATYPE_SERDES 0x03 /* Internal SERDES */
319 1.199 msaitoh int sc_funcid; /* unit number of the chip (0 to 3) */
320 1.1 thorpej int sc_flags; /* flags; see below */
321 1.179 msaitoh int sc_if_flags; /* last if_flags */
322 1.71 thorpej int sc_flowflags; /* 802.3x flow control flags */
323 1.199 msaitoh int sc_align_tweak;
324 1.1 thorpej
325 1.335 msaitoh void *sc_ihs[WM_MAX_NINTR]; /*
326 1.335 msaitoh * interrupt cookie.
327 1.335 msaitoh * legacy and msi use sc_ihs[0].
328 1.335 msaitoh */
329 1.335 msaitoh pci_intr_handle_t *sc_intrs; /* legacy and msi use sc_intrs[0] */
330 1.335 msaitoh int sc_nintrs; /* number of interrupts */
331 1.335 msaitoh
332 1.199 msaitoh callout_t sc_tick_ch; /* tick callout */
333 1.272 ozaki bool sc_stopping;
334 1.1 thorpej
335 1.328 msaitoh int sc_nvm_ver_major;
336 1.328 msaitoh int sc_nvm_ver_minor;
337 1.294 msaitoh int sc_nvm_addrbits; /* NVM address bits */
338 1.328 msaitoh unsigned int sc_nvm_wordsize; /* NVM word size */
339 1.199 msaitoh int sc_ich8_flash_base;
340 1.199 msaitoh int sc_ich8_flash_bank_size;
341 1.199 msaitoh int sc_nvm_k1_enabled;
342 1.42 thorpej
343 1.281 msaitoh /* Software state for the transmit and receive descriptors. */
344 1.203 msaitoh int sc_txnum; /* must be a power of two */
345 1.203 msaitoh struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX];
346 1.203 msaitoh struct wm_rxsoft sc_rxsoft[WM_NRXDESC];
347 1.1 thorpej
348 1.281 msaitoh /* Control data structures. */
349 1.201 msaitoh int sc_ntxdesc; /* must be a power of two */
350 1.75 thorpej struct wm_control_data_82544 *sc_control_data;
351 1.201 msaitoh bus_dmamap_t sc_cddmamap; /* control data DMA map */
352 1.201 msaitoh bus_dma_segment_t sc_cd_seg; /* control data segment */
353 1.201 msaitoh int sc_cd_rseg; /* real number of control segment */
354 1.201 msaitoh size_t sc_cd_size; /* control data size */
355 1.201 msaitoh #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
356 1.232 bouyer #define sc_txdescs sc_control_data->wdc_u.wcdu_txdescs
357 1.232 bouyer #define sc_nq_txdescs sc_control_data->wdc_u.wcdu_nq_txdescs
358 1.1 thorpej #define sc_rxdescs sc_control_data->wcd_rxdescs
359 1.1 thorpej
360 1.1 thorpej #ifdef WM_EVENT_COUNTERS
361 1.1 thorpej /* Event counters. */
362 1.1 thorpej struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */
363 1.1 thorpej struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */
364 1.78 thorpej struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
365 1.4 thorpej struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */
366 1.4 thorpej struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */
367 1.1 thorpej struct evcnt sc_ev_rxintr; /* Rx interrupts */
368 1.1 thorpej struct evcnt sc_ev_linkintr; /* Link interrupts */
369 1.1 thorpej
370 1.1 thorpej struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */
371 1.1 thorpej struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */
372 1.1 thorpej struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */
373 1.1 thorpej struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */
374 1.107 yamt struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */
375 1.131 yamt struct evcnt sc_ev_txtso; /* TCP seg offload out-bound (IPv4) */
376 1.131 yamt struct evcnt sc_ev_txtso6; /* TCP seg offload out-bound (IPv6) */
377 1.99 matt struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */
378 1.1 thorpej
379 1.2 thorpej struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
380 1.1 thorpej struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */
381 1.1 thorpej
382 1.1 thorpej struct evcnt sc_ev_tu; /* Tx underrun */
383 1.71 thorpej
384 1.71 thorpej struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */
385 1.71 thorpej struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */
386 1.71 thorpej struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */
387 1.71 thorpej struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */
388 1.71 thorpej struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */
389 1.1 thorpej #endif /* WM_EVENT_COUNTERS */
390 1.1 thorpej
391 1.1 thorpej bus_addr_t sc_tdt_reg; /* offset of TDT register */
392 1.1 thorpej
393 1.1 thorpej int sc_txfree; /* number of free Tx descriptors */
394 1.1 thorpej int sc_txnext; /* next ready Tx descriptor */
395 1.1 thorpej
396 1.1 thorpej int sc_txsfree; /* number of free Tx jobs */
397 1.1 thorpej int sc_txsnext; /* next free Tx job */
398 1.1 thorpej int sc_txsdirty; /* dirty Tx jobs */
399 1.1 thorpej
400 1.78 thorpej /* These 5 variables are used only on the 82547. */
401 1.78 thorpej int sc_txfifo_size; /* Tx FIFO size */
402 1.78 thorpej int sc_txfifo_head; /* current head of FIFO */
403 1.78 thorpej uint32_t sc_txfifo_addr; /* internal address of start of FIFO */
404 1.78 thorpej int sc_txfifo_stall; /* Tx FIFO is stalled */
405 1.142 ad callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */
406 1.78 thorpej
407 1.1 thorpej bus_addr_t sc_rdt_reg; /* offset of RDT register */
408 1.1 thorpej
409 1.1 thorpej int sc_rxptr; /* next ready Rx descriptor/queue ent */
410 1.1 thorpej int sc_rxdiscard;
411 1.1 thorpej int sc_rxlen;
412 1.1 thorpej struct mbuf *sc_rxhead;
413 1.1 thorpej struct mbuf *sc_rxtail;
414 1.1 thorpej struct mbuf **sc_rxtailp;
415 1.1 thorpej
416 1.1 thorpej uint32_t sc_ctrl; /* prototype CTRL register */
417 1.1 thorpej #if 0
418 1.1 thorpej uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */
419 1.1 thorpej #endif
420 1.1 thorpej uint32_t sc_icr; /* prototype interrupt bits */
421 1.92 briggs uint32_t sc_itr; /* prototype intr throttling reg */
422 1.1 thorpej uint32_t sc_tctl; /* prototype TCTL register */
423 1.1 thorpej uint32_t sc_rctl; /* prototype RCTL register */
424 1.1 thorpej uint32_t sc_txcw; /* prototype TXCW register */
425 1.1 thorpej uint32_t sc_tipg; /* prototype TIPG register */
426 1.71 thorpej uint32_t sc_fcrtl; /* prototype FCRTL register */
427 1.78 thorpej uint32_t sc_pba; /* prototype PBA register */
428 1.1 thorpej
429 1.1 thorpej int sc_tbi_linkup; /* TBI link status */
430 1.325 msaitoh int sc_tbi_serdes_anegticks; /* autonegotiation ticks */
431 1.325 msaitoh int sc_tbi_serdes_ticks; /* tbi ticks */
432 1.1 thorpej
433 1.1 thorpej int sc_mchash_type; /* multicast filter offset */
434 1.21 itojun
435 1.224 tls krndsource_t rnd_source; /* random source */
436 1.272 ozaki
437 1.283 ozaki kmutex_t *sc_tx_lock; /* lock for tx operations */
438 1.283 ozaki kmutex_t *sc_rx_lock; /* lock for rx operations */
439 1.1 thorpej };
440 1.1 thorpej
441 1.283 ozaki #define WM_TX_LOCK(_sc) if ((_sc)->sc_tx_lock) mutex_enter((_sc)->sc_tx_lock)
442 1.283 ozaki #define WM_TX_UNLOCK(_sc) if ((_sc)->sc_tx_lock) mutex_exit((_sc)->sc_tx_lock)
443 1.283 ozaki #define WM_TX_LOCKED(_sc) (!(_sc)->sc_tx_lock || mutex_owned((_sc)->sc_tx_lock))
444 1.283 ozaki #define WM_RX_LOCK(_sc) if ((_sc)->sc_rx_lock) mutex_enter((_sc)->sc_rx_lock)
445 1.283 ozaki #define WM_RX_UNLOCK(_sc) if ((_sc)->sc_rx_lock) mutex_exit((_sc)->sc_rx_lock)
446 1.283 ozaki #define WM_RX_LOCKED(_sc) (!(_sc)->sc_rx_lock || mutex_owned((_sc)->sc_rx_lock))
447 1.283 ozaki #define WM_BOTH_LOCK(_sc) do {WM_TX_LOCK(_sc); WM_RX_LOCK(_sc);} while (0)
448 1.283 ozaki #define WM_BOTH_UNLOCK(_sc) do {WM_RX_UNLOCK(_sc); WM_TX_UNLOCK(_sc);} while (0)
449 1.283 ozaki #define WM_BOTH_LOCKED(_sc) (WM_TX_LOCKED(_sc) && WM_RX_LOCKED(_sc))
450 1.272 ozaki
451 1.272 ozaki #ifdef WM_MPSAFE
452 1.272 ozaki #define CALLOUT_FLAGS CALLOUT_MPSAFE
453 1.272 ozaki #else
454 1.272 ozaki #define CALLOUT_FLAGS 0
455 1.272 ozaki #endif
456 1.272 ozaki
457 1.1 thorpej #define WM_RXCHAIN_RESET(sc) \
458 1.1 thorpej do { \
459 1.1 thorpej (sc)->sc_rxtailp = &(sc)->sc_rxhead; \
460 1.1 thorpej *(sc)->sc_rxtailp = NULL; \
461 1.1 thorpej (sc)->sc_rxlen = 0; \
462 1.1 thorpej } while (/*CONSTCOND*/0)
463 1.1 thorpej
464 1.1 thorpej #define WM_RXCHAIN_LINK(sc, m) \
465 1.1 thorpej do { \
466 1.1 thorpej *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \
467 1.1 thorpej (sc)->sc_rxtailp = &(m)->m_next; \
468 1.1 thorpej } while (/*CONSTCOND*/0)
469 1.1 thorpej
470 1.1 thorpej #ifdef WM_EVENT_COUNTERS
471 1.1 thorpej #define WM_EVCNT_INCR(ev) (ev)->ev_count++
472 1.71 thorpej #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val)
473 1.1 thorpej #else
474 1.1 thorpej #define WM_EVCNT_INCR(ev) /* nothing */
475 1.71 thorpej #define WM_EVCNT_ADD(ev, val) /* nothing */
476 1.1 thorpej #endif
477 1.1 thorpej
478 1.1 thorpej #define CSR_READ(sc, reg) \
479 1.1 thorpej bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
480 1.1 thorpej #define CSR_WRITE(sc, reg, val) \
481 1.1 thorpej bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
482 1.78 thorpej #define CSR_WRITE_FLUSH(sc) \
483 1.78 thorpej (void) CSR_READ((sc), WMREG_STATUS)
484 1.1 thorpej
485 1.139 bouyer #define ICH8_FLASH_READ32(sc, reg) \
486 1.139 bouyer bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg))
487 1.139 bouyer #define ICH8_FLASH_WRITE32(sc, reg, data) \
488 1.139 bouyer bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
489 1.139 bouyer
490 1.139 bouyer #define ICH8_FLASH_READ16(sc, reg) \
491 1.139 bouyer bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg))
492 1.139 bouyer #define ICH8_FLASH_WRITE16(sc, reg, data) \
493 1.139 bouyer bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
494 1.139 bouyer
495 1.1 thorpej #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x)))
496 1.1 thorpej #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x)))
497 1.1 thorpej
498 1.69 thorpej #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU)
499 1.69 thorpej #define WM_CDTXADDR_HI(sc, x) \
500 1.69 thorpej (sizeof(bus_addr_t) == 8 ? \
501 1.69 thorpej (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
502 1.69 thorpej
503 1.69 thorpej #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU)
504 1.69 thorpej #define WM_CDRXADDR_HI(sc, x) \
505 1.69 thorpej (sizeof(bus_addr_t) == 8 ? \
506 1.69 thorpej (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
507 1.69 thorpej
508 1.1 thorpej #define WM_CDTXSYNC(sc, x, n, ops) \
509 1.1 thorpej do { \
510 1.1 thorpej int __x, __n; \
511 1.1 thorpej \
512 1.1 thorpej __x = (x); \
513 1.1 thorpej __n = (n); \
514 1.1 thorpej \
515 1.1 thorpej /* If it will wrap around, sync to the end of the ring. */ \
516 1.75 thorpej if ((__x + __n) > WM_NTXDESC(sc)) { \
517 1.1 thorpej bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
518 1.1 thorpej WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \
519 1.75 thorpej (WM_NTXDESC(sc) - __x), (ops)); \
520 1.75 thorpej __n -= (WM_NTXDESC(sc) - __x); \
521 1.1 thorpej __x = 0; \
522 1.1 thorpej } \
523 1.1 thorpej \
524 1.1 thorpej /* Now sync whatever is left. */ \
525 1.1 thorpej bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
526 1.1 thorpej WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \
527 1.1 thorpej } while (/*CONSTCOND*/0)
528 1.1 thorpej
529 1.1 thorpej #define WM_CDRXSYNC(sc, x, ops) \
530 1.1 thorpej do { \
531 1.1 thorpej bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
532 1.1 thorpej WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \
533 1.1 thorpej } while (/*CONSTCOND*/0)
534 1.1 thorpej
535 1.1 thorpej #define WM_INIT_RXDESC(sc, x) \
536 1.1 thorpej do { \
537 1.1 thorpej struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \
538 1.1 thorpej wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \
539 1.1 thorpej struct mbuf *__m = __rxs->rxs_mbuf; \
540 1.1 thorpej \
541 1.1 thorpej /* \
542 1.1 thorpej * Note: We scoot the packet forward 2 bytes in the buffer \
543 1.1 thorpej * so that the payload after the Ethernet header is aligned \
544 1.1 thorpej * to a 4-byte boundary. \
545 1.1 thorpej * \
546 1.1 thorpej * XXX BRAINDAMAGE ALERT! \
547 1.1 thorpej * The stupid chip uses the same size for every buffer, which \
548 1.1 thorpej * is set in the Receive Control register. We are using the 2K \
549 1.1 thorpej * size option, but what we REALLY want is (2K - 2)! For this \
550 1.41 tls * reason, we can't "scoot" packets longer than the standard \
551 1.41 tls * Ethernet MTU. On strict-alignment platforms, if the total \
552 1.42 thorpej * size exceeds (2K - 2) we set align_tweak to 0 and let \
553 1.41 tls * the upper layer copy the headers. \
554 1.1 thorpej */ \
555 1.42 thorpej __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \
556 1.1 thorpej \
557 1.69 thorpej wm_set_dma_addr(&__rxd->wrx_addr, \
558 1.69 thorpej __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \
559 1.1 thorpej __rxd->wrx_len = 0; \
560 1.1 thorpej __rxd->wrx_cksum = 0; \
561 1.1 thorpej __rxd->wrx_status = 0; \
562 1.1 thorpej __rxd->wrx_errors = 0; \
563 1.1 thorpej __rxd->wrx_special = 0; \
564 1.1 thorpej WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
565 1.1 thorpej \
566 1.1 thorpej CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \
567 1.1 thorpej } while (/*CONSTCOND*/0)
568 1.1 thorpej
569 1.280 msaitoh /*
570 1.280 msaitoh * Register read/write functions.
571 1.280 msaitoh * Other than CSR_{READ|WRITE}().
572 1.280 msaitoh */
573 1.280 msaitoh #if 0
574 1.280 msaitoh static inline uint32_t wm_io_read(struct wm_softc *, int);
575 1.280 msaitoh #endif
576 1.280 msaitoh static inline void wm_io_write(struct wm_softc *, int, uint32_t);
577 1.280 msaitoh static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
578 1.280 msaitoh uint32_t, uint32_t);
579 1.280 msaitoh static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
580 1.280 msaitoh
581 1.280 msaitoh /*
582 1.280 msaitoh * Device driver interface functions and commonly used functions.
583 1.280 msaitoh * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
584 1.280 msaitoh */
585 1.280 msaitoh static const struct wm_product *wm_lookup(const struct pci_attach_args *);
586 1.280 msaitoh static int wm_match(device_t, cfdata_t, void *);
587 1.280 msaitoh static void wm_attach(device_t, device_t, void *);
588 1.280 msaitoh static int wm_detach(device_t, int);
589 1.280 msaitoh static bool wm_suspend(device_t, const pmf_qual_t *);
590 1.280 msaitoh static bool wm_resume(device_t, const pmf_qual_t *);
591 1.47 thorpej static void wm_watchdog(struct ifnet *);
592 1.280 msaitoh static void wm_tick(void *);
593 1.213 msaitoh static int wm_ifflags_cb(struct ethercom *);
594 1.135 christos static int wm_ioctl(struct ifnet *, u_long, void *);
595 1.280 msaitoh /* MAC address related */
596 1.306 msaitoh static uint16_t wm_check_alt_mac_addr(struct wm_softc *);
597 1.280 msaitoh static int wm_read_mac_addr(struct wm_softc *, uint8_t *);
598 1.280 msaitoh static void wm_set_ral(struct wm_softc *, const uint8_t *, int);
599 1.280 msaitoh static uint32_t wm_mchash(struct wm_softc *, const uint8_t *);
600 1.280 msaitoh static void wm_set_filter(struct wm_softc *);
601 1.280 msaitoh /* Reset and init related */
602 1.280 msaitoh static void wm_set_vlan(struct wm_softc *);
603 1.280 msaitoh static void wm_set_pcie_completion_timeout(struct wm_softc *);
604 1.280 msaitoh static void wm_get_auto_rd_done(struct wm_softc *);
605 1.280 msaitoh static void wm_lan_init_done(struct wm_softc *);
606 1.280 msaitoh static void wm_get_cfg_done(struct wm_softc *);
607 1.312 msaitoh static void wm_initialize_hardware_bits(struct wm_softc *);
608 1.320 msaitoh static uint32_t wm_rxpbs_adjust_82580(uint32_t);
609 1.280 msaitoh static void wm_reset(struct wm_softc *);
610 1.280 msaitoh static int wm_add_rxbuf(struct wm_softc *, int);
611 1.280 msaitoh static void wm_rxdrain(struct wm_softc *);
612 1.47 thorpej static int wm_init(struct ifnet *);
613 1.272 ozaki static int wm_init_locked(struct ifnet *);
614 1.47 thorpej static void wm_stop(struct ifnet *, int);
615 1.272 ozaki static void wm_stop_locked(struct ifnet *, int);
616 1.280 msaitoh static int wm_tx_offload(struct wm_softc *, struct wm_txsoft *,
617 1.280 msaitoh uint32_t *, uint8_t *);
618 1.280 msaitoh static void wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
619 1.280 msaitoh static void wm_82547_txfifo_stall(void *);
620 1.280 msaitoh static int wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
621 1.280 msaitoh /* Start */
622 1.280 msaitoh static void wm_start(struct ifnet *);
623 1.280 msaitoh static void wm_start_locked(struct ifnet *);
624 1.280 msaitoh static int wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *,
625 1.280 msaitoh uint32_t *, uint32_t *, bool *);
626 1.280 msaitoh static void wm_nq_start(struct ifnet *);
627 1.280 msaitoh static void wm_nq_start_locked(struct ifnet *);
628 1.280 msaitoh /* Interrupt */
629 1.335 msaitoh static int wm_txeof(struct wm_softc *);
630 1.335 msaitoh static void wm_rxeof(struct wm_softc *);
631 1.280 msaitoh static void wm_linkintr_gmii(struct wm_softc *, uint32_t);
632 1.280 msaitoh static void wm_linkintr_tbi(struct wm_softc *, uint32_t);
633 1.325 msaitoh static void wm_linkintr_serdes(struct wm_softc *, uint32_t);
634 1.47 thorpej static void wm_linkintr(struct wm_softc *, uint32_t);
635 1.335 msaitoh static int wm_intr_legacy(void *);
636 1.335 msaitoh #ifdef WM_MSI_MSIX
637 1.335 msaitoh static int wm_txintr_msix(void *);
638 1.335 msaitoh static int wm_rxintr_msix(void *);
639 1.335 msaitoh static int wm_linkintr_msix(void *);
640 1.335 msaitoh #endif
641 1.1 thorpej
642 1.280 msaitoh /*
643 1.280 msaitoh * Media related.
644 1.292 msaitoh * GMII, SGMII, TBI, SERDES and SFP.
645 1.280 msaitoh */
646 1.325 msaitoh /* Common */
647 1.325 msaitoh static void wm_tbi_serdes_set_linkled(struct wm_softc *);
648 1.280 msaitoh /* GMII related */
649 1.47 thorpej static void wm_gmii_reset(struct wm_softc *);
650 1.280 msaitoh static int wm_get_phy_id_82575(struct wm_softc *);
651 1.280 msaitoh static void wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
652 1.324 msaitoh static int wm_gmii_mediachange(struct ifnet *);
653 1.280 msaitoh static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
654 1.280 msaitoh static void wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
655 1.280 msaitoh static uint32_t wm_i82543_mii_recvbits(struct wm_softc *);
656 1.157 dyoung static int wm_gmii_i82543_readreg(device_t, int, int);
657 1.157 dyoung static void wm_gmii_i82543_writereg(device_t, int, int, int);
658 1.157 dyoung static int wm_gmii_i82544_readreg(device_t, int, int);
659 1.157 dyoung static void wm_gmii_i82544_writereg(device_t, int, int, int);
660 1.157 dyoung static int wm_gmii_i80003_readreg(device_t, int, int);
661 1.157 dyoung static void wm_gmii_i80003_writereg(device_t, int, int, int);
662 1.167 msaitoh static int wm_gmii_bm_readreg(device_t, int, int);
663 1.167 msaitoh static void wm_gmii_bm_writereg(device_t, int, int, int);
664 1.280 msaitoh static void wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int);
665 1.192 msaitoh static int wm_gmii_hv_readreg(device_t, int, int);
666 1.192 msaitoh static void wm_gmii_hv_writereg(device_t, int, int, int);
667 1.243 msaitoh static int wm_gmii_82580_readreg(device_t, int, int);
668 1.243 msaitoh static void wm_gmii_82580_writereg(device_t, int, int, int);
669 1.329 msaitoh static int wm_gmii_gs40g_readreg(device_t, int, int);
670 1.329 msaitoh static void wm_gmii_gs40g_writereg(device_t, int, int, int);
671 1.280 msaitoh static void wm_gmii_statchg(struct ifnet *);
672 1.280 msaitoh static int wm_kmrn_readreg(struct wm_softc *, int);
673 1.280 msaitoh static void wm_kmrn_writereg(struct wm_softc *, int, int);
674 1.280 msaitoh /* SGMII */
675 1.265 msaitoh static bool wm_sgmii_uses_mdio(struct wm_softc *);
676 1.199 msaitoh static int wm_sgmii_readreg(device_t, int, int);
677 1.199 msaitoh static void wm_sgmii_writereg(device_t, int, int, int);
678 1.280 msaitoh /* TBI related */
679 1.280 msaitoh static void wm_tbi_mediainit(struct wm_softc *);
680 1.324 msaitoh static int wm_tbi_mediachange(struct ifnet *);
681 1.280 msaitoh static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
682 1.325 msaitoh static int wm_check_for_link(struct wm_softc *);
683 1.325 msaitoh static void wm_tbi_tick(struct wm_softc *);
684 1.325 msaitoh /* SERDES related */
685 1.325 msaitoh static void wm_serdes_power_up_link_82575(struct wm_softc *);
686 1.325 msaitoh static int wm_serdes_mediachange(struct ifnet *);
687 1.325 msaitoh static void wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
688 1.325 msaitoh static void wm_serdes_tick(struct wm_softc *);
689 1.292 msaitoh /* SFP related */
690 1.295 msaitoh static int wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
691 1.295 msaitoh static uint32_t wm_sfp_get_media_type(struct wm_softc *);
692 1.167 msaitoh
693 1.280 msaitoh /*
694 1.280 msaitoh * NVM related.
695 1.280 msaitoh * Microwire, SPI (w/wo EERD) and Flash.
696 1.280 msaitoh */
697 1.294 msaitoh /* Misc functions */
698 1.280 msaitoh static void wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
699 1.280 msaitoh static void wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
700 1.294 msaitoh static int wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
701 1.280 msaitoh /* Microwire */
702 1.280 msaitoh static int wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
703 1.280 msaitoh /* SPI */
704 1.280 msaitoh static int wm_nvm_ready_spi(struct wm_softc *);
705 1.280 msaitoh static int wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
706 1.280 msaitoh /* Using with EERD */
707 1.280 msaitoh static int wm_poll_eerd_eewr_done(struct wm_softc *, int);
708 1.280 msaitoh static int wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
709 1.280 msaitoh /* Flash */
710 1.280 msaitoh static int wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
711 1.280 msaitoh unsigned int *);
712 1.280 msaitoh static int32_t wm_ich8_cycle_init(struct wm_softc *);
713 1.280 msaitoh static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
714 1.280 msaitoh static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
715 1.280 msaitoh uint16_t *);
716 1.280 msaitoh static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
717 1.280 msaitoh static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
718 1.280 msaitoh static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
719 1.321 msaitoh /* iNVM */
720 1.321 msaitoh static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
721 1.321 msaitoh static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
722 1.327 msaitoh /* Lock, detecting NVM type, validate checksum and read */
723 1.280 msaitoh static int wm_nvm_acquire(struct wm_softc *);
724 1.280 msaitoh static void wm_nvm_release(struct wm_softc *);
725 1.280 msaitoh static int wm_nvm_is_onboard_eeprom(struct wm_softc *);
726 1.321 msaitoh static int wm_nvm_get_flash_presence_i210(struct wm_softc *);
727 1.280 msaitoh static int wm_nvm_validate_checksum(struct wm_softc *);
728 1.347 msaitoh static void wm_nvm_version_invm(struct wm_softc *);
729 1.328 msaitoh static void wm_nvm_version(struct wm_softc *);
730 1.280 msaitoh static int wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
731 1.1 thorpej
732 1.280 msaitoh /*
733 1.280 msaitoh * Hardware semaphores.
734 1.280 msaitoh * Very complexed...
735 1.280 msaitoh */
736 1.127 bouyer static int wm_get_swsm_semaphore(struct wm_softc *);
737 1.127 bouyer static void wm_put_swsm_semaphore(struct wm_softc *);
738 1.127 bouyer static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
739 1.127 bouyer static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
740 1.139 bouyer static int wm_get_swfwhw_semaphore(struct wm_softc *);
741 1.139 bouyer static void wm_put_swfwhw_semaphore(struct wm_softc *);
742 1.259 msaitoh static int wm_get_hw_semaphore_82573(struct wm_softc *);
743 1.259 msaitoh static void wm_put_hw_semaphore_82573(struct wm_softc *);
744 1.139 bouyer
745 1.280 msaitoh /*
746 1.280 msaitoh * Management mode and power management related subroutines.
747 1.280 msaitoh * BMC, AMT, suspend/resume and EEE.
748 1.280 msaitoh */
749 1.169 msaitoh static int wm_check_mng_mode(struct wm_softc *);
750 1.169 msaitoh static int wm_check_mng_mode_ich8lan(struct wm_softc *);
751 1.169 msaitoh static int wm_check_mng_mode_82574(struct wm_softc *);
752 1.169 msaitoh static int wm_check_mng_mode_generic(struct wm_softc *);
753 1.203 msaitoh static int wm_enable_mng_pass_thru(struct wm_softc *);
754 1.189 msaitoh static int wm_check_reset_block(struct wm_softc *);
755 1.169 msaitoh static void wm_get_hw_control(struct wm_softc *);
756 1.280 msaitoh static void wm_release_hw_control(struct wm_softc *);
757 1.280 msaitoh static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int);
758 1.280 msaitoh static void wm_smbustopci(struct wm_softc *);
759 1.280 msaitoh static void wm_init_manageability(struct wm_softc *);
760 1.280 msaitoh static void wm_release_manageability(struct wm_softc *);
761 1.280 msaitoh static void wm_get_wakeup(struct wm_softc *);
762 1.203 msaitoh #ifdef WM_WOL
763 1.280 msaitoh static void wm_enable_phy_wakeup(struct wm_softc *);
764 1.203 msaitoh static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
765 1.280 msaitoh static void wm_enable_wakeup(struct wm_softc *);
766 1.203 msaitoh #endif
767 1.280 msaitoh /* EEE */
768 1.280 msaitoh static void wm_set_eee_i350(struct wm_softc *);
769 1.280 msaitoh
770 1.280 msaitoh /*
771 1.280 msaitoh * Workarounds (mainly PHY related).
772 1.280 msaitoh * Basically, PHY's workarounds are in the PHY drivers.
773 1.280 msaitoh */
774 1.280 msaitoh static void wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
775 1.280 msaitoh static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
776 1.192 msaitoh static void wm_hv_phy_workaround_ich8lan(struct wm_softc *);
777 1.221 msaitoh static void wm_lv_phy_workaround_ich8lan(struct wm_softc *);
778 1.192 msaitoh static void wm_k1_gig_workaround_hv(struct wm_softc *, int);
779 1.221 msaitoh static void wm_set_mdio_slow_mode_hv(struct wm_softc *);
780 1.192 msaitoh static void wm_configure_k1_ich8lan(struct wm_softc *, int);
781 1.199 msaitoh static void wm_reset_init_script_82575(struct wm_softc *);
782 1.325 msaitoh static void wm_reset_mdicnfg_82580(struct wm_softc *);
783 1.329 msaitoh static void wm_pll_workaround_i210(struct wm_softc *);
784 1.1 thorpej
785 1.340 knakahar #ifdef WM_MSI_MSIX
786 1.340 knakahar struct _msix_matrix {
787 1.340 knakahar const char *intrname;
788 1.340 knakahar int(*func)(void *);
789 1.340 knakahar int intridx;
790 1.340 knakahar int cpuid;
791 1.340 knakahar } msix_matrix[WM_MSIX_NINTR] = {
792 1.340 knakahar { "TX", wm_txintr_msix, WM_MSIX_TXINTR_IDX, WM_MSIX_TXINTR_CPUID },
793 1.342 knakahar { "RX", wm_rxintr_msix, WM_MSIX_RXINTR_IDX, WM_MSIX_RXINTR_CPUID },
794 1.340 knakahar { "LINK", wm_linkintr_msix, WM_MSIX_LINKINTR_IDX,
795 1.340 knakahar WM_MSIX_LINKINTR_CPUID },
796 1.340 knakahar };
797 1.340 knakahar #endif
798 1.340 knakahar
799 1.201 msaitoh CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
800 1.201 msaitoh wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
801 1.1 thorpej
802 1.1 thorpej /*
803 1.1 thorpej * Devices supported by this driver.
804 1.1 thorpej */
805 1.76 thorpej static const struct wm_product {
806 1.1 thorpej pci_vendor_id_t wmp_vendor;
807 1.1 thorpej pci_product_id_t wmp_product;
808 1.1 thorpej const char *wmp_name;
809 1.43 thorpej wm_chip_type wmp_type;
810 1.292 msaitoh uint32_t wmp_flags;
811 1.311 msaitoh #define WMP_F_UNKNOWN WM_MEDIATYPE_UNKNOWN
812 1.311 msaitoh #define WMP_F_FIBER WM_MEDIATYPE_FIBER
813 1.311 msaitoh #define WMP_F_COPPER WM_MEDIATYPE_COPPER
814 1.311 msaitoh #define WMP_F_SERDES WM_MEDIATYPE_SERDES
815 1.292 msaitoh #define WMP_MEDIATYPE(x) ((x) & 0x03)
816 1.1 thorpej } wm_products[] = {
817 1.1 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542,
818 1.1 thorpej "Intel i82542 1000BASE-X Ethernet",
819 1.291 msaitoh WM_T_82542_2_1, WMP_F_FIBER },
820 1.1 thorpej
821 1.11 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER,
822 1.11 thorpej "Intel i82543GC 1000BASE-X Ethernet",
823 1.291 msaitoh WM_T_82543, WMP_F_FIBER },
824 1.1 thorpej
825 1.11 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER,
826 1.11 thorpej "Intel i82543GC 1000BASE-T Ethernet",
827 1.291 msaitoh WM_T_82543, WMP_F_COPPER },
828 1.1 thorpej
829 1.11 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER,
830 1.11 thorpej "Intel i82544EI 1000BASE-T Ethernet",
831 1.291 msaitoh WM_T_82544, WMP_F_COPPER },
832 1.1 thorpej
833 1.11 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER,
834 1.11 thorpej "Intel i82544EI 1000BASE-X Ethernet",
835 1.291 msaitoh WM_T_82544, WMP_F_FIBER },
836 1.1 thorpej
837 1.11 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER,
838 1.1 thorpej "Intel i82544GC 1000BASE-T Ethernet",
839 1.291 msaitoh WM_T_82544, WMP_F_COPPER },
840 1.1 thorpej
841 1.11 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM,
842 1.11 thorpej "Intel i82544GC (LOM) 1000BASE-T Ethernet",
843 1.291 msaitoh WM_T_82544, WMP_F_COPPER },
844 1.1 thorpej
845 1.17 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM,
846 1.17 thorpej "Intel i82540EM 1000BASE-T Ethernet",
847 1.291 msaitoh WM_T_82540, WMP_F_COPPER },
848 1.34 kent
849 1.55 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM,
850 1.55 thorpej "Intel i82540EM (LOM) 1000BASE-T Ethernet",
851 1.291 msaitoh WM_T_82540, WMP_F_COPPER },
852 1.55 thorpej
853 1.34 kent { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM,
854 1.34 kent "Intel i82540EP 1000BASE-T Ethernet",
855 1.291 msaitoh WM_T_82540, WMP_F_COPPER },
856 1.34 kent
857 1.34 kent { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP,
858 1.34 kent "Intel i82540EP 1000BASE-T Ethernet",
859 1.291 msaitoh WM_T_82540, WMP_F_COPPER },
860 1.33 kent
861 1.33 kent { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP,
862 1.33 kent "Intel i82540EP 1000BASE-T Ethernet",
863 1.291 msaitoh WM_T_82540, WMP_F_COPPER },
864 1.17 thorpej
865 1.17 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER,
866 1.17 thorpej "Intel i82545EM 1000BASE-T Ethernet",
867 1.291 msaitoh WM_T_82545, WMP_F_COPPER },
868 1.17 thorpej
869 1.55 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER,
870 1.55 thorpej "Intel i82545GM 1000BASE-T Ethernet",
871 1.291 msaitoh WM_T_82545_3, WMP_F_COPPER },
872 1.55 thorpej
873 1.55 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER,
874 1.55 thorpej "Intel i82545GM 1000BASE-X Ethernet",
875 1.291 msaitoh WM_T_82545_3, WMP_F_FIBER },
876 1.279 msaitoh
877 1.55 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES,
878 1.55 thorpej "Intel i82545GM Gigabit Ethernet (SERDES)",
879 1.55 thorpej WM_T_82545_3, WMP_F_SERDES },
880 1.279 msaitoh
881 1.17 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER,
882 1.39 thorpej "Intel i82546EB 1000BASE-T Ethernet",
883 1.291 msaitoh WM_T_82546, WMP_F_COPPER },
884 1.39 thorpej
885 1.198 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD,
886 1.17 thorpej "Intel i82546EB 1000BASE-T Ethernet",
887 1.291 msaitoh WM_T_82546, WMP_F_COPPER },
888 1.17 thorpej
889 1.17 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER,
890 1.17 thorpej "Intel i82545EM 1000BASE-X Ethernet",
891 1.291 msaitoh WM_T_82545, WMP_F_FIBER },
892 1.17 thorpej
893 1.17 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER,
894 1.17 thorpej "Intel i82546EB 1000BASE-X Ethernet",
895 1.291 msaitoh WM_T_82546, WMP_F_FIBER },
896 1.17 thorpej
897 1.55 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER,
898 1.55 thorpej "Intel i82546GB 1000BASE-T Ethernet",
899 1.291 msaitoh WM_T_82546_3, WMP_F_COPPER },
900 1.55 thorpej
901 1.55 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER,
902 1.55 thorpej "Intel i82546GB 1000BASE-X Ethernet",
903 1.291 msaitoh WM_T_82546_3, WMP_F_FIBER },
904 1.279 msaitoh
905 1.55 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES,
906 1.55 thorpej "Intel i82546GB Gigabit Ethernet (SERDES)",
907 1.55 thorpej WM_T_82546_3, WMP_F_SERDES },
908 1.279 msaitoh
909 1.127 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
910 1.127 bouyer "i82546GB quad-port Gigabit Ethernet",
911 1.291 msaitoh WM_T_82546_3, WMP_F_COPPER },
912 1.127 bouyer
913 1.127 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
914 1.127 bouyer "i82546GB quad-port Gigabit Ethernet (KSP3)",
915 1.291 msaitoh WM_T_82546_3, WMP_F_COPPER },
916 1.127 bouyer
917 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE,
918 1.116 msaitoh "Intel PRO/1000MT (82546GB)",
919 1.291 msaitoh WM_T_82546_3, WMP_F_COPPER },
920 1.116 msaitoh
921 1.63 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI,
922 1.63 thorpej "Intel i82541EI 1000BASE-T Ethernet",
923 1.291 msaitoh WM_T_82541, WMP_F_COPPER },
924 1.63 thorpej
925 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM,
926 1.116 msaitoh "Intel i82541ER (LOM) 1000BASE-T Ethernet",
927 1.291 msaitoh WM_T_82541, WMP_F_COPPER },
928 1.116 msaitoh
929 1.57 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE,
930 1.57 thorpej "Intel i82541EI Mobile 1000BASE-T Ethernet",
931 1.291 msaitoh WM_T_82541, WMP_F_COPPER },
932 1.57 thorpej
933 1.57 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER,
934 1.57 thorpej "Intel i82541ER 1000BASE-T Ethernet",
935 1.291 msaitoh WM_T_82541_2, WMP_F_COPPER },
936 1.57 thorpej
937 1.57 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI,
938 1.57 thorpej "Intel i82541GI 1000BASE-T Ethernet",
939 1.291 msaitoh WM_T_82541_2, WMP_F_COPPER },
940 1.57 thorpej
941 1.57 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE,
942 1.57 thorpej "Intel i82541GI Mobile 1000BASE-T Ethernet",
943 1.291 msaitoh WM_T_82541_2, WMP_F_COPPER },
944 1.57 thorpej
945 1.101 tron { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI,
946 1.101 tron "Intel i82541PI 1000BASE-T Ethernet",
947 1.291 msaitoh WM_T_82541_2, WMP_F_COPPER },
948 1.101 tron
949 1.57 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI,
950 1.57 thorpej "Intel i82547EI 1000BASE-T Ethernet",
951 1.291 msaitoh WM_T_82547, WMP_F_COPPER },
952 1.57 thorpej
953 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE,
954 1.141 simonb "Intel i82547EI Mobile 1000BASE-T Ethernet",
955 1.291 msaitoh WM_T_82547, WMP_F_COPPER },
956 1.116 msaitoh
957 1.57 thorpej { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI,
958 1.57 thorpej "Intel i82547GI 1000BASE-T Ethernet",
959 1.291 msaitoh WM_T_82547_2, WMP_F_COPPER },
960 1.116 msaitoh
961 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER,
962 1.116 msaitoh "Intel PRO/1000 PT (82571EB)",
963 1.291 msaitoh WM_T_82571, WMP_F_COPPER },
964 1.116 msaitoh
965 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER,
966 1.116 msaitoh "Intel PRO/1000 PF (82571EB)",
967 1.291 msaitoh WM_T_82571, WMP_F_FIBER },
968 1.279 msaitoh
969 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES,
970 1.116 msaitoh "Intel PRO/1000 PB (82571EB)",
971 1.116 msaitoh WM_T_82571, WMP_F_SERDES },
972 1.279 msaitoh
973 1.127 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
974 1.127 bouyer "Intel PRO/1000 QT (82571EB)",
975 1.291 msaitoh WM_T_82571, WMP_F_COPPER },
976 1.127 bouyer
977 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
978 1.299 msaitoh "Intel PRO/1000 PT Quad Port Server Adapter",
979 1.299 msaitoh WM_T_82571, WMP_F_COPPER, },
980 1.299 msaitoh
981 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER,
982 1.299 msaitoh "Intel Gigabit PT Quad Port Server ExpressModule",
983 1.299 msaitoh WM_T_82571, WMP_F_COPPER, },
984 1.299 msaitoh
985 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES,
986 1.299 msaitoh "Intel 82571EB Dual Gigabit Ethernet (SERDES)",
987 1.299 msaitoh WM_T_82571, WMP_F_SERDES, },
988 1.299 msaitoh
989 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES,
990 1.299 msaitoh "Intel 82571EB Quad Gigabit Ethernet (SERDES)",
991 1.299 msaitoh WM_T_82571, WMP_F_SERDES, },
992 1.299 msaitoh
993 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER,
994 1.299 msaitoh "Intel 82571EB Quad 1000baseX Ethernet",
995 1.299 msaitoh WM_T_82571, WMP_F_FIBER, },
996 1.299 msaitoh
997 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER,
998 1.116 msaitoh "Intel i82572EI 1000baseT Ethernet",
999 1.291 msaitoh WM_T_82572, WMP_F_COPPER },
1000 1.116 msaitoh
1001 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER,
1002 1.116 msaitoh "Intel i82572EI 1000baseX Ethernet",
1003 1.291 msaitoh WM_T_82572, WMP_F_FIBER },
1004 1.279 msaitoh
1005 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES,
1006 1.116 msaitoh "Intel i82572EI Gigabit Ethernet (SERDES)",
1007 1.116 msaitoh WM_T_82572, WMP_F_SERDES },
1008 1.116 msaitoh
1009 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI,
1010 1.116 msaitoh "Intel i82572EI 1000baseT Ethernet",
1011 1.291 msaitoh WM_T_82572, WMP_F_COPPER },
1012 1.116 msaitoh
1013 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E,
1014 1.116 msaitoh "Intel i82573E",
1015 1.291 msaitoh WM_T_82573, WMP_F_COPPER },
1016 1.116 msaitoh
1017 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT,
1018 1.117 msaitoh "Intel i82573E IAMT",
1019 1.291 msaitoh WM_T_82573, WMP_F_COPPER },
1020 1.116 msaitoh
1021 1.116 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L,
1022 1.116 msaitoh "Intel i82573L Gigabit Ethernet",
1023 1.291 msaitoh WM_T_82573, WMP_F_COPPER },
1024 1.116 msaitoh
1025 1.165 sborrill { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L,
1026 1.165 sborrill "Intel i82574L",
1027 1.291 msaitoh WM_T_82574, WMP_F_COPPER },
1028 1.165 sborrill
1029 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA,
1030 1.299 msaitoh "Intel i82574L",
1031 1.299 msaitoh WM_T_82574, WMP_F_COPPER },
1032 1.299 msaitoh
1033 1.185 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V,
1034 1.185 msaitoh "Intel i82583V",
1035 1.291 msaitoh WM_T_82583, WMP_F_COPPER },
1036 1.185 msaitoh
1037 1.127 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
1038 1.127 bouyer "i80003 dual 1000baseT Ethernet",
1039 1.291 msaitoh WM_T_80003, WMP_F_COPPER },
1040 1.127 bouyer
1041 1.127 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
1042 1.127 bouyer "i80003 dual 1000baseX Ethernet",
1043 1.291 msaitoh WM_T_80003, WMP_F_COPPER },
1044 1.279 msaitoh
1045 1.127 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
1046 1.127 bouyer "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
1047 1.127 bouyer WM_T_80003, WMP_F_SERDES },
1048 1.127 bouyer
1049 1.127 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
1050 1.127 bouyer "Intel i80003 1000baseT Ethernet",
1051 1.291 msaitoh WM_T_80003, WMP_F_COPPER },
1052 1.279 msaitoh
1053 1.127 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
1054 1.127 bouyer "Intel i80003 Gigabit Ethernet (SERDES)",
1055 1.127 bouyer WM_T_80003, WMP_F_SERDES },
1056 1.279 msaitoh
1057 1.139 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT,
1058 1.139 bouyer "Intel i82801H (M_AMT) LAN Controller",
1059 1.291 msaitoh WM_T_ICH8, WMP_F_COPPER },
1060 1.139 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT,
1061 1.139 bouyer "Intel i82801H (AMT) LAN Controller",
1062 1.291 msaitoh WM_T_ICH8, WMP_F_COPPER },
1063 1.139 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN,
1064 1.139 bouyer "Intel i82801H LAN Controller",
1065 1.291 msaitoh WM_T_ICH8, WMP_F_COPPER },
1066 1.139 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN,
1067 1.139 bouyer "Intel i82801H (IFE) LAN Controller",
1068 1.291 msaitoh WM_T_ICH8, WMP_F_COPPER },
1069 1.139 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN,
1070 1.139 bouyer "Intel i82801H (M) LAN Controller",
1071 1.291 msaitoh WM_T_ICH8, WMP_F_COPPER },
1072 1.139 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT,
1073 1.139 bouyer "Intel i82801H IFE (GT) LAN Controller",
1074 1.291 msaitoh WM_T_ICH8, WMP_F_COPPER },
1075 1.139 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G,
1076 1.139 bouyer "Intel i82801H IFE (G) LAN Controller",
1077 1.291 msaitoh WM_T_ICH8, WMP_F_COPPER },
1078 1.144 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT,
1079 1.144 msaitoh "82801I (AMT) LAN Controller",
1080 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1081 1.144 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE,
1082 1.144 msaitoh "82801I LAN Controller",
1083 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1084 1.144 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G,
1085 1.144 msaitoh "82801I (G) LAN Controller",
1086 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1087 1.144 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT,
1088 1.144 msaitoh "82801I (GT) LAN Controller",
1089 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1090 1.144 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C,
1091 1.144 msaitoh "82801I (C) LAN Controller",
1092 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1093 1.162 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M,
1094 1.162 bouyer "82801I mobile LAN Controller",
1095 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1096 1.162 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IGP_M_V,
1097 1.162 bouyer "82801I mobile (V) LAN Controller",
1098 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1099 1.162 bouyer { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
1100 1.162 bouyer "82801I mobile (AMT) LAN Controller",
1101 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1102 1.191 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_BM,
1103 1.191 msaitoh "82567LM-4 LAN Controller",
1104 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1105 1.191 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_82567V_3,
1106 1.191 msaitoh "82567V-3 LAN Controller",
1107 1.291 msaitoh WM_T_ICH9, WMP_F_COPPER },
1108 1.191 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LM,
1109 1.191 msaitoh "82567LM-2 LAN Controller",
1110 1.291 msaitoh WM_T_ICH10, WMP_F_COPPER },
1111 1.191 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LF,
1112 1.191 msaitoh "82567LF-2 LAN Controller",
1113 1.291 msaitoh WM_T_ICH10, WMP_F_COPPER },
1114 1.191 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LM,
1115 1.164 markd "82567LM-3 LAN Controller",
1116 1.291 msaitoh WM_T_ICH10, WMP_F_COPPER },
1117 1.191 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LF,
1118 1.167 msaitoh "82567LF-3 LAN Controller",
1119 1.291 msaitoh WM_T_ICH10, WMP_F_COPPER },
1120 1.191 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_V,
1121 1.191 msaitoh "82567V-2 LAN Controller",
1122 1.291 msaitoh WM_T_ICH10, WMP_F_COPPER },
1123 1.221 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_V,
1124 1.221 msaitoh "82567V-3? LAN Controller",
1125 1.291 msaitoh WM_T_ICH10, WMP_F_COPPER },
1126 1.221 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HANKSVILLE,
1127 1.221 msaitoh "HANKSVILLE LAN Controller",
1128 1.291 msaitoh WM_T_ICH10, WMP_F_COPPER },
1129 1.190 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LM,
1130 1.207 msaitoh "PCH LAN (82577LM) Controller",
1131 1.291 msaitoh WM_T_PCH, WMP_F_COPPER },
1132 1.190 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LC,
1133 1.207 msaitoh "PCH LAN (82577LC) Controller",
1134 1.291 msaitoh WM_T_PCH, WMP_F_COPPER },
1135 1.190 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DM,
1136 1.190 msaitoh "PCH LAN (82578DM) Controller",
1137 1.291 msaitoh WM_T_PCH, WMP_F_COPPER },
1138 1.190 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC,
1139 1.190 msaitoh "PCH LAN (82578DC) Controller",
1140 1.291 msaitoh WM_T_PCH, WMP_F_COPPER },
1141 1.221 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM,
1142 1.221 msaitoh "PCH2 LAN (82579LM) Controller",
1143 1.291 msaitoh WM_T_PCH2, WMP_F_COPPER },
1144 1.221 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V,
1145 1.221 msaitoh "PCH2 LAN (82579V) Controller",
1146 1.291 msaitoh WM_T_PCH2, WMP_F_COPPER },
1147 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER,
1148 1.199 msaitoh "82575EB dual-1000baseT Ethernet",
1149 1.291 msaitoh WM_T_82575, WMP_F_COPPER },
1150 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES,
1151 1.199 msaitoh "82575EB dual-1000baseX Ethernet (SERDES)",
1152 1.199 msaitoh WM_T_82575, WMP_F_SERDES },
1153 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER,
1154 1.199 msaitoh "82575GB quad-1000baseT Ethernet",
1155 1.291 msaitoh WM_T_82575, WMP_F_COPPER },
1156 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM,
1157 1.199 msaitoh "82575GB quad-1000baseT Ethernet (PM)",
1158 1.291 msaitoh WM_T_82575, WMP_F_COPPER },
1159 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_COPPER,
1160 1.199 msaitoh "82576 1000BaseT Ethernet",
1161 1.291 msaitoh WM_T_82576, WMP_F_COPPER },
1162 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER,
1163 1.199 msaitoh "82576 1000BaseX Ethernet",
1164 1.291 msaitoh WM_T_82576, WMP_F_FIBER },
1165 1.279 msaitoh
1166 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES,
1167 1.199 msaitoh "82576 gigabit Ethernet (SERDES)",
1168 1.199 msaitoh WM_T_82576, WMP_F_SERDES },
1169 1.279 msaitoh
1170 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER,
1171 1.199 msaitoh "82576 quad-1000BaseT Ethernet",
1172 1.291 msaitoh WM_T_82576, WMP_F_COPPER },
1173 1.299 msaitoh
1174 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2,
1175 1.299 msaitoh "82576 Gigabit ET2 Quad Port Server Adapter",
1176 1.299 msaitoh WM_T_82576, WMP_F_COPPER },
1177 1.299 msaitoh
1178 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS,
1179 1.199 msaitoh "82576 gigabit Ethernet",
1180 1.291 msaitoh WM_T_82576, WMP_F_COPPER },
1181 1.279 msaitoh
1182 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES,
1183 1.199 msaitoh "82576 gigabit Ethernet (SERDES)",
1184 1.199 msaitoh WM_T_82576, WMP_F_SERDES },
1185 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD,
1186 1.199 msaitoh "82576 quad-gigabit Ethernet (SERDES)",
1187 1.199 msaitoh WM_T_82576, WMP_F_SERDES },
1188 1.279 msaitoh
1189 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER,
1190 1.199 msaitoh "82580 1000BaseT Ethernet",
1191 1.291 msaitoh WM_T_82580, WMP_F_COPPER },
1192 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER,
1193 1.199 msaitoh "82580 1000BaseX Ethernet",
1194 1.291 msaitoh WM_T_82580, WMP_F_FIBER },
1195 1.279 msaitoh
1196 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES,
1197 1.199 msaitoh "82580 1000BaseT Ethernet (SERDES)",
1198 1.199 msaitoh WM_T_82580, WMP_F_SERDES },
1199 1.279 msaitoh
1200 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII,
1201 1.199 msaitoh "82580 gigabit Ethernet (SGMII)",
1202 1.291 msaitoh WM_T_82580, WMP_F_COPPER },
1203 1.199 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL,
1204 1.199 msaitoh "82580 dual-1000BaseT Ethernet",
1205 1.291 msaitoh WM_T_82580, WMP_F_COPPER },
1206 1.300 msaitoh
1207 1.221 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER,
1208 1.221 msaitoh "82580 quad-1000BaseX Ethernet",
1209 1.291 msaitoh WM_T_82580, WMP_F_FIBER },
1210 1.300 msaitoh
1211 1.304 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII,
1212 1.304 msaitoh "DH89XXCC Gigabit Ethernet (SGMII)",
1213 1.304 msaitoh WM_T_82580, WMP_F_COPPER },
1214 1.304 msaitoh
1215 1.304 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES,
1216 1.304 msaitoh "DH89XXCC Gigabit Ethernet (SERDES)",
1217 1.304 msaitoh WM_T_82580, WMP_F_SERDES },
1218 1.304 msaitoh
1219 1.304 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE,
1220 1.304 msaitoh "DH89XXCC 1000BASE-KX Ethernet",
1221 1.304 msaitoh WM_T_82580, WMP_F_SERDES },
1222 1.304 msaitoh
1223 1.304 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP,
1224 1.304 msaitoh "DH89XXCC Gigabit Ethernet (SFP)",
1225 1.304 msaitoh WM_T_82580, WMP_F_SERDES },
1226 1.304 msaitoh
1227 1.228 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER,
1228 1.228 msaitoh "I350 Gigabit Network Connection",
1229 1.291 msaitoh WM_T_I350, WMP_F_COPPER },
1230 1.304 msaitoh
1231 1.228 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER,
1232 1.228 msaitoh "I350 Gigabit Fiber Network Connection",
1233 1.291 msaitoh WM_T_I350, WMP_F_FIBER },
1234 1.279 msaitoh
1235 1.228 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES,
1236 1.228 msaitoh "I350 Gigabit Backplane Connection",
1237 1.228 msaitoh WM_T_I350, WMP_F_SERDES },
1238 1.292 msaitoh
1239 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_DA4,
1240 1.299 msaitoh "I350 Quad Port Gigabit Ethernet",
1241 1.299 msaitoh WM_T_I350, WMP_F_SERDES },
1242 1.299 msaitoh
1243 1.228 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII,
1244 1.228 msaitoh "I350 Gigabit Connection",
1245 1.291 msaitoh WM_T_I350, WMP_F_COPPER },
1246 1.292 msaitoh
1247 1.308 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_1000KX,
1248 1.308 msaitoh "I354 Gigabit Ethernet (KX)",
1249 1.308 msaitoh WM_T_I354, WMP_F_SERDES },
1250 1.308 msaitoh
1251 1.265 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_SGMII,
1252 1.308 msaitoh "I354 Gigabit Ethernet (SGMII)",
1253 1.308 msaitoh WM_T_I354, WMP_F_COPPER },
1254 1.308 msaitoh
1255 1.308 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_25GBE,
1256 1.308 msaitoh "I354 Gigabit Ethernet (2.5G)",
1257 1.291 msaitoh WM_T_I354, WMP_F_COPPER },
1258 1.308 msaitoh
1259 1.247 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_T1,
1260 1.247 msaitoh "I210-T1 Ethernet Server Adapter",
1261 1.291 msaitoh WM_T_I210, WMP_F_COPPER },
1262 1.299 msaitoh
1263 1.247 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1,
1264 1.247 msaitoh "I210 Ethernet (Copper OEM)",
1265 1.291 msaitoh WM_T_I210, WMP_F_COPPER },
1266 1.299 msaitoh
1267 1.247 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT,
1268 1.247 msaitoh "I210 Ethernet (Copper IT)",
1269 1.291 msaitoh WM_T_I210, WMP_F_COPPER },
1270 1.299 msaitoh
1271 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_WOF,
1272 1.299 msaitoh "I210 Ethernet (FLASH less)",
1273 1.299 msaitoh WM_T_I210, WMP_F_COPPER },
1274 1.299 msaitoh
1275 1.247 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER,
1276 1.247 msaitoh "I210 Gigabit Ethernet (Fiber)",
1277 1.291 msaitoh WM_T_I210, WMP_F_FIBER },
1278 1.279 msaitoh
1279 1.247 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES,
1280 1.247 msaitoh "I210 Gigabit Ethernet (SERDES)",
1281 1.247 msaitoh WM_T_I210, WMP_F_SERDES },
1282 1.292 msaitoh
1283 1.299 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_WOF,
1284 1.299 msaitoh "I210 Gigabit Ethernet (FLASH less)",
1285 1.299 msaitoh WM_T_I210, WMP_F_SERDES },
1286 1.299 msaitoh
1287 1.247 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII,
1288 1.247 msaitoh "I210 Gigabit Ethernet (SGMII)",
1289 1.292 msaitoh WM_T_I210, WMP_F_COPPER },
1290 1.292 msaitoh
1291 1.247 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER,
1292 1.247 msaitoh "I211 Ethernet (COPPER)",
1293 1.291 msaitoh WM_T_I211, WMP_F_COPPER },
1294 1.249 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V,
1295 1.249 msaitoh "I217 V Ethernet Connection",
1296 1.291 msaitoh WM_T_PCH_LPT, WMP_F_COPPER },
1297 1.249 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM,
1298 1.249 msaitoh "I217 LM Ethernet Connection",
1299 1.291 msaitoh WM_T_PCH_LPT, WMP_F_COPPER },
1300 1.249 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V,
1301 1.249 msaitoh "I218 V Ethernet Connection",
1302 1.291 msaitoh WM_T_PCH_LPT, WMP_F_COPPER },
1303 1.298 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V2,
1304 1.298 msaitoh "I218 V Ethernet Connection",
1305 1.298 msaitoh WM_T_PCH_LPT, WMP_F_COPPER },
1306 1.298 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V3,
1307 1.298 msaitoh "I218 V Ethernet Connection",
1308 1.298 msaitoh WM_T_PCH_LPT, WMP_F_COPPER },
1309 1.249 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM,
1310 1.249 msaitoh "I218 LM Ethernet Connection",
1311 1.291 msaitoh WM_T_PCH_LPT, WMP_F_COPPER },
1312 1.298 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM2,
1313 1.298 msaitoh "I218 LM Ethernet Connection",
1314 1.298 msaitoh WM_T_PCH_LPT, WMP_F_COPPER },
1315 1.298 msaitoh { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3,
1316 1.298 msaitoh "I218 LM Ethernet Connection",
1317 1.298 msaitoh WM_T_PCH_LPT, WMP_F_COPPER },
1318 1.1 thorpej { 0, 0,
1319 1.1 thorpej NULL,
1320 1.1 thorpej 0, 0 },
1321 1.1 thorpej };
1322 1.1 thorpej
1323 1.2 thorpej #ifdef WM_EVENT_COUNTERS
1324 1.75 thorpej static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")];
1325 1.2 thorpej #endif /* WM_EVENT_COUNTERS */
1326 1.2 thorpej
1327 1.280 msaitoh
1328 1.280 msaitoh /*
1329 1.280 msaitoh * Register read/write functions.
1330 1.280 msaitoh * Other than CSR_{READ|WRITE}().
1331 1.280 msaitoh */
1332 1.280 msaitoh
1333 1.53 thorpej #if 0 /* Not currently used */
1334 1.110 perry static inline uint32_t
1335 1.53 thorpej wm_io_read(struct wm_softc *sc, int reg)
1336 1.53 thorpej {
1337 1.53 thorpej
1338 1.53 thorpej bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
1339 1.53 thorpej return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
1340 1.53 thorpej }
1341 1.53 thorpej #endif
1342 1.53 thorpej
1343 1.110 perry static inline void
1344 1.53 thorpej wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
1345 1.53 thorpej {
1346 1.53 thorpej
1347 1.53 thorpej bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
1348 1.53 thorpej bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
1349 1.53 thorpej }
1350 1.53 thorpej
1351 1.110 perry static inline void
1352 1.199 msaitoh wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off,
1353 1.199 msaitoh uint32_t data)
1354 1.199 msaitoh {
1355 1.199 msaitoh uint32_t regval;
1356 1.199 msaitoh int i;
1357 1.199 msaitoh
1358 1.199 msaitoh regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT);
1359 1.199 msaitoh
1360 1.199 msaitoh CSR_WRITE(sc, reg, regval);
1361 1.199 msaitoh
1362 1.199 msaitoh for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) {
1363 1.199 msaitoh delay(5);
1364 1.199 msaitoh if (CSR_READ(sc, reg) & SCTL_CTL_READY)
1365 1.199 msaitoh break;
1366 1.199 msaitoh }
1367 1.199 msaitoh if (i == SCTL_CTL_POLL_TIMEOUT) {
1368 1.280 msaitoh aprint_error("%s: WARNING:"
1369 1.280 msaitoh " i82575 reg 0x%08x setup did not indicate ready\n",
1370 1.199 msaitoh device_xname(sc->sc_dev), reg);
1371 1.199 msaitoh }
1372 1.199 msaitoh }
1373 1.199 msaitoh
1374 1.199 msaitoh static inline void
1375 1.110 perry wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
1376 1.69 thorpej {
1377 1.69 thorpej wa->wa_low = htole32(v & 0xffffffffU);
1378 1.69 thorpej if (sizeof(bus_addr_t) == 8)
1379 1.69 thorpej wa->wa_high = htole32((uint64_t) v >> 32);
1380 1.69 thorpej else
1381 1.69 thorpej wa->wa_high = 0;
1382 1.69 thorpej }
1383 1.69 thorpej
1384 1.280 msaitoh /*
1385 1.280 msaitoh * Device driver interface functions and commonly used functions.
1386 1.280 msaitoh * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
1387 1.280 msaitoh */
1388 1.280 msaitoh
1389 1.280 msaitoh /* Lookup supported device table */
1390 1.1 thorpej static const struct wm_product *
1391 1.1 thorpej wm_lookup(const struct pci_attach_args *pa)
1392 1.1 thorpej {
1393 1.1 thorpej const struct wm_product *wmp;
1394 1.1 thorpej
1395 1.1 thorpej for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
1396 1.1 thorpej if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
1397 1.1 thorpej PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
1398 1.194 msaitoh return wmp;
1399 1.1 thorpej }
1400 1.194 msaitoh return NULL;
1401 1.1 thorpej }
1402 1.1 thorpej
1403 1.280 msaitoh /* The match function (ca_match) */
1404 1.47 thorpej static int
1405 1.160 christos wm_match(device_t parent, cfdata_t cf, void *aux)
1406 1.1 thorpej {
1407 1.1 thorpej struct pci_attach_args *pa = aux;
1408 1.1 thorpej
1409 1.1 thorpej if (wm_lookup(pa) != NULL)
1410 1.194 msaitoh return 1;
1411 1.1 thorpej
1412 1.194 msaitoh return 0;
1413 1.1 thorpej }
1414 1.1 thorpej
1415 1.280 msaitoh /* The attach function (ca_attach) */
1416 1.47 thorpej static void
1417 1.157 dyoung wm_attach(device_t parent, device_t self, void *aux)
1418 1.1 thorpej {
1419 1.157 dyoung struct wm_softc *sc = device_private(self);
1420 1.1 thorpej struct pci_attach_args *pa = aux;
1421 1.182 msaitoh prop_dictionary_t dict;
1422 1.1 thorpej struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1423 1.1 thorpej pci_chipset_tag_t pc = pa->pa_pc;
1424 1.335 msaitoh #ifndef WM_MSI_MSIX
1425 1.1 thorpej pci_intr_handle_t ih;
1426 1.335 msaitoh #else
1427 1.340 knakahar int counts[PCI_INTR_TYPE_SIZE];
1428 1.340 knakahar pci_intr_type_t max_type;
1429 1.335 msaitoh #endif
1430 1.1 thorpej const char *intrstr = NULL;
1431 1.160 christos const char *eetype, *xname;
1432 1.1 thorpej bus_space_tag_t memt;
1433 1.1 thorpej bus_space_handle_t memh;
1434 1.201 msaitoh bus_size_t memsize;
1435 1.1 thorpej int memh_valid;
1436 1.201 msaitoh int i, error;
1437 1.1 thorpej const struct wm_product *wmp;
1438 1.115 thorpej prop_data_t ea;
1439 1.115 thorpej prop_number_t pn;
1440 1.1 thorpej uint8_t enaddr[ETHER_ADDR_LEN];
1441 1.325 msaitoh uint16_t cfg1, cfg2, swdpin, nvmword;
1442 1.1 thorpej pcireg_t preg, memtype;
1443 1.203 msaitoh uint16_t eeprom_data, apme_mask;
1444 1.273 msaitoh bool force_clear_smbi;
1445 1.292 msaitoh uint32_t link_mode;
1446 1.44 thorpej uint32_t reg;
1447 1.268 christos char intrbuf[PCI_INTRSTR_LEN];
1448 1.1 thorpej
1449 1.160 christos sc->sc_dev = self;
1450 1.272 ozaki callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS);
1451 1.272 ozaki sc->sc_stopping = false;
1452 1.1 thorpej
1453 1.292 msaitoh wmp = wm_lookup(pa);
1454 1.292 msaitoh #ifdef DIAGNOSTIC
1455 1.1 thorpej if (wmp == NULL) {
1456 1.1 thorpej printf("\n");
1457 1.1 thorpej panic("wm_attach: impossible");
1458 1.1 thorpej }
1459 1.292 msaitoh #endif
1460 1.292 msaitoh sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags);
1461 1.1 thorpej
1462 1.123 jmcneill sc->sc_pc = pa->pa_pc;
1463 1.123 jmcneill sc->sc_pcitag = pa->pa_tag;
1464 1.123 jmcneill
1465 1.69 thorpej if (pci_dma64_available(pa))
1466 1.69 thorpej sc->sc_dmat = pa->pa_dmat64;
1467 1.69 thorpej else
1468 1.69 thorpej sc->sc_dmat = pa->pa_dmat;
1469 1.1 thorpej
1470 1.304 msaitoh sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id);
1471 1.192 msaitoh sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG));
1472 1.226 drochner pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1);
1473 1.1 thorpej
1474 1.1 thorpej sc->sc_type = wmp->wmp_type;
1475 1.11 thorpej if (sc->sc_type < WM_T_82543) {
1476 1.192 msaitoh if (sc->sc_rev < 2) {
1477 1.160 christos aprint_error_dev(sc->sc_dev,
1478 1.160 christos "i82542 must be at least rev. 2\n");
1479 1.1 thorpej return;
1480 1.1 thorpej }
1481 1.192 msaitoh if (sc->sc_rev < 3)
1482 1.11 thorpej sc->sc_type = WM_T_82542_2_0;
1483 1.1 thorpej }
1484 1.1 thorpej
1485 1.335 msaitoh /*
1486 1.335 msaitoh * Disable MSI for Errata:
1487 1.335 msaitoh * "Message Signaled Interrupt Feature May Corrupt Write Transactions"
1488 1.335 msaitoh *
1489 1.335 msaitoh * 82544: Errata 25
1490 1.335 msaitoh * 82540: Errata 6 (easy to reproduce device timeout)
1491 1.335 msaitoh * 82545: Errata 4 (easy to reproduce device timeout)
1492 1.335 msaitoh * 82546: Errata 26 (easy to reproduce device timeout)
1493 1.335 msaitoh * 82541: Errata 7 (easy to reproduce device timeout)
1494 1.337 msaitoh *
1495 1.337 msaitoh * "Byte Enables 2 and 3 are not set on MSI writes"
1496 1.337 msaitoh *
1497 1.337 msaitoh * 82571 & 82572: Errata 63
1498 1.335 msaitoh */
1499 1.337 msaitoh if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571)
1500 1.337 msaitoh || (sc->sc_type == WM_T_82572))
1501 1.335 msaitoh pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY;
1502 1.335 msaitoh
1503 1.199 msaitoh if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
1504 1.300 msaitoh || (sc->sc_type == WM_T_82580)
1505 1.265 msaitoh || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
1506 1.265 msaitoh || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
1507 1.203 msaitoh sc->sc_flags |= WM_F_NEWQUEUE;
1508 1.199 msaitoh
1509 1.184 msaitoh /* Set device properties (mactype) */
1510 1.182 msaitoh dict = device_properties(sc->sc_dev);
1511 1.182 msaitoh prop_dictionary_set_uint32(dict, "mactype", sc->sc_type);
1512 1.182 msaitoh
1513 1.1 thorpej /*
1514 1.53 thorpej * Map the device. All devices support memory-mapped acccess,
1515 1.53 thorpej * and it is really required for normal operation.
1516 1.1 thorpej */
1517 1.1 thorpej memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
1518 1.1 thorpej switch (memtype) {
1519 1.1 thorpej case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
1520 1.1 thorpej case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
1521 1.1 thorpej memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
1522 1.201 msaitoh memtype, 0, &memt, &memh, NULL, &memsize) == 0);
1523 1.1 thorpej break;
1524 1.1 thorpej default:
1525 1.1 thorpej memh_valid = 0;
1526 1.189 msaitoh break;
1527 1.1 thorpej }
1528 1.1 thorpej
1529 1.1 thorpej if (memh_valid) {
1530 1.1 thorpej sc->sc_st = memt;
1531 1.1 thorpej sc->sc_sh = memh;
1532 1.201 msaitoh sc->sc_ss = memsize;
1533 1.1 thorpej } else {
1534 1.160 christos aprint_error_dev(sc->sc_dev,
1535 1.160 christos "unable to map device registers\n");
1536 1.1 thorpej return;
1537 1.1 thorpej }
1538 1.1 thorpej
1539 1.53 thorpej /*
1540 1.53 thorpej * In addition, i82544 and later support I/O mapped indirect
1541 1.53 thorpej * register access. It is not desirable (nor supported in
1542 1.53 thorpej * this driver) to use it for normal operation, though it is
1543 1.53 thorpej * required to work around bugs in some chip versions.
1544 1.53 thorpej */
1545 1.53 thorpej if (sc->sc_type >= WM_T_82544) {
1546 1.53 thorpej /* First we have to find the I/O BAR. */
1547 1.53 thorpej for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
1548 1.241 msaitoh memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
1549 1.241 msaitoh if (memtype == PCI_MAPREG_TYPE_IO)
1550 1.53 thorpej break;
1551 1.241 msaitoh if (PCI_MAPREG_MEM_TYPE(memtype) ==
1552 1.241 msaitoh PCI_MAPREG_MEM_TYPE_64BIT)
1553 1.241 msaitoh i += 4; /* skip high bits, too */
1554 1.53 thorpej }
1555 1.241 msaitoh if (i < PCI_MAPREG_END) {
1556 1.88 briggs /*
1557 1.218 msaitoh * We found PCI_MAPREG_TYPE_IO. Note that 82580
1558 1.218 msaitoh * (and newer?) chip has no PCI_MAPREG_TYPE_IO.
1559 1.218 msaitoh * It's no problem because newer chips has no this
1560 1.218 msaitoh * bug.
1561 1.218 msaitoh *
1562 1.88 briggs * The i8254x doesn't apparently respond when the
1563 1.88 briggs * I/O BAR is 0, which looks somewhat like it's not
1564 1.88 briggs * been configured.
1565 1.88 briggs */
1566 1.88 briggs preg = pci_conf_read(pc, pa->pa_tag, i);
1567 1.88 briggs if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
1568 1.160 christos aprint_error_dev(sc->sc_dev,
1569 1.160 christos "WARNING: I/O BAR at zero.\n");
1570 1.88 briggs } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
1571 1.53 thorpej 0, &sc->sc_iot, &sc->sc_ioh,
1572 1.212 jakllsch NULL, &sc->sc_ios) == 0) {
1573 1.88 briggs sc->sc_flags |= WM_F_IOH_VALID;
1574 1.88 briggs } else {
1575 1.160 christos aprint_error_dev(sc->sc_dev,
1576 1.160 christos "WARNING: unable to map I/O space\n");
1577 1.88 briggs }
1578 1.88 briggs }
1579 1.88 briggs
1580 1.53 thorpej }
1581 1.53 thorpej
1582 1.11 thorpej /* Enable bus mastering. Disable MWI on the i82542 2.0. */
1583 1.1 thorpej preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1584 1.1 thorpej preg |= PCI_COMMAND_MASTER_ENABLE;
1585 1.11 thorpej if (sc->sc_type < WM_T_82542_2_1)
1586 1.1 thorpej preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
1587 1.1 thorpej pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
1588 1.1 thorpej
1589 1.122 christos /* power up chip */
1590 1.157 dyoung if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
1591 1.122 christos NULL)) && error != EOPNOTSUPP) {
1592 1.160 christos aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
1593 1.122 christos return;
1594 1.1 thorpej }
1595 1.1 thorpej
1596 1.335 msaitoh #ifndef WM_MSI_MSIX
1597 1.1 thorpej /*
1598 1.1 thorpej * Map and establish our interrupt.
1599 1.1 thorpej */
1600 1.1 thorpej if (pci_intr_map(pa, &ih)) {
1601 1.160 christos aprint_error_dev(sc->sc_dev, "unable to map interrupt\n");
1602 1.1 thorpej return;
1603 1.1 thorpej }
1604 1.268 christos intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
1605 1.272 ozaki #ifdef WM_MPSAFE
1606 1.272 ozaki pci_intr_setattr(pc, &ih, PCI_INTR_MPSAFE, true);
1607 1.272 ozaki #endif
1608 1.346 knakahar sc->sc_ihs[0] = pci_intr_establish_xname(pc, ih, IPL_NET,
1609 1.346 knakahar wm_intr_legacy, sc, device_xname(sc->sc_dev));
1610 1.335 msaitoh if (sc->sc_ihs[0] == NULL) {
1611 1.160 christos aprint_error_dev(sc->sc_dev, "unable to establish interrupt");
1612 1.1 thorpej if (intrstr != NULL)
1613 1.181 njoly aprint_error(" at %s", intrstr);
1614 1.181 njoly aprint_error("\n");
1615 1.1 thorpej return;
1616 1.1 thorpej }
1617 1.160 christos aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
1618 1.335 msaitoh sc->sc_nintrs = 1;
1619 1.335 msaitoh #else /* WM_MSI_MSIX */
1620 1.340 knakahar /* Allocation settings */
1621 1.340 knakahar max_type = PCI_INTR_TYPE_MSIX;
1622 1.340 knakahar counts[PCI_INTR_TYPE_MSIX] = WM_MAX_NINTR;
1623 1.340 knakahar counts[PCI_INTR_TYPE_MSI] = 1;
1624 1.340 knakahar counts[PCI_INTR_TYPE_INTX] = 1;
1625 1.340 knakahar
1626 1.340 knakahar alloc_retry:
1627 1.340 knakahar if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) {
1628 1.340 knakahar aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n");
1629 1.340 knakahar return;
1630 1.340 knakahar }
1631 1.340 knakahar
1632 1.340 knakahar if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) {
1633 1.335 msaitoh void *vih;
1634 1.335 msaitoh kcpuset_t *affinity;
1635 1.346 knakahar char intr_xname[INTRDEVNAMEBUF];
1636 1.335 msaitoh
1637 1.335 msaitoh kcpuset_create(&affinity, false);
1638 1.335 msaitoh
1639 1.340 knakahar for (i = 0; i < WM_MSIX_NINTR; i++) {
1640 1.340 knakahar intrstr = pci_intr_string(pc,
1641 1.340 knakahar sc->sc_intrs[msix_matrix[i].intridx], intrbuf,
1642 1.340 knakahar sizeof(intrbuf));
1643 1.335 msaitoh #ifdef WM_MPSAFE
1644 1.340 knakahar pci_intr_setattr(pc,
1645 1.340 knakahar &sc->sc_intrs[msix_matrix[i].intridx],
1646 1.340 knakahar PCI_INTR_MPSAFE, true);
1647 1.340 knakahar #endif
1648 1.346 knakahar memset(intr_xname, 0, sizeof(intr_xname));
1649 1.346 knakahar strlcat(intr_xname, device_xname(sc->sc_dev),
1650 1.346 knakahar sizeof(intr_xname));
1651 1.346 knakahar strlcat(intr_xname, msix_matrix[i].intrname,
1652 1.346 knakahar sizeof(intr_xname));
1653 1.346 knakahar vih = pci_intr_establish_xname(pc,
1654 1.340 knakahar sc->sc_intrs[msix_matrix[i].intridx], IPL_NET,
1655 1.346 knakahar msix_matrix[i].func, sc, intr_xname);
1656 1.340 knakahar if (vih == NULL) {
1657 1.340 knakahar aprint_error_dev(sc->sc_dev,
1658 1.340 knakahar "unable to establish MSI-X(for %s)%s%s\n",
1659 1.340 knakahar msix_matrix[i].intrname,
1660 1.340 knakahar intrstr ? " at " : "",
1661 1.340 knakahar intrstr ? intrstr : "");
1662 1.340 knakahar pci_intr_release(sc->sc_pc, sc->sc_intrs,
1663 1.340 knakahar WM_MSIX_NINTR);
1664 1.340 knakahar kcpuset_destroy(affinity);
1665 1.340 knakahar
1666 1.340 knakahar /* Setup for MSI: Disable MSI-X */
1667 1.340 knakahar max_type = PCI_INTR_TYPE_MSI;
1668 1.340 knakahar counts[PCI_INTR_TYPE_MSI] = 1;
1669 1.340 knakahar counts[PCI_INTR_TYPE_INTX] = 1;
1670 1.340 knakahar goto alloc_retry;
1671 1.340 knakahar }
1672 1.340 knakahar kcpuset_zero(affinity);
1673 1.340 knakahar /* Round-robin affinity */
1674 1.340 knakahar kcpuset_set(affinity, msix_matrix[i].cpuid % ncpu);
1675 1.346 knakahar error = interrupt_distribute(vih, affinity, NULL);
1676 1.340 knakahar if (error == 0) {
1677 1.340 knakahar aprint_normal_dev(sc->sc_dev,
1678 1.345 msaitoh "for %s interrupting at %s affinity to %u\n",
1679 1.345 msaitoh msix_matrix[i].intrname, intrstr,
1680 1.345 msaitoh msix_matrix[i].cpuid % ncpu);
1681 1.340 knakahar } else {
1682 1.340 knakahar aprint_normal_dev(sc->sc_dev,
1683 1.345 msaitoh "for %s interrupting at %s\n",
1684 1.345 msaitoh msix_matrix[i].intrname, intrstr);
1685 1.340 knakahar }
1686 1.340 knakahar sc->sc_ihs[msix_matrix[i].intridx] = vih;
1687 1.335 msaitoh }
1688 1.335 msaitoh
1689 1.340 knakahar sc->sc_nintrs = WM_MSIX_NINTR;
1690 1.335 msaitoh kcpuset_destroy(affinity);
1691 1.340 knakahar } else {
1692 1.340 knakahar /* MSI or INTx */
1693 1.335 msaitoh intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf,
1694 1.335 msaitoh sizeof(intrbuf));
1695 1.335 msaitoh #ifdef WM_MPSAFE
1696 1.335 msaitoh pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true);
1697 1.335 msaitoh #endif
1698 1.346 knakahar sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0],
1699 1.346 knakahar IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev));
1700 1.335 msaitoh if (sc->sc_ihs[0] == NULL) {
1701 1.340 knakahar aprint_error_dev(sc->sc_dev,"unable to establish %s\n",
1702 1.340 knakahar (pci_intr_type(sc->sc_intrs[0])
1703 1.340 knakahar == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx");
1704 1.335 msaitoh pci_intr_release(sc->sc_pc, sc->sc_intrs, 1);
1705 1.340 knakahar switch (pci_intr_type(sc->sc_intrs[0])) {
1706 1.340 knakahar case PCI_INTR_TYPE_MSI:
1707 1.340 knakahar /* The next try is for INTx: Disable MSI */
1708 1.340 knakahar max_type = PCI_INTR_TYPE_INTX;
1709 1.340 knakahar counts[PCI_INTR_TYPE_INTX] = 1;
1710 1.340 knakahar goto alloc_retry;
1711 1.340 knakahar case PCI_INTR_TYPE_INTX:
1712 1.340 knakahar default:
1713 1.340 knakahar return;
1714 1.340 knakahar }
1715 1.335 msaitoh }
1716 1.340 knakahar aprint_normal_dev(sc->sc_dev, "%s at %s\n",
1717 1.340 knakahar (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI)
1718 1.340 knakahar ? "MSI" : "interrupting", intrstr);
1719 1.335 msaitoh
1720 1.335 msaitoh sc->sc_nintrs = 1;
1721 1.335 msaitoh }
1722 1.335 msaitoh #endif /* WM_MSI_MSIX */
1723 1.52 thorpej
1724 1.52 thorpej /*
1725 1.199 msaitoh * Check the function ID (unit number of the chip).
1726 1.199 msaitoh */
1727 1.199 msaitoh if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
1728 1.199 msaitoh || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003)
1729 1.208 msaitoh || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
1730 1.300 msaitoh || (sc->sc_type == WM_T_82580)
1731 1.265 msaitoh || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
1732 1.199 msaitoh sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
1733 1.199 msaitoh >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;
1734 1.199 msaitoh else
1735 1.199 msaitoh sc->sc_funcid = 0;
1736 1.199 msaitoh
1737 1.199 msaitoh /*
1738 1.52 thorpej * Determine a few things about the bus we're connected to.
1739 1.52 thorpej */
1740 1.52 thorpej if (sc->sc_type < WM_T_82543) {
1741 1.52 thorpej /* We don't really know the bus characteristics here. */
1742 1.52 thorpej sc->sc_bus_speed = 33;
1743 1.73 tron } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
1744 1.73 tron /*
1745 1.73 tron * CSA (Communication Streaming Architecture) is about as fast
1746 1.73 tron * a 32-bit 66MHz PCI Bus.
1747 1.73 tron */
1748 1.73 tron sc->sc_flags |= WM_F_CSA;
1749 1.73 tron sc->sc_bus_speed = 66;
1750 1.160 christos aprint_verbose_dev(sc->sc_dev,
1751 1.160 christos "Communication Streaming Architecture\n");
1752 1.78 thorpej if (sc->sc_type == WM_T_82547) {
1753 1.272 ozaki callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS);
1754 1.78 thorpej callout_setfunc(&sc->sc_txfifo_ch,
1755 1.78 thorpej wm_82547_txfifo_stall, sc);
1756 1.160 christos aprint_verbose_dev(sc->sc_dev,
1757 1.160 christos "using 82547 Tx FIFO stall work-around\n");
1758 1.78 thorpej }
1759 1.116 msaitoh } else if (sc->sc_type >= WM_T_82571) {
1760 1.139 bouyer sc->sc_flags |= WM_F_PCIE;
1761 1.167 msaitoh if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
1762 1.190 msaitoh && (sc->sc_type != WM_T_ICH10)
1763 1.221 msaitoh && (sc->sc_type != WM_T_PCH)
1764 1.249 msaitoh && (sc->sc_type != WM_T_PCH2)
1765 1.249 msaitoh && (sc->sc_type != WM_T_PCH_LPT)) {
1766 1.221 msaitoh /* ICH* and PCH* have no PCIe capability registers */
1767 1.199 msaitoh if (pci_get_capability(pa->pa_pc, pa->pa_tag,
1768 1.199 msaitoh PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
1769 1.199 msaitoh NULL) == 0)
1770 1.199 msaitoh aprint_error_dev(sc->sc_dev,
1771 1.199 msaitoh "unable to find PCIe capability\n");
1772 1.199 msaitoh }
1773 1.160 christos aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
1774 1.73 tron } else {
1775 1.52 thorpej reg = CSR_READ(sc, WMREG_STATUS);
1776 1.52 thorpej if (reg & STATUS_BUS64)
1777 1.52 thorpej sc->sc_flags |= WM_F_BUS64;
1778 1.176 msaitoh if ((reg & STATUS_PCIX_MODE) != 0) {
1779 1.54 thorpej pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
1780 1.54 thorpej
1781 1.52 thorpej sc->sc_flags |= WM_F_PCIX;
1782 1.54 thorpej if (pci_get_capability(pa->pa_pc, pa->pa_tag,
1783 1.199 msaitoh PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0)
1784 1.160 christos aprint_error_dev(sc->sc_dev,
1785 1.160 christos "unable to find PCIX capability\n");
1786 1.54 thorpej else if (sc->sc_type != WM_T_82545_3 &&
1787 1.54 thorpej sc->sc_type != WM_T_82546_3) {
1788 1.54 thorpej /*
1789 1.54 thorpej * Work around a problem caused by the BIOS
1790 1.54 thorpej * setting the max memory read byte count
1791 1.54 thorpej * incorrectly.
1792 1.54 thorpej */
1793 1.54 thorpej pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
1794 1.248 msaitoh sc->sc_pcixe_capoff + PCIX_CMD);
1795 1.54 thorpej pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
1796 1.248 msaitoh sc->sc_pcixe_capoff + PCIX_STATUS);
1797 1.54 thorpej
1798 1.54 thorpej bytecnt =
1799 1.248 msaitoh (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >>
1800 1.248 msaitoh PCIX_CMD_BYTECNT_SHIFT;
1801 1.54 thorpej maxb =
1802 1.248 msaitoh (pcix_sts & PCIX_STATUS_MAXB_MASK) >>
1803 1.248 msaitoh PCIX_STATUS_MAXB_SHIFT;
1804 1.54 thorpej if (bytecnt > maxb) {
1805 1.160 christos aprint_verbose_dev(sc->sc_dev,
1806 1.160 christos "resetting PCI-X MMRBC: %d -> %d\n",
1807 1.54 thorpej 512 << bytecnt, 512 << maxb);
1808 1.54 thorpej pcix_cmd = (pcix_cmd &
1809 1.248 msaitoh ~PCIX_CMD_BYTECNT_MASK) |
1810 1.248 msaitoh (maxb << PCIX_CMD_BYTECNT_SHIFT);
1811 1.54 thorpej pci_conf_write(pa->pa_pc, pa->pa_tag,
1812 1.248 msaitoh sc->sc_pcixe_capoff + PCIX_CMD,
1813 1.54 thorpej pcix_cmd);
1814 1.54 thorpej }
1815 1.54 thorpej }
1816 1.54 thorpej }
1817 1.52 thorpej /*
1818 1.52 thorpej * The quad port adapter is special; it has a PCIX-PCIX
1819 1.52 thorpej * bridge on the board, and can run the secondary bus at
1820 1.52 thorpej * a higher speed.
1821 1.52 thorpej */
1822 1.52 thorpej if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
1823 1.52 thorpej sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
1824 1.52 thorpej : 66;
1825 1.52 thorpej } else if (sc->sc_flags & WM_F_PCIX) {
1826 1.62 thorpej switch (reg & STATUS_PCIXSPD_MASK) {
1827 1.52 thorpej case STATUS_PCIXSPD_50_66:
1828 1.52 thorpej sc->sc_bus_speed = 66;
1829 1.52 thorpej break;
1830 1.52 thorpej case STATUS_PCIXSPD_66_100:
1831 1.52 thorpej sc->sc_bus_speed = 100;
1832 1.52 thorpej break;
1833 1.52 thorpej case STATUS_PCIXSPD_100_133:
1834 1.52 thorpej sc->sc_bus_speed = 133;
1835 1.52 thorpej break;
1836 1.52 thorpej default:
1837 1.160 christos aprint_error_dev(sc->sc_dev,
1838 1.158 cegger "unknown PCIXSPD %d; assuming 66MHz\n",
1839 1.62 thorpej reg & STATUS_PCIXSPD_MASK);
1840 1.52 thorpej sc->sc_bus_speed = 66;
1841 1.189 msaitoh break;
1842 1.52 thorpej }
1843 1.52 thorpej } else
1844 1.52 thorpej sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
1845 1.160 christos aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n",
1846 1.52 thorpej (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
1847 1.52 thorpej (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
1848 1.52 thorpej }
1849 1.1 thorpej
1850 1.1 thorpej /*
1851 1.1 thorpej * Allocate the control data structures, and create and load the
1852 1.1 thorpej * DMA map for it.
1853 1.69 thorpej *
1854 1.69 thorpej * NOTE: All Tx descriptors must be in the same 4G segment of
1855 1.69 thorpej * memory. So must Rx descriptors. We simplify by allocating
1856 1.69 thorpej * both sets within the same 4G segment.
1857 1.1 thorpej */
1858 1.75 thorpej WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ?
1859 1.75 thorpej WM_NTXDESC_82542 : WM_NTXDESC_82544;
1860 1.201 msaitoh sc->sc_cd_size = sc->sc_type < WM_T_82544 ?
1861 1.75 thorpej sizeof(struct wm_control_data_82542) :
1862 1.75 thorpej sizeof(struct wm_control_data_82544);
1863 1.201 msaitoh if ((error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_cd_size, PAGE_SIZE,
1864 1.201 msaitoh (bus_size_t) 0x100000000ULL, &sc->sc_cd_seg, 1,
1865 1.201 msaitoh &sc->sc_cd_rseg, 0)) != 0) {
1866 1.160 christos aprint_error_dev(sc->sc_dev,
1867 1.158 cegger "unable to allocate control data, error = %d\n",
1868 1.158 cegger error);
1869 1.1 thorpej goto fail_0;
1870 1.1 thorpej }
1871 1.1 thorpej
1872 1.201 msaitoh if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cd_seg,
1873 1.201 msaitoh sc->sc_cd_rseg, sc->sc_cd_size,
1874 1.194 msaitoh (void **)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) {
1875 1.160 christos aprint_error_dev(sc->sc_dev,
1876 1.160 christos "unable to map control data, error = %d\n", error);
1877 1.1 thorpej goto fail_1;
1878 1.1 thorpej }
1879 1.1 thorpej
1880 1.201 msaitoh if ((error = bus_dmamap_create(sc->sc_dmat, sc->sc_cd_size, 1,
1881 1.201 msaitoh sc->sc_cd_size, 0, 0, &sc->sc_cddmamap)) != 0) {
1882 1.160 christos aprint_error_dev(sc->sc_dev,
1883 1.160 christos "unable to create control data DMA map, error = %d\n",
1884 1.160 christos error);
1885 1.1 thorpej goto fail_2;
1886 1.1 thorpej }
1887 1.1 thorpej
1888 1.1 thorpej if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
1889 1.201 msaitoh sc->sc_control_data, sc->sc_cd_size, NULL, 0)) != 0) {
1890 1.160 christos aprint_error_dev(sc->sc_dev,
1891 1.158 cegger "unable to load control data DMA map, error = %d\n",
1892 1.158 cegger error);
1893 1.1 thorpej goto fail_3;
1894 1.1 thorpej }
1895 1.1 thorpej
1896 1.281 msaitoh /* Create the transmit buffer DMA maps. */
1897 1.74 tron WM_TXQUEUELEN(sc) =
1898 1.74 tron (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
1899 1.74 tron WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
1900 1.74 tron for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
1901 1.82 thorpej if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
1902 1.194 msaitoh WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
1903 1.194 msaitoh &sc->sc_txsoft[i].txs_dmamap)) != 0) {
1904 1.160 christos aprint_error_dev(sc->sc_dev,
1905 1.160 christos "unable to create Tx DMA map %d, error = %d\n",
1906 1.160 christos i, error);
1907 1.1 thorpej goto fail_4;
1908 1.1 thorpej }
1909 1.1 thorpej }
1910 1.1 thorpej
1911 1.281 msaitoh /* Create the receive buffer DMA maps. */
1912 1.1 thorpej for (i = 0; i < WM_NRXDESC; i++) {
1913 1.1 thorpej if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
1914 1.194 msaitoh MCLBYTES, 0, 0,
1915 1.194 msaitoh &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
1916 1.160 christos aprint_error_dev(sc->sc_dev,
1917 1.160 christos "unable to create Rx DMA map %d error = %d\n",
1918 1.160 christos i, error);
1919 1.1 thorpej goto fail_5;
1920 1.1 thorpej }
1921 1.1 thorpej sc->sc_rxsoft[i].rxs_mbuf = NULL;
1922 1.1 thorpej }
1923 1.1 thorpej
1924 1.127 bouyer /* clear interesting stat counters */
1925 1.127 bouyer CSR_READ(sc, WMREG_COLC);
1926 1.127 bouyer CSR_READ(sc, WMREG_RXERRC);
1927 1.127 bouyer
1928 1.221 msaitoh /* get PHY control from SMBus to PCIe */
1929 1.249 msaitoh if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
1930 1.249 msaitoh || (sc->sc_type == WM_T_PCH_LPT))
1931 1.221 msaitoh wm_smbustopci(sc);
1932 1.221 msaitoh
1933 1.281 msaitoh /* Reset the chip to a known state. */
1934 1.1 thorpej wm_reset(sc);
1935 1.1 thorpej
1936 1.281 msaitoh /* Get some information about the EEPROM. */
1937 1.185 msaitoh switch (sc->sc_type) {
1938 1.185 msaitoh case WM_T_82542_2_0:
1939 1.185 msaitoh case WM_T_82542_2_1:
1940 1.185 msaitoh case WM_T_82543:
1941 1.185 msaitoh case WM_T_82544:
1942 1.185 msaitoh /* Microwire */
1943 1.294 msaitoh sc->sc_nvm_wordsize = 64;
1944 1.294 msaitoh sc->sc_nvm_addrbits = 6;
1945 1.185 msaitoh break;
1946 1.185 msaitoh case WM_T_82540:
1947 1.185 msaitoh case WM_T_82545:
1948 1.185 msaitoh case WM_T_82545_3:
1949 1.185 msaitoh case WM_T_82546:
1950 1.185 msaitoh case WM_T_82546_3:
1951 1.185 msaitoh /* Microwire */
1952 1.185 msaitoh reg = CSR_READ(sc, WMREG_EECD);
1953 1.294 msaitoh if (reg & EECD_EE_SIZE) {
1954 1.294 msaitoh sc->sc_nvm_wordsize = 256;
1955 1.294 msaitoh sc->sc_nvm_addrbits = 8;
1956 1.294 msaitoh } else {
1957 1.294 msaitoh sc->sc_nvm_wordsize = 64;
1958 1.294 msaitoh sc->sc_nvm_addrbits = 6;
1959 1.294 msaitoh }
1960 1.275 msaitoh sc->sc_flags |= WM_F_LOCK_EECD;
1961 1.185 msaitoh break;
1962 1.185 msaitoh case WM_T_82541:
1963 1.185 msaitoh case WM_T_82541_2:
1964 1.185 msaitoh case WM_T_82547:
1965 1.185 msaitoh case WM_T_82547_2:
1966 1.313 msaitoh sc->sc_flags |= WM_F_LOCK_EECD;
1967 1.185 msaitoh reg = CSR_READ(sc, WMREG_EECD);
1968 1.185 msaitoh if (reg & EECD_EE_TYPE) {
1969 1.185 msaitoh /* SPI */
1970 1.294 msaitoh sc->sc_flags |= WM_F_EEPROM_SPI;
1971 1.294 msaitoh wm_nvm_set_addrbits_size_eecd(sc);
1972 1.294 msaitoh } else {
1973 1.185 msaitoh /* Microwire */
1974 1.294 msaitoh if ((reg & EECD_EE_ABITS) != 0) {
1975 1.294 msaitoh sc->sc_nvm_wordsize = 256;
1976 1.294 msaitoh sc->sc_nvm_addrbits = 8;
1977 1.294 msaitoh } else {
1978 1.294 msaitoh sc->sc_nvm_wordsize = 64;
1979 1.294 msaitoh sc->sc_nvm_addrbits = 6;
1980 1.294 msaitoh }
1981 1.294 msaitoh }
1982 1.185 msaitoh break;
1983 1.185 msaitoh case WM_T_82571:
1984 1.185 msaitoh case WM_T_82572:
1985 1.185 msaitoh /* SPI */
1986 1.294 msaitoh sc->sc_flags |= WM_F_EEPROM_SPI;
1987 1.294 msaitoh wm_nvm_set_addrbits_size_eecd(sc);
1988 1.275 msaitoh sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM;
1989 1.185 msaitoh break;
1990 1.185 msaitoh case WM_T_82573:
1991 1.275 msaitoh sc->sc_flags |= WM_F_LOCK_SWSM;
1992 1.273 msaitoh /* FALLTHROUGH */
1993 1.185 msaitoh case WM_T_82574:
1994 1.185 msaitoh case WM_T_82583:
1995 1.294 msaitoh if (wm_nvm_is_onboard_eeprom(sc) == 0) {
1996 1.185 msaitoh sc->sc_flags |= WM_F_EEPROM_FLASH;
1997 1.294 msaitoh sc->sc_nvm_wordsize = 2048;
1998 1.294 msaitoh } else {
1999 1.185 msaitoh /* SPI */
2000 1.294 msaitoh sc->sc_flags |= WM_F_EEPROM_SPI;
2001 1.294 msaitoh wm_nvm_set_addrbits_size_eecd(sc);
2002 1.185 msaitoh }
2003 1.185 msaitoh sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
2004 1.185 msaitoh break;
2005 1.199 msaitoh case WM_T_82575:
2006 1.199 msaitoh case WM_T_82576:
2007 1.199 msaitoh case WM_T_82580:
2008 1.228 msaitoh case WM_T_I350:
2009 1.278 msaitoh case WM_T_I354:
2010 1.185 msaitoh case WM_T_80003:
2011 1.185 msaitoh /* SPI */
2012 1.294 msaitoh sc->sc_flags |= WM_F_EEPROM_SPI;
2013 1.294 msaitoh wm_nvm_set_addrbits_size_eecd(sc);
2014 1.275 msaitoh sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW
2015 1.275 msaitoh | WM_F_LOCK_SWSM;
2016 1.185 msaitoh break;
2017 1.185 msaitoh case WM_T_ICH8:
2018 1.185 msaitoh case WM_T_ICH9:
2019 1.185 msaitoh case WM_T_ICH10:
2020 1.190 msaitoh case WM_T_PCH:
2021 1.221 msaitoh case WM_T_PCH2:
2022 1.249 msaitoh case WM_T_PCH_LPT:
2023 1.185 msaitoh /* FLASH */
2024 1.276 msaitoh sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF;
2025 1.294 msaitoh sc->sc_nvm_wordsize = 2048;
2026 1.139 bouyer memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH);
2027 1.139 bouyer if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
2028 1.336 msaitoh &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) {
2029 1.160 christos aprint_error_dev(sc->sc_dev,
2030 1.160 christos "can't map FLASH registers\n");
2031 1.290 msaitoh goto fail_5;
2032 1.139 bouyer }
2033 1.185 msaitoh reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
2034 1.185 msaitoh sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *
2035 1.139 bouyer ICH_FLASH_SECTOR_SIZE;
2036 1.199 msaitoh sc->sc_ich8_flash_bank_size =
2037 1.199 msaitoh ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
2038 1.139 bouyer sc->sc_ich8_flash_bank_size -=
2039 1.199 msaitoh (reg & ICH_GFPREG_BASE_MASK);
2040 1.139 bouyer sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
2041 1.139 bouyer sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
2042 1.185 msaitoh break;
2043 1.247 msaitoh case WM_T_I210:
2044 1.247 msaitoh case WM_T_I211:
2045 1.321 msaitoh if (wm_nvm_get_flash_presence_i210(sc)) {
2046 1.321 msaitoh wm_nvm_set_addrbits_size_eecd(sc);
2047 1.321 msaitoh sc->sc_flags |= WM_F_EEPROM_FLASH_HW;
2048 1.321 msaitoh sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW;
2049 1.321 msaitoh } else {
2050 1.321 msaitoh sc->sc_nvm_wordsize = INVM_SIZE;
2051 1.321 msaitoh sc->sc_flags |= WM_F_EEPROM_INVM;
2052 1.343 msaitoh sc->sc_flags |= WM_F_LOCK_SWFW;
2053 1.321 msaitoh }
2054 1.247 msaitoh break;
2055 1.185 msaitoh default:
2056 1.185 msaitoh break;
2057 1.44 thorpej }
2058 1.112 gavan
2059 1.273 msaitoh /* Ensure the SMBI bit is clear before first NVM or PHY access */
2060 1.273 msaitoh switch (sc->sc_type) {
2061 1.273 msaitoh case WM_T_82571:
2062 1.273 msaitoh case WM_T_82572:
2063 1.273 msaitoh reg = CSR_READ(sc, WMREG_SWSM2);
2064 1.310 msaitoh if ((reg & SWSM2_LOCK) == 0) {
2065 1.273 msaitoh CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);
2066 1.273 msaitoh force_clear_smbi = true;
2067 1.273 msaitoh } else
2068 1.273 msaitoh force_clear_smbi = false;
2069 1.273 msaitoh break;
2070 1.284 msaitoh case WM_T_82573:
2071 1.284 msaitoh case WM_T_82574:
2072 1.284 msaitoh case WM_T_82583:
2073 1.284 msaitoh force_clear_smbi = true;
2074 1.284 msaitoh break;
2075 1.273 msaitoh default:
2076 1.284 msaitoh force_clear_smbi = false;
2077 1.273 msaitoh break;
2078 1.273 msaitoh }
2079 1.273 msaitoh if (force_clear_smbi) {
2080 1.273 msaitoh reg = CSR_READ(sc, WMREG_SWSM);
2081 1.284 msaitoh if ((reg & SWSM_SMBI) != 0)
2082 1.273 msaitoh aprint_error_dev(sc->sc_dev,
2083 1.273 msaitoh "Please update the Bootagent\n");
2084 1.273 msaitoh CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI);
2085 1.273 msaitoh }
2086 1.273 msaitoh
2087 1.112 gavan /*
2088 1.112 gavan * Defer printing the EEPROM type until after verifying the checksum
2089 1.112 gavan * This allows the EEPROM type to be printed correctly in the case
2090 1.112 gavan * that no EEPROM is attached.
2091 1.112 gavan */
2092 1.185 msaitoh /*
2093 1.185 msaitoh * Validate the EEPROM checksum. If the checksum fails, flag
2094 1.185 msaitoh * this for later, so we can fail future reads from the EEPROM.
2095 1.185 msaitoh */
2096 1.280 msaitoh if (wm_nvm_validate_checksum(sc)) {
2097 1.169 msaitoh /*
2098 1.185 msaitoh * Read twice again because some PCI-e parts fail the
2099 1.185 msaitoh * first check due to the link being in sleep state.
2100 1.169 msaitoh */
2101 1.280 msaitoh if (wm_nvm_validate_checksum(sc))
2102 1.185 msaitoh sc->sc_flags |= WM_F_EEPROM_INVALID;
2103 1.169 msaitoh }
2104 1.185 msaitoh
2105 1.184 msaitoh /* Set device properties (macflags) */
2106 1.183 msaitoh prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags);
2107 1.112 gavan
2108 1.113 gavan if (sc->sc_flags & WM_F_EEPROM_INVALID)
2109 1.328 msaitoh aprint_verbose_dev(sc->sc_dev, "No EEPROM");
2110 1.294 msaitoh else {
2111 1.294 msaitoh aprint_verbose_dev(sc->sc_dev, "%u words ",
2112 1.294 msaitoh sc->sc_nvm_wordsize);
2113 1.321 msaitoh if (sc->sc_flags & WM_F_EEPROM_INVM)
2114 1.328 msaitoh aprint_verbose("iNVM");
2115 1.321 msaitoh else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW)
2116 1.328 msaitoh aprint_verbose("FLASH(HW)");
2117 1.321 msaitoh else if (sc->sc_flags & WM_F_EEPROM_FLASH)
2118 1.328 msaitoh aprint_verbose("FLASH");
2119 1.321 msaitoh else {
2120 1.294 msaitoh if (sc->sc_flags & WM_F_EEPROM_SPI)
2121 1.294 msaitoh eetype = "SPI";
2122 1.294 msaitoh else
2123 1.294 msaitoh eetype = "MicroWire";
2124 1.328 msaitoh aprint_verbose("(%d address bits) %s EEPROM",
2125 1.294 msaitoh sc->sc_nvm_addrbits, eetype);
2126 1.294 msaitoh }
2127 1.112 gavan }
2128 1.328 msaitoh wm_nvm_version(sc);
2129 1.328 msaitoh aprint_verbose("\n");
2130 1.112 gavan
2131 1.329 msaitoh /* Check for I21[01] PLL workaround */
2132 1.329 msaitoh if (sc->sc_type == WM_T_I210)
2133 1.329 msaitoh sc->sc_flags |= WM_F_PLL_WA_I210;
2134 1.329 msaitoh if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) {
2135 1.329 msaitoh /* NVM image release 3.25 has a workaround */
2136 1.344 msaitoh if ((sc->sc_nvm_ver_major < 3)
2137 1.329 msaitoh || ((sc->sc_nvm_ver_major == 3)
2138 1.344 msaitoh && (sc->sc_nvm_ver_minor < 25))) {
2139 1.329 msaitoh aprint_verbose_dev(sc->sc_dev,
2140 1.329 msaitoh "ROM image version %d.%d is older than 3.25\n",
2141 1.329 msaitoh sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor);
2142 1.329 msaitoh sc->sc_flags |= WM_F_PLL_WA_I210;
2143 1.329 msaitoh }
2144 1.329 msaitoh }
2145 1.329 msaitoh if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
2146 1.329 msaitoh wm_pll_workaround_i210(sc);
2147 1.329 msaitoh
2148 1.261 msaitoh switch (sc->sc_type) {
2149 1.261 msaitoh case WM_T_82571:
2150 1.261 msaitoh case WM_T_82572:
2151 1.261 msaitoh case WM_T_82573:
2152 1.261 msaitoh case WM_T_82574:
2153 1.261 msaitoh case WM_T_82583:
2154 1.261 msaitoh case WM_T_80003:
2155 1.261 msaitoh case WM_T_ICH8:
2156 1.261 msaitoh case WM_T_ICH9:
2157 1.261 msaitoh case WM_T_ICH10:
2158 1.261 msaitoh case WM_T_PCH:
2159 1.261 msaitoh case WM_T_PCH2:
2160 1.261 msaitoh case WM_T_PCH_LPT:
2161 1.263 msaitoh if (wm_check_mng_mode(sc) != 0)
2162 1.261 msaitoh wm_get_hw_control(sc);
2163 1.261 msaitoh break;
2164 1.261 msaitoh default:
2165 1.261 msaitoh break;
2166 1.261 msaitoh }
2167 1.261 msaitoh wm_get_wakeup(sc);
2168 1.113 gavan /*
2169 1.113 gavan * Read the Ethernet address from the EEPROM, if not first found
2170 1.113 gavan * in device properties.
2171 1.113 gavan */
2172 1.195 martin ea = prop_dictionary_get(dict, "mac-address");
2173 1.115 thorpej if (ea != NULL) {
2174 1.115 thorpej KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
2175 1.115 thorpej KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
2176 1.115 thorpej memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
2177 1.115 thorpej } else {
2178 1.210 msaitoh if (wm_read_mac_addr(sc, enaddr) != 0) {
2179 1.160 christos aprint_error_dev(sc->sc_dev,
2180 1.160 christos "unable to read Ethernet address\n");
2181 1.290 msaitoh goto fail_5;
2182 1.210 msaitoh }
2183 1.17 thorpej }
2184 1.17 thorpej
2185 1.160 christos aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
2186 1.1 thorpej ether_sprintf(enaddr));
2187 1.1 thorpej
2188 1.1 thorpej /*
2189 1.1 thorpej * Read the config info from the EEPROM, and set up various
2190 1.1 thorpej * bits in the control registers based on their contents.
2191 1.1 thorpej */
2192 1.182 msaitoh pn = prop_dictionary_get(dict, "i82543-cfg1");
2193 1.115 thorpej if (pn != NULL) {
2194 1.115 thorpej KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
2195 1.115 thorpej cfg1 = (uint16_t) prop_number_integer_value(pn);
2196 1.115 thorpej } else {
2197 1.293 msaitoh if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {
2198 1.160 christos aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
2199 1.290 msaitoh goto fail_5;
2200 1.113 gavan }
2201 1.51 thorpej }
2202 1.115 thorpej
2203 1.182 msaitoh pn = prop_dictionary_get(dict, "i82543-cfg2");
2204 1.115 thorpej if (pn != NULL) {
2205 1.115 thorpej KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
2206 1.115 thorpej cfg2 = (uint16_t) prop_number_integer_value(pn);
2207 1.115 thorpej } else {
2208 1.293 msaitoh if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) {
2209 1.160 christos aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
2210 1.290 msaitoh goto fail_5;
2211 1.113 gavan }
2212 1.51 thorpej }
2213 1.115 thorpej
2214 1.203 msaitoh /* check for WM_F_WOL */
2215 1.203 msaitoh switch (sc->sc_type) {
2216 1.203 msaitoh case WM_T_82542_2_0:
2217 1.203 msaitoh case WM_T_82542_2_1:
2218 1.203 msaitoh case WM_T_82543:
2219 1.203 msaitoh /* dummy? */
2220 1.203 msaitoh eeprom_data = 0;
2221 1.293 msaitoh apme_mask = NVM_CFG3_APME;
2222 1.203 msaitoh break;
2223 1.203 msaitoh case WM_T_82544:
2224 1.293 msaitoh apme_mask = NVM_CFG2_82544_APM_EN;
2225 1.203 msaitoh eeprom_data = cfg2;
2226 1.203 msaitoh break;
2227 1.203 msaitoh case WM_T_82546:
2228 1.203 msaitoh case WM_T_82546_3:
2229 1.203 msaitoh case WM_T_82571:
2230 1.203 msaitoh case WM_T_82572:
2231 1.203 msaitoh case WM_T_82573:
2232 1.203 msaitoh case WM_T_82574:
2233 1.203 msaitoh case WM_T_82583:
2234 1.203 msaitoh case WM_T_80003:
2235 1.203 msaitoh default:
2236 1.293 msaitoh apme_mask = NVM_CFG3_APME;
2237 1.293 msaitoh wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB
2238 1.293 msaitoh : NVM_OFF_CFG3_PORTA, 1, &eeprom_data);
2239 1.203 msaitoh break;
2240 1.203 msaitoh case WM_T_82575:
2241 1.203 msaitoh case WM_T_82576:
2242 1.203 msaitoh case WM_T_82580:
2243 1.228 msaitoh case WM_T_I350:
2244 1.265 msaitoh case WM_T_I354: /* XXX ok? */
2245 1.203 msaitoh case WM_T_ICH8:
2246 1.203 msaitoh case WM_T_ICH9:
2247 1.203 msaitoh case WM_T_ICH10:
2248 1.203 msaitoh case WM_T_PCH:
2249 1.221 msaitoh case WM_T_PCH2:
2250 1.249 msaitoh case WM_T_PCH_LPT:
2251 1.228 msaitoh /* XXX The funcid should be checked on some devices */
2252 1.203 msaitoh apme_mask = WUC_APME;
2253 1.203 msaitoh eeprom_data = CSR_READ(sc, WMREG_WUC);
2254 1.203 msaitoh break;
2255 1.203 msaitoh }
2256 1.203 msaitoh
2257 1.203 msaitoh /* Check for WM_F_WOL flag after the setting of the EEPROM stuff */
2258 1.203 msaitoh if ((eeprom_data & apme_mask) != 0)
2259 1.203 msaitoh sc->sc_flags |= WM_F_WOL;
2260 1.203 msaitoh #ifdef WM_DEBUG
2261 1.203 msaitoh if ((sc->sc_flags & WM_F_WOL) != 0)
2262 1.203 msaitoh printf("WOL\n");
2263 1.203 msaitoh #endif
2264 1.203 msaitoh
2265 1.325 msaitoh if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) {
2266 1.325 msaitoh /* Check NVM for autonegotiation */
2267 1.325 msaitoh if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) {
2268 1.325 msaitoh if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0)
2269 1.325 msaitoh sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO;
2270 1.325 msaitoh }
2271 1.325 msaitoh }
2272 1.325 msaitoh
2273 1.203 msaitoh /*
2274 1.203 msaitoh * XXX need special handling for some multiple port cards
2275 1.203 msaitoh * to disable a paticular port.
2276 1.203 msaitoh */
2277 1.203 msaitoh
2278 1.51 thorpej if (sc->sc_type >= WM_T_82544) {
2279 1.182 msaitoh pn = prop_dictionary_get(dict, "i82543-swdpin");
2280 1.115 thorpej if (pn != NULL) {
2281 1.115 thorpej KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
2282 1.115 thorpej swdpin = (uint16_t) prop_number_integer_value(pn);
2283 1.115 thorpej } else {
2284 1.293 msaitoh if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) {
2285 1.160 christos aprint_error_dev(sc->sc_dev,
2286 1.160 christos "unable to read SWDPIN\n");
2287 1.290 msaitoh goto fail_5;
2288 1.113 gavan }
2289 1.51 thorpej }
2290 1.51 thorpej }
2291 1.1 thorpej
2292 1.293 msaitoh if (cfg1 & NVM_CFG1_ILOS)
2293 1.1 thorpej sc->sc_ctrl |= CTRL_ILOS;
2294 1.325 msaitoh
2295 1.325 msaitoh /*
2296 1.325 msaitoh * XXX
2297 1.325 msaitoh * This code isn't correct because pin 2 and 3 are located
2298 1.325 msaitoh * in different position on newer chips. Check all datasheet.
2299 1.325 msaitoh *
2300 1.325 msaitoh * Until resolve this problem, check if a chip < 82580
2301 1.325 msaitoh */
2302 1.325 msaitoh if (sc->sc_type <= WM_T_82580) {
2303 1.325 msaitoh if (sc->sc_type >= WM_T_82544) {
2304 1.325 msaitoh sc->sc_ctrl |=
2305 1.325 msaitoh ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
2306 1.325 msaitoh CTRL_SWDPIO_SHIFT;
2307 1.325 msaitoh sc->sc_ctrl |=
2308 1.325 msaitoh ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
2309 1.325 msaitoh CTRL_SWDPINS_SHIFT;
2310 1.325 msaitoh } else {
2311 1.325 msaitoh sc->sc_ctrl |=
2312 1.325 msaitoh ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<
2313 1.325 msaitoh CTRL_SWDPIO_SHIFT;
2314 1.325 msaitoh }
2315 1.325 msaitoh }
2316 1.325 msaitoh
2317 1.325 msaitoh /* XXX For other than 82580? */
2318 1.325 msaitoh if (sc->sc_type == WM_T_82580) {
2319 1.325 msaitoh wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword);
2320 1.325 msaitoh printf("CFG3 = %08x\n", (uint32_t)nvmword);
2321 1.325 msaitoh if (nvmword & __BIT(13)) {
2322 1.325 msaitoh printf("SET ILOS\n");
2323 1.325 msaitoh sc->sc_ctrl |= CTRL_ILOS;
2324 1.325 msaitoh }
2325 1.1 thorpej }
2326 1.1 thorpej
2327 1.1 thorpej #if 0
2328 1.11 thorpej if (sc->sc_type >= WM_T_82544) {
2329 1.293 msaitoh if (cfg1 & NVM_CFG1_IPS0)
2330 1.1 thorpej sc->sc_ctrl_ext |= CTRL_EXT_IPS;
2331 1.293 msaitoh if (cfg1 & NVM_CFG1_IPS1)
2332 1.1 thorpej sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
2333 1.1 thorpej sc->sc_ctrl_ext |=
2334 1.293 msaitoh ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
2335 1.1 thorpej CTRL_EXT_SWDPIO_SHIFT;
2336 1.1 thorpej sc->sc_ctrl_ext |=
2337 1.293 msaitoh ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
2338 1.1 thorpej CTRL_EXT_SWDPINS_SHIFT;
2339 1.1 thorpej } else {
2340 1.1 thorpej sc->sc_ctrl_ext |=
2341 1.293 msaitoh ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) <<
2342 1.1 thorpej CTRL_EXT_SWDPIO_SHIFT;
2343 1.1 thorpej }
2344 1.1 thorpej #endif
2345 1.1 thorpej
2346 1.1 thorpej CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
2347 1.1 thorpej #if 0
2348 1.1 thorpej CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
2349 1.1 thorpej #endif
2350 1.1 thorpej
2351 1.1 thorpej /*
2352 1.1 thorpej * Set up some register offsets that are different between
2353 1.11 thorpej * the i82542 and the i82543 and later chips.
2354 1.1 thorpej */
2355 1.11 thorpej if (sc->sc_type < WM_T_82543) {
2356 1.1 thorpej sc->sc_rdt_reg = WMREG_OLD_RDT0;
2357 1.1 thorpej sc->sc_tdt_reg = WMREG_OLD_TDT;
2358 1.1 thorpej } else {
2359 1.1 thorpej sc->sc_rdt_reg = WMREG_RDT;
2360 1.1 thorpej sc->sc_tdt_reg = WMREG_TDT;
2361 1.1 thorpej }
2362 1.1 thorpej
2363 1.192 msaitoh if (sc->sc_type == WM_T_PCH) {
2364 1.192 msaitoh uint16_t val;
2365 1.192 msaitoh
2366 1.192 msaitoh /* Save the NVM K1 bit setting */
2367 1.293 msaitoh wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val);
2368 1.192 msaitoh
2369 1.293 msaitoh if ((val & NVM_K1_CONFIG_ENABLE) != 0)
2370 1.192 msaitoh sc->sc_nvm_k1_enabled = 1;
2371 1.192 msaitoh else
2372 1.192 msaitoh sc->sc_nvm_k1_enabled = 0;
2373 1.192 msaitoh }
2374 1.192 msaitoh
2375 1.1 thorpej /*
2376 1.199 msaitoh * Determine if we're TBI,GMII or SGMII mode, and initialize the
2377 1.1 thorpej * media structures accordingly.
2378 1.1 thorpej */
2379 1.144 msaitoh if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
2380 1.190 msaitoh || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
2381 1.249 msaitoh || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
2382 1.249 msaitoh || sc->sc_type == WM_T_82573
2383 1.185 msaitoh || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
2384 1.139 bouyer /* STATUS_TBIMODE reserved/reused, can't rely on it */
2385 1.191 msaitoh wm_gmii_mediainit(sc, wmp->wmp_product);
2386 1.139 bouyer } else if (sc->sc_type < WM_T_82543 ||
2387 1.1 thorpej (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
2388 1.311 msaitoh if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) {
2389 1.160 christos aprint_error_dev(sc->sc_dev,
2390 1.160 christos "WARNING: TBIMODE set on 1000BASE-T product!\n");
2391 1.311 msaitoh sc->sc_mediatype = WM_MEDIATYPE_FIBER;
2392 1.292 msaitoh }
2393 1.1 thorpej wm_tbi_mediainit(sc);
2394 1.1 thorpej } else {
2395 1.199 msaitoh switch (sc->sc_type) {
2396 1.199 msaitoh case WM_T_82575:
2397 1.199 msaitoh case WM_T_82576:
2398 1.199 msaitoh case WM_T_82580:
2399 1.228 msaitoh case WM_T_I350:
2400 1.265 msaitoh case WM_T_I354:
2401 1.247 msaitoh case WM_T_I210:
2402 1.247 msaitoh case WM_T_I211:
2403 1.199 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
2404 1.292 msaitoh link_mode = reg & CTRL_EXT_LINK_MODE_MASK;
2405 1.292 msaitoh switch (link_mode) {
2406 1.265 msaitoh case CTRL_EXT_LINK_MODE_1000KX:
2407 1.265 msaitoh aprint_verbose_dev(sc->sc_dev, "1000KX\n");
2408 1.311 msaitoh sc->sc_mediatype = WM_MEDIATYPE_SERDES;
2409 1.199 msaitoh break;
2410 1.265 msaitoh case CTRL_EXT_LINK_MODE_SGMII:
2411 1.265 msaitoh if (wm_sgmii_uses_mdio(sc)) {
2412 1.265 msaitoh aprint_verbose_dev(sc->sc_dev,
2413 1.265 msaitoh "SGMII(MDIO)\n");
2414 1.265 msaitoh sc->sc_flags |= WM_F_SGMII;
2415 1.311 msaitoh sc->sc_mediatype = WM_MEDIATYPE_COPPER;
2416 1.265 msaitoh break;
2417 1.265 msaitoh }
2418 1.265 msaitoh aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n");
2419 1.265 msaitoh /*FALLTHROUGH*/
2420 1.199 msaitoh case CTRL_EXT_LINK_MODE_PCIE_SERDES:
2421 1.295 msaitoh sc->sc_mediatype = wm_sfp_get_media_type(sc);
2422 1.311 msaitoh if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) {
2423 1.292 msaitoh if (link_mode
2424 1.292 msaitoh == CTRL_EXT_LINK_MODE_SGMII) {
2425 1.292 msaitoh sc->sc_mediatype
2426 1.311 msaitoh = WM_MEDIATYPE_COPPER;
2427 1.292 msaitoh sc->sc_flags |= WM_F_SGMII;
2428 1.292 msaitoh } else {
2429 1.292 msaitoh sc->sc_mediatype
2430 1.311 msaitoh = WM_MEDIATYPE_SERDES;
2431 1.292 msaitoh aprint_verbose_dev(sc->sc_dev,
2432 1.292 msaitoh "SERDES\n");
2433 1.292 msaitoh }
2434 1.292 msaitoh break;
2435 1.292 msaitoh }
2436 1.311 msaitoh if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
2437 1.292 msaitoh aprint_verbose_dev(sc->sc_dev,
2438 1.292 msaitoh "SERDES\n");
2439 1.292 msaitoh
2440 1.292 msaitoh /* Change current link mode setting */
2441 1.292 msaitoh reg &= ~CTRL_EXT_LINK_MODE_MASK;
2442 1.292 msaitoh switch (sc->sc_mediatype) {
2443 1.311 msaitoh case WM_MEDIATYPE_COPPER:
2444 1.292 msaitoh reg |= CTRL_EXT_LINK_MODE_SGMII;
2445 1.292 msaitoh break;
2446 1.311 msaitoh case WM_MEDIATYPE_SERDES:
2447 1.292 msaitoh reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES;
2448 1.292 msaitoh break;
2449 1.292 msaitoh default:
2450 1.292 msaitoh break;
2451 1.292 msaitoh }
2452 1.292 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
2453 1.199 msaitoh break;
2454 1.199 msaitoh case CTRL_EXT_LINK_MODE_GMII:
2455 1.199 msaitoh default:
2456 1.295 msaitoh aprint_verbose_dev(sc->sc_dev, "Copper\n");
2457 1.311 msaitoh sc->sc_mediatype = WM_MEDIATYPE_COPPER;
2458 1.199 msaitoh break;
2459 1.199 msaitoh }
2460 1.292 msaitoh
2461 1.292 msaitoh reg &= ~CTRL_EXT_I2C_ENA;
2462 1.292 msaitoh if ((sc->sc_flags & WM_F_SGMII) != 0)
2463 1.292 msaitoh reg |= CTRL_EXT_I2C_ENA;
2464 1.292 msaitoh else
2465 1.292 msaitoh reg &= ~CTRL_EXT_I2C_ENA;
2466 1.292 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
2467 1.292 msaitoh
2468 1.311 msaitoh if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)
2469 1.292 msaitoh wm_gmii_mediainit(sc, wmp->wmp_product);
2470 1.292 msaitoh else
2471 1.292 msaitoh wm_tbi_mediainit(sc);
2472 1.199 msaitoh break;
2473 1.199 msaitoh default:
2474 1.311 msaitoh if (sc->sc_mediatype == WM_MEDIATYPE_FIBER)
2475 1.199 msaitoh aprint_error_dev(sc->sc_dev,
2476 1.199 msaitoh "WARNING: TBIMODE clear on 1000BASE-X product!\n");
2477 1.311 msaitoh sc->sc_mediatype = WM_MEDIATYPE_COPPER;
2478 1.199 msaitoh wm_gmii_mediainit(sc, wmp->wmp_product);
2479 1.199 msaitoh }
2480 1.1 thorpej }
2481 1.1 thorpej
2482 1.1 thorpej ifp = &sc->sc_ethercom.ec_if;
2483 1.160 christos xname = device_xname(sc->sc_dev);
2484 1.160 christos strlcpy(ifp->if_xname, xname, IFNAMSIZ);
2485 1.1 thorpej ifp->if_softc = sc;
2486 1.1 thorpej ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2487 1.1 thorpej ifp->if_ioctl = wm_ioctl;
2488 1.233 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
2489 1.232 bouyer ifp->if_start = wm_nq_start;
2490 1.232 bouyer else
2491 1.232 bouyer ifp->if_start = wm_start;
2492 1.1 thorpej ifp->if_watchdog = wm_watchdog;
2493 1.1 thorpej ifp->if_init = wm_init;
2494 1.1 thorpej ifp->if_stop = wm_stop;
2495 1.58 ragge IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
2496 1.1 thorpej IFQ_SET_READY(&ifp->if_snd);
2497 1.1 thorpej
2498 1.187 msaitoh /* Check for jumbo frame */
2499 1.187 msaitoh switch (sc->sc_type) {
2500 1.187 msaitoh case WM_T_82573:
2501 1.187 msaitoh /* XXX limited to 9234 if ASPM is disabled */
2502 1.325 msaitoh wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword);
2503 1.325 msaitoh if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0)
2504 1.187 msaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
2505 1.187 msaitoh break;
2506 1.187 msaitoh case WM_T_82571:
2507 1.187 msaitoh case WM_T_82572:
2508 1.187 msaitoh case WM_T_82574:
2509 1.199 msaitoh case WM_T_82575:
2510 1.199 msaitoh case WM_T_82576:
2511 1.199 msaitoh case WM_T_82580:
2512 1.228 msaitoh case WM_T_I350:
2513 1.265 msaitoh case WM_T_I354: /* XXXX ok? */
2514 1.247 msaitoh case WM_T_I210:
2515 1.247 msaitoh case WM_T_I211:
2516 1.187 msaitoh case WM_T_80003:
2517 1.187 msaitoh case WM_T_ICH9:
2518 1.187 msaitoh case WM_T_ICH10:
2519 1.221 msaitoh case WM_T_PCH2: /* PCH2 supports 9K frame size */
2520 1.249 msaitoh case WM_T_PCH_LPT:
2521 1.187 msaitoh /* XXX limited to 9234 */
2522 1.120 msaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
2523 1.187 msaitoh break;
2524 1.190 msaitoh case WM_T_PCH:
2525 1.190 msaitoh /* XXX limited to 4096 */
2526 1.190 msaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
2527 1.190 msaitoh break;
2528 1.187 msaitoh case WM_T_82542_2_0:
2529 1.187 msaitoh case WM_T_82542_2_1:
2530 1.187 msaitoh case WM_T_82583:
2531 1.187 msaitoh case WM_T_ICH8:
2532 1.187 msaitoh /* No support for jumbo frame */
2533 1.187 msaitoh break;
2534 1.187 msaitoh default:
2535 1.187 msaitoh /* ETHER_MAX_LEN_JUMBO */
2536 1.187 msaitoh sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
2537 1.187 msaitoh break;
2538 1.187 msaitoh }
2539 1.41 tls
2540 1.281 msaitoh /* If we're a i82543 or greater, we can support VLANs. */
2541 1.233 msaitoh if (sc->sc_type >= WM_T_82543)
2542 1.1 thorpej sc->sc_ethercom.ec_capabilities |=
2543 1.172 darran ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
2544 1.1 thorpej
2545 1.1 thorpej /*
2546 1.1 thorpej * We can perform TCPv4 and UDPv4 checkums in-bound. Only
2547 1.11 thorpej * on i82543 and later.
2548 1.1 thorpej */
2549 1.130 yamt if (sc->sc_type >= WM_T_82543) {
2550 1.1 thorpej ifp->if_capabilities |=
2551 1.103 yamt IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
2552 1.103 yamt IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
2553 1.107 yamt IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
2554 1.107 yamt IFCAP_CSUM_TCPv6_Tx |
2555 1.107 yamt IFCAP_CSUM_UDPv6_Tx;
2556 1.130 yamt }
2557 1.130 yamt
2558 1.130 yamt /*
2559 1.130 yamt * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL.
2560 1.130 yamt *
2561 1.130 yamt * 82541GI (8086:1076) ... no
2562 1.130 yamt * 82572EI (8086:10b9) ... yes
2563 1.130 yamt */
2564 1.130 yamt if (sc->sc_type >= WM_T_82571) {
2565 1.130 yamt ifp->if_capabilities |=
2566 1.130 yamt IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
2567 1.130 yamt }
2568 1.1 thorpej
2569 1.198 msaitoh /*
2570 1.99 matt * If we're a i82544 or greater (except i82547), we can do
2571 1.99 matt * TCP segmentation offload.
2572 1.99 matt */
2573 1.131 yamt if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) {
2574 1.99 matt ifp->if_capabilities |= IFCAP_TSOv4;
2575 1.131 yamt }
2576 1.131 yamt
2577 1.131 yamt if (sc->sc_type >= WM_T_82571) {
2578 1.131 yamt ifp->if_capabilities |= IFCAP_TSOv6;
2579 1.131 yamt }
2580 1.99 matt
2581 1.272 ozaki #ifdef WM_MPSAFE
2582 1.283 ozaki sc->sc_tx_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
2583 1.283 ozaki sc->sc_rx_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
2584 1.272 ozaki #else
2585 1.283 ozaki sc->sc_tx_lock = NULL;
2586 1.283 ozaki sc->sc_rx_lock = NULL;
2587 1.272 ozaki #endif
2588 1.272 ozaki
2589 1.281 msaitoh /* Attach the interface. */
2590 1.1 thorpej if_attach(ifp);
2591 1.1 thorpej ether_ifattach(ifp, enaddr);
2592 1.213 msaitoh ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb);
2593 1.289 tls rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET,
2594 1.289 tls RND_FLAG_DEFAULT);
2595 1.1 thorpej
2596 1.1 thorpej #ifdef WM_EVENT_COUNTERS
2597 1.1 thorpej /* Attach event counters. */
2598 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
2599 1.160 christos NULL, xname, "txsstall");
2600 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
2601 1.160 christos NULL, xname, "txdstall");
2602 1.78 thorpej evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC,
2603 1.160 christos NULL, xname, "txfifo_stall");
2604 1.4 thorpej evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR,
2605 1.160 christos NULL, xname, "txdw");
2606 1.4 thorpej evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR,
2607 1.160 christos NULL, xname, "txqe");
2608 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
2609 1.160 christos NULL, xname, "rxintr");
2610 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
2611 1.160 christos NULL, xname, "linkintr");
2612 1.1 thorpej
2613 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
2614 1.160 christos NULL, xname, "rxipsum");
2615 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC,
2616 1.160 christos NULL, xname, "rxtusum");
2617 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
2618 1.160 christos NULL, xname, "txipsum");
2619 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC,
2620 1.160 christos NULL, xname, "txtusum");
2621 1.107 yamt evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC,
2622 1.160 christos NULL, xname, "txtusum6");
2623 1.1 thorpej
2624 1.99 matt evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC,
2625 1.160 christos NULL, xname, "txtso");
2626 1.131 yamt evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC,
2627 1.160 christos NULL, xname, "txtso6");
2628 1.99 matt evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC,
2629 1.160 christos NULL, xname, "txtsopain");
2630 1.99 matt
2631 1.75 thorpej for (i = 0; i < WM_NTXSEGS; i++) {
2632 1.267 christos snprintf(wm_txseg_evcnt_names[i],
2633 1.267 christos sizeof(wm_txseg_evcnt_names[i]), "txseg%d", i);
2634 1.2 thorpej evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC,
2635 1.160 christos NULL, xname, wm_txseg_evcnt_names[i]);
2636 1.75 thorpej }
2637 1.2 thorpej
2638 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC,
2639 1.160 christos NULL, xname, "txdrop");
2640 1.1 thorpej
2641 1.1 thorpej evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC,
2642 1.160 christos NULL, xname, "tu");
2643 1.71 thorpej
2644 1.71 thorpej evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
2645 1.160 christos NULL, xname, "tx_xoff");
2646 1.71 thorpej evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
2647 1.160 christos NULL, xname, "tx_xon");
2648 1.71 thorpej evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
2649 1.160 christos NULL, xname, "rx_xoff");
2650 1.71 thorpej evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
2651 1.160 christos NULL, xname, "rx_xon");
2652 1.71 thorpej evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
2653 1.160 christos NULL, xname, "rx_macctl");
2654 1.1 thorpej #endif /* WM_EVENT_COUNTERS */
2655 1.1 thorpej
2656 1.203 msaitoh if (pmf_device_register(self, wm_suspend, wm_resume))
2657 1.180 tsutsui pmf_class_network_register(self, ifp);
2658 1.180 tsutsui else
2659 1.149 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
2660 1.123 jmcneill
2661 1.290 msaitoh sc->sc_flags |= WM_F_ATTACHED;
2662 1.1 thorpej return;
2663 1.1 thorpej
2664 1.1 thorpej /*
2665 1.1 thorpej * Free any resources we've allocated during the failed attach
2666 1.1 thorpej * attempt. Do this in reverse order and fall through.
2667 1.1 thorpej */
2668 1.1 thorpej fail_5:
2669 1.1 thorpej for (i = 0; i < WM_NRXDESC; i++) {
2670 1.1 thorpej if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
2671 1.1 thorpej bus_dmamap_destroy(sc->sc_dmat,
2672 1.1 thorpej sc->sc_rxsoft[i].rxs_dmamap);
2673 1.1 thorpej }
2674 1.1 thorpej fail_4:
2675 1.74 tron for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
2676 1.1 thorpej if (sc->sc_txsoft[i].txs_dmamap != NULL)
2677 1.1 thorpej bus_dmamap_destroy(sc->sc_dmat,
2678 1.1 thorpej sc->sc_txsoft[i].txs_dmamap);
2679 1.1 thorpej }
2680 1.1 thorpej bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
2681 1.1 thorpej fail_3:
2682 1.1 thorpej bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
2683 1.1 thorpej fail_2:
2684 1.135 christos bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
2685 1.201 msaitoh sc->sc_cd_size);
2686 1.1 thorpej fail_1:
2687 1.201 msaitoh bus_dmamem_free(sc->sc_dmat, &sc->sc_cd_seg, sc->sc_cd_rseg);
2688 1.1 thorpej fail_0:
2689 1.1 thorpej return;
2690 1.1 thorpej }
2691 1.1 thorpej
2692 1.280 msaitoh /* The detach function (ca_detach) */
2693 1.201 msaitoh static int
2694 1.201 msaitoh wm_detach(device_t self, int flags __unused)
2695 1.201 msaitoh {
2696 1.201 msaitoh struct wm_softc *sc = device_private(self);
2697 1.201 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2698 1.272 ozaki int i;
2699 1.272 ozaki #ifndef WM_MPSAFE
2700 1.272 ozaki int s;
2701 1.290 msaitoh #endif
2702 1.201 msaitoh
2703 1.290 msaitoh if ((sc->sc_flags & WM_F_ATTACHED) == 0)
2704 1.290 msaitoh return 0;
2705 1.290 msaitoh
2706 1.290 msaitoh #ifndef WM_MPSAFE
2707 1.201 msaitoh s = splnet();
2708 1.272 ozaki #endif
2709 1.201 msaitoh /* Stop the interface. Callouts are stopped in it. */
2710 1.201 msaitoh wm_stop(ifp, 1);
2711 1.272 ozaki
2712 1.272 ozaki #ifndef WM_MPSAFE
2713 1.201 msaitoh splx(s);
2714 1.272 ozaki #endif
2715 1.201 msaitoh
2716 1.201 msaitoh pmf_device_deregister(self);
2717 1.201 msaitoh
2718 1.201 msaitoh /* Tell the firmware about the release */
2719 1.283 ozaki WM_BOTH_LOCK(sc);
2720 1.201 msaitoh wm_release_manageability(sc);
2721 1.212 jakllsch wm_release_hw_control(sc);
2722 1.283 ozaki WM_BOTH_UNLOCK(sc);
2723 1.201 msaitoh
2724 1.201 msaitoh mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
2725 1.201 msaitoh
2726 1.201 msaitoh /* Delete all remaining media. */
2727 1.201 msaitoh ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
2728 1.201 msaitoh
2729 1.201 msaitoh ether_ifdetach(ifp);
2730 1.201 msaitoh if_detach(ifp);
2731 1.201 msaitoh
2732 1.201 msaitoh
2733 1.246 christos /* Unload RX dmamaps and free mbufs */
2734 1.283 ozaki WM_RX_LOCK(sc);
2735 1.201 msaitoh wm_rxdrain(sc);
2736 1.283 ozaki WM_RX_UNLOCK(sc);
2737 1.272 ozaki /* Must unlock here */
2738 1.201 msaitoh
2739 1.201 msaitoh /* Free dmamap. It's the same as the end of the wm_attach() function */
2740 1.201 msaitoh for (i = 0; i < WM_NRXDESC; i++) {
2741 1.201 msaitoh if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
2742 1.201 msaitoh bus_dmamap_destroy(sc->sc_dmat,
2743 1.201 msaitoh sc->sc_rxsoft[i].rxs_dmamap);
2744 1.201 msaitoh }
2745 1.201 msaitoh for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
2746 1.201 msaitoh if (sc->sc_txsoft[i].txs_dmamap != NULL)
2747 1.201 msaitoh bus_dmamap_destroy(sc->sc_dmat,
2748 1.201 msaitoh sc->sc_txsoft[i].txs_dmamap);
2749 1.201 msaitoh }
2750 1.201 msaitoh bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
2751 1.201 msaitoh bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
2752 1.201 msaitoh bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
2753 1.201 msaitoh sc->sc_cd_size);
2754 1.201 msaitoh bus_dmamem_free(sc->sc_dmat, &sc->sc_cd_seg, sc->sc_cd_rseg);
2755 1.201 msaitoh
2756 1.201 msaitoh /* Disestablish the interrupt handler */
2757 1.335 msaitoh for (i = 0; i < sc->sc_nintrs; i++) {
2758 1.335 msaitoh if (sc->sc_ihs[i] != NULL) {
2759 1.335 msaitoh pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
2760 1.335 msaitoh sc->sc_ihs[i] = NULL;
2761 1.335 msaitoh }
2762 1.201 msaitoh }
2763 1.335 msaitoh #ifdef WM_MSI_MSIX
2764 1.335 msaitoh pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs);
2765 1.335 msaitoh #endif /* WM_MSI_MSIX */
2766 1.201 msaitoh
2767 1.212 jakllsch /* Unmap the registers */
2768 1.201 msaitoh if (sc->sc_ss) {
2769 1.201 msaitoh bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss);
2770 1.201 msaitoh sc->sc_ss = 0;
2771 1.201 msaitoh }
2772 1.212 jakllsch if (sc->sc_ios) {
2773 1.212 jakllsch bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
2774 1.212 jakllsch sc->sc_ios = 0;
2775 1.212 jakllsch }
2776 1.336 msaitoh if (sc->sc_flashs) {
2777 1.336 msaitoh bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs);
2778 1.336 msaitoh sc->sc_flashs = 0;
2779 1.336 msaitoh }
2780 1.201 msaitoh
2781 1.283 ozaki if (sc->sc_tx_lock)
2782 1.283 ozaki mutex_obj_free(sc->sc_tx_lock);
2783 1.283 ozaki if (sc->sc_rx_lock)
2784 1.283 ozaki mutex_obj_free(sc->sc_rx_lock);
2785 1.272 ozaki
2786 1.201 msaitoh return 0;
2787 1.201 msaitoh }
2788 1.201 msaitoh
2789 1.281 msaitoh static bool
2790 1.281 msaitoh wm_suspend(device_t self, const pmf_qual_t *qual)
2791 1.281 msaitoh {
2792 1.281 msaitoh struct wm_softc *sc = device_private(self);
2793 1.281 msaitoh
2794 1.281 msaitoh wm_release_manageability(sc);
2795 1.281 msaitoh wm_release_hw_control(sc);
2796 1.281 msaitoh #ifdef WM_WOL
2797 1.281 msaitoh wm_enable_wakeup(sc);
2798 1.281 msaitoh #endif
2799 1.281 msaitoh
2800 1.281 msaitoh return true;
2801 1.281 msaitoh }
2802 1.281 msaitoh
2803 1.281 msaitoh static bool
2804 1.281 msaitoh wm_resume(device_t self, const pmf_qual_t *qual)
2805 1.281 msaitoh {
2806 1.281 msaitoh struct wm_softc *sc = device_private(self);
2807 1.281 msaitoh
2808 1.281 msaitoh wm_init_manageability(sc);
2809 1.281 msaitoh
2810 1.281 msaitoh return true;
2811 1.281 msaitoh }
2812 1.281 msaitoh
2813 1.1 thorpej /*
2814 1.281 msaitoh * wm_watchdog: [ifnet interface function]
2815 1.1 thorpej *
2816 1.281 msaitoh * Watchdog timer handler.
2817 1.1 thorpej */
2818 1.281 msaitoh static void
2819 1.281 msaitoh wm_watchdog(struct ifnet *ifp)
2820 1.1 thorpej {
2821 1.281 msaitoh struct wm_softc *sc = ifp->if_softc;
2822 1.1 thorpej
2823 1.1 thorpej /*
2824 1.281 msaitoh * Since we're using delayed interrupts, sweep up
2825 1.281 msaitoh * before we report an error.
2826 1.1 thorpej */
2827 1.283 ozaki WM_TX_LOCK(sc);
2828 1.335 msaitoh wm_txeof(sc);
2829 1.283 ozaki WM_TX_UNLOCK(sc);
2830 1.281 msaitoh
2831 1.281 msaitoh if (sc->sc_txfree != WM_NTXDESC(sc)) {
2832 1.281 msaitoh #ifdef WM_DEBUG
2833 1.281 msaitoh int i, j;
2834 1.281 msaitoh struct wm_txsoft *txs;
2835 1.281 msaitoh #endif
2836 1.281 msaitoh log(LOG_ERR,
2837 1.281 msaitoh "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
2838 1.281 msaitoh device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree,
2839 1.281 msaitoh sc->sc_txnext);
2840 1.281 msaitoh ifp->if_oerrors++;
2841 1.281 msaitoh #ifdef WM_DEBUG
2842 1.281 msaitoh for (i = sc->sc_txsdirty; i != sc->sc_txsnext ;
2843 1.281 msaitoh i = WM_NEXTTXS(sc, i)) {
2844 1.281 msaitoh txs = &sc->sc_txsoft[i];
2845 1.281 msaitoh printf("txs %d tx %d -> %d\n",
2846 1.281 msaitoh i, txs->txs_firstdesc, txs->txs_lastdesc);
2847 1.281 msaitoh for (j = txs->txs_firstdesc; ;
2848 1.281 msaitoh j = WM_NEXTTX(sc, j)) {
2849 1.281 msaitoh printf("\tdesc %d: 0x%" PRIx64 "\n", j,
2850 1.281 msaitoh sc->sc_nq_txdescs[j].nqtx_data.nqtxd_addr);
2851 1.281 msaitoh printf("\t %#08x%08x\n",
2852 1.281 msaitoh sc->sc_nq_txdescs[j].nqtx_data.nqtxd_fields,
2853 1.281 msaitoh sc->sc_nq_txdescs[j].nqtx_data.nqtxd_cmdlen);
2854 1.281 msaitoh if (j == txs->txs_lastdesc)
2855 1.281 msaitoh break;
2856 1.281 msaitoh }
2857 1.281 msaitoh }
2858 1.281 msaitoh #endif
2859 1.281 msaitoh /* Reset the interface. */
2860 1.281 msaitoh (void) wm_init(ifp);
2861 1.281 msaitoh }
2862 1.281 msaitoh
2863 1.281 msaitoh /* Try to get more packets going. */
2864 1.281 msaitoh ifp->if_start(ifp);
2865 1.281 msaitoh }
2866 1.1 thorpej
2867 1.281 msaitoh /*
2868 1.281 msaitoh * wm_tick:
2869 1.281 msaitoh *
2870 1.281 msaitoh * One second timer, used to check link status, sweep up
2871 1.281 msaitoh * completed transmit jobs, etc.
2872 1.281 msaitoh */
2873 1.281 msaitoh static void
2874 1.281 msaitoh wm_tick(void *arg)
2875 1.281 msaitoh {
2876 1.281 msaitoh struct wm_softc *sc = arg;
2877 1.281 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2878 1.281 msaitoh #ifndef WM_MPSAFE
2879 1.281 msaitoh int s;
2880 1.281 msaitoh
2881 1.281 msaitoh s = splnet();
2882 1.281 msaitoh #endif
2883 1.35 thorpej
2884 1.283 ozaki WM_TX_LOCK(sc);
2885 1.13 thorpej
2886 1.281 msaitoh if (sc->sc_stopping)
2887 1.281 msaitoh goto out;
2888 1.1 thorpej
2889 1.281 msaitoh if (sc->sc_type >= WM_T_82542_2_1) {
2890 1.281 msaitoh WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
2891 1.281 msaitoh WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
2892 1.281 msaitoh WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
2893 1.281 msaitoh WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
2894 1.281 msaitoh WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
2895 1.107 yamt }
2896 1.1 thorpej
2897 1.281 msaitoh ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
2898 1.281 msaitoh ifp->if_ierrors += 0ULL + /* ensure quad_t */
2899 1.281 msaitoh + CSR_READ(sc, WMREG_CRCERRS)
2900 1.281 msaitoh + CSR_READ(sc, WMREG_ALGNERRC)
2901 1.281 msaitoh + CSR_READ(sc, WMREG_SYMERRC)
2902 1.281 msaitoh + CSR_READ(sc, WMREG_RXERRC)
2903 1.281 msaitoh + CSR_READ(sc, WMREG_SEC)
2904 1.281 msaitoh + CSR_READ(sc, WMREG_CEXTERR)
2905 1.281 msaitoh + CSR_READ(sc, WMREG_RLEC);
2906 1.281 msaitoh ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC) + CSR_READ(sc, WMREG_RNBC);
2907 1.98 thorpej
2908 1.281 msaitoh if (sc->sc_flags & WM_F_HAS_MII)
2909 1.281 msaitoh mii_tick(&sc->sc_mii);
2910 1.325 msaitoh else if ((sc->sc_type >= WM_T_82575)
2911 1.325 msaitoh && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
2912 1.325 msaitoh wm_serdes_tick(sc);
2913 1.281 msaitoh else
2914 1.325 msaitoh wm_tbi_tick(sc);
2915 1.131 yamt
2916 1.281 msaitoh out:
2917 1.283 ozaki WM_TX_UNLOCK(sc);
2918 1.281 msaitoh #ifndef WM_MPSAFE
2919 1.281 msaitoh splx(s);
2920 1.281 msaitoh #endif
2921 1.99 matt
2922 1.281 msaitoh if (!sc->sc_stopping)
2923 1.281 msaitoh callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
2924 1.281 msaitoh }
2925 1.99 matt
2926 1.281 msaitoh static int
2927 1.281 msaitoh wm_ifflags_cb(struct ethercom *ec)
2928 1.281 msaitoh {
2929 1.281 msaitoh struct ifnet *ifp = &ec->ec_if;
2930 1.281 msaitoh struct wm_softc *sc = ifp->if_softc;
2931 1.281 msaitoh int change = ifp->if_flags ^ sc->sc_if_flags;
2932 1.281 msaitoh int rc = 0;
2933 1.99 matt
2934 1.283 ozaki WM_BOTH_LOCK(sc);
2935 1.99 matt
2936 1.281 msaitoh if (change != 0)
2937 1.281 msaitoh sc->sc_if_flags = ifp->if_flags;
2938 1.99 matt
2939 1.281 msaitoh if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) {
2940 1.281 msaitoh rc = ENETRESET;
2941 1.281 msaitoh goto out;
2942 1.281 msaitoh }
2943 1.99 matt
2944 1.281 msaitoh if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2945 1.281 msaitoh wm_set_filter(sc);
2946 1.131 yamt
2947 1.281 msaitoh wm_set_vlan(sc);
2948 1.131 yamt
2949 1.281 msaitoh out:
2950 1.283 ozaki WM_BOTH_UNLOCK(sc);
2951 1.99 matt
2952 1.281 msaitoh return rc;
2953 1.75 thorpej }
2954 1.75 thorpej
2955 1.1 thorpej /*
2956 1.281 msaitoh * wm_ioctl: [ifnet interface function]
2957 1.78 thorpej *
2958 1.281 msaitoh * Handle control requests from the operator.
2959 1.78 thorpej */
2960 1.281 msaitoh static int
2961 1.281 msaitoh wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
2962 1.78 thorpej {
2963 1.281 msaitoh struct wm_softc *sc = ifp->if_softc;
2964 1.281 msaitoh struct ifreq *ifr = (struct ifreq *) data;
2965 1.281 msaitoh struct ifaddr *ifa = (struct ifaddr *)data;
2966 1.281 msaitoh struct sockaddr_dl *sdl;
2967 1.281 msaitoh int s, error;
2968 1.281 msaitoh
2969 1.272 ozaki #ifndef WM_MPSAFE
2970 1.78 thorpej s = splnet();
2971 1.272 ozaki #endif
2972 1.281 msaitoh switch (cmd) {
2973 1.281 msaitoh case SIOCSIFMEDIA:
2974 1.281 msaitoh case SIOCGIFMEDIA:
2975 1.303 ozaki WM_BOTH_LOCK(sc);
2976 1.281 msaitoh /* Flow control requires full-duplex mode. */
2977 1.327 msaitoh if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
2978 1.281 msaitoh (ifr->ifr_media & IFM_FDX) == 0)
2979 1.281 msaitoh ifr->ifr_media &= ~IFM_ETH_FMASK;
2980 1.281 msaitoh if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
2981 1.281 msaitoh if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
2982 1.281 msaitoh /* We can do both TXPAUSE and RXPAUSE. */
2983 1.281 msaitoh ifr->ifr_media |=
2984 1.281 msaitoh IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
2985 1.281 msaitoh }
2986 1.281 msaitoh sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
2987 1.281 msaitoh }
2988 1.302 ozaki WM_BOTH_UNLOCK(sc);
2989 1.302 ozaki #ifdef WM_MPSAFE
2990 1.302 ozaki s = splnet();
2991 1.302 ozaki #endif
2992 1.281 msaitoh error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
2993 1.302 ozaki #ifdef WM_MPSAFE
2994 1.302 ozaki splx(s);
2995 1.302 ozaki #endif
2996 1.281 msaitoh break;
2997 1.281 msaitoh case SIOCINITIFADDR:
2998 1.303 ozaki WM_BOTH_LOCK(sc);
2999 1.281 msaitoh if (ifa->ifa_addr->sa_family == AF_LINK) {
3000 1.281 msaitoh sdl = satosdl(ifp->if_dl->ifa_addr);
3001 1.281 msaitoh (void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
3002 1.281 msaitoh LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen);
3003 1.281 msaitoh /* unicast address is first multicast entry */
3004 1.281 msaitoh wm_set_filter(sc);
3005 1.281 msaitoh error = 0;
3006 1.303 ozaki WM_BOTH_UNLOCK(sc);
3007 1.281 msaitoh break;
3008 1.281 msaitoh }
3009 1.303 ozaki WM_BOTH_UNLOCK(sc);
3010 1.281 msaitoh /*FALLTHROUGH*/
3011 1.281 msaitoh default:
3012 1.281 msaitoh #ifdef WM_MPSAFE
3013 1.281 msaitoh s = splnet();
3014 1.281 msaitoh #endif
3015 1.281 msaitoh /* It may call wm_start, so unlock here */
3016 1.281 msaitoh error = ether_ioctl(ifp, cmd, data);
3017 1.281 msaitoh #ifdef WM_MPSAFE
3018 1.281 msaitoh splx(s);
3019 1.281 msaitoh #endif
3020 1.281 msaitoh if (error != ENETRESET)
3021 1.281 msaitoh break;
3022 1.78 thorpej
3023 1.281 msaitoh error = 0;
3024 1.78 thorpej
3025 1.281 msaitoh if (cmd == SIOCSIFCAP) {
3026 1.281 msaitoh error = (*ifp->if_init)(ifp);
3027 1.281 msaitoh } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
3028 1.281 msaitoh ;
3029 1.281 msaitoh else if (ifp->if_flags & IFF_RUNNING) {
3030 1.78 thorpej /*
3031 1.281 msaitoh * Multicast list has changed; set the hardware filter
3032 1.281 msaitoh * accordingly.
3033 1.78 thorpej */
3034 1.303 ozaki WM_BOTH_LOCK(sc);
3035 1.281 msaitoh wm_set_filter(sc);
3036 1.303 ozaki WM_BOTH_UNLOCK(sc);
3037 1.78 thorpej }
3038 1.281 msaitoh break;
3039 1.78 thorpej }
3040 1.78 thorpej
3041 1.272 ozaki #ifndef WM_MPSAFE
3042 1.78 thorpej splx(s);
3043 1.272 ozaki #endif
3044 1.281 msaitoh return error;
3045 1.78 thorpej }
3046 1.78 thorpej
3047 1.281 msaitoh /* MAC address related */
3048 1.281 msaitoh
3049 1.306 msaitoh /*
3050 1.306 msaitoh * Get the offset of MAC address and return it.
3051 1.306 msaitoh * If error occured, use offset 0.
3052 1.306 msaitoh */
3053 1.306 msaitoh static uint16_t
3054 1.281 msaitoh wm_check_alt_mac_addr(struct wm_softc *sc)
3055 1.221 msaitoh {
3056 1.281 msaitoh uint16_t myea[ETHER_ADDR_LEN / 2];
3057 1.293 msaitoh uint16_t offset = NVM_OFF_MACADDR;
3058 1.281 msaitoh
3059 1.281 msaitoh /* Try to read alternative MAC address pointer */
3060 1.293 msaitoh if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0)
3061 1.306 msaitoh return 0;
3062 1.221 msaitoh
3063 1.306 msaitoh /* Check pointer if it's valid or not. */
3064 1.306 msaitoh if ((offset == 0x0000) || (offset == 0xffff))
3065 1.306 msaitoh return 0;
3066 1.221 msaitoh
3067 1.306 msaitoh offset += NVM_OFF_MACADDR_82571(sc->sc_funcid);
3068 1.281 msaitoh /*
3069 1.281 msaitoh * Check whether alternative MAC address is valid or not.
3070 1.281 msaitoh * Some cards have non 0xffff pointer but those don't use
3071 1.281 msaitoh * alternative MAC address in reality.
3072 1.281 msaitoh *
3073 1.281 msaitoh * Check whether the broadcast bit is set or not.
3074 1.281 msaitoh */
3075 1.281 msaitoh if (wm_nvm_read(sc, offset, 1, myea) == 0)
3076 1.281 msaitoh if (((myea[0] & 0xff) & 0x01) == 0)
3077 1.306 msaitoh return offset; /* Found */
3078 1.221 msaitoh
3079 1.306 msaitoh /* Not found */
3080 1.306 msaitoh return 0;
3081 1.221 msaitoh }
3082 1.221 msaitoh
3083 1.78 thorpej static int
3084 1.281 msaitoh wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)
3085 1.78 thorpej {
3086 1.281 msaitoh uint16_t myea[ETHER_ADDR_LEN / 2];
3087 1.293 msaitoh uint16_t offset = NVM_OFF_MACADDR;
3088 1.281 msaitoh int do_invert = 0;
3089 1.78 thorpej
3090 1.281 msaitoh switch (sc->sc_type) {
3091 1.281 msaitoh case WM_T_82580:
3092 1.281 msaitoh case WM_T_I350:
3093 1.281 msaitoh case WM_T_I354:
3094 1.307 msaitoh /* EEPROM Top Level Partitioning */
3095 1.307 msaitoh offset = NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + 0;
3096 1.281 msaitoh break;
3097 1.281 msaitoh case WM_T_82571:
3098 1.281 msaitoh case WM_T_82575:
3099 1.281 msaitoh case WM_T_82576:
3100 1.281 msaitoh case WM_T_80003:
3101 1.281 msaitoh case WM_T_I210:
3102 1.281 msaitoh case WM_T_I211:
3103 1.306 msaitoh offset = wm_check_alt_mac_addr(sc);
3104 1.306 msaitoh if (offset == 0)
3105 1.281 msaitoh if ((sc->sc_funcid & 0x01) == 1)
3106 1.281 msaitoh do_invert = 1;
3107 1.281 msaitoh break;
3108 1.281 msaitoh default:
3109 1.281 msaitoh if ((sc->sc_funcid & 0x01) == 1)
3110 1.281 msaitoh do_invert = 1;
3111 1.281 msaitoh break;
3112 1.281 msaitoh }
3113 1.78 thorpej
3114 1.281 msaitoh if (wm_nvm_read(sc, offset, sizeof(myea) / sizeof(myea[0]),
3115 1.306 msaitoh myea) != 0)
3116 1.281 msaitoh goto bad;
3117 1.78 thorpej
3118 1.281 msaitoh enaddr[0] = myea[0] & 0xff;
3119 1.281 msaitoh enaddr[1] = myea[0] >> 8;
3120 1.281 msaitoh enaddr[2] = myea[1] & 0xff;
3121 1.281 msaitoh enaddr[3] = myea[1] >> 8;
3122 1.281 msaitoh enaddr[4] = myea[2] & 0xff;
3123 1.281 msaitoh enaddr[5] = myea[2] >> 8;
3124 1.78 thorpej
3125 1.281 msaitoh /*
3126 1.281 msaitoh * Toggle the LSB of the MAC address on the second port
3127 1.281 msaitoh * of some dual port cards.
3128 1.281 msaitoh */
3129 1.281 msaitoh if (do_invert != 0)
3130 1.281 msaitoh enaddr[5] ^= 1;
3131 1.78 thorpej
3132 1.194 msaitoh return 0;
3133 1.281 msaitoh
3134 1.281 msaitoh bad:
3135 1.281 msaitoh return -1;
3136 1.78 thorpej }
3137 1.78 thorpej
3138 1.78 thorpej /*
3139 1.281 msaitoh * wm_set_ral:
3140 1.1 thorpej *
3141 1.281 msaitoh * Set an entery in the receive address list.
3142 1.1 thorpej */
3143 1.47 thorpej static void
3144 1.281 msaitoh wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
3145 1.281 msaitoh {
3146 1.281 msaitoh uint32_t ral_lo, ral_hi;
3147 1.281 msaitoh
3148 1.281 msaitoh if (enaddr != NULL) {
3149 1.281 msaitoh ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
3150 1.281 msaitoh (enaddr[3] << 24);
3151 1.281 msaitoh ral_hi = enaddr[4] | (enaddr[5] << 8);
3152 1.281 msaitoh ral_hi |= RAL_AV;
3153 1.281 msaitoh } else {
3154 1.281 msaitoh ral_lo = 0;
3155 1.281 msaitoh ral_hi = 0;
3156 1.281 msaitoh }
3157 1.281 msaitoh
3158 1.281 msaitoh if (sc->sc_type >= WM_T_82544) {
3159 1.281 msaitoh CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),
3160 1.281 msaitoh ral_lo);
3161 1.281 msaitoh CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),
3162 1.281 msaitoh ral_hi);
3163 1.281 msaitoh } else {
3164 1.281 msaitoh CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo);
3165 1.281 msaitoh CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi);
3166 1.281 msaitoh }
3167 1.281 msaitoh }
3168 1.281 msaitoh
3169 1.281 msaitoh /*
3170 1.281 msaitoh * wm_mchash:
3171 1.281 msaitoh *
3172 1.281 msaitoh * Compute the hash of the multicast address for the 4096-bit
3173 1.281 msaitoh * multicast filter.
3174 1.281 msaitoh */
3175 1.281 msaitoh static uint32_t
3176 1.281 msaitoh wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
3177 1.1 thorpej {
3178 1.281 msaitoh static const int lo_shift[4] = { 4, 3, 2, 0 };
3179 1.281 msaitoh static const int hi_shift[4] = { 4, 5, 6, 8 };
3180 1.281 msaitoh static const int ich8_lo_shift[4] = { 6, 5, 4, 2 };
3181 1.281 msaitoh static const int ich8_hi_shift[4] = { 2, 3, 4, 6 };
3182 1.281 msaitoh uint32_t hash;
3183 1.281 msaitoh
3184 1.281 msaitoh if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
3185 1.281 msaitoh || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
3186 1.281 msaitoh || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
3187 1.281 msaitoh hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
3188 1.281 msaitoh (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
3189 1.281 msaitoh return (hash & 0x3ff);
3190 1.281 msaitoh }
3191 1.281 msaitoh hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
3192 1.281 msaitoh (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
3193 1.272 ozaki
3194 1.281 msaitoh return (hash & 0xfff);
3195 1.272 ozaki }
3196 1.272 ozaki
3197 1.281 msaitoh /*
3198 1.281 msaitoh * wm_set_filter:
3199 1.281 msaitoh *
3200 1.281 msaitoh * Set up the receive filter.
3201 1.281 msaitoh */
3202 1.272 ozaki static void
3203 1.281 msaitoh wm_set_filter(struct wm_softc *sc)
3204 1.272 ozaki {
3205 1.281 msaitoh struct ethercom *ec = &sc->sc_ethercom;
3206 1.281 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3207 1.281 msaitoh struct ether_multi *enm;
3208 1.281 msaitoh struct ether_multistep step;
3209 1.281 msaitoh bus_addr_t mta_reg;
3210 1.281 msaitoh uint32_t hash, reg, bit;
3211 1.281 msaitoh int i, size;
3212 1.281 msaitoh
3213 1.281 msaitoh if (sc->sc_type >= WM_T_82544)
3214 1.281 msaitoh mta_reg = WMREG_CORDOVA_MTA;
3215 1.281 msaitoh else
3216 1.281 msaitoh mta_reg = WMREG_MTA;
3217 1.1 thorpej
3218 1.281 msaitoh sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
3219 1.272 ozaki
3220 1.281 msaitoh if (ifp->if_flags & IFF_BROADCAST)
3221 1.281 msaitoh sc->sc_rctl |= RCTL_BAM;
3222 1.281 msaitoh if (ifp->if_flags & IFF_PROMISC) {
3223 1.281 msaitoh sc->sc_rctl |= RCTL_UPE;
3224 1.281 msaitoh goto allmulti;
3225 1.281 msaitoh }
3226 1.1 thorpej
3227 1.1 thorpej /*
3228 1.281 msaitoh * Set the station address in the first RAL slot, and
3229 1.281 msaitoh * clear the remaining slots.
3230 1.1 thorpej */
3231 1.281 msaitoh if (sc->sc_type == WM_T_ICH8)
3232 1.281 msaitoh size = WM_RAL_TABSIZE_ICH8 -1;
3233 1.281 msaitoh else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10)
3234 1.281 msaitoh || (sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
3235 1.281 msaitoh || (sc->sc_type == WM_T_PCH_LPT))
3236 1.281 msaitoh size = WM_RAL_TABSIZE_ICH8;
3237 1.281 msaitoh else if (sc->sc_type == WM_T_82575)
3238 1.281 msaitoh size = WM_RAL_TABSIZE_82575;
3239 1.281 msaitoh else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580))
3240 1.281 msaitoh size = WM_RAL_TABSIZE_82576;
3241 1.281 msaitoh else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
3242 1.281 msaitoh size = WM_RAL_TABSIZE_I350;
3243 1.281 msaitoh else
3244 1.281 msaitoh size = WM_RAL_TABSIZE;
3245 1.281 msaitoh wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
3246 1.281 msaitoh for (i = 1; i < size; i++)
3247 1.281 msaitoh wm_set_ral(sc, NULL, i);
3248 1.1 thorpej
3249 1.281 msaitoh if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
3250 1.281 msaitoh || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
3251 1.281 msaitoh || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
3252 1.281 msaitoh size = WM_ICH8_MC_TABSIZE;
3253 1.281 msaitoh else
3254 1.281 msaitoh size = WM_MC_TABSIZE;
3255 1.281 msaitoh /* Clear out the multicast table. */
3256 1.281 msaitoh for (i = 0; i < size; i++)
3257 1.281 msaitoh CSR_WRITE(sc, mta_reg + (i << 2), 0);
3258 1.1 thorpej
3259 1.281 msaitoh ETHER_FIRST_MULTI(step, ec, enm);
3260 1.281 msaitoh while (enm != NULL) {
3261 1.281 msaitoh if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
3262 1.281 msaitoh /*
3263 1.281 msaitoh * We must listen to a range of multicast addresses.
3264 1.281 msaitoh * For now, just accept all multicasts, rather than
3265 1.281 msaitoh * trying to set only those filter bits needed to match
3266 1.281 msaitoh * the range. (At this time, the only use of address
3267 1.281 msaitoh * ranges is for IP multicast routing, for which the
3268 1.281 msaitoh * range is big enough to require all bits set.)
3269 1.281 msaitoh */
3270 1.281 msaitoh goto allmulti;
3271 1.1 thorpej }
3272 1.1 thorpej
3273 1.281 msaitoh hash = wm_mchash(sc, enm->enm_addrlo);
3274 1.272 ozaki
3275 1.281 msaitoh reg = (hash >> 5);
3276 1.281 msaitoh if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
3277 1.281 msaitoh || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
3278 1.281 msaitoh || (sc->sc_type == WM_T_PCH2)
3279 1.281 msaitoh || (sc->sc_type == WM_T_PCH_LPT))
3280 1.281 msaitoh reg &= 0x1f;
3281 1.281 msaitoh else
3282 1.281 msaitoh reg &= 0x7f;
3283 1.281 msaitoh bit = hash & 0x1f;
3284 1.272 ozaki
3285 1.281 msaitoh hash = CSR_READ(sc, mta_reg + (reg << 2));
3286 1.281 msaitoh hash |= 1U << bit;
3287 1.1 thorpej
3288 1.281 msaitoh /* XXX Hardware bug?? */
3289 1.281 msaitoh if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
3290 1.281 msaitoh bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
3291 1.281 msaitoh CSR_WRITE(sc, mta_reg + (reg << 2), hash);
3292 1.281 msaitoh CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
3293 1.281 msaitoh } else
3294 1.281 msaitoh CSR_WRITE(sc, mta_reg + (reg << 2), hash);
3295 1.99 matt
3296 1.281 msaitoh ETHER_NEXT_MULTI(step, enm);
3297 1.281 msaitoh }
3298 1.99 matt
3299 1.281 msaitoh ifp->if_flags &= ~IFF_ALLMULTI;
3300 1.281 msaitoh goto setit;
3301 1.1 thorpej
3302 1.281 msaitoh allmulti:
3303 1.281 msaitoh ifp->if_flags |= IFF_ALLMULTI;
3304 1.281 msaitoh sc->sc_rctl |= RCTL_MPE;
3305 1.80 thorpej
3306 1.281 msaitoh setit:
3307 1.281 msaitoh CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
3308 1.281 msaitoh }
3309 1.1 thorpej
3310 1.281 msaitoh /* Reset and init related */
3311 1.78 thorpej
3312 1.281 msaitoh static void
3313 1.281 msaitoh wm_set_vlan(struct wm_softc *sc)
3314 1.281 msaitoh {
3315 1.281 msaitoh /* Deal with VLAN enables. */
3316 1.281 msaitoh if (VLAN_ATTACHED(&sc->sc_ethercom))
3317 1.281 msaitoh sc->sc_ctrl |= CTRL_VME;
3318 1.281 msaitoh else
3319 1.281 msaitoh sc->sc_ctrl &= ~CTRL_VME;
3320 1.1 thorpej
3321 1.281 msaitoh /* Write the control registers. */
3322 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
3323 1.281 msaitoh }
3324 1.1 thorpej
3325 1.281 msaitoh static void
3326 1.281 msaitoh wm_set_pcie_completion_timeout(struct wm_softc *sc)
3327 1.281 msaitoh {
3328 1.281 msaitoh uint32_t gcr;
3329 1.281 msaitoh pcireg_t ctrl2;
3330 1.1 thorpej
3331 1.281 msaitoh gcr = CSR_READ(sc, WMREG_GCR);
3332 1.4 thorpej
3333 1.281 msaitoh /* Only take action if timeout value is defaulted to 0 */
3334 1.281 msaitoh if ((gcr & GCR_CMPL_TMOUT_MASK) != 0)
3335 1.281 msaitoh goto out;
3336 1.1 thorpej
3337 1.281 msaitoh if ((gcr & GCR_CAP_VER2) == 0) {
3338 1.281 msaitoh gcr |= GCR_CMPL_TMOUT_10MS;
3339 1.281 msaitoh goto out;
3340 1.281 msaitoh }
3341 1.6 thorpej
3342 1.281 msaitoh ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
3343 1.281 msaitoh sc->sc_pcixe_capoff + PCIE_DCSR2);
3344 1.281 msaitoh ctrl2 |= WM_PCIE_DCSR2_16MS;
3345 1.281 msaitoh pci_conf_write(sc->sc_pc, sc->sc_pcitag,
3346 1.281 msaitoh sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2);
3347 1.81 thorpej
3348 1.281 msaitoh out:
3349 1.281 msaitoh /* Disable completion timeout resend */
3350 1.281 msaitoh gcr &= ~GCR_CMPL_TMOUT_RESEND;
3351 1.80 thorpej
3352 1.281 msaitoh CSR_WRITE(sc, WMREG_GCR, gcr);
3353 1.281 msaitoh }
3354 1.99 matt
3355 1.281 msaitoh void
3356 1.281 msaitoh wm_get_auto_rd_done(struct wm_softc *sc)
3357 1.281 msaitoh {
3358 1.281 msaitoh int i;
3359 1.1 thorpej
3360 1.281 msaitoh /* wait for eeprom to reload */
3361 1.281 msaitoh switch (sc->sc_type) {
3362 1.281 msaitoh case WM_T_82571:
3363 1.281 msaitoh case WM_T_82572:
3364 1.281 msaitoh case WM_T_82573:
3365 1.281 msaitoh case WM_T_82574:
3366 1.281 msaitoh case WM_T_82583:
3367 1.281 msaitoh case WM_T_82575:
3368 1.281 msaitoh case WM_T_82576:
3369 1.281 msaitoh case WM_T_82580:
3370 1.281 msaitoh case WM_T_I350:
3371 1.281 msaitoh case WM_T_I354:
3372 1.281 msaitoh case WM_T_I210:
3373 1.281 msaitoh case WM_T_I211:
3374 1.281 msaitoh case WM_T_80003:
3375 1.281 msaitoh case WM_T_ICH8:
3376 1.281 msaitoh case WM_T_ICH9:
3377 1.281 msaitoh for (i = 0; i < 10; i++) {
3378 1.281 msaitoh if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
3379 1.281 msaitoh break;
3380 1.281 msaitoh delay(1000);
3381 1.1 thorpej }
3382 1.281 msaitoh if (i == 10) {
3383 1.281 msaitoh log(LOG_ERR, "%s: auto read from eeprom failed to "
3384 1.281 msaitoh "complete\n", device_xname(sc->sc_dev));
3385 1.281 msaitoh }
3386 1.281 msaitoh break;
3387 1.281 msaitoh default:
3388 1.281 msaitoh break;
3389 1.281 msaitoh }
3390 1.281 msaitoh }
3391 1.59 christos
3392 1.281 msaitoh void
3393 1.281 msaitoh wm_lan_init_done(struct wm_softc *sc)
3394 1.281 msaitoh {
3395 1.281 msaitoh uint32_t reg = 0;
3396 1.281 msaitoh int i;
3397 1.1 thorpej
3398 1.281 msaitoh /* wait for eeprom to reload */
3399 1.281 msaitoh switch (sc->sc_type) {
3400 1.281 msaitoh case WM_T_ICH10:
3401 1.281 msaitoh case WM_T_PCH:
3402 1.281 msaitoh case WM_T_PCH2:
3403 1.281 msaitoh case WM_T_PCH_LPT:
3404 1.281 msaitoh for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
3405 1.281 msaitoh reg = CSR_READ(sc, WMREG_STATUS);
3406 1.281 msaitoh if ((reg & STATUS_LAN_INIT_DONE) != 0)
3407 1.281 msaitoh break;
3408 1.281 msaitoh delay(100);
3409 1.281 msaitoh }
3410 1.281 msaitoh if (i >= WM_ICH8_LAN_INIT_TIMEOUT) {
3411 1.281 msaitoh log(LOG_ERR, "%s: %s: lan_init_done failed to "
3412 1.281 msaitoh "complete\n", device_xname(sc->sc_dev), __func__);
3413 1.1 thorpej }
3414 1.281 msaitoh break;
3415 1.281 msaitoh default:
3416 1.281 msaitoh panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
3417 1.281 msaitoh __func__);
3418 1.281 msaitoh break;
3419 1.281 msaitoh }
3420 1.1 thorpej
3421 1.281 msaitoh reg &= ~STATUS_LAN_INIT_DONE;
3422 1.281 msaitoh CSR_WRITE(sc, WMREG_STATUS, reg);
3423 1.281 msaitoh }
3424 1.6 thorpej
3425 1.281 msaitoh void
3426 1.281 msaitoh wm_get_cfg_done(struct wm_softc *sc)
3427 1.281 msaitoh {
3428 1.281 msaitoh int mask;
3429 1.281 msaitoh uint32_t reg;
3430 1.281 msaitoh int i;
3431 1.1 thorpej
3432 1.281 msaitoh /* wait for eeprom to reload */
3433 1.281 msaitoh switch (sc->sc_type) {
3434 1.281 msaitoh case WM_T_82542_2_0:
3435 1.281 msaitoh case WM_T_82542_2_1:
3436 1.281 msaitoh /* null */
3437 1.281 msaitoh break;
3438 1.281 msaitoh case WM_T_82543:
3439 1.281 msaitoh case WM_T_82544:
3440 1.281 msaitoh case WM_T_82540:
3441 1.281 msaitoh case WM_T_82545:
3442 1.281 msaitoh case WM_T_82545_3:
3443 1.281 msaitoh case WM_T_82546:
3444 1.281 msaitoh case WM_T_82546_3:
3445 1.281 msaitoh case WM_T_82541:
3446 1.281 msaitoh case WM_T_82541_2:
3447 1.281 msaitoh case WM_T_82547:
3448 1.281 msaitoh case WM_T_82547_2:
3449 1.281 msaitoh case WM_T_82573:
3450 1.281 msaitoh case WM_T_82574:
3451 1.281 msaitoh case WM_T_82583:
3452 1.281 msaitoh /* generic */
3453 1.281 msaitoh delay(10*1000);
3454 1.281 msaitoh break;
3455 1.281 msaitoh case WM_T_80003:
3456 1.281 msaitoh case WM_T_82571:
3457 1.281 msaitoh case WM_T_82572:
3458 1.281 msaitoh case WM_T_82575:
3459 1.281 msaitoh case WM_T_82576:
3460 1.281 msaitoh case WM_T_82580:
3461 1.281 msaitoh case WM_T_I350:
3462 1.281 msaitoh case WM_T_I354:
3463 1.281 msaitoh case WM_T_I210:
3464 1.281 msaitoh case WM_T_I211:
3465 1.281 msaitoh if (sc->sc_type == WM_T_82571) {
3466 1.281 msaitoh /* Only 82571 shares port 0 */
3467 1.281 msaitoh mask = EEMNGCTL_CFGDONE_0;
3468 1.281 msaitoh } else
3469 1.281 msaitoh mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid;
3470 1.281 msaitoh for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) {
3471 1.281 msaitoh if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
3472 1.281 msaitoh break;
3473 1.281 msaitoh delay(1000);
3474 1.281 msaitoh }
3475 1.281 msaitoh if (i >= WM_PHY_CFG_TIMEOUT) {
3476 1.281 msaitoh DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n",
3477 1.281 msaitoh device_xname(sc->sc_dev), __func__));
3478 1.281 msaitoh }
3479 1.281 msaitoh break;
3480 1.281 msaitoh case WM_T_ICH8:
3481 1.281 msaitoh case WM_T_ICH9:
3482 1.281 msaitoh case WM_T_ICH10:
3483 1.281 msaitoh case WM_T_PCH:
3484 1.281 msaitoh case WM_T_PCH2:
3485 1.281 msaitoh case WM_T_PCH_LPT:
3486 1.281 msaitoh delay(10*1000);
3487 1.281 msaitoh if (sc->sc_type >= WM_T_ICH10)
3488 1.281 msaitoh wm_lan_init_done(sc);
3489 1.281 msaitoh else
3490 1.281 msaitoh wm_get_auto_rd_done(sc);
3491 1.1 thorpej
3492 1.281 msaitoh reg = CSR_READ(sc, WMREG_STATUS);
3493 1.281 msaitoh if ((reg & STATUS_PHYRA) != 0)
3494 1.281 msaitoh CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA);
3495 1.281 msaitoh break;
3496 1.281 msaitoh default:
3497 1.281 msaitoh panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
3498 1.281 msaitoh __func__);
3499 1.281 msaitoh break;
3500 1.1 thorpej }
3501 1.1 thorpej }
3502 1.1 thorpej
3503 1.312 msaitoh /* Init hardware bits */
3504 1.312 msaitoh void
3505 1.312 msaitoh wm_initialize_hardware_bits(struct wm_softc *sc)
3506 1.312 msaitoh {
3507 1.312 msaitoh uint32_t tarc0, tarc1, reg;
3508 1.332 msaitoh
3509 1.312 msaitoh /* For 82571 variant, 80003 and ICHs */
3510 1.312 msaitoh if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583))
3511 1.312 msaitoh || (sc->sc_type >= WM_T_80003)) {
3512 1.312 msaitoh
3513 1.312 msaitoh /* Transmit Descriptor Control 0 */
3514 1.312 msaitoh reg = CSR_READ(sc, WMREG_TXDCTL(0));
3515 1.312 msaitoh reg |= TXDCTL_COUNT_DESC;
3516 1.312 msaitoh CSR_WRITE(sc, WMREG_TXDCTL(0), reg);
3517 1.312 msaitoh
3518 1.312 msaitoh /* Transmit Descriptor Control 1 */
3519 1.312 msaitoh reg = CSR_READ(sc, WMREG_TXDCTL(1));
3520 1.312 msaitoh reg |= TXDCTL_COUNT_DESC;
3521 1.312 msaitoh CSR_WRITE(sc, WMREG_TXDCTL(1), reg);
3522 1.312 msaitoh
3523 1.312 msaitoh /* TARC0 */
3524 1.312 msaitoh tarc0 = CSR_READ(sc, WMREG_TARC0);
3525 1.312 msaitoh switch (sc->sc_type) {
3526 1.312 msaitoh case WM_T_82571:
3527 1.312 msaitoh case WM_T_82572:
3528 1.312 msaitoh case WM_T_82573:
3529 1.312 msaitoh case WM_T_82574:
3530 1.312 msaitoh case WM_T_82583:
3531 1.312 msaitoh case WM_T_80003:
3532 1.312 msaitoh /* Clear bits 30..27 */
3533 1.312 msaitoh tarc0 &= ~__BITS(30, 27);
3534 1.312 msaitoh break;
3535 1.312 msaitoh default:
3536 1.312 msaitoh break;
3537 1.312 msaitoh }
3538 1.312 msaitoh
3539 1.312 msaitoh switch (sc->sc_type) {
3540 1.312 msaitoh case WM_T_82571:
3541 1.312 msaitoh case WM_T_82572:
3542 1.312 msaitoh tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */
3543 1.312 msaitoh
3544 1.312 msaitoh tarc1 = CSR_READ(sc, WMREG_TARC1);
3545 1.312 msaitoh tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */
3546 1.312 msaitoh tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */
3547 1.312 msaitoh /* 8257[12] Errata No.7 */
3548 1.312 msaitoh tarc1 |= __BIT(22); /* TARC1 bits 22 */
3549 1.312 msaitoh
3550 1.312 msaitoh /* TARC1 bit 28 */
3551 1.312 msaitoh if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
3552 1.312 msaitoh tarc1 &= ~__BIT(28);
3553 1.312 msaitoh else
3554 1.312 msaitoh tarc1 |= __BIT(28);
3555 1.312 msaitoh CSR_WRITE(sc, WMREG_TARC1, tarc1);
3556 1.312 msaitoh
3557 1.312 msaitoh /*
3558 1.312 msaitoh * 8257[12] Errata No.13
3559 1.312 msaitoh * Disable Dyamic Clock Gating.
3560 1.312 msaitoh */
3561 1.312 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
3562 1.312 msaitoh reg &= ~CTRL_EXT_DMA_DYN_CLK;
3563 1.312 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
3564 1.312 msaitoh break;
3565 1.312 msaitoh case WM_T_82573:
3566 1.312 msaitoh case WM_T_82574:
3567 1.312 msaitoh case WM_T_82583:
3568 1.312 msaitoh if ((sc->sc_type == WM_T_82574)
3569 1.312 msaitoh || (sc->sc_type == WM_T_82583))
3570 1.312 msaitoh tarc0 |= __BIT(26); /* TARC0 bit 26 */
3571 1.312 msaitoh
3572 1.312 msaitoh /* Extended Device Control */
3573 1.312 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
3574 1.312 msaitoh reg &= ~__BIT(23); /* Clear bit 23 */
3575 1.312 msaitoh reg |= __BIT(22); /* Set bit 22 */
3576 1.312 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
3577 1.312 msaitoh
3578 1.312 msaitoh /* Device Control */
3579 1.312 msaitoh sc->sc_ctrl &= ~__BIT(29); /* Clear bit 29 */
3580 1.312 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
3581 1.312 msaitoh
3582 1.312 msaitoh /* PCIe Control Register */
3583 1.312 msaitoh if ((sc->sc_type == WM_T_82574)
3584 1.312 msaitoh || (sc->sc_type == WM_T_82583)) {
3585 1.312 msaitoh /*
3586 1.312 msaitoh * Document says this bit must be set for
3587 1.312 msaitoh * proper operation.
3588 1.312 msaitoh */
3589 1.312 msaitoh reg = CSR_READ(sc, WMREG_GCR);
3590 1.312 msaitoh reg |= __BIT(22);
3591 1.312 msaitoh CSR_WRITE(sc, WMREG_GCR, reg);
3592 1.312 msaitoh
3593 1.312 msaitoh /*
3594 1.312 msaitoh * Apply workaround for hardware errata
3595 1.312 msaitoh * documented in errata docs Fixes issue where
3596 1.312 msaitoh * some error prone or unreliable PCIe
3597 1.312 msaitoh * completions are occurring, particularly
3598 1.312 msaitoh * with ASPM enabled. Without fix, issue can
3599 1.312 msaitoh * cause Tx timeouts.
3600 1.312 msaitoh */
3601 1.312 msaitoh reg = CSR_READ(sc, WMREG_GCR2);
3602 1.312 msaitoh reg |= __BIT(0);
3603 1.312 msaitoh CSR_WRITE(sc, WMREG_GCR2, reg);
3604 1.312 msaitoh }
3605 1.312 msaitoh break;
3606 1.312 msaitoh case WM_T_80003:
3607 1.312 msaitoh /* TARC0 */
3608 1.312 msaitoh if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
3609 1.312 msaitoh || (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
3610 1.312 msaitoh tarc0 &= ~__BIT(20); /* Clear bits 20 */
3611 1.312 msaitoh
3612 1.312 msaitoh /* TARC1 bit 28 */
3613 1.312 msaitoh tarc1 = CSR_READ(sc, WMREG_TARC1);
3614 1.312 msaitoh if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
3615 1.312 msaitoh tarc1 &= ~__BIT(28);
3616 1.312 msaitoh else
3617 1.312 msaitoh tarc1 |= __BIT(28);
3618 1.312 msaitoh CSR_WRITE(sc, WMREG_TARC1, tarc1);
3619 1.312 msaitoh break;
3620 1.312 msaitoh case WM_T_ICH8:
3621 1.312 msaitoh case WM_T_ICH9:
3622 1.312 msaitoh case WM_T_ICH10:
3623 1.312 msaitoh case WM_T_PCH:
3624 1.312 msaitoh case WM_T_PCH2:
3625 1.312 msaitoh case WM_T_PCH_LPT:
3626 1.312 msaitoh /* TARC 0 */
3627 1.312 msaitoh if (sc->sc_type == WM_T_ICH8) {
3628 1.312 msaitoh /* Set TARC0 bits 29 and 28 */
3629 1.312 msaitoh tarc0 |= __BITS(29, 28);
3630 1.312 msaitoh }
3631 1.312 msaitoh /* Set TARC0 bits 23,24,26,27 */
3632 1.312 msaitoh tarc0 |= __BITS(27, 26) | __BITS(24, 23);
3633 1.312 msaitoh
3634 1.312 msaitoh /* CTRL_EXT */
3635 1.312 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
3636 1.312 msaitoh reg |= __BIT(22); /* Set bit 22 */
3637 1.312 msaitoh /*
3638 1.312 msaitoh * Enable PHY low-power state when MAC is at D3
3639 1.312 msaitoh * w/o WoL
3640 1.312 msaitoh */
3641 1.312 msaitoh if (sc->sc_type >= WM_T_PCH)
3642 1.312 msaitoh reg |= CTRL_EXT_PHYPDEN;
3643 1.312 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
3644 1.312 msaitoh
3645 1.312 msaitoh /* TARC1 */
3646 1.312 msaitoh tarc1 = CSR_READ(sc, WMREG_TARC1);
3647 1.312 msaitoh /* bit 28 */
3648 1.312 msaitoh if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
3649 1.312 msaitoh tarc1 &= ~__BIT(28);
3650 1.312 msaitoh else
3651 1.312 msaitoh tarc1 |= __BIT(28);
3652 1.312 msaitoh tarc1 |= __BIT(24) | __BIT(26) | __BIT(30);
3653 1.312 msaitoh CSR_WRITE(sc, WMREG_TARC1, tarc1);
3654 1.312 msaitoh
3655 1.312 msaitoh /* Device Status */
3656 1.312 msaitoh if (sc->sc_type == WM_T_ICH8) {
3657 1.312 msaitoh reg = CSR_READ(sc, WMREG_STATUS);
3658 1.312 msaitoh reg &= ~__BIT(31);
3659 1.312 msaitoh CSR_WRITE(sc, WMREG_STATUS, reg);
3660 1.312 msaitoh
3661 1.312 msaitoh }
3662 1.312 msaitoh
3663 1.312 msaitoh /*
3664 1.312 msaitoh * Work-around descriptor data corruption issue during
3665 1.312 msaitoh * NFS v2 UDP traffic, just disable the NFS filtering
3666 1.312 msaitoh * capability.
3667 1.312 msaitoh */
3668 1.312 msaitoh reg = CSR_READ(sc, WMREG_RFCTL);
3669 1.312 msaitoh reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS;
3670 1.312 msaitoh CSR_WRITE(sc, WMREG_RFCTL, reg);
3671 1.312 msaitoh break;
3672 1.312 msaitoh default:
3673 1.312 msaitoh break;
3674 1.312 msaitoh }
3675 1.312 msaitoh CSR_WRITE(sc, WMREG_TARC0, tarc0);
3676 1.312 msaitoh
3677 1.312 msaitoh /*
3678 1.312 msaitoh * 8257[12] Errata No.52 and some others.
3679 1.312 msaitoh * Avoid RSS Hash Value bug.
3680 1.312 msaitoh */
3681 1.312 msaitoh switch (sc->sc_type) {
3682 1.312 msaitoh case WM_T_82571:
3683 1.312 msaitoh case WM_T_82572:
3684 1.312 msaitoh case WM_T_82573:
3685 1.312 msaitoh case WM_T_80003:
3686 1.312 msaitoh case WM_T_ICH8:
3687 1.312 msaitoh reg = CSR_READ(sc, WMREG_RFCTL);
3688 1.312 msaitoh reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS;
3689 1.312 msaitoh CSR_WRITE(sc, WMREG_RFCTL, reg);
3690 1.312 msaitoh break;
3691 1.312 msaitoh default:
3692 1.312 msaitoh break;
3693 1.312 msaitoh }
3694 1.312 msaitoh }
3695 1.312 msaitoh }
3696 1.312 msaitoh
3697 1.320 msaitoh static uint32_t
3698 1.320 msaitoh wm_rxpbs_adjust_82580(uint32_t val)
3699 1.320 msaitoh {
3700 1.320 msaitoh uint32_t rv = 0;
3701 1.320 msaitoh
3702 1.320 msaitoh if (val < __arraycount(wm_82580_rxpbs_table))
3703 1.320 msaitoh rv = wm_82580_rxpbs_table[val];
3704 1.320 msaitoh
3705 1.320 msaitoh return rv;
3706 1.320 msaitoh }
3707 1.320 msaitoh
3708 1.1 thorpej /*
3709 1.281 msaitoh * wm_reset:
3710 1.232 bouyer *
3711 1.281 msaitoh * Reset the i82542 chip.
3712 1.232 bouyer */
3713 1.281 msaitoh static void
3714 1.281 msaitoh wm_reset(struct wm_softc *sc)
3715 1.232 bouyer {
3716 1.281 msaitoh int phy_reset = 0;
3717 1.281 msaitoh int error = 0;
3718 1.281 msaitoh uint32_t reg, mask;
3719 1.232 bouyer
3720 1.232 bouyer /*
3721 1.281 msaitoh * Allocate on-chip memory according to the MTU size.
3722 1.281 msaitoh * The Packet Buffer Allocation register must be written
3723 1.281 msaitoh * before the chip is reset.
3724 1.232 bouyer */
3725 1.281 msaitoh switch (sc->sc_type) {
3726 1.281 msaitoh case WM_T_82547:
3727 1.281 msaitoh case WM_T_82547_2:
3728 1.281 msaitoh sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
3729 1.281 msaitoh PBA_22K : PBA_30K;
3730 1.281 msaitoh sc->sc_txfifo_head = 0;
3731 1.281 msaitoh sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
3732 1.281 msaitoh sc->sc_txfifo_size =
3733 1.281 msaitoh (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
3734 1.281 msaitoh sc->sc_txfifo_stall = 0;
3735 1.281 msaitoh break;
3736 1.281 msaitoh case WM_T_82571:
3737 1.281 msaitoh case WM_T_82572:
3738 1.281 msaitoh case WM_T_82575: /* XXX need special handing for jumbo frames */
3739 1.281 msaitoh case WM_T_80003:
3740 1.281 msaitoh sc->sc_pba = PBA_32K;
3741 1.281 msaitoh break;
3742 1.281 msaitoh case WM_T_82573:
3743 1.281 msaitoh sc->sc_pba = PBA_12K;
3744 1.281 msaitoh break;
3745 1.281 msaitoh case WM_T_82574:
3746 1.281 msaitoh case WM_T_82583:
3747 1.281 msaitoh sc->sc_pba = PBA_20K;
3748 1.281 msaitoh break;
3749 1.320 msaitoh case WM_T_82576:
3750 1.320 msaitoh sc->sc_pba = CSR_READ(sc, WMREG_RXPBS);
3751 1.320 msaitoh sc->sc_pba &= RXPBS_SIZE_MASK_82576;
3752 1.320 msaitoh break;
3753 1.320 msaitoh case WM_T_82580:
3754 1.320 msaitoh case WM_T_I350:
3755 1.320 msaitoh case WM_T_I354:
3756 1.320 msaitoh sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS));
3757 1.320 msaitoh break;
3758 1.320 msaitoh case WM_T_I210:
3759 1.320 msaitoh case WM_T_I211:
3760 1.320 msaitoh sc->sc_pba = PBA_34K;
3761 1.320 msaitoh break;
3762 1.281 msaitoh case WM_T_ICH8:
3763 1.312 msaitoh /* Workaround for a bit corruption issue in FIFO memory */
3764 1.281 msaitoh sc->sc_pba = PBA_8K;
3765 1.281 msaitoh CSR_WRITE(sc, WMREG_PBS, PBA_16K);
3766 1.281 msaitoh break;
3767 1.281 msaitoh case WM_T_ICH9:
3768 1.281 msaitoh case WM_T_ICH10:
3769 1.318 msaitoh sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ?
3770 1.318 msaitoh PBA_14K : PBA_10K;
3771 1.232 bouyer break;
3772 1.281 msaitoh case WM_T_PCH:
3773 1.281 msaitoh case WM_T_PCH2:
3774 1.281 msaitoh case WM_T_PCH_LPT:
3775 1.281 msaitoh sc->sc_pba = PBA_26K;
3776 1.232 bouyer break;
3777 1.232 bouyer default:
3778 1.281 msaitoh sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
3779 1.281 msaitoh PBA_40K : PBA_48K;
3780 1.281 msaitoh break;
3781 1.232 bouyer }
3782 1.320 msaitoh /*
3783 1.320 msaitoh * Only old or non-multiqueue devices have the PBA register
3784 1.320 msaitoh * XXX Need special handling for 82575.
3785 1.320 msaitoh */
3786 1.320 msaitoh if (((sc->sc_flags & WM_F_NEWQUEUE) == 0)
3787 1.320 msaitoh || (sc->sc_type == WM_T_82575))
3788 1.320 msaitoh CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
3789 1.232 bouyer
3790 1.281 msaitoh /* Prevent the PCI-E bus from sticking */
3791 1.281 msaitoh if (sc->sc_flags & WM_F_PCIE) {
3792 1.281 msaitoh int timeout = 800;
3793 1.232 bouyer
3794 1.281 msaitoh sc->sc_ctrl |= CTRL_GIO_M_DIS;
3795 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
3796 1.232 bouyer
3797 1.281 msaitoh while (timeout--) {
3798 1.281 msaitoh if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA)
3799 1.281 msaitoh == 0)
3800 1.281 msaitoh break;
3801 1.281 msaitoh delay(100);
3802 1.281 msaitoh }
3803 1.232 bouyer }
3804 1.232 bouyer
3805 1.281 msaitoh /* Set the completion timeout for interface */
3806 1.281 msaitoh if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
3807 1.300 msaitoh || (sc->sc_type == WM_T_82580)
3808 1.282 msaitoh || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
3809 1.282 msaitoh || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
3810 1.281 msaitoh wm_set_pcie_completion_timeout(sc);
3811 1.232 bouyer
3812 1.281 msaitoh /* Clear interrupt */
3813 1.281 msaitoh CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
3814 1.335 msaitoh if (sc->sc_nintrs > 1) {
3815 1.335 msaitoh if (sc->sc_type != WM_T_82574) {
3816 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
3817 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAC, 0);
3818 1.335 msaitoh } else {
3819 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAC_82574, 0);
3820 1.335 msaitoh }
3821 1.335 msaitoh }
3822 1.232 bouyer
3823 1.281 msaitoh /* Stop the transmit and receive processes. */
3824 1.281 msaitoh CSR_WRITE(sc, WMREG_RCTL, 0);
3825 1.281 msaitoh sc->sc_rctl &= ~RCTL_EN;
3826 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP);
3827 1.281 msaitoh CSR_WRITE_FLUSH(sc);
3828 1.232 bouyer
3829 1.281 msaitoh /* XXX set_tbi_sbp_82543() */
3830 1.232 bouyer
3831 1.281 msaitoh delay(10*1000);
3832 1.232 bouyer
3833 1.281 msaitoh /* Must acquire the MDIO ownership before MAC reset */
3834 1.281 msaitoh switch (sc->sc_type) {
3835 1.281 msaitoh case WM_T_82573:
3836 1.281 msaitoh case WM_T_82574:
3837 1.281 msaitoh case WM_T_82583:
3838 1.281 msaitoh error = wm_get_hw_semaphore_82573(sc);
3839 1.281 msaitoh break;
3840 1.281 msaitoh default:
3841 1.281 msaitoh break;
3842 1.281 msaitoh }
3843 1.232 bouyer
3844 1.281 msaitoh /*
3845 1.281 msaitoh * 82541 Errata 29? & 82547 Errata 28?
3846 1.281 msaitoh * See also the description about PHY_RST bit in CTRL register
3847 1.281 msaitoh * in 8254x_GBe_SDM.pdf.
3848 1.281 msaitoh */
3849 1.281 msaitoh if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) {
3850 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL,
3851 1.281 msaitoh CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
3852 1.281 msaitoh CSR_WRITE_FLUSH(sc);
3853 1.281 msaitoh delay(5000);
3854 1.281 msaitoh }
3855 1.232 bouyer
3856 1.281 msaitoh switch (sc->sc_type) {
3857 1.281 msaitoh case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */
3858 1.281 msaitoh case WM_T_82541:
3859 1.281 msaitoh case WM_T_82541_2:
3860 1.281 msaitoh case WM_T_82547:
3861 1.281 msaitoh case WM_T_82547_2:
3862 1.281 msaitoh /*
3863 1.281 msaitoh * On some chipsets, a reset through a memory-mapped write
3864 1.281 msaitoh * cycle can cause the chip to reset before completing the
3865 1.281 msaitoh * write cycle. This causes major headache that can be
3866 1.281 msaitoh * avoided by issuing the reset via indirect register writes
3867 1.281 msaitoh * through I/O space.
3868 1.281 msaitoh *
3869 1.281 msaitoh * So, if we successfully mapped the I/O BAR at attach time,
3870 1.281 msaitoh * use that. Otherwise, try our luck with a memory-mapped
3871 1.281 msaitoh * reset.
3872 1.281 msaitoh */
3873 1.281 msaitoh if (sc->sc_flags & WM_F_IOH_VALID)
3874 1.281 msaitoh wm_io_write(sc, WMREG_CTRL, CTRL_RST);
3875 1.281 msaitoh else
3876 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
3877 1.281 msaitoh break;
3878 1.281 msaitoh case WM_T_82545_3:
3879 1.281 msaitoh case WM_T_82546_3:
3880 1.281 msaitoh /* Use the shadow control register on these chips. */
3881 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
3882 1.281 msaitoh break;
3883 1.281 msaitoh case WM_T_80003:
3884 1.281 msaitoh mask = swfwphysem[sc->sc_funcid];
3885 1.281 msaitoh reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
3886 1.281 msaitoh wm_get_swfw_semaphore(sc, mask);
3887 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, reg);
3888 1.281 msaitoh wm_put_swfw_semaphore(sc, mask);
3889 1.281 msaitoh break;
3890 1.281 msaitoh case WM_T_ICH8:
3891 1.281 msaitoh case WM_T_ICH9:
3892 1.281 msaitoh case WM_T_ICH10:
3893 1.281 msaitoh case WM_T_PCH:
3894 1.281 msaitoh case WM_T_PCH2:
3895 1.281 msaitoh case WM_T_PCH_LPT:
3896 1.281 msaitoh reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
3897 1.281 msaitoh if (wm_check_reset_block(sc) == 0) {
3898 1.232 bouyer /*
3899 1.281 msaitoh * Gate automatic PHY configuration by hardware on
3900 1.281 msaitoh * non-managed 82579
3901 1.232 bouyer */
3902 1.281 msaitoh if ((sc->sc_type == WM_T_PCH2)
3903 1.281 msaitoh && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
3904 1.281 msaitoh != 0))
3905 1.281 msaitoh wm_gate_hw_phy_config_ich8lan(sc, 1);
3906 1.232 bouyer
3907 1.232 bouyer
3908 1.281 msaitoh reg |= CTRL_PHY_RESET;
3909 1.281 msaitoh phy_reset = 1;
3910 1.232 bouyer }
3911 1.281 msaitoh wm_get_swfwhw_semaphore(sc);
3912 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, reg);
3913 1.281 msaitoh /* Don't insert a completion barrier when reset */
3914 1.281 msaitoh delay(20*1000);
3915 1.281 msaitoh wm_put_swfwhw_semaphore(sc);
3916 1.281 msaitoh break;
3917 1.304 msaitoh case WM_T_82580:
3918 1.304 msaitoh case WM_T_I350:
3919 1.304 msaitoh case WM_T_I354:
3920 1.304 msaitoh case WM_T_I210:
3921 1.304 msaitoh case WM_T_I211:
3922 1.304 msaitoh CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
3923 1.304 msaitoh if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII)
3924 1.304 msaitoh CSR_WRITE_FLUSH(sc);
3925 1.304 msaitoh delay(5000);
3926 1.304 msaitoh break;
3927 1.281 msaitoh case WM_T_82542_2_0:
3928 1.281 msaitoh case WM_T_82542_2_1:
3929 1.281 msaitoh case WM_T_82543:
3930 1.281 msaitoh case WM_T_82540:
3931 1.281 msaitoh case WM_T_82545:
3932 1.281 msaitoh case WM_T_82546:
3933 1.281 msaitoh case WM_T_82571:
3934 1.281 msaitoh case WM_T_82572:
3935 1.281 msaitoh case WM_T_82573:
3936 1.281 msaitoh case WM_T_82574:
3937 1.281 msaitoh case WM_T_82575:
3938 1.281 msaitoh case WM_T_82576:
3939 1.281 msaitoh case WM_T_82583:
3940 1.281 msaitoh default:
3941 1.281 msaitoh /* Everything else can safely use the documented method. */
3942 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
3943 1.281 msaitoh break;
3944 1.281 msaitoh }
3945 1.232 bouyer
3946 1.281 msaitoh /* Must release the MDIO ownership after MAC reset */
3947 1.281 msaitoh switch (sc->sc_type) {
3948 1.281 msaitoh case WM_T_82573:
3949 1.281 msaitoh case WM_T_82574:
3950 1.281 msaitoh case WM_T_82583:
3951 1.281 msaitoh if (error == 0)
3952 1.281 msaitoh wm_put_hw_semaphore_82573(sc);
3953 1.281 msaitoh break;
3954 1.281 msaitoh default:
3955 1.281 msaitoh break;
3956 1.232 bouyer }
3957 1.232 bouyer
3958 1.281 msaitoh if (phy_reset != 0)
3959 1.281 msaitoh wm_get_cfg_done(sc);
3960 1.232 bouyer
3961 1.281 msaitoh /* reload EEPROM */
3962 1.281 msaitoh switch (sc->sc_type) {
3963 1.281 msaitoh case WM_T_82542_2_0:
3964 1.281 msaitoh case WM_T_82542_2_1:
3965 1.281 msaitoh case WM_T_82543:
3966 1.281 msaitoh case WM_T_82544:
3967 1.281 msaitoh delay(10);
3968 1.281 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
3969 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
3970 1.281 msaitoh CSR_WRITE_FLUSH(sc);
3971 1.281 msaitoh delay(2000);
3972 1.281 msaitoh break;
3973 1.281 msaitoh case WM_T_82540:
3974 1.281 msaitoh case WM_T_82545:
3975 1.281 msaitoh case WM_T_82545_3:
3976 1.281 msaitoh case WM_T_82546:
3977 1.281 msaitoh case WM_T_82546_3:
3978 1.281 msaitoh delay(5*1000);
3979 1.281 msaitoh /* XXX Disable HW ARPs on ASF enabled adapters */
3980 1.281 msaitoh break;
3981 1.281 msaitoh case WM_T_82541:
3982 1.281 msaitoh case WM_T_82541_2:
3983 1.281 msaitoh case WM_T_82547:
3984 1.281 msaitoh case WM_T_82547_2:
3985 1.281 msaitoh delay(20000);
3986 1.281 msaitoh /* XXX Disable HW ARPs on ASF enabled adapters */
3987 1.281 msaitoh break;
3988 1.281 msaitoh case WM_T_82571:
3989 1.281 msaitoh case WM_T_82572:
3990 1.281 msaitoh case WM_T_82573:
3991 1.281 msaitoh case WM_T_82574:
3992 1.281 msaitoh case WM_T_82583:
3993 1.281 msaitoh if (sc->sc_flags & WM_F_EEPROM_FLASH) {
3994 1.281 msaitoh delay(10);
3995 1.281 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
3996 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
3997 1.281 msaitoh CSR_WRITE_FLUSH(sc);
3998 1.232 bouyer }
3999 1.281 msaitoh /* check EECD_EE_AUTORD */
4000 1.281 msaitoh wm_get_auto_rd_done(sc);
4001 1.281 msaitoh /*
4002 1.281 msaitoh * Phy configuration from NVM just starts after EECD_AUTO_RD
4003 1.281 msaitoh * is set.
4004 1.281 msaitoh */
4005 1.281 msaitoh if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574)
4006 1.281 msaitoh || (sc->sc_type == WM_T_82583))
4007 1.281 msaitoh delay(25*1000);
4008 1.281 msaitoh break;
4009 1.281 msaitoh case WM_T_82575:
4010 1.281 msaitoh case WM_T_82576:
4011 1.281 msaitoh case WM_T_82580:
4012 1.281 msaitoh case WM_T_I350:
4013 1.281 msaitoh case WM_T_I354:
4014 1.281 msaitoh case WM_T_I210:
4015 1.281 msaitoh case WM_T_I211:
4016 1.281 msaitoh case WM_T_80003:
4017 1.281 msaitoh /* check EECD_EE_AUTORD */
4018 1.281 msaitoh wm_get_auto_rd_done(sc);
4019 1.281 msaitoh break;
4020 1.281 msaitoh case WM_T_ICH8:
4021 1.281 msaitoh case WM_T_ICH9:
4022 1.281 msaitoh case WM_T_ICH10:
4023 1.281 msaitoh case WM_T_PCH:
4024 1.281 msaitoh case WM_T_PCH2:
4025 1.281 msaitoh case WM_T_PCH_LPT:
4026 1.281 msaitoh break;
4027 1.281 msaitoh default:
4028 1.281 msaitoh panic("%s: unknown type\n", __func__);
4029 1.232 bouyer }
4030 1.281 msaitoh
4031 1.281 msaitoh /* Check whether EEPROM is present or not */
4032 1.281 msaitoh switch (sc->sc_type) {
4033 1.281 msaitoh case WM_T_82575:
4034 1.281 msaitoh case WM_T_82576:
4035 1.281 msaitoh case WM_T_82580:
4036 1.281 msaitoh case WM_T_I350:
4037 1.281 msaitoh case WM_T_I354:
4038 1.281 msaitoh case WM_T_ICH8:
4039 1.281 msaitoh case WM_T_ICH9:
4040 1.281 msaitoh if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
4041 1.281 msaitoh /* Not found */
4042 1.281 msaitoh sc->sc_flags |= WM_F_EEPROM_INVALID;
4043 1.325 msaitoh if (sc->sc_type == WM_T_82575)
4044 1.281 msaitoh wm_reset_init_script_82575(sc);
4045 1.232 bouyer }
4046 1.281 msaitoh break;
4047 1.281 msaitoh default:
4048 1.281 msaitoh break;
4049 1.281 msaitoh }
4050 1.281 msaitoh
4051 1.300 msaitoh if ((sc->sc_type == WM_T_82580)
4052 1.281 msaitoh || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
4053 1.281 msaitoh /* clear global device reset status bit */
4054 1.281 msaitoh CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
4055 1.281 msaitoh }
4056 1.281 msaitoh
4057 1.281 msaitoh /* Clear any pending interrupt events. */
4058 1.281 msaitoh CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
4059 1.281 msaitoh reg = CSR_READ(sc, WMREG_ICR);
4060 1.335 msaitoh if (sc->sc_nintrs > 1) {
4061 1.335 msaitoh if (sc->sc_type != WM_T_82574) {
4062 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
4063 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAC, 0);
4064 1.335 msaitoh } else
4065 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAC_82574, 0);
4066 1.335 msaitoh }
4067 1.281 msaitoh
4068 1.281 msaitoh /* reload sc_ctrl */
4069 1.281 msaitoh sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
4070 1.281 msaitoh
4071 1.322 msaitoh if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
4072 1.281 msaitoh wm_set_eee_i350(sc);
4073 1.281 msaitoh
4074 1.281 msaitoh /* dummy read from WUC */
4075 1.281 msaitoh if (sc->sc_type == WM_T_PCH)
4076 1.281 msaitoh reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC);
4077 1.281 msaitoh /*
4078 1.281 msaitoh * For PCH, this write will make sure that any noise will be detected
4079 1.281 msaitoh * as a CRC error and be dropped rather than show up as a bad packet
4080 1.281 msaitoh * to the DMA engine
4081 1.281 msaitoh */
4082 1.281 msaitoh if (sc->sc_type == WM_T_PCH)
4083 1.281 msaitoh CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565);
4084 1.281 msaitoh
4085 1.281 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
4086 1.281 msaitoh CSR_WRITE(sc, WMREG_WUC, 0);
4087 1.281 msaitoh
4088 1.325 msaitoh wm_reset_mdicnfg_82580(sc);
4089 1.332 msaitoh
4090 1.332 msaitoh if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
4091 1.332 msaitoh wm_pll_workaround_i210(sc);
4092 1.281 msaitoh }
4093 1.281 msaitoh
4094 1.281 msaitoh /*
4095 1.281 msaitoh * wm_add_rxbuf:
4096 1.281 msaitoh *
4097 1.281 msaitoh * Add a receive buffer to the indiciated descriptor.
4098 1.281 msaitoh */
4099 1.281 msaitoh static int
4100 1.281 msaitoh wm_add_rxbuf(struct wm_softc *sc, int idx)
4101 1.281 msaitoh {
4102 1.281 msaitoh struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx];
4103 1.281 msaitoh struct mbuf *m;
4104 1.281 msaitoh int error;
4105 1.281 msaitoh
4106 1.283 ozaki KASSERT(WM_RX_LOCKED(sc));
4107 1.281 msaitoh
4108 1.281 msaitoh MGETHDR(m, M_DONTWAIT, MT_DATA);
4109 1.281 msaitoh if (m == NULL)
4110 1.281 msaitoh return ENOBUFS;
4111 1.281 msaitoh
4112 1.281 msaitoh MCLGET(m, M_DONTWAIT);
4113 1.281 msaitoh if ((m->m_flags & M_EXT) == 0) {
4114 1.281 msaitoh m_freem(m);
4115 1.281 msaitoh return ENOBUFS;
4116 1.281 msaitoh }
4117 1.281 msaitoh
4118 1.281 msaitoh if (rxs->rxs_mbuf != NULL)
4119 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
4120 1.281 msaitoh
4121 1.281 msaitoh rxs->rxs_mbuf = m;
4122 1.281 msaitoh
4123 1.281 msaitoh m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
4124 1.281 msaitoh error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
4125 1.281 msaitoh BUS_DMA_READ|BUS_DMA_NOWAIT);
4126 1.281 msaitoh if (error) {
4127 1.281 msaitoh /* XXX XXX XXX */
4128 1.281 msaitoh aprint_error_dev(sc->sc_dev,
4129 1.281 msaitoh "unable to load rx DMA map %d, error = %d\n",
4130 1.281 msaitoh idx, error);
4131 1.281 msaitoh panic("wm_add_rxbuf");
4132 1.232 bouyer }
4133 1.232 bouyer
4134 1.281 msaitoh bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
4135 1.281 msaitoh rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
4136 1.281 msaitoh
4137 1.281 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
4138 1.281 msaitoh if ((sc->sc_rctl & RCTL_EN) != 0)
4139 1.281 msaitoh WM_INIT_RXDESC(sc, idx);
4140 1.281 msaitoh } else
4141 1.281 msaitoh WM_INIT_RXDESC(sc, idx);
4142 1.281 msaitoh
4143 1.232 bouyer return 0;
4144 1.232 bouyer }
4145 1.232 bouyer
4146 1.232 bouyer /*
4147 1.281 msaitoh * wm_rxdrain:
4148 1.232 bouyer *
4149 1.281 msaitoh * Drain the receive queue.
4150 1.232 bouyer */
4151 1.232 bouyer static void
4152 1.281 msaitoh wm_rxdrain(struct wm_softc *sc)
4153 1.281 msaitoh {
4154 1.281 msaitoh struct wm_rxsoft *rxs;
4155 1.281 msaitoh int i;
4156 1.281 msaitoh
4157 1.283 ozaki KASSERT(WM_RX_LOCKED(sc));
4158 1.281 msaitoh
4159 1.281 msaitoh for (i = 0; i < WM_NRXDESC; i++) {
4160 1.281 msaitoh rxs = &sc->sc_rxsoft[i];
4161 1.281 msaitoh if (rxs->rxs_mbuf != NULL) {
4162 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
4163 1.281 msaitoh m_freem(rxs->rxs_mbuf);
4164 1.281 msaitoh rxs->rxs_mbuf = NULL;
4165 1.281 msaitoh }
4166 1.281 msaitoh }
4167 1.281 msaitoh }
4168 1.281 msaitoh
4169 1.281 msaitoh /*
4170 1.281 msaitoh * wm_init: [ifnet interface function]
4171 1.281 msaitoh *
4172 1.281 msaitoh * Initialize the interface.
4173 1.281 msaitoh */
4174 1.281 msaitoh static int
4175 1.281 msaitoh wm_init(struct ifnet *ifp)
4176 1.232 bouyer {
4177 1.232 bouyer struct wm_softc *sc = ifp->if_softc;
4178 1.281 msaitoh int ret;
4179 1.272 ozaki
4180 1.283 ozaki WM_BOTH_LOCK(sc);
4181 1.281 msaitoh ret = wm_init_locked(ifp);
4182 1.283 ozaki WM_BOTH_UNLOCK(sc);
4183 1.281 msaitoh
4184 1.281 msaitoh return ret;
4185 1.272 ozaki }
4186 1.272 ozaki
4187 1.281 msaitoh static int
4188 1.281 msaitoh wm_init_locked(struct ifnet *ifp)
4189 1.272 ozaki {
4190 1.272 ozaki struct wm_softc *sc = ifp->if_softc;
4191 1.281 msaitoh struct wm_rxsoft *rxs;
4192 1.281 msaitoh int i, j, trynum, error = 0;
4193 1.281 msaitoh uint32_t reg;
4194 1.232 bouyer
4195 1.283 ozaki KASSERT(WM_BOTH_LOCKED(sc));
4196 1.232 bouyer /*
4197 1.281 msaitoh * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
4198 1.281 msaitoh * There is a small but measurable benefit to avoiding the adjusment
4199 1.281 msaitoh * of the descriptor so that the headers are aligned, for normal mtu,
4200 1.281 msaitoh * on such platforms. One possibility is that the DMA itself is
4201 1.281 msaitoh * slightly more efficient if the front of the entire packet (instead
4202 1.281 msaitoh * of the front of the headers) is aligned.
4203 1.281 msaitoh *
4204 1.281 msaitoh * Note we must always set align_tweak to 0 if we are using
4205 1.281 msaitoh * jumbo frames.
4206 1.232 bouyer */
4207 1.281 msaitoh #ifdef __NO_STRICT_ALIGNMENT
4208 1.281 msaitoh sc->sc_align_tweak = 0;
4209 1.281 msaitoh #else
4210 1.281 msaitoh if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
4211 1.281 msaitoh sc->sc_align_tweak = 0;
4212 1.281 msaitoh else
4213 1.281 msaitoh sc->sc_align_tweak = 2;
4214 1.281 msaitoh #endif /* __NO_STRICT_ALIGNMENT */
4215 1.281 msaitoh
4216 1.281 msaitoh /* Cancel any pending I/O. */
4217 1.281 msaitoh wm_stop_locked(ifp, 0);
4218 1.281 msaitoh
4219 1.281 msaitoh /* update statistics before reset */
4220 1.281 msaitoh ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
4221 1.281 msaitoh ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
4222 1.281 msaitoh
4223 1.281 msaitoh /* Reset the chip to a known state. */
4224 1.281 msaitoh wm_reset(sc);
4225 1.281 msaitoh
4226 1.281 msaitoh switch (sc->sc_type) {
4227 1.281 msaitoh case WM_T_82571:
4228 1.281 msaitoh case WM_T_82572:
4229 1.281 msaitoh case WM_T_82573:
4230 1.281 msaitoh case WM_T_82574:
4231 1.281 msaitoh case WM_T_82583:
4232 1.281 msaitoh case WM_T_80003:
4233 1.281 msaitoh case WM_T_ICH8:
4234 1.281 msaitoh case WM_T_ICH9:
4235 1.281 msaitoh case WM_T_ICH10:
4236 1.281 msaitoh case WM_T_PCH:
4237 1.281 msaitoh case WM_T_PCH2:
4238 1.281 msaitoh case WM_T_PCH_LPT:
4239 1.281 msaitoh if (wm_check_mng_mode(sc) != 0)
4240 1.281 msaitoh wm_get_hw_control(sc);
4241 1.281 msaitoh break;
4242 1.281 msaitoh default:
4243 1.281 msaitoh break;
4244 1.281 msaitoh }
4245 1.232 bouyer
4246 1.312 msaitoh /* Init hardware bits */
4247 1.312 msaitoh wm_initialize_hardware_bits(sc);
4248 1.312 msaitoh
4249 1.281 msaitoh /* Reset the PHY. */
4250 1.281 msaitoh if (sc->sc_flags & WM_F_HAS_MII)
4251 1.281 msaitoh wm_gmii_reset(sc);
4252 1.232 bouyer
4253 1.319 msaitoh /* Calculate (E)ITR value */
4254 1.319 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
4255 1.319 msaitoh sc->sc_itr = 450; /* For EITR */
4256 1.319 msaitoh } else if (sc->sc_type >= WM_T_82543) {
4257 1.319 msaitoh /*
4258 1.319 msaitoh * Set up the interrupt throttling register (units of 256ns)
4259 1.319 msaitoh * Note that a footnote in Intel's documentation says this
4260 1.319 msaitoh * ticker runs at 1/4 the rate when the chip is in 100Mbit
4261 1.319 msaitoh * or 10Mbit mode. Empirically, it appears to be the case
4262 1.319 msaitoh * that that is also true for the 1024ns units of the other
4263 1.319 msaitoh * interrupt-related timer registers -- so, really, we ought
4264 1.319 msaitoh * to divide this value by 4 when the link speed is low.
4265 1.319 msaitoh *
4266 1.319 msaitoh * XXX implement this division at link speed change!
4267 1.319 msaitoh */
4268 1.319 msaitoh
4269 1.319 msaitoh /*
4270 1.319 msaitoh * For N interrupts/sec, set this value to:
4271 1.319 msaitoh * 1000000000 / (N * 256). Note that we set the
4272 1.319 msaitoh * absolute and packet timer values to this value
4273 1.319 msaitoh * divided by 4 to get "simple timer" behavior.
4274 1.319 msaitoh */
4275 1.319 msaitoh
4276 1.319 msaitoh sc->sc_itr = 1500; /* 2604 ints/sec */
4277 1.319 msaitoh }
4278 1.319 msaitoh
4279 1.281 msaitoh /* Initialize the transmit descriptor ring. */
4280 1.281 msaitoh memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc));
4281 1.281 msaitoh WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc),
4282 1.281 msaitoh BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
4283 1.281 msaitoh sc->sc_txfree = WM_NTXDESC(sc);
4284 1.281 msaitoh sc->sc_txnext = 0;
4285 1.272 ozaki
4286 1.281 msaitoh if (sc->sc_type < WM_T_82543) {
4287 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(sc, 0));
4288 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(sc, 0));
4289 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc));
4290 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_TDH, 0);
4291 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_TDT, 0);
4292 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
4293 1.281 msaitoh } else {
4294 1.281 msaitoh CSR_WRITE(sc, WMREG_TDBAH, WM_CDTXADDR_HI(sc, 0));
4295 1.281 msaitoh CSR_WRITE(sc, WMREG_TDBAL, WM_CDTXADDR_LO(sc, 0));
4296 1.281 msaitoh CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc));
4297 1.281 msaitoh CSR_WRITE(sc, WMREG_TDH, 0);
4298 1.232 bouyer
4299 1.281 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
4300 1.232 bouyer /*
4301 1.281 msaitoh * Don't write TDT before TCTL.EN is set.
4302 1.281 msaitoh * See the document.
4303 1.232 bouyer */
4304 1.312 msaitoh CSR_WRITE(sc, WMREG_TXDCTL(0), TXDCTL_QUEUE_ENABLE
4305 1.281 msaitoh | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0)
4306 1.281 msaitoh | TXDCTL_WTHRESH(0));
4307 1.281 msaitoh else {
4308 1.319 msaitoh /* ITR / 4 */
4309 1.319 msaitoh CSR_WRITE(sc, WMREG_TIDV, sc->sc_itr / 4);
4310 1.319 msaitoh if (sc->sc_type >= WM_T_82540) {
4311 1.319 msaitoh /* should be same */
4312 1.319 msaitoh CSR_WRITE(sc, WMREG_TADV, sc->sc_itr / 4);
4313 1.319 msaitoh }
4314 1.319 msaitoh
4315 1.281 msaitoh CSR_WRITE(sc, WMREG_TDT, 0);
4316 1.312 msaitoh CSR_WRITE(sc, WMREG_TXDCTL(0), TXDCTL_PTHRESH(0) |
4317 1.281 msaitoh TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
4318 1.281 msaitoh CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
4319 1.281 msaitoh RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
4320 1.232 bouyer }
4321 1.281 msaitoh }
4322 1.281 msaitoh
4323 1.281 msaitoh /* Initialize the transmit job descriptors. */
4324 1.281 msaitoh for (i = 0; i < WM_TXQUEUELEN(sc); i++)
4325 1.281 msaitoh sc->sc_txsoft[i].txs_mbuf = NULL;
4326 1.281 msaitoh sc->sc_txsfree = WM_TXQUEUELEN(sc);
4327 1.281 msaitoh sc->sc_txsnext = 0;
4328 1.281 msaitoh sc->sc_txsdirty = 0;
4329 1.232 bouyer
4330 1.281 msaitoh /*
4331 1.281 msaitoh * Initialize the receive descriptor and receive job
4332 1.281 msaitoh * descriptor rings.
4333 1.281 msaitoh */
4334 1.281 msaitoh if (sc->sc_type < WM_T_82543) {
4335 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0));
4336 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0));
4337 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs));
4338 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
4339 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
4340 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
4341 1.232 bouyer
4342 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
4343 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
4344 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
4345 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
4346 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
4347 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
4348 1.281 msaitoh } else {
4349 1.281 msaitoh CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0));
4350 1.281 msaitoh CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0));
4351 1.281 msaitoh CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs));
4352 1.319 msaitoh
4353 1.281 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
4354 1.281 msaitoh if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
4355 1.281 msaitoh panic("%s: MCLBYTES %d unsupported for i2575 or higher\n", __func__, MCLBYTES);
4356 1.281 msaitoh CSR_WRITE(sc, WMREG_SRRCTL, SRRCTL_DESCTYPE_LEGACY
4357 1.281 msaitoh | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
4358 1.281 msaitoh CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_QUEUE_ENABLE
4359 1.281 msaitoh | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
4360 1.281 msaitoh | RXDCTL_WTHRESH(1));
4361 1.281 msaitoh } else {
4362 1.281 msaitoh CSR_WRITE(sc, WMREG_RDH, 0);
4363 1.281 msaitoh CSR_WRITE(sc, WMREG_RDT, 0);
4364 1.348 knakahar /* ITR/4 */
4365 1.348 knakahar CSR_WRITE(sc, WMREG_RDTR, (sc->sc_itr / 4) | RDTR_FPD);
4366 1.348 knakahar /* MUST be same */
4367 1.348 knakahar CSR_WRITE(sc, WMREG_RADV, sc->sc_itr);
4368 1.281 msaitoh }
4369 1.281 msaitoh }
4370 1.281 msaitoh for (i = 0; i < WM_NRXDESC; i++) {
4371 1.281 msaitoh rxs = &sc->sc_rxsoft[i];
4372 1.281 msaitoh if (rxs->rxs_mbuf == NULL) {
4373 1.281 msaitoh if ((error = wm_add_rxbuf(sc, i)) != 0) {
4374 1.281 msaitoh log(LOG_ERR, "%s: unable to allocate or map "
4375 1.281 msaitoh "rx buffer %d, error = %d\n",
4376 1.281 msaitoh device_xname(sc->sc_dev), i, error);
4377 1.281 msaitoh /*
4378 1.281 msaitoh * XXX Should attempt to run with fewer receive
4379 1.281 msaitoh * XXX buffers instead of just failing.
4380 1.281 msaitoh */
4381 1.281 msaitoh wm_rxdrain(sc);
4382 1.281 msaitoh goto out;
4383 1.281 msaitoh }
4384 1.281 msaitoh } else {
4385 1.281 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) == 0)
4386 1.281 msaitoh WM_INIT_RXDESC(sc, i);
4387 1.232 bouyer /*
4388 1.281 msaitoh * For 82575 and newer device, the RX descriptors
4389 1.281 msaitoh * must be initialized after the setting of RCTL.EN in
4390 1.281 msaitoh * wm_set_filter()
4391 1.232 bouyer */
4392 1.232 bouyer }
4393 1.281 msaitoh }
4394 1.281 msaitoh sc->sc_rxptr = 0;
4395 1.281 msaitoh sc->sc_rxdiscard = 0;
4396 1.281 msaitoh WM_RXCHAIN_RESET(sc);
4397 1.232 bouyer
4398 1.281 msaitoh /*
4399 1.281 msaitoh * Clear out the VLAN table -- we don't use it (yet).
4400 1.281 msaitoh */
4401 1.281 msaitoh CSR_WRITE(sc, WMREG_VET, 0);
4402 1.281 msaitoh if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
4403 1.281 msaitoh trynum = 10; /* Due to hw errata */
4404 1.281 msaitoh else
4405 1.281 msaitoh trynum = 1;
4406 1.281 msaitoh for (i = 0; i < WM_VLAN_TABSIZE; i++)
4407 1.281 msaitoh for (j = 0; j < trynum; j++)
4408 1.281 msaitoh CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
4409 1.232 bouyer
4410 1.281 msaitoh /*
4411 1.281 msaitoh * Set up flow-control parameters.
4412 1.281 msaitoh *
4413 1.281 msaitoh * XXX Values could probably stand some tuning.
4414 1.281 msaitoh */
4415 1.281 msaitoh if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
4416 1.281 msaitoh && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
4417 1.281 msaitoh && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)) {
4418 1.281 msaitoh CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
4419 1.281 msaitoh CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
4420 1.281 msaitoh CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
4421 1.281 msaitoh }
4422 1.232 bouyer
4423 1.281 msaitoh sc->sc_fcrtl = FCRTL_DFLT;
4424 1.281 msaitoh if (sc->sc_type < WM_T_82543) {
4425 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
4426 1.281 msaitoh CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
4427 1.281 msaitoh } else {
4428 1.281 msaitoh CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
4429 1.281 msaitoh CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
4430 1.281 msaitoh }
4431 1.232 bouyer
4432 1.281 msaitoh if (sc->sc_type == WM_T_80003)
4433 1.281 msaitoh CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
4434 1.281 msaitoh else
4435 1.281 msaitoh CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
4436 1.232 bouyer
4437 1.281 msaitoh /* Writes the control register. */
4438 1.281 msaitoh wm_set_vlan(sc);
4439 1.232 bouyer
4440 1.281 msaitoh if (sc->sc_flags & WM_F_HAS_MII) {
4441 1.281 msaitoh int val;
4442 1.232 bouyer
4443 1.281 msaitoh switch (sc->sc_type) {
4444 1.281 msaitoh case WM_T_80003:
4445 1.281 msaitoh case WM_T_ICH8:
4446 1.281 msaitoh case WM_T_ICH9:
4447 1.281 msaitoh case WM_T_ICH10:
4448 1.281 msaitoh case WM_T_PCH:
4449 1.281 msaitoh case WM_T_PCH2:
4450 1.281 msaitoh case WM_T_PCH_LPT:
4451 1.281 msaitoh /*
4452 1.281 msaitoh * Set the mac to wait the maximum time between each
4453 1.281 msaitoh * iteration and increase the max iterations when
4454 1.281 msaitoh * polling the phy; this fixes erroneous timeouts at
4455 1.281 msaitoh * 10Mbps.
4456 1.281 msaitoh */
4457 1.281 msaitoh wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
4458 1.281 msaitoh 0xFFFF);
4459 1.281 msaitoh val = wm_kmrn_readreg(sc,
4460 1.281 msaitoh KUMCTRLSTA_OFFSET_INB_PARAM);
4461 1.281 msaitoh val |= 0x3F;
4462 1.281 msaitoh wm_kmrn_writereg(sc,
4463 1.281 msaitoh KUMCTRLSTA_OFFSET_INB_PARAM, val);
4464 1.281 msaitoh break;
4465 1.281 msaitoh default:
4466 1.281 msaitoh break;
4467 1.232 bouyer }
4468 1.232 bouyer
4469 1.281 msaitoh if (sc->sc_type == WM_T_80003) {
4470 1.281 msaitoh val = CSR_READ(sc, WMREG_CTRL_EXT);
4471 1.281 msaitoh val &= ~CTRL_EXT_LINK_MODE_MASK;
4472 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, val);
4473 1.232 bouyer
4474 1.281 msaitoh /* Bypass RX and TX FIFO's */
4475 1.281 msaitoh wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
4476 1.281 msaitoh KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
4477 1.281 msaitoh | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
4478 1.281 msaitoh wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
4479 1.281 msaitoh KUMCTRLSTA_INB_CTRL_DIS_PADDING |
4480 1.281 msaitoh KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
4481 1.232 bouyer }
4482 1.281 msaitoh }
4483 1.281 msaitoh #if 0
4484 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
4485 1.281 msaitoh #endif
4486 1.232 bouyer
4487 1.281 msaitoh /* Set up checksum offload parameters. */
4488 1.281 msaitoh reg = CSR_READ(sc, WMREG_RXCSUM);
4489 1.281 msaitoh reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
4490 1.281 msaitoh if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
4491 1.281 msaitoh reg |= RXCSUM_IPOFL;
4492 1.281 msaitoh if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
4493 1.281 msaitoh reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
4494 1.281 msaitoh if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
4495 1.281 msaitoh reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
4496 1.281 msaitoh CSR_WRITE(sc, WMREG_RXCSUM, reg);
4497 1.232 bouyer
4498 1.335 msaitoh /* Set up MSI-X */
4499 1.335 msaitoh if (sc->sc_nintrs > 1) {
4500 1.335 msaitoh uint32_t ivar;
4501 1.335 msaitoh
4502 1.335 msaitoh if (sc->sc_type == WM_T_82575) {
4503 1.335 msaitoh /* Interrupt control */
4504 1.335 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
4505 1.335 msaitoh reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;
4506 1.335 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
4507 1.335 msaitoh
4508 1.335 msaitoh /* TX */
4509 1.340 knakahar CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_TXINTR_IDX),
4510 1.335 msaitoh EITR_TX_QUEUE0);
4511 1.335 msaitoh /* RX */
4512 1.340 knakahar CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_RXINTR_IDX),
4513 1.335 msaitoh EITR_RX_QUEUE0);
4514 1.335 msaitoh /* Link status */
4515 1.340 knakahar CSR_WRITE(sc, WMREG_MSIXBM(WM_MSIX_LINKINTR_IDX),
4516 1.335 msaitoh EITR_OTHER);
4517 1.335 msaitoh } else if (sc->sc_type == WM_T_82574) {
4518 1.335 msaitoh /* Interrupt control */
4519 1.335 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
4520 1.335 msaitoh reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;
4521 1.335 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
4522 1.335 msaitoh
4523 1.335 msaitoh /* TX, RX and Link status */
4524 1.340 knakahar ivar = __SHIFTIN((IVAR_VALID_82574|WM_MSIX_TXINTR_IDX),
4525 1.335 msaitoh IVAR_TX_MASK_Q_82574(0));
4526 1.340 knakahar ivar |= __SHIFTIN((IVAR_VALID_82574
4527 1.340 knakahar | WM_MSIX_RXINTR_IDX),
4528 1.335 msaitoh IVAR_RX_MASK_Q_82574(0));
4529 1.340 knakahar ivar |=__SHIFTIN((IVAR_VALID_82574|WM_MSIX_LINKINTR_IDX),
4530 1.335 msaitoh IVAR_OTHER_MASK);
4531 1.335 msaitoh CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
4532 1.335 msaitoh } else {
4533 1.335 msaitoh /* Interrupt control */
4534 1.335 msaitoh CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR
4535 1.335 msaitoh | GPIE_MULTI_MSIX | GPIE_EIAME
4536 1.335 msaitoh | GPIE_PBA);
4537 1.335 msaitoh
4538 1.335 msaitoh switch (sc->sc_type) {
4539 1.335 msaitoh case WM_T_82580:
4540 1.335 msaitoh case WM_T_I350:
4541 1.335 msaitoh case WM_T_I354:
4542 1.335 msaitoh case WM_T_I210:
4543 1.335 msaitoh case WM_T_I211:
4544 1.335 msaitoh /* TX */
4545 1.335 msaitoh ivar = CSR_READ(sc, WMREG_IVAR_Q(0));
4546 1.335 msaitoh ivar &= ~IVAR_TX_MASK_Q(0);
4547 1.335 msaitoh ivar |= __SHIFTIN(
4548 1.340 knakahar (WM_MSIX_TXINTR_IDX | IVAR_VALID),
4549 1.335 msaitoh IVAR_TX_MASK_Q(0));
4550 1.335 msaitoh CSR_WRITE(sc, WMREG_IVAR_Q(0), ivar);
4551 1.335 msaitoh
4552 1.335 msaitoh /* RX */
4553 1.335 msaitoh ivar = CSR_READ(sc, WMREG_IVAR_Q(0));
4554 1.335 msaitoh ivar &= ~IVAR_RX_MASK_Q(0);
4555 1.335 msaitoh ivar |= __SHIFTIN(
4556 1.340 knakahar (WM_MSIX_RXINTR_IDX | IVAR_VALID),
4557 1.335 msaitoh IVAR_RX_MASK_Q(0));
4558 1.335 msaitoh CSR_WRITE(sc, WMREG_IVAR_Q(0), ivar);
4559 1.335 msaitoh break;
4560 1.335 msaitoh case WM_T_82576:
4561 1.335 msaitoh /* TX */
4562 1.335 msaitoh ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(0));
4563 1.335 msaitoh ivar &= ~IVAR_TX_MASK_Q_82576(0);
4564 1.335 msaitoh ivar |= __SHIFTIN(
4565 1.340 knakahar (WM_MSIX_TXINTR_IDX | IVAR_VALID),
4566 1.335 msaitoh IVAR_TX_MASK_Q_82576(0));
4567 1.335 msaitoh CSR_WRITE(sc, WMREG_IVAR_Q_82576(0), ivar);
4568 1.335 msaitoh
4569 1.335 msaitoh /* RX */
4570 1.335 msaitoh ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(0));
4571 1.335 msaitoh ivar &= ~IVAR_RX_MASK_Q_82576(0);
4572 1.335 msaitoh ivar |= __SHIFTIN(
4573 1.340 knakahar (WM_MSIX_RXINTR_IDX | IVAR_VALID),
4574 1.335 msaitoh IVAR_RX_MASK_Q_82576(0));
4575 1.335 msaitoh CSR_WRITE(sc, WMREG_IVAR_Q_82576(0), ivar);
4576 1.335 msaitoh break;
4577 1.335 msaitoh default:
4578 1.335 msaitoh break;
4579 1.335 msaitoh }
4580 1.335 msaitoh
4581 1.335 msaitoh /* Link status */
4582 1.340 knakahar ivar = __SHIFTIN((WM_MSIX_LINKINTR_IDX | IVAR_VALID),
4583 1.335 msaitoh IVAR_MISC_OTHER);
4584 1.335 msaitoh CSR_WRITE(sc, WMREG_IVAR_MISC, ivar);
4585 1.335 msaitoh }
4586 1.335 msaitoh }
4587 1.335 msaitoh
4588 1.281 msaitoh /* Set up the interrupt registers. */
4589 1.281 msaitoh CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
4590 1.281 msaitoh sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
4591 1.281 msaitoh ICR_RXO | ICR_RXT0;
4592 1.335 msaitoh if (sc->sc_nintrs > 1) {
4593 1.335 msaitoh uint32_t mask;
4594 1.335 msaitoh switch (sc->sc_type) {
4595 1.335 msaitoh case WM_T_82574:
4596 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAC_82574,
4597 1.335 msaitoh WMREG_EIAC_82574_MSIX_MASK);
4598 1.335 msaitoh sc->sc_icr |= WMREG_EIAC_82574_MSIX_MASK;
4599 1.335 msaitoh CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
4600 1.335 msaitoh break;
4601 1.335 msaitoh default:
4602 1.335 msaitoh if (sc->sc_type == WM_T_82575)
4603 1.335 msaitoh mask = EITR_RX_QUEUE0 |EITR_TX_QUEUE0
4604 1.335 msaitoh | EITR_OTHER;
4605 1.335 msaitoh else
4606 1.340 knakahar mask = (1 << WM_MSIX_RXINTR_IDX)
4607 1.340 knakahar | (1 << WM_MSIX_TXINTR_IDX)
4608 1.340 knakahar | (1 << WM_MSIX_LINKINTR_IDX);
4609 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAC, mask);
4610 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAM, mask);
4611 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMS, mask);
4612 1.335 msaitoh CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
4613 1.335 msaitoh break;
4614 1.335 msaitoh }
4615 1.335 msaitoh } else
4616 1.335 msaitoh CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
4617 1.232 bouyer
4618 1.281 msaitoh if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
4619 1.281 msaitoh || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
4620 1.281 msaitoh || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
4621 1.281 msaitoh reg = CSR_READ(sc, WMREG_KABGTXD);
4622 1.281 msaitoh reg |= KABGTXD_BGSQLBIAS;
4623 1.281 msaitoh CSR_WRITE(sc, WMREG_KABGTXD, reg);
4624 1.281 msaitoh }
4625 1.232 bouyer
4626 1.281 msaitoh /* Set up the inter-packet gap. */
4627 1.281 msaitoh CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
4628 1.232 bouyer
4629 1.281 msaitoh if (sc->sc_type >= WM_T_82543) {
4630 1.281 msaitoh /*
4631 1.319 msaitoh * XXX 82574 has both ITR and EITR. SET EITR when we use
4632 1.319 msaitoh * the multi queue function with MSI-X.
4633 1.281 msaitoh */
4634 1.349 knakahar if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
4635 1.349 knakahar if (sc->sc_nintrs > 1) {
4636 1.349 knakahar CSR_WRITE(sc, WMREG_EITR(WM_MSIX_RXINTR_IDX),
4637 1.349 knakahar sc->sc_itr);
4638 1.349 knakahar CSR_WRITE(sc, WMREG_EITR(WM_MSIX_TXINTR_IDX),
4639 1.349 knakahar sc->sc_itr);
4640 1.349 knakahar /*
4641 1.349 knakahar * Link interrupts occur much less than TX
4642 1.349 knakahar * interrupts and RX interrupts. So, we don't
4643 1.349 knakahar * tune EINTR(WM_MSIX_LINKINTR_IDX) value like
4644 1.349 knakahar * FreeBSD's if_igb.
4645 1.349 knakahar */
4646 1.349 knakahar } else
4647 1.349 knakahar CSR_WRITE(sc, WMREG_EITR(0), sc->sc_itr);
4648 1.349 knakahar } else
4649 1.319 msaitoh CSR_WRITE(sc, WMREG_ITR, sc->sc_itr);
4650 1.281 msaitoh }
4651 1.232 bouyer
4652 1.281 msaitoh /* Set the VLAN ethernetype. */
4653 1.281 msaitoh CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
4654 1.232 bouyer
4655 1.281 msaitoh /*
4656 1.281 msaitoh * Set up the transmit control register; we start out with
4657 1.281 msaitoh * a collision distance suitable for FDX, but update it whe
4658 1.281 msaitoh * we resolve the media type.
4659 1.281 msaitoh */
4660 1.281 msaitoh sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
4661 1.281 msaitoh | TCTL_CT(TX_COLLISION_THRESHOLD)
4662 1.281 msaitoh | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
4663 1.281 msaitoh if (sc->sc_type >= WM_T_82571)
4664 1.281 msaitoh sc->sc_tctl |= TCTL_MULR;
4665 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
4666 1.232 bouyer
4667 1.281 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
4668 1.281 msaitoh /* Write TDT after TCTL.EN is set. See the document. */
4669 1.281 msaitoh CSR_WRITE(sc, WMREG_TDT, 0);
4670 1.232 bouyer }
4671 1.232 bouyer
4672 1.281 msaitoh if (sc->sc_type == WM_T_80003) {
4673 1.281 msaitoh reg = CSR_READ(sc, WMREG_TCTL_EXT);
4674 1.281 msaitoh reg &= ~TCTL_EXT_GCEX_MASK;
4675 1.281 msaitoh reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
4676 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
4677 1.272 ozaki }
4678 1.272 ozaki
4679 1.281 msaitoh /* Set the media. */
4680 1.281 msaitoh if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
4681 1.281 msaitoh goto out;
4682 1.281 msaitoh
4683 1.281 msaitoh /* Configure for OS presence */
4684 1.281 msaitoh wm_init_manageability(sc);
4685 1.232 bouyer
4686 1.281 msaitoh /*
4687 1.281 msaitoh * Set up the receive control register; we actually program
4688 1.281 msaitoh * the register when we set the receive filter. Use multicast
4689 1.281 msaitoh * address offset type 0.
4690 1.281 msaitoh *
4691 1.281 msaitoh * Only the i82544 has the ability to strip the incoming
4692 1.281 msaitoh * CRC, so we don't enable that feature.
4693 1.281 msaitoh */
4694 1.281 msaitoh sc->sc_mchash_type = 0;
4695 1.281 msaitoh sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
4696 1.281 msaitoh | RCTL_MO(sc->sc_mchash_type);
4697 1.281 msaitoh
4698 1.281 msaitoh /*
4699 1.281 msaitoh * The I350 has a bug where it always strips the CRC whether
4700 1.281 msaitoh * asked to or not. So ask for stripped CRC here and cope in rxeof
4701 1.281 msaitoh */
4702 1.281 msaitoh if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
4703 1.281 msaitoh || (sc->sc_type == WM_T_I210))
4704 1.281 msaitoh sc->sc_rctl |= RCTL_SECRC;
4705 1.281 msaitoh
4706 1.281 msaitoh if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
4707 1.281 msaitoh && (ifp->if_mtu > ETHERMTU)) {
4708 1.281 msaitoh sc->sc_rctl |= RCTL_LPE;
4709 1.281 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
4710 1.281 msaitoh CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
4711 1.281 msaitoh }
4712 1.281 msaitoh
4713 1.281 msaitoh if (MCLBYTES == 2048) {
4714 1.281 msaitoh sc->sc_rctl |= RCTL_2k;
4715 1.281 msaitoh } else {
4716 1.281 msaitoh if (sc->sc_type >= WM_T_82543) {
4717 1.281 msaitoh switch (MCLBYTES) {
4718 1.281 msaitoh case 4096:
4719 1.281 msaitoh sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
4720 1.281 msaitoh break;
4721 1.281 msaitoh case 8192:
4722 1.281 msaitoh sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
4723 1.281 msaitoh break;
4724 1.281 msaitoh case 16384:
4725 1.281 msaitoh sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
4726 1.281 msaitoh break;
4727 1.281 msaitoh default:
4728 1.281 msaitoh panic("wm_init: MCLBYTES %d unsupported",
4729 1.281 msaitoh MCLBYTES);
4730 1.281 msaitoh break;
4731 1.281 msaitoh }
4732 1.281 msaitoh } else panic("wm_init: i82542 requires MCLBYTES = 2048");
4733 1.281 msaitoh }
4734 1.281 msaitoh
4735 1.281 msaitoh /* Set the receive filter. */
4736 1.281 msaitoh wm_set_filter(sc);
4737 1.281 msaitoh
4738 1.281 msaitoh /* Enable ECC */
4739 1.281 msaitoh switch (sc->sc_type) {
4740 1.281 msaitoh case WM_T_82571:
4741 1.281 msaitoh reg = CSR_READ(sc, WMREG_PBA_ECC);
4742 1.281 msaitoh reg |= PBA_ECC_CORR_EN;
4743 1.281 msaitoh CSR_WRITE(sc, WMREG_PBA_ECC, reg);
4744 1.281 msaitoh break;
4745 1.281 msaitoh case WM_T_PCH_LPT:
4746 1.281 msaitoh reg = CSR_READ(sc, WMREG_PBECCSTS);
4747 1.281 msaitoh reg |= PBECCSTS_UNCORR_ECC_ENABLE;
4748 1.281 msaitoh CSR_WRITE(sc, WMREG_PBECCSTS, reg);
4749 1.281 msaitoh
4750 1.281 msaitoh reg = CSR_READ(sc, WMREG_CTRL);
4751 1.281 msaitoh reg |= CTRL_MEHE;
4752 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, reg);
4753 1.281 msaitoh break;
4754 1.281 msaitoh default:
4755 1.281 msaitoh break;
4756 1.232 bouyer }
4757 1.281 msaitoh
4758 1.281 msaitoh /* On 575 and later set RDT only if RX enabled */
4759 1.281 msaitoh if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
4760 1.281 msaitoh for (i = 0; i < WM_NRXDESC; i++)
4761 1.281 msaitoh WM_INIT_RXDESC(sc, i);
4762 1.281 msaitoh
4763 1.281 msaitoh sc->sc_stopping = false;
4764 1.281 msaitoh
4765 1.281 msaitoh /* Start the one second link check clock. */
4766 1.281 msaitoh callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
4767 1.281 msaitoh
4768 1.281 msaitoh /* ...all done! */
4769 1.281 msaitoh ifp->if_flags |= IFF_RUNNING;
4770 1.281 msaitoh ifp->if_flags &= ~IFF_OACTIVE;
4771 1.281 msaitoh
4772 1.281 msaitoh out:
4773 1.281 msaitoh sc->sc_if_flags = ifp->if_flags;
4774 1.281 msaitoh if (error)
4775 1.281 msaitoh log(LOG_ERR, "%s: interface not running\n",
4776 1.281 msaitoh device_xname(sc->sc_dev));
4777 1.281 msaitoh return error;
4778 1.232 bouyer }
4779 1.232 bouyer
4780 1.232 bouyer /*
4781 1.281 msaitoh * wm_stop: [ifnet interface function]
4782 1.1 thorpej *
4783 1.281 msaitoh * Stop transmission on the interface.
4784 1.1 thorpej */
4785 1.47 thorpej static void
4786 1.281 msaitoh wm_stop(struct ifnet *ifp, int disable)
4787 1.1 thorpej {
4788 1.1 thorpej struct wm_softc *sc = ifp->if_softc;
4789 1.1 thorpej
4790 1.283 ozaki WM_BOTH_LOCK(sc);
4791 1.281 msaitoh wm_stop_locked(ifp, disable);
4792 1.283 ozaki WM_BOTH_UNLOCK(sc);
4793 1.1 thorpej }
4794 1.1 thorpej
4795 1.281 msaitoh static void
4796 1.281 msaitoh wm_stop_locked(struct ifnet *ifp, int disable)
4797 1.213 msaitoh {
4798 1.213 msaitoh struct wm_softc *sc = ifp->if_softc;
4799 1.281 msaitoh struct wm_txsoft *txs;
4800 1.281 msaitoh int i;
4801 1.281 msaitoh
4802 1.283 ozaki KASSERT(WM_BOTH_LOCKED(sc));
4803 1.281 msaitoh
4804 1.281 msaitoh sc->sc_stopping = true;
4805 1.272 ozaki
4806 1.281 msaitoh /* Stop the one second clock. */
4807 1.281 msaitoh callout_stop(&sc->sc_tick_ch);
4808 1.213 msaitoh
4809 1.281 msaitoh /* Stop the 82547 Tx FIFO stall check timer. */
4810 1.281 msaitoh if (sc->sc_type == WM_T_82547)
4811 1.281 msaitoh callout_stop(&sc->sc_txfifo_ch);
4812 1.217 dyoung
4813 1.281 msaitoh if (sc->sc_flags & WM_F_HAS_MII) {
4814 1.281 msaitoh /* Down the MII. */
4815 1.281 msaitoh mii_down(&sc->sc_mii);
4816 1.281 msaitoh } else {
4817 1.281 msaitoh #if 0
4818 1.281 msaitoh /* Should we clear PHY's status properly? */
4819 1.281 msaitoh wm_reset(sc);
4820 1.281 msaitoh #endif
4821 1.272 ozaki }
4822 1.213 msaitoh
4823 1.281 msaitoh /* Stop the transmit and receive processes. */
4824 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL, 0);
4825 1.281 msaitoh CSR_WRITE(sc, WMREG_RCTL, 0);
4826 1.281 msaitoh sc->sc_rctl &= ~RCTL_EN;
4827 1.281 msaitoh
4828 1.281 msaitoh /*
4829 1.281 msaitoh * Clear the interrupt mask to ensure the device cannot assert its
4830 1.281 msaitoh * interrupt line.
4831 1.335 msaitoh * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to
4832 1.335 msaitoh * service any currently pending or shared interrupt.
4833 1.281 msaitoh */
4834 1.281 msaitoh CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
4835 1.281 msaitoh sc->sc_icr = 0;
4836 1.335 msaitoh if (sc->sc_nintrs > 1) {
4837 1.335 msaitoh if (sc->sc_type != WM_T_82574) {
4838 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
4839 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAC, 0);
4840 1.335 msaitoh } else
4841 1.335 msaitoh CSR_WRITE(sc, WMREG_EIAC_82574, 0);
4842 1.335 msaitoh }
4843 1.281 msaitoh
4844 1.281 msaitoh /* Release any queued transmit buffers. */
4845 1.281 msaitoh for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
4846 1.281 msaitoh txs = &sc->sc_txsoft[i];
4847 1.281 msaitoh if (txs->txs_mbuf != NULL) {
4848 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
4849 1.281 msaitoh m_freem(txs->txs_mbuf);
4850 1.281 msaitoh txs->txs_mbuf = NULL;
4851 1.281 msaitoh }
4852 1.281 msaitoh }
4853 1.217 dyoung
4854 1.281 msaitoh /* Mark the interface as down and cancel the watchdog timer. */
4855 1.281 msaitoh ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
4856 1.281 msaitoh ifp->if_timer = 0;
4857 1.213 msaitoh
4858 1.281 msaitoh if (disable)
4859 1.281 msaitoh wm_rxdrain(sc);
4860 1.272 ozaki
4861 1.281 msaitoh #if 0 /* notyet */
4862 1.281 msaitoh if (sc->sc_type >= WM_T_82544)
4863 1.281 msaitoh CSR_WRITE(sc, WMREG_WUC, 0);
4864 1.281 msaitoh #endif
4865 1.213 msaitoh }
4866 1.213 msaitoh
4867 1.1 thorpej /*
4868 1.281 msaitoh * wm_tx_offload:
4869 1.1 thorpej *
4870 1.281 msaitoh * Set up TCP/IP checksumming parameters for the
4871 1.281 msaitoh * specified packet.
4872 1.1 thorpej */
4873 1.47 thorpej static int
4874 1.281 msaitoh wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp,
4875 1.281 msaitoh uint8_t *fieldsp)
4876 1.1 thorpej {
4877 1.281 msaitoh struct mbuf *m0 = txs->txs_mbuf;
4878 1.281 msaitoh struct livengood_tcpip_ctxdesc *t;
4879 1.281 msaitoh uint32_t ipcs, tucs, cmd, cmdlen, seg;
4880 1.281 msaitoh uint32_t ipcse;
4881 1.281 msaitoh struct ether_header *eh;
4882 1.281 msaitoh int offset, iphl;
4883 1.281 msaitoh uint8_t fields;
4884 1.281 msaitoh
4885 1.281 msaitoh /*
4886 1.281 msaitoh * XXX It would be nice if the mbuf pkthdr had offset
4887 1.281 msaitoh * fields for the protocol headers.
4888 1.281 msaitoh */
4889 1.281 msaitoh
4890 1.281 msaitoh eh = mtod(m0, struct ether_header *);
4891 1.281 msaitoh switch (htons(eh->ether_type)) {
4892 1.281 msaitoh case ETHERTYPE_IP:
4893 1.281 msaitoh case ETHERTYPE_IPV6:
4894 1.281 msaitoh offset = ETHER_HDR_LEN;
4895 1.281 msaitoh break;
4896 1.1 thorpej
4897 1.281 msaitoh case ETHERTYPE_VLAN:
4898 1.281 msaitoh offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
4899 1.281 msaitoh break;
4900 1.1 thorpej
4901 1.281 msaitoh default:
4902 1.281 msaitoh /*
4903 1.281 msaitoh * Don't support this protocol or encapsulation.
4904 1.281 msaitoh */
4905 1.281 msaitoh *fieldsp = 0;
4906 1.281 msaitoh *cmdp = 0;
4907 1.281 msaitoh return 0;
4908 1.281 msaitoh }
4909 1.281 msaitoh
4910 1.281 msaitoh if ((m0->m_pkthdr.csum_flags &
4911 1.281 msaitoh (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) {
4912 1.281 msaitoh iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
4913 1.281 msaitoh } else {
4914 1.281 msaitoh iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
4915 1.281 msaitoh }
4916 1.281 msaitoh ipcse = offset + iphl - 1;
4917 1.272 ozaki
4918 1.281 msaitoh cmd = WTX_CMD_DEXT | WTX_DTYP_D;
4919 1.281 msaitoh cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
4920 1.281 msaitoh seg = 0;
4921 1.281 msaitoh fields = 0;
4922 1.154 dyoung
4923 1.281 msaitoh if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
4924 1.281 msaitoh int hlen = offset + iphl;
4925 1.281 msaitoh bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
4926 1.154 dyoung
4927 1.281 msaitoh if (__predict_false(m0->m_len <
4928 1.281 msaitoh (hlen + sizeof(struct tcphdr)))) {
4929 1.1 thorpej /*
4930 1.281 msaitoh * TCP/IP headers are not in the first mbuf; we need
4931 1.281 msaitoh * to do this the slow and painful way. Let's just
4932 1.281 msaitoh * hope this doesn't happen very often.
4933 1.1 thorpej */
4934 1.281 msaitoh struct tcphdr th;
4935 1.281 msaitoh
4936 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtsopain);
4937 1.1 thorpej
4938 1.281 msaitoh m_copydata(m0, hlen, sizeof(th), &th);
4939 1.281 msaitoh if (v4) {
4940 1.281 msaitoh struct ip ip;
4941 1.272 ozaki
4942 1.281 msaitoh m_copydata(m0, offset, sizeof(ip), &ip);
4943 1.281 msaitoh ip.ip_len = 0;
4944 1.281 msaitoh m_copyback(m0,
4945 1.281 msaitoh offset + offsetof(struct ip, ip_len),
4946 1.281 msaitoh sizeof(ip.ip_len), &ip.ip_len);
4947 1.281 msaitoh th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
4948 1.281 msaitoh ip.ip_dst.s_addr, htons(IPPROTO_TCP));
4949 1.281 msaitoh } else {
4950 1.281 msaitoh struct ip6_hdr ip6;
4951 1.1 thorpej
4952 1.281 msaitoh m_copydata(m0, offset, sizeof(ip6), &ip6);
4953 1.281 msaitoh ip6.ip6_plen = 0;
4954 1.281 msaitoh m_copyback(m0,
4955 1.281 msaitoh offset + offsetof(struct ip6_hdr, ip6_plen),
4956 1.281 msaitoh sizeof(ip6.ip6_plen), &ip6.ip6_plen);
4957 1.281 msaitoh th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
4958 1.281 msaitoh &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
4959 1.281 msaitoh }
4960 1.281 msaitoh m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
4961 1.281 msaitoh sizeof(th.th_sum), &th.th_sum);
4962 1.1 thorpej
4963 1.281 msaitoh hlen += th.th_off << 2;
4964 1.281 msaitoh } else {
4965 1.281 msaitoh /*
4966 1.281 msaitoh * TCP/IP headers are in the first mbuf; we can do
4967 1.281 msaitoh * this the easy way.
4968 1.281 msaitoh */
4969 1.281 msaitoh struct tcphdr *th;
4970 1.1 thorpej
4971 1.281 msaitoh if (v4) {
4972 1.281 msaitoh struct ip *ip =
4973 1.281 msaitoh (void *)(mtod(m0, char *) + offset);
4974 1.281 msaitoh th = (void *)(mtod(m0, char *) + hlen);
4975 1.1 thorpej
4976 1.281 msaitoh ip->ip_len = 0;
4977 1.281 msaitoh th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
4978 1.281 msaitoh ip->ip_dst.s_addr, htons(IPPROTO_TCP));
4979 1.281 msaitoh } else {
4980 1.281 msaitoh struct ip6_hdr *ip6 =
4981 1.281 msaitoh (void *)(mtod(m0, char *) + offset);
4982 1.281 msaitoh th = (void *)(mtod(m0, char *) + hlen);
4983 1.272 ozaki
4984 1.281 msaitoh ip6->ip6_plen = 0;
4985 1.281 msaitoh th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
4986 1.281 msaitoh &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
4987 1.281 msaitoh }
4988 1.281 msaitoh hlen += th->th_off << 2;
4989 1.272 ozaki }
4990 1.272 ozaki
4991 1.281 msaitoh if (v4) {
4992 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtso);
4993 1.281 msaitoh cmdlen |= WTX_TCPIP_CMD_IP;
4994 1.281 msaitoh } else {
4995 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtso6);
4996 1.281 msaitoh ipcse = 0;
4997 1.1 thorpej }
4998 1.281 msaitoh cmd |= WTX_TCPIP_CMD_TSE;
4999 1.281 msaitoh cmdlen |= WTX_TCPIP_CMD_TSE |
5000 1.281 msaitoh WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
5001 1.281 msaitoh seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
5002 1.281 msaitoh WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
5003 1.281 msaitoh }
5004 1.1 thorpej
5005 1.281 msaitoh /*
5006 1.281 msaitoh * NOTE: Even if we're not using the IP or TCP/UDP checksum
5007 1.281 msaitoh * offload feature, if we load the context descriptor, we
5008 1.281 msaitoh * MUST provide valid values for IPCSS and TUCSS fields.
5009 1.281 msaitoh */
5010 1.1 thorpej
5011 1.281 msaitoh ipcs = WTX_TCPIP_IPCSS(offset) |
5012 1.281 msaitoh WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
5013 1.281 msaitoh WTX_TCPIP_IPCSE(ipcse);
5014 1.281 msaitoh if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) {
5015 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txipsum);
5016 1.281 msaitoh fields |= WTX_IXSM;
5017 1.281 msaitoh }
5018 1.1 thorpej
5019 1.281 msaitoh offset += iphl;
5020 1.272 ozaki
5021 1.281 msaitoh if (m0->m_pkthdr.csum_flags &
5022 1.281 msaitoh (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) {
5023 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtusum);
5024 1.281 msaitoh fields |= WTX_TXSM;
5025 1.281 msaitoh tucs = WTX_TCPIP_TUCSS(offset) |
5026 1.281 msaitoh WTX_TCPIP_TUCSO(offset +
5027 1.281 msaitoh M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
5028 1.281 msaitoh WTX_TCPIP_TUCSE(0) /* rest of packet */;
5029 1.281 msaitoh } else if ((m0->m_pkthdr.csum_flags &
5030 1.281 msaitoh (M_CSUM_TCPv6|M_CSUM_UDPv6|M_CSUM_TSOv6)) != 0) {
5031 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtusum6);
5032 1.281 msaitoh fields |= WTX_TXSM;
5033 1.281 msaitoh tucs = WTX_TCPIP_TUCSS(offset) |
5034 1.281 msaitoh WTX_TCPIP_TUCSO(offset +
5035 1.281 msaitoh M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
5036 1.281 msaitoh WTX_TCPIP_TUCSE(0) /* rest of packet */;
5037 1.281 msaitoh } else {
5038 1.281 msaitoh /* Just initialize it to a valid TCP context. */
5039 1.281 msaitoh tucs = WTX_TCPIP_TUCSS(offset) |
5040 1.281 msaitoh WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
5041 1.281 msaitoh WTX_TCPIP_TUCSE(0) /* rest of packet */;
5042 1.1 thorpej }
5043 1.1 thorpej
5044 1.281 msaitoh /* Fill in the context descriptor. */
5045 1.281 msaitoh t = (struct livengood_tcpip_ctxdesc *)
5046 1.281 msaitoh &sc->sc_txdescs[sc->sc_txnext];
5047 1.281 msaitoh t->tcpip_ipcs = htole32(ipcs);
5048 1.281 msaitoh t->tcpip_tucs = htole32(tucs);
5049 1.281 msaitoh t->tcpip_cmdlen = htole32(cmdlen);
5050 1.281 msaitoh t->tcpip_seg = htole32(seg);
5051 1.281 msaitoh WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE);
5052 1.281 msaitoh
5053 1.281 msaitoh sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext);
5054 1.281 msaitoh txs->txs_ndesc++;
5055 1.281 msaitoh
5056 1.281 msaitoh *cmdp = cmd;
5057 1.281 msaitoh *fieldsp = fields;
5058 1.1 thorpej
5059 1.281 msaitoh return 0;
5060 1.1 thorpej }
5061 1.1 thorpej
5062 1.47 thorpej static void
5063 1.281 msaitoh wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
5064 1.1 thorpej {
5065 1.281 msaitoh struct mbuf *m;
5066 1.1 thorpej int i;
5067 1.1 thorpej
5068 1.281 msaitoh log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev));
5069 1.281 msaitoh for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
5070 1.281 msaitoh log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
5071 1.281 msaitoh "m_flags = 0x%08x\n", device_xname(sc->sc_dev),
5072 1.281 msaitoh m->m_data, m->m_len, m->m_flags);
5073 1.281 msaitoh log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev),
5074 1.281 msaitoh i, i == 1 ? "" : "s");
5075 1.281 msaitoh }
5076 1.272 ozaki
5077 1.281 msaitoh /*
5078 1.281 msaitoh * wm_82547_txfifo_stall:
5079 1.281 msaitoh *
5080 1.281 msaitoh * Callout used to wait for the 82547 Tx FIFO to drain,
5081 1.281 msaitoh * reset the FIFO pointers, and restart packet transmission.
5082 1.281 msaitoh */
5083 1.281 msaitoh static void
5084 1.281 msaitoh wm_82547_txfifo_stall(void *arg)
5085 1.281 msaitoh {
5086 1.281 msaitoh struct wm_softc *sc = arg;
5087 1.281 msaitoh #ifndef WM_MPSAFE
5088 1.281 msaitoh int s;
5089 1.1 thorpej
5090 1.281 msaitoh s = splnet();
5091 1.281 msaitoh #endif
5092 1.283 ozaki WM_TX_LOCK(sc);
5093 1.1 thorpej
5094 1.281 msaitoh if (sc->sc_stopping)
5095 1.281 msaitoh goto out;
5096 1.1 thorpej
5097 1.281 msaitoh if (sc->sc_txfifo_stall) {
5098 1.281 msaitoh if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) &&
5099 1.281 msaitoh CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
5100 1.281 msaitoh CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
5101 1.281 msaitoh /*
5102 1.281 msaitoh * Packets have drained. Stop transmitter, reset
5103 1.281 msaitoh * FIFO pointers, restart transmitter, and kick
5104 1.281 msaitoh * the packet queue.
5105 1.281 msaitoh */
5106 1.281 msaitoh uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
5107 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
5108 1.281 msaitoh CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr);
5109 1.281 msaitoh CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr);
5110 1.281 msaitoh CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr);
5111 1.281 msaitoh CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr);
5112 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL, tctl);
5113 1.281 msaitoh CSR_WRITE_FLUSH(sc);
5114 1.1 thorpej
5115 1.281 msaitoh sc->sc_txfifo_head = 0;
5116 1.281 msaitoh sc->sc_txfifo_stall = 0;
5117 1.281 msaitoh wm_start_locked(&sc->sc_ethercom.ec_if);
5118 1.281 msaitoh } else {
5119 1.281 msaitoh /*
5120 1.281 msaitoh * Still waiting for packets to drain; try again in
5121 1.281 msaitoh * another tick.
5122 1.281 msaitoh */
5123 1.281 msaitoh callout_schedule(&sc->sc_txfifo_ch, 1);
5124 1.20 thorpej }
5125 1.281 msaitoh }
5126 1.1 thorpej
5127 1.281 msaitoh out:
5128 1.283 ozaki WM_TX_UNLOCK(sc);
5129 1.281 msaitoh #ifndef WM_MPSAFE
5130 1.281 msaitoh splx(s);
5131 1.281 msaitoh #endif
5132 1.281 msaitoh }
5133 1.1 thorpej
5134 1.281 msaitoh /*
5135 1.281 msaitoh * wm_82547_txfifo_bugchk:
5136 1.281 msaitoh *
5137 1.281 msaitoh * Check for bug condition in the 82547 Tx FIFO. We need to
5138 1.281 msaitoh * prevent enqueueing a packet that would wrap around the end
5139 1.281 msaitoh * if the Tx FIFO ring buffer, otherwise the chip will croak.
5140 1.281 msaitoh *
5141 1.281 msaitoh * We do this by checking the amount of space before the end
5142 1.281 msaitoh * of the Tx FIFO buffer. If the packet will not fit, we "stall"
5143 1.281 msaitoh * the Tx FIFO, wait for all remaining packets to drain, reset
5144 1.281 msaitoh * the internal FIFO pointers to the beginning, and restart
5145 1.281 msaitoh * transmission on the interface.
5146 1.281 msaitoh */
5147 1.281 msaitoh #define WM_FIFO_HDR 0x10
5148 1.281 msaitoh #define WM_82547_PAD_LEN 0x3e0
5149 1.281 msaitoh static int
5150 1.281 msaitoh wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
5151 1.281 msaitoh {
5152 1.281 msaitoh int space = sc->sc_txfifo_size - sc->sc_txfifo_head;
5153 1.281 msaitoh int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
5154 1.1 thorpej
5155 1.281 msaitoh /* Just return if already stalled. */
5156 1.281 msaitoh if (sc->sc_txfifo_stall)
5157 1.281 msaitoh return 1;
5158 1.1 thorpej
5159 1.281 msaitoh if (sc->sc_mii.mii_media_active & IFM_FDX) {
5160 1.281 msaitoh /* Stall only occurs in half-duplex mode. */
5161 1.281 msaitoh goto send_packet;
5162 1.281 msaitoh }
5163 1.1 thorpej
5164 1.281 msaitoh if (len >= WM_82547_PAD_LEN + space) {
5165 1.281 msaitoh sc->sc_txfifo_stall = 1;
5166 1.281 msaitoh callout_schedule(&sc->sc_txfifo_ch, 1);
5167 1.281 msaitoh return 1;
5168 1.1 thorpej }
5169 1.1 thorpej
5170 1.281 msaitoh send_packet:
5171 1.281 msaitoh sc->sc_txfifo_head += len;
5172 1.281 msaitoh if (sc->sc_txfifo_head >= sc->sc_txfifo_size)
5173 1.281 msaitoh sc->sc_txfifo_head -= sc->sc_txfifo_size;
5174 1.1 thorpej
5175 1.281 msaitoh return 0;
5176 1.1 thorpej }
5177 1.1 thorpej
5178 1.1 thorpej /*
5179 1.281 msaitoh * wm_start: [ifnet interface function]
5180 1.1 thorpej *
5181 1.281 msaitoh * Start packet transmission on the interface.
5182 1.1 thorpej */
5183 1.47 thorpej static void
5184 1.281 msaitoh wm_start(struct ifnet *ifp)
5185 1.1 thorpej {
5186 1.281 msaitoh struct wm_softc *sc = ifp->if_softc;
5187 1.281 msaitoh
5188 1.283 ozaki WM_TX_LOCK(sc);
5189 1.281 msaitoh if (!sc->sc_stopping)
5190 1.281 msaitoh wm_start_locked(ifp);
5191 1.283 ozaki WM_TX_UNLOCK(sc);
5192 1.281 msaitoh }
5193 1.1 thorpej
5194 1.281 msaitoh static void
5195 1.281 msaitoh wm_start_locked(struct ifnet *ifp)
5196 1.281 msaitoh {
5197 1.281 msaitoh struct wm_softc *sc = ifp->if_softc;
5198 1.281 msaitoh struct mbuf *m0;
5199 1.281 msaitoh struct m_tag *mtag;
5200 1.281 msaitoh struct wm_txsoft *txs;
5201 1.281 msaitoh bus_dmamap_t dmamap;
5202 1.281 msaitoh int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
5203 1.281 msaitoh bus_addr_t curaddr;
5204 1.281 msaitoh bus_size_t seglen, curlen;
5205 1.281 msaitoh uint32_t cksumcmd;
5206 1.281 msaitoh uint8_t cksumfields;
5207 1.1 thorpej
5208 1.283 ozaki KASSERT(WM_TX_LOCKED(sc));
5209 1.1 thorpej
5210 1.281 msaitoh if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
5211 1.281 msaitoh return;
5212 1.1 thorpej
5213 1.281 msaitoh /* Remember the previous number of free descriptors. */
5214 1.281 msaitoh ofree = sc->sc_txfree;
5215 1.1 thorpej
5216 1.281 msaitoh /*
5217 1.281 msaitoh * Loop through the send queue, setting up transmit descriptors
5218 1.281 msaitoh * until we drain the queue, or use up all available transmit
5219 1.281 msaitoh * descriptors.
5220 1.281 msaitoh */
5221 1.281 msaitoh for (;;) {
5222 1.281 msaitoh m0 = NULL;
5223 1.1 thorpej
5224 1.281 msaitoh /* Get a work queue entry. */
5225 1.281 msaitoh if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) {
5226 1.335 msaitoh wm_txeof(sc);
5227 1.281 msaitoh if (sc->sc_txsfree == 0) {
5228 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5229 1.281 msaitoh ("%s: TX: no free job descriptors\n",
5230 1.281 msaitoh device_xname(sc->sc_dev)));
5231 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txsstall);
5232 1.281 msaitoh break;
5233 1.1 thorpej }
5234 1.1 thorpej }
5235 1.1 thorpej
5236 1.281 msaitoh /* Grab a packet off the queue. */
5237 1.281 msaitoh IFQ_DEQUEUE(&ifp->if_snd, m0);
5238 1.281 msaitoh if (m0 == NULL)
5239 1.281 msaitoh break;
5240 1.281 msaitoh
5241 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5242 1.281 msaitoh ("%s: TX: have packet to transmit: %p\n",
5243 1.281 msaitoh device_xname(sc->sc_dev), m0));
5244 1.281 msaitoh
5245 1.281 msaitoh txs = &sc->sc_txsoft[sc->sc_txsnext];
5246 1.281 msaitoh dmamap = txs->txs_dmamap;
5247 1.1 thorpej
5248 1.281 msaitoh use_tso = (m0->m_pkthdr.csum_flags &
5249 1.281 msaitoh (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0;
5250 1.1 thorpej
5251 1.1 thorpej /*
5252 1.281 msaitoh * So says the Linux driver:
5253 1.281 msaitoh * The controller does a simple calculation to make sure
5254 1.281 msaitoh * there is enough room in the FIFO before initiating the
5255 1.281 msaitoh * DMA for each buffer. The calc is:
5256 1.281 msaitoh * 4 = ceil(buffer len / MSS)
5257 1.281 msaitoh * To make sure we don't overrun the FIFO, adjust the max
5258 1.281 msaitoh * buffer len if the MSS drops.
5259 1.281 msaitoh */
5260 1.281 msaitoh dmamap->dm_maxsegsz =
5261 1.281 msaitoh (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
5262 1.281 msaitoh ? m0->m_pkthdr.segsz << 2
5263 1.281 msaitoh : WTX_MAX_LEN;
5264 1.281 msaitoh
5265 1.281 msaitoh /*
5266 1.281 msaitoh * Load the DMA map. If this fails, the packet either
5267 1.281 msaitoh * didn't fit in the allotted number of segments, or we
5268 1.281 msaitoh * were short on resources. For the too-many-segments
5269 1.281 msaitoh * case, we simply report an error and drop the packet,
5270 1.281 msaitoh * since we can't sanely copy a jumbo packet to a single
5271 1.281 msaitoh * buffer.
5272 1.1 thorpej */
5273 1.281 msaitoh error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
5274 1.281 msaitoh BUS_DMA_WRITE|BUS_DMA_NOWAIT);
5275 1.281 msaitoh if (error) {
5276 1.281 msaitoh if (error == EFBIG) {
5277 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txdrop);
5278 1.281 msaitoh log(LOG_ERR, "%s: Tx packet consumes too many "
5279 1.281 msaitoh "DMA segments, dropping...\n",
5280 1.281 msaitoh device_xname(sc->sc_dev));
5281 1.281 msaitoh wm_dump_mbuf_chain(sc, m0);
5282 1.281 msaitoh m_freem(m0);
5283 1.281 msaitoh continue;
5284 1.281 msaitoh }
5285 1.281 msaitoh /* Short on resources, just stop for now. */
5286 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5287 1.281 msaitoh ("%s: TX: dmamap load failed: %d\n",
5288 1.281 msaitoh device_xname(sc->sc_dev), error));
5289 1.281 msaitoh break;
5290 1.1 thorpej }
5291 1.1 thorpej
5292 1.281 msaitoh segs_needed = dmamap->dm_nsegs;
5293 1.281 msaitoh if (use_tso) {
5294 1.281 msaitoh /* For sentinel descriptor; see below. */
5295 1.281 msaitoh segs_needed++;
5296 1.281 msaitoh }
5297 1.1 thorpej
5298 1.1 thorpej /*
5299 1.281 msaitoh * Ensure we have enough descriptors free to describe
5300 1.281 msaitoh * the packet. Note, we always reserve one descriptor
5301 1.281 msaitoh * at the end of the ring due to the semantics of the
5302 1.281 msaitoh * TDT register, plus one more in the event we need
5303 1.281 msaitoh * to load offload context.
5304 1.1 thorpej */
5305 1.281 msaitoh if (segs_needed > sc->sc_txfree - 2) {
5306 1.281 msaitoh /*
5307 1.281 msaitoh * Not enough free descriptors to transmit this
5308 1.281 msaitoh * packet. We haven't committed anything yet,
5309 1.281 msaitoh * so just unload the DMA map, put the packet
5310 1.281 msaitoh * pack on the queue, and punt. Notify the upper
5311 1.281 msaitoh * layer that there are no more slots left.
5312 1.281 msaitoh */
5313 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5314 1.281 msaitoh ("%s: TX: need %d (%d) descriptors, have %d\n",
5315 1.281 msaitoh device_xname(sc->sc_dev), dmamap->dm_nsegs,
5316 1.281 msaitoh segs_needed, sc->sc_txfree - 1));
5317 1.281 msaitoh ifp->if_flags |= IFF_OACTIVE;
5318 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, dmamap);
5319 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txdstall);
5320 1.281 msaitoh break;
5321 1.1 thorpej }
5322 1.1 thorpej
5323 1.1 thorpej /*
5324 1.281 msaitoh * Check for 82547 Tx FIFO bug. We need to do this
5325 1.281 msaitoh * once we know we can transmit the packet, since we
5326 1.281 msaitoh * do some internal FIFO space accounting here.
5327 1.1 thorpej */
5328 1.281 msaitoh if (sc->sc_type == WM_T_82547 &&
5329 1.281 msaitoh wm_82547_txfifo_bugchk(sc, m0)) {
5330 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5331 1.281 msaitoh ("%s: TX: 82547 Tx FIFO bug detected\n",
5332 1.281 msaitoh device_xname(sc->sc_dev)));
5333 1.281 msaitoh ifp->if_flags |= IFF_OACTIVE;
5334 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, dmamap);
5335 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall);
5336 1.281 msaitoh break;
5337 1.281 msaitoh }
5338 1.93 thorpej
5339 1.281 msaitoh /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
5340 1.1 thorpej
5341 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5342 1.281 msaitoh ("%s: TX: packet has %d (%d) DMA segments\n",
5343 1.281 msaitoh device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
5344 1.1 thorpej
5345 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]);
5346 1.1 thorpej
5347 1.1 thorpej /*
5348 1.281 msaitoh * Store a pointer to the packet so that we can free it
5349 1.281 msaitoh * later.
5350 1.281 msaitoh *
5351 1.281 msaitoh * Initially, we consider the number of descriptors the
5352 1.281 msaitoh * packet uses the number of DMA segments. This may be
5353 1.281 msaitoh * incremented by 1 if we do checksum offload (a descriptor
5354 1.281 msaitoh * is used to set the checksum context).
5355 1.1 thorpej */
5356 1.281 msaitoh txs->txs_mbuf = m0;
5357 1.281 msaitoh txs->txs_firstdesc = sc->sc_txnext;
5358 1.281 msaitoh txs->txs_ndesc = segs_needed;
5359 1.281 msaitoh
5360 1.281 msaitoh /* Set up offload parameters for this packet. */
5361 1.281 msaitoh if (m0->m_pkthdr.csum_flags &
5362 1.281 msaitoh (M_CSUM_TSOv4|M_CSUM_TSOv6|
5363 1.281 msaitoh M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
5364 1.281 msaitoh M_CSUM_TCPv6|M_CSUM_UDPv6)) {
5365 1.281 msaitoh if (wm_tx_offload(sc, txs, &cksumcmd,
5366 1.281 msaitoh &cksumfields) != 0) {
5367 1.281 msaitoh /* Error message already displayed. */
5368 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, dmamap);
5369 1.281 msaitoh continue;
5370 1.281 msaitoh }
5371 1.281 msaitoh } else {
5372 1.281 msaitoh cksumcmd = 0;
5373 1.281 msaitoh cksumfields = 0;
5374 1.1 thorpej }
5375 1.1 thorpej
5376 1.281 msaitoh cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
5377 1.281 msaitoh
5378 1.281 msaitoh /* Sync the DMA map. */
5379 1.281 msaitoh bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
5380 1.281 msaitoh BUS_DMASYNC_PREWRITE);
5381 1.1 thorpej
5382 1.281 msaitoh /* Initialize the transmit descriptor. */
5383 1.281 msaitoh for (nexttx = sc->sc_txnext, seg = 0;
5384 1.281 msaitoh seg < dmamap->dm_nsegs; seg++) {
5385 1.281 msaitoh for (seglen = dmamap->dm_segs[seg].ds_len,
5386 1.281 msaitoh curaddr = dmamap->dm_segs[seg].ds_addr;
5387 1.281 msaitoh seglen != 0;
5388 1.281 msaitoh curaddr += curlen, seglen -= curlen,
5389 1.281 msaitoh nexttx = WM_NEXTTX(sc, nexttx)) {
5390 1.281 msaitoh curlen = seglen;
5391 1.1 thorpej
5392 1.106 yamt /*
5393 1.281 msaitoh * So says the Linux driver:
5394 1.281 msaitoh * Work around for premature descriptor
5395 1.281 msaitoh * write-backs in TSO mode. Append a
5396 1.281 msaitoh * 4-byte sentinel descriptor.
5397 1.106 yamt */
5398 1.281 msaitoh if (use_tso &&
5399 1.281 msaitoh seg == dmamap->dm_nsegs - 1 &&
5400 1.281 msaitoh curlen > 8)
5401 1.281 msaitoh curlen -= 4;
5402 1.281 msaitoh
5403 1.281 msaitoh wm_set_dma_addr(
5404 1.281 msaitoh &sc->sc_txdescs[nexttx].wtx_addr,
5405 1.281 msaitoh curaddr);
5406 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_cmdlen =
5407 1.281 msaitoh htole32(cksumcmd | curlen);
5408 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_fields.wtxu_status =
5409 1.281 msaitoh 0;
5410 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_fields.wtxu_options =
5411 1.281 msaitoh cksumfields;
5412 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0;
5413 1.281 msaitoh lasttx = nexttx;
5414 1.281 msaitoh
5415 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5416 1.281 msaitoh ("%s: TX: desc %d: low %#" PRIx64 ", "
5417 1.281 msaitoh "len %#04zx\n",
5418 1.281 msaitoh device_xname(sc->sc_dev), nexttx,
5419 1.281 msaitoh (uint64_t)curaddr, curlen));
5420 1.106 yamt }
5421 1.1 thorpej }
5422 1.1 thorpej
5423 1.281 msaitoh KASSERT(lasttx != -1);
5424 1.1 thorpej
5425 1.281 msaitoh /*
5426 1.281 msaitoh * Set up the command byte on the last descriptor of
5427 1.281 msaitoh * the packet. If we're in the interrupt delay window,
5428 1.281 msaitoh * delay the interrupt.
5429 1.281 msaitoh */
5430 1.281 msaitoh sc->sc_txdescs[lasttx].wtx_cmdlen |=
5431 1.281 msaitoh htole32(WTX_CMD_EOP | WTX_CMD_RS);
5432 1.281 msaitoh
5433 1.281 msaitoh /*
5434 1.281 msaitoh * If VLANs are enabled and the packet has a VLAN tag, set
5435 1.281 msaitoh * up the descriptor to encapsulate the packet for us.
5436 1.281 msaitoh *
5437 1.281 msaitoh * This is only valid on the last descriptor of the packet.
5438 1.281 msaitoh */
5439 1.281 msaitoh if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
5440 1.281 msaitoh sc->sc_txdescs[lasttx].wtx_cmdlen |=
5441 1.281 msaitoh htole32(WTX_CMD_VLE);
5442 1.281 msaitoh sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan
5443 1.281 msaitoh = htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
5444 1.281 msaitoh }
5445 1.281 msaitoh
5446 1.281 msaitoh txs->txs_lastdesc = lasttx;
5447 1.281 msaitoh
5448 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5449 1.281 msaitoh ("%s: TX: desc %d: cmdlen 0x%08x\n",
5450 1.281 msaitoh device_xname(sc->sc_dev),
5451 1.281 msaitoh lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen)));
5452 1.281 msaitoh
5453 1.281 msaitoh /* Sync the descriptors we're using. */
5454 1.281 msaitoh WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc,
5455 1.281 msaitoh BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5456 1.281 msaitoh
5457 1.281 msaitoh /* Give the packet to the chip. */
5458 1.281 msaitoh CSR_WRITE(sc, sc->sc_tdt_reg, nexttx);
5459 1.281 msaitoh
5460 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5461 1.281 msaitoh ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
5462 1.281 msaitoh
5463 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5464 1.281 msaitoh ("%s: TX: finished transmitting packet, job %d\n",
5465 1.281 msaitoh device_xname(sc->sc_dev), sc->sc_txsnext));
5466 1.272 ozaki
5467 1.281 msaitoh /* Advance the tx pointer. */
5468 1.281 msaitoh sc->sc_txfree -= txs->txs_ndesc;
5469 1.281 msaitoh sc->sc_txnext = nexttx;
5470 1.1 thorpej
5471 1.281 msaitoh sc->sc_txsfree--;
5472 1.281 msaitoh sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext);
5473 1.272 ozaki
5474 1.281 msaitoh /* Pass the packet to any BPF listeners. */
5475 1.281 msaitoh bpf_mtap(ifp, m0);
5476 1.281 msaitoh }
5477 1.272 ozaki
5478 1.281 msaitoh if (m0 != NULL) {
5479 1.281 msaitoh ifp->if_flags |= IFF_OACTIVE;
5480 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txdrop);
5481 1.281 msaitoh DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n", __func__));
5482 1.281 msaitoh m_freem(m0);
5483 1.1 thorpej }
5484 1.1 thorpej
5485 1.281 msaitoh if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) {
5486 1.281 msaitoh /* No more slots; notify upper layer. */
5487 1.281 msaitoh ifp->if_flags |= IFF_OACTIVE;
5488 1.281 msaitoh }
5489 1.1 thorpej
5490 1.281 msaitoh if (sc->sc_txfree != ofree) {
5491 1.281 msaitoh /* Set a watchdog timer in case the chip flakes out. */
5492 1.281 msaitoh ifp->if_timer = 5;
5493 1.281 msaitoh }
5494 1.1 thorpej }
5495 1.1 thorpej
5496 1.1 thorpej /*
5497 1.281 msaitoh * wm_nq_tx_offload:
5498 1.1 thorpej *
5499 1.281 msaitoh * Set up TCP/IP checksumming parameters for the
5500 1.281 msaitoh * specified packet, for NEWQUEUE devices
5501 1.1 thorpej */
5502 1.281 msaitoh static int
5503 1.281 msaitoh wm_nq_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs,
5504 1.281 msaitoh uint32_t *cmdlenp, uint32_t *fieldsp, bool *do_csum)
5505 1.1 thorpej {
5506 1.281 msaitoh struct mbuf *m0 = txs->txs_mbuf;
5507 1.281 msaitoh struct m_tag *mtag;
5508 1.281 msaitoh uint32_t vl_len, mssidx, cmdc;
5509 1.281 msaitoh struct ether_header *eh;
5510 1.281 msaitoh int offset, iphl;
5511 1.281 msaitoh
5512 1.281 msaitoh /*
5513 1.281 msaitoh * XXX It would be nice if the mbuf pkthdr had offset
5514 1.281 msaitoh * fields for the protocol headers.
5515 1.281 msaitoh */
5516 1.281 msaitoh *cmdlenp = 0;
5517 1.281 msaitoh *fieldsp = 0;
5518 1.281 msaitoh
5519 1.281 msaitoh eh = mtod(m0, struct ether_header *);
5520 1.281 msaitoh switch (htons(eh->ether_type)) {
5521 1.281 msaitoh case ETHERTYPE_IP:
5522 1.281 msaitoh case ETHERTYPE_IPV6:
5523 1.281 msaitoh offset = ETHER_HDR_LEN;
5524 1.281 msaitoh break;
5525 1.281 msaitoh
5526 1.281 msaitoh case ETHERTYPE_VLAN:
5527 1.281 msaitoh offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
5528 1.281 msaitoh break;
5529 1.281 msaitoh
5530 1.281 msaitoh default:
5531 1.281 msaitoh /* Don't support this protocol or encapsulation. */
5532 1.281 msaitoh *do_csum = false;
5533 1.281 msaitoh return 0;
5534 1.281 msaitoh }
5535 1.281 msaitoh *do_csum = true;
5536 1.281 msaitoh *cmdlenp = NQTX_DTYP_D | NQTX_CMD_DEXT | NQTX_CMD_IFCS;
5537 1.281 msaitoh cmdc = NQTX_DTYP_C | NQTX_CMD_DEXT;
5538 1.1 thorpej
5539 1.281 msaitoh vl_len = (offset << NQTXC_VLLEN_MACLEN_SHIFT);
5540 1.281 msaitoh KASSERT((offset & ~NQTXC_VLLEN_MACLEN_MASK) == 0);
5541 1.281 msaitoh
5542 1.281 msaitoh if ((m0->m_pkthdr.csum_flags &
5543 1.281 msaitoh (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4|M_CSUM_IPv4)) != 0) {
5544 1.281 msaitoh iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
5545 1.281 msaitoh } else {
5546 1.281 msaitoh iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
5547 1.281 msaitoh }
5548 1.281 msaitoh vl_len |= (iphl << NQTXC_VLLEN_IPLEN_SHIFT);
5549 1.281 msaitoh KASSERT((iphl & ~NQTXC_VLLEN_IPLEN_MASK) == 0);
5550 1.281 msaitoh
5551 1.281 msaitoh if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
5552 1.281 msaitoh vl_len |= ((VLAN_TAG_VALUE(mtag) & NQTXC_VLLEN_VLAN_MASK)
5553 1.281 msaitoh << NQTXC_VLLEN_VLAN_SHIFT);
5554 1.281 msaitoh *cmdlenp |= NQTX_CMD_VLE;
5555 1.281 msaitoh }
5556 1.272 ozaki
5557 1.281 msaitoh mssidx = 0;
5558 1.170 msaitoh
5559 1.281 msaitoh if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
5560 1.281 msaitoh int hlen = offset + iphl;
5561 1.281 msaitoh int tcp_hlen;
5562 1.281 msaitoh bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
5563 1.192 msaitoh
5564 1.281 msaitoh if (__predict_false(m0->m_len <
5565 1.281 msaitoh (hlen + sizeof(struct tcphdr)))) {
5566 1.192 msaitoh /*
5567 1.281 msaitoh * TCP/IP headers are not in the first mbuf; we need
5568 1.281 msaitoh * to do this the slow and painful way. Let's just
5569 1.281 msaitoh * hope this doesn't happen very often.
5570 1.192 msaitoh */
5571 1.281 msaitoh struct tcphdr th;
5572 1.170 msaitoh
5573 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtsopain);
5574 1.192 msaitoh
5575 1.281 msaitoh m_copydata(m0, hlen, sizeof(th), &th);
5576 1.281 msaitoh if (v4) {
5577 1.281 msaitoh struct ip ip;
5578 1.192 msaitoh
5579 1.281 msaitoh m_copydata(m0, offset, sizeof(ip), &ip);
5580 1.281 msaitoh ip.ip_len = 0;
5581 1.281 msaitoh m_copyback(m0,
5582 1.281 msaitoh offset + offsetof(struct ip, ip_len),
5583 1.281 msaitoh sizeof(ip.ip_len), &ip.ip_len);
5584 1.281 msaitoh th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
5585 1.281 msaitoh ip.ip_dst.s_addr, htons(IPPROTO_TCP));
5586 1.281 msaitoh } else {
5587 1.281 msaitoh struct ip6_hdr ip6;
5588 1.192 msaitoh
5589 1.281 msaitoh m_copydata(m0, offset, sizeof(ip6), &ip6);
5590 1.281 msaitoh ip6.ip6_plen = 0;
5591 1.281 msaitoh m_copyback(m0,
5592 1.281 msaitoh offset + offsetof(struct ip6_hdr, ip6_plen),
5593 1.281 msaitoh sizeof(ip6.ip6_plen), &ip6.ip6_plen);
5594 1.281 msaitoh th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
5595 1.281 msaitoh &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
5596 1.170 msaitoh }
5597 1.281 msaitoh m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
5598 1.281 msaitoh sizeof(th.th_sum), &th.th_sum);
5599 1.192 msaitoh
5600 1.281 msaitoh tcp_hlen = th.th_off << 2;
5601 1.281 msaitoh } else {
5602 1.173 msaitoh /*
5603 1.281 msaitoh * TCP/IP headers are in the first mbuf; we can do
5604 1.281 msaitoh * this the easy way.
5605 1.173 msaitoh */
5606 1.281 msaitoh struct tcphdr *th;
5607 1.198 msaitoh
5608 1.281 msaitoh if (v4) {
5609 1.281 msaitoh struct ip *ip =
5610 1.281 msaitoh (void *)(mtod(m0, char *) + offset);
5611 1.281 msaitoh th = (void *)(mtod(m0, char *) + hlen);
5612 1.1 thorpej
5613 1.281 msaitoh ip->ip_len = 0;
5614 1.281 msaitoh th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
5615 1.281 msaitoh ip->ip_dst.s_addr, htons(IPPROTO_TCP));
5616 1.281 msaitoh } else {
5617 1.281 msaitoh struct ip6_hdr *ip6 =
5618 1.281 msaitoh (void *)(mtod(m0, char *) + offset);
5619 1.281 msaitoh th = (void *)(mtod(m0, char *) + hlen);
5620 1.192 msaitoh
5621 1.281 msaitoh ip6->ip6_plen = 0;
5622 1.281 msaitoh th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
5623 1.281 msaitoh &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
5624 1.281 msaitoh }
5625 1.281 msaitoh tcp_hlen = th->th_off << 2;
5626 1.144 msaitoh }
5627 1.281 msaitoh hlen += tcp_hlen;
5628 1.281 msaitoh *cmdlenp |= NQTX_CMD_TSE;
5629 1.144 msaitoh
5630 1.281 msaitoh if (v4) {
5631 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtso);
5632 1.281 msaitoh *fieldsp |= NQTXD_FIELDS_IXSM | NQTXD_FIELDS_TUXSM;
5633 1.281 msaitoh } else {
5634 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtso6);
5635 1.281 msaitoh *fieldsp |= NQTXD_FIELDS_TUXSM;
5636 1.189 msaitoh }
5637 1.281 msaitoh *fieldsp |= ((m0->m_pkthdr.len - hlen) << NQTXD_FIELDS_PAYLEN_SHIFT);
5638 1.281 msaitoh KASSERT(((m0->m_pkthdr.len - hlen) & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
5639 1.281 msaitoh mssidx |= (m0->m_pkthdr.segsz << NQTXC_MSSIDX_MSS_SHIFT);
5640 1.281 msaitoh KASSERT((m0->m_pkthdr.segsz & ~NQTXC_MSSIDX_MSS_MASK) == 0);
5641 1.281 msaitoh mssidx |= (tcp_hlen << NQTXC_MSSIDX_L4LEN_SHIFT);
5642 1.281 msaitoh KASSERT((tcp_hlen & ~NQTXC_MSSIDX_L4LEN_MASK) == 0);
5643 1.281 msaitoh } else {
5644 1.281 msaitoh *fieldsp |= (m0->m_pkthdr.len << NQTXD_FIELDS_PAYLEN_SHIFT);
5645 1.281 msaitoh KASSERT((m0->m_pkthdr.len & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
5646 1.208 msaitoh }
5647 1.208 msaitoh
5648 1.281 msaitoh if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
5649 1.281 msaitoh *fieldsp |= NQTXD_FIELDS_IXSM;
5650 1.281 msaitoh cmdc |= NQTXC_CMD_IP4;
5651 1.281 msaitoh }
5652 1.144 msaitoh
5653 1.281 msaitoh if (m0->m_pkthdr.csum_flags &
5654 1.281 msaitoh (M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
5655 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtusum);
5656 1.281 msaitoh if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
5657 1.281 msaitoh cmdc |= NQTXC_CMD_TCP;
5658 1.281 msaitoh } else {
5659 1.281 msaitoh cmdc |= NQTXC_CMD_UDP;
5660 1.281 msaitoh }
5661 1.281 msaitoh cmdc |= NQTXC_CMD_IP4;
5662 1.281 msaitoh *fieldsp |= NQTXD_FIELDS_TUXSM;
5663 1.281 msaitoh }
5664 1.281 msaitoh if (m0->m_pkthdr.csum_flags &
5665 1.281 msaitoh (M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
5666 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txtusum6);
5667 1.281 msaitoh if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
5668 1.281 msaitoh cmdc |= NQTXC_CMD_TCP;
5669 1.281 msaitoh } else {
5670 1.281 msaitoh cmdc |= NQTXC_CMD_UDP;
5671 1.281 msaitoh }
5672 1.281 msaitoh cmdc |= NQTXC_CMD_IP6;
5673 1.281 msaitoh *fieldsp |= NQTXD_FIELDS_TUXSM;
5674 1.281 msaitoh }
5675 1.1 thorpej
5676 1.281 msaitoh /* Fill in the context descriptor. */
5677 1.281 msaitoh sc->sc_nq_txdescs[sc->sc_txnext].nqrx_ctx.nqtxc_vl_len =
5678 1.281 msaitoh htole32(vl_len);
5679 1.281 msaitoh sc->sc_nq_txdescs[sc->sc_txnext].nqrx_ctx.nqtxc_sn = 0;
5680 1.281 msaitoh sc->sc_nq_txdescs[sc->sc_txnext].nqrx_ctx.nqtxc_cmd =
5681 1.281 msaitoh htole32(cmdc);
5682 1.281 msaitoh sc->sc_nq_txdescs[sc->sc_txnext].nqrx_ctx.nqtxc_mssidx =
5683 1.281 msaitoh htole32(mssidx);
5684 1.281 msaitoh WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE);
5685 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5686 1.281 msaitoh ("%s: TX: context desc %d 0x%08x%08x\n", device_xname(sc->sc_dev),
5687 1.281 msaitoh sc->sc_txnext, 0, vl_len));
5688 1.281 msaitoh DPRINTF(WM_DEBUG_TX, ("\t0x%08x%08x\n", mssidx, cmdc));
5689 1.281 msaitoh sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext);
5690 1.281 msaitoh txs->txs_ndesc++;
5691 1.281 msaitoh return 0;
5692 1.217 dyoung }
5693 1.217 dyoung
5694 1.1 thorpej /*
5695 1.281 msaitoh * wm_nq_start: [ifnet interface function]
5696 1.1 thorpej *
5697 1.281 msaitoh * Start packet transmission on the interface for NEWQUEUE devices
5698 1.1 thorpej */
5699 1.281 msaitoh static void
5700 1.281 msaitoh wm_nq_start(struct ifnet *ifp)
5701 1.1 thorpej {
5702 1.1 thorpej struct wm_softc *sc = ifp->if_softc;
5703 1.272 ozaki
5704 1.283 ozaki WM_TX_LOCK(sc);
5705 1.281 msaitoh if (!sc->sc_stopping)
5706 1.281 msaitoh wm_nq_start_locked(ifp);
5707 1.283 ozaki WM_TX_UNLOCK(sc);
5708 1.272 ozaki }
5709 1.272 ozaki
5710 1.281 msaitoh static void
5711 1.281 msaitoh wm_nq_start_locked(struct ifnet *ifp)
5712 1.272 ozaki {
5713 1.272 ozaki struct wm_softc *sc = ifp->if_softc;
5714 1.281 msaitoh struct mbuf *m0;
5715 1.281 msaitoh struct m_tag *mtag;
5716 1.281 msaitoh struct wm_txsoft *txs;
5717 1.281 msaitoh bus_dmamap_t dmamap;
5718 1.281 msaitoh int error, nexttx, lasttx = -1, seg, segs_needed;
5719 1.281 msaitoh bool do_csum, sent;
5720 1.1 thorpej
5721 1.283 ozaki KASSERT(WM_TX_LOCKED(sc));
5722 1.41 tls
5723 1.281 msaitoh if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
5724 1.281 msaitoh return;
5725 1.1 thorpej
5726 1.281 msaitoh sent = false;
5727 1.1 thorpej
5728 1.1 thorpej /*
5729 1.281 msaitoh * Loop through the send queue, setting up transmit descriptors
5730 1.281 msaitoh * until we drain the queue, or use up all available transmit
5731 1.281 msaitoh * descriptors.
5732 1.1 thorpej */
5733 1.281 msaitoh for (;;) {
5734 1.281 msaitoh m0 = NULL;
5735 1.281 msaitoh
5736 1.281 msaitoh /* Get a work queue entry. */
5737 1.281 msaitoh if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) {
5738 1.335 msaitoh wm_txeof(sc);
5739 1.281 msaitoh if (sc->sc_txsfree == 0) {
5740 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5741 1.281 msaitoh ("%s: TX: no free job descriptors\n",
5742 1.281 msaitoh device_xname(sc->sc_dev)));
5743 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txsstall);
5744 1.281 msaitoh break;
5745 1.281 msaitoh }
5746 1.281 msaitoh }
5747 1.1 thorpej
5748 1.281 msaitoh /* Grab a packet off the queue. */
5749 1.281 msaitoh IFQ_DEQUEUE(&ifp->if_snd, m0);
5750 1.281 msaitoh if (m0 == NULL)
5751 1.281 msaitoh break;
5752 1.71 thorpej
5753 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5754 1.281 msaitoh ("%s: TX: have packet to transmit: %p\n",
5755 1.281 msaitoh device_xname(sc->sc_dev), m0));
5756 1.177 msaitoh
5757 1.281 msaitoh txs = &sc->sc_txsoft[sc->sc_txsnext];
5758 1.281 msaitoh dmamap = txs->txs_dmamap;
5759 1.1 thorpej
5760 1.281 msaitoh /*
5761 1.281 msaitoh * Load the DMA map. If this fails, the packet either
5762 1.281 msaitoh * didn't fit in the allotted number of segments, or we
5763 1.281 msaitoh * were short on resources. For the too-many-segments
5764 1.281 msaitoh * case, we simply report an error and drop the packet,
5765 1.281 msaitoh * since we can't sanely copy a jumbo packet to a single
5766 1.281 msaitoh * buffer.
5767 1.281 msaitoh */
5768 1.281 msaitoh error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
5769 1.281 msaitoh BUS_DMA_WRITE|BUS_DMA_NOWAIT);
5770 1.281 msaitoh if (error) {
5771 1.281 msaitoh if (error == EFBIG) {
5772 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txdrop);
5773 1.281 msaitoh log(LOG_ERR, "%s: Tx packet consumes too many "
5774 1.281 msaitoh "DMA segments, dropping...\n",
5775 1.281 msaitoh device_xname(sc->sc_dev));
5776 1.281 msaitoh wm_dump_mbuf_chain(sc, m0);
5777 1.281 msaitoh m_freem(m0);
5778 1.281 msaitoh continue;
5779 1.281 msaitoh }
5780 1.281 msaitoh /* Short on resources, just stop for now. */
5781 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5782 1.281 msaitoh ("%s: TX: dmamap load failed: %d\n",
5783 1.281 msaitoh device_xname(sc->sc_dev), error));
5784 1.281 msaitoh break;
5785 1.281 msaitoh }
5786 1.177 msaitoh
5787 1.281 msaitoh segs_needed = dmamap->dm_nsegs;
5788 1.177 msaitoh
5789 1.281 msaitoh /*
5790 1.281 msaitoh * Ensure we have enough descriptors free to describe
5791 1.281 msaitoh * the packet. Note, we always reserve one descriptor
5792 1.281 msaitoh * at the end of the ring due to the semantics of the
5793 1.281 msaitoh * TDT register, plus one more in the event we need
5794 1.281 msaitoh * to load offload context.
5795 1.281 msaitoh */
5796 1.281 msaitoh if (segs_needed > sc->sc_txfree - 2) {
5797 1.177 msaitoh /*
5798 1.281 msaitoh * Not enough free descriptors to transmit this
5799 1.281 msaitoh * packet. We haven't committed anything yet,
5800 1.281 msaitoh * so just unload the DMA map, put the packet
5801 1.281 msaitoh * pack on the queue, and punt. Notify the upper
5802 1.281 msaitoh * layer that there are no more slots left.
5803 1.177 msaitoh */
5804 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5805 1.281 msaitoh ("%s: TX: need %d (%d) descriptors, have %d\n",
5806 1.281 msaitoh device_xname(sc->sc_dev), dmamap->dm_nsegs,
5807 1.281 msaitoh segs_needed, sc->sc_txfree - 1));
5808 1.281 msaitoh ifp->if_flags |= IFF_OACTIVE;
5809 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, dmamap);
5810 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txdstall);
5811 1.177 msaitoh break;
5812 1.177 msaitoh }
5813 1.177 msaitoh
5814 1.281 msaitoh /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
5815 1.281 msaitoh
5816 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5817 1.281 msaitoh ("%s: TX: packet has %d (%d) DMA segments\n",
5818 1.281 msaitoh device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
5819 1.177 msaitoh
5820 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]);
5821 1.1 thorpej
5822 1.281 msaitoh /*
5823 1.281 msaitoh * Store a pointer to the packet so that we can free it
5824 1.281 msaitoh * later.
5825 1.281 msaitoh *
5826 1.281 msaitoh * Initially, we consider the number of descriptors the
5827 1.281 msaitoh * packet uses the number of DMA segments. This may be
5828 1.281 msaitoh * incremented by 1 if we do checksum offload (a descriptor
5829 1.281 msaitoh * is used to set the checksum context).
5830 1.281 msaitoh */
5831 1.281 msaitoh txs->txs_mbuf = m0;
5832 1.281 msaitoh txs->txs_firstdesc = sc->sc_txnext;
5833 1.281 msaitoh txs->txs_ndesc = segs_needed;
5834 1.1 thorpej
5835 1.281 msaitoh /* Set up offload parameters for this packet. */
5836 1.281 msaitoh uint32_t cmdlen, fields, dcmdlen;
5837 1.281 msaitoh if (m0->m_pkthdr.csum_flags &
5838 1.281 msaitoh (M_CSUM_TSOv4|M_CSUM_TSOv6|
5839 1.281 msaitoh M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
5840 1.281 msaitoh M_CSUM_TCPv6|M_CSUM_UDPv6)) {
5841 1.281 msaitoh if (wm_nq_tx_offload(sc, txs, &cmdlen, &fields,
5842 1.281 msaitoh &do_csum) != 0) {
5843 1.281 msaitoh /* Error message already displayed. */
5844 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, dmamap);
5845 1.281 msaitoh continue;
5846 1.281 msaitoh }
5847 1.281 msaitoh } else {
5848 1.281 msaitoh do_csum = false;
5849 1.281 msaitoh cmdlen = 0;
5850 1.281 msaitoh fields = 0;
5851 1.281 msaitoh }
5852 1.173 msaitoh
5853 1.281 msaitoh /* Sync the DMA map. */
5854 1.281 msaitoh bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
5855 1.281 msaitoh BUS_DMASYNC_PREWRITE);
5856 1.1 thorpej
5857 1.281 msaitoh /* Initialize the first transmit descriptor. */
5858 1.281 msaitoh nexttx = sc->sc_txnext;
5859 1.281 msaitoh if (!do_csum) {
5860 1.281 msaitoh /* setup a legacy descriptor */
5861 1.281 msaitoh wm_set_dma_addr(
5862 1.281 msaitoh &sc->sc_txdescs[nexttx].wtx_addr,
5863 1.281 msaitoh dmamap->dm_segs[0].ds_addr);
5864 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_cmdlen =
5865 1.281 msaitoh htole32(WTX_CMD_IFCS | dmamap->dm_segs[0].ds_len);
5866 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 0;
5867 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 0;
5868 1.281 msaitoh if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) !=
5869 1.281 msaitoh NULL) {
5870 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_cmdlen |=
5871 1.281 msaitoh htole32(WTX_CMD_VLE);
5872 1.281 msaitoh sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan =
5873 1.281 msaitoh htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
5874 1.281 msaitoh } else {
5875 1.335 msaitoh sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan =0;
5876 1.281 msaitoh }
5877 1.281 msaitoh dcmdlen = 0;
5878 1.281 msaitoh } else {
5879 1.281 msaitoh /* setup an advanced data descriptor */
5880 1.281 msaitoh sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_addr =
5881 1.281 msaitoh htole64(dmamap->dm_segs[0].ds_addr);
5882 1.281 msaitoh KASSERT((dmamap->dm_segs[0].ds_len & cmdlen) == 0);
5883 1.281 msaitoh sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_cmdlen =
5884 1.281 msaitoh htole32(dmamap->dm_segs[0].ds_len | cmdlen );
5885 1.281 msaitoh sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_fields =
5886 1.281 msaitoh htole32(fields);
5887 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5888 1.281 msaitoh ("%s: TX: adv data desc %d 0x%" PRIx64 "\n",
5889 1.281 msaitoh device_xname(sc->sc_dev), nexttx,
5890 1.281 msaitoh (uint64_t)dmamap->dm_segs[0].ds_addr));
5891 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5892 1.281 msaitoh ("\t 0x%08x%08x\n", fields,
5893 1.281 msaitoh (uint32_t)dmamap->dm_segs[0].ds_len | cmdlen));
5894 1.281 msaitoh dcmdlen = NQTX_DTYP_D | NQTX_CMD_DEXT;
5895 1.281 msaitoh }
5896 1.177 msaitoh
5897 1.281 msaitoh lasttx = nexttx;
5898 1.281 msaitoh nexttx = WM_NEXTTX(sc, nexttx);
5899 1.150 tls /*
5900 1.281 msaitoh * fill in the next descriptors. legacy or adcanced format
5901 1.281 msaitoh * is the same here
5902 1.150 tls */
5903 1.281 msaitoh for (seg = 1; seg < dmamap->dm_nsegs;
5904 1.281 msaitoh seg++, nexttx = WM_NEXTTX(sc, nexttx)) {
5905 1.281 msaitoh sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_addr =
5906 1.281 msaitoh htole64(dmamap->dm_segs[seg].ds_addr);
5907 1.281 msaitoh sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_cmdlen =
5908 1.281 msaitoh htole32(dcmdlen | dmamap->dm_segs[seg].ds_len);
5909 1.281 msaitoh KASSERT((dcmdlen & dmamap->dm_segs[seg].ds_len) == 0);
5910 1.281 msaitoh sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_fields = 0;
5911 1.281 msaitoh lasttx = nexttx;
5912 1.153 tls
5913 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5914 1.281 msaitoh ("%s: TX: desc %d: %#" PRIx64 ", "
5915 1.281 msaitoh "len %#04zx\n",
5916 1.281 msaitoh device_xname(sc->sc_dev), nexttx,
5917 1.281 msaitoh (uint64_t)dmamap->dm_segs[seg].ds_addr,
5918 1.281 msaitoh dmamap->dm_segs[seg].ds_len));
5919 1.281 msaitoh }
5920 1.153 tls
5921 1.281 msaitoh KASSERT(lasttx != -1);
5922 1.1 thorpej
5923 1.211 msaitoh /*
5924 1.281 msaitoh * Set up the command byte on the last descriptor of
5925 1.281 msaitoh * the packet. If we're in the interrupt delay window,
5926 1.281 msaitoh * delay the interrupt.
5927 1.211 msaitoh */
5928 1.281 msaitoh KASSERT((WTX_CMD_EOP | WTX_CMD_RS) ==
5929 1.281 msaitoh (NQTX_CMD_EOP | NQTX_CMD_RS));
5930 1.281 msaitoh sc->sc_txdescs[lasttx].wtx_cmdlen |=
5931 1.281 msaitoh htole32(WTX_CMD_EOP | WTX_CMD_RS);
5932 1.211 msaitoh
5933 1.281 msaitoh txs->txs_lastdesc = lasttx;
5934 1.177 msaitoh
5935 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5936 1.281 msaitoh ("%s: TX: desc %d: cmdlen 0x%08x\n",
5937 1.281 msaitoh device_xname(sc->sc_dev),
5938 1.281 msaitoh lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen)));
5939 1.1 thorpej
5940 1.281 msaitoh /* Sync the descriptors we're using. */
5941 1.281 msaitoh WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc,
5942 1.281 msaitoh BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5943 1.203 msaitoh
5944 1.281 msaitoh /* Give the packet to the chip. */
5945 1.281 msaitoh CSR_WRITE(sc, sc->sc_tdt_reg, nexttx);
5946 1.281 msaitoh sent = true;
5947 1.120 msaitoh
5948 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5949 1.281 msaitoh ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
5950 1.228 msaitoh
5951 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
5952 1.281 msaitoh ("%s: TX: finished transmitting packet, job %d\n",
5953 1.281 msaitoh device_xname(sc->sc_dev), sc->sc_txsnext));
5954 1.41 tls
5955 1.281 msaitoh /* Advance the tx pointer. */
5956 1.281 msaitoh sc->sc_txfree -= txs->txs_ndesc;
5957 1.281 msaitoh sc->sc_txnext = nexttx;
5958 1.1 thorpej
5959 1.281 msaitoh sc->sc_txsfree--;
5960 1.281 msaitoh sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext);
5961 1.1 thorpej
5962 1.281 msaitoh /* Pass the packet to any BPF listeners. */
5963 1.281 msaitoh bpf_mtap(ifp, m0);
5964 1.281 msaitoh }
5965 1.257 msaitoh
5966 1.281 msaitoh if (m0 != NULL) {
5967 1.281 msaitoh ifp->if_flags |= IFF_OACTIVE;
5968 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txdrop);
5969 1.281 msaitoh DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n", __func__));
5970 1.281 msaitoh m_freem(m0);
5971 1.257 msaitoh }
5972 1.257 msaitoh
5973 1.281 msaitoh if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) {
5974 1.281 msaitoh /* No more slots; notify upper layer. */
5975 1.281 msaitoh ifp->if_flags |= IFF_OACTIVE;
5976 1.281 msaitoh }
5977 1.199 msaitoh
5978 1.281 msaitoh if (sent) {
5979 1.281 msaitoh /* Set a watchdog timer in case the chip flakes out. */
5980 1.281 msaitoh ifp->if_timer = 5;
5981 1.281 msaitoh }
5982 1.281 msaitoh }
5983 1.272 ozaki
5984 1.281 msaitoh /* Interrupt */
5985 1.1 thorpej
5986 1.1 thorpej /*
5987 1.335 msaitoh * wm_txeof:
5988 1.1 thorpej *
5989 1.281 msaitoh * Helper; handle transmit interrupts.
5990 1.1 thorpej */
5991 1.335 msaitoh static int
5992 1.335 msaitoh wm_txeof(struct wm_softc *sc)
5993 1.1 thorpej {
5994 1.281 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
5995 1.281 msaitoh struct wm_txsoft *txs;
5996 1.335 msaitoh bool processed = false;
5997 1.335 msaitoh int count = 0;
5998 1.335 msaitoh int i;
5999 1.281 msaitoh uint8_t status;
6000 1.1 thorpej
6001 1.281 msaitoh if (sc->sc_stopping)
6002 1.335 msaitoh return 0;
6003 1.281 msaitoh
6004 1.281 msaitoh ifp->if_flags &= ~IFF_OACTIVE;
6005 1.272 ozaki
6006 1.281 msaitoh /*
6007 1.281 msaitoh * Go through the Tx list and free mbufs for those
6008 1.281 msaitoh * frames which have been transmitted.
6009 1.281 msaitoh */
6010 1.281 msaitoh for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc);
6011 1.281 msaitoh i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) {
6012 1.281 msaitoh txs = &sc->sc_txsoft[i];
6013 1.1 thorpej
6014 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
6015 1.281 msaitoh ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i));
6016 1.272 ozaki
6017 1.281 msaitoh WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc,
6018 1.281 msaitoh BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
6019 1.272 ozaki
6020 1.281 msaitoh status =
6021 1.281 msaitoh sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status;
6022 1.281 msaitoh if ((status & WTX_ST_DD) == 0) {
6023 1.281 msaitoh WM_CDTXSYNC(sc, txs->txs_lastdesc, 1,
6024 1.281 msaitoh BUS_DMASYNC_PREREAD);
6025 1.281 msaitoh break;
6026 1.281 msaitoh }
6027 1.1 thorpej
6028 1.335 msaitoh processed = true;
6029 1.335 msaitoh count++;
6030 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
6031 1.281 msaitoh ("%s: TX: job %d done: descs %d..%d\n",
6032 1.281 msaitoh device_xname(sc->sc_dev), i, txs->txs_firstdesc,
6033 1.281 msaitoh txs->txs_lastdesc));
6034 1.272 ozaki
6035 1.281 msaitoh /*
6036 1.281 msaitoh * XXX We should probably be using the statistics
6037 1.281 msaitoh * XXX registers, but I don't know if they exist
6038 1.281 msaitoh * XXX on chips before the i82544.
6039 1.281 msaitoh */
6040 1.272 ozaki
6041 1.281 msaitoh #ifdef WM_EVENT_COUNTERS
6042 1.281 msaitoh if (status & WTX_ST_TU)
6043 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_tu);
6044 1.281 msaitoh #endif /* WM_EVENT_COUNTERS */
6045 1.1 thorpej
6046 1.281 msaitoh if (status & (WTX_ST_EC|WTX_ST_LC)) {
6047 1.281 msaitoh ifp->if_oerrors++;
6048 1.281 msaitoh if (status & WTX_ST_LC)
6049 1.281 msaitoh log(LOG_WARNING, "%s: late collision\n",
6050 1.281 msaitoh device_xname(sc->sc_dev));
6051 1.281 msaitoh else if (status & WTX_ST_EC) {
6052 1.281 msaitoh ifp->if_collisions += 16;
6053 1.281 msaitoh log(LOG_WARNING, "%s: excessive collisions\n",
6054 1.281 msaitoh device_xname(sc->sc_dev));
6055 1.281 msaitoh }
6056 1.281 msaitoh } else
6057 1.281 msaitoh ifp->if_opackets++;
6058 1.78 thorpej
6059 1.281 msaitoh sc->sc_txfree += txs->txs_ndesc;
6060 1.281 msaitoh bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
6061 1.281 msaitoh 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
6062 1.281 msaitoh bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
6063 1.281 msaitoh m_freem(txs->txs_mbuf);
6064 1.281 msaitoh txs->txs_mbuf = NULL;
6065 1.1 thorpej }
6066 1.1 thorpej
6067 1.281 msaitoh /* Update the dirty transmit buffer pointer. */
6068 1.281 msaitoh sc->sc_txsdirty = i;
6069 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
6070 1.281 msaitoh ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i));
6071 1.1 thorpej
6072 1.335 msaitoh if (count != 0)
6073 1.335 msaitoh rnd_add_uint32(&sc->rnd_source, count);
6074 1.335 msaitoh
6075 1.102 scw /*
6076 1.281 msaitoh * If there are no more pending transmissions, cancel the watchdog
6077 1.281 msaitoh * timer.
6078 1.102 scw */
6079 1.281 msaitoh if (sc->sc_txsfree == WM_TXQUEUELEN(sc))
6080 1.281 msaitoh ifp->if_timer = 0;
6081 1.335 msaitoh
6082 1.335 msaitoh return processed;
6083 1.281 msaitoh }
6084 1.102 scw
6085 1.281 msaitoh /*
6086 1.335 msaitoh * wm_rxeof:
6087 1.281 msaitoh *
6088 1.281 msaitoh * Helper; handle receive interrupts.
6089 1.281 msaitoh */
6090 1.281 msaitoh static void
6091 1.335 msaitoh wm_rxeof(struct wm_softc *sc)
6092 1.281 msaitoh {
6093 1.281 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
6094 1.281 msaitoh struct wm_rxsoft *rxs;
6095 1.281 msaitoh struct mbuf *m;
6096 1.281 msaitoh int i, len;
6097 1.335 msaitoh int count = 0;
6098 1.281 msaitoh uint8_t status, errors;
6099 1.281 msaitoh uint16_t vlantag;
6100 1.1 thorpej
6101 1.281 msaitoh for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
6102 1.281 msaitoh rxs = &sc->sc_rxsoft[i];
6103 1.156 dyoung
6104 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6105 1.281 msaitoh ("%s: RX: checking descriptor %d\n",
6106 1.281 msaitoh device_xname(sc->sc_dev), i));
6107 1.199 msaitoh
6108 1.281 msaitoh WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
6109 1.1 thorpej
6110 1.281 msaitoh status = sc->sc_rxdescs[i].wrx_status;
6111 1.281 msaitoh errors = sc->sc_rxdescs[i].wrx_errors;
6112 1.281 msaitoh len = le16toh(sc->sc_rxdescs[i].wrx_len);
6113 1.281 msaitoh vlantag = sc->sc_rxdescs[i].wrx_special;
6114 1.145 msaitoh
6115 1.281 msaitoh if ((status & WRX_ST_DD) == 0) {
6116 1.281 msaitoh /* We have processed all of the receive descriptors. */
6117 1.281 msaitoh WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
6118 1.281 msaitoh break;
6119 1.145 msaitoh }
6120 1.189 msaitoh
6121 1.335 msaitoh count++;
6122 1.281 msaitoh if (__predict_false(sc->sc_rxdiscard)) {
6123 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6124 1.281 msaitoh ("%s: RX: discarding contents of descriptor %d\n",
6125 1.281 msaitoh device_xname(sc->sc_dev), i));
6126 1.281 msaitoh WM_INIT_RXDESC(sc, i);
6127 1.281 msaitoh if (status & WRX_ST_EOP) {
6128 1.281 msaitoh /* Reset our state. */
6129 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6130 1.281 msaitoh ("%s: RX: resetting rxdiscard -> 0\n",
6131 1.281 msaitoh device_xname(sc->sc_dev)));
6132 1.281 msaitoh sc->sc_rxdiscard = 0;
6133 1.281 msaitoh }
6134 1.281 msaitoh continue;
6135 1.189 msaitoh }
6136 1.189 msaitoh
6137 1.281 msaitoh bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
6138 1.281 msaitoh rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
6139 1.189 msaitoh
6140 1.281 msaitoh m = rxs->rxs_mbuf;
6141 1.189 msaitoh
6142 1.281 msaitoh /*
6143 1.281 msaitoh * Add a new receive buffer to the ring, unless of
6144 1.281 msaitoh * course the length is zero. Treat the latter as a
6145 1.281 msaitoh * failed mapping.
6146 1.281 msaitoh */
6147 1.281 msaitoh if ((len == 0) || (wm_add_rxbuf(sc, i) != 0)) {
6148 1.281 msaitoh /*
6149 1.281 msaitoh * Failed, throw away what we've done so
6150 1.281 msaitoh * far, and discard the rest of the packet.
6151 1.281 msaitoh */
6152 1.281 msaitoh ifp->if_ierrors++;
6153 1.281 msaitoh bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
6154 1.281 msaitoh rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
6155 1.281 msaitoh WM_INIT_RXDESC(sc, i);
6156 1.281 msaitoh if ((status & WRX_ST_EOP) == 0)
6157 1.281 msaitoh sc->sc_rxdiscard = 1;
6158 1.281 msaitoh if (sc->sc_rxhead != NULL)
6159 1.281 msaitoh m_freem(sc->sc_rxhead);
6160 1.281 msaitoh WM_RXCHAIN_RESET(sc);
6161 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6162 1.281 msaitoh ("%s: RX: Rx buffer allocation failed, "
6163 1.281 msaitoh "dropping packet%s\n", device_xname(sc->sc_dev),
6164 1.281 msaitoh sc->sc_rxdiscard ? " (discard)" : ""));
6165 1.281 msaitoh continue;
6166 1.189 msaitoh }
6167 1.253 msaitoh
6168 1.281 msaitoh m->m_len = len;
6169 1.281 msaitoh sc->sc_rxlen += len;
6170 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6171 1.281 msaitoh ("%s: RX: buffer at %p len %d\n",
6172 1.281 msaitoh device_xname(sc->sc_dev), m->m_data, len));
6173 1.145 msaitoh
6174 1.281 msaitoh /* If this is not the end of the packet, keep looking. */
6175 1.281 msaitoh if ((status & WRX_ST_EOP) == 0) {
6176 1.281 msaitoh WM_RXCHAIN_LINK(sc, m);
6177 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6178 1.281 msaitoh ("%s: RX: not yet EOP, rxlen -> %d\n",
6179 1.281 msaitoh device_xname(sc->sc_dev), sc->sc_rxlen));
6180 1.281 msaitoh continue;
6181 1.281 msaitoh }
6182 1.45 thorpej
6183 1.281 msaitoh /*
6184 1.281 msaitoh * Okay, we have the entire packet now. The chip is
6185 1.281 msaitoh * configured to include the FCS except I350 and I21[01]
6186 1.281 msaitoh * (not all chips can be configured to strip it),
6187 1.281 msaitoh * so we need to trim it.
6188 1.281 msaitoh * May need to adjust length of previous mbuf in the
6189 1.281 msaitoh * chain if the current mbuf is too short.
6190 1.281 msaitoh * For an eratta, the RCTL_SECRC bit in RCTL register
6191 1.281 msaitoh * is always set in I350, so we don't trim it.
6192 1.281 msaitoh */
6193 1.281 msaitoh if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I354)
6194 1.281 msaitoh && (sc->sc_type != WM_T_I210)
6195 1.281 msaitoh && (sc->sc_type != WM_T_I211)) {
6196 1.281 msaitoh if (m->m_len < ETHER_CRC_LEN) {
6197 1.281 msaitoh sc->sc_rxtail->m_len
6198 1.281 msaitoh -= (ETHER_CRC_LEN - m->m_len);
6199 1.281 msaitoh m->m_len = 0;
6200 1.281 msaitoh } else
6201 1.281 msaitoh m->m_len -= ETHER_CRC_LEN;
6202 1.281 msaitoh len = sc->sc_rxlen - ETHER_CRC_LEN;
6203 1.281 msaitoh } else
6204 1.281 msaitoh len = sc->sc_rxlen;
6205 1.117 msaitoh
6206 1.281 msaitoh WM_RXCHAIN_LINK(sc, m);
6207 1.127 bouyer
6208 1.281 msaitoh *sc->sc_rxtailp = NULL;
6209 1.281 msaitoh m = sc->sc_rxhead;
6210 1.117 msaitoh
6211 1.281 msaitoh WM_RXCHAIN_RESET(sc);
6212 1.45 thorpej
6213 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6214 1.281 msaitoh ("%s: RX: have entire packet, len -> %d\n",
6215 1.281 msaitoh device_xname(sc->sc_dev), len));
6216 1.45 thorpej
6217 1.281 msaitoh /* If an error occurred, update stats and drop the packet. */
6218 1.281 msaitoh if (errors &
6219 1.281 msaitoh (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
6220 1.281 msaitoh if (errors & WRX_ER_SE)
6221 1.281 msaitoh log(LOG_WARNING, "%s: symbol error\n",
6222 1.281 msaitoh device_xname(sc->sc_dev));
6223 1.281 msaitoh else if (errors & WRX_ER_SEQ)
6224 1.281 msaitoh log(LOG_WARNING, "%s: receive sequence error\n",
6225 1.281 msaitoh device_xname(sc->sc_dev));
6226 1.281 msaitoh else if (errors & WRX_ER_CE)
6227 1.281 msaitoh log(LOG_WARNING, "%s: CRC error\n",
6228 1.281 msaitoh device_xname(sc->sc_dev));
6229 1.281 msaitoh m_freem(m);
6230 1.281 msaitoh continue;
6231 1.45 thorpej }
6232 1.45 thorpej
6233 1.281 msaitoh /* No errors. Receive the packet. */
6234 1.281 msaitoh m->m_pkthdr.rcvif = ifp;
6235 1.281 msaitoh m->m_pkthdr.len = len;
6236 1.45 thorpej
6237 1.281 msaitoh /*
6238 1.281 msaitoh * If VLANs are enabled, VLAN packets have been unwrapped
6239 1.281 msaitoh * for us. Associate the tag with the packet.
6240 1.281 msaitoh */
6241 1.281 msaitoh /* XXXX should check for i350 and i354 */
6242 1.281 msaitoh if ((status & WRX_ST_VP) != 0) {
6243 1.281 msaitoh VLAN_INPUT_TAG(ifp, m,
6244 1.281 msaitoh le16toh(vlantag),
6245 1.281 msaitoh continue);
6246 1.281 msaitoh }
6247 1.45 thorpej
6248 1.281 msaitoh /* Set up checksum info for this packet. */
6249 1.281 msaitoh if ((status & WRX_ST_IXSM) == 0) {
6250 1.281 msaitoh if (status & WRX_ST_IPCS) {
6251 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_rxipsum);
6252 1.281 msaitoh m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
6253 1.281 msaitoh if (errors & WRX_ER_IPE)
6254 1.281 msaitoh m->m_pkthdr.csum_flags |=
6255 1.281 msaitoh M_CSUM_IPv4_BAD;
6256 1.281 msaitoh }
6257 1.281 msaitoh if (status & WRX_ST_TCPCS) {
6258 1.281 msaitoh /*
6259 1.281 msaitoh * Note: we don't know if this was TCP or UDP,
6260 1.281 msaitoh * so we just set both bits, and expect the
6261 1.281 msaitoh * upper layers to deal.
6262 1.281 msaitoh */
6263 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_rxtusum);
6264 1.281 msaitoh m->m_pkthdr.csum_flags |=
6265 1.281 msaitoh M_CSUM_TCPv4 | M_CSUM_UDPv4 |
6266 1.281 msaitoh M_CSUM_TCPv6 | M_CSUM_UDPv6;
6267 1.281 msaitoh if (errors & WRX_ER_TCPE)
6268 1.281 msaitoh m->m_pkthdr.csum_flags |=
6269 1.281 msaitoh M_CSUM_TCP_UDP_BAD;
6270 1.281 msaitoh }
6271 1.281 msaitoh }
6272 1.117 msaitoh
6273 1.281 msaitoh ifp->if_ipackets++;
6274 1.117 msaitoh
6275 1.283 ozaki WM_RX_UNLOCK(sc);
6276 1.45 thorpej
6277 1.281 msaitoh /* Pass this up to any BPF listeners. */
6278 1.281 msaitoh bpf_mtap(ifp, m);
6279 1.46 thorpej
6280 1.281 msaitoh /* Pass it on. */
6281 1.281 msaitoh (*ifp->if_input)(ifp, m);
6282 1.46 thorpej
6283 1.283 ozaki WM_RX_LOCK(sc);
6284 1.46 thorpej
6285 1.281 msaitoh if (sc->sc_stopping)
6286 1.281 msaitoh break;
6287 1.48 thorpej }
6288 1.281 msaitoh
6289 1.281 msaitoh /* Update the receive pointer. */
6290 1.281 msaitoh sc->sc_rxptr = i;
6291 1.335 msaitoh if (count != 0)
6292 1.335 msaitoh rnd_add_uint32(&sc->rnd_source, count);
6293 1.281 msaitoh
6294 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6295 1.281 msaitoh ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i));
6296 1.48 thorpej }
6297 1.48 thorpej
6298 1.48 thorpej /*
6299 1.281 msaitoh * wm_linkintr_gmii:
6300 1.50 thorpej *
6301 1.281 msaitoh * Helper; handle link interrupts for GMII.
6302 1.50 thorpej */
6303 1.281 msaitoh static void
6304 1.281 msaitoh wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
6305 1.50 thorpej {
6306 1.51 thorpej
6307 1.283 ozaki KASSERT(WM_TX_LOCKED(sc));
6308 1.281 msaitoh
6309 1.281 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
6310 1.281 msaitoh __func__));
6311 1.281 msaitoh
6312 1.281 msaitoh if (icr & ICR_LSC) {
6313 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
6314 1.281 msaitoh ("%s: LINK: LSC -> mii_pollstat\n",
6315 1.281 msaitoh device_xname(sc->sc_dev)));
6316 1.281 msaitoh mii_pollstat(&sc->sc_mii);
6317 1.281 msaitoh if (sc->sc_type == WM_T_82543) {
6318 1.281 msaitoh int miistatus, active;
6319 1.281 msaitoh
6320 1.281 msaitoh /*
6321 1.281 msaitoh * With 82543, we need to force speed and
6322 1.281 msaitoh * duplex on the MAC equal to what the PHY
6323 1.281 msaitoh * speed and duplex configuration is.
6324 1.281 msaitoh */
6325 1.281 msaitoh miistatus = sc->sc_mii.mii_media_status;
6326 1.50 thorpej
6327 1.281 msaitoh if (miistatus & IFM_ACTIVE) {
6328 1.281 msaitoh active = sc->sc_mii.mii_media_active;
6329 1.281 msaitoh sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
6330 1.281 msaitoh switch (IFM_SUBTYPE(active)) {
6331 1.281 msaitoh case IFM_10_T:
6332 1.281 msaitoh sc->sc_ctrl |= CTRL_SPEED_10;
6333 1.281 msaitoh break;
6334 1.281 msaitoh case IFM_100_TX:
6335 1.281 msaitoh sc->sc_ctrl |= CTRL_SPEED_100;
6336 1.281 msaitoh break;
6337 1.281 msaitoh case IFM_1000_T:
6338 1.281 msaitoh sc->sc_ctrl |= CTRL_SPEED_1000;
6339 1.281 msaitoh break;
6340 1.281 msaitoh default:
6341 1.281 msaitoh /*
6342 1.281 msaitoh * fiber?
6343 1.281 msaitoh * Shoud not enter here.
6344 1.281 msaitoh */
6345 1.281 msaitoh printf("unknown media (%x)\n",
6346 1.281 msaitoh active);
6347 1.281 msaitoh break;
6348 1.281 msaitoh }
6349 1.281 msaitoh if (active & IFM_FDX)
6350 1.281 msaitoh sc->sc_ctrl |= CTRL_FD;
6351 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
6352 1.281 msaitoh }
6353 1.281 msaitoh } else if ((sc->sc_type == WM_T_ICH8)
6354 1.281 msaitoh && (sc->sc_phytype == WMPHY_IGP_3)) {
6355 1.281 msaitoh wm_kmrn_lock_loss_workaround_ich8lan(sc);
6356 1.281 msaitoh } else if (sc->sc_type == WM_T_PCH) {
6357 1.281 msaitoh wm_k1_gig_workaround_hv(sc,
6358 1.281 msaitoh ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
6359 1.230 msaitoh }
6360 1.51 thorpej
6361 1.281 msaitoh if ((sc->sc_phytype == WMPHY_82578)
6362 1.281 msaitoh && (IFM_SUBTYPE(sc->sc_mii.mii_media_active)
6363 1.281 msaitoh == IFM_1000_T)) {
6364 1.51 thorpej
6365 1.281 msaitoh if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0) {
6366 1.281 msaitoh delay(200*1000); /* XXX too big */
6367 1.51 thorpej
6368 1.281 msaitoh /* Link stall fix for link up */
6369 1.281 msaitoh wm_gmii_hv_writereg(sc->sc_dev, 1,
6370 1.281 msaitoh HV_MUX_DATA_CTRL,
6371 1.281 msaitoh HV_MUX_DATA_CTRL_GEN_TO_MAC
6372 1.281 msaitoh | HV_MUX_DATA_CTRL_FORCE_SPEED);
6373 1.281 msaitoh wm_gmii_hv_writereg(sc->sc_dev, 1,
6374 1.281 msaitoh HV_MUX_DATA_CTRL,
6375 1.281 msaitoh HV_MUX_DATA_CTRL_GEN_TO_MAC);
6376 1.281 msaitoh }
6377 1.281 msaitoh }
6378 1.281 msaitoh } else if (icr & ICR_RXSEQ) {
6379 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
6380 1.281 msaitoh ("%s: LINK Receive sequence error\n",
6381 1.281 msaitoh device_xname(sc->sc_dev)));
6382 1.51 thorpej }
6383 1.50 thorpej }
6384 1.50 thorpej
6385 1.50 thorpej /*
6386 1.281 msaitoh * wm_linkintr_tbi:
6387 1.57 thorpej *
6388 1.281 msaitoh * Helper; handle link interrupts for TBI mode.
6389 1.57 thorpej */
6390 1.281 msaitoh static void
6391 1.281 msaitoh wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
6392 1.57 thorpej {
6393 1.281 msaitoh uint32_t status;
6394 1.281 msaitoh
6395 1.281 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
6396 1.281 msaitoh __func__));
6397 1.281 msaitoh
6398 1.281 msaitoh status = CSR_READ(sc, WMREG_STATUS);
6399 1.281 msaitoh if (icr & ICR_LSC) {
6400 1.281 msaitoh if (status & STATUS_LU) {
6401 1.281 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
6402 1.281 msaitoh device_xname(sc->sc_dev),
6403 1.281 msaitoh (status & STATUS_FD) ? "FDX" : "HDX"));
6404 1.281 msaitoh /*
6405 1.281 msaitoh * NOTE: CTRL will update TFCE and RFCE automatically,
6406 1.281 msaitoh * so we should update sc->sc_ctrl
6407 1.281 msaitoh */
6408 1.57 thorpej
6409 1.281 msaitoh sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
6410 1.281 msaitoh sc->sc_tctl &= ~TCTL_COLD(0x3ff);
6411 1.281 msaitoh sc->sc_fcrtl &= ~FCRTL_XONE;
6412 1.281 msaitoh if (status & STATUS_FD)
6413 1.281 msaitoh sc->sc_tctl |=
6414 1.281 msaitoh TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
6415 1.281 msaitoh else
6416 1.281 msaitoh sc->sc_tctl |=
6417 1.281 msaitoh TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
6418 1.281 msaitoh if (sc->sc_ctrl & CTRL_TFCE)
6419 1.281 msaitoh sc->sc_fcrtl |= FCRTL_XONE;
6420 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
6421 1.281 msaitoh CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
6422 1.281 msaitoh WMREG_OLD_FCRTL : WMREG_FCRTL,
6423 1.281 msaitoh sc->sc_fcrtl);
6424 1.281 msaitoh sc->sc_tbi_linkup = 1;
6425 1.281 msaitoh } else {
6426 1.281 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
6427 1.281 msaitoh device_xname(sc->sc_dev)));
6428 1.281 msaitoh sc->sc_tbi_linkup = 0;
6429 1.281 msaitoh }
6430 1.325 msaitoh /* Update LED */
6431 1.325 msaitoh wm_tbi_serdes_set_linkled(sc);
6432 1.281 msaitoh } else if (icr & ICR_RXSEQ) {
6433 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
6434 1.281 msaitoh ("%s: LINK: Receive sequence error\n",
6435 1.281 msaitoh device_xname(sc->sc_dev)));
6436 1.57 thorpej }
6437 1.57 thorpej }
6438 1.57 thorpej
6439 1.57 thorpej /*
6440 1.325 msaitoh * wm_linkintr_serdes:
6441 1.325 msaitoh *
6442 1.325 msaitoh * Helper; handle link interrupts for TBI mode.
6443 1.325 msaitoh */
6444 1.325 msaitoh static void
6445 1.325 msaitoh wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
6446 1.325 msaitoh {
6447 1.325 msaitoh struct mii_data *mii = &sc->sc_mii;
6448 1.325 msaitoh struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
6449 1.325 msaitoh uint32_t pcs_adv, pcs_lpab, reg;
6450 1.325 msaitoh
6451 1.325 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
6452 1.325 msaitoh __func__));
6453 1.325 msaitoh
6454 1.325 msaitoh if (icr & ICR_LSC) {
6455 1.325 msaitoh /* Check PCS */
6456 1.325 msaitoh reg = CSR_READ(sc, WMREG_PCS_LSTS);
6457 1.325 msaitoh if ((reg & PCS_LSTS_LINKOK) != 0) {
6458 1.325 msaitoh mii->mii_media_status |= IFM_ACTIVE;
6459 1.325 msaitoh sc->sc_tbi_linkup = 1;
6460 1.325 msaitoh } else {
6461 1.325 msaitoh mii->mii_media_status |= IFM_NONE;
6462 1.325 msaitoh sc->sc_tbi_linkup = 0;
6463 1.325 msaitoh wm_tbi_serdes_set_linkled(sc);
6464 1.325 msaitoh return;
6465 1.325 msaitoh }
6466 1.325 msaitoh mii->mii_media_active |= IFM_1000_SX;
6467 1.325 msaitoh if ((reg & PCS_LSTS_FDX) != 0)
6468 1.325 msaitoh mii->mii_media_active |= IFM_FDX;
6469 1.325 msaitoh else
6470 1.325 msaitoh mii->mii_media_active |= IFM_HDX;
6471 1.325 msaitoh if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
6472 1.325 msaitoh /* Check flow */
6473 1.325 msaitoh reg = CSR_READ(sc, WMREG_PCS_LSTS);
6474 1.325 msaitoh if ((reg & PCS_LSTS_AN_COMP) == 0) {
6475 1.325 msaitoh DPRINTF(WM_DEBUG_LINK,
6476 1.325 msaitoh ("XXX LINKOK but not ACOMP\n"));
6477 1.325 msaitoh return;
6478 1.325 msaitoh }
6479 1.325 msaitoh pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
6480 1.325 msaitoh pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
6481 1.325 msaitoh DPRINTF(WM_DEBUG_LINK,
6482 1.325 msaitoh ("XXX AN result %08x, %08x\n", pcs_adv, pcs_lpab));
6483 1.325 msaitoh if ((pcs_adv & TXCW_SYM_PAUSE)
6484 1.325 msaitoh && (pcs_lpab & TXCW_SYM_PAUSE)) {
6485 1.325 msaitoh mii->mii_media_active |= IFM_FLOW
6486 1.325 msaitoh | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
6487 1.325 msaitoh } else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
6488 1.325 msaitoh && (pcs_adv & TXCW_ASYM_PAUSE)
6489 1.325 msaitoh && (pcs_lpab & TXCW_SYM_PAUSE)
6490 1.325 msaitoh && (pcs_lpab & TXCW_ASYM_PAUSE))
6491 1.325 msaitoh mii->mii_media_active |= IFM_FLOW
6492 1.325 msaitoh | IFM_ETH_TXPAUSE;
6493 1.325 msaitoh else if ((pcs_adv & TXCW_SYM_PAUSE)
6494 1.325 msaitoh && (pcs_adv & TXCW_ASYM_PAUSE)
6495 1.325 msaitoh && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
6496 1.325 msaitoh && (pcs_lpab & TXCW_ASYM_PAUSE))
6497 1.325 msaitoh mii->mii_media_active |= IFM_FLOW
6498 1.325 msaitoh | IFM_ETH_RXPAUSE;
6499 1.325 msaitoh }
6500 1.325 msaitoh /* Update LED */
6501 1.325 msaitoh wm_tbi_serdes_set_linkled(sc);
6502 1.325 msaitoh } else {
6503 1.325 msaitoh DPRINTF(WM_DEBUG_LINK,
6504 1.325 msaitoh ("%s: LINK: Receive sequence error\n",
6505 1.325 msaitoh device_xname(sc->sc_dev)));
6506 1.325 msaitoh }
6507 1.325 msaitoh }
6508 1.325 msaitoh
6509 1.325 msaitoh /*
6510 1.281 msaitoh * wm_linkintr:
6511 1.57 thorpej *
6512 1.281 msaitoh * Helper; handle link interrupts.
6513 1.57 thorpej */
6514 1.281 msaitoh static void
6515 1.281 msaitoh wm_linkintr(struct wm_softc *sc, uint32_t icr)
6516 1.57 thorpej {
6517 1.57 thorpej
6518 1.281 msaitoh if (sc->sc_flags & WM_F_HAS_MII)
6519 1.281 msaitoh wm_linkintr_gmii(sc, icr);
6520 1.325 msaitoh else if ((sc->sc_mediatype == WM_MEDIATYPE_SERDES)
6521 1.332 msaitoh && (sc->sc_type >= WM_T_82575))
6522 1.325 msaitoh wm_linkintr_serdes(sc, icr);
6523 1.281 msaitoh else
6524 1.281 msaitoh wm_linkintr_tbi(sc, icr);
6525 1.57 thorpej }
6526 1.57 thorpej
6527 1.112 gavan /*
6528 1.335 msaitoh * wm_intr_legacy:
6529 1.112 gavan *
6530 1.335 msaitoh * Interrupt service routine for INTx and MSI.
6531 1.112 gavan */
6532 1.112 gavan static int
6533 1.335 msaitoh wm_intr_legacy(void *arg)
6534 1.198 msaitoh {
6535 1.281 msaitoh struct wm_softc *sc = arg;
6536 1.281 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
6537 1.335 msaitoh uint32_t icr, rndval = 0;
6538 1.281 msaitoh int handled = 0;
6539 1.281 msaitoh
6540 1.335 msaitoh DPRINTF(WM_DEBUG_TX,
6541 1.335 msaitoh ("%s: INTx: got intr\n", device_xname(sc->sc_dev)));
6542 1.281 msaitoh while (1 /* CONSTCOND */) {
6543 1.281 msaitoh icr = CSR_READ(sc, WMREG_ICR);
6544 1.281 msaitoh if ((icr & sc->sc_icr) == 0)
6545 1.281 msaitoh break;
6546 1.335 msaitoh if (rndval == 0)
6547 1.335 msaitoh rndval = icr;
6548 1.112 gavan
6549 1.283 ozaki WM_RX_LOCK(sc);
6550 1.112 gavan
6551 1.281 msaitoh if (sc->sc_stopping) {
6552 1.283 ozaki WM_RX_UNLOCK(sc);
6553 1.281 msaitoh break;
6554 1.281 msaitoh }
6555 1.247 msaitoh
6556 1.281 msaitoh handled = 1;
6557 1.249 msaitoh
6558 1.281 msaitoh #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
6559 1.281 msaitoh if (icr & (ICR_RXDMT0|ICR_RXT0)) {
6560 1.281 msaitoh DPRINTF(WM_DEBUG_RX,
6561 1.281 msaitoh ("%s: RX: got Rx intr 0x%08x\n",
6562 1.281 msaitoh device_xname(sc->sc_dev),
6563 1.281 msaitoh icr & (ICR_RXDMT0|ICR_RXT0)));
6564 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_rxintr);
6565 1.240 msaitoh }
6566 1.281 msaitoh #endif
6567 1.335 msaitoh wm_rxeof(sc);
6568 1.240 msaitoh
6569 1.283 ozaki WM_RX_UNLOCK(sc);
6570 1.283 ozaki WM_TX_LOCK(sc);
6571 1.283 ozaki
6572 1.281 msaitoh #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
6573 1.281 msaitoh if (icr & ICR_TXDW) {
6574 1.281 msaitoh DPRINTF(WM_DEBUG_TX,
6575 1.281 msaitoh ("%s: TX: got TXDW interrupt\n",
6576 1.281 msaitoh device_xname(sc->sc_dev)));
6577 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txdw);
6578 1.240 msaitoh }
6579 1.281 msaitoh #endif
6580 1.335 msaitoh wm_txeof(sc);
6581 1.240 msaitoh
6582 1.285 msaitoh if (icr & (ICR_LSC|ICR_RXSEQ)) {
6583 1.281 msaitoh WM_EVCNT_INCR(&sc->sc_ev_linkintr);
6584 1.281 msaitoh wm_linkintr(sc, icr);
6585 1.281 msaitoh }
6586 1.240 msaitoh
6587 1.283 ozaki WM_TX_UNLOCK(sc);
6588 1.112 gavan
6589 1.281 msaitoh if (icr & ICR_RXO) {
6590 1.281 msaitoh #if defined(WM_DEBUG)
6591 1.281 msaitoh log(LOG_WARNING, "%s: Receive overrun\n",
6592 1.281 msaitoh device_xname(sc->sc_dev));
6593 1.281 msaitoh #endif /* defined(WM_DEBUG) */
6594 1.281 msaitoh }
6595 1.249 msaitoh }
6596 1.112 gavan
6597 1.335 msaitoh rnd_add_uint32(&sc->rnd_source, rndval);
6598 1.335 msaitoh
6599 1.335 msaitoh if (handled) {
6600 1.335 msaitoh /* Try to get more packets going. */
6601 1.335 msaitoh ifp->if_start(ifp);
6602 1.335 msaitoh }
6603 1.335 msaitoh
6604 1.335 msaitoh return handled;
6605 1.335 msaitoh }
6606 1.335 msaitoh
6607 1.335 msaitoh #ifdef WM_MSI_MSIX
6608 1.335 msaitoh /*
6609 1.335 msaitoh * wm_txintr_msix:
6610 1.335 msaitoh *
6611 1.335 msaitoh * Interrupt service routine for TX complete interrupt for MSI-X.
6612 1.335 msaitoh */
6613 1.335 msaitoh static int
6614 1.335 msaitoh wm_txintr_msix(void *arg)
6615 1.335 msaitoh {
6616 1.335 msaitoh struct wm_softc *sc = arg;
6617 1.335 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
6618 1.335 msaitoh int handled = 0;
6619 1.335 msaitoh
6620 1.335 msaitoh DPRINTF(WM_DEBUG_TX,
6621 1.335 msaitoh ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev)));
6622 1.335 msaitoh
6623 1.335 msaitoh if (sc->sc_type == WM_T_82574)
6624 1.335 msaitoh CSR_WRITE(sc, WMREG_IMC, ICR_TXQ0); /* 82574 only */
6625 1.335 msaitoh else if (sc->sc_type == WM_T_82575)
6626 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMC, EITR_TX_QUEUE0);
6627 1.335 msaitoh else
6628 1.340 knakahar CSR_WRITE(sc, WMREG_EIMC, 1 << WM_MSIX_TXINTR_IDX);
6629 1.335 msaitoh
6630 1.335 msaitoh WM_TX_LOCK(sc);
6631 1.335 msaitoh
6632 1.335 msaitoh if (sc->sc_stopping)
6633 1.335 msaitoh goto out;
6634 1.335 msaitoh
6635 1.335 msaitoh WM_EVCNT_INCR(&sc->sc_ev_txdw);
6636 1.335 msaitoh handled = wm_txeof(sc);
6637 1.335 msaitoh
6638 1.335 msaitoh out:
6639 1.335 msaitoh WM_TX_UNLOCK(sc);
6640 1.335 msaitoh
6641 1.335 msaitoh if (sc->sc_type == WM_T_82574)
6642 1.335 msaitoh CSR_WRITE(sc, WMREG_IMS, ICR_TXQ0); /* 82574 only */
6643 1.335 msaitoh else if (sc->sc_type == WM_T_82575)
6644 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMS, EITR_TX_QUEUE0);
6645 1.335 msaitoh else
6646 1.340 knakahar CSR_WRITE(sc, WMREG_EIMS, 1 << WM_MSIX_TXINTR_IDX);
6647 1.335 msaitoh
6648 1.281 msaitoh if (handled) {
6649 1.281 msaitoh /* Try to get more packets going. */
6650 1.281 msaitoh ifp->if_start(ifp);
6651 1.117 msaitoh }
6652 1.119 uebayasi
6653 1.281 msaitoh return handled;
6654 1.117 msaitoh }
6655 1.117 msaitoh
6656 1.281 msaitoh /*
6657 1.335 msaitoh * wm_rxintr_msix:
6658 1.335 msaitoh *
6659 1.335 msaitoh * Interrupt service routine for RX interrupt for MSI-X.
6660 1.335 msaitoh */
6661 1.335 msaitoh static int
6662 1.335 msaitoh wm_rxintr_msix(void *arg)
6663 1.335 msaitoh {
6664 1.335 msaitoh struct wm_softc *sc = arg;
6665 1.335 msaitoh
6666 1.335 msaitoh DPRINTF(WM_DEBUG_TX,
6667 1.335 msaitoh ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev)));
6668 1.335 msaitoh
6669 1.335 msaitoh if (sc->sc_type == WM_T_82574)
6670 1.335 msaitoh CSR_WRITE(sc, WMREG_IMC, ICR_RXQ0); /* 82574 only */
6671 1.335 msaitoh else if (sc->sc_type == WM_T_82575)
6672 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMC, EITR_RX_QUEUE0);
6673 1.335 msaitoh else
6674 1.340 knakahar CSR_WRITE(sc, WMREG_EIMC, 1 << WM_MSIX_RXINTR_IDX);
6675 1.335 msaitoh
6676 1.335 msaitoh WM_RX_LOCK(sc);
6677 1.335 msaitoh
6678 1.335 msaitoh if (sc->sc_stopping)
6679 1.335 msaitoh goto out;
6680 1.335 msaitoh
6681 1.335 msaitoh WM_EVCNT_INCR(&sc->sc_ev_rxintr);
6682 1.335 msaitoh wm_rxeof(sc);
6683 1.335 msaitoh
6684 1.335 msaitoh out:
6685 1.335 msaitoh WM_RX_UNLOCK(sc);
6686 1.335 msaitoh
6687 1.335 msaitoh if (sc->sc_type == WM_T_82574)
6688 1.335 msaitoh CSR_WRITE(sc, WMREG_IMS, ICR_RXQ0);
6689 1.335 msaitoh else if (sc->sc_type == WM_T_82575)
6690 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMS, EITR_RX_QUEUE0);
6691 1.335 msaitoh else
6692 1.340 knakahar CSR_WRITE(sc, WMREG_EIMS, 1 << WM_MSIX_RXINTR_IDX);
6693 1.335 msaitoh
6694 1.335 msaitoh return 1;
6695 1.335 msaitoh }
6696 1.335 msaitoh
6697 1.335 msaitoh /*
6698 1.335 msaitoh * wm_linkintr_msix:
6699 1.335 msaitoh *
6700 1.335 msaitoh * Interrupt service routine for link status change for MSI-X.
6701 1.335 msaitoh */
6702 1.335 msaitoh static int
6703 1.335 msaitoh wm_linkintr_msix(void *arg)
6704 1.335 msaitoh {
6705 1.335 msaitoh struct wm_softc *sc = arg;
6706 1.335 msaitoh
6707 1.335 msaitoh DPRINTF(WM_DEBUG_TX,
6708 1.335 msaitoh ("%s: LINK: got link intr\n", device_xname(sc->sc_dev)));
6709 1.335 msaitoh
6710 1.335 msaitoh if (sc->sc_type == WM_T_82574)
6711 1.335 msaitoh CSR_WRITE(sc, WMREG_IMC, ICR_OTHER); /* 82574 only */
6712 1.335 msaitoh else if (sc->sc_type == WM_T_82575)
6713 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMC, EITR_OTHER);
6714 1.335 msaitoh else
6715 1.340 knakahar CSR_WRITE(sc, WMREG_EIMC, 1 << WM_MSIX_LINKINTR_IDX);
6716 1.335 msaitoh WM_TX_LOCK(sc);
6717 1.335 msaitoh if (sc->sc_stopping)
6718 1.335 msaitoh goto out;
6719 1.335 msaitoh
6720 1.335 msaitoh WM_EVCNT_INCR(&sc->sc_ev_linkintr);
6721 1.335 msaitoh wm_linkintr(sc, ICR_LSC);
6722 1.335 msaitoh
6723 1.335 msaitoh out:
6724 1.335 msaitoh WM_TX_UNLOCK(sc);
6725 1.335 msaitoh
6726 1.335 msaitoh if (sc->sc_type == WM_T_82574)
6727 1.335 msaitoh CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC); /* 82574 only */
6728 1.335 msaitoh else if (sc->sc_type == WM_T_82575)
6729 1.335 msaitoh CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER);
6730 1.335 msaitoh else
6731 1.340 knakahar CSR_WRITE(sc, WMREG_EIMS, 1 << WM_MSIX_LINKINTR_IDX);
6732 1.335 msaitoh
6733 1.335 msaitoh return 1;
6734 1.335 msaitoh }
6735 1.335 msaitoh #endif /* WM_MSI_MSIX */
6736 1.335 msaitoh
6737 1.335 msaitoh /*
6738 1.281 msaitoh * Media related.
6739 1.281 msaitoh * GMII, SGMII, TBI (and SERDES)
6740 1.281 msaitoh */
6741 1.117 msaitoh
6742 1.325 msaitoh /* Common */
6743 1.325 msaitoh
6744 1.325 msaitoh /*
6745 1.325 msaitoh * wm_tbi_serdes_set_linkled:
6746 1.325 msaitoh *
6747 1.325 msaitoh * Update the link LED on TBI and SERDES devices.
6748 1.325 msaitoh */
6749 1.325 msaitoh static void
6750 1.325 msaitoh wm_tbi_serdes_set_linkled(struct wm_softc *sc)
6751 1.325 msaitoh {
6752 1.325 msaitoh
6753 1.325 msaitoh if (sc->sc_tbi_linkup)
6754 1.325 msaitoh sc->sc_ctrl |= CTRL_SWDPIN(0);
6755 1.325 msaitoh else
6756 1.325 msaitoh sc->sc_ctrl &= ~CTRL_SWDPIN(0);
6757 1.325 msaitoh
6758 1.325 msaitoh /* 82540 or newer devices are active low */
6759 1.325 msaitoh sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0;
6760 1.325 msaitoh
6761 1.325 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
6762 1.325 msaitoh }
6763 1.325 msaitoh
6764 1.281 msaitoh /* GMII related */
6765 1.117 msaitoh
6766 1.280 msaitoh /*
6767 1.281 msaitoh * wm_gmii_reset:
6768 1.280 msaitoh *
6769 1.281 msaitoh * Reset the PHY.
6770 1.280 msaitoh */
6771 1.281 msaitoh static void
6772 1.281 msaitoh wm_gmii_reset(struct wm_softc *sc)
6773 1.280 msaitoh {
6774 1.281 msaitoh uint32_t reg;
6775 1.280 msaitoh int rv;
6776 1.280 msaitoh
6777 1.281 msaitoh /* get phy semaphore */
6778 1.281 msaitoh switch (sc->sc_type) {
6779 1.281 msaitoh case WM_T_82571:
6780 1.281 msaitoh case WM_T_82572:
6781 1.281 msaitoh case WM_T_82573:
6782 1.281 msaitoh case WM_T_82574:
6783 1.281 msaitoh case WM_T_82583:
6784 1.281 msaitoh /* XXX should get sw semaphore, too */
6785 1.281 msaitoh rv = wm_get_swsm_semaphore(sc);
6786 1.281 msaitoh break;
6787 1.281 msaitoh case WM_T_82575:
6788 1.281 msaitoh case WM_T_82576:
6789 1.281 msaitoh case WM_T_82580:
6790 1.281 msaitoh case WM_T_I350:
6791 1.281 msaitoh case WM_T_I354:
6792 1.281 msaitoh case WM_T_I210:
6793 1.281 msaitoh case WM_T_I211:
6794 1.281 msaitoh case WM_T_80003:
6795 1.281 msaitoh rv = wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
6796 1.281 msaitoh break;
6797 1.281 msaitoh case WM_T_ICH8:
6798 1.281 msaitoh case WM_T_ICH9:
6799 1.281 msaitoh case WM_T_ICH10:
6800 1.281 msaitoh case WM_T_PCH:
6801 1.281 msaitoh case WM_T_PCH2:
6802 1.281 msaitoh case WM_T_PCH_LPT:
6803 1.281 msaitoh rv = wm_get_swfwhw_semaphore(sc);
6804 1.281 msaitoh break;
6805 1.281 msaitoh default:
6806 1.281 msaitoh /* nothing to do*/
6807 1.281 msaitoh rv = 0;
6808 1.281 msaitoh break;
6809 1.281 msaitoh }
6810 1.281 msaitoh if (rv != 0) {
6811 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
6812 1.281 msaitoh __func__);
6813 1.281 msaitoh return;
6814 1.281 msaitoh }
6815 1.280 msaitoh
6816 1.281 msaitoh switch (sc->sc_type) {
6817 1.281 msaitoh case WM_T_82542_2_0:
6818 1.281 msaitoh case WM_T_82542_2_1:
6819 1.281 msaitoh /* null */
6820 1.281 msaitoh break;
6821 1.281 msaitoh case WM_T_82543:
6822 1.281 msaitoh /*
6823 1.281 msaitoh * With 82543, we need to force speed and duplex on the MAC
6824 1.281 msaitoh * equal to what the PHY speed and duplex configuration is.
6825 1.281 msaitoh * In addition, we need to perform a hardware reset on the PHY
6826 1.281 msaitoh * to take it out of reset.
6827 1.281 msaitoh */
6828 1.281 msaitoh sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
6829 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
6830 1.280 msaitoh
6831 1.281 msaitoh /* The PHY reset pin is active-low. */
6832 1.281 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
6833 1.281 msaitoh reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
6834 1.281 msaitoh CTRL_EXT_SWDPIN(4));
6835 1.281 msaitoh reg |= CTRL_EXT_SWDPIO(4);
6836 1.218 msaitoh
6837 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
6838 1.281 msaitoh CSR_WRITE_FLUSH(sc);
6839 1.281 msaitoh delay(10*1000);
6840 1.218 msaitoh
6841 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
6842 1.281 msaitoh CSR_WRITE_FLUSH(sc);
6843 1.281 msaitoh delay(150);
6844 1.281 msaitoh #if 0
6845 1.281 msaitoh sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
6846 1.281 msaitoh #endif
6847 1.281 msaitoh delay(20*1000); /* XXX extra delay to get PHY ID? */
6848 1.281 msaitoh break;
6849 1.281 msaitoh case WM_T_82544: /* reset 10000us */
6850 1.281 msaitoh case WM_T_82540:
6851 1.281 msaitoh case WM_T_82545:
6852 1.281 msaitoh case WM_T_82545_3:
6853 1.281 msaitoh case WM_T_82546:
6854 1.281 msaitoh case WM_T_82546_3:
6855 1.281 msaitoh case WM_T_82541:
6856 1.281 msaitoh case WM_T_82541_2:
6857 1.281 msaitoh case WM_T_82547:
6858 1.281 msaitoh case WM_T_82547_2:
6859 1.281 msaitoh case WM_T_82571: /* reset 100us */
6860 1.281 msaitoh case WM_T_82572:
6861 1.281 msaitoh case WM_T_82573:
6862 1.281 msaitoh case WM_T_82574:
6863 1.281 msaitoh case WM_T_82575:
6864 1.281 msaitoh case WM_T_82576:
6865 1.218 msaitoh case WM_T_82580:
6866 1.228 msaitoh case WM_T_I350:
6867 1.265 msaitoh case WM_T_I354:
6868 1.281 msaitoh case WM_T_I210:
6869 1.281 msaitoh case WM_T_I211:
6870 1.281 msaitoh case WM_T_82583:
6871 1.281 msaitoh case WM_T_80003:
6872 1.281 msaitoh /* generic reset */
6873 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
6874 1.281 msaitoh CSR_WRITE_FLUSH(sc);
6875 1.281 msaitoh delay(20000);
6876 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
6877 1.281 msaitoh CSR_WRITE_FLUSH(sc);
6878 1.281 msaitoh delay(20000);
6879 1.281 msaitoh
6880 1.281 msaitoh if ((sc->sc_type == WM_T_82541)
6881 1.281 msaitoh || (sc->sc_type == WM_T_82541_2)
6882 1.281 msaitoh || (sc->sc_type == WM_T_82547)
6883 1.281 msaitoh || (sc->sc_type == WM_T_82547_2)) {
6884 1.281 msaitoh /* workaround for igp are done in igp_reset() */
6885 1.281 msaitoh /* XXX add code to set LED after phy reset */
6886 1.218 msaitoh }
6887 1.218 msaitoh break;
6888 1.281 msaitoh case WM_T_ICH8:
6889 1.281 msaitoh case WM_T_ICH9:
6890 1.281 msaitoh case WM_T_ICH10:
6891 1.281 msaitoh case WM_T_PCH:
6892 1.281 msaitoh case WM_T_PCH2:
6893 1.281 msaitoh case WM_T_PCH_LPT:
6894 1.281 msaitoh /* generic reset */
6895 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
6896 1.281 msaitoh CSR_WRITE_FLUSH(sc);
6897 1.281 msaitoh delay(100);
6898 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
6899 1.281 msaitoh CSR_WRITE_FLUSH(sc);
6900 1.281 msaitoh delay(150);
6901 1.281 msaitoh break;
6902 1.281 msaitoh default:
6903 1.281 msaitoh panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
6904 1.281 msaitoh __func__);
6905 1.281 msaitoh break;
6906 1.281 msaitoh }
6907 1.281 msaitoh
6908 1.281 msaitoh /* release PHY semaphore */
6909 1.281 msaitoh switch (sc->sc_type) {
6910 1.218 msaitoh case WM_T_82571:
6911 1.281 msaitoh case WM_T_82572:
6912 1.281 msaitoh case WM_T_82573:
6913 1.281 msaitoh case WM_T_82574:
6914 1.281 msaitoh case WM_T_82583:
6915 1.281 msaitoh /* XXX should put sw semaphore, too */
6916 1.281 msaitoh wm_put_swsm_semaphore(sc);
6917 1.281 msaitoh break;
6918 1.218 msaitoh case WM_T_82575:
6919 1.218 msaitoh case WM_T_82576:
6920 1.281 msaitoh case WM_T_82580:
6921 1.281 msaitoh case WM_T_I350:
6922 1.281 msaitoh case WM_T_I354:
6923 1.247 msaitoh case WM_T_I210:
6924 1.247 msaitoh case WM_T_I211:
6925 1.281 msaitoh case WM_T_80003:
6926 1.281 msaitoh wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
6927 1.281 msaitoh break;
6928 1.281 msaitoh case WM_T_ICH8:
6929 1.281 msaitoh case WM_T_ICH9:
6930 1.281 msaitoh case WM_T_ICH10:
6931 1.281 msaitoh case WM_T_PCH:
6932 1.281 msaitoh case WM_T_PCH2:
6933 1.281 msaitoh case WM_T_PCH_LPT:
6934 1.281 msaitoh wm_put_swfwhw_semaphore(sc);
6935 1.218 msaitoh break;
6936 1.218 msaitoh default:
6937 1.281 msaitoh /* nothing to do*/
6938 1.281 msaitoh rv = 0;
6939 1.218 msaitoh break;
6940 1.218 msaitoh }
6941 1.210 msaitoh
6942 1.281 msaitoh /* get_cfg_done */
6943 1.281 msaitoh wm_get_cfg_done(sc);
6944 1.208 msaitoh
6945 1.281 msaitoh /* extra setup */
6946 1.281 msaitoh switch (sc->sc_type) {
6947 1.281 msaitoh case WM_T_82542_2_0:
6948 1.281 msaitoh case WM_T_82542_2_1:
6949 1.281 msaitoh case WM_T_82543:
6950 1.281 msaitoh case WM_T_82544:
6951 1.281 msaitoh case WM_T_82540:
6952 1.281 msaitoh case WM_T_82545:
6953 1.281 msaitoh case WM_T_82545_3:
6954 1.281 msaitoh case WM_T_82546:
6955 1.281 msaitoh case WM_T_82546_3:
6956 1.281 msaitoh case WM_T_82541_2:
6957 1.281 msaitoh case WM_T_82547_2:
6958 1.281 msaitoh case WM_T_82571:
6959 1.281 msaitoh case WM_T_82572:
6960 1.281 msaitoh case WM_T_82573:
6961 1.281 msaitoh case WM_T_82574:
6962 1.281 msaitoh case WM_T_82575:
6963 1.281 msaitoh case WM_T_82576:
6964 1.281 msaitoh case WM_T_82580:
6965 1.281 msaitoh case WM_T_I350:
6966 1.281 msaitoh case WM_T_I354:
6967 1.281 msaitoh case WM_T_I210:
6968 1.281 msaitoh case WM_T_I211:
6969 1.281 msaitoh case WM_T_82583:
6970 1.281 msaitoh case WM_T_80003:
6971 1.281 msaitoh /* null */
6972 1.281 msaitoh break;
6973 1.281 msaitoh case WM_T_82541:
6974 1.281 msaitoh case WM_T_82547:
6975 1.281 msaitoh /* XXX Configure actively LED after PHY reset */
6976 1.281 msaitoh break;
6977 1.281 msaitoh case WM_T_ICH8:
6978 1.281 msaitoh case WM_T_ICH9:
6979 1.281 msaitoh case WM_T_ICH10:
6980 1.281 msaitoh case WM_T_PCH:
6981 1.281 msaitoh case WM_T_PCH2:
6982 1.281 msaitoh case WM_T_PCH_LPT:
6983 1.281 msaitoh /* Allow time for h/w to get to a quiescent state afer reset */
6984 1.281 msaitoh delay(10*1000);
6985 1.1 thorpej
6986 1.281 msaitoh if (sc->sc_type == WM_T_PCH)
6987 1.281 msaitoh wm_hv_phy_workaround_ich8lan(sc);
6988 1.1 thorpej
6989 1.281 msaitoh if (sc->sc_type == WM_T_PCH2)
6990 1.281 msaitoh wm_lv_phy_workaround_ich8lan(sc);
6991 1.1 thorpej
6992 1.281 msaitoh if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)) {
6993 1.281 msaitoh /*
6994 1.281 msaitoh * dummy read to clear the phy wakeup bit after lcd
6995 1.281 msaitoh * reset
6996 1.281 msaitoh */
6997 1.281 msaitoh reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC);
6998 1.281 msaitoh }
6999 1.1 thorpej
7000 1.281 msaitoh /*
7001 1.281 msaitoh * XXX Configure the LCD with th extended configuration region
7002 1.281 msaitoh * in NVM
7003 1.281 msaitoh */
7004 1.1 thorpej
7005 1.281 msaitoh /* Configure the LCD with the OEM bits in NVM */
7006 1.281 msaitoh if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
7007 1.281 msaitoh || (sc->sc_type == WM_T_PCH_LPT)) {
7008 1.281 msaitoh /*
7009 1.281 msaitoh * Disable LPLU.
7010 1.281 msaitoh * XXX It seems that 82567 has LPLU, too.
7011 1.281 msaitoh */
7012 1.281 msaitoh reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_OEM_BITS);
7013 1.281 msaitoh reg &= ~(HV_OEM_BITS_A1KDIS| HV_OEM_BITS_LPLU);
7014 1.281 msaitoh reg |= HV_OEM_BITS_ANEGNOW;
7015 1.281 msaitoh wm_gmii_hv_writereg(sc->sc_dev, 1, HV_OEM_BITS, reg);
7016 1.281 msaitoh }
7017 1.281 msaitoh break;
7018 1.281 msaitoh default:
7019 1.281 msaitoh panic("%s: unknown type\n", __func__);
7020 1.281 msaitoh break;
7021 1.1 thorpej }
7022 1.1 thorpej }
7023 1.1 thorpej
7024 1.1 thorpej /*
7025 1.281 msaitoh * wm_get_phy_id_82575:
7026 1.1 thorpej *
7027 1.281 msaitoh * Return PHY ID. Return -1 if it failed.
7028 1.1 thorpej */
7029 1.281 msaitoh static int
7030 1.281 msaitoh wm_get_phy_id_82575(struct wm_softc *sc)
7031 1.1 thorpej {
7032 1.281 msaitoh uint32_t reg;
7033 1.281 msaitoh int phyid = -1;
7034 1.281 msaitoh
7035 1.281 msaitoh /* XXX */
7036 1.281 msaitoh if ((sc->sc_flags & WM_F_SGMII) == 0)
7037 1.281 msaitoh return -1;
7038 1.1 thorpej
7039 1.281 msaitoh if (wm_sgmii_uses_mdio(sc)) {
7040 1.281 msaitoh switch (sc->sc_type) {
7041 1.281 msaitoh case WM_T_82575:
7042 1.281 msaitoh case WM_T_82576:
7043 1.281 msaitoh reg = CSR_READ(sc, WMREG_MDIC);
7044 1.281 msaitoh phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT;
7045 1.281 msaitoh break;
7046 1.281 msaitoh case WM_T_82580:
7047 1.281 msaitoh case WM_T_I350:
7048 1.281 msaitoh case WM_T_I354:
7049 1.281 msaitoh case WM_T_I210:
7050 1.281 msaitoh case WM_T_I211:
7051 1.281 msaitoh reg = CSR_READ(sc, WMREG_MDICNFG);
7052 1.281 msaitoh phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT;
7053 1.281 msaitoh break;
7054 1.281 msaitoh default:
7055 1.281 msaitoh return -1;
7056 1.281 msaitoh }
7057 1.139 bouyer }
7058 1.1 thorpej
7059 1.281 msaitoh return phyid;
7060 1.1 thorpej }
7061 1.1 thorpej
7062 1.281 msaitoh
7063 1.1 thorpej /*
7064 1.281 msaitoh * wm_gmii_mediainit:
7065 1.1 thorpej *
7066 1.281 msaitoh * Initialize media for use on 1000BASE-T devices.
7067 1.1 thorpej */
7068 1.47 thorpej static void
7069 1.281 msaitoh wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
7070 1.1 thorpej {
7071 1.1 thorpej struct ifnet *ifp = &sc->sc_ethercom.ec_if;
7072 1.281 msaitoh struct mii_data *mii = &sc->sc_mii;
7073 1.282 msaitoh uint32_t reg;
7074 1.281 msaitoh
7075 1.292 msaitoh /* We have GMII. */
7076 1.281 msaitoh sc->sc_flags |= WM_F_HAS_MII;
7077 1.1 thorpej
7078 1.281 msaitoh if (sc->sc_type == WM_T_80003)
7079 1.281 msaitoh sc->sc_tipg = TIPG_1000T_80003_DFLT;
7080 1.1 thorpej else
7081 1.281 msaitoh sc->sc_tipg = TIPG_1000T_DFLT;
7082 1.1 thorpej
7083 1.282 msaitoh /* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */
7084 1.300 msaitoh if ((sc->sc_type == WM_T_82580)
7085 1.282 msaitoh || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210)
7086 1.282 msaitoh || (sc->sc_type == WM_T_I211)) {
7087 1.282 msaitoh reg = CSR_READ(sc, WMREG_PHPM);
7088 1.282 msaitoh reg &= ~PHPM_GO_LINK_D;
7089 1.282 msaitoh CSR_WRITE(sc, WMREG_PHPM, reg);
7090 1.282 msaitoh }
7091 1.282 msaitoh
7092 1.281 msaitoh /*
7093 1.281 msaitoh * Let the chip set speed/duplex on its own based on
7094 1.281 msaitoh * signals from the PHY.
7095 1.281 msaitoh * XXXbouyer - I'm not sure this is right for the 80003,
7096 1.281 msaitoh * the em driver only sets CTRL_SLU here - but it seems to work.
7097 1.281 msaitoh */
7098 1.281 msaitoh sc->sc_ctrl |= CTRL_SLU;
7099 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
7100 1.1 thorpej
7101 1.281 msaitoh /* Initialize our media structures and probe the GMII. */
7102 1.281 msaitoh mii->mii_ifp = ifp;
7103 1.1 thorpej
7104 1.1 thorpej /*
7105 1.281 msaitoh * Determine the PHY access method.
7106 1.281 msaitoh *
7107 1.281 msaitoh * For SGMII, use SGMII specific method.
7108 1.281 msaitoh *
7109 1.281 msaitoh * For some devices, we can determine the PHY access method
7110 1.281 msaitoh * from sc_type.
7111 1.281 msaitoh *
7112 1.316 msaitoh * For ICH and PCH variants, it's difficult to determine the PHY
7113 1.316 msaitoh * access method by sc_type, so use the PCI product ID for some
7114 1.316 msaitoh * devices.
7115 1.281 msaitoh * For other ICH8 variants, try to use igp's method. If the PHY
7116 1.281 msaitoh * can't detect, then use bm's method.
7117 1.1 thorpej */
7118 1.281 msaitoh switch (prodid) {
7119 1.281 msaitoh case PCI_PRODUCT_INTEL_PCH_M_LM:
7120 1.281 msaitoh case PCI_PRODUCT_INTEL_PCH_M_LC:
7121 1.281 msaitoh /* 82577 */
7122 1.281 msaitoh sc->sc_phytype = WMPHY_82577;
7123 1.281 msaitoh break;
7124 1.281 msaitoh case PCI_PRODUCT_INTEL_PCH_D_DM:
7125 1.281 msaitoh case PCI_PRODUCT_INTEL_PCH_D_DC:
7126 1.281 msaitoh /* 82578 */
7127 1.281 msaitoh sc->sc_phytype = WMPHY_82578;
7128 1.281 msaitoh break;
7129 1.281 msaitoh case PCI_PRODUCT_INTEL_PCH2_LV_LM:
7130 1.281 msaitoh case PCI_PRODUCT_INTEL_PCH2_LV_V:
7131 1.281 msaitoh /* 82579 */
7132 1.281 msaitoh sc->sc_phytype = WMPHY_82579;
7133 1.281 msaitoh break;
7134 1.281 msaitoh case PCI_PRODUCT_INTEL_82801I_BM:
7135 1.281 msaitoh case PCI_PRODUCT_INTEL_82801J_R_BM_LM:
7136 1.281 msaitoh case PCI_PRODUCT_INTEL_82801J_R_BM_LF:
7137 1.281 msaitoh case PCI_PRODUCT_INTEL_82801J_D_BM_LM:
7138 1.281 msaitoh case PCI_PRODUCT_INTEL_82801J_D_BM_LF:
7139 1.281 msaitoh case PCI_PRODUCT_INTEL_82801J_R_BM_V:
7140 1.281 msaitoh /* 82567 */
7141 1.281 msaitoh sc->sc_phytype = WMPHY_BM;
7142 1.281 msaitoh mii->mii_readreg = wm_gmii_bm_readreg;
7143 1.281 msaitoh mii->mii_writereg = wm_gmii_bm_writereg;
7144 1.281 msaitoh break;
7145 1.281 msaitoh default:
7146 1.281 msaitoh if (((sc->sc_flags & WM_F_SGMII) != 0)
7147 1.281 msaitoh && !wm_sgmii_uses_mdio(sc)){
7148 1.329 msaitoh /* SGMII */
7149 1.281 msaitoh mii->mii_readreg = wm_sgmii_readreg;
7150 1.281 msaitoh mii->mii_writereg = wm_sgmii_writereg;
7151 1.281 msaitoh } else if (sc->sc_type >= WM_T_80003) {
7152 1.329 msaitoh /* 80003 */
7153 1.281 msaitoh mii->mii_readreg = wm_gmii_i80003_readreg;
7154 1.281 msaitoh mii->mii_writereg = wm_gmii_i80003_writereg;
7155 1.281 msaitoh } else if (sc->sc_type >= WM_T_I210) {
7156 1.329 msaitoh /* I210 and I211 */
7157 1.329 msaitoh mii->mii_readreg = wm_gmii_gs40g_readreg;
7158 1.329 msaitoh mii->mii_writereg = wm_gmii_gs40g_writereg;
7159 1.281 msaitoh } else if (sc->sc_type >= WM_T_82580) {
7160 1.329 msaitoh /* 82580, I350 and I354 */
7161 1.281 msaitoh sc->sc_phytype = WMPHY_82580;
7162 1.281 msaitoh mii->mii_readreg = wm_gmii_82580_readreg;
7163 1.281 msaitoh mii->mii_writereg = wm_gmii_82580_writereg;
7164 1.281 msaitoh } else if (sc->sc_type >= WM_T_82544) {
7165 1.329 msaitoh /* 82544, 0, [56], [17], 8257[1234] and 82583 */
7166 1.281 msaitoh mii->mii_readreg = wm_gmii_i82544_readreg;
7167 1.281 msaitoh mii->mii_writereg = wm_gmii_i82544_writereg;
7168 1.281 msaitoh } else {
7169 1.281 msaitoh mii->mii_readreg = wm_gmii_i82543_readreg;
7170 1.281 msaitoh mii->mii_writereg = wm_gmii_i82543_writereg;
7171 1.1 thorpej }
7172 1.281 msaitoh break;
7173 1.1 thorpej }
7174 1.316 msaitoh if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_LPT)) {
7175 1.316 msaitoh /* All PCH* use _hv_ */
7176 1.316 msaitoh mii->mii_readreg = wm_gmii_hv_readreg;
7177 1.316 msaitoh mii->mii_writereg = wm_gmii_hv_writereg;
7178 1.316 msaitoh }
7179 1.281 msaitoh mii->mii_statchg = wm_gmii_statchg;
7180 1.1 thorpej
7181 1.281 msaitoh wm_gmii_reset(sc);
7182 1.1 thorpej
7183 1.281 msaitoh sc->sc_ethercom.ec_mii = &sc->sc_mii;
7184 1.327 msaitoh ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange,
7185 1.327 msaitoh wm_gmii_mediastatus);
7186 1.1 thorpej
7187 1.281 msaitoh if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
7188 1.300 msaitoh || (sc->sc_type == WM_T_82580)
7189 1.281 msaitoh || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
7190 1.281 msaitoh || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) {
7191 1.281 msaitoh if ((sc->sc_flags & WM_F_SGMII) == 0) {
7192 1.281 msaitoh /* Attach only one port */
7193 1.281 msaitoh mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
7194 1.281 msaitoh MII_OFFSET_ANY, MIIF_DOPAUSE);
7195 1.281 msaitoh } else {
7196 1.281 msaitoh int i, id;
7197 1.281 msaitoh uint32_t ctrl_ext;
7198 1.1 thorpej
7199 1.281 msaitoh id = wm_get_phy_id_82575(sc);
7200 1.281 msaitoh if (id != -1) {
7201 1.281 msaitoh mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
7202 1.281 msaitoh id, MII_OFFSET_ANY, MIIF_DOPAUSE);
7203 1.281 msaitoh }
7204 1.281 msaitoh if ((id == -1)
7205 1.281 msaitoh || (LIST_FIRST(&mii->mii_phys) == NULL)) {
7206 1.281 msaitoh /* Power on sgmii phy if it is disabled */
7207 1.281 msaitoh ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
7208 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT,
7209 1.281 msaitoh ctrl_ext &~ CTRL_EXT_SWDPIN(3));
7210 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7211 1.281 msaitoh delay(300*1000); /* XXX too long */
7212 1.1 thorpej
7213 1.281 msaitoh /* from 1 to 8 */
7214 1.281 msaitoh for (i = 1; i < 8; i++)
7215 1.281 msaitoh mii_attach(sc->sc_dev, &sc->sc_mii,
7216 1.281 msaitoh 0xffffffff, i, MII_OFFSET_ANY,
7217 1.281 msaitoh MIIF_DOPAUSE);
7218 1.1 thorpej
7219 1.281 msaitoh /* restore previous sfp cage power state */
7220 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
7221 1.281 msaitoh }
7222 1.281 msaitoh }
7223 1.281 msaitoh } else {
7224 1.281 msaitoh mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
7225 1.281 msaitoh MII_OFFSET_ANY, MIIF_DOPAUSE);
7226 1.281 msaitoh }
7227 1.173 msaitoh
7228 1.281 msaitoh /*
7229 1.281 msaitoh * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
7230 1.281 msaitoh * wm_set_mdio_slow_mode_hv() for a workaround and retry.
7231 1.281 msaitoh */
7232 1.281 msaitoh if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) &&
7233 1.281 msaitoh (LIST_FIRST(&mii->mii_phys) == NULL)) {
7234 1.281 msaitoh wm_set_mdio_slow_mode_hv(sc);
7235 1.281 msaitoh mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
7236 1.281 msaitoh MII_OFFSET_ANY, MIIF_DOPAUSE);
7237 1.281 msaitoh }
7238 1.1 thorpej
7239 1.1 thorpej /*
7240 1.281 msaitoh * (For ICH8 variants)
7241 1.281 msaitoh * If PHY detection failed, use BM's r/w function and retry.
7242 1.1 thorpej */
7243 1.281 msaitoh if (LIST_FIRST(&mii->mii_phys) == NULL) {
7244 1.281 msaitoh /* if failed, retry with *_bm_* */
7245 1.281 msaitoh mii->mii_readreg = wm_gmii_bm_readreg;
7246 1.281 msaitoh mii->mii_writereg = wm_gmii_bm_writereg;
7247 1.1 thorpej
7248 1.281 msaitoh mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
7249 1.281 msaitoh MII_OFFSET_ANY, MIIF_DOPAUSE);
7250 1.281 msaitoh }
7251 1.1 thorpej
7252 1.281 msaitoh if (LIST_FIRST(&mii->mii_phys) == NULL) {
7253 1.281 msaitoh /* Any PHY wasn't find */
7254 1.281 msaitoh ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
7255 1.281 msaitoh ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE);
7256 1.281 msaitoh sc->sc_phytype = WMPHY_NONE;
7257 1.281 msaitoh } else {
7258 1.281 msaitoh /*
7259 1.281 msaitoh * PHY Found!
7260 1.281 msaitoh * Check PHY type.
7261 1.281 msaitoh */
7262 1.281 msaitoh uint32_t model;
7263 1.281 msaitoh struct mii_softc *child;
7264 1.1 thorpej
7265 1.281 msaitoh child = LIST_FIRST(&mii->mii_phys);
7266 1.281 msaitoh if (device_is_a(child->mii_dev, "igphy")) {
7267 1.281 msaitoh struct igphy_softc *isc = (struct igphy_softc *)child;
7268 1.1 thorpej
7269 1.281 msaitoh model = isc->sc_mii.mii_mpd_model;
7270 1.281 msaitoh if (model == MII_MODEL_yyINTEL_I82566)
7271 1.281 msaitoh sc->sc_phytype = WMPHY_IGP_3;
7272 1.281 msaitoh }
7273 1.1 thorpej
7274 1.281 msaitoh ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
7275 1.281 msaitoh }
7276 1.1 thorpej }
7277 1.1 thorpej
7278 1.1 thorpej /*
7279 1.281 msaitoh * wm_gmii_mediachange: [ifmedia interface function]
7280 1.1 thorpej *
7281 1.281 msaitoh * Set hardware to newly-selected media on a 1000BASE-T device.
7282 1.1 thorpej */
7283 1.47 thorpej static int
7284 1.281 msaitoh wm_gmii_mediachange(struct ifnet *ifp)
7285 1.1 thorpej {
7286 1.1 thorpej struct wm_softc *sc = ifp->if_softc;
7287 1.1 thorpej struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
7288 1.281 msaitoh int rc;
7289 1.1 thorpej
7290 1.281 msaitoh if ((ifp->if_flags & IFF_UP) == 0)
7291 1.279 msaitoh return 0;
7292 1.279 msaitoh
7293 1.281 msaitoh sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
7294 1.281 msaitoh sc->sc_ctrl |= CTRL_SLU;
7295 1.281 msaitoh if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
7296 1.281 msaitoh || (sc->sc_type > WM_T_82543)) {
7297 1.281 msaitoh sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX);
7298 1.134 msaitoh } else {
7299 1.281 msaitoh sc->sc_ctrl &= ~CTRL_ASDE;
7300 1.281 msaitoh sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
7301 1.281 msaitoh if (ife->ifm_media & IFM_FDX)
7302 1.281 msaitoh sc->sc_ctrl |= CTRL_FD;
7303 1.281 msaitoh switch (IFM_SUBTYPE(ife->ifm_media)) {
7304 1.281 msaitoh case IFM_10_T:
7305 1.281 msaitoh sc->sc_ctrl |= CTRL_SPEED_10;
7306 1.281 msaitoh break;
7307 1.281 msaitoh case IFM_100_TX:
7308 1.281 msaitoh sc->sc_ctrl |= CTRL_SPEED_100;
7309 1.281 msaitoh break;
7310 1.281 msaitoh case IFM_1000_T:
7311 1.281 msaitoh sc->sc_ctrl |= CTRL_SPEED_1000;
7312 1.281 msaitoh break;
7313 1.281 msaitoh default:
7314 1.281 msaitoh panic("wm_gmii_mediachange: bad media 0x%x",
7315 1.281 msaitoh ife->ifm_media);
7316 1.281 msaitoh }
7317 1.134 msaitoh }
7318 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
7319 1.281 msaitoh if (sc->sc_type <= WM_T_82543)
7320 1.281 msaitoh wm_gmii_reset(sc);
7321 1.281 msaitoh
7322 1.281 msaitoh if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
7323 1.281 msaitoh return 0;
7324 1.281 msaitoh return rc;
7325 1.281 msaitoh }
7326 1.1 thorpej
7327 1.324 msaitoh /*
7328 1.324 msaitoh * wm_gmii_mediastatus: [ifmedia interface function]
7329 1.324 msaitoh *
7330 1.324 msaitoh * Get the current interface media status on a 1000BASE-T device.
7331 1.324 msaitoh */
7332 1.324 msaitoh static void
7333 1.324 msaitoh wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
7334 1.324 msaitoh {
7335 1.324 msaitoh struct wm_softc *sc = ifp->if_softc;
7336 1.324 msaitoh
7337 1.324 msaitoh ether_mediastatus(ifp, ifmr);
7338 1.324 msaitoh ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
7339 1.324 msaitoh | sc->sc_flowflags;
7340 1.324 msaitoh }
7341 1.324 msaitoh
7342 1.281 msaitoh #define MDI_IO CTRL_SWDPIN(2)
7343 1.281 msaitoh #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */
7344 1.281 msaitoh #define MDI_CLK CTRL_SWDPIN(3)
7345 1.1 thorpej
7346 1.281 msaitoh static void
7347 1.281 msaitoh wm_i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
7348 1.281 msaitoh {
7349 1.281 msaitoh uint32_t i, v;
7350 1.134 msaitoh
7351 1.281 msaitoh v = CSR_READ(sc, WMREG_CTRL);
7352 1.281 msaitoh v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
7353 1.281 msaitoh v |= MDI_DIR | CTRL_SWDPIO(3);
7354 1.134 msaitoh
7355 1.281 msaitoh for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
7356 1.281 msaitoh if (data & i)
7357 1.281 msaitoh v |= MDI_IO;
7358 1.281 msaitoh else
7359 1.281 msaitoh v &= ~MDI_IO;
7360 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v);
7361 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7362 1.281 msaitoh delay(10);
7363 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
7364 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7365 1.281 msaitoh delay(10);
7366 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v);
7367 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7368 1.281 msaitoh delay(10);
7369 1.281 msaitoh }
7370 1.281 msaitoh }
7371 1.134 msaitoh
7372 1.281 msaitoh static uint32_t
7373 1.281 msaitoh wm_i82543_mii_recvbits(struct wm_softc *sc)
7374 1.281 msaitoh {
7375 1.281 msaitoh uint32_t v, i, data = 0;
7376 1.1 thorpej
7377 1.281 msaitoh v = CSR_READ(sc, WMREG_CTRL);
7378 1.281 msaitoh v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
7379 1.281 msaitoh v |= CTRL_SWDPIO(3);
7380 1.134 msaitoh
7381 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v);
7382 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7383 1.281 msaitoh delay(10);
7384 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
7385 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7386 1.281 msaitoh delay(10);
7387 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v);
7388 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7389 1.281 msaitoh delay(10);
7390 1.173 msaitoh
7391 1.281 msaitoh for (i = 0; i < 16; i++) {
7392 1.281 msaitoh data <<= 1;
7393 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
7394 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7395 1.281 msaitoh delay(10);
7396 1.281 msaitoh if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
7397 1.281 msaitoh data |= 1;
7398 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v);
7399 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7400 1.281 msaitoh delay(10);
7401 1.1 thorpej }
7402 1.1 thorpej
7403 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
7404 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7405 1.281 msaitoh delay(10);
7406 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, v);
7407 1.281 msaitoh CSR_WRITE_FLUSH(sc);
7408 1.281 msaitoh delay(10);
7409 1.1 thorpej
7410 1.281 msaitoh return data;
7411 1.1 thorpej }
7412 1.1 thorpej
7413 1.281 msaitoh #undef MDI_IO
7414 1.281 msaitoh #undef MDI_DIR
7415 1.281 msaitoh #undef MDI_CLK
7416 1.281 msaitoh
7417 1.1 thorpej /*
7418 1.281 msaitoh * wm_gmii_i82543_readreg: [mii interface function]
7419 1.1 thorpej *
7420 1.281 msaitoh * Read a PHY register on the GMII (i82543 version).
7421 1.1 thorpej */
7422 1.281 msaitoh static int
7423 1.281 msaitoh wm_gmii_i82543_readreg(device_t self, int phy, int reg)
7424 1.1 thorpej {
7425 1.281 msaitoh struct wm_softc *sc = device_private(self);
7426 1.281 msaitoh int rv;
7427 1.1 thorpej
7428 1.281 msaitoh wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
7429 1.281 msaitoh wm_i82543_mii_sendbits(sc, reg | (phy << 5) |
7430 1.281 msaitoh (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
7431 1.281 msaitoh rv = wm_i82543_mii_recvbits(sc) & 0xffff;
7432 1.1 thorpej
7433 1.281 msaitoh DPRINTF(WM_DEBUG_GMII,
7434 1.281 msaitoh ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
7435 1.281 msaitoh device_xname(sc->sc_dev), phy, reg, rv));
7436 1.173 msaitoh
7437 1.281 msaitoh return rv;
7438 1.1 thorpej }
7439 1.1 thorpej
7440 1.1 thorpej /*
7441 1.281 msaitoh * wm_gmii_i82543_writereg: [mii interface function]
7442 1.1 thorpej *
7443 1.281 msaitoh * Write a PHY register on the GMII (i82543 version).
7444 1.1 thorpej */
7445 1.47 thorpej static void
7446 1.281 msaitoh wm_gmii_i82543_writereg(device_t self, int phy, int reg, int val)
7447 1.1 thorpej {
7448 1.281 msaitoh struct wm_softc *sc = device_private(self);
7449 1.1 thorpej
7450 1.281 msaitoh wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
7451 1.281 msaitoh wm_i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
7452 1.281 msaitoh (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
7453 1.281 msaitoh (MII_COMMAND_START << 30), 32);
7454 1.281 msaitoh }
7455 1.272 ozaki
7456 1.281 msaitoh /*
7457 1.281 msaitoh * wm_gmii_i82544_readreg: [mii interface function]
7458 1.281 msaitoh *
7459 1.281 msaitoh * Read a PHY register on the GMII.
7460 1.281 msaitoh */
7461 1.281 msaitoh static int
7462 1.281 msaitoh wm_gmii_i82544_readreg(device_t self, int phy, int reg)
7463 1.281 msaitoh {
7464 1.281 msaitoh struct wm_softc *sc = device_private(self);
7465 1.281 msaitoh uint32_t mdic = 0;
7466 1.281 msaitoh int i, rv;
7467 1.279 msaitoh
7468 1.281 msaitoh CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
7469 1.281 msaitoh MDIC_REGADD(reg));
7470 1.1 thorpej
7471 1.281 msaitoh for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
7472 1.281 msaitoh mdic = CSR_READ(sc, WMREG_MDIC);
7473 1.281 msaitoh if (mdic & MDIC_READY)
7474 1.281 msaitoh break;
7475 1.327 msaitoh delay(50);
7476 1.1 thorpej }
7477 1.1 thorpej
7478 1.281 msaitoh if ((mdic & MDIC_READY) == 0) {
7479 1.281 msaitoh log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
7480 1.281 msaitoh device_xname(sc->sc_dev), phy, reg);
7481 1.281 msaitoh rv = 0;
7482 1.281 msaitoh } else if (mdic & MDIC_E) {
7483 1.281 msaitoh #if 0 /* This is normal if no PHY is present. */
7484 1.281 msaitoh log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
7485 1.281 msaitoh device_xname(sc->sc_dev), phy, reg);
7486 1.281 msaitoh #endif
7487 1.281 msaitoh rv = 0;
7488 1.281 msaitoh } else {
7489 1.281 msaitoh rv = MDIC_DATA(mdic);
7490 1.281 msaitoh if (rv == 0xffff)
7491 1.281 msaitoh rv = 0;
7492 1.173 msaitoh }
7493 1.173 msaitoh
7494 1.281 msaitoh return rv;
7495 1.1 thorpej }
7496 1.1 thorpej
7497 1.1 thorpej /*
7498 1.281 msaitoh * wm_gmii_i82544_writereg: [mii interface function]
7499 1.1 thorpej *
7500 1.281 msaitoh * Write a PHY register on the GMII.
7501 1.1 thorpej */
7502 1.47 thorpej static void
7503 1.281 msaitoh wm_gmii_i82544_writereg(device_t self, int phy, int reg, int val)
7504 1.1 thorpej {
7505 1.281 msaitoh struct wm_softc *sc = device_private(self);
7506 1.281 msaitoh uint32_t mdic = 0;
7507 1.281 msaitoh int i;
7508 1.281 msaitoh
7509 1.281 msaitoh CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
7510 1.281 msaitoh MDIC_REGADD(reg) | MDIC_DATA(val));
7511 1.1 thorpej
7512 1.281 msaitoh for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
7513 1.281 msaitoh mdic = CSR_READ(sc, WMREG_MDIC);
7514 1.281 msaitoh if (mdic & MDIC_READY)
7515 1.281 msaitoh break;
7516 1.327 msaitoh delay(50);
7517 1.127 bouyer }
7518 1.1 thorpej
7519 1.281 msaitoh if ((mdic & MDIC_READY) == 0)
7520 1.281 msaitoh log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n",
7521 1.281 msaitoh device_xname(sc->sc_dev), phy, reg);
7522 1.281 msaitoh else if (mdic & MDIC_E)
7523 1.281 msaitoh log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n",
7524 1.281 msaitoh device_xname(sc->sc_dev), phy, reg);
7525 1.281 msaitoh }
7526 1.133 msaitoh
7527 1.281 msaitoh /*
7528 1.281 msaitoh * wm_gmii_i80003_readreg: [mii interface function]
7529 1.281 msaitoh *
7530 1.281 msaitoh * Read a PHY register on the kumeran
7531 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7532 1.281 msaitoh * ressource ...
7533 1.281 msaitoh */
7534 1.281 msaitoh static int
7535 1.281 msaitoh wm_gmii_i80003_readreg(device_t self, int phy, int reg)
7536 1.281 msaitoh {
7537 1.281 msaitoh struct wm_softc *sc = device_private(self);
7538 1.281 msaitoh int sem;
7539 1.281 msaitoh int rv;
7540 1.1 thorpej
7541 1.281 msaitoh if (phy != 1) /* only one PHY on kumeran bus */
7542 1.281 msaitoh return 0;
7543 1.1 thorpej
7544 1.281 msaitoh sem = swfwphysem[sc->sc_funcid];
7545 1.281 msaitoh if (wm_get_swfw_semaphore(sc, sem)) {
7546 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7547 1.189 msaitoh __func__);
7548 1.281 msaitoh return 0;
7549 1.1 thorpej }
7550 1.186 msaitoh
7551 1.281 msaitoh if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
7552 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
7553 1.281 msaitoh reg >> GG82563_PAGE_SHIFT);
7554 1.281 msaitoh } else {
7555 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT,
7556 1.281 msaitoh reg >> GG82563_PAGE_SHIFT);
7557 1.189 msaitoh }
7558 1.281 msaitoh /* Wait more 200us for a bug of the ready bit in the MDIC register */
7559 1.281 msaitoh delay(200);
7560 1.281 msaitoh rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS);
7561 1.281 msaitoh delay(200);
7562 1.189 msaitoh
7563 1.281 msaitoh wm_put_swfw_semaphore(sc, sem);
7564 1.281 msaitoh return rv;
7565 1.281 msaitoh }
7566 1.190 msaitoh
7567 1.281 msaitoh /*
7568 1.281 msaitoh * wm_gmii_i80003_writereg: [mii interface function]
7569 1.281 msaitoh *
7570 1.281 msaitoh * Write a PHY register on the kumeran.
7571 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7572 1.281 msaitoh * ressource ...
7573 1.281 msaitoh */
7574 1.281 msaitoh static void
7575 1.281 msaitoh wm_gmii_i80003_writereg(device_t self, int phy, int reg, int val)
7576 1.281 msaitoh {
7577 1.281 msaitoh struct wm_softc *sc = device_private(self);
7578 1.281 msaitoh int sem;
7579 1.221 msaitoh
7580 1.281 msaitoh if (phy != 1) /* only one PHY on kumeran bus */
7581 1.281 msaitoh return;
7582 1.190 msaitoh
7583 1.281 msaitoh sem = swfwphysem[sc->sc_funcid];
7584 1.281 msaitoh if (wm_get_swfw_semaphore(sc, sem)) {
7585 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7586 1.281 msaitoh __func__);
7587 1.281 msaitoh return;
7588 1.281 msaitoh }
7589 1.192 msaitoh
7590 1.281 msaitoh if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
7591 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
7592 1.281 msaitoh reg >> GG82563_PAGE_SHIFT);
7593 1.281 msaitoh } else {
7594 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT,
7595 1.281 msaitoh reg >> GG82563_PAGE_SHIFT);
7596 1.189 msaitoh }
7597 1.281 msaitoh /* Wait more 200us for a bug of the ready bit in the MDIC register */
7598 1.281 msaitoh delay(200);
7599 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val);
7600 1.281 msaitoh delay(200);
7601 1.281 msaitoh
7602 1.281 msaitoh wm_put_swfw_semaphore(sc, sem);
7603 1.1 thorpej }
7604 1.1 thorpej
7605 1.1 thorpej /*
7606 1.281 msaitoh * wm_gmii_bm_readreg: [mii interface function]
7607 1.265 msaitoh *
7608 1.281 msaitoh * Read a PHY register on the kumeran
7609 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7610 1.281 msaitoh * ressource ...
7611 1.265 msaitoh */
7612 1.265 msaitoh static int
7613 1.281 msaitoh wm_gmii_bm_readreg(device_t self, int phy, int reg)
7614 1.265 msaitoh {
7615 1.281 msaitoh struct wm_softc *sc = device_private(self);
7616 1.281 msaitoh int sem;
7617 1.281 msaitoh int rv;
7618 1.265 msaitoh
7619 1.281 msaitoh sem = swfwphysem[sc->sc_funcid];
7620 1.281 msaitoh if (wm_get_swfw_semaphore(sc, sem)) {
7621 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7622 1.281 msaitoh __func__);
7623 1.281 msaitoh return 0;
7624 1.281 msaitoh }
7625 1.265 msaitoh
7626 1.281 msaitoh if (reg > BME1000_MAX_MULTI_PAGE_REG) {
7627 1.281 msaitoh if (phy == 1)
7628 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, MII_IGPHY_PAGE_SELECT,
7629 1.281 msaitoh reg);
7630 1.281 msaitoh else
7631 1.281 msaitoh wm_gmii_i82544_writereg(self, phy,
7632 1.281 msaitoh GG82563_PHY_PAGE_SELECT,
7633 1.281 msaitoh reg >> GG82563_PAGE_SHIFT);
7634 1.265 msaitoh }
7635 1.265 msaitoh
7636 1.281 msaitoh rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS);
7637 1.281 msaitoh wm_put_swfw_semaphore(sc, sem);
7638 1.281 msaitoh return rv;
7639 1.265 msaitoh }
7640 1.265 msaitoh
7641 1.265 msaitoh /*
7642 1.281 msaitoh * wm_gmii_bm_writereg: [mii interface function]
7643 1.1 thorpej *
7644 1.281 msaitoh * Write a PHY register on the kumeran.
7645 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7646 1.281 msaitoh * ressource ...
7647 1.1 thorpej */
7648 1.47 thorpej static void
7649 1.281 msaitoh wm_gmii_bm_writereg(device_t self, int phy, int reg, int val)
7650 1.281 msaitoh {
7651 1.281 msaitoh struct wm_softc *sc = device_private(self);
7652 1.281 msaitoh int sem;
7653 1.281 msaitoh
7654 1.281 msaitoh sem = swfwphysem[sc->sc_funcid];
7655 1.281 msaitoh if (wm_get_swfw_semaphore(sc, sem)) {
7656 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7657 1.281 msaitoh __func__);
7658 1.281 msaitoh return;
7659 1.281 msaitoh }
7660 1.281 msaitoh
7661 1.281 msaitoh if (reg > BME1000_MAX_MULTI_PAGE_REG) {
7662 1.281 msaitoh if (phy == 1)
7663 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, MII_IGPHY_PAGE_SELECT,
7664 1.281 msaitoh reg);
7665 1.281 msaitoh else
7666 1.281 msaitoh wm_gmii_i82544_writereg(self, phy,
7667 1.281 msaitoh GG82563_PHY_PAGE_SELECT,
7668 1.281 msaitoh reg >> GG82563_PAGE_SHIFT);
7669 1.281 msaitoh }
7670 1.281 msaitoh
7671 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val);
7672 1.281 msaitoh wm_put_swfw_semaphore(sc, sem);
7673 1.281 msaitoh }
7674 1.281 msaitoh
7675 1.281 msaitoh static void
7676 1.281 msaitoh wm_access_phy_wakeup_reg_bm(device_t self, int offset, int16_t *val, int rd)
7677 1.1 thorpej {
7678 1.281 msaitoh struct wm_softc *sc = device_private(self);
7679 1.281 msaitoh uint16_t regnum = BM_PHY_REG_NUM(offset);
7680 1.281 msaitoh uint16_t wuce;
7681 1.281 msaitoh
7682 1.281 msaitoh /* XXX Gig must be disabled for MDIO accesses to page 800 */
7683 1.281 msaitoh if (sc->sc_type == WM_T_PCH) {
7684 1.281 msaitoh /* XXX e1000 driver do nothing... why? */
7685 1.281 msaitoh }
7686 1.281 msaitoh
7687 1.281 msaitoh /* Set page 769 */
7688 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
7689 1.281 msaitoh BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
7690 1.281 msaitoh
7691 1.281 msaitoh wuce = wm_gmii_i82544_readreg(self, 1, BM_WUC_ENABLE_REG);
7692 1.281 msaitoh
7693 1.281 msaitoh wuce &= ~BM_WUC_HOST_WU_BIT;
7694 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, BM_WUC_ENABLE_REG,
7695 1.281 msaitoh wuce | BM_WUC_ENABLE_BIT);
7696 1.281 msaitoh
7697 1.281 msaitoh /* Select page 800 */
7698 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
7699 1.281 msaitoh BM_WUC_PAGE << BME1000_PAGE_SHIFT);
7700 1.1 thorpej
7701 1.281 msaitoh /* Write page 800 */
7702 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, BM_WUC_ADDRESS_OPCODE, regnum);
7703 1.1 thorpej
7704 1.281 msaitoh if (rd)
7705 1.281 msaitoh *val = wm_gmii_i82544_readreg(self, 1, BM_WUC_DATA_OPCODE);
7706 1.127 bouyer else
7707 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, BM_WUC_DATA_OPCODE, *val);
7708 1.281 msaitoh
7709 1.281 msaitoh /* Set page 769 */
7710 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
7711 1.281 msaitoh BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
7712 1.281 msaitoh
7713 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, BM_WUC_ENABLE_REG, wuce);
7714 1.281 msaitoh }
7715 1.281 msaitoh
7716 1.281 msaitoh /*
7717 1.281 msaitoh * wm_gmii_hv_readreg: [mii interface function]
7718 1.281 msaitoh *
7719 1.281 msaitoh * Read a PHY register on the kumeran
7720 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7721 1.281 msaitoh * ressource ...
7722 1.281 msaitoh */
7723 1.281 msaitoh static int
7724 1.281 msaitoh wm_gmii_hv_readreg(device_t self, int phy, int reg)
7725 1.281 msaitoh {
7726 1.281 msaitoh struct wm_softc *sc = device_private(self);
7727 1.281 msaitoh uint16_t page = BM_PHY_REG_PAGE(reg);
7728 1.281 msaitoh uint16_t regnum = BM_PHY_REG_NUM(reg);
7729 1.281 msaitoh uint16_t val;
7730 1.281 msaitoh int rv;
7731 1.281 msaitoh
7732 1.281 msaitoh if (wm_get_swfwhw_semaphore(sc)) {
7733 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7734 1.281 msaitoh __func__);
7735 1.281 msaitoh return 0;
7736 1.281 msaitoh }
7737 1.281 msaitoh
7738 1.281 msaitoh /* XXX Workaround failure in MDIO access while cable is disconnected */
7739 1.281 msaitoh if (sc->sc_phytype == WMPHY_82577) {
7740 1.281 msaitoh /* XXX must write */
7741 1.281 msaitoh }
7742 1.1 thorpej
7743 1.281 msaitoh /* Page 800 works differently than the rest so it has its own func */
7744 1.281 msaitoh if (page == BM_WUC_PAGE) {
7745 1.281 msaitoh wm_access_phy_wakeup_reg_bm(self, reg, &val, 1);
7746 1.281 msaitoh return val;
7747 1.281 msaitoh }
7748 1.1 thorpej
7749 1.244 msaitoh /*
7750 1.281 msaitoh * Lower than page 768 works differently than the rest so it has its
7751 1.281 msaitoh * own func
7752 1.244 msaitoh */
7753 1.281 msaitoh if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
7754 1.281 msaitoh printf("gmii_hv_readreg!!!\n");
7755 1.281 msaitoh return 0;
7756 1.281 msaitoh }
7757 1.281 msaitoh
7758 1.281 msaitoh if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
7759 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
7760 1.281 msaitoh page << BME1000_PAGE_SHIFT);
7761 1.1 thorpej }
7762 1.1 thorpej
7763 1.281 msaitoh rv = wm_gmii_i82544_readreg(self, phy, regnum & IGPHY_MAXREGADDR);
7764 1.281 msaitoh wm_put_swfwhw_semaphore(sc);
7765 1.281 msaitoh return rv;
7766 1.281 msaitoh }
7767 1.1 thorpej
7768 1.281 msaitoh /*
7769 1.281 msaitoh * wm_gmii_hv_writereg: [mii interface function]
7770 1.281 msaitoh *
7771 1.281 msaitoh * Write a PHY register on the kumeran.
7772 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7773 1.281 msaitoh * ressource ...
7774 1.281 msaitoh */
7775 1.281 msaitoh static void
7776 1.281 msaitoh wm_gmii_hv_writereg(device_t self, int phy, int reg, int val)
7777 1.281 msaitoh {
7778 1.281 msaitoh struct wm_softc *sc = device_private(self);
7779 1.281 msaitoh uint16_t page = BM_PHY_REG_PAGE(reg);
7780 1.281 msaitoh uint16_t regnum = BM_PHY_REG_NUM(reg);
7781 1.1 thorpej
7782 1.281 msaitoh if (wm_get_swfwhw_semaphore(sc)) {
7783 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7784 1.281 msaitoh __func__);
7785 1.281 msaitoh return;
7786 1.281 msaitoh }
7787 1.208 msaitoh
7788 1.281 msaitoh /* XXX Workaround failure in MDIO access while cable is disconnected */
7789 1.265 msaitoh
7790 1.281 msaitoh /* Page 800 works differently than the rest so it has its own func */
7791 1.281 msaitoh if (page == BM_WUC_PAGE) {
7792 1.281 msaitoh uint16_t tmp;
7793 1.208 msaitoh
7794 1.281 msaitoh tmp = val;
7795 1.281 msaitoh wm_access_phy_wakeup_reg_bm(self, reg, &tmp, 0);
7796 1.281 msaitoh return;
7797 1.208 msaitoh }
7798 1.184 msaitoh
7799 1.244 msaitoh /*
7800 1.281 msaitoh * Lower than page 768 works differently than the rest so it has its
7801 1.281 msaitoh * own func
7802 1.244 msaitoh */
7803 1.281 msaitoh if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
7804 1.281 msaitoh printf("gmii_hv_writereg!!!\n");
7805 1.281 msaitoh return;
7806 1.221 msaitoh }
7807 1.244 msaitoh
7808 1.244 msaitoh /*
7809 1.281 msaitoh * XXX Workaround MDIO accesses being disabled after entering IEEE
7810 1.281 msaitoh * Power Down (whenever bit 11 of the PHY control register is set)
7811 1.244 msaitoh */
7812 1.184 msaitoh
7813 1.281 msaitoh if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
7814 1.281 msaitoh wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
7815 1.281 msaitoh page << BME1000_PAGE_SHIFT);
7816 1.281 msaitoh }
7817 1.281 msaitoh
7818 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, regnum & IGPHY_MAXREGADDR, val);
7819 1.281 msaitoh wm_put_swfwhw_semaphore(sc);
7820 1.281 msaitoh }
7821 1.281 msaitoh
7822 1.281 msaitoh /*
7823 1.281 msaitoh * wm_gmii_82580_readreg: [mii interface function]
7824 1.281 msaitoh *
7825 1.281 msaitoh * Read a PHY register on the 82580 and I350.
7826 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7827 1.281 msaitoh * ressource ...
7828 1.281 msaitoh */
7829 1.281 msaitoh static int
7830 1.281 msaitoh wm_gmii_82580_readreg(device_t self, int phy, int reg)
7831 1.281 msaitoh {
7832 1.281 msaitoh struct wm_softc *sc = device_private(self);
7833 1.281 msaitoh int sem;
7834 1.281 msaitoh int rv;
7835 1.281 msaitoh
7836 1.281 msaitoh sem = swfwphysem[sc->sc_funcid];
7837 1.281 msaitoh if (wm_get_swfw_semaphore(sc, sem)) {
7838 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7839 1.281 msaitoh __func__);
7840 1.281 msaitoh return 0;
7841 1.184 msaitoh }
7842 1.244 msaitoh
7843 1.281 msaitoh rv = wm_gmii_i82544_readreg(self, phy, reg);
7844 1.202 msaitoh
7845 1.281 msaitoh wm_put_swfw_semaphore(sc, sem);
7846 1.281 msaitoh return rv;
7847 1.281 msaitoh }
7848 1.202 msaitoh
7849 1.281 msaitoh /*
7850 1.281 msaitoh * wm_gmii_82580_writereg: [mii interface function]
7851 1.281 msaitoh *
7852 1.281 msaitoh * Write a PHY register on the 82580 and I350.
7853 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7854 1.281 msaitoh * ressource ...
7855 1.281 msaitoh */
7856 1.281 msaitoh static void
7857 1.281 msaitoh wm_gmii_82580_writereg(device_t self, int phy, int reg, int val)
7858 1.281 msaitoh {
7859 1.281 msaitoh struct wm_softc *sc = device_private(self);
7860 1.281 msaitoh int sem;
7861 1.202 msaitoh
7862 1.281 msaitoh sem = swfwphysem[sc->sc_funcid];
7863 1.281 msaitoh if (wm_get_swfw_semaphore(sc, sem)) {
7864 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7865 1.281 msaitoh __func__);
7866 1.281 msaitoh return;
7867 1.192 msaitoh }
7868 1.281 msaitoh
7869 1.281 msaitoh wm_gmii_i82544_writereg(self, phy, reg, val);
7870 1.281 msaitoh
7871 1.281 msaitoh wm_put_swfw_semaphore(sc, sem);
7872 1.1 thorpej }
7873 1.1 thorpej
7874 1.1 thorpej /*
7875 1.329 msaitoh * wm_gmii_gs40g_readreg: [mii interface function]
7876 1.329 msaitoh *
7877 1.329 msaitoh * Read a PHY register on the I2100 and I211.
7878 1.329 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7879 1.329 msaitoh * ressource ...
7880 1.329 msaitoh */
7881 1.329 msaitoh static int
7882 1.329 msaitoh wm_gmii_gs40g_readreg(device_t self, int phy, int reg)
7883 1.329 msaitoh {
7884 1.329 msaitoh struct wm_softc *sc = device_private(self);
7885 1.329 msaitoh int sem;
7886 1.329 msaitoh int page, offset;
7887 1.329 msaitoh int rv;
7888 1.329 msaitoh
7889 1.329 msaitoh /* Acquire semaphore */
7890 1.329 msaitoh sem = swfwphysem[sc->sc_funcid];
7891 1.329 msaitoh if (wm_get_swfw_semaphore(sc, sem)) {
7892 1.329 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7893 1.329 msaitoh __func__);
7894 1.329 msaitoh return 0;
7895 1.329 msaitoh }
7896 1.329 msaitoh
7897 1.329 msaitoh /* Page select */
7898 1.329 msaitoh page = reg >> GS40G_PAGE_SHIFT;
7899 1.329 msaitoh wm_gmii_i82544_writereg(self, phy, GS40G_PAGE_SELECT, page);
7900 1.329 msaitoh
7901 1.329 msaitoh /* Read reg */
7902 1.329 msaitoh offset = reg & GS40G_OFFSET_MASK;
7903 1.329 msaitoh rv = wm_gmii_i82544_readreg(self, phy, offset);
7904 1.329 msaitoh
7905 1.329 msaitoh wm_put_swfw_semaphore(sc, sem);
7906 1.329 msaitoh return rv;
7907 1.329 msaitoh }
7908 1.329 msaitoh
7909 1.329 msaitoh /*
7910 1.329 msaitoh * wm_gmii_gs40g_writereg: [mii interface function]
7911 1.329 msaitoh *
7912 1.329 msaitoh * Write a PHY register on the I210 and I211.
7913 1.329 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
7914 1.329 msaitoh * ressource ...
7915 1.329 msaitoh */
7916 1.329 msaitoh static void
7917 1.329 msaitoh wm_gmii_gs40g_writereg(device_t self, int phy, int reg, int val)
7918 1.329 msaitoh {
7919 1.329 msaitoh struct wm_softc *sc = device_private(self);
7920 1.329 msaitoh int sem;
7921 1.329 msaitoh int page, offset;
7922 1.329 msaitoh
7923 1.329 msaitoh /* Acquire semaphore */
7924 1.329 msaitoh sem = swfwphysem[sc->sc_funcid];
7925 1.329 msaitoh if (wm_get_swfw_semaphore(sc, sem)) {
7926 1.329 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
7927 1.329 msaitoh __func__);
7928 1.329 msaitoh return;
7929 1.329 msaitoh }
7930 1.329 msaitoh
7931 1.329 msaitoh /* Page select */
7932 1.329 msaitoh page = reg >> GS40G_PAGE_SHIFT;
7933 1.329 msaitoh wm_gmii_i82544_writereg(self, phy, GS40G_PAGE_SELECT, page);
7934 1.329 msaitoh
7935 1.329 msaitoh /* Write reg */
7936 1.329 msaitoh offset = reg & GS40G_OFFSET_MASK;
7937 1.329 msaitoh wm_gmii_i82544_writereg(self, phy, offset, val);
7938 1.329 msaitoh
7939 1.329 msaitoh /* Release semaphore */
7940 1.329 msaitoh wm_put_swfw_semaphore(sc, sem);
7941 1.329 msaitoh }
7942 1.329 msaitoh
7943 1.329 msaitoh /*
7944 1.281 msaitoh * wm_gmii_statchg: [mii interface function]
7945 1.1 thorpej *
7946 1.281 msaitoh * Callback from MII layer when media changes.
7947 1.1 thorpej */
7948 1.47 thorpej static void
7949 1.281 msaitoh wm_gmii_statchg(struct ifnet *ifp)
7950 1.1 thorpej {
7951 1.1 thorpej struct wm_softc *sc = ifp->if_softc;
7952 1.281 msaitoh struct mii_data *mii = &sc->sc_mii;
7953 1.1 thorpej
7954 1.281 msaitoh sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
7955 1.281 msaitoh sc->sc_tctl &= ~TCTL_COLD(0x3ff);
7956 1.281 msaitoh sc->sc_fcrtl &= ~FCRTL_XONE;
7957 1.1 thorpej
7958 1.281 msaitoh /*
7959 1.281 msaitoh * Get flow control negotiation result.
7960 1.281 msaitoh */
7961 1.281 msaitoh if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
7962 1.281 msaitoh (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
7963 1.281 msaitoh sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
7964 1.281 msaitoh mii->mii_media_active &= ~IFM_ETH_FMASK;
7965 1.281 msaitoh }
7966 1.1 thorpej
7967 1.281 msaitoh if (sc->sc_flowflags & IFM_FLOW) {
7968 1.281 msaitoh if (sc->sc_flowflags & IFM_ETH_TXPAUSE) {
7969 1.281 msaitoh sc->sc_ctrl |= CTRL_TFCE;
7970 1.281 msaitoh sc->sc_fcrtl |= FCRTL_XONE;
7971 1.281 msaitoh }
7972 1.281 msaitoh if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
7973 1.281 msaitoh sc->sc_ctrl |= CTRL_RFCE;
7974 1.281 msaitoh }
7975 1.152 dyoung
7976 1.281 msaitoh if (sc->sc_mii.mii_media_active & IFM_FDX) {
7977 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
7978 1.281 msaitoh ("%s: LINK: statchg: FDX\n", ifp->if_xname));
7979 1.281 msaitoh sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
7980 1.152 dyoung } else {
7981 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
7982 1.281 msaitoh ("%s: LINK: statchg: HDX\n", ifp->if_xname));
7983 1.281 msaitoh sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
7984 1.281 msaitoh }
7985 1.281 msaitoh
7986 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
7987 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
7988 1.281 msaitoh CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
7989 1.281 msaitoh : WMREG_FCRTL, sc->sc_fcrtl);
7990 1.281 msaitoh if (sc->sc_type == WM_T_80003) {
7991 1.281 msaitoh switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
7992 1.152 dyoung case IFM_1000_T:
7993 1.281 msaitoh wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
7994 1.281 msaitoh KUMCTRLSTA_HD_CTRL_1000_DEFAULT);
7995 1.281 msaitoh sc->sc_tipg = TIPG_1000T_80003_DFLT;
7996 1.152 dyoung break;
7997 1.152 dyoung default:
7998 1.281 msaitoh wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
7999 1.281 msaitoh KUMCTRLSTA_HD_CTRL_10_100_DEFAULT);
8000 1.281 msaitoh sc->sc_tipg = TIPG_10_100_80003_DFLT;
8001 1.281 msaitoh break;
8002 1.127 bouyer }
8003 1.281 msaitoh CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
8004 1.127 bouyer }
8005 1.1 thorpej }
8006 1.1 thorpej
8007 1.281 msaitoh /*
8008 1.281 msaitoh * wm_kmrn_readreg:
8009 1.281 msaitoh *
8010 1.281 msaitoh * Read a kumeran register
8011 1.281 msaitoh */
8012 1.281 msaitoh static int
8013 1.281 msaitoh wm_kmrn_readreg(struct wm_softc *sc, int reg)
8014 1.1 thorpej {
8015 1.281 msaitoh int rv;
8016 1.1 thorpej
8017 1.323 msaitoh if (sc->sc_flags & WM_F_LOCK_SWFW) {
8018 1.281 msaitoh if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) {
8019 1.281 msaitoh aprint_error_dev(sc->sc_dev,
8020 1.281 msaitoh "%s: failed to get semaphore\n", __func__);
8021 1.281 msaitoh return 0;
8022 1.281 msaitoh }
8023 1.323 msaitoh } else if (sc->sc_flags & WM_F_LOCK_EXTCNF) {
8024 1.281 msaitoh if (wm_get_swfwhw_semaphore(sc)) {
8025 1.281 msaitoh aprint_error_dev(sc->sc_dev,
8026 1.281 msaitoh "%s: failed to get semaphore\n", __func__);
8027 1.281 msaitoh return 0;
8028 1.281 msaitoh }
8029 1.1 thorpej }
8030 1.1 thorpej
8031 1.281 msaitoh CSR_WRITE(sc, WMREG_KUMCTRLSTA,
8032 1.281 msaitoh ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
8033 1.281 msaitoh KUMCTRLSTA_REN);
8034 1.266 msaitoh CSR_WRITE_FLUSH(sc);
8035 1.281 msaitoh delay(2);
8036 1.1 thorpej
8037 1.281 msaitoh rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
8038 1.1 thorpej
8039 1.323 msaitoh if (sc->sc_flags & WM_F_LOCK_SWFW)
8040 1.281 msaitoh wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
8041 1.323 msaitoh else if (sc->sc_flags & WM_F_LOCK_EXTCNF)
8042 1.281 msaitoh wm_put_swfwhw_semaphore(sc);
8043 1.1 thorpej
8044 1.281 msaitoh return rv;
8045 1.1 thorpej }
8046 1.1 thorpej
8047 1.1 thorpej /*
8048 1.281 msaitoh * wm_kmrn_writereg:
8049 1.1 thorpej *
8050 1.281 msaitoh * Write a kumeran register
8051 1.1 thorpej */
8052 1.281 msaitoh static void
8053 1.281 msaitoh wm_kmrn_writereg(struct wm_softc *sc, int reg, int val)
8054 1.1 thorpej {
8055 1.1 thorpej
8056 1.323 msaitoh if (sc->sc_flags & WM_F_LOCK_SWFW) {
8057 1.281 msaitoh if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) {
8058 1.281 msaitoh aprint_error_dev(sc->sc_dev,
8059 1.281 msaitoh "%s: failed to get semaphore\n", __func__);
8060 1.281 msaitoh return;
8061 1.281 msaitoh }
8062 1.323 msaitoh } else if (sc->sc_flags & WM_F_LOCK_EXTCNF) {
8063 1.281 msaitoh if (wm_get_swfwhw_semaphore(sc)) {
8064 1.281 msaitoh aprint_error_dev(sc->sc_dev,
8065 1.281 msaitoh "%s: failed to get semaphore\n", __func__);
8066 1.281 msaitoh return;
8067 1.281 msaitoh }
8068 1.281 msaitoh }
8069 1.1 thorpej
8070 1.281 msaitoh CSR_WRITE(sc, WMREG_KUMCTRLSTA,
8071 1.281 msaitoh ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
8072 1.281 msaitoh (val & KUMCTRLSTA_MASK));
8073 1.1 thorpej
8074 1.323 msaitoh if (sc->sc_flags & WM_F_LOCK_SWFW)
8075 1.281 msaitoh wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
8076 1.323 msaitoh else if (sc->sc_flags & WM_F_LOCK_EXTCNF)
8077 1.281 msaitoh wm_put_swfwhw_semaphore(sc);
8078 1.1 thorpej }
8079 1.1 thorpej
8080 1.281 msaitoh /* SGMII related */
8081 1.281 msaitoh
8082 1.1 thorpej /*
8083 1.281 msaitoh * wm_sgmii_uses_mdio
8084 1.1 thorpej *
8085 1.281 msaitoh * Check whether the transaction is to the internal PHY or the external
8086 1.281 msaitoh * MDIO interface. Return true if it's MDIO.
8087 1.281 msaitoh */
8088 1.281 msaitoh static bool
8089 1.281 msaitoh wm_sgmii_uses_mdio(struct wm_softc *sc)
8090 1.281 msaitoh {
8091 1.281 msaitoh uint32_t reg;
8092 1.281 msaitoh bool ismdio = false;
8093 1.281 msaitoh
8094 1.281 msaitoh switch (sc->sc_type) {
8095 1.281 msaitoh case WM_T_82575:
8096 1.281 msaitoh case WM_T_82576:
8097 1.281 msaitoh reg = CSR_READ(sc, WMREG_MDIC);
8098 1.281 msaitoh ismdio = ((reg & MDIC_DEST) != 0);
8099 1.281 msaitoh break;
8100 1.281 msaitoh case WM_T_82580:
8101 1.281 msaitoh case WM_T_I350:
8102 1.281 msaitoh case WM_T_I354:
8103 1.281 msaitoh case WM_T_I210:
8104 1.281 msaitoh case WM_T_I211:
8105 1.281 msaitoh reg = CSR_READ(sc, WMREG_MDICNFG);
8106 1.281 msaitoh ismdio = ((reg & MDICNFG_DEST) != 0);
8107 1.281 msaitoh break;
8108 1.281 msaitoh default:
8109 1.281 msaitoh break;
8110 1.281 msaitoh }
8111 1.1 thorpej
8112 1.281 msaitoh return ismdio;
8113 1.1 thorpej }
8114 1.1 thorpej
8115 1.1 thorpej /*
8116 1.281 msaitoh * wm_sgmii_readreg: [mii interface function]
8117 1.1 thorpej *
8118 1.281 msaitoh * Read a PHY register on the SGMII
8119 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
8120 1.281 msaitoh * ressource ...
8121 1.1 thorpej */
8122 1.47 thorpej static int
8123 1.281 msaitoh wm_sgmii_readreg(device_t self, int phy, int reg)
8124 1.1 thorpej {
8125 1.157 dyoung struct wm_softc *sc = device_private(self);
8126 1.281 msaitoh uint32_t i2ccmd;
8127 1.1 thorpej int i, rv;
8128 1.1 thorpej
8129 1.281 msaitoh if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) {
8130 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
8131 1.281 msaitoh __func__);
8132 1.281 msaitoh return 0;
8133 1.281 msaitoh }
8134 1.281 msaitoh
8135 1.281 msaitoh i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
8136 1.281 msaitoh | (phy << I2CCMD_PHY_ADDR_SHIFT)
8137 1.281 msaitoh | I2CCMD_OPCODE_READ;
8138 1.281 msaitoh CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
8139 1.1 thorpej
8140 1.281 msaitoh /* Poll the ready bit */
8141 1.281 msaitoh for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
8142 1.281 msaitoh delay(50);
8143 1.281 msaitoh i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
8144 1.281 msaitoh if (i2ccmd & I2CCMD_READY)
8145 1.1 thorpej break;
8146 1.1 thorpej }
8147 1.281 msaitoh if ((i2ccmd & I2CCMD_READY) == 0)
8148 1.281 msaitoh aprint_error_dev(sc->sc_dev, "I2CCMD Read did not complete\n");
8149 1.281 msaitoh if ((i2ccmd & I2CCMD_ERROR) != 0)
8150 1.281 msaitoh aprint_error_dev(sc->sc_dev, "I2CCMD Error bit set\n");
8151 1.1 thorpej
8152 1.281 msaitoh rv = ((i2ccmd >> 8) & 0x00ff) | ((i2ccmd << 8) & 0xff00);
8153 1.1 thorpej
8154 1.281 msaitoh wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
8155 1.194 msaitoh return rv;
8156 1.1 thorpej }
8157 1.1 thorpej
8158 1.1 thorpej /*
8159 1.281 msaitoh * wm_sgmii_writereg: [mii interface function]
8160 1.1 thorpej *
8161 1.281 msaitoh * Write a PHY register on the SGMII.
8162 1.281 msaitoh * This could be handled by the PHY layer if we didn't have to lock the
8163 1.281 msaitoh * ressource ...
8164 1.1 thorpej */
8165 1.47 thorpej static void
8166 1.281 msaitoh wm_sgmii_writereg(device_t self, int phy, int reg, int val)
8167 1.1 thorpej {
8168 1.157 dyoung struct wm_softc *sc = device_private(self);
8169 1.281 msaitoh uint32_t i2ccmd;
8170 1.1 thorpej int i;
8171 1.314 msaitoh int val_swapped;
8172 1.1 thorpej
8173 1.281 msaitoh if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) {
8174 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
8175 1.281 msaitoh __func__);
8176 1.281 msaitoh return;
8177 1.281 msaitoh }
8178 1.314 msaitoh /* Swap the data bytes for the I2C interface */
8179 1.314 msaitoh val_swapped = ((val >> 8) & 0x00FF) | ((val << 8) & 0xFF00);
8180 1.281 msaitoh i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
8181 1.281 msaitoh | (phy << I2CCMD_PHY_ADDR_SHIFT)
8182 1.314 msaitoh | I2CCMD_OPCODE_WRITE | val_swapped;
8183 1.281 msaitoh CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
8184 1.1 thorpej
8185 1.281 msaitoh /* Poll the ready bit */
8186 1.281 msaitoh for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
8187 1.281 msaitoh delay(50);
8188 1.281 msaitoh i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
8189 1.281 msaitoh if (i2ccmd & I2CCMD_READY)
8190 1.1 thorpej break;
8191 1.1 thorpej }
8192 1.281 msaitoh if ((i2ccmd & I2CCMD_READY) == 0)
8193 1.281 msaitoh aprint_error_dev(sc->sc_dev, "I2CCMD Write did not complete\n");
8194 1.281 msaitoh if ((i2ccmd & I2CCMD_ERROR) != 0)
8195 1.281 msaitoh aprint_error_dev(sc->sc_dev, "I2CCMD Error bit set\n");
8196 1.1 thorpej
8197 1.281 msaitoh wm_put_swfw_semaphore(sc, SWFW_PHY0_SM);
8198 1.1 thorpej }
8199 1.1 thorpej
8200 1.281 msaitoh /* TBI related */
8201 1.281 msaitoh
8202 1.127 bouyer /*
8203 1.281 msaitoh * wm_tbi_mediainit:
8204 1.127 bouyer *
8205 1.281 msaitoh * Initialize media for use on 1000BASE-X devices.
8206 1.127 bouyer */
8207 1.127 bouyer static void
8208 1.281 msaitoh wm_tbi_mediainit(struct wm_softc *sc)
8209 1.127 bouyer {
8210 1.281 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
8211 1.281 msaitoh const char *sep = "";
8212 1.281 msaitoh
8213 1.281 msaitoh if (sc->sc_type < WM_T_82543)
8214 1.281 msaitoh sc->sc_tipg = TIPG_WM_DFLT;
8215 1.281 msaitoh else
8216 1.281 msaitoh sc->sc_tipg = TIPG_LG_DFLT;
8217 1.281 msaitoh
8218 1.325 msaitoh sc->sc_tbi_serdes_anegticks = 5;
8219 1.281 msaitoh
8220 1.281 msaitoh /* Initialize our media structures */
8221 1.281 msaitoh sc->sc_mii.mii_ifp = ifp;
8222 1.325 msaitoh sc->sc_ethercom.ec_mii = &sc->sc_mii;
8223 1.281 msaitoh
8224 1.325 msaitoh if ((sc->sc_type >= WM_T_82575)
8225 1.325 msaitoh && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
8226 1.327 msaitoh ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
8227 1.325 msaitoh wm_serdes_mediachange, wm_serdes_mediastatus);
8228 1.325 msaitoh else
8229 1.327 msaitoh ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
8230 1.325 msaitoh wm_tbi_mediachange, wm_tbi_mediastatus);
8231 1.281 msaitoh
8232 1.281 msaitoh /*
8233 1.281 msaitoh * SWD Pins:
8234 1.281 msaitoh *
8235 1.281 msaitoh * 0 = Link LED (output)
8236 1.281 msaitoh * 1 = Loss Of Signal (input)
8237 1.281 msaitoh */
8238 1.281 msaitoh sc->sc_ctrl |= CTRL_SWDPIO(0);
8239 1.325 msaitoh
8240 1.325 msaitoh /* XXX Perhaps this is only for TBI */
8241 1.325 msaitoh if (sc->sc_mediatype != WM_MEDIATYPE_SERDES)
8242 1.325 msaitoh sc->sc_ctrl &= ~CTRL_SWDPIO(1);
8243 1.325 msaitoh
8244 1.311 msaitoh if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
8245 1.281 msaitoh sc->sc_ctrl &= ~CTRL_LRST;
8246 1.281 msaitoh
8247 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
8248 1.127 bouyer
8249 1.281 msaitoh #define ADD(ss, mm, dd) \
8250 1.281 msaitoh do { \
8251 1.281 msaitoh aprint_normal("%s%s", sep, ss); \
8252 1.281 msaitoh ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \
8253 1.281 msaitoh sep = ", "; \
8254 1.281 msaitoh } while (/*CONSTCOND*/0)
8255 1.127 bouyer
8256 1.281 msaitoh aprint_normal_dev(sc->sc_dev, "");
8257 1.285 msaitoh
8258 1.285 msaitoh /* Only 82545 is LX */
8259 1.285 msaitoh if (sc->sc_type == WM_T_82545) {
8260 1.285 msaitoh ADD("1000baseLX", IFM_1000_LX, ANAR_X_HD);
8261 1.285 msaitoh ADD("1000baseLX-FDX", IFM_1000_LX|IFM_FDX, ANAR_X_FD);
8262 1.285 msaitoh } else {
8263 1.285 msaitoh ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
8264 1.285 msaitoh ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD);
8265 1.285 msaitoh }
8266 1.281 msaitoh ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD);
8267 1.281 msaitoh aprint_normal("\n");
8268 1.127 bouyer
8269 1.281 msaitoh #undef ADD
8270 1.127 bouyer
8271 1.281 msaitoh ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
8272 1.127 bouyer }
8273 1.127 bouyer
8274 1.127 bouyer /*
8275 1.281 msaitoh * wm_tbi_mediachange: [ifmedia interface function]
8276 1.167 msaitoh *
8277 1.281 msaitoh * Set hardware to newly-selected media on a 1000BASE-X device.
8278 1.167 msaitoh */
8279 1.281 msaitoh static int
8280 1.281 msaitoh wm_tbi_mediachange(struct ifnet *ifp)
8281 1.167 msaitoh {
8282 1.281 msaitoh struct wm_softc *sc = ifp->if_softc;
8283 1.281 msaitoh struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
8284 1.281 msaitoh uint32_t status;
8285 1.281 msaitoh int i;
8286 1.167 msaitoh
8287 1.325 msaitoh if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {
8288 1.325 msaitoh /* XXX need some work for >= 82571 and < 82575 */
8289 1.325 msaitoh if (sc->sc_type < WM_T_82575)
8290 1.325 msaitoh return 0;
8291 1.325 msaitoh }
8292 1.167 msaitoh
8293 1.285 msaitoh if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)
8294 1.285 msaitoh || (sc->sc_type >= WM_T_82575))
8295 1.285 msaitoh CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK);
8296 1.285 msaitoh
8297 1.285 msaitoh sc->sc_ctrl &= ~CTRL_LRST;
8298 1.285 msaitoh sc->sc_txcw = TXCW_ANE;
8299 1.285 msaitoh if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
8300 1.285 msaitoh sc->sc_txcw |= TXCW_FD | TXCW_HD;
8301 1.285 msaitoh else if (ife->ifm_media & IFM_FDX)
8302 1.285 msaitoh sc->sc_txcw |= TXCW_FD;
8303 1.285 msaitoh else
8304 1.285 msaitoh sc->sc_txcw |= TXCW_HD;
8305 1.285 msaitoh
8306 1.327 msaitoh if ((sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
8307 1.281 msaitoh sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE;
8308 1.167 msaitoh
8309 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n",
8310 1.285 msaitoh device_xname(sc->sc_dev), sc->sc_txcw));
8311 1.281 msaitoh CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
8312 1.285 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
8313 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8314 1.285 msaitoh delay(1000);
8315 1.167 msaitoh
8316 1.281 msaitoh i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1);
8317 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i));
8318 1.192 msaitoh
8319 1.281 msaitoh /*
8320 1.281 msaitoh * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the
8321 1.281 msaitoh * optics detect a signal, 0 if they don't.
8322 1.281 msaitoh */
8323 1.281 msaitoh if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) {
8324 1.281 msaitoh /* Have signal; wait for the link to come up. */
8325 1.281 msaitoh for (i = 0; i < WM_LINKUP_TIMEOUT; i++) {
8326 1.281 msaitoh delay(10000);
8327 1.281 msaitoh if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
8328 1.281 msaitoh break;
8329 1.281 msaitoh }
8330 1.192 msaitoh
8331 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n",
8332 1.281 msaitoh device_xname(sc->sc_dev),i));
8333 1.192 msaitoh
8334 1.281 msaitoh status = CSR_READ(sc, WMREG_STATUS);
8335 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
8336 1.281 msaitoh ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n",
8337 1.281 msaitoh device_xname(sc->sc_dev),status, STATUS_LU));
8338 1.281 msaitoh if (status & STATUS_LU) {
8339 1.281 msaitoh /* Link is up. */
8340 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
8341 1.281 msaitoh ("%s: LINK: set media -> link up %s\n",
8342 1.281 msaitoh device_xname(sc->sc_dev),
8343 1.281 msaitoh (status & STATUS_FD) ? "FDX" : "HDX"));
8344 1.192 msaitoh
8345 1.281 msaitoh /*
8346 1.281 msaitoh * NOTE: CTRL will update TFCE and RFCE automatically,
8347 1.281 msaitoh * so we should update sc->sc_ctrl
8348 1.281 msaitoh */
8349 1.281 msaitoh sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
8350 1.281 msaitoh sc->sc_tctl &= ~TCTL_COLD(0x3ff);
8351 1.281 msaitoh sc->sc_fcrtl &= ~FCRTL_XONE;
8352 1.281 msaitoh if (status & STATUS_FD)
8353 1.281 msaitoh sc->sc_tctl |=
8354 1.281 msaitoh TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
8355 1.281 msaitoh else
8356 1.281 msaitoh sc->sc_tctl |=
8357 1.281 msaitoh TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
8358 1.281 msaitoh if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
8359 1.281 msaitoh sc->sc_fcrtl |= FCRTL_XONE;
8360 1.281 msaitoh CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
8361 1.281 msaitoh CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
8362 1.281 msaitoh WMREG_OLD_FCRTL : WMREG_FCRTL,
8363 1.281 msaitoh sc->sc_fcrtl);
8364 1.281 msaitoh sc->sc_tbi_linkup = 1;
8365 1.281 msaitoh } else {
8366 1.281 msaitoh if (i == WM_LINKUP_TIMEOUT)
8367 1.281 msaitoh wm_check_for_link(sc);
8368 1.281 msaitoh /* Link is down. */
8369 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
8370 1.281 msaitoh ("%s: LINK: set media -> link down\n",
8371 1.281 msaitoh device_xname(sc->sc_dev)));
8372 1.281 msaitoh sc->sc_tbi_linkup = 0;
8373 1.281 msaitoh }
8374 1.281 msaitoh } else {
8375 1.281 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
8376 1.281 msaitoh device_xname(sc->sc_dev)));
8377 1.281 msaitoh sc->sc_tbi_linkup = 0;
8378 1.281 msaitoh }
8379 1.198 msaitoh
8380 1.325 msaitoh wm_tbi_serdes_set_linkled(sc);
8381 1.192 msaitoh
8382 1.281 msaitoh return 0;
8383 1.192 msaitoh }
8384 1.192 msaitoh
8385 1.167 msaitoh /*
8386 1.324 msaitoh * wm_tbi_mediastatus: [ifmedia interface function]
8387 1.324 msaitoh *
8388 1.324 msaitoh * Get the current interface media status on a 1000BASE-X device.
8389 1.324 msaitoh */
8390 1.324 msaitoh static void
8391 1.324 msaitoh wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
8392 1.324 msaitoh {
8393 1.324 msaitoh struct wm_softc *sc = ifp->if_softc;
8394 1.324 msaitoh uint32_t ctrl, status;
8395 1.324 msaitoh
8396 1.324 msaitoh ifmr->ifm_status = IFM_AVALID;
8397 1.324 msaitoh ifmr->ifm_active = IFM_ETHER;
8398 1.324 msaitoh
8399 1.324 msaitoh status = CSR_READ(sc, WMREG_STATUS);
8400 1.324 msaitoh if ((status & STATUS_LU) == 0) {
8401 1.324 msaitoh ifmr->ifm_active |= IFM_NONE;
8402 1.324 msaitoh return;
8403 1.324 msaitoh }
8404 1.324 msaitoh
8405 1.324 msaitoh ifmr->ifm_status |= IFM_ACTIVE;
8406 1.324 msaitoh /* Only 82545 is LX */
8407 1.324 msaitoh if (sc->sc_type == WM_T_82545)
8408 1.324 msaitoh ifmr->ifm_active |= IFM_1000_LX;
8409 1.324 msaitoh else
8410 1.324 msaitoh ifmr->ifm_active |= IFM_1000_SX;
8411 1.324 msaitoh if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
8412 1.324 msaitoh ifmr->ifm_active |= IFM_FDX;
8413 1.324 msaitoh else
8414 1.324 msaitoh ifmr->ifm_active |= IFM_HDX;
8415 1.324 msaitoh ctrl = CSR_READ(sc, WMREG_CTRL);
8416 1.324 msaitoh if (ctrl & CTRL_RFCE)
8417 1.324 msaitoh ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE;
8418 1.324 msaitoh if (ctrl & CTRL_TFCE)
8419 1.324 msaitoh ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE;
8420 1.324 msaitoh }
8421 1.324 msaitoh
8422 1.325 msaitoh /* XXX TBI only */
8423 1.324 msaitoh static int
8424 1.324 msaitoh wm_check_for_link(struct wm_softc *sc)
8425 1.324 msaitoh {
8426 1.324 msaitoh struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
8427 1.324 msaitoh uint32_t rxcw;
8428 1.324 msaitoh uint32_t ctrl;
8429 1.324 msaitoh uint32_t status;
8430 1.324 msaitoh uint32_t sig;
8431 1.324 msaitoh
8432 1.324 msaitoh if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {
8433 1.325 msaitoh /* XXX need some work for >= 82571 */
8434 1.325 msaitoh if (sc->sc_type >= WM_T_82571) {
8435 1.325 msaitoh sc->sc_tbi_linkup = 1;
8436 1.325 msaitoh return 0;
8437 1.325 msaitoh }
8438 1.324 msaitoh }
8439 1.324 msaitoh
8440 1.324 msaitoh rxcw = CSR_READ(sc, WMREG_RXCW);
8441 1.324 msaitoh ctrl = CSR_READ(sc, WMREG_CTRL);
8442 1.324 msaitoh status = CSR_READ(sc, WMREG_STATUS);
8443 1.324 msaitoh
8444 1.324 msaitoh sig = (sc->sc_type > WM_T_82544) ? CTRL_SWDPIN(1) : 0;
8445 1.324 msaitoh
8446 1.324 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: %s: sig = %d, status_lu = %d, rxcw_c = %d\n",
8447 1.324 msaitoh device_xname(sc->sc_dev), __func__,
8448 1.324 msaitoh ((ctrl & CTRL_SWDPIN(1)) == sig),
8449 1.324 msaitoh ((status & STATUS_LU) != 0),
8450 1.324 msaitoh ((rxcw & RXCW_C) != 0)
8451 1.324 msaitoh ));
8452 1.324 msaitoh
8453 1.324 msaitoh /*
8454 1.324 msaitoh * SWDPIN LU RXCW
8455 1.324 msaitoh * 0 0 0
8456 1.324 msaitoh * 0 0 1 (should not happen)
8457 1.324 msaitoh * 0 1 0 (should not happen)
8458 1.324 msaitoh * 0 1 1 (should not happen)
8459 1.324 msaitoh * 1 0 0 Disable autonego and force linkup
8460 1.324 msaitoh * 1 0 1 got /C/ but not linkup yet
8461 1.324 msaitoh * 1 1 0 (linkup)
8462 1.324 msaitoh * 1 1 1 If IFM_AUTO, back to autonego
8463 1.324 msaitoh *
8464 1.324 msaitoh */
8465 1.324 msaitoh if (((ctrl & CTRL_SWDPIN(1)) == sig)
8466 1.324 msaitoh && ((status & STATUS_LU) == 0)
8467 1.324 msaitoh && ((rxcw & RXCW_C) == 0)) {
8468 1.324 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: force linkup and fullduplex\n",
8469 1.324 msaitoh __func__));
8470 1.324 msaitoh sc->sc_tbi_linkup = 0;
8471 1.324 msaitoh /* Disable auto-negotiation in the TXCW register */
8472 1.324 msaitoh CSR_WRITE(sc, WMREG_TXCW, (sc->sc_txcw & ~TXCW_ANE));
8473 1.324 msaitoh
8474 1.324 msaitoh /*
8475 1.324 msaitoh * Force link-up and also force full-duplex.
8476 1.324 msaitoh *
8477 1.324 msaitoh * NOTE: CTRL was updated TFCE and RFCE automatically,
8478 1.324 msaitoh * so we should update sc->sc_ctrl
8479 1.324 msaitoh */
8480 1.324 msaitoh sc->sc_ctrl = ctrl | CTRL_SLU | CTRL_FD;
8481 1.324 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
8482 1.324 msaitoh } else if (((status & STATUS_LU) != 0)
8483 1.324 msaitoh && ((rxcw & RXCW_C) != 0)
8484 1.324 msaitoh && (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)) {
8485 1.324 msaitoh sc->sc_tbi_linkup = 1;
8486 1.324 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: go back to autonego\n",
8487 1.324 msaitoh __func__));
8488 1.324 msaitoh CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
8489 1.324 msaitoh CSR_WRITE(sc, WMREG_CTRL, (ctrl & ~CTRL_SLU));
8490 1.324 msaitoh } else if (((ctrl & CTRL_SWDPIN(1)) == sig)
8491 1.324 msaitoh && ((rxcw & RXCW_C) != 0)) {
8492 1.324 msaitoh DPRINTF(WM_DEBUG_LINK, ("/C/"));
8493 1.324 msaitoh } else {
8494 1.324 msaitoh DPRINTF(WM_DEBUG_LINK, ("%s: %x,%x,%x\n", __func__, rxcw, ctrl,
8495 1.324 msaitoh status));
8496 1.324 msaitoh }
8497 1.324 msaitoh
8498 1.324 msaitoh return 0;
8499 1.324 msaitoh }
8500 1.324 msaitoh
8501 1.324 msaitoh /*
8502 1.325 msaitoh * wm_tbi_tick:
8503 1.191 msaitoh *
8504 1.325 msaitoh * Check the link on TBI devices.
8505 1.325 msaitoh * This function acts as mii_tick().
8506 1.191 msaitoh */
8507 1.281 msaitoh static void
8508 1.325 msaitoh wm_tbi_tick(struct wm_softc *sc)
8509 1.191 msaitoh {
8510 1.325 msaitoh struct mii_data *mii = &sc->sc_mii;
8511 1.325 msaitoh struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
8512 1.281 msaitoh uint32_t status;
8513 1.281 msaitoh
8514 1.283 ozaki KASSERT(WM_TX_LOCKED(sc));
8515 1.191 msaitoh
8516 1.281 msaitoh status = CSR_READ(sc, WMREG_STATUS);
8517 1.192 msaitoh
8518 1.281 msaitoh /* XXX is this needed? */
8519 1.281 msaitoh (void)CSR_READ(sc, WMREG_RXCW);
8520 1.281 msaitoh (void)CSR_READ(sc, WMREG_CTRL);
8521 1.192 msaitoh
8522 1.281 msaitoh /* set link status */
8523 1.281 msaitoh if ((status & STATUS_LU) == 0) {
8524 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
8525 1.281 msaitoh ("%s: LINK: checklink -> down\n",
8526 1.281 msaitoh device_xname(sc->sc_dev)));
8527 1.281 msaitoh sc->sc_tbi_linkup = 0;
8528 1.281 msaitoh } else if (sc->sc_tbi_linkup == 0) {
8529 1.281 msaitoh DPRINTF(WM_DEBUG_LINK,
8530 1.281 msaitoh ("%s: LINK: checklink -> up %s\n",
8531 1.281 msaitoh device_xname(sc->sc_dev),
8532 1.281 msaitoh (status & STATUS_FD) ? "FDX" : "HDX"));
8533 1.281 msaitoh sc->sc_tbi_linkup = 1;
8534 1.325 msaitoh sc->sc_tbi_serdes_ticks = 0;
8535 1.325 msaitoh }
8536 1.325 msaitoh
8537 1.325 msaitoh if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) == 0)
8538 1.325 msaitoh goto setled;
8539 1.325 msaitoh
8540 1.325 msaitoh if ((status & STATUS_LU) == 0) {
8541 1.325 msaitoh sc->sc_tbi_linkup = 0;
8542 1.325 msaitoh /* If the timer expired, retry autonegotiation */
8543 1.325 msaitoh if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
8544 1.325 msaitoh && (++sc->sc_tbi_serdes_ticks
8545 1.325 msaitoh >= sc->sc_tbi_serdes_anegticks)) {
8546 1.325 msaitoh DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
8547 1.325 msaitoh sc->sc_tbi_serdes_ticks = 0;
8548 1.325 msaitoh /*
8549 1.325 msaitoh * Reset the link, and let autonegotiation do
8550 1.325 msaitoh * its thing
8551 1.325 msaitoh */
8552 1.325 msaitoh sc->sc_ctrl |= CTRL_LRST;
8553 1.325 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
8554 1.325 msaitoh CSR_WRITE_FLUSH(sc);
8555 1.325 msaitoh delay(1000);
8556 1.325 msaitoh sc->sc_ctrl &= ~CTRL_LRST;
8557 1.325 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
8558 1.325 msaitoh CSR_WRITE_FLUSH(sc);
8559 1.325 msaitoh delay(1000);
8560 1.325 msaitoh CSR_WRITE(sc, WMREG_TXCW,
8561 1.325 msaitoh sc->sc_txcw & ~TXCW_ANE);
8562 1.325 msaitoh CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
8563 1.325 msaitoh }
8564 1.192 msaitoh }
8565 1.192 msaitoh
8566 1.325 msaitoh setled:
8567 1.325 msaitoh wm_tbi_serdes_set_linkled(sc);
8568 1.325 msaitoh }
8569 1.325 msaitoh
8570 1.325 msaitoh /* SERDES related */
8571 1.325 msaitoh static void
8572 1.325 msaitoh wm_serdes_power_up_link_82575(struct wm_softc *sc)
8573 1.325 msaitoh {
8574 1.325 msaitoh uint32_t reg;
8575 1.325 msaitoh
8576 1.325 msaitoh if ((sc->sc_mediatype != WM_MEDIATYPE_SERDES)
8577 1.325 msaitoh && ((sc->sc_flags & WM_F_SGMII) == 0))
8578 1.325 msaitoh return;
8579 1.325 msaitoh
8580 1.325 msaitoh reg = CSR_READ(sc, WMREG_PCS_CFG);
8581 1.325 msaitoh reg |= PCS_CFG_PCS_EN;
8582 1.325 msaitoh CSR_WRITE(sc, WMREG_PCS_CFG, reg);
8583 1.325 msaitoh
8584 1.325 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
8585 1.325 msaitoh reg &= ~CTRL_EXT_SWDPIN(3);
8586 1.325 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
8587 1.325 msaitoh CSR_WRITE_FLUSH(sc);
8588 1.325 msaitoh }
8589 1.325 msaitoh
8590 1.325 msaitoh static int
8591 1.325 msaitoh wm_serdes_mediachange(struct ifnet *ifp)
8592 1.325 msaitoh {
8593 1.325 msaitoh struct wm_softc *sc = ifp->if_softc;
8594 1.325 msaitoh bool pcs_autoneg = true; /* XXX */
8595 1.325 msaitoh uint32_t ctrl_ext, pcs_lctl, reg;
8596 1.325 msaitoh
8597 1.325 msaitoh /* XXX Currently, this function is not called on 8257[12] */
8598 1.325 msaitoh if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)
8599 1.325 msaitoh || (sc->sc_type >= WM_T_82575))
8600 1.325 msaitoh CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK);
8601 1.325 msaitoh
8602 1.325 msaitoh wm_serdes_power_up_link_82575(sc);
8603 1.325 msaitoh
8604 1.325 msaitoh sc->sc_ctrl |= CTRL_SLU;
8605 1.325 msaitoh
8606 1.325 msaitoh if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576))
8607 1.325 msaitoh sc->sc_ctrl |= CTRL_SWDPIN(0) | CTRL_SWDPIN(1);
8608 1.325 msaitoh
8609 1.325 msaitoh ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
8610 1.325 msaitoh pcs_lctl = CSR_READ(sc, WMREG_PCS_LCTL);
8611 1.325 msaitoh switch (ctrl_ext & CTRL_EXT_LINK_MODE_MASK) {
8612 1.325 msaitoh case CTRL_EXT_LINK_MODE_SGMII:
8613 1.325 msaitoh pcs_autoneg = true;
8614 1.325 msaitoh pcs_lctl &= ~PCS_LCTL_AN_TIMEOUT;
8615 1.325 msaitoh break;
8616 1.325 msaitoh case CTRL_EXT_LINK_MODE_1000KX:
8617 1.325 msaitoh pcs_autoneg = false;
8618 1.325 msaitoh /* FALLTHROUGH */
8619 1.325 msaitoh default:
8620 1.325 msaitoh if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)){
8621 1.325 msaitoh if ((sc->sc_flags & WM_F_PCS_DIS_AUTONEGO) != 0)
8622 1.325 msaitoh pcs_autoneg = false;
8623 1.325 msaitoh }
8624 1.325 msaitoh sc->sc_ctrl |= CTRL_SPEED_1000 | CTRL_FRCSPD | CTRL_FD
8625 1.325 msaitoh | CTRL_FRCFDX;
8626 1.325 msaitoh pcs_lctl |= PCS_LCTL_FSV_1000 | PCS_LCTL_FDV_FULL;
8627 1.325 msaitoh }
8628 1.325 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
8629 1.325 msaitoh
8630 1.325 msaitoh if (pcs_autoneg) {
8631 1.325 msaitoh pcs_lctl |= PCS_LCTL_AN_ENABLE | PCS_LCTL_AN_RESTART;
8632 1.325 msaitoh pcs_lctl &= ~PCS_LCTL_FORCE_FC;
8633 1.325 msaitoh
8634 1.325 msaitoh reg = CSR_READ(sc, WMREG_PCS_ANADV);
8635 1.325 msaitoh reg &= ~(TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE);
8636 1.327 msaitoh reg |= TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE;
8637 1.325 msaitoh CSR_WRITE(sc, WMREG_PCS_ANADV, reg);
8638 1.325 msaitoh } else
8639 1.325 msaitoh pcs_lctl |= PCS_LCTL_FSD | PCS_LCTL_FORCE_FC;
8640 1.325 msaitoh
8641 1.325 msaitoh CSR_WRITE(sc, WMREG_PCS_LCTL, pcs_lctl);
8642 1.325 msaitoh
8643 1.325 msaitoh
8644 1.325 msaitoh return 0;
8645 1.325 msaitoh }
8646 1.325 msaitoh
8647 1.325 msaitoh static void
8648 1.325 msaitoh wm_serdes_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
8649 1.325 msaitoh {
8650 1.325 msaitoh struct wm_softc *sc = ifp->if_softc;
8651 1.325 msaitoh struct mii_data *mii = &sc->sc_mii;
8652 1.325 msaitoh struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
8653 1.325 msaitoh uint32_t pcs_adv, pcs_lpab, reg;
8654 1.325 msaitoh
8655 1.325 msaitoh ifmr->ifm_status = IFM_AVALID;
8656 1.325 msaitoh ifmr->ifm_active = IFM_ETHER;
8657 1.325 msaitoh
8658 1.325 msaitoh /* Check PCS */
8659 1.325 msaitoh reg = CSR_READ(sc, WMREG_PCS_LSTS);
8660 1.325 msaitoh if ((reg & PCS_LSTS_LINKOK) == 0) {
8661 1.325 msaitoh ifmr->ifm_active |= IFM_NONE;
8662 1.325 msaitoh sc->sc_tbi_linkup = 0;
8663 1.325 msaitoh goto setled;
8664 1.325 msaitoh }
8665 1.325 msaitoh
8666 1.325 msaitoh sc->sc_tbi_linkup = 1;
8667 1.325 msaitoh ifmr->ifm_status |= IFM_ACTIVE;
8668 1.325 msaitoh ifmr->ifm_active |= IFM_1000_SX; /* XXX */
8669 1.325 msaitoh if ((reg & PCS_LSTS_FDX) != 0)
8670 1.325 msaitoh ifmr->ifm_active |= IFM_FDX;
8671 1.325 msaitoh else
8672 1.325 msaitoh ifmr->ifm_active |= IFM_HDX;
8673 1.325 msaitoh mii->mii_media_active &= ~IFM_ETH_FMASK;
8674 1.325 msaitoh if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
8675 1.325 msaitoh /* Check flow */
8676 1.325 msaitoh reg = CSR_READ(sc, WMREG_PCS_LSTS);
8677 1.325 msaitoh if ((reg & PCS_LSTS_AN_COMP) == 0) {
8678 1.325 msaitoh printf("XXX LINKOK but not ACOMP\n");
8679 1.325 msaitoh goto setled;
8680 1.325 msaitoh }
8681 1.325 msaitoh pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
8682 1.325 msaitoh pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
8683 1.325 msaitoh printf("XXX AN result(2) %08x, %08x\n", pcs_adv, pcs_lpab);
8684 1.325 msaitoh if ((pcs_adv & TXCW_SYM_PAUSE)
8685 1.325 msaitoh && (pcs_lpab & TXCW_SYM_PAUSE)) {
8686 1.325 msaitoh mii->mii_media_active |= IFM_FLOW
8687 1.325 msaitoh | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
8688 1.325 msaitoh } else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
8689 1.325 msaitoh && (pcs_adv & TXCW_ASYM_PAUSE)
8690 1.325 msaitoh && (pcs_lpab & TXCW_SYM_PAUSE)
8691 1.325 msaitoh && (pcs_lpab & TXCW_ASYM_PAUSE)) {
8692 1.325 msaitoh mii->mii_media_active |= IFM_FLOW
8693 1.325 msaitoh | IFM_ETH_TXPAUSE;
8694 1.325 msaitoh } else if ((pcs_adv & TXCW_SYM_PAUSE)
8695 1.325 msaitoh && (pcs_adv & TXCW_ASYM_PAUSE)
8696 1.325 msaitoh && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
8697 1.325 msaitoh && (pcs_lpab & TXCW_ASYM_PAUSE)) {
8698 1.325 msaitoh mii->mii_media_active |= IFM_FLOW
8699 1.325 msaitoh | IFM_ETH_RXPAUSE;
8700 1.325 msaitoh } else {
8701 1.325 msaitoh }
8702 1.325 msaitoh }
8703 1.325 msaitoh ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
8704 1.325 msaitoh | (mii->mii_media_active & IFM_ETH_FMASK);
8705 1.325 msaitoh setled:
8706 1.325 msaitoh wm_tbi_serdes_set_linkled(sc);
8707 1.325 msaitoh }
8708 1.325 msaitoh
8709 1.325 msaitoh /*
8710 1.325 msaitoh * wm_serdes_tick:
8711 1.325 msaitoh *
8712 1.325 msaitoh * Check the link on serdes devices.
8713 1.325 msaitoh */
8714 1.325 msaitoh static void
8715 1.325 msaitoh wm_serdes_tick(struct wm_softc *sc)
8716 1.325 msaitoh {
8717 1.325 msaitoh struct ifnet *ifp = &sc->sc_ethercom.ec_if;
8718 1.325 msaitoh struct mii_data *mii = &sc->sc_mii;
8719 1.325 msaitoh struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
8720 1.325 msaitoh uint32_t reg;
8721 1.325 msaitoh
8722 1.325 msaitoh KASSERT(WM_TX_LOCKED(sc));
8723 1.325 msaitoh
8724 1.325 msaitoh mii->mii_media_status = IFM_AVALID;
8725 1.325 msaitoh mii->mii_media_active = IFM_ETHER;
8726 1.325 msaitoh
8727 1.325 msaitoh /* Check PCS */
8728 1.325 msaitoh reg = CSR_READ(sc, WMREG_PCS_LSTS);
8729 1.325 msaitoh if ((reg & PCS_LSTS_LINKOK) != 0) {
8730 1.325 msaitoh mii->mii_media_status |= IFM_ACTIVE;
8731 1.325 msaitoh sc->sc_tbi_linkup = 1;
8732 1.325 msaitoh sc->sc_tbi_serdes_ticks = 0;
8733 1.325 msaitoh mii->mii_media_active |= IFM_1000_SX; /* XXX */
8734 1.325 msaitoh if ((reg & PCS_LSTS_FDX) != 0)
8735 1.325 msaitoh mii->mii_media_active |= IFM_FDX;
8736 1.325 msaitoh else
8737 1.325 msaitoh mii->mii_media_active |= IFM_HDX;
8738 1.325 msaitoh } else {
8739 1.325 msaitoh mii->mii_media_status |= IFM_NONE;
8740 1.281 msaitoh sc->sc_tbi_linkup = 0;
8741 1.325 msaitoh /* If the timer expired, retry autonegotiation */
8742 1.325 msaitoh if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
8743 1.325 msaitoh && (++sc->sc_tbi_serdes_ticks
8744 1.325 msaitoh >= sc->sc_tbi_serdes_anegticks)) {
8745 1.325 msaitoh DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
8746 1.325 msaitoh sc->sc_tbi_serdes_ticks = 0;
8747 1.325 msaitoh /* XXX */
8748 1.325 msaitoh wm_serdes_mediachange(ifp);
8749 1.281 msaitoh }
8750 1.192 msaitoh }
8751 1.192 msaitoh
8752 1.325 msaitoh wm_tbi_serdes_set_linkled(sc);
8753 1.191 msaitoh }
8754 1.191 msaitoh
8755 1.292 msaitoh /* SFP related */
8756 1.295 msaitoh
8757 1.295 msaitoh static int
8758 1.295 msaitoh wm_sfp_read_data_byte(struct wm_softc *sc, uint16_t offset, uint8_t *data)
8759 1.295 msaitoh {
8760 1.295 msaitoh uint32_t i2ccmd;
8761 1.295 msaitoh int i;
8762 1.295 msaitoh
8763 1.295 msaitoh i2ccmd = (offset << I2CCMD_REG_ADDR_SHIFT) | I2CCMD_OPCODE_READ;
8764 1.295 msaitoh CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
8765 1.295 msaitoh
8766 1.295 msaitoh /* Poll the ready bit */
8767 1.295 msaitoh for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
8768 1.295 msaitoh delay(50);
8769 1.295 msaitoh i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
8770 1.295 msaitoh if (i2ccmd & I2CCMD_READY)
8771 1.295 msaitoh break;
8772 1.295 msaitoh }
8773 1.295 msaitoh if ((i2ccmd & I2CCMD_READY) == 0)
8774 1.295 msaitoh return -1;
8775 1.295 msaitoh if ((i2ccmd & I2CCMD_ERROR) != 0)
8776 1.295 msaitoh return -1;
8777 1.295 msaitoh
8778 1.295 msaitoh *data = i2ccmd & 0x00ff;
8779 1.295 msaitoh
8780 1.295 msaitoh return 0;
8781 1.295 msaitoh }
8782 1.295 msaitoh
8783 1.292 msaitoh static uint32_t
8784 1.295 msaitoh wm_sfp_get_media_type(struct wm_softc *sc)
8785 1.292 msaitoh {
8786 1.295 msaitoh uint32_t ctrl_ext;
8787 1.295 msaitoh uint8_t val = 0;
8788 1.295 msaitoh int timeout = 3;
8789 1.311 msaitoh uint32_t mediatype = WM_MEDIATYPE_UNKNOWN;
8790 1.295 msaitoh int rv = -1;
8791 1.292 msaitoh
8792 1.295 msaitoh ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
8793 1.295 msaitoh ctrl_ext &= ~CTRL_EXT_SWDPIN(3);
8794 1.295 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_I2C_ENA);
8795 1.295 msaitoh CSR_WRITE_FLUSH(sc);
8796 1.295 msaitoh
8797 1.295 msaitoh /* Read SFP module data */
8798 1.295 msaitoh while (timeout) {
8799 1.295 msaitoh rv = wm_sfp_read_data_byte(sc, SFF_SFP_ID_OFF, &val);
8800 1.295 msaitoh if (rv == 0)
8801 1.295 msaitoh break;
8802 1.295 msaitoh delay(100*1000); /* XXX too big */
8803 1.295 msaitoh timeout--;
8804 1.295 msaitoh }
8805 1.295 msaitoh if (rv != 0)
8806 1.295 msaitoh goto out;
8807 1.295 msaitoh switch (val) {
8808 1.295 msaitoh case SFF_SFP_ID_SFF:
8809 1.295 msaitoh aprint_normal_dev(sc->sc_dev,
8810 1.295 msaitoh "Module/Connector soldered to board\n");
8811 1.295 msaitoh break;
8812 1.295 msaitoh case SFF_SFP_ID_SFP:
8813 1.295 msaitoh aprint_normal_dev(sc->sc_dev, "SFP\n");
8814 1.295 msaitoh break;
8815 1.295 msaitoh case SFF_SFP_ID_UNKNOWN:
8816 1.295 msaitoh goto out;
8817 1.295 msaitoh default:
8818 1.295 msaitoh break;
8819 1.295 msaitoh }
8820 1.295 msaitoh
8821 1.295 msaitoh rv = wm_sfp_read_data_byte(sc, SFF_SFP_ETH_FLAGS_OFF, &val);
8822 1.295 msaitoh if (rv != 0) {
8823 1.295 msaitoh goto out;
8824 1.295 msaitoh }
8825 1.295 msaitoh
8826 1.295 msaitoh if ((val & (SFF_SFP_ETH_FLAGS_1000SX | SFF_SFP_ETH_FLAGS_1000LX)) != 0)
8827 1.311 msaitoh mediatype = WM_MEDIATYPE_SERDES;
8828 1.295 msaitoh else if ((val & SFF_SFP_ETH_FLAGS_1000T) != 0){
8829 1.295 msaitoh sc->sc_flags |= WM_F_SGMII;
8830 1.311 msaitoh mediatype = WM_MEDIATYPE_COPPER;
8831 1.295 msaitoh } else if ((val & SFF_SFP_ETH_FLAGS_100FX) != 0){
8832 1.295 msaitoh sc->sc_flags |= WM_F_SGMII;
8833 1.311 msaitoh mediatype = WM_MEDIATYPE_SERDES;
8834 1.295 msaitoh }
8835 1.295 msaitoh
8836 1.295 msaitoh out:
8837 1.295 msaitoh /* Restore I2C interface setting */
8838 1.295 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
8839 1.295 msaitoh
8840 1.295 msaitoh return mediatype;
8841 1.292 msaitoh }
8842 1.191 msaitoh /*
8843 1.281 msaitoh * NVM related.
8844 1.281 msaitoh * Microwire, SPI (w/wo EERD) and Flash.
8845 1.265 msaitoh */
8846 1.265 msaitoh
8847 1.281 msaitoh /* Both spi and uwire */
8848 1.265 msaitoh
8849 1.265 msaitoh /*
8850 1.281 msaitoh * wm_eeprom_sendbits:
8851 1.199 msaitoh *
8852 1.281 msaitoh * Send a series of bits to the EEPROM.
8853 1.199 msaitoh */
8854 1.281 msaitoh static void
8855 1.281 msaitoh wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
8856 1.199 msaitoh {
8857 1.281 msaitoh uint32_t reg;
8858 1.281 msaitoh int x;
8859 1.199 msaitoh
8860 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD);
8861 1.199 msaitoh
8862 1.281 msaitoh for (x = nbits; x > 0; x--) {
8863 1.281 msaitoh if (bits & (1U << (x - 1)))
8864 1.281 msaitoh reg |= EECD_DI;
8865 1.281 msaitoh else
8866 1.281 msaitoh reg &= ~EECD_DI;
8867 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
8868 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8869 1.281 msaitoh delay(2);
8870 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
8871 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8872 1.281 msaitoh delay(2);
8873 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
8874 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8875 1.281 msaitoh delay(2);
8876 1.199 msaitoh }
8877 1.199 msaitoh }
8878 1.199 msaitoh
8879 1.199 msaitoh /*
8880 1.281 msaitoh * wm_eeprom_recvbits:
8881 1.199 msaitoh *
8882 1.281 msaitoh * Receive a series of bits from the EEPROM.
8883 1.199 msaitoh */
8884 1.199 msaitoh static void
8885 1.281 msaitoh wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
8886 1.199 msaitoh {
8887 1.281 msaitoh uint32_t reg, val;
8888 1.281 msaitoh int x;
8889 1.199 msaitoh
8890 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
8891 1.199 msaitoh
8892 1.281 msaitoh val = 0;
8893 1.281 msaitoh for (x = nbits; x > 0; x--) {
8894 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
8895 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8896 1.281 msaitoh delay(2);
8897 1.281 msaitoh if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
8898 1.281 msaitoh val |= (1U << (x - 1));
8899 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
8900 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8901 1.281 msaitoh delay(2);
8902 1.199 msaitoh }
8903 1.281 msaitoh *valp = val;
8904 1.281 msaitoh }
8905 1.199 msaitoh
8906 1.281 msaitoh /* Microwire */
8907 1.199 msaitoh
8908 1.199 msaitoh /*
8909 1.281 msaitoh * wm_nvm_read_uwire:
8910 1.243 msaitoh *
8911 1.281 msaitoh * Read a word from the EEPROM using the MicroWire protocol.
8912 1.243 msaitoh */
8913 1.243 msaitoh static int
8914 1.281 msaitoh wm_nvm_read_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
8915 1.243 msaitoh {
8916 1.281 msaitoh uint32_t reg, val;
8917 1.281 msaitoh int i;
8918 1.281 msaitoh
8919 1.281 msaitoh for (i = 0; i < wordcnt; i++) {
8920 1.281 msaitoh /* Clear SK and DI. */
8921 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
8922 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
8923 1.281 msaitoh
8924 1.281 msaitoh /*
8925 1.281 msaitoh * XXX: workaround for a bug in qemu-0.12.x and prior
8926 1.281 msaitoh * and Xen.
8927 1.281 msaitoh *
8928 1.281 msaitoh * We use this workaround only for 82540 because qemu's
8929 1.281 msaitoh * e1000 act as 82540.
8930 1.281 msaitoh */
8931 1.281 msaitoh if (sc->sc_type == WM_T_82540) {
8932 1.281 msaitoh reg |= EECD_SK;
8933 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
8934 1.281 msaitoh reg &= ~EECD_SK;
8935 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
8936 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8937 1.281 msaitoh delay(2);
8938 1.281 msaitoh }
8939 1.281 msaitoh /* XXX: end of workaround */
8940 1.332 msaitoh
8941 1.281 msaitoh /* Set CHIP SELECT. */
8942 1.281 msaitoh reg |= EECD_CS;
8943 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
8944 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8945 1.281 msaitoh delay(2);
8946 1.281 msaitoh
8947 1.281 msaitoh /* Shift in the READ command. */
8948 1.281 msaitoh wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
8949 1.281 msaitoh
8950 1.281 msaitoh /* Shift in address. */
8951 1.294 msaitoh wm_eeprom_sendbits(sc, word + i, sc->sc_nvm_addrbits);
8952 1.281 msaitoh
8953 1.281 msaitoh /* Shift out the data. */
8954 1.281 msaitoh wm_eeprom_recvbits(sc, &val, 16);
8955 1.281 msaitoh data[i] = val & 0xffff;
8956 1.243 msaitoh
8957 1.281 msaitoh /* Clear CHIP SELECT. */
8958 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
8959 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
8960 1.281 msaitoh CSR_WRITE_FLUSH(sc);
8961 1.281 msaitoh delay(2);
8962 1.243 msaitoh }
8963 1.243 msaitoh
8964 1.281 msaitoh return 0;
8965 1.281 msaitoh }
8966 1.243 msaitoh
8967 1.281 msaitoh /* SPI */
8968 1.243 msaitoh
8969 1.294 msaitoh /*
8970 1.294 msaitoh * Set SPI and FLASH related information from the EECD register.
8971 1.294 msaitoh * For 82541 and 82547, the word size is taken from EEPROM.
8972 1.294 msaitoh */
8973 1.294 msaitoh static int
8974 1.294 msaitoh wm_nvm_set_addrbits_size_eecd(struct wm_softc *sc)
8975 1.243 msaitoh {
8976 1.294 msaitoh int size;
8977 1.281 msaitoh uint32_t reg;
8978 1.294 msaitoh uint16_t data;
8979 1.243 msaitoh
8980 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD);
8981 1.294 msaitoh sc->sc_nvm_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
8982 1.294 msaitoh
8983 1.294 msaitoh /* Read the size of NVM from EECD by default */
8984 1.294 msaitoh size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);
8985 1.294 msaitoh switch (sc->sc_type) {
8986 1.294 msaitoh case WM_T_82541:
8987 1.294 msaitoh case WM_T_82541_2:
8988 1.294 msaitoh case WM_T_82547:
8989 1.294 msaitoh case WM_T_82547_2:
8990 1.294 msaitoh /* Set dummy value to access EEPROM */
8991 1.294 msaitoh sc->sc_nvm_wordsize = 64;
8992 1.294 msaitoh wm_nvm_read(sc, NVM_OFF_EEPROM_SIZE, 1, &data);
8993 1.294 msaitoh reg = data;
8994 1.294 msaitoh size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);
8995 1.294 msaitoh if (size == 0)
8996 1.294 msaitoh size = 6; /* 64 word size */
8997 1.294 msaitoh else
8998 1.294 msaitoh size += NVM_WORD_SIZE_BASE_SHIFT + 1;
8999 1.294 msaitoh break;
9000 1.294 msaitoh case WM_T_80003:
9001 1.294 msaitoh case WM_T_82571:
9002 1.294 msaitoh case WM_T_82572:
9003 1.294 msaitoh case WM_T_82573: /* SPI case */
9004 1.294 msaitoh case WM_T_82574: /* SPI case */
9005 1.294 msaitoh case WM_T_82583: /* SPI case */
9006 1.294 msaitoh size += NVM_WORD_SIZE_BASE_SHIFT;
9007 1.294 msaitoh if (size > 14)
9008 1.294 msaitoh size = 14;
9009 1.294 msaitoh break;
9010 1.294 msaitoh case WM_T_82575:
9011 1.294 msaitoh case WM_T_82576:
9012 1.294 msaitoh case WM_T_82580:
9013 1.294 msaitoh case WM_T_I350:
9014 1.294 msaitoh case WM_T_I354:
9015 1.294 msaitoh case WM_T_I210:
9016 1.294 msaitoh case WM_T_I211:
9017 1.294 msaitoh size += NVM_WORD_SIZE_BASE_SHIFT;
9018 1.294 msaitoh if (size > 15)
9019 1.294 msaitoh size = 15;
9020 1.294 msaitoh break;
9021 1.294 msaitoh default:
9022 1.294 msaitoh aprint_error_dev(sc->sc_dev,
9023 1.294 msaitoh "%s: unknown device(%d)?\n", __func__, sc->sc_type);
9024 1.294 msaitoh return -1;
9025 1.294 msaitoh break;
9026 1.294 msaitoh }
9027 1.294 msaitoh
9028 1.294 msaitoh sc->sc_nvm_wordsize = 1 << size;
9029 1.294 msaitoh
9030 1.294 msaitoh return 0;
9031 1.243 msaitoh }
9032 1.243 msaitoh
9033 1.243 msaitoh /*
9034 1.281 msaitoh * wm_nvm_ready_spi:
9035 1.1 thorpej *
9036 1.281 msaitoh * Wait for a SPI EEPROM to be ready for commands.
9037 1.1 thorpej */
9038 1.281 msaitoh static int
9039 1.281 msaitoh wm_nvm_ready_spi(struct wm_softc *sc)
9040 1.1 thorpej {
9041 1.281 msaitoh uint32_t val;
9042 1.281 msaitoh int usec;
9043 1.1 thorpej
9044 1.281 msaitoh for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) {
9045 1.281 msaitoh wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8);
9046 1.281 msaitoh wm_eeprom_recvbits(sc, &val, 8);
9047 1.281 msaitoh if ((val & SPI_SR_RDY) == 0)
9048 1.281 msaitoh break;
9049 1.71 thorpej }
9050 1.281 msaitoh if (usec >= SPI_MAX_RETRIES) {
9051 1.281 msaitoh aprint_error_dev(sc->sc_dev, "EEPROM failed to become ready\n");
9052 1.281 msaitoh return 1;
9053 1.127 bouyer }
9054 1.281 msaitoh return 0;
9055 1.127 bouyer }
9056 1.127 bouyer
9057 1.127 bouyer /*
9058 1.281 msaitoh * wm_nvm_read_spi:
9059 1.127 bouyer *
9060 1.281 msaitoh * Read a work from the EEPROM using the SPI protocol.
9061 1.127 bouyer */
9062 1.127 bouyer static int
9063 1.281 msaitoh wm_nvm_read_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
9064 1.127 bouyer {
9065 1.281 msaitoh uint32_t reg, val;
9066 1.281 msaitoh int i;
9067 1.281 msaitoh uint8_t opc;
9068 1.281 msaitoh
9069 1.281 msaitoh /* Clear SK and CS. */
9070 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
9071 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
9072 1.281 msaitoh CSR_WRITE_FLUSH(sc);
9073 1.281 msaitoh delay(2);
9074 1.127 bouyer
9075 1.281 msaitoh if (wm_nvm_ready_spi(sc))
9076 1.281 msaitoh return 1;
9077 1.127 bouyer
9078 1.281 msaitoh /* Toggle CS to flush commands. */
9079 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
9080 1.281 msaitoh CSR_WRITE_FLUSH(sc);
9081 1.281 msaitoh delay(2);
9082 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
9083 1.266 msaitoh CSR_WRITE_FLUSH(sc);
9084 1.127 bouyer delay(2);
9085 1.127 bouyer
9086 1.281 msaitoh opc = SPI_OPC_READ;
9087 1.294 msaitoh if (sc->sc_nvm_addrbits == 8 && word >= 128)
9088 1.281 msaitoh opc |= SPI_OPC_A8;
9089 1.281 msaitoh
9090 1.281 msaitoh wm_eeprom_sendbits(sc, opc, 8);
9091 1.294 msaitoh wm_eeprom_sendbits(sc, word << 1, sc->sc_nvm_addrbits);
9092 1.281 msaitoh
9093 1.281 msaitoh for (i = 0; i < wordcnt; i++) {
9094 1.281 msaitoh wm_eeprom_recvbits(sc, &val, 16);
9095 1.281 msaitoh data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
9096 1.281 msaitoh }
9097 1.178 msaitoh
9098 1.281 msaitoh /* Raise CS and clear SK. */
9099 1.281 msaitoh reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
9100 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
9101 1.281 msaitoh CSR_WRITE_FLUSH(sc);
9102 1.281 msaitoh delay(2);
9103 1.178 msaitoh
9104 1.281 msaitoh return 0;
9105 1.127 bouyer }
9106 1.127 bouyer
9107 1.281 msaitoh /* Using with EERD */
9108 1.281 msaitoh
9109 1.281 msaitoh static int
9110 1.281 msaitoh wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
9111 1.127 bouyer {
9112 1.281 msaitoh uint32_t attempts = 100000;
9113 1.281 msaitoh uint32_t i, reg = 0;
9114 1.281 msaitoh int32_t done = -1;
9115 1.281 msaitoh
9116 1.281 msaitoh for (i = 0; i < attempts; i++) {
9117 1.281 msaitoh reg = CSR_READ(sc, rw);
9118 1.127 bouyer
9119 1.281 msaitoh if (reg & EERD_DONE) {
9120 1.281 msaitoh done = 0;
9121 1.281 msaitoh break;
9122 1.178 msaitoh }
9123 1.281 msaitoh delay(5);
9124 1.169 msaitoh }
9125 1.127 bouyer
9126 1.281 msaitoh return done;
9127 1.1 thorpej }
9128 1.117 msaitoh
9129 1.117 msaitoh static int
9130 1.281 msaitoh wm_nvm_read_eerd(struct wm_softc *sc, int offset, int wordcnt,
9131 1.281 msaitoh uint16_t *data)
9132 1.117 msaitoh {
9133 1.281 msaitoh int i, eerd = 0;
9134 1.281 msaitoh int error = 0;
9135 1.117 msaitoh
9136 1.281 msaitoh for (i = 0; i < wordcnt; i++) {
9137 1.281 msaitoh eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
9138 1.117 msaitoh
9139 1.281 msaitoh CSR_WRITE(sc, WMREG_EERD, eerd);
9140 1.281 msaitoh error = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
9141 1.281 msaitoh if (error != 0)
9142 1.281 msaitoh break;
9143 1.117 msaitoh
9144 1.281 msaitoh data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
9145 1.117 msaitoh }
9146 1.281 msaitoh
9147 1.281 msaitoh return error;
9148 1.117 msaitoh }
9149 1.117 msaitoh
9150 1.281 msaitoh /* Flash */
9151 1.281 msaitoh
9152 1.117 msaitoh static int
9153 1.281 msaitoh wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank)
9154 1.117 msaitoh {
9155 1.281 msaitoh uint32_t eecd;
9156 1.281 msaitoh uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1;
9157 1.281 msaitoh uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t);
9158 1.281 msaitoh uint8_t sig_byte = 0;
9159 1.117 msaitoh
9160 1.281 msaitoh switch (sc->sc_type) {
9161 1.281 msaitoh case WM_T_ICH8:
9162 1.281 msaitoh case WM_T_ICH9:
9163 1.281 msaitoh eecd = CSR_READ(sc, WMREG_EECD);
9164 1.281 msaitoh if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) {
9165 1.281 msaitoh *bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0;
9166 1.281 msaitoh return 0;
9167 1.281 msaitoh }
9168 1.281 msaitoh /* FALLTHROUGH */
9169 1.281 msaitoh default:
9170 1.281 msaitoh /* Default to 0 */
9171 1.281 msaitoh *bank = 0;
9172 1.271 ozaki
9173 1.281 msaitoh /* Check bank 0 */
9174 1.281 msaitoh wm_read_ich8_byte(sc, act_offset, &sig_byte);
9175 1.281 msaitoh if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
9176 1.281 msaitoh *bank = 0;
9177 1.281 msaitoh return 0;
9178 1.281 msaitoh }
9179 1.271 ozaki
9180 1.281 msaitoh /* Check bank 1 */
9181 1.281 msaitoh wm_read_ich8_byte(sc, act_offset + bank1_offset,
9182 1.281 msaitoh &sig_byte);
9183 1.281 msaitoh if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
9184 1.281 msaitoh *bank = 1;
9185 1.281 msaitoh return 0;
9186 1.281 msaitoh }
9187 1.271 ozaki }
9188 1.271 ozaki
9189 1.281 msaitoh DPRINTF(WM_DEBUG_NVM, ("%s: No valid NVM bank present\n",
9190 1.281 msaitoh device_xname(sc->sc_dev)));
9191 1.281 msaitoh return -1;
9192 1.281 msaitoh }
9193 1.281 msaitoh
9194 1.281 msaitoh /******************************************************************************
9195 1.281 msaitoh * This function does initial flash setup so that a new read/write/erase cycle
9196 1.281 msaitoh * can be started.
9197 1.281 msaitoh *
9198 1.281 msaitoh * sc - The pointer to the hw structure
9199 1.281 msaitoh ****************************************************************************/
9200 1.281 msaitoh static int32_t
9201 1.281 msaitoh wm_ich8_cycle_init(struct wm_softc *sc)
9202 1.281 msaitoh {
9203 1.281 msaitoh uint16_t hsfsts;
9204 1.281 msaitoh int32_t error = 1;
9205 1.281 msaitoh int32_t i = 0;
9206 1.271 ozaki
9207 1.281 msaitoh hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
9208 1.117 msaitoh
9209 1.281 msaitoh /* May be check the Flash Des Valid bit in Hw status */
9210 1.281 msaitoh if ((hsfsts & HSFSTS_FLDVAL) == 0) {
9211 1.281 msaitoh return error;
9212 1.117 msaitoh }
9213 1.117 msaitoh
9214 1.281 msaitoh /* Clear FCERR in Hw status by writing 1 */
9215 1.281 msaitoh /* Clear DAEL in Hw status by writing a 1 */
9216 1.281 msaitoh hsfsts |= HSFSTS_ERR | HSFSTS_DAEL;
9217 1.117 msaitoh
9218 1.281 msaitoh ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
9219 1.117 msaitoh
9220 1.281 msaitoh /*
9221 1.281 msaitoh * Either we should have a hardware SPI cycle in progress bit to check
9222 1.281 msaitoh * against, in order to start a new cycle or FDONE bit should be
9223 1.281 msaitoh * changed in the hardware so that it is 1 after harware reset, which
9224 1.281 msaitoh * can then be used as an indication whether a cycle is in progress or
9225 1.281 msaitoh * has been completed .. we should also have some software semaphore
9226 1.281 msaitoh * mechanism to guard FDONE or the cycle in progress bit so that two
9227 1.281 msaitoh * threads access to those bits can be sequentiallized or a way so that
9228 1.281 msaitoh * 2 threads dont start the cycle at the same time
9229 1.281 msaitoh */
9230 1.127 bouyer
9231 1.281 msaitoh if ((hsfsts & HSFSTS_FLINPRO) == 0) {
9232 1.281 msaitoh /*
9233 1.281 msaitoh * There is no cycle running at present, so we can start a
9234 1.281 msaitoh * cycle
9235 1.281 msaitoh */
9236 1.127 bouyer
9237 1.281 msaitoh /* Begin by setting Flash Cycle Done. */
9238 1.281 msaitoh hsfsts |= HSFSTS_DONE;
9239 1.281 msaitoh ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
9240 1.281 msaitoh error = 0;
9241 1.281 msaitoh } else {
9242 1.281 msaitoh /*
9243 1.281 msaitoh * otherwise poll for sometime so the current cycle has a
9244 1.281 msaitoh * chance to end before giving up.
9245 1.281 msaitoh */
9246 1.281 msaitoh for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
9247 1.281 msaitoh hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
9248 1.281 msaitoh if ((hsfsts & HSFSTS_FLINPRO) == 0) {
9249 1.281 msaitoh error = 0;
9250 1.281 msaitoh break;
9251 1.169 msaitoh }
9252 1.281 msaitoh delay(1);
9253 1.127 bouyer }
9254 1.281 msaitoh if (error == 0) {
9255 1.281 msaitoh /*
9256 1.281 msaitoh * Successful in waiting for previous cycle to timeout,
9257 1.281 msaitoh * now set the Flash Cycle Done.
9258 1.281 msaitoh */
9259 1.281 msaitoh hsfsts |= HSFSTS_DONE;
9260 1.281 msaitoh ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
9261 1.127 bouyer }
9262 1.127 bouyer }
9263 1.281 msaitoh return error;
9264 1.127 bouyer }
9265 1.127 bouyer
9266 1.281 msaitoh /******************************************************************************
9267 1.281 msaitoh * This function starts a flash cycle and waits for its completion
9268 1.281 msaitoh *
9269 1.281 msaitoh * sc - The pointer to the hw structure
9270 1.281 msaitoh ****************************************************************************/
9271 1.281 msaitoh static int32_t
9272 1.281 msaitoh wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout)
9273 1.136 msaitoh {
9274 1.281 msaitoh uint16_t hsflctl;
9275 1.281 msaitoh uint16_t hsfsts;
9276 1.281 msaitoh int32_t error = 1;
9277 1.281 msaitoh uint32_t i = 0;
9278 1.127 bouyer
9279 1.281 msaitoh /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
9280 1.281 msaitoh hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
9281 1.281 msaitoh hsflctl |= HSFCTL_GO;
9282 1.281 msaitoh ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
9283 1.139 bouyer
9284 1.281 msaitoh /* Wait till FDONE bit is set to 1 */
9285 1.281 msaitoh do {
9286 1.281 msaitoh hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
9287 1.281 msaitoh if (hsfsts & HSFSTS_DONE)
9288 1.281 msaitoh break;
9289 1.281 msaitoh delay(1);
9290 1.281 msaitoh i++;
9291 1.281 msaitoh } while (i < timeout);
9292 1.281 msaitoh if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0)
9293 1.281 msaitoh error = 0;
9294 1.139 bouyer
9295 1.281 msaitoh return error;
9296 1.139 bouyer }
9297 1.139 bouyer
9298 1.281 msaitoh /******************************************************************************
9299 1.281 msaitoh * Reads a byte or word from the NVM using the ICH8 flash access registers.
9300 1.281 msaitoh *
9301 1.281 msaitoh * sc - The pointer to the hw structure
9302 1.281 msaitoh * index - The index of the byte or word to read.
9303 1.281 msaitoh * size - Size of data to read, 1=byte 2=word
9304 1.281 msaitoh * data - Pointer to the word to store the value read.
9305 1.281 msaitoh *****************************************************************************/
9306 1.281 msaitoh static int32_t
9307 1.281 msaitoh wm_read_ich8_data(struct wm_softc *sc, uint32_t index,
9308 1.281 msaitoh uint32_t size, uint16_t *data)
9309 1.139 bouyer {
9310 1.281 msaitoh uint16_t hsfsts;
9311 1.281 msaitoh uint16_t hsflctl;
9312 1.281 msaitoh uint32_t flash_linear_address;
9313 1.281 msaitoh uint32_t flash_data = 0;
9314 1.281 msaitoh int32_t error = 1;
9315 1.281 msaitoh int32_t count = 0;
9316 1.281 msaitoh
9317 1.281 msaitoh if (size < 1 || size > 2 || data == 0x0 ||
9318 1.281 msaitoh index > ICH_FLASH_LINEAR_ADDR_MASK)
9319 1.281 msaitoh return error;
9320 1.139 bouyer
9321 1.281 msaitoh flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
9322 1.281 msaitoh sc->sc_ich8_flash_base;
9323 1.259 msaitoh
9324 1.259 msaitoh do {
9325 1.281 msaitoh delay(1);
9326 1.281 msaitoh /* Steps */
9327 1.281 msaitoh error = wm_ich8_cycle_init(sc);
9328 1.281 msaitoh if (error)
9329 1.259 msaitoh break;
9330 1.259 msaitoh
9331 1.281 msaitoh hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
9332 1.281 msaitoh /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
9333 1.281 msaitoh hsflctl |= ((size - 1) << HSFCTL_BCOUNT_SHIFT)
9334 1.281 msaitoh & HSFCTL_BCOUNT_MASK;
9335 1.281 msaitoh hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT;
9336 1.281 msaitoh ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
9337 1.281 msaitoh
9338 1.281 msaitoh /*
9339 1.281 msaitoh * Write the last 24 bits of index into Flash Linear address
9340 1.281 msaitoh * field in Flash Address
9341 1.281 msaitoh */
9342 1.281 msaitoh /* TODO: TBD maybe check the index against the size of flash */
9343 1.281 msaitoh
9344 1.281 msaitoh ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address);
9345 1.259 msaitoh
9346 1.281 msaitoh error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT);
9347 1.259 msaitoh
9348 1.281 msaitoh /*
9349 1.281 msaitoh * Check if FCERR is set to 1, if set to 1, clear it and try
9350 1.281 msaitoh * the whole sequence a few more times, else read in (shift in)
9351 1.281 msaitoh * the Flash Data0, the order is least significant byte first
9352 1.281 msaitoh * msb to lsb
9353 1.281 msaitoh */
9354 1.281 msaitoh if (error == 0) {
9355 1.281 msaitoh flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0);
9356 1.281 msaitoh if (size == 1)
9357 1.281 msaitoh *data = (uint8_t)(flash_data & 0x000000FF);
9358 1.281 msaitoh else if (size == 2)
9359 1.281 msaitoh *data = (uint16_t)(flash_data & 0x0000FFFF);
9360 1.281 msaitoh break;
9361 1.281 msaitoh } else {
9362 1.281 msaitoh /*
9363 1.281 msaitoh * If we've gotten here, then things are probably
9364 1.281 msaitoh * completely hosed, but if the error condition is
9365 1.281 msaitoh * detected, it won't hurt to give it another try...
9366 1.281 msaitoh * ICH_FLASH_CYCLE_REPEAT_COUNT times.
9367 1.281 msaitoh */
9368 1.281 msaitoh hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
9369 1.281 msaitoh if (hsfsts & HSFSTS_ERR) {
9370 1.281 msaitoh /* Repeat for some time before giving up. */
9371 1.281 msaitoh continue;
9372 1.281 msaitoh } else if ((hsfsts & HSFSTS_DONE) == 0)
9373 1.281 msaitoh break;
9374 1.281 msaitoh }
9375 1.281 msaitoh } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
9376 1.259 msaitoh
9377 1.281 msaitoh return error;
9378 1.259 msaitoh }
9379 1.259 msaitoh
9380 1.281 msaitoh /******************************************************************************
9381 1.281 msaitoh * Reads a single byte from the NVM using the ICH8 flash access registers.
9382 1.281 msaitoh *
9383 1.281 msaitoh * sc - pointer to wm_hw structure
9384 1.281 msaitoh * index - The index of the byte to read.
9385 1.281 msaitoh * data - Pointer to a byte to store the value read.
9386 1.281 msaitoh *****************************************************************************/
9387 1.281 msaitoh static int32_t
9388 1.281 msaitoh wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data)
9389 1.169 msaitoh {
9390 1.281 msaitoh int32_t status;
9391 1.281 msaitoh uint16_t word = 0;
9392 1.250 msaitoh
9393 1.281 msaitoh status = wm_read_ich8_data(sc, index, 1, &word);
9394 1.281 msaitoh if (status == 0)
9395 1.281 msaitoh *data = (uint8_t)word;
9396 1.281 msaitoh else
9397 1.281 msaitoh *data = 0;
9398 1.169 msaitoh
9399 1.281 msaitoh return status;
9400 1.281 msaitoh }
9401 1.250 msaitoh
9402 1.281 msaitoh /******************************************************************************
9403 1.281 msaitoh * Reads a word from the NVM using the ICH8 flash access registers.
9404 1.281 msaitoh *
9405 1.281 msaitoh * sc - pointer to wm_hw structure
9406 1.281 msaitoh * index - The starting byte index of the word to read.
9407 1.281 msaitoh * data - Pointer to a word to store the value read.
9408 1.281 msaitoh *****************************************************************************/
9409 1.281 msaitoh static int32_t
9410 1.281 msaitoh wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data)
9411 1.281 msaitoh {
9412 1.281 msaitoh int32_t status;
9413 1.169 msaitoh
9414 1.281 msaitoh status = wm_read_ich8_data(sc, index, 2, data);
9415 1.281 msaitoh return status;
9416 1.169 msaitoh }
9417 1.169 msaitoh
9418 1.139 bouyer /******************************************************************************
9419 1.139 bouyer * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
9420 1.139 bouyer * register.
9421 1.139 bouyer *
9422 1.139 bouyer * sc - Struct containing variables accessed by shared code
9423 1.139 bouyer * offset - offset of word in the EEPROM to read
9424 1.139 bouyer * data - word read from the EEPROM
9425 1.139 bouyer * words - number of words to read
9426 1.139 bouyer *****************************************************************************/
9427 1.139 bouyer static int
9428 1.280 msaitoh wm_nvm_read_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data)
9429 1.139 bouyer {
9430 1.194 msaitoh int32_t error = 0;
9431 1.194 msaitoh uint32_t flash_bank = 0;
9432 1.194 msaitoh uint32_t act_offset = 0;
9433 1.194 msaitoh uint32_t bank_offset = 0;
9434 1.194 msaitoh uint16_t word = 0;
9435 1.194 msaitoh uint16_t i = 0;
9436 1.194 msaitoh
9437 1.281 msaitoh /*
9438 1.281 msaitoh * We need to know which is the valid flash bank. In the event
9439 1.194 msaitoh * that we didn't allocate eeprom_shadow_ram, we may not be
9440 1.194 msaitoh * managing flash_bank. So it cannot be trusted and needs
9441 1.194 msaitoh * to be updated with each read.
9442 1.194 msaitoh */
9443 1.280 msaitoh error = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
9444 1.194 msaitoh if (error) {
9445 1.297 msaitoh DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
9446 1.297 msaitoh device_xname(sc->sc_dev)));
9447 1.262 msaitoh flash_bank = 0;
9448 1.194 msaitoh }
9449 1.139 bouyer
9450 1.238 msaitoh /*
9451 1.238 msaitoh * Adjust offset appropriately if we're on bank 1 - adjust for word
9452 1.238 msaitoh * size
9453 1.238 msaitoh */
9454 1.194 msaitoh bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
9455 1.139 bouyer
9456 1.194 msaitoh error = wm_get_swfwhw_semaphore(sc);
9457 1.194 msaitoh if (error) {
9458 1.194 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
9459 1.169 msaitoh __func__);
9460 1.194 msaitoh return error;
9461 1.194 msaitoh }
9462 1.139 bouyer
9463 1.194 msaitoh for (i = 0; i < words; i++) {
9464 1.194 msaitoh /* The NVM part needs a byte offset, hence * 2 */
9465 1.194 msaitoh act_offset = bank_offset + ((offset + i) * 2);
9466 1.194 msaitoh error = wm_read_ich8_word(sc, act_offset, &word);
9467 1.194 msaitoh if (error) {
9468 1.238 msaitoh aprint_error_dev(sc->sc_dev,
9469 1.238 msaitoh "%s: failed to read NVM\n", __func__);
9470 1.194 msaitoh break;
9471 1.194 msaitoh }
9472 1.194 msaitoh data[i] = word;
9473 1.194 msaitoh }
9474 1.194 msaitoh
9475 1.194 msaitoh wm_put_swfwhw_semaphore(sc);
9476 1.194 msaitoh return error;
9477 1.139 bouyer }
9478 1.139 bouyer
9479 1.321 msaitoh /* iNVM */
9480 1.321 msaitoh
9481 1.321 msaitoh static int
9482 1.321 msaitoh wm_nvm_read_word_invm(struct wm_softc *sc, uint16_t address, uint16_t *data)
9483 1.321 msaitoh {
9484 1.321 msaitoh int32_t rv = 0;
9485 1.321 msaitoh uint32_t invm_dword;
9486 1.321 msaitoh uint16_t i;
9487 1.321 msaitoh uint8_t record_type, word_address;
9488 1.321 msaitoh
9489 1.321 msaitoh for (i = 0; i < INVM_SIZE; i++) {
9490 1.329 msaitoh invm_dword = CSR_READ(sc, WM_INVM_DATA_REG(i));
9491 1.321 msaitoh /* Get record type */
9492 1.321 msaitoh record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
9493 1.321 msaitoh if (record_type == INVM_UNINITIALIZED_STRUCTURE)
9494 1.321 msaitoh break;
9495 1.321 msaitoh if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE)
9496 1.321 msaitoh i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
9497 1.321 msaitoh if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE)
9498 1.321 msaitoh i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
9499 1.321 msaitoh if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) {
9500 1.321 msaitoh word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
9501 1.321 msaitoh if (word_address == address) {
9502 1.321 msaitoh *data = INVM_DWORD_TO_WORD_DATA(invm_dword);
9503 1.321 msaitoh rv = 0;
9504 1.321 msaitoh break;
9505 1.321 msaitoh }
9506 1.321 msaitoh }
9507 1.321 msaitoh }
9508 1.321 msaitoh
9509 1.321 msaitoh return rv;
9510 1.321 msaitoh }
9511 1.321 msaitoh
9512 1.321 msaitoh static int
9513 1.321 msaitoh wm_nvm_read_invm(struct wm_softc *sc, int offset, int words, uint16_t *data)
9514 1.321 msaitoh {
9515 1.321 msaitoh int rv = 0;
9516 1.321 msaitoh int i;
9517 1.321 msaitoh
9518 1.321 msaitoh for (i = 0; i < words; i++) {
9519 1.321 msaitoh switch (offset + i) {
9520 1.321 msaitoh case NVM_OFF_MACADDR:
9521 1.321 msaitoh case NVM_OFF_MACADDR1:
9522 1.321 msaitoh case NVM_OFF_MACADDR2:
9523 1.321 msaitoh rv = wm_nvm_read_word_invm(sc, offset + i, &data[i]);
9524 1.321 msaitoh if (rv != 0) {
9525 1.321 msaitoh data[i] = 0xffff;
9526 1.321 msaitoh rv = -1;
9527 1.321 msaitoh }
9528 1.321 msaitoh break;
9529 1.321 msaitoh case NVM_OFF_CFG2:
9530 1.321 msaitoh rv = wm_nvm_read_word_invm(sc, offset, data);
9531 1.321 msaitoh if (rv != 0) {
9532 1.321 msaitoh *data = NVM_INIT_CTRL_2_DEFAULT_I211;
9533 1.321 msaitoh rv = 0;
9534 1.321 msaitoh }
9535 1.321 msaitoh break;
9536 1.321 msaitoh case NVM_OFF_CFG4:
9537 1.321 msaitoh rv = wm_nvm_read_word_invm(sc, offset, data);
9538 1.321 msaitoh if (rv != 0) {
9539 1.321 msaitoh *data = NVM_INIT_CTRL_4_DEFAULT_I211;
9540 1.321 msaitoh rv = 0;
9541 1.321 msaitoh }
9542 1.321 msaitoh break;
9543 1.321 msaitoh case NVM_OFF_LED_1_CFG:
9544 1.321 msaitoh rv = wm_nvm_read_word_invm(sc, offset, data);
9545 1.321 msaitoh if (rv != 0) {
9546 1.321 msaitoh *data = NVM_LED_1_CFG_DEFAULT_I211;
9547 1.321 msaitoh rv = 0;
9548 1.321 msaitoh }
9549 1.321 msaitoh break;
9550 1.321 msaitoh case NVM_OFF_LED_0_2_CFG:
9551 1.321 msaitoh rv = wm_nvm_read_word_invm(sc, offset, data);
9552 1.321 msaitoh if (rv != 0) {
9553 1.321 msaitoh *data = NVM_LED_0_2_CFG_DEFAULT_I211;
9554 1.321 msaitoh rv = 0;
9555 1.321 msaitoh }
9556 1.321 msaitoh break;
9557 1.321 msaitoh case NVM_OFF_ID_LED_SETTINGS:
9558 1.321 msaitoh rv = wm_nvm_read_word_invm(sc, offset, data);
9559 1.321 msaitoh if (rv != 0) {
9560 1.321 msaitoh *data = ID_LED_RESERVED_FFFF;
9561 1.321 msaitoh rv = 0;
9562 1.321 msaitoh }
9563 1.321 msaitoh break;
9564 1.321 msaitoh default:
9565 1.321 msaitoh DPRINTF(WM_DEBUG_NVM,
9566 1.321 msaitoh ("NVM word 0x%02x is not mapped.\n", offset));
9567 1.321 msaitoh *data = NVM_RESERVED_WORD;
9568 1.321 msaitoh break;
9569 1.321 msaitoh }
9570 1.321 msaitoh }
9571 1.321 msaitoh
9572 1.321 msaitoh return rv;
9573 1.321 msaitoh }
9574 1.321 msaitoh
9575 1.328 msaitoh /* Lock, detecting NVM type, validate checksum, version and read */
9576 1.281 msaitoh
9577 1.281 msaitoh /*
9578 1.281 msaitoh * wm_nvm_acquire:
9579 1.139 bouyer *
9580 1.281 msaitoh * Perform the EEPROM handshake required on some chips.
9581 1.281 msaitoh */
9582 1.281 msaitoh static int
9583 1.281 msaitoh wm_nvm_acquire(struct wm_softc *sc)
9584 1.139 bouyer {
9585 1.281 msaitoh uint32_t reg;
9586 1.281 msaitoh int x;
9587 1.281 msaitoh int ret = 0;
9588 1.194 msaitoh
9589 1.281 msaitoh /* always success */
9590 1.281 msaitoh if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0)
9591 1.281 msaitoh return 0;
9592 1.194 msaitoh
9593 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_EXTCNF) {
9594 1.281 msaitoh ret = wm_get_swfwhw_semaphore(sc);
9595 1.281 msaitoh } else if (sc->sc_flags & WM_F_LOCK_SWFW) {
9596 1.281 msaitoh /* This will also do wm_get_swsm_semaphore() if needed */
9597 1.281 msaitoh ret = wm_get_swfw_semaphore(sc, SWFW_EEP_SM);
9598 1.281 msaitoh } else if (sc->sc_flags & WM_F_LOCK_SWSM) {
9599 1.281 msaitoh ret = wm_get_swsm_semaphore(sc);
9600 1.194 msaitoh }
9601 1.194 msaitoh
9602 1.281 msaitoh if (ret) {
9603 1.281 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
9604 1.281 msaitoh __func__);
9605 1.281 msaitoh return 1;
9606 1.281 msaitoh }
9607 1.194 msaitoh
9608 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_EECD) {
9609 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD);
9610 1.194 msaitoh
9611 1.281 msaitoh /* Request EEPROM access. */
9612 1.281 msaitoh reg |= EECD_EE_REQ;
9613 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
9614 1.194 msaitoh
9615 1.281 msaitoh /* ..and wait for it to be granted. */
9616 1.281 msaitoh for (x = 0; x < 1000; x++) {
9617 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD);
9618 1.281 msaitoh if (reg & EECD_EE_GNT)
9619 1.194 msaitoh break;
9620 1.281 msaitoh delay(5);
9621 1.194 msaitoh }
9622 1.281 msaitoh if ((reg & EECD_EE_GNT) == 0) {
9623 1.281 msaitoh aprint_error_dev(sc->sc_dev,
9624 1.281 msaitoh "could not acquire EEPROM GNT\n");
9625 1.281 msaitoh reg &= ~EECD_EE_REQ;
9626 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
9627 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_EXTCNF)
9628 1.281 msaitoh wm_put_swfwhw_semaphore(sc);
9629 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_SWFW)
9630 1.281 msaitoh wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
9631 1.281 msaitoh else if (sc->sc_flags & WM_F_LOCK_SWSM)
9632 1.281 msaitoh wm_put_swsm_semaphore(sc);
9633 1.281 msaitoh return 1;
9634 1.194 msaitoh }
9635 1.194 msaitoh }
9636 1.281 msaitoh
9637 1.281 msaitoh return 0;
9638 1.139 bouyer }
9639 1.139 bouyer
9640 1.281 msaitoh /*
9641 1.281 msaitoh * wm_nvm_release:
9642 1.139 bouyer *
9643 1.281 msaitoh * Release the EEPROM mutex.
9644 1.281 msaitoh */
9645 1.281 msaitoh static void
9646 1.281 msaitoh wm_nvm_release(struct wm_softc *sc)
9647 1.139 bouyer {
9648 1.281 msaitoh uint32_t reg;
9649 1.194 msaitoh
9650 1.281 msaitoh /* always success */
9651 1.281 msaitoh if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0)
9652 1.281 msaitoh return;
9653 1.194 msaitoh
9654 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_EECD) {
9655 1.281 msaitoh reg = CSR_READ(sc, WMREG_EECD);
9656 1.281 msaitoh reg &= ~EECD_EE_REQ;
9657 1.281 msaitoh CSR_WRITE(sc, WMREG_EECD, reg);
9658 1.281 msaitoh }
9659 1.194 msaitoh
9660 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_EXTCNF)
9661 1.281 msaitoh wm_put_swfwhw_semaphore(sc);
9662 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_SWFW)
9663 1.281 msaitoh wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
9664 1.281 msaitoh else if (sc->sc_flags & WM_F_LOCK_SWSM)
9665 1.281 msaitoh wm_put_swsm_semaphore(sc);
9666 1.139 bouyer }
9667 1.139 bouyer
9668 1.281 msaitoh static int
9669 1.281 msaitoh wm_nvm_is_onboard_eeprom(struct wm_softc *sc)
9670 1.139 bouyer {
9671 1.281 msaitoh uint32_t eecd = 0;
9672 1.281 msaitoh
9673 1.281 msaitoh if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574
9674 1.281 msaitoh || sc->sc_type == WM_T_82583) {
9675 1.281 msaitoh eecd = CSR_READ(sc, WMREG_EECD);
9676 1.281 msaitoh
9677 1.281 msaitoh /* Isolate bits 15 & 16 */
9678 1.281 msaitoh eecd = ((eecd >> 15) & 0x03);
9679 1.194 msaitoh
9680 1.281 msaitoh /* If both bits are set, device is Flash type */
9681 1.281 msaitoh if (eecd == 0x03)
9682 1.281 msaitoh return 0;
9683 1.281 msaitoh }
9684 1.281 msaitoh return 1;
9685 1.281 msaitoh }
9686 1.194 msaitoh
9687 1.321 msaitoh static int
9688 1.321 msaitoh wm_nvm_get_flash_presence_i210(struct wm_softc *sc)
9689 1.321 msaitoh {
9690 1.321 msaitoh uint32_t eec;
9691 1.321 msaitoh
9692 1.321 msaitoh eec = CSR_READ(sc, WMREG_EEC);
9693 1.321 msaitoh if ((eec & EEC_FLASH_DETECTED) != 0)
9694 1.321 msaitoh return 1;
9695 1.321 msaitoh
9696 1.321 msaitoh return 0;
9697 1.321 msaitoh }
9698 1.321 msaitoh
9699 1.281 msaitoh /*
9700 1.281 msaitoh * wm_nvm_validate_checksum
9701 1.281 msaitoh *
9702 1.281 msaitoh * The checksum is defined as the sum of the first 64 (16 bit) words.
9703 1.281 msaitoh */
9704 1.281 msaitoh static int
9705 1.281 msaitoh wm_nvm_validate_checksum(struct wm_softc *sc)
9706 1.281 msaitoh {
9707 1.281 msaitoh uint16_t checksum;
9708 1.281 msaitoh uint16_t eeprom_data;
9709 1.281 msaitoh #ifdef WM_DEBUG
9710 1.281 msaitoh uint16_t csum_wordaddr, valid_checksum;
9711 1.281 msaitoh #endif
9712 1.281 msaitoh int i;
9713 1.194 msaitoh
9714 1.281 msaitoh checksum = 0;
9715 1.139 bouyer
9716 1.281 msaitoh /* Don't check for I211 */
9717 1.281 msaitoh if (sc->sc_type == WM_T_I211)
9718 1.281 msaitoh return 0;
9719 1.194 msaitoh
9720 1.281 msaitoh #ifdef WM_DEBUG
9721 1.281 msaitoh if (sc->sc_type == WM_T_PCH_LPT) {
9722 1.293 msaitoh csum_wordaddr = NVM_OFF_COMPAT;
9723 1.281 msaitoh valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
9724 1.281 msaitoh } else {
9725 1.293 msaitoh csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1;
9726 1.281 msaitoh valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;
9727 1.281 msaitoh }
9728 1.194 msaitoh
9729 1.281 msaitoh /* Dump EEPROM image for debug */
9730 1.281 msaitoh if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
9731 1.281 msaitoh || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
9732 1.281 msaitoh || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
9733 1.281 msaitoh wm_nvm_read(sc, csum_wordaddr, 1, &eeprom_data);
9734 1.281 msaitoh if ((eeprom_data & valid_checksum) == 0) {
9735 1.281 msaitoh DPRINTF(WM_DEBUG_NVM,
9736 1.281 msaitoh ("%s: NVM need to be updated (%04x != %04x)\n",
9737 1.281 msaitoh device_xname(sc->sc_dev), eeprom_data,
9738 1.281 msaitoh valid_checksum));
9739 1.281 msaitoh }
9740 1.281 msaitoh }
9741 1.194 msaitoh
9742 1.281 msaitoh if ((wm_debug & WM_DEBUG_NVM) != 0) {
9743 1.281 msaitoh printf("%s: NVM dump:\n", device_xname(sc->sc_dev));
9744 1.293 msaitoh for (i = 0; i < NVM_SIZE; i++) {
9745 1.281 msaitoh if (wm_nvm_read(sc, i, 1, &eeprom_data))
9746 1.301 msaitoh printf("XXXX ");
9747 1.281 msaitoh else
9748 1.301 msaitoh printf("%04hx ", eeprom_data);
9749 1.281 msaitoh if (i % 8 == 7)
9750 1.281 msaitoh printf("\n");
9751 1.194 msaitoh }
9752 1.281 msaitoh }
9753 1.194 msaitoh
9754 1.281 msaitoh #endif /* WM_DEBUG */
9755 1.139 bouyer
9756 1.293 msaitoh for (i = 0; i < NVM_SIZE; i++) {
9757 1.281 msaitoh if (wm_nvm_read(sc, i, 1, &eeprom_data))
9758 1.281 msaitoh return 1;
9759 1.281 msaitoh checksum += eeprom_data;
9760 1.281 msaitoh }
9761 1.139 bouyer
9762 1.281 msaitoh if (checksum != (uint16_t) NVM_CHECKSUM) {
9763 1.281 msaitoh #ifdef WM_DEBUG
9764 1.281 msaitoh printf("%s: NVM checksum mismatch (%04x != %04x)\n",
9765 1.281 msaitoh device_xname(sc->sc_dev), checksum, NVM_CHECKSUM);
9766 1.281 msaitoh #endif
9767 1.281 msaitoh }
9768 1.139 bouyer
9769 1.281 msaitoh return 0;
9770 1.139 bouyer }
9771 1.139 bouyer
9772 1.328 msaitoh static void
9773 1.347 msaitoh wm_nvm_version_invm(struct wm_softc *sc)
9774 1.347 msaitoh {
9775 1.347 msaitoh uint32_t dword;
9776 1.347 msaitoh
9777 1.347 msaitoh /*
9778 1.347 msaitoh * Linux's code to decode version is very strange, so we don't
9779 1.347 msaitoh * obey that algorithm and just use word 61 as the document.
9780 1.347 msaitoh * Perhaps it's not perfect though...
9781 1.347 msaitoh *
9782 1.347 msaitoh * Example:
9783 1.347 msaitoh *
9784 1.347 msaitoh * Word61: 00800030 -> Version 0.6 (I211 spec update notes about 0.6)
9785 1.347 msaitoh */
9786 1.347 msaitoh dword = CSR_READ(sc, WM_INVM_DATA_REG(61));
9787 1.347 msaitoh dword = __SHIFTOUT(dword, INVM_VER_1);
9788 1.347 msaitoh sc->sc_nvm_ver_major = __SHIFTOUT(dword, INVM_MAJOR);
9789 1.347 msaitoh sc->sc_nvm_ver_minor = __SHIFTOUT(dword, INVM_MINOR);
9790 1.347 msaitoh }
9791 1.347 msaitoh
9792 1.347 msaitoh static void
9793 1.328 msaitoh wm_nvm_version(struct wm_softc *sc)
9794 1.328 msaitoh {
9795 1.331 msaitoh uint16_t major, minor, build, patch;
9796 1.328 msaitoh uint16_t uid0, uid1;
9797 1.328 msaitoh uint16_t nvm_data;
9798 1.328 msaitoh uint16_t off;
9799 1.330 msaitoh bool check_version = false;
9800 1.330 msaitoh bool check_optionrom = false;
9801 1.334 msaitoh bool have_build = false;
9802 1.328 msaitoh
9803 1.334 msaitoh /*
9804 1.334 msaitoh * Version format:
9805 1.334 msaitoh *
9806 1.334 msaitoh * XYYZ
9807 1.334 msaitoh * X0YZ
9808 1.334 msaitoh * X0YY
9809 1.334 msaitoh *
9810 1.334 msaitoh * Example:
9811 1.334 msaitoh *
9812 1.334 msaitoh * 82571 0x50a2 5.10.2? (the spec update notes about 5.6-5.10)
9813 1.334 msaitoh * 82571 0x50a6 5.10.6?
9814 1.334 msaitoh * 82572 0x506a 5.6.10?
9815 1.334 msaitoh * 82572EI 0x5069 5.6.9?
9816 1.334 msaitoh * 82574L 0x1080 1.8.0? (the spec update notes about 2.1.4)
9817 1.334 msaitoh * 0x2013 2.1.3?
9818 1.334 msaitoh * 82583 0x10a0 1.10.0? (document says it's default vaule)
9819 1.334 msaitoh */
9820 1.328 msaitoh wm_nvm_read(sc, NVM_OFF_IMAGE_UID1, 1, &uid1);
9821 1.328 msaitoh switch (sc->sc_type) {
9822 1.334 msaitoh case WM_T_82571:
9823 1.334 msaitoh case WM_T_82572:
9824 1.334 msaitoh case WM_T_82574:
9825 1.334 msaitoh check_version = true;
9826 1.334 msaitoh check_optionrom = true;
9827 1.334 msaitoh have_build = true;
9828 1.334 msaitoh break;
9829 1.328 msaitoh case WM_T_82575:
9830 1.328 msaitoh case WM_T_82576:
9831 1.328 msaitoh case WM_T_82580:
9832 1.330 msaitoh if ((uid1 & NVM_MAJOR_MASK) != NVM_UID_VALID)
9833 1.330 msaitoh check_version = true;
9834 1.328 msaitoh break;
9835 1.328 msaitoh case WM_T_I211:
9836 1.347 msaitoh wm_nvm_version_invm(sc);
9837 1.347 msaitoh goto printver;
9838 1.328 msaitoh case WM_T_I210:
9839 1.328 msaitoh if (!wm_nvm_get_flash_presence_i210(sc)) {
9840 1.347 msaitoh wm_nvm_version_invm(sc);
9841 1.347 msaitoh goto printver;
9842 1.328 msaitoh }
9843 1.328 msaitoh /* FALLTHROUGH */
9844 1.328 msaitoh case WM_T_I350:
9845 1.328 msaitoh case WM_T_I354:
9846 1.330 msaitoh check_version = true;
9847 1.330 msaitoh check_optionrom = true;
9848 1.330 msaitoh break;
9849 1.330 msaitoh default:
9850 1.330 msaitoh return;
9851 1.330 msaitoh }
9852 1.330 msaitoh if (check_version) {
9853 1.330 msaitoh wm_nvm_read(sc, NVM_OFF_VERSION, 1, &nvm_data);
9854 1.330 msaitoh major = (nvm_data & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
9855 1.334 msaitoh if (have_build || ((nvm_data & 0x0f00) != 0x0000)) {
9856 1.330 msaitoh minor = (nvm_data & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
9857 1.330 msaitoh build = nvm_data & NVM_BUILD_MASK;
9858 1.331 msaitoh have_build = true;
9859 1.334 msaitoh } else
9860 1.334 msaitoh minor = nvm_data & 0x00ff;
9861 1.334 msaitoh
9862 1.330 msaitoh /* Decimal */
9863 1.330 msaitoh minor = (minor / 16) * 10 + (minor % 16);
9864 1.347 msaitoh sc->sc_nvm_ver_major = major;
9865 1.347 msaitoh sc->sc_nvm_ver_minor = minor;
9866 1.330 msaitoh
9867 1.347 msaitoh printver:
9868 1.347 msaitoh aprint_verbose(", version %d.%d", sc->sc_nvm_ver_major,
9869 1.347 msaitoh sc->sc_nvm_ver_minor);
9870 1.331 msaitoh if (have_build)
9871 1.334 msaitoh aprint_verbose(".%d", build);
9872 1.330 msaitoh }
9873 1.330 msaitoh if (check_optionrom) {
9874 1.328 msaitoh wm_nvm_read(sc, NVM_OFF_COMB_VER_PTR, 1, &off);
9875 1.328 msaitoh /* Option ROM Version */
9876 1.328 msaitoh if ((off != 0x0000) && (off != 0xffff)) {
9877 1.328 msaitoh off += NVM_COMBO_VER_OFF;
9878 1.328 msaitoh wm_nvm_read(sc, off + 1, 1, &uid1);
9879 1.328 msaitoh wm_nvm_read(sc, off, 1, &uid0);
9880 1.328 msaitoh if ((uid0 != 0) && (uid0 != 0xffff)
9881 1.328 msaitoh && (uid1 != 0) && (uid1 != 0xffff)) {
9882 1.331 msaitoh /* 16bits */
9883 1.331 msaitoh major = uid0 >> 8;
9884 1.331 msaitoh build = (uid0 << 8) | (uid1 >> 8);
9885 1.331 msaitoh patch = uid1 & 0x00ff;
9886 1.330 msaitoh aprint_verbose(", option ROM Version %d.%d.%d",
9887 1.331 msaitoh major, build, patch);
9888 1.328 msaitoh }
9889 1.328 msaitoh }
9890 1.328 msaitoh }
9891 1.328 msaitoh
9892 1.328 msaitoh wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0);
9893 1.328 msaitoh aprint_verbose(", Image Unique ID %08x", (uid1 << 16) | uid0);
9894 1.328 msaitoh }
9895 1.328 msaitoh
9896 1.281 msaitoh /*
9897 1.281 msaitoh * wm_nvm_read:
9898 1.139 bouyer *
9899 1.281 msaitoh * Read data from the serial EEPROM.
9900 1.281 msaitoh */
9901 1.169 msaitoh static int
9902 1.281 msaitoh wm_nvm_read(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
9903 1.169 msaitoh {
9904 1.169 msaitoh int rv;
9905 1.169 msaitoh
9906 1.281 msaitoh if (sc->sc_flags & WM_F_EEPROM_INVALID)
9907 1.281 msaitoh return 1;
9908 1.281 msaitoh
9909 1.281 msaitoh if (wm_nvm_acquire(sc))
9910 1.281 msaitoh return 1;
9911 1.281 msaitoh
9912 1.281 msaitoh if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
9913 1.281 msaitoh || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
9914 1.281 msaitoh || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
9915 1.281 msaitoh rv = wm_nvm_read_ich8(sc, word, wordcnt, data);
9916 1.321 msaitoh else if (sc->sc_flags & WM_F_EEPROM_INVM)
9917 1.321 msaitoh rv = wm_nvm_read_invm(sc, word, wordcnt, data);
9918 1.281 msaitoh else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR)
9919 1.281 msaitoh rv = wm_nvm_read_eerd(sc, word, wordcnt, data);
9920 1.281 msaitoh else if (sc->sc_flags & WM_F_EEPROM_SPI)
9921 1.281 msaitoh rv = wm_nvm_read_spi(sc, word, wordcnt, data);
9922 1.281 msaitoh else
9923 1.281 msaitoh rv = wm_nvm_read_uwire(sc, word, wordcnt, data);
9924 1.169 msaitoh
9925 1.281 msaitoh wm_nvm_release(sc);
9926 1.169 msaitoh return rv;
9927 1.169 msaitoh }
9928 1.169 msaitoh
9929 1.281 msaitoh /*
9930 1.281 msaitoh * Hardware semaphores.
9931 1.281 msaitoh * Very complexed...
9932 1.281 msaitoh */
9933 1.281 msaitoh
9934 1.169 msaitoh static int
9935 1.281 msaitoh wm_get_swsm_semaphore(struct wm_softc *sc)
9936 1.169 msaitoh {
9937 1.281 msaitoh int32_t timeout;
9938 1.281 msaitoh uint32_t swsm;
9939 1.281 msaitoh
9940 1.287 msaitoh if (sc->sc_flags & WM_F_LOCK_SWSM) {
9941 1.287 msaitoh /* Get the SW semaphore. */
9942 1.294 msaitoh timeout = sc->sc_nvm_wordsize + 1;
9943 1.287 msaitoh while (timeout) {
9944 1.287 msaitoh swsm = CSR_READ(sc, WMREG_SWSM);
9945 1.281 msaitoh
9946 1.287 msaitoh if ((swsm & SWSM_SMBI) == 0)
9947 1.287 msaitoh break;
9948 1.169 msaitoh
9949 1.287 msaitoh delay(50);
9950 1.287 msaitoh timeout--;
9951 1.287 msaitoh }
9952 1.169 msaitoh
9953 1.287 msaitoh if (timeout == 0) {
9954 1.287 msaitoh aprint_error_dev(sc->sc_dev,
9955 1.287 msaitoh "could not acquire SWSM SMBI\n");
9956 1.287 msaitoh return 1;
9957 1.287 msaitoh }
9958 1.281 msaitoh }
9959 1.281 msaitoh
9960 1.281 msaitoh /* Get the FW semaphore. */
9961 1.294 msaitoh timeout = sc->sc_nvm_wordsize + 1;
9962 1.281 msaitoh while (timeout) {
9963 1.281 msaitoh swsm = CSR_READ(sc, WMREG_SWSM);
9964 1.281 msaitoh swsm |= SWSM_SWESMBI;
9965 1.281 msaitoh CSR_WRITE(sc, WMREG_SWSM, swsm);
9966 1.281 msaitoh /* If we managed to set the bit we got the semaphore. */
9967 1.281 msaitoh swsm = CSR_READ(sc, WMREG_SWSM);
9968 1.281 msaitoh if (swsm & SWSM_SWESMBI)
9969 1.281 msaitoh break;
9970 1.169 msaitoh
9971 1.281 msaitoh delay(50);
9972 1.281 msaitoh timeout--;
9973 1.281 msaitoh }
9974 1.281 msaitoh
9975 1.281 msaitoh if (timeout == 0) {
9976 1.281 msaitoh aprint_error_dev(sc->sc_dev, "could not acquire SWSM SWESMBI\n");
9977 1.281 msaitoh /* Release semaphores */
9978 1.281 msaitoh wm_put_swsm_semaphore(sc);
9979 1.281 msaitoh return 1;
9980 1.281 msaitoh }
9981 1.169 msaitoh return 0;
9982 1.169 msaitoh }
9983 1.169 msaitoh
9984 1.281 msaitoh static void
9985 1.281 msaitoh wm_put_swsm_semaphore(struct wm_softc *sc)
9986 1.169 msaitoh {
9987 1.281 msaitoh uint32_t swsm;
9988 1.169 msaitoh
9989 1.281 msaitoh swsm = CSR_READ(sc, WMREG_SWSM);
9990 1.281 msaitoh swsm &= ~(SWSM_SMBI | SWSM_SWESMBI);
9991 1.281 msaitoh CSR_WRITE(sc, WMREG_SWSM, swsm);
9992 1.169 msaitoh }
9993 1.169 msaitoh
9994 1.169 msaitoh static int
9995 1.281 msaitoh wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
9996 1.169 msaitoh {
9997 1.281 msaitoh uint32_t swfw_sync;
9998 1.281 msaitoh uint32_t swmask = mask << SWFW_SOFT_SHIFT;
9999 1.281 msaitoh uint32_t fwmask = mask << SWFW_FIRM_SHIFT;
10000 1.281 msaitoh int timeout = 200;
10001 1.169 msaitoh
10002 1.281 msaitoh for (timeout = 0; timeout < 200; timeout++) {
10003 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_SWSM) {
10004 1.281 msaitoh if (wm_get_swsm_semaphore(sc)) {
10005 1.281 msaitoh aprint_error_dev(sc->sc_dev,
10006 1.281 msaitoh "%s: failed to get semaphore\n",
10007 1.281 msaitoh __func__);
10008 1.281 msaitoh return 1;
10009 1.281 msaitoh }
10010 1.281 msaitoh }
10011 1.281 msaitoh swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
10012 1.281 msaitoh if ((swfw_sync & (swmask | fwmask)) == 0) {
10013 1.281 msaitoh swfw_sync |= swmask;
10014 1.281 msaitoh CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
10015 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_SWSM)
10016 1.281 msaitoh wm_put_swsm_semaphore(sc);
10017 1.281 msaitoh return 0;
10018 1.281 msaitoh }
10019 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_SWSM)
10020 1.281 msaitoh wm_put_swsm_semaphore(sc);
10021 1.281 msaitoh delay(5000);
10022 1.281 msaitoh }
10023 1.281 msaitoh printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n",
10024 1.281 msaitoh device_xname(sc->sc_dev), mask, swfw_sync);
10025 1.281 msaitoh return 1;
10026 1.281 msaitoh }
10027 1.169 msaitoh
10028 1.281 msaitoh static void
10029 1.281 msaitoh wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
10030 1.281 msaitoh {
10031 1.281 msaitoh uint32_t swfw_sync;
10032 1.169 msaitoh
10033 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_SWSM) {
10034 1.281 msaitoh while (wm_get_swsm_semaphore(sc) != 0)
10035 1.281 msaitoh continue;
10036 1.281 msaitoh }
10037 1.281 msaitoh swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
10038 1.281 msaitoh swfw_sync &= ~(mask << SWFW_SOFT_SHIFT);
10039 1.281 msaitoh CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
10040 1.281 msaitoh if (sc->sc_flags & WM_F_LOCK_SWSM)
10041 1.281 msaitoh wm_put_swsm_semaphore(sc);
10042 1.169 msaitoh }
10043 1.169 msaitoh
10044 1.189 msaitoh static int
10045 1.281 msaitoh wm_get_swfwhw_semaphore(struct wm_softc *sc)
10046 1.203 msaitoh {
10047 1.281 msaitoh uint32_t ext_ctrl;
10048 1.281 msaitoh int timeout = 200;
10049 1.203 msaitoh
10050 1.281 msaitoh for (timeout = 0; timeout < 200; timeout++) {
10051 1.281 msaitoh ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
10052 1.329 msaitoh ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
10053 1.281 msaitoh CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
10054 1.203 msaitoh
10055 1.281 msaitoh ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
10056 1.329 msaitoh if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
10057 1.281 msaitoh return 0;
10058 1.281 msaitoh delay(5000);
10059 1.281 msaitoh }
10060 1.281 msaitoh printf("%s: failed to get swfwhw semaphore ext_ctrl 0x%x\n",
10061 1.281 msaitoh device_xname(sc->sc_dev), ext_ctrl);
10062 1.281 msaitoh return 1;
10063 1.281 msaitoh }
10064 1.203 msaitoh
10065 1.281 msaitoh static void
10066 1.281 msaitoh wm_put_swfwhw_semaphore(struct wm_softc *sc)
10067 1.281 msaitoh {
10068 1.281 msaitoh uint32_t ext_ctrl;
10069 1.281 msaitoh ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
10070 1.329 msaitoh ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
10071 1.281 msaitoh CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
10072 1.203 msaitoh }
10073 1.203 msaitoh
10074 1.203 msaitoh static int
10075 1.281 msaitoh wm_get_hw_semaphore_82573(struct wm_softc *sc)
10076 1.189 msaitoh {
10077 1.281 msaitoh int i = 0;
10078 1.189 msaitoh uint32_t reg;
10079 1.189 msaitoh
10080 1.281 msaitoh reg = CSR_READ(sc, WMREG_EXTCNFCTR);
10081 1.281 msaitoh do {
10082 1.281 msaitoh CSR_WRITE(sc, WMREG_EXTCNFCTR,
10083 1.281 msaitoh reg | EXTCNFCTR_MDIO_SW_OWNERSHIP);
10084 1.281 msaitoh reg = CSR_READ(sc, WMREG_EXTCNFCTR);
10085 1.281 msaitoh if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0)
10086 1.281 msaitoh break;
10087 1.281 msaitoh delay(2*1000);
10088 1.281 msaitoh i++;
10089 1.281 msaitoh } while (i < WM_MDIO_OWNERSHIP_TIMEOUT);
10090 1.281 msaitoh
10091 1.281 msaitoh if (i == WM_MDIO_OWNERSHIP_TIMEOUT) {
10092 1.281 msaitoh wm_put_hw_semaphore_82573(sc);
10093 1.281 msaitoh log(LOG_ERR, "%s: Driver can't access the PHY\n",
10094 1.281 msaitoh device_xname(sc->sc_dev));
10095 1.281 msaitoh return -1;
10096 1.189 msaitoh }
10097 1.189 msaitoh
10098 1.189 msaitoh return 0;
10099 1.189 msaitoh }
10100 1.189 msaitoh
10101 1.169 msaitoh static void
10102 1.281 msaitoh wm_put_hw_semaphore_82573(struct wm_softc *sc)
10103 1.169 msaitoh {
10104 1.169 msaitoh uint32_t reg;
10105 1.169 msaitoh
10106 1.281 msaitoh reg = CSR_READ(sc, WMREG_EXTCNFCTR);
10107 1.281 msaitoh reg &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
10108 1.281 msaitoh CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
10109 1.281 msaitoh }
10110 1.281 msaitoh
10111 1.281 msaitoh /*
10112 1.281 msaitoh * Management mode and power management related subroutines.
10113 1.281 msaitoh * BMC, AMT, suspend/resume and EEE.
10114 1.281 msaitoh */
10115 1.281 msaitoh
10116 1.281 msaitoh static int
10117 1.281 msaitoh wm_check_mng_mode(struct wm_softc *sc)
10118 1.281 msaitoh {
10119 1.281 msaitoh int rv;
10120 1.281 msaitoh
10121 1.169 msaitoh switch (sc->sc_type) {
10122 1.169 msaitoh case WM_T_ICH8:
10123 1.169 msaitoh case WM_T_ICH9:
10124 1.169 msaitoh case WM_T_ICH10:
10125 1.190 msaitoh case WM_T_PCH:
10126 1.221 msaitoh case WM_T_PCH2:
10127 1.249 msaitoh case WM_T_PCH_LPT:
10128 1.281 msaitoh rv = wm_check_mng_mode_ich8lan(sc);
10129 1.281 msaitoh break;
10130 1.281 msaitoh case WM_T_82574:
10131 1.281 msaitoh case WM_T_82583:
10132 1.281 msaitoh rv = wm_check_mng_mode_82574(sc);
10133 1.281 msaitoh break;
10134 1.281 msaitoh case WM_T_82571:
10135 1.281 msaitoh case WM_T_82572:
10136 1.281 msaitoh case WM_T_82573:
10137 1.281 msaitoh case WM_T_80003:
10138 1.281 msaitoh rv = wm_check_mng_mode_generic(sc);
10139 1.169 msaitoh break;
10140 1.169 msaitoh default:
10141 1.281 msaitoh /* noting to do */
10142 1.281 msaitoh rv = 0;
10143 1.169 msaitoh break;
10144 1.169 msaitoh }
10145 1.281 msaitoh
10146 1.281 msaitoh return rv;
10147 1.169 msaitoh }
10148 1.173 msaitoh
10149 1.281 msaitoh static int
10150 1.281 msaitoh wm_check_mng_mode_ich8lan(struct wm_softc *sc)
10151 1.203 msaitoh {
10152 1.281 msaitoh uint32_t fwsm;
10153 1.281 msaitoh
10154 1.281 msaitoh fwsm = CSR_READ(sc, WMREG_FWSM);
10155 1.203 msaitoh
10156 1.281 msaitoh if ((fwsm & FWSM_MODE_MASK) == (MNG_ICH_IAMT_MODE << FWSM_MODE_SHIFT))
10157 1.281 msaitoh return 1;
10158 1.246 christos
10159 1.281 msaitoh return 0;
10160 1.203 msaitoh }
10161 1.203 msaitoh
10162 1.173 msaitoh static int
10163 1.281 msaitoh wm_check_mng_mode_82574(struct wm_softc *sc)
10164 1.173 msaitoh {
10165 1.281 msaitoh uint16_t data;
10166 1.173 msaitoh
10167 1.293 msaitoh wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
10168 1.279 msaitoh
10169 1.293 msaitoh if ((data & NVM_CFG2_MNGM_MASK) != 0)
10170 1.281 msaitoh return 1;
10171 1.173 msaitoh
10172 1.173 msaitoh return 0;
10173 1.173 msaitoh }
10174 1.192 msaitoh
10175 1.281 msaitoh static int
10176 1.281 msaitoh wm_check_mng_mode_generic(struct wm_softc *sc)
10177 1.202 msaitoh {
10178 1.281 msaitoh uint32_t fwsm;
10179 1.202 msaitoh
10180 1.281 msaitoh fwsm = CSR_READ(sc, WMREG_FWSM);
10181 1.202 msaitoh
10182 1.281 msaitoh if ((fwsm & FWSM_MODE_MASK) == (MNG_IAMT_MODE << FWSM_MODE_SHIFT))
10183 1.281 msaitoh return 1;
10184 1.202 msaitoh
10185 1.281 msaitoh return 0;
10186 1.202 msaitoh }
10187 1.202 msaitoh
10188 1.281 msaitoh static int
10189 1.281 msaitoh wm_enable_mng_pass_thru(struct wm_softc *sc)
10190 1.202 msaitoh {
10191 1.281 msaitoh uint32_t manc, fwsm, factps;
10192 1.202 msaitoh
10193 1.281 msaitoh if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) == 0)
10194 1.281 msaitoh return 0;
10195 1.202 msaitoh
10196 1.281 msaitoh manc = CSR_READ(sc, WMREG_MANC);
10197 1.203 msaitoh
10198 1.281 msaitoh DPRINTF(WM_DEBUG_MANAGE, ("%s: MANC (%08x)\n",
10199 1.281 msaitoh device_xname(sc->sc_dev), manc));
10200 1.281 msaitoh if ((manc & MANC_RECV_TCO_EN) == 0)
10201 1.281 msaitoh return 0;
10202 1.203 msaitoh
10203 1.281 msaitoh if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) {
10204 1.281 msaitoh fwsm = CSR_READ(sc, WMREG_FWSM);
10205 1.281 msaitoh factps = CSR_READ(sc, WMREG_FACTPS);
10206 1.281 msaitoh if (((factps & FACTPS_MNGCG) == 0)
10207 1.281 msaitoh && ((fwsm & FWSM_MODE_MASK)
10208 1.281 msaitoh == (MNG_ICH_IAMT_MODE << FWSM_MODE_SHIFT)))
10209 1.281 msaitoh return 1;
10210 1.281 msaitoh } else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
10211 1.281 msaitoh uint16_t data;
10212 1.203 msaitoh
10213 1.281 msaitoh factps = CSR_READ(sc, WMREG_FACTPS);
10214 1.293 msaitoh wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
10215 1.281 msaitoh DPRINTF(WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n",
10216 1.281 msaitoh device_xname(sc->sc_dev), factps, data));
10217 1.281 msaitoh if (((factps & FACTPS_MNGCG) == 0)
10218 1.293 msaitoh && ((data & NVM_CFG2_MNGM_MASK)
10219 1.293 msaitoh == (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT)))
10220 1.281 msaitoh return 1;
10221 1.281 msaitoh } else if (((manc & MANC_SMBUS_EN) != 0)
10222 1.281 msaitoh && ((manc & MANC_ASF_EN) == 0))
10223 1.281 msaitoh return 1;
10224 1.203 msaitoh
10225 1.281 msaitoh return 0;
10226 1.203 msaitoh }
10227 1.203 msaitoh
10228 1.281 msaitoh static int
10229 1.281 msaitoh wm_check_reset_block(struct wm_softc *sc)
10230 1.192 msaitoh {
10231 1.281 msaitoh uint32_t reg;
10232 1.192 msaitoh
10233 1.281 msaitoh switch (sc->sc_type) {
10234 1.281 msaitoh case WM_T_ICH8:
10235 1.281 msaitoh case WM_T_ICH9:
10236 1.281 msaitoh case WM_T_ICH10:
10237 1.281 msaitoh case WM_T_PCH:
10238 1.281 msaitoh case WM_T_PCH2:
10239 1.281 msaitoh case WM_T_PCH_LPT:
10240 1.281 msaitoh reg = CSR_READ(sc, WMREG_FWSM);
10241 1.281 msaitoh if ((reg & FWSM_RSPCIPHY) != 0)
10242 1.281 msaitoh return 0;
10243 1.281 msaitoh else
10244 1.281 msaitoh return -1;
10245 1.281 msaitoh break;
10246 1.281 msaitoh case WM_T_82571:
10247 1.281 msaitoh case WM_T_82572:
10248 1.281 msaitoh case WM_T_82573:
10249 1.281 msaitoh case WM_T_82574:
10250 1.281 msaitoh case WM_T_82583:
10251 1.281 msaitoh case WM_T_80003:
10252 1.281 msaitoh reg = CSR_READ(sc, WMREG_MANC);
10253 1.281 msaitoh if ((reg & MANC_BLK_PHY_RST_ON_IDE) != 0)
10254 1.281 msaitoh return -1;
10255 1.281 msaitoh else
10256 1.281 msaitoh return 0;
10257 1.281 msaitoh break;
10258 1.281 msaitoh default:
10259 1.281 msaitoh /* no problem */
10260 1.281 msaitoh break;
10261 1.192 msaitoh }
10262 1.192 msaitoh
10263 1.281 msaitoh return 0;
10264 1.192 msaitoh }
10265 1.192 msaitoh
10266 1.192 msaitoh static void
10267 1.281 msaitoh wm_get_hw_control(struct wm_softc *sc)
10268 1.221 msaitoh {
10269 1.281 msaitoh uint32_t reg;
10270 1.221 msaitoh
10271 1.281 msaitoh switch (sc->sc_type) {
10272 1.281 msaitoh case WM_T_82573:
10273 1.281 msaitoh reg = CSR_READ(sc, WMREG_SWSM);
10274 1.281 msaitoh CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD);
10275 1.281 msaitoh break;
10276 1.281 msaitoh case WM_T_82571:
10277 1.281 msaitoh case WM_T_82572:
10278 1.281 msaitoh case WM_T_82574:
10279 1.281 msaitoh case WM_T_82583:
10280 1.281 msaitoh case WM_T_80003:
10281 1.281 msaitoh case WM_T_ICH8:
10282 1.281 msaitoh case WM_T_ICH9:
10283 1.281 msaitoh case WM_T_ICH10:
10284 1.281 msaitoh case WM_T_PCH:
10285 1.281 msaitoh case WM_T_PCH2:
10286 1.281 msaitoh case WM_T_PCH_LPT:
10287 1.281 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
10288 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);
10289 1.281 msaitoh break;
10290 1.281 msaitoh default:
10291 1.281 msaitoh break;
10292 1.281 msaitoh }
10293 1.221 msaitoh }
10294 1.221 msaitoh
10295 1.221 msaitoh static void
10296 1.281 msaitoh wm_release_hw_control(struct wm_softc *sc)
10297 1.192 msaitoh {
10298 1.281 msaitoh uint32_t reg;
10299 1.192 msaitoh
10300 1.281 msaitoh if ((sc->sc_flags & WM_F_HAS_MANAGE) == 0)
10301 1.281 msaitoh return;
10302 1.192 msaitoh
10303 1.281 msaitoh if (sc->sc_type == WM_T_82573) {
10304 1.281 msaitoh reg = CSR_READ(sc, WMREG_SWSM);
10305 1.281 msaitoh reg &= ~SWSM_DRV_LOAD;
10306 1.281 msaitoh CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_DRV_LOAD);
10307 1.192 msaitoh } else {
10308 1.281 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
10309 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg & ~CTRL_EXT_DRV_LOAD);
10310 1.192 msaitoh }
10311 1.192 msaitoh }
10312 1.192 msaitoh
10313 1.192 msaitoh static void
10314 1.281 msaitoh wm_gate_hw_phy_config_ich8lan(struct wm_softc *sc, int on)
10315 1.221 msaitoh {
10316 1.221 msaitoh uint32_t reg;
10317 1.221 msaitoh
10318 1.281 msaitoh reg = CSR_READ(sc, WMREG_EXTCNFCTR);
10319 1.221 msaitoh
10320 1.281 msaitoh if (on != 0)
10321 1.281 msaitoh reg |= EXTCNFCTR_GATE_PHY_CFG;
10322 1.192 msaitoh else
10323 1.281 msaitoh reg &= ~EXTCNFCTR_GATE_PHY_CFG;
10324 1.192 msaitoh
10325 1.281 msaitoh CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
10326 1.192 msaitoh }
10327 1.199 msaitoh
10328 1.199 msaitoh static void
10329 1.221 msaitoh wm_smbustopci(struct wm_softc *sc)
10330 1.221 msaitoh {
10331 1.221 msaitoh uint32_t fwsm;
10332 1.221 msaitoh
10333 1.221 msaitoh fwsm = CSR_READ(sc, WMREG_FWSM);
10334 1.221 msaitoh if (((fwsm & FWSM_FW_VALID) == 0)
10335 1.221 msaitoh && ((wm_check_reset_block(sc) == 0))) {
10336 1.221 msaitoh sc->sc_ctrl |= CTRL_LANPHYPC_OVERRIDE;
10337 1.221 msaitoh sc->sc_ctrl &= ~CTRL_LANPHYPC_VALUE;
10338 1.221 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
10339 1.266 msaitoh CSR_WRITE_FLUSH(sc);
10340 1.221 msaitoh delay(10);
10341 1.221 msaitoh sc->sc_ctrl &= ~CTRL_LANPHYPC_OVERRIDE;
10342 1.221 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
10343 1.266 msaitoh CSR_WRITE_FLUSH(sc);
10344 1.221 msaitoh delay(50*1000);
10345 1.221 msaitoh
10346 1.221 msaitoh /*
10347 1.221 msaitoh * Gate automatic PHY configuration by hardware on non-managed
10348 1.221 msaitoh * 82579
10349 1.221 msaitoh */
10350 1.221 msaitoh if (sc->sc_type == WM_T_PCH2)
10351 1.221 msaitoh wm_gate_hw_phy_config_ich8lan(sc, 1);
10352 1.221 msaitoh }
10353 1.221 msaitoh }
10354 1.221 msaitoh
10355 1.221 msaitoh static void
10356 1.203 msaitoh wm_init_manageability(struct wm_softc *sc)
10357 1.203 msaitoh {
10358 1.203 msaitoh
10359 1.203 msaitoh if (sc->sc_flags & WM_F_HAS_MANAGE) {
10360 1.203 msaitoh uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H);
10361 1.203 msaitoh uint32_t manc = CSR_READ(sc, WMREG_MANC);
10362 1.203 msaitoh
10363 1.281 msaitoh /* Disable hardware interception of ARP */
10364 1.203 msaitoh manc &= ~MANC_ARP_EN;
10365 1.203 msaitoh
10366 1.281 msaitoh /* Enable receiving management packets to the host */
10367 1.203 msaitoh if (sc->sc_type >= WM_T_82571) {
10368 1.203 msaitoh manc |= MANC_EN_MNG2HOST;
10369 1.203 msaitoh manc2h |= MANC2H_PORT_623| MANC2H_PORT_624;
10370 1.203 msaitoh CSR_WRITE(sc, WMREG_MANC2H, manc2h);
10371 1.203 msaitoh }
10372 1.203 msaitoh
10373 1.203 msaitoh CSR_WRITE(sc, WMREG_MANC, manc);
10374 1.203 msaitoh }
10375 1.203 msaitoh }
10376 1.203 msaitoh
10377 1.203 msaitoh static void
10378 1.203 msaitoh wm_release_manageability(struct wm_softc *sc)
10379 1.203 msaitoh {
10380 1.203 msaitoh
10381 1.203 msaitoh if (sc->sc_flags & WM_F_HAS_MANAGE) {
10382 1.203 msaitoh uint32_t manc = CSR_READ(sc, WMREG_MANC);
10383 1.203 msaitoh
10384 1.260 msaitoh manc |= MANC_ARP_EN;
10385 1.203 msaitoh if (sc->sc_type >= WM_T_82571)
10386 1.203 msaitoh manc &= ~MANC_EN_MNG2HOST;
10387 1.203 msaitoh
10388 1.203 msaitoh CSR_WRITE(sc, WMREG_MANC, manc);
10389 1.203 msaitoh }
10390 1.203 msaitoh }
10391 1.203 msaitoh
10392 1.203 msaitoh static void
10393 1.203 msaitoh wm_get_wakeup(struct wm_softc *sc)
10394 1.203 msaitoh {
10395 1.203 msaitoh
10396 1.203 msaitoh /* 0: HAS_AMT, ARC_SUBSYS_VALID, ASF_FIRMWARE_PRES */
10397 1.203 msaitoh switch (sc->sc_type) {
10398 1.203 msaitoh case WM_T_82573:
10399 1.203 msaitoh case WM_T_82583:
10400 1.203 msaitoh sc->sc_flags |= WM_F_HAS_AMT;
10401 1.203 msaitoh /* FALLTHROUGH */
10402 1.246 christos case WM_T_80003:
10403 1.203 msaitoh case WM_T_82541:
10404 1.203 msaitoh case WM_T_82547:
10405 1.203 msaitoh case WM_T_82571:
10406 1.203 msaitoh case WM_T_82572:
10407 1.203 msaitoh case WM_T_82574:
10408 1.203 msaitoh case WM_T_82575:
10409 1.203 msaitoh case WM_T_82576:
10410 1.208 msaitoh case WM_T_82580:
10411 1.228 msaitoh case WM_T_I350:
10412 1.265 msaitoh case WM_T_I354:
10413 1.203 msaitoh if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE_MASK) != 0)
10414 1.203 msaitoh sc->sc_flags |= WM_F_ARC_SUBSYS_VALID;
10415 1.203 msaitoh sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
10416 1.203 msaitoh break;
10417 1.203 msaitoh case WM_T_ICH8:
10418 1.203 msaitoh case WM_T_ICH9:
10419 1.203 msaitoh case WM_T_ICH10:
10420 1.203 msaitoh case WM_T_PCH:
10421 1.221 msaitoh case WM_T_PCH2:
10422 1.249 msaitoh case WM_T_PCH_LPT:
10423 1.203 msaitoh sc->sc_flags |= WM_F_HAS_AMT;
10424 1.203 msaitoh sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
10425 1.203 msaitoh break;
10426 1.203 msaitoh default:
10427 1.203 msaitoh break;
10428 1.203 msaitoh }
10429 1.203 msaitoh
10430 1.203 msaitoh /* 1: HAS_MANAGE */
10431 1.203 msaitoh if (wm_enable_mng_pass_thru(sc) != 0)
10432 1.203 msaitoh sc->sc_flags |= WM_F_HAS_MANAGE;
10433 1.203 msaitoh
10434 1.203 msaitoh #ifdef WM_DEBUG
10435 1.203 msaitoh printf("\n");
10436 1.203 msaitoh if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
10437 1.203 msaitoh printf("HAS_AMT,");
10438 1.203 msaitoh if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0)
10439 1.203 msaitoh printf("ARC_SUBSYS_VALID,");
10440 1.203 msaitoh if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) != 0)
10441 1.203 msaitoh printf("ASF_FIRMWARE_PRES,");
10442 1.203 msaitoh if ((sc->sc_flags & WM_F_HAS_MANAGE) != 0)
10443 1.203 msaitoh printf("HAS_MANAGE,");
10444 1.203 msaitoh printf("\n");
10445 1.203 msaitoh #endif
10446 1.203 msaitoh /*
10447 1.203 msaitoh * Note that the WOL flags is set after the resetting of the eeprom
10448 1.203 msaitoh * stuff
10449 1.203 msaitoh */
10450 1.203 msaitoh }
10451 1.203 msaitoh
10452 1.203 msaitoh #ifdef WM_WOL
10453 1.203 msaitoh /* WOL in the newer chipset interfaces (pchlan) */
10454 1.203 msaitoh static void
10455 1.203 msaitoh wm_enable_phy_wakeup(struct wm_softc *sc)
10456 1.203 msaitoh {
10457 1.203 msaitoh #if 0
10458 1.203 msaitoh uint16_t preg;
10459 1.203 msaitoh
10460 1.203 msaitoh /* Copy MAC RARs to PHY RARs */
10461 1.203 msaitoh
10462 1.203 msaitoh /* Copy MAC MTA to PHY MTA */
10463 1.203 msaitoh
10464 1.281 msaitoh /* Configure PHY Rx Control register */
10465 1.281 msaitoh
10466 1.281 msaitoh /* Enable PHY wakeup in MAC register */
10467 1.281 msaitoh
10468 1.281 msaitoh /* Configure and enable PHY wakeup in PHY registers */
10469 1.281 msaitoh
10470 1.281 msaitoh /* Activate PHY wakeup */
10471 1.281 msaitoh
10472 1.281 msaitoh /* XXX */
10473 1.281 msaitoh #endif
10474 1.281 msaitoh }
10475 1.281 msaitoh
10476 1.281 msaitoh /* Power down workaround on D3 */
10477 1.281 msaitoh static void
10478 1.281 msaitoh wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *sc)
10479 1.281 msaitoh {
10480 1.281 msaitoh uint32_t reg;
10481 1.281 msaitoh int i;
10482 1.281 msaitoh
10483 1.281 msaitoh for (i = 0; i < 2; i++) {
10484 1.281 msaitoh /* Disable link */
10485 1.281 msaitoh reg = CSR_READ(sc, WMREG_PHY_CTRL);
10486 1.281 msaitoh reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
10487 1.281 msaitoh CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
10488 1.281 msaitoh
10489 1.281 msaitoh /*
10490 1.281 msaitoh * Call gig speed drop workaround on Gig disable before
10491 1.281 msaitoh * accessing any PHY registers
10492 1.281 msaitoh */
10493 1.281 msaitoh if (sc->sc_type == WM_T_ICH8)
10494 1.281 msaitoh wm_gig_downshift_workaround_ich8lan(sc);
10495 1.203 msaitoh
10496 1.281 msaitoh /* Write VR power-down enable */
10497 1.281 msaitoh reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL);
10498 1.281 msaitoh reg &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
10499 1.281 msaitoh reg |= IGP3_VR_CTRL_MODE_SHUTDOWN;
10500 1.281 msaitoh sc->sc_mii.mii_writereg(sc->sc_dev, 1, IGP3_VR_CTRL, reg);
10501 1.203 msaitoh
10502 1.281 msaitoh /* Read it back and test */
10503 1.281 msaitoh reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL);
10504 1.281 msaitoh reg &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
10505 1.281 msaitoh if ((reg == IGP3_VR_CTRL_MODE_SHUTDOWN) || (i != 0))
10506 1.281 msaitoh break;
10507 1.203 msaitoh
10508 1.281 msaitoh /* Issue PHY reset and repeat at most one more time */
10509 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
10510 1.281 msaitoh }
10511 1.203 msaitoh }
10512 1.203 msaitoh
10513 1.203 msaitoh static void
10514 1.203 msaitoh wm_enable_wakeup(struct wm_softc *sc)
10515 1.203 msaitoh {
10516 1.203 msaitoh uint32_t reg, pmreg;
10517 1.203 msaitoh pcireg_t pmode;
10518 1.203 msaitoh
10519 1.203 msaitoh if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT,
10520 1.203 msaitoh &pmreg, NULL) == 0)
10521 1.203 msaitoh return;
10522 1.203 msaitoh
10523 1.203 msaitoh /* Advertise the wakeup capability */
10524 1.203 msaitoh CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_SWDPIN(2)
10525 1.203 msaitoh | CTRL_SWDPIN(3));
10526 1.203 msaitoh CSR_WRITE(sc, WMREG_WUC, WUC_APME);
10527 1.203 msaitoh
10528 1.203 msaitoh /* ICH workaround */
10529 1.203 msaitoh switch (sc->sc_type) {
10530 1.203 msaitoh case WM_T_ICH8:
10531 1.203 msaitoh case WM_T_ICH9:
10532 1.203 msaitoh case WM_T_ICH10:
10533 1.203 msaitoh case WM_T_PCH:
10534 1.221 msaitoh case WM_T_PCH2:
10535 1.249 msaitoh case WM_T_PCH_LPT:
10536 1.203 msaitoh /* Disable gig during WOL */
10537 1.203 msaitoh reg = CSR_READ(sc, WMREG_PHY_CTRL);
10538 1.203 msaitoh reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS;
10539 1.203 msaitoh CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
10540 1.203 msaitoh if (sc->sc_type == WM_T_PCH)
10541 1.203 msaitoh wm_gmii_reset(sc);
10542 1.203 msaitoh
10543 1.203 msaitoh /* Power down workaround */
10544 1.203 msaitoh if (sc->sc_phytype == WMPHY_82577) {
10545 1.203 msaitoh struct mii_softc *child;
10546 1.203 msaitoh
10547 1.203 msaitoh /* Assume that the PHY is copper */
10548 1.203 msaitoh child = LIST_FIRST(&sc->sc_mii.mii_phys);
10549 1.203 msaitoh if (child->mii_mpd_rev <= 2)
10550 1.203 msaitoh sc->sc_mii.mii_writereg(sc->sc_dev, 1,
10551 1.203 msaitoh (768 << 5) | 25, 0x0444); /* magic num */
10552 1.203 msaitoh }
10553 1.203 msaitoh break;
10554 1.203 msaitoh default:
10555 1.203 msaitoh break;
10556 1.203 msaitoh }
10557 1.203 msaitoh
10558 1.203 msaitoh /* Keep the laser running on fiber adapters */
10559 1.311 msaitoh if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
10560 1.311 msaitoh || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) {
10561 1.203 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
10562 1.203 msaitoh reg |= CTRL_EXT_SWDPIN(3);
10563 1.203 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
10564 1.203 msaitoh }
10565 1.203 msaitoh
10566 1.203 msaitoh reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG;
10567 1.203 msaitoh #if 0 /* for the multicast packet */
10568 1.203 msaitoh reg |= WUFC_MC;
10569 1.203 msaitoh CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE);
10570 1.203 msaitoh #endif
10571 1.203 msaitoh
10572 1.203 msaitoh if (sc->sc_type == WM_T_PCH) {
10573 1.203 msaitoh wm_enable_phy_wakeup(sc);
10574 1.203 msaitoh } else {
10575 1.203 msaitoh CSR_WRITE(sc, WMREG_WUC, WUC_PME_EN);
10576 1.203 msaitoh CSR_WRITE(sc, WMREG_WUFC, reg);
10577 1.203 msaitoh }
10578 1.203 msaitoh
10579 1.203 msaitoh if (((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
10580 1.221 msaitoh || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
10581 1.221 msaitoh || (sc->sc_type == WM_T_PCH2))
10582 1.203 msaitoh && (sc->sc_phytype == WMPHY_IGP_3))
10583 1.203 msaitoh wm_igp3_phy_powerdown_workaround_ich8lan(sc);
10584 1.203 msaitoh
10585 1.203 msaitoh /* Request PME */
10586 1.203 msaitoh pmode = pci_conf_read(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR);
10587 1.203 msaitoh #if 0
10588 1.203 msaitoh /* Disable WOL */
10589 1.203 msaitoh pmode &= ~(PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN);
10590 1.203 msaitoh #else
10591 1.203 msaitoh /* For WOL */
10592 1.203 msaitoh pmode |= PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN;
10593 1.203 msaitoh #endif
10594 1.203 msaitoh pci_conf_write(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR, pmode);
10595 1.203 msaitoh }
10596 1.203 msaitoh #endif /* WM_WOL */
10597 1.203 msaitoh
10598 1.281 msaitoh /* EEE */
10599 1.228 msaitoh
10600 1.228 msaitoh static void
10601 1.281 msaitoh wm_set_eee_i350(struct wm_softc *sc)
10602 1.228 msaitoh {
10603 1.228 msaitoh uint32_t ipcnfg, eeer;
10604 1.228 msaitoh
10605 1.228 msaitoh ipcnfg = CSR_READ(sc, WMREG_IPCNFG);
10606 1.228 msaitoh eeer = CSR_READ(sc, WMREG_EEER);
10607 1.228 msaitoh
10608 1.228 msaitoh if ((sc->sc_flags & WM_F_EEE) != 0) {
10609 1.228 msaitoh ipcnfg |= (IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN);
10610 1.228 msaitoh eeer |= (EEER_TX_LPI_EN | EEER_RX_LPI_EN
10611 1.228 msaitoh | EEER_LPI_FC);
10612 1.228 msaitoh } else {
10613 1.228 msaitoh ipcnfg &= ~(IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN);
10614 1.322 msaitoh ipcnfg &= ~IPCNFG_10BASE_TE;
10615 1.228 msaitoh eeer &= ~(EEER_TX_LPI_EN | EEER_RX_LPI_EN
10616 1.228 msaitoh | EEER_LPI_FC);
10617 1.228 msaitoh }
10618 1.228 msaitoh
10619 1.228 msaitoh CSR_WRITE(sc, WMREG_IPCNFG, ipcnfg);
10620 1.228 msaitoh CSR_WRITE(sc, WMREG_EEER, eeer);
10621 1.228 msaitoh CSR_READ(sc, WMREG_IPCNFG); /* XXX flush? */
10622 1.228 msaitoh CSR_READ(sc, WMREG_EEER); /* XXX flush? */
10623 1.228 msaitoh }
10624 1.281 msaitoh
10625 1.281 msaitoh /*
10626 1.281 msaitoh * Workarounds (mainly PHY related).
10627 1.281 msaitoh * Basically, PHY's workarounds are in the PHY drivers.
10628 1.281 msaitoh */
10629 1.281 msaitoh
10630 1.281 msaitoh /* Work-around for 82566 Kumeran PCS lock loss */
10631 1.281 msaitoh static void
10632 1.281 msaitoh wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *sc)
10633 1.281 msaitoh {
10634 1.281 msaitoh int miistatus, active, i;
10635 1.281 msaitoh int reg;
10636 1.281 msaitoh
10637 1.281 msaitoh miistatus = sc->sc_mii.mii_media_status;
10638 1.281 msaitoh
10639 1.281 msaitoh /* If the link is not up, do nothing */
10640 1.281 msaitoh if ((miistatus & IFM_ACTIVE) != 0)
10641 1.281 msaitoh return;
10642 1.281 msaitoh
10643 1.281 msaitoh active = sc->sc_mii.mii_media_active;
10644 1.281 msaitoh
10645 1.281 msaitoh /* Nothing to do if the link is other than 1Gbps */
10646 1.281 msaitoh if (IFM_SUBTYPE(active) != IFM_1000_T)
10647 1.281 msaitoh return;
10648 1.281 msaitoh
10649 1.281 msaitoh for (i = 0; i < 10; i++) {
10650 1.281 msaitoh /* read twice */
10651 1.281 msaitoh reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
10652 1.281 msaitoh reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
10653 1.281 msaitoh if ((reg & IGP3_KMRN_DIAG_PCS_LOCK_LOSS) != 0)
10654 1.281 msaitoh goto out; /* GOOD! */
10655 1.281 msaitoh
10656 1.281 msaitoh /* Reset the PHY */
10657 1.281 msaitoh wm_gmii_reset(sc);
10658 1.281 msaitoh delay(5*1000);
10659 1.281 msaitoh }
10660 1.281 msaitoh
10661 1.281 msaitoh /* Disable GigE link negotiation */
10662 1.281 msaitoh reg = CSR_READ(sc, WMREG_PHY_CTRL);
10663 1.281 msaitoh reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
10664 1.281 msaitoh CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
10665 1.281 msaitoh
10666 1.281 msaitoh /*
10667 1.281 msaitoh * Call gig speed drop workaround on Gig disable before accessing
10668 1.281 msaitoh * any PHY registers.
10669 1.281 msaitoh */
10670 1.281 msaitoh wm_gig_downshift_workaround_ich8lan(sc);
10671 1.281 msaitoh
10672 1.281 msaitoh out:
10673 1.281 msaitoh return;
10674 1.281 msaitoh }
10675 1.281 msaitoh
10676 1.281 msaitoh /* WOL from S5 stops working */
10677 1.281 msaitoh static void
10678 1.281 msaitoh wm_gig_downshift_workaround_ich8lan(struct wm_softc *sc)
10679 1.281 msaitoh {
10680 1.281 msaitoh uint16_t kmrn_reg;
10681 1.281 msaitoh
10682 1.281 msaitoh /* Only for igp3 */
10683 1.281 msaitoh if (sc->sc_phytype == WMPHY_IGP_3) {
10684 1.281 msaitoh kmrn_reg = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_DIAG);
10685 1.281 msaitoh kmrn_reg |= KUMCTRLSTA_DIAG_NELPBK;
10686 1.281 msaitoh wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg);
10687 1.281 msaitoh kmrn_reg &= ~KUMCTRLSTA_DIAG_NELPBK;
10688 1.281 msaitoh wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg);
10689 1.281 msaitoh }
10690 1.281 msaitoh }
10691 1.281 msaitoh
10692 1.281 msaitoh /*
10693 1.281 msaitoh * Workaround for pch's PHYs
10694 1.281 msaitoh * XXX should be moved to new PHY driver?
10695 1.281 msaitoh */
10696 1.281 msaitoh static void
10697 1.281 msaitoh wm_hv_phy_workaround_ich8lan(struct wm_softc *sc)
10698 1.281 msaitoh {
10699 1.281 msaitoh if (sc->sc_phytype == WMPHY_82577)
10700 1.281 msaitoh wm_set_mdio_slow_mode_hv(sc);
10701 1.281 msaitoh
10702 1.281 msaitoh /* (PCH rev.2) && (82577 && (phy rev 2 or 3)) */
10703 1.281 msaitoh
10704 1.281 msaitoh /* (82577 && (phy rev 1 or 2)) || (82578 & phy rev 1)*/
10705 1.281 msaitoh
10706 1.281 msaitoh /* 82578 */
10707 1.281 msaitoh if (sc->sc_phytype == WMPHY_82578) {
10708 1.281 msaitoh /* PCH rev. < 3 */
10709 1.281 msaitoh if (sc->sc_rev < 3) {
10710 1.281 msaitoh /* XXX 6 bit shift? Why? Is it page2? */
10711 1.281 msaitoh wm_gmii_hv_writereg(sc->sc_dev, 1, ((1 << 6) | 0x29),
10712 1.281 msaitoh 0x66c0);
10713 1.281 msaitoh wm_gmii_hv_writereg(sc->sc_dev, 1, ((1 << 6) | 0x1e),
10714 1.281 msaitoh 0xffff);
10715 1.281 msaitoh }
10716 1.281 msaitoh
10717 1.281 msaitoh /* XXX phy rev. < 2 */
10718 1.281 msaitoh }
10719 1.281 msaitoh
10720 1.281 msaitoh /* Select page 0 */
10721 1.281 msaitoh
10722 1.281 msaitoh /* XXX acquire semaphore */
10723 1.281 msaitoh wm_gmii_i82544_writereg(sc->sc_dev, 1, MII_IGPHY_PAGE_SELECT, 0);
10724 1.281 msaitoh /* XXX release semaphore */
10725 1.281 msaitoh
10726 1.281 msaitoh /*
10727 1.281 msaitoh * Configure the K1 Si workaround during phy reset assuming there is
10728 1.281 msaitoh * link so that it disables K1 if link is in 1Gbps.
10729 1.281 msaitoh */
10730 1.281 msaitoh wm_k1_gig_workaround_hv(sc, 1);
10731 1.281 msaitoh }
10732 1.281 msaitoh
10733 1.281 msaitoh static void
10734 1.281 msaitoh wm_lv_phy_workaround_ich8lan(struct wm_softc *sc)
10735 1.281 msaitoh {
10736 1.281 msaitoh
10737 1.281 msaitoh wm_set_mdio_slow_mode_hv(sc);
10738 1.281 msaitoh }
10739 1.281 msaitoh
10740 1.281 msaitoh static void
10741 1.281 msaitoh wm_k1_gig_workaround_hv(struct wm_softc *sc, int link)
10742 1.281 msaitoh {
10743 1.281 msaitoh int k1_enable = sc->sc_nvm_k1_enabled;
10744 1.281 msaitoh
10745 1.281 msaitoh /* XXX acquire semaphore */
10746 1.281 msaitoh
10747 1.281 msaitoh if (link) {
10748 1.281 msaitoh k1_enable = 0;
10749 1.281 msaitoh
10750 1.281 msaitoh /* Link stall fix for link up */
10751 1.281 msaitoh wm_gmii_hv_writereg(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x0100);
10752 1.281 msaitoh } else {
10753 1.281 msaitoh /* Link stall fix for link down */
10754 1.281 msaitoh wm_gmii_hv_writereg(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x4100);
10755 1.281 msaitoh }
10756 1.281 msaitoh
10757 1.281 msaitoh wm_configure_k1_ich8lan(sc, k1_enable);
10758 1.281 msaitoh
10759 1.281 msaitoh /* XXX release semaphore */
10760 1.281 msaitoh }
10761 1.281 msaitoh
10762 1.281 msaitoh static void
10763 1.281 msaitoh wm_set_mdio_slow_mode_hv(struct wm_softc *sc)
10764 1.281 msaitoh {
10765 1.281 msaitoh uint32_t reg;
10766 1.281 msaitoh
10767 1.281 msaitoh reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL);
10768 1.281 msaitoh wm_gmii_hv_writereg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL,
10769 1.281 msaitoh reg | HV_KMRN_MDIO_SLOW);
10770 1.281 msaitoh }
10771 1.281 msaitoh
10772 1.281 msaitoh static void
10773 1.281 msaitoh wm_configure_k1_ich8lan(struct wm_softc *sc, int k1_enable)
10774 1.281 msaitoh {
10775 1.281 msaitoh uint32_t ctrl, ctrl_ext, tmp;
10776 1.281 msaitoh uint16_t kmrn_reg;
10777 1.281 msaitoh
10778 1.281 msaitoh kmrn_reg = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_K1_CONFIG);
10779 1.281 msaitoh
10780 1.281 msaitoh if (k1_enable)
10781 1.281 msaitoh kmrn_reg |= KUMCTRLSTA_K1_ENABLE;
10782 1.281 msaitoh else
10783 1.281 msaitoh kmrn_reg &= ~KUMCTRLSTA_K1_ENABLE;
10784 1.281 msaitoh
10785 1.281 msaitoh wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, kmrn_reg);
10786 1.281 msaitoh
10787 1.281 msaitoh delay(20);
10788 1.281 msaitoh
10789 1.281 msaitoh ctrl = CSR_READ(sc, WMREG_CTRL);
10790 1.281 msaitoh ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
10791 1.281 msaitoh
10792 1.281 msaitoh tmp = ctrl & ~(CTRL_SPEED_1000 | CTRL_SPEED_100);
10793 1.281 msaitoh tmp |= CTRL_FRCSPD;
10794 1.281 msaitoh
10795 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, tmp);
10796 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_SPD_BYPS);
10797 1.281 msaitoh CSR_WRITE_FLUSH(sc);
10798 1.281 msaitoh delay(20);
10799 1.281 msaitoh
10800 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL, ctrl);
10801 1.281 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
10802 1.281 msaitoh CSR_WRITE_FLUSH(sc);
10803 1.281 msaitoh delay(20);
10804 1.281 msaitoh }
10805 1.281 msaitoh
10806 1.281 msaitoh /* special case - for 82575 - need to do manual init ... */
10807 1.281 msaitoh static void
10808 1.281 msaitoh wm_reset_init_script_82575(struct wm_softc *sc)
10809 1.281 msaitoh {
10810 1.281 msaitoh /*
10811 1.281 msaitoh * remark: this is untested code - we have no board without EEPROM
10812 1.312 msaitoh * same setup as mentioned int the FreeBSD driver for the i82575
10813 1.281 msaitoh */
10814 1.281 msaitoh
10815 1.281 msaitoh /* SerDes configuration via SERDESCTRL */
10816 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x00, 0x0c);
10817 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x01, 0x78);
10818 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x1b, 0x23);
10819 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x23, 0x15);
10820 1.281 msaitoh
10821 1.281 msaitoh /* CCM configuration via CCMCTL register */
10822 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x14, 0x00);
10823 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x10, 0x00);
10824 1.281 msaitoh
10825 1.281 msaitoh /* PCIe lanes configuration */
10826 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x00, 0xec);
10827 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x61, 0xdf);
10828 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x34, 0x05);
10829 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x2f, 0x81);
10830 1.281 msaitoh
10831 1.281 msaitoh /* PCIe PLL Configuration */
10832 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x02, 0x47);
10833 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x14, 0x00);
10834 1.281 msaitoh wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x10, 0x00);
10835 1.281 msaitoh }
10836 1.325 msaitoh
10837 1.325 msaitoh static void
10838 1.325 msaitoh wm_reset_mdicnfg_82580(struct wm_softc *sc)
10839 1.325 msaitoh {
10840 1.325 msaitoh uint32_t reg;
10841 1.325 msaitoh uint16_t nvmword;
10842 1.325 msaitoh int rv;
10843 1.325 msaitoh
10844 1.325 msaitoh if ((sc->sc_flags & WM_F_SGMII) == 0)
10845 1.325 msaitoh return;
10846 1.325 msaitoh
10847 1.325 msaitoh rv = wm_nvm_read(sc, NVM_OFF_LAN_FUNC_82580(sc->sc_funcid)
10848 1.325 msaitoh + NVM_OFF_CFG3_PORTA, 1, &nvmword);
10849 1.325 msaitoh if (rv != 0) {
10850 1.325 msaitoh aprint_error_dev(sc->sc_dev, "%s: failed to read NVM\n",
10851 1.325 msaitoh __func__);
10852 1.325 msaitoh return;
10853 1.325 msaitoh }
10854 1.325 msaitoh
10855 1.325 msaitoh reg = CSR_READ(sc, WMREG_MDICNFG);
10856 1.325 msaitoh if (nvmword & NVM_CFG3_PORTA_EXT_MDIO)
10857 1.325 msaitoh reg |= MDICNFG_DEST;
10858 1.325 msaitoh if (nvmword & NVM_CFG3_PORTA_COM_MDIO)
10859 1.325 msaitoh reg |= MDICNFG_COM_MDIO;
10860 1.325 msaitoh CSR_WRITE(sc, WMREG_MDICNFG, reg);
10861 1.325 msaitoh }
10862 1.329 msaitoh
10863 1.329 msaitoh /*
10864 1.329 msaitoh * I210 Errata 25 and I211 Errata 10
10865 1.329 msaitoh * Slow System Clock.
10866 1.329 msaitoh */
10867 1.329 msaitoh static void
10868 1.329 msaitoh wm_pll_workaround_i210(struct wm_softc *sc)
10869 1.329 msaitoh {
10870 1.329 msaitoh uint32_t mdicnfg, wuc;
10871 1.329 msaitoh uint32_t reg;
10872 1.329 msaitoh pcireg_t pcireg;
10873 1.329 msaitoh uint32_t pmreg;
10874 1.329 msaitoh uint16_t nvmword, tmp_nvmword;
10875 1.329 msaitoh int phyval;
10876 1.329 msaitoh bool wa_done = false;
10877 1.329 msaitoh int i;
10878 1.329 msaitoh
10879 1.329 msaitoh /* Save WUC and MDICNFG registers */
10880 1.329 msaitoh wuc = CSR_READ(sc, WMREG_WUC);
10881 1.329 msaitoh mdicnfg = CSR_READ(sc, WMREG_MDICNFG);
10882 1.329 msaitoh
10883 1.329 msaitoh reg = mdicnfg & ~MDICNFG_DEST;
10884 1.329 msaitoh CSR_WRITE(sc, WMREG_MDICNFG, reg);
10885 1.329 msaitoh
10886 1.329 msaitoh if (wm_nvm_read(sc, INVM_AUTOLOAD, 1, &nvmword) != 0)
10887 1.329 msaitoh nvmword = INVM_DEFAULT_AL;
10888 1.329 msaitoh tmp_nvmword = nvmword | INVM_PLL_WO_VAL;
10889 1.329 msaitoh
10890 1.329 msaitoh /* Get Power Management cap offset */
10891 1.329 msaitoh if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT,
10892 1.329 msaitoh &pmreg, NULL) == 0)
10893 1.329 msaitoh return;
10894 1.329 msaitoh for (i = 0; i < WM_MAX_PLL_TRIES; i++) {
10895 1.329 msaitoh phyval = wm_gmii_gs40g_readreg(sc->sc_dev, 1,
10896 1.329 msaitoh GS40G_PHY_PLL_FREQ_PAGE | GS40G_PHY_PLL_FREQ_REG);
10897 1.332 msaitoh
10898 1.329 msaitoh if ((phyval & GS40G_PHY_PLL_UNCONF) != GS40G_PHY_PLL_UNCONF) {
10899 1.329 msaitoh break; /* OK */
10900 1.329 msaitoh }
10901 1.329 msaitoh
10902 1.329 msaitoh wa_done = true;
10903 1.329 msaitoh /* Directly reset the internal PHY */
10904 1.329 msaitoh reg = CSR_READ(sc, WMREG_CTRL);
10905 1.329 msaitoh CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);
10906 1.329 msaitoh
10907 1.329 msaitoh reg = CSR_READ(sc, WMREG_CTRL_EXT);
10908 1.329 msaitoh reg |= CTRL_EXT_PHYPDEN | CTRL_EXT_SDLPE;
10909 1.329 msaitoh CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
10910 1.329 msaitoh
10911 1.329 msaitoh CSR_WRITE(sc, WMREG_WUC, 0);
10912 1.329 msaitoh reg = (INVM_AUTOLOAD << 4) | (tmp_nvmword << 16);
10913 1.329 msaitoh CSR_WRITE(sc, WMREG_EEARBC_I210, reg);
10914 1.332 msaitoh
10915 1.329 msaitoh pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
10916 1.329 msaitoh pmreg + PCI_PMCSR);
10917 1.329 msaitoh pcireg |= PCI_PMCSR_STATE_D3;
10918 1.329 msaitoh pci_conf_write(sc->sc_pc, sc->sc_pcitag,
10919 1.329 msaitoh pmreg + PCI_PMCSR, pcireg);
10920 1.329 msaitoh delay(1000);
10921 1.329 msaitoh pcireg &= ~PCI_PMCSR_STATE_D3;
10922 1.329 msaitoh pci_conf_write(sc->sc_pc, sc->sc_pcitag,
10923 1.329 msaitoh pmreg + PCI_PMCSR, pcireg);
10924 1.329 msaitoh
10925 1.329 msaitoh reg = (INVM_AUTOLOAD << 4) | (nvmword << 16);
10926 1.329 msaitoh CSR_WRITE(sc, WMREG_EEARBC_I210, reg);
10927 1.332 msaitoh
10928 1.329 msaitoh /* Restore WUC register */
10929 1.329 msaitoh CSR_WRITE(sc, WMREG_WUC, wuc);
10930 1.329 msaitoh }
10931 1.332 msaitoh
10932 1.329 msaitoh /* Restore MDICNFG setting */
10933 1.329 msaitoh CSR_WRITE(sc, WMREG_MDICNFG, mdicnfg);
10934 1.329 msaitoh if (wa_done)
10935 1.329 msaitoh aprint_verbose_dev(sc->sc_dev, "I210 workaround done\n");
10936 1.329 msaitoh }
10937