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if_wm.c revision 1.522
      1  1.521   msaitoh /*	$NetBSD: if_wm.c,v 1.522 2017/07/13 08:04:56 msaitoh Exp $	*/
      2    1.1   thorpej 
      3    1.1   thorpej /*
      4   1.69   thorpej  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
      5    1.1   thorpej  * All rights reserved.
      6    1.1   thorpej  *
      7    1.1   thorpej  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8    1.1   thorpej  *
      9    1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     10    1.1   thorpej  * modification, are permitted provided that the following conditions
     11    1.1   thorpej  * are met:
     12    1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     13    1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     14    1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     15    1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     16    1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     17    1.1   thorpej  * 3. All advertising materials mentioning features or use of this software
     18    1.1   thorpej  *    must display the following acknowledgement:
     19    1.1   thorpej  *	This product includes software developed for the NetBSD Project by
     20    1.1   thorpej  *	Wasabi Systems, Inc.
     21    1.1   thorpej  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22    1.1   thorpej  *    or promote products derived from this software without specific prior
     23    1.1   thorpej  *    written permission.
     24    1.1   thorpej  *
     25    1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26    1.1   thorpej  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27    1.1   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28    1.1   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29    1.1   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30    1.1   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31    1.1   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32    1.1   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33    1.1   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34    1.1   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35    1.1   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     36    1.1   thorpej  */
     37    1.1   thorpej 
     38  1.139    bouyer /*******************************************************************************
     39  1.139    bouyer 
     40  1.246  christos   Copyright (c) 2001-2005, Intel Corporation
     41  1.139    bouyer   All rights reserved.
     42  1.246  christos 
     43  1.246  christos   Redistribution and use in source and binary forms, with or without
     44  1.139    bouyer   modification, are permitted provided that the following conditions are met:
     45  1.246  christos 
     46  1.246  christos    1. Redistributions of source code must retain the above copyright notice,
     47  1.139    bouyer       this list of conditions and the following disclaimer.
     48  1.246  christos 
     49  1.246  christos    2. Redistributions in binary form must reproduce the above copyright
     50  1.246  christos       notice, this list of conditions and the following disclaimer in the
     51  1.139    bouyer       documentation and/or other materials provided with the distribution.
     52  1.246  christos 
     53  1.246  christos    3. Neither the name of the Intel Corporation nor the names of its
     54  1.246  christos       contributors may be used to endorse or promote products derived from
     55  1.139    bouyer       this software without specific prior written permission.
     56  1.246  christos 
     57  1.139    bouyer   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     58  1.246  christos   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     59  1.246  christos   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     60  1.246  christos   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     61  1.246  christos   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     62  1.246  christos   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     63  1.246  christos   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     64  1.246  christos   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     65  1.246  christos   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     66  1.139    bouyer   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     67  1.139    bouyer   POSSIBILITY OF SUCH DAMAGE.
     68  1.139    bouyer 
     69  1.139    bouyer *******************************************************************************/
     70    1.1   thorpej /*
     71   1.11   thorpej  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
     72    1.1   thorpej  *
     73    1.1   thorpej  * TODO (in order of importance):
     74    1.1   thorpej  *
     75  1.288   msaitoh  *	- Check XXX'ed comments
     76  1.407  knakahar  *	- TX Multi queue improvement (refine queue selection logic)
     77  1.467  knakahar  *	- Split header buffer for newer descriptors
     78  1.286   msaitoh  *	- EEE (Energy Efficiency Ethernet)
     79  1.286   msaitoh  *	- Virtual Function
     80  1.286   msaitoh  *	- Set LED correctly (based on contents in EEPROM)
     81   1.61   thorpej  *	- Rework how parameters are loaded from the EEPROM.
     82  1.371   msaitoh  *	- Image Unique ID
     83    1.1   thorpej  */
     84   1.38     lukem 
     85   1.38     lukem #include <sys/cdefs.h>
     86  1.521   msaitoh __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.522 2017/07/13 08:04:56 msaitoh Exp $");
     87  1.309     ozaki 
     88  1.309     ozaki #ifdef _KERNEL_OPT
     89  1.309     ozaki #include "opt_net_mpsafe.h"
     90  1.494  knakahar #include "opt_if_wm.h"
     91  1.309     ozaki #endif
     92    1.1   thorpej 
     93    1.1   thorpej #include <sys/param.h>
     94    1.1   thorpej #include <sys/systm.h>
     95   1.96     perry #include <sys/callout.h>
     96    1.1   thorpej #include <sys/mbuf.h>
     97    1.1   thorpej #include <sys/malloc.h>
     98  1.356  knakahar #include <sys/kmem.h>
     99    1.1   thorpej #include <sys/kernel.h>
    100    1.1   thorpej #include <sys/socket.h>
    101    1.1   thorpej #include <sys/ioctl.h>
    102    1.1   thorpej #include <sys/errno.h>
    103    1.1   thorpej #include <sys/device.h>
    104    1.1   thorpej #include <sys/queue.h>
    105   1.84   thorpej #include <sys/syslog.h>
    106  1.346  knakahar #include <sys/interrupt.h>
    107  1.403  knakahar #include <sys/cpu.h>
    108  1.403  knakahar #include <sys/pcq.h>
    109    1.1   thorpej 
    110  1.315  riastrad #include <sys/rndsource.h>
    111   1.21    itojun 
    112    1.1   thorpej #include <net/if.h>
    113   1.96     perry #include <net/if_dl.h>
    114    1.1   thorpej #include <net/if_media.h>
    115    1.1   thorpej #include <net/if_ether.h>
    116    1.1   thorpej 
    117    1.1   thorpej #include <net/bpf.h>
    118    1.1   thorpej 
    119    1.1   thorpej #include <netinet/in.h>			/* XXX for struct ip */
    120    1.1   thorpej #include <netinet/in_systm.h>		/* XXX for struct ip */
    121    1.1   thorpej #include <netinet/ip.h>			/* XXX for struct ip */
    122  1.131      yamt #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
    123   1.13   thorpej #include <netinet/tcp.h>		/* XXX for struct tcphdr */
    124    1.1   thorpej 
    125  1.147        ad #include <sys/bus.h>
    126  1.147        ad #include <sys/intr.h>
    127    1.1   thorpej #include <machine/endian.h>
    128    1.1   thorpej 
    129    1.1   thorpej #include <dev/mii/mii.h>
    130    1.1   thorpej #include <dev/mii/miivar.h>
    131  1.202   msaitoh #include <dev/mii/miidevs.h>
    132    1.1   thorpej #include <dev/mii/mii_bitbang.h>
    133  1.127    bouyer #include <dev/mii/ikphyreg.h>
    134  1.191   msaitoh #include <dev/mii/igphyreg.h>
    135  1.202   msaitoh #include <dev/mii/igphyvar.h>
    136  1.192   msaitoh #include <dev/mii/inbmphyreg.h>
    137    1.1   thorpej 
    138    1.1   thorpej #include <dev/pci/pcireg.h>
    139    1.1   thorpej #include <dev/pci/pcivar.h>
    140    1.1   thorpej #include <dev/pci/pcidevs.h>
    141    1.1   thorpej 
    142    1.1   thorpej #include <dev/pci/if_wmreg.h>
    143  1.182   msaitoh #include <dev/pci/if_wmvar.h>
    144    1.1   thorpej 
    145    1.1   thorpej #ifdef WM_DEBUG
    146  1.420   msaitoh #define	WM_DEBUG_LINK		__BIT(0)
    147  1.420   msaitoh #define	WM_DEBUG_TX		__BIT(1)
    148  1.420   msaitoh #define	WM_DEBUG_RX		__BIT(2)
    149  1.420   msaitoh #define	WM_DEBUG_GMII		__BIT(3)
    150  1.420   msaitoh #define	WM_DEBUG_MANAGE		__BIT(4)
    151  1.420   msaitoh #define	WM_DEBUG_NVM		__BIT(5)
    152  1.420   msaitoh #define	WM_DEBUG_INIT		__BIT(6)
    153  1.420   msaitoh #define	WM_DEBUG_LOCK		__BIT(7)
    154  1.203   msaitoh int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
    155  1.420   msaitoh     | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT | WM_DEBUG_LOCK;
    156    1.1   thorpej 
    157    1.1   thorpej #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
    158    1.1   thorpej #else
    159    1.1   thorpej #define	DPRINTF(x, y)	/* nothing */
    160    1.1   thorpej #endif /* WM_DEBUG */
    161    1.1   thorpej 
    162  1.272     ozaki #ifdef NET_MPSAFE
    163  1.272     ozaki #define WM_MPSAFE	1
    164  1.492  knakahar #define CALLOUT_FLAGS	CALLOUT_MPSAFE
    165  1.492  knakahar #else
    166  1.492  knakahar #define CALLOUT_FLAGS	0
    167  1.272     ozaki #endif
    168  1.272     ozaki 
    169  1.335   msaitoh /*
    170  1.364  knakahar  * This device driver's max interrupt numbers.
    171  1.335   msaitoh  */
    172  1.405  knakahar #define WM_MAX_NQUEUEINTR	16
    173  1.405  knakahar #define WM_MAX_NINTR		(WM_MAX_NQUEUEINTR + 1)
    174  1.335   msaitoh 
    175  1.508  knakahar #ifndef WM_DISABLE_MSI
    176  1.508  knakahar #define	WM_DISABLE_MSI 0
    177  1.508  knakahar #endif
    178  1.508  knakahar #ifndef WM_DISABLE_MSIX
    179  1.508  knakahar #define	WM_DISABLE_MSIX 0
    180  1.508  knakahar #endif
    181  1.508  knakahar 
    182  1.508  knakahar int wm_disable_msi = WM_DISABLE_MSI;
    183  1.508  knakahar int wm_disable_msix = WM_DISABLE_MSIX;
    184  1.508  knakahar 
    185    1.1   thorpej /*
    186    1.2   thorpej  * Transmit descriptor list size.  Due to errata, we can only have
    187   1.75   thorpej  * 256 hardware descriptors in the ring on < 82544, but we use 4096
    188   1.75   thorpej  * on >= 82544.  We tell the upper layers that they can queue a lot
    189   1.75   thorpej  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
    190   1.75   thorpej  * of them at a time.
    191   1.75   thorpej  *
    192   1.75   thorpej  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
    193   1.75   thorpej  * chains containing many small mbufs have been observed in zero-copy
    194   1.75   thorpej  * situations with jumbo frames.
    195    1.1   thorpej  */
    196   1.75   thorpej #define	WM_NTXSEGS		256
    197    1.2   thorpej #define	WM_IFQUEUELEN		256
    198   1.74      tron #define	WM_TXQUEUELEN_MAX	64
    199   1.74      tron #define	WM_TXQUEUELEN_MAX_82547	16
    200  1.356  knakahar #define	WM_TXQUEUELEN(txq)	((txq)->txq_num)
    201  1.356  knakahar #define	WM_TXQUEUELEN_MASK(txq)	(WM_TXQUEUELEN(txq) - 1)
    202  1.356  knakahar #define	WM_TXQUEUE_GC(txq)	(WM_TXQUEUELEN(txq) / 8)
    203   1.75   thorpej #define	WM_NTXDESC_82542	256
    204   1.75   thorpej #define	WM_NTXDESC_82544	4096
    205  1.356  knakahar #define	WM_NTXDESC(txq)		((txq)->txq_ndesc)
    206  1.356  knakahar #define	WM_NTXDESC_MASK(txq)	(WM_NTXDESC(txq) - 1)
    207  1.398  knakahar #define	WM_TXDESCS_SIZE(txq)	(WM_NTXDESC(txq) * (txq)->txq_descsize)
    208  1.356  knakahar #define	WM_NEXTTX(txq, x)	(((x) + 1) & WM_NTXDESC_MASK(txq))
    209  1.356  knakahar #define	WM_NEXTTXS(txq, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(txq))
    210    1.1   thorpej 
    211  1.269       tls #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
    212   1.82   thorpej 
    213  1.403  knakahar #define	WM_TXINTERQSIZE		256
    214  1.403  knakahar 
    215    1.1   thorpej /*
    216    1.1   thorpej  * Receive descriptor list size.  We have one Rx buffer for normal
    217    1.1   thorpej  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
    218   1.10   thorpej  * packet.  We allocate 256 receive descriptors, each with a 2k
    219   1.10   thorpej  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
    220    1.1   thorpej  */
    221   1.10   thorpej #define	WM_NRXDESC		256
    222    1.1   thorpej #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
    223    1.1   thorpej #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
    224    1.1   thorpej #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
    225    1.1   thorpej 
    226  1.494  knakahar #ifndef WM_RX_PROCESS_LIMIT_DEFAULT
    227  1.493  knakahar #define	WM_RX_PROCESS_LIMIT_DEFAULT		100U
    228  1.494  knakahar #endif
    229  1.494  knakahar #ifndef WM_RX_INTR_PROCESS_LIMIT_DEFAULT
    230  1.493  knakahar #define	WM_RX_INTR_PROCESS_LIMIT_DEFAULT	0U
    231  1.494  knakahar #endif
    232  1.493  knakahar 
    233  1.354  knakahar typedef union txdescs {
    234  1.354  knakahar 	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
    235  1.354  knakahar 	nq_txdesc_t      sctxu_nq_txdescs[WM_NTXDESC_82544];
    236  1.354  knakahar } txdescs_t;
    237    1.1   thorpej 
    238  1.466  knakahar typedef union rxdescs {
    239  1.466  knakahar 	wiseman_rxdesc_t sctxu_rxdescs[WM_NRXDESC];
    240  1.466  knakahar 	ext_rxdesc_t      sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
    241  1.466  knakahar 	nq_rxdesc_t      sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
    242  1.466  knakahar } rxdescs_t;
    243  1.466  knakahar 
    244  1.398  knakahar #define	WM_CDTXOFF(txq, x)	((txq)->txq_descsize * (x))
    245  1.466  knakahar #define	WM_CDRXOFF(rxq, x)	((rxq)->rxq_descsize * (x))
    246    1.1   thorpej 
    247    1.1   thorpej /*
    248    1.1   thorpej  * Software state for transmit jobs.
    249    1.1   thorpej  */
    250    1.1   thorpej struct wm_txsoft {
    251    1.1   thorpej 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
    252    1.1   thorpej 	bus_dmamap_t txs_dmamap;	/* our DMA map */
    253    1.1   thorpej 	int txs_firstdesc;		/* first descriptor in packet */
    254    1.1   thorpej 	int txs_lastdesc;		/* last descriptor in packet */
    255    1.4   thorpej 	int txs_ndesc;			/* # of descriptors used */
    256    1.1   thorpej };
    257    1.1   thorpej 
    258    1.1   thorpej /*
    259    1.1   thorpej  * Software state for receive buffers.  Each descriptor gets a
    260    1.1   thorpej  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
    261    1.1   thorpej  * more than one buffer, we chain them together.
    262    1.1   thorpej  */
    263    1.1   thorpej struct wm_rxsoft {
    264    1.1   thorpej 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
    265    1.1   thorpej 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
    266    1.1   thorpej };
    267    1.1   thorpej 
    268  1.173   msaitoh #define WM_LINKUP_TIMEOUT	50
    269  1.173   msaitoh 
    270  1.199   msaitoh static uint16_t swfwphysem[] = {
    271  1.199   msaitoh 	SWFW_PHY0_SM,
    272  1.199   msaitoh 	SWFW_PHY1_SM,
    273  1.199   msaitoh 	SWFW_PHY2_SM,
    274  1.199   msaitoh 	SWFW_PHY3_SM
    275  1.199   msaitoh };
    276  1.199   msaitoh 
    277  1.320   msaitoh static const uint32_t wm_82580_rxpbs_table[] = {
    278  1.320   msaitoh 	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
    279  1.320   msaitoh };
    280  1.320   msaitoh 
    281  1.356  knakahar struct wm_softc;
    282  1.356  knakahar 
    283  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    284  1.417  knakahar #define WM_Q_EVCNT_DEFINE(qname, evname)				\
    285  1.417  knakahar 	char qname##_##evname##_evcnt_name[sizeof("qname##XX##evname")]; \
    286  1.417  knakahar 	struct evcnt qname##_ev_##evname;
    287  1.417  knakahar 
    288  1.417  knakahar #define WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, evtype)	\
    289  1.417  knakahar 	do{								\
    290  1.417  knakahar 		snprintf((q)->qname##_##evname##_evcnt_name,		\
    291  1.417  knakahar 		    sizeof((q)->qname##_##evname##_evcnt_name),		\
    292  1.417  knakahar 		    "%s%02d%s", #qname, (qnum), #evname);		\
    293  1.417  knakahar 		evcnt_attach_dynamic(&(q)->qname##_ev_##evname,		\
    294  1.417  knakahar 		    (evtype), NULL, (xname),				\
    295  1.417  knakahar 		    (q)->qname##_##evname##_evcnt_name);		\
    296  1.417  knakahar 	}while(0)
    297  1.417  knakahar 
    298  1.417  knakahar #define WM_Q_MISC_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
    299  1.417  knakahar 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_MISC)
    300  1.417  knakahar 
    301  1.417  knakahar #define WM_Q_INTR_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
    302  1.417  knakahar 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_INTR)
    303  1.477  knakahar 
    304  1.477  knakahar #define WM_Q_EVCNT_DETACH(qname, evname, q, qnum)	\
    305  1.477  knakahar 	evcnt_detach(&(q)->qname##_ev_##evname);
    306  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
    307  1.417  knakahar 
    308  1.356  knakahar struct wm_txqueue {
    309  1.357  knakahar 	kmutex_t *txq_lock;		/* lock for tx operations */
    310  1.356  knakahar 
    311  1.405  knakahar 	struct wm_softc *txq_sc;	/* shortcut (skip struct wm_queue) */
    312  1.364  knakahar 
    313  1.356  knakahar 	/* Software state for the transmit descriptors. */
    314  1.356  knakahar 	int txq_num;			/* must be a power of two */
    315  1.356  knakahar 	struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
    316  1.356  knakahar 
    317  1.356  knakahar 	/* TX control data structures. */
    318  1.356  knakahar 	int txq_ndesc;			/* must be a power of two */
    319  1.398  knakahar 	size_t txq_descsize;		/* a tx descriptor size */
    320  1.356  knakahar 	txdescs_t *txq_descs_u;
    321  1.356  knakahar         bus_dmamap_t txq_desc_dmamap;	/* control data DMA map */
    322  1.356  knakahar 	bus_dma_segment_t txq_desc_seg;	/* control data segment */
    323  1.356  knakahar 	int txq_desc_rseg;		/* real number of control segment */
    324  1.356  knakahar #define	txq_desc_dma	txq_desc_dmamap->dm_segs[0].ds_addr
    325  1.356  knakahar #define	txq_descs	txq_descs_u->sctxu_txdescs
    326  1.356  knakahar #define	txq_nq_descs	txq_descs_u->sctxu_nq_txdescs
    327  1.356  knakahar 
    328  1.356  knakahar 	bus_addr_t txq_tdt_reg;		/* offset of TDT register */
    329  1.356  knakahar 
    330  1.356  knakahar 	int txq_free;			/* number of free Tx descriptors */
    331  1.356  knakahar 	int txq_next;			/* next ready Tx descriptor */
    332  1.356  knakahar 
    333  1.356  knakahar 	int txq_sfree;			/* number of free Tx jobs */
    334  1.356  knakahar 	int txq_snext;			/* next free Tx job */
    335  1.356  knakahar 	int txq_sdirty;			/* dirty Tx jobs */
    336  1.356  knakahar 
    337  1.356  knakahar 	/* These 4 variables are used only on the 82547. */
    338  1.356  knakahar 	int txq_fifo_size;		/* Tx FIFO size */
    339  1.356  knakahar 	int txq_fifo_head;		/* current head of FIFO */
    340  1.356  knakahar 	uint32_t txq_fifo_addr;		/* internal address of start of FIFO */
    341  1.356  knakahar 	int txq_fifo_stall;		/* Tx FIFO is stalled */
    342  1.356  knakahar 
    343  1.400  knakahar 	/*
    344  1.403  knakahar 	 * When ncpu > number of Tx queues, a Tx queue is shared by multiple
    345  1.403  knakahar 	 * CPUs. This queue intermediate them without block.
    346  1.403  knakahar 	 */
    347  1.403  knakahar 	pcq_t *txq_interq;
    348  1.403  knakahar 
    349  1.403  knakahar 	/*
    350  1.400  knakahar 	 * NEWQUEUE devices must use not ifp->if_flags but txq->txq_flags
    351  1.400  knakahar 	 * to manage Tx H/W queue's busy flag.
    352  1.400  knakahar 	 */
    353  1.400  knakahar 	int txq_flags;			/* flags for H/W queue, see below */
    354  1.401  knakahar #define	WM_TXQ_NO_SPACE	0x1
    355  1.400  knakahar 
    356  1.429  knakahar 	bool txq_stopping;
    357  1.429  knakahar 
    358  1.495  knakahar 	uint32_t txq_packets;		/* for AIM */
    359  1.495  knakahar 	uint32_t txq_bytes;		/* for AIM */
    360  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    361  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txsstall)	/* Tx stalled due to no txs */
    362  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdstall)	/* Tx stalled due to no txd */
    363  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txfifo_stall)	/* Tx FIFO stalls (82547) */
    364  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdw)		/* Tx descriptor interrupts */
    365  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txqe)		/* Tx queue empty interrupts */
    366  1.417  knakahar 						/* XXX not used? */
    367  1.417  knakahar 
    368  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txipsum)		/* IP checksums comp. out-bound */
    369  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq,txtusum)		/* TCP/UDP cksums comp. out-bound */
    370  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtusum6)	/* TCP/UDP v6 cksums comp. out-bound */
    371  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtso)		/* TCP seg offload out-bound (IPv4) */
    372  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtso6)		/* TCP seg offload out-bound (IPv6) */
    373  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtsopain)	/* painful header manip. for TSO */
    374  1.417  knakahar 
    375  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdrop)		/* Tx packets dropped(too many segs) */
    376  1.417  knakahar 
    377  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, tu)		/* Tx underrun */
    378  1.417  knakahar 
    379  1.417  knakahar 	char txq_txseg_evcnt_names[WM_NTXSEGS][sizeof("txqXXtxsegXXX")];
    380  1.417  knakahar 	struct evcnt txq_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
    381  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
    382  1.356  knakahar };
    383  1.356  knakahar 
    384  1.356  knakahar struct wm_rxqueue {
    385  1.357  knakahar 	kmutex_t *rxq_lock;		/* lock for rx operations */
    386  1.356  knakahar 
    387  1.405  knakahar 	struct wm_softc *rxq_sc;	/* shortcut (skip struct wm_queue) */
    388  1.364  knakahar 
    389  1.356  knakahar 	/* Software state for the receive descriptors. */
    390  1.466  knakahar 	struct wm_rxsoft rxq_soft[WM_NRXDESC];
    391  1.356  knakahar 
    392  1.356  knakahar 	/* RX control data structures. */
    393  1.466  knakahar 	int rxq_ndesc;			/* must be a power of two */
    394  1.466  knakahar 	size_t rxq_descsize;		/* a rx descriptor size */
    395  1.466  knakahar 	rxdescs_t *rxq_descs_u;
    396  1.356  knakahar 	bus_dmamap_t rxq_desc_dmamap;	/* control data DMA map */
    397  1.356  knakahar 	bus_dma_segment_t rxq_desc_seg;	/* control data segment */
    398  1.356  knakahar 	int rxq_desc_rseg;		/* real number of control segment */
    399  1.356  knakahar #define	rxq_desc_dma	rxq_desc_dmamap->dm_segs[0].ds_addr
    400  1.466  knakahar #define	rxq_descs	rxq_descs_u->sctxu_rxdescs
    401  1.466  knakahar #define	rxq_ext_descs	rxq_descs_u->sctxu_ext_rxdescs
    402  1.466  knakahar #define	rxq_nq_descs	rxq_descs_u->sctxu_nq_rxdescs
    403  1.356  knakahar 
    404  1.356  knakahar 	bus_addr_t rxq_rdt_reg;		/* offset of RDT register */
    405  1.356  knakahar 
    406  1.388   msaitoh 	int rxq_ptr;			/* next ready Rx desc/queue ent */
    407  1.356  knakahar 	int rxq_discard;
    408  1.356  knakahar 	int rxq_len;
    409  1.356  knakahar 	struct mbuf *rxq_head;
    410  1.356  knakahar 	struct mbuf *rxq_tail;
    411  1.356  knakahar 	struct mbuf **rxq_tailp;
    412  1.356  knakahar 
    413  1.429  knakahar 	bool rxq_stopping;
    414  1.429  knakahar 
    415  1.495  knakahar 	uint32_t rxq_packets;		/* for AIM */
    416  1.495  knakahar 	uint32_t rxq_bytes;		/* for AIM */
    417  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    418  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxintr);		/* Rx interrupts */
    419  1.417  knakahar 
    420  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxipsum);	/* IP checksums checked in-bound */
    421  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxtusum);	/* TCP/UDP cksums checked in-bound */
    422  1.417  knakahar #endif
    423  1.356  knakahar };
    424  1.356  knakahar 
    425  1.405  knakahar struct wm_queue {
    426  1.405  knakahar 	int wmq_id;			/* index of transmit and receive queues */
    427  1.405  knakahar 	int wmq_intr_idx;		/* index of MSI-X tables */
    428  1.405  knakahar 
    429  1.490  knakahar 	uint32_t wmq_itr;		/* interrupt interval per queue. */
    430  1.495  knakahar 	bool wmq_set_itr;
    431  1.490  knakahar 
    432  1.405  knakahar 	struct wm_txqueue wmq_txq;
    433  1.405  knakahar 	struct wm_rxqueue wmq_rxq;
    434  1.484  knakahar 
    435  1.484  knakahar 	void *wmq_si;
    436  1.405  knakahar };
    437  1.405  knakahar 
    438  1.424   msaitoh struct wm_phyop {
    439  1.424   msaitoh 	int (*acquire)(struct wm_softc *);
    440  1.424   msaitoh 	void (*release)(struct wm_softc *);
    441  1.447   msaitoh 	int reset_delay_us;
    442  1.424   msaitoh };
    443  1.424   msaitoh 
    444    1.1   thorpej /*
    445    1.1   thorpej  * Software state per device.
    446    1.1   thorpej  */
    447    1.1   thorpej struct wm_softc {
    448  1.160  christos 	device_t sc_dev;		/* generic device information */
    449    1.1   thorpej 	bus_space_tag_t sc_st;		/* bus space tag */
    450    1.1   thorpej 	bus_space_handle_t sc_sh;	/* bus space handle */
    451  1.204   msaitoh 	bus_size_t sc_ss;		/* bus space size */
    452   1.53   thorpej 	bus_space_tag_t sc_iot;		/* I/O space tag */
    453   1.53   thorpej 	bus_space_handle_t sc_ioh;	/* I/O space handle */
    454  1.212  jakllsch 	bus_size_t sc_ios;		/* I/O space size */
    455  1.139    bouyer 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
    456  1.139    bouyer 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
    457  1.336   msaitoh 	bus_size_t sc_flashs;		/* flash registers space size */
    458  1.392   msaitoh 	off_t sc_flashreg_offset;	/*
    459  1.392   msaitoh 					 * offset to flash registers from
    460  1.392   msaitoh 					 * start of BAR
    461  1.392   msaitoh 					 */
    462    1.1   thorpej 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
    463  1.199   msaitoh 
    464    1.1   thorpej 	struct ethercom sc_ethercom;	/* ethernet common data */
    465  1.199   msaitoh 	struct mii_data sc_mii;		/* MII/media information */
    466  1.199   msaitoh 
    467  1.123  jmcneill 	pci_chipset_tag_t sc_pc;
    468  1.123  jmcneill 	pcitag_t sc_pcitag;
    469  1.199   msaitoh 	int sc_bus_speed;		/* PCI/PCIX bus speed */
    470  1.281   msaitoh 	int sc_pcixe_capoff;		/* PCI[Xe] capability reg offset */
    471    1.1   thorpej 
    472  1.304   msaitoh 	uint16_t sc_pcidevid;		/* PCI device ID */
    473  1.192   msaitoh 	wm_chip_type sc_type;		/* MAC type */
    474  1.192   msaitoh 	int sc_rev;			/* MAC revision */
    475  1.192   msaitoh 	wm_phy_type sc_phytype;		/* PHY type */
    476  1.292   msaitoh 	uint32_t sc_mediatype;		/* Media type (Copper, Fiber, SERDES)*/
    477  1.311   msaitoh #define	WM_MEDIATYPE_UNKNOWN		0x00
    478  1.311   msaitoh #define	WM_MEDIATYPE_FIBER		0x01
    479  1.311   msaitoh #define	WM_MEDIATYPE_COPPER		0x02
    480  1.311   msaitoh #define	WM_MEDIATYPE_SERDES		0x03 /* Internal SERDES */
    481  1.199   msaitoh 	int sc_funcid;			/* unit number of the chip (0 to 3) */
    482    1.1   thorpej 	int sc_flags;			/* flags; see below */
    483  1.179   msaitoh 	int sc_if_flags;		/* last if_flags */
    484   1.71   thorpej 	int sc_flowflags;		/* 802.3x flow control flags */
    485  1.199   msaitoh 	int sc_align_tweak;
    486    1.1   thorpej 
    487  1.335   msaitoh 	void *sc_ihs[WM_MAX_NINTR];	/*
    488  1.335   msaitoh 					 * interrupt cookie.
    489  1.507  knakahar 					 * - legacy and msi use sc_ihs[0] only
    490  1.507  knakahar 					 * - msix use sc_ihs[0] to sc_ihs[nintrs-1]
    491  1.507  knakahar 					 */
    492  1.507  knakahar 	pci_intr_handle_t *sc_intrs;	/*
    493  1.507  knakahar 					 * legacy and msi use sc_intrs[0] only
    494  1.507  knakahar 					 * msix use sc_intrs[0] to sc_ihs[nintrs-1]
    495  1.335   msaitoh 					 */
    496  1.335   msaitoh 	int sc_nintrs;			/* number of interrupts */
    497  1.335   msaitoh 
    498  1.364  knakahar 	int sc_link_intr_idx;		/* index of MSI-X tables */
    499  1.364  knakahar 
    500  1.199   msaitoh 	callout_t sc_tick_ch;		/* tick callout */
    501  1.429  knakahar 	bool sc_core_stopping;
    502    1.1   thorpej 
    503  1.328   msaitoh 	int sc_nvm_ver_major;
    504  1.328   msaitoh 	int sc_nvm_ver_minor;
    505  1.350   msaitoh 	int sc_nvm_ver_build;
    506  1.294   msaitoh 	int sc_nvm_addrbits;		/* NVM address bits */
    507  1.328   msaitoh 	unsigned int sc_nvm_wordsize;	/* NVM word size */
    508  1.199   msaitoh 	int sc_ich8_flash_base;
    509  1.199   msaitoh 	int sc_ich8_flash_bank_size;
    510  1.199   msaitoh 	int sc_nvm_k1_enabled;
    511   1.42   thorpej 
    512  1.405  knakahar 	int sc_nqueues;
    513  1.405  knakahar 	struct wm_queue *sc_queue;
    514  1.493  knakahar 	u_int sc_rx_process_limit;	/* Rx processing repeat limit in softint */
    515  1.493  knakahar 	u_int sc_rx_intr_process_limit;	/* Rx processing repeat limit in H/W intr */
    516    1.1   thorpej 
    517  1.404  knakahar 	int sc_affinity_offset;
    518  1.404  knakahar 
    519    1.1   thorpej #ifdef WM_EVENT_COUNTERS
    520    1.1   thorpej 	/* Event counters. */
    521    1.1   thorpej 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
    522    1.1   thorpej 
    523  1.417  knakahar         /* WM_T_82542_2_1 only */
    524   1.71   thorpej 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
    525   1.71   thorpej 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
    526   1.71   thorpej 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
    527   1.71   thorpej 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
    528   1.71   thorpej 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
    529    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
    530    1.1   thorpej 
    531  1.356  knakahar 	/* This variable are used only on the 82547. */
    532  1.142        ad 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
    533   1.78   thorpej 
    534    1.1   thorpej 	uint32_t sc_ctrl;		/* prototype CTRL register */
    535    1.1   thorpej #if 0
    536    1.1   thorpej 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
    537    1.1   thorpej #endif
    538    1.1   thorpej 	uint32_t sc_icr;		/* prototype interrupt bits */
    539  1.490  knakahar 	uint32_t sc_itr_init;		/* prototype intr throttling reg */
    540    1.1   thorpej 	uint32_t sc_tctl;		/* prototype TCTL register */
    541    1.1   thorpej 	uint32_t sc_rctl;		/* prototype RCTL register */
    542    1.1   thorpej 	uint32_t sc_txcw;		/* prototype TXCW register */
    543    1.1   thorpej 	uint32_t sc_tipg;		/* prototype TIPG register */
    544   1.71   thorpej 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
    545   1.78   thorpej 	uint32_t sc_pba;		/* prototype PBA register */
    546    1.1   thorpej 
    547    1.1   thorpej 	int sc_tbi_linkup;		/* TBI link status */
    548  1.325   msaitoh 	int sc_tbi_serdes_anegticks;	/* autonegotiation ticks */
    549  1.325   msaitoh 	int sc_tbi_serdes_ticks;	/* tbi ticks */
    550    1.1   thorpej 
    551    1.1   thorpej 	int sc_mchash_type;		/* multicast filter offset */
    552   1.21    itojun 
    553  1.224       tls 	krndsource_t rnd_source;	/* random source */
    554  1.272     ozaki 
    555  1.424   msaitoh 	struct if_percpuq *sc_ipq;	/* softint-based input queues */
    556  1.424   msaitoh 
    557  1.357  knakahar 	kmutex_t *sc_core_lock;		/* lock for softc operations */
    558  1.424   msaitoh 	kmutex_t *sc_ich_phymtx;	/*
    559  1.424   msaitoh 					 * 82574/82583/ICH/PCH specific PHY
    560  1.424   msaitoh 					 * mutex. For 82574/82583, the mutex
    561  1.424   msaitoh 					 * is used for both PHY and NVM.
    562  1.424   msaitoh 					 */
    563  1.423   msaitoh 	kmutex_t *sc_ich_nvmmtx;	/* ICH/PCH specific NVM mutex */
    564  1.391     ozaki 
    565  1.424   msaitoh 	struct wm_phyop phy;
    566    1.1   thorpej };
    567    1.1   thorpej 
    568  1.357  knakahar #define WM_CORE_LOCK(_sc)	if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
    569  1.357  knakahar #define WM_CORE_UNLOCK(_sc)	if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
    570  1.357  knakahar #define WM_CORE_LOCKED(_sc)	(!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
    571  1.272     ozaki 
    572  1.356  knakahar #define	WM_RXCHAIN_RESET(rxq)						\
    573    1.1   thorpej do {									\
    574  1.356  knakahar 	(rxq)->rxq_tailp = &(rxq)->rxq_head;				\
    575  1.356  knakahar 	*(rxq)->rxq_tailp = NULL;					\
    576  1.356  knakahar 	(rxq)->rxq_len = 0;						\
    577    1.1   thorpej } while (/*CONSTCOND*/0)
    578    1.1   thorpej 
    579  1.356  knakahar #define	WM_RXCHAIN_LINK(rxq, m)						\
    580    1.1   thorpej do {									\
    581  1.356  knakahar 	*(rxq)->rxq_tailp = (rxq)->rxq_tail = (m);			\
    582  1.356  knakahar 	(rxq)->rxq_tailp = &(m)->m_next;				\
    583    1.1   thorpej } while (/*CONSTCOND*/0)
    584    1.1   thorpej 
    585    1.1   thorpej #ifdef WM_EVENT_COUNTERS
    586    1.1   thorpej #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
    587   1.71   thorpej #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
    588  1.417  knakahar 
    589  1.417  knakahar #define WM_Q_EVCNT_INCR(qname, evname)			\
    590  1.417  knakahar 	WM_EVCNT_INCR(&(qname)->qname##_ev_##evname)
    591  1.417  knakahar #define WM_Q_EVCNT_ADD(qname, evname, val)		\
    592  1.417  knakahar 	WM_EVCNT_ADD(&(qname)->qname##_ev_##evname, (val))
    593  1.417  knakahar #else /* !WM_EVENT_COUNTERS */
    594    1.1   thorpej #define	WM_EVCNT_INCR(ev)	/* nothing */
    595   1.71   thorpej #define	WM_EVCNT_ADD(ev, val)	/* nothing */
    596  1.417  knakahar 
    597  1.417  knakahar #define WM_Q_EVCNT_INCR(qname, evname)		/* nothing */
    598  1.417  knakahar #define WM_Q_EVCNT_ADD(qname, evname, val)	/* nothing */
    599  1.417  knakahar #endif /* !WM_EVENT_COUNTERS */
    600    1.1   thorpej 
    601    1.1   thorpej #define	CSR_READ(sc, reg)						\
    602    1.1   thorpej 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
    603    1.1   thorpej #define	CSR_WRITE(sc, reg, val)						\
    604    1.1   thorpej 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
    605   1.78   thorpej #define	CSR_WRITE_FLUSH(sc)						\
    606   1.78   thorpej 	(void) CSR_READ((sc), WMREG_STATUS)
    607    1.1   thorpej 
    608  1.392   msaitoh #define ICH8_FLASH_READ32(sc, reg)					\
    609  1.392   msaitoh 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh,		\
    610  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset)
    611  1.392   msaitoh #define ICH8_FLASH_WRITE32(sc, reg, data)				\
    612  1.392   msaitoh 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh,		\
    613  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset, (data))
    614  1.392   msaitoh 
    615  1.392   msaitoh #define ICH8_FLASH_READ16(sc, reg)					\
    616  1.392   msaitoh 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh,		\
    617  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset)
    618  1.392   msaitoh #define ICH8_FLASH_WRITE16(sc, reg, data)				\
    619  1.392   msaitoh 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh,		\
    620  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset, (data))
    621  1.139    bouyer 
    622  1.398  knakahar #define	WM_CDTXADDR(txq, x)	((txq)->txq_desc_dma + WM_CDTXOFF((txq), (x)))
    623  1.466  knakahar #define	WM_CDRXADDR(rxq, x)	((rxq)->rxq_desc_dma + WM_CDRXOFF((rxq), (x)))
    624    1.1   thorpej 
    625  1.356  knakahar #define	WM_CDTXADDR_LO(txq, x)	(WM_CDTXADDR((txq), (x)) & 0xffffffffU)
    626  1.356  knakahar #define	WM_CDTXADDR_HI(txq, x)						\
    627   1.69   thorpej 	(sizeof(bus_addr_t) == 8 ?					\
    628  1.356  knakahar 	 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
    629   1.69   thorpej 
    630  1.356  knakahar #define	WM_CDRXADDR_LO(rxq, x)	(WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
    631  1.356  knakahar #define	WM_CDRXADDR_HI(rxq, x)						\
    632   1.69   thorpej 	(sizeof(bus_addr_t) == 8 ?					\
    633  1.356  knakahar 	 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
    634   1.69   thorpej 
    635  1.280   msaitoh /*
    636  1.280   msaitoh  * Register read/write functions.
    637  1.280   msaitoh  * Other than CSR_{READ|WRITE}().
    638  1.280   msaitoh  */
    639  1.280   msaitoh #if 0
    640  1.280   msaitoh static inline uint32_t wm_io_read(struct wm_softc *, int);
    641  1.280   msaitoh #endif
    642  1.280   msaitoh static inline void wm_io_write(struct wm_softc *, int, uint32_t);
    643  1.280   msaitoh static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
    644  1.280   msaitoh 	uint32_t, uint32_t);
    645  1.280   msaitoh static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
    646  1.280   msaitoh 
    647  1.280   msaitoh /*
    648  1.352  knakahar  * Descriptor sync/init functions.
    649  1.352  knakahar  */
    650  1.362  knakahar static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int);
    651  1.362  knakahar static inline void wm_cdrxsync(struct wm_rxqueue *, int, int);
    652  1.362  knakahar static inline void wm_init_rxdesc(struct wm_rxqueue *, int);
    653  1.352  knakahar 
    654  1.352  knakahar /*
    655  1.280   msaitoh  * Device driver interface functions and commonly used functions.
    656  1.280   msaitoh  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
    657  1.280   msaitoh  */
    658  1.280   msaitoh static const struct wm_product *wm_lookup(const struct pci_attach_args *);
    659  1.280   msaitoh static int	wm_match(device_t, cfdata_t, void *);
    660  1.280   msaitoh static void	wm_attach(device_t, device_t, void *);
    661  1.280   msaitoh static int	wm_detach(device_t, int);
    662  1.280   msaitoh static bool	wm_suspend(device_t, const pmf_qual_t *);
    663  1.280   msaitoh static bool	wm_resume(device_t, const pmf_qual_t *);
    664   1.47   thorpej static void	wm_watchdog(struct ifnet *);
    665  1.403  knakahar static void	wm_watchdog_txq(struct ifnet *, struct wm_txqueue *);
    666  1.280   msaitoh static void	wm_tick(void *);
    667  1.213   msaitoh static int	wm_ifflags_cb(struct ethercom *);
    668  1.135  christos static int	wm_ioctl(struct ifnet *, u_long, void *);
    669  1.280   msaitoh /* MAC address related */
    670  1.306   msaitoh static uint16_t	wm_check_alt_mac_addr(struct wm_softc *);
    671  1.280   msaitoh static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
    672  1.280   msaitoh static void	wm_set_ral(struct wm_softc *, const uint8_t *, int);
    673  1.280   msaitoh static uint32_t	wm_mchash(struct wm_softc *, const uint8_t *);
    674  1.280   msaitoh static void	wm_set_filter(struct wm_softc *);
    675  1.280   msaitoh /* Reset and init related */
    676  1.280   msaitoh static void	wm_set_vlan(struct wm_softc *);
    677  1.280   msaitoh static void	wm_set_pcie_completion_timeout(struct wm_softc *);
    678  1.280   msaitoh static void	wm_get_auto_rd_done(struct wm_softc *);
    679  1.280   msaitoh static void	wm_lan_init_done(struct wm_softc *);
    680  1.280   msaitoh static void	wm_get_cfg_done(struct wm_softc *);
    681  1.517   msaitoh static void	wm_phy_post_reset(struct wm_softc *);
    682  1.312   msaitoh static void	wm_initialize_hardware_bits(struct wm_softc *);
    683  1.320   msaitoh static uint32_t	wm_rxpbs_adjust_82580(uint32_t);
    684  1.447   msaitoh static void	wm_reset_phy(struct wm_softc *);
    685  1.443   msaitoh static void	wm_flush_desc_rings(struct wm_softc *);
    686  1.280   msaitoh static void	wm_reset(struct wm_softc *);
    687  1.362  knakahar static int	wm_add_rxbuf(struct wm_rxqueue *, int);
    688  1.362  knakahar static void	wm_rxdrain(struct wm_rxqueue *);
    689  1.372  knakahar static void	wm_rss_getkey(uint8_t *);
    690  1.365  knakahar static void	wm_init_rss(struct wm_softc *);
    691  1.371   msaitoh static void	wm_adjust_qnum(struct wm_softc *, int);
    692  1.502  knakahar static inline bool	wm_is_using_msix(struct wm_softc *);
    693  1.502  knakahar static inline bool	wm_is_using_multiqueue(struct wm_softc *);
    694  1.501  knakahar static int	wm_softint_establish(struct wm_softc *, int, int);
    695  1.371   msaitoh static int	wm_setup_legacy(struct wm_softc *);
    696  1.371   msaitoh static int	wm_setup_msix(struct wm_softc *);
    697   1.47   thorpej static int	wm_init(struct ifnet *);
    698  1.272     ozaki static int	wm_init_locked(struct ifnet *);
    699  1.429  knakahar static void	wm_turnon(struct wm_softc *);
    700  1.429  knakahar static void	wm_turnoff(struct wm_softc *);
    701   1.47   thorpej static void	wm_stop(struct ifnet *, int);
    702  1.272     ozaki static void	wm_stop_locked(struct ifnet *, int);
    703  1.280   msaitoh static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
    704  1.280   msaitoh static void	wm_82547_txfifo_stall(void *);
    705  1.280   msaitoh static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
    706  1.491  knakahar static void	wm_itrs_writereg(struct wm_softc *, struct wm_queue *);
    707  1.353  knakahar /* DMA related */
    708  1.362  knakahar static int	wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *);
    709  1.362  knakahar static void	wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *);
    710  1.362  knakahar static void	wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *);
    711  1.405  knakahar static void	wm_init_tx_regs(struct wm_softc *, struct wm_queue *,
    712  1.405  knakahar     struct wm_txqueue *);
    713  1.362  knakahar static int	wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *);
    714  1.362  knakahar static void	wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *);
    715  1.405  knakahar static void	wm_init_rx_regs(struct wm_softc *, struct wm_queue *,
    716  1.405  knakahar     struct wm_rxqueue *);
    717  1.362  knakahar static int	wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    718  1.362  knakahar static void	wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    719  1.362  knakahar static void	wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    720  1.362  knakahar static int	wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    721  1.362  knakahar static void	wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    722  1.362  knakahar static int	wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    723  1.405  knakahar static void	wm_init_tx_queue(struct wm_softc *, struct wm_queue *,
    724  1.405  knakahar     struct wm_txqueue *);
    725  1.405  knakahar static int	wm_init_rx_queue(struct wm_softc *, struct wm_queue *,
    726  1.405  knakahar     struct wm_rxqueue *);
    727  1.353  knakahar static int	wm_alloc_txrx_queues(struct wm_softc *);
    728  1.353  knakahar static void	wm_free_txrx_queues(struct wm_softc *);
    729  1.355  knakahar static int	wm_init_txrx_queues(struct wm_softc *);
    730  1.280   msaitoh /* Start */
    731  1.498  knakahar static int	wm_tx_offload(struct wm_softc *, struct wm_txqueue *,
    732  1.498  knakahar     struct wm_txsoft *, uint32_t *, uint8_t *);
    733  1.454  knakahar static inline int	wm_select_txqueue(struct ifnet *, struct mbuf *);
    734  1.280   msaitoh static void	wm_start(struct ifnet *);
    735  1.280   msaitoh static void	wm_start_locked(struct ifnet *);
    736  1.454  knakahar static int	wm_transmit(struct ifnet *, struct mbuf *);
    737  1.454  knakahar static void	wm_transmit_locked(struct ifnet *, struct wm_txqueue *);
    738  1.454  knakahar static void	wm_send_common_locked(struct ifnet *, struct wm_txqueue *, bool);
    739  1.403  knakahar static int	wm_nq_tx_offload(struct wm_softc *, struct wm_txqueue *,
    740  1.403  knakahar     struct wm_txsoft *, uint32_t *, uint32_t *, bool *);
    741  1.280   msaitoh static void	wm_nq_start(struct ifnet *);
    742  1.280   msaitoh static void	wm_nq_start_locked(struct ifnet *);
    743  1.403  knakahar static int	wm_nq_transmit(struct ifnet *, struct mbuf *);
    744  1.403  knakahar static void	wm_nq_transmit_locked(struct ifnet *, struct wm_txqueue *);
    745  1.403  knakahar static void	wm_nq_send_common_locked(struct ifnet *, struct wm_txqueue *, bool);
    746  1.481  knakahar static void	wm_deferred_start_locked(struct wm_txqueue *);
    747  1.484  knakahar static void	wm_handle_queue(void *);
    748  1.280   msaitoh /* Interrupt */
    749  1.403  knakahar static int	wm_txeof(struct wm_softc *, struct wm_txqueue *);
    750  1.493  knakahar static void	wm_rxeof(struct wm_rxqueue *, u_int);
    751  1.280   msaitoh static void	wm_linkintr_gmii(struct wm_softc *, uint32_t);
    752  1.280   msaitoh static void	wm_linkintr_tbi(struct wm_softc *, uint32_t);
    753  1.325   msaitoh static void	wm_linkintr_serdes(struct wm_softc *, uint32_t);
    754   1.47   thorpej static void	wm_linkintr(struct wm_softc *, uint32_t);
    755  1.335   msaitoh static int	wm_intr_legacy(void *);
    756  1.480  knakahar static inline void	wm_txrxintr_disable(struct wm_queue *);
    757  1.480  knakahar static inline void	wm_txrxintr_enable(struct wm_queue *);
    758  1.495  knakahar static void	wm_itrs_calculate(struct wm_softc *, struct wm_queue *);
    759  1.405  knakahar static int	wm_txrxintr_msix(void *);
    760  1.335   msaitoh static int	wm_linkintr_msix(void *);
    761    1.1   thorpej 
    762  1.280   msaitoh /*
    763  1.280   msaitoh  * Media related.
    764  1.292   msaitoh  * GMII, SGMII, TBI, SERDES and SFP.
    765  1.280   msaitoh  */
    766  1.325   msaitoh /* Common */
    767  1.325   msaitoh static void	wm_tbi_serdes_set_linkled(struct wm_softc *);
    768  1.280   msaitoh /* GMII related */
    769   1.47   thorpej static void	wm_gmii_reset(struct wm_softc *);
    770  1.475   msaitoh static void	wm_gmii_setup_phytype(struct wm_softc *sc, uint32_t, uint16_t);
    771  1.280   msaitoh static int	wm_get_phy_id_82575(struct wm_softc *);
    772  1.280   msaitoh static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
    773  1.324   msaitoh static int	wm_gmii_mediachange(struct ifnet *);
    774  1.280   msaitoh static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
    775  1.280   msaitoh static void	wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
    776  1.280   msaitoh static uint32_t	wm_i82543_mii_recvbits(struct wm_softc *);
    777  1.157    dyoung static int	wm_gmii_i82543_readreg(device_t, int, int);
    778  1.157    dyoung static void	wm_gmii_i82543_writereg(device_t, int, int, int);
    779  1.424   msaitoh static int	wm_gmii_mdic_readreg(device_t, int, int);
    780  1.424   msaitoh static void	wm_gmii_mdic_writereg(device_t, int, int, int);
    781  1.157    dyoung static int	wm_gmii_i82544_readreg(device_t, int, int);
    782  1.157    dyoung static void	wm_gmii_i82544_writereg(device_t, int, int, int);
    783  1.157    dyoung static int	wm_gmii_i80003_readreg(device_t, int, int);
    784  1.157    dyoung static void	wm_gmii_i80003_writereg(device_t, int, int, int);
    785  1.167   msaitoh static int	wm_gmii_bm_readreg(device_t, int, int);
    786  1.167   msaitoh static void	wm_gmii_bm_writereg(device_t, int, int, int);
    787  1.280   msaitoh static void	wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int);
    788  1.192   msaitoh static int	wm_gmii_hv_readreg(device_t, int, int);
    789  1.424   msaitoh static int	wm_gmii_hv_readreg_locked(device_t, int, int);
    790  1.192   msaitoh static void	wm_gmii_hv_writereg(device_t, int, int, int);
    791  1.424   msaitoh static void	wm_gmii_hv_writereg_locked(device_t, int, int, int);
    792  1.243   msaitoh static int	wm_gmii_82580_readreg(device_t, int, int);
    793  1.243   msaitoh static void	wm_gmii_82580_writereg(device_t, int, int, int);
    794  1.329   msaitoh static int	wm_gmii_gs40g_readreg(device_t, int, int);
    795  1.329   msaitoh static void	wm_gmii_gs40g_writereg(device_t, int, int, int);
    796  1.280   msaitoh static void	wm_gmii_statchg(struct ifnet *);
    797  1.453   msaitoh /*
    798  1.453   msaitoh  * kumeran related (80003, ICH* and PCH*).
    799  1.453   msaitoh  * These functions are not for accessing MII registers but for accessing
    800  1.453   msaitoh  * kumeran specific registers.
    801  1.453   msaitoh  */
    802  1.280   msaitoh static int	wm_kmrn_readreg(struct wm_softc *, int);
    803  1.424   msaitoh static int	wm_kmrn_readreg_locked(struct wm_softc *, int);
    804  1.280   msaitoh static void	wm_kmrn_writereg(struct wm_softc *, int, int);
    805  1.424   msaitoh static void	wm_kmrn_writereg_locked(struct wm_softc *, int, int);
    806  1.280   msaitoh /* SGMII */
    807  1.265   msaitoh static bool	wm_sgmii_uses_mdio(struct wm_softc *);
    808  1.199   msaitoh static int	wm_sgmii_readreg(device_t, int, int);
    809  1.199   msaitoh static void	wm_sgmii_writereg(device_t, int, int, int);
    810  1.280   msaitoh /* TBI related */
    811  1.280   msaitoh static void	wm_tbi_mediainit(struct wm_softc *);
    812  1.324   msaitoh static int	wm_tbi_mediachange(struct ifnet *);
    813  1.280   msaitoh static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
    814  1.325   msaitoh static int	wm_check_for_link(struct wm_softc *);
    815  1.325   msaitoh static void	wm_tbi_tick(struct wm_softc *);
    816  1.325   msaitoh /* SERDES related */
    817  1.325   msaitoh static void	wm_serdes_power_up_link_82575(struct wm_softc *);
    818  1.325   msaitoh static int	wm_serdes_mediachange(struct ifnet *);
    819  1.325   msaitoh static void	wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
    820  1.325   msaitoh static void	wm_serdes_tick(struct wm_softc *);
    821  1.292   msaitoh /* SFP related */
    822  1.295   msaitoh static int	wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
    823  1.295   msaitoh static uint32_t	wm_sfp_get_media_type(struct wm_softc *);
    824  1.167   msaitoh 
    825  1.280   msaitoh /*
    826  1.280   msaitoh  * NVM related.
    827  1.280   msaitoh  * Microwire, SPI (w/wo EERD) and Flash.
    828  1.280   msaitoh  */
    829  1.294   msaitoh /* Misc functions */
    830  1.280   msaitoh static void	wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
    831  1.280   msaitoh static void	wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
    832  1.294   msaitoh static int	wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
    833  1.280   msaitoh /* Microwire */
    834  1.280   msaitoh static int	wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
    835  1.280   msaitoh /* SPI */
    836  1.280   msaitoh static int	wm_nvm_ready_spi(struct wm_softc *);
    837  1.280   msaitoh static int	wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
    838  1.280   msaitoh /* Using with EERD */
    839  1.280   msaitoh static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
    840  1.280   msaitoh static int	wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
    841  1.280   msaitoh /* Flash */
    842  1.280   msaitoh static int	wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
    843  1.280   msaitoh     unsigned int *);
    844  1.280   msaitoh static int32_t	wm_ich8_cycle_init(struct wm_softc *);
    845  1.280   msaitoh static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
    846  1.280   msaitoh static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
    847  1.392   msaitoh 	uint32_t *);
    848  1.280   msaitoh static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
    849  1.280   msaitoh static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
    850  1.392   msaitoh static int32_t	wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
    851  1.280   msaitoh static int	wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
    852  1.392   msaitoh static int	wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *);
    853  1.321   msaitoh /* iNVM */
    854  1.321   msaitoh static int	wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
    855  1.321   msaitoh static int	wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
    856  1.327   msaitoh /* Lock, detecting NVM type, validate checksum and read */
    857  1.280   msaitoh static int	wm_nvm_acquire(struct wm_softc *);
    858  1.280   msaitoh static void	wm_nvm_release(struct wm_softc *);
    859  1.280   msaitoh static int	wm_nvm_is_onboard_eeprom(struct wm_softc *);
    860  1.321   msaitoh static int	wm_nvm_get_flash_presence_i210(struct wm_softc *);
    861  1.280   msaitoh static int	wm_nvm_validate_checksum(struct wm_softc *);
    862  1.347   msaitoh static void	wm_nvm_version_invm(struct wm_softc *);
    863  1.328   msaitoh static void	wm_nvm_version(struct wm_softc *);
    864  1.280   msaitoh static int	wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
    865    1.1   thorpej 
    866  1.280   msaitoh /*
    867  1.280   msaitoh  * Hardware semaphores.
    868  1.280   msaitoh  * Very complexed...
    869  1.280   msaitoh  */
    870  1.424   msaitoh static int	wm_get_null(struct wm_softc *);
    871  1.424   msaitoh static void	wm_put_null(struct wm_softc *);
    872  1.424   msaitoh static int	wm_get_swsm_semaphore(struct wm_softc *); /* 8257[123] */
    873  1.127    bouyer static void	wm_put_swsm_semaphore(struct wm_softc *);
    874  1.127    bouyer static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
    875  1.127    bouyer static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
    876  1.424   msaitoh static int	wm_get_phy_82575(struct wm_softc *);
    877  1.424   msaitoh static void	wm_put_phy_82575(struct wm_softc *);
    878  1.424   msaitoh static int	wm_get_swfwhw_semaphore(struct wm_softc *); /* For 574/583 */
    879  1.139    bouyer static void	wm_put_swfwhw_semaphore(struct wm_softc *);
    880  1.424   msaitoh static int	wm_get_swflag_ich8lan(struct wm_softc *);	/* For PHY */
    881  1.424   msaitoh static void	wm_put_swflag_ich8lan(struct wm_softc *);
    882  1.423   msaitoh static int	wm_get_nvm_ich8lan(struct wm_softc *);		/* For NVM */
    883  1.423   msaitoh static void	wm_put_nvm_ich8lan(struct wm_softc *);
    884  1.259   msaitoh static int	wm_get_hw_semaphore_82573(struct wm_softc *);
    885  1.259   msaitoh static void	wm_put_hw_semaphore_82573(struct wm_softc *);
    886  1.139    bouyer 
    887  1.280   msaitoh /*
    888  1.280   msaitoh  * Management mode and power management related subroutines.
    889  1.280   msaitoh  * BMC, AMT, suspend/resume and EEE.
    890  1.280   msaitoh  */
    891  1.439   msaitoh #if 0
    892  1.169   msaitoh static int	wm_check_mng_mode(struct wm_softc *);
    893  1.169   msaitoh static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
    894  1.169   msaitoh static int	wm_check_mng_mode_82574(struct wm_softc *);
    895  1.169   msaitoh static int	wm_check_mng_mode_generic(struct wm_softc *);
    896  1.378   msaitoh #endif
    897  1.203   msaitoh static int	wm_enable_mng_pass_thru(struct wm_softc *);
    898  1.386   msaitoh static bool	wm_phy_resetisblocked(struct wm_softc *);
    899  1.169   msaitoh static void	wm_get_hw_control(struct wm_softc *);
    900  1.280   msaitoh static void	wm_release_hw_control(struct wm_softc *);
    901  1.392   msaitoh static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool);
    902  1.280   msaitoh static void	wm_smbustopci(struct wm_softc *);
    903  1.280   msaitoh static void	wm_init_manageability(struct wm_softc *);
    904  1.280   msaitoh static void	wm_release_manageability(struct wm_softc *);
    905  1.280   msaitoh static void	wm_get_wakeup(struct wm_softc *);
    906  1.447   msaitoh static void	wm_ulp_disable(struct wm_softc *);
    907  1.280   msaitoh static void	wm_enable_phy_wakeup(struct wm_softc *);
    908  1.203   msaitoh static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
    909  1.280   msaitoh static void	wm_enable_wakeup(struct wm_softc *);
    910  1.377   msaitoh /* LPLU (Low Power Link Up) */
    911  1.377   msaitoh static void	wm_lplu_d0_disable(struct wm_softc *);
    912  1.280   msaitoh /* EEE */
    913  1.280   msaitoh static void	wm_set_eee_i350(struct wm_softc *);
    914  1.280   msaitoh 
    915  1.280   msaitoh /*
    916  1.280   msaitoh  * Workarounds (mainly PHY related).
    917  1.280   msaitoh  * Basically, PHY's workarounds are in the PHY drivers.
    918  1.280   msaitoh  */
    919  1.280   msaitoh static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
    920  1.280   msaitoh static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
    921  1.192   msaitoh static void	wm_hv_phy_workaround_ich8lan(struct wm_softc *);
    922  1.221   msaitoh static void	wm_lv_phy_workaround_ich8lan(struct wm_softc *);
    923  1.424   msaitoh static int	wm_k1_gig_workaround_hv(struct wm_softc *, int);
    924  1.221   msaitoh static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
    925  1.192   msaitoh static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
    926  1.199   msaitoh static void	wm_reset_init_script_82575(struct wm_softc *);
    927  1.325   msaitoh static void	wm_reset_mdicnfg_82580(struct wm_softc *);
    928  1.447   msaitoh static bool	wm_phy_is_accessible_pchlan(struct wm_softc *);
    929  1.447   msaitoh static void	wm_toggle_lanphypc_pch_lpt(struct wm_softc *);
    930  1.445   msaitoh static int	wm_platform_pm_pch_lpt(struct wm_softc *, bool);
    931  1.329   msaitoh static void	wm_pll_workaround_i210(struct wm_softc *);
    932  1.517   msaitoh static void	wm_legacy_irq_quirk_spt(struct wm_softc *);
    933    1.1   thorpej 
    934  1.201   msaitoh CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
    935  1.201   msaitoh     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
    936    1.1   thorpej 
    937    1.1   thorpej /*
    938    1.1   thorpej  * Devices supported by this driver.
    939    1.1   thorpej  */
    940   1.76   thorpej static const struct wm_product {
    941    1.1   thorpej 	pci_vendor_id_t		wmp_vendor;
    942    1.1   thorpej 	pci_product_id_t	wmp_product;
    943    1.1   thorpej 	const char		*wmp_name;
    944   1.43   thorpej 	wm_chip_type		wmp_type;
    945  1.292   msaitoh 	uint32_t		wmp_flags;
    946  1.311   msaitoh #define	WMP_F_UNKNOWN		WM_MEDIATYPE_UNKNOWN
    947  1.311   msaitoh #define	WMP_F_FIBER		WM_MEDIATYPE_FIBER
    948  1.311   msaitoh #define	WMP_F_COPPER		WM_MEDIATYPE_COPPER
    949  1.311   msaitoh #define	WMP_F_SERDES		WM_MEDIATYPE_SERDES
    950  1.292   msaitoh #define WMP_MEDIATYPE(x)	((x) & 0x03)
    951    1.1   thorpej } wm_products[] = {
    952    1.1   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
    953    1.1   thorpej 	  "Intel i82542 1000BASE-X Ethernet",
    954  1.291   msaitoh 	  WM_T_82542_2_1,	WMP_F_FIBER },
    955    1.1   thorpej 
    956   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
    957   1.11   thorpej 	  "Intel i82543GC 1000BASE-X Ethernet",
    958  1.291   msaitoh 	  WM_T_82543,		WMP_F_FIBER },
    959    1.1   thorpej 
    960   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
    961   1.11   thorpej 	  "Intel i82543GC 1000BASE-T Ethernet",
    962  1.291   msaitoh 	  WM_T_82543,		WMP_F_COPPER },
    963    1.1   thorpej 
    964   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
    965   1.11   thorpej 	  "Intel i82544EI 1000BASE-T Ethernet",
    966  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
    967    1.1   thorpej 
    968   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
    969   1.11   thorpej 	  "Intel i82544EI 1000BASE-X Ethernet",
    970  1.291   msaitoh 	  WM_T_82544,		WMP_F_FIBER },
    971    1.1   thorpej 
    972   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
    973    1.1   thorpej 	  "Intel i82544GC 1000BASE-T Ethernet",
    974  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
    975    1.1   thorpej 
    976   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
    977   1.11   thorpej 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
    978  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
    979    1.1   thorpej 
    980   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
    981   1.17   thorpej 	  "Intel i82540EM 1000BASE-T Ethernet",
    982  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
    983   1.34      kent 
    984   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
    985   1.55   thorpej 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
    986  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
    987   1.55   thorpej 
    988   1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
    989   1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    990  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
    991   1.34      kent 
    992   1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
    993   1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    994  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
    995   1.33      kent 
    996   1.33      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
    997   1.33      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
    998  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
    999   1.17   thorpej 
   1000   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
   1001   1.17   thorpej 	  "Intel i82545EM 1000BASE-T Ethernet",
   1002  1.291   msaitoh 	  WM_T_82545,		WMP_F_COPPER },
   1003   1.17   thorpej 
   1004   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
   1005   1.55   thorpej 	  "Intel i82545GM 1000BASE-T Ethernet",
   1006  1.291   msaitoh 	  WM_T_82545_3,		WMP_F_COPPER },
   1007   1.55   thorpej 
   1008   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
   1009   1.55   thorpej 	  "Intel i82545GM 1000BASE-X Ethernet",
   1010  1.291   msaitoh 	  WM_T_82545_3,		WMP_F_FIBER },
   1011  1.279   msaitoh 
   1012   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
   1013   1.55   thorpej 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
   1014   1.55   thorpej 	  WM_T_82545_3,		WMP_F_SERDES },
   1015  1.279   msaitoh 
   1016   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
   1017   1.39   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
   1018  1.291   msaitoh 	  WM_T_82546,		WMP_F_COPPER },
   1019   1.39   thorpej 
   1020  1.198   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_QUAD,
   1021   1.17   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
   1022  1.291   msaitoh 	  WM_T_82546,		WMP_F_COPPER },
   1023   1.17   thorpej 
   1024   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
   1025   1.17   thorpej 	  "Intel i82545EM 1000BASE-X Ethernet",
   1026  1.291   msaitoh 	  WM_T_82545,		WMP_F_FIBER },
   1027   1.17   thorpej 
   1028   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
   1029   1.17   thorpej 	  "Intel i82546EB 1000BASE-X Ethernet",
   1030  1.291   msaitoh 	  WM_T_82546,		WMP_F_FIBER },
   1031   1.17   thorpej 
   1032   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
   1033   1.55   thorpej 	  "Intel i82546GB 1000BASE-T Ethernet",
   1034  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1035   1.55   thorpej 
   1036   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
   1037   1.55   thorpej 	  "Intel i82546GB 1000BASE-X Ethernet",
   1038  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_FIBER },
   1039  1.279   msaitoh 
   1040   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
   1041   1.55   thorpej 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
   1042   1.55   thorpej 	  WM_T_82546_3,		WMP_F_SERDES },
   1043  1.279   msaitoh 
   1044  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
   1045  1.127    bouyer 	  "i82546GB quad-port Gigabit Ethernet",
   1046  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1047  1.127    bouyer 
   1048  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
   1049  1.127    bouyer 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
   1050  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1051  1.127    bouyer 
   1052  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
   1053  1.116   msaitoh 	  "Intel PRO/1000MT (82546GB)",
   1054  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1055  1.116   msaitoh 
   1056   1.63   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
   1057   1.63   thorpej 	  "Intel i82541EI 1000BASE-T Ethernet",
   1058  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1059   1.63   thorpej 
   1060  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
   1061  1.116   msaitoh 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
   1062  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1063  1.116   msaitoh 
   1064   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
   1065   1.57   thorpej 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
   1066  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1067   1.57   thorpej 
   1068   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
   1069   1.57   thorpej 	  "Intel i82541ER 1000BASE-T Ethernet",
   1070  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1071   1.57   thorpej 
   1072   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
   1073   1.57   thorpej 	  "Intel i82541GI 1000BASE-T Ethernet",
   1074  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1075   1.57   thorpej 
   1076   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
   1077   1.57   thorpej 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
   1078  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1079   1.57   thorpej 
   1080  1.101      tron 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
   1081  1.101      tron 	  "Intel i82541PI 1000BASE-T Ethernet",
   1082  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1083  1.101      tron 
   1084   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
   1085   1.57   thorpej 	  "Intel i82547EI 1000BASE-T Ethernet",
   1086  1.291   msaitoh 	  WM_T_82547,		WMP_F_COPPER },
   1087   1.57   thorpej 
   1088  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
   1089  1.141    simonb 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
   1090  1.291   msaitoh 	  WM_T_82547,		WMP_F_COPPER },
   1091  1.116   msaitoh 
   1092   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
   1093   1.57   thorpej 	  "Intel i82547GI 1000BASE-T Ethernet",
   1094  1.291   msaitoh 	  WM_T_82547_2,		WMP_F_COPPER },
   1095  1.116   msaitoh 
   1096  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
   1097  1.116   msaitoh 	  "Intel PRO/1000 PT (82571EB)",
   1098  1.291   msaitoh 	  WM_T_82571,		WMP_F_COPPER },
   1099  1.116   msaitoh 
   1100  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
   1101  1.116   msaitoh 	  "Intel PRO/1000 PF (82571EB)",
   1102  1.291   msaitoh 	  WM_T_82571,		WMP_F_FIBER },
   1103  1.279   msaitoh 
   1104  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
   1105  1.116   msaitoh 	  "Intel PRO/1000 PB (82571EB)",
   1106  1.116   msaitoh 	  WM_T_82571,		WMP_F_SERDES },
   1107  1.279   msaitoh 
   1108  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
   1109  1.127    bouyer 	  "Intel PRO/1000 QT (82571EB)",
   1110  1.291   msaitoh 	  WM_T_82571,		WMP_F_COPPER },
   1111  1.127    bouyer 
   1112  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
   1113  1.299   msaitoh 	  "Intel PRO/1000 PT Quad Port Server Adapter",
   1114  1.299   msaitoh 	  WM_T_82571,		WMP_F_COPPER, },
   1115  1.299   msaitoh 
   1116  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER,
   1117  1.299   msaitoh 	  "Intel Gigabit PT Quad Port Server ExpressModule",
   1118  1.299   msaitoh 	  WM_T_82571,		WMP_F_COPPER, },
   1119  1.299   msaitoh 
   1120  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES,
   1121  1.299   msaitoh 	  "Intel 82571EB Dual Gigabit Ethernet (SERDES)",
   1122  1.299   msaitoh 	  WM_T_82571,		WMP_F_SERDES, },
   1123  1.299   msaitoh 
   1124  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES,
   1125  1.299   msaitoh 	  "Intel 82571EB Quad Gigabit Ethernet (SERDES)",
   1126  1.299   msaitoh 	  WM_T_82571,		WMP_F_SERDES, },
   1127  1.299   msaitoh 
   1128  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER,
   1129  1.299   msaitoh 	  "Intel 82571EB Quad 1000baseX Ethernet",
   1130  1.299   msaitoh 	  WM_T_82571,		WMP_F_FIBER, },
   1131  1.299   msaitoh 
   1132  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
   1133  1.116   msaitoh 	  "Intel i82572EI 1000baseT Ethernet",
   1134  1.291   msaitoh 	  WM_T_82572,		WMP_F_COPPER },
   1135  1.116   msaitoh 
   1136  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
   1137  1.116   msaitoh 	  "Intel i82572EI 1000baseX Ethernet",
   1138  1.291   msaitoh 	  WM_T_82572,		WMP_F_FIBER },
   1139  1.279   msaitoh 
   1140  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
   1141  1.116   msaitoh 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
   1142  1.116   msaitoh 	  WM_T_82572,		WMP_F_SERDES },
   1143  1.116   msaitoh 
   1144  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
   1145  1.116   msaitoh 	  "Intel i82572EI 1000baseT Ethernet",
   1146  1.291   msaitoh 	  WM_T_82572,		WMP_F_COPPER },
   1147  1.116   msaitoh 
   1148  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
   1149  1.116   msaitoh 	  "Intel i82573E",
   1150  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1151  1.116   msaitoh 
   1152  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
   1153  1.117   msaitoh 	  "Intel i82573E IAMT",
   1154  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1155  1.116   msaitoh 
   1156  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
   1157  1.116   msaitoh 	  "Intel i82573L Gigabit Ethernet",
   1158  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1159  1.116   msaitoh 
   1160  1.165  sborrill 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
   1161  1.165  sborrill 	  "Intel i82574L",
   1162  1.291   msaitoh 	  WM_T_82574,		WMP_F_COPPER },
   1163  1.165  sborrill 
   1164  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574LA,
   1165  1.299   msaitoh 	  "Intel i82574L",
   1166  1.299   msaitoh 	  WM_T_82574,		WMP_F_COPPER },
   1167  1.299   msaitoh 
   1168  1.185   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82583V,
   1169  1.185   msaitoh 	  "Intel i82583V",
   1170  1.291   msaitoh 	  WM_T_82583,		WMP_F_COPPER },
   1171  1.185   msaitoh 
   1172  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
   1173  1.127    bouyer 	  "i80003 dual 1000baseT Ethernet",
   1174  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1175  1.127    bouyer 
   1176  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
   1177  1.127    bouyer 	  "i80003 dual 1000baseX Ethernet",
   1178  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1179  1.279   msaitoh 
   1180  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
   1181  1.127    bouyer 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
   1182  1.127    bouyer 	  WM_T_80003,		WMP_F_SERDES },
   1183  1.127    bouyer 
   1184  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
   1185  1.127    bouyer 	  "Intel i80003 1000baseT Ethernet",
   1186  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1187  1.279   msaitoh 
   1188  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
   1189  1.127    bouyer 	  "Intel i80003 Gigabit Ethernet (SERDES)",
   1190  1.127    bouyer 	  WM_T_80003,		WMP_F_SERDES },
   1191  1.279   msaitoh 
   1192  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
   1193  1.139    bouyer 	  "Intel i82801H (M_AMT) LAN Controller",
   1194  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1195  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
   1196  1.139    bouyer 	  "Intel i82801H (AMT) LAN Controller",
   1197  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1198  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
   1199  1.139    bouyer 	  "Intel i82801H LAN Controller",
   1200  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1201  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
   1202  1.438   msaitoh 	  "Intel i82801H (IFE) 10/100 LAN Controller",
   1203  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1204  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
   1205  1.139    bouyer 	  "Intel i82801H (M) LAN Controller",
   1206  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1207  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
   1208  1.438   msaitoh 	  "Intel i82801H IFE (GT) 10/100 LAN Controller",
   1209  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1210  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
   1211  1.438   msaitoh 	  "Intel i82801H IFE (G) 10/100 LAN Controller",
   1212  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1213  1.426   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_82567V_3,
   1214  1.426   msaitoh 	  "82567V-3 LAN Controller",
   1215  1.426   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1216  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
   1217  1.144   msaitoh 	  "82801I (AMT) LAN Controller",
   1218  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1219  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
   1220  1.438   msaitoh 	  "82801I 10/100 LAN Controller",
   1221  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1222  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
   1223  1.438   msaitoh 	  "82801I (G) 10/100 LAN Controller",
   1224  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1225  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
   1226  1.438   msaitoh 	  "82801I (GT) 10/100 LAN Controller",
   1227  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1228  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
   1229  1.144   msaitoh 	  "82801I (C) LAN Controller",
   1230  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1231  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
   1232  1.162    bouyer 	  "82801I mobile LAN Controller",
   1233  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1234  1.459   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_V,
   1235  1.162    bouyer 	  "82801I mobile (V) LAN Controller",
   1236  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1237  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
   1238  1.162    bouyer 	  "82801I mobile (AMT) LAN Controller",
   1239  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1240  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_BM,
   1241  1.191   msaitoh 	  "82567LM-4 LAN Controller",
   1242  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1243  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LM,
   1244  1.191   msaitoh 	  "82567LM-2 LAN Controller",
   1245  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1246  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LF,
   1247  1.191   msaitoh 	  "82567LF-2 LAN Controller",
   1248  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1249  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LM,
   1250  1.164     markd 	  "82567LM-3 LAN Controller",
   1251  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1252  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LF,
   1253  1.167   msaitoh 	  "82567LF-3 LAN Controller",
   1254  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1255  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_V,
   1256  1.191   msaitoh 	  "82567V-2 LAN Controller",
   1257  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1258  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_V,
   1259  1.221   msaitoh 	  "82567V-3? LAN Controller",
   1260  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1261  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_HANKSVILLE,
   1262  1.221   msaitoh 	  "HANKSVILLE LAN Controller",
   1263  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1264  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LM,
   1265  1.207   msaitoh 	  "PCH LAN (82577LM) Controller",
   1266  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1267  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LC,
   1268  1.207   msaitoh 	  "PCH LAN (82577LC) Controller",
   1269  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1270  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DM,
   1271  1.190   msaitoh 	  "PCH LAN (82578DM) Controller",
   1272  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1273  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DC,
   1274  1.190   msaitoh 	  "PCH LAN (82578DC) Controller",
   1275  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1276  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_LM,
   1277  1.221   msaitoh 	  "PCH2 LAN (82579LM) Controller",
   1278  1.291   msaitoh 	  WM_T_PCH2,		WMP_F_COPPER },
   1279  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_V,
   1280  1.221   msaitoh 	  "PCH2 LAN (82579V) Controller",
   1281  1.291   msaitoh 	  WM_T_PCH2,		WMP_F_COPPER },
   1282  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_COPPER,
   1283  1.199   msaitoh 	  "82575EB dual-1000baseT Ethernet",
   1284  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1285  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES,
   1286  1.199   msaitoh 	  "82575EB dual-1000baseX Ethernet (SERDES)",
   1287  1.199   msaitoh 	  WM_T_82575,		WMP_F_SERDES },
   1288  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER,
   1289  1.199   msaitoh 	  "82575GB quad-1000baseT Ethernet",
   1290  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1291  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM,
   1292  1.199   msaitoh 	  "82575GB quad-1000baseT Ethernet (PM)",
   1293  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1294  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_COPPER,
   1295  1.199   msaitoh 	  "82576 1000BaseT Ethernet",
   1296  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1297  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_FIBER,
   1298  1.199   msaitoh 	  "82576 1000BaseX Ethernet",
   1299  1.291   msaitoh 	  WM_T_82576,		WMP_F_FIBER },
   1300  1.279   msaitoh 
   1301  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES,
   1302  1.199   msaitoh 	  "82576 gigabit Ethernet (SERDES)",
   1303  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1304  1.279   msaitoh 
   1305  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_QUAD_COPPER,
   1306  1.199   msaitoh 	  "82576 quad-1000BaseT Ethernet",
   1307  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1308  1.299   msaitoh 
   1309  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2,
   1310  1.299   msaitoh 	  "82576 Gigabit ET2 Quad Port Server Adapter",
   1311  1.299   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1312  1.299   msaitoh 
   1313  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS,
   1314  1.199   msaitoh 	  "82576 gigabit Ethernet",
   1315  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1316  1.279   msaitoh 
   1317  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS_SERDES,
   1318  1.199   msaitoh 	  "82576 gigabit Ethernet (SERDES)",
   1319  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1320  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES_QUAD,
   1321  1.199   msaitoh 	  "82576 quad-gigabit Ethernet (SERDES)",
   1322  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1323  1.279   msaitoh 
   1324  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER,
   1325  1.199   msaitoh 	  "82580 1000BaseT Ethernet",
   1326  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1327  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_FIBER,
   1328  1.199   msaitoh 	  "82580 1000BaseX Ethernet",
   1329  1.291   msaitoh 	  WM_T_82580,		WMP_F_FIBER },
   1330  1.279   msaitoh 
   1331  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SERDES,
   1332  1.199   msaitoh 	  "82580 1000BaseT Ethernet (SERDES)",
   1333  1.199   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1334  1.279   msaitoh 
   1335  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SGMII,
   1336  1.199   msaitoh 	  "82580 gigabit Ethernet (SGMII)",
   1337  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1338  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER_DUAL,
   1339  1.199   msaitoh 	  "82580 dual-1000BaseT Ethernet",
   1340  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1341  1.300   msaitoh 
   1342  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_QUAD_FIBER,
   1343  1.221   msaitoh 	  "82580 quad-1000BaseX Ethernet",
   1344  1.291   msaitoh 	  WM_T_82580,		WMP_F_FIBER },
   1345  1.300   msaitoh 
   1346  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SGMII,
   1347  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SGMII)",
   1348  1.304   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1349  1.304   msaitoh 
   1350  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SERDES,
   1351  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SERDES)",
   1352  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1353  1.304   msaitoh 
   1354  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_BPLANE,
   1355  1.304   msaitoh 	  "DH89XXCC 1000BASE-KX Ethernet",
   1356  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1357  1.304   msaitoh 
   1358  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SFP,
   1359  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SFP)",
   1360  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1361  1.304   msaitoh 
   1362  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_COPPER,
   1363  1.228   msaitoh 	  "I350 Gigabit Network Connection",
   1364  1.291   msaitoh 	  WM_T_I350,		WMP_F_COPPER },
   1365  1.304   msaitoh 
   1366  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_FIBER,
   1367  1.228   msaitoh 	  "I350 Gigabit Fiber Network Connection",
   1368  1.291   msaitoh 	  WM_T_I350,		WMP_F_FIBER },
   1369  1.279   msaitoh 
   1370  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SERDES,
   1371  1.228   msaitoh 	  "I350 Gigabit Backplane Connection",
   1372  1.228   msaitoh 	  WM_T_I350,		WMP_F_SERDES },
   1373  1.292   msaitoh 
   1374  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_DA4,
   1375  1.299   msaitoh 	  "I350 Quad Port Gigabit Ethernet",
   1376  1.299   msaitoh 	  WM_T_I350,		WMP_F_SERDES },
   1377  1.299   msaitoh 
   1378  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SGMII,
   1379  1.228   msaitoh 	  "I350 Gigabit Connection",
   1380  1.291   msaitoh 	  WM_T_I350,		WMP_F_COPPER },
   1381  1.292   msaitoh 
   1382  1.308   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_1000KX,
   1383  1.308   msaitoh 	  "I354 Gigabit Ethernet (KX)",
   1384  1.308   msaitoh 	  WM_T_I354,		WMP_F_SERDES },
   1385  1.308   msaitoh 
   1386  1.265   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_SGMII,
   1387  1.308   msaitoh 	  "I354 Gigabit Ethernet (SGMII)",
   1388  1.308   msaitoh 	  WM_T_I354,		WMP_F_COPPER },
   1389  1.308   msaitoh 
   1390  1.308   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_25GBE,
   1391  1.308   msaitoh 	  "I354 Gigabit Ethernet (2.5G)",
   1392  1.291   msaitoh 	  WM_T_I354,		WMP_F_COPPER },
   1393  1.308   msaitoh 
   1394  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_T1,
   1395  1.247   msaitoh 	  "I210-T1 Ethernet Server Adapter",
   1396  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1397  1.299   msaitoh 
   1398  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_OEM1,
   1399  1.247   msaitoh 	  "I210 Ethernet (Copper OEM)",
   1400  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1401  1.299   msaitoh 
   1402  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_IT,
   1403  1.247   msaitoh 	  "I210 Ethernet (Copper IT)",
   1404  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1405  1.299   msaitoh 
   1406  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_WOF,
   1407  1.299   msaitoh 	  "I210 Ethernet (FLASH less)",
   1408  1.299   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1409  1.299   msaitoh 
   1410  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_FIBER,
   1411  1.247   msaitoh 	  "I210 Gigabit Ethernet (Fiber)",
   1412  1.291   msaitoh 	  WM_T_I210,		WMP_F_FIBER },
   1413  1.279   msaitoh 
   1414  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES,
   1415  1.247   msaitoh 	  "I210 Gigabit Ethernet (SERDES)",
   1416  1.247   msaitoh 	  WM_T_I210,		WMP_F_SERDES },
   1417  1.292   msaitoh 
   1418  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES_WOF,
   1419  1.299   msaitoh 	  "I210 Gigabit Ethernet (FLASH less)",
   1420  1.299   msaitoh 	  WM_T_I210,		WMP_F_SERDES },
   1421  1.299   msaitoh 
   1422  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SGMII,
   1423  1.247   msaitoh 	  "I210 Gigabit Ethernet (SGMII)",
   1424  1.292   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1425  1.292   msaitoh 
   1426  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I211_COPPER,
   1427  1.247   msaitoh 	  "I211 Ethernet (COPPER)",
   1428  1.291   msaitoh 	  WM_T_I211,		WMP_F_COPPER },
   1429  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_V,
   1430  1.249   msaitoh 	  "I217 V Ethernet Connection",
   1431  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1432  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_LM,
   1433  1.249   msaitoh 	  "I217 LM Ethernet Connection",
   1434  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1435  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V,
   1436  1.249   msaitoh 	  "I218 V Ethernet Connection",
   1437  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1438  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V2,
   1439  1.298   msaitoh 	  "I218 V Ethernet Connection",
   1440  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1441  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V3,
   1442  1.298   msaitoh 	  "I218 V Ethernet Connection",
   1443  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1444  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM,
   1445  1.249   msaitoh 	  "I218 LM Ethernet Connection",
   1446  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1447  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM2,
   1448  1.298   msaitoh 	  "I218 LM Ethernet Connection",
   1449  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1450  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM3,
   1451  1.298   msaitoh 	  "I218 LM Ethernet Connection",
   1452  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1453  1.392   msaitoh #if 0
   1454  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V,
   1455  1.392   msaitoh 	  "I219 V Ethernet Connection",
   1456  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1457  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V2,
   1458  1.392   msaitoh 	  "I219 V Ethernet Connection",
   1459  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1460  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V4,
   1461  1.422   msaitoh 	  "I219 V Ethernet Connection",
   1462  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1463  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V5,
   1464  1.422   msaitoh 	  "I219 V Ethernet Connection",
   1465  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1466  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM,
   1467  1.392   msaitoh 	  "I219 LM Ethernet Connection",
   1468  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1469  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM2,
   1470  1.392   msaitoh 	  "I219 LM Ethernet Connection",
   1471  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1472  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM3,
   1473  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1474  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1475  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM4,
   1476  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1477  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1478  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM5,
   1479  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1480  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1481  1.392   msaitoh #endif
   1482    1.1   thorpej 	{ 0,			0,
   1483    1.1   thorpej 	  NULL,
   1484    1.1   thorpej 	  0,			0 },
   1485    1.1   thorpej };
   1486    1.1   thorpej 
   1487  1.280   msaitoh /*
   1488  1.280   msaitoh  * Register read/write functions.
   1489  1.280   msaitoh  * Other than CSR_{READ|WRITE}().
   1490  1.280   msaitoh  */
   1491  1.280   msaitoh 
   1492   1.53   thorpej #if 0 /* Not currently used */
   1493  1.110     perry static inline uint32_t
   1494   1.53   thorpej wm_io_read(struct wm_softc *sc, int reg)
   1495   1.53   thorpej {
   1496   1.53   thorpej 
   1497   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
   1498   1.53   thorpej 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
   1499   1.53   thorpej }
   1500   1.53   thorpej #endif
   1501   1.53   thorpej 
   1502  1.110     perry static inline void
   1503   1.53   thorpej wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
   1504   1.53   thorpej {
   1505   1.53   thorpej 
   1506   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
   1507   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
   1508   1.53   thorpej }
   1509   1.53   thorpej 
   1510  1.110     perry static inline void
   1511  1.199   msaitoh wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off,
   1512  1.199   msaitoh     uint32_t data)
   1513  1.199   msaitoh {
   1514  1.199   msaitoh 	uint32_t regval;
   1515  1.199   msaitoh 	int i;
   1516  1.199   msaitoh 
   1517  1.199   msaitoh 	regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT);
   1518  1.199   msaitoh 
   1519  1.199   msaitoh 	CSR_WRITE(sc, reg, regval);
   1520  1.199   msaitoh 
   1521  1.199   msaitoh 	for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) {
   1522  1.199   msaitoh 		delay(5);
   1523  1.199   msaitoh 		if (CSR_READ(sc, reg) & SCTL_CTL_READY)
   1524  1.199   msaitoh 			break;
   1525  1.199   msaitoh 	}
   1526  1.199   msaitoh 	if (i == SCTL_CTL_POLL_TIMEOUT) {
   1527  1.280   msaitoh 		aprint_error("%s: WARNING:"
   1528  1.280   msaitoh 		    " i82575 reg 0x%08x setup did not indicate ready\n",
   1529  1.199   msaitoh 		    device_xname(sc->sc_dev), reg);
   1530  1.199   msaitoh 	}
   1531  1.199   msaitoh }
   1532  1.199   msaitoh 
   1533  1.199   msaitoh static inline void
   1534  1.110     perry wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
   1535   1.69   thorpej {
   1536   1.69   thorpej 	wa->wa_low = htole32(v & 0xffffffffU);
   1537   1.69   thorpej 	if (sizeof(bus_addr_t) == 8)
   1538   1.69   thorpej 		wa->wa_high = htole32((uint64_t) v >> 32);
   1539   1.69   thorpej 	else
   1540   1.69   thorpej 		wa->wa_high = 0;
   1541   1.69   thorpej }
   1542   1.69   thorpej 
   1543  1.280   msaitoh /*
   1544  1.352  knakahar  * Descriptor sync/init functions.
   1545  1.352  knakahar  */
   1546  1.352  knakahar static inline void
   1547  1.362  knakahar wm_cdtxsync(struct wm_txqueue *txq, int start, int num, int ops)
   1548  1.352  knakahar {
   1549  1.362  knakahar 	struct wm_softc *sc = txq->txq_sc;
   1550  1.352  knakahar 
   1551  1.352  knakahar 	/* If it will wrap around, sync to the end of the ring. */
   1552  1.356  knakahar 	if ((start + num) > WM_NTXDESC(txq)) {
   1553  1.356  knakahar 		bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
   1554  1.398  knakahar 		    WM_CDTXOFF(txq, start), txq->txq_descsize *
   1555  1.356  knakahar 		    (WM_NTXDESC(txq) - start), ops);
   1556  1.356  knakahar 		num -= (WM_NTXDESC(txq) - start);
   1557  1.352  knakahar 		start = 0;
   1558  1.352  knakahar 	}
   1559  1.352  knakahar 
   1560  1.352  knakahar 	/* Now sync whatever is left. */
   1561  1.356  knakahar 	bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
   1562  1.398  knakahar 	    WM_CDTXOFF(txq, start), txq->txq_descsize * num, ops);
   1563  1.352  knakahar }
   1564  1.352  knakahar 
   1565  1.352  knakahar static inline void
   1566  1.362  knakahar wm_cdrxsync(struct wm_rxqueue *rxq, int start, int ops)
   1567  1.352  knakahar {
   1568  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   1569  1.352  knakahar 
   1570  1.356  knakahar 	bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap,
   1571  1.466  knakahar 	    WM_CDRXOFF(rxq, start), rxq->rxq_descsize, ops);
   1572  1.352  knakahar }
   1573  1.352  knakahar 
   1574  1.352  knakahar static inline void
   1575  1.362  knakahar wm_init_rxdesc(struct wm_rxqueue *rxq, int start)
   1576  1.352  knakahar {
   1577  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   1578  1.356  knakahar 	struct wm_rxsoft *rxs = &rxq->rxq_soft[start];
   1579  1.352  knakahar 	struct mbuf *m = rxs->rxs_mbuf;
   1580  1.352  knakahar 
   1581  1.352  knakahar 	/*
   1582  1.352  knakahar 	 * Note: We scoot the packet forward 2 bytes in the buffer
   1583  1.352  knakahar 	 * so that the payload after the Ethernet header is aligned
   1584  1.352  knakahar 	 * to a 4-byte boundary.
   1585  1.352  knakahar 
   1586  1.352  knakahar 	 * XXX BRAINDAMAGE ALERT!
   1587  1.352  knakahar 	 * The stupid chip uses the same size for every buffer, which
   1588  1.352  knakahar 	 * is set in the Receive Control register.  We are using the 2K
   1589  1.352  knakahar 	 * size option, but what we REALLY want is (2K - 2)!  For this
   1590  1.352  knakahar 	 * reason, we can't "scoot" packets longer than the standard
   1591  1.352  knakahar 	 * Ethernet MTU.  On strict-alignment platforms, if the total
   1592  1.352  knakahar 	 * size exceeds (2K - 2) we set align_tweak to 0 and let
   1593  1.352  knakahar 	 * the upper layer copy the headers.
   1594  1.352  knakahar 	 */
   1595  1.352  knakahar 	m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak;
   1596  1.352  knakahar 
   1597  1.466  knakahar 	if (sc->sc_type == WM_T_82574) {
   1598  1.466  knakahar 		ext_rxdesc_t *rxd = &rxq->rxq_ext_descs[start];
   1599  1.466  knakahar 		rxd->erx_data.erxd_addr =
   1600  1.466  knakahar 			htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1601  1.466  knakahar 		rxd->erx_data.erxd_dd = 0;
   1602  1.466  knakahar 	} else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   1603  1.466  knakahar 		nq_rxdesc_t *rxd = &rxq->rxq_nq_descs[start];
   1604  1.466  knakahar 
   1605  1.466  knakahar 		rxd->nqrx_data.nrxd_paddr =
   1606  1.466  knakahar 			htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1607  1.466  knakahar 		/* Currently, split header is not supported. */
   1608  1.466  knakahar 		rxd->nqrx_data.nrxd_haddr = 0;
   1609  1.466  knakahar 	} else {
   1610  1.466  knakahar 		wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start];
   1611  1.466  knakahar 
   1612  1.466  knakahar 		wm_set_dma_addr(&rxd->wrx_addr,
   1613  1.466  knakahar 		    rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1614  1.466  knakahar 		rxd->wrx_len = 0;
   1615  1.466  knakahar 		rxd->wrx_cksum = 0;
   1616  1.466  knakahar 		rxd->wrx_status = 0;
   1617  1.466  knakahar 		rxd->wrx_errors = 0;
   1618  1.466  knakahar 		rxd->wrx_special = 0;
   1619  1.466  knakahar 	}
   1620  1.388   msaitoh 	wm_cdrxsync(rxq, start, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   1621  1.352  knakahar 
   1622  1.356  knakahar 	CSR_WRITE(sc, rxq->rxq_rdt_reg, start);
   1623  1.352  knakahar }
   1624  1.352  knakahar 
   1625  1.352  knakahar /*
   1626  1.280   msaitoh  * Device driver interface functions and commonly used functions.
   1627  1.280   msaitoh  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
   1628  1.280   msaitoh  */
   1629  1.280   msaitoh 
   1630  1.280   msaitoh /* Lookup supported device table */
   1631    1.1   thorpej static const struct wm_product *
   1632    1.1   thorpej wm_lookup(const struct pci_attach_args *pa)
   1633    1.1   thorpej {
   1634    1.1   thorpej 	const struct wm_product *wmp;
   1635    1.1   thorpej 
   1636    1.1   thorpej 	for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
   1637    1.1   thorpej 		if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
   1638    1.1   thorpej 		    PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
   1639  1.194   msaitoh 			return wmp;
   1640    1.1   thorpej 	}
   1641  1.194   msaitoh 	return NULL;
   1642    1.1   thorpej }
   1643    1.1   thorpej 
   1644  1.280   msaitoh /* The match function (ca_match) */
   1645   1.47   thorpej static int
   1646  1.160  christos wm_match(device_t parent, cfdata_t cf, void *aux)
   1647    1.1   thorpej {
   1648    1.1   thorpej 	struct pci_attach_args *pa = aux;
   1649    1.1   thorpej 
   1650    1.1   thorpej 	if (wm_lookup(pa) != NULL)
   1651  1.194   msaitoh 		return 1;
   1652    1.1   thorpej 
   1653  1.194   msaitoh 	return 0;
   1654    1.1   thorpej }
   1655    1.1   thorpej 
   1656  1.280   msaitoh /* The attach function (ca_attach) */
   1657   1.47   thorpej static void
   1658  1.157    dyoung wm_attach(device_t parent, device_t self, void *aux)
   1659    1.1   thorpej {
   1660  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   1661    1.1   thorpej 	struct pci_attach_args *pa = aux;
   1662  1.182   msaitoh 	prop_dictionary_t dict;
   1663    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1664    1.1   thorpej 	pci_chipset_tag_t pc = pa->pa_pc;
   1665  1.340  knakahar 	int counts[PCI_INTR_TYPE_SIZE];
   1666  1.340  knakahar 	pci_intr_type_t max_type;
   1667  1.160  christos 	const char *eetype, *xname;
   1668    1.1   thorpej 	bus_space_tag_t memt;
   1669    1.1   thorpej 	bus_space_handle_t memh;
   1670  1.201   msaitoh 	bus_size_t memsize;
   1671    1.1   thorpej 	int memh_valid;
   1672  1.201   msaitoh 	int i, error;
   1673    1.1   thorpej 	const struct wm_product *wmp;
   1674  1.115   thorpej 	prop_data_t ea;
   1675  1.115   thorpej 	prop_number_t pn;
   1676    1.1   thorpej 	uint8_t enaddr[ETHER_ADDR_LEN];
   1677  1.513   msaitoh 	char buf[256];
   1678  1.325   msaitoh 	uint16_t cfg1, cfg2, swdpin, nvmword;
   1679    1.1   thorpej 	pcireg_t preg, memtype;
   1680  1.203   msaitoh 	uint16_t eeprom_data, apme_mask;
   1681  1.273   msaitoh 	bool force_clear_smbi;
   1682  1.292   msaitoh 	uint32_t link_mode;
   1683   1.44   thorpej 	uint32_t reg;
   1684    1.1   thorpej 
   1685  1.160  christos 	sc->sc_dev = self;
   1686  1.272     ozaki 	callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS);
   1687  1.429  knakahar 	sc->sc_core_stopping = false;
   1688    1.1   thorpej 
   1689  1.292   msaitoh 	wmp = wm_lookup(pa);
   1690  1.292   msaitoh #ifdef DIAGNOSTIC
   1691    1.1   thorpej 	if (wmp == NULL) {
   1692    1.1   thorpej 		printf("\n");
   1693    1.1   thorpej 		panic("wm_attach: impossible");
   1694    1.1   thorpej 	}
   1695  1.292   msaitoh #endif
   1696  1.292   msaitoh 	sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags);
   1697    1.1   thorpej 
   1698  1.123  jmcneill 	sc->sc_pc = pa->pa_pc;
   1699  1.123  jmcneill 	sc->sc_pcitag = pa->pa_tag;
   1700  1.123  jmcneill 
   1701   1.69   thorpej 	if (pci_dma64_available(pa))
   1702   1.69   thorpej 		sc->sc_dmat = pa->pa_dmat64;
   1703   1.69   thorpej 	else
   1704   1.69   thorpej 		sc->sc_dmat = pa->pa_dmat;
   1705    1.1   thorpej 
   1706  1.304   msaitoh 	sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id);
   1707  1.388   msaitoh 	sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag,PCI_CLASS_REG));
   1708  1.226  drochner 	pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1);
   1709    1.1   thorpej 
   1710    1.1   thorpej 	sc->sc_type = wmp->wmp_type;
   1711  1.424   msaitoh 
   1712  1.424   msaitoh 	/* Set default function pointers */
   1713  1.424   msaitoh 	sc->phy.acquire = wm_get_null;
   1714  1.424   msaitoh 	sc->phy.release = wm_put_null;
   1715  1.447   msaitoh 	sc->phy.reset_delay_us = (sc->sc_type >= WM_T_82571) ? 100 : 10000;
   1716  1.424   msaitoh 
   1717   1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
   1718  1.192   msaitoh 		if (sc->sc_rev < 2) {
   1719  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1720  1.160  christos 			    "i82542 must be at least rev. 2\n");
   1721    1.1   thorpej 			return;
   1722    1.1   thorpej 		}
   1723  1.192   msaitoh 		if (sc->sc_rev < 3)
   1724   1.11   thorpej 			sc->sc_type = WM_T_82542_2_0;
   1725    1.1   thorpej 	}
   1726    1.1   thorpej 
   1727  1.335   msaitoh 	/*
   1728  1.335   msaitoh 	 * Disable MSI for Errata:
   1729  1.335   msaitoh 	 * "Message Signaled Interrupt Feature May Corrupt Write Transactions"
   1730  1.335   msaitoh 	 *
   1731  1.335   msaitoh 	 *  82544: Errata 25
   1732  1.335   msaitoh 	 *  82540: Errata  6 (easy to reproduce device timeout)
   1733  1.335   msaitoh 	 *  82545: Errata  4 (easy to reproduce device timeout)
   1734  1.335   msaitoh 	 *  82546: Errata 26 (easy to reproduce device timeout)
   1735  1.335   msaitoh 	 *  82541: Errata  7 (easy to reproduce device timeout)
   1736  1.337   msaitoh 	 *
   1737  1.337   msaitoh 	 * "Byte Enables 2 and 3 are not set on MSI writes"
   1738  1.337   msaitoh 	 *
   1739  1.337   msaitoh 	 *  82571 & 82572: Errata 63
   1740  1.335   msaitoh 	 */
   1741  1.337   msaitoh 	if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571)
   1742  1.337   msaitoh 	    || (sc->sc_type == WM_T_82572))
   1743  1.335   msaitoh 		pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY;
   1744  1.335   msaitoh 
   1745  1.199   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   1746  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   1747  1.265   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   1748  1.265   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
   1749  1.203   msaitoh 		sc->sc_flags |= WM_F_NEWQUEUE;
   1750  1.199   msaitoh 
   1751  1.184   msaitoh 	/* Set device properties (mactype) */
   1752  1.182   msaitoh 	dict = device_properties(sc->sc_dev);
   1753  1.182   msaitoh 	prop_dictionary_set_uint32(dict, "mactype", sc->sc_type);
   1754  1.182   msaitoh 
   1755    1.1   thorpej 	/*
   1756   1.53   thorpej 	 * Map the device.  All devices support memory-mapped acccess,
   1757   1.53   thorpej 	 * and it is really required for normal operation.
   1758    1.1   thorpej 	 */
   1759    1.1   thorpej 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
   1760    1.1   thorpej 	switch (memtype) {
   1761    1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
   1762    1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
   1763    1.1   thorpej 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
   1764  1.201   msaitoh 		    memtype, 0, &memt, &memh, NULL, &memsize) == 0);
   1765    1.1   thorpej 		break;
   1766    1.1   thorpej 	default:
   1767    1.1   thorpej 		memh_valid = 0;
   1768  1.189   msaitoh 		break;
   1769    1.1   thorpej 	}
   1770    1.1   thorpej 
   1771    1.1   thorpej 	if (memh_valid) {
   1772    1.1   thorpej 		sc->sc_st = memt;
   1773    1.1   thorpej 		sc->sc_sh = memh;
   1774  1.201   msaitoh 		sc->sc_ss = memsize;
   1775    1.1   thorpej 	} else {
   1776  1.160  christos 		aprint_error_dev(sc->sc_dev,
   1777  1.160  christos 		    "unable to map device registers\n");
   1778    1.1   thorpej 		return;
   1779    1.1   thorpej 	}
   1780    1.1   thorpej 
   1781   1.53   thorpej 	/*
   1782   1.53   thorpej 	 * In addition, i82544 and later support I/O mapped indirect
   1783   1.53   thorpej 	 * register access.  It is not desirable (nor supported in
   1784   1.53   thorpej 	 * this driver) to use it for normal operation, though it is
   1785   1.53   thorpej 	 * required to work around bugs in some chip versions.
   1786   1.53   thorpej 	 */
   1787   1.53   thorpej 	if (sc->sc_type >= WM_T_82544) {
   1788   1.53   thorpej 		/* First we have to find the I/O BAR. */
   1789   1.53   thorpej 		for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
   1790  1.241   msaitoh 			memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
   1791  1.241   msaitoh 			if (memtype == PCI_MAPREG_TYPE_IO)
   1792   1.53   thorpej 				break;
   1793  1.241   msaitoh 			if (PCI_MAPREG_MEM_TYPE(memtype) ==
   1794  1.241   msaitoh 			    PCI_MAPREG_MEM_TYPE_64BIT)
   1795  1.241   msaitoh 				i += 4;	/* skip high bits, too */
   1796   1.53   thorpej 		}
   1797  1.241   msaitoh 		if (i < PCI_MAPREG_END) {
   1798   1.88    briggs 			/*
   1799  1.218   msaitoh 			 * We found PCI_MAPREG_TYPE_IO. Note that 82580
   1800  1.218   msaitoh 			 * (and newer?) chip has no PCI_MAPREG_TYPE_IO.
   1801  1.218   msaitoh 			 * It's no problem because newer chips has no this
   1802  1.218   msaitoh 			 * bug.
   1803  1.218   msaitoh 			 *
   1804   1.88    briggs 			 * The i8254x doesn't apparently respond when the
   1805   1.88    briggs 			 * I/O BAR is 0, which looks somewhat like it's not
   1806   1.88    briggs 			 * been configured.
   1807   1.88    briggs 			 */
   1808   1.88    briggs 			preg = pci_conf_read(pc, pa->pa_tag, i);
   1809   1.88    briggs 			if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
   1810  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1811  1.160  christos 				    "WARNING: I/O BAR at zero.\n");
   1812   1.88    briggs 			} else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
   1813   1.53   thorpej 					0, &sc->sc_iot, &sc->sc_ioh,
   1814  1.212  jakllsch 					NULL, &sc->sc_ios) == 0) {
   1815   1.88    briggs 				sc->sc_flags |= WM_F_IOH_VALID;
   1816   1.88    briggs 			} else {
   1817  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1818  1.160  christos 				    "WARNING: unable to map I/O space\n");
   1819   1.88    briggs 			}
   1820   1.88    briggs 		}
   1821   1.88    briggs 
   1822   1.53   thorpej 	}
   1823   1.53   thorpej 
   1824   1.11   thorpej 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
   1825    1.1   thorpej 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
   1826    1.1   thorpej 	preg |= PCI_COMMAND_MASTER_ENABLE;
   1827   1.11   thorpej 	if (sc->sc_type < WM_T_82542_2_1)
   1828    1.1   thorpej 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
   1829    1.1   thorpej 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
   1830    1.1   thorpej 
   1831  1.122  christos 	/* power up chip */
   1832  1.157    dyoung 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
   1833  1.122  christos 	    NULL)) && error != EOPNOTSUPP) {
   1834  1.160  christos 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
   1835  1.122  christos 		return;
   1836    1.1   thorpej 	}
   1837    1.1   thorpej 
   1838  1.365  knakahar 	wm_adjust_qnum(sc, pci_msix_count(pa->pa_pc, pa->pa_tag));
   1839  1.365  knakahar 
   1840  1.340  knakahar 	/* Allocation settings */
   1841  1.340  knakahar 	max_type = PCI_INTR_TYPE_MSIX;
   1842  1.405  knakahar 	counts[PCI_INTR_TYPE_MSIX] = sc->sc_nqueues + 1;
   1843  1.340  knakahar 	counts[PCI_INTR_TYPE_MSI] = 1;
   1844  1.340  knakahar 	counts[PCI_INTR_TYPE_INTX] = 1;
   1845  1.508  knakahar 	/* overridden by disable flags */
   1846  1.508  knakahar 	if (wm_disable_msi != 0) {
   1847  1.508  knakahar 		counts[PCI_INTR_TYPE_MSI] = 0;
   1848  1.508  knakahar 		if (wm_disable_msix != 0) {
   1849  1.508  knakahar 			max_type = PCI_INTR_TYPE_INTX;
   1850  1.508  knakahar 			counts[PCI_INTR_TYPE_MSIX] = 0;
   1851  1.508  knakahar 		}
   1852  1.508  knakahar 	} else if (wm_disable_msix != 0) {
   1853  1.508  knakahar 		max_type = PCI_INTR_TYPE_MSI;
   1854  1.508  knakahar 		counts[PCI_INTR_TYPE_MSIX] = 0;
   1855  1.508  knakahar 	}
   1856  1.340  knakahar 
   1857  1.340  knakahar alloc_retry:
   1858  1.340  knakahar 	if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) {
   1859  1.340  knakahar 		aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n");
   1860  1.340  knakahar 		return;
   1861  1.340  knakahar 	}
   1862  1.340  knakahar 
   1863  1.416  knakahar 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) {
   1864  1.360  knakahar 		error = wm_setup_msix(sc);
   1865  1.360  knakahar 		if (error) {
   1866  1.360  knakahar 			pci_intr_release(pc, sc->sc_intrs,
   1867  1.360  knakahar 			    counts[PCI_INTR_TYPE_MSIX]);
   1868  1.360  knakahar 
   1869  1.360  knakahar 			/* Setup for MSI: Disable MSI-X */
   1870  1.360  knakahar 			max_type = PCI_INTR_TYPE_MSI;
   1871  1.360  knakahar 			counts[PCI_INTR_TYPE_MSI] = 1;
   1872  1.360  knakahar 			counts[PCI_INTR_TYPE_INTX] = 1;
   1873  1.360  knakahar 			goto alloc_retry;
   1874  1.335   msaitoh 		}
   1875  1.416  knakahar 	} else 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
   1876  1.375   msaitoh 		wm_adjust_qnum(sc, 0);	/* must not use multiqueue */
   1877  1.360  knakahar 		error = wm_setup_legacy(sc);
   1878  1.360  knakahar 		if (error) {
   1879  1.360  knakahar 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
   1880  1.360  knakahar 			    counts[PCI_INTR_TYPE_MSI]);
   1881  1.335   msaitoh 
   1882  1.360  knakahar 			/* The next try is for INTx: Disable MSI */
   1883  1.360  knakahar 			max_type = PCI_INTR_TYPE_INTX;
   1884  1.360  knakahar 			counts[PCI_INTR_TYPE_INTX] = 1;
   1885  1.360  knakahar 			goto alloc_retry;
   1886  1.360  knakahar 		}
   1887  1.340  knakahar 	} else {
   1888  1.375   msaitoh 		wm_adjust_qnum(sc, 0);	/* must not use multiqueue */
   1889  1.360  knakahar 		error = wm_setup_legacy(sc);
   1890  1.360  knakahar 		if (error) {
   1891  1.360  knakahar 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
   1892  1.360  knakahar 			    counts[PCI_INTR_TYPE_INTX]);
   1893  1.360  knakahar 			return;
   1894  1.335   msaitoh 		}
   1895  1.335   msaitoh 	}
   1896   1.52   thorpej 
   1897   1.52   thorpej 	/*
   1898  1.199   msaitoh 	 * Check the function ID (unit number of the chip).
   1899  1.199   msaitoh 	 */
   1900  1.199   msaitoh 	if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
   1901  1.199   msaitoh 	    || (sc->sc_type ==  WM_T_82571) || (sc->sc_type == WM_T_80003)
   1902  1.208   msaitoh 	    || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   1903  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   1904  1.265   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   1905  1.199   msaitoh 		sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
   1906  1.199   msaitoh 		    >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;
   1907  1.199   msaitoh 	else
   1908  1.199   msaitoh 		sc->sc_funcid = 0;
   1909  1.199   msaitoh 
   1910  1.199   msaitoh 	/*
   1911   1.52   thorpej 	 * Determine a few things about the bus we're connected to.
   1912   1.52   thorpej 	 */
   1913   1.52   thorpej 	if (sc->sc_type < WM_T_82543) {
   1914   1.52   thorpej 		/* We don't really know the bus characteristics here. */
   1915   1.52   thorpej 		sc->sc_bus_speed = 33;
   1916   1.73      tron 	} else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
   1917   1.73      tron 		/*
   1918   1.73      tron 		 * CSA (Communication Streaming Architecture) is about as fast
   1919   1.73      tron 		 * a 32-bit 66MHz PCI Bus.
   1920   1.73      tron 		 */
   1921   1.73      tron 		sc->sc_flags |= WM_F_CSA;
   1922   1.73      tron 		sc->sc_bus_speed = 66;
   1923  1.160  christos 		aprint_verbose_dev(sc->sc_dev,
   1924  1.160  christos 		    "Communication Streaming Architecture\n");
   1925   1.78   thorpej 		if (sc->sc_type == WM_T_82547) {
   1926  1.272     ozaki 			callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS);
   1927   1.78   thorpej 			callout_setfunc(&sc->sc_txfifo_ch,
   1928   1.78   thorpej 					wm_82547_txfifo_stall, sc);
   1929  1.160  christos 			aprint_verbose_dev(sc->sc_dev,
   1930  1.160  christos 			    "using 82547 Tx FIFO stall work-around\n");
   1931   1.78   thorpej 		}
   1932  1.116   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   1933  1.139    bouyer 		sc->sc_flags |= WM_F_PCIE;
   1934  1.167   msaitoh 		if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
   1935  1.190   msaitoh 		    && (sc->sc_type != WM_T_ICH10)
   1936  1.221   msaitoh 		    && (sc->sc_type != WM_T_PCH)
   1937  1.249   msaitoh 		    && (sc->sc_type != WM_T_PCH2)
   1938  1.392   msaitoh 		    && (sc->sc_type != WM_T_PCH_LPT)
   1939  1.392   msaitoh 		    && (sc->sc_type != WM_T_PCH_SPT)) {
   1940  1.221   msaitoh 			/* ICH* and PCH* have no PCIe capability registers */
   1941  1.199   msaitoh 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
   1942  1.199   msaitoh 				PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
   1943  1.199   msaitoh 				NULL) == 0)
   1944  1.199   msaitoh 				aprint_error_dev(sc->sc_dev,
   1945  1.199   msaitoh 				    "unable to find PCIe capability\n");
   1946  1.199   msaitoh 		}
   1947  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
   1948   1.73      tron 	} else {
   1949   1.52   thorpej 		reg = CSR_READ(sc, WMREG_STATUS);
   1950   1.52   thorpej 		if (reg & STATUS_BUS64)
   1951   1.52   thorpej 			sc->sc_flags |= WM_F_BUS64;
   1952  1.176   msaitoh 		if ((reg & STATUS_PCIX_MODE) != 0) {
   1953   1.54   thorpej 			pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
   1954   1.54   thorpej 
   1955   1.52   thorpej 			sc->sc_flags |= WM_F_PCIX;
   1956   1.54   thorpej 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
   1957  1.199   msaitoh 				PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0)
   1958  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1959  1.160  christos 				    "unable to find PCIX capability\n");
   1960   1.54   thorpej 			else if (sc->sc_type != WM_T_82545_3 &&
   1961   1.54   thorpej 				 sc->sc_type != WM_T_82546_3) {
   1962   1.54   thorpej 				/*
   1963   1.54   thorpej 				 * Work around a problem caused by the BIOS
   1964   1.54   thorpej 				 * setting the max memory read byte count
   1965   1.54   thorpej 				 * incorrectly.
   1966   1.54   thorpej 				 */
   1967   1.54   thorpej 				pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
   1968  1.248   msaitoh 				    sc->sc_pcixe_capoff + PCIX_CMD);
   1969   1.54   thorpej 				pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
   1970  1.248   msaitoh 				    sc->sc_pcixe_capoff + PCIX_STATUS);
   1971   1.54   thorpej 
   1972  1.388   msaitoh 				bytecnt = (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >>
   1973  1.248   msaitoh 				    PCIX_CMD_BYTECNT_SHIFT;
   1974  1.388   msaitoh 				maxb = (pcix_sts & PCIX_STATUS_MAXB_MASK) >>
   1975  1.248   msaitoh 				    PCIX_STATUS_MAXB_SHIFT;
   1976   1.54   thorpej 				if (bytecnt > maxb) {
   1977  1.160  christos 					aprint_verbose_dev(sc->sc_dev,
   1978  1.160  christos 					    "resetting PCI-X MMRBC: %d -> %d\n",
   1979   1.54   thorpej 					    512 << bytecnt, 512 << maxb);
   1980   1.54   thorpej 					pcix_cmd = (pcix_cmd &
   1981  1.248   msaitoh 					    ~PCIX_CMD_BYTECNT_MASK) |
   1982  1.248   msaitoh 					   (maxb << PCIX_CMD_BYTECNT_SHIFT);
   1983   1.54   thorpej 					pci_conf_write(pa->pa_pc, pa->pa_tag,
   1984  1.248   msaitoh 					    sc->sc_pcixe_capoff + PCIX_CMD,
   1985   1.54   thorpej 					    pcix_cmd);
   1986   1.54   thorpej 				}
   1987   1.54   thorpej 			}
   1988   1.54   thorpej 		}
   1989   1.52   thorpej 		/*
   1990   1.52   thorpej 		 * The quad port adapter is special; it has a PCIX-PCIX
   1991   1.52   thorpej 		 * bridge on the board, and can run the secondary bus at
   1992   1.52   thorpej 		 * a higher speed.
   1993   1.52   thorpej 		 */
   1994   1.52   thorpej 		if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
   1995   1.52   thorpej 			sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
   1996   1.52   thorpej 								      : 66;
   1997   1.52   thorpej 		} else if (sc->sc_flags & WM_F_PCIX) {
   1998   1.62   thorpej 			switch (reg & STATUS_PCIXSPD_MASK) {
   1999   1.52   thorpej 			case STATUS_PCIXSPD_50_66:
   2000   1.52   thorpej 				sc->sc_bus_speed = 66;
   2001   1.52   thorpej 				break;
   2002   1.52   thorpej 			case STATUS_PCIXSPD_66_100:
   2003   1.52   thorpej 				sc->sc_bus_speed = 100;
   2004   1.52   thorpej 				break;
   2005   1.52   thorpej 			case STATUS_PCIXSPD_100_133:
   2006   1.52   thorpej 				sc->sc_bus_speed = 133;
   2007   1.52   thorpej 				break;
   2008   1.52   thorpej 			default:
   2009  1.160  christos 				aprint_error_dev(sc->sc_dev,
   2010  1.158    cegger 				    "unknown PCIXSPD %d; assuming 66MHz\n",
   2011   1.62   thorpej 				    reg & STATUS_PCIXSPD_MASK);
   2012   1.52   thorpej 				sc->sc_bus_speed = 66;
   2013  1.189   msaitoh 				break;
   2014   1.52   thorpej 			}
   2015   1.52   thorpej 		} else
   2016   1.52   thorpej 			sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
   2017  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n",
   2018   1.52   thorpej 		    (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
   2019   1.52   thorpej 		    (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
   2020   1.52   thorpej 	}
   2021    1.1   thorpej 
   2022  1.127    bouyer 	/* clear interesting stat counters */
   2023  1.127    bouyer 	CSR_READ(sc, WMREG_COLC);
   2024  1.127    bouyer 	CSR_READ(sc, WMREG_RXERRC);
   2025  1.127    bouyer 
   2026  1.424   msaitoh 	if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)
   2027  1.424   msaitoh 	    || (sc->sc_type >= WM_T_ICH8))
   2028  1.424   msaitoh 		sc->sc_ich_phymtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2029  1.423   msaitoh 	if (sc->sc_type >= WM_T_ICH8)
   2030  1.423   msaitoh 		sc->sc_ich_nvmmtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2031    1.1   thorpej 
   2032  1.423   msaitoh 	/* Set PHY, NVM mutex related stuff */
   2033  1.185   msaitoh 	switch (sc->sc_type) {
   2034  1.185   msaitoh 	case WM_T_82542_2_0:
   2035  1.185   msaitoh 	case WM_T_82542_2_1:
   2036  1.185   msaitoh 	case WM_T_82543:
   2037  1.185   msaitoh 	case WM_T_82544:
   2038  1.185   msaitoh 		/* Microwire */
   2039  1.294   msaitoh 		sc->sc_nvm_wordsize = 64;
   2040  1.294   msaitoh 		sc->sc_nvm_addrbits = 6;
   2041  1.185   msaitoh 		break;
   2042  1.185   msaitoh 	case WM_T_82540:
   2043  1.185   msaitoh 	case WM_T_82545:
   2044  1.185   msaitoh 	case WM_T_82545_3:
   2045  1.185   msaitoh 	case WM_T_82546:
   2046  1.185   msaitoh 	case WM_T_82546_3:
   2047  1.185   msaitoh 		/* Microwire */
   2048  1.185   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   2049  1.294   msaitoh 		if (reg & EECD_EE_SIZE) {
   2050  1.294   msaitoh 			sc->sc_nvm_wordsize = 256;
   2051  1.294   msaitoh 			sc->sc_nvm_addrbits = 8;
   2052  1.294   msaitoh 		} else {
   2053  1.294   msaitoh 			sc->sc_nvm_wordsize = 64;
   2054  1.294   msaitoh 			sc->sc_nvm_addrbits = 6;
   2055  1.294   msaitoh 		}
   2056  1.275   msaitoh 		sc->sc_flags |= WM_F_LOCK_EECD;
   2057  1.185   msaitoh 		break;
   2058  1.185   msaitoh 	case WM_T_82541:
   2059  1.185   msaitoh 	case WM_T_82541_2:
   2060  1.185   msaitoh 	case WM_T_82547:
   2061  1.185   msaitoh 	case WM_T_82547_2:
   2062  1.313   msaitoh 		sc->sc_flags |= WM_F_LOCK_EECD;
   2063  1.185   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   2064  1.185   msaitoh 		if (reg & EECD_EE_TYPE) {
   2065  1.185   msaitoh 			/* SPI */
   2066  1.294   msaitoh 			sc->sc_flags |= WM_F_EEPROM_SPI;
   2067  1.294   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2068  1.294   msaitoh 		} else {
   2069  1.185   msaitoh 			/* Microwire */
   2070  1.294   msaitoh 			if ((reg & EECD_EE_ABITS) != 0) {
   2071  1.294   msaitoh 				sc->sc_nvm_wordsize = 256;
   2072  1.294   msaitoh 				sc->sc_nvm_addrbits = 8;
   2073  1.294   msaitoh 			} else {
   2074  1.294   msaitoh 				sc->sc_nvm_wordsize = 64;
   2075  1.294   msaitoh 				sc->sc_nvm_addrbits = 6;
   2076  1.294   msaitoh 			}
   2077  1.294   msaitoh 		}
   2078  1.185   msaitoh 		break;
   2079  1.185   msaitoh 	case WM_T_82571:
   2080  1.185   msaitoh 	case WM_T_82572:
   2081  1.185   msaitoh 		/* SPI */
   2082  1.294   msaitoh 		sc->sc_flags |= WM_F_EEPROM_SPI;
   2083  1.294   msaitoh 		wm_nvm_set_addrbits_size_eecd(sc);
   2084  1.275   msaitoh 		sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM;
   2085  1.424   msaitoh 		sc->phy.acquire = wm_get_swsm_semaphore;
   2086  1.424   msaitoh 		sc->phy.release = wm_put_swsm_semaphore;
   2087  1.185   msaitoh 		break;
   2088  1.185   msaitoh 	case WM_T_82573:
   2089  1.185   msaitoh 	case WM_T_82574:
   2090  1.185   msaitoh 	case WM_T_82583:
   2091  1.424   msaitoh 		if (sc->sc_type == WM_T_82573) {
   2092  1.424   msaitoh 			sc->sc_flags |= WM_F_LOCK_SWSM;
   2093  1.424   msaitoh 			sc->phy.acquire = wm_get_swsm_semaphore;
   2094  1.424   msaitoh 			sc->phy.release = wm_put_swsm_semaphore;
   2095  1.424   msaitoh 		} else {
   2096  1.424   msaitoh 			sc->sc_flags |= WM_F_LOCK_EXTCNF;
   2097  1.424   msaitoh 			/* Both PHY and NVM use the same semaphore. */
   2098  1.424   msaitoh 			sc->phy.acquire
   2099  1.424   msaitoh 			    = wm_get_swfwhw_semaphore;
   2100  1.424   msaitoh 			sc->phy.release
   2101  1.424   msaitoh 			    = wm_put_swfwhw_semaphore;
   2102  1.424   msaitoh 		}
   2103  1.294   msaitoh 		if (wm_nvm_is_onboard_eeprom(sc) == 0) {
   2104  1.185   msaitoh 			sc->sc_flags |= WM_F_EEPROM_FLASH;
   2105  1.294   msaitoh 			sc->sc_nvm_wordsize = 2048;
   2106  1.294   msaitoh 		} else {
   2107  1.185   msaitoh 			/* SPI */
   2108  1.294   msaitoh 			sc->sc_flags |= WM_F_EEPROM_SPI;
   2109  1.294   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2110  1.185   msaitoh 		}
   2111  1.185   msaitoh 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
   2112  1.185   msaitoh 		break;
   2113  1.199   msaitoh 	case WM_T_82575:
   2114  1.199   msaitoh 	case WM_T_82576:
   2115  1.199   msaitoh 	case WM_T_82580:
   2116  1.228   msaitoh 	case WM_T_I350:
   2117  1.278   msaitoh 	case WM_T_I354:
   2118  1.185   msaitoh 	case WM_T_80003:
   2119  1.185   msaitoh 		/* SPI */
   2120  1.294   msaitoh 		sc->sc_flags |= WM_F_EEPROM_SPI;
   2121  1.294   msaitoh 		wm_nvm_set_addrbits_size_eecd(sc);
   2122  1.275   msaitoh 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW
   2123  1.275   msaitoh 		    | WM_F_LOCK_SWSM;
   2124  1.424   msaitoh 		sc->phy.acquire = wm_get_phy_82575;
   2125  1.424   msaitoh 		sc->phy.release = wm_put_phy_82575;
   2126  1.185   msaitoh 		break;
   2127  1.185   msaitoh 	case WM_T_ICH8:
   2128  1.185   msaitoh 	case WM_T_ICH9:
   2129  1.185   msaitoh 	case WM_T_ICH10:
   2130  1.190   msaitoh 	case WM_T_PCH:
   2131  1.221   msaitoh 	case WM_T_PCH2:
   2132  1.249   msaitoh 	case WM_T_PCH_LPT:
   2133  1.185   msaitoh 		/* FLASH */
   2134  1.276   msaitoh 		sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF;
   2135  1.294   msaitoh 		sc->sc_nvm_wordsize = 2048;
   2136  1.388   msaitoh 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,WM_ICH8_FLASH);
   2137  1.139    bouyer 		if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
   2138  1.336   msaitoh 		    &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) {
   2139  1.160  christos 			aprint_error_dev(sc->sc_dev,
   2140  1.160  christos 			    "can't map FLASH registers\n");
   2141  1.353  knakahar 			goto out;
   2142  1.139    bouyer 		}
   2143  1.185   msaitoh 		reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
   2144  1.185   msaitoh 		sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *
   2145  1.388   msaitoh 		    ICH_FLASH_SECTOR_SIZE;
   2146  1.199   msaitoh 		sc->sc_ich8_flash_bank_size =
   2147  1.199   msaitoh 		    ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
   2148  1.388   msaitoh 		sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK);
   2149  1.139    bouyer 		sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
   2150  1.139    bouyer 		sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
   2151  1.392   msaitoh 		sc->sc_flashreg_offset = 0;
   2152  1.424   msaitoh 		sc->phy.acquire = wm_get_swflag_ich8lan;
   2153  1.424   msaitoh 		sc->phy.release = wm_put_swflag_ich8lan;
   2154  1.392   msaitoh 		break;
   2155  1.392   msaitoh 	case WM_T_PCH_SPT:
   2156  1.392   msaitoh 		/* SPT has no GFPREG; flash registers mapped through BAR0 */
   2157  1.392   msaitoh 		sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF;
   2158  1.392   msaitoh 		sc->sc_flasht = sc->sc_st;
   2159  1.392   msaitoh 		sc->sc_flashh = sc->sc_sh;
   2160  1.392   msaitoh 		sc->sc_ich8_flash_base = 0;
   2161  1.392   msaitoh 		sc->sc_nvm_wordsize =
   2162  1.392   msaitoh 			(((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
   2163  1.392   msaitoh 			* NVM_SIZE_MULTIPLIER;
   2164  1.392   msaitoh 		/* It is size in bytes, we want words */
   2165  1.392   msaitoh 		sc->sc_nvm_wordsize /= 2;
   2166  1.392   msaitoh 		/* assume 2 banks */
   2167  1.392   msaitoh 		sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2;
   2168  1.392   msaitoh 		sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET;
   2169  1.424   msaitoh 		sc->phy.acquire = wm_get_swflag_ich8lan;
   2170  1.424   msaitoh 		sc->phy.release = wm_put_swflag_ich8lan;
   2171  1.185   msaitoh 		break;
   2172  1.247   msaitoh 	case WM_T_I210:
   2173  1.247   msaitoh 	case WM_T_I211:
   2174  1.321   msaitoh 		if (wm_nvm_get_flash_presence_i210(sc)) {
   2175  1.321   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2176  1.321   msaitoh 			sc->sc_flags |= WM_F_EEPROM_FLASH_HW;
   2177  1.424   msaitoh 			sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
   2178  1.321   msaitoh 		} else {
   2179  1.321   msaitoh 			sc->sc_nvm_wordsize = INVM_SIZE;
   2180  1.321   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVM;
   2181  1.321   msaitoh 		}
   2182  1.424   msaitoh 		sc->sc_flags |= WM_F_LOCK_SWFW | WM_F_LOCK_SWSM;
   2183  1.424   msaitoh 		sc->phy.acquire = wm_get_phy_82575;
   2184  1.424   msaitoh 		sc->phy.release = wm_put_phy_82575;
   2185  1.247   msaitoh 		break;
   2186  1.185   msaitoh 	default:
   2187  1.185   msaitoh 		break;
   2188   1.44   thorpej 	}
   2189  1.112     gavan 
   2190  1.423   msaitoh 	/* Reset the chip to a known state. */
   2191  1.423   msaitoh 	wm_reset(sc);
   2192  1.423   msaitoh 
   2193  1.273   msaitoh 	/* Ensure the SMBI bit is clear before first NVM or PHY access */
   2194  1.273   msaitoh 	switch (sc->sc_type) {
   2195  1.273   msaitoh 	case WM_T_82571:
   2196  1.273   msaitoh 	case WM_T_82572:
   2197  1.273   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM2);
   2198  1.310   msaitoh 		if ((reg & SWSM2_LOCK) == 0) {
   2199  1.273   msaitoh 			CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);
   2200  1.273   msaitoh 			force_clear_smbi = true;
   2201  1.273   msaitoh 		} else
   2202  1.273   msaitoh 			force_clear_smbi = false;
   2203  1.273   msaitoh 		break;
   2204  1.284   msaitoh 	case WM_T_82573:
   2205  1.284   msaitoh 	case WM_T_82574:
   2206  1.284   msaitoh 	case WM_T_82583:
   2207  1.284   msaitoh 		force_clear_smbi = true;
   2208  1.284   msaitoh 		break;
   2209  1.273   msaitoh 	default:
   2210  1.284   msaitoh 		force_clear_smbi = false;
   2211  1.273   msaitoh 		break;
   2212  1.273   msaitoh 	}
   2213  1.273   msaitoh 	if (force_clear_smbi) {
   2214  1.273   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   2215  1.284   msaitoh 		if ((reg & SWSM_SMBI) != 0)
   2216  1.273   msaitoh 			aprint_error_dev(sc->sc_dev,
   2217  1.273   msaitoh 			    "Please update the Bootagent\n");
   2218  1.273   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI);
   2219  1.273   msaitoh 	}
   2220  1.273   msaitoh 
   2221  1.112     gavan 	/*
   2222  1.112     gavan 	 * Defer printing the EEPROM type until after verifying the checksum
   2223  1.112     gavan 	 * This allows the EEPROM type to be printed correctly in the case
   2224  1.112     gavan 	 * that no EEPROM is attached.
   2225  1.112     gavan 	 */
   2226  1.185   msaitoh 	/*
   2227  1.185   msaitoh 	 * Validate the EEPROM checksum. If the checksum fails, flag
   2228  1.185   msaitoh 	 * this for later, so we can fail future reads from the EEPROM.
   2229  1.185   msaitoh 	 */
   2230  1.280   msaitoh 	if (wm_nvm_validate_checksum(sc)) {
   2231  1.169   msaitoh 		/*
   2232  1.185   msaitoh 		 * Read twice again because some PCI-e parts fail the
   2233  1.185   msaitoh 		 * first check due to the link being in sleep state.
   2234  1.169   msaitoh 		 */
   2235  1.280   msaitoh 		if (wm_nvm_validate_checksum(sc))
   2236  1.185   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVALID;
   2237  1.169   msaitoh 	}
   2238  1.185   msaitoh 
   2239  1.184   msaitoh 	/* Set device properties (macflags) */
   2240  1.183   msaitoh 	prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags);
   2241  1.112     gavan 
   2242  1.113     gavan 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   2243  1.328   msaitoh 		aprint_verbose_dev(sc->sc_dev, "No EEPROM");
   2244  1.294   msaitoh 	else {
   2245  1.294   msaitoh 		aprint_verbose_dev(sc->sc_dev, "%u words ",
   2246  1.294   msaitoh 		    sc->sc_nvm_wordsize);
   2247  1.321   msaitoh 		if (sc->sc_flags & WM_F_EEPROM_INVM)
   2248  1.328   msaitoh 			aprint_verbose("iNVM");
   2249  1.321   msaitoh 		else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW)
   2250  1.328   msaitoh 			aprint_verbose("FLASH(HW)");
   2251  1.321   msaitoh 		else if (sc->sc_flags & WM_F_EEPROM_FLASH)
   2252  1.328   msaitoh 			aprint_verbose("FLASH");
   2253  1.321   msaitoh 		else {
   2254  1.294   msaitoh 			if (sc->sc_flags & WM_F_EEPROM_SPI)
   2255  1.294   msaitoh 				eetype = "SPI";
   2256  1.294   msaitoh 			else
   2257  1.294   msaitoh 				eetype = "MicroWire";
   2258  1.328   msaitoh 			aprint_verbose("(%d address bits) %s EEPROM",
   2259  1.294   msaitoh 			    sc->sc_nvm_addrbits, eetype);
   2260  1.294   msaitoh 		}
   2261  1.112     gavan 	}
   2262  1.328   msaitoh 	wm_nvm_version(sc);
   2263  1.328   msaitoh 	aprint_verbose("\n");
   2264  1.112     gavan 
   2265  1.329   msaitoh 	/* Check for I21[01] PLL workaround */
   2266  1.329   msaitoh 	if (sc->sc_type == WM_T_I210)
   2267  1.329   msaitoh 		sc->sc_flags |= WM_F_PLL_WA_I210;
   2268  1.329   msaitoh 	if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) {
   2269  1.329   msaitoh 		/* NVM image release 3.25 has a workaround */
   2270  1.344   msaitoh 		if ((sc->sc_nvm_ver_major < 3)
   2271  1.329   msaitoh 		    || ((sc->sc_nvm_ver_major == 3)
   2272  1.344   msaitoh 			&& (sc->sc_nvm_ver_minor < 25))) {
   2273  1.329   msaitoh 			aprint_verbose_dev(sc->sc_dev,
   2274  1.329   msaitoh 			    "ROM image version %d.%d is older than 3.25\n",
   2275  1.329   msaitoh 			    sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor);
   2276  1.329   msaitoh 			sc->sc_flags |= WM_F_PLL_WA_I210;
   2277  1.329   msaitoh 		}
   2278  1.329   msaitoh 	}
   2279  1.329   msaitoh 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
   2280  1.329   msaitoh 		wm_pll_workaround_i210(sc);
   2281  1.329   msaitoh 
   2282  1.379   msaitoh 	wm_get_wakeup(sc);
   2283  1.446   msaitoh 
   2284  1.446   msaitoh 	/* Non-AMT based hardware can now take control from firmware */
   2285  1.446   msaitoh 	if ((sc->sc_flags & WM_F_HAS_AMT) == 0)
   2286  1.446   msaitoh 		wm_get_hw_control(sc);
   2287  1.379   msaitoh 
   2288  1.113     gavan 	/*
   2289  1.113     gavan 	 * Read the Ethernet address from the EEPROM, if not first found
   2290  1.113     gavan 	 * in device properties.
   2291  1.113     gavan 	 */
   2292  1.195    martin 	ea = prop_dictionary_get(dict, "mac-address");
   2293  1.115   thorpej 	if (ea != NULL) {
   2294  1.115   thorpej 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
   2295  1.115   thorpej 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
   2296  1.115   thorpej 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
   2297  1.115   thorpej 	} else {
   2298  1.210   msaitoh 		if (wm_read_mac_addr(sc, enaddr) != 0) {
   2299  1.160  christos 			aprint_error_dev(sc->sc_dev,
   2300  1.160  christos 			    "unable to read Ethernet address\n");
   2301  1.353  knakahar 			goto out;
   2302  1.210   msaitoh 		}
   2303   1.17   thorpej 	}
   2304   1.17   thorpej 
   2305  1.160  christos 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
   2306    1.1   thorpej 	    ether_sprintf(enaddr));
   2307    1.1   thorpej 
   2308    1.1   thorpej 	/*
   2309    1.1   thorpej 	 * Read the config info from the EEPROM, and set up various
   2310    1.1   thorpej 	 * bits in the control registers based on their contents.
   2311    1.1   thorpej 	 */
   2312  1.182   msaitoh 	pn = prop_dictionary_get(dict, "i82543-cfg1");
   2313  1.115   thorpej 	if (pn != NULL) {
   2314  1.115   thorpej 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2315  1.115   thorpej 		cfg1 = (uint16_t) prop_number_integer_value(pn);
   2316  1.115   thorpej 	} else {
   2317  1.293   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {
   2318  1.160  christos 			aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
   2319  1.353  knakahar 			goto out;
   2320  1.113     gavan 		}
   2321   1.51   thorpej 	}
   2322  1.115   thorpej 
   2323  1.182   msaitoh 	pn = prop_dictionary_get(dict, "i82543-cfg2");
   2324  1.115   thorpej 	if (pn != NULL) {
   2325  1.115   thorpej 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2326  1.115   thorpej 		cfg2 = (uint16_t) prop_number_integer_value(pn);
   2327  1.115   thorpej 	} else {
   2328  1.293   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) {
   2329  1.160  christos 			aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
   2330  1.353  knakahar 			goto out;
   2331  1.113     gavan 		}
   2332   1.51   thorpej 	}
   2333  1.115   thorpej 
   2334  1.203   msaitoh 	/* check for WM_F_WOL */
   2335  1.203   msaitoh 	switch (sc->sc_type) {
   2336  1.203   msaitoh 	case WM_T_82542_2_0:
   2337  1.203   msaitoh 	case WM_T_82542_2_1:
   2338  1.203   msaitoh 	case WM_T_82543:
   2339  1.203   msaitoh 		/* dummy? */
   2340  1.203   msaitoh 		eeprom_data = 0;
   2341  1.293   msaitoh 		apme_mask = NVM_CFG3_APME;
   2342  1.203   msaitoh 		break;
   2343  1.203   msaitoh 	case WM_T_82544:
   2344  1.293   msaitoh 		apme_mask = NVM_CFG2_82544_APM_EN;
   2345  1.203   msaitoh 		eeprom_data = cfg2;
   2346  1.203   msaitoh 		break;
   2347  1.203   msaitoh 	case WM_T_82546:
   2348  1.203   msaitoh 	case WM_T_82546_3:
   2349  1.203   msaitoh 	case WM_T_82571:
   2350  1.203   msaitoh 	case WM_T_82572:
   2351  1.203   msaitoh 	case WM_T_82573:
   2352  1.203   msaitoh 	case WM_T_82574:
   2353  1.203   msaitoh 	case WM_T_82583:
   2354  1.203   msaitoh 	case WM_T_80003:
   2355  1.203   msaitoh 	default:
   2356  1.293   msaitoh 		apme_mask = NVM_CFG3_APME;
   2357  1.293   msaitoh 		wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB
   2358  1.293   msaitoh 		    : NVM_OFF_CFG3_PORTA, 1, &eeprom_data);
   2359  1.203   msaitoh 		break;
   2360  1.203   msaitoh 	case WM_T_82575:
   2361  1.203   msaitoh 	case WM_T_82576:
   2362  1.203   msaitoh 	case WM_T_82580:
   2363  1.228   msaitoh 	case WM_T_I350:
   2364  1.265   msaitoh 	case WM_T_I354: /* XXX ok? */
   2365  1.203   msaitoh 	case WM_T_ICH8:
   2366  1.203   msaitoh 	case WM_T_ICH9:
   2367  1.203   msaitoh 	case WM_T_ICH10:
   2368  1.203   msaitoh 	case WM_T_PCH:
   2369  1.221   msaitoh 	case WM_T_PCH2:
   2370  1.249   msaitoh 	case WM_T_PCH_LPT:
   2371  1.392   msaitoh 	case WM_T_PCH_SPT:
   2372  1.228   msaitoh 		/* XXX The funcid should be checked on some devices */
   2373  1.203   msaitoh 		apme_mask = WUC_APME;
   2374  1.203   msaitoh 		eeprom_data = CSR_READ(sc, WMREG_WUC);
   2375  1.203   msaitoh 		break;
   2376  1.203   msaitoh 	}
   2377  1.203   msaitoh 
   2378  1.203   msaitoh 	/* Check for WM_F_WOL flag after the setting of the EEPROM stuff */
   2379  1.203   msaitoh 	if ((eeprom_data & apme_mask) != 0)
   2380  1.203   msaitoh 		sc->sc_flags |= WM_F_WOL;
   2381  1.203   msaitoh 
   2382  1.325   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) {
   2383  1.325   msaitoh 		/* Check NVM for autonegotiation */
   2384  1.325   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) {
   2385  1.325   msaitoh 			if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0)
   2386  1.325   msaitoh 				sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO;
   2387  1.325   msaitoh 		}
   2388  1.325   msaitoh 	}
   2389  1.325   msaitoh 
   2390  1.203   msaitoh 	/*
   2391  1.203   msaitoh 	 * XXX need special handling for some multiple port cards
   2392  1.203   msaitoh 	 * to disable a paticular port.
   2393  1.203   msaitoh 	 */
   2394  1.203   msaitoh 
   2395   1.51   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2396  1.182   msaitoh 		pn = prop_dictionary_get(dict, "i82543-swdpin");
   2397  1.115   thorpej 		if (pn != NULL) {
   2398  1.115   thorpej 			KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2399  1.115   thorpej 			swdpin = (uint16_t) prop_number_integer_value(pn);
   2400  1.115   thorpej 		} else {
   2401  1.293   msaitoh 			if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) {
   2402  1.160  christos 				aprint_error_dev(sc->sc_dev,
   2403  1.160  christos 				    "unable to read SWDPIN\n");
   2404  1.353  knakahar 				goto out;
   2405  1.113     gavan 			}
   2406   1.51   thorpej 		}
   2407   1.51   thorpej 	}
   2408    1.1   thorpej 
   2409  1.293   msaitoh 	if (cfg1 & NVM_CFG1_ILOS)
   2410    1.1   thorpej 		sc->sc_ctrl |= CTRL_ILOS;
   2411  1.325   msaitoh 
   2412  1.325   msaitoh 	/*
   2413  1.325   msaitoh 	 * XXX
   2414  1.325   msaitoh 	 * This code isn't correct because pin 2 and 3 are located
   2415  1.325   msaitoh 	 * in different position on newer chips. Check all datasheet.
   2416  1.325   msaitoh 	 *
   2417  1.325   msaitoh 	 * Until resolve this problem, check if a chip < 82580
   2418  1.325   msaitoh 	 */
   2419  1.325   msaitoh 	if (sc->sc_type <= WM_T_82580) {
   2420  1.325   msaitoh 		if (sc->sc_type >= WM_T_82544) {
   2421  1.325   msaitoh 			sc->sc_ctrl |=
   2422  1.325   msaitoh 			    ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
   2423  1.325   msaitoh 			    CTRL_SWDPIO_SHIFT;
   2424  1.325   msaitoh 			sc->sc_ctrl |=
   2425  1.325   msaitoh 			    ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
   2426  1.325   msaitoh 			    CTRL_SWDPINS_SHIFT;
   2427  1.325   msaitoh 		} else {
   2428  1.325   msaitoh 			sc->sc_ctrl |=
   2429  1.325   msaitoh 			    ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<
   2430  1.325   msaitoh 			    CTRL_SWDPIO_SHIFT;
   2431  1.325   msaitoh 		}
   2432  1.325   msaitoh 	}
   2433  1.325   msaitoh 
   2434  1.325   msaitoh 	/* XXX For other than 82580? */
   2435  1.325   msaitoh 	if (sc->sc_type == WM_T_82580) {
   2436  1.325   msaitoh 		wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword);
   2437  1.389   msaitoh 		if (nvmword & __BIT(13))
   2438  1.325   msaitoh 			sc->sc_ctrl |= CTRL_ILOS;
   2439    1.1   thorpej 	}
   2440    1.1   thorpej 
   2441    1.1   thorpej #if 0
   2442   1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2443  1.293   msaitoh 		if (cfg1 & NVM_CFG1_IPS0)
   2444    1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
   2445  1.293   msaitoh 		if (cfg1 & NVM_CFG1_IPS1)
   2446    1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
   2447    1.1   thorpej 		sc->sc_ctrl_ext |=
   2448  1.293   msaitoh 		    ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
   2449    1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
   2450    1.1   thorpej 		sc->sc_ctrl_ext |=
   2451  1.293   msaitoh 		    ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
   2452    1.1   thorpej 		    CTRL_EXT_SWDPINS_SHIFT;
   2453    1.1   thorpej 	} else {
   2454    1.1   thorpej 		sc->sc_ctrl_ext |=
   2455  1.293   msaitoh 		    ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) <<
   2456    1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
   2457    1.1   thorpej 	}
   2458    1.1   thorpej #endif
   2459    1.1   thorpej 
   2460    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2461    1.1   thorpej #if 0
   2462    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   2463    1.1   thorpej #endif
   2464    1.1   thorpej 
   2465  1.192   msaitoh 	if (sc->sc_type == WM_T_PCH) {
   2466  1.192   msaitoh 		uint16_t val;
   2467  1.192   msaitoh 
   2468  1.192   msaitoh 		/* Save the NVM K1 bit setting */
   2469  1.293   msaitoh 		wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val);
   2470  1.192   msaitoh 
   2471  1.293   msaitoh 		if ((val & NVM_K1_CONFIG_ENABLE) != 0)
   2472  1.192   msaitoh 			sc->sc_nvm_k1_enabled = 1;
   2473  1.192   msaitoh 		else
   2474  1.192   msaitoh 			sc->sc_nvm_k1_enabled = 0;
   2475  1.192   msaitoh 	}
   2476  1.192   msaitoh 
   2477    1.1   thorpej 	/*
   2478  1.199   msaitoh 	 * Determine if we're TBI,GMII or SGMII mode, and initialize the
   2479    1.1   thorpej 	 * media structures accordingly.
   2480    1.1   thorpej 	 */
   2481  1.144   msaitoh 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
   2482  1.190   msaitoh 	    || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
   2483  1.249   msaitoh 	    || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
   2484  1.392   msaitoh 	    || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573
   2485  1.185   msaitoh 	    || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
   2486  1.139    bouyer 		/* STATUS_TBIMODE reserved/reused, can't rely on it */
   2487  1.191   msaitoh 		wm_gmii_mediainit(sc, wmp->wmp_product);
   2488  1.457   msaitoh 	} else if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   2489  1.457   msaitoh 	    || (sc->sc_type ==WM_T_82580) || (sc->sc_type ==WM_T_I350)
   2490  1.457   msaitoh 	    || (sc->sc_type ==WM_T_I354) || (sc->sc_type ==WM_T_I210)
   2491  1.457   msaitoh 	    || (sc->sc_type ==WM_T_I211)) {
   2492  1.457   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   2493  1.457   msaitoh 		link_mode = reg & CTRL_EXT_LINK_MODE_MASK;
   2494  1.457   msaitoh 		switch (link_mode) {
   2495  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_1000KX:
   2496  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "1000KX\n");
   2497  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_SERDES;
   2498  1.457   msaitoh 			break;
   2499  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_SGMII:
   2500  1.457   msaitoh 			if (wm_sgmii_uses_mdio(sc)) {
   2501  1.457   msaitoh 				aprint_verbose_dev(sc->sc_dev,
   2502  1.457   msaitoh 				    "SGMII(MDIO)\n");
   2503  1.457   msaitoh 				sc->sc_flags |= WM_F_SGMII;
   2504  1.457   msaitoh 				sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2505  1.199   msaitoh 				break;
   2506  1.457   msaitoh 			}
   2507  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n");
   2508  1.457   msaitoh 			/*FALLTHROUGH*/
   2509  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_PCIE_SERDES:
   2510  1.457   msaitoh 			sc->sc_mediatype = wm_sfp_get_media_type(sc);
   2511  1.457   msaitoh 			if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) {
   2512  1.457   msaitoh 				if (link_mode
   2513  1.457   msaitoh 				    == CTRL_EXT_LINK_MODE_SGMII) {
   2514  1.457   msaitoh 					sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2515  1.265   msaitoh 					sc->sc_flags |= WM_F_SGMII;
   2516  1.457   msaitoh 				} else {
   2517  1.457   msaitoh 					sc->sc_mediatype = WM_MEDIATYPE_SERDES;
   2518  1.292   msaitoh 					aprint_verbose_dev(sc->sc_dev,
   2519  1.292   msaitoh 					    "SERDES\n");
   2520  1.457   msaitoh 				}
   2521  1.457   msaitoh 				break;
   2522  1.457   msaitoh 			}
   2523  1.457   msaitoh 			if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   2524  1.457   msaitoh 				aprint_verbose_dev(sc->sc_dev, "SERDES\n");
   2525  1.292   msaitoh 
   2526  1.457   msaitoh 			/* Change current link mode setting */
   2527  1.457   msaitoh 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
   2528  1.457   msaitoh 			switch (sc->sc_mediatype) {
   2529  1.457   msaitoh 			case WM_MEDIATYPE_COPPER:
   2530  1.457   msaitoh 				reg |= CTRL_EXT_LINK_MODE_SGMII;
   2531  1.457   msaitoh 				break;
   2532  1.457   msaitoh 			case WM_MEDIATYPE_SERDES:
   2533  1.457   msaitoh 				reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES;
   2534  1.199   msaitoh 				break;
   2535  1.199   msaitoh 			default:
   2536  1.199   msaitoh 				break;
   2537  1.199   msaitoh 			}
   2538  1.292   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   2539  1.199   msaitoh 			break;
   2540  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_GMII:
   2541  1.199   msaitoh 		default:
   2542  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "Copper\n");
   2543  1.311   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2544  1.457   msaitoh 			break;
   2545  1.457   msaitoh 		}
   2546  1.457   msaitoh 
   2547  1.457   msaitoh 		reg &= ~CTRL_EXT_I2C_ENA;
   2548  1.457   msaitoh 		if ((sc->sc_flags & WM_F_SGMII) != 0)
   2549  1.457   msaitoh 			reg |= CTRL_EXT_I2C_ENA;
   2550  1.457   msaitoh 		else
   2551  1.457   msaitoh 			reg &= ~CTRL_EXT_I2C_ENA;
   2552  1.457   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   2553  1.457   msaitoh 
   2554  1.457   msaitoh 		if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)
   2555  1.199   msaitoh 			wm_gmii_mediainit(sc, wmp->wmp_product);
   2556  1.457   msaitoh 		else
   2557  1.457   msaitoh 			wm_tbi_mediainit(sc);
   2558  1.457   msaitoh 	} else if (sc->sc_type < WM_T_82543 ||
   2559  1.457   msaitoh 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
   2560  1.457   msaitoh 		if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) {
   2561  1.457   msaitoh 			aprint_error_dev(sc->sc_dev,
   2562  1.457   msaitoh 			    "WARNING: TBIMODE set on 1000BASE-T product!\n");
   2563  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_FIBER;
   2564  1.457   msaitoh 		}
   2565  1.457   msaitoh 		wm_tbi_mediainit(sc);
   2566  1.457   msaitoh 	} else {
   2567  1.457   msaitoh 		if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) {
   2568  1.457   msaitoh 			aprint_error_dev(sc->sc_dev,
   2569  1.457   msaitoh 			    "WARNING: TBIMODE clear on 1000BASE-X product!\n");
   2570  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2571  1.199   msaitoh 		}
   2572  1.457   msaitoh 		wm_gmii_mediainit(sc, wmp->wmp_product);
   2573    1.1   thorpej 	}
   2574  1.513   msaitoh 	snprintb(buf, sizeof(buf), WM_FLAGS, sc->sc_flags);
   2575  1.513   msaitoh 	aprint_verbose_dev(sc->sc_dev, "%s\n", buf);
   2576    1.1   thorpej 
   2577    1.1   thorpej 	ifp = &sc->sc_ethercom.ec_if;
   2578  1.160  christos 	xname = device_xname(sc->sc_dev);
   2579  1.160  christos 	strlcpy(ifp->if_xname, xname, IFNAMSIZ);
   2580    1.1   thorpej 	ifp->if_softc = sc;
   2581    1.1   thorpej 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   2582  1.492  knakahar #ifdef WM_MPSAFE
   2583  1.415  knakahar 	ifp->if_extflags = IFEF_START_MPSAFE;
   2584  1.492  knakahar #endif
   2585    1.1   thorpej 	ifp->if_ioctl = wm_ioctl;
   2586  1.403  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   2587  1.232    bouyer 		ifp->if_start = wm_nq_start;
   2588  1.503  knakahar 		/*
   2589  1.503  knakahar 		 * When the number of CPUs is one and the controller can use
   2590  1.505  knakahar 		 * MSI-X, wm(4) use MSI-X but *does not* use multiqueue.
   2591  1.503  knakahar 		 * That is, wm(4) use two interrupts, one is used for Tx/Rx
   2592  1.503  knakahar 		 * and the other is used for link status changing.
   2593  1.503  knakahar 		 * In this situation, wm_nq_transmit() is disadvantageous
   2594  1.503  knakahar 		 * because of wm_select_txqueue() and pcq(9) overhead.
   2595  1.503  knakahar 		 */
   2596  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   2597  1.403  knakahar 			ifp->if_transmit = wm_nq_transmit;
   2598  1.454  knakahar 	} else {
   2599  1.232    bouyer 		ifp->if_start = wm_start;
   2600  1.503  knakahar 		/*
   2601  1.503  knakahar 		 * wm_transmit() has the same disadvantage as wm_transmit().
   2602  1.503  knakahar 		 */
   2603  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   2604  1.454  knakahar 			ifp->if_transmit = wm_transmit;
   2605  1.454  knakahar 	}
   2606    1.1   thorpej 	ifp->if_watchdog = wm_watchdog;
   2607    1.1   thorpej 	ifp->if_init = wm_init;
   2608    1.1   thorpej 	ifp->if_stop = wm_stop;
   2609   1.58     ragge 	IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
   2610    1.1   thorpej 	IFQ_SET_READY(&ifp->if_snd);
   2611    1.1   thorpej 
   2612  1.187   msaitoh 	/* Check for jumbo frame */
   2613  1.187   msaitoh 	switch (sc->sc_type) {
   2614  1.187   msaitoh 	case WM_T_82573:
   2615  1.187   msaitoh 		/* XXX limited to 9234 if ASPM is disabled */
   2616  1.325   msaitoh 		wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword);
   2617  1.325   msaitoh 		if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0)
   2618  1.187   msaitoh 			sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2619  1.187   msaitoh 		break;
   2620  1.187   msaitoh 	case WM_T_82571:
   2621  1.187   msaitoh 	case WM_T_82572:
   2622  1.187   msaitoh 	case WM_T_82574:
   2623  1.199   msaitoh 	case WM_T_82575:
   2624  1.199   msaitoh 	case WM_T_82576:
   2625  1.199   msaitoh 	case WM_T_82580:
   2626  1.228   msaitoh 	case WM_T_I350:
   2627  1.265   msaitoh 	case WM_T_I354: /* XXXX ok? */
   2628  1.247   msaitoh 	case WM_T_I210:
   2629  1.247   msaitoh 	case WM_T_I211:
   2630  1.187   msaitoh 	case WM_T_80003:
   2631  1.187   msaitoh 	case WM_T_ICH9:
   2632  1.187   msaitoh 	case WM_T_ICH10:
   2633  1.221   msaitoh 	case WM_T_PCH2:	/* PCH2 supports 9K frame size */
   2634  1.249   msaitoh 	case WM_T_PCH_LPT:
   2635  1.392   msaitoh 	case WM_T_PCH_SPT:
   2636  1.187   msaitoh 		/* XXX limited to 9234 */
   2637  1.120   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2638  1.187   msaitoh 		break;
   2639  1.190   msaitoh 	case WM_T_PCH:
   2640  1.190   msaitoh 		/* XXX limited to 4096 */
   2641  1.190   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2642  1.190   msaitoh 		break;
   2643  1.187   msaitoh 	case WM_T_82542_2_0:
   2644  1.187   msaitoh 	case WM_T_82542_2_1:
   2645  1.187   msaitoh 	case WM_T_82583:
   2646  1.187   msaitoh 	case WM_T_ICH8:
   2647  1.187   msaitoh 		/* No support for jumbo frame */
   2648  1.187   msaitoh 		break;
   2649  1.187   msaitoh 	default:
   2650  1.187   msaitoh 		/* ETHER_MAX_LEN_JUMBO */
   2651  1.187   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2652  1.187   msaitoh 		break;
   2653  1.187   msaitoh 	}
   2654   1.41       tls 
   2655  1.281   msaitoh 	/* If we're a i82543 or greater, we can support VLANs. */
   2656  1.233   msaitoh 	if (sc->sc_type >= WM_T_82543)
   2657    1.1   thorpej 		sc->sc_ethercom.ec_capabilities |=
   2658  1.172    darran 		    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
   2659    1.1   thorpej 
   2660    1.1   thorpej 	/*
   2661    1.1   thorpej 	 * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
   2662   1.11   thorpej 	 * on i82543 and later.
   2663    1.1   thorpej 	 */
   2664  1.130      yamt 	if (sc->sc_type >= WM_T_82543) {
   2665    1.1   thorpej 		ifp->if_capabilities |=
   2666  1.103      yamt 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
   2667  1.103      yamt 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   2668  1.107      yamt 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
   2669  1.107      yamt 		    IFCAP_CSUM_TCPv6_Tx |
   2670  1.107      yamt 		    IFCAP_CSUM_UDPv6_Tx;
   2671  1.130      yamt 	}
   2672  1.130      yamt 
   2673  1.130      yamt 	/*
   2674  1.130      yamt 	 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL.
   2675  1.130      yamt 	 *
   2676  1.130      yamt 	 *	82541GI (8086:1076) ... no
   2677  1.130      yamt 	 *	82572EI (8086:10b9) ... yes
   2678  1.130      yamt 	 */
   2679  1.130      yamt 	if (sc->sc_type >= WM_T_82571) {
   2680  1.130      yamt 		ifp->if_capabilities |=
   2681  1.130      yamt 		    IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
   2682  1.130      yamt 	}
   2683    1.1   thorpej 
   2684  1.198   msaitoh 	/*
   2685   1.99      matt 	 * If we're a i82544 or greater (except i82547), we can do
   2686   1.99      matt 	 * TCP segmentation offload.
   2687   1.99      matt 	 */
   2688  1.131      yamt 	if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) {
   2689   1.99      matt 		ifp->if_capabilities |= IFCAP_TSOv4;
   2690  1.131      yamt 	}
   2691  1.131      yamt 
   2692  1.131      yamt 	if (sc->sc_type >= WM_T_82571) {
   2693  1.131      yamt 		ifp->if_capabilities |= IFCAP_TSOv6;
   2694  1.131      yamt 	}
   2695   1.99      matt 
   2696  1.493  knakahar 	sc->sc_rx_process_limit = WM_RX_PROCESS_LIMIT_DEFAULT;
   2697  1.493  knakahar 	sc->sc_rx_intr_process_limit = WM_RX_INTR_PROCESS_LIMIT_DEFAULT;
   2698  1.493  knakahar 
   2699  1.272     ozaki #ifdef WM_MPSAFE
   2700  1.357  knakahar 	sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2701  1.272     ozaki #else
   2702  1.357  knakahar 	sc->sc_core_lock = NULL;
   2703  1.272     ozaki #endif
   2704  1.272     ozaki 
   2705  1.281   msaitoh 	/* Attach the interface. */
   2706  1.391     ozaki 	if_initialize(ifp);
   2707  1.391     ozaki 	sc->sc_ipq = if_percpuq_create(&sc->sc_ethercom.ec_if);
   2708    1.1   thorpej 	ether_ifattach(ifp, enaddr);
   2709  1.391     ozaki 	if_register(ifp);
   2710  1.213   msaitoh 	ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb);
   2711  1.289       tls 	rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET,
   2712  1.289       tls 			  RND_FLAG_DEFAULT);
   2713    1.1   thorpej 
   2714    1.1   thorpej #ifdef WM_EVENT_COUNTERS
   2715    1.1   thorpej 	/* Attach event counters. */
   2716    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
   2717  1.160  christos 	    NULL, xname, "linkintr");
   2718    1.1   thorpej 
   2719   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
   2720  1.160  christos 	    NULL, xname, "tx_xoff");
   2721   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
   2722  1.160  christos 	    NULL, xname, "tx_xon");
   2723   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
   2724  1.160  christos 	    NULL, xname, "rx_xoff");
   2725   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
   2726  1.160  christos 	    NULL, xname, "rx_xon");
   2727   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
   2728  1.160  christos 	    NULL, xname, "rx_macctl");
   2729    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
   2730    1.1   thorpej 
   2731  1.203   msaitoh 	if (pmf_device_register(self, wm_suspend, wm_resume))
   2732  1.180   tsutsui 		pmf_class_network_register(self, ifp);
   2733  1.180   tsutsui 	else
   2734  1.149  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
   2735  1.123  jmcneill 
   2736  1.290   msaitoh 	sc->sc_flags |= WM_F_ATTACHED;
   2737  1.353  knakahar  out:
   2738    1.1   thorpej 	return;
   2739    1.1   thorpej }
   2740    1.1   thorpej 
   2741  1.280   msaitoh /* The detach function (ca_detach) */
   2742  1.201   msaitoh static int
   2743  1.201   msaitoh wm_detach(device_t self, int flags __unused)
   2744  1.201   msaitoh {
   2745  1.201   msaitoh 	struct wm_softc *sc = device_private(self);
   2746  1.201   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2747  1.272     ozaki 	int i;
   2748  1.201   msaitoh 
   2749  1.290   msaitoh 	if ((sc->sc_flags & WM_F_ATTACHED) == 0)
   2750  1.290   msaitoh 		return 0;
   2751  1.290   msaitoh 
   2752  1.201   msaitoh 	/* Stop the interface. Callouts are stopped in it. */
   2753  1.201   msaitoh 	wm_stop(ifp, 1);
   2754  1.272     ozaki 
   2755  1.201   msaitoh 	pmf_device_deregister(self);
   2756  1.201   msaitoh 
   2757  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   2758  1.477  knakahar 	evcnt_detach(&sc->sc_ev_linkintr);
   2759  1.477  knakahar 
   2760  1.477  knakahar 	evcnt_detach(&sc->sc_ev_tx_xoff);
   2761  1.477  knakahar 	evcnt_detach(&sc->sc_ev_tx_xon);
   2762  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_xoff);
   2763  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_xon);
   2764  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_macctl);
   2765  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   2766  1.477  knakahar 
   2767  1.201   msaitoh 	/* Tell the firmware about the release */
   2768  1.357  knakahar 	WM_CORE_LOCK(sc);
   2769  1.201   msaitoh 	wm_release_manageability(sc);
   2770  1.212  jakllsch 	wm_release_hw_control(sc);
   2771  1.439   msaitoh 	wm_enable_wakeup(sc);
   2772  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   2773  1.201   msaitoh 
   2774  1.201   msaitoh 	mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
   2775  1.201   msaitoh 
   2776  1.201   msaitoh 	/* Delete all remaining media. */
   2777  1.201   msaitoh 	ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
   2778  1.201   msaitoh 
   2779  1.201   msaitoh 	ether_ifdetach(ifp);
   2780  1.201   msaitoh 	if_detach(ifp);
   2781  1.391     ozaki 	if_percpuq_destroy(sc->sc_ipq);
   2782  1.201   msaitoh 
   2783  1.246  christos 	/* Unload RX dmamaps and free mbufs */
   2784  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   2785  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   2786  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   2787  1.364  knakahar 		wm_rxdrain(rxq);
   2788  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   2789  1.364  knakahar 	}
   2790  1.272     ozaki 	/* Must unlock here */
   2791  1.201   msaitoh 
   2792  1.201   msaitoh 	/* Disestablish the interrupt handler */
   2793  1.335   msaitoh 	for (i = 0; i < sc->sc_nintrs; i++) {
   2794  1.335   msaitoh 		if (sc->sc_ihs[i] != NULL) {
   2795  1.335   msaitoh 			pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
   2796  1.335   msaitoh 			sc->sc_ihs[i] = NULL;
   2797  1.335   msaitoh 		}
   2798  1.201   msaitoh 	}
   2799  1.335   msaitoh 	pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs);
   2800  1.201   msaitoh 
   2801  1.396  knakahar 	wm_free_txrx_queues(sc);
   2802  1.396  knakahar 
   2803  1.212  jakllsch 	/* Unmap the registers */
   2804  1.201   msaitoh 	if (sc->sc_ss) {
   2805  1.201   msaitoh 		bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss);
   2806  1.201   msaitoh 		sc->sc_ss = 0;
   2807  1.201   msaitoh 	}
   2808  1.212  jakllsch 	if (sc->sc_ios) {
   2809  1.212  jakllsch 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
   2810  1.212  jakllsch 		sc->sc_ios = 0;
   2811  1.212  jakllsch 	}
   2812  1.336   msaitoh 	if (sc->sc_flashs) {
   2813  1.336   msaitoh 		bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs);
   2814  1.336   msaitoh 		sc->sc_flashs = 0;
   2815  1.336   msaitoh 	}
   2816  1.201   msaitoh 
   2817  1.357  knakahar 	if (sc->sc_core_lock)
   2818  1.357  knakahar 		mutex_obj_free(sc->sc_core_lock);
   2819  1.424   msaitoh 	if (sc->sc_ich_phymtx)
   2820  1.424   msaitoh 		mutex_obj_free(sc->sc_ich_phymtx);
   2821  1.423   msaitoh 	if (sc->sc_ich_nvmmtx)
   2822  1.423   msaitoh 		mutex_obj_free(sc->sc_ich_nvmmtx);
   2823  1.272     ozaki 
   2824  1.201   msaitoh 	return 0;
   2825  1.201   msaitoh }
   2826  1.201   msaitoh 
   2827  1.281   msaitoh static bool
   2828  1.281   msaitoh wm_suspend(device_t self, const pmf_qual_t *qual)
   2829  1.281   msaitoh {
   2830  1.281   msaitoh 	struct wm_softc *sc = device_private(self);
   2831  1.281   msaitoh 
   2832  1.281   msaitoh 	wm_release_manageability(sc);
   2833  1.281   msaitoh 	wm_release_hw_control(sc);
   2834  1.281   msaitoh 	wm_enable_wakeup(sc);
   2835  1.281   msaitoh 
   2836  1.281   msaitoh 	return true;
   2837  1.281   msaitoh }
   2838  1.281   msaitoh 
   2839  1.281   msaitoh static bool
   2840  1.281   msaitoh wm_resume(device_t self, const pmf_qual_t *qual)
   2841  1.281   msaitoh {
   2842  1.281   msaitoh 	struct wm_softc *sc = device_private(self);
   2843  1.281   msaitoh 
   2844  1.281   msaitoh 	wm_init_manageability(sc);
   2845  1.281   msaitoh 
   2846  1.281   msaitoh 	return true;
   2847  1.281   msaitoh }
   2848  1.281   msaitoh 
   2849    1.1   thorpej /*
   2850  1.281   msaitoh  * wm_watchdog:		[ifnet interface function]
   2851    1.1   thorpej  *
   2852  1.281   msaitoh  *	Watchdog timer handler.
   2853    1.1   thorpej  */
   2854  1.281   msaitoh static void
   2855  1.281   msaitoh wm_watchdog(struct ifnet *ifp)
   2856    1.1   thorpej {
   2857  1.403  knakahar 	int qid;
   2858  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   2859  1.403  knakahar 
   2860  1.405  knakahar 	for (qid = 0; qid < sc->sc_nqueues; qid++) {
   2861  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[qid].wmq_txq;
   2862  1.403  knakahar 
   2863  1.403  knakahar 		wm_watchdog_txq(ifp, txq);
   2864  1.403  knakahar 	}
   2865  1.403  knakahar 
   2866  1.403  knakahar 	/* Reset the interface. */
   2867  1.403  knakahar 	(void) wm_init(ifp);
   2868  1.403  knakahar 
   2869  1.403  knakahar 	/*
   2870  1.403  knakahar 	 * There are still some upper layer processing which call
   2871  1.503  knakahar 	 * ifp->if_start(). e.g. ALTQ or one CPU system
   2872  1.403  knakahar 	 */
   2873  1.403  knakahar 	/* Try to get more packets going. */
   2874  1.403  knakahar 	ifp->if_start(ifp);
   2875  1.403  knakahar }
   2876  1.403  knakahar 
   2877  1.403  knakahar static void
   2878  1.403  knakahar wm_watchdog_txq(struct ifnet *ifp, struct wm_txqueue *txq)
   2879  1.403  knakahar {
   2880  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   2881    1.1   thorpej 
   2882    1.1   thorpej 	/*
   2883  1.281   msaitoh 	 * Since we're using delayed interrupts, sweep up
   2884  1.281   msaitoh 	 * before we report an error.
   2885    1.1   thorpej 	 */
   2886  1.413     skrll 	mutex_enter(txq->txq_lock);
   2887  1.403  knakahar 	wm_txeof(sc, txq);
   2888  1.413     skrll 	mutex_exit(txq->txq_lock);
   2889  1.281   msaitoh 
   2890  1.356  knakahar 	if (txq->txq_free != WM_NTXDESC(txq)) {
   2891  1.281   msaitoh #ifdef WM_DEBUG
   2892  1.281   msaitoh 		int i, j;
   2893  1.281   msaitoh 		struct wm_txsoft *txs;
   2894  1.281   msaitoh #endif
   2895  1.281   msaitoh 		log(LOG_ERR,
   2896  1.281   msaitoh 		    "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
   2897  1.356  knakahar 		    device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree,
   2898  1.356  knakahar 		    txq->txq_next);
   2899  1.281   msaitoh 		ifp->if_oerrors++;
   2900  1.281   msaitoh #ifdef WM_DEBUG
   2901  1.366  knakahar 		for (i = txq->txq_sdirty; i != txq->txq_snext ;
   2902  1.356  knakahar 		    i = WM_NEXTTXS(txq, i)) {
   2903  1.366  knakahar 		    txs = &txq->txq_soft[i];
   2904  1.281   msaitoh 		    printf("txs %d tx %d -> %d\n",
   2905  1.281   msaitoh 			i, txs->txs_firstdesc, txs->txs_lastdesc);
   2906  1.281   msaitoh 		    for (j = txs->txs_firstdesc; ;
   2907  1.356  knakahar 			j = WM_NEXTTX(txq, j)) {
   2908  1.281   msaitoh 			printf("\tdesc %d: 0x%" PRIx64 "\n", j,
   2909  1.366  knakahar 			    txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
   2910  1.281   msaitoh 			printf("\t %#08x%08x\n",
   2911  1.366  knakahar 			    txq->txq_nq_descs[j].nqtx_data.nqtxd_fields,
   2912  1.366  knakahar 			    txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen);
   2913  1.281   msaitoh 			if (j == txs->txs_lastdesc)
   2914  1.281   msaitoh 				break;
   2915  1.281   msaitoh 			}
   2916  1.281   msaitoh 		}
   2917  1.281   msaitoh #endif
   2918  1.281   msaitoh 	}
   2919  1.281   msaitoh }
   2920    1.1   thorpej 
   2921  1.281   msaitoh /*
   2922  1.281   msaitoh  * wm_tick:
   2923  1.281   msaitoh  *
   2924  1.281   msaitoh  *	One second timer, used to check link status, sweep up
   2925  1.281   msaitoh  *	completed transmit jobs, etc.
   2926  1.281   msaitoh  */
   2927  1.281   msaitoh static void
   2928  1.281   msaitoh wm_tick(void *arg)
   2929  1.281   msaitoh {
   2930  1.281   msaitoh 	struct wm_softc *sc = arg;
   2931  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2932  1.281   msaitoh #ifndef WM_MPSAFE
   2933  1.413     skrll 	int s = splnet();
   2934  1.281   msaitoh #endif
   2935   1.35   thorpej 
   2936  1.357  knakahar 	WM_CORE_LOCK(sc);
   2937   1.13   thorpej 
   2938  1.429  knakahar 	if (sc->sc_core_stopping)
   2939  1.281   msaitoh 		goto out;
   2940    1.1   thorpej 
   2941  1.281   msaitoh 	if (sc->sc_type >= WM_T_82542_2_1) {
   2942  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
   2943  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
   2944  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
   2945  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
   2946  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
   2947  1.107      yamt 	}
   2948    1.1   thorpej 
   2949  1.281   msaitoh 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
   2950  1.504  knakahar 	ifp->if_ierrors += 0ULL /* ensure quad_t */
   2951  1.281   msaitoh 	    + CSR_READ(sc, WMREG_CRCERRS)
   2952  1.281   msaitoh 	    + CSR_READ(sc, WMREG_ALGNERRC)
   2953  1.281   msaitoh 	    + CSR_READ(sc, WMREG_SYMERRC)
   2954  1.281   msaitoh 	    + CSR_READ(sc, WMREG_RXERRC)
   2955  1.281   msaitoh 	    + CSR_READ(sc, WMREG_SEC)
   2956  1.281   msaitoh 	    + CSR_READ(sc, WMREG_CEXTERR)
   2957  1.281   msaitoh 	    + CSR_READ(sc, WMREG_RLEC);
   2958  1.431  knakahar 	/*
   2959  1.431  knakahar 	 * WMREG_RNBC is incremented when there is no available buffers in host
   2960  1.431  knakahar 	 * memory. It does not mean the number of dropped packet. Because
   2961  1.431  knakahar 	 * ethernet controller can receive packets in such case if there is
   2962  1.431  knakahar 	 * space in phy's FIFO.
   2963  1.431  knakahar 	 *
   2964  1.431  knakahar 	 * If you want to know the nubmer of WMREG_RMBC, you should use such as
   2965  1.431  knakahar 	 * own EVCNT instead of if_iqdrops.
   2966  1.431  knakahar 	 */
   2967  1.431  knakahar 	ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC);
   2968   1.98   thorpej 
   2969  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   2970  1.281   msaitoh 		mii_tick(&sc->sc_mii);
   2971  1.325   msaitoh 	else if ((sc->sc_type >= WM_T_82575)
   2972  1.325   msaitoh 	    && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   2973  1.325   msaitoh 		wm_serdes_tick(sc);
   2974  1.281   msaitoh 	else
   2975  1.325   msaitoh 		wm_tbi_tick(sc);
   2976  1.131      yamt 
   2977  1.463  knakahar 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   2978  1.281   msaitoh out:
   2979  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   2980  1.281   msaitoh #ifndef WM_MPSAFE
   2981  1.281   msaitoh 	splx(s);
   2982  1.281   msaitoh #endif
   2983  1.281   msaitoh }
   2984   1.99      matt 
   2985  1.281   msaitoh static int
   2986  1.281   msaitoh wm_ifflags_cb(struct ethercom *ec)
   2987  1.281   msaitoh {
   2988  1.281   msaitoh 	struct ifnet *ifp = &ec->ec_if;
   2989  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   2990  1.281   msaitoh 	int rc = 0;
   2991   1.99      matt 
   2992  1.511   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   2993  1.511   msaitoh 		device_xname(sc->sc_dev), __func__));
   2994  1.511   msaitoh 
   2995  1.357  knakahar 	WM_CORE_LOCK(sc);
   2996   1.99      matt 
   2997  1.418     skrll 	int change = ifp->if_flags ^ sc->sc_if_flags;
   2998  1.418     skrll 	sc->sc_if_flags = ifp->if_flags;
   2999   1.99      matt 
   3000  1.388   msaitoh 	if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
   3001  1.281   msaitoh 		rc = ENETRESET;
   3002  1.281   msaitoh 		goto out;
   3003  1.281   msaitoh 	}
   3004   1.99      matt 
   3005  1.281   msaitoh 	if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
   3006  1.281   msaitoh 		wm_set_filter(sc);
   3007  1.131      yamt 
   3008  1.281   msaitoh 	wm_set_vlan(sc);
   3009  1.131      yamt 
   3010  1.281   msaitoh out:
   3011  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   3012   1.99      matt 
   3013  1.281   msaitoh 	return rc;
   3014   1.75   thorpej }
   3015   1.75   thorpej 
   3016    1.1   thorpej /*
   3017  1.281   msaitoh  * wm_ioctl:		[ifnet interface function]
   3018   1.78   thorpej  *
   3019  1.281   msaitoh  *	Handle control requests from the operator.
   3020   1.78   thorpej  */
   3021  1.281   msaitoh static int
   3022  1.281   msaitoh wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
   3023   1.78   thorpej {
   3024  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   3025  1.281   msaitoh 	struct ifreq *ifr = (struct ifreq *) data;
   3026  1.281   msaitoh 	struct ifaddr *ifa = (struct ifaddr *)data;
   3027  1.281   msaitoh 	struct sockaddr_dl *sdl;
   3028  1.281   msaitoh 	int s, error;
   3029  1.281   msaitoh 
   3030  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3031  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3032  1.420   msaitoh 
   3033  1.272     ozaki #ifndef WM_MPSAFE
   3034   1.78   thorpej 	s = splnet();
   3035  1.272     ozaki #endif
   3036  1.281   msaitoh 	switch (cmd) {
   3037  1.281   msaitoh 	case SIOCSIFMEDIA:
   3038  1.281   msaitoh 	case SIOCGIFMEDIA:
   3039  1.357  knakahar 		WM_CORE_LOCK(sc);
   3040  1.281   msaitoh 		/* Flow control requires full-duplex mode. */
   3041  1.327   msaitoh 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
   3042  1.281   msaitoh 		    (ifr->ifr_media & IFM_FDX) == 0)
   3043  1.281   msaitoh 			ifr->ifr_media &= ~IFM_ETH_FMASK;
   3044  1.281   msaitoh 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
   3045  1.281   msaitoh 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
   3046  1.281   msaitoh 				/* We can do both TXPAUSE and RXPAUSE. */
   3047  1.281   msaitoh 				ifr->ifr_media |=
   3048  1.281   msaitoh 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   3049  1.281   msaitoh 			}
   3050  1.281   msaitoh 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
   3051  1.281   msaitoh 		}
   3052  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   3053  1.302     ozaki #ifdef WM_MPSAFE
   3054  1.302     ozaki 		s = splnet();
   3055  1.302     ozaki #endif
   3056  1.281   msaitoh 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
   3057  1.302     ozaki #ifdef WM_MPSAFE
   3058  1.302     ozaki 		splx(s);
   3059  1.302     ozaki #endif
   3060  1.281   msaitoh 		break;
   3061  1.281   msaitoh 	case SIOCINITIFADDR:
   3062  1.357  knakahar 		WM_CORE_LOCK(sc);
   3063  1.281   msaitoh 		if (ifa->ifa_addr->sa_family == AF_LINK) {
   3064  1.281   msaitoh 			sdl = satosdl(ifp->if_dl->ifa_addr);
   3065  1.281   msaitoh 			(void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
   3066  1.281   msaitoh 			    LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen);
   3067  1.281   msaitoh 			/* unicast address is first multicast entry */
   3068  1.281   msaitoh 			wm_set_filter(sc);
   3069  1.281   msaitoh 			error = 0;
   3070  1.357  knakahar 			WM_CORE_UNLOCK(sc);
   3071  1.281   msaitoh 			break;
   3072  1.281   msaitoh 		}
   3073  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   3074  1.281   msaitoh 		/*FALLTHROUGH*/
   3075  1.281   msaitoh 	default:
   3076  1.281   msaitoh #ifdef WM_MPSAFE
   3077  1.281   msaitoh 		s = splnet();
   3078  1.281   msaitoh #endif
   3079  1.281   msaitoh 		/* It may call wm_start, so unlock here */
   3080  1.281   msaitoh 		error = ether_ioctl(ifp, cmd, data);
   3081  1.281   msaitoh #ifdef WM_MPSAFE
   3082  1.281   msaitoh 		splx(s);
   3083  1.281   msaitoh #endif
   3084  1.281   msaitoh 		if (error != ENETRESET)
   3085  1.281   msaitoh 			break;
   3086   1.78   thorpej 
   3087  1.281   msaitoh 		error = 0;
   3088   1.78   thorpej 
   3089  1.281   msaitoh 		if (cmd == SIOCSIFCAP) {
   3090  1.281   msaitoh 			error = (*ifp->if_init)(ifp);
   3091  1.281   msaitoh 		} else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
   3092  1.281   msaitoh 			;
   3093  1.281   msaitoh 		else if (ifp->if_flags & IFF_RUNNING) {
   3094   1.78   thorpej 			/*
   3095  1.281   msaitoh 			 * Multicast list has changed; set the hardware filter
   3096  1.281   msaitoh 			 * accordingly.
   3097   1.78   thorpej 			 */
   3098  1.357  knakahar 			WM_CORE_LOCK(sc);
   3099  1.281   msaitoh 			wm_set_filter(sc);
   3100  1.357  knakahar 			WM_CORE_UNLOCK(sc);
   3101   1.78   thorpej 		}
   3102  1.281   msaitoh 		break;
   3103   1.78   thorpej 	}
   3104   1.78   thorpej 
   3105  1.272     ozaki #ifndef WM_MPSAFE
   3106   1.78   thorpej 	splx(s);
   3107  1.272     ozaki #endif
   3108  1.281   msaitoh 	return error;
   3109   1.78   thorpej }
   3110   1.78   thorpej 
   3111  1.281   msaitoh /* MAC address related */
   3112  1.281   msaitoh 
   3113  1.306   msaitoh /*
   3114  1.306   msaitoh  * Get the offset of MAC address and return it.
   3115  1.306   msaitoh  * If error occured, use offset 0.
   3116  1.306   msaitoh  */
   3117  1.306   msaitoh static uint16_t
   3118  1.281   msaitoh wm_check_alt_mac_addr(struct wm_softc *sc)
   3119  1.221   msaitoh {
   3120  1.281   msaitoh 	uint16_t myea[ETHER_ADDR_LEN / 2];
   3121  1.293   msaitoh 	uint16_t offset = NVM_OFF_MACADDR;
   3122  1.281   msaitoh 
   3123  1.281   msaitoh 	/* Try to read alternative MAC address pointer */
   3124  1.293   msaitoh 	if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0)
   3125  1.306   msaitoh 		return 0;
   3126  1.221   msaitoh 
   3127  1.306   msaitoh 	/* Check pointer if it's valid or not. */
   3128  1.306   msaitoh 	if ((offset == 0x0000) || (offset == 0xffff))
   3129  1.306   msaitoh 		return 0;
   3130  1.221   msaitoh 
   3131  1.306   msaitoh 	offset += NVM_OFF_MACADDR_82571(sc->sc_funcid);
   3132  1.281   msaitoh 	/*
   3133  1.281   msaitoh 	 * Check whether alternative MAC address is valid or not.
   3134  1.281   msaitoh 	 * Some cards have non 0xffff pointer but those don't use
   3135  1.281   msaitoh 	 * alternative MAC address in reality.
   3136  1.281   msaitoh 	 *
   3137  1.281   msaitoh 	 * Check whether the broadcast bit is set or not.
   3138  1.281   msaitoh 	 */
   3139  1.281   msaitoh 	if (wm_nvm_read(sc, offset, 1, myea) == 0)
   3140  1.281   msaitoh 		if (((myea[0] & 0xff) & 0x01) == 0)
   3141  1.306   msaitoh 			return offset; /* Found */
   3142  1.221   msaitoh 
   3143  1.306   msaitoh 	/* Not found */
   3144  1.306   msaitoh 	return 0;
   3145  1.221   msaitoh }
   3146  1.221   msaitoh 
   3147   1.78   thorpej static int
   3148  1.281   msaitoh wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)
   3149   1.78   thorpej {
   3150  1.281   msaitoh 	uint16_t myea[ETHER_ADDR_LEN / 2];
   3151  1.293   msaitoh 	uint16_t offset = NVM_OFF_MACADDR;
   3152  1.281   msaitoh 	int do_invert = 0;
   3153   1.78   thorpej 
   3154  1.281   msaitoh 	switch (sc->sc_type) {
   3155  1.281   msaitoh 	case WM_T_82580:
   3156  1.281   msaitoh 	case WM_T_I350:
   3157  1.281   msaitoh 	case WM_T_I354:
   3158  1.307   msaitoh 		/* EEPROM Top Level Partitioning */
   3159  1.307   msaitoh 		offset = NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + 0;
   3160  1.281   msaitoh 		break;
   3161  1.281   msaitoh 	case WM_T_82571:
   3162  1.281   msaitoh 	case WM_T_82575:
   3163  1.281   msaitoh 	case WM_T_82576:
   3164  1.281   msaitoh 	case WM_T_80003:
   3165  1.281   msaitoh 	case WM_T_I210:
   3166  1.281   msaitoh 	case WM_T_I211:
   3167  1.306   msaitoh 		offset = wm_check_alt_mac_addr(sc);
   3168  1.306   msaitoh 		if (offset == 0)
   3169  1.281   msaitoh 			if ((sc->sc_funcid & 0x01) == 1)
   3170  1.281   msaitoh 				do_invert = 1;
   3171  1.281   msaitoh 		break;
   3172  1.281   msaitoh 	default:
   3173  1.281   msaitoh 		if ((sc->sc_funcid & 0x01) == 1)
   3174  1.281   msaitoh 			do_invert = 1;
   3175  1.281   msaitoh 		break;
   3176  1.281   msaitoh 	}
   3177   1.78   thorpej 
   3178  1.424   msaitoh 	if (wm_nvm_read(sc, offset, sizeof(myea) / sizeof(myea[0]), myea) != 0)
   3179  1.281   msaitoh 		goto bad;
   3180   1.78   thorpej 
   3181  1.281   msaitoh 	enaddr[0] = myea[0] & 0xff;
   3182  1.281   msaitoh 	enaddr[1] = myea[0] >> 8;
   3183  1.281   msaitoh 	enaddr[2] = myea[1] & 0xff;
   3184  1.281   msaitoh 	enaddr[3] = myea[1] >> 8;
   3185  1.281   msaitoh 	enaddr[4] = myea[2] & 0xff;
   3186  1.281   msaitoh 	enaddr[5] = myea[2] >> 8;
   3187   1.78   thorpej 
   3188  1.281   msaitoh 	/*
   3189  1.281   msaitoh 	 * Toggle the LSB of the MAC address on the second port
   3190  1.281   msaitoh 	 * of some dual port cards.
   3191  1.281   msaitoh 	 */
   3192  1.281   msaitoh 	if (do_invert != 0)
   3193  1.281   msaitoh 		enaddr[5] ^= 1;
   3194   1.78   thorpej 
   3195  1.194   msaitoh 	return 0;
   3196  1.281   msaitoh 
   3197  1.281   msaitoh  bad:
   3198  1.281   msaitoh 	return -1;
   3199   1.78   thorpej }
   3200   1.78   thorpej 
   3201   1.78   thorpej /*
   3202  1.281   msaitoh  * wm_set_ral:
   3203    1.1   thorpej  *
   3204  1.281   msaitoh  *	Set an entery in the receive address list.
   3205    1.1   thorpej  */
   3206   1.47   thorpej static void
   3207  1.281   msaitoh wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
   3208  1.281   msaitoh {
   3209  1.514   msaitoh 	uint32_t ral_lo, ral_hi, addrl, addrh;
   3210  1.514   msaitoh 	uint32_t wlock_mac;
   3211  1.514   msaitoh 	int rv;
   3212  1.281   msaitoh 
   3213  1.281   msaitoh 	if (enaddr != NULL) {
   3214  1.281   msaitoh 		ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
   3215  1.281   msaitoh 		    (enaddr[3] << 24);
   3216  1.281   msaitoh 		ral_hi = enaddr[4] | (enaddr[5] << 8);
   3217  1.281   msaitoh 		ral_hi |= RAL_AV;
   3218  1.281   msaitoh 	} else {
   3219  1.281   msaitoh 		ral_lo = 0;
   3220  1.281   msaitoh 		ral_hi = 0;
   3221  1.281   msaitoh 	}
   3222  1.281   msaitoh 
   3223  1.514   msaitoh 	switch (sc->sc_type) {
   3224  1.514   msaitoh 	case WM_T_82542_2_0:
   3225  1.514   msaitoh 	case WM_T_82542_2_1:
   3226  1.514   msaitoh 	case WM_T_82543:
   3227  1.514   msaitoh 		CSR_WRITE(sc, WMREG_RAL(idx), ral_lo);
   3228  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3229  1.514   msaitoh 		CSR_WRITE(sc, WMREG_RAH(idx), ral_hi);
   3230  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3231  1.514   msaitoh 		break;
   3232  1.514   msaitoh 	case WM_T_PCH2:
   3233  1.514   msaitoh 	case WM_T_PCH_LPT:
   3234  1.514   msaitoh 	case WM_T_PCH_SPT:
   3235  1.514   msaitoh 		if (idx == 0) {
   3236  1.514   msaitoh 			CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
   3237  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3238  1.514   msaitoh 			CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
   3239  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3240  1.514   msaitoh 			return;
   3241  1.514   msaitoh 		}
   3242  1.514   msaitoh 		if (sc->sc_type != WM_T_PCH2) {
   3243  1.514   msaitoh 			wlock_mac = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM),
   3244  1.514   msaitoh 			    FWSM_WLOCK_MAC);
   3245  1.514   msaitoh 			addrl = WMREG_SHRAL(idx - 1);
   3246  1.514   msaitoh 			addrh = WMREG_SHRAH(idx - 1);
   3247  1.514   msaitoh 		} else {
   3248  1.514   msaitoh 			wlock_mac = 0;
   3249  1.514   msaitoh 			addrl = WMREG_PCH_LPT_SHRAL(idx - 1);
   3250  1.514   msaitoh 			addrh = WMREG_PCH_LPT_SHRAH(idx - 1);
   3251  1.514   msaitoh 		}
   3252  1.514   msaitoh 
   3253  1.514   msaitoh 		if ((wlock_mac == 0) || (idx <= wlock_mac)) {
   3254  1.514   msaitoh 			rv = wm_get_swflag_ich8lan(sc);
   3255  1.514   msaitoh 			if (rv != 0)
   3256  1.514   msaitoh 				return;
   3257  1.514   msaitoh 			CSR_WRITE(sc, addrl, ral_lo);
   3258  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3259  1.514   msaitoh 			CSR_WRITE(sc, addrh, ral_hi);
   3260  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3261  1.514   msaitoh 			wm_put_swflag_ich8lan(sc);
   3262  1.514   msaitoh 		}
   3263  1.514   msaitoh 
   3264  1.514   msaitoh 		break;
   3265  1.514   msaitoh 	default:
   3266  1.514   msaitoh 		CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
   3267  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3268  1.514   msaitoh 		CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
   3269  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3270  1.514   msaitoh 		break;
   3271  1.281   msaitoh 	}
   3272  1.281   msaitoh }
   3273  1.281   msaitoh 
   3274  1.281   msaitoh /*
   3275  1.281   msaitoh  * wm_mchash:
   3276  1.281   msaitoh  *
   3277  1.281   msaitoh  *	Compute the hash of the multicast address for the 4096-bit
   3278  1.281   msaitoh  *	multicast filter.
   3279  1.281   msaitoh  */
   3280  1.281   msaitoh static uint32_t
   3281  1.281   msaitoh wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
   3282    1.1   thorpej {
   3283  1.281   msaitoh 	static const int lo_shift[4] = { 4, 3, 2, 0 };
   3284  1.281   msaitoh 	static const int hi_shift[4] = { 4, 5, 6, 8 };
   3285  1.281   msaitoh 	static const int ich8_lo_shift[4] = { 6, 5, 4, 2 };
   3286  1.281   msaitoh 	static const int ich8_hi_shift[4] = { 2, 3, 4, 6 };
   3287  1.281   msaitoh 	uint32_t hash;
   3288  1.281   msaitoh 
   3289  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3290  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3291  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   3292  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT)) {
   3293  1.281   msaitoh 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
   3294  1.281   msaitoh 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
   3295  1.281   msaitoh 		return (hash & 0x3ff);
   3296  1.281   msaitoh 	}
   3297  1.281   msaitoh 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
   3298  1.281   msaitoh 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
   3299  1.272     ozaki 
   3300  1.281   msaitoh 	return (hash & 0xfff);
   3301  1.272     ozaki }
   3302  1.272     ozaki 
   3303  1.281   msaitoh /*
   3304  1.281   msaitoh  * wm_set_filter:
   3305  1.281   msaitoh  *
   3306  1.281   msaitoh  *	Set up the receive filter.
   3307  1.281   msaitoh  */
   3308  1.272     ozaki static void
   3309  1.281   msaitoh wm_set_filter(struct wm_softc *sc)
   3310  1.272     ozaki {
   3311  1.281   msaitoh 	struct ethercom *ec = &sc->sc_ethercom;
   3312  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   3313  1.281   msaitoh 	struct ether_multi *enm;
   3314  1.281   msaitoh 	struct ether_multistep step;
   3315  1.281   msaitoh 	bus_addr_t mta_reg;
   3316  1.281   msaitoh 	uint32_t hash, reg, bit;
   3317  1.390   msaitoh 	int i, size, ralmax;
   3318  1.281   msaitoh 
   3319  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3320  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3321  1.420   msaitoh 
   3322  1.281   msaitoh 	if (sc->sc_type >= WM_T_82544)
   3323  1.281   msaitoh 		mta_reg = WMREG_CORDOVA_MTA;
   3324  1.281   msaitoh 	else
   3325  1.281   msaitoh 		mta_reg = WMREG_MTA;
   3326    1.1   thorpej 
   3327  1.281   msaitoh 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
   3328  1.272     ozaki 
   3329  1.281   msaitoh 	if (ifp->if_flags & IFF_BROADCAST)
   3330  1.281   msaitoh 		sc->sc_rctl |= RCTL_BAM;
   3331  1.281   msaitoh 	if (ifp->if_flags & IFF_PROMISC) {
   3332  1.281   msaitoh 		sc->sc_rctl |= RCTL_UPE;
   3333  1.281   msaitoh 		goto allmulti;
   3334  1.281   msaitoh 	}
   3335    1.1   thorpej 
   3336    1.1   thorpej 	/*
   3337  1.281   msaitoh 	 * Set the station address in the first RAL slot, and
   3338  1.281   msaitoh 	 * clear the remaining slots.
   3339    1.1   thorpej 	 */
   3340  1.281   msaitoh 	if (sc->sc_type == WM_T_ICH8)
   3341  1.281   msaitoh 		size = WM_RAL_TABSIZE_ICH8 -1;
   3342  1.281   msaitoh 	else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10)
   3343  1.386   msaitoh 	    || (sc->sc_type == WM_T_PCH))
   3344  1.281   msaitoh 		size = WM_RAL_TABSIZE_ICH8;
   3345  1.386   msaitoh 	else if (sc->sc_type == WM_T_PCH2)
   3346  1.386   msaitoh 		size = WM_RAL_TABSIZE_PCH2;
   3347  1.392   msaitoh 	else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT))
   3348  1.386   msaitoh 		size = WM_RAL_TABSIZE_PCH_LPT;
   3349  1.281   msaitoh 	else if (sc->sc_type == WM_T_82575)
   3350  1.281   msaitoh 		size = WM_RAL_TABSIZE_82575;
   3351  1.281   msaitoh 	else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580))
   3352  1.281   msaitoh 		size = WM_RAL_TABSIZE_82576;
   3353  1.281   msaitoh 	else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   3354  1.281   msaitoh 		size = WM_RAL_TABSIZE_I350;
   3355  1.281   msaitoh 	else
   3356  1.281   msaitoh 		size = WM_RAL_TABSIZE;
   3357  1.281   msaitoh 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
   3358  1.386   msaitoh 
   3359  1.392   msaitoh 	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
   3360  1.386   msaitoh 		i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
   3361  1.386   msaitoh 		switch (i) {
   3362  1.386   msaitoh 		case 0:
   3363  1.386   msaitoh 			/* We can use all entries */
   3364  1.390   msaitoh 			ralmax = size;
   3365  1.386   msaitoh 			break;
   3366  1.386   msaitoh 		case 1:
   3367  1.386   msaitoh 			/* Only RAR[0] */
   3368  1.390   msaitoh 			ralmax = 1;
   3369  1.386   msaitoh 			break;
   3370  1.386   msaitoh 		default:
   3371  1.386   msaitoh 			/* available SHRA + RAR[0] */
   3372  1.390   msaitoh 			ralmax = i + 1;
   3373  1.386   msaitoh 		}
   3374  1.386   msaitoh 	} else
   3375  1.390   msaitoh 		ralmax = size;
   3376  1.386   msaitoh 	for (i = 1; i < size; i++) {
   3377  1.390   msaitoh 		if (i < ralmax)
   3378  1.386   msaitoh 			wm_set_ral(sc, NULL, i);
   3379  1.386   msaitoh 	}
   3380    1.1   thorpej 
   3381  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3382  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3383  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   3384  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT))
   3385  1.281   msaitoh 		size = WM_ICH8_MC_TABSIZE;
   3386  1.281   msaitoh 	else
   3387  1.281   msaitoh 		size = WM_MC_TABSIZE;
   3388  1.281   msaitoh 	/* Clear out the multicast table. */
   3389  1.515   msaitoh 	for (i = 0; i < size; i++) {
   3390  1.281   msaitoh 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
   3391  1.515   msaitoh 		CSR_WRITE_FLUSH(sc);
   3392  1.515   msaitoh 	}
   3393    1.1   thorpej 
   3394  1.460     ozaki 	ETHER_LOCK(ec);
   3395  1.281   msaitoh 	ETHER_FIRST_MULTI(step, ec, enm);
   3396  1.281   msaitoh 	while (enm != NULL) {
   3397  1.281   msaitoh 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   3398  1.460     ozaki 			ETHER_UNLOCK(ec);
   3399  1.281   msaitoh 			/*
   3400  1.281   msaitoh 			 * We must listen to a range of multicast addresses.
   3401  1.281   msaitoh 			 * For now, just accept all multicasts, rather than
   3402  1.281   msaitoh 			 * trying to set only those filter bits needed to match
   3403  1.281   msaitoh 			 * the range.  (At this time, the only use of address
   3404  1.281   msaitoh 			 * ranges is for IP multicast routing, for which the
   3405  1.281   msaitoh 			 * range is big enough to require all bits set.)
   3406  1.281   msaitoh 			 */
   3407  1.281   msaitoh 			goto allmulti;
   3408    1.1   thorpej 		}
   3409    1.1   thorpej 
   3410  1.281   msaitoh 		hash = wm_mchash(sc, enm->enm_addrlo);
   3411  1.272     ozaki 
   3412  1.281   msaitoh 		reg = (hash >> 5);
   3413  1.281   msaitoh 		if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3414  1.281   msaitoh 		    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3415  1.281   msaitoh 		    || (sc->sc_type == WM_T_PCH2)
   3416  1.392   msaitoh 		    || (sc->sc_type == WM_T_PCH_LPT)
   3417  1.392   msaitoh 		    || (sc->sc_type == WM_T_PCH_SPT))
   3418  1.281   msaitoh 			reg &= 0x1f;
   3419  1.281   msaitoh 		else
   3420  1.281   msaitoh 			reg &= 0x7f;
   3421  1.281   msaitoh 		bit = hash & 0x1f;
   3422  1.272     ozaki 
   3423  1.281   msaitoh 		hash = CSR_READ(sc, mta_reg + (reg << 2));
   3424  1.281   msaitoh 		hash |= 1U << bit;
   3425    1.1   thorpej 
   3426  1.382  christos 		if (sc->sc_type == WM_T_82544 && (reg & 1) != 0) {
   3427  1.387   msaitoh 			/*
   3428  1.387   msaitoh 			 * 82544 Errata 9: Certain register cannot be written
   3429  1.387   msaitoh 			 * with particular alignments in PCI-X bus operation
   3430  1.387   msaitoh 			 * (FCAH, MTA and VFTA).
   3431  1.387   msaitoh 			 */
   3432  1.281   msaitoh 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
   3433  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   3434  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3435  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
   3436  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3437  1.515   msaitoh 		} else {
   3438  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   3439  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3440  1.515   msaitoh 		}
   3441   1.99      matt 
   3442  1.281   msaitoh 		ETHER_NEXT_MULTI(step, enm);
   3443  1.281   msaitoh 	}
   3444  1.460     ozaki 	ETHER_UNLOCK(ec);
   3445   1.99      matt 
   3446  1.281   msaitoh 	ifp->if_flags &= ~IFF_ALLMULTI;
   3447  1.281   msaitoh 	goto setit;
   3448    1.1   thorpej 
   3449  1.281   msaitoh  allmulti:
   3450  1.281   msaitoh 	ifp->if_flags |= IFF_ALLMULTI;
   3451  1.281   msaitoh 	sc->sc_rctl |= RCTL_MPE;
   3452   1.80   thorpej 
   3453  1.281   msaitoh  setit:
   3454  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
   3455  1.281   msaitoh }
   3456    1.1   thorpej 
   3457  1.281   msaitoh /* Reset and init related */
   3458   1.78   thorpej 
   3459  1.281   msaitoh static void
   3460  1.281   msaitoh wm_set_vlan(struct wm_softc *sc)
   3461  1.281   msaitoh {
   3462  1.392   msaitoh 
   3463  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3464  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3465  1.420   msaitoh 
   3466  1.281   msaitoh 	/* Deal with VLAN enables. */
   3467  1.281   msaitoh 	if (VLAN_ATTACHED(&sc->sc_ethercom))
   3468  1.281   msaitoh 		sc->sc_ctrl |= CTRL_VME;
   3469  1.281   msaitoh 	else
   3470  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_VME;
   3471    1.1   thorpej 
   3472  1.281   msaitoh 	/* Write the control registers. */
   3473  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3474  1.281   msaitoh }
   3475    1.1   thorpej 
   3476  1.281   msaitoh static void
   3477  1.281   msaitoh wm_set_pcie_completion_timeout(struct wm_softc *sc)
   3478  1.281   msaitoh {
   3479  1.281   msaitoh 	uint32_t gcr;
   3480  1.281   msaitoh 	pcireg_t ctrl2;
   3481    1.1   thorpej 
   3482  1.281   msaitoh 	gcr = CSR_READ(sc, WMREG_GCR);
   3483    1.4   thorpej 
   3484  1.281   msaitoh 	/* Only take action if timeout value is defaulted to 0 */
   3485  1.281   msaitoh 	if ((gcr & GCR_CMPL_TMOUT_MASK) != 0)
   3486  1.281   msaitoh 		goto out;
   3487    1.1   thorpej 
   3488  1.281   msaitoh 	if ((gcr & GCR_CAP_VER2) == 0) {
   3489  1.281   msaitoh 		gcr |= GCR_CMPL_TMOUT_10MS;
   3490  1.281   msaitoh 		goto out;
   3491  1.281   msaitoh 	}
   3492    1.6   thorpej 
   3493  1.281   msaitoh 	ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   3494  1.281   msaitoh 	    sc->sc_pcixe_capoff + PCIE_DCSR2);
   3495  1.281   msaitoh 	ctrl2 |= WM_PCIE_DCSR2_16MS;
   3496  1.281   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   3497  1.281   msaitoh 	    sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2);
   3498   1.81   thorpej 
   3499  1.281   msaitoh out:
   3500  1.281   msaitoh 	/* Disable completion timeout resend */
   3501  1.281   msaitoh 	gcr &= ~GCR_CMPL_TMOUT_RESEND;
   3502   1.80   thorpej 
   3503  1.281   msaitoh 	CSR_WRITE(sc, WMREG_GCR, gcr);
   3504  1.281   msaitoh }
   3505   1.99      matt 
   3506  1.281   msaitoh void
   3507  1.281   msaitoh wm_get_auto_rd_done(struct wm_softc *sc)
   3508  1.281   msaitoh {
   3509  1.281   msaitoh 	int i;
   3510    1.1   thorpej 
   3511  1.281   msaitoh 	/* wait for eeprom to reload */
   3512  1.281   msaitoh 	switch (sc->sc_type) {
   3513  1.281   msaitoh 	case WM_T_82571:
   3514  1.281   msaitoh 	case WM_T_82572:
   3515  1.281   msaitoh 	case WM_T_82573:
   3516  1.281   msaitoh 	case WM_T_82574:
   3517  1.281   msaitoh 	case WM_T_82583:
   3518  1.281   msaitoh 	case WM_T_82575:
   3519  1.281   msaitoh 	case WM_T_82576:
   3520  1.281   msaitoh 	case WM_T_82580:
   3521  1.281   msaitoh 	case WM_T_I350:
   3522  1.281   msaitoh 	case WM_T_I354:
   3523  1.281   msaitoh 	case WM_T_I210:
   3524  1.281   msaitoh 	case WM_T_I211:
   3525  1.281   msaitoh 	case WM_T_80003:
   3526  1.281   msaitoh 	case WM_T_ICH8:
   3527  1.281   msaitoh 	case WM_T_ICH9:
   3528  1.281   msaitoh 		for (i = 0; i < 10; i++) {
   3529  1.281   msaitoh 			if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
   3530  1.281   msaitoh 				break;
   3531  1.281   msaitoh 			delay(1000);
   3532    1.1   thorpej 		}
   3533  1.281   msaitoh 		if (i == 10) {
   3534  1.281   msaitoh 			log(LOG_ERR, "%s: auto read from eeprom failed to "
   3535  1.281   msaitoh 			    "complete\n", device_xname(sc->sc_dev));
   3536  1.281   msaitoh 		}
   3537  1.281   msaitoh 		break;
   3538  1.281   msaitoh 	default:
   3539  1.281   msaitoh 		break;
   3540  1.281   msaitoh 	}
   3541  1.281   msaitoh }
   3542   1.59  christos 
   3543  1.281   msaitoh void
   3544  1.281   msaitoh wm_lan_init_done(struct wm_softc *sc)
   3545  1.281   msaitoh {
   3546  1.281   msaitoh 	uint32_t reg = 0;
   3547  1.281   msaitoh 	int i;
   3548    1.1   thorpej 
   3549  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3550  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   3551  1.420   msaitoh 
   3552  1.420   msaitoh 	/* Wait for eeprom to reload */
   3553  1.281   msaitoh 	switch (sc->sc_type) {
   3554  1.281   msaitoh 	case WM_T_ICH10:
   3555  1.281   msaitoh 	case WM_T_PCH:
   3556  1.281   msaitoh 	case WM_T_PCH2:
   3557  1.281   msaitoh 	case WM_T_PCH_LPT:
   3558  1.392   msaitoh 	case WM_T_PCH_SPT:
   3559  1.281   msaitoh 		for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
   3560  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_STATUS);
   3561  1.281   msaitoh 			if ((reg & STATUS_LAN_INIT_DONE) != 0)
   3562  1.281   msaitoh 				break;
   3563  1.281   msaitoh 			delay(100);
   3564  1.281   msaitoh 		}
   3565  1.281   msaitoh 		if (i >= WM_ICH8_LAN_INIT_TIMEOUT) {
   3566  1.281   msaitoh 			log(LOG_ERR, "%s: %s: lan_init_done failed to "
   3567  1.281   msaitoh 			    "complete\n", device_xname(sc->sc_dev), __func__);
   3568    1.1   thorpej 		}
   3569  1.281   msaitoh 		break;
   3570  1.281   msaitoh 	default:
   3571  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   3572  1.281   msaitoh 		    __func__);
   3573  1.281   msaitoh 		break;
   3574  1.281   msaitoh 	}
   3575    1.1   thorpej 
   3576  1.281   msaitoh 	reg &= ~STATUS_LAN_INIT_DONE;
   3577  1.281   msaitoh 	CSR_WRITE(sc, WMREG_STATUS, reg);
   3578  1.281   msaitoh }
   3579    1.6   thorpej 
   3580  1.281   msaitoh void
   3581  1.281   msaitoh wm_get_cfg_done(struct wm_softc *sc)
   3582  1.281   msaitoh {
   3583  1.281   msaitoh 	int mask;
   3584  1.281   msaitoh 	uint32_t reg;
   3585  1.281   msaitoh 	int i;
   3586    1.1   thorpej 
   3587  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3588  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   3589  1.420   msaitoh 
   3590  1.420   msaitoh 	/* Wait for eeprom to reload */
   3591  1.281   msaitoh 	switch (sc->sc_type) {
   3592  1.281   msaitoh 	case WM_T_82542_2_0:
   3593  1.281   msaitoh 	case WM_T_82542_2_1:
   3594  1.281   msaitoh 		/* null */
   3595  1.281   msaitoh 		break;
   3596  1.281   msaitoh 	case WM_T_82543:
   3597  1.281   msaitoh 	case WM_T_82544:
   3598  1.281   msaitoh 	case WM_T_82540:
   3599  1.281   msaitoh 	case WM_T_82545:
   3600  1.281   msaitoh 	case WM_T_82545_3:
   3601  1.281   msaitoh 	case WM_T_82546:
   3602  1.281   msaitoh 	case WM_T_82546_3:
   3603  1.281   msaitoh 	case WM_T_82541:
   3604  1.281   msaitoh 	case WM_T_82541_2:
   3605  1.281   msaitoh 	case WM_T_82547:
   3606  1.281   msaitoh 	case WM_T_82547_2:
   3607  1.281   msaitoh 	case WM_T_82573:
   3608  1.281   msaitoh 	case WM_T_82574:
   3609  1.281   msaitoh 	case WM_T_82583:
   3610  1.281   msaitoh 		/* generic */
   3611  1.281   msaitoh 		delay(10*1000);
   3612  1.281   msaitoh 		break;
   3613  1.281   msaitoh 	case WM_T_80003:
   3614  1.281   msaitoh 	case WM_T_82571:
   3615  1.281   msaitoh 	case WM_T_82572:
   3616  1.281   msaitoh 	case WM_T_82575:
   3617  1.281   msaitoh 	case WM_T_82576:
   3618  1.281   msaitoh 	case WM_T_82580:
   3619  1.281   msaitoh 	case WM_T_I350:
   3620  1.281   msaitoh 	case WM_T_I354:
   3621  1.281   msaitoh 	case WM_T_I210:
   3622  1.281   msaitoh 	case WM_T_I211:
   3623  1.281   msaitoh 		if (sc->sc_type == WM_T_82571) {
   3624  1.281   msaitoh 			/* Only 82571 shares port 0 */
   3625  1.281   msaitoh 			mask = EEMNGCTL_CFGDONE_0;
   3626  1.281   msaitoh 		} else
   3627  1.281   msaitoh 			mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid;
   3628  1.281   msaitoh 		for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) {
   3629  1.281   msaitoh 			if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
   3630  1.281   msaitoh 				break;
   3631  1.281   msaitoh 			delay(1000);
   3632  1.281   msaitoh 		}
   3633  1.281   msaitoh 		if (i >= WM_PHY_CFG_TIMEOUT) {
   3634  1.281   msaitoh 			DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n",
   3635  1.281   msaitoh 				device_xname(sc->sc_dev), __func__));
   3636  1.281   msaitoh 		}
   3637  1.281   msaitoh 		break;
   3638  1.281   msaitoh 	case WM_T_ICH8:
   3639  1.281   msaitoh 	case WM_T_ICH9:
   3640  1.281   msaitoh 	case WM_T_ICH10:
   3641  1.281   msaitoh 	case WM_T_PCH:
   3642  1.281   msaitoh 	case WM_T_PCH2:
   3643  1.281   msaitoh 	case WM_T_PCH_LPT:
   3644  1.392   msaitoh 	case WM_T_PCH_SPT:
   3645  1.281   msaitoh 		delay(10*1000);
   3646  1.281   msaitoh 		if (sc->sc_type >= WM_T_ICH10)
   3647  1.281   msaitoh 			wm_lan_init_done(sc);
   3648  1.281   msaitoh 		else
   3649  1.281   msaitoh 			wm_get_auto_rd_done(sc);
   3650    1.1   thorpej 
   3651  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_STATUS);
   3652  1.281   msaitoh 		if ((reg & STATUS_PHYRA) != 0)
   3653  1.281   msaitoh 			CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA);
   3654  1.281   msaitoh 		break;
   3655  1.281   msaitoh 	default:
   3656  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   3657  1.281   msaitoh 		    __func__);
   3658  1.281   msaitoh 		break;
   3659    1.1   thorpej 	}
   3660    1.1   thorpej }
   3661    1.1   thorpej 
   3662  1.517   msaitoh void
   3663  1.517   msaitoh wm_phy_post_reset(struct wm_softc *sc)
   3664  1.517   msaitoh {
   3665  1.517   msaitoh 	uint32_t reg;
   3666  1.517   msaitoh 
   3667  1.517   msaitoh 	/* This function is only for ICH8 and newer. */
   3668  1.517   msaitoh 	if (sc->sc_type < WM_T_ICH8)
   3669  1.517   msaitoh 		return;
   3670  1.517   msaitoh 
   3671  1.517   msaitoh 	if (wm_phy_resetisblocked(sc)) {
   3672  1.517   msaitoh 		/* XXX */
   3673  1.517   msaitoh 		device_printf(sc->sc_dev, " PHY is blocked\n");
   3674  1.517   msaitoh 		return;
   3675  1.517   msaitoh 	}
   3676  1.517   msaitoh 
   3677  1.517   msaitoh 	/* Allow time for h/w to get to quiescent state after reset */
   3678  1.517   msaitoh 	delay(10*1000);
   3679  1.517   msaitoh 
   3680  1.517   msaitoh 	/* Perform any necessary post-reset workarounds */
   3681  1.517   msaitoh 	if (sc->sc_type == WM_T_PCH)
   3682  1.517   msaitoh 		wm_hv_phy_workaround_ich8lan(sc);
   3683  1.517   msaitoh 	if (sc->sc_type == WM_T_PCH2)
   3684  1.517   msaitoh 		wm_lv_phy_workaround_ich8lan(sc);
   3685  1.517   msaitoh 
   3686  1.517   msaitoh 	/* Clear the host wakeup bit after lcd reset */
   3687  1.517   msaitoh 	if (sc->sc_type >= WM_T_PCH) {
   3688  1.517   msaitoh 		reg = wm_gmii_hv_readreg(sc->sc_dev, 2,
   3689  1.517   msaitoh 		    BM_PORT_GEN_CFG);
   3690  1.517   msaitoh 		reg &= ~BM_WUC_HOST_WU_BIT;
   3691  1.517   msaitoh 		wm_gmii_hv_writereg(sc->sc_dev, 2,
   3692  1.517   msaitoh 		    BM_PORT_GEN_CFG, reg);
   3693  1.517   msaitoh 	}
   3694  1.517   msaitoh 
   3695  1.517   msaitoh 	/*
   3696  1.517   msaitoh 	 * XXX Configure the LCD with th extended configuration region
   3697  1.517   msaitoh 	 * in NVM
   3698  1.517   msaitoh 	 */
   3699  1.517   msaitoh 
   3700  1.517   msaitoh 	/* Configure the LCD with the OEM bits in NVM */
   3701  1.517   msaitoh }
   3702  1.517   msaitoh 
   3703  1.312   msaitoh /* Init hardware bits */
   3704  1.312   msaitoh void
   3705  1.312   msaitoh wm_initialize_hardware_bits(struct wm_softc *sc)
   3706  1.312   msaitoh {
   3707  1.312   msaitoh 	uint32_t tarc0, tarc1, reg;
   3708  1.332   msaitoh 
   3709  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3710  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3711  1.420   msaitoh 
   3712  1.312   msaitoh 	/* For 82571 variant, 80003 and ICHs */
   3713  1.312   msaitoh 	if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583))
   3714  1.312   msaitoh 	    || (sc->sc_type >= WM_T_80003)) {
   3715  1.312   msaitoh 
   3716  1.312   msaitoh 		/* Transmit Descriptor Control 0 */
   3717  1.312   msaitoh 		reg = CSR_READ(sc, WMREG_TXDCTL(0));
   3718  1.312   msaitoh 		reg |= TXDCTL_COUNT_DESC;
   3719  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TXDCTL(0), reg);
   3720  1.312   msaitoh 
   3721  1.312   msaitoh 		/* Transmit Descriptor Control 1 */
   3722  1.312   msaitoh 		reg = CSR_READ(sc, WMREG_TXDCTL(1));
   3723  1.312   msaitoh 		reg |= TXDCTL_COUNT_DESC;
   3724  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TXDCTL(1), reg);
   3725  1.312   msaitoh 
   3726  1.312   msaitoh 		/* TARC0 */
   3727  1.312   msaitoh 		tarc0 = CSR_READ(sc, WMREG_TARC0);
   3728  1.312   msaitoh 		switch (sc->sc_type) {
   3729  1.312   msaitoh 		case WM_T_82571:
   3730  1.312   msaitoh 		case WM_T_82572:
   3731  1.312   msaitoh 		case WM_T_82573:
   3732  1.312   msaitoh 		case WM_T_82574:
   3733  1.312   msaitoh 		case WM_T_82583:
   3734  1.312   msaitoh 		case WM_T_80003:
   3735  1.312   msaitoh 			/* Clear bits 30..27 */
   3736  1.312   msaitoh 			tarc0 &= ~__BITS(30, 27);
   3737  1.312   msaitoh 			break;
   3738  1.312   msaitoh 		default:
   3739  1.312   msaitoh 			break;
   3740  1.312   msaitoh 		}
   3741  1.312   msaitoh 
   3742  1.312   msaitoh 		switch (sc->sc_type) {
   3743  1.312   msaitoh 		case WM_T_82571:
   3744  1.312   msaitoh 		case WM_T_82572:
   3745  1.312   msaitoh 			tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */
   3746  1.312   msaitoh 
   3747  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   3748  1.312   msaitoh 			tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */
   3749  1.312   msaitoh 			tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */
   3750  1.312   msaitoh 			/* 8257[12] Errata No.7 */
   3751  1.312   msaitoh 			tarc1 |= __BIT(22); /* TARC1 bits 22 */
   3752  1.312   msaitoh 
   3753  1.312   msaitoh 			/* TARC1 bit 28 */
   3754  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   3755  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   3756  1.312   msaitoh 			else
   3757  1.312   msaitoh 				tarc1 |= __BIT(28);
   3758  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   3759  1.312   msaitoh 
   3760  1.312   msaitoh 			/*
   3761  1.312   msaitoh 			 * 8257[12] Errata No.13
   3762  1.312   msaitoh 			 * Disable Dyamic Clock Gating.
   3763  1.312   msaitoh 			 */
   3764  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   3765  1.312   msaitoh 			reg &= ~CTRL_EXT_DMA_DYN_CLK;
   3766  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   3767  1.312   msaitoh 			break;
   3768  1.312   msaitoh 		case WM_T_82573:
   3769  1.312   msaitoh 		case WM_T_82574:
   3770  1.312   msaitoh 		case WM_T_82583:
   3771  1.312   msaitoh 			if ((sc->sc_type == WM_T_82574)
   3772  1.312   msaitoh 			    || (sc->sc_type == WM_T_82583))
   3773  1.312   msaitoh 				tarc0 |= __BIT(26); /* TARC0 bit 26 */
   3774  1.312   msaitoh 
   3775  1.312   msaitoh 			/* Extended Device Control */
   3776  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   3777  1.312   msaitoh 			reg &= ~__BIT(23);	/* Clear bit 23 */
   3778  1.312   msaitoh 			reg |= __BIT(22);	/* Set bit 22 */
   3779  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   3780  1.312   msaitoh 
   3781  1.312   msaitoh 			/* Device Control */
   3782  1.312   msaitoh 			sc->sc_ctrl &= ~__BIT(29);	/* Clear bit 29 */
   3783  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3784  1.312   msaitoh 
   3785  1.312   msaitoh 			/* PCIe Control Register */
   3786  1.350   msaitoh 			/*
   3787  1.350   msaitoh 			 * 82573 Errata (unknown).
   3788  1.350   msaitoh 			 *
   3789  1.350   msaitoh 			 * 82574 Errata 25 and 82583 Errata 12
   3790  1.350   msaitoh 			 * "Dropped Rx Packets":
   3791  1.350   msaitoh 			 *   NVM Image Version 2.1.4 and newer has no this bug.
   3792  1.350   msaitoh 			 */
   3793  1.350   msaitoh 			reg = CSR_READ(sc, WMREG_GCR);
   3794  1.350   msaitoh 			reg |= GCR_L1_ACT_WITHOUT_L0S_RX;
   3795  1.350   msaitoh 			CSR_WRITE(sc, WMREG_GCR, reg);
   3796  1.350   msaitoh 
   3797  1.312   msaitoh 			if ((sc->sc_type == WM_T_82574)
   3798  1.312   msaitoh 			    || (sc->sc_type == WM_T_82583)) {
   3799  1.312   msaitoh 				/*
   3800  1.312   msaitoh 				 * Document says this bit must be set for
   3801  1.312   msaitoh 				 * proper operation.
   3802  1.312   msaitoh 				 */
   3803  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_GCR);
   3804  1.312   msaitoh 				reg |= __BIT(22);
   3805  1.312   msaitoh 				CSR_WRITE(sc, WMREG_GCR, reg);
   3806  1.312   msaitoh 
   3807  1.312   msaitoh 				/*
   3808  1.312   msaitoh 				 * Apply workaround for hardware errata
   3809  1.312   msaitoh 				 * documented in errata docs Fixes issue where
   3810  1.312   msaitoh 				 * some error prone or unreliable PCIe
   3811  1.312   msaitoh 				 * completions are occurring, particularly
   3812  1.312   msaitoh 				 * with ASPM enabled. Without fix, issue can
   3813  1.312   msaitoh 				 * cause Tx timeouts.
   3814  1.312   msaitoh 				 */
   3815  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_GCR2);
   3816  1.312   msaitoh 				reg |= __BIT(0);
   3817  1.312   msaitoh 				CSR_WRITE(sc, WMREG_GCR2, reg);
   3818  1.312   msaitoh 			}
   3819  1.312   msaitoh 			break;
   3820  1.312   msaitoh 		case WM_T_80003:
   3821  1.312   msaitoh 			/* TARC0 */
   3822  1.312   msaitoh 			if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
   3823  1.312   msaitoh 			    || (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   3824  1.312   msaitoh 				tarc0 &= ~__BIT(20); /* Clear bits 20 */
   3825  1.312   msaitoh 
   3826  1.312   msaitoh 			/* TARC1 bit 28 */
   3827  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   3828  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   3829  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   3830  1.312   msaitoh 			else
   3831  1.312   msaitoh 				tarc1 |= __BIT(28);
   3832  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   3833  1.312   msaitoh 			break;
   3834  1.312   msaitoh 		case WM_T_ICH8:
   3835  1.312   msaitoh 		case WM_T_ICH9:
   3836  1.312   msaitoh 		case WM_T_ICH10:
   3837  1.312   msaitoh 		case WM_T_PCH:
   3838  1.312   msaitoh 		case WM_T_PCH2:
   3839  1.312   msaitoh 		case WM_T_PCH_LPT:
   3840  1.393   msaitoh 		case WM_T_PCH_SPT:
   3841  1.393   msaitoh 			/* TARC0 */
   3842  1.393   msaitoh 			if ((sc->sc_type == WM_T_ICH8)
   3843  1.393   msaitoh 			    || (sc->sc_type == WM_T_PCH_SPT)) {
   3844  1.312   msaitoh 				/* Set TARC0 bits 29 and 28 */
   3845  1.312   msaitoh 				tarc0 |= __BITS(29, 28);
   3846  1.312   msaitoh 			}
   3847  1.312   msaitoh 			/* Set TARC0 bits 23,24,26,27 */
   3848  1.312   msaitoh 			tarc0 |= __BITS(27, 26) | __BITS(24, 23);
   3849  1.312   msaitoh 
   3850  1.312   msaitoh 			/* CTRL_EXT */
   3851  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   3852  1.312   msaitoh 			reg |= __BIT(22);	/* Set bit 22 */
   3853  1.312   msaitoh 			/*
   3854  1.312   msaitoh 			 * Enable PHY low-power state when MAC is at D3
   3855  1.312   msaitoh 			 * w/o WoL
   3856  1.312   msaitoh 			 */
   3857  1.312   msaitoh 			if (sc->sc_type >= WM_T_PCH)
   3858  1.312   msaitoh 				reg |= CTRL_EXT_PHYPDEN;
   3859  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   3860  1.312   msaitoh 
   3861  1.312   msaitoh 			/* TARC1 */
   3862  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   3863  1.312   msaitoh 			/* bit 28 */
   3864  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   3865  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   3866  1.312   msaitoh 			else
   3867  1.312   msaitoh 				tarc1 |= __BIT(28);
   3868  1.312   msaitoh 			tarc1 |= __BIT(24) | __BIT(26) | __BIT(30);
   3869  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   3870  1.312   msaitoh 
   3871  1.312   msaitoh 			/* Device Status */
   3872  1.312   msaitoh 			if (sc->sc_type == WM_T_ICH8) {
   3873  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_STATUS);
   3874  1.312   msaitoh 				reg &= ~__BIT(31);
   3875  1.312   msaitoh 				CSR_WRITE(sc, WMREG_STATUS, reg);
   3876  1.312   msaitoh 
   3877  1.312   msaitoh 			}
   3878  1.312   msaitoh 
   3879  1.393   msaitoh 			/* IOSFPC */
   3880  1.393   msaitoh 			if (sc->sc_type == WM_T_PCH_SPT) {
   3881  1.393   msaitoh 				reg = CSR_READ(sc, WMREG_IOSFPC);
   3882  1.393   msaitoh 				reg |= RCTL_RDMTS_HEX; /* XXX RTCL bit? */
   3883  1.393   msaitoh 				CSR_WRITE(sc, WMREG_IOSFPC, reg);
   3884  1.393   msaitoh 			}
   3885  1.312   msaitoh 			/*
   3886  1.312   msaitoh 			 * Work-around descriptor data corruption issue during
   3887  1.312   msaitoh 			 * NFS v2 UDP traffic, just disable the NFS filtering
   3888  1.312   msaitoh 			 * capability.
   3889  1.312   msaitoh 			 */
   3890  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_RFCTL);
   3891  1.312   msaitoh 			reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS;
   3892  1.312   msaitoh 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   3893  1.312   msaitoh 			break;
   3894  1.312   msaitoh 		default:
   3895  1.312   msaitoh 			break;
   3896  1.312   msaitoh 		}
   3897  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TARC0, tarc0);
   3898  1.312   msaitoh 
   3899  1.462   msaitoh 		switch (sc->sc_type) {
   3900  1.312   msaitoh 		/*
   3901  1.462   msaitoh 		 * 8257[12] Errata No.52, 82573 Errata No.43 and some others.
   3902  1.312   msaitoh 		 * Avoid RSS Hash Value bug.
   3903  1.312   msaitoh 		 */
   3904  1.312   msaitoh 		case WM_T_82571:
   3905  1.312   msaitoh 		case WM_T_82572:
   3906  1.312   msaitoh 		case WM_T_82573:
   3907  1.312   msaitoh 		case WM_T_80003:
   3908  1.312   msaitoh 		case WM_T_ICH8:
   3909  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_RFCTL);
   3910  1.312   msaitoh 			reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS;
   3911  1.312   msaitoh 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   3912  1.312   msaitoh 			break;
   3913  1.466  knakahar 		case WM_T_82574:
   3914  1.466  knakahar 			/* use extened Rx descriptor. */
   3915  1.466  knakahar 			reg = CSR_READ(sc, WMREG_RFCTL);
   3916  1.466  knakahar 			reg |= WMREG_RFCTL_EXSTEN;
   3917  1.466  knakahar 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   3918  1.466  knakahar 			break;
   3919  1.464   msaitoh 		default:
   3920  1.464   msaitoh 			break;
   3921  1.464   msaitoh 		}
   3922  1.464   msaitoh 	} else if ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211)) {
   3923  1.462   msaitoh 		/*
   3924  1.462   msaitoh 		 * 82575 Errata XXX, 82576 Errata 46, 82580 Errata 24,
   3925  1.462   msaitoh 		 * I350 Errata 37, I210 Errata No. 31 and I211 Errata No. 11:
   3926  1.462   msaitoh 		 * "Certain Malformed IPv6 Extension Headers are Not Processed
   3927  1.462   msaitoh 		 * Correctly by the Device"
   3928  1.462   msaitoh 		 *
   3929  1.462   msaitoh 		 * I354(C2000) Errata AVR53:
   3930  1.462   msaitoh 		 * "Malformed IPv6 Extension Headers May Result in LAN Device
   3931  1.462   msaitoh 		 * Hang"
   3932  1.462   msaitoh 		 */
   3933  1.464   msaitoh 		reg = CSR_READ(sc, WMREG_RFCTL);
   3934  1.464   msaitoh 		reg |= WMREG_RFCTL_IPV6EXDIS;
   3935  1.464   msaitoh 		CSR_WRITE(sc, WMREG_RFCTL, reg);
   3936  1.312   msaitoh 	}
   3937  1.312   msaitoh }
   3938  1.312   msaitoh 
   3939  1.320   msaitoh static uint32_t
   3940  1.320   msaitoh wm_rxpbs_adjust_82580(uint32_t val)
   3941  1.320   msaitoh {
   3942  1.320   msaitoh 	uint32_t rv = 0;
   3943  1.320   msaitoh 
   3944  1.320   msaitoh 	if (val < __arraycount(wm_82580_rxpbs_table))
   3945  1.320   msaitoh 		rv = wm_82580_rxpbs_table[val];
   3946  1.320   msaitoh 
   3947  1.320   msaitoh 	return rv;
   3948  1.320   msaitoh }
   3949  1.320   msaitoh 
   3950  1.447   msaitoh /*
   3951  1.447   msaitoh  * wm_reset_phy:
   3952  1.447   msaitoh  *
   3953  1.447   msaitoh  *	generic PHY reset function.
   3954  1.447   msaitoh  *	Same as e1000_phy_hw_reset_generic()
   3955  1.447   msaitoh  */
   3956  1.447   msaitoh static void
   3957  1.447   msaitoh wm_reset_phy(struct wm_softc *sc)
   3958  1.447   msaitoh {
   3959  1.447   msaitoh 	uint32_t reg;
   3960  1.447   msaitoh 
   3961  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3962  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   3963  1.447   msaitoh 	if (wm_phy_resetisblocked(sc))
   3964  1.447   msaitoh 		return;
   3965  1.447   msaitoh 
   3966  1.447   msaitoh 	sc->phy.acquire(sc);
   3967  1.447   msaitoh 
   3968  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL);
   3969  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);
   3970  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   3971  1.447   msaitoh 
   3972  1.447   msaitoh 	delay(sc->phy.reset_delay_us);
   3973  1.447   msaitoh 
   3974  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   3975  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   3976  1.447   msaitoh 
   3977  1.447   msaitoh 	delay(150);
   3978  1.447   msaitoh 
   3979  1.447   msaitoh 	sc->phy.release(sc);
   3980  1.447   msaitoh 
   3981  1.447   msaitoh 	wm_get_cfg_done(sc);
   3982  1.517   msaitoh 	wm_phy_post_reset(sc);
   3983  1.447   msaitoh }
   3984  1.447   msaitoh 
   3985  1.443   msaitoh static void
   3986  1.443   msaitoh wm_flush_desc_rings(struct wm_softc *sc)
   3987  1.443   msaitoh {
   3988  1.443   msaitoh 	pcireg_t preg;
   3989  1.443   msaitoh 	uint32_t reg;
   3990  1.443   msaitoh 	int nexttx;
   3991  1.443   msaitoh 
   3992  1.443   msaitoh 	/* First, disable MULR fix in FEXTNVM11 */
   3993  1.443   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM11);
   3994  1.443   msaitoh 	reg |= FEXTNVM11_DIS_MULRFIX;
   3995  1.443   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM11, reg);
   3996  1.443   msaitoh 
   3997  1.443   msaitoh 	preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, WM_PCI_DESCRING_STATUS);
   3998  1.443   msaitoh 	reg = CSR_READ(sc, WMREG_TDLEN(0));
   3999  1.443   msaitoh 	if (((preg & DESCRING_STATUS_FLUSH_REQ) != 0) && (reg != 0)) {
   4000  1.443   msaitoh 		struct wm_txqueue *txq;
   4001  1.443   msaitoh 		wiseman_txdesc_t *txd;
   4002  1.443   msaitoh 
   4003  1.443   msaitoh 		/* TX */
   4004  1.443   msaitoh 		printf("%s: Need TX flush (reg = %08x, len = %u)\n",
   4005  1.443   msaitoh 		    device_xname(sc->sc_dev), preg, reg);
   4006  1.443   msaitoh 		reg = CSR_READ(sc, WMREG_TCTL);
   4007  1.443   msaitoh 		CSR_WRITE(sc, WMREG_TCTL, reg | TCTL_EN);
   4008  1.443   msaitoh 
   4009  1.443   msaitoh 		txq = &sc->sc_queue[0].wmq_txq;
   4010  1.443   msaitoh 		nexttx = txq->txq_next;
   4011  1.443   msaitoh 		txd = &txq->txq_descs[nexttx];
   4012  1.443   msaitoh 		wm_set_dma_addr(&txd->wtx_addr, WM_CDTXADDR(txq, nexttx));
   4013  1.443   msaitoh 		txd->wtx_cmdlen = htole32(WTX_CMD_IFCS| 512);
   4014  1.443   msaitoh 		txd->wtx_fields.wtxu_status = 0;
   4015  1.443   msaitoh 		txd->wtx_fields.wtxu_options = 0;
   4016  1.443   msaitoh 		txd->wtx_fields.wtxu_vlan = 0;
   4017  1.443   msaitoh 
   4018  1.443   msaitoh 		bus_space_barrier(sc->sc_st, sc->sc_sh, 0, 0,
   4019  1.443   msaitoh 			BUS_SPACE_BARRIER_WRITE);
   4020  1.443   msaitoh 
   4021  1.443   msaitoh 		txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   4022  1.443   msaitoh 		CSR_WRITE(sc, WMREG_TDT(0), txq->txq_next);
   4023  1.443   msaitoh 		bus_space_barrier(sc->sc_st, sc->sc_sh, 0, 0,
   4024  1.443   msaitoh 			BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
   4025  1.443   msaitoh 		delay(250);
   4026  1.443   msaitoh 	}
   4027  1.443   msaitoh 	preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, WM_PCI_DESCRING_STATUS);
   4028  1.443   msaitoh 	if (preg & DESCRING_STATUS_FLUSH_REQ) {
   4029  1.443   msaitoh 		uint32_t rctl;
   4030  1.443   msaitoh 
   4031  1.443   msaitoh 		/* RX */
   4032  1.443   msaitoh 		printf("%s: Need RX flush (reg = %08x)\n",
   4033  1.443   msaitoh 		    device_xname(sc->sc_dev), preg);
   4034  1.443   msaitoh 		rctl = CSR_READ(sc, WMREG_RCTL);
   4035  1.443   msaitoh 		CSR_WRITE(sc, WMREG_RCTL, rctl & ~RCTL_EN);
   4036  1.443   msaitoh 		CSR_WRITE_FLUSH(sc);
   4037  1.443   msaitoh 		delay(150);
   4038  1.443   msaitoh 
   4039  1.443   msaitoh 		reg = CSR_READ(sc, WMREG_RXDCTL(0));
   4040  1.443   msaitoh 		/* zero the lower 14 bits (prefetch and host thresholds) */
   4041  1.443   msaitoh 		reg &= 0xffffc000;
   4042  1.443   msaitoh 		/*
   4043  1.443   msaitoh 		 * update thresholds: prefetch threshold to 31, host threshold
   4044  1.443   msaitoh 		 * to 1 and make sure the granularity is "descriptors" and not
   4045  1.443   msaitoh 		 * "cache lines"
   4046  1.443   msaitoh 		 */
   4047  1.443   msaitoh 		reg |= (0x1f | (1 << 8) | RXDCTL_GRAN);
   4048  1.443   msaitoh 		CSR_WRITE(sc, WMREG_RXDCTL(0), reg);
   4049  1.443   msaitoh 
   4050  1.443   msaitoh 		/*
   4051  1.443   msaitoh 		 * momentarily enable the RX ring for the changes to take
   4052  1.443   msaitoh 		 * effect
   4053  1.443   msaitoh 		 */
   4054  1.443   msaitoh 		CSR_WRITE(sc, WMREG_RCTL, rctl | RCTL_EN);
   4055  1.443   msaitoh 		CSR_WRITE_FLUSH(sc);
   4056  1.443   msaitoh 		delay(150);
   4057  1.443   msaitoh 		CSR_WRITE(sc, WMREG_RCTL, rctl & ~RCTL_EN);
   4058  1.443   msaitoh 	}
   4059  1.443   msaitoh }
   4060  1.443   msaitoh 
   4061    1.1   thorpej /*
   4062  1.281   msaitoh  * wm_reset:
   4063  1.232    bouyer  *
   4064  1.281   msaitoh  *	Reset the i82542 chip.
   4065  1.232    bouyer  */
   4066  1.281   msaitoh static void
   4067  1.281   msaitoh wm_reset(struct wm_softc *sc)
   4068  1.232    bouyer {
   4069  1.281   msaitoh 	int phy_reset = 0;
   4070  1.364  knakahar 	int i, error = 0;
   4071  1.424   msaitoh 	uint32_t reg;
   4072  1.232    bouyer 
   4073  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   4074  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   4075  1.420   msaitoh 	KASSERT(sc->sc_type != 0);
   4076  1.420   msaitoh 
   4077  1.232    bouyer 	/*
   4078  1.281   msaitoh 	 * Allocate on-chip memory according to the MTU size.
   4079  1.281   msaitoh 	 * The Packet Buffer Allocation register must be written
   4080  1.281   msaitoh 	 * before the chip is reset.
   4081  1.232    bouyer 	 */
   4082  1.281   msaitoh 	switch (sc->sc_type) {
   4083  1.281   msaitoh 	case WM_T_82547:
   4084  1.281   msaitoh 	case WM_T_82547_2:
   4085  1.281   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   4086  1.281   msaitoh 		    PBA_22K : PBA_30K;
   4087  1.405  knakahar 		for (i = 0; i < sc->sc_nqueues; i++) {
   4088  1.405  knakahar 			struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   4089  1.364  knakahar 			txq->txq_fifo_head = 0;
   4090  1.364  knakahar 			txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
   4091  1.364  knakahar 			txq->txq_fifo_size =
   4092  1.364  knakahar 				(PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
   4093  1.364  knakahar 			txq->txq_fifo_stall = 0;
   4094  1.364  knakahar 		}
   4095  1.281   msaitoh 		break;
   4096  1.281   msaitoh 	case WM_T_82571:
   4097  1.281   msaitoh 	case WM_T_82572:
   4098  1.281   msaitoh 	case WM_T_82575:	/* XXX need special handing for jumbo frames */
   4099  1.281   msaitoh 	case WM_T_80003:
   4100  1.281   msaitoh 		sc->sc_pba = PBA_32K;
   4101  1.281   msaitoh 		break;
   4102  1.281   msaitoh 	case WM_T_82573:
   4103  1.281   msaitoh 		sc->sc_pba = PBA_12K;
   4104  1.281   msaitoh 		break;
   4105  1.281   msaitoh 	case WM_T_82574:
   4106  1.281   msaitoh 	case WM_T_82583:
   4107  1.281   msaitoh 		sc->sc_pba = PBA_20K;
   4108  1.281   msaitoh 		break;
   4109  1.320   msaitoh 	case WM_T_82576:
   4110  1.320   msaitoh 		sc->sc_pba = CSR_READ(sc, WMREG_RXPBS);
   4111  1.320   msaitoh 		sc->sc_pba &= RXPBS_SIZE_MASK_82576;
   4112  1.320   msaitoh 		break;
   4113  1.320   msaitoh 	case WM_T_82580:
   4114  1.320   msaitoh 	case WM_T_I350:
   4115  1.320   msaitoh 	case WM_T_I354:
   4116  1.320   msaitoh 		sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS));
   4117  1.320   msaitoh 		break;
   4118  1.320   msaitoh 	case WM_T_I210:
   4119  1.320   msaitoh 	case WM_T_I211:
   4120  1.320   msaitoh 		sc->sc_pba = PBA_34K;
   4121  1.320   msaitoh 		break;
   4122  1.281   msaitoh 	case WM_T_ICH8:
   4123  1.312   msaitoh 		/* Workaround for a bit corruption issue in FIFO memory */
   4124  1.281   msaitoh 		sc->sc_pba = PBA_8K;
   4125  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBS, PBA_16K);
   4126  1.281   msaitoh 		break;
   4127  1.281   msaitoh 	case WM_T_ICH9:
   4128  1.281   msaitoh 	case WM_T_ICH10:
   4129  1.318   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ?
   4130  1.318   msaitoh 		    PBA_14K : PBA_10K;
   4131  1.232    bouyer 		break;
   4132  1.281   msaitoh 	case WM_T_PCH:
   4133  1.281   msaitoh 	case WM_T_PCH2:
   4134  1.281   msaitoh 	case WM_T_PCH_LPT:
   4135  1.392   msaitoh 	case WM_T_PCH_SPT:
   4136  1.281   msaitoh 		sc->sc_pba = PBA_26K;
   4137  1.232    bouyer 		break;
   4138  1.232    bouyer 	default:
   4139  1.281   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   4140  1.281   msaitoh 		    PBA_40K : PBA_48K;
   4141  1.281   msaitoh 		break;
   4142  1.232    bouyer 	}
   4143  1.320   msaitoh 	/*
   4144  1.320   msaitoh 	 * Only old or non-multiqueue devices have the PBA register
   4145  1.320   msaitoh 	 * XXX Need special handling for 82575.
   4146  1.320   msaitoh 	 */
   4147  1.320   msaitoh 	if (((sc->sc_flags & WM_F_NEWQUEUE) == 0)
   4148  1.320   msaitoh 	    || (sc->sc_type == WM_T_82575))
   4149  1.320   msaitoh 		CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
   4150  1.232    bouyer 
   4151  1.281   msaitoh 	/* Prevent the PCI-E bus from sticking */
   4152  1.281   msaitoh 	if (sc->sc_flags & WM_F_PCIE) {
   4153  1.281   msaitoh 		int timeout = 800;
   4154  1.232    bouyer 
   4155  1.281   msaitoh 		sc->sc_ctrl |= CTRL_GIO_M_DIS;
   4156  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4157  1.232    bouyer 
   4158  1.281   msaitoh 		while (timeout--) {
   4159  1.281   msaitoh 			if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA)
   4160  1.281   msaitoh 			    == 0)
   4161  1.281   msaitoh 				break;
   4162  1.281   msaitoh 			delay(100);
   4163  1.281   msaitoh 		}
   4164  1.511   msaitoh 		if (timeout == 0)
   4165  1.511   msaitoh 			device_printf(sc->sc_dev,
   4166  1.511   msaitoh 			    "failed to disable busmastering\n");
   4167  1.232    bouyer 	}
   4168  1.232    bouyer 
   4169  1.281   msaitoh 	/* Set the completion timeout for interface */
   4170  1.281   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   4171  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   4172  1.282   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   4173  1.282   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
   4174  1.281   msaitoh 		wm_set_pcie_completion_timeout(sc);
   4175  1.232    bouyer 
   4176  1.281   msaitoh 	/* Clear interrupt */
   4177  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   4178  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   4179  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   4180  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   4181  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   4182  1.335   msaitoh 		} else {
   4183  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   4184  1.335   msaitoh 		}
   4185  1.335   msaitoh 	}
   4186  1.232    bouyer 
   4187  1.281   msaitoh 	/* Stop the transmit and receive processes. */
   4188  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, 0);
   4189  1.281   msaitoh 	sc->sc_rctl &= ~RCTL_EN;
   4190  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP);
   4191  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   4192  1.232    bouyer 
   4193  1.281   msaitoh 	/* XXX set_tbi_sbp_82543() */
   4194  1.232    bouyer 
   4195  1.281   msaitoh 	delay(10*1000);
   4196  1.232    bouyer 
   4197  1.281   msaitoh 	/* Must acquire the MDIO ownership before MAC reset */
   4198  1.281   msaitoh 	switch (sc->sc_type) {
   4199  1.281   msaitoh 	case WM_T_82573:
   4200  1.281   msaitoh 	case WM_T_82574:
   4201  1.281   msaitoh 	case WM_T_82583:
   4202  1.281   msaitoh 		error = wm_get_hw_semaphore_82573(sc);
   4203  1.281   msaitoh 		break;
   4204  1.281   msaitoh 	default:
   4205  1.281   msaitoh 		break;
   4206  1.281   msaitoh 	}
   4207  1.232    bouyer 
   4208  1.281   msaitoh 	/*
   4209  1.281   msaitoh 	 * 82541 Errata 29? & 82547 Errata 28?
   4210  1.281   msaitoh 	 * See also the description about PHY_RST bit in CTRL register
   4211  1.281   msaitoh 	 * in 8254x_GBe_SDM.pdf.
   4212  1.281   msaitoh 	 */
   4213  1.281   msaitoh 	if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) {
   4214  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL,
   4215  1.281   msaitoh 		    CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
   4216  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   4217  1.281   msaitoh 		delay(5000);
   4218  1.281   msaitoh 	}
   4219  1.232    bouyer 
   4220  1.281   msaitoh 	switch (sc->sc_type) {
   4221  1.281   msaitoh 	case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */
   4222  1.281   msaitoh 	case WM_T_82541:
   4223  1.281   msaitoh 	case WM_T_82541_2:
   4224  1.281   msaitoh 	case WM_T_82547:
   4225  1.281   msaitoh 	case WM_T_82547_2:
   4226  1.281   msaitoh 		/*
   4227  1.281   msaitoh 		 * On some chipsets, a reset through a memory-mapped write
   4228  1.281   msaitoh 		 * cycle can cause the chip to reset before completing the
   4229  1.281   msaitoh 		 * write cycle.  This causes major headache that can be
   4230  1.281   msaitoh 		 * avoided by issuing the reset via indirect register writes
   4231  1.281   msaitoh 		 * through I/O space.
   4232  1.281   msaitoh 		 *
   4233  1.281   msaitoh 		 * So, if we successfully mapped the I/O BAR at attach time,
   4234  1.281   msaitoh 		 * use that.  Otherwise, try our luck with a memory-mapped
   4235  1.281   msaitoh 		 * reset.
   4236  1.281   msaitoh 		 */
   4237  1.281   msaitoh 		if (sc->sc_flags & WM_F_IOH_VALID)
   4238  1.281   msaitoh 			wm_io_write(sc, WMREG_CTRL, CTRL_RST);
   4239  1.281   msaitoh 		else
   4240  1.281   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
   4241  1.281   msaitoh 		break;
   4242  1.281   msaitoh 	case WM_T_82545_3:
   4243  1.281   msaitoh 	case WM_T_82546_3:
   4244  1.281   msaitoh 		/* Use the shadow control register on these chips. */
   4245  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
   4246  1.281   msaitoh 		break;
   4247  1.281   msaitoh 	case WM_T_80003:
   4248  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
   4249  1.424   msaitoh 		sc->phy.acquire(sc);
   4250  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg);
   4251  1.424   msaitoh 		sc->phy.release(sc);
   4252  1.281   msaitoh 		break;
   4253  1.281   msaitoh 	case WM_T_ICH8:
   4254  1.281   msaitoh 	case WM_T_ICH9:
   4255  1.281   msaitoh 	case WM_T_ICH10:
   4256  1.281   msaitoh 	case WM_T_PCH:
   4257  1.281   msaitoh 	case WM_T_PCH2:
   4258  1.281   msaitoh 	case WM_T_PCH_LPT:
   4259  1.392   msaitoh 	case WM_T_PCH_SPT:
   4260  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
   4261  1.386   msaitoh 		if (wm_phy_resetisblocked(sc) == false) {
   4262  1.232    bouyer 			/*
   4263  1.281   msaitoh 			 * Gate automatic PHY configuration by hardware on
   4264  1.281   msaitoh 			 * non-managed 82579
   4265  1.232    bouyer 			 */
   4266  1.281   msaitoh 			if ((sc->sc_type == WM_T_PCH2)
   4267  1.281   msaitoh 			    && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
   4268  1.380   msaitoh 				== 0))
   4269  1.392   msaitoh 				wm_gate_hw_phy_config_ich8lan(sc, true);
   4270  1.232    bouyer 
   4271  1.281   msaitoh 			reg |= CTRL_PHY_RESET;
   4272  1.281   msaitoh 			phy_reset = 1;
   4273  1.394   msaitoh 		} else
   4274  1.394   msaitoh 			printf("XXX reset is blocked!!!\n");
   4275  1.424   msaitoh 		sc->phy.acquire(sc);
   4276  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg);
   4277  1.281   msaitoh 		/* Don't insert a completion barrier when reset */
   4278  1.281   msaitoh 		delay(20*1000);
   4279  1.424   msaitoh 		mutex_exit(sc->sc_ich_phymtx);
   4280  1.281   msaitoh 		break;
   4281  1.304   msaitoh 	case WM_T_82580:
   4282  1.304   msaitoh 	case WM_T_I350:
   4283  1.304   msaitoh 	case WM_T_I354:
   4284  1.304   msaitoh 	case WM_T_I210:
   4285  1.304   msaitoh 	case WM_T_I211:
   4286  1.304   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
   4287  1.304   msaitoh 		if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII)
   4288  1.304   msaitoh 			CSR_WRITE_FLUSH(sc);
   4289  1.304   msaitoh 		delay(5000);
   4290  1.304   msaitoh 		break;
   4291  1.281   msaitoh 	case WM_T_82542_2_0:
   4292  1.281   msaitoh 	case WM_T_82542_2_1:
   4293  1.281   msaitoh 	case WM_T_82543:
   4294  1.281   msaitoh 	case WM_T_82540:
   4295  1.281   msaitoh 	case WM_T_82545:
   4296  1.281   msaitoh 	case WM_T_82546:
   4297  1.281   msaitoh 	case WM_T_82571:
   4298  1.281   msaitoh 	case WM_T_82572:
   4299  1.281   msaitoh 	case WM_T_82573:
   4300  1.281   msaitoh 	case WM_T_82574:
   4301  1.281   msaitoh 	case WM_T_82575:
   4302  1.281   msaitoh 	case WM_T_82576:
   4303  1.281   msaitoh 	case WM_T_82583:
   4304  1.281   msaitoh 	default:
   4305  1.281   msaitoh 		/* Everything else can safely use the documented method. */
   4306  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
   4307  1.281   msaitoh 		break;
   4308  1.281   msaitoh 	}
   4309  1.232    bouyer 
   4310  1.281   msaitoh 	/* Must release the MDIO ownership after MAC reset */
   4311  1.281   msaitoh 	switch (sc->sc_type) {
   4312  1.281   msaitoh 	case WM_T_82573:
   4313  1.281   msaitoh 	case WM_T_82574:
   4314  1.281   msaitoh 	case WM_T_82583:
   4315  1.281   msaitoh 		if (error == 0)
   4316  1.281   msaitoh 			wm_put_hw_semaphore_82573(sc);
   4317  1.281   msaitoh 		break;
   4318  1.281   msaitoh 	default:
   4319  1.281   msaitoh 		break;
   4320  1.232    bouyer 	}
   4321  1.232    bouyer 
   4322  1.437   msaitoh 	if (phy_reset != 0)
   4323  1.281   msaitoh 		wm_get_cfg_done(sc);
   4324  1.232    bouyer 
   4325  1.281   msaitoh 	/* reload EEPROM */
   4326  1.281   msaitoh 	switch (sc->sc_type) {
   4327  1.281   msaitoh 	case WM_T_82542_2_0:
   4328  1.281   msaitoh 	case WM_T_82542_2_1:
   4329  1.281   msaitoh 	case WM_T_82543:
   4330  1.281   msaitoh 	case WM_T_82544:
   4331  1.281   msaitoh 		delay(10);
   4332  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
   4333  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4334  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   4335  1.281   msaitoh 		delay(2000);
   4336  1.281   msaitoh 		break;
   4337  1.281   msaitoh 	case WM_T_82540:
   4338  1.281   msaitoh 	case WM_T_82545:
   4339  1.281   msaitoh 	case WM_T_82545_3:
   4340  1.281   msaitoh 	case WM_T_82546:
   4341  1.281   msaitoh 	case WM_T_82546_3:
   4342  1.281   msaitoh 		delay(5*1000);
   4343  1.281   msaitoh 		/* XXX Disable HW ARPs on ASF enabled adapters */
   4344  1.281   msaitoh 		break;
   4345  1.281   msaitoh 	case WM_T_82541:
   4346  1.281   msaitoh 	case WM_T_82541_2:
   4347  1.281   msaitoh 	case WM_T_82547:
   4348  1.281   msaitoh 	case WM_T_82547_2:
   4349  1.281   msaitoh 		delay(20000);
   4350  1.281   msaitoh 		/* XXX Disable HW ARPs on ASF enabled adapters */
   4351  1.281   msaitoh 		break;
   4352  1.281   msaitoh 	case WM_T_82571:
   4353  1.281   msaitoh 	case WM_T_82572:
   4354  1.281   msaitoh 	case WM_T_82573:
   4355  1.281   msaitoh 	case WM_T_82574:
   4356  1.281   msaitoh 	case WM_T_82583:
   4357  1.281   msaitoh 		if (sc->sc_flags & WM_F_EEPROM_FLASH) {
   4358  1.281   msaitoh 			delay(10);
   4359  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
   4360  1.281   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4361  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   4362  1.232    bouyer 		}
   4363  1.281   msaitoh 		/* check EECD_EE_AUTORD */
   4364  1.281   msaitoh 		wm_get_auto_rd_done(sc);
   4365  1.281   msaitoh 		/*
   4366  1.281   msaitoh 		 * Phy configuration from NVM just starts after EECD_AUTO_RD
   4367  1.281   msaitoh 		 * is set.
   4368  1.281   msaitoh 		 */
   4369  1.281   msaitoh 		if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574)
   4370  1.281   msaitoh 		    || (sc->sc_type == WM_T_82583))
   4371  1.281   msaitoh 			delay(25*1000);
   4372  1.281   msaitoh 		break;
   4373  1.281   msaitoh 	case WM_T_82575:
   4374  1.281   msaitoh 	case WM_T_82576:
   4375  1.281   msaitoh 	case WM_T_82580:
   4376  1.281   msaitoh 	case WM_T_I350:
   4377  1.281   msaitoh 	case WM_T_I354:
   4378  1.281   msaitoh 	case WM_T_I210:
   4379  1.281   msaitoh 	case WM_T_I211:
   4380  1.281   msaitoh 	case WM_T_80003:
   4381  1.281   msaitoh 		/* check EECD_EE_AUTORD */
   4382  1.281   msaitoh 		wm_get_auto_rd_done(sc);
   4383  1.281   msaitoh 		break;
   4384  1.281   msaitoh 	case WM_T_ICH8:
   4385  1.281   msaitoh 	case WM_T_ICH9:
   4386  1.281   msaitoh 	case WM_T_ICH10:
   4387  1.281   msaitoh 	case WM_T_PCH:
   4388  1.281   msaitoh 	case WM_T_PCH2:
   4389  1.281   msaitoh 	case WM_T_PCH_LPT:
   4390  1.392   msaitoh 	case WM_T_PCH_SPT:
   4391  1.281   msaitoh 		break;
   4392  1.281   msaitoh 	default:
   4393  1.281   msaitoh 		panic("%s: unknown type\n", __func__);
   4394  1.232    bouyer 	}
   4395  1.281   msaitoh 
   4396  1.281   msaitoh 	/* Check whether EEPROM is present or not */
   4397  1.281   msaitoh 	switch (sc->sc_type) {
   4398  1.281   msaitoh 	case WM_T_82575:
   4399  1.281   msaitoh 	case WM_T_82576:
   4400  1.281   msaitoh 	case WM_T_82580:
   4401  1.281   msaitoh 	case WM_T_I350:
   4402  1.281   msaitoh 	case WM_T_I354:
   4403  1.281   msaitoh 	case WM_T_ICH8:
   4404  1.281   msaitoh 	case WM_T_ICH9:
   4405  1.281   msaitoh 		if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
   4406  1.281   msaitoh 			/* Not found */
   4407  1.281   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVALID;
   4408  1.325   msaitoh 			if (sc->sc_type == WM_T_82575)
   4409  1.281   msaitoh 				wm_reset_init_script_82575(sc);
   4410  1.232    bouyer 		}
   4411  1.281   msaitoh 		break;
   4412  1.281   msaitoh 	default:
   4413  1.281   msaitoh 		break;
   4414  1.281   msaitoh 	}
   4415  1.281   msaitoh 
   4416  1.517   msaitoh 	if (phy_reset != 0)
   4417  1.517   msaitoh 		wm_phy_post_reset(sc);
   4418  1.517   msaitoh 
   4419  1.300   msaitoh 	if ((sc->sc_type == WM_T_82580)
   4420  1.281   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
   4421  1.281   msaitoh 		/* clear global device reset status bit */
   4422  1.281   msaitoh 		CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
   4423  1.281   msaitoh 	}
   4424  1.281   msaitoh 
   4425  1.281   msaitoh 	/* Clear any pending interrupt events. */
   4426  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   4427  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_ICR);
   4428  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   4429  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   4430  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   4431  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   4432  1.335   msaitoh 		} else
   4433  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   4434  1.335   msaitoh 	}
   4435  1.281   msaitoh 
   4436  1.510   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4437  1.510   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   4438  1.510   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   4439  1.510   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT)) {
   4440  1.510   msaitoh 		reg = CSR_READ(sc, WMREG_KABGTXD);
   4441  1.510   msaitoh 		reg |= KABGTXD_BGSQLBIAS;
   4442  1.510   msaitoh 		CSR_WRITE(sc, WMREG_KABGTXD, reg);
   4443  1.510   msaitoh 	}
   4444  1.510   msaitoh 
   4445  1.281   msaitoh 	/* reload sc_ctrl */
   4446  1.281   msaitoh 	sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   4447  1.281   msaitoh 
   4448  1.322   msaitoh 	if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
   4449  1.281   msaitoh 		wm_set_eee_i350(sc);
   4450  1.281   msaitoh 
   4451  1.281   msaitoh 	/*
   4452  1.281   msaitoh 	 * For PCH, this write will make sure that any noise will be detected
   4453  1.281   msaitoh 	 * as a CRC error and be dropped rather than show up as a bad packet
   4454  1.281   msaitoh 	 * to the DMA engine
   4455  1.281   msaitoh 	 */
   4456  1.281   msaitoh 	if (sc->sc_type == WM_T_PCH)
   4457  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565);
   4458  1.281   msaitoh 
   4459  1.380   msaitoh 	if (sc->sc_type >= WM_T_82544)
   4460  1.281   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   4461  1.281   msaitoh 
   4462  1.325   msaitoh 	wm_reset_mdicnfg_82580(sc);
   4463  1.332   msaitoh 
   4464  1.332   msaitoh 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
   4465  1.332   msaitoh 		wm_pll_workaround_i210(sc);
   4466  1.281   msaitoh }
   4467  1.281   msaitoh 
   4468  1.281   msaitoh /*
   4469  1.281   msaitoh  * wm_add_rxbuf:
   4470  1.281   msaitoh  *
   4471  1.281   msaitoh  *	Add a receive buffer to the indiciated descriptor.
   4472  1.281   msaitoh  */
   4473  1.281   msaitoh static int
   4474  1.362  knakahar wm_add_rxbuf(struct wm_rxqueue *rxq, int idx)
   4475  1.281   msaitoh {
   4476  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   4477  1.356  knakahar 	struct wm_rxsoft *rxs = &rxq->rxq_soft[idx];
   4478  1.281   msaitoh 	struct mbuf *m;
   4479  1.281   msaitoh 	int error;
   4480  1.281   msaitoh 
   4481  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   4482  1.281   msaitoh 
   4483  1.281   msaitoh 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   4484  1.281   msaitoh 	if (m == NULL)
   4485  1.281   msaitoh 		return ENOBUFS;
   4486  1.281   msaitoh 
   4487  1.281   msaitoh 	MCLGET(m, M_DONTWAIT);
   4488  1.281   msaitoh 	if ((m->m_flags & M_EXT) == 0) {
   4489  1.281   msaitoh 		m_freem(m);
   4490  1.281   msaitoh 		return ENOBUFS;
   4491  1.281   msaitoh 	}
   4492  1.281   msaitoh 
   4493  1.281   msaitoh 	if (rxs->rxs_mbuf != NULL)
   4494  1.281   msaitoh 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   4495  1.281   msaitoh 
   4496  1.281   msaitoh 	rxs->rxs_mbuf = m;
   4497  1.281   msaitoh 
   4498  1.281   msaitoh 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
   4499  1.281   msaitoh 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
   4500  1.388   msaitoh 	    BUS_DMA_READ | BUS_DMA_NOWAIT);
   4501  1.281   msaitoh 	if (error) {
   4502  1.281   msaitoh 		/* XXX XXX XXX */
   4503  1.281   msaitoh 		aprint_error_dev(sc->sc_dev,
   4504  1.281   msaitoh 		    "unable to load rx DMA map %d, error = %d\n",
   4505  1.281   msaitoh 		    idx, error);
   4506  1.281   msaitoh 		panic("wm_add_rxbuf");
   4507  1.232    bouyer 	}
   4508  1.232    bouyer 
   4509  1.281   msaitoh 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   4510  1.281   msaitoh 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   4511  1.281   msaitoh 
   4512  1.281   msaitoh 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   4513  1.281   msaitoh 		if ((sc->sc_rctl & RCTL_EN) != 0)
   4514  1.362  knakahar 			wm_init_rxdesc(rxq, idx);
   4515  1.281   msaitoh 	} else
   4516  1.362  knakahar 		wm_init_rxdesc(rxq, idx);
   4517  1.281   msaitoh 
   4518  1.232    bouyer 	return 0;
   4519  1.232    bouyer }
   4520  1.232    bouyer 
   4521  1.232    bouyer /*
   4522  1.281   msaitoh  * wm_rxdrain:
   4523  1.232    bouyer  *
   4524  1.281   msaitoh  *	Drain the receive queue.
   4525  1.232    bouyer  */
   4526  1.232    bouyer static void
   4527  1.362  knakahar wm_rxdrain(struct wm_rxqueue *rxq)
   4528  1.281   msaitoh {
   4529  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   4530  1.281   msaitoh 	struct wm_rxsoft *rxs;
   4531  1.281   msaitoh 	int i;
   4532  1.281   msaitoh 
   4533  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   4534  1.281   msaitoh 
   4535  1.281   msaitoh 	for (i = 0; i < WM_NRXDESC; i++) {
   4536  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   4537  1.281   msaitoh 		if (rxs->rxs_mbuf != NULL) {
   4538  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   4539  1.281   msaitoh 			m_freem(rxs->rxs_mbuf);
   4540  1.281   msaitoh 			rxs->rxs_mbuf = NULL;
   4541  1.281   msaitoh 		}
   4542  1.281   msaitoh 	}
   4543  1.281   msaitoh }
   4544  1.281   msaitoh 
   4545  1.372  knakahar 
   4546  1.372  knakahar /*
   4547  1.372  knakahar  * XXX copy from FreeBSD's sys/net/rss_config.c
   4548  1.372  knakahar  */
   4549  1.372  knakahar /*
   4550  1.372  knakahar  * RSS secret key, intended to prevent attacks on load-balancing.  Its
   4551  1.372  knakahar  * effectiveness may be limited by algorithm choice and available entropy
   4552  1.372  knakahar  * during the boot.
   4553  1.372  knakahar  *
   4554  1.372  knakahar  * XXXRW: And that we don't randomize it yet!
   4555  1.372  knakahar  *
   4556  1.372  knakahar  * This is the default Microsoft RSS specification key which is also
   4557  1.372  knakahar  * the Chelsio T5 firmware default key.
   4558  1.372  knakahar  */
   4559  1.372  knakahar #define RSS_KEYSIZE 40
   4560  1.372  knakahar static uint8_t wm_rss_key[RSS_KEYSIZE] = {
   4561  1.372  knakahar 	0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
   4562  1.372  knakahar 	0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
   4563  1.372  knakahar 	0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
   4564  1.372  knakahar 	0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
   4565  1.372  knakahar 	0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa,
   4566  1.372  knakahar };
   4567  1.372  knakahar 
   4568  1.372  knakahar /*
   4569  1.372  knakahar  * Caller must pass an array of size sizeof(rss_key).
   4570  1.372  knakahar  *
   4571  1.372  knakahar  * XXX
   4572  1.372  knakahar  * As if_ixgbe may use this function, this function should not be
   4573  1.372  knakahar  * if_wm specific function.
   4574  1.372  knakahar  */
   4575  1.372  knakahar static void
   4576  1.372  knakahar wm_rss_getkey(uint8_t *key)
   4577  1.372  knakahar {
   4578  1.373  knakahar 
   4579  1.372  knakahar 	memcpy(key, wm_rss_key, sizeof(wm_rss_key));
   4580  1.372  knakahar }
   4581  1.372  knakahar 
   4582  1.365  knakahar /*
   4583  1.367  knakahar  * Setup registers for RSS.
   4584  1.367  knakahar  *
   4585  1.367  knakahar  * XXX not yet VMDq support
   4586  1.367  knakahar  */
   4587  1.367  knakahar static void
   4588  1.367  knakahar wm_init_rss(struct wm_softc *sc)
   4589  1.367  knakahar {
   4590  1.372  knakahar 	uint32_t mrqc, reta_reg, rss_key[RSSRK_NUM_REGS];
   4591  1.367  knakahar 	int i;
   4592  1.367  knakahar 
   4593  1.373  knakahar 	CTASSERT(sizeof(rss_key) == sizeof(wm_rss_key));
   4594  1.373  knakahar 
   4595  1.367  knakahar 	for (i = 0; i < RETA_NUM_ENTRIES; i++) {
   4596  1.367  knakahar 		int qid, reta_ent;
   4597  1.367  knakahar 
   4598  1.405  knakahar 		qid  = i % sc->sc_nqueues;
   4599  1.367  knakahar 		switch(sc->sc_type) {
   4600  1.367  knakahar 		case WM_T_82574:
   4601  1.367  knakahar 			reta_ent = __SHIFTIN(qid,
   4602  1.367  knakahar 			    RETA_ENT_QINDEX_MASK_82574);
   4603  1.367  knakahar 			break;
   4604  1.367  knakahar 		case WM_T_82575:
   4605  1.367  knakahar 			reta_ent = __SHIFTIN(qid,
   4606  1.367  knakahar 			    RETA_ENT_QINDEX1_MASK_82575);
   4607  1.367  knakahar 			break;
   4608  1.367  knakahar 		default:
   4609  1.367  knakahar 			reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK);
   4610  1.367  knakahar 			break;
   4611  1.367  knakahar 		}
   4612  1.367  knakahar 
   4613  1.367  knakahar 		reta_reg = CSR_READ(sc, WMREG_RETA_Q(i));
   4614  1.367  knakahar 		reta_reg &= ~RETA_ENTRY_MASK_Q(i);
   4615  1.367  knakahar 		reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i));
   4616  1.367  knakahar 		CSR_WRITE(sc, WMREG_RETA_Q(i), reta_reg);
   4617  1.367  knakahar 	}
   4618  1.367  knakahar 
   4619  1.372  knakahar 	wm_rss_getkey((uint8_t *)rss_key);
   4620  1.367  knakahar 	for (i = 0; i < RSSRK_NUM_REGS; i++)
   4621  1.372  knakahar 		CSR_WRITE(sc, WMREG_RSSRK(i), rss_key[i]);
   4622  1.367  knakahar 
   4623  1.367  knakahar 	if (sc->sc_type == WM_T_82574)
   4624  1.367  knakahar 		mrqc = MRQC_ENABLE_RSS_MQ_82574;
   4625  1.367  knakahar 	else
   4626  1.367  knakahar 		mrqc = MRQC_ENABLE_RSS_MQ;
   4627  1.367  knakahar 
   4628  1.462   msaitoh 	/*
   4629  1.462   msaitoh 	 * MRQC_RSS_FIELD_IPV6_EX is not set because of an errata.
   4630  1.462   msaitoh 	 * See IPV6EXDIS bit in wm_initialize_hardware_bits().
   4631  1.367  knakahar 	 */
   4632  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV4 | MRQC_RSS_FIELD_IPV4_TCP);
   4633  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV6 | MRQC_RSS_FIELD_IPV6_TCP);
   4634  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV4_UDP | MRQC_RSS_FIELD_IPV6_UDP);
   4635  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV6_UDP_EX | MRQC_RSS_FIELD_IPV6_TCP_EX);
   4636  1.367  knakahar 
   4637  1.367  knakahar 	CSR_WRITE(sc, WMREG_MRQC, mrqc);
   4638  1.367  knakahar }
   4639  1.367  knakahar 
   4640  1.367  knakahar /*
   4641  1.365  knakahar  * Adjust TX and RX queue numbers which the system actulally uses.
   4642  1.365  knakahar  *
   4643  1.365  knakahar  * The numbers are affected by below parameters.
   4644  1.365  knakahar  *     - The nubmer of hardware queues
   4645  1.365  knakahar  *     - The number of MSI-X vectors (= "nvectors" argument)
   4646  1.365  knakahar  *     - ncpu
   4647  1.365  knakahar  */
   4648  1.365  knakahar static void
   4649  1.365  knakahar wm_adjust_qnum(struct wm_softc *sc, int nvectors)
   4650  1.365  knakahar {
   4651  1.405  knakahar 	int hw_ntxqueues, hw_nrxqueues, hw_nqueues;
   4652  1.365  knakahar 
   4653  1.405  knakahar 	if (nvectors < 2) {
   4654  1.405  knakahar 		sc->sc_nqueues = 1;
   4655  1.365  knakahar 		return;
   4656  1.365  knakahar 	}
   4657  1.365  knakahar 
   4658  1.365  knakahar 	switch(sc->sc_type) {
   4659  1.365  knakahar 	case WM_T_82572:
   4660  1.365  knakahar 		hw_ntxqueues = 2;
   4661  1.365  knakahar 		hw_nrxqueues = 2;
   4662  1.365  knakahar 		break;
   4663  1.365  knakahar 	case WM_T_82574:
   4664  1.365  knakahar 		hw_ntxqueues = 2;
   4665  1.365  knakahar 		hw_nrxqueues = 2;
   4666  1.365  knakahar 		break;
   4667  1.365  knakahar 	case WM_T_82575:
   4668  1.365  knakahar 		hw_ntxqueues = 4;
   4669  1.365  knakahar 		hw_nrxqueues = 4;
   4670  1.365  knakahar 		break;
   4671  1.365  knakahar 	case WM_T_82576:
   4672  1.365  knakahar 		hw_ntxqueues = 16;
   4673  1.365  knakahar 		hw_nrxqueues = 16;
   4674  1.365  knakahar 		break;
   4675  1.365  knakahar 	case WM_T_82580:
   4676  1.365  knakahar 	case WM_T_I350:
   4677  1.365  knakahar 	case WM_T_I354:
   4678  1.365  knakahar 		hw_ntxqueues = 8;
   4679  1.365  knakahar 		hw_nrxqueues = 8;
   4680  1.365  knakahar 		break;
   4681  1.365  knakahar 	case WM_T_I210:
   4682  1.365  knakahar 		hw_ntxqueues = 4;
   4683  1.365  knakahar 		hw_nrxqueues = 4;
   4684  1.365  knakahar 		break;
   4685  1.365  knakahar 	case WM_T_I211:
   4686  1.365  knakahar 		hw_ntxqueues = 2;
   4687  1.365  knakahar 		hw_nrxqueues = 2;
   4688  1.365  knakahar 		break;
   4689  1.365  knakahar 		/*
   4690  1.365  knakahar 		 * As below ethernet controllers does not support MSI-X,
   4691  1.365  knakahar 		 * this driver let them not use multiqueue.
   4692  1.365  knakahar 		 *     - WM_T_80003
   4693  1.365  knakahar 		 *     - WM_T_ICH8
   4694  1.365  knakahar 		 *     - WM_T_ICH9
   4695  1.365  knakahar 		 *     - WM_T_ICH10
   4696  1.365  knakahar 		 *     - WM_T_PCH
   4697  1.365  knakahar 		 *     - WM_T_PCH2
   4698  1.365  knakahar 		 *     - WM_T_PCH_LPT
   4699  1.365  knakahar 		 */
   4700  1.365  knakahar 	default:
   4701  1.365  knakahar 		hw_ntxqueues = 1;
   4702  1.365  knakahar 		hw_nrxqueues = 1;
   4703  1.365  knakahar 		break;
   4704  1.365  knakahar 	}
   4705  1.365  knakahar 
   4706  1.405  knakahar 	hw_nqueues = min(hw_ntxqueues, hw_nrxqueues);
   4707  1.405  knakahar 
   4708  1.365  knakahar 	/*
   4709  1.405  knakahar 	 * As queues more than MSI-X vectors cannot improve scaling, we limit
   4710  1.365  knakahar 	 * the number of queues used actually.
   4711  1.405  knakahar 	 */
   4712  1.405  knakahar 	if (nvectors < hw_nqueues + 1) {
   4713  1.405  knakahar 		sc->sc_nqueues = nvectors - 1;
   4714  1.365  knakahar 	} else {
   4715  1.405  knakahar 		sc->sc_nqueues = hw_nqueues;
   4716  1.365  knakahar 	}
   4717  1.365  knakahar 
   4718  1.365  knakahar 	/*
   4719  1.365  knakahar 	 * As queues more then cpus cannot improve scaling, we limit
   4720  1.365  knakahar 	 * the number of queues used actually.
   4721  1.365  knakahar 	 */
   4722  1.405  knakahar 	if (ncpu < sc->sc_nqueues)
   4723  1.405  knakahar 		sc->sc_nqueues = ncpu;
   4724  1.365  knakahar }
   4725  1.365  knakahar 
   4726  1.502  knakahar static inline bool
   4727  1.502  knakahar wm_is_using_msix(struct wm_softc *sc)
   4728  1.502  knakahar {
   4729  1.502  knakahar 
   4730  1.502  knakahar 	return (sc->sc_nintrs > 1);
   4731  1.502  knakahar }
   4732  1.502  knakahar 
   4733  1.502  knakahar static inline bool
   4734  1.502  knakahar wm_is_using_multiqueue(struct wm_softc *sc)
   4735  1.502  knakahar {
   4736  1.502  knakahar 
   4737  1.502  knakahar 	return (sc->sc_nqueues > 1);
   4738  1.502  knakahar }
   4739  1.502  knakahar 
   4740  1.485  christos static int
   4741  1.485  christos wm_softint_establish(struct wm_softc *sc, int qidx, int intr_idx)
   4742  1.485  christos {
   4743  1.485  christos 	struct wm_queue *wmq = &sc->sc_queue[qidx];
   4744  1.485  christos 	wmq->wmq_id = qidx;
   4745  1.485  christos 	wmq->wmq_intr_idx = intr_idx;
   4746  1.485  christos 	wmq->wmq_si = softint_establish(SOFTINT_NET
   4747  1.485  christos #ifdef WM_MPSAFE
   4748  1.485  christos 	    | SOFTINT_MPSAFE
   4749  1.485  christos #endif
   4750  1.485  christos 	    , wm_handle_queue, wmq);
   4751  1.485  christos 	if (wmq->wmq_si != NULL)
   4752  1.485  christos 		return 0;
   4753  1.485  christos 
   4754  1.485  christos 	aprint_error_dev(sc->sc_dev, "unable to establish queue[%d] handler\n",
   4755  1.485  christos 	    wmq->wmq_id);
   4756  1.485  christos 
   4757  1.485  christos 	pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[wmq->wmq_intr_idx]);
   4758  1.485  christos 	sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
   4759  1.485  christos 	return ENOMEM;
   4760  1.485  christos }
   4761  1.485  christos 
   4762  1.365  knakahar /*
   4763  1.360  knakahar  * Both single interrupt MSI and INTx can use this function.
   4764  1.360  knakahar  */
   4765  1.360  knakahar static int
   4766  1.360  knakahar wm_setup_legacy(struct wm_softc *sc)
   4767  1.360  knakahar {
   4768  1.360  knakahar 	pci_chipset_tag_t pc = sc->sc_pc;
   4769  1.360  knakahar 	const char *intrstr = NULL;
   4770  1.360  knakahar 	char intrbuf[PCI_INTRSTR_LEN];
   4771  1.375   msaitoh 	int error;
   4772  1.360  knakahar 
   4773  1.375   msaitoh 	error = wm_alloc_txrx_queues(sc);
   4774  1.375   msaitoh 	if (error) {
   4775  1.375   msaitoh 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
   4776  1.375   msaitoh 		    error);
   4777  1.375   msaitoh 		return ENOMEM;
   4778  1.375   msaitoh 	}
   4779  1.360  knakahar 	intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf,
   4780  1.360  knakahar 	    sizeof(intrbuf));
   4781  1.360  knakahar #ifdef WM_MPSAFE
   4782  1.360  knakahar 	pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true);
   4783  1.360  knakahar #endif
   4784  1.360  knakahar 	sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0],
   4785  1.360  knakahar 	    IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev));
   4786  1.360  knakahar 	if (sc->sc_ihs[0] == NULL) {
   4787  1.360  knakahar 		aprint_error_dev(sc->sc_dev,"unable to establish %s\n",
   4788  1.416  knakahar 		    (pci_intr_type(pc, sc->sc_intrs[0])
   4789  1.360  knakahar 			== PCI_INTR_TYPE_MSI) ? "MSI" : "INTx");
   4790  1.360  knakahar 		return ENOMEM;
   4791  1.360  knakahar 	}
   4792  1.360  knakahar 
   4793  1.360  knakahar 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
   4794  1.360  knakahar 	sc->sc_nintrs = 1;
   4795  1.485  christos 
   4796  1.485  christos 	return wm_softint_establish(sc, 0, 0);
   4797  1.360  knakahar }
   4798  1.360  knakahar 
   4799  1.360  knakahar static int
   4800  1.360  knakahar wm_setup_msix(struct wm_softc *sc)
   4801  1.360  knakahar {
   4802  1.360  knakahar 	void *vih;
   4803  1.360  knakahar 	kcpuset_t *affinity;
   4804  1.405  knakahar 	int qidx, error, intr_idx, txrx_established;
   4805  1.360  knakahar 	pci_chipset_tag_t pc = sc->sc_pc;
   4806  1.360  knakahar 	const char *intrstr = NULL;
   4807  1.360  knakahar 	char intrbuf[PCI_INTRSTR_LEN];
   4808  1.360  knakahar 	char intr_xname[INTRDEVNAMEBUF];
   4809  1.404  knakahar 
   4810  1.405  knakahar 	if (sc->sc_nqueues < ncpu) {
   4811  1.404  knakahar 		/*
   4812  1.404  knakahar 		 * To avoid other devices' interrupts, the affinity of Tx/Rx
   4813  1.404  knakahar 		 * interrupts start from CPU#1.
   4814  1.404  knakahar 		 */
   4815  1.404  knakahar 		sc->sc_affinity_offset = 1;
   4816  1.404  knakahar 	} else {
   4817  1.404  knakahar 		/*
   4818  1.404  knakahar 		 * In this case, this device use all CPUs. So, we unify
   4819  1.404  knakahar 		 * affinitied cpu_index to msix vector number for readability.
   4820  1.404  knakahar 		 */
   4821  1.404  knakahar 		sc->sc_affinity_offset = 0;
   4822  1.404  knakahar 	}
   4823  1.360  knakahar 
   4824  1.375   msaitoh 	error = wm_alloc_txrx_queues(sc);
   4825  1.375   msaitoh 	if (error) {
   4826  1.375   msaitoh 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
   4827  1.375   msaitoh 		    error);
   4828  1.375   msaitoh 		return ENOMEM;
   4829  1.375   msaitoh 	}
   4830  1.375   msaitoh 
   4831  1.364  knakahar 	kcpuset_create(&affinity, false);
   4832  1.364  knakahar 	intr_idx = 0;
   4833  1.363  knakahar 
   4834  1.364  knakahar 	/*
   4835  1.405  knakahar 	 * TX and RX
   4836  1.364  knakahar 	 */
   4837  1.405  knakahar 	txrx_established = 0;
   4838  1.405  knakahar 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   4839  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   4840  1.404  knakahar 		int affinity_to = (sc->sc_affinity_offset + intr_idx) % ncpu;
   4841  1.364  knakahar 
   4842  1.364  knakahar 		intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
   4843  1.364  knakahar 		    sizeof(intrbuf));
   4844  1.364  knakahar #ifdef WM_MPSAFE
   4845  1.364  knakahar 		pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
   4846  1.364  knakahar 		    PCI_INTR_MPSAFE, true);
   4847  1.364  knakahar #endif
   4848  1.364  knakahar 		memset(intr_xname, 0, sizeof(intr_xname));
   4849  1.405  knakahar 		snprintf(intr_xname, sizeof(intr_xname), "%sTXRX%d",
   4850  1.364  knakahar 		    device_xname(sc->sc_dev), qidx);
   4851  1.364  knakahar 		vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
   4852  1.405  knakahar 		    IPL_NET, wm_txrxintr_msix, wmq, intr_xname);
   4853  1.364  knakahar 		if (vih == NULL) {
   4854  1.364  knakahar 			aprint_error_dev(sc->sc_dev,
   4855  1.405  knakahar 			    "unable to establish MSI-X(for TX and RX)%s%s\n",
   4856  1.364  knakahar 			    intrstr ? " at " : "",
   4857  1.364  knakahar 			    intrstr ? intrstr : "");
   4858  1.364  knakahar 
   4859  1.405  knakahar 			goto fail;
   4860  1.360  knakahar 		}
   4861  1.360  knakahar 		kcpuset_zero(affinity);
   4862  1.360  knakahar 		/* Round-robin affinity */
   4863  1.383  knakahar 		kcpuset_set(affinity, affinity_to);
   4864  1.360  knakahar 		error = interrupt_distribute(vih, affinity, NULL);
   4865  1.360  knakahar 		if (error == 0) {
   4866  1.360  knakahar 			aprint_normal_dev(sc->sc_dev,
   4867  1.405  knakahar 			    "for TX and RX interrupting at %s affinity to %u\n",
   4868  1.383  knakahar 			    intrstr, affinity_to);
   4869  1.360  knakahar 		} else {
   4870  1.360  knakahar 			aprint_normal_dev(sc->sc_dev,
   4871  1.405  knakahar 			    "for TX and RX interrupting at %s\n", intrstr);
   4872  1.360  knakahar 		}
   4873  1.364  knakahar 		sc->sc_ihs[intr_idx] = vih;
   4874  1.485  christos 		if (wm_softint_establish(sc, qidx, intr_idx) != 0)
   4875  1.484  knakahar 			goto fail;
   4876  1.405  knakahar 		txrx_established++;
   4877  1.364  knakahar 		intr_idx++;
   4878  1.364  knakahar 	}
   4879  1.364  knakahar 
   4880  1.364  knakahar 	/*
   4881  1.364  knakahar 	 * LINK
   4882  1.364  knakahar 	 */
   4883  1.364  knakahar 	intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
   4884  1.364  knakahar 	    sizeof(intrbuf));
   4885  1.364  knakahar #ifdef WM_MPSAFE
   4886  1.388   msaitoh 	pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], PCI_INTR_MPSAFE, true);
   4887  1.364  knakahar #endif
   4888  1.364  knakahar 	memset(intr_xname, 0, sizeof(intr_xname));
   4889  1.364  knakahar 	snprintf(intr_xname, sizeof(intr_xname), "%sLINK",
   4890  1.364  knakahar 	    device_xname(sc->sc_dev));
   4891  1.364  knakahar 	vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
   4892  1.364  knakahar 		    IPL_NET, wm_linkintr_msix, sc, intr_xname);
   4893  1.364  knakahar 	if (vih == NULL) {
   4894  1.364  knakahar 		aprint_error_dev(sc->sc_dev,
   4895  1.364  knakahar 		    "unable to establish MSI-X(for LINK)%s%s\n",
   4896  1.364  knakahar 		    intrstr ? " at " : "",
   4897  1.364  knakahar 		    intrstr ? intrstr : "");
   4898  1.364  knakahar 
   4899  1.405  knakahar 		goto fail;
   4900  1.360  knakahar 	}
   4901  1.364  knakahar 	/* keep default affinity to LINK interrupt */
   4902  1.364  knakahar 	aprint_normal_dev(sc->sc_dev,
   4903  1.364  knakahar 	    "for LINK interrupting at %s\n", intrstr);
   4904  1.364  knakahar 	sc->sc_ihs[intr_idx] = vih;
   4905  1.364  knakahar 	sc->sc_link_intr_idx = intr_idx;
   4906  1.360  knakahar 
   4907  1.405  knakahar 	sc->sc_nintrs = sc->sc_nqueues + 1;
   4908  1.360  knakahar 	kcpuset_destroy(affinity);
   4909  1.360  knakahar 	return 0;
   4910  1.364  knakahar 
   4911  1.405  knakahar  fail:
   4912  1.405  knakahar 	for (qidx = 0; qidx < txrx_established; qidx++) {
   4913  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   4914  1.405  knakahar 		pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[wmq->wmq_intr_idx]);
   4915  1.405  knakahar 		sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
   4916  1.364  knakahar 	}
   4917  1.364  knakahar 
   4918  1.364  knakahar 	kcpuset_destroy(affinity);
   4919  1.364  knakahar 	return ENOMEM;
   4920  1.360  knakahar }
   4921  1.360  knakahar 
   4922  1.429  knakahar static void
   4923  1.429  knakahar wm_turnon(struct wm_softc *sc)
   4924  1.429  knakahar {
   4925  1.429  knakahar 	int i;
   4926  1.429  knakahar 
   4927  1.436  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   4928  1.436  knakahar 
   4929  1.476  knakahar 	/*
   4930  1.476  knakahar 	 * must unset stopping flags in ascending order.
   4931  1.476  knakahar 	 */
   4932  1.429  knakahar 	for(i = 0; i < sc->sc_nqueues; i++) {
   4933  1.429  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   4934  1.429  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   4935  1.429  knakahar 
   4936  1.429  knakahar 		mutex_enter(txq->txq_lock);
   4937  1.429  knakahar 		txq->txq_stopping = false;
   4938  1.429  knakahar 		mutex_exit(txq->txq_lock);
   4939  1.429  knakahar 
   4940  1.429  knakahar 		mutex_enter(rxq->rxq_lock);
   4941  1.429  knakahar 		rxq->rxq_stopping = false;
   4942  1.429  knakahar 		mutex_exit(rxq->rxq_lock);
   4943  1.429  knakahar 	}
   4944  1.429  knakahar 
   4945  1.429  knakahar 	sc->sc_core_stopping = false;
   4946  1.429  knakahar }
   4947  1.429  knakahar 
   4948  1.429  knakahar static void
   4949  1.429  knakahar wm_turnoff(struct wm_softc *sc)
   4950  1.429  knakahar {
   4951  1.429  knakahar 	int i;
   4952  1.429  knakahar 
   4953  1.436  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   4954  1.436  knakahar 
   4955  1.429  knakahar 	sc->sc_core_stopping = true;
   4956  1.429  knakahar 
   4957  1.476  knakahar 	/*
   4958  1.476  knakahar 	 * must set stopping flags in ascending order.
   4959  1.476  knakahar 	 */
   4960  1.429  knakahar 	for(i = 0; i < sc->sc_nqueues; i++) {
   4961  1.429  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   4962  1.429  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   4963  1.429  knakahar 
   4964  1.429  knakahar 		mutex_enter(rxq->rxq_lock);
   4965  1.429  knakahar 		rxq->rxq_stopping = true;
   4966  1.429  knakahar 		mutex_exit(rxq->rxq_lock);
   4967  1.429  knakahar 
   4968  1.429  knakahar 		mutex_enter(txq->txq_lock);
   4969  1.429  knakahar 		txq->txq_stopping = true;
   4970  1.429  knakahar 		mutex_exit(txq->txq_lock);
   4971  1.429  knakahar 	}
   4972  1.429  knakahar }
   4973  1.429  knakahar 
   4974  1.281   msaitoh /*
   4975  1.491  knakahar  * write interrupt interval value to ITR or EITR
   4976  1.491  knakahar  */
   4977  1.491  knakahar static void
   4978  1.491  knakahar wm_itrs_writereg(struct wm_softc *sc, struct wm_queue *wmq)
   4979  1.491  knakahar {
   4980  1.491  knakahar 
   4981  1.495  knakahar 	if (!wmq->wmq_set_itr)
   4982  1.495  knakahar 		return;
   4983  1.495  knakahar 
   4984  1.491  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   4985  1.491  knakahar 		uint32_t eitr = __SHIFTIN(wmq->wmq_itr, EITR_ITR_INT_MASK);
   4986  1.491  knakahar 
   4987  1.491  knakahar 		/*
   4988  1.491  knakahar 		 * 82575 doesn't have CNT_INGR field.
   4989  1.491  knakahar 		 * So, overwrite counter field by software.
   4990  1.491  knakahar 		 */
   4991  1.491  knakahar 		if (sc->sc_type == WM_T_82575)
   4992  1.491  knakahar 			eitr |= __SHIFTIN(wmq->wmq_itr, EITR_COUNTER_MASK_82575);
   4993  1.491  knakahar 		else
   4994  1.491  knakahar 			eitr |= EITR_CNT_INGR;
   4995  1.491  knakahar 
   4996  1.491  knakahar 		CSR_WRITE(sc, WMREG_EITR(wmq->wmq_intr_idx), eitr);
   4997  1.502  knakahar 	} else if (sc->sc_type == WM_T_82574 && wm_is_using_msix(sc)) {
   4998  1.491  knakahar 		/*
   4999  1.491  knakahar 		 * 82574 has both ITR and EITR. SET EITR when we use
   5000  1.491  knakahar 		 * the multi queue function with MSI-X.
   5001  1.491  knakahar 		 */
   5002  1.491  knakahar 		CSR_WRITE(sc, WMREG_EITR_82574(wmq->wmq_intr_idx),
   5003  1.491  knakahar 			    wmq->wmq_itr & EITR_ITR_INT_MASK_82574);
   5004  1.491  knakahar 	} else {
   5005  1.491  knakahar 		KASSERT(wmq->wmq_id == 0);
   5006  1.491  knakahar 		CSR_WRITE(sc, WMREG_ITR, wmq->wmq_itr);
   5007  1.491  knakahar 	}
   5008  1.495  knakahar 
   5009  1.495  knakahar 	wmq->wmq_set_itr = false;
   5010  1.495  knakahar }
   5011  1.495  knakahar 
   5012  1.495  knakahar /*
   5013  1.495  knakahar  * TODO
   5014  1.495  knakahar  * Below dynamic calculation of itr is almost the same as linux igb,
   5015  1.495  knakahar  * however it does not fit to wm(4). So, we will have been disable AIM
   5016  1.495  knakahar  * until we will find appropriate calculation of itr.
   5017  1.495  knakahar  */
   5018  1.495  knakahar /*
   5019  1.495  knakahar  * calculate interrupt interval value to be going to write register in
   5020  1.495  knakahar  * wm_itrs_writereg(). This function does not write ITR/EITR register.
   5021  1.495  knakahar  */
   5022  1.495  knakahar static void
   5023  1.495  knakahar wm_itrs_calculate(struct wm_softc *sc, struct wm_queue *wmq)
   5024  1.495  knakahar {
   5025  1.495  knakahar #ifdef NOTYET
   5026  1.495  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   5027  1.495  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   5028  1.495  knakahar 	uint32_t avg_size = 0;
   5029  1.495  knakahar 	uint32_t new_itr;
   5030  1.495  knakahar 
   5031  1.495  knakahar 	if (rxq->rxq_packets)
   5032  1.495  knakahar 		avg_size =  rxq->rxq_bytes / rxq->rxq_packets;
   5033  1.495  knakahar 	if (txq->txq_packets)
   5034  1.495  knakahar 		avg_size = max(avg_size, txq->txq_bytes / txq->txq_packets);
   5035  1.495  knakahar 
   5036  1.495  knakahar 	if (avg_size == 0) {
   5037  1.495  knakahar 		new_itr = 450; /* restore default value */
   5038  1.495  knakahar 		goto out;
   5039  1.495  knakahar 	}
   5040  1.495  knakahar 
   5041  1.495  knakahar 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
   5042  1.495  knakahar 	avg_size += 24;
   5043  1.495  knakahar 
   5044  1.495  knakahar 	/* Don't starve jumbo frames */
   5045  1.495  knakahar 	avg_size = min(avg_size, 3000);
   5046  1.495  knakahar 
   5047  1.495  knakahar 	/* Give a little boost to mid-size frames */
   5048  1.495  knakahar 	if ((avg_size > 300) && (avg_size < 1200))
   5049  1.495  knakahar 		new_itr = avg_size / 3;
   5050  1.495  knakahar 	else
   5051  1.495  knakahar 		new_itr = avg_size / 2;
   5052  1.495  knakahar 
   5053  1.495  knakahar out:
   5054  1.495  knakahar 	/*
   5055  1.495  knakahar 	 * The usage of 82574 and 82575 EITR is different from otther NEWQUEUE
   5056  1.495  knakahar 	 * controllers. See sc->sc_itr_init setting in wm_init_locked().
   5057  1.495  knakahar 	 */
   5058  1.495  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) == 0 || sc->sc_type != WM_T_82575)
   5059  1.495  knakahar 		new_itr *= 4;
   5060  1.495  knakahar 
   5061  1.495  knakahar 	if (new_itr != wmq->wmq_itr) {
   5062  1.495  knakahar 		wmq->wmq_itr = new_itr;
   5063  1.495  knakahar 		wmq->wmq_set_itr = true;
   5064  1.495  knakahar 	} else
   5065  1.495  knakahar 		wmq->wmq_set_itr = false;
   5066  1.495  knakahar 
   5067  1.495  knakahar 	rxq->rxq_packets = 0;
   5068  1.495  knakahar 	rxq->rxq_bytes = 0;
   5069  1.495  knakahar 	txq->txq_packets = 0;
   5070  1.495  knakahar 	txq->txq_bytes = 0;
   5071  1.495  knakahar #endif
   5072  1.491  knakahar }
   5073  1.491  knakahar 
   5074  1.491  knakahar /*
   5075  1.281   msaitoh  * wm_init:		[ifnet interface function]
   5076  1.281   msaitoh  *
   5077  1.281   msaitoh  *	Initialize the interface.
   5078  1.281   msaitoh  */
   5079  1.281   msaitoh static int
   5080  1.281   msaitoh wm_init(struct ifnet *ifp)
   5081  1.232    bouyer {
   5082  1.232    bouyer 	struct wm_softc *sc = ifp->if_softc;
   5083  1.281   msaitoh 	int ret;
   5084  1.272     ozaki 
   5085  1.357  knakahar 	WM_CORE_LOCK(sc);
   5086  1.281   msaitoh 	ret = wm_init_locked(ifp);
   5087  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   5088  1.281   msaitoh 
   5089  1.281   msaitoh 	return ret;
   5090  1.272     ozaki }
   5091  1.272     ozaki 
   5092  1.281   msaitoh static int
   5093  1.281   msaitoh wm_init_locked(struct ifnet *ifp)
   5094  1.272     ozaki {
   5095  1.272     ozaki 	struct wm_softc *sc = ifp->if_softc;
   5096  1.281   msaitoh 	int i, j, trynum, error = 0;
   5097  1.281   msaitoh 	uint32_t reg;
   5098  1.232    bouyer 
   5099  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   5100  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   5101  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5102  1.420   msaitoh 
   5103  1.232    bouyer 	/*
   5104  1.281   msaitoh 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
   5105  1.281   msaitoh 	 * There is a small but measurable benefit to avoiding the adjusment
   5106  1.281   msaitoh 	 * of the descriptor so that the headers are aligned, for normal mtu,
   5107  1.281   msaitoh 	 * on such platforms.  One possibility is that the DMA itself is
   5108  1.281   msaitoh 	 * slightly more efficient if the front of the entire packet (instead
   5109  1.281   msaitoh 	 * of the front of the headers) is aligned.
   5110  1.281   msaitoh 	 *
   5111  1.281   msaitoh 	 * Note we must always set align_tweak to 0 if we are using
   5112  1.281   msaitoh 	 * jumbo frames.
   5113  1.232    bouyer 	 */
   5114  1.281   msaitoh #ifdef __NO_STRICT_ALIGNMENT
   5115  1.281   msaitoh 	sc->sc_align_tweak = 0;
   5116  1.281   msaitoh #else
   5117  1.281   msaitoh 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
   5118  1.281   msaitoh 		sc->sc_align_tweak = 0;
   5119  1.281   msaitoh 	else
   5120  1.281   msaitoh 		sc->sc_align_tweak = 2;
   5121  1.281   msaitoh #endif /* __NO_STRICT_ALIGNMENT */
   5122  1.281   msaitoh 
   5123  1.281   msaitoh 	/* Cancel any pending I/O. */
   5124  1.281   msaitoh 	wm_stop_locked(ifp, 0);
   5125  1.281   msaitoh 
   5126  1.281   msaitoh 	/* update statistics before reset */
   5127  1.281   msaitoh 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
   5128  1.281   msaitoh 	ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
   5129  1.281   msaitoh 
   5130  1.443   msaitoh 	/* PCH_SPT hardware workaround */
   5131  1.443   msaitoh 	if (sc->sc_type == WM_T_PCH_SPT)
   5132  1.443   msaitoh 		wm_flush_desc_rings(sc);
   5133  1.443   msaitoh 
   5134  1.281   msaitoh 	/* Reset the chip to a known state. */
   5135  1.281   msaitoh 	wm_reset(sc);
   5136  1.281   msaitoh 
   5137  1.518   msaitoh 	/*
   5138  1.518   msaitoh 	 * AMT based hardware can now take control from firmware
   5139  1.518   msaitoh 	 * Do this after reset.
   5140  1.518   msaitoh 	 */
   5141  1.518   msaitoh 	if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
   5142  1.518   msaitoh 		wm_get_hw_control(sc);
   5143  1.518   msaitoh 
   5144  1.517   msaitoh 	if ((sc->sc_type == WM_T_PCH_SPT) &&
   5145  1.517   msaitoh 	    pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
   5146  1.517   msaitoh 		wm_legacy_irq_quirk_spt(sc);
   5147  1.232    bouyer 
   5148  1.312   msaitoh 	/* Init hardware bits */
   5149  1.312   msaitoh 	wm_initialize_hardware_bits(sc);
   5150  1.312   msaitoh 
   5151  1.281   msaitoh 	/* Reset the PHY. */
   5152  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   5153  1.281   msaitoh 		wm_gmii_reset(sc);
   5154  1.232    bouyer 
   5155  1.319   msaitoh 	/* Calculate (E)ITR value */
   5156  1.489  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0 && sc->sc_type != WM_T_82575) {
   5157  1.489  knakahar 		/*
   5158  1.489  knakahar 		 * For NEWQUEUE's EITR (except for 82575).
   5159  1.489  knakahar 		 * 82575's EITR should be set same throttling value as other
   5160  1.489  knakahar 		 * old controllers' ITR because the interrupt/sec calculation
   5161  1.489  knakahar 		 * is the same, that is, 1,000,000,000 / (N * 256).
   5162  1.489  knakahar 		 *
   5163  1.489  knakahar 		 * 82574's EITR should be set same throttling value as ITR.
   5164  1.489  knakahar 		 *
   5165  1.489  knakahar 		 * For N interrupts/sec, set this value to:
   5166  1.489  knakahar 		 * 1,000,000 / N in contrast to ITR throttoling value.
   5167  1.489  knakahar 		 */
   5168  1.490  knakahar 		sc->sc_itr_init = 450;
   5169  1.319   msaitoh 	} else if (sc->sc_type >= WM_T_82543) {
   5170  1.319   msaitoh 		/*
   5171  1.319   msaitoh 		 * Set up the interrupt throttling register (units of 256ns)
   5172  1.319   msaitoh 		 * Note that a footnote in Intel's documentation says this
   5173  1.319   msaitoh 		 * ticker runs at 1/4 the rate when the chip is in 100Mbit
   5174  1.319   msaitoh 		 * or 10Mbit mode.  Empirically, it appears to be the case
   5175  1.319   msaitoh 		 * that that is also true for the 1024ns units of the other
   5176  1.319   msaitoh 		 * interrupt-related timer registers -- so, really, we ought
   5177  1.319   msaitoh 		 * to divide this value by 4 when the link speed is low.
   5178  1.319   msaitoh 		 *
   5179  1.319   msaitoh 		 * XXX implement this division at link speed change!
   5180  1.319   msaitoh 		 */
   5181  1.319   msaitoh 
   5182  1.319   msaitoh 		/*
   5183  1.319   msaitoh 		 * For N interrupts/sec, set this value to:
   5184  1.489  knakahar 		 * 1,000,000,000 / (N * 256).  Note that we set the
   5185  1.319   msaitoh 		 * absolute and packet timer values to this value
   5186  1.319   msaitoh 		 * divided by 4 to get "simple timer" behavior.
   5187  1.319   msaitoh 		 */
   5188  1.490  knakahar 		sc->sc_itr_init = 1500;		/* 2604 ints/sec */
   5189  1.319   msaitoh 	}
   5190  1.319   msaitoh 
   5191  1.355  knakahar 	error = wm_init_txrx_queues(sc);
   5192  1.355  knakahar 	if (error)
   5193  1.355  knakahar 		goto out;
   5194  1.232    bouyer 
   5195  1.281   msaitoh 	/*
   5196  1.281   msaitoh 	 * Clear out the VLAN table -- we don't use it (yet).
   5197  1.281   msaitoh 	 */
   5198  1.281   msaitoh 	CSR_WRITE(sc, WMREG_VET, 0);
   5199  1.281   msaitoh 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   5200  1.281   msaitoh 		trynum = 10; /* Due to hw errata */
   5201  1.281   msaitoh 	else
   5202  1.281   msaitoh 		trynum = 1;
   5203  1.281   msaitoh 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
   5204  1.281   msaitoh 		for (j = 0; j < trynum; j++)
   5205  1.281   msaitoh 			CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
   5206  1.232    bouyer 
   5207  1.281   msaitoh 	/*
   5208  1.281   msaitoh 	 * Set up flow-control parameters.
   5209  1.281   msaitoh 	 *
   5210  1.281   msaitoh 	 * XXX Values could probably stand some tuning.
   5211  1.281   msaitoh 	 */
   5212  1.281   msaitoh 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
   5213  1.281   msaitoh 	    && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
   5214  1.392   msaitoh 	    && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)
   5215  1.392   msaitoh 	    && (sc->sc_type != WM_T_PCH_SPT)) {
   5216  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
   5217  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
   5218  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
   5219  1.281   msaitoh 	}
   5220  1.232    bouyer 
   5221  1.281   msaitoh 	sc->sc_fcrtl = FCRTL_DFLT;
   5222  1.281   msaitoh 	if (sc->sc_type < WM_T_82543) {
   5223  1.281   msaitoh 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
   5224  1.281   msaitoh 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
   5225  1.281   msaitoh 	} else {
   5226  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
   5227  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
   5228  1.281   msaitoh 	}
   5229  1.232    bouyer 
   5230  1.281   msaitoh 	if (sc->sc_type == WM_T_80003)
   5231  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
   5232  1.281   msaitoh 	else
   5233  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
   5234  1.232    bouyer 
   5235  1.281   msaitoh 	/* Writes the control register. */
   5236  1.281   msaitoh 	wm_set_vlan(sc);
   5237  1.232    bouyer 
   5238  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII) {
   5239  1.281   msaitoh 		int val;
   5240  1.232    bouyer 
   5241  1.281   msaitoh 		switch (sc->sc_type) {
   5242  1.281   msaitoh 		case WM_T_80003:
   5243  1.281   msaitoh 		case WM_T_ICH8:
   5244  1.281   msaitoh 		case WM_T_ICH9:
   5245  1.281   msaitoh 		case WM_T_ICH10:
   5246  1.281   msaitoh 		case WM_T_PCH:
   5247  1.281   msaitoh 		case WM_T_PCH2:
   5248  1.281   msaitoh 		case WM_T_PCH_LPT:
   5249  1.392   msaitoh 		case WM_T_PCH_SPT:
   5250  1.281   msaitoh 			/*
   5251  1.281   msaitoh 			 * Set the mac to wait the maximum time between each
   5252  1.281   msaitoh 			 * iteration and increase the max iterations when
   5253  1.281   msaitoh 			 * polling the phy; this fixes erroneous timeouts at
   5254  1.281   msaitoh 			 * 10Mbps.
   5255  1.281   msaitoh 			 */
   5256  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
   5257  1.281   msaitoh 			    0xFFFF);
   5258  1.388   msaitoh 			val = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM);
   5259  1.281   msaitoh 			val |= 0x3F;
   5260  1.281   msaitoh 			wm_kmrn_writereg(sc,
   5261  1.281   msaitoh 			    KUMCTRLSTA_OFFSET_INB_PARAM, val);
   5262  1.281   msaitoh 			break;
   5263  1.281   msaitoh 		default:
   5264  1.281   msaitoh 			break;
   5265  1.232    bouyer 		}
   5266  1.232    bouyer 
   5267  1.281   msaitoh 		if (sc->sc_type == WM_T_80003) {
   5268  1.281   msaitoh 			val = CSR_READ(sc, WMREG_CTRL_EXT);
   5269  1.281   msaitoh 			val &= ~CTRL_EXT_LINK_MODE_MASK;
   5270  1.281   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, val);
   5271  1.232    bouyer 
   5272  1.281   msaitoh 			/* Bypass RX and TX FIFO's */
   5273  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
   5274  1.281   msaitoh 			    KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
   5275  1.281   msaitoh 			    | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
   5276  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
   5277  1.281   msaitoh 			    KUMCTRLSTA_INB_CTRL_DIS_PADDING |
   5278  1.281   msaitoh 			    KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
   5279  1.232    bouyer 		}
   5280  1.281   msaitoh 	}
   5281  1.281   msaitoh #if 0
   5282  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   5283  1.281   msaitoh #endif
   5284  1.232    bouyer 
   5285  1.281   msaitoh 	/* Set up checksum offload parameters. */
   5286  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_RXCSUM);
   5287  1.281   msaitoh 	reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
   5288  1.281   msaitoh 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
   5289  1.281   msaitoh 		reg |= RXCSUM_IPOFL;
   5290  1.281   msaitoh 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
   5291  1.281   msaitoh 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
   5292  1.281   msaitoh 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
   5293  1.281   msaitoh 		reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
   5294  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
   5295  1.232    bouyer 
   5296  1.502  knakahar 	/* Set registers about MSI-X */
   5297  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   5298  1.335   msaitoh 		uint32_t ivar;
   5299  1.405  knakahar 		struct wm_queue *wmq;
   5300  1.405  knakahar 		int qid, qintr_idx;
   5301  1.335   msaitoh 
   5302  1.335   msaitoh 		if (sc->sc_type == WM_T_82575) {
   5303  1.335   msaitoh 			/* Interrupt control */
   5304  1.335   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5305  1.335   msaitoh 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;
   5306  1.335   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   5307  1.335   msaitoh 
   5308  1.405  knakahar 			/* TX and RX */
   5309  1.405  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5310  1.405  knakahar 				wmq = &sc->sc_queue[i];
   5311  1.405  knakahar 				CSR_WRITE(sc, WMREG_MSIXBM(wmq->wmq_intr_idx),
   5312  1.405  knakahar 				    EITR_TX_QUEUE(wmq->wmq_id)
   5313  1.405  knakahar 				    | EITR_RX_QUEUE(wmq->wmq_id));
   5314  1.364  knakahar 			}
   5315  1.335   msaitoh 			/* Link status */
   5316  1.364  knakahar 			CSR_WRITE(sc, WMREG_MSIXBM(sc->sc_link_intr_idx),
   5317  1.335   msaitoh 			    EITR_OTHER);
   5318  1.335   msaitoh 		} else if (sc->sc_type == WM_T_82574) {
   5319  1.335   msaitoh 			/* Interrupt control */
   5320  1.335   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5321  1.335   msaitoh 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;
   5322  1.335   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   5323  1.335   msaitoh 
   5324  1.487  knakahar 			/*
   5325  1.487  knakahar 			 * workaround issue with spurious interrupts
   5326  1.487  knakahar 			 * in MSI-X mode.
   5327  1.487  knakahar 			 * At wm_initialize_hardware_bits(), sc_nintrs has not
   5328  1.487  knakahar 			 * initialized yet. So re-initialize WMREG_RFCTL here.
   5329  1.487  knakahar 			 */
   5330  1.487  knakahar 			reg = CSR_READ(sc, WMREG_RFCTL);
   5331  1.487  knakahar 			reg |= WMREG_RFCTL_ACKDIS;
   5332  1.487  knakahar 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   5333  1.487  knakahar 
   5334  1.364  knakahar 			ivar = 0;
   5335  1.405  knakahar 			/* TX and RX */
   5336  1.405  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5337  1.405  knakahar 				wmq = &sc->sc_queue[i];
   5338  1.405  knakahar 				qid = wmq->wmq_id;
   5339  1.405  knakahar 				qintr_idx = wmq->wmq_intr_idx;
   5340  1.405  knakahar 
   5341  1.405  knakahar 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
   5342  1.405  knakahar 				    IVAR_TX_MASK_Q_82574(qid));
   5343  1.405  knakahar 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
   5344  1.405  knakahar 				    IVAR_RX_MASK_Q_82574(qid));
   5345  1.364  knakahar 			}
   5346  1.364  knakahar 			/* Link status */
   5347  1.388   msaitoh 			ivar |= __SHIFTIN((IVAR_VALID_82574
   5348  1.388   msaitoh 				| sc->sc_link_intr_idx), IVAR_OTHER_MASK);
   5349  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
   5350  1.335   msaitoh 		} else {
   5351  1.335   msaitoh 			/* Interrupt control */
   5352  1.388   msaitoh 			CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | GPIE_MULTI_MSIX
   5353  1.388   msaitoh 			    | GPIE_EIAME | GPIE_PBA);
   5354  1.335   msaitoh 
   5355  1.335   msaitoh 			switch (sc->sc_type) {
   5356  1.335   msaitoh 			case WM_T_82580:
   5357  1.335   msaitoh 			case WM_T_I350:
   5358  1.335   msaitoh 			case WM_T_I354:
   5359  1.335   msaitoh 			case WM_T_I210:
   5360  1.335   msaitoh 			case WM_T_I211:
   5361  1.405  knakahar 				/* TX and RX */
   5362  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5363  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5364  1.405  knakahar 					qid = wmq->wmq_id;
   5365  1.405  knakahar 					qintr_idx = wmq->wmq_intr_idx;
   5366  1.405  knakahar 
   5367  1.364  knakahar 					ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
   5368  1.364  knakahar 					ivar &= ~IVAR_TX_MASK_Q(qid);
   5369  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5370  1.388   msaitoh 						| IVAR_VALID),
   5371  1.388   msaitoh 					    IVAR_TX_MASK_Q(qid));
   5372  1.364  knakahar 					ivar &= ~IVAR_RX_MASK_Q(qid);
   5373  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5374  1.388   msaitoh 						| IVAR_VALID),
   5375  1.388   msaitoh 					    IVAR_RX_MASK_Q(qid));
   5376  1.364  knakahar 					CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
   5377  1.364  knakahar 				}
   5378  1.335   msaitoh 				break;
   5379  1.335   msaitoh 			case WM_T_82576:
   5380  1.405  knakahar 				/* TX and RX */
   5381  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5382  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5383  1.405  knakahar 					qid = wmq->wmq_id;
   5384  1.405  knakahar 					qintr_idx = wmq->wmq_intr_idx;
   5385  1.405  knakahar 
   5386  1.388   msaitoh 					ivar = CSR_READ(sc,
   5387  1.388   msaitoh 					    WMREG_IVAR_Q_82576(qid));
   5388  1.364  knakahar 					ivar &= ~IVAR_TX_MASK_Q_82576(qid);
   5389  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5390  1.388   msaitoh 						| IVAR_VALID),
   5391  1.388   msaitoh 					    IVAR_TX_MASK_Q_82576(qid));
   5392  1.364  knakahar 					ivar &= ~IVAR_RX_MASK_Q_82576(qid);
   5393  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5394  1.388   msaitoh 						| IVAR_VALID),
   5395  1.388   msaitoh 					    IVAR_RX_MASK_Q_82576(qid));
   5396  1.388   msaitoh 					CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid),
   5397  1.388   msaitoh 					    ivar);
   5398  1.364  knakahar 				}
   5399  1.335   msaitoh 				break;
   5400  1.335   msaitoh 			default:
   5401  1.335   msaitoh 				break;
   5402  1.335   msaitoh 			}
   5403  1.335   msaitoh 
   5404  1.335   msaitoh 			/* Link status */
   5405  1.364  knakahar 			ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID),
   5406  1.335   msaitoh 			    IVAR_MISC_OTHER);
   5407  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IVAR_MISC, ivar);
   5408  1.335   msaitoh 		}
   5409  1.365  knakahar 
   5410  1.502  knakahar 		if (wm_is_using_multiqueue(sc)) {
   5411  1.365  knakahar 			wm_init_rss(sc);
   5412  1.365  knakahar 
   5413  1.365  knakahar 			/*
   5414  1.365  knakahar 			** NOTE: Receive Full-Packet Checksum Offload
   5415  1.365  knakahar 			** is mutually exclusive with Multiqueue. However
   5416  1.365  knakahar 			** this is not the same as TCP/IP checksums which
   5417  1.365  knakahar 			** still work.
   5418  1.365  knakahar 			*/
   5419  1.365  knakahar 			reg = CSR_READ(sc, WMREG_RXCSUM);
   5420  1.365  knakahar 			reg |= RXCSUM_PCSD;
   5421  1.365  knakahar 			CSR_WRITE(sc, WMREG_RXCSUM, reg);
   5422  1.365  knakahar 		}
   5423  1.335   msaitoh 	}
   5424  1.335   msaitoh 
   5425  1.281   msaitoh 	/* Set up the interrupt registers. */
   5426  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   5427  1.281   msaitoh 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
   5428  1.281   msaitoh 	    ICR_RXO | ICR_RXT0;
   5429  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   5430  1.335   msaitoh 		uint32_t mask;
   5431  1.405  knakahar 		struct wm_queue *wmq;
   5432  1.388   msaitoh 
   5433  1.335   msaitoh 		switch (sc->sc_type) {
   5434  1.335   msaitoh 		case WM_T_82574:
   5435  1.486  knakahar 			mask = 0;
   5436  1.486  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5437  1.486  knakahar 				wmq = &sc->sc_queue[i];
   5438  1.486  knakahar 				mask |= ICR_TXQ(wmq->wmq_id);
   5439  1.486  knakahar 				mask |= ICR_RXQ(wmq->wmq_id);
   5440  1.486  knakahar 			}
   5441  1.486  knakahar 			mask |= ICR_OTHER;
   5442  1.486  knakahar 			CSR_WRITE(sc, WMREG_EIAC_82574, mask);
   5443  1.486  knakahar 			CSR_WRITE(sc, WMREG_IMS, mask | ICR_LSC);
   5444  1.335   msaitoh 			break;
   5445  1.335   msaitoh 		default:
   5446  1.364  knakahar 			if (sc->sc_type == WM_T_82575) {
   5447  1.364  knakahar 				mask = 0;
   5448  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5449  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5450  1.405  knakahar 					mask |= EITR_TX_QUEUE(wmq->wmq_id);
   5451  1.405  knakahar 					mask |= EITR_RX_QUEUE(wmq->wmq_id);
   5452  1.364  knakahar 				}
   5453  1.364  knakahar 				mask |= EITR_OTHER;
   5454  1.364  knakahar 			} else {
   5455  1.364  knakahar 				mask = 0;
   5456  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5457  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5458  1.405  knakahar 					mask |= 1 << wmq->wmq_intr_idx;
   5459  1.364  knakahar 				}
   5460  1.364  knakahar 				mask |= 1 << sc->sc_link_intr_idx;
   5461  1.364  knakahar 			}
   5462  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, mask);
   5463  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAM, mask);
   5464  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMS, mask);
   5465  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
   5466  1.335   msaitoh 			break;
   5467  1.335   msaitoh 		}
   5468  1.335   msaitoh 	} else
   5469  1.335   msaitoh 		CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
   5470  1.232    bouyer 
   5471  1.281   msaitoh 	/* Set up the inter-packet gap. */
   5472  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   5473  1.232    bouyer 
   5474  1.281   msaitoh 	if (sc->sc_type >= WM_T_82543) {
   5475  1.491  knakahar 		for (int qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5476  1.491  knakahar 			struct wm_queue *wmq = &sc->sc_queue[qidx];
   5477  1.491  knakahar 			wm_itrs_writereg(sc, wmq);
   5478  1.491  knakahar 		}
   5479  1.491  knakahar 		/*
   5480  1.491  knakahar 		 * Link interrupts occur much less than TX
   5481  1.491  knakahar 		 * interrupts and RX interrupts. So, we don't
   5482  1.491  knakahar 		 * tune EINTR(WM_MSIX_LINKINTR_IDX) value like
   5483  1.491  knakahar 		 * FreeBSD's if_igb.
   5484  1.491  knakahar 		 */
   5485  1.281   msaitoh 	}
   5486  1.232    bouyer 
   5487  1.281   msaitoh 	/* Set the VLAN ethernetype. */
   5488  1.281   msaitoh 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
   5489  1.232    bouyer 
   5490  1.281   msaitoh 	/*
   5491  1.281   msaitoh 	 * Set up the transmit control register; we start out with
   5492  1.281   msaitoh 	 * a collision distance suitable for FDX, but update it whe
   5493  1.281   msaitoh 	 * we resolve the media type.
   5494  1.281   msaitoh 	 */
   5495  1.281   msaitoh 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
   5496  1.281   msaitoh 	    | TCTL_CT(TX_COLLISION_THRESHOLD)
   5497  1.281   msaitoh 	    | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   5498  1.281   msaitoh 	if (sc->sc_type >= WM_T_82571)
   5499  1.281   msaitoh 		sc->sc_tctl |= TCTL_MULR;
   5500  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   5501  1.232    bouyer 
   5502  1.281   msaitoh 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   5503  1.281   msaitoh 		/* Write TDT after TCTL.EN is set. See the document. */
   5504  1.361  knakahar 		CSR_WRITE(sc, WMREG_TDT(0), 0);
   5505  1.232    bouyer 	}
   5506  1.232    bouyer 
   5507  1.281   msaitoh 	if (sc->sc_type == WM_T_80003) {
   5508  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_TCTL_EXT);
   5509  1.281   msaitoh 		reg &= ~TCTL_EXT_GCEX_MASK;
   5510  1.281   msaitoh 		reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
   5511  1.281   msaitoh 		CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
   5512  1.272     ozaki 	}
   5513  1.272     ozaki 
   5514  1.281   msaitoh 	/* Set the media. */
   5515  1.281   msaitoh 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
   5516  1.281   msaitoh 		goto out;
   5517  1.281   msaitoh 
   5518  1.281   msaitoh 	/* Configure for OS presence */
   5519  1.281   msaitoh 	wm_init_manageability(sc);
   5520  1.232    bouyer 
   5521  1.281   msaitoh 	/*
   5522  1.281   msaitoh 	 * Set up the receive control register; we actually program
   5523  1.281   msaitoh 	 * the register when we set the receive filter.  Use multicast
   5524  1.281   msaitoh 	 * address offset type 0.
   5525  1.281   msaitoh 	 *
   5526  1.281   msaitoh 	 * Only the i82544 has the ability to strip the incoming
   5527  1.281   msaitoh 	 * CRC, so we don't enable that feature.
   5528  1.281   msaitoh 	 */
   5529  1.281   msaitoh 	sc->sc_mchash_type = 0;
   5530  1.281   msaitoh 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
   5531  1.281   msaitoh 	    | RCTL_MO(sc->sc_mchash_type);
   5532  1.281   msaitoh 
   5533  1.281   msaitoh 	/*
   5534  1.466  knakahar 	 * 82574 use one buffer extended Rx descriptor.
   5535  1.466  knakahar 	 */
   5536  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   5537  1.466  knakahar 		sc->sc_rctl |= RCTL_DTYP_ONEBUF;
   5538  1.466  knakahar 
   5539  1.466  knakahar 	/*
   5540  1.281   msaitoh 	 * The I350 has a bug where it always strips the CRC whether
   5541  1.281   msaitoh 	 * asked to or not. So ask for stripped CRC here and cope in rxeof
   5542  1.281   msaitoh 	 */
   5543  1.281   msaitoh 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   5544  1.281   msaitoh 	    || (sc->sc_type == WM_T_I210))
   5545  1.281   msaitoh 		sc->sc_rctl |= RCTL_SECRC;
   5546  1.281   msaitoh 
   5547  1.281   msaitoh 	if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
   5548  1.281   msaitoh 	    && (ifp->if_mtu > ETHERMTU)) {
   5549  1.281   msaitoh 		sc->sc_rctl |= RCTL_LPE;
   5550  1.281   msaitoh 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   5551  1.281   msaitoh 			CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
   5552  1.281   msaitoh 	}
   5553  1.281   msaitoh 
   5554  1.281   msaitoh 	if (MCLBYTES == 2048) {
   5555  1.281   msaitoh 		sc->sc_rctl |= RCTL_2k;
   5556  1.281   msaitoh 	} else {
   5557  1.281   msaitoh 		if (sc->sc_type >= WM_T_82543) {
   5558  1.281   msaitoh 			switch (MCLBYTES) {
   5559  1.281   msaitoh 			case 4096:
   5560  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
   5561  1.281   msaitoh 				break;
   5562  1.281   msaitoh 			case 8192:
   5563  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
   5564  1.281   msaitoh 				break;
   5565  1.281   msaitoh 			case 16384:
   5566  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
   5567  1.281   msaitoh 				break;
   5568  1.281   msaitoh 			default:
   5569  1.281   msaitoh 				panic("wm_init: MCLBYTES %d unsupported",
   5570  1.281   msaitoh 				    MCLBYTES);
   5571  1.281   msaitoh 				break;
   5572  1.281   msaitoh 			}
   5573  1.281   msaitoh 		} else panic("wm_init: i82542 requires MCLBYTES = 2048");
   5574  1.281   msaitoh 	}
   5575  1.281   msaitoh 
   5576  1.281   msaitoh 	/* Enable ECC */
   5577  1.281   msaitoh 	switch (sc->sc_type) {
   5578  1.281   msaitoh 	case WM_T_82571:
   5579  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PBA_ECC);
   5580  1.281   msaitoh 		reg |= PBA_ECC_CORR_EN;
   5581  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBA_ECC, reg);
   5582  1.281   msaitoh 		break;
   5583  1.281   msaitoh 	case WM_T_PCH_LPT:
   5584  1.392   msaitoh 	case WM_T_PCH_SPT:
   5585  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PBECCSTS);
   5586  1.281   msaitoh 		reg |= PBECCSTS_UNCORR_ECC_ENABLE;
   5587  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBECCSTS, reg);
   5588  1.281   msaitoh 
   5589  1.444   msaitoh 		sc->sc_ctrl |= CTRL_MEHE;
   5590  1.444   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   5591  1.281   msaitoh 		break;
   5592  1.281   msaitoh 	default:
   5593  1.281   msaitoh 		break;
   5594  1.232    bouyer 	}
   5595  1.281   msaitoh 
   5596  1.281   msaitoh 	/* On 575 and later set RDT only if RX enabled */
   5597  1.362  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   5598  1.364  knakahar 		int qidx;
   5599  1.405  knakahar 		for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5600  1.405  knakahar 			struct wm_rxqueue *rxq = &sc->sc_queue[qidx].wmq_rxq;
   5601  1.364  knakahar 			for (i = 0; i < WM_NRXDESC; i++) {
   5602  1.413     skrll 				mutex_enter(rxq->rxq_lock);
   5603  1.364  knakahar 				wm_init_rxdesc(rxq, i);
   5604  1.413     skrll 				mutex_exit(rxq->rxq_lock);
   5605  1.364  knakahar 
   5606  1.364  knakahar 			}
   5607  1.364  knakahar 		}
   5608  1.362  knakahar 	}
   5609  1.281   msaitoh 
   5610  1.515   msaitoh 	/* Set the receive filter. */
   5611  1.515   msaitoh 	wm_set_filter(sc);
   5612  1.515   msaitoh 
   5613  1.429  knakahar 	wm_turnon(sc);
   5614  1.281   msaitoh 
   5615  1.281   msaitoh 	/* Start the one second link check clock. */
   5616  1.281   msaitoh 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   5617  1.281   msaitoh 
   5618  1.281   msaitoh 	/* ...all done! */
   5619  1.281   msaitoh 	ifp->if_flags |= IFF_RUNNING;
   5620  1.281   msaitoh 	ifp->if_flags &= ~IFF_OACTIVE;
   5621  1.281   msaitoh 
   5622  1.281   msaitoh  out:
   5623  1.281   msaitoh 	sc->sc_if_flags = ifp->if_flags;
   5624  1.281   msaitoh 	if (error)
   5625  1.281   msaitoh 		log(LOG_ERR, "%s: interface not running\n",
   5626  1.281   msaitoh 		    device_xname(sc->sc_dev));
   5627  1.281   msaitoh 	return error;
   5628  1.232    bouyer }
   5629  1.232    bouyer 
   5630  1.232    bouyer /*
   5631  1.281   msaitoh  * wm_stop:		[ifnet interface function]
   5632    1.1   thorpej  *
   5633  1.281   msaitoh  *	Stop transmission on the interface.
   5634    1.1   thorpej  */
   5635   1.47   thorpej static void
   5636  1.281   msaitoh wm_stop(struct ifnet *ifp, int disable)
   5637    1.1   thorpej {
   5638    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   5639    1.1   thorpej 
   5640  1.357  knakahar 	WM_CORE_LOCK(sc);
   5641  1.281   msaitoh 	wm_stop_locked(ifp, disable);
   5642  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   5643    1.1   thorpej }
   5644    1.1   thorpej 
   5645  1.281   msaitoh static void
   5646  1.281   msaitoh wm_stop_locked(struct ifnet *ifp, int disable)
   5647  1.213   msaitoh {
   5648  1.213   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   5649  1.281   msaitoh 	struct wm_txsoft *txs;
   5650  1.364  knakahar 	int i, qidx;
   5651  1.281   msaitoh 
   5652  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   5653  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   5654  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5655  1.281   msaitoh 
   5656  1.429  knakahar 	wm_turnoff(sc);
   5657  1.272     ozaki 
   5658  1.281   msaitoh 	/* Stop the one second clock. */
   5659  1.281   msaitoh 	callout_stop(&sc->sc_tick_ch);
   5660  1.213   msaitoh 
   5661  1.281   msaitoh 	/* Stop the 82547 Tx FIFO stall check timer. */
   5662  1.281   msaitoh 	if (sc->sc_type == WM_T_82547)
   5663  1.281   msaitoh 		callout_stop(&sc->sc_txfifo_ch);
   5664  1.217    dyoung 
   5665  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII) {
   5666  1.281   msaitoh 		/* Down the MII. */
   5667  1.281   msaitoh 		mii_down(&sc->sc_mii);
   5668  1.281   msaitoh 	} else {
   5669  1.281   msaitoh #if 0
   5670  1.281   msaitoh 		/* Should we clear PHY's status properly? */
   5671  1.281   msaitoh 		wm_reset(sc);
   5672  1.281   msaitoh #endif
   5673  1.272     ozaki 	}
   5674  1.213   msaitoh 
   5675  1.281   msaitoh 	/* Stop the transmit and receive processes. */
   5676  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, 0);
   5677  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, 0);
   5678  1.281   msaitoh 	sc->sc_rctl &= ~RCTL_EN;
   5679  1.281   msaitoh 
   5680  1.281   msaitoh 	/*
   5681  1.281   msaitoh 	 * Clear the interrupt mask to ensure the device cannot assert its
   5682  1.281   msaitoh 	 * interrupt line.
   5683  1.335   msaitoh 	 * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to
   5684  1.335   msaitoh 	 * service any currently pending or shared interrupt.
   5685  1.281   msaitoh 	 */
   5686  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   5687  1.281   msaitoh 	sc->sc_icr = 0;
   5688  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   5689  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   5690  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   5691  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   5692  1.335   msaitoh 		} else
   5693  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   5694  1.335   msaitoh 	}
   5695  1.281   msaitoh 
   5696  1.281   msaitoh 	/* Release any queued transmit buffers. */
   5697  1.405  knakahar 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5698  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   5699  1.405  knakahar 		struct wm_txqueue *txq = &wmq->wmq_txq;
   5700  1.413     skrll 		mutex_enter(txq->txq_lock);
   5701  1.364  knakahar 		for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   5702  1.364  knakahar 			txs = &txq->txq_soft[i];
   5703  1.364  knakahar 			if (txs->txs_mbuf != NULL) {
   5704  1.388   msaitoh 				bus_dmamap_unload(sc->sc_dmat,txs->txs_dmamap);
   5705  1.364  knakahar 				m_freem(txs->txs_mbuf);
   5706  1.364  knakahar 				txs->txs_mbuf = NULL;
   5707  1.364  knakahar 			}
   5708  1.281   msaitoh 		}
   5709  1.413     skrll 		mutex_exit(txq->txq_lock);
   5710  1.281   msaitoh 	}
   5711  1.217    dyoung 
   5712  1.281   msaitoh 	/* Mark the interface as down and cancel the watchdog timer. */
   5713  1.281   msaitoh 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   5714  1.281   msaitoh 	ifp->if_timer = 0;
   5715  1.213   msaitoh 
   5716  1.357  knakahar 	if (disable) {
   5717  1.405  knakahar 		for (i = 0; i < sc->sc_nqueues; i++) {
   5718  1.405  knakahar 			struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   5719  1.413     skrll 			mutex_enter(rxq->rxq_lock);
   5720  1.364  knakahar 			wm_rxdrain(rxq);
   5721  1.413     skrll 			mutex_exit(rxq->rxq_lock);
   5722  1.364  knakahar 		}
   5723  1.357  knakahar 	}
   5724  1.272     ozaki 
   5725  1.281   msaitoh #if 0 /* notyet */
   5726  1.281   msaitoh 	if (sc->sc_type >= WM_T_82544)
   5727  1.281   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   5728  1.281   msaitoh #endif
   5729  1.213   msaitoh }
   5730  1.213   msaitoh 
   5731   1.47   thorpej static void
   5732  1.281   msaitoh wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
   5733    1.1   thorpej {
   5734  1.281   msaitoh 	struct mbuf *m;
   5735    1.1   thorpej 	int i;
   5736    1.1   thorpej 
   5737  1.281   msaitoh 	log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev));
   5738  1.281   msaitoh 	for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
   5739  1.281   msaitoh 		log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
   5740  1.281   msaitoh 		    "m_flags = 0x%08x\n", device_xname(sc->sc_dev),
   5741  1.281   msaitoh 		    m->m_data, m->m_len, m->m_flags);
   5742  1.281   msaitoh 	log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev),
   5743  1.281   msaitoh 	    i, i == 1 ? "" : "s");
   5744  1.281   msaitoh }
   5745  1.272     ozaki 
   5746  1.281   msaitoh /*
   5747  1.281   msaitoh  * wm_82547_txfifo_stall:
   5748  1.281   msaitoh  *
   5749  1.281   msaitoh  *	Callout used to wait for the 82547 Tx FIFO to drain,
   5750  1.281   msaitoh  *	reset the FIFO pointers, and restart packet transmission.
   5751  1.281   msaitoh  */
   5752  1.281   msaitoh static void
   5753  1.281   msaitoh wm_82547_txfifo_stall(void *arg)
   5754  1.281   msaitoh {
   5755  1.281   msaitoh 	struct wm_softc *sc = arg;
   5756  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   5757    1.1   thorpej 
   5758  1.413     skrll 	mutex_enter(txq->txq_lock);
   5759    1.1   thorpej 
   5760  1.429  knakahar 	if (txq->txq_stopping)
   5761  1.281   msaitoh 		goto out;
   5762    1.1   thorpej 
   5763  1.356  knakahar 	if (txq->txq_fifo_stall) {
   5764  1.361  knakahar 		if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) &&
   5765  1.281   msaitoh 		    CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
   5766  1.281   msaitoh 		    CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
   5767  1.281   msaitoh 			/*
   5768  1.281   msaitoh 			 * Packets have drained.  Stop transmitter, reset
   5769  1.281   msaitoh 			 * FIFO pointers, restart transmitter, and kick
   5770  1.281   msaitoh 			 * the packet queue.
   5771  1.281   msaitoh 			 */
   5772  1.281   msaitoh 			uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
   5773  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
   5774  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr);
   5775  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr);
   5776  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr);
   5777  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr);
   5778  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, tctl);
   5779  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   5780    1.1   thorpej 
   5781  1.356  knakahar 			txq->txq_fifo_head = 0;
   5782  1.356  knakahar 			txq->txq_fifo_stall = 0;
   5783  1.281   msaitoh 			wm_start_locked(&sc->sc_ethercom.ec_if);
   5784  1.281   msaitoh 		} else {
   5785  1.281   msaitoh 			/*
   5786  1.281   msaitoh 			 * Still waiting for packets to drain; try again in
   5787  1.281   msaitoh 			 * another tick.
   5788  1.281   msaitoh 			 */
   5789  1.281   msaitoh 			callout_schedule(&sc->sc_txfifo_ch, 1);
   5790   1.20   thorpej 		}
   5791  1.281   msaitoh 	}
   5792    1.1   thorpej 
   5793  1.281   msaitoh out:
   5794  1.413     skrll 	mutex_exit(txq->txq_lock);
   5795  1.281   msaitoh }
   5796    1.1   thorpej 
   5797  1.281   msaitoh /*
   5798  1.281   msaitoh  * wm_82547_txfifo_bugchk:
   5799  1.281   msaitoh  *
   5800  1.281   msaitoh  *	Check for bug condition in the 82547 Tx FIFO.  We need to
   5801  1.281   msaitoh  *	prevent enqueueing a packet that would wrap around the end
   5802  1.281   msaitoh  *	if the Tx FIFO ring buffer, otherwise the chip will croak.
   5803  1.281   msaitoh  *
   5804  1.281   msaitoh  *	We do this by checking the amount of space before the end
   5805  1.281   msaitoh  *	of the Tx FIFO buffer.  If the packet will not fit, we "stall"
   5806  1.281   msaitoh  *	the Tx FIFO, wait for all remaining packets to drain, reset
   5807  1.281   msaitoh  *	the internal FIFO pointers to the beginning, and restart
   5808  1.281   msaitoh  *	transmission on the interface.
   5809  1.281   msaitoh  */
   5810  1.281   msaitoh #define	WM_FIFO_HDR		0x10
   5811  1.281   msaitoh #define	WM_82547_PAD_LEN	0x3e0
   5812  1.281   msaitoh static int
   5813  1.281   msaitoh wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
   5814  1.281   msaitoh {
   5815  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   5816  1.356  knakahar 	int space = txq->txq_fifo_size - txq->txq_fifo_head;
   5817  1.281   msaitoh 	int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
   5818    1.1   thorpej 
   5819  1.281   msaitoh 	/* Just return if already stalled. */
   5820  1.356  knakahar 	if (txq->txq_fifo_stall)
   5821  1.281   msaitoh 		return 1;
   5822    1.1   thorpej 
   5823  1.281   msaitoh 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   5824  1.281   msaitoh 		/* Stall only occurs in half-duplex mode. */
   5825  1.281   msaitoh 		goto send_packet;
   5826  1.281   msaitoh 	}
   5827    1.1   thorpej 
   5828  1.281   msaitoh 	if (len >= WM_82547_PAD_LEN + space) {
   5829  1.356  knakahar 		txq->txq_fifo_stall = 1;
   5830  1.281   msaitoh 		callout_schedule(&sc->sc_txfifo_ch, 1);
   5831  1.281   msaitoh 		return 1;
   5832    1.1   thorpej 	}
   5833    1.1   thorpej 
   5834  1.281   msaitoh  send_packet:
   5835  1.356  knakahar 	txq->txq_fifo_head += len;
   5836  1.356  knakahar 	if (txq->txq_fifo_head >= txq->txq_fifo_size)
   5837  1.356  knakahar 		txq->txq_fifo_head -= txq->txq_fifo_size;
   5838    1.1   thorpej 
   5839  1.281   msaitoh 	return 0;
   5840    1.1   thorpej }
   5841    1.1   thorpej 
   5842  1.353  knakahar static int
   5843  1.362  knakahar wm_alloc_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
   5844  1.354  knakahar {
   5845  1.354  knakahar 	int error;
   5846  1.354  knakahar 
   5847  1.354  knakahar 	/*
   5848  1.354  knakahar 	 * Allocate the control data structures, and create and load the
   5849  1.354  knakahar 	 * DMA map for it.
   5850  1.354  knakahar 	 *
   5851  1.354  knakahar 	 * NOTE: All Tx descriptors must be in the same 4G segment of
   5852  1.354  knakahar 	 * memory.  So must Rx descriptors.  We simplify by allocating
   5853  1.354  knakahar 	 * both sets within the same 4G segment.
   5854  1.354  knakahar 	 */
   5855  1.399  knakahar 	if (sc->sc_type < WM_T_82544)
   5856  1.356  knakahar 		WM_NTXDESC(txq) = WM_NTXDESC_82542;
   5857  1.399  knakahar 	else
   5858  1.356  knakahar 		WM_NTXDESC(txq) = WM_NTXDESC_82544;
   5859  1.398  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   5860  1.398  knakahar 		txq->txq_descsize = sizeof(nq_txdesc_t);
   5861  1.398  knakahar 	else
   5862  1.398  knakahar 		txq->txq_descsize = sizeof(wiseman_txdesc_t);
   5863  1.354  knakahar 
   5864  1.399  knakahar 	if ((error = bus_dmamem_alloc(sc->sc_dmat, WM_TXDESCS_SIZE(txq),
   5865  1.388   msaitoh 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg,
   5866  1.388   msaitoh 		    1, &txq->txq_desc_rseg, 0)) != 0) {
   5867  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   5868  1.354  knakahar 		    "unable to allocate TX control data, error = %d\n",
   5869  1.354  knakahar 		    error);
   5870  1.354  knakahar 		goto fail_0;
   5871  1.354  knakahar 	}
   5872  1.354  knakahar 
   5873  1.356  knakahar 	if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg,
   5874  1.399  knakahar 		    txq->txq_desc_rseg, WM_TXDESCS_SIZE(txq),
   5875  1.356  knakahar 		    (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) {
   5876  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   5877  1.354  knakahar 		    "unable to map TX control data, error = %d\n", error);
   5878  1.354  knakahar 		goto fail_1;
   5879  1.354  knakahar 	}
   5880  1.354  knakahar 
   5881  1.399  knakahar 	if ((error = bus_dmamap_create(sc->sc_dmat, WM_TXDESCS_SIZE(txq), 1,
   5882  1.399  knakahar 		    WM_TXDESCS_SIZE(txq), 0, 0, &txq->txq_desc_dmamap)) != 0) {
   5883  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   5884  1.354  knakahar 		    "unable to create TX control data DMA map, error = %d\n",
   5885  1.354  knakahar 		    error);
   5886  1.354  knakahar 		goto fail_2;
   5887  1.354  knakahar 	}
   5888  1.354  knakahar 
   5889  1.356  knakahar 	if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap,
   5890  1.399  knakahar 		    txq->txq_descs_u, WM_TXDESCS_SIZE(txq), NULL, 0)) != 0) {
   5891  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   5892  1.354  knakahar 		    "unable to load TX control data DMA map, error = %d\n",
   5893  1.354  knakahar 		    error);
   5894  1.354  knakahar 		goto fail_3;
   5895  1.354  knakahar 	}
   5896  1.354  knakahar 
   5897  1.354  knakahar 	return 0;
   5898  1.354  knakahar 
   5899  1.354  knakahar  fail_3:
   5900  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
   5901  1.354  knakahar  fail_2:
   5902  1.356  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
   5903  1.399  knakahar 	    WM_TXDESCS_SIZE(txq));
   5904  1.354  knakahar  fail_1:
   5905  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
   5906  1.354  knakahar  fail_0:
   5907  1.354  knakahar 	return error;
   5908  1.354  knakahar }
   5909  1.354  knakahar 
   5910  1.354  knakahar static void
   5911  1.362  knakahar wm_free_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
   5912  1.354  knakahar {
   5913  1.354  knakahar 
   5914  1.356  knakahar 	bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap);
   5915  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
   5916  1.356  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
   5917  1.399  knakahar 	    WM_TXDESCS_SIZE(txq));
   5918  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
   5919  1.354  knakahar }
   5920  1.354  knakahar 
   5921  1.354  knakahar static int
   5922  1.362  knakahar wm_alloc_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
   5923  1.353  knakahar {
   5924  1.353  knakahar 	int error;
   5925  1.466  knakahar 	size_t rxq_descs_size;
   5926  1.353  knakahar 
   5927  1.353  knakahar 	/*
   5928  1.353  knakahar 	 * Allocate the control data structures, and create and load the
   5929  1.353  knakahar 	 * DMA map for it.
   5930  1.353  knakahar 	 *
   5931  1.353  knakahar 	 * NOTE: All Tx descriptors must be in the same 4G segment of
   5932  1.353  knakahar 	 * memory.  So must Rx descriptors.  We simplify by allocating
   5933  1.353  knakahar 	 * both sets within the same 4G segment.
   5934  1.353  knakahar 	 */
   5935  1.466  knakahar 	rxq->rxq_ndesc = WM_NRXDESC;
   5936  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   5937  1.466  knakahar 		rxq->rxq_descsize = sizeof(ext_rxdesc_t);
   5938  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   5939  1.466  knakahar 		rxq->rxq_descsize = sizeof(nq_rxdesc_t);
   5940  1.466  knakahar 	else
   5941  1.466  knakahar 		rxq->rxq_descsize = sizeof(wiseman_rxdesc_t);
   5942  1.466  knakahar 	rxq_descs_size = rxq->rxq_descsize * rxq->rxq_ndesc;
   5943  1.466  knakahar 
   5944  1.466  knakahar 	if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq_descs_size,
   5945  1.388   msaitoh 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &rxq->rxq_desc_seg,
   5946  1.388   msaitoh 		    1, &rxq->rxq_desc_rseg, 0)) != 0) {
   5947  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   5948  1.354  knakahar 		    "unable to allocate RX control data, error = %d\n",
   5949  1.353  knakahar 		    error);
   5950  1.353  knakahar 		goto fail_0;
   5951  1.353  knakahar 	}
   5952  1.353  knakahar 
   5953  1.356  knakahar 	if ((error = bus_dmamem_map(sc->sc_dmat, &rxq->rxq_desc_seg,
   5954  1.466  knakahar 		    rxq->rxq_desc_rseg, rxq_descs_size,
   5955  1.466  knakahar 		    (void **)&rxq->rxq_descs_u, BUS_DMA_COHERENT)) != 0) {
   5956  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   5957  1.354  knakahar 		    "unable to map RX control data, error = %d\n", error);
   5958  1.353  knakahar 		goto fail_1;
   5959  1.353  knakahar 	}
   5960  1.353  knakahar 
   5961  1.466  knakahar 	if ((error = bus_dmamap_create(sc->sc_dmat, rxq_descs_size, 1,
   5962  1.466  knakahar 		    rxq_descs_size, 0, 0, &rxq->rxq_desc_dmamap)) != 0) {
   5963  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   5964  1.354  knakahar 		    "unable to create RX control data DMA map, error = %d\n",
   5965  1.353  knakahar 		    error);
   5966  1.353  knakahar 		goto fail_2;
   5967  1.353  knakahar 	}
   5968  1.353  knakahar 
   5969  1.356  knakahar 	if ((error = bus_dmamap_load(sc->sc_dmat, rxq->rxq_desc_dmamap,
   5970  1.466  knakahar 		    rxq->rxq_descs_u, rxq_descs_size, NULL, 0)) != 0) {
   5971  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   5972  1.354  knakahar 		    "unable to load RX control data DMA map, error = %d\n",
   5973  1.353  knakahar 		    error);
   5974  1.353  knakahar 		goto fail_3;
   5975  1.353  knakahar 	}
   5976  1.353  knakahar 
   5977  1.353  knakahar 	return 0;
   5978  1.353  knakahar 
   5979  1.353  knakahar  fail_3:
   5980  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
   5981  1.353  knakahar  fail_2:
   5982  1.466  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
   5983  1.466  knakahar 	    rxq_descs_size);
   5984  1.353  knakahar  fail_1:
   5985  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
   5986  1.353  knakahar  fail_0:
   5987  1.353  knakahar 	return error;
   5988  1.353  knakahar }
   5989  1.353  knakahar 
   5990  1.353  knakahar static void
   5991  1.362  knakahar wm_free_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
   5992  1.353  knakahar {
   5993  1.353  knakahar 
   5994  1.356  knakahar 	bus_dmamap_unload(sc->sc_dmat, rxq->rxq_desc_dmamap);
   5995  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
   5996  1.466  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
   5997  1.466  knakahar 	    rxq->rxq_descsize * rxq->rxq_ndesc);
   5998  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
   5999  1.353  knakahar }
   6000  1.353  knakahar 
   6001  1.354  knakahar 
   6002  1.353  knakahar static int
   6003  1.362  knakahar wm_alloc_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
   6004  1.353  knakahar {
   6005  1.353  knakahar 	int i, error;
   6006  1.353  knakahar 
   6007  1.353  knakahar 	/* Create the transmit buffer DMA maps. */
   6008  1.356  knakahar 	WM_TXQUEUELEN(txq) =
   6009  1.353  knakahar 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
   6010  1.353  knakahar 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
   6011  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6012  1.353  knakahar 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
   6013  1.353  knakahar 			    WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
   6014  1.356  knakahar 			    &txq->txq_soft[i].txs_dmamap)) != 0) {
   6015  1.353  knakahar 			aprint_error_dev(sc->sc_dev,
   6016  1.353  knakahar 			    "unable to create Tx DMA map %d, error = %d\n",
   6017  1.353  knakahar 			    i, error);
   6018  1.353  knakahar 			goto fail;
   6019  1.353  knakahar 		}
   6020  1.353  knakahar 	}
   6021  1.353  knakahar 
   6022  1.353  knakahar 	return 0;
   6023  1.353  knakahar 
   6024  1.353  knakahar  fail:
   6025  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6026  1.356  knakahar 		if (txq->txq_soft[i].txs_dmamap != NULL)
   6027  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6028  1.356  knakahar 			    txq->txq_soft[i].txs_dmamap);
   6029  1.353  knakahar 	}
   6030  1.353  knakahar 	return error;
   6031  1.353  knakahar }
   6032  1.353  knakahar 
   6033  1.353  knakahar static void
   6034  1.362  knakahar wm_free_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
   6035  1.353  knakahar {
   6036  1.353  knakahar 	int i;
   6037  1.353  knakahar 
   6038  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6039  1.356  knakahar 		if (txq->txq_soft[i].txs_dmamap != NULL)
   6040  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6041  1.356  knakahar 			    txq->txq_soft[i].txs_dmamap);
   6042  1.353  knakahar 	}
   6043  1.353  knakahar }
   6044  1.353  knakahar 
   6045  1.353  knakahar static int
   6046  1.362  knakahar wm_alloc_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6047  1.353  knakahar {
   6048  1.353  knakahar 	int i, error;
   6049  1.353  knakahar 
   6050  1.353  knakahar 	/* Create the receive buffer DMA maps. */
   6051  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6052  1.353  knakahar 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
   6053  1.353  knakahar 			    MCLBYTES, 0, 0,
   6054  1.356  knakahar 			    &rxq->rxq_soft[i].rxs_dmamap)) != 0) {
   6055  1.353  knakahar 			aprint_error_dev(sc->sc_dev,
   6056  1.353  knakahar 			    "unable to create Rx DMA map %d error = %d\n",
   6057  1.353  knakahar 			    i, error);
   6058  1.353  knakahar 			goto fail;
   6059  1.353  knakahar 		}
   6060  1.356  knakahar 		rxq->rxq_soft[i].rxs_mbuf = NULL;
   6061  1.353  knakahar 	}
   6062  1.353  knakahar 
   6063  1.353  knakahar 	return 0;
   6064  1.353  knakahar 
   6065  1.353  knakahar  fail:
   6066  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6067  1.356  knakahar 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
   6068  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6069  1.356  knakahar 			    rxq->rxq_soft[i].rxs_dmamap);
   6070  1.353  knakahar 	}
   6071  1.353  knakahar 	return error;
   6072  1.353  knakahar }
   6073  1.353  knakahar 
   6074  1.353  knakahar static void
   6075  1.362  knakahar wm_free_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6076  1.353  knakahar {
   6077  1.353  knakahar 	int i;
   6078  1.353  knakahar 
   6079  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6080  1.356  knakahar 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
   6081  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6082  1.356  knakahar 			    rxq->rxq_soft[i].rxs_dmamap);
   6083  1.353  knakahar 	}
   6084  1.353  knakahar }
   6085  1.353  knakahar 
   6086  1.353  knakahar /*
   6087  1.353  knakahar  * wm_alloc_quques:
   6088  1.353  knakahar  *	Allocate {tx,rx}descs and {tx,rx} buffers
   6089  1.353  knakahar  */
   6090  1.353  knakahar static int
   6091  1.353  knakahar wm_alloc_txrx_queues(struct wm_softc *sc)
   6092  1.353  knakahar {
   6093  1.364  knakahar 	int i, error, tx_done, rx_done;
   6094  1.353  knakahar 
   6095  1.405  knakahar 	sc->sc_queue = kmem_zalloc(sizeof(struct wm_queue) * sc->sc_nqueues,
   6096  1.356  knakahar 	    KM_SLEEP);
   6097  1.405  knakahar 	if (sc->sc_queue == NULL) {
   6098  1.405  knakahar 		aprint_error_dev(sc->sc_dev,"unable to allocate wm_queue\n");
   6099  1.356  knakahar 		error = ENOMEM;
   6100  1.356  knakahar 		goto fail_0;
   6101  1.356  knakahar 	}
   6102  1.364  knakahar 
   6103  1.405  knakahar 	/*
   6104  1.405  knakahar 	 * For transmission
   6105  1.405  knakahar 	 */
   6106  1.364  knakahar 	error = 0;
   6107  1.364  knakahar 	tx_done = 0;
   6108  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6109  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6110  1.417  knakahar 		int j;
   6111  1.417  knakahar 		const char *xname;
   6112  1.417  knakahar #endif
   6113  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6114  1.364  knakahar 		txq->txq_sc = sc;
   6115  1.362  knakahar 		txq->txq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   6116  1.408  knakahar 
   6117  1.362  knakahar 		error = wm_alloc_tx_descs(sc, txq);
   6118  1.364  knakahar 		if (error)
   6119  1.364  knakahar 			break;
   6120  1.364  knakahar 		error = wm_alloc_tx_buffer(sc, txq);
   6121  1.364  knakahar 		if (error) {
   6122  1.364  knakahar 			wm_free_tx_descs(sc, txq);
   6123  1.364  knakahar 			break;
   6124  1.364  knakahar 		}
   6125  1.403  knakahar 		txq->txq_interq = pcq_create(WM_TXINTERQSIZE, KM_SLEEP);
   6126  1.403  knakahar 		if (txq->txq_interq == NULL) {
   6127  1.403  knakahar 			wm_free_tx_descs(sc, txq);
   6128  1.403  knakahar 			wm_free_tx_buffer(sc, txq);
   6129  1.403  knakahar 			error = ENOMEM;
   6130  1.403  knakahar 			break;
   6131  1.403  knakahar 		}
   6132  1.417  knakahar 
   6133  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6134  1.417  knakahar 		xname = device_xname(sc->sc_dev);
   6135  1.417  knakahar 
   6136  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txsstall, txq, i, xname);
   6137  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txdstall, txq, i, xname);
   6138  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txfifo_stall, txq, i, xname);
   6139  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(txq, txdw, txq, i, xname);
   6140  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(txq, txqe, txq, i, xname);
   6141  1.417  knakahar 
   6142  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txipsum, txq, i, xname);
   6143  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtusum, txq, i, xname);
   6144  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtusum6, txq, i, xname);
   6145  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtso, txq, i, xname);
   6146  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtso6, txq, i, xname);
   6147  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtsopain, txq, i, xname);
   6148  1.417  knakahar 
   6149  1.417  knakahar 		for (j = 0; j < WM_NTXSEGS; j++) {
   6150  1.417  knakahar 			snprintf(txq->txq_txseg_evcnt_names[j],
   6151  1.417  knakahar 			    sizeof(txq->txq_txseg_evcnt_names[j]), "txq%02dtxseg%d", i, j);
   6152  1.417  knakahar 			evcnt_attach_dynamic(&txq->txq_ev_txseg[j], EVCNT_TYPE_MISC,
   6153  1.417  knakahar 			    NULL, xname, txq->txq_txseg_evcnt_names[j]);
   6154  1.417  knakahar 		}
   6155  1.417  knakahar 
   6156  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txdrop, txq, i, xname);
   6157  1.417  knakahar 
   6158  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, tu, txq, i, xname);
   6159  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
   6160  1.417  knakahar 
   6161  1.364  knakahar 		tx_done++;
   6162  1.364  knakahar 	}
   6163  1.353  knakahar 	if (error)
   6164  1.356  knakahar 		goto fail_1;
   6165  1.353  knakahar 
   6166  1.354  knakahar 	/*
   6167  1.354  knakahar 	 * For recieve
   6168  1.354  knakahar 	 */
   6169  1.364  knakahar 	error = 0;
   6170  1.364  knakahar 	rx_done = 0;
   6171  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6172  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6173  1.417  knakahar 		const char *xname;
   6174  1.417  knakahar #endif
   6175  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6176  1.364  knakahar 		rxq->rxq_sc = sc;
   6177  1.362  knakahar 		rxq->rxq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   6178  1.414  knakahar 
   6179  1.364  knakahar 		error = wm_alloc_rx_descs(sc, rxq);
   6180  1.364  knakahar 		if (error)
   6181  1.364  knakahar 			break;
   6182  1.356  knakahar 
   6183  1.364  knakahar 		error = wm_alloc_rx_buffer(sc, rxq);
   6184  1.364  knakahar 		if (error) {
   6185  1.364  knakahar 			wm_free_rx_descs(sc, rxq);
   6186  1.364  knakahar 			break;
   6187  1.364  knakahar 		}
   6188  1.354  knakahar 
   6189  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6190  1.417  knakahar 		xname = device_xname(sc->sc_dev);
   6191  1.417  knakahar 
   6192  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxintr, rxq, i, xname);
   6193  1.417  knakahar 
   6194  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxipsum, rxq, i, xname);
   6195  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxtusum, rxq, i, xname);
   6196  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
   6197  1.417  knakahar 
   6198  1.364  knakahar 		rx_done++;
   6199  1.364  knakahar 	}
   6200  1.353  knakahar 	if (error)
   6201  1.364  knakahar 		goto fail_2;
   6202  1.353  knakahar 
   6203  1.353  knakahar 	return 0;
   6204  1.353  knakahar 
   6205  1.356  knakahar  fail_2:
   6206  1.364  knakahar 	for (i = 0; i < rx_done; i++) {
   6207  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6208  1.364  knakahar 		wm_free_rx_buffer(sc, rxq);
   6209  1.364  knakahar 		wm_free_rx_descs(sc, rxq);
   6210  1.364  knakahar 		if (rxq->rxq_lock)
   6211  1.364  knakahar 			mutex_obj_free(rxq->rxq_lock);
   6212  1.364  knakahar 	}
   6213  1.356  knakahar  fail_1:
   6214  1.364  knakahar 	for (i = 0; i < tx_done; i++) {
   6215  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6216  1.403  knakahar 		pcq_destroy(txq->txq_interq);
   6217  1.364  knakahar 		wm_free_tx_buffer(sc, txq);
   6218  1.364  knakahar 		wm_free_tx_descs(sc, txq);
   6219  1.364  knakahar 		if (txq->txq_lock)
   6220  1.364  knakahar 			mutex_obj_free(txq->txq_lock);
   6221  1.364  knakahar 	}
   6222  1.405  knakahar 
   6223  1.405  knakahar 	kmem_free(sc->sc_queue,
   6224  1.405  knakahar 	    sizeof(struct wm_queue) * sc->sc_nqueues);
   6225  1.356  knakahar  fail_0:
   6226  1.353  knakahar 	return error;
   6227  1.353  knakahar }
   6228  1.353  knakahar 
   6229  1.353  knakahar /*
   6230  1.353  knakahar  * wm_free_quques:
   6231  1.353  knakahar  *	Free {tx,rx}descs and {tx,rx} buffers
   6232  1.353  knakahar  */
   6233  1.353  knakahar static void
   6234  1.353  knakahar wm_free_txrx_queues(struct wm_softc *sc)
   6235  1.353  knakahar {
   6236  1.364  knakahar 	int i;
   6237  1.362  knakahar 
   6238  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6239  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6240  1.477  knakahar 
   6241  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   6242  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxintr, rxq, i);
   6243  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxipsum, rxq, i);
   6244  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxtusum, rxq, i);
   6245  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   6246  1.477  knakahar 
   6247  1.364  knakahar 		wm_free_rx_buffer(sc, rxq);
   6248  1.364  knakahar 		wm_free_rx_descs(sc, rxq);
   6249  1.364  knakahar 		if (rxq->rxq_lock)
   6250  1.364  knakahar 			mutex_obj_free(rxq->rxq_lock);
   6251  1.364  knakahar 	}
   6252  1.364  knakahar 
   6253  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6254  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6255  1.469  knakahar 		struct mbuf *m;
   6256  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   6257  1.477  knakahar 		int j;
   6258  1.477  knakahar 
   6259  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txsstall, txq, i);
   6260  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdstall, txq, i);
   6261  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txfifo_stall, txq, i);
   6262  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdw, txq, i);
   6263  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txqe, txq, i);
   6264  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txipsum, txq, i);
   6265  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtusum, txq, i);
   6266  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtusum6, txq, i);
   6267  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtso, txq, i);
   6268  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtso6, txq, i);
   6269  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtsopain, txq, i);
   6270  1.477  knakahar 
   6271  1.477  knakahar 		for (j = 0; j < WM_NTXSEGS; j++)
   6272  1.477  knakahar 			evcnt_detach(&txq->txq_ev_txseg[j]);
   6273  1.477  knakahar 
   6274  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdrop, txq, i);
   6275  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, tu, txq, i);
   6276  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   6277  1.469  knakahar 
   6278  1.469  knakahar 		/* drain txq_interq */
   6279  1.469  knakahar 		while ((m = pcq_get(txq->txq_interq)) != NULL)
   6280  1.469  knakahar 			m_freem(m);
   6281  1.469  knakahar 		pcq_destroy(txq->txq_interq);
   6282  1.469  knakahar 
   6283  1.364  knakahar 		wm_free_tx_buffer(sc, txq);
   6284  1.364  knakahar 		wm_free_tx_descs(sc, txq);
   6285  1.364  knakahar 		if (txq->txq_lock)
   6286  1.364  knakahar 			mutex_obj_free(txq->txq_lock);
   6287  1.364  knakahar 	}
   6288  1.405  knakahar 
   6289  1.405  knakahar 	kmem_free(sc->sc_queue, sizeof(struct wm_queue) * sc->sc_nqueues);
   6290  1.353  knakahar }
   6291  1.353  knakahar 
   6292  1.355  knakahar static void
   6293  1.362  knakahar wm_init_tx_descs(struct wm_softc *sc __unused, struct wm_txqueue *txq)
   6294  1.355  knakahar {
   6295  1.355  knakahar 
   6296  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6297  1.355  knakahar 
   6298  1.355  knakahar 	/* Initialize the transmit descriptor ring. */
   6299  1.398  knakahar 	memset(txq->txq_descs, 0, WM_TXDESCS_SIZE(txq));
   6300  1.362  knakahar 	wm_cdtxsync(txq, 0, WM_NTXDESC(txq),
   6301  1.388   msaitoh 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   6302  1.356  knakahar 	txq->txq_free = WM_NTXDESC(txq);
   6303  1.356  knakahar 	txq->txq_next = 0;
   6304  1.358  knakahar }
   6305  1.358  knakahar 
   6306  1.358  knakahar static void
   6307  1.405  knakahar wm_init_tx_regs(struct wm_softc *sc, struct wm_queue *wmq,
   6308  1.405  knakahar     struct wm_txqueue *txq)
   6309  1.358  knakahar {
   6310  1.358  knakahar 
   6311  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   6312  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   6313  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6314  1.355  knakahar 
   6315  1.355  knakahar 	if (sc->sc_type < WM_T_82543) {
   6316  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(txq, 0));
   6317  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(txq, 0));
   6318  1.398  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCS_SIZE(txq));
   6319  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
   6320  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
   6321  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
   6322  1.355  knakahar 	} else {
   6323  1.405  knakahar 		int qid = wmq->wmq_id;
   6324  1.364  knakahar 
   6325  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDBAH(qid), WM_CDTXADDR_HI(txq, 0));
   6326  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDBAL(qid), WM_CDTXADDR_LO(txq, 0));
   6327  1.398  knakahar 		CSR_WRITE(sc, WMREG_TDLEN(qid), WM_TXDESCS_SIZE(txq));
   6328  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDH(qid), 0);
   6329  1.355  knakahar 
   6330  1.355  knakahar 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   6331  1.355  knakahar 			/*
   6332  1.355  knakahar 			 * Don't write TDT before TCTL.EN is set.
   6333  1.355  knakahar 			 * See the document.
   6334  1.355  knakahar 			 */
   6335  1.364  knakahar 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_QUEUE_ENABLE
   6336  1.355  knakahar 			    | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0)
   6337  1.355  knakahar 			    | TXDCTL_WTHRESH(0));
   6338  1.355  knakahar 		else {
   6339  1.490  knakahar 			/* XXX should update with AIM? */
   6340  1.490  knakahar 			CSR_WRITE(sc, WMREG_TIDV, wmq->wmq_itr / 4);
   6341  1.355  knakahar 			if (sc->sc_type >= WM_T_82540) {
   6342  1.355  knakahar 				/* should be same */
   6343  1.490  knakahar 				CSR_WRITE(sc, WMREG_TADV, wmq->wmq_itr / 4);
   6344  1.355  knakahar 			}
   6345  1.355  knakahar 
   6346  1.364  knakahar 			CSR_WRITE(sc, WMREG_TDT(qid), 0);
   6347  1.364  knakahar 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_PTHRESH(0) |
   6348  1.355  knakahar 			    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
   6349  1.355  knakahar 		}
   6350  1.355  knakahar 	}
   6351  1.355  knakahar }
   6352  1.355  knakahar 
   6353  1.355  knakahar static void
   6354  1.362  knakahar wm_init_tx_buffer(struct wm_softc *sc __unused, struct wm_txqueue *txq)
   6355  1.355  knakahar {
   6356  1.355  knakahar 	int i;
   6357  1.355  knakahar 
   6358  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6359  1.355  knakahar 
   6360  1.355  knakahar 	/* Initialize the transmit job descriptors. */
   6361  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++)
   6362  1.356  knakahar 		txq->txq_soft[i].txs_mbuf = NULL;
   6363  1.356  knakahar 	txq->txq_sfree = WM_TXQUEUELEN(txq);
   6364  1.356  knakahar 	txq->txq_snext = 0;
   6365  1.356  knakahar 	txq->txq_sdirty = 0;
   6366  1.355  knakahar }
   6367  1.355  knakahar 
   6368  1.355  knakahar static void
   6369  1.405  knakahar wm_init_tx_queue(struct wm_softc *sc, struct wm_queue *wmq,
   6370  1.405  knakahar     struct wm_txqueue *txq)
   6371  1.355  knakahar {
   6372  1.355  knakahar 
   6373  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6374  1.355  knakahar 
   6375  1.355  knakahar 	/*
   6376  1.355  knakahar 	 * Set up some register offsets that are different between
   6377  1.355  knakahar 	 * the i82542 and the i82543 and later chips.
   6378  1.355  knakahar 	 */
   6379  1.388   msaitoh 	if (sc->sc_type < WM_T_82543)
   6380  1.356  knakahar 		txq->txq_tdt_reg = WMREG_OLD_TDT;
   6381  1.388   msaitoh 	else
   6382  1.405  knakahar 		txq->txq_tdt_reg = WMREG_TDT(wmq->wmq_id);
   6383  1.355  knakahar 
   6384  1.362  knakahar 	wm_init_tx_descs(sc, txq);
   6385  1.405  knakahar 	wm_init_tx_regs(sc, wmq, txq);
   6386  1.362  knakahar 	wm_init_tx_buffer(sc, txq);
   6387  1.355  knakahar }
   6388  1.355  knakahar 
   6389  1.355  knakahar static void
   6390  1.405  knakahar wm_init_rx_regs(struct wm_softc *sc, struct wm_queue *wmq,
   6391  1.405  knakahar     struct wm_rxqueue *rxq)
   6392  1.355  knakahar {
   6393  1.355  knakahar 
   6394  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6395  1.355  knakahar 
   6396  1.355  knakahar 	/*
   6397  1.355  knakahar 	 * Initialize the receive descriptor and receive job
   6398  1.355  knakahar 	 * descriptor rings.
   6399  1.355  knakahar 	 */
   6400  1.355  knakahar 	if (sc->sc_type < WM_T_82543) {
   6401  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(rxq, 0));
   6402  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(rxq, 0));
   6403  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDLEN0,
   6404  1.466  knakahar 		    rxq->rxq_descsize * rxq->rxq_ndesc);
   6405  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
   6406  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
   6407  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
   6408  1.355  knakahar 
   6409  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
   6410  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
   6411  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
   6412  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
   6413  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
   6414  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
   6415  1.355  knakahar 	} else {
   6416  1.405  knakahar 		int qid = wmq->wmq_id;
   6417  1.364  knakahar 
   6418  1.364  knakahar 		CSR_WRITE(sc, WMREG_RDBAH(qid), WM_CDRXADDR_HI(rxq, 0));
   6419  1.364  knakahar 		CSR_WRITE(sc, WMREG_RDBAL(qid), WM_CDRXADDR_LO(rxq, 0));
   6420  1.466  knakahar 		CSR_WRITE(sc, WMREG_RDLEN(qid), rxq->rxq_descsize * rxq->rxq_ndesc);
   6421  1.355  knakahar 
   6422  1.355  knakahar 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   6423  1.355  knakahar 			if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
   6424  1.478  knakahar 				panic("%s: MCLBYTES %d unsupported for 82575 or higher\n", __func__, MCLBYTES);
   6425  1.466  knakahar 
   6426  1.466  knakahar 			/* Currently, support SRRCTL_DESCTYPE_ADV_ONEBUF only. */
   6427  1.466  knakahar 			CSR_WRITE(sc, WMREG_SRRCTL(qid), SRRCTL_DESCTYPE_ADV_ONEBUF
   6428  1.355  knakahar 			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
   6429  1.364  knakahar 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_QUEUE_ENABLE
   6430  1.355  knakahar 			    | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
   6431  1.355  knakahar 			    | RXDCTL_WTHRESH(1));
   6432  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
   6433  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
   6434  1.355  knakahar 		} else {
   6435  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
   6436  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
   6437  1.490  knakahar 			/* XXX should update with AIM? */
   6438  1.490  knakahar 			CSR_WRITE(sc, WMREG_RDTR, (wmq->wmq_itr / 4) | RDTR_FPD);
   6439  1.368  knakahar 			/* MUST be same */
   6440  1.490  knakahar 			CSR_WRITE(sc, WMREG_RADV, wmq->wmq_itr / 4);
   6441  1.364  knakahar 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_PTHRESH(0) |
   6442  1.358  knakahar 			    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
   6443  1.355  knakahar 		}
   6444  1.355  knakahar 	}
   6445  1.355  knakahar }
   6446  1.355  knakahar 
   6447  1.355  knakahar static int
   6448  1.362  knakahar wm_init_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6449  1.355  knakahar {
   6450  1.355  knakahar 	struct wm_rxsoft *rxs;
   6451  1.355  knakahar 	int error, i;
   6452  1.355  knakahar 
   6453  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6454  1.355  knakahar 
   6455  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6456  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   6457  1.355  knakahar 		if (rxs->rxs_mbuf == NULL) {
   6458  1.362  knakahar 			if ((error = wm_add_rxbuf(rxq, i)) != 0) {
   6459  1.355  knakahar 				log(LOG_ERR, "%s: unable to allocate or map "
   6460  1.355  knakahar 				    "rx buffer %d, error = %d\n",
   6461  1.355  knakahar 				    device_xname(sc->sc_dev), i, error);
   6462  1.355  knakahar 				/*
   6463  1.355  knakahar 				 * XXX Should attempt to run with fewer receive
   6464  1.355  knakahar 				 * XXX buffers instead of just failing.
   6465  1.355  knakahar 				 */
   6466  1.362  knakahar 				wm_rxdrain(rxq);
   6467  1.355  knakahar 				return ENOMEM;
   6468  1.355  knakahar 			}
   6469  1.355  knakahar 		} else {
   6470  1.355  knakahar 			if ((sc->sc_flags & WM_F_NEWQUEUE) == 0)
   6471  1.362  knakahar 				wm_init_rxdesc(rxq, i);
   6472  1.355  knakahar 			/*
   6473  1.355  knakahar 			 * For 82575 and newer device, the RX descriptors
   6474  1.355  knakahar 			 * must be initialized after the setting of RCTL.EN in
   6475  1.355  knakahar 			 * wm_set_filter()
   6476  1.355  knakahar 			 */
   6477  1.355  knakahar 		}
   6478  1.355  knakahar 	}
   6479  1.356  knakahar 	rxq->rxq_ptr = 0;
   6480  1.356  knakahar 	rxq->rxq_discard = 0;
   6481  1.356  knakahar 	WM_RXCHAIN_RESET(rxq);
   6482  1.355  knakahar 
   6483  1.355  knakahar 	return 0;
   6484  1.355  knakahar }
   6485  1.355  knakahar 
   6486  1.355  knakahar static int
   6487  1.405  knakahar wm_init_rx_queue(struct wm_softc *sc, struct wm_queue *wmq,
   6488  1.405  knakahar     struct wm_rxqueue *rxq)
   6489  1.355  knakahar {
   6490  1.355  knakahar 
   6491  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6492  1.355  knakahar 
   6493  1.355  knakahar 	/*
   6494  1.355  knakahar 	 * Set up some register offsets that are different between
   6495  1.355  knakahar 	 * the i82542 and the i82543 and later chips.
   6496  1.355  knakahar 	 */
   6497  1.388   msaitoh 	if (sc->sc_type < WM_T_82543)
   6498  1.356  knakahar 		rxq->rxq_rdt_reg = WMREG_OLD_RDT0;
   6499  1.388   msaitoh 	else
   6500  1.405  knakahar 		rxq->rxq_rdt_reg = WMREG_RDT(wmq->wmq_id);
   6501  1.355  knakahar 
   6502  1.405  knakahar 	wm_init_rx_regs(sc, wmq, rxq);
   6503  1.362  knakahar 	return wm_init_rx_buffer(sc, rxq);
   6504  1.355  knakahar }
   6505  1.355  knakahar 
   6506  1.355  knakahar /*
   6507  1.355  knakahar  * wm_init_quques:
   6508  1.355  knakahar  *	Initialize {tx,rx}descs and {tx,rx} buffers
   6509  1.355  knakahar  */
   6510  1.355  knakahar static int
   6511  1.355  knakahar wm_init_txrx_queues(struct wm_softc *sc)
   6512  1.355  knakahar {
   6513  1.406  knakahar 	int i, error = 0;
   6514  1.355  knakahar 
   6515  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   6516  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   6517  1.420   msaitoh 
   6518  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6519  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[i];
   6520  1.405  knakahar 		struct wm_txqueue *txq = &wmq->wmq_txq;
   6521  1.405  knakahar 		struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   6522  1.405  knakahar 
   6523  1.495  knakahar 		/*
   6524  1.495  knakahar 		 * TODO
   6525  1.495  knakahar 		 * Currently, use constant variable instead of AIM.
   6526  1.495  knakahar 		 * Furthermore, the interrupt interval of multiqueue which use
   6527  1.495  knakahar 		 * polling mode is less than default value.
   6528  1.495  knakahar 		 * More tuning and AIM are required.
   6529  1.495  knakahar 		 */
   6530  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   6531  1.495  knakahar 			wmq->wmq_itr = 50;
   6532  1.495  knakahar 		else
   6533  1.495  knakahar 			wmq->wmq_itr = sc->sc_itr_init;
   6534  1.495  knakahar 		wmq->wmq_set_itr = true;
   6535  1.490  knakahar 
   6536  1.413     skrll 		mutex_enter(txq->txq_lock);
   6537  1.405  knakahar 		wm_init_tx_queue(sc, wmq, txq);
   6538  1.413     skrll 		mutex_exit(txq->txq_lock);
   6539  1.355  knakahar 
   6540  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   6541  1.405  knakahar 		error = wm_init_rx_queue(sc, wmq, rxq);
   6542  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   6543  1.364  knakahar 		if (error)
   6544  1.364  knakahar 			break;
   6545  1.364  knakahar 	}
   6546  1.355  knakahar 
   6547  1.355  knakahar 	return error;
   6548  1.355  knakahar }
   6549  1.355  knakahar 
   6550    1.1   thorpej /*
   6551  1.371   msaitoh  * wm_tx_offload:
   6552  1.371   msaitoh  *
   6553  1.371   msaitoh  *	Set up TCP/IP checksumming parameters for the
   6554  1.371   msaitoh  *	specified packet.
   6555  1.371   msaitoh  */
   6556  1.371   msaitoh static int
   6557  1.498  knakahar wm_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
   6558  1.498  knakahar     struct wm_txsoft *txs, uint32_t *cmdp, uint8_t *fieldsp)
   6559  1.371   msaitoh {
   6560  1.371   msaitoh 	struct mbuf *m0 = txs->txs_mbuf;
   6561  1.371   msaitoh 	struct livengood_tcpip_ctxdesc *t;
   6562  1.371   msaitoh 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
   6563  1.371   msaitoh 	uint32_t ipcse;
   6564  1.371   msaitoh 	struct ether_header *eh;
   6565  1.371   msaitoh 	int offset, iphl;
   6566  1.371   msaitoh 	uint8_t fields;
   6567  1.371   msaitoh 
   6568  1.371   msaitoh 	/*
   6569  1.371   msaitoh 	 * XXX It would be nice if the mbuf pkthdr had offset
   6570  1.371   msaitoh 	 * fields for the protocol headers.
   6571  1.371   msaitoh 	 */
   6572  1.371   msaitoh 
   6573  1.371   msaitoh 	eh = mtod(m0, struct ether_header *);
   6574  1.371   msaitoh 	switch (htons(eh->ether_type)) {
   6575  1.371   msaitoh 	case ETHERTYPE_IP:
   6576  1.371   msaitoh 	case ETHERTYPE_IPV6:
   6577  1.371   msaitoh 		offset = ETHER_HDR_LEN;
   6578  1.371   msaitoh 		break;
   6579  1.371   msaitoh 
   6580  1.371   msaitoh 	case ETHERTYPE_VLAN:
   6581  1.371   msaitoh 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   6582  1.371   msaitoh 		break;
   6583  1.371   msaitoh 
   6584  1.371   msaitoh 	default:
   6585  1.371   msaitoh 		/*
   6586  1.371   msaitoh 		 * Don't support this protocol or encapsulation.
   6587  1.371   msaitoh 		 */
   6588  1.371   msaitoh 		*fieldsp = 0;
   6589  1.371   msaitoh 		*cmdp = 0;
   6590  1.371   msaitoh 		return 0;
   6591  1.371   msaitoh 	}
   6592  1.371   msaitoh 
   6593  1.371   msaitoh 	if ((m0->m_pkthdr.csum_flags &
   6594  1.499  knakahar 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
   6595  1.371   msaitoh 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   6596  1.371   msaitoh 	} else {
   6597  1.371   msaitoh 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
   6598  1.371   msaitoh 	}
   6599  1.371   msaitoh 	ipcse = offset + iphl - 1;
   6600  1.371   msaitoh 
   6601  1.371   msaitoh 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
   6602  1.371   msaitoh 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
   6603  1.371   msaitoh 	seg = 0;
   6604  1.371   msaitoh 	fields = 0;
   6605  1.371   msaitoh 
   6606  1.371   msaitoh 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
   6607  1.371   msaitoh 		int hlen = offset + iphl;
   6608  1.371   msaitoh 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   6609  1.371   msaitoh 
   6610  1.371   msaitoh 		if (__predict_false(m0->m_len <
   6611  1.371   msaitoh 				    (hlen + sizeof(struct tcphdr)))) {
   6612  1.371   msaitoh 			/*
   6613  1.371   msaitoh 			 * TCP/IP headers are not in the first mbuf; we need
   6614  1.371   msaitoh 			 * to do this the slow and painful way.  Let's just
   6615  1.371   msaitoh 			 * hope this doesn't happen very often.
   6616  1.371   msaitoh 			 */
   6617  1.371   msaitoh 			struct tcphdr th;
   6618  1.371   msaitoh 
   6619  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtsopain);
   6620  1.371   msaitoh 
   6621  1.371   msaitoh 			m_copydata(m0, hlen, sizeof(th), &th);
   6622  1.371   msaitoh 			if (v4) {
   6623  1.371   msaitoh 				struct ip ip;
   6624  1.371   msaitoh 
   6625  1.371   msaitoh 				m_copydata(m0, offset, sizeof(ip), &ip);
   6626  1.371   msaitoh 				ip.ip_len = 0;
   6627  1.371   msaitoh 				m_copyback(m0,
   6628  1.371   msaitoh 				    offset + offsetof(struct ip, ip_len),
   6629  1.371   msaitoh 				    sizeof(ip.ip_len), &ip.ip_len);
   6630  1.371   msaitoh 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   6631  1.371   msaitoh 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   6632  1.371   msaitoh 			} else {
   6633  1.371   msaitoh 				struct ip6_hdr ip6;
   6634  1.371   msaitoh 
   6635  1.371   msaitoh 				m_copydata(m0, offset, sizeof(ip6), &ip6);
   6636  1.371   msaitoh 				ip6.ip6_plen = 0;
   6637  1.371   msaitoh 				m_copyback(m0,
   6638  1.371   msaitoh 				    offset + offsetof(struct ip6_hdr, ip6_plen),
   6639  1.371   msaitoh 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
   6640  1.371   msaitoh 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
   6641  1.371   msaitoh 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
   6642  1.371   msaitoh 			}
   6643  1.371   msaitoh 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   6644  1.371   msaitoh 			    sizeof(th.th_sum), &th.th_sum);
   6645  1.371   msaitoh 
   6646  1.371   msaitoh 			hlen += th.th_off << 2;
   6647  1.371   msaitoh 		} else {
   6648  1.371   msaitoh 			/*
   6649  1.371   msaitoh 			 * TCP/IP headers are in the first mbuf; we can do
   6650  1.371   msaitoh 			 * this the easy way.
   6651  1.371   msaitoh 			 */
   6652  1.371   msaitoh 			struct tcphdr *th;
   6653  1.371   msaitoh 
   6654  1.371   msaitoh 			if (v4) {
   6655  1.371   msaitoh 				struct ip *ip =
   6656  1.371   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   6657  1.371   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   6658  1.371   msaitoh 
   6659  1.371   msaitoh 				ip->ip_len = 0;
   6660  1.371   msaitoh 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   6661  1.371   msaitoh 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   6662  1.371   msaitoh 			} else {
   6663  1.371   msaitoh 				struct ip6_hdr *ip6 =
   6664  1.371   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   6665  1.371   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   6666  1.371   msaitoh 
   6667  1.371   msaitoh 				ip6->ip6_plen = 0;
   6668  1.371   msaitoh 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
   6669  1.371   msaitoh 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
   6670  1.371   msaitoh 			}
   6671  1.371   msaitoh 			hlen += th->th_off << 2;
   6672  1.371   msaitoh 		}
   6673  1.371   msaitoh 
   6674  1.371   msaitoh 		if (v4) {
   6675  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso);
   6676  1.371   msaitoh 			cmdlen |= WTX_TCPIP_CMD_IP;
   6677  1.371   msaitoh 		} else {
   6678  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso6);
   6679  1.371   msaitoh 			ipcse = 0;
   6680  1.371   msaitoh 		}
   6681  1.371   msaitoh 		cmd |= WTX_TCPIP_CMD_TSE;
   6682  1.371   msaitoh 		cmdlen |= WTX_TCPIP_CMD_TSE |
   6683  1.371   msaitoh 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
   6684  1.371   msaitoh 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
   6685  1.371   msaitoh 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
   6686  1.371   msaitoh 	}
   6687  1.371   msaitoh 
   6688  1.371   msaitoh 	/*
   6689  1.371   msaitoh 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
   6690  1.371   msaitoh 	 * offload feature, if we load the context descriptor, we
   6691  1.371   msaitoh 	 * MUST provide valid values for IPCSS and TUCSS fields.
   6692  1.371   msaitoh 	 */
   6693  1.371   msaitoh 
   6694  1.371   msaitoh 	ipcs = WTX_TCPIP_IPCSS(offset) |
   6695  1.371   msaitoh 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
   6696  1.371   msaitoh 	    WTX_TCPIP_IPCSE(ipcse);
   6697  1.388   msaitoh 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4 | M_CSUM_TSOv4)) {
   6698  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txipsum);
   6699  1.371   msaitoh 		fields |= WTX_IXSM;
   6700  1.371   msaitoh 	}
   6701  1.371   msaitoh 
   6702  1.371   msaitoh 	offset += iphl;
   6703  1.371   msaitoh 
   6704  1.371   msaitoh 	if (m0->m_pkthdr.csum_flags &
   6705  1.388   msaitoh 	    (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TSOv4)) {
   6706  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum);
   6707  1.371   msaitoh 		fields |= WTX_TXSM;
   6708  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   6709  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset +
   6710  1.371   msaitoh 		    M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
   6711  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   6712  1.371   msaitoh 	} else if ((m0->m_pkthdr.csum_flags &
   6713  1.388   msaitoh 	    (M_CSUM_TCPv6 | M_CSUM_UDPv6 | M_CSUM_TSOv6)) != 0) {
   6714  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum6);
   6715  1.371   msaitoh 		fields |= WTX_TXSM;
   6716  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   6717  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset +
   6718  1.371   msaitoh 		    M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
   6719  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   6720  1.371   msaitoh 	} else {
   6721  1.371   msaitoh 		/* Just initialize it to a valid TCP context. */
   6722  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   6723  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
   6724  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   6725  1.371   msaitoh 	}
   6726  1.371   msaitoh 
   6727  1.500  knakahar 	/*
   6728  1.500  knakahar 	 * We don't have to write context descriptor for every packet
   6729  1.500  knakahar 	 * except for 82574. For 82574, we must write context descriptor
   6730  1.500  knakahar 	 * for every packet when we use two descriptor queues.
   6731  1.500  knakahar 	 * It would be overhead to write context descriptor for every packet,
   6732  1.500  knakahar 	 * however it does not cause problems.
   6733  1.500  knakahar 	 */
   6734  1.371   msaitoh 	/* Fill in the context descriptor. */
   6735  1.371   msaitoh 	t = (struct livengood_tcpip_ctxdesc *)
   6736  1.371   msaitoh 	    &txq->txq_descs[txq->txq_next];
   6737  1.371   msaitoh 	t->tcpip_ipcs = htole32(ipcs);
   6738  1.371   msaitoh 	t->tcpip_tucs = htole32(tucs);
   6739  1.371   msaitoh 	t->tcpip_cmdlen = htole32(cmdlen);
   6740  1.371   msaitoh 	t->tcpip_seg = htole32(seg);
   6741  1.371   msaitoh 	wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE);
   6742  1.371   msaitoh 
   6743  1.371   msaitoh 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   6744  1.371   msaitoh 	txs->txs_ndesc++;
   6745  1.371   msaitoh 
   6746  1.371   msaitoh 	*cmdp = cmd;
   6747  1.371   msaitoh 	*fieldsp = fields;
   6748  1.371   msaitoh 
   6749  1.371   msaitoh 	return 0;
   6750  1.371   msaitoh }
   6751  1.371   msaitoh 
   6752  1.454  knakahar static inline int
   6753  1.454  knakahar wm_select_txqueue(struct ifnet *ifp, struct mbuf *m)
   6754  1.454  knakahar {
   6755  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   6756  1.454  knakahar 	u_int cpuid = cpu_index(curcpu());
   6757  1.454  knakahar 
   6758  1.454  knakahar 	/*
   6759  1.454  knakahar 	 * Currently, simple distribute strategy.
   6760  1.454  knakahar 	 * TODO:
   6761  1.461  knakahar 	 * distribute by flowid(RSS has value).
   6762  1.454  knakahar 	 */
   6763  1.488  knakahar         return (cpuid + ncpu - sc->sc_affinity_offset) % sc->sc_nqueues;
   6764  1.454  knakahar }
   6765  1.454  knakahar 
   6766  1.371   msaitoh /*
   6767  1.281   msaitoh  * wm_start:		[ifnet interface function]
   6768    1.1   thorpej  *
   6769  1.281   msaitoh  *	Start packet transmission on the interface.
   6770    1.1   thorpej  */
   6771   1.47   thorpej static void
   6772  1.281   msaitoh wm_start(struct ifnet *ifp)
   6773    1.1   thorpej {
   6774  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   6775  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   6776  1.281   msaitoh 
   6777  1.496  knakahar #ifdef WM_MPSAFE
   6778  1.415  knakahar 	KASSERT(ifp->if_extflags & IFEF_START_MPSAFE);
   6779  1.496  knakahar #endif
   6780  1.455  knakahar 	/*
   6781  1.455  knakahar 	 * ifp->if_obytes and ifp->if_omcasts are added in if_transmit()@if.c.
   6782  1.455  knakahar 	 */
   6783  1.455  knakahar 
   6784  1.413     skrll 	mutex_enter(txq->txq_lock);
   6785  1.429  knakahar 	if (!txq->txq_stopping)
   6786  1.281   msaitoh 		wm_start_locked(ifp);
   6787  1.413     skrll 	mutex_exit(txq->txq_lock);
   6788  1.281   msaitoh }
   6789    1.1   thorpej 
   6790  1.281   msaitoh static void
   6791  1.281   msaitoh wm_start_locked(struct ifnet *ifp)
   6792  1.281   msaitoh {
   6793  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   6794  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   6795  1.454  knakahar 
   6796  1.454  knakahar 	wm_send_common_locked(ifp, txq, false);
   6797  1.454  knakahar }
   6798  1.454  knakahar 
   6799  1.454  knakahar static int
   6800  1.454  knakahar wm_transmit(struct ifnet *ifp, struct mbuf *m)
   6801  1.454  knakahar {
   6802  1.454  knakahar 	int qid;
   6803  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   6804  1.454  knakahar 	struct wm_txqueue *txq;
   6805  1.454  knakahar 
   6806  1.454  knakahar 	qid = wm_select_txqueue(ifp, m);
   6807  1.454  knakahar 	txq = &sc->sc_queue[qid].wmq_txq;
   6808  1.454  knakahar 
   6809  1.454  knakahar 	if (__predict_false(!pcq_put(txq->txq_interq, m))) {
   6810  1.454  knakahar 		m_freem(m);
   6811  1.454  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   6812  1.454  knakahar 		return ENOBUFS;
   6813  1.454  knakahar 	}
   6814  1.454  knakahar 
   6815  1.455  knakahar 	/*
   6816  1.455  knakahar 	 * XXXX NOMPSAFE: ifp->if_data should be percpu.
   6817  1.455  knakahar 	 */
   6818  1.455  knakahar 	ifp->if_obytes += m->m_pkthdr.len;
   6819  1.455  knakahar 	if (m->m_flags & M_MCAST)
   6820  1.455  knakahar 		ifp->if_omcasts++;
   6821  1.455  knakahar 
   6822  1.454  knakahar 	if (mutex_tryenter(txq->txq_lock)) {
   6823  1.454  knakahar 		if (!txq->txq_stopping)
   6824  1.454  knakahar 			wm_transmit_locked(ifp, txq);
   6825  1.454  knakahar 		mutex_exit(txq->txq_lock);
   6826  1.454  knakahar 	}
   6827  1.454  knakahar 
   6828  1.454  knakahar 	return 0;
   6829  1.454  knakahar }
   6830  1.454  knakahar 
   6831  1.454  knakahar static void
   6832  1.454  knakahar wm_transmit_locked(struct ifnet *ifp, struct wm_txqueue *txq)
   6833  1.454  knakahar {
   6834  1.454  knakahar 
   6835  1.454  knakahar 	wm_send_common_locked(ifp, txq, true);
   6836  1.454  knakahar }
   6837  1.454  knakahar 
   6838  1.454  knakahar static void
   6839  1.454  knakahar wm_send_common_locked(struct ifnet *ifp, struct wm_txqueue *txq,
   6840  1.454  knakahar     bool is_transmit)
   6841  1.454  knakahar {
   6842  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   6843  1.281   msaitoh 	struct mbuf *m0;
   6844  1.281   msaitoh 	struct m_tag *mtag;
   6845  1.281   msaitoh 	struct wm_txsoft *txs;
   6846  1.281   msaitoh 	bus_dmamap_t dmamap;
   6847  1.281   msaitoh 	int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
   6848  1.281   msaitoh 	bus_addr_t curaddr;
   6849  1.281   msaitoh 	bus_size_t seglen, curlen;
   6850  1.281   msaitoh 	uint32_t cksumcmd;
   6851  1.281   msaitoh 	uint8_t cksumfields;
   6852    1.1   thorpej 
   6853  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6854    1.1   thorpej 
   6855  1.482  knakahar 	if ((ifp->if_flags & IFF_RUNNING) == 0)
   6856  1.482  knakahar 		return;
   6857  1.482  knakahar 	if ((ifp->if_flags & IFF_OACTIVE) != 0 && !is_transmit)
   6858  1.281   msaitoh 		return;
   6859  1.479  knakahar 	if ((txq->txq_flags & WM_TXQ_NO_SPACE) != 0)
   6860  1.479  knakahar 		return;
   6861    1.1   thorpej 
   6862  1.281   msaitoh 	/* Remember the previous number of free descriptors. */
   6863  1.356  knakahar 	ofree = txq->txq_free;
   6864    1.1   thorpej 
   6865  1.281   msaitoh 	/*
   6866  1.281   msaitoh 	 * Loop through the send queue, setting up transmit descriptors
   6867  1.281   msaitoh 	 * until we drain the queue, or use up all available transmit
   6868  1.281   msaitoh 	 * descriptors.
   6869  1.281   msaitoh 	 */
   6870  1.281   msaitoh 	for (;;) {
   6871  1.281   msaitoh 		m0 = NULL;
   6872    1.1   thorpej 
   6873  1.281   msaitoh 		/* Get a work queue entry. */
   6874  1.356  knakahar 		if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) {
   6875  1.403  knakahar 			wm_txeof(sc, txq);
   6876  1.356  knakahar 			if (txq->txq_sfree == 0) {
   6877  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   6878  1.281   msaitoh 				    ("%s: TX: no free job descriptors\n",
   6879  1.281   msaitoh 					device_xname(sc->sc_dev)));
   6880  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txsstall);
   6881  1.281   msaitoh 				break;
   6882    1.1   thorpej 			}
   6883    1.1   thorpej 		}
   6884    1.1   thorpej 
   6885  1.281   msaitoh 		/* Grab a packet off the queue. */
   6886  1.454  knakahar 		if (is_transmit)
   6887  1.454  knakahar 			m0 = pcq_get(txq->txq_interq);
   6888  1.454  knakahar 		else
   6889  1.454  knakahar 			IFQ_DEQUEUE(&ifp->if_snd, m0);
   6890  1.281   msaitoh 		if (m0 == NULL)
   6891  1.281   msaitoh 			break;
   6892  1.281   msaitoh 
   6893  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   6894  1.281   msaitoh 		    ("%s: TX: have packet to transmit: %p\n",
   6895  1.281   msaitoh 		    device_xname(sc->sc_dev), m0));
   6896  1.281   msaitoh 
   6897  1.356  knakahar 		txs = &txq->txq_soft[txq->txq_snext];
   6898  1.281   msaitoh 		dmamap = txs->txs_dmamap;
   6899    1.1   thorpej 
   6900  1.281   msaitoh 		use_tso = (m0->m_pkthdr.csum_flags &
   6901  1.281   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0;
   6902    1.1   thorpej 
   6903    1.1   thorpej 		/*
   6904  1.281   msaitoh 		 * So says the Linux driver:
   6905  1.281   msaitoh 		 * The controller does a simple calculation to make sure
   6906  1.281   msaitoh 		 * there is enough room in the FIFO before initiating the
   6907  1.281   msaitoh 		 * DMA for each buffer.  The calc is:
   6908  1.281   msaitoh 		 *	4 = ceil(buffer len / MSS)
   6909  1.281   msaitoh 		 * To make sure we don't overrun the FIFO, adjust the max
   6910  1.281   msaitoh 		 * buffer len if the MSS drops.
   6911  1.281   msaitoh 		 */
   6912  1.281   msaitoh 		dmamap->dm_maxsegsz =
   6913  1.281   msaitoh 		    (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
   6914  1.281   msaitoh 		    ? m0->m_pkthdr.segsz << 2
   6915  1.281   msaitoh 		    : WTX_MAX_LEN;
   6916  1.281   msaitoh 
   6917  1.281   msaitoh 		/*
   6918  1.281   msaitoh 		 * Load the DMA map.  If this fails, the packet either
   6919  1.281   msaitoh 		 * didn't fit in the allotted number of segments, or we
   6920  1.281   msaitoh 		 * were short on resources.  For the too-many-segments
   6921  1.281   msaitoh 		 * case, we simply report an error and drop the packet,
   6922  1.281   msaitoh 		 * since we can't sanely copy a jumbo packet to a single
   6923  1.281   msaitoh 		 * buffer.
   6924    1.1   thorpej 		 */
   6925  1.281   msaitoh 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   6926  1.388   msaitoh 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
   6927  1.281   msaitoh 		if (error) {
   6928  1.281   msaitoh 			if (error == EFBIG) {
   6929  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txdrop);
   6930  1.281   msaitoh 				log(LOG_ERR, "%s: Tx packet consumes too many "
   6931  1.281   msaitoh 				    "DMA segments, dropping...\n",
   6932  1.281   msaitoh 				    device_xname(sc->sc_dev));
   6933  1.281   msaitoh 				wm_dump_mbuf_chain(sc, m0);
   6934  1.281   msaitoh 				m_freem(m0);
   6935  1.281   msaitoh 				continue;
   6936  1.281   msaitoh 			}
   6937  1.281   msaitoh 			/*  Short on resources, just stop for now. */
   6938  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   6939  1.281   msaitoh 			    ("%s: TX: dmamap load failed: %d\n",
   6940  1.281   msaitoh 			    device_xname(sc->sc_dev), error));
   6941  1.281   msaitoh 			break;
   6942    1.1   thorpej 		}
   6943    1.1   thorpej 
   6944  1.281   msaitoh 		segs_needed = dmamap->dm_nsegs;
   6945  1.281   msaitoh 		if (use_tso) {
   6946  1.281   msaitoh 			/* For sentinel descriptor; see below. */
   6947  1.281   msaitoh 			segs_needed++;
   6948  1.281   msaitoh 		}
   6949    1.1   thorpej 
   6950    1.1   thorpej 		/*
   6951  1.281   msaitoh 		 * Ensure we have enough descriptors free to describe
   6952  1.281   msaitoh 		 * the packet.  Note, we always reserve one descriptor
   6953  1.281   msaitoh 		 * at the end of the ring due to the semantics of the
   6954  1.281   msaitoh 		 * TDT register, plus one more in the event we need
   6955  1.281   msaitoh 		 * to load offload context.
   6956    1.1   thorpej 		 */
   6957  1.356  knakahar 		if (segs_needed > txq->txq_free - 2) {
   6958  1.281   msaitoh 			/*
   6959  1.281   msaitoh 			 * Not enough free descriptors to transmit this
   6960  1.281   msaitoh 			 * packet.  We haven't committed anything yet,
   6961  1.281   msaitoh 			 * so just unload the DMA map, put the packet
   6962  1.281   msaitoh 			 * pack on the queue, and punt.  Notify the upper
   6963  1.281   msaitoh 			 * layer that there are no more slots left.
   6964  1.281   msaitoh 			 */
   6965  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   6966  1.281   msaitoh 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
   6967  1.281   msaitoh 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
   6968  1.366  knakahar 			    segs_needed, txq->txq_free - 1));
   6969  1.482  knakahar 			if (!is_transmit)
   6970  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   6971  1.479  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   6972  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   6973  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdstall);
   6974  1.281   msaitoh 			break;
   6975    1.1   thorpej 		}
   6976    1.1   thorpej 
   6977    1.1   thorpej 		/*
   6978  1.281   msaitoh 		 * Check for 82547 Tx FIFO bug.  We need to do this
   6979  1.281   msaitoh 		 * once we know we can transmit the packet, since we
   6980  1.281   msaitoh 		 * do some internal FIFO space accounting here.
   6981    1.1   thorpej 		 */
   6982  1.281   msaitoh 		if (sc->sc_type == WM_T_82547 &&
   6983  1.281   msaitoh 		    wm_82547_txfifo_bugchk(sc, m0)) {
   6984  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   6985  1.281   msaitoh 			    ("%s: TX: 82547 Tx FIFO bug detected\n",
   6986  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   6987  1.482  knakahar 			if (!is_transmit)
   6988  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   6989  1.479  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   6990  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   6991  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txfifo_stall);
   6992  1.281   msaitoh 			break;
   6993  1.281   msaitoh 		}
   6994   1.93   thorpej 
   6995  1.281   msaitoh 		/* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
   6996    1.1   thorpej 
   6997  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   6998  1.281   msaitoh 		    ("%s: TX: packet has %d (%d) DMA segments\n",
   6999  1.281   msaitoh 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
   7000    1.1   thorpej 
   7001  1.417  knakahar 		WM_EVCNT_INCR(&txq->txq_ev_txseg[dmamap->dm_nsegs - 1]);
   7002    1.1   thorpej 
   7003    1.1   thorpej 		/*
   7004  1.281   msaitoh 		 * Store a pointer to the packet so that we can free it
   7005  1.281   msaitoh 		 * later.
   7006  1.281   msaitoh 		 *
   7007  1.281   msaitoh 		 * Initially, we consider the number of descriptors the
   7008  1.281   msaitoh 		 * packet uses the number of DMA segments.  This may be
   7009  1.281   msaitoh 		 * incremented by 1 if we do checksum offload (a descriptor
   7010  1.281   msaitoh 		 * is used to set the checksum context).
   7011    1.1   thorpej 		 */
   7012  1.281   msaitoh 		txs->txs_mbuf = m0;
   7013  1.356  knakahar 		txs->txs_firstdesc = txq->txq_next;
   7014  1.281   msaitoh 		txs->txs_ndesc = segs_needed;
   7015  1.281   msaitoh 
   7016  1.281   msaitoh 		/* Set up offload parameters for this packet. */
   7017  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags &
   7018  1.388   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6 |
   7019  1.388   msaitoh 		    M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   7020  1.388   msaitoh 		    M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
   7021  1.498  knakahar 			if (wm_tx_offload(sc, txq, txs, &cksumcmd,
   7022  1.281   msaitoh 					  &cksumfields) != 0) {
   7023  1.281   msaitoh 				/* Error message already displayed. */
   7024  1.281   msaitoh 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   7025  1.281   msaitoh 				continue;
   7026  1.281   msaitoh 			}
   7027  1.281   msaitoh 		} else {
   7028  1.281   msaitoh 			cksumcmd = 0;
   7029  1.281   msaitoh 			cksumfields = 0;
   7030    1.1   thorpej 		}
   7031    1.1   thorpej 
   7032  1.281   msaitoh 		cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
   7033  1.281   msaitoh 
   7034  1.281   msaitoh 		/* Sync the DMA map. */
   7035  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   7036  1.281   msaitoh 		    BUS_DMASYNC_PREWRITE);
   7037    1.1   thorpej 
   7038  1.281   msaitoh 		/* Initialize the transmit descriptor. */
   7039  1.356  knakahar 		for (nexttx = txq->txq_next, seg = 0;
   7040  1.281   msaitoh 		     seg < dmamap->dm_nsegs; seg++) {
   7041  1.281   msaitoh 			for (seglen = dmamap->dm_segs[seg].ds_len,
   7042  1.281   msaitoh 			     curaddr = dmamap->dm_segs[seg].ds_addr;
   7043  1.281   msaitoh 			     seglen != 0;
   7044  1.281   msaitoh 			     curaddr += curlen, seglen -= curlen,
   7045  1.356  knakahar 			     nexttx = WM_NEXTTX(txq, nexttx)) {
   7046  1.281   msaitoh 				curlen = seglen;
   7047    1.1   thorpej 
   7048  1.106      yamt 				/*
   7049  1.281   msaitoh 				 * So says the Linux driver:
   7050  1.281   msaitoh 				 * Work around for premature descriptor
   7051  1.281   msaitoh 				 * write-backs in TSO mode.  Append a
   7052  1.281   msaitoh 				 * 4-byte sentinel descriptor.
   7053  1.106      yamt 				 */
   7054  1.388   msaitoh 				if (use_tso && seg == dmamap->dm_nsegs - 1 &&
   7055  1.281   msaitoh 				    curlen > 8)
   7056  1.281   msaitoh 					curlen -= 4;
   7057  1.281   msaitoh 
   7058  1.281   msaitoh 				wm_set_dma_addr(
   7059  1.388   msaitoh 				    &txq->txq_descs[nexttx].wtx_addr, curaddr);
   7060  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_cmdlen
   7061  1.388   msaitoh 				    = htole32(cksumcmd | curlen);
   7062  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_status
   7063  1.388   msaitoh 				    = 0;
   7064  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_options
   7065  1.388   msaitoh 				    = cksumfields;
   7066  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
   7067  1.281   msaitoh 				lasttx = nexttx;
   7068  1.281   msaitoh 
   7069  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   7070  1.281   msaitoh 				    ("%s: TX: desc %d: low %#" PRIx64 ", "
   7071  1.281   msaitoh 				     "len %#04zx\n",
   7072  1.281   msaitoh 				    device_xname(sc->sc_dev), nexttx,
   7073  1.281   msaitoh 				    (uint64_t)curaddr, curlen));
   7074  1.106      yamt 			}
   7075    1.1   thorpej 		}
   7076    1.1   thorpej 
   7077  1.281   msaitoh 		KASSERT(lasttx != -1);
   7078    1.1   thorpej 
   7079  1.281   msaitoh 		/*
   7080  1.281   msaitoh 		 * Set up the command byte on the last descriptor of
   7081  1.281   msaitoh 		 * the packet.  If we're in the interrupt delay window,
   7082  1.281   msaitoh 		 * delay the interrupt.
   7083  1.281   msaitoh 		 */
   7084  1.356  knakahar 		txq->txq_descs[lasttx].wtx_cmdlen |=
   7085  1.281   msaitoh 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
   7086  1.281   msaitoh 
   7087  1.281   msaitoh 		/*
   7088  1.281   msaitoh 		 * If VLANs are enabled and the packet has a VLAN tag, set
   7089  1.281   msaitoh 		 * up the descriptor to encapsulate the packet for us.
   7090  1.281   msaitoh 		 *
   7091  1.281   msaitoh 		 * This is only valid on the last descriptor of the packet.
   7092  1.281   msaitoh 		 */
   7093  1.281   msaitoh 		if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
   7094  1.356  knakahar 			txq->txq_descs[lasttx].wtx_cmdlen |=
   7095  1.281   msaitoh 			    htole32(WTX_CMD_VLE);
   7096  1.356  knakahar 			txq->txq_descs[lasttx].wtx_fields.wtxu_vlan
   7097  1.281   msaitoh 			    = htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
   7098  1.281   msaitoh 		}
   7099  1.281   msaitoh 
   7100  1.281   msaitoh 		txs->txs_lastdesc = lasttx;
   7101  1.281   msaitoh 
   7102  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7103  1.281   msaitoh 		    ("%s: TX: desc %d: cmdlen 0x%08x\n",
   7104  1.281   msaitoh 		    device_xname(sc->sc_dev),
   7105  1.366  knakahar 		    lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
   7106  1.281   msaitoh 
   7107  1.281   msaitoh 		/* Sync the descriptors we're using. */
   7108  1.362  knakahar 		wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc,
   7109  1.388   msaitoh 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   7110  1.281   msaitoh 
   7111  1.281   msaitoh 		/* Give the packet to the chip. */
   7112  1.356  knakahar 		CSR_WRITE(sc, txq->txq_tdt_reg, nexttx);
   7113  1.281   msaitoh 
   7114  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7115  1.281   msaitoh 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
   7116  1.281   msaitoh 
   7117  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7118  1.281   msaitoh 		    ("%s: TX: finished transmitting packet, job %d\n",
   7119  1.366  knakahar 		    device_xname(sc->sc_dev), txq->txq_snext));
   7120  1.272     ozaki 
   7121  1.281   msaitoh 		/* Advance the tx pointer. */
   7122  1.356  knakahar 		txq->txq_free -= txs->txs_ndesc;
   7123  1.356  knakahar 		txq->txq_next = nexttx;
   7124    1.1   thorpej 
   7125  1.356  knakahar 		txq->txq_sfree--;
   7126  1.356  knakahar 		txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext);
   7127  1.272     ozaki 
   7128  1.281   msaitoh 		/* Pass the packet to any BPF listeners. */
   7129  1.281   msaitoh 		bpf_mtap(ifp, m0);
   7130  1.281   msaitoh 	}
   7131  1.272     ozaki 
   7132  1.281   msaitoh 	if (m0 != NULL) {
   7133  1.482  knakahar 		if (!is_transmit)
   7134  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7135  1.479  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7136  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7137  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n",
   7138  1.388   msaitoh 			__func__));
   7139  1.281   msaitoh 		m_freem(m0);
   7140    1.1   thorpej 	}
   7141    1.1   thorpej 
   7142  1.356  knakahar 	if (txq->txq_sfree == 0 || txq->txq_free <= 2) {
   7143  1.281   msaitoh 		/* No more slots; notify upper layer. */
   7144  1.482  knakahar 		if (!is_transmit)
   7145  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7146  1.479  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7147  1.281   msaitoh 	}
   7148    1.1   thorpej 
   7149  1.356  knakahar 	if (txq->txq_free != ofree) {
   7150  1.281   msaitoh 		/* Set a watchdog timer in case the chip flakes out. */
   7151  1.281   msaitoh 		ifp->if_timer = 5;
   7152  1.281   msaitoh 	}
   7153    1.1   thorpej }
   7154    1.1   thorpej 
   7155    1.1   thorpej /*
   7156  1.281   msaitoh  * wm_nq_tx_offload:
   7157    1.1   thorpej  *
   7158  1.281   msaitoh  *	Set up TCP/IP checksumming parameters for the
   7159  1.281   msaitoh  *	specified packet, for NEWQUEUE devices
   7160    1.1   thorpej  */
   7161  1.281   msaitoh static int
   7162  1.403  knakahar wm_nq_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
   7163  1.403  knakahar     struct wm_txsoft *txs, uint32_t *cmdlenp, uint32_t *fieldsp, bool *do_csum)
   7164    1.1   thorpej {
   7165  1.281   msaitoh 	struct mbuf *m0 = txs->txs_mbuf;
   7166  1.281   msaitoh 	struct m_tag *mtag;
   7167  1.281   msaitoh 	uint32_t vl_len, mssidx, cmdc;
   7168  1.281   msaitoh 	struct ether_header *eh;
   7169  1.281   msaitoh 	int offset, iphl;
   7170  1.281   msaitoh 
   7171  1.281   msaitoh 	/*
   7172  1.281   msaitoh 	 * XXX It would be nice if the mbuf pkthdr had offset
   7173  1.281   msaitoh 	 * fields for the protocol headers.
   7174  1.281   msaitoh 	 */
   7175  1.281   msaitoh 	*cmdlenp = 0;
   7176  1.281   msaitoh 	*fieldsp = 0;
   7177  1.281   msaitoh 
   7178  1.281   msaitoh 	eh = mtod(m0, struct ether_header *);
   7179  1.281   msaitoh 	switch (htons(eh->ether_type)) {
   7180  1.281   msaitoh 	case ETHERTYPE_IP:
   7181  1.281   msaitoh 	case ETHERTYPE_IPV6:
   7182  1.281   msaitoh 		offset = ETHER_HDR_LEN;
   7183  1.281   msaitoh 		break;
   7184  1.281   msaitoh 
   7185  1.281   msaitoh 	case ETHERTYPE_VLAN:
   7186  1.281   msaitoh 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   7187  1.281   msaitoh 		break;
   7188  1.281   msaitoh 
   7189  1.281   msaitoh 	default:
   7190  1.281   msaitoh 		/* Don't support this protocol or encapsulation. */
   7191  1.281   msaitoh 		*do_csum = false;
   7192  1.281   msaitoh 		return 0;
   7193  1.281   msaitoh 	}
   7194  1.281   msaitoh 	*do_csum = true;
   7195  1.281   msaitoh 	*cmdlenp = NQTX_DTYP_D | NQTX_CMD_DEXT | NQTX_CMD_IFCS;
   7196  1.281   msaitoh 	cmdc = NQTX_DTYP_C | NQTX_CMD_DEXT;
   7197    1.1   thorpej 
   7198  1.281   msaitoh 	vl_len = (offset << NQTXC_VLLEN_MACLEN_SHIFT);
   7199  1.281   msaitoh 	KASSERT((offset & ~NQTXC_VLLEN_MACLEN_MASK) == 0);
   7200  1.281   msaitoh 
   7201  1.281   msaitoh 	if ((m0->m_pkthdr.csum_flags &
   7202  1.388   msaitoh 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
   7203  1.281   msaitoh 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   7204  1.281   msaitoh 	} else {
   7205  1.281   msaitoh 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
   7206  1.281   msaitoh 	}
   7207  1.281   msaitoh 	vl_len |= (iphl << NQTXC_VLLEN_IPLEN_SHIFT);
   7208  1.281   msaitoh 	KASSERT((iphl & ~NQTXC_VLLEN_IPLEN_MASK) == 0);
   7209  1.281   msaitoh 
   7210  1.281   msaitoh 	if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
   7211  1.281   msaitoh 		vl_len |= ((VLAN_TAG_VALUE(mtag) & NQTXC_VLLEN_VLAN_MASK)
   7212  1.281   msaitoh 		     << NQTXC_VLLEN_VLAN_SHIFT);
   7213  1.281   msaitoh 		*cmdlenp |= NQTX_CMD_VLE;
   7214  1.281   msaitoh 	}
   7215  1.272     ozaki 
   7216  1.281   msaitoh 	mssidx = 0;
   7217  1.170   msaitoh 
   7218  1.281   msaitoh 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
   7219  1.281   msaitoh 		int hlen = offset + iphl;
   7220  1.281   msaitoh 		int tcp_hlen;
   7221  1.281   msaitoh 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   7222  1.192   msaitoh 
   7223  1.281   msaitoh 		if (__predict_false(m0->m_len <
   7224  1.281   msaitoh 				    (hlen + sizeof(struct tcphdr)))) {
   7225  1.192   msaitoh 			/*
   7226  1.281   msaitoh 			 * TCP/IP headers are not in the first mbuf; we need
   7227  1.281   msaitoh 			 * to do this the slow and painful way.  Let's just
   7228  1.281   msaitoh 			 * hope this doesn't happen very often.
   7229  1.192   msaitoh 			 */
   7230  1.281   msaitoh 			struct tcphdr th;
   7231  1.170   msaitoh 
   7232  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtsopain);
   7233  1.192   msaitoh 
   7234  1.281   msaitoh 			m_copydata(m0, hlen, sizeof(th), &th);
   7235  1.281   msaitoh 			if (v4) {
   7236  1.281   msaitoh 				struct ip ip;
   7237  1.192   msaitoh 
   7238  1.281   msaitoh 				m_copydata(m0, offset, sizeof(ip), &ip);
   7239  1.281   msaitoh 				ip.ip_len = 0;
   7240  1.281   msaitoh 				m_copyback(m0,
   7241  1.281   msaitoh 				    offset + offsetof(struct ip, ip_len),
   7242  1.281   msaitoh 				    sizeof(ip.ip_len), &ip.ip_len);
   7243  1.281   msaitoh 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   7244  1.281   msaitoh 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   7245  1.281   msaitoh 			} else {
   7246  1.281   msaitoh 				struct ip6_hdr ip6;
   7247  1.192   msaitoh 
   7248  1.281   msaitoh 				m_copydata(m0, offset, sizeof(ip6), &ip6);
   7249  1.281   msaitoh 				ip6.ip6_plen = 0;
   7250  1.281   msaitoh 				m_copyback(m0,
   7251  1.281   msaitoh 				    offset + offsetof(struct ip6_hdr, ip6_plen),
   7252  1.281   msaitoh 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
   7253  1.281   msaitoh 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
   7254  1.281   msaitoh 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
   7255  1.170   msaitoh 			}
   7256  1.281   msaitoh 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   7257  1.281   msaitoh 			    sizeof(th.th_sum), &th.th_sum);
   7258  1.192   msaitoh 
   7259  1.281   msaitoh 			tcp_hlen = th.th_off << 2;
   7260  1.281   msaitoh 		} else {
   7261  1.173   msaitoh 			/*
   7262  1.281   msaitoh 			 * TCP/IP headers are in the first mbuf; we can do
   7263  1.281   msaitoh 			 * this the easy way.
   7264  1.173   msaitoh 			 */
   7265  1.281   msaitoh 			struct tcphdr *th;
   7266  1.198   msaitoh 
   7267  1.281   msaitoh 			if (v4) {
   7268  1.281   msaitoh 				struct ip *ip =
   7269  1.281   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   7270  1.281   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   7271    1.1   thorpej 
   7272  1.281   msaitoh 				ip->ip_len = 0;
   7273  1.281   msaitoh 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   7274  1.281   msaitoh 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   7275  1.281   msaitoh 			} else {
   7276  1.281   msaitoh 				struct ip6_hdr *ip6 =
   7277  1.281   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   7278  1.281   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   7279  1.192   msaitoh 
   7280  1.281   msaitoh 				ip6->ip6_plen = 0;
   7281  1.281   msaitoh 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
   7282  1.281   msaitoh 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
   7283  1.281   msaitoh 			}
   7284  1.281   msaitoh 			tcp_hlen = th->th_off << 2;
   7285  1.144   msaitoh 		}
   7286  1.281   msaitoh 		hlen += tcp_hlen;
   7287  1.281   msaitoh 		*cmdlenp |= NQTX_CMD_TSE;
   7288  1.144   msaitoh 
   7289  1.281   msaitoh 		if (v4) {
   7290  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso);
   7291  1.281   msaitoh 			*fieldsp |= NQTXD_FIELDS_IXSM | NQTXD_FIELDS_TUXSM;
   7292  1.281   msaitoh 		} else {
   7293  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso6);
   7294  1.281   msaitoh 			*fieldsp |= NQTXD_FIELDS_TUXSM;
   7295  1.189   msaitoh 		}
   7296  1.281   msaitoh 		*fieldsp |= ((m0->m_pkthdr.len - hlen) << NQTXD_FIELDS_PAYLEN_SHIFT);
   7297  1.281   msaitoh 		KASSERT(((m0->m_pkthdr.len - hlen) & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
   7298  1.281   msaitoh 		mssidx |= (m0->m_pkthdr.segsz << NQTXC_MSSIDX_MSS_SHIFT);
   7299  1.281   msaitoh 		KASSERT((m0->m_pkthdr.segsz & ~NQTXC_MSSIDX_MSS_MASK) == 0);
   7300  1.281   msaitoh 		mssidx |= (tcp_hlen << NQTXC_MSSIDX_L4LEN_SHIFT);
   7301  1.281   msaitoh 		KASSERT((tcp_hlen & ~NQTXC_MSSIDX_L4LEN_MASK) == 0);
   7302  1.281   msaitoh 	} else {
   7303  1.281   msaitoh 		*fieldsp |= (m0->m_pkthdr.len << NQTXD_FIELDS_PAYLEN_SHIFT);
   7304  1.281   msaitoh 		KASSERT((m0->m_pkthdr.len & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
   7305  1.208   msaitoh 	}
   7306  1.208   msaitoh 
   7307  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
   7308  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_IXSM;
   7309  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP4;
   7310  1.281   msaitoh 	}
   7311  1.144   msaitoh 
   7312  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags &
   7313  1.281   msaitoh 	    (M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
   7314  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum);
   7315  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
   7316  1.281   msaitoh 			cmdc |= NQTXC_CMD_TCP;
   7317  1.281   msaitoh 		} else {
   7318  1.281   msaitoh 			cmdc |= NQTXC_CMD_UDP;
   7319  1.281   msaitoh 		}
   7320  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP4;
   7321  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_TUXSM;
   7322  1.281   msaitoh 	}
   7323  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags &
   7324  1.281   msaitoh 	    (M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
   7325  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum6);
   7326  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
   7327  1.281   msaitoh 			cmdc |= NQTXC_CMD_TCP;
   7328  1.281   msaitoh 		} else {
   7329  1.281   msaitoh 			cmdc |= NQTXC_CMD_UDP;
   7330  1.281   msaitoh 		}
   7331  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP6;
   7332  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_TUXSM;
   7333  1.281   msaitoh 	}
   7334    1.1   thorpej 
   7335  1.500  knakahar 	/*
   7336  1.500  knakahar 	 * We don't have to write context descriptor for every packet to
   7337  1.500  knakahar 	 * NEWQUEUE controllers, that is 82575, 82576, 82580, I350, I354,
   7338  1.500  knakahar 	 * I210 and I211. It is enough to write once per a Tx queue for these
   7339  1.500  knakahar 	 * controllers.
   7340  1.500  knakahar 	 * It would be overhead to write context descriptor for every packet,
   7341  1.500  knakahar 	 * however it does not cause problems.
   7342  1.500  knakahar 	 */
   7343  1.281   msaitoh 	/* Fill in the context descriptor. */
   7344  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_vl_len =
   7345  1.281   msaitoh 	    htole32(vl_len);
   7346  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_sn = 0;
   7347  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_cmd =
   7348  1.281   msaitoh 	    htole32(cmdc);
   7349  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_mssidx =
   7350  1.281   msaitoh 	    htole32(mssidx);
   7351  1.362  knakahar 	wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE);
   7352  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX,
   7353  1.281   msaitoh 	    ("%s: TX: context desc %d 0x%08x%08x\n", device_xname(sc->sc_dev),
   7354  1.366  knakahar 	    txq->txq_next, 0, vl_len));
   7355  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX, ("\t0x%08x%08x\n", mssidx, cmdc));
   7356  1.356  knakahar 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   7357  1.281   msaitoh 	txs->txs_ndesc++;
   7358  1.281   msaitoh 	return 0;
   7359  1.217    dyoung }
   7360  1.217    dyoung 
   7361    1.1   thorpej /*
   7362  1.281   msaitoh  * wm_nq_start:		[ifnet interface function]
   7363    1.1   thorpej  *
   7364  1.281   msaitoh  *	Start packet transmission on the interface for NEWQUEUE devices
   7365    1.1   thorpej  */
   7366  1.281   msaitoh static void
   7367  1.281   msaitoh wm_nq_start(struct ifnet *ifp)
   7368    1.1   thorpej {
   7369    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   7370  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7371  1.272     ozaki 
   7372  1.496  knakahar #ifdef WM_MPSAFE
   7373  1.415  knakahar 	KASSERT(ifp->if_extflags & IFEF_START_MPSAFE);
   7374  1.496  knakahar #endif
   7375  1.455  knakahar 	/*
   7376  1.455  knakahar 	 * ifp->if_obytes and ifp->if_omcasts are added in if_transmit()@if.c.
   7377  1.455  knakahar 	 */
   7378  1.455  knakahar 
   7379  1.413     skrll 	mutex_enter(txq->txq_lock);
   7380  1.429  knakahar 	if (!txq->txq_stopping)
   7381  1.281   msaitoh 		wm_nq_start_locked(ifp);
   7382  1.413     skrll 	mutex_exit(txq->txq_lock);
   7383  1.272     ozaki }
   7384  1.272     ozaki 
   7385  1.281   msaitoh static void
   7386  1.281   msaitoh wm_nq_start_locked(struct ifnet *ifp)
   7387  1.272     ozaki {
   7388  1.272     ozaki 	struct wm_softc *sc = ifp->if_softc;
   7389  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7390  1.403  knakahar 
   7391  1.403  knakahar 	wm_nq_send_common_locked(ifp, txq, false);
   7392  1.403  knakahar }
   7393  1.403  knakahar 
   7394  1.403  knakahar static int
   7395  1.403  knakahar wm_nq_transmit(struct ifnet *ifp, struct mbuf *m)
   7396  1.403  knakahar {
   7397  1.403  knakahar 	int qid;
   7398  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7399  1.403  knakahar 	struct wm_txqueue *txq;
   7400  1.403  knakahar 
   7401  1.454  knakahar 	qid = wm_select_txqueue(ifp, m);
   7402  1.405  knakahar 	txq = &sc->sc_queue[qid].wmq_txq;
   7403  1.403  knakahar 
   7404  1.403  knakahar 	if (__predict_false(!pcq_put(txq->txq_interq, m))) {
   7405  1.403  knakahar 		m_freem(m);
   7406  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7407  1.403  knakahar 		return ENOBUFS;
   7408  1.403  knakahar 	}
   7409  1.403  knakahar 
   7410  1.455  knakahar 	/*
   7411  1.455  knakahar 	 * XXXX NOMPSAFE: ifp->if_data should be percpu.
   7412  1.455  knakahar 	 */
   7413  1.455  knakahar 	ifp->if_obytes += m->m_pkthdr.len;
   7414  1.455  knakahar 	if (m->m_flags & M_MCAST)
   7415  1.455  knakahar 		ifp->if_omcasts++;
   7416  1.455  knakahar 
   7417  1.470  knakahar 	/*
   7418  1.470  knakahar 	 * The situations which this mutex_tryenter() fails at running time
   7419  1.470  knakahar 	 * are below two patterns.
   7420  1.470  knakahar 	 *     (1) contention with interrupt handler(wm_txrxintr_msix())
   7421  1.484  knakahar 	 *     (2) contention with deferred if_start softint(wm_handle_queue())
   7422  1.470  knakahar 	 * In the case of (1), the last packet enqueued to txq->txq_interq is
   7423  1.484  knakahar 	 * dequeued by wm_deferred_start_locked(). So, it does not get stuck.
   7424  1.470  knakahar 	 * In the case of (2), the last packet enqueued to txq->txq_interq is also
   7425  1.484  knakahar 	 * dequeued by wm_deferred_start_locked(). So, it does not get stuck, either.
   7426  1.470  knakahar 	 */
   7427  1.413     skrll 	if (mutex_tryenter(txq->txq_lock)) {
   7428  1.429  knakahar 		if (!txq->txq_stopping)
   7429  1.403  knakahar 			wm_nq_transmit_locked(ifp, txq);
   7430  1.413     skrll 		mutex_exit(txq->txq_lock);
   7431  1.403  knakahar 	}
   7432  1.403  knakahar 
   7433  1.403  knakahar 	return 0;
   7434  1.403  knakahar }
   7435  1.403  knakahar 
   7436  1.403  knakahar static void
   7437  1.403  knakahar wm_nq_transmit_locked(struct ifnet *ifp, struct wm_txqueue *txq)
   7438  1.403  knakahar {
   7439  1.403  knakahar 
   7440  1.403  knakahar 	wm_nq_send_common_locked(ifp, txq, true);
   7441  1.403  knakahar }
   7442  1.403  knakahar 
   7443  1.403  knakahar static void
   7444  1.403  knakahar wm_nq_send_common_locked(struct ifnet *ifp, struct wm_txqueue *txq,
   7445  1.403  knakahar     bool is_transmit)
   7446  1.403  knakahar {
   7447  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7448  1.281   msaitoh 	struct mbuf *m0;
   7449  1.281   msaitoh 	struct m_tag *mtag;
   7450  1.281   msaitoh 	struct wm_txsoft *txs;
   7451  1.281   msaitoh 	bus_dmamap_t dmamap;
   7452  1.281   msaitoh 	int error, nexttx, lasttx = -1, seg, segs_needed;
   7453  1.281   msaitoh 	bool do_csum, sent;
   7454    1.1   thorpej 
   7455  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   7456   1.41       tls 
   7457  1.482  knakahar 	if ((ifp->if_flags & IFF_RUNNING) == 0)
   7458  1.482  knakahar 		return;
   7459  1.482  knakahar 	if ((ifp->if_flags & IFF_OACTIVE) != 0 && !is_transmit)
   7460  1.281   msaitoh 		return;
   7461  1.401  knakahar 	if ((txq->txq_flags & WM_TXQ_NO_SPACE) != 0)
   7462  1.400  knakahar 		return;
   7463    1.1   thorpej 
   7464  1.281   msaitoh 	sent = false;
   7465    1.1   thorpej 
   7466    1.1   thorpej 	/*
   7467  1.281   msaitoh 	 * Loop through the send queue, setting up transmit descriptors
   7468  1.281   msaitoh 	 * until we drain the queue, or use up all available transmit
   7469  1.281   msaitoh 	 * descriptors.
   7470    1.1   thorpej 	 */
   7471  1.281   msaitoh 	for (;;) {
   7472  1.281   msaitoh 		m0 = NULL;
   7473  1.281   msaitoh 
   7474  1.281   msaitoh 		/* Get a work queue entry. */
   7475  1.356  knakahar 		if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) {
   7476  1.403  knakahar 			wm_txeof(sc, txq);
   7477  1.356  knakahar 			if (txq->txq_sfree == 0) {
   7478  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   7479  1.281   msaitoh 				    ("%s: TX: no free job descriptors\n",
   7480  1.281   msaitoh 					device_xname(sc->sc_dev)));
   7481  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txsstall);
   7482  1.281   msaitoh 				break;
   7483  1.281   msaitoh 			}
   7484  1.281   msaitoh 		}
   7485    1.1   thorpej 
   7486  1.281   msaitoh 		/* Grab a packet off the queue. */
   7487  1.403  knakahar 		if (is_transmit)
   7488  1.403  knakahar 			m0 = pcq_get(txq->txq_interq);
   7489  1.403  knakahar 		else
   7490  1.403  knakahar 			IFQ_DEQUEUE(&ifp->if_snd, m0);
   7491  1.281   msaitoh 		if (m0 == NULL)
   7492  1.281   msaitoh 			break;
   7493   1.71   thorpej 
   7494  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7495  1.281   msaitoh 		    ("%s: TX: have packet to transmit: %p\n",
   7496  1.281   msaitoh 		    device_xname(sc->sc_dev), m0));
   7497  1.177   msaitoh 
   7498  1.356  knakahar 		txs = &txq->txq_soft[txq->txq_snext];
   7499  1.281   msaitoh 		dmamap = txs->txs_dmamap;
   7500    1.1   thorpej 
   7501  1.281   msaitoh 		/*
   7502  1.281   msaitoh 		 * Load the DMA map.  If this fails, the packet either
   7503  1.281   msaitoh 		 * didn't fit in the allotted number of segments, or we
   7504  1.281   msaitoh 		 * were short on resources.  For the too-many-segments
   7505  1.281   msaitoh 		 * case, we simply report an error and drop the packet,
   7506  1.281   msaitoh 		 * since we can't sanely copy a jumbo packet to a single
   7507  1.281   msaitoh 		 * buffer.
   7508  1.281   msaitoh 		 */
   7509  1.281   msaitoh 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   7510  1.388   msaitoh 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
   7511  1.281   msaitoh 		if (error) {
   7512  1.281   msaitoh 			if (error == EFBIG) {
   7513  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txdrop);
   7514  1.281   msaitoh 				log(LOG_ERR, "%s: Tx packet consumes too many "
   7515  1.281   msaitoh 				    "DMA segments, dropping...\n",
   7516  1.281   msaitoh 				    device_xname(sc->sc_dev));
   7517  1.281   msaitoh 				wm_dump_mbuf_chain(sc, m0);
   7518  1.281   msaitoh 				m_freem(m0);
   7519  1.281   msaitoh 				continue;
   7520  1.281   msaitoh 			}
   7521  1.281   msaitoh 			/* Short on resources, just stop for now. */
   7522  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7523  1.281   msaitoh 			    ("%s: TX: dmamap load failed: %d\n",
   7524  1.281   msaitoh 			    device_xname(sc->sc_dev), error));
   7525  1.281   msaitoh 			break;
   7526  1.281   msaitoh 		}
   7527  1.177   msaitoh 
   7528  1.281   msaitoh 		segs_needed = dmamap->dm_nsegs;
   7529  1.177   msaitoh 
   7530  1.281   msaitoh 		/*
   7531  1.281   msaitoh 		 * Ensure we have enough descriptors free to describe
   7532  1.281   msaitoh 		 * the packet.  Note, we always reserve one descriptor
   7533  1.281   msaitoh 		 * at the end of the ring due to the semantics of the
   7534  1.281   msaitoh 		 * TDT register, plus one more in the event we need
   7535  1.281   msaitoh 		 * to load offload context.
   7536  1.281   msaitoh 		 */
   7537  1.356  knakahar 		if (segs_needed > txq->txq_free - 2) {
   7538  1.177   msaitoh 			/*
   7539  1.281   msaitoh 			 * Not enough free descriptors to transmit this
   7540  1.281   msaitoh 			 * packet.  We haven't committed anything yet,
   7541  1.281   msaitoh 			 * so just unload the DMA map, put the packet
   7542  1.281   msaitoh 			 * pack on the queue, and punt.  Notify the upper
   7543  1.281   msaitoh 			 * layer that there are no more slots left.
   7544  1.177   msaitoh 			 */
   7545  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7546  1.281   msaitoh 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
   7547  1.281   msaitoh 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
   7548  1.366  knakahar 			    segs_needed, txq->txq_free - 1));
   7549  1.482  knakahar 			if (!is_transmit)
   7550  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   7551  1.401  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   7552  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   7553  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdstall);
   7554  1.177   msaitoh 			break;
   7555  1.177   msaitoh 		}
   7556  1.177   msaitoh 
   7557  1.281   msaitoh 		/* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
   7558  1.281   msaitoh 
   7559  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7560  1.281   msaitoh 		    ("%s: TX: packet has %d (%d) DMA segments\n",
   7561  1.281   msaitoh 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
   7562  1.177   msaitoh 
   7563  1.417  knakahar 		WM_EVCNT_INCR(&txq->txq_ev_txseg[dmamap->dm_nsegs - 1]);
   7564    1.1   thorpej 
   7565  1.281   msaitoh 		/*
   7566  1.281   msaitoh 		 * Store a pointer to the packet so that we can free it
   7567  1.281   msaitoh 		 * later.
   7568  1.281   msaitoh 		 *
   7569  1.281   msaitoh 		 * Initially, we consider the number of descriptors the
   7570  1.281   msaitoh 		 * packet uses the number of DMA segments.  This may be
   7571  1.281   msaitoh 		 * incremented by 1 if we do checksum offload (a descriptor
   7572  1.281   msaitoh 		 * is used to set the checksum context).
   7573  1.281   msaitoh 		 */
   7574  1.281   msaitoh 		txs->txs_mbuf = m0;
   7575  1.356  knakahar 		txs->txs_firstdesc = txq->txq_next;
   7576  1.281   msaitoh 		txs->txs_ndesc = segs_needed;
   7577    1.1   thorpej 
   7578  1.281   msaitoh 		/* Set up offload parameters for this packet. */
   7579  1.281   msaitoh 		uint32_t cmdlen, fields, dcmdlen;
   7580  1.388   msaitoh 		if (m0->m_pkthdr.csum_flags &
   7581  1.388   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6 |
   7582  1.388   msaitoh 			M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   7583  1.388   msaitoh 			M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
   7584  1.403  knakahar 			if (wm_nq_tx_offload(sc, txq, txs, &cmdlen, &fields,
   7585  1.281   msaitoh 			    &do_csum) != 0) {
   7586  1.281   msaitoh 				/* Error message already displayed. */
   7587  1.281   msaitoh 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   7588  1.281   msaitoh 				continue;
   7589  1.281   msaitoh 			}
   7590  1.281   msaitoh 		} else {
   7591  1.281   msaitoh 			do_csum = false;
   7592  1.281   msaitoh 			cmdlen = 0;
   7593  1.281   msaitoh 			fields = 0;
   7594  1.281   msaitoh 		}
   7595  1.173   msaitoh 
   7596  1.281   msaitoh 		/* Sync the DMA map. */
   7597  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   7598  1.281   msaitoh 		    BUS_DMASYNC_PREWRITE);
   7599    1.1   thorpej 
   7600  1.281   msaitoh 		/* Initialize the first transmit descriptor. */
   7601  1.356  knakahar 		nexttx = txq->txq_next;
   7602  1.281   msaitoh 		if (!do_csum) {
   7603  1.281   msaitoh 			/* setup a legacy descriptor */
   7604  1.388   msaitoh 			wm_set_dma_addr(&txq->txq_descs[nexttx].wtx_addr,
   7605  1.281   msaitoh 			    dmamap->dm_segs[0].ds_addr);
   7606  1.356  knakahar 			txq->txq_descs[nexttx].wtx_cmdlen =
   7607  1.281   msaitoh 			    htole32(WTX_CMD_IFCS | dmamap->dm_segs[0].ds_len);
   7608  1.356  knakahar 			txq->txq_descs[nexttx].wtx_fields.wtxu_status = 0;
   7609  1.356  knakahar 			txq->txq_descs[nexttx].wtx_fields.wtxu_options = 0;
   7610  1.281   msaitoh 			if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) !=
   7611  1.281   msaitoh 			    NULL) {
   7612  1.356  knakahar 				txq->txq_descs[nexttx].wtx_cmdlen |=
   7613  1.281   msaitoh 				    htole32(WTX_CMD_VLE);
   7614  1.356  knakahar 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =
   7615  1.281   msaitoh 				    htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
   7616  1.281   msaitoh 			} else {
   7617  1.356  knakahar 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
   7618  1.281   msaitoh 			}
   7619  1.281   msaitoh 			dcmdlen = 0;
   7620  1.281   msaitoh 		} else {
   7621  1.281   msaitoh 			/* setup an advanced data descriptor */
   7622  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr =
   7623  1.281   msaitoh 			    htole64(dmamap->dm_segs[0].ds_addr);
   7624  1.281   msaitoh 			KASSERT((dmamap->dm_segs[0].ds_len & cmdlen) == 0);
   7625  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen =
   7626  1.281   msaitoh 			    htole32(dmamap->dm_segs[0].ds_len | cmdlen );
   7627  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields =
   7628  1.281   msaitoh 			    htole32(fields);
   7629  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7630  1.281   msaitoh 			    ("%s: TX: adv data desc %d 0x%" PRIx64 "\n",
   7631  1.281   msaitoh 			    device_xname(sc->sc_dev), nexttx,
   7632  1.281   msaitoh 			    (uint64_t)dmamap->dm_segs[0].ds_addr));
   7633  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7634  1.281   msaitoh 			    ("\t 0x%08x%08x\n", fields,
   7635  1.281   msaitoh 			    (uint32_t)dmamap->dm_segs[0].ds_len | cmdlen));
   7636  1.281   msaitoh 			dcmdlen = NQTX_DTYP_D | NQTX_CMD_DEXT;
   7637  1.281   msaitoh 		}
   7638  1.177   msaitoh 
   7639  1.281   msaitoh 		lasttx = nexttx;
   7640  1.356  knakahar 		nexttx = WM_NEXTTX(txq, nexttx);
   7641  1.150       tls 		/*
   7642  1.281   msaitoh 		 * fill in the next descriptors. legacy or adcanced format
   7643  1.281   msaitoh 		 * is the same here
   7644  1.150       tls 		 */
   7645  1.281   msaitoh 		for (seg = 1; seg < dmamap->dm_nsegs;
   7646  1.356  knakahar 		    seg++, nexttx = WM_NEXTTX(txq, nexttx)) {
   7647  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr =
   7648  1.281   msaitoh 			    htole64(dmamap->dm_segs[seg].ds_addr);
   7649  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen =
   7650  1.281   msaitoh 			    htole32(dcmdlen | dmamap->dm_segs[seg].ds_len);
   7651  1.281   msaitoh 			KASSERT((dcmdlen & dmamap->dm_segs[seg].ds_len) == 0);
   7652  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields = 0;
   7653  1.281   msaitoh 			lasttx = nexttx;
   7654  1.153       tls 
   7655  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7656  1.281   msaitoh 			    ("%s: TX: desc %d: %#" PRIx64 ", "
   7657  1.281   msaitoh 			     "len %#04zx\n",
   7658  1.281   msaitoh 			    device_xname(sc->sc_dev), nexttx,
   7659  1.281   msaitoh 			    (uint64_t)dmamap->dm_segs[seg].ds_addr,
   7660  1.281   msaitoh 			    dmamap->dm_segs[seg].ds_len));
   7661  1.281   msaitoh 		}
   7662  1.153       tls 
   7663  1.281   msaitoh 		KASSERT(lasttx != -1);
   7664    1.1   thorpej 
   7665  1.211   msaitoh 		/*
   7666  1.281   msaitoh 		 * Set up the command byte on the last descriptor of
   7667  1.281   msaitoh 		 * the packet.  If we're in the interrupt delay window,
   7668  1.281   msaitoh 		 * delay the interrupt.
   7669  1.211   msaitoh 		 */
   7670  1.281   msaitoh 		KASSERT((WTX_CMD_EOP | WTX_CMD_RS) ==
   7671  1.281   msaitoh 		    (NQTX_CMD_EOP | NQTX_CMD_RS));
   7672  1.356  knakahar 		txq->txq_descs[lasttx].wtx_cmdlen |=
   7673  1.281   msaitoh 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
   7674  1.211   msaitoh 
   7675  1.281   msaitoh 		txs->txs_lastdesc = lasttx;
   7676  1.177   msaitoh 
   7677  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: desc %d: cmdlen 0x%08x\n",
   7678  1.281   msaitoh 		    device_xname(sc->sc_dev),
   7679  1.366  knakahar 		    lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
   7680    1.1   thorpej 
   7681  1.281   msaitoh 		/* Sync the descriptors we're using. */
   7682  1.362  knakahar 		wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc,
   7683  1.388   msaitoh 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   7684  1.203   msaitoh 
   7685  1.281   msaitoh 		/* Give the packet to the chip. */
   7686  1.356  knakahar 		CSR_WRITE(sc, txq->txq_tdt_reg, nexttx);
   7687  1.281   msaitoh 		sent = true;
   7688  1.120   msaitoh 
   7689  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7690  1.281   msaitoh 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
   7691  1.228   msaitoh 
   7692  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7693  1.281   msaitoh 		    ("%s: TX: finished transmitting packet, job %d\n",
   7694  1.366  knakahar 		    device_xname(sc->sc_dev), txq->txq_snext));
   7695   1.41       tls 
   7696  1.281   msaitoh 		/* Advance the tx pointer. */
   7697  1.356  knakahar 		txq->txq_free -= txs->txs_ndesc;
   7698  1.356  knakahar 		txq->txq_next = nexttx;
   7699    1.1   thorpej 
   7700  1.356  knakahar 		txq->txq_sfree--;
   7701  1.356  knakahar 		txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext);
   7702    1.1   thorpej 
   7703  1.281   msaitoh 		/* Pass the packet to any BPF listeners. */
   7704  1.281   msaitoh 		bpf_mtap(ifp, m0);
   7705  1.281   msaitoh 	}
   7706  1.257   msaitoh 
   7707  1.281   msaitoh 	if (m0 != NULL) {
   7708  1.482  knakahar 		if (!is_transmit)
   7709  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7710  1.401  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7711  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7712  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n",
   7713  1.388   msaitoh 			__func__));
   7714  1.281   msaitoh 		m_freem(m0);
   7715  1.257   msaitoh 	}
   7716  1.257   msaitoh 
   7717  1.356  knakahar 	if (txq->txq_sfree == 0 || txq->txq_free <= 2) {
   7718  1.281   msaitoh 		/* No more slots; notify upper layer. */
   7719  1.482  knakahar 		if (!is_transmit)
   7720  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7721  1.401  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7722  1.281   msaitoh 	}
   7723  1.199   msaitoh 
   7724  1.281   msaitoh 	if (sent) {
   7725  1.281   msaitoh 		/* Set a watchdog timer in case the chip flakes out. */
   7726  1.281   msaitoh 		ifp->if_timer = 5;
   7727  1.281   msaitoh 	}
   7728  1.281   msaitoh }
   7729  1.272     ozaki 
   7730  1.456     ozaki static void
   7731  1.481  knakahar wm_deferred_start_locked(struct wm_txqueue *txq)
   7732  1.481  knakahar {
   7733  1.481  knakahar 	struct wm_softc *sc = txq->txq_sc;
   7734  1.481  knakahar 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   7735  1.481  knakahar 	struct wm_queue *wmq = container_of(txq, struct wm_queue, wmq_txq);
   7736  1.481  knakahar 	int qid = wmq->wmq_id;
   7737  1.481  knakahar 
   7738  1.481  knakahar 	KASSERT(mutex_owned(txq->txq_lock));
   7739  1.456     ozaki 
   7740  1.481  knakahar 	if (txq->txq_stopping) {
   7741  1.456     ozaki 		mutex_exit(txq->txq_lock);
   7742  1.481  knakahar 		return;
   7743  1.481  knakahar 	}
   7744  1.481  knakahar 
   7745  1.481  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   7746  1.503  knakahar 		/* XXX need for ALTQ or one CPU system */
   7747  1.481  knakahar 		if (qid == 0)
   7748  1.481  knakahar 			wm_nq_start_locked(ifp);
   7749  1.481  knakahar 		wm_nq_transmit_locked(ifp, txq);
   7750  1.481  knakahar 	} else {
   7751  1.503  knakahar 		/* XXX need for ALTQ or one CPU system */
   7752  1.481  knakahar 		if (qid == 0)
   7753  1.481  knakahar 			wm_start_locked(ifp);
   7754  1.481  knakahar 		wm_transmit_locked(ifp, txq);
   7755  1.456     ozaki 	}
   7756  1.456     ozaki }
   7757  1.456     ozaki 
   7758  1.281   msaitoh /* Interrupt */
   7759    1.1   thorpej 
   7760    1.1   thorpej /*
   7761  1.335   msaitoh  * wm_txeof:
   7762    1.1   thorpej  *
   7763  1.281   msaitoh  *	Helper; handle transmit interrupts.
   7764    1.1   thorpej  */
   7765  1.335   msaitoh static int
   7766  1.403  knakahar wm_txeof(struct wm_softc *sc, struct wm_txqueue *txq)
   7767    1.1   thorpej {
   7768  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   7769  1.281   msaitoh 	struct wm_txsoft *txs;
   7770  1.335   msaitoh 	bool processed = false;
   7771  1.335   msaitoh 	int count = 0;
   7772  1.335   msaitoh 	int i;
   7773  1.281   msaitoh 	uint8_t status;
   7774  1.479  knakahar 	struct wm_queue *wmq = container_of(txq, struct wm_queue, wmq_txq);
   7775    1.1   thorpej 
   7776  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   7777  1.405  knakahar 
   7778  1.429  knakahar 	if (txq->txq_stopping)
   7779  1.335   msaitoh 		return 0;
   7780  1.281   msaitoh 
   7781  1.479  knakahar 	txq->txq_flags &= ~WM_TXQ_NO_SPACE;
   7782  1.479  knakahar 	/* for ALTQ and legacy(not use multiqueue) ethernet controller */
   7783  1.479  knakahar 	if (wmq->wmq_id == 0)
   7784  1.411  knakahar 		ifp->if_flags &= ~IFF_OACTIVE;
   7785  1.272     ozaki 
   7786  1.281   msaitoh 	/*
   7787  1.281   msaitoh 	 * Go through the Tx list and free mbufs for those
   7788  1.281   msaitoh 	 * frames which have been transmitted.
   7789  1.281   msaitoh 	 */
   7790  1.356  knakahar 	for (i = txq->txq_sdirty; txq->txq_sfree != WM_TXQUEUELEN(txq);
   7791  1.356  knakahar 	     i = WM_NEXTTXS(txq, i), txq->txq_sfree++) {
   7792  1.356  knakahar 		txs = &txq->txq_soft[i];
   7793    1.1   thorpej 
   7794  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: checking job %d\n",
   7795  1.388   msaitoh 			device_xname(sc->sc_dev), i));
   7796  1.272     ozaki 
   7797  1.362  knakahar 		wm_cdtxsync(txq, txs->txs_firstdesc, txs->txs_ndesc,
   7798  1.388   msaitoh 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
   7799  1.272     ozaki 
   7800  1.281   msaitoh 		status =
   7801  1.356  knakahar 		    txq->txq_descs[txs->txs_lastdesc].wtx_fields.wtxu_status;
   7802  1.281   msaitoh 		if ((status & WTX_ST_DD) == 0) {
   7803  1.362  knakahar 			wm_cdtxsync(txq, txs->txs_lastdesc, 1,
   7804  1.281   msaitoh 			    BUS_DMASYNC_PREREAD);
   7805  1.281   msaitoh 			break;
   7806  1.281   msaitoh 		}
   7807    1.1   thorpej 
   7808  1.335   msaitoh 		processed = true;
   7809  1.335   msaitoh 		count++;
   7810  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7811  1.281   msaitoh 		    ("%s: TX: job %d done: descs %d..%d\n",
   7812  1.281   msaitoh 		    device_xname(sc->sc_dev), i, txs->txs_firstdesc,
   7813  1.281   msaitoh 		    txs->txs_lastdesc));
   7814  1.272     ozaki 
   7815  1.281   msaitoh 		/*
   7816  1.281   msaitoh 		 * XXX We should probably be using the statistics
   7817  1.281   msaitoh 		 * XXX registers, but I don't know if they exist
   7818  1.281   msaitoh 		 * XXX on chips before the i82544.
   7819  1.281   msaitoh 		 */
   7820  1.272     ozaki 
   7821  1.281   msaitoh #ifdef WM_EVENT_COUNTERS
   7822  1.281   msaitoh 		if (status & WTX_ST_TU)
   7823  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, tu);
   7824  1.281   msaitoh #endif /* WM_EVENT_COUNTERS */
   7825    1.1   thorpej 
   7826  1.388   msaitoh 		if (status & (WTX_ST_EC | WTX_ST_LC)) {
   7827  1.281   msaitoh 			ifp->if_oerrors++;
   7828  1.281   msaitoh 			if (status & WTX_ST_LC)
   7829  1.281   msaitoh 				log(LOG_WARNING, "%s: late collision\n",
   7830  1.281   msaitoh 				    device_xname(sc->sc_dev));
   7831  1.281   msaitoh 			else if (status & WTX_ST_EC) {
   7832  1.281   msaitoh 				ifp->if_collisions += 16;
   7833  1.281   msaitoh 				log(LOG_WARNING, "%s: excessive collisions\n",
   7834  1.281   msaitoh 				    device_xname(sc->sc_dev));
   7835  1.281   msaitoh 			}
   7836  1.281   msaitoh 		} else
   7837  1.281   msaitoh 			ifp->if_opackets++;
   7838   1.78   thorpej 
   7839  1.495  knakahar 		txq->txq_packets++;
   7840  1.495  knakahar 		txq->txq_bytes += txs->txs_mbuf->m_pkthdr.len;
   7841  1.495  knakahar 
   7842  1.356  knakahar 		txq->txq_free += txs->txs_ndesc;
   7843  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
   7844  1.281   msaitoh 		    0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   7845  1.281   msaitoh 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   7846  1.281   msaitoh 		m_freem(txs->txs_mbuf);
   7847  1.281   msaitoh 		txs->txs_mbuf = NULL;
   7848    1.1   thorpej 	}
   7849    1.1   thorpej 
   7850  1.281   msaitoh 	/* Update the dirty transmit buffer pointer. */
   7851  1.356  knakahar 	txq->txq_sdirty = i;
   7852  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX,
   7853  1.281   msaitoh 	    ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i));
   7854    1.1   thorpej 
   7855  1.335   msaitoh 	if (count != 0)
   7856  1.335   msaitoh 		rnd_add_uint32(&sc->rnd_source, count);
   7857  1.335   msaitoh 
   7858  1.102       scw 	/*
   7859  1.281   msaitoh 	 * If there are no more pending transmissions, cancel the watchdog
   7860  1.281   msaitoh 	 * timer.
   7861  1.102       scw 	 */
   7862  1.356  knakahar 	if (txq->txq_sfree == WM_TXQUEUELEN(txq))
   7863  1.281   msaitoh 		ifp->if_timer = 0;
   7864  1.335   msaitoh 
   7865  1.335   msaitoh 	return processed;
   7866  1.281   msaitoh }
   7867  1.102       scw 
   7868  1.466  knakahar static inline uint32_t
   7869  1.466  knakahar wm_rxdesc_get_status(struct wm_rxqueue *rxq, int idx)
   7870  1.466  knakahar {
   7871  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   7872  1.466  knakahar 
   7873  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   7874  1.466  knakahar 		return EXTRXC_STATUS(rxq->rxq_ext_descs[idx].erx_ctx.erxc_err_stat);
   7875  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   7876  1.466  knakahar 		return NQRXC_STATUS(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_err_stat);
   7877  1.466  knakahar 	else
   7878  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_status;
   7879  1.466  knakahar }
   7880  1.466  knakahar 
   7881  1.466  knakahar static inline uint32_t
   7882  1.466  knakahar wm_rxdesc_get_errors(struct wm_rxqueue *rxq, int idx)
   7883  1.466  knakahar {
   7884  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   7885  1.466  knakahar 
   7886  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   7887  1.466  knakahar 		return EXTRXC_ERROR(rxq->rxq_ext_descs[idx].erx_ctx.erxc_err_stat);
   7888  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   7889  1.466  knakahar 		return NQRXC_ERROR(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_err_stat);
   7890  1.466  knakahar 	else
   7891  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_errors;
   7892  1.466  knakahar }
   7893  1.466  knakahar 
   7894  1.466  knakahar static inline uint16_t
   7895  1.466  knakahar wm_rxdesc_get_vlantag(struct wm_rxqueue *rxq, int idx)
   7896  1.466  knakahar {
   7897  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   7898  1.466  knakahar 
   7899  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   7900  1.466  knakahar 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_vlan;
   7901  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   7902  1.466  knakahar 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_vlan;
   7903  1.466  knakahar 	else
   7904  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_special;
   7905  1.466  knakahar }
   7906  1.466  knakahar 
   7907  1.466  knakahar static inline int
   7908  1.466  knakahar wm_rxdesc_get_pktlen(struct wm_rxqueue *rxq, int idx)
   7909  1.466  knakahar {
   7910  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   7911  1.466  knakahar 
   7912  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   7913  1.466  knakahar 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_pktlen;
   7914  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   7915  1.466  knakahar 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_pktlen;
   7916  1.466  knakahar 	else
   7917  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_len;
   7918  1.466  knakahar }
   7919  1.466  knakahar 
   7920  1.466  knakahar #ifdef WM_DEBUG
   7921  1.466  knakahar static inline uint32_t
   7922  1.466  knakahar wm_rxdesc_get_rsshash(struct wm_rxqueue *rxq, int idx)
   7923  1.466  knakahar {
   7924  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   7925  1.466  knakahar 
   7926  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   7927  1.466  knakahar 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_rsshash;
   7928  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   7929  1.466  knakahar 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_rsshash;
   7930  1.466  knakahar 	else
   7931  1.466  knakahar 		return 0;
   7932  1.466  knakahar }
   7933  1.466  knakahar 
   7934  1.466  knakahar static inline uint8_t
   7935  1.466  knakahar wm_rxdesc_get_rsstype(struct wm_rxqueue *rxq, int idx)
   7936  1.466  knakahar {
   7937  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   7938  1.466  knakahar 
   7939  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   7940  1.466  knakahar 		return EXTRXC_RSS_TYPE(rxq->rxq_ext_descs[idx].erx_ctx.erxc_mrq);
   7941  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   7942  1.466  knakahar 		return NQRXC_RSS_TYPE(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_misc);
   7943  1.466  knakahar 	else
   7944  1.466  knakahar 		return 0;
   7945  1.466  knakahar }
   7946  1.466  knakahar #endif /* WM_DEBUG */
   7947  1.466  knakahar 
   7948  1.466  knakahar static inline bool
   7949  1.466  knakahar wm_rxdesc_is_set_status(struct wm_softc *sc, uint32_t status,
   7950  1.466  knakahar     uint32_t legacy_bit, uint32_t ext_bit, uint32_t nq_bit)
   7951  1.466  knakahar {
   7952  1.466  knakahar 
   7953  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   7954  1.466  knakahar 		return (status & ext_bit) != 0;
   7955  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   7956  1.466  knakahar 		return (status & nq_bit) != 0;
   7957  1.466  knakahar 	else
   7958  1.466  knakahar 		return (status & legacy_bit) != 0;
   7959  1.466  knakahar }
   7960  1.466  knakahar 
   7961  1.466  knakahar static inline bool
   7962  1.466  knakahar wm_rxdesc_is_set_error(struct wm_softc *sc, uint32_t error,
   7963  1.466  knakahar     uint32_t legacy_bit, uint32_t ext_bit, uint32_t nq_bit)
   7964  1.466  knakahar {
   7965  1.466  knakahar 
   7966  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   7967  1.466  knakahar 		return (error & ext_bit) != 0;
   7968  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   7969  1.466  knakahar 		return (error & nq_bit) != 0;
   7970  1.466  knakahar 	else
   7971  1.466  knakahar 		return (error & legacy_bit) != 0;
   7972  1.466  knakahar }
   7973  1.466  knakahar 
   7974  1.466  knakahar static inline bool
   7975  1.466  knakahar wm_rxdesc_is_eop(struct wm_rxqueue *rxq, uint32_t status)
   7976  1.466  knakahar {
   7977  1.466  knakahar 
   7978  1.466  knakahar 	if (wm_rxdesc_is_set_status(rxq->rxq_sc, status,
   7979  1.466  knakahar 		WRX_ST_EOP, EXTRXC_STATUS_EOP, NQRXC_STATUS_EOP))
   7980  1.466  knakahar 		return true;
   7981  1.466  knakahar 	else
   7982  1.466  knakahar 		return false;
   7983  1.466  knakahar }
   7984  1.466  knakahar 
   7985  1.466  knakahar static inline bool
   7986  1.466  knakahar wm_rxdesc_has_errors(struct wm_rxqueue *rxq, uint32_t errors)
   7987  1.466  knakahar {
   7988  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   7989  1.466  knakahar 
   7990  1.466  knakahar 	/* XXXX missing error bit for newqueue? */
   7991  1.466  knakahar 	if (wm_rxdesc_is_set_error(sc, errors,
   7992  1.466  knakahar 		WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE,
   7993  1.466  knakahar 		EXTRXC_ERROR_CE|EXTRXC_ERROR_SE|EXTRXC_ERROR_SEQ|EXTRXC_ERROR_CXE|EXTRXC_ERROR_RXE,
   7994  1.466  knakahar 		NQRXC_ERROR_RXE)) {
   7995  1.466  knakahar 		if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_SE, EXTRXC_ERROR_SE, 0))
   7996  1.466  knakahar 			log(LOG_WARNING, "%s: symbol error\n",
   7997  1.466  knakahar 			    device_xname(sc->sc_dev));
   7998  1.466  knakahar 		else if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_SEQ, EXTRXC_ERROR_SEQ, 0))
   7999  1.466  knakahar 			log(LOG_WARNING, "%s: receive sequence error\n",
   8000  1.466  knakahar 			    device_xname(sc->sc_dev));
   8001  1.466  knakahar 		else if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_CE, EXTRXC_ERROR_CE, 0))
   8002  1.466  knakahar 			log(LOG_WARNING, "%s: CRC error\n",
   8003  1.466  knakahar 			    device_xname(sc->sc_dev));
   8004  1.466  knakahar 		return true;
   8005  1.466  knakahar 	}
   8006  1.466  knakahar 
   8007  1.466  knakahar 	return false;
   8008  1.466  knakahar }
   8009  1.466  knakahar 
   8010  1.466  knakahar static inline bool
   8011  1.466  knakahar wm_rxdesc_dd(struct wm_rxqueue *rxq, int idx, uint32_t status)
   8012  1.466  knakahar {
   8013  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8014  1.466  knakahar 
   8015  1.466  knakahar 	if (!wm_rxdesc_is_set_status(sc, status, WRX_ST_DD, EXTRXC_STATUS_DD,
   8016  1.466  knakahar 		NQRXC_STATUS_DD)) {
   8017  1.466  knakahar 		/* We have processed all of the receive descriptors. */
   8018  1.466  knakahar 		wm_cdrxsync(rxq, idx, BUS_DMASYNC_PREREAD);
   8019  1.466  knakahar 		return false;
   8020  1.466  knakahar 	}
   8021  1.466  knakahar 
   8022  1.466  knakahar 	return true;
   8023  1.466  knakahar }
   8024  1.466  knakahar 
   8025  1.466  knakahar static inline bool
   8026  1.466  knakahar wm_rxdesc_input_vlantag(struct wm_rxqueue *rxq, uint32_t status, uint16_t vlantag,
   8027  1.466  knakahar     struct mbuf *m)
   8028  1.466  knakahar {
   8029  1.466  knakahar 	struct ifnet *ifp = &rxq->rxq_sc->sc_ethercom.ec_if;
   8030  1.466  knakahar 
   8031  1.466  knakahar 	if (wm_rxdesc_is_set_status(rxq->rxq_sc, status,
   8032  1.466  knakahar 		WRX_ST_VP, EXTRXC_STATUS_VP, NQRXC_STATUS_VP)) {
   8033  1.466  knakahar 		VLAN_INPUT_TAG(ifp, m, le16toh(vlantag), return false);
   8034  1.466  knakahar 	}
   8035  1.466  knakahar 
   8036  1.466  knakahar 	return true;
   8037  1.466  knakahar }
   8038  1.466  knakahar 
   8039  1.466  knakahar static inline void
   8040  1.466  knakahar wm_rxdesc_ensure_checksum(struct wm_rxqueue *rxq, uint32_t status,
   8041  1.466  knakahar     uint32_t errors, struct mbuf *m)
   8042  1.466  knakahar {
   8043  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8044  1.466  knakahar 
   8045  1.466  knakahar 	if (!wm_rxdesc_is_set_status(sc, status, WRX_ST_IXSM, 0, 0)) {
   8046  1.466  knakahar 		if (wm_rxdesc_is_set_status(sc, status,
   8047  1.466  knakahar 			WRX_ST_IPCS, EXTRXC_STATUS_IPCS, NQRXC_STATUS_IPCS)) {
   8048  1.466  knakahar 			WM_Q_EVCNT_INCR(rxq, rxipsum);
   8049  1.466  knakahar 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
   8050  1.466  knakahar 			if (wm_rxdesc_is_set_error(sc, errors,
   8051  1.466  knakahar 				WRX_ER_IPE, EXTRXC_ERROR_IPE, NQRXC_ERROR_IPE))
   8052  1.466  knakahar 				m->m_pkthdr.csum_flags |=
   8053  1.466  knakahar 					M_CSUM_IPv4_BAD;
   8054  1.466  knakahar 		}
   8055  1.466  knakahar 		if (wm_rxdesc_is_set_status(sc, status,
   8056  1.466  knakahar 			WRX_ST_TCPCS, EXTRXC_STATUS_TCPCS, NQRXC_STATUS_L4I)) {
   8057  1.466  knakahar 			/*
   8058  1.466  knakahar 			 * Note: we don't know if this was TCP or UDP,
   8059  1.466  knakahar 			 * so we just set both bits, and expect the
   8060  1.466  knakahar 			 * upper layers to deal.
   8061  1.466  knakahar 			 */
   8062  1.466  knakahar 			WM_Q_EVCNT_INCR(rxq, rxtusum);
   8063  1.466  knakahar 			m->m_pkthdr.csum_flags |=
   8064  1.466  knakahar 				M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   8065  1.466  knakahar 				M_CSUM_TCPv6 | M_CSUM_UDPv6;
   8066  1.466  knakahar 			if (wm_rxdesc_is_set_error(sc, errors,
   8067  1.466  knakahar 				WRX_ER_TCPE, EXTRXC_ERROR_TCPE, NQRXC_ERROR_L4E))
   8068  1.466  knakahar 				m->m_pkthdr.csum_flags |=
   8069  1.466  knakahar 					M_CSUM_TCP_UDP_BAD;
   8070  1.466  knakahar 		}
   8071  1.466  knakahar 	}
   8072  1.466  knakahar }
   8073  1.466  knakahar 
   8074  1.281   msaitoh /*
   8075  1.335   msaitoh  * wm_rxeof:
   8076  1.281   msaitoh  *
   8077  1.281   msaitoh  *	Helper; handle receive interrupts.
   8078  1.281   msaitoh  */
   8079  1.281   msaitoh static void
   8080  1.493  knakahar wm_rxeof(struct wm_rxqueue *rxq, u_int limit)
   8081  1.281   msaitoh {
   8082  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8083  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8084  1.281   msaitoh 	struct wm_rxsoft *rxs;
   8085  1.281   msaitoh 	struct mbuf *m;
   8086  1.281   msaitoh 	int i, len;
   8087  1.335   msaitoh 	int count = 0;
   8088  1.466  knakahar 	uint32_t status, errors;
   8089  1.281   msaitoh 	uint16_t vlantag;
   8090    1.1   thorpej 
   8091  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   8092  1.405  knakahar 
   8093  1.356  knakahar 	for (i = rxq->rxq_ptr;; i = WM_NEXTRX(i)) {
   8094  1.493  knakahar 		if (limit-- == 0) {
   8095  1.493  knakahar 			rxq->rxq_ptr = i;
   8096  1.493  knakahar 			break;
   8097  1.493  knakahar 		}
   8098  1.493  knakahar 
   8099  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   8100  1.156    dyoung 
   8101  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8102  1.281   msaitoh 		    ("%s: RX: checking descriptor %d\n",
   8103  1.281   msaitoh 		    device_xname(sc->sc_dev), i));
   8104  1.466  knakahar 		wm_cdrxsync(rxq, i,BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   8105  1.199   msaitoh 
   8106  1.466  knakahar 		status = wm_rxdesc_get_status(rxq, i);
   8107  1.466  knakahar 		errors = wm_rxdesc_get_errors(rxq, i);
   8108  1.466  knakahar 		len = le16toh(wm_rxdesc_get_pktlen(rxq, i));
   8109  1.466  knakahar 		vlantag = wm_rxdesc_get_vlantag(rxq, i);
   8110  1.466  knakahar #ifdef WM_DEBUG
   8111  1.471  knakahar 		uint32_t rsshash = le32toh(wm_rxdesc_get_rsshash(rxq, i));
   8112  1.468      maya 		uint8_t rsstype = wm_rxdesc_get_rsstype(rxq, i);
   8113  1.466  knakahar #endif
   8114    1.1   thorpej 
   8115  1.483  knakahar 		if (!wm_rxdesc_dd(rxq, i, status)) {
   8116  1.483  knakahar 			/*
   8117  1.483  knakahar 			 * Update the receive pointer holding rxq_lock
   8118  1.483  knakahar 			 * consistent with increment counter.
   8119  1.483  knakahar 			 */
   8120  1.483  knakahar 			rxq->rxq_ptr = i;
   8121  1.281   msaitoh 			break;
   8122  1.483  knakahar 		}
   8123  1.189   msaitoh 
   8124  1.335   msaitoh 		count++;
   8125  1.356  knakahar 		if (__predict_false(rxq->rxq_discard)) {
   8126  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8127  1.281   msaitoh 			    ("%s: RX: discarding contents of descriptor %d\n",
   8128  1.281   msaitoh 			    device_xname(sc->sc_dev), i));
   8129  1.362  knakahar 			wm_init_rxdesc(rxq, i);
   8130  1.466  knakahar 			if (wm_rxdesc_is_eop(rxq, status)) {
   8131  1.281   msaitoh 				/* Reset our state. */
   8132  1.281   msaitoh 				DPRINTF(WM_DEBUG_RX,
   8133  1.281   msaitoh 				    ("%s: RX: resetting rxdiscard -> 0\n",
   8134  1.281   msaitoh 				    device_xname(sc->sc_dev)));
   8135  1.356  knakahar 				rxq->rxq_discard = 0;
   8136  1.281   msaitoh 			}
   8137  1.281   msaitoh 			continue;
   8138  1.189   msaitoh 		}
   8139  1.189   msaitoh 
   8140  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   8141  1.281   msaitoh 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   8142  1.189   msaitoh 
   8143  1.281   msaitoh 		m = rxs->rxs_mbuf;
   8144  1.189   msaitoh 
   8145  1.281   msaitoh 		/*
   8146  1.281   msaitoh 		 * Add a new receive buffer to the ring, unless of
   8147  1.281   msaitoh 		 * course the length is zero. Treat the latter as a
   8148  1.281   msaitoh 		 * failed mapping.
   8149  1.281   msaitoh 		 */
   8150  1.362  knakahar 		if ((len == 0) || (wm_add_rxbuf(rxq, i) != 0)) {
   8151  1.281   msaitoh 			/*
   8152  1.281   msaitoh 			 * Failed, throw away what we've done so
   8153  1.281   msaitoh 			 * far, and discard the rest of the packet.
   8154  1.281   msaitoh 			 */
   8155  1.281   msaitoh 			ifp->if_ierrors++;
   8156  1.281   msaitoh 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   8157  1.281   msaitoh 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   8158  1.362  knakahar 			wm_init_rxdesc(rxq, i);
   8159  1.466  knakahar 			if (!wm_rxdesc_is_eop(rxq, status))
   8160  1.356  knakahar 				rxq->rxq_discard = 1;
   8161  1.356  knakahar 			if (rxq->rxq_head != NULL)
   8162  1.356  knakahar 				m_freem(rxq->rxq_head);
   8163  1.356  knakahar 			WM_RXCHAIN_RESET(rxq);
   8164  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8165  1.281   msaitoh 			    ("%s: RX: Rx buffer allocation failed, "
   8166  1.281   msaitoh 			    "dropping packet%s\n", device_xname(sc->sc_dev),
   8167  1.366  knakahar 			    rxq->rxq_discard ? " (discard)" : ""));
   8168  1.281   msaitoh 			continue;
   8169  1.189   msaitoh 		}
   8170  1.253   msaitoh 
   8171  1.281   msaitoh 		m->m_len = len;
   8172  1.356  knakahar 		rxq->rxq_len += len;
   8173  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8174  1.281   msaitoh 		    ("%s: RX: buffer at %p len %d\n",
   8175  1.281   msaitoh 		    device_xname(sc->sc_dev), m->m_data, len));
   8176  1.145   msaitoh 
   8177  1.281   msaitoh 		/* If this is not the end of the packet, keep looking. */
   8178  1.466  knakahar 		if (!wm_rxdesc_is_eop(rxq, status)) {
   8179  1.356  knakahar 			WM_RXCHAIN_LINK(rxq, m);
   8180  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8181  1.281   msaitoh 			    ("%s: RX: not yet EOP, rxlen -> %d\n",
   8182  1.366  knakahar 			    device_xname(sc->sc_dev), rxq->rxq_len));
   8183  1.281   msaitoh 			continue;
   8184  1.281   msaitoh 		}
   8185   1.45   thorpej 
   8186  1.281   msaitoh 		/*
   8187  1.281   msaitoh 		 * Okay, we have the entire packet now.  The chip is
   8188  1.281   msaitoh 		 * configured to include the FCS except I350 and I21[01]
   8189  1.281   msaitoh 		 * (not all chips can be configured to strip it),
   8190  1.281   msaitoh 		 * so we need to trim it.
   8191  1.281   msaitoh 		 * May need to adjust length of previous mbuf in the
   8192  1.281   msaitoh 		 * chain if the current mbuf is too short.
   8193  1.281   msaitoh 		 * For an eratta, the RCTL_SECRC bit in RCTL register
   8194  1.281   msaitoh 		 * is always set in I350, so we don't trim it.
   8195  1.281   msaitoh 		 */
   8196  1.281   msaitoh 		if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I354)
   8197  1.281   msaitoh 		    && (sc->sc_type != WM_T_I210)
   8198  1.281   msaitoh 		    && (sc->sc_type != WM_T_I211)) {
   8199  1.281   msaitoh 			if (m->m_len < ETHER_CRC_LEN) {
   8200  1.356  knakahar 				rxq->rxq_tail->m_len
   8201  1.281   msaitoh 				    -= (ETHER_CRC_LEN - m->m_len);
   8202  1.281   msaitoh 				m->m_len = 0;
   8203  1.281   msaitoh 			} else
   8204  1.281   msaitoh 				m->m_len -= ETHER_CRC_LEN;
   8205  1.356  knakahar 			len = rxq->rxq_len - ETHER_CRC_LEN;
   8206  1.281   msaitoh 		} else
   8207  1.356  knakahar 			len = rxq->rxq_len;
   8208  1.117   msaitoh 
   8209  1.356  knakahar 		WM_RXCHAIN_LINK(rxq, m);
   8210  1.127    bouyer 
   8211  1.356  knakahar 		*rxq->rxq_tailp = NULL;
   8212  1.356  knakahar 		m = rxq->rxq_head;
   8213  1.117   msaitoh 
   8214  1.356  knakahar 		WM_RXCHAIN_RESET(rxq);
   8215   1.45   thorpej 
   8216  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8217  1.281   msaitoh 		    ("%s: RX: have entire packet, len -> %d\n",
   8218  1.281   msaitoh 		    device_xname(sc->sc_dev), len));
   8219   1.45   thorpej 
   8220  1.281   msaitoh 		/* If an error occurred, update stats and drop the packet. */
   8221  1.466  knakahar 		if (wm_rxdesc_has_errors(rxq, errors)) {
   8222  1.281   msaitoh 			m_freem(m);
   8223  1.281   msaitoh 			continue;
   8224   1.45   thorpej 		}
   8225   1.45   thorpej 
   8226  1.281   msaitoh 		/* No errors.  Receive the packet. */
   8227  1.412     ozaki 		m_set_rcvif(m, ifp);
   8228  1.281   msaitoh 		m->m_pkthdr.len = len;
   8229  1.471  knakahar 		/*
   8230  1.471  knakahar 		 * TODO
   8231  1.471  knakahar 		 * should be save rsshash and rsstype to this mbuf.
   8232  1.471  knakahar 		 */
   8233  1.471  knakahar 		DPRINTF(WM_DEBUG_RX,
   8234  1.471  knakahar 		    ("%s: RX: RSS type=%" PRIu8 ", RSS hash=%" PRIu32 "\n",
   8235  1.471  knakahar 			device_xname(sc->sc_dev), rsstype, rsshash));
   8236   1.45   thorpej 
   8237  1.281   msaitoh 		/*
   8238  1.281   msaitoh 		 * If VLANs are enabled, VLAN packets have been unwrapped
   8239  1.281   msaitoh 		 * for us.  Associate the tag with the packet.
   8240  1.281   msaitoh 		 */
   8241  1.466  knakahar 		if (!wm_rxdesc_input_vlantag(rxq, status, vlantag, m))
   8242  1.466  knakahar 			continue;
   8243   1.45   thorpej 
   8244  1.281   msaitoh 		/* Set up checksum info for this packet. */
   8245  1.466  knakahar 		wm_rxdesc_ensure_checksum(rxq, status, errors, m);
   8246  1.483  knakahar 		/*
   8247  1.483  knakahar 		 * Update the receive pointer holding rxq_lock consistent with
   8248  1.483  knakahar 		 * increment counter.
   8249  1.483  knakahar 		 */
   8250  1.483  knakahar 		rxq->rxq_ptr = i;
   8251  1.495  knakahar 		rxq->rxq_packets++;
   8252  1.495  knakahar 		rxq->rxq_bytes += len;
   8253  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   8254   1.45   thorpej 
   8255  1.281   msaitoh 		/* Pass it on. */
   8256  1.391     ozaki 		if_percpuq_enqueue(sc->sc_ipq, m);
   8257   1.46   thorpej 
   8258  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   8259   1.46   thorpej 
   8260  1.429  knakahar 		if (rxq->rxq_stopping)
   8261  1.281   msaitoh 			break;
   8262   1.48   thorpej 	}
   8263  1.281   msaitoh 
   8264  1.335   msaitoh 	if (count != 0)
   8265  1.335   msaitoh 		rnd_add_uint32(&sc->rnd_source, count);
   8266  1.281   msaitoh 
   8267  1.281   msaitoh 	DPRINTF(WM_DEBUG_RX,
   8268  1.281   msaitoh 	    ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i));
   8269   1.48   thorpej }
   8270   1.48   thorpej 
   8271   1.48   thorpej /*
   8272  1.281   msaitoh  * wm_linkintr_gmii:
   8273   1.50   thorpej  *
   8274  1.281   msaitoh  *	Helper; handle link interrupts for GMII.
   8275   1.50   thorpej  */
   8276  1.281   msaitoh static void
   8277  1.281   msaitoh wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
   8278   1.50   thorpej {
   8279   1.51   thorpej 
   8280  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   8281  1.281   msaitoh 
   8282  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8283  1.281   msaitoh 		__func__));
   8284  1.281   msaitoh 
   8285  1.281   msaitoh 	if (icr & ICR_LSC) {
   8286  1.445   msaitoh 		uint32_t reg;
   8287  1.381   msaitoh 		uint32_t status = CSR_READ(sc, WMREG_STATUS);
   8288  1.381   msaitoh 
   8289  1.381   msaitoh 		if ((sc->sc_type == WM_T_ICH8) && ((status & STATUS_LU) == 0))
   8290  1.381   msaitoh 			wm_gig_downshift_workaround_ich8lan(sc);
   8291  1.381   msaitoh 
   8292  1.381   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> mii_pollstat\n",
   8293  1.281   msaitoh 			device_xname(sc->sc_dev)));
   8294  1.281   msaitoh 		mii_pollstat(&sc->sc_mii);
   8295  1.281   msaitoh 		if (sc->sc_type == WM_T_82543) {
   8296  1.281   msaitoh 			int miistatus, active;
   8297  1.281   msaitoh 
   8298  1.281   msaitoh 			/*
   8299  1.281   msaitoh 			 * With 82543, we need to force speed and
   8300  1.281   msaitoh 			 * duplex on the MAC equal to what the PHY
   8301  1.281   msaitoh 			 * speed and duplex configuration is.
   8302  1.281   msaitoh 			 */
   8303  1.281   msaitoh 			miistatus = sc->sc_mii.mii_media_status;
   8304   1.50   thorpej 
   8305  1.281   msaitoh 			if (miistatus & IFM_ACTIVE) {
   8306  1.281   msaitoh 				active = sc->sc_mii.mii_media_active;
   8307  1.281   msaitoh 				sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
   8308  1.281   msaitoh 				switch (IFM_SUBTYPE(active)) {
   8309  1.281   msaitoh 				case IFM_10_T:
   8310  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_10;
   8311  1.281   msaitoh 					break;
   8312  1.281   msaitoh 				case IFM_100_TX:
   8313  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_100;
   8314  1.281   msaitoh 					break;
   8315  1.281   msaitoh 				case IFM_1000_T:
   8316  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_1000;
   8317  1.281   msaitoh 					break;
   8318  1.281   msaitoh 				default:
   8319  1.281   msaitoh 					/*
   8320  1.281   msaitoh 					 * fiber?
   8321  1.281   msaitoh 					 * Shoud not enter here.
   8322  1.281   msaitoh 					 */
   8323  1.388   msaitoh 					printf("unknown media (%x)\n", active);
   8324  1.281   msaitoh 					break;
   8325  1.281   msaitoh 				}
   8326  1.281   msaitoh 				if (active & IFM_FDX)
   8327  1.281   msaitoh 					sc->sc_ctrl |= CTRL_FD;
   8328  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   8329  1.281   msaitoh 			}
   8330  1.281   msaitoh 		} else if ((sc->sc_type == WM_T_ICH8)
   8331  1.281   msaitoh 		    && (sc->sc_phytype == WMPHY_IGP_3)) {
   8332  1.281   msaitoh 			wm_kmrn_lock_loss_workaround_ich8lan(sc);
   8333  1.281   msaitoh 		} else if (sc->sc_type == WM_T_PCH) {
   8334  1.281   msaitoh 			wm_k1_gig_workaround_hv(sc,
   8335  1.281   msaitoh 			    ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
   8336  1.230   msaitoh 		}
   8337   1.51   thorpej 
   8338  1.281   msaitoh 		if ((sc->sc_phytype == WMPHY_82578)
   8339  1.281   msaitoh 		    && (IFM_SUBTYPE(sc->sc_mii.mii_media_active)
   8340  1.281   msaitoh 			== IFM_1000_T)) {
   8341   1.51   thorpej 
   8342  1.281   msaitoh 			if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0) {
   8343  1.281   msaitoh 				delay(200*1000); /* XXX too big */
   8344   1.51   thorpej 
   8345  1.281   msaitoh 				/* Link stall fix for link up */
   8346  1.281   msaitoh 				wm_gmii_hv_writereg(sc->sc_dev, 1,
   8347  1.281   msaitoh 				    HV_MUX_DATA_CTRL,
   8348  1.281   msaitoh 				    HV_MUX_DATA_CTRL_GEN_TO_MAC
   8349  1.281   msaitoh 				    | HV_MUX_DATA_CTRL_FORCE_SPEED);
   8350  1.281   msaitoh 				wm_gmii_hv_writereg(sc->sc_dev, 1,
   8351  1.281   msaitoh 				    HV_MUX_DATA_CTRL,
   8352  1.281   msaitoh 				    HV_MUX_DATA_CTRL_GEN_TO_MAC);
   8353  1.281   msaitoh 			}
   8354  1.281   msaitoh 		}
   8355  1.445   msaitoh 		/*
   8356  1.445   msaitoh 		 * I217 Packet Loss issue:
   8357  1.445   msaitoh 		 * ensure that FEXTNVM4 Beacon Duration is set correctly
   8358  1.445   msaitoh 		 * on power up.
   8359  1.445   msaitoh 		 * Set the Beacon Duration for I217 to 8 usec
   8360  1.445   msaitoh 		 */
   8361  1.445   msaitoh 		if ((sc->sc_type == WM_T_PCH_LPT)
   8362  1.445   msaitoh 		    || (sc->sc_type == WM_T_PCH_SPT)) {
   8363  1.445   msaitoh 			reg = CSR_READ(sc, WMREG_FEXTNVM4);
   8364  1.445   msaitoh 			reg &= ~FEXTNVM4_BEACON_DURATION;
   8365  1.445   msaitoh 			reg |= FEXTNVM4_BEACON_DURATION_8US;
   8366  1.445   msaitoh 			CSR_WRITE(sc, WMREG_FEXTNVM4, reg);
   8367  1.445   msaitoh 		}
   8368  1.445   msaitoh 
   8369  1.445   msaitoh 		/* XXX Work-around I218 hang issue */
   8370  1.445   msaitoh 		/* e1000_k1_workaround_lpt_lp() */
   8371  1.445   msaitoh 
   8372  1.445   msaitoh 		if ((sc->sc_type == WM_T_PCH_LPT)
   8373  1.445   msaitoh 		    || (sc->sc_type == WM_T_PCH_SPT)) {
   8374  1.445   msaitoh 			/*
   8375  1.445   msaitoh 			 * Set platform power management values for Latency
   8376  1.445   msaitoh 			 * Tolerance Reporting (LTR)
   8377  1.445   msaitoh 			 */
   8378  1.445   msaitoh 			wm_platform_pm_pch_lpt(sc,
   8379  1.445   msaitoh 				((sc->sc_mii.mii_media_status & IFM_ACTIVE)
   8380  1.445   msaitoh 				    != 0));
   8381  1.445   msaitoh 		}
   8382  1.445   msaitoh 
   8383  1.445   msaitoh 		/* FEXTNVM6 K1-off workaround */
   8384  1.445   msaitoh 		if (sc->sc_type == WM_T_PCH_SPT) {
   8385  1.445   msaitoh 			reg = CSR_READ(sc, WMREG_FEXTNVM6);
   8386  1.445   msaitoh 			if (CSR_READ(sc, WMREG_PCIEANACFG)
   8387  1.445   msaitoh 			    & FEXTNVM6_K1_OFF_ENABLE)
   8388  1.445   msaitoh 				reg |= FEXTNVM6_K1_OFF_ENABLE;
   8389  1.445   msaitoh 			else
   8390  1.445   msaitoh 				reg &= ~FEXTNVM6_K1_OFF_ENABLE;
   8391  1.445   msaitoh 			CSR_WRITE(sc, WMREG_FEXTNVM6, reg);
   8392  1.445   msaitoh 		}
   8393  1.281   msaitoh 	} else if (icr & ICR_RXSEQ) {
   8394  1.388   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK Receive sequence error\n",
   8395  1.281   msaitoh 			device_xname(sc->sc_dev)));
   8396   1.51   thorpej 	}
   8397   1.50   thorpej }
   8398   1.50   thorpej 
   8399   1.50   thorpej /*
   8400  1.281   msaitoh  * wm_linkintr_tbi:
   8401   1.57   thorpej  *
   8402  1.281   msaitoh  *	Helper; handle link interrupts for TBI mode.
   8403   1.57   thorpej  */
   8404  1.281   msaitoh static void
   8405  1.281   msaitoh wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
   8406   1.57   thorpej {
   8407  1.506   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8408  1.281   msaitoh 	uint32_t status;
   8409  1.281   msaitoh 
   8410  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8411  1.281   msaitoh 		__func__));
   8412  1.281   msaitoh 
   8413  1.281   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   8414  1.281   msaitoh 	if (icr & ICR_LSC) {
   8415  1.281   msaitoh 		if (status & STATUS_LU) {
   8416  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
   8417  1.281   msaitoh 			    device_xname(sc->sc_dev),
   8418  1.281   msaitoh 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   8419  1.281   msaitoh 			/*
   8420  1.281   msaitoh 			 * NOTE: CTRL will update TFCE and RFCE automatically,
   8421  1.281   msaitoh 			 * so we should update sc->sc_ctrl
   8422  1.281   msaitoh 			 */
   8423   1.57   thorpej 
   8424  1.281   msaitoh 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   8425  1.281   msaitoh 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   8426  1.281   msaitoh 			sc->sc_fcrtl &= ~FCRTL_XONE;
   8427  1.281   msaitoh 			if (status & STATUS_FD)
   8428  1.281   msaitoh 				sc->sc_tctl |=
   8429  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   8430  1.281   msaitoh 			else
   8431  1.281   msaitoh 				sc->sc_tctl |=
   8432  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   8433  1.281   msaitoh 			if (sc->sc_ctrl & CTRL_TFCE)
   8434  1.281   msaitoh 				sc->sc_fcrtl |= FCRTL_XONE;
   8435  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   8436  1.281   msaitoh 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   8437  1.281   msaitoh 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   8438  1.281   msaitoh 				      sc->sc_fcrtl);
   8439  1.281   msaitoh 			sc->sc_tbi_linkup = 1;
   8440  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_UP);
   8441  1.281   msaitoh 		} else {
   8442  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   8443  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   8444  1.281   msaitoh 			sc->sc_tbi_linkup = 0;
   8445  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_DOWN);
   8446  1.281   msaitoh 		}
   8447  1.325   msaitoh 		/* Update LED */
   8448  1.325   msaitoh 		wm_tbi_serdes_set_linkled(sc);
   8449  1.281   msaitoh 	} else if (icr & ICR_RXSEQ) {
   8450  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   8451  1.281   msaitoh 		    ("%s: LINK: Receive sequence error\n",
   8452  1.281   msaitoh 		    device_xname(sc->sc_dev)));
   8453   1.57   thorpej 	}
   8454   1.57   thorpej }
   8455   1.57   thorpej 
   8456   1.57   thorpej /*
   8457  1.325   msaitoh  * wm_linkintr_serdes:
   8458  1.325   msaitoh  *
   8459  1.325   msaitoh  *	Helper; handle link interrupts for TBI mode.
   8460  1.325   msaitoh  */
   8461  1.325   msaitoh static void
   8462  1.325   msaitoh wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
   8463  1.325   msaitoh {
   8464  1.506   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8465  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   8466  1.325   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   8467  1.325   msaitoh 	uint32_t pcs_adv, pcs_lpab, reg;
   8468  1.325   msaitoh 
   8469  1.325   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8470  1.325   msaitoh 		__func__));
   8471  1.325   msaitoh 
   8472  1.325   msaitoh 	if (icr & ICR_LSC) {
   8473  1.325   msaitoh 		/* Check PCS */
   8474  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_LSTS);
   8475  1.325   msaitoh 		if ((reg & PCS_LSTS_LINKOK) != 0) {
   8476  1.506   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up\n",
   8477  1.506   msaitoh 				device_xname(sc->sc_dev)));
   8478  1.325   msaitoh 			mii->mii_media_status |= IFM_ACTIVE;
   8479  1.325   msaitoh 			sc->sc_tbi_linkup = 1;
   8480  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_UP);
   8481  1.325   msaitoh 		} else {
   8482  1.506   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   8483  1.506   msaitoh 				device_xname(sc->sc_dev)));
   8484  1.325   msaitoh 			mii->mii_media_status |= IFM_NONE;
   8485  1.325   msaitoh 			sc->sc_tbi_linkup = 0;
   8486  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_DOWN);
   8487  1.325   msaitoh 			wm_tbi_serdes_set_linkled(sc);
   8488  1.325   msaitoh 			return;
   8489  1.325   msaitoh 		}
   8490  1.325   msaitoh 		mii->mii_media_active |= IFM_1000_SX;
   8491  1.325   msaitoh 		if ((reg & PCS_LSTS_FDX) != 0)
   8492  1.325   msaitoh 			mii->mii_media_active |= IFM_FDX;
   8493  1.325   msaitoh 		else
   8494  1.325   msaitoh 			mii->mii_media_active |= IFM_HDX;
   8495  1.325   msaitoh 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   8496  1.325   msaitoh 			/* Check flow */
   8497  1.325   msaitoh 			reg = CSR_READ(sc, WMREG_PCS_LSTS);
   8498  1.325   msaitoh 			if ((reg & PCS_LSTS_AN_COMP) == 0) {
   8499  1.325   msaitoh 				DPRINTF(WM_DEBUG_LINK,
   8500  1.325   msaitoh 				    ("XXX LINKOK but not ACOMP\n"));
   8501  1.325   msaitoh 				return;
   8502  1.325   msaitoh 			}
   8503  1.325   msaitoh 			pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
   8504  1.325   msaitoh 			pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
   8505  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   8506  1.325   msaitoh 			    ("XXX AN result %08x, %08x\n", pcs_adv, pcs_lpab));
   8507  1.325   msaitoh 			if ((pcs_adv & TXCW_SYM_PAUSE)
   8508  1.325   msaitoh 			    && (pcs_lpab & TXCW_SYM_PAUSE)) {
   8509  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8510  1.325   msaitoh 				    | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   8511  1.325   msaitoh 			} else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
   8512  1.325   msaitoh 			    && (pcs_adv & TXCW_ASYM_PAUSE)
   8513  1.325   msaitoh 			    && (pcs_lpab & TXCW_SYM_PAUSE)
   8514  1.325   msaitoh 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
   8515  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8516  1.325   msaitoh 				    | IFM_ETH_TXPAUSE;
   8517  1.325   msaitoh 			else if ((pcs_adv & TXCW_SYM_PAUSE)
   8518  1.325   msaitoh 			    && (pcs_adv & TXCW_ASYM_PAUSE)
   8519  1.325   msaitoh 			    && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
   8520  1.325   msaitoh 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
   8521  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8522  1.325   msaitoh 				    | IFM_ETH_RXPAUSE;
   8523  1.325   msaitoh 		}
   8524  1.325   msaitoh 		/* Update LED */
   8525  1.325   msaitoh 		wm_tbi_serdes_set_linkled(sc);
   8526  1.325   msaitoh 	} else {
   8527  1.325   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   8528  1.325   msaitoh 		    ("%s: LINK: Receive sequence error\n",
   8529  1.325   msaitoh 		    device_xname(sc->sc_dev)));
   8530  1.325   msaitoh 	}
   8531  1.325   msaitoh }
   8532  1.325   msaitoh 
   8533  1.325   msaitoh /*
   8534  1.281   msaitoh  * wm_linkintr:
   8535   1.57   thorpej  *
   8536  1.281   msaitoh  *	Helper; handle link interrupts.
   8537   1.57   thorpej  */
   8538  1.281   msaitoh static void
   8539  1.281   msaitoh wm_linkintr(struct wm_softc *sc, uint32_t icr)
   8540   1.57   thorpej {
   8541   1.57   thorpej 
   8542  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   8543  1.357  knakahar 
   8544  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   8545  1.281   msaitoh 		wm_linkintr_gmii(sc, icr);
   8546  1.325   msaitoh 	else if ((sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   8547  1.332   msaitoh 	    && (sc->sc_type >= WM_T_82575))
   8548  1.325   msaitoh 		wm_linkintr_serdes(sc, icr);
   8549  1.281   msaitoh 	else
   8550  1.281   msaitoh 		wm_linkintr_tbi(sc, icr);
   8551   1.57   thorpej }
   8552   1.57   thorpej 
   8553  1.112     gavan /*
   8554  1.335   msaitoh  * wm_intr_legacy:
   8555  1.112     gavan  *
   8556  1.335   msaitoh  *	Interrupt service routine for INTx and MSI.
   8557  1.112     gavan  */
   8558  1.112     gavan static int
   8559  1.335   msaitoh wm_intr_legacy(void *arg)
   8560  1.198   msaitoh {
   8561  1.281   msaitoh 	struct wm_softc *sc = arg;
   8562  1.484  knakahar 	struct wm_queue *wmq = &sc->sc_queue[0];
   8563  1.484  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   8564  1.484  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   8565  1.335   msaitoh 	uint32_t icr, rndval = 0;
   8566  1.281   msaitoh 	int handled = 0;
   8567  1.281   msaitoh 
   8568  1.281   msaitoh 	while (1 /* CONSTCOND */) {
   8569  1.281   msaitoh 		icr = CSR_READ(sc, WMREG_ICR);
   8570  1.281   msaitoh 		if ((icr & sc->sc_icr) == 0)
   8571  1.281   msaitoh 			break;
   8572  1.511   msaitoh 		if (handled == 0) {
   8573  1.511   msaitoh 			DPRINTF(WM_DEBUG_TX,
   8574  1.517   msaitoh 			    ("%s: INTx: got intr\n",device_xname(sc->sc_dev)));
   8575  1.511   msaitoh 		}
   8576  1.335   msaitoh 		if (rndval == 0)
   8577  1.335   msaitoh 			rndval = icr;
   8578  1.112     gavan 
   8579  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   8580  1.112     gavan 
   8581  1.429  knakahar 		if (rxq->rxq_stopping) {
   8582  1.413     skrll 			mutex_exit(rxq->rxq_lock);
   8583  1.281   msaitoh 			break;
   8584  1.281   msaitoh 		}
   8585  1.247   msaitoh 
   8586  1.281   msaitoh 		handled = 1;
   8587  1.249   msaitoh 
   8588  1.281   msaitoh #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   8589  1.388   msaitoh 		if (icr & (ICR_RXDMT0 | ICR_RXT0)) {
   8590  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8591  1.281   msaitoh 			    ("%s: RX: got Rx intr 0x%08x\n",
   8592  1.281   msaitoh 			    device_xname(sc->sc_dev),
   8593  1.388   msaitoh 			    icr & (ICR_RXDMT0 | ICR_RXT0)));
   8594  1.417  knakahar 			WM_Q_EVCNT_INCR(rxq, rxintr);
   8595  1.240   msaitoh 		}
   8596  1.281   msaitoh #endif
   8597  1.493  knakahar 		wm_rxeof(rxq, UINT_MAX);
   8598  1.240   msaitoh 
   8599  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   8600  1.413     skrll 		mutex_enter(txq->txq_lock);
   8601  1.283     ozaki 
   8602  1.429  knakahar 		if (txq->txq_stopping) {
   8603  1.429  knakahar 			mutex_exit(txq->txq_lock);
   8604  1.429  knakahar 			break;
   8605  1.429  knakahar 		}
   8606  1.429  knakahar 
   8607  1.281   msaitoh #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   8608  1.281   msaitoh 		if (icr & ICR_TXDW) {
   8609  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   8610  1.281   msaitoh 			    ("%s: TX: got TXDW interrupt\n",
   8611  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   8612  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdw);
   8613  1.240   msaitoh 		}
   8614  1.281   msaitoh #endif
   8615  1.403  knakahar 		wm_txeof(sc, txq);
   8616  1.240   msaitoh 
   8617  1.413     skrll 		mutex_exit(txq->txq_lock);
   8618  1.357  knakahar 		WM_CORE_LOCK(sc);
   8619  1.357  knakahar 
   8620  1.429  knakahar 		if (sc->sc_core_stopping) {
   8621  1.429  knakahar 			WM_CORE_UNLOCK(sc);
   8622  1.429  knakahar 			break;
   8623  1.429  knakahar 		}
   8624  1.429  knakahar 
   8625  1.388   msaitoh 		if (icr & (ICR_LSC | ICR_RXSEQ)) {
   8626  1.281   msaitoh 			WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   8627  1.281   msaitoh 			wm_linkintr(sc, icr);
   8628  1.281   msaitoh 		}
   8629  1.240   msaitoh 
   8630  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   8631  1.112     gavan 
   8632  1.281   msaitoh 		if (icr & ICR_RXO) {
   8633  1.281   msaitoh #if defined(WM_DEBUG)
   8634  1.281   msaitoh 			log(LOG_WARNING, "%s: Receive overrun\n",
   8635  1.281   msaitoh 			    device_xname(sc->sc_dev));
   8636  1.281   msaitoh #endif /* defined(WM_DEBUG) */
   8637  1.281   msaitoh 		}
   8638  1.249   msaitoh 	}
   8639  1.112     gavan 
   8640  1.335   msaitoh 	rnd_add_uint32(&sc->rnd_source, rndval);
   8641  1.335   msaitoh 
   8642  1.335   msaitoh 	if (handled) {
   8643  1.335   msaitoh 		/* Try to get more packets going. */
   8644  1.484  knakahar 		softint_schedule(wmq->wmq_si);
   8645  1.335   msaitoh 	}
   8646  1.335   msaitoh 
   8647  1.335   msaitoh 	return handled;
   8648  1.335   msaitoh }
   8649  1.335   msaitoh 
   8650  1.480  knakahar static inline void
   8651  1.480  knakahar wm_txrxintr_disable(struct wm_queue *wmq)
   8652  1.480  knakahar {
   8653  1.480  knakahar 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
   8654  1.480  knakahar 
   8655  1.480  knakahar 	if (sc->sc_type == WM_T_82574)
   8656  1.480  knakahar 		CSR_WRITE(sc, WMREG_IMC, ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id));
   8657  1.480  knakahar 	else if (sc->sc_type == WM_T_82575)
   8658  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMC, EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
   8659  1.480  knakahar 	else
   8660  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMC, 1 << wmq->wmq_intr_idx);
   8661  1.480  knakahar }
   8662  1.480  knakahar 
   8663  1.480  knakahar static inline void
   8664  1.480  knakahar wm_txrxintr_enable(struct wm_queue *wmq)
   8665  1.480  knakahar {
   8666  1.480  knakahar 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
   8667  1.480  knakahar 
   8668  1.495  knakahar 	wm_itrs_calculate(sc, wmq);
   8669  1.495  knakahar 
   8670  1.480  knakahar 	if (sc->sc_type == WM_T_82574)
   8671  1.480  knakahar 		CSR_WRITE(sc, WMREG_IMS, ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id));
   8672  1.480  knakahar 	else if (sc->sc_type == WM_T_82575)
   8673  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMS, EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
   8674  1.480  knakahar 	else
   8675  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMS, 1 << wmq->wmq_intr_idx);
   8676  1.480  knakahar }
   8677  1.480  knakahar 
   8678  1.335   msaitoh static int
   8679  1.405  knakahar wm_txrxintr_msix(void *arg)
   8680  1.335   msaitoh {
   8681  1.405  knakahar 	struct wm_queue *wmq = arg;
   8682  1.405  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   8683  1.405  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   8684  1.363  knakahar 	struct wm_softc *sc = txq->txq_sc;
   8685  1.493  knakahar 	u_int limit = sc->sc_rx_intr_process_limit;
   8686  1.335   msaitoh 
   8687  1.405  knakahar 	KASSERT(wmq->wmq_intr_idx == wmq->wmq_id);
   8688  1.405  knakahar 
   8689  1.335   msaitoh 	DPRINTF(WM_DEBUG_TX,
   8690  1.335   msaitoh 	    ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev)));
   8691  1.335   msaitoh 
   8692  1.480  knakahar 	wm_txrxintr_disable(wmq);
   8693  1.335   msaitoh 
   8694  1.429  knakahar 	mutex_enter(txq->txq_lock);
   8695  1.429  knakahar 
   8696  1.429  knakahar 	if (txq->txq_stopping) {
   8697  1.429  knakahar 		mutex_exit(txq->txq_lock);
   8698  1.429  knakahar 		return 0;
   8699  1.429  knakahar 	}
   8700  1.335   msaitoh 
   8701  1.429  knakahar 	WM_Q_EVCNT_INCR(txq, txdw);
   8702  1.429  knakahar 	wm_txeof(sc, txq);
   8703  1.484  knakahar 	/* wm_deferred start() is done in wm_handle_queue(). */
   8704  1.429  knakahar 	mutex_exit(txq->txq_lock);
   8705  1.429  knakahar 
   8706  1.364  knakahar 	DPRINTF(WM_DEBUG_RX,
   8707  1.335   msaitoh 	    ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev)));
   8708  1.429  knakahar 	mutex_enter(rxq->rxq_lock);
   8709  1.335   msaitoh 
   8710  1.429  knakahar 	if (rxq->rxq_stopping) {
   8711  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   8712  1.429  knakahar 		return 0;
   8713  1.405  knakahar 	}
   8714  1.335   msaitoh 
   8715  1.429  knakahar 	WM_Q_EVCNT_INCR(rxq, rxintr);
   8716  1.493  knakahar 	wm_rxeof(rxq, limit);
   8717  1.429  knakahar 	mutex_exit(rxq->rxq_lock);
   8718  1.429  knakahar 
   8719  1.495  knakahar 	wm_itrs_writereg(sc, wmq);
   8720  1.495  knakahar 
   8721  1.484  knakahar 	softint_schedule(wmq->wmq_si);
   8722  1.484  knakahar 
   8723  1.335   msaitoh 	return 1;
   8724  1.335   msaitoh }
   8725  1.335   msaitoh 
   8726  1.484  knakahar static void
   8727  1.484  knakahar wm_handle_queue(void *arg)
   8728  1.484  knakahar {
   8729  1.484  knakahar 	struct wm_queue *wmq = arg;
   8730  1.484  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   8731  1.484  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   8732  1.484  knakahar 	struct wm_softc *sc = txq->txq_sc;
   8733  1.493  knakahar 	u_int limit = sc->sc_rx_process_limit;
   8734  1.484  knakahar 
   8735  1.484  knakahar 	mutex_enter(txq->txq_lock);
   8736  1.484  knakahar 	if (txq->txq_stopping) {
   8737  1.484  knakahar 		mutex_exit(txq->txq_lock);
   8738  1.484  knakahar 		return;
   8739  1.484  knakahar 	}
   8740  1.484  knakahar 	wm_txeof(sc, txq);
   8741  1.484  knakahar 	wm_deferred_start_locked(txq);
   8742  1.484  knakahar 	mutex_exit(txq->txq_lock);
   8743  1.484  knakahar 
   8744  1.484  knakahar 	mutex_enter(rxq->rxq_lock);
   8745  1.484  knakahar 	if (rxq->rxq_stopping) {
   8746  1.484  knakahar 		mutex_exit(rxq->rxq_lock);
   8747  1.484  knakahar 		return;
   8748  1.484  knakahar 	}
   8749  1.484  knakahar 	WM_Q_EVCNT_INCR(rxq, rxintr);
   8750  1.493  knakahar 	wm_rxeof(rxq, limit);
   8751  1.484  knakahar 	mutex_exit(rxq->rxq_lock);
   8752  1.493  knakahar 
   8753  1.493  knakahar 	wm_txrxintr_enable(wmq);
   8754  1.484  knakahar }
   8755  1.484  knakahar 
   8756  1.335   msaitoh /*
   8757  1.335   msaitoh  * wm_linkintr_msix:
   8758  1.335   msaitoh  *
   8759  1.335   msaitoh  *	Interrupt service routine for link status change for MSI-X.
   8760  1.335   msaitoh  */
   8761  1.335   msaitoh static int
   8762  1.335   msaitoh wm_linkintr_msix(void *arg)
   8763  1.335   msaitoh {
   8764  1.335   msaitoh 	struct wm_softc *sc = arg;
   8765  1.351   msaitoh 	uint32_t reg;
   8766  1.335   msaitoh 
   8767  1.369  knakahar 	DPRINTF(WM_DEBUG_LINK,
   8768  1.335   msaitoh 	    ("%s: LINK: got link intr\n", device_xname(sc->sc_dev)));
   8769  1.335   msaitoh 
   8770  1.351   msaitoh 	reg = CSR_READ(sc, WMREG_ICR);
   8771  1.357  knakahar 	WM_CORE_LOCK(sc);
   8772  1.429  knakahar 	if ((sc->sc_core_stopping) || ((reg & ICR_LSC) == 0))
   8773  1.335   msaitoh 		goto out;
   8774  1.335   msaitoh 
   8775  1.335   msaitoh 	WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   8776  1.335   msaitoh 	wm_linkintr(sc, ICR_LSC);
   8777  1.335   msaitoh 
   8778  1.335   msaitoh out:
   8779  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   8780  1.335   msaitoh 
   8781  1.335   msaitoh 	if (sc->sc_type == WM_T_82574)
   8782  1.388   msaitoh 		CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC);
   8783  1.335   msaitoh 	else if (sc->sc_type == WM_T_82575)
   8784  1.335   msaitoh 		CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER);
   8785  1.335   msaitoh 	else
   8786  1.364  knakahar 		CSR_WRITE(sc, WMREG_EIMS, 1 << sc->sc_link_intr_idx);
   8787  1.335   msaitoh 
   8788  1.335   msaitoh 	return 1;
   8789  1.335   msaitoh }
   8790  1.335   msaitoh 
   8791  1.335   msaitoh /*
   8792  1.281   msaitoh  * Media related.
   8793  1.281   msaitoh  * GMII, SGMII, TBI (and SERDES)
   8794  1.281   msaitoh  */
   8795  1.117   msaitoh 
   8796  1.325   msaitoh /* Common */
   8797  1.325   msaitoh 
   8798  1.325   msaitoh /*
   8799  1.325   msaitoh  * wm_tbi_serdes_set_linkled:
   8800  1.325   msaitoh  *
   8801  1.325   msaitoh  *	Update the link LED on TBI and SERDES devices.
   8802  1.325   msaitoh  */
   8803  1.325   msaitoh static void
   8804  1.325   msaitoh wm_tbi_serdes_set_linkled(struct wm_softc *sc)
   8805  1.325   msaitoh {
   8806  1.325   msaitoh 
   8807  1.325   msaitoh 	if (sc->sc_tbi_linkup)
   8808  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SWDPIN(0);
   8809  1.325   msaitoh 	else
   8810  1.325   msaitoh 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
   8811  1.325   msaitoh 
   8812  1.325   msaitoh 	/* 82540 or newer devices are active low */
   8813  1.325   msaitoh 	sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0;
   8814  1.325   msaitoh 
   8815  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   8816  1.325   msaitoh }
   8817  1.325   msaitoh 
   8818  1.281   msaitoh /* GMII related */
   8819  1.117   msaitoh 
   8820  1.280   msaitoh /*
   8821  1.281   msaitoh  * wm_gmii_reset:
   8822  1.280   msaitoh  *
   8823  1.281   msaitoh  *	Reset the PHY.
   8824  1.280   msaitoh  */
   8825  1.281   msaitoh static void
   8826  1.281   msaitoh wm_gmii_reset(struct wm_softc *sc)
   8827  1.280   msaitoh {
   8828  1.281   msaitoh 	uint32_t reg;
   8829  1.280   msaitoh 	int rv;
   8830  1.280   msaitoh 
   8831  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   8832  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   8833  1.420   msaitoh 
   8834  1.424   msaitoh 	rv = sc->phy.acquire(sc);
   8835  1.281   msaitoh 	if (rv != 0) {
   8836  1.281   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   8837  1.281   msaitoh 		    __func__);
   8838  1.281   msaitoh 		return;
   8839  1.281   msaitoh 	}
   8840  1.280   msaitoh 
   8841  1.281   msaitoh 	switch (sc->sc_type) {
   8842  1.281   msaitoh 	case WM_T_82542_2_0:
   8843  1.281   msaitoh 	case WM_T_82542_2_1:
   8844  1.281   msaitoh 		/* null */
   8845  1.281   msaitoh 		break;
   8846  1.281   msaitoh 	case WM_T_82543:
   8847  1.281   msaitoh 		/*
   8848  1.281   msaitoh 		 * With 82543, we need to force speed and duplex on the MAC
   8849  1.281   msaitoh 		 * equal to what the PHY speed and duplex configuration is.
   8850  1.281   msaitoh 		 * In addition, we need to perform a hardware reset on the PHY
   8851  1.281   msaitoh 		 * to take it out of reset.
   8852  1.281   msaitoh 		 */
   8853  1.281   msaitoh 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
   8854  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   8855  1.280   msaitoh 
   8856  1.281   msaitoh 		/* The PHY reset pin is active-low. */
   8857  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   8858  1.281   msaitoh 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
   8859  1.281   msaitoh 		    CTRL_EXT_SWDPIN(4));
   8860  1.281   msaitoh 		reg |= CTRL_EXT_SWDPIO(4);
   8861  1.218   msaitoh 
   8862  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   8863  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   8864  1.281   msaitoh 		delay(10*1000);
   8865  1.218   msaitoh 
   8866  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   8867  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   8868  1.281   msaitoh 		delay(150);
   8869  1.281   msaitoh #if 0
   8870  1.281   msaitoh 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
   8871  1.281   msaitoh #endif
   8872  1.281   msaitoh 		delay(20*1000);	/* XXX extra delay to get PHY ID? */
   8873  1.281   msaitoh 		break;
   8874  1.281   msaitoh 	case WM_T_82544:	/* reset 10000us */
   8875  1.281   msaitoh 	case WM_T_82540:
   8876  1.281   msaitoh 	case WM_T_82545:
   8877  1.281   msaitoh 	case WM_T_82545_3:
   8878  1.281   msaitoh 	case WM_T_82546:
   8879  1.281   msaitoh 	case WM_T_82546_3:
   8880  1.281   msaitoh 	case WM_T_82541:
   8881  1.281   msaitoh 	case WM_T_82541_2:
   8882  1.281   msaitoh 	case WM_T_82547:
   8883  1.281   msaitoh 	case WM_T_82547_2:
   8884  1.281   msaitoh 	case WM_T_82571:	/* reset 100us */
   8885  1.281   msaitoh 	case WM_T_82572:
   8886  1.281   msaitoh 	case WM_T_82573:
   8887  1.281   msaitoh 	case WM_T_82574:
   8888  1.281   msaitoh 	case WM_T_82575:
   8889  1.281   msaitoh 	case WM_T_82576:
   8890  1.218   msaitoh 	case WM_T_82580:
   8891  1.228   msaitoh 	case WM_T_I350:
   8892  1.265   msaitoh 	case WM_T_I354:
   8893  1.281   msaitoh 	case WM_T_I210:
   8894  1.281   msaitoh 	case WM_T_I211:
   8895  1.281   msaitoh 	case WM_T_82583:
   8896  1.281   msaitoh 	case WM_T_80003:
   8897  1.281   msaitoh 		/* generic reset */
   8898  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   8899  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   8900  1.281   msaitoh 		delay(20000);
   8901  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   8902  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   8903  1.281   msaitoh 		delay(20000);
   8904  1.281   msaitoh 
   8905  1.281   msaitoh 		if ((sc->sc_type == WM_T_82541)
   8906  1.281   msaitoh 		    || (sc->sc_type == WM_T_82541_2)
   8907  1.281   msaitoh 		    || (sc->sc_type == WM_T_82547)
   8908  1.281   msaitoh 		    || (sc->sc_type == WM_T_82547_2)) {
   8909  1.281   msaitoh 			/* workaround for igp are done in igp_reset() */
   8910  1.281   msaitoh 			/* XXX add code to set LED after phy reset */
   8911  1.218   msaitoh 		}
   8912  1.218   msaitoh 		break;
   8913  1.281   msaitoh 	case WM_T_ICH8:
   8914  1.281   msaitoh 	case WM_T_ICH9:
   8915  1.281   msaitoh 	case WM_T_ICH10:
   8916  1.281   msaitoh 	case WM_T_PCH:
   8917  1.281   msaitoh 	case WM_T_PCH2:
   8918  1.281   msaitoh 	case WM_T_PCH_LPT:
   8919  1.392   msaitoh 	case WM_T_PCH_SPT:
   8920  1.281   msaitoh 		/* generic reset */
   8921  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   8922  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   8923  1.281   msaitoh 		delay(100);
   8924  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   8925  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   8926  1.281   msaitoh 		delay(150);
   8927  1.281   msaitoh 		break;
   8928  1.281   msaitoh 	default:
   8929  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   8930  1.281   msaitoh 		    __func__);
   8931  1.281   msaitoh 		break;
   8932  1.281   msaitoh 	}
   8933  1.281   msaitoh 
   8934  1.424   msaitoh 	sc->phy.release(sc);
   8935  1.210   msaitoh 
   8936  1.281   msaitoh 	/* get_cfg_done */
   8937  1.281   msaitoh 	wm_get_cfg_done(sc);
   8938  1.208   msaitoh 
   8939  1.281   msaitoh 	/* extra setup */
   8940  1.281   msaitoh 	switch (sc->sc_type) {
   8941  1.281   msaitoh 	case WM_T_82542_2_0:
   8942  1.281   msaitoh 	case WM_T_82542_2_1:
   8943  1.281   msaitoh 	case WM_T_82543:
   8944  1.281   msaitoh 	case WM_T_82544:
   8945  1.281   msaitoh 	case WM_T_82540:
   8946  1.281   msaitoh 	case WM_T_82545:
   8947  1.281   msaitoh 	case WM_T_82545_3:
   8948  1.281   msaitoh 	case WM_T_82546:
   8949  1.281   msaitoh 	case WM_T_82546_3:
   8950  1.281   msaitoh 	case WM_T_82541_2:
   8951  1.281   msaitoh 	case WM_T_82547_2:
   8952  1.281   msaitoh 	case WM_T_82571:
   8953  1.281   msaitoh 	case WM_T_82572:
   8954  1.281   msaitoh 	case WM_T_82573:
   8955  1.519   msaitoh 	case WM_T_82574:
   8956  1.519   msaitoh 	case WM_T_82583:
   8957  1.281   msaitoh 	case WM_T_82575:
   8958  1.281   msaitoh 	case WM_T_82576:
   8959  1.281   msaitoh 	case WM_T_82580:
   8960  1.281   msaitoh 	case WM_T_I350:
   8961  1.281   msaitoh 	case WM_T_I354:
   8962  1.281   msaitoh 	case WM_T_I210:
   8963  1.281   msaitoh 	case WM_T_I211:
   8964  1.281   msaitoh 	case WM_T_80003:
   8965  1.281   msaitoh 		/* null */
   8966  1.281   msaitoh 		break;
   8967  1.281   msaitoh 	case WM_T_82541:
   8968  1.281   msaitoh 	case WM_T_82547:
   8969  1.281   msaitoh 		/* XXX Configure actively LED after PHY reset */
   8970  1.281   msaitoh 		break;
   8971  1.281   msaitoh 	case WM_T_ICH8:
   8972  1.281   msaitoh 	case WM_T_ICH9:
   8973  1.281   msaitoh 	case WM_T_ICH10:
   8974  1.281   msaitoh 	case WM_T_PCH:
   8975  1.281   msaitoh 	case WM_T_PCH2:
   8976  1.281   msaitoh 	case WM_T_PCH_LPT:
   8977  1.392   msaitoh 	case WM_T_PCH_SPT:
   8978  1.517   msaitoh 		wm_phy_post_reset(sc);
   8979  1.281   msaitoh 		break;
   8980  1.281   msaitoh 	default:
   8981  1.281   msaitoh 		panic("%s: unknown type\n", __func__);
   8982  1.281   msaitoh 		break;
   8983    1.1   thorpej 	}
   8984    1.1   thorpej }
   8985    1.1   thorpej 
   8986    1.1   thorpej /*
   8987  1.475   msaitoh  * Setup sc_phytype and mii_{read|write}reg.
   8988  1.475   msaitoh  *
   8989  1.475   msaitoh  *  To identify PHY type, correct read/write function should be selected.
   8990  1.475   msaitoh  * To select correct read/write function, PCI ID or MAC type are required
   8991  1.475   msaitoh  * without accessing PHY registers.
   8992  1.475   msaitoh  *
   8993  1.475   msaitoh  *  On the first call of this function, PHY ID is not known yet. Check
   8994  1.475   msaitoh  * PCI ID or MAC type. The list of the PCI ID may not be perfect, so the
   8995  1.475   msaitoh  * result might be incorrect.
   8996  1.475   msaitoh  *
   8997  1.475   msaitoh  *  In the second call, PHY OUI and model is used to identify PHY type.
   8998  1.475   msaitoh  * It might not be perfpect because of the lack of compared entry, but it
   8999  1.475   msaitoh  * would be better than the first call.
   9000  1.475   msaitoh  *
   9001  1.475   msaitoh  *  If the detected new result and previous assumption is different,
   9002  1.475   msaitoh  * diagnous message will be printed.
   9003  1.475   msaitoh  */
   9004  1.475   msaitoh static void
   9005  1.475   msaitoh wm_gmii_setup_phytype(struct wm_softc *sc, uint32_t phy_oui,
   9006  1.475   msaitoh     uint16_t phy_model)
   9007  1.475   msaitoh {
   9008  1.475   msaitoh 	device_t dev = sc->sc_dev;
   9009  1.475   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   9010  1.475   msaitoh 	uint16_t new_phytype = WMPHY_UNKNOWN;
   9011  1.475   msaitoh 	uint16_t doubt_phytype = WMPHY_UNKNOWN;
   9012  1.475   msaitoh 	mii_readreg_t new_readreg;
   9013  1.475   msaitoh 	mii_writereg_t new_writereg;
   9014  1.475   msaitoh 
   9015  1.521   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   9016  1.521   msaitoh 		device_xname(sc->sc_dev), __func__));
   9017  1.521   msaitoh 
   9018  1.475   msaitoh 	if (mii->mii_readreg == NULL) {
   9019  1.475   msaitoh 		/*
   9020  1.475   msaitoh 		 *  This is the first call of this function. For ICH and PCH
   9021  1.475   msaitoh 		 * variants, it's difficult to determine the PHY access method
   9022  1.475   msaitoh 		 * by sc_type, so use the PCI product ID for some devices.
   9023  1.475   msaitoh 		 */
   9024  1.475   msaitoh 
   9025  1.475   msaitoh 		switch (sc->sc_pcidevid) {
   9026  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_M_LM:
   9027  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_M_LC:
   9028  1.475   msaitoh 			/* 82577 */
   9029  1.475   msaitoh 			new_phytype = WMPHY_82577;
   9030  1.475   msaitoh 			break;
   9031  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_D_DM:
   9032  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_D_DC:
   9033  1.475   msaitoh 			/* 82578 */
   9034  1.475   msaitoh 			new_phytype = WMPHY_82578;
   9035  1.475   msaitoh 			break;
   9036  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH2_LV_LM:
   9037  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH2_LV_V:
   9038  1.475   msaitoh 			/* 82579 */
   9039  1.475   msaitoh 			new_phytype = WMPHY_82579;
   9040  1.475   msaitoh 			break;
   9041  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801H_82567V_3:
   9042  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801I_BM:
   9043  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801I_IGP_M_AMT: /* Not IGP but BM */
   9044  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_LM:
   9045  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_LF:
   9046  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_D_BM_LM:
   9047  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_D_BM_LF:
   9048  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_V:
   9049  1.475   msaitoh 			/* ICH8, 9, 10 with 82567 */
   9050  1.475   msaitoh 			new_phytype = WMPHY_BM;
   9051  1.475   msaitoh 			break;
   9052  1.475   msaitoh 		default:
   9053  1.475   msaitoh 			break;
   9054  1.475   msaitoh 		}
   9055  1.475   msaitoh 	} else {
   9056  1.475   msaitoh 		/* It's not the first call. Use PHY OUI and model */
   9057  1.475   msaitoh 		switch (phy_oui) {
   9058  1.475   msaitoh 		case MII_OUI_ATHEROS: /* XXX ??? */
   9059  1.475   msaitoh 			switch (phy_model) {
   9060  1.475   msaitoh 			case 0x0004: /* XXX */
   9061  1.475   msaitoh 				new_phytype = WMPHY_82578;
   9062  1.475   msaitoh 				break;
   9063  1.475   msaitoh 			default:
   9064  1.475   msaitoh 				break;
   9065  1.475   msaitoh 			}
   9066  1.475   msaitoh 			break;
   9067  1.475   msaitoh 		case MII_OUI_xxMARVELL:
   9068  1.475   msaitoh 			switch (phy_model) {
   9069  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I210:
   9070  1.475   msaitoh 				new_phytype = WMPHY_I210;
   9071  1.475   msaitoh 				break;
   9072  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1011:
   9073  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1000_3:
   9074  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1000_5:
   9075  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1112:
   9076  1.475   msaitoh 				new_phytype = WMPHY_M88;
   9077  1.475   msaitoh 				break;
   9078  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1149:
   9079  1.475   msaitoh 				new_phytype = WMPHY_BM;
   9080  1.475   msaitoh 				break;
   9081  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1111:
   9082  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I347:
   9083  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1512:
   9084  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1340M:
   9085  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1543:
   9086  1.475   msaitoh 				new_phytype = WMPHY_M88;
   9087  1.475   msaitoh 				break;
   9088  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I82563:
   9089  1.475   msaitoh 				new_phytype = WMPHY_GG82563;
   9090  1.475   msaitoh 				break;
   9091  1.475   msaitoh 			default:
   9092  1.475   msaitoh 				break;
   9093  1.475   msaitoh 			}
   9094  1.475   msaitoh 			break;
   9095  1.475   msaitoh 		case MII_OUI_INTEL:
   9096  1.475   msaitoh 			switch (phy_model) {
   9097  1.475   msaitoh 			case MII_MODEL_INTEL_I82577:
   9098  1.475   msaitoh 				new_phytype = WMPHY_82577;
   9099  1.475   msaitoh 				break;
   9100  1.475   msaitoh 			case MII_MODEL_INTEL_I82579:
   9101  1.475   msaitoh 				new_phytype = WMPHY_82579;
   9102  1.475   msaitoh 				break;
   9103  1.475   msaitoh 			case MII_MODEL_INTEL_I217:
   9104  1.475   msaitoh 				new_phytype = WMPHY_I217;
   9105  1.475   msaitoh 				break;
   9106  1.475   msaitoh 			case MII_MODEL_INTEL_I82580:
   9107  1.475   msaitoh 			case MII_MODEL_INTEL_I350:
   9108  1.475   msaitoh 				new_phytype = WMPHY_82580;
   9109  1.475   msaitoh 				break;
   9110  1.475   msaitoh 			default:
   9111  1.475   msaitoh 				break;
   9112  1.475   msaitoh 			}
   9113  1.475   msaitoh 			break;
   9114  1.475   msaitoh 		case MII_OUI_yyINTEL:
   9115  1.475   msaitoh 			switch (phy_model) {
   9116  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562G:
   9117  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562EM:
   9118  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562ET:
   9119  1.475   msaitoh 				new_phytype = WMPHY_IFE;
   9120  1.475   msaitoh 				break;
   9121  1.475   msaitoh 			case MII_MODEL_yyINTEL_IGP01E1000:
   9122  1.475   msaitoh 				new_phytype = WMPHY_IGP;
   9123  1.475   msaitoh 				break;
   9124  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82566:
   9125  1.475   msaitoh 				new_phytype = WMPHY_IGP_3;
   9126  1.475   msaitoh 				break;
   9127  1.475   msaitoh 			default:
   9128  1.475   msaitoh 				break;
   9129  1.475   msaitoh 			}
   9130  1.475   msaitoh 			break;
   9131  1.475   msaitoh 		default:
   9132  1.475   msaitoh 			break;
   9133  1.475   msaitoh 		}
   9134  1.475   msaitoh 		if (new_phytype == WMPHY_UNKNOWN)
   9135  1.475   msaitoh 			aprint_verbose_dev(dev, "%s: unknown PHY model\n",
   9136  1.475   msaitoh 			    __func__);
   9137  1.475   msaitoh 
   9138  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9139  1.475   msaitoh 		    && (sc->sc_phytype != new_phytype )) {
   9140  1.475   msaitoh 			aprint_error_dev(dev, "Previously assumed PHY type(%u)"
   9141  1.475   msaitoh 			    "was incorrect. PHY type from PHY ID = %u\n",
   9142  1.475   msaitoh 			    sc->sc_phytype, new_phytype);
   9143  1.475   msaitoh 		}
   9144  1.475   msaitoh 	}
   9145  1.475   msaitoh 
   9146  1.475   msaitoh 	/* Next, use sc->sc_flags and sc->sc_type to set read/write funcs. */
   9147  1.475   msaitoh 	if (((sc->sc_flags & WM_F_SGMII) != 0) && !wm_sgmii_uses_mdio(sc)) {
   9148  1.475   msaitoh 		/* SGMII */
   9149  1.475   msaitoh 		new_readreg = wm_sgmii_readreg;
   9150  1.475   msaitoh 		new_writereg = wm_sgmii_writereg;
   9151  1.475   msaitoh 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
   9152  1.475   msaitoh 		/* BM2 (phyaddr == 1) */
   9153  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9154  1.475   msaitoh 		    && (new_phytype != WMPHY_BM)
   9155  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9156  1.475   msaitoh 			doubt_phytype = new_phytype;
   9157  1.475   msaitoh 		new_phytype = WMPHY_BM;
   9158  1.475   msaitoh 		new_readreg = wm_gmii_bm_readreg;
   9159  1.475   msaitoh 		new_writereg = wm_gmii_bm_writereg;
   9160  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_PCH) {
   9161  1.475   msaitoh 		/* All PCH* use _hv_ */
   9162  1.475   msaitoh 		new_readreg = wm_gmii_hv_readreg;
   9163  1.475   msaitoh 		new_writereg = wm_gmii_hv_writereg;
   9164  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_ICH8) {
   9165  1.475   msaitoh 		/* non-82567 ICH8, 9 and 10 */
   9166  1.475   msaitoh 		new_readreg = wm_gmii_i82544_readreg;
   9167  1.475   msaitoh 		new_writereg = wm_gmii_i82544_writereg;
   9168  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_80003) {
   9169  1.475   msaitoh 		/* 80003 */
   9170  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9171  1.475   msaitoh 		    && (new_phytype != WMPHY_GG82563)
   9172  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9173  1.475   msaitoh 			doubt_phytype = new_phytype;
   9174  1.475   msaitoh 		new_phytype = WMPHY_GG82563;
   9175  1.475   msaitoh 		new_readreg = wm_gmii_i80003_readreg;
   9176  1.475   msaitoh 		new_writereg = wm_gmii_i80003_writereg;
   9177  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_I210) {
   9178  1.475   msaitoh 		/* I210 and I211 */
   9179  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9180  1.475   msaitoh 		    && (new_phytype != WMPHY_I210)
   9181  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9182  1.475   msaitoh 			doubt_phytype = new_phytype;
   9183  1.475   msaitoh 		new_phytype = WMPHY_I210;
   9184  1.475   msaitoh 		new_readreg = wm_gmii_gs40g_readreg;
   9185  1.475   msaitoh 		new_writereg = wm_gmii_gs40g_writereg;
   9186  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_82580) {
   9187  1.475   msaitoh 		/* 82580, I350 and I354 */
   9188  1.475   msaitoh 		new_readreg = wm_gmii_82580_readreg;
   9189  1.475   msaitoh 		new_writereg = wm_gmii_82580_writereg;
   9190  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_82544) {
   9191  1.475   msaitoh 		/* 82544, 0, [56], [17], 8257[1234] and 82583 */
   9192  1.475   msaitoh 		new_readreg = wm_gmii_i82544_readreg;
   9193  1.475   msaitoh 		new_writereg = wm_gmii_i82544_writereg;
   9194  1.475   msaitoh 	} else {
   9195  1.475   msaitoh 		new_readreg = wm_gmii_i82543_readreg;
   9196  1.475   msaitoh 		new_writereg = wm_gmii_i82543_writereg;
   9197  1.475   msaitoh 	}
   9198  1.475   msaitoh 
   9199  1.475   msaitoh 	if (new_phytype == WMPHY_BM) {
   9200  1.475   msaitoh 		/* All BM use _bm_ */
   9201  1.475   msaitoh 		new_readreg = wm_gmii_bm_readreg;
   9202  1.475   msaitoh 		new_writereg = wm_gmii_bm_writereg;
   9203  1.475   msaitoh 	}
   9204  1.475   msaitoh 	if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_SPT)) {
   9205  1.475   msaitoh 		/* All PCH* use _hv_ */
   9206  1.475   msaitoh 		new_readreg = wm_gmii_hv_readreg;
   9207  1.475   msaitoh 		new_writereg = wm_gmii_hv_writereg;
   9208  1.475   msaitoh 	}
   9209  1.475   msaitoh 
   9210  1.475   msaitoh 	/* Diag output */
   9211  1.475   msaitoh 	if (doubt_phytype != WMPHY_UNKNOWN)
   9212  1.475   msaitoh 		aprint_error_dev(dev, "Assumed new PHY type was "
   9213  1.475   msaitoh 		    "incorrect. old = %u, new = %u\n", sc->sc_phytype,
   9214  1.475   msaitoh 		    new_phytype);
   9215  1.475   msaitoh 	else if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9216  1.475   msaitoh 	    && (sc->sc_phytype != new_phytype ))
   9217  1.475   msaitoh 		aprint_error_dev(dev, "Previously assumed PHY type(%u)"
   9218  1.475   msaitoh 		    "was incorrect. New PHY type = %u\n",
   9219  1.475   msaitoh 		    sc->sc_phytype, new_phytype);
   9220  1.475   msaitoh 
   9221  1.475   msaitoh 	if ((mii->mii_readreg != NULL) && (new_phytype == WMPHY_UNKNOWN))
   9222  1.475   msaitoh 		aprint_error_dev(dev, "PHY type is still unknown.\n");
   9223  1.475   msaitoh 
   9224  1.475   msaitoh 	if ((mii->mii_readreg != NULL) && (mii->mii_readreg != new_readreg))
   9225  1.475   msaitoh 		aprint_error_dev(dev, "Previously assumed PHY read/write "
   9226  1.475   msaitoh 		    "function was incorrect.\n");
   9227  1.475   msaitoh 
   9228  1.475   msaitoh 	/* Update now */
   9229  1.475   msaitoh 	sc->sc_phytype = new_phytype;
   9230  1.475   msaitoh 	mii->mii_readreg = new_readreg;
   9231  1.475   msaitoh 	mii->mii_writereg = new_writereg;
   9232  1.475   msaitoh }
   9233  1.475   msaitoh 
   9234  1.475   msaitoh /*
   9235  1.281   msaitoh  * wm_get_phy_id_82575:
   9236    1.1   thorpej  *
   9237  1.281   msaitoh  * Return PHY ID. Return -1 if it failed.
   9238    1.1   thorpej  */
   9239  1.281   msaitoh static int
   9240  1.281   msaitoh wm_get_phy_id_82575(struct wm_softc *sc)
   9241    1.1   thorpej {
   9242  1.281   msaitoh 	uint32_t reg;
   9243  1.281   msaitoh 	int phyid = -1;
   9244  1.281   msaitoh 
   9245  1.281   msaitoh 	/* XXX */
   9246  1.281   msaitoh 	if ((sc->sc_flags & WM_F_SGMII) == 0)
   9247  1.281   msaitoh 		return -1;
   9248    1.1   thorpej 
   9249  1.281   msaitoh 	if (wm_sgmii_uses_mdio(sc)) {
   9250  1.281   msaitoh 		switch (sc->sc_type) {
   9251  1.281   msaitoh 		case WM_T_82575:
   9252  1.281   msaitoh 		case WM_T_82576:
   9253  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_MDIC);
   9254  1.281   msaitoh 			phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT;
   9255  1.281   msaitoh 			break;
   9256  1.281   msaitoh 		case WM_T_82580:
   9257  1.281   msaitoh 		case WM_T_I350:
   9258  1.281   msaitoh 		case WM_T_I354:
   9259  1.281   msaitoh 		case WM_T_I210:
   9260  1.281   msaitoh 		case WM_T_I211:
   9261  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_MDICNFG);
   9262  1.281   msaitoh 			phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT;
   9263  1.281   msaitoh 			break;
   9264  1.281   msaitoh 		default:
   9265  1.281   msaitoh 			return -1;
   9266  1.281   msaitoh 		}
   9267  1.139    bouyer 	}
   9268    1.1   thorpej 
   9269  1.281   msaitoh 	return phyid;
   9270    1.1   thorpej }
   9271    1.1   thorpej 
   9272  1.281   msaitoh 
   9273    1.1   thorpej /*
   9274  1.281   msaitoh  * wm_gmii_mediainit:
   9275    1.1   thorpej  *
   9276  1.281   msaitoh  *	Initialize media for use on 1000BASE-T devices.
   9277    1.1   thorpej  */
   9278   1.47   thorpej static void
   9279  1.281   msaitoh wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
   9280    1.1   thorpej {
   9281  1.475   msaitoh 	device_t dev = sc->sc_dev;
   9282    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   9283  1.281   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   9284  1.282   msaitoh 	uint32_t reg;
   9285  1.281   msaitoh 
   9286  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   9287  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   9288  1.425   msaitoh 
   9289  1.292   msaitoh 	/* We have GMII. */
   9290  1.281   msaitoh 	sc->sc_flags |= WM_F_HAS_MII;
   9291    1.1   thorpej 
   9292  1.281   msaitoh 	if (sc->sc_type == WM_T_80003)
   9293  1.281   msaitoh 		sc->sc_tipg =  TIPG_1000T_80003_DFLT;
   9294    1.1   thorpej 	else
   9295  1.281   msaitoh 		sc->sc_tipg = TIPG_1000T_DFLT;
   9296    1.1   thorpej 
   9297  1.282   msaitoh 	/* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */
   9298  1.300   msaitoh 	if ((sc->sc_type == WM_T_82580)
   9299  1.282   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210)
   9300  1.282   msaitoh 	    || (sc->sc_type == WM_T_I211)) {
   9301  1.282   msaitoh 		reg = CSR_READ(sc, WMREG_PHPM);
   9302  1.282   msaitoh 		reg &= ~PHPM_GO_LINK_D;
   9303  1.282   msaitoh 		CSR_WRITE(sc, WMREG_PHPM, reg);
   9304  1.282   msaitoh 	}
   9305  1.282   msaitoh 
   9306  1.281   msaitoh 	/*
   9307  1.281   msaitoh 	 * Let the chip set speed/duplex on its own based on
   9308  1.281   msaitoh 	 * signals from the PHY.
   9309  1.281   msaitoh 	 * XXXbouyer - I'm not sure this is right for the 80003,
   9310  1.281   msaitoh 	 * the em driver only sets CTRL_SLU here - but it seems to work.
   9311  1.281   msaitoh 	 */
   9312  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   9313  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9314    1.1   thorpej 
   9315  1.281   msaitoh 	/* Initialize our media structures and probe the GMII. */
   9316  1.281   msaitoh 	mii->mii_ifp = ifp;
   9317    1.1   thorpej 
   9318    1.1   thorpej 	/*
   9319  1.475   msaitoh 	 * The first call of wm_mii_setup_phytype. The result might be
   9320  1.475   msaitoh 	 * incorrect.
   9321  1.475   msaitoh 	 */
   9322  1.475   msaitoh 	wm_gmii_setup_phytype(sc, 0, 0);
   9323  1.475   msaitoh 
   9324  1.281   msaitoh 	mii->mii_statchg = wm_gmii_statchg;
   9325    1.1   thorpej 
   9326  1.448   msaitoh 	/* get PHY control from SMBus to PCIe */
   9327  1.448   msaitoh 	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
   9328  1.448   msaitoh 	    || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT))
   9329  1.448   msaitoh 		wm_smbustopci(sc);
   9330  1.448   msaitoh 
   9331  1.281   msaitoh 	wm_gmii_reset(sc);
   9332    1.1   thorpej 
   9333  1.281   msaitoh 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   9334  1.327   msaitoh 	ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange,
   9335  1.327   msaitoh 	    wm_gmii_mediastatus);
   9336    1.1   thorpej 
   9337  1.281   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   9338  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   9339  1.281   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   9340  1.281   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) {
   9341  1.281   msaitoh 		if ((sc->sc_flags & WM_F_SGMII) == 0) {
   9342  1.281   msaitoh 			/* Attach only one port */
   9343  1.281   msaitoh 			mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
   9344  1.281   msaitoh 			    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9345  1.281   msaitoh 		} else {
   9346  1.281   msaitoh 			int i, id;
   9347  1.281   msaitoh 			uint32_t ctrl_ext;
   9348    1.1   thorpej 
   9349  1.281   msaitoh 			id = wm_get_phy_id_82575(sc);
   9350  1.281   msaitoh 			if (id != -1) {
   9351  1.281   msaitoh 				mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
   9352  1.281   msaitoh 				    id, MII_OFFSET_ANY, MIIF_DOPAUSE);
   9353  1.281   msaitoh 			}
   9354  1.281   msaitoh 			if ((id == -1)
   9355  1.281   msaitoh 			    || (LIST_FIRST(&mii->mii_phys) == NULL)) {
   9356  1.281   msaitoh 				/* Power on sgmii phy if it is disabled */
   9357  1.281   msaitoh 				ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   9358  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL_EXT,
   9359  1.281   msaitoh 				    ctrl_ext &~ CTRL_EXT_SWDPIN(3));
   9360  1.281   msaitoh 				CSR_WRITE_FLUSH(sc);
   9361  1.281   msaitoh 				delay(300*1000); /* XXX too long */
   9362    1.1   thorpej 
   9363  1.281   msaitoh 				/* from 1 to 8 */
   9364  1.281   msaitoh 				for (i = 1; i < 8; i++)
   9365  1.281   msaitoh 					mii_attach(sc->sc_dev, &sc->sc_mii,
   9366  1.281   msaitoh 					    0xffffffff, i, MII_OFFSET_ANY,
   9367  1.281   msaitoh 					    MIIF_DOPAUSE);
   9368    1.1   thorpej 
   9369  1.281   msaitoh 				/* restore previous sfp cage power state */
   9370  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   9371  1.281   msaitoh 			}
   9372  1.281   msaitoh 		}
   9373  1.281   msaitoh 	} else {
   9374  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9375  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9376  1.281   msaitoh 	}
   9377  1.173   msaitoh 
   9378  1.281   msaitoh 	/*
   9379  1.281   msaitoh 	 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
   9380  1.281   msaitoh 	 * wm_set_mdio_slow_mode_hv() for a workaround and retry.
   9381  1.281   msaitoh 	 */
   9382  1.281   msaitoh 	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) &&
   9383  1.281   msaitoh 	    (LIST_FIRST(&mii->mii_phys) == NULL)) {
   9384  1.281   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   9385  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9386  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9387  1.281   msaitoh 	}
   9388    1.1   thorpej 
   9389    1.1   thorpej 	/*
   9390  1.281   msaitoh 	 * (For ICH8 variants)
   9391  1.281   msaitoh 	 * If PHY detection failed, use BM's r/w function and retry.
   9392    1.1   thorpej 	 */
   9393  1.281   msaitoh 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
   9394  1.281   msaitoh 		/* if failed, retry with *_bm_* */
   9395  1.475   msaitoh 		aprint_verbose_dev(dev, "Assumed PHY access function "
   9396  1.475   msaitoh 		    "(type = %d) might be incorrect. Use BM and retry.\n",
   9397  1.475   msaitoh 		    sc->sc_phytype);
   9398  1.475   msaitoh 		sc->sc_phytype = WMPHY_BM;
   9399  1.281   msaitoh 		mii->mii_readreg = wm_gmii_bm_readreg;
   9400  1.281   msaitoh 		mii->mii_writereg = wm_gmii_bm_writereg;
   9401    1.1   thorpej 
   9402  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9403  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9404  1.281   msaitoh 	}
   9405    1.1   thorpej 
   9406  1.281   msaitoh 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
   9407  1.281   msaitoh 		/* Any PHY wasn't find */
   9408  1.388   msaitoh 		ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
   9409  1.388   msaitoh 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
   9410  1.281   msaitoh 		sc->sc_phytype = WMPHY_NONE;
   9411  1.281   msaitoh 	} else {
   9412  1.475   msaitoh 		struct mii_softc *child = LIST_FIRST(&mii->mii_phys);
   9413  1.475   msaitoh 
   9414  1.281   msaitoh 		/*
   9415  1.475   msaitoh 		 * PHY Found! Check PHY type again by the second call of
   9416  1.475   msaitoh 		 * wm_mii_setup_phytype.
   9417  1.281   msaitoh 		 */
   9418  1.475   msaitoh 		wm_gmii_setup_phytype(sc, child->mii_mpd_oui,
   9419  1.475   msaitoh 		    child->mii_mpd_model);
   9420    1.1   thorpej 
   9421  1.281   msaitoh 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
   9422  1.281   msaitoh 	}
   9423    1.1   thorpej }
   9424    1.1   thorpej 
   9425    1.1   thorpej /*
   9426  1.281   msaitoh  * wm_gmii_mediachange:	[ifmedia interface function]
   9427    1.1   thorpej  *
   9428  1.281   msaitoh  *	Set hardware to newly-selected media on a 1000BASE-T device.
   9429    1.1   thorpej  */
   9430   1.47   thorpej static int
   9431  1.281   msaitoh wm_gmii_mediachange(struct ifnet *ifp)
   9432    1.1   thorpej {
   9433    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   9434    1.1   thorpej 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   9435  1.281   msaitoh 	int rc;
   9436    1.1   thorpej 
   9437  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   9438  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   9439  1.281   msaitoh 	if ((ifp->if_flags & IFF_UP) == 0)
   9440  1.279   msaitoh 		return 0;
   9441  1.279   msaitoh 
   9442  1.517   msaitoh 	/* Disable D0 LPLU. */
   9443  1.519   msaitoh 	wm_lplu_d0_disable(sc);
   9444  1.517   msaitoh 
   9445  1.281   msaitoh 	sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
   9446  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   9447  1.281   msaitoh 	if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   9448  1.281   msaitoh 	    || (sc->sc_type > WM_T_82543)) {
   9449  1.281   msaitoh 		sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX);
   9450  1.134   msaitoh 	} else {
   9451  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_ASDE;
   9452  1.281   msaitoh 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
   9453  1.281   msaitoh 		if (ife->ifm_media & IFM_FDX)
   9454  1.281   msaitoh 			sc->sc_ctrl |= CTRL_FD;
   9455  1.281   msaitoh 		switch (IFM_SUBTYPE(ife->ifm_media)) {
   9456  1.281   msaitoh 		case IFM_10_T:
   9457  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_10;
   9458  1.281   msaitoh 			break;
   9459  1.281   msaitoh 		case IFM_100_TX:
   9460  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_100;
   9461  1.281   msaitoh 			break;
   9462  1.281   msaitoh 		case IFM_1000_T:
   9463  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_1000;
   9464  1.281   msaitoh 			break;
   9465  1.281   msaitoh 		default:
   9466  1.281   msaitoh 			panic("wm_gmii_mediachange: bad media 0x%x",
   9467  1.281   msaitoh 			    ife->ifm_media);
   9468  1.281   msaitoh 		}
   9469  1.134   msaitoh 	}
   9470  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9471  1.515   msaitoh 	CSR_WRITE_FLUSH(sc);
   9472  1.281   msaitoh 	if (sc->sc_type <= WM_T_82543)
   9473  1.281   msaitoh 		wm_gmii_reset(sc);
   9474  1.281   msaitoh 
   9475  1.281   msaitoh 	if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
   9476  1.281   msaitoh 		return 0;
   9477  1.281   msaitoh 	return rc;
   9478  1.281   msaitoh }
   9479    1.1   thorpej 
   9480  1.324   msaitoh /*
   9481  1.324   msaitoh  * wm_gmii_mediastatus:	[ifmedia interface function]
   9482  1.324   msaitoh  *
   9483  1.324   msaitoh  *	Get the current interface media status on a 1000BASE-T device.
   9484  1.324   msaitoh  */
   9485  1.324   msaitoh static void
   9486  1.324   msaitoh wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   9487  1.324   msaitoh {
   9488  1.324   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   9489  1.324   msaitoh 
   9490  1.324   msaitoh 	ether_mediastatus(ifp, ifmr);
   9491  1.324   msaitoh 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
   9492  1.324   msaitoh 	    | sc->sc_flowflags;
   9493  1.324   msaitoh }
   9494  1.324   msaitoh 
   9495  1.281   msaitoh #define	MDI_IO		CTRL_SWDPIN(2)
   9496  1.281   msaitoh #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
   9497  1.281   msaitoh #define	MDI_CLK		CTRL_SWDPIN(3)
   9498    1.1   thorpej 
   9499  1.281   msaitoh static void
   9500  1.281   msaitoh wm_i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
   9501  1.281   msaitoh {
   9502  1.281   msaitoh 	uint32_t i, v;
   9503  1.134   msaitoh 
   9504  1.281   msaitoh 	v = CSR_READ(sc, WMREG_CTRL);
   9505  1.388   msaitoh 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   9506  1.281   msaitoh 	v |= MDI_DIR | CTRL_SWDPIO(3);
   9507  1.134   msaitoh 
   9508  1.281   msaitoh 	for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
   9509  1.281   msaitoh 		if (data & i)
   9510  1.281   msaitoh 			v |= MDI_IO;
   9511  1.281   msaitoh 		else
   9512  1.281   msaitoh 			v &= ~MDI_IO;
   9513  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9514  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9515  1.281   msaitoh 		delay(10);
   9516  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9517  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9518  1.281   msaitoh 		delay(10);
   9519  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9520  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9521  1.281   msaitoh 		delay(10);
   9522  1.281   msaitoh 	}
   9523  1.281   msaitoh }
   9524  1.134   msaitoh 
   9525  1.281   msaitoh static uint32_t
   9526  1.281   msaitoh wm_i82543_mii_recvbits(struct wm_softc *sc)
   9527  1.281   msaitoh {
   9528  1.281   msaitoh 	uint32_t v, i, data = 0;
   9529    1.1   thorpej 
   9530  1.281   msaitoh 	v = CSR_READ(sc, WMREG_CTRL);
   9531  1.388   msaitoh 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   9532  1.281   msaitoh 	v |= CTRL_SWDPIO(3);
   9533  1.134   msaitoh 
   9534  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9535  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9536  1.281   msaitoh 	delay(10);
   9537  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9538  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9539  1.281   msaitoh 	delay(10);
   9540  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9541  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9542  1.281   msaitoh 	delay(10);
   9543  1.173   msaitoh 
   9544  1.281   msaitoh 	for (i = 0; i < 16; i++) {
   9545  1.281   msaitoh 		data <<= 1;
   9546  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9547  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9548  1.281   msaitoh 		delay(10);
   9549  1.281   msaitoh 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
   9550  1.281   msaitoh 			data |= 1;
   9551  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9552  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9553  1.281   msaitoh 		delay(10);
   9554    1.1   thorpej 	}
   9555    1.1   thorpej 
   9556  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9557  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9558  1.281   msaitoh 	delay(10);
   9559  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9560  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9561  1.281   msaitoh 	delay(10);
   9562    1.1   thorpej 
   9563  1.281   msaitoh 	return data;
   9564    1.1   thorpej }
   9565    1.1   thorpej 
   9566  1.281   msaitoh #undef MDI_IO
   9567  1.281   msaitoh #undef MDI_DIR
   9568  1.281   msaitoh #undef MDI_CLK
   9569  1.281   msaitoh 
   9570    1.1   thorpej /*
   9571  1.281   msaitoh  * wm_gmii_i82543_readreg:	[mii interface function]
   9572    1.1   thorpej  *
   9573  1.281   msaitoh  *	Read a PHY register on the GMII (i82543 version).
   9574    1.1   thorpej  */
   9575  1.281   msaitoh static int
   9576  1.521   msaitoh wm_gmii_i82543_readreg(device_t dev, int phy, int reg)
   9577    1.1   thorpej {
   9578  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9579  1.281   msaitoh 	int rv;
   9580    1.1   thorpej 
   9581  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
   9582  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, reg | (phy << 5) |
   9583  1.281   msaitoh 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
   9584  1.281   msaitoh 	rv = wm_i82543_mii_recvbits(sc) & 0xffff;
   9585    1.1   thorpej 
   9586  1.388   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
   9587  1.521   msaitoh 	    device_xname(dev), phy, reg, rv));
   9588  1.173   msaitoh 
   9589  1.281   msaitoh 	return rv;
   9590    1.1   thorpej }
   9591    1.1   thorpej 
   9592    1.1   thorpej /*
   9593  1.281   msaitoh  * wm_gmii_i82543_writereg:	[mii interface function]
   9594    1.1   thorpej  *
   9595  1.281   msaitoh  *	Write a PHY register on the GMII (i82543 version).
   9596    1.1   thorpej  */
   9597   1.47   thorpej static void
   9598  1.521   msaitoh wm_gmii_i82543_writereg(device_t dev, int phy, int reg, int val)
   9599    1.1   thorpej {
   9600  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9601    1.1   thorpej 
   9602  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
   9603  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
   9604  1.281   msaitoh 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
   9605  1.281   msaitoh 	    (MII_COMMAND_START << 30), 32);
   9606  1.281   msaitoh }
   9607  1.272     ozaki 
   9608  1.281   msaitoh /*
   9609  1.424   msaitoh  * wm_gmii_mdic_readreg:	[mii interface function]
   9610  1.281   msaitoh  *
   9611  1.281   msaitoh  *	Read a PHY register on the GMII.
   9612  1.281   msaitoh  */
   9613  1.281   msaitoh static int
   9614  1.521   msaitoh wm_gmii_mdic_readreg(device_t dev, int phy, int reg)
   9615  1.281   msaitoh {
   9616  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9617  1.281   msaitoh 	uint32_t mdic = 0;
   9618  1.281   msaitoh 	int i, rv;
   9619  1.279   msaitoh 
   9620  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   9621  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   9622  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   9623  1.522   msaitoh 		reg &= MII_ADDRMASK;
   9624  1.522   msaitoh 	}
   9625  1.522   msaitoh 
   9626  1.281   msaitoh 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
   9627  1.281   msaitoh 	    MDIC_REGADD(reg));
   9628    1.1   thorpej 
   9629  1.281   msaitoh 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
   9630  1.281   msaitoh 		mdic = CSR_READ(sc, WMREG_MDIC);
   9631  1.281   msaitoh 		if (mdic & MDIC_READY)
   9632  1.281   msaitoh 			break;
   9633  1.327   msaitoh 		delay(50);
   9634    1.1   thorpej 	}
   9635    1.1   thorpej 
   9636  1.281   msaitoh 	if ((mdic & MDIC_READY) == 0) {
   9637  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
   9638  1.521   msaitoh 		    device_xname(dev), phy, reg);
   9639  1.281   msaitoh 		rv = 0;
   9640  1.281   msaitoh 	} else if (mdic & MDIC_E) {
   9641  1.281   msaitoh #if 0 /* This is normal if no PHY is present. */
   9642  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
   9643  1.521   msaitoh 		    device_xname(dev), phy, reg);
   9644  1.281   msaitoh #endif
   9645  1.281   msaitoh 		rv = 0;
   9646  1.281   msaitoh 	} else {
   9647  1.281   msaitoh 		rv = MDIC_DATA(mdic);
   9648  1.281   msaitoh 		if (rv == 0xffff)
   9649  1.281   msaitoh 			rv = 0;
   9650  1.173   msaitoh 	}
   9651  1.173   msaitoh 
   9652  1.281   msaitoh 	return rv;
   9653    1.1   thorpej }
   9654    1.1   thorpej 
   9655    1.1   thorpej /*
   9656  1.424   msaitoh  * wm_gmii_mdic_writereg:	[mii interface function]
   9657    1.1   thorpej  *
   9658  1.281   msaitoh  *	Write a PHY register on the GMII.
   9659    1.1   thorpej  */
   9660   1.47   thorpej static void
   9661  1.521   msaitoh wm_gmii_mdic_writereg(device_t dev, int phy, int reg, int val)
   9662    1.1   thorpej {
   9663  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9664  1.281   msaitoh 	uint32_t mdic = 0;
   9665  1.281   msaitoh 	int i;
   9666  1.281   msaitoh 
   9667  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   9668  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   9669  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   9670  1.522   msaitoh 		reg &= MII_ADDRMASK;
   9671  1.522   msaitoh 	}
   9672  1.522   msaitoh 
   9673  1.281   msaitoh 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
   9674  1.281   msaitoh 	    MDIC_REGADD(reg) | MDIC_DATA(val));
   9675    1.1   thorpej 
   9676  1.281   msaitoh 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
   9677  1.281   msaitoh 		mdic = CSR_READ(sc, WMREG_MDIC);
   9678  1.281   msaitoh 		if (mdic & MDIC_READY)
   9679  1.281   msaitoh 			break;
   9680  1.327   msaitoh 		delay(50);
   9681  1.127    bouyer 	}
   9682    1.1   thorpej 
   9683  1.281   msaitoh 	if ((mdic & MDIC_READY) == 0)
   9684  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n",
   9685  1.521   msaitoh 		    device_xname(dev), phy, reg);
   9686  1.281   msaitoh 	else if (mdic & MDIC_E)
   9687  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n",
   9688  1.521   msaitoh 		    device_xname(dev), phy, reg);
   9689  1.281   msaitoh }
   9690  1.133   msaitoh 
   9691  1.281   msaitoh /*
   9692  1.424   msaitoh  * wm_gmii_i82544_readreg:	[mii interface function]
   9693  1.424   msaitoh  *
   9694  1.424   msaitoh  *	Read a PHY register on the GMII.
   9695  1.424   msaitoh  */
   9696  1.424   msaitoh static int
   9697  1.521   msaitoh wm_gmii_i82544_readreg(device_t dev, int phy, int reg)
   9698  1.424   msaitoh {
   9699  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9700  1.424   msaitoh 	int rv;
   9701  1.424   msaitoh 
   9702  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   9703  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   9704  1.424   msaitoh 		return 0;
   9705  1.424   msaitoh 	}
   9706  1.522   msaitoh 
   9707  1.522   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   9708  1.522   msaitoh 		switch (sc->sc_phytype) {
   9709  1.522   msaitoh 		case WMPHY_IGP:
   9710  1.522   msaitoh 		case WMPHY_IGP_2:
   9711  1.522   msaitoh 		case WMPHY_IGP_3:
   9712  1.522   msaitoh 			wm_gmii_mdic_writereg(dev, phy, MII_IGPHY_PAGE_SELECT, reg);
   9713  1.522   msaitoh 			break;
   9714  1.522   msaitoh 		default:
   9715  1.522   msaitoh #ifdef WM_DEBUG
   9716  1.522   msaitoh 			device_printf(dev, "%s: PHYTYPE = 0x%x, addr = %02x\n",
   9717  1.522   msaitoh 			    __func__, sc->sc_phytype, reg);
   9718  1.522   msaitoh #endif
   9719  1.522   msaitoh 			break;
   9720  1.522   msaitoh 		}
   9721  1.522   msaitoh 	}
   9722  1.522   msaitoh 
   9723  1.522   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   9724  1.424   msaitoh 	sc->phy.release(sc);
   9725  1.424   msaitoh 
   9726  1.424   msaitoh 	return rv;
   9727  1.424   msaitoh }
   9728  1.424   msaitoh 
   9729  1.424   msaitoh /*
   9730  1.424   msaitoh  * wm_gmii_i82544_writereg:	[mii interface function]
   9731  1.424   msaitoh  *
   9732  1.424   msaitoh  *	Write a PHY register on the GMII.
   9733  1.424   msaitoh  */
   9734  1.424   msaitoh static void
   9735  1.521   msaitoh wm_gmii_i82544_writereg(device_t dev, int phy, int reg, int val)
   9736  1.424   msaitoh {
   9737  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9738  1.424   msaitoh 
   9739  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   9740  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   9741  1.521   msaitoh 		return;
   9742  1.424   msaitoh 	}
   9743  1.522   msaitoh 
   9744  1.522   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   9745  1.522   msaitoh 		switch (sc->sc_phytype) {
   9746  1.522   msaitoh 		case WMPHY_IGP:
   9747  1.522   msaitoh 		case WMPHY_IGP_2:
   9748  1.522   msaitoh 		case WMPHY_IGP_3:
   9749  1.522   msaitoh 			wm_gmii_mdic_writereg(dev, phy, MII_IGPHY_PAGE_SELECT, reg);
   9750  1.522   msaitoh 			break;
   9751  1.522   msaitoh 		default:
   9752  1.522   msaitoh #ifdef WM_DEBUG
   9753  1.522   msaitoh 			device_printf(dev, "%s: PHYTYPE == 0x%x, addr = %02x",
   9754  1.522   msaitoh 			    __func__, sc->sc_phytype, reg);
   9755  1.522   msaitoh #endif
   9756  1.522   msaitoh 			break;
   9757  1.522   msaitoh 		}
   9758  1.522   msaitoh 	}
   9759  1.522   msaitoh 
   9760  1.522   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   9761  1.424   msaitoh 	sc->phy.release(sc);
   9762  1.424   msaitoh }
   9763  1.424   msaitoh 
   9764  1.424   msaitoh /*
   9765  1.281   msaitoh  * wm_gmii_i80003_readreg:	[mii interface function]
   9766  1.281   msaitoh  *
   9767  1.281   msaitoh  *	Read a PHY register on the kumeran
   9768  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   9769  1.281   msaitoh  * ressource ...
   9770  1.281   msaitoh  */
   9771  1.281   msaitoh static int
   9772  1.521   msaitoh wm_gmii_i80003_readreg(device_t dev, int phy, int reg)
   9773  1.281   msaitoh {
   9774  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9775  1.281   msaitoh 	int rv;
   9776    1.1   thorpej 
   9777  1.281   msaitoh 	if (phy != 1) /* only one PHY on kumeran bus */
   9778  1.281   msaitoh 		return 0;
   9779    1.1   thorpej 
   9780  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   9781  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   9782  1.281   msaitoh 		return 0;
   9783    1.1   thorpej 	}
   9784  1.186   msaitoh 
   9785  1.432   msaitoh 	if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG) {
   9786  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, phy, GG82563_PHY_PAGE_SELECT,
   9787  1.281   msaitoh 		    reg >> GG82563_PAGE_SHIFT);
   9788  1.281   msaitoh 	} else {
   9789  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, phy, GG82563_PHY_PAGE_SELECT_ALT,
   9790  1.281   msaitoh 		    reg >> GG82563_PAGE_SHIFT);
   9791  1.189   msaitoh 	}
   9792  1.281   msaitoh 	/* Wait more 200us for a bug of the ready bit in the MDIC register */
   9793  1.281   msaitoh 	delay(200);
   9794  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   9795  1.281   msaitoh 	delay(200);
   9796  1.424   msaitoh 	sc->phy.release(sc);
   9797  1.189   msaitoh 
   9798  1.281   msaitoh 	return rv;
   9799  1.281   msaitoh }
   9800  1.190   msaitoh 
   9801  1.281   msaitoh /*
   9802  1.281   msaitoh  * wm_gmii_i80003_writereg:	[mii interface function]
   9803  1.281   msaitoh  *
   9804  1.281   msaitoh  *	Write a PHY register on the kumeran.
   9805  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   9806  1.281   msaitoh  * ressource ...
   9807  1.281   msaitoh  */
   9808  1.281   msaitoh static void
   9809  1.521   msaitoh wm_gmii_i80003_writereg(device_t dev, int phy, int reg, int val)
   9810  1.281   msaitoh {
   9811  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9812  1.221   msaitoh 
   9813  1.281   msaitoh 	if (phy != 1) /* only one PHY on kumeran bus */
   9814  1.281   msaitoh 		return;
   9815  1.190   msaitoh 
   9816  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   9817  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   9818  1.281   msaitoh 		return;
   9819  1.281   msaitoh 	}
   9820  1.192   msaitoh 
   9821  1.432   msaitoh 	if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG) {
   9822  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, phy, GG82563_PHY_PAGE_SELECT,
   9823  1.281   msaitoh 		    reg >> GG82563_PAGE_SHIFT);
   9824  1.281   msaitoh 	} else {
   9825  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, phy, GG82563_PHY_PAGE_SELECT_ALT,
   9826  1.281   msaitoh 		    reg >> GG82563_PAGE_SHIFT);
   9827  1.189   msaitoh 	}
   9828  1.281   msaitoh 	/* Wait more 200us for a bug of the ready bit in the MDIC register */
   9829  1.281   msaitoh 	delay(200);
   9830  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   9831  1.281   msaitoh 	delay(200);
   9832  1.281   msaitoh 
   9833  1.424   msaitoh 	sc->phy.release(sc);
   9834    1.1   thorpej }
   9835    1.1   thorpej 
   9836    1.1   thorpej /*
   9837  1.281   msaitoh  * wm_gmii_bm_readreg:	[mii interface function]
   9838  1.265   msaitoh  *
   9839  1.281   msaitoh  *	Read a PHY register on the kumeran
   9840  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   9841  1.281   msaitoh  * ressource ...
   9842  1.265   msaitoh  */
   9843  1.265   msaitoh static int
   9844  1.521   msaitoh wm_gmii_bm_readreg(device_t dev, int phy, int reg)
   9845  1.265   msaitoh {
   9846  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9847  1.435   msaitoh 	uint16_t page = reg >> BME1000_PAGE_SHIFT;
   9848  1.435   msaitoh 	uint16_t val;
   9849  1.281   msaitoh 	int rv;
   9850  1.265   msaitoh 
   9851  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   9852  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   9853  1.281   msaitoh 		return 0;
   9854  1.281   msaitoh 	}
   9855  1.265   msaitoh 
   9856  1.435   msaitoh 	if ((sc->sc_type != WM_T_82574) && (sc->sc_type != WM_T_82583))
   9857  1.435   msaitoh 		phy = ((page >= 768) || ((page == 0) && (reg == 25))
   9858  1.435   msaitoh 		    || (reg == 31)) ? 1 : phy;
   9859  1.435   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   9860  1.435   msaitoh 	if (page == BM_WUC_PAGE) {
   9861  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &val, 1);
   9862  1.435   msaitoh 		rv = val;
   9863  1.435   msaitoh 		goto release;
   9864  1.435   msaitoh 	}
   9865  1.435   msaitoh 
   9866  1.281   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   9867  1.435   msaitoh 		if ((phy == 1) && (sc->sc_type != WM_T_82574)
   9868  1.435   msaitoh 		    && (sc->sc_type != WM_T_82583))
   9869  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   9870  1.435   msaitoh 			    MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
   9871  1.281   msaitoh 		else
   9872  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   9873  1.435   msaitoh 			    BME1000_PHY_PAGE_SELECT, page);
   9874  1.265   msaitoh 	}
   9875  1.265   msaitoh 
   9876  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   9877  1.435   msaitoh 
   9878  1.435   msaitoh release:
   9879  1.424   msaitoh 	sc->phy.release(sc);
   9880  1.281   msaitoh 	return rv;
   9881  1.265   msaitoh }
   9882  1.265   msaitoh 
   9883  1.265   msaitoh /*
   9884  1.281   msaitoh  * wm_gmii_bm_writereg:	[mii interface function]
   9885    1.1   thorpej  *
   9886  1.281   msaitoh  *	Write a PHY register on the kumeran.
   9887  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   9888  1.281   msaitoh  * ressource ...
   9889    1.1   thorpej  */
   9890   1.47   thorpej static void
   9891  1.521   msaitoh wm_gmii_bm_writereg(device_t dev, int phy, int reg, int val)
   9892  1.281   msaitoh {
   9893  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9894  1.435   msaitoh 	uint16_t page = reg >> BME1000_PAGE_SHIFT;
   9895  1.281   msaitoh 
   9896  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   9897  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   9898  1.281   msaitoh 		return;
   9899  1.281   msaitoh 	}
   9900  1.281   msaitoh 
   9901  1.435   msaitoh 	if ((sc->sc_type != WM_T_82574) && (sc->sc_type != WM_T_82583))
   9902  1.435   msaitoh 		phy = ((page >= 768) || ((page == 0) && (reg == 25))
   9903  1.435   msaitoh 		    || (reg == 31)) ? 1 : phy;
   9904  1.435   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   9905  1.435   msaitoh 	if (page == BM_WUC_PAGE) {
   9906  1.435   msaitoh 		uint16_t tmp;
   9907  1.435   msaitoh 
   9908  1.435   msaitoh 		tmp = val;
   9909  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &tmp, 0);
   9910  1.435   msaitoh 		goto release;
   9911  1.435   msaitoh 	}
   9912  1.435   msaitoh 
   9913  1.281   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   9914  1.435   msaitoh 		if ((phy == 1) && (sc->sc_type != WM_T_82574)
   9915  1.435   msaitoh 		    && (sc->sc_type != WM_T_82583))
   9916  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   9917  1.435   msaitoh 			    MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
   9918  1.281   msaitoh 		else
   9919  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   9920  1.435   msaitoh 			    BME1000_PHY_PAGE_SELECT, page);
   9921  1.281   msaitoh 	}
   9922  1.281   msaitoh 
   9923  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   9924  1.435   msaitoh 
   9925  1.435   msaitoh release:
   9926  1.424   msaitoh 	sc->phy.release(sc);
   9927  1.281   msaitoh }
   9928  1.281   msaitoh 
   9929  1.281   msaitoh static void
   9930  1.521   msaitoh wm_access_phy_wakeup_reg_bm(device_t dev, int offset, int16_t *val, int rd)
   9931    1.1   thorpej {
   9932  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9933  1.281   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(offset);
   9934  1.441   msaitoh 	uint16_t wuce, reg;
   9935  1.281   msaitoh 
   9936  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   9937  1.521   msaitoh 		device_xname(dev), __func__));
   9938  1.281   msaitoh 	/* XXX Gig must be disabled for MDIO accesses to page 800 */
   9939  1.281   msaitoh 	if (sc->sc_type == WM_T_PCH) {
   9940  1.281   msaitoh 		/* XXX e1000 driver do nothing... why? */
   9941  1.281   msaitoh 	}
   9942  1.281   msaitoh 
   9943  1.441   msaitoh 	/*
   9944  1.441   msaitoh 	 * 1) Enable PHY wakeup register first.
   9945  1.441   msaitoh 	 * See e1000_enable_phy_wakeup_reg_access_bm().
   9946  1.441   msaitoh 	 */
   9947  1.441   msaitoh 
   9948  1.281   msaitoh 	/* Set page 769 */
   9949  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   9950  1.281   msaitoh 	    BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
   9951  1.281   msaitoh 
   9952  1.441   msaitoh 	/* Read WUCE and save it */
   9953  1.521   msaitoh 	wuce = wm_gmii_mdic_readreg(dev, 1, BM_WUC_ENABLE_REG);
   9954  1.281   msaitoh 
   9955  1.441   msaitoh 	reg = wuce | BM_WUC_ENABLE_BIT;
   9956  1.441   msaitoh 	reg &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
   9957  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ENABLE_REG, reg);
   9958  1.281   msaitoh 
   9959  1.281   msaitoh 	/* Select page 800 */
   9960  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   9961  1.281   msaitoh 	    BM_WUC_PAGE << BME1000_PAGE_SHIFT);
   9962    1.1   thorpej 
   9963  1.441   msaitoh 	/*
   9964  1.441   msaitoh 	 * 2) Access PHY wakeup register.
   9965  1.441   msaitoh 	 * See e1000_access_phy_wakeup_reg_bm.
   9966  1.441   msaitoh 	 */
   9967  1.441   msaitoh 
   9968  1.281   msaitoh 	/* Write page 800 */
   9969  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ADDRESS_OPCODE, regnum);
   9970    1.1   thorpej 
   9971  1.281   msaitoh 	if (rd)
   9972  1.521   msaitoh 		*val = wm_gmii_mdic_readreg(dev, 1, BM_WUC_DATA_OPCODE);
   9973  1.127    bouyer 	else
   9974  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, 1, BM_WUC_DATA_OPCODE, *val);
   9975  1.281   msaitoh 
   9976  1.441   msaitoh 	/*
   9977  1.441   msaitoh 	 * 3) Disable PHY wakeup register.
   9978  1.441   msaitoh 	 * See e1000_disable_phy_wakeup_reg_access_bm().
   9979  1.441   msaitoh 	 */
   9980  1.281   msaitoh 	/* Set page 769 */
   9981  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   9982  1.281   msaitoh 	    BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
   9983  1.281   msaitoh 
   9984  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ENABLE_REG, wuce);
   9985  1.281   msaitoh }
   9986  1.281   msaitoh 
   9987  1.281   msaitoh /*
   9988  1.281   msaitoh  * wm_gmii_hv_readreg:	[mii interface function]
   9989  1.281   msaitoh  *
   9990  1.281   msaitoh  *	Read a PHY register on the kumeran
   9991  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   9992  1.281   msaitoh  * ressource ...
   9993  1.281   msaitoh  */
   9994  1.281   msaitoh static int
   9995  1.521   msaitoh wm_gmii_hv_readreg(device_t dev, int phy, int reg)
   9996  1.281   msaitoh {
   9997  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9998  1.281   msaitoh 	int rv;
   9999  1.281   msaitoh 
   10000  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   10001  1.521   msaitoh 		device_xname(dev), __func__));
   10002  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10003  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10004  1.281   msaitoh 		return 0;
   10005  1.281   msaitoh 	}
   10006  1.281   msaitoh 
   10007  1.521   msaitoh 	rv = wm_gmii_hv_readreg_locked(dev, phy, reg);
   10008  1.424   msaitoh 	sc->phy.release(sc);
   10009  1.424   msaitoh 	return rv;
   10010  1.424   msaitoh }
   10011  1.424   msaitoh 
   10012  1.424   msaitoh static int
   10013  1.521   msaitoh wm_gmii_hv_readreg_locked(device_t dev, int phy, int reg)
   10014  1.424   msaitoh {
   10015  1.424   msaitoh 	uint16_t page = BM_PHY_REG_PAGE(reg);
   10016  1.424   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(reg);
   10017  1.424   msaitoh 	uint16_t val;
   10018  1.424   msaitoh 	int rv;
   10019  1.424   msaitoh 
   10020  1.437   msaitoh 	phy = (page >= HV_INTC_FC_PAGE_START) ? 1 : phy;
   10021    1.1   thorpej 
   10022  1.281   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10023  1.281   msaitoh 	if (page == BM_WUC_PAGE) {
   10024  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &val, 1);
   10025  1.281   msaitoh 		return val;
   10026  1.281   msaitoh 	}
   10027    1.1   thorpej 
   10028  1.244   msaitoh 	/*
   10029  1.281   msaitoh 	 * Lower than page 768 works differently than the rest so it has its
   10030  1.281   msaitoh 	 * own func
   10031  1.244   msaitoh 	 */
   10032  1.281   msaitoh 	if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
   10033  1.281   msaitoh 		printf("gmii_hv_readreg!!!\n");
   10034  1.281   msaitoh 		return 0;
   10035  1.281   msaitoh 	}
   10036  1.281   msaitoh 
   10037  1.281   msaitoh 	if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
   10038  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10039  1.281   msaitoh 		    page << BME1000_PAGE_SHIFT);
   10040    1.1   thorpej 	}
   10041    1.1   thorpej 
   10042  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, regnum & MII_ADDRMASK);
   10043  1.281   msaitoh 	return rv;
   10044  1.281   msaitoh }
   10045    1.1   thorpej 
   10046  1.281   msaitoh /*
   10047  1.281   msaitoh  * wm_gmii_hv_writereg:	[mii interface function]
   10048  1.281   msaitoh  *
   10049  1.281   msaitoh  *	Write a PHY register on the kumeran.
   10050  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10051  1.281   msaitoh  * ressource ...
   10052  1.281   msaitoh  */
   10053  1.281   msaitoh static void
   10054  1.521   msaitoh wm_gmii_hv_writereg(device_t dev, int phy, int reg, int val)
   10055  1.281   msaitoh {
   10056  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10057    1.1   thorpej 
   10058  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   10059  1.521   msaitoh 		device_xname(dev), __func__));
   10060  1.425   msaitoh 
   10061  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10062  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10063  1.281   msaitoh 		return;
   10064  1.281   msaitoh 	}
   10065  1.208   msaitoh 
   10066  1.521   msaitoh 	wm_gmii_hv_writereg_locked(dev, phy, reg, val);
   10067  1.424   msaitoh 	sc->phy.release(sc);
   10068  1.424   msaitoh }
   10069  1.424   msaitoh 
   10070  1.424   msaitoh static void
   10071  1.521   msaitoh wm_gmii_hv_writereg_locked(device_t dev, int phy, int reg, int val)
   10072  1.424   msaitoh {
   10073  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10074  1.424   msaitoh 	uint16_t page = BM_PHY_REG_PAGE(reg);
   10075  1.424   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(reg);
   10076  1.424   msaitoh 
   10077  1.437   msaitoh 	phy = (page >= HV_INTC_FC_PAGE_START) ? 1 : phy;
   10078  1.265   msaitoh 
   10079  1.281   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10080  1.281   msaitoh 	if (page == BM_WUC_PAGE) {
   10081  1.281   msaitoh 		uint16_t tmp;
   10082  1.208   msaitoh 
   10083  1.281   msaitoh 		tmp = val;
   10084  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &tmp, 0);
   10085  1.281   msaitoh 		return;
   10086  1.208   msaitoh 	}
   10087  1.184   msaitoh 
   10088  1.244   msaitoh 	/*
   10089  1.281   msaitoh 	 * Lower than page 768 works differently than the rest so it has its
   10090  1.281   msaitoh 	 * own func
   10091  1.244   msaitoh 	 */
   10092  1.281   msaitoh 	if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
   10093  1.281   msaitoh 		printf("gmii_hv_writereg!!!\n");
   10094  1.281   msaitoh 		return;
   10095  1.221   msaitoh 	}
   10096  1.244   msaitoh 
   10097  1.437   msaitoh 	{
   10098  1.437   msaitoh 		/*
   10099  1.437   msaitoh 		 * XXX Workaround MDIO accesses being disabled after entering
   10100  1.437   msaitoh 		 * IEEE Power Down (whenever bit 11 of the PHY control
   10101  1.437   msaitoh 		 * register is set)
   10102  1.437   msaitoh 		 */
   10103  1.437   msaitoh 		if (sc->sc_phytype == WMPHY_82578) {
   10104  1.437   msaitoh 			struct mii_softc *child;
   10105  1.437   msaitoh 
   10106  1.437   msaitoh 			child = LIST_FIRST(&sc->sc_mii.mii_phys);
   10107  1.437   msaitoh 			if ((child != NULL) && (child->mii_mpd_rev >= 1)
   10108  1.437   msaitoh 			    && (phy == 2) && ((regnum & MII_ADDRMASK) == 0)
   10109  1.437   msaitoh 			    && ((val & (1 << 11)) != 0)) {
   10110  1.437   msaitoh 				printf("XXX need workaround\n");
   10111  1.437   msaitoh 			}
   10112  1.437   msaitoh 		}
   10113  1.184   msaitoh 
   10114  1.437   msaitoh 		if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
   10115  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10116  1.437   msaitoh 			    page << BME1000_PAGE_SHIFT);
   10117  1.437   msaitoh 		}
   10118  1.281   msaitoh 	}
   10119  1.281   msaitoh 
   10120  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, regnum & MII_ADDRMASK, val);
   10121  1.281   msaitoh }
   10122  1.281   msaitoh 
   10123  1.281   msaitoh /*
   10124  1.281   msaitoh  * wm_gmii_82580_readreg:	[mii interface function]
   10125  1.281   msaitoh  *
   10126  1.281   msaitoh  *	Read a PHY register on the 82580 and I350.
   10127  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10128  1.281   msaitoh  * ressource ...
   10129  1.281   msaitoh  */
   10130  1.281   msaitoh static int
   10131  1.521   msaitoh wm_gmii_82580_readreg(device_t dev, int phy, int reg)
   10132  1.281   msaitoh {
   10133  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10134  1.281   msaitoh 	int rv;
   10135  1.281   msaitoh 
   10136  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10137  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10138  1.281   msaitoh 		return 0;
   10139  1.184   msaitoh 	}
   10140  1.244   msaitoh 
   10141  1.522   msaitoh #ifdef DIAGNOSTIC
   10142  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   10143  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   10144  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   10145  1.522   msaitoh 		reg &= MII_ADDRMASK;
   10146  1.522   msaitoh 	}
   10147  1.522   msaitoh #endif
   10148  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg);
   10149  1.202   msaitoh 
   10150  1.424   msaitoh 	sc->phy.release(sc);
   10151  1.281   msaitoh 	return rv;
   10152  1.281   msaitoh }
   10153  1.202   msaitoh 
   10154  1.281   msaitoh /*
   10155  1.281   msaitoh  * wm_gmii_82580_writereg:	[mii interface function]
   10156  1.281   msaitoh  *
   10157  1.281   msaitoh  *	Write a PHY register on the 82580 and I350.
   10158  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10159  1.281   msaitoh  * ressource ...
   10160  1.281   msaitoh  */
   10161  1.281   msaitoh static void
   10162  1.521   msaitoh wm_gmii_82580_writereg(device_t dev, int phy, int reg, int val)
   10163  1.281   msaitoh {
   10164  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10165  1.202   msaitoh 
   10166  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10167  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10168  1.281   msaitoh 		return;
   10169  1.192   msaitoh 	}
   10170  1.281   msaitoh 
   10171  1.522   msaitoh #ifdef DIAGNOSTIC
   10172  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   10173  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   10174  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   10175  1.522   msaitoh 		reg &= MII_ADDRMASK;
   10176  1.522   msaitoh 	}
   10177  1.522   msaitoh #endif
   10178  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg, val);
   10179  1.281   msaitoh 
   10180  1.424   msaitoh 	sc->phy.release(sc);
   10181    1.1   thorpej }
   10182    1.1   thorpej 
   10183    1.1   thorpej /*
   10184  1.329   msaitoh  * wm_gmii_gs40g_readreg:	[mii interface function]
   10185  1.329   msaitoh  *
   10186  1.329   msaitoh  *	Read a PHY register on the I2100 and I211.
   10187  1.329   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10188  1.329   msaitoh  * ressource ...
   10189  1.329   msaitoh  */
   10190  1.329   msaitoh static int
   10191  1.521   msaitoh wm_gmii_gs40g_readreg(device_t dev, int phy, int reg)
   10192  1.329   msaitoh {
   10193  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10194  1.329   msaitoh 	int page, offset;
   10195  1.329   msaitoh 	int rv;
   10196  1.329   msaitoh 
   10197  1.329   msaitoh 	/* Acquire semaphore */
   10198  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10199  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10200  1.329   msaitoh 		return 0;
   10201  1.329   msaitoh 	}
   10202  1.329   msaitoh 
   10203  1.329   msaitoh 	/* Page select */
   10204  1.329   msaitoh 	page = reg >> GS40G_PAGE_SHIFT;
   10205  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, GS40G_PAGE_SELECT, page);
   10206  1.329   msaitoh 
   10207  1.329   msaitoh 	/* Read reg */
   10208  1.329   msaitoh 	offset = reg & GS40G_OFFSET_MASK;
   10209  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, offset);
   10210  1.329   msaitoh 
   10211  1.424   msaitoh 	sc->phy.release(sc);
   10212  1.329   msaitoh 	return rv;
   10213  1.329   msaitoh }
   10214  1.329   msaitoh 
   10215  1.329   msaitoh /*
   10216  1.329   msaitoh  * wm_gmii_gs40g_writereg:	[mii interface function]
   10217  1.329   msaitoh  *
   10218  1.329   msaitoh  *	Write a PHY register on the I210 and I211.
   10219  1.329   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10220  1.329   msaitoh  * ressource ...
   10221  1.329   msaitoh  */
   10222  1.329   msaitoh static void
   10223  1.521   msaitoh wm_gmii_gs40g_writereg(device_t dev, int phy, int reg, int val)
   10224  1.329   msaitoh {
   10225  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10226  1.329   msaitoh 	int page, offset;
   10227  1.329   msaitoh 
   10228  1.329   msaitoh 	/* Acquire semaphore */
   10229  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10230  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10231  1.329   msaitoh 		return;
   10232  1.329   msaitoh 	}
   10233  1.329   msaitoh 
   10234  1.329   msaitoh 	/* Page select */
   10235  1.329   msaitoh 	page = reg >> GS40G_PAGE_SHIFT;
   10236  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, GS40G_PAGE_SELECT, page);
   10237  1.329   msaitoh 
   10238  1.329   msaitoh 	/* Write reg */
   10239  1.329   msaitoh 	offset = reg & GS40G_OFFSET_MASK;
   10240  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, offset, val);
   10241  1.329   msaitoh 
   10242  1.329   msaitoh 	/* Release semaphore */
   10243  1.424   msaitoh 	sc->phy.release(sc);
   10244  1.329   msaitoh }
   10245  1.329   msaitoh 
   10246  1.329   msaitoh /*
   10247  1.281   msaitoh  * wm_gmii_statchg:	[mii interface function]
   10248    1.1   thorpej  *
   10249  1.281   msaitoh  *	Callback from MII layer when media changes.
   10250    1.1   thorpej  */
   10251   1.47   thorpej static void
   10252  1.281   msaitoh wm_gmii_statchg(struct ifnet *ifp)
   10253    1.1   thorpej {
   10254    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   10255  1.281   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   10256    1.1   thorpej 
   10257  1.281   msaitoh 	sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
   10258  1.281   msaitoh 	sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   10259  1.281   msaitoh 	sc->sc_fcrtl &= ~FCRTL_XONE;
   10260    1.1   thorpej 
   10261  1.281   msaitoh 	/*
   10262  1.281   msaitoh 	 * Get flow control negotiation result.
   10263  1.281   msaitoh 	 */
   10264  1.281   msaitoh 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
   10265  1.281   msaitoh 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
   10266  1.281   msaitoh 		sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
   10267  1.281   msaitoh 		mii->mii_media_active &= ~IFM_ETH_FMASK;
   10268  1.281   msaitoh 	}
   10269    1.1   thorpej 
   10270  1.281   msaitoh 	if (sc->sc_flowflags & IFM_FLOW) {
   10271  1.281   msaitoh 		if (sc->sc_flowflags & IFM_ETH_TXPAUSE) {
   10272  1.281   msaitoh 			sc->sc_ctrl |= CTRL_TFCE;
   10273  1.281   msaitoh 			sc->sc_fcrtl |= FCRTL_XONE;
   10274  1.281   msaitoh 		}
   10275  1.281   msaitoh 		if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
   10276  1.281   msaitoh 			sc->sc_ctrl |= CTRL_RFCE;
   10277  1.281   msaitoh 	}
   10278  1.152    dyoung 
   10279  1.281   msaitoh 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   10280  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10281  1.281   msaitoh 		    ("%s: LINK: statchg: FDX\n", ifp->if_xname));
   10282  1.281   msaitoh 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   10283  1.152    dyoung 	} else {
   10284  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10285  1.281   msaitoh 		    ("%s: LINK: statchg: HDX\n", ifp->if_xname));
   10286  1.281   msaitoh 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   10287  1.281   msaitoh 	}
   10288  1.281   msaitoh 
   10289  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10290  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   10291  1.281   msaitoh 	CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
   10292  1.281   msaitoh 						 : WMREG_FCRTL, sc->sc_fcrtl);
   10293  1.281   msaitoh 	if (sc->sc_type == WM_T_80003) {
   10294  1.281   msaitoh 		switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
   10295  1.152    dyoung 		case IFM_1000_T:
   10296  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
   10297  1.281   msaitoh 			    KUMCTRLSTA_HD_CTRL_1000_DEFAULT);
   10298  1.281   msaitoh 			sc->sc_tipg =  TIPG_1000T_80003_DFLT;
   10299  1.152    dyoung 			break;
   10300  1.152    dyoung 		default:
   10301  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
   10302  1.281   msaitoh 			    KUMCTRLSTA_HD_CTRL_10_100_DEFAULT);
   10303  1.281   msaitoh 			sc->sc_tipg =  TIPG_10_100_80003_DFLT;
   10304  1.281   msaitoh 			break;
   10305  1.127    bouyer 		}
   10306  1.281   msaitoh 		CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   10307  1.127    bouyer 	}
   10308    1.1   thorpej }
   10309    1.1   thorpej 
   10310  1.453   msaitoh /* kumeran related (80003, ICH* and PCH*) */
   10311  1.453   msaitoh 
   10312  1.281   msaitoh /*
   10313  1.281   msaitoh  * wm_kmrn_readreg:
   10314  1.281   msaitoh  *
   10315  1.281   msaitoh  *	Read a kumeran register
   10316  1.281   msaitoh  */
   10317  1.281   msaitoh static int
   10318  1.281   msaitoh wm_kmrn_readreg(struct wm_softc *sc, int reg)
   10319    1.1   thorpej {
   10320  1.281   msaitoh 	int rv;
   10321    1.1   thorpej 
   10322  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10323  1.424   msaitoh 		rv = wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10324  1.424   msaitoh 	else
   10325  1.424   msaitoh 		rv = sc->phy.acquire(sc);
   10326  1.424   msaitoh 	if (rv != 0) {
   10327  1.521   msaitoh 		device_printf(sc->sc_dev, "%s: failed to get semaphore\n",
   10328  1.521   msaitoh 		    __func__);
   10329  1.424   msaitoh 		return 0;
   10330    1.1   thorpej 	}
   10331    1.1   thorpej 
   10332  1.425   msaitoh 	rv = wm_kmrn_readreg_locked(sc, reg);
   10333  1.424   msaitoh 
   10334  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10335  1.424   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10336  1.424   msaitoh 	else
   10337  1.424   msaitoh 		sc->phy.release(sc);
   10338  1.424   msaitoh 
   10339  1.424   msaitoh 	return rv;
   10340  1.424   msaitoh }
   10341  1.424   msaitoh 
   10342  1.424   msaitoh static int
   10343  1.424   msaitoh wm_kmrn_readreg_locked(struct wm_softc *sc, int reg)
   10344  1.424   msaitoh {
   10345  1.424   msaitoh 	int rv;
   10346  1.424   msaitoh 
   10347  1.281   msaitoh 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
   10348  1.281   msaitoh 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
   10349  1.281   msaitoh 	    KUMCTRLSTA_REN);
   10350  1.266   msaitoh 	CSR_WRITE_FLUSH(sc);
   10351  1.281   msaitoh 	delay(2);
   10352    1.1   thorpej 
   10353  1.281   msaitoh 	rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
   10354    1.1   thorpej 
   10355  1.281   msaitoh 	return rv;
   10356    1.1   thorpej }
   10357    1.1   thorpej 
   10358    1.1   thorpej /*
   10359  1.281   msaitoh  * wm_kmrn_writereg:
   10360    1.1   thorpej  *
   10361  1.281   msaitoh  *	Write a kumeran register
   10362    1.1   thorpej  */
   10363  1.281   msaitoh static void
   10364  1.281   msaitoh wm_kmrn_writereg(struct wm_softc *sc, int reg, int val)
   10365    1.1   thorpej {
   10366  1.424   msaitoh 	int rv;
   10367    1.1   thorpej 
   10368  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10369  1.424   msaitoh 		rv = wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10370  1.424   msaitoh 	else
   10371  1.424   msaitoh 		rv = sc->phy.acquire(sc);
   10372  1.424   msaitoh 	if (rv != 0) {
   10373  1.521   msaitoh 		device_printf(sc->sc_dev, "%s: failed to get semaphore\n",
   10374  1.521   msaitoh 		    __func__);
   10375  1.424   msaitoh 		return;
   10376  1.281   msaitoh 	}
   10377    1.1   thorpej 
   10378  1.424   msaitoh 	wm_kmrn_writereg_locked(sc, reg, val);
   10379  1.424   msaitoh 
   10380  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10381  1.424   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10382  1.424   msaitoh 	else
   10383  1.424   msaitoh 		sc->phy.release(sc);
   10384  1.424   msaitoh }
   10385  1.424   msaitoh 
   10386  1.424   msaitoh static void
   10387  1.424   msaitoh wm_kmrn_writereg_locked(struct wm_softc *sc, int reg, int val)
   10388  1.424   msaitoh {
   10389  1.424   msaitoh 
   10390  1.281   msaitoh 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
   10391  1.281   msaitoh 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
   10392  1.281   msaitoh 	    (val & KUMCTRLSTA_MASK));
   10393    1.1   thorpej }
   10394    1.1   thorpej 
   10395  1.281   msaitoh /* SGMII related */
   10396  1.281   msaitoh 
   10397    1.1   thorpej /*
   10398  1.281   msaitoh  * wm_sgmii_uses_mdio
   10399    1.1   thorpej  *
   10400  1.281   msaitoh  * Check whether the transaction is to the internal PHY or the external
   10401  1.281   msaitoh  * MDIO interface. Return true if it's MDIO.
   10402  1.281   msaitoh  */
   10403  1.281   msaitoh static bool
   10404  1.281   msaitoh wm_sgmii_uses_mdio(struct wm_softc *sc)
   10405  1.281   msaitoh {
   10406  1.281   msaitoh 	uint32_t reg;
   10407  1.281   msaitoh 	bool ismdio = false;
   10408  1.281   msaitoh 
   10409  1.281   msaitoh 	switch (sc->sc_type) {
   10410  1.281   msaitoh 	case WM_T_82575:
   10411  1.281   msaitoh 	case WM_T_82576:
   10412  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MDIC);
   10413  1.281   msaitoh 		ismdio = ((reg & MDIC_DEST) != 0);
   10414  1.281   msaitoh 		break;
   10415  1.281   msaitoh 	case WM_T_82580:
   10416  1.281   msaitoh 	case WM_T_I350:
   10417  1.281   msaitoh 	case WM_T_I354:
   10418  1.281   msaitoh 	case WM_T_I210:
   10419  1.281   msaitoh 	case WM_T_I211:
   10420  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MDICNFG);
   10421  1.281   msaitoh 		ismdio = ((reg & MDICNFG_DEST) != 0);
   10422  1.281   msaitoh 		break;
   10423  1.281   msaitoh 	default:
   10424  1.281   msaitoh 		break;
   10425  1.281   msaitoh 	}
   10426    1.1   thorpej 
   10427  1.281   msaitoh 	return ismdio;
   10428    1.1   thorpej }
   10429    1.1   thorpej 
   10430    1.1   thorpej /*
   10431  1.281   msaitoh  * wm_sgmii_readreg:	[mii interface function]
   10432    1.1   thorpej  *
   10433  1.281   msaitoh  *	Read a PHY register on the SGMII
   10434  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10435  1.281   msaitoh  * ressource ...
   10436    1.1   thorpej  */
   10437   1.47   thorpej static int
   10438  1.521   msaitoh wm_sgmii_readreg(device_t dev, int phy, int reg)
   10439    1.1   thorpej {
   10440  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10441  1.281   msaitoh 	uint32_t i2ccmd;
   10442    1.1   thorpej 	int i, rv;
   10443    1.1   thorpej 
   10444  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10445  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10446  1.281   msaitoh 		return 0;
   10447  1.281   msaitoh 	}
   10448  1.281   msaitoh 
   10449  1.281   msaitoh 	i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
   10450  1.281   msaitoh 	    | (phy << I2CCMD_PHY_ADDR_SHIFT)
   10451  1.281   msaitoh 	    | I2CCMD_OPCODE_READ;
   10452  1.281   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   10453    1.1   thorpej 
   10454  1.281   msaitoh 	/* Poll the ready bit */
   10455  1.281   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   10456  1.281   msaitoh 		delay(50);
   10457  1.281   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   10458  1.281   msaitoh 		if (i2ccmd & I2CCMD_READY)
   10459    1.1   thorpej 			break;
   10460    1.1   thorpej 	}
   10461  1.281   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   10462  1.521   msaitoh 		device_printf(dev, "I2CCMD Read did not complete\n");
   10463  1.281   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   10464  1.521   msaitoh 		device_printf(dev, "I2CCMD Error bit set\n");
   10465    1.1   thorpej 
   10466  1.281   msaitoh 	rv = ((i2ccmd >> 8) & 0x00ff) | ((i2ccmd << 8) & 0xff00);
   10467    1.1   thorpej 
   10468  1.424   msaitoh 	sc->phy.release(sc);
   10469  1.194   msaitoh 	return rv;
   10470    1.1   thorpej }
   10471    1.1   thorpej 
   10472    1.1   thorpej /*
   10473  1.281   msaitoh  * wm_sgmii_writereg:	[mii interface function]
   10474    1.1   thorpej  *
   10475  1.281   msaitoh  *	Write a PHY register on the SGMII.
   10476  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10477  1.281   msaitoh  * ressource ...
   10478    1.1   thorpej  */
   10479   1.47   thorpej static void
   10480  1.521   msaitoh wm_sgmii_writereg(device_t dev, int phy, int reg, int val)
   10481    1.1   thorpej {
   10482  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10483  1.281   msaitoh 	uint32_t i2ccmd;
   10484    1.1   thorpej 	int i;
   10485  1.314   msaitoh 	int val_swapped;
   10486    1.1   thorpej 
   10487  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10488  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10489  1.281   msaitoh 		return;
   10490  1.281   msaitoh 	}
   10491  1.314   msaitoh 	/* Swap the data bytes for the I2C interface */
   10492  1.314   msaitoh 	val_swapped = ((val >> 8) & 0x00FF) | ((val << 8) & 0xFF00);
   10493  1.281   msaitoh 	i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
   10494  1.281   msaitoh 	    | (phy << I2CCMD_PHY_ADDR_SHIFT)
   10495  1.314   msaitoh 	    | I2CCMD_OPCODE_WRITE | val_swapped;
   10496  1.281   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   10497    1.1   thorpej 
   10498  1.281   msaitoh 	/* Poll the ready bit */
   10499  1.281   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   10500  1.281   msaitoh 		delay(50);
   10501  1.281   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   10502  1.281   msaitoh 		if (i2ccmd & I2CCMD_READY)
   10503    1.1   thorpej 			break;
   10504    1.1   thorpej 	}
   10505  1.281   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   10506  1.521   msaitoh 		device_printf(dev, "I2CCMD Write did not complete\n");
   10507  1.281   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   10508  1.521   msaitoh 		device_printf(dev, "I2CCMD Error bit set\n");
   10509    1.1   thorpej 
   10510  1.424   msaitoh 	sc->phy.release(sc);
   10511    1.1   thorpej }
   10512    1.1   thorpej 
   10513  1.281   msaitoh /* TBI related */
   10514  1.281   msaitoh 
   10515  1.127    bouyer /*
   10516  1.281   msaitoh  * wm_tbi_mediainit:
   10517  1.127    bouyer  *
   10518  1.281   msaitoh  *	Initialize media for use on 1000BASE-X devices.
   10519  1.127    bouyer  */
   10520  1.127    bouyer static void
   10521  1.281   msaitoh wm_tbi_mediainit(struct wm_softc *sc)
   10522  1.127    bouyer {
   10523  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   10524  1.281   msaitoh 	const char *sep = "";
   10525  1.281   msaitoh 
   10526  1.281   msaitoh 	if (sc->sc_type < WM_T_82543)
   10527  1.281   msaitoh 		sc->sc_tipg = TIPG_WM_DFLT;
   10528  1.281   msaitoh 	else
   10529  1.281   msaitoh 		sc->sc_tipg = TIPG_LG_DFLT;
   10530  1.281   msaitoh 
   10531  1.325   msaitoh 	sc->sc_tbi_serdes_anegticks = 5;
   10532  1.281   msaitoh 
   10533  1.281   msaitoh 	/* Initialize our media structures */
   10534  1.281   msaitoh 	sc->sc_mii.mii_ifp = ifp;
   10535  1.325   msaitoh 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   10536  1.281   msaitoh 
   10537  1.325   msaitoh 	if ((sc->sc_type >= WM_T_82575)
   10538  1.325   msaitoh 	    && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   10539  1.327   msaitoh 		ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
   10540  1.325   msaitoh 		    wm_serdes_mediachange, wm_serdes_mediastatus);
   10541  1.325   msaitoh 	else
   10542  1.327   msaitoh 		ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
   10543  1.325   msaitoh 		    wm_tbi_mediachange, wm_tbi_mediastatus);
   10544  1.281   msaitoh 
   10545  1.281   msaitoh 	/*
   10546  1.281   msaitoh 	 * SWD Pins:
   10547  1.281   msaitoh 	 *
   10548  1.281   msaitoh 	 *	0 = Link LED (output)
   10549  1.281   msaitoh 	 *	1 = Loss Of Signal (input)
   10550  1.281   msaitoh 	 */
   10551  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SWDPIO(0);
   10552  1.325   msaitoh 
   10553  1.325   msaitoh 	/* XXX Perhaps this is only for TBI */
   10554  1.325   msaitoh 	if (sc->sc_mediatype != WM_MEDIATYPE_SERDES)
   10555  1.325   msaitoh 		sc->sc_ctrl &= ~CTRL_SWDPIO(1);
   10556  1.325   msaitoh 
   10557  1.311   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   10558  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_LRST;
   10559  1.281   msaitoh 
   10560  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10561  1.127    bouyer 
   10562  1.281   msaitoh #define	ADD(ss, mm, dd)							\
   10563  1.281   msaitoh do {									\
   10564  1.281   msaitoh 	aprint_normal("%s%s", sep, ss);					\
   10565  1.388   msaitoh 	ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | (mm), (dd), NULL); \
   10566  1.281   msaitoh 	sep = ", ";							\
   10567  1.281   msaitoh } while (/*CONSTCOND*/0)
   10568  1.127    bouyer 
   10569  1.281   msaitoh 	aprint_normal_dev(sc->sc_dev, "");
   10570  1.285   msaitoh 
   10571  1.457   msaitoh 	if (sc->sc_type == WM_T_I354) {
   10572  1.457   msaitoh 		uint32_t status;
   10573  1.457   msaitoh 
   10574  1.457   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   10575  1.457   msaitoh 		if (((status & STATUS_2P5_SKU) != 0)
   10576  1.457   msaitoh 		    && ((status & STATUS_2P5_SKU_OVER) == 0)) {
   10577  1.509   msaitoh 			ADD("2500baseKX-FDX", IFM_2500_KX | IFM_FDX,ANAR_X_FD);
   10578  1.457   msaitoh 		} else
   10579  1.509   msaitoh 			ADD("1000baseKX-FDX", IFM_1000_KX | IFM_FDX,ANAR_X_FD);
   10580  1.457   msaitoh 	} else if (sc->sc_type == WM_T_82545) {
   10581  1.457   msaitoh 		/* Only 82545 is LX (XXX except SFP) */
   10582  1.285   msaitoh 		ADD("1000baseLX", IFM_1000_LX, ANAR_X_HD);
   10583  1.388   msaitoh 		ADD("1000baseLX-FDX", IFM_1000_LX | IFM_FDX, ANAR_X_FD);
   10584  1.285   msaitoh 	} else {
   10585  1.285   msaitoh 		ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
   10586  1.388   msaitoh 		ADD("1000baseSX-FDX", IFM_1000_SX | IFM_FDX, ANAR_X_FD);
   10587  1.285   msaitoh 	}
   10588  1.388   msaitoh 	ADD("auto", IFM_AUTO, ANAR_X_FD | ANAR_X_HD);
   10589  1.281   msaitoh 	aprint_normal("\n");
   10590  1.127    bouyer 
   10591  1.281   msaitoh #undef ADD
   10592  1.127    bouyer 
   10593  1.281   msaitoh 	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
   10594  1.127    bouyer }
   10595  1.127    bouyer 
   10596  1.127    bouyer /*
   10597  1.281   msaitoh  * wm_tbi_mediachange:	[ifmedia interface function]
   10598  1.167   msaitoh  *
   10599  1.281   msaitoh  *	Set hardware to newly-selected media on a 1000BASE-X device.
   10600  1.167   msaitoh  */
   10601  1.281   msaitoh static int
   10602  1.281   msaitoh wm_tbi_mediachange(struct ifnet *ifp)
   10603  1.167   msaitoh {
   10604  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   10605  1.281   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   10606  1.281   msaitoh 	uint32_t status;
   10607  1.281   msaitoh 	int i;
   10608  1.167   msaitoh 
   10609  1.325   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {
   10610  1.325   msaitoh 		/* XXX need some work for >= 82571 and < 82575 */
   10611  1.325   msaitoh 		if (sc->sc_type < WM_T_82575)
   10612  1.325   msaitoh 			return 0;
   10613  1.325   msaitoh 	}
   10614  1.167   msaitoh 
   10615  1.285   msaitoh 	if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)
   10616  1.285   msaitoh 	    || (sc->sc_type >= WM_T_82575))
   10617  1.285   msaitoh 		CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK);
   10618  1.285   msaitoh 
   10619  1.285   msaitoh 	sc->sc_ctrl &= ~CTRL_LRST;
   10620  1.285   msaitoh 	sc->sc_txcw = TXCW_ANE;
   10621  1.285   msaitoh 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   10622  1.285   msaitoh 		sc->sc_txcw |= TXCW_FD | TXCW_HD;
   10623  1.285   msaitoh 	else if (ife->ifm_media & IFM_FDX)
   10624  1.285   msaitoh 		sc->sc_txcw |= TXCW_FD;
   10625  1.285   msaitoh 	else
   10626  1.285   msaitoh 		sc->sc_txcw |= TXCW_HD;
   10627  1.285   msaitoh 
   10628  1.327   msaitoh 	if ((sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
   10629  1.281   msaitoh 		sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE;
   10630  1.167   msaitoh 
   10631  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n",
   10632  1.285   msaitoh 		    device_xname(sc->sc_dev), sc->sc_txcw));
   10633  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   10634  1.285   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10635  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   10636  1.285   msaitoh 	delay(1000);
   10637  1.167   msaitoh 
   10638  1.281   msaitoh 	i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1);
   10639  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i));
   10640  1.192   msaitoh 
   10641  1.281   msaitoh 	/*
   10642  1.281   msaitoh 	 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the
   10643  1.281   msaitoh 	 * optics detect a signal, 0 if they don't.
   10644  1.281   msaitoh 	 */
   10645  1.281   msaitoh 	if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) {
   10646  1.281   msaitoh 		/* Have signal; wait for the link to come up. */
   10647  1.281   msaitoh 		for (i = 0; i < WM_LINKUP_TIMEOUT; i++) {
   10648  1.281   msaitoh 			delay(10000);
   10649  1.281   msaitoh 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
   10650  1.281   msaitoh 				break;
   10651  1.281   msaitoh 		}
   10652  1.192   msaitoh 
   10653  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n",
   10654  1.281   msaitoh 			    device_xname(sc->sc_dev),i));
   10655  1.192   msaitoh 
   10656  1.281   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   10657  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10658  1.281   msaitoh 		    ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n",
   10659  1.281   msaitoh 			device_xname(sc->sc_dev),status, STATUS_LU));
   10660  1.281   msaitoh 		if (status & STATUS_LU) {
   10661  1.281   msaitoh 			/* Link is up. */
   10662  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   10663  1.281   msaitoh 			    ("%s: LINK: set media -> link up %s\n",
   10664  1.281   msaitoh 			    device_xname(sc->sc_dev),
   10665  1.281   msaitoh 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   10666  1.192   msaitoh 
   10667  1.281   msaitoh 			/*
   10668  1.281   msaitoh 			 * NOTE: CTRL will update TFCE and RFCE automatically,
   10669  1.281   msaitoh 			 * so we should update sc->sc_ctrl
   10670  1.281   msaitoh 			 */
   10671  1.281   msaitoh 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   10672  1.281   msaitoh 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   10673  1.281   msaitoh 			sc->sc_fcrtl &= ~FCRTL_XONE;
   10674  1.281   msaitoh 			if (status & STATUS_FD)
   10675  1.281   msaitoh 				sc->sc_tctl |=
   10676  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   10677  1.281   msaitoh 			else
   10678  1.281   msaitoh 				sc->sc_tctl |=
   10679  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   10680  1.281   msaitoh 			if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
   10681  1.281   msaitoh 				sc->sc_fcrtl |= FCRTL_XONE;
   10682  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   10683  1.281   msaitoh 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   10684  1.281   msaitoh 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   10685  1.281   msaitoh 				      sc->sc_fcrtl);
   10686  1.281   msaitoh 			sc->sc_tbi_linkup = 1;
   10687  1.281   msaitoh 		} else {
   10688  1.281   msaitoh 			if (i == WM_LINKUP_TIMEOUT)
   10689  1.281   msaitoh 				wm_check_for_link(sc);
   10690  1.281   msaitoh 			/* Link is down. */
   10691  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   10692  1.281   msaitoh 			    ("%s: LINK: set media -> link down\n",
   10693  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   10694  1.281   msaitoh 			sc->sc_tbi_linkup = 0;
   10695  1.281   msaitoh 		}
   10696  1.281   msaitoh 	} else {
   10697  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
   10698  1.281   msaitoh 		    device_xname(sc->sc_dev)));
   10699  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   10700  1.281   msaitoh 	}
   10701  1.198   msaitoh 
   10702  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   10703  1.192   msaitoh 
   10704  1.281   msaitoh 	return 0;
   10705  1.192   msaitoh }
   10706  1.192   msaitoh 
   10707  1.167   msaitoh /*
   10708  1.324   msaitoh  * wm_tbi_mediastatus:	[ifmedia interface function]
   10709  1.324   msaitoh  *
   10710  1.324   msaitoh  *	Get the current interface media status on a 1000BASE-X device.
   10711  1.324   msaitoh  */
   10712  1.324   msaitoh static void
   10713  1.324   msaitoh wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   10714  1.324   msaitoh {
   10715  1.324   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   10716  1.324   msaitoh 	uint32_t ctrl, status;
   10717  1.324   msaitoh 
   10718  1.324   msaitoh 	ifmr->ifm_status = IFM_AVALID;
   10719  1.324   msaitoh 	ifmr->ifm_active = IFM_ETHER;
   10720  1.324   msaitoh 
   10721  1.324   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   10722  1.324   msaitoh 	if ((status & STATUS_LU) == 0) {
   10723  1.324   msaitoh 		ifmr->ifm_active |= IFM_NONE;
   10724  1.324   msaitoh 		return;
   10725  1.324   msaitoh 	}
   10726  1.324   msaitoh 
   10727  1.324   msaitoh 	ifmr->ifm_status |= IFM_ACTIVE;
   10728  1.324   msaitoh 	/* Only 82545 is LX */
   10729  1.324   msaitoh 	if (sc->sc_type == WM_T_82545)
   10730  1.324   msaitoh 		ifmr->ifm_active |= IFM_1000_LX;
   10731  1.324   msaitoh 	else
   10732  1.324   msaitoh 		ifmr->ifm_active |= IFM_1000_SX;
   10733  1.324   msaitoh 	if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
   10734  1.324   msaitoh 		ifmr->ifm_active |= IFM_FDX;
   10735  1.324   msaitoh 	else
   10736  1.324   msaitoh 		ifmr->ifm_active |= IFM_HDX;
   10737  1.324   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   10738  1.324   msaitoh 	if (ctrl & CTRL_RFCE)
   10739  1.324   msaitoh 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE;
   10740  1.324   msaitoh 	if (ctrl & CTRL_TFCE)
   10741  1.324   msaitoh 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE;
   10742  1.324   msaitoh }
   10743  1.324   msaitoh 
   10744  1.325   msaitoh /* XXX TBI only */
   10745  1.324   msaitoh static int
   10746  1.324   msaitoh wm_check_for_link(struct wm_softc *sc)
   10747  1.324   msaitoh {
   10748  1.324   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   10749  1.324   msaitoh 	uint32_t rxcw;
   10750  1.324   msaitoh 	uint32_t ctrl;
   10751  1.324   msaitoh 	uint32_t status;
   10752  1.324   msaitoh 	uint32_t sig;
   10753  1.324   msaitoh 
   10754  1.324   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {
   10755  1.325   msaitoh 		/* XXX need some work for >= 82571 */
   10756  1.325   msaitoh 		if (sc->sc_type >= WM_T_82571) {
   10757  1.325   msaitoh 			sc->sc_tbi_linkup = 1;
   10758  1.325   msaitoh 			return 0;
   10759  1.325   msaitoh 		}
   10760  1.324   msaitoh 	}
   10761  1.324   msaitoh 
   10762  1.324   msaitoh 	rxcw = CSR_READ(sc, WMREG_RXCW);
   10763  1.324   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   10764  1.324   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   10765  1.324   msaitoh 
   10766  1.324   msaitoh 	sig = (sc->sc_type > WM_T_82544) ? CTRL_SWDPIN(1) : 0;
   10767  1.324   msaitoh 
   10768  1.388   msaitoh 	DPRINTF(WM_DEBUG_LINK,
   10769  1.388   msaitoh 	    ("%s: %s: sig = %d, status_lu = %d, rxcw_c = %d\n",
   10770  1.324   msaitoh 		device_xname(sc->sc_dev), __func__,
   10771  1.324   msaitoh 		((ctrl & CTRL_SWDPIN(1)) == sig),
   10772  1.388   msaitoh 		((status & STATUS_LU) != 0), ((rxcw & RXCW_C) != 0)));
   10773  1.324   msaitoh 
   10774  1.324   msaitoh 	/*
   10775  1.324   msaitoh 	 * SWDPIN   LU RXCW
   10776  1.324   msaitoh 	 *      0    0    0
   10777  1.324   msaitoh 	 *      0    0    1	(should not happen)
   10778  1.324   msaitoh 	 *      0    1    0	(should not happen)
   10779  1.324   msaitoh 	 *      0    1    1	(should not happen)
   10780  1.324   msaitoh 	 *      1    0    0	Disable autonego and force linkup
   10781  1.324   msaitoh 	 *      1    0    1	got /C/ but not linkup yet
   10782  1.324   msaitoh 	 *      1    1    0	(linkup)
   10783  1.324   msaitoh 	 *      1    1    1	If IFM_AUTO, back to autonego
   10784  1.324   msaitoh 	 *
   10785  1.324   msaitoh 	 */
   10786  1.324   msaitoh 	if (((ctrl & CTRL_SWDPIN(1)) == sig)
   10787  1.324   msaitoh 	    && ((status & STATUS_LU) == 0)
   10788  1.324   msaitoh 	    && ((rxcw & RXCW_C) == 0)) {
   10789  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: force linkup and fullduplex\n",
   10790  1.324   msaitoh 			__func__));
   10791  1.324   msaitoh 		sc->sc_tbi_linkup = 0;
   10792  1.324   msaitoh 		/* Disable auto-negotiation in the TXCW register */
   10793  1.324   msaitoh 		CSR_WRITE(sc, WMREG_TXCW, (sc->sc_txcw & ~TXCW_ANE));
   10794  1.324   msaitoh 
   10795  1.324   msaitoh 		/*
   10796  1.324   msaitoh 		 * Force link-up and also force full-duplex.
   10797  1.324   msaitoh 		 *
   10798  1.324   msaitoh 		 * NOTE: CTRL was updated TFCE and RFCE automatically,
   10799  1.324   msaitoh 		 * so we should update sc->sc_ctrl
   10800  1.324   msaitoh 		 */
   10801  1.324   msaitoh 		sc->sc_ctrl = ctrl | CTRL_SLU | CTRL_FD;
   10802  1.324   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10803  1.324   msaitoh 	} else if (((status & STATUS_LU) != 0)
   10804  1.324   msaitoh 	    && ((rxcw & RXCW_C) != 0)
   10805  1.324   msaitoh 	    && (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)) {
   10806  1.324   msaitoh 		sc->sc_tbi_linkup = 1;
   10807  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: go back to autonego\n",
   10808  1.324   msaitoh 			__func__));
   10809  1.324   msaitoh 		CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   10810  1.324   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, (ctrl & ~CTRL_SLU));
   10811  1.324   msaitoh 	} else if (((ctrl & CTRL_SWDPIN(1)) == sig)
   10812  1.324   msaitoh 	    && ((rxcw & RXCW_C) != 0)) {
   10813  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("/C/"));
   10814  1.324   msaitoh 	} else {
   10815  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: %x,%x,%x\n", __func__, rxcw, ctrl,
   10816  1.324   msaitoh 			status));
   10817  1.324   msaitoh 	}
   10818  1.324   msaitoh 
   10819  1.324   msaitoh 	return 0;
   10820  1.324   msaitoh }
   10821  1.324   msaitoh 
   10822  1.324   msaitoh /*
   10823  1.325   msaitoh  * wm_tbi_tick:
   10824  1.191   msaitoh  *
   10825  1.325   msaitoh  *	Check the link on TBI devices.
   10826  1.325   msaitoh  *	This function acts as mii_tick().
   10827  1.191   msaitoh  */
   10828  1.281   msaitoh static void
   10829  1.325   msaitoh wm_tbi_tick(struct wm_softc *sc)
   10830  1.191   msaitoh {
   10831  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   10832  1.325   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
   10833  1.281   msaitoh 	uint32_t status;
   10834  1.281   msaitoh 
   10835  1.384  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   10836  1.191   msaitoh 
   10837  1.281   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   10838  1.192   msaitoh 
   10839  1.281   msaitoh 	/* XXX is this needed? */
   10840  1.281   msaitoh 	(void)CSR_READ(sc, WMREG_RXCW);
   10841  1.281   msaitoh 	(void)CSR_READ(sc, WMREG_CTRL);
   10842  1.192   msaitoh 
   10843  1.281   msaitoh 	/* set link status */
   10844  1.281   msaitoh 	if ((status & STATUS_LU) == 0) {
   10845  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10846  1.281   msaitoh 		    ("%s: LINK: checklink -> down\n",
   10847  1.281   msaitoh 			device_xname(sc->sc_dev)));
   10848  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   10849  1.281   msaitoh 	} else if (sc->sc_tbi_linkup == 0) {
   10850  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10851  1.281   msaitoh 		    ("%s: LINK: checklink -> up %s\n",
   10852  1.281   msaitoh 			device_xname(sc->sc_dev),
   10853  1.281   msaitoh 			(status & STATUS_FD) ? "FDX" : "HDX"));
   10854  1.281   msaitoh 		sc->sc_tbi_linkup = 1;
   10855  1.325   msaitoh 		sc->sc_tbi_serdes_ticks = 0;
   10856  1.325   msaitoh 	}
   10857  1.325   msaitoh 
   10858  1.325   msaitoh 	if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) == 0)
   10859  1.325   msaitoh 		goto setled;
   10860  1.325   msaitoh 
   10861  1.325   msaitoh 	if ((status & STATUS_LU) == 0) {
   10862  1.325   msaitoh 		sc->sc_tbi_linkup = 0;
   10863  1.325   msaitoh 		/* If the timer expired, retry autonegotiation */
   10864  1.325   msaitoh 		if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   10865  1.325   msaitoh 		    && (++sc->sc_tbi_serdes_ticks
   10866  1.325   msaitoh 			>= sc->sc_tbi_serdes_anegticks)) {
   10867  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
   10868  1.325   msaitoh 			sc->sc_tbi_serdes_ticks = 0;
   10869  1.325   msaitoh 			/*
   10870  1.325   msaitoh 			 * Reset the link, and let autonegotiation do
   10871  1.325   msaitoh 			 * its thing
   10872  1.325   msaitoh 			 */
   10873  1.325   msaitoh 			sc->sc_ctrl |= CTRL_LRST;
   10874  1.325   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10875  1.325   msaitoh 			CSR_WRITE_FLUSH(sc);
   10876  1.325   msaitoh 			delay(1000);
   10877  1.325   msaitoh 			sc->sc_ctrl &= ~CTRL_LRST;
   10878  1.325   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10879  1.325   msaitoh 			CSR_WRITE_FLUSH(sc);
   10880  1.325   msaitoh 			delay(1000);
   10881  1.325   msaitoh 			CSR_WRITE(sc, WMREG_TXCW,
   10882  1.325   msaitoh 			    sc->sc_txcw & ~TXCW_ANE);
   10883  1.325   msaitoh 			CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   10884  1.325   msaitoh 		}
   10885  1.192   msaitoh 	}
   10886  1.192   msaitoh 
   10887  1.325   msaitoh setled:
   10888  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   10889  1.325   msaitoh }
   10890  1.325   msaitoh 
   10891  1.325   msaitoh /* SERDES related */
   10892  1.325   msaitoh static void
   10893  1.325   msaitoh wm_serdes_power_up_link_82575(struct wm_softc *sc)
   10894  1.325   msaitoh {
   10895  1.325   msaitoh 	uint32_t reg;
   10896  1.325   msaitoh 
   10897  1.325   msaitoh 	if ((sc->sc_mediatype != WM_MEDIATYPE_SERDES)
   10898  1.325   msaitoh 	    && ((sc->sc_flags & WM_F_SGMII) == 0))
   10899  1.325   msaitoh 		return;
   10900  1.325   msaitoh 
   10901  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_CFG);
   10902  1.325   msaitoh 	reg |= PCS_CFG_PCS_EN;
   10903  1.325   msaitoh 	CSR_WRITE(sc, WMREG_PCS_CFG, reg);
   10904  1.325   msaitoh 
   10905  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL_EXT);
   10906  1.325   msaitoh 	reg &= ~CTRL_EXT_SWDPIN(3);
   10907  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   10908  1.325   msaitoh 	CSR_WRITE_FLUSH(sc);
   10909  1.325   msaitoh }
   10910  1.325   msaitoh 
   10911  1.325   msaitoh static int
   10912  1.325   msaitoh wm_serdes_mediachange(struct ifnet *ifp)
   10913  1.325   msaitoh {
   10914  1.325   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   10915  1.325   msaitoh 	bool pcs_autoneg = true; /* XXX */
   10916  1.325   msaitoh 	uint32_t ctrl_ext, pcs_lctl, reg;
   10917  1.325   msaitoh 
   10918  1.325   msaitoh 	/* XXX Currently, this function is not called on 8257[12] */
   10919  1.325   msaitoh 	if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)
   10920  1.325   msaitoh 	    || (sc->sc_type >= WM_T_82575))
   10921  1.325   msaitoh 		CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK);
   10922  1.325   msaitoh 
   10923  1.325   msaitoh 	wm_serdes_power_up_link_82575(sc);
   10924  1.325   msaitoh 
   10925  1.325   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   10926  1.325   msaitoh 
   10927  1.325   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576))
   10928  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SWDPIN(0) | CTRL_SWDPIN(1);
   10929  1.325   msaitoh 
   10930  1.325   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   10931  1.325   msaitoh 	pcs_lctl = CSR_READ(sc, WMREG_PCS_LCTL);
   10932  1.325   msaitoh 	switch (ctrl_ext & CTRL_EXT_LINK_MODE_MASK) {
   10933  1.325   msaitoh 	case CTRL_EXT_LINK_MODE_SGMII:
   10934  1.325   msaitoh 		pcs_autoneg = true;
   10935  1.325   msaitoh 		pcs_lctl &= ~PCS_LCTL_AN_TIMEOUT;
   10936  1.325   msaitoh 		break;
   10937  1.325   msaitoh 	case CTRL_EXT_LINK_MODE_1000KX:
   10938  1.325   msaitoh 		pcs_autoneg = false;
   10939  1.325   msaitoh 		/* FALLTHROUGH */
   10940  1.325   msaitoh 	default:
   10941  1.388   msaitoh 		if ((sc->sc_type == WM_T_82575)
   10942  1.388   msaitoh 		    || (sc->sc_type == WM_T_82576)) {
   10943  1.325   msaitoh 			if ((sc->sc_flags & WM_F_PCS_DIS_AUTONEGO) != 0)
   10944  1.325   msaitoh 				pcs_autoneg = false;
   10945  1.325   msaitoh 		}
   10946  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SPEED_1000 | CTRL_FRCSPD | CTRL_FD
   10947  1.325   msaitoh 		    | CTRL_FRCFDX;
   10948  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_FSV_1000 | PCS_LCTL_FDV_FULL;
   10949  1.325   msaitoh 	}
   10950  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10951  1.325   msaitoh 
   10952  1.325   msaitoh 	if (pcs_autoneg) {
   10953  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_AN_ENABLE | PCS_LCTL_AN_RESTART;
   10954  1.325   msaitoh 		pcs_lctl &= ~PCS_LCTL_FORCE_FC;
   10955  1.325   msaitoh 
   10956  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_ANADV);
   10957  1.325   msaitoh 		reg &= ~(TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE);
   10958  1.327   msaitoh 		reg |= TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE;
   10959  1.325   msaitoh 		CSR_WRITE(sc, WMREG_PCS_ANADV, reg);
   10960  1.325   msaitoh 	} else
   10961  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_FSD | PCS_LCTL_FORCE_FC;
   10962  1.325   msaitoh 
   10963  1.325   msaitoh 	CSR_WRITE(sc, WMREG_PCS_LCTL, pcs_lctl);
   10964  1.325   msaitoh 
   10965  1.325   msaitoh 
   10966  1.325   msaitoh 	return 0;
   10967  1.325   msaitoh }
   10968  1.325   msaitoh 
   10969  1.325   msaitoh static void
   10970  1.325   msaitoh wm_serdes_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   10971  1.325   msaitoh {
   10972  1.325   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   10973  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   10974  1.325   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   10975  1.325   msaitoh 	uint32_t pcs_adv, pcs_lpab, reg;
   10976  1.325   msaitoh 
   10977  1.325   msaitoh 	ifmr->ifm_status = IFM_AVALID;
   10978  1.325   msaitoh 	ifmr->ifm_active = IFM_ETHER;
   10979  1.325   msaitoh 
   10980  1.325   msaitoh 	/* Check PCS */
   10981  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_LSTS);
   10982  1.325   msaitoh 	if ((reg & PCS_LSTS_LINKOK) == 0) {
   10983  1.325   msaitoh 		ifmr->ifm_active |= IFM_NONE;
   10984  1.325   msaitoh 		sc->sc_tbi_linkup = 0;
   10985  1.325   msaitoh 		goto setled;
   10986  1.325   msaitoh 	}
   10987  1.325   msaitoh 
   10988  1.325   msaitoh 	sc->sc_tbi_linkup = 1;
   10989  1.325   msaitoh 	ifmr->ifm_status |= IFM_ACTIVE;
   10990  1.457   msaitoh 	if (sc->sc_type == WM_T_I354) {
   10991  1.457   msaitoh 		uint32_t status;
   10992  1.457   msaitoh 
   10993  1.457   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   10994  1.457   msaitoh 		if (((status & STATUS_2P5_SKU) != 0)
   10995  1.457   msaitoh 		    && ((status & STATUS_2P5_SKU_OVER) == 0)) {
   10996  1.457   msaitoh 			ifmr->ifm_active |= IFM_2500_SX; /* XXX KX */
   10997  1.457   msaitoh 		} else
   10998  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX KX */
   10999  1.457   msaitoh 	} else {
   11000  1.457   msaitoh 		switch (__SHIFTOUT(reg, PCS_LSTS_SPEED)) {
   11001  1.457   msaitoh 		case PCS_LSTS_SPEED_10:
   11002  1.457   msaitoh 			ifmr->ifm_active |= IFM_10_T; /* XXX */
   11003  1.457   msaitoh 			break;
   11004  1.457   msaitoh 		case PCS_LSTS_SPEED_100:
   11005  1.457   msaitoh 			ifmr->ifm_active |= IFM_100_FX; /* XXX */
   11006  1.457   msaitoh 			break;
   11007  1.457   msaitoh 		case PCS_LSTS_SPEED_1000:
   11008  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX */
   11009  1.457   msaitoh 			break;
   11010  1.457   msaitoh 		default:
   11011  1.457   msaitoh 			device_printf(sc->sc_dev, "Unknown speed\n");
   11012  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX */
   11013  1.457   msaitoh 			break;
   11014  1.457   msaitoh 		}
   11015  1.457   msaitoh 	}
   11016  1.325   msaitoh 	if ((reg & PCS_LSTS_FDX) != 0)
   11017  1.325   msaitoh 		ifmr->ifm_active |= IFM_FDX;
   11018  1.325   msaitoh 	else
   11019  1.325   msaitoh 		ifmr->ifm_active |= IFM_HDX;
   11020  1.325   msaitoh 	mii->mii_media_active &= ~IFM_ETH_FMASK;
   11021  1.325   msaitoh 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   11022  1.325   msaitoh 		/* Check flow */
   11023  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_LSTS);
   11024  1.325   msaitoh 		if ((reg & PCS_LSTS_AN_COMP) == 0) {
   11025  1.388   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("XXX LINKOK but not ACOMP\n"));
   11026  1.325   msaitoh 			goto setled;
   11027  1.325   msaitoh 		}
   11028  1.325   msaitoh 		pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
   11029  1.325   msaitoh 		pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
   11030  1.388   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   11031  1.388   msaitoh 		    ("XXX AN result(2) %08x, %08x\n", pcs_adv, pcs_lpab));
   11032  1.325   msaitoh 		if ((pcs_adv & TXCW_SYM_PAUSE)
   11033  1.325   msaitoh 		    && (pcs_lpab & TXCW_SYM_PAUSE)) {
   11034  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11035  1.325   msaitoh 			    | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   11036  1.325   msaitoh 		} else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
   11037  1.325   msaitoh 		    && (pcs_adv & TXCW_ASYM_PAUSE)
   11038  1.325   msaitoh 		    && (pcs_lpab & TXCW_SYM_PAUSE)
   11039  1.325   msaitoh 		    && (pcs_lpab & TXCW_ASYM_PAUSE)) {
   11040  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11041  1.325   msaitoh 			    | IFM_ETH_TXPAUSE;
   11042  1.325   msaitoh 		} else if ((pcs_adv & TXCW_SYM_PAUSE)
   11043  1.325   msaitoh 		    && (pcs_adv & TXCW_ASYM_PAUSE)
   11044  1.325   msaitoh 		    && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
   11045  1.325   msaitoh 		    && (pcs_lpab & TXCW_ASYM_PAUSE)) {
   11046  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11047  1.325   msaitoh 			    | IFM_ETH_RXPAUSE;
   11048  1.325   msaitoh 		}
   11049  1.325   msaitoh 	}
   11050  1.325   msaitoh 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
   11051  1.325   msaitoh 	    | (mii->mii_media_active & IFM_ETH_FMASK);
   11052  1.325   msaitoh setled:
   11053  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11054  1.325   msaitoh }
   11055  1.325   msaitoh 
   11056  1.325   msaitoh /*
   11057  1.325   msaitoh  * wm_serdes_tick:
   11058  1.325   msaitoh  *
   11059  1.325   msaitoh  *	Check the link on serdes devices.
   11060  1.325   msaitoh  */
   11061  1.325   msaitoh static void
   11062  1.325   msaitoh wm_serdes_tick(struct wm_softc *sc)
   11063  1.325   msaitoh {
   11064  1.325   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   11065  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   11066  1.325   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
   11067  1.325   msaitoh 	uint32_t reg;
   11068  1.325   msaitoh 
   11069  1.384  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   11070  1.325   msaitoh 
   11071  1.325   msaitoh 	mii->mii_media_status = IFM_AVALID;
   11072  1.325   msaitoh 	mii->mii_media_active = IFM_ETHER;
   11073  1.325   msaitoh 
   11074  1.325   msaitoh 	/* Check PCS */
   11075  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_LSTS);
   11076  1.325   msaitoh 	if ((reg & PCS_LSTS_LINKOK) != 0) {
   11077  1.325   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
   11078  1.325   msaitoh 		sc->sc_tbi_linkup = 1;
   11079  1.325   msaitoh 		sc->sc_tbi_serdes_ticks = 0;
   11080  1.325   msaitoh 		mii->mii_media_active |= IFM_1000_SX; /* XXX */
   11081  1.325   msaitoh 		if ((reg & PCS_LSTS_FDX) != 0)
   11082  1.325   msaitoh 			mii->mii_media_active |= IFM_FDX;
   11083  1.325   msaitoh 		else
   11084  1.325   msaitoh 			mii->mii_media_active |= IFM_HDX;
   11085  1.325   msaitoh 	} else {
   11086  1.325   msaitoh 		mii->mii_media_status |= IFM_NONE;
   11087  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   11088  1.457   msaitoh 		/* If the timer expired, retry autonegotiation */
   11089  1.325   msaitoh 		if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   11090  1.325   msaitoh 		    && (++sc->sc_tbi_serdes_ticks
   11091  1.325   msaitoh 			>= sc->sc_tbi_serdes_anegticks)) {
   11092  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
   11093  1.325   msaitoh 			sc->sc_tbi_serdes_ticks = 0;
   11094  1.325   msaitoh 			/* XXX */
   11095  1.325   msaitoh 			wm_serdes_mediachange(ifp);
   11096  1.281   msaitoh 		}
   11097  1.192   msaitoh 	}
   11098  1.192   msaitoh 
   11099  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11100  1.191   msaitoh }
   11101  1.191   msaitoh 
   11102  1.292   msaitoh /* SFP related */
   11103  1.295   msaitoh 
   11104  1.295   msaitoh static int
   11105  1.295   msaitoh wm_sfp_read_data_byte(struct wm_softc *sc, uint16_t offset, uint8_t *data)
   11106  1.295   msaitoh {
   11107  1.295   msaitoh 	uint32_t i2ccmd;
   11108  1.295   msaitoh 	int i;
   11109  1.295   msaitoh 
   11110  1.295   msaitoh 	i2ccmd = (offset << I2CCMD_REG_ADDR_SHIFT) | I2CCMD_OPCODE_READ;
   11111  1.295   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   11112  1.295   msaitoh 
   11113  1.295   msaitoh 	/* Poll the ready bit */
   11114  1.295   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   11115  1.295   msaitoh 		delay(50);
   11116  1.295   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   11117  1.295   msaitoh 		if (i2ccmd & I2CCMD_READY)
   11118  1.295   msaitoh 			break;
   11119  1.295   msaitoh 	}
   11120  1.295   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   11121  1.295   msaitoh 		return -1;
   11122  1.295   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   11123  1.295   msaitoh 		return -1;
   11124  1.295   msaitoh 
   11125  1.295   msaitoh 	*data = i2ccmd & 0x00ff;
   11126  1.295   msaitoh 
   11127  1.295   msaitoh 	return 0;
   11128  1.295   msaitoh }
   11129  1.295   msaitoh 
   11130  1.292   msaitoh static uint32_t
   11131  1.295   msaitoh wm_sfp_get_media_type(struct wm_softc *sc)
   11132  1.292   msaitoh {
   11133  1.295   msaitoh 	uint32_t ctrl_ext;
   11134  1.295   msaitoh 	uint8_t val = 0;
   11135  1.295   msaitoh 	int timeout = 3;
   11136  1.311   msaitoh 	uint32_t mediatype = WM_MEDIATYPE_UNKNOWN;
   11137  1.295   msaitoh 	int rv = -1;
   11138  1.292   msaitoh 
   11139  1.295   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   11140  1.295   msaitoh 	ctrl_ext &= ~CTRL_EXT_SWDPIN(3);
   11141  1.295   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_I2C_ENA);
   11142  1.295   msaitoh 	CSR_WRITE_FLUSH(sc);
   11143  1.295   msaitoh 
   11144  1.295   msaitoh 	/* Read SFP module data */
   11145  1.295   msaitoh 	while (timeout) {
   11146  1.295   msaitoh 		rv = wm_sfp_read_data_byte(sc, SFF_SFP_ID_OFF, &val);
   11147  1.295   msaitoh 		if (rv == 0)
   11148  1.295   msaitoh 			break;
   11149  1.295   msaitoh 		delay(100*1000); /* XXX too big */
   11150  1.295   msaitoh 		timeout--;
   11151  1.295   msaitoh 	}
   11152  1.295   msaitoh 	if (rv != 0)
   11153  1.295   msaitoh 		goto out;
   11154  1.295   msaitoh 	switch (val) {
   11155  1.295   msaitoh 	case SFF_SFP_ID_SFF:
   11156  1.295   msaitoh 		aprint_normal_dev(sc->sc_dev,
   11157  1.295   msaitoh 		    "Module/Connector soldered to board\n");
   11158  1.295   msaitoh 		break;
   11159  1.295   msaitoh 	case SFF_SFP_ID_SFP:
   11160  1.295   msaitoh 		aprint_normal_dev(sc->sc_dev, "SFP\n");
   11161  1.295   msaitoh 		break;
   11162  1.295   msaitoh 	case SFF_SFP_ID_UNKNOWN:
   11163  1.295   msaitoh 		goto out;
   11164  1.295   msaitoh 	default:
   11165  1.295   msaitoh 		break;
   11166  1.295   msaitoh 	}
   11167  1.295   msaitoh 
   11168  1.295   msaitoh 	rv = wm_sfp_read_data_byte(sc, SFF_SFP_ETH_FLAGS_OFF, &val);
   11169  1.295   msaitoh 	if (rv != 0) {
   11170  1.295   msaitoh 		goto out;
   11171  1.295   msaitoh 	}
   11172  1.295   msaitoh 
   11173  1.295   msaitoh 	if ((val & (SFF_SFP_ETH_FLAGS_1000SX | SFF_SFP_ETH_FLAGS_1000LX)) != 0)
   11174  1.311   msaitoh 		mediatype = WM_MEDIATYPE_SERDES;
   11175  1.295   msaitoh 	else if ((val & SFF_SFP_ETH_FLAGS_1000T) != 0){
   11176  1.295   msaitoh 		sc->sc_flags |= WM_F_SGMII;
   11177  1.311   msaitoh 		mediatype = WM_MEDIATYPE_COPPER;
   11178  1.295   msaitoh 	} else if ((val & SFF_SFP_ETH_FLAGS_100FX) != 0){
   11179  1.295   msaitoh 		sc->sc_flags |= WM_F_SGMII;
   11180  1.311   msaitoh 		mediatype = WM_MEDIATYPE_SERDES;
   11181  1.295   msaitoh 	}
   11182  1.295   msaitoh 
   11183  1.295   msaitoh out:
   11184  1.295   msaitoh 	/* Restore I2C interface setting */
   11185  1.295   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   11186  1.295   msaitoh 
   11187  1.295   msaitoh 	return mediatype;
   11188  1.292   msaitoh }
   11189  1.453   msaitoh 
   11190  1.191   msaitoh /*
   11191  1.281   msaitoh  * NVM related.
   11192  1.281   msaitoh  * Microwire, SPI (w/wo EERD) and Flash.
   11193  1.265   msaitoh  */
   11194  1.265   msaitoh 
   11195  1.281   msaitoh /* Both spi and uwire */
   11196  1.265   msaitoh 
   11197  1.265   msaitoh /*
   11198  1.281   msaitoh  * wm_eeprom_sendbits:
   11199  1.199   msaitoh  *
   11200  1.281   msaitoh  *	Send a series of bits to the EEPROM.
   11201  1.199   msaitoh  */
   11202  1.281   msaitoh static void
   11203  1.281   msaitoh wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
   11204  1.199   msaitoh {
   11205  1.281   msaitoh 	uint32_t reg;
   11206  1.281   msaitoh 	int x;
   11207  1.199   msaitoh 
   11208  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   11209  1.199   msaitoh 
   11210  1.281   msaitoh 	for (x = nbits; x > 0; x--) {
   11211  1.281   msaitoh 		if (bits & (1U << (x - 1)))
   11212  1.281   msaitoh 			reg |= EECD_DI;
   11213  1.281   msaitoh 		else
   11214  1.281   msaitoh 			reg &= ~EECD_DI;
   11215  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11216  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11217  1.281   msaitoh 		delay(2);
   11218  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   11219  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11220  1.281   msaitoh 		delay(2);
   11221  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11222  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11223  1.281   msaitoh 		delay(2);
   11224  1.199   msaitoh 	}
   11225  1.199   msaitoh }
   11226  1.199   msaitoh 
   11227  1.199   msaitoh /*
   11228  1.281   msaitoh  * wm_eeprom_recvbits:
   11229  1.199   msaitoh  *
   11230  1.281   msaitoh  *	Receive a series of bits from the EEPROM.
   11231  1.199   msaitoh  */
   11232  1.199   msaitoh static void
   11233  1.281   msaitoh wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
   11234  1.199   msaitoh {
   11235  1.281   msaitoh 	uint32_t reg, val;
   11236  1.281   msaitoh 	int x;
   11237  1.199   msaitoh 
   11238  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
   11239  1.199   msaitoh 
   11240  1.281   msaitoh 	val = 0;
   11241  1.281   msaitoh 	for (x = nbits; x > 0; x--) {
   11242  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   11243  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11244  1.281   msaitoh 		delay(2);
   11245  1.281   msaitoh 		if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
   11246  1.281   msaitoh 			val |= (1U << (x - 1));
   11247  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11248  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11249  1.281   msaitoh 		delay(2);
   11250  1.199   msaitoh 	}
   11251  1.281   msaitoh 	*valp = val;
   11252  1.281   msaitoh }
   11253  1.199   msaitoh 
   11254  1.281   msaitoh /* Microwire */
   11255  1.199   msaitoh 
   11256  1.199   msaitoh /*
   11257  1.281   msaitoh  * wm_nvm_read_uwire:
   11258  1.243   msaitoh  *
   11259  1.281   msaitoh  *	Read a word from the EEPROM using the MicroWire protocol.
   11260  1.243   msaitoh  */
   11261  1.243   msaitoh static int
   11262  1.281   msaitoh wm_nvm_read_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   11263  1.243   msaitoh {
   11264  1.281   msaitoh 	uint32_t reg, val;
   11265  1.281   msaitoh 	int i;
   11266  1.281   msaitoh 
   11267  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11268  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11269  1.420   msaitoh 
   11270  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11271  1.281   msaitoh 		/* Clear SK and DI. */
   11272  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
   11273  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11274  1.281   msaitoh 
   11275  1.281   msaitoh 		/*
   11276  1.281   msaitoh 		 * XXX: workaround for a bug in qemu-0.12.x and prior
   11277  1.281   msaitoh 		 * and Xen.
   11278  1.281   msaitoh 		 *
   11279  1.281   msaitoh 		 * We use this workaround only for 82540 because qemu's
   11280  1.281   msaitoh 		 * e1000 act as 82540.
   11281  1.281   msaitoh 		 */
   11282  1.281   msaitoh 		if (sc->sc_type == WM_T_82540) {
   11283  1.281   msaitoh 			reg |= EECD_SK;
   11284  1.281   msaitoh 			CSR_WRITE(sc, WMREG_EECD, reg);
   11285  1.281   msaitoh 			reg &= ~EECD_SK;
   11286  1.281   msaitoh 			CSR_WRITE(sc, WMREG_EECD, reg);
   11287  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   11288  1.281   msaitoh 			delay(2);
   11289  1.281   msaitoh 		}
   11290  1.281   msaitoh 		/* XXX: end of workaround */
   11291  1.332   msaitoh 
   11292  1.281   msaitoh 		/* Set CHIP SELECT. */
   11293  1.281   msaitoh 		reg |= EECD_CS;
   11294  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11295  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11296  1.281   msaitoh 		delay(2);
   11297  1.281   msaitoh 
   11298  1.281   msaitoh 		/* Shift in the READ command. */
   11299  1.281   msaitoh 		wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
   11300  1.281   msaitoh 
   11301  1.281   msaitoh 		/* Shift in address. */
   11302  1.294   msaitoh 		wm_eeprom_sendbits(sc, word + i, sc->sc_nvm_addrbits);
   11303  1.281   msaitoh 
   11304  1.281   msaitoh 		/* Shift out the data. */
   11305  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 16);
   11306  1.281   msaitoh 		data[i] = val & 0xffff;
   11307  1.243   msaitoh 
   11308  1.281   msaitoh 		/* Clear CHIP SELECT. */
   11309  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
   11310  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11311  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11312  1.281   msaitoh 		delay(2);
   11313  1.243   msaitoh 	}
   11314  1.243   msaitoh 
   11315  1.281   msaitoh 	return 0;
   11316  1.281   msaitoh }
   11317  1.243   msaitoh 
   11318  1.281   msaitoh /* SPI */
   11319  1.243   msaitoh 
   11320  1.294   msaitoh /*
   11321  1.294   msaitoh  * Set SPI and FLASH related information from the EECD register.
   11322  1.294   msaitoh  * For 82541 and 82547, the word size is taken from EEPROM.
   11323  1.294   msaitoh  */
   11324  1.294   msaitoh static int
   11325  1.294   msaitoh wm_nvm_set_addrbits_size_eecd(struct wm_softc *sc)
   11326  1.243   msaitoh {
   11327  1.294   msaitoh 	int size;
   11328  1.281   msaitoh 	uint32_t reg;
   11329  1.294   msaitoh 	uint16_t data;
   11330  1.243   msaitoh 
   11331  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   11332  1.294   msaitoh 	sc->sc_nvm_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
   11333  1.294   msaitoh 
   11334  1.294   msaitoh 	/* Read the size of NVM from EECD by default */
   11335  1.294   msaitoh 	size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);
   11336  1.294   msaitoh 	switch (sc->sc_type) {
   11337  1.294   msaitoh 	case WM_T_82541:
   11338  1.294   msaitoh 	case WM_T_82541_2:
   11339  1.294   msaitoh 	case WM_T_82547:
   11340  1.294   msaitoh 	case WM_T_82547_2:
   11341  1.294   msaitoh 		/* Set dummy value to access EEPROM */
   11342  1.294   msaitoh 		sc->sc_nvm_wordsize = 64;
   11343  1.294   msaitoh 		wm_nvm_read(sc, NVM_OFF_EEPROM_SIZE, 1, &data);
   11344  1.294   msaitoh 		reg = data;
   11345  1.294   msaitoh 		size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);
   11346  1.294   msaitoh 		if (size == 0)
   11347  1.294   msaitoh 			size = 6; /* 64 word size */
   11348  1.294   msaitoh 		else
   11349  1.294   msaitoh 			size += NVM_WORD_SIZE_BASE_SHIFT + 1;
   11350  1.294   msaitoh 		break;
   11351  1.294   msaitoh 	case WM_T_80003:
   11352  1.294   msaitoh 	case WM_T_82571:
   11353  1.294   msaitoh 	case WM_T_82572:
   11354  1.294   msaitoh 	case WM_T_82573: /* SPI case */
   11355  1.294   msaitoh 	case WM_T_82574: /* SPI case */
   11356  1.294   msaitoh 	case WM_T_82583: /* SPI case */
   11357  1.294   msaitoh 		size += NVM_WORD_SIZE_BASE_SHIFT;
   11358  1.294   msaitoh 		if (size > 14)
   11359  1.294   msaitoh 			size = 14;
   11360  1.294   msaitoh 		break;
   11361  1.294   msaitoh 	case WM_T_82575:
   11362  1.294   msaitoh 	case WM_T_82576:
   11363  1.294   msaitoh 	case WM_T_82580:
   11364  1.294   msaitoh 	case WM_T_I350:
   11365  1.294   msaitoh 	case WM_T_I354:
   11366  1.294   msaitoh 	case WM_T_I210:
   11367  1.294   msaitoh 	case WM_T_I211:
   11368  1.294   msaitoh 		size += NVM_WORD_SIZE_BASE_SHIFT;
   11369  1.294   msaitoh 		if (size > 15)
   11370  1.294   msaitoh 			size = 15;
   11371  1.294   msaitoh 		break;
   11372  1.294   msaitoh 	default:
   11373  1.294   msaitoh 		aprint_error_dev(sc->sc_dev,
   11374  1.294   msaitoh 		    "%s: unknown device(%d)?\n", __func__, sc->sc_type);
   11375  1.294   msaitoh 		return -1;
   11376  1.294   msaitoh 		break;
   11377  1.294   msaitoh 	}
   11378  1.294   msaitoh 
   11379  1.294   msaitoh 	sc->sc_nvm_wordsize = 1 << size;
   11380  1.294   msaitoh 
   11381  1.294   msaitoh 	return 0;
   11382  1.243   msaitoh }
   11383  1.243   msaitoh 
   11384  1.243   msaitoh /*
   11385  1.281   msaitoh  * wm_nvm_ready_spi:
   11386    1.1   thorpej  *
   11387  1.281   msaitoh  *	Wait for a SPI EEPROM to be ready for commands.
   11388    1.1   thorpej  */
   11389  1.281   msaitoh static int
   11390  1.281   msaitoh wm_nvm_ready_spi(struct wm_softc *sc)
   11391    1.1   thorpej {
   11392  1.281   msaitoh 	uint32_t val;
   11393  1.281   msaitoh 	int usec;
   11394    1.1   thorpej 
   11395  1.421   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11396  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   11397  1.421   msaitoh 
   11398  1.281   msaitoh 	for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) {
   11399  1.281   msaitoh 		wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8);
   11400  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 8);
   11401  1.281   msaitoh 		if ((val & SPI_SR_RDY) == 0)
   11402  1.281   msaitoh 			break;
   11403   1.71   thorpej 	}
   11404  1.281   msaitoh 	if (usec >= SPI_MAX_RETRIES) {
   11405  1.388   msaitoh 		aprint_error_dev(sc->sc_dev,"EEPROM failed to become ready\n");
   11406  1.281   msaitoh 		return 1;
   11407  1.127    bouyer 	}
   11408  1.281   msaitoh 	return 0;
   11409  1.127    bouyer }
   11410  1.127    bouyer 
   11411  1.127    bouyer /*
   11412  1.281   msaitoh  * wm_nvm_read_spi:
   11413  1.127    bouyer  *
   11414  1.281   msaitoh  *	Read a work from the EEPROM using the SPI protocol.
   11415  1.127    bouyer  */
   11416  1.127    bouyer static int
   11417  1.281   msaitoh wm_nvm_read_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   11418  1.127    bouyer {
   11419  1.281   msaitoh 	uint32_t reg, val;
   11420  1.281   msaitoh 	int i;
   11421  1.281   msaitoh 	uint8_t opc;
   11422  1.281   msaitoh 
   11423  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11424  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11425  1.420   msaitoh 
   11426  1.281   msaitoh 	/* Clear SK and CS. */
   11427  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
   11428  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11429  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11430  1.281   msaitoh 	delay(2);
   11431  1.127    bouyer 
   11432  1.281   msaitoh 	if (wm_nvm_ready_spi(sc))
   11433  1.281   msaitoh 		return 1;
   11434  1.127    bouyer 
   11435  1.281   msaitoh 	/* Toggle CS to flush commands. */
   11436  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
   11437  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11438  1.281   msaitoh 	delay(2);
   11439  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11440  1.266   msaitoh 	CSR_WRITE_FLUSH(sc);
   11441  1.127    bouyer 	delay(2);
   11442  1.127    bouyer 
   11443  1.281   msaitoh 	opc = SPI_OPC_READ;
   11444  1.294   msaitoh 	if (sc->sc_nvm_addrbits == 8 && word >= 128)
   11445  1.281   msaitoh 		opc |= SPI_OPC_A8;
   11446  1.281   msaitoh 
   11447  1.281   msaitoh 	wm_eeprom_sendbits(sc, opc, 8);
   11448  1.294   msaitoh 	wm_eeprom_sendbits(sc, word << 1, sc->sc_nvm_addrbits);
   11449  1.281   msaitoh 
   11450  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11451  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 16);
   11452  1.281   msaitoh 		data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
   11453  1.281   msaitoh 	}
   11454  1.178   msaitoh 
   11455  1.281   msaitoh 	/* Raise CS and clear SK. */
   11456  1.281   msaitoh 	reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
   11457  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11458  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11459  1.281   msaitoh 	delay(2);
   11460  1.178   msaitoh 
   11461  1.281   msaitoh 	return 0;
   11462  1.127    bouyer }
   11463  1.127    bouyer 
   11464  1.281   msaitoh /* Using with EERD */
   11465  1.281   msaitoh 
   11466  1.281   msaitoh static int
   11467  1.281   msaitoh wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
   11468  1.127    bouyer {
   11469  1.281   msaitoh 	uint32_t attempts = 100000;
   11470  1.281   msaitoh 	uint32_t i, reg = 0;
   11471  1.281   msaitoh 	int32_t done = -1;
   11472  1.281   msaitoh 
   11473  1.281   msaitoh 	for (i = 0; i < attempts; i++) {
   11474  1.281   msaitoh 		reg = CSR_READ(sc, rw);
   11475  1.127    bouyer 
   11476  1.281   msaitoh 		if (reg & EERD_DONE) {
   11477  1.281   msaitoh 			done = 0;
   11478  1.281   msaitoh 			break;
   11479  1.178   msaitoh 		}
   11480  1.281   msaitoh 		delay(5);
   11481  1.169   msaitoh 	}
   11482  1.127    bouyer 
   11483  1.281   msaitoh 	return done;
   11484    1.1   thorpej }
   11485  1.117   msaitoh 
   11486  1.117   msaitoh static int
   11487  1.281   msaitoh wm_nvm_read_eerd(struct wm_softc *sc, int offset, int wordcnt,
   11488  1.281   msaitoh     uint16_t *data)
   11489  1.117   msaitoh {
   11490  1.281   msaitoh 	int i, eerd = 0;
   11491  1.281   msaitoh 	int error = 0;
   11492  1.117   msaitoh 
   11493  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11494  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11495  1.420   msaitoh 
   11496  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11497  1.281   msaitoh 		eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
   11498  1.117   msaitoh 
   11499  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EERD, eerd);
   11500  1.281   msaitoh 		error = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
   11501  1.281   msaitoh 		if (error != 0)
   11502  1.281   msaitoh 			break;
   11503  1.117   msaitoh 
   11504  1.281   msaitoh 		data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
   11505  1.117   msaitoh 	}
   11506  1.281   msaitoh 
   11507  1.281   msaitoh 	return error;
   11508  1.117   msaitoh }
   11509  1.117   msaitoh 
   11510  1.281   msaitoh /* Flash */
   11511  1.281   msaitoh 
   11512  1.117   msaitoh static int
   11513  1.281   msaitoh wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank)
   11514  1.117   msaitoh {
   11515  1.281   msaitoh 	uint32_t eecd;
   11516  1.281   msaitoh 	uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1;
   11517  1.281   msaitoh 	uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t);
   11518  1.281   msaitoh 	uint8_t sig_byte = 0;
   11519  1.117   msaitoh 
   11520  1.281   msaitoh 	switch (sc->sc_type) {
   11521  1.392   msaitoh 	case WM_T_PCH_SPT:
   11522  1.392   msaitoh 		/*
   11523  1.392   msaitoh 		 * In SPT, read from the CTRL_EXT reg instead of accessing the
   11524  1.392   msaitoh 		 * sector valid bits from the NVM.
   11525  1.392   msaitoh 		 */
   11526  1.392   msaitoh 		*bank = CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_NVMVS;
   11527  1.392   msaitoh 		if ((*bank == 0) || (*bank == 1)) {
   11528  1.392   msaitoh 			aprint_error_dev(sc->sc_dev,
   11529  1.424   msaitoh 			    "%s: no valid NVM bank present (%u)\n", __func__,
   11530  1.424   msaitoh 				*bank);
   11531  1.392   msaitoh 			return -1;
   11532  1.392   msaitoh 		} else {
   11533  1.392   msaitoh 			*bank = *bank - 2;
   11534  1.392   msaitoh 			return 0;
   11535  1.392   msaitoh 		}
   11536  1.281   msaitoh 	case WM_T_ICH8:
   11537  1.281   msaitoh 	case WM_T_ICH9:
   11538  1.281   msaitoh 		eecd = CSR_READ(sc, WMREG_EECD);
   11539  1.281   msaitoh 		if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) {
   11540  1.281   msaitoh 			*bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0;
   11541  1.281   msaitoh 			return 0;
   11542  1.281   msaitoh 		}
   11543  1.281   msaitoh 		/* FALLTHROUGH */
   11544  1.281   msaitoh 	default:
   11545  1.281   msaitoh 		/* Default to 0 */
   11546  1.281   msaitoh 		*bank = 0;
   11547  1.271     ozaki 
   11548  1.281   msaitoh 		/* Check bank 0 */
   11549  1.281   msaitoh 		wm_read_ich8_byte(sc, act_offset, &sig_byte);
   11550  1.281   msaitoh 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
   11551  1.281   msaitoh 			*bank = 0;
   11552  1.281   msaitoh 			return 0;
   11553  1.281   msaitoh 		}
   11554  1.271     ozaki 
   11555  1.281   msaitoh 		/* Check bank 1 */
   11556  1.281   msaitoh 		wm_read_ich8_byte(sc, act_offset + bank1_offset,
   11557  1.281   msaitoh 		    &sig_byte);
   11558  1.281   msaitoh 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
   11559  1.281   msaitoh 			*bank = 1;
   11560  1.281   msaitoh 			return 0;
   11561  1.281   msaitoh 		}
   11562  1.271     ozaki 	}
   11563  1.271     ozaki 
   11564  1.281   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: No valid NVM bank present\n",
   11565  1.281   msaitoh 		device_xname(sc->sc_dev)));
   11566  1.281   msaitoh 	return -1;
   11567  1.281   msaitoh }
   11568  1.281   msaitoh 
   11569  1.281   msaitoh /******************************************************************************
   11570  1.281   msaitoh  * This function does initial flash setup so that a new read/write/erase cycle
   11571  1.281   msaitoh  * can be started.
   11572  1.281   msaitoh  *
   11573  1.281   msaitoh  * sc - The pointer to the hw structure
   11574  1.281   msaitoh  ****************************************************************************/
   11575  1.281   msaitoh static int32_t
   11576  1.281   msaitoh wm_ich8_cycle_init(struct wm_softc *sc)
   11577  1.281   msaitoh {
   11578  1.281   msaitoh 	uint16_t hsfsts;
   11579  1.281   msaitoh 	int32_t error = 1;
   11580  1.281   msaitoh 	int32_t i     = 0;
   11581  1.271     ozaki 
   11582  1.281   msaitoh 	hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   11583  1.117   msaitoh 
   11584  1.281   msaitoh 	/* May be check the Flash Des Valid bit in Hw status */
   11585  1.281   msaitoh 	if ((hsfsts & HSFSTS_FLDVAL) == 0) {
   11586  1.281   msaitoh 		return error;
   11587  1.117   msaitoh 	}
   11588  1.117   msaitoh 
   11589  1.281   msaitoh 	/* Clear FCERR in Hw status by writing 1 */
   11590  1.281   msaitoh 	/* Clear DAEL in Hw status by writing a 1 */
   11591  1.281   msaitoh 	hsfsts |= HSFSTS_ERR | HSFSTS_DAEL;
   11592  1.117   msaitoh 
   11593  1.281   msaitoh 	ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   11594  1.117   msaitoh 
   11595  1.281   msaitoh 	/*
   11596  1.281   msaitoh 	 * Either we should have a hardware SPI cycle in progress bit to check
   11597  1.281   msaitoh 	 * against, in order to start a new cycle or FDONE bit should be
   11598  1.281   msaitoh 	 * changed in the hardware so that it is 1 after harware reset, which
   11599  1.281   msaitoh 	 * can then be used as an indication whether a cycle is in progress or
   11600  1.281   msaitoh 	 * has been completed .. we should also have some software semaphore
   11601  1.281   msaitoh 	 * mechanism to guard FDONE or the cycle in progress bit so that two
   11602  1.281   msaitoh 	 * threads access to those bits can be sequentiallized or a way so that
   11603  1.281   msaitoh 	 * 2 threads dont start the cycle at the same time
   11604  1.281   msaitoh 	 */
   11605  1.127    bouyer 
   11606  1.281   msaitoh 	if ((hsfsts & HSFSTS_FLINPRO) == 0) {
   11607  1.281   msaitoh 		/*
   11608  1.281   msaitoh 		 * There is no cycle running at present, so we can start a
   11609  1.281   msaitoh 		 * cycle
   11610  1.281   msaitoh 		 */
   11611  1.127    bouyer 
   11612  1.281   msaitoh 		/* Begin by setting Flash Cycle Done. */
   11613  1.281   msaitoh 		hsfsts |= HSFSTS_DONE;
   11614  1.281   msaitoh 		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   11615  1.281   msaitoh 		error = 0;
   11616  1.281   msaitoh 	} else {
   11617  1.281   msaitoh 		/*
   11618  1.281   msaitoh 		 * otherwise poll for sometime so the current cycle has a
   11619  1.281   msaitoh 		 * chance to end before giving up.
   11620  1.281   msaitoh 		 */
   11621  1.281   msaitoh 		for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
   11622  1.281   msaitoh 			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   11623  1.281   msaitoh 			if ((hsfsts & HSFSTS_FLINPRO) == 0) {
   11624  1.281   msaitoh 				error = 0;
   11625  1.281   msaitoh 				break;
   11626  1.169   msaitoh 			}
   11627  1.281   msaitoh 			delay(1);
   11628  1.127    bouyer 		}
   11629  1.281   msaitoh 		if (error == 0) {
   11630  1.281   msaitoh 			/*
   11631  1.281   msaitoh 			 * Successful in waiting for previous cycle to timeout,
   11632  1.281   msaitoh 			 * now set the Flash Cycle Done.
   11633  1.281   msaitoh 			 */
   11634  1.281   msaitoh 			hsfsts |= HSFSTS_DONE;
   11635  1.281   msaitoh 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   11636  1.127    bouyer 		}
   11637  1.127    bouyer 	}
   11638  1.281   msaitoh 	return error;
   11639  1.127    bouyer }
   11640  1.127    bouyer 
   11641  1.281   msaitoh /******************************************************************************
   11642  1.281   msaitoh  * This function starts a flash cycle and waits for its completion
   11643  1.281   msaitoh  *
   11644  1.281   msaitoh  * sc - The pointer to the hw structure
   11645  1.281   msaitoh  ****************************************************************************/
   11646  1.281   msaitoh static int32_t
   11647  1.281   msaitoh wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout)
   11648  1.136   msaitoh {
   11649  1.281   msaitoh 	uint16_t hsflctl;
   11650  1.281   msaitoh 	uint16_t hsfsts;
   11651  1.281   msaitoh 	int32_t error = 1;
   11652  1.281   msaitoh 	uint32_t i = 0;
   11653  1.127    bouyer 
   11654  1.281   msaitoh 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
   11655  1.281   msaitoh 	hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
   11656  1.281   msaitoh 	hsflctl |= HSFCTL_GO;
   11657  1.281   msaitoh 	ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
   11658  1.139    bouyer 
   11659  1.281   msaitoh 	/* Wait till FDONE bit is set to 1 */
   11660  1.281   msaitoh 	do {
   11661  1.281   msaitoh 		hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   11662  1.281   msaitoh 		if (hsfsts & HSFSTS_DONE)
   11663  1.281   msaitoh 			break;
   11664  1.281   msaitoh 		delay(1);
   11665  1.281   msaitoh 		i++;
   11666  1.281   msaitoh 	} while (i < timeout);
   11667  1.281   msaitoh 	if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0)
   11668  1.281   msaitoh 		error = 0;
   11669  1.139    bouyer 
   11670  1.281   msaitoh 	return error;
   11671  1.139    bouyer }
   11672  1.139    bouyer 
   11673  1.281   msaitoh /******************************************************************************
   11674  1.392   msaitoh  * Reads a byte or (d)word from the NVM using the ICH8 flash access registers.
   11675  1.281   msaitoh  *
   11676  1.281   msaitoh  * sc - The pointer to the hw structure
   11677  1.281   msaitoh  * index - The index of the byte or word to read.
   11678  1.392   msaitoh  * size - Size of data to read, 1=byte 2=word, 4=dword
   11679  1.281   msaitoh  * data - Pointer to the word to store the value read.
   11680  1.281   msaitoh  *****************************************************************************/
   11681  1.281   msaitoh static int32_t
   11682  1.281   msaitoh wm_read_ich8_data(struct wm_softc *sc, uint32_t index,
   11683  1.392   msaitoh     uint32_t size, uint32_t *data)
   11684  1.139    bouyer {
   11685  1.281   msaitoh 	uint16_t hsfsts;
   11686  1.281   msaitoh 	uint16_t hsflctl;
   11687  1.281   msaitoh 	uint32_t flash_linear_address;
   11688  1.281   msaitoh 	uint32_t flash_data = 0;
   11689  1.281   msaitoh 	int32_t error = 1;
   11690  1.281   msaitoh 	int32_t count = 0;
   11691  1.281   msaitoh 
   11692  1.392   msaitoh 	if (size < 1  || size > 4 || data == 0x0 ||
   11693  1.281   msaitoh 	    index > ICH_FLASH_LINEAR_ADDR_MASK)
   11694  1.281   msaitoh 		return error;
   11695  1.139    bouyer 
   11696  1.281   msaitoh 	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
   11697  1.281   msaitoh 	    sc->sc_ich8_flash_base;
   11698  1.259   msaitoh 
   11699  1.259   msaitoh 	do {
   11700  1.281   msaitoh 		delay(1);
   11701  1.281   msaitoh 		/* Steps */
   11702  1.281   msaitoh 		error = wm_ich8_cycle_init(sc);
   11703  1.281   msaitoh 		if (error)
   11704  1.259   msaitoh 			break;
   11705  1.259   msaitoh 
   11706  1.281   msaitoh 		hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
   11707  1.281   msaitoh 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
   11708  1.281   msaitoh 		hsflctl |=  ((size - 1) << HSFCTL_BCOUNT_SHIFT)
   11709  1.281   msaitoh 		    & HSFCTL_BCOUNT_MASK;
   11710  1.281   msaitoh 		hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT;
   11711  1.392   msaitoh 		if (sc->sc_type == WM_T_PCH_SPT) {
   11712  1.392   msaitoh 			/*
   11713  1.392   msaitoh 			 * In SPT, This register is in Lan memory space, not
   11714  1.392   msaitoh 			 * flash. Therefore, only 32 bit access is supported.
   11715  1.392   msaitoh 			 */
   11716  1.392   msaitoh 			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFCTL,
   11717  1.392   msaitoh 			    (uint32_t)hsflctl);
   11718  1.392   msaitoh 		} else
   11719  1.392   msaitoh 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
   11720  1.281   msaitoh 
   11721  1.281   msaitoh 		/*
   11722  1.281   msaitoh 		 * Write the last 24 bits of index into Flash Linear address
   11723  1.281   msaitoh 		 * field in Flash Address
   11724  1.281   msaitoh 		 */
   11725  1.281   msaitoh 		/* TODO: TBD maybe check the index against the size of flash */
   11726  1.281   msaitoh 
   11727  1.281   msaitoh 		ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address);
   11728  1.259   msaitoh 
   11729  1.281   msaitoh 		error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT);
   11730  1.259   msaitoh 
   11731  1.281   msaitoh 		/*
   11732  1.281   msaitoh 		 * Check if FCERR is set to 1, if set to 1, clear it and try
   11733  1.281   msaitoh 		 * the whole sequence a few more times, else read in (shift in)
   11734  1.281   msaitoh 		 * the Flash Data0, the order is least significant byte first
   11735  1.281   msaitoh 		 * msb to lsb
   11736  1.281   msaitoh 		 */
   11737  1.281   msaitoh 		if (error == 0) {
   11738  1.281   msaitoh 			flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0);
   11739  1.281   msaitoh 			if (size == 1)
   11740  1.281   msaitoh 				*data = (uint8_t)(flash_data & 0x000000FF);
   11741  1.281   msaitoh 			else if (size == 2)
   11742  1.281   msaitoh 				*data = (uint16_t)(flash_data & 0x0000FFFF);
   11743  1.392   msaitoh 			else if (size == 4)
   11744  1.392   msaitoh 				*data = (uint32_t)flash_data;
   11745  1.281   msaitoh 			break;
   11746  1.281   msaitoh 		} else {
   11747  1.281   msaitoh 			/*
   11748  1.281   msaitoh 			 * If we've gotten here, then things are probably
   11749  1.281   msaitoh 			 * completely hosed, but if the error condition is
   11750  1.281   msaitoh 			 * detected, it won't hurt to give it another try...
   11751  1.281   msaitoh 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
   11752  1.281   msaitoh 			 */
   11753  1.281   msaitoh 			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   11754  1.281   msaitoh 			if (hsfsts & HSFSTS_ERR) {
   11755  1.281   msaitoh 				/* Repeat for some time before giving up. */
   11756  1.281   msaitoh 				continue;
   11757  1.281   msaitoh 			} else if ((hsfsts & HSFSTS_DONE) == 0)
   11758  1.281   msaitoh 				break;
   11759  1.281   msaitoh 		}
   11760  1.281   msaitoh 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
   11761  1.259   msaitoh 
   11762  1.281   msaitoh 	return error;
   11763  1.259   msaitoh }
   11764  1.259   msaitoh 
   11765  1.281   msaitoh /******************************************************************************
   11766  1.281   msaitoh  * Reads a single byte from the NVM using the ICH8 flash access registers.
   11767  1.281   msaitoh  *
   11768  1.281   msaitoh  * sc - pointer to wm_hw structure
   11769  1.281   msaitoh  * index - The index of the byte to read.
   11770  1.281   msaitoh  * data - Pointer to a byte to store the value read.
   11771  1.281   msaitoh  *****************************************************************************/
   11772  1.281   msaitoh static int32_t
   11773  1.281   msaitoh wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data)
   11774  1.169   msaitoh {
   11775  1.281   msaitoh 	int32_t status;
   11776  1.392   msaitoh 	uint32_t word = 0;
   11777  1.250   msaitoh 
   11778  1.281   msaitoh 	status = wm_read_ich8_data(sc, index, 1, &word);
   11779  1.281   msaitoh 	if (status == 0)
   11780  1.281   msaitoh 		*data = (uint8_t)word;
   11781  1.281   msaitoh 	else
   11782  1.281   msaitoh 		*data = 0;
   11783  1.169   msaitoh 
   11784  1.281   msaitoh 	return status;
   11785  1.281   msaitoh }
   11786  1.250   msaitoh 
   11787  1.281   msaitoh /******************************************************************************
   11788  1.281   msaitoh  * Reads a word from the NVM using the ICH8 flash access registers.
   11789  1.281   msaitoh  *
   11790  1.281   msaitoh  * sc - pointer to wm_hw structure
   11791  1.281   msaitoh  * index - The starting byte index of the word to read.
   11792  1.281   msaitoh  * data - Pointer to a word to store the value read.
   11793  1.281   msaitoh  *****************************************************************************/
   11794  1.281   msaitoh static int32_t
   11795  1.281   msaitoh wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data)
   11796  1.281   msaitoh {
   11797  1.281   msaitoh 	int32_t status;
   11798  1.392   msaitoh 	uint32_t word = 0;
   11799  1.392   msaitoh 
   11800  1.392   msaitoh 	status = wm_read_ich8_data(sc, index, 2, &word);
   11801  1.392   msaitoh 	if (status == 0)
   11802  1.392   msaitoh 		*data = (uint16_t)word;
   11803  1.392   msaitoh 	else
   11804  1.392   msaitoh 		*data = 0;
   11805  1.392   msaitoh 
   11806  1.392   msaitoh 	return status;
   11807  1.392   msaitoh }
   11808  1.392   msaitoh 
   11809  1.392   msaitoh /******************************************************************************
   11810  1.392   msaitoh  * Reads a dword from the NVM using the ICH8 flash access registers.
   11811  1.392   msaitoh  *
   11812  1.392   msaitoh  * sc - pointer to wm_hw structure
   11813  1.392   msaitoh  * index - The starting byte index of the word to read.
   11814  1.392   msaitoh  * data - Pointer to a word to store the value read.
   11815  1.392   msaitoh  *****************************************************************************/
   11816  1.392   msaitoh static int32_t
   11817  1.392   msaitoh wm_read_ich8_dword(struct wm_softc *sc, uint32_t index, uint32_t *data)
   11818  1.392   msaitoh {
   11819  1.392   msaitoh 	int32_t status;
   11820  1.169   msaitoh 
   11821  1.392   msaitoh 	status = wm_read_ich8_data(sc, index, 4, data);
   11822  1.281   msaitoh 	return status;
   11823  1.169   msaitoh }
   11824  1.169   msaitoh 
   11825  1.139    bouyer /******************************************************************************
   11826  1.139    bouyer  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
   11827  1.139    bouyer  * register.
   11828  1.139    bouyer  *
   11829  1.139    bouyer  * sc - Struct containing variables accessed by shared code
   11830  1.139    bouyer  * offset - offset of word in the EEPROM to read
   11831  1.139    bouyer  * data - word read from the EEPROM
   11832  1.139    bouyer  * words - number of words to read
   11833  1.139    bouyer  *****************************************************************************/
   11834  1.139    bouyer static int
   11835  1.280   msaitoh wm_nvm_read_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data)
   11836  1.139    bouyer {
   11837  1.194   msaitoh 	int32_t  error = 0;
   11838  1.194   msaitoh 	uint32_t flash_bank = 0;
   11839  1.194   msaitoh 	uint32_t act_offset = 0;
   11840  1.194   msaitoh 	uint32_t bank_offset = 0;
   11841  1.194   msaitoh 	uint16_t word = 0;
   11842  1.194   msaitoh 	uint16_t i = 0;
   11843  1.194   msaitoh 
   11844  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11845  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11846  1.420   msaitoh 
   11847  1.281   msaitoh 	/*
   11848  1.281   msaitoh 	 * We need to know which is the valid flash bank.  In the event
   11849  1.194   msaitoh 	 * that we didn't allocate eeprom_shadow_ram, we may not be
   11850  1.194   msaitoh 	 * managing flash_bank.  So it cannot be trusted and needs
   11851  1.194   msaitoh 	 * to be updated with each read.
   11852  1.194   msaitoh 	 */
   11853  1.280   msaitoh 	error = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
   11854  1.194   msaitoh 	if (error) {
   11855  1.297   msaitoh 		DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
   11856  1.297   msaitoh 			device_xname(sc->sc_dev)));
   11857  1.262   msaitoh 		flash_bank = 0;
   11858  1.194   msaitoh 	}
   11859  1.139    bouyer 
   11860  1.238   msaitoh 	/*
   11861  1.238   msaitoh 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
   11862  1.238   msaitoh 	 * size
   11863  1.238   msaitoh 	 */
   11864  1.194   msaitoh 	bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
   11865  1.139    bouyer 
   11866  1.194   msaitoh 	error = wm_get_swfwhw_semaphore(sc);
   11867  1.194   msaitoh 	if (error) {
   11868  1.194   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   11869  1.169   msaitoh 		    __func__);
   11870  1.194   msaitoh 		return error;
   11871  1.194   msaitoh 	}
   11872  1.139    bouyer 
   11873  1.194   msaitoh 	for (i = 0; i < words; i++) {
   11874  1.194   msaitoh 		/* The NVM part needs a byte offset, hence * 2 */
   11875  1.194   msaitoh 		act_offset = bank_offset + ((offset + i) * 2);
   11876  1.194   msaitoh 		error = wm_read_ich8_word(sc, act_offset, &word);
   11877  1.194   msaitoh 		if (error) {
   11878  1.238   msaitoh 			aprint_error_dev(sc->sc_dev,
   11879  1.238   msaitoh 			    "%s: failed to read NVM\n", __func__);
   11880  1.194   msaitoh 			break;
   11881  1.194   msaitoh 		}
   11882  1.194   msaitoh 		data[i] = word;
   11883  1.194   msaitoh 	}
   11884  1.194   msaitoh 
   11885  1.194   msaitoh 	wm_put_swfwhw_semaphore(sc);
   11886  1.194   msaitoh 	return error;
   11887  1.139    bouyer }
   11888  1.139    bouyer 
   11889  1.392   msaitoh /******************************************************************************
   11890  1.392   msaitoh  * Reads a 16 bit word or words from the EEPROM using the SPT's flash access
   11891  1.392   msaitoh  * register.
   11892  1.392   msaitoh  *
   11893  1.392   msaitoh  * sc - Struct containing variables accessed by shared code
   11894  1.392   msaitoh  * offset - offset of word in the EEPROM to read
   11895  1.392   msaitoh  * data - word read from the EEPROM
   11896  1.392   msaitoh  * words - number of words to read
   11897  1.392   msaitoh  *****************************************************************************/
   11898  1.392   msaitoh static int
   11899  1.392   msaitoh wm_nvm_read_spt(struct wm_softc *sc, int offset, int words, uint16_t *data)
   11900  1.392   msaitoh {
   11901  1.392   msaitoh 	int32_t  error = 0;
   11902  1.392   msaitoh 	uint32_t flash_bank = 0;
   11903  1.392   msaitoh 	uint32_t act_offset = 0;
   11904  1.392   msaitoh 	uint32_t bank_offset = 0;
   11905  1.392   msaitoh 	uint32_t dword = 0;
   11906  1.392   msaitoh 	uint16_t i = 0;
   11907  1.392   msaitoh 
   11908  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11909  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11910  1.420   msaitoh 
   11911  1.392   msaitoh 	/*
   11912  1.392   msaitoh 	 * We need to know which is the valid flash bank.  In the event
   11913  1.392   msaitoh 	 * that we didn't allocate eeprom_shadow_ram, we may not be
   11914  1.392   msaitoh 	 * managing flash_bank.  So it cannot be trusted and needs
   11915  1.392   msaitoh 	 * to be updated with each read.
   11916  1.392   msaitoh 	 */
   11917  1.392   msaitoh 	error = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
   11918  1.392   msaitoh 	if (error) {
   11919  1.392   msaitoh 		DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
   11920  1.392   msaitoh 			device_xname(sc->sc_dev)));
   11921  1.392   msaitoh 		flash_bank = 0;
   11922  1.392   msaitoh 	}
   11923  1.392   msaitoh 
   11924  1.392   msaitoh 	/*
   11925  1.392   msaitoh 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
   11926  1.392   msaitoh 	 * size
   11927  1.392   msaitoh 	 */
   11928  1.392   msaitoh 	bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
   11929  1.392   msaitoh 
   11930  1.392   msaitoh 	error = wm_get_swfwhw_semaphore(sc);
   11931  1.392   msaitoh 	if (error) {
   11932  1.392   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   11933  1.392   msaitoh 		    __func__);
   11934  1.392   msaitoh 		return error;
   11935  1.392   msaitoh 	}
   11936  1.392   msaitoh 
   11937  1.392   msaitoh 	for (i = 0; i < words; i++) {
   11938  1.392   msaitoh 		/* The NVM part needs a byte offset, hence * 2 */
   11939  1.392   msaitoh 		act_offset = bank_offset + ((offset + i) * 2);
   11940  1.392   msaitoh 		/* but we must read dword aligned, so mask ... */
   11941  1.392   msaitoh 		error = wm_read_ich8_dword(sc, act_offset & ~0x3, &dword);
   11942  1.392   msaitoh 		if (error) {
   11943  1.392   msaitoh 			aprint_error_dev(sc->sc_dev,
   11944  1.392   msaitoh 			    "%s: failed to read NVM\n", __func__);
   11945  1.392   msaitoh 			break;
   11946  1.392   msaitoh 		}
   11947  1.392   msaitoh 		/* ... and pick out low or high word */
   11948  1.392   msaitoh 		if ((act_offset & 0x2) == 0)
   11949  1.392   msaitoh 			data[i] = (uint16_t)(dword & 0xFFFF);
   11950  1.392   msaitoh 		else
   11951  1.392   msaitoh 			data[i] = (uint16_t)((dword >> 16) & 0xFFFF);
   11952  1.392   msaitoh 	}
   11953  1.392   msaitoh 
   11954  1.392   msaitoh 	wm_put_swfwhw_semaphore(sc);
   11955  1.392   msaitoh 	return error;
   11956  1.392   msaitoh }
   11957  1.392   msaitoh 
   11958  1.321   msaitoh /* iNVM */
   11959  1.321   msaitoh 
   11960  1.321   msaitoh static int
   11961  1.321   msaitoh wm_nvm_read_word_invm(struct wm_softc *sc, uint16_t address, uint16_t *data)
   11962  1.321   msaitoh {
   11963  1.321   msaitoh 	int32_t  rv = 0;
   11964  1.321   msaitoh 	uint32_t invm_dword;
   11965  1.321   msaitoh 	uint16_t i;
   11966  1.321   msaitoh 	uint8_t record_type, word_address;
   11967  1.321   msaitoh 
   11968  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11969  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11970  1.420   msaitoh 
   11971  1.321   msaitoh 	for (i = 0; i < INVM_SIZE; i++) {
   11972  1.329   msaitoh 		invm_dword = CSR_READ(sc, WM_INVM_DATA_REG(i));
   11973  1.321   msaitoh 		/* Get record type */
   11974  1.321   msaitoh 		record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
   11975  1.321   msaitoh 		if (record_type == INVM_UNINITIALIZED_STRUCTURE)
   11976  1.321   msaitoh 			break;
   11977  1.321   msaitoh 		if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE)
   11978  1.321   msaitoh 			i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
   11979  1.321   msaitoh 		if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE)
   11980  1.321   msaitoh 			i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
   11981  1.321   msaitoh 		if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) {
   11982  1.321   msaitoh 			word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
   11983  1.321   msaitoh 			if (word_address == address) {
   11984  1.321   msaitoh 				*data = INVM_DWORD_TO_WORD_DATA(invm_dword);
   11985  1.321   msaitoh 				rv = 0;
   11986  1.321   msaitoh 				break;
   11987  1.321   msaitoh 			}
   11988  1.321   msaitoh 		}
   11989  1.321   msaitoh 	}
   11990  1.321   msaitoh 
   11991  1.321   msaitoh 	return rv;
   11992  1.321   msaitoh }
   11993  1.321   msaitoh 
   11994  1.321   msaitoh static int
   11995  1.321   msaitoh wm_nvm_read_invm(struct wm_softc *sc, int offset, int words, uint16_t *data)
   11996  1.321   msaitoh {
   11997  1.321   msaitoh 	int rv = 0;
   11998  1.321   msaitoh 	int i;
   11999  1.421   msaitoh 
   12000  1.421   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12001  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   12002  1.321   msaitoh 
   12003  1.321   msaitoh 	for (i = 0; i < words; i++) {
   12004  1.321   msaitoh 		switch (offset + i) {
   12005  1.321   msaitoh 		case NVM_OFF_MACADDR:
   12006  1.321   msaitoh 		case NVM_OFF_MACADDR1:
   12007  1.321   msaitoh 		case NVM_OFF_MACADDR2:
   12008  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset + i, &data[i]);
   12009  1.321   msaitoh 			if (rv != 0) {
   12010  1.321   msaitoh 				data[i] = 0xffff;
   12011  1.321   msaitoh 				rv = -1;
   12012  1.321   msaitoh 			}
   12013  1.321   msaitoh 			break;
   12014  1.321   msaitoh 		case NVM_OFF_CFG2:
   12015  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12016  1.321   msaitoh 			if (rv != 0) {
   12017  1.321   msaitoh 				*data = NVM_INIT_CTRL_2_DEFAULT_I211;
   12018  1.321   msaitoh 				rv = 0;
   12019  1.321   msaitoh 			}
   12020  1.321   msaitoh 			break;
   12021  1.321   msaitoh 		case NVM_OFF_CFG4:
   12022  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12023  1.321   msaitoh 			if (rv != 0) {
   12024  1.321   msaitoh 				*data = NVM_INIT_CTRL_4_DEFAULT_I211;
   12025  1.321   msaitoh 				rv = 0;
   12026  1.321   msaitoh 			}
   12027  1.321   msaitoh 			break;
   12028  1.321   msaitoh 		case NVM_OFF_LED_1_CFG:
   12029  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12030  1.321   msaitoh 			if (rv != 0) {
   12031  1.321   msaitoh 				*data = NVM_LED_1_CFG_DEFAULT_I211;
   12032  1.321   msaitoh 				rv = 0;
   12033  1.321   msaitoh 			}
   12034  1.321   msaitoh 			break;
   12035  1.321   msaitoh 		case NVM_OFF_LED_0_2_CFG:
   12036  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12037  1.321   msaitoh 			if (rv != 0) {
   12038  1.321   msaitoh 				*data = NVM_LED_0_2_CFG_DEFAULT_I211;
   12039  1.321   msaitoh 				rv = 0;
   12040  1.321   msaitoh 			}
   12041  1.321   msaitoh 			break;
   12042  1.321   msaitoh 		case NVM_OFF_ID_LED_SETTINGS:
   12043  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12044  1.321   msaitoh 			if (rv != 0) {
   12045  1.321   msaitoh 				*data = ID_LED_RESERVED_FFFF;
   12046  1.321   msaitoh 				rv = 0;
   12047  1.321   msaitoh 			}
   12048  1.321   msaitoh 			break;
   12049  1.321   msaitoh 		default:
   12050  1.321   msaitoh 			DPRINTF(WM_DEBUG_NVM,
   12051  1.321   msaitoh 			    ("NVM word 0x%02x is not mapped.\n", offset));
   12052  1.321   msaitoh 			*data = NVM_RESERVED_WORD;
   12053  1.321   msaitoh 			break;
   12054  1.321   msaitoh 		}
   12055  1.321   msaitoh 	}
   12056  1.321   msaitoh 
   12057  1.321   msaitoh 	return rv;
   12058  1.321   msaitoh }
   12059  1.321   msaitoh 
   12060  1.328   msaitoh /* Lock, detecting NVM type, validate checksum, version and read */
   12061  1.281   msaitoh 
   12062  1.281   msaitoh /*
   12063  1.281   msaitoh  * wm_nvm_acquire:
   12064  1.139    bouyer  *
   12065  1.281   msaitoh  *	Perform the EEPROM handshake required on some chips.
   12066  1.281   msaitoh  */
   12067  1.281   msaitoh static int
   12068  1.281   msaitoh wm_nvm_acquire(struct wm_softc *sc)
   12069  1.139    bouyer {
   12070  1.281   msaitoh 	uint32_t reg;
   12071  1.281   msaitoh 	int x;
   12072  1.281   msaitoh 	int ret = 0;
   12073  1.194   msaitoh 
   12074  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12075  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12076  1.420   msaitoh 
   12077  1.423   msaitoh 	if (sc->sc_type >= WM_T_ICH8) {
   12078  1.423   msaitoh 		ret = wm_get_nvm_ich8lan(sc);
   12079  1.423   msaitoh 	} else if (sc->sc_flags & WM_F_LOCK_EXTCNF) {
   12080  1.281   msaitoh 		ret = wm_get_swfwhw_semaphore(sc);
   12081  1.281   msaitoh 	} else if (sc->sc_flags & WM_F_LOCK_SWFW) {
   12082  1.281   msaitoh 		/* This will also do wm_get_swsm_semaphore() if needed */
   12083  1.281   msaitoh 		ret = wm_get_swfw_semaphore(sc, SWFW_EEP_SM);
   12084  1.281   msaitoh 	} else if (sc->sc_flags & WM_F_LOCK_SWSM) {
   12085  1.281   msaitoh 		ret = wm_get_swsm_semaphore(sc);
   12086  1.194   msaitoh 	}
   12087  1.194   msaitoh 
   12088  1.281   msaitoh 	if (ret) {
   12089  1.281   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   12090  1.281   msaitoh 			__func__);
   12091  1.281   msaitoh 		return 1;
   12092  1.281   msaitoh 	}
   12093  1.194   msaitoh 
   12094  1.281   msaitoh 	if (sc->sc_flags & WM_F_LOCK_EECD) {
   12095  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   12096  1.194   msaitoh 
   12097  1.281   msaitoh 		/* Request EEPROM access. */
   12098  1.281   msaitoh 		reg |= EECD_EE_REQ;
   12099  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   12100  1.194   msaitoh 
   12101  1.281   msaitoh 		/* ..and wait for it to be granted. */
   12102  1.281   msaitoh 		for (x = 0; x < 1000; x++) {
   12103  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_EECD);
   12104  1.281   msaitoh 			if (reg & EECD_EE_GNT)
   12105  1.194   msaitoh 				break;
   12106  1.281   msaitoh 			delay(5);
   12107  1.194   msaitoh 		}
   12108  1.281   msaitoh 		if ((reg & EECD_EE_GNT) == 0) {
   12109  1.281   msaitoh 			aprint_error_dev(sc->sc_dev,
   12110  1.281   msaitoh 			    "could not acquire EEPROM GNT\n");
   12111  1.281   msaitoh 			reg &= ~EECD_EE_REQ;
   12112  1.281   msaitoh 			CSR_WRITE(sc, WMREG_EECD, reg);
   12113  1.281   msaitoh 			if (sc->sc_flags & WM_F_LOCK_EXTCNF)
   12114  1.281   msaitoh 				wm_put_swfwhw_semaphore(sc);
   12115  1.281   msaitoh 			if (sc->sc_flags & WM_F_LOCK_SWFW)
   12116  1.281   msaitoh 				wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
   12117  1.281   msaitoh 			else if (sc->sc_flags & WM_F_LOCK_SWSM)
   12118  1.281   msaitoh 				wm_put_swsm_semaphore(sc);
   12119  1.281   msaitoh 			return 1;
   12120  1.194   msaitoh 		}
   12121  1.194   msaitoh 	}
   12122  1.281   msaitoh 
   12123  1.281   msaitoh 	return 0;
   12124  1.139    bouyer }
   12125  1.139    bouyer 
   12126  1.281   msaitoh /*
   12127  1.281   msaitoh  * wm_nvm_release:
   12128  1.139    bouyer  *
   12129  1.281   msaitoh  *	Release the EEPROM mutex.
   12130  1.281   msaitoh  */
   12131  1.281   msaitoh static void
   12132  1.281   msaitoh wm_nvm_release(struct wm_softc *sc)
   12133  1.139    bouyer {
   12134  1.281   msaitoh 	uint32_t reg;
   12135  1.194   msaitoh 
   12136  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12137  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12138  1.420   msaitoh 
   12139  1.281   msaitoh 	if (sc->sc_flags & WM_F_LOCK_EECD) {
   12140  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   12141  1.281   msaitoh 		reg &= ~EECD_EE_REQ;
   12142  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   12143  1.281   msaitoh 	}
   12144  1.194   msaitoh 
   12145  1.423   msaitoh 	if (sc->sc_type >= WM_T_ICH8) {
   12146  1.423   msaitoh 		wm_put_nvm_ich8lan(sc);
   12147  1.423   msaitoh 	} else if (sc->sc_flags & WM_F_LOCK_EXTCNF)
   12148  1.281   msaitoh 		wm_put_swfwhw_semaphore(sc);
   12149  1.516   msaitoh 	else if (sc->sc_flags & WM_F_LOCK_SWFW)
   12150  1.281   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
   12151  1.281   msaitoh 	else if (sc->sc_flags & WM_F_LOCK_SWSM)
   12152  1.281   msaitoh 		wm_put_swsm_semaphore(sc);
   12153  1.139    bouyer }
   12154  1.139    bouyer 
   12155  1.281   msaitoh static int
   12156  1.281   msaitoh wm_nvm_is_onboard_eeprom(struct wm_softc *sc)
   12157  1.139    bouyer {
   12158  1.281   msaitoh 	uint32_t eecd = 0;
   12159  1.281   msaitoh 
   12160  1.281   msaitoh 	if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574
   12161  1.281   msaitoh 	    || sc->sc_type == WM_T_82583) {
   12162  1.281   msaitoh 		eecd = CSR_READ(sc, WMREG_EECD);
   12163  1.281   msaitoh 
   12164  1.281   msaitoh 		/* Isolate bits 15 & 16 */
   12165  1.281   msaitoh 		eecd = ((eecd >> 15) & 0x03);
   12166  1.194   msaitoh 
   12167  1.281   msaitoh 		/* If both bits are set, device is Flash type */
   12168  1.281   msaitoh 		if (eecd == 0x03)
   12169  1.281   msaitoh 			return 0;
   12170  1.281   msaitoh 	}
   12171  1.281   msaitoh 	return 1;
   12172  1.281   msaitoh }
   12173  1.194   msaitoh 
   12174  1.321   msaitoh static int
   12175  1.321   msaitoh wm_nvm_get_flash_presence_i210(struct wm_softc *sc)
   12176  1.321   msaitoh {
   12177  1.321   msaitoh 	uint32_t eec;
   12178  1.321   msaitoh 
   12179  1.321   msaitoh 	eec = CSR_READ(sc, WMREG_EEC);
   12180  1.321   msaitoh 	if ((eec & EEC_FLASH_DETECTED) != 0)
   12181  1.321   msaitoh 		return 1;
   12182  1.321   msaitoh 
   12183  1.321   msaitoh 	return 0;
   12184  1.321   msaitoh }
   12185  1.321   msaitoh 
   12186  1.281   msaitoh /*
   12187  1.281   msaitoh  * wm_nvm_validate_checksum
   12188  1.281   msaitoh  *
   12189  1.281   msaitoh  * The checksum is defined as the sum of the first 64 (16 bit) words.
   12190  1.281   msaitoh  */
   12191  1.281   msaitoh static int
   12192  1.281   msaitoh wm_nvm_validate_checksum(struct wm_softc *sc)
   12193  1.281   msaitoh {
   12194  1.281   msaitoh 	uint16_t checksum;
   12195  1.281   msaitoh 	uint16_t eeprom_data;
   12196  1.281   msaitoh #ifdef WM_DEBUG
   12197  1.281   msaitoh 	uint16_t csum_wordaddr, valid_checksum;
   12198  1.281   msaitoh #endif
   12199  1.281   msaitoh 	int i;
   12200  1.194   msaitoh 
   12201  1.281   msaitoh 	checksum = 0;
   12202  1.139    bouyer 
   12203  1.281   msaitoh 	/* Don't check for I211 */
   12204  1.281   msaitoh 	if (sc->sc_type == WM_T_I211)
   12205  1.281   msaitoh 		return 0;
   12206  1.194   msaitoh 
   12207  1.281   msaitoh #ifdef WM_DEBUG
   12208  1.281   msaitoh 	if (sc->sc_type == WM_T_PCH_LPT) {
   12209  1.293   msaitoh 		csum_wordaddr = NVM_OFF_COMPAT;
   12210  1.281   msaitoh 		valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
   12211  1.281   msaitoh 	} else {
   12212  1.293   msaitoh 		csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1;
   12213  1.281   msaitoh 		valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;
   12214  1.281   msaitoh 	}
   12215  1.194   msaitoh 
   12216  1.281   msaitoh 	/* Dump EEPROM image for debug */
   12217  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   12218  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   12219  1.281   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
   12220  1.392   msaitoh 		/* XXX PCH_SPT? */
   12221  1.281   msaitoh 		wm_nvm_read(sc, csum_wordaddr, 1, &eeprom_data);
   12222  1.281   msaitoh 		if ((eeprom_data & valid_checksum) == 0) {
   12223  1.281   msaitoh 			DPRINTF(WM_DEBUG_NVM,
   12224  1.281   msaitoh 			    ("%s: NVM need to be updated (%04x != %04x)\n",
   12225  1.281   msaitoh 				device_xname(sc->sc_dev), eeprom_data,
   12226  1.281   msaitoh 				    valid_checksum));
   12227  1.281   msaitoh 		}
   12228  1.281   msaitoh 	}
   12229  1.194   msaitoh 
   12230  1.281   msaitoh 	if ((wm_debug & WM_DEBUG_NVM) != 0) {
   12231  1.281   msaitoh 		printf("%s: NVM dump:\n", device_xname(sc->sc_dev));
   12232  1.293   msaitoh 		for (i = 0; i < NVM_SIZE; i++) {
   12233  1.281   msaitoh 			if (wm_nvm_read(sc, i, 1, &eeprom_data))
   12234  1.301   msaitoh 				printf("XXXX ");
   12235  1.281   msaitoh 			else
   12236  1.301   msaitoh 				printf("%04hx ", eeprom_data);
   12237  1.281   msaitoh 			if (i % 8 == 7)
   12238  1.281   msaitoh 				printf("\n");
   12239  1.194   msaitoh 		}
   12240  1.281   msaitoh 	}
   12241  1.194   msaitoh 
   12242  1.281   msaitoh #endif /* WM_DEBUG */
   12243  1.139    bouyer 
   12244  1.293   msaitoh 	for (i = 0; i < NVM_SIZE; i++) {
   12245  1.281   msaitoh 		if (wm_nvm_read(sc, i, 1, &eeprom_data))
   12246  1.281   msaitoh 			return 1;
   12247  1.281   msaitoh 		checksum += eeprom_data;
   12248  1.281   msaitoh 	}
   12249  1.139    bouyer 
   12250  1.281   msaitoh 	if (checksum != (uint16_t) NVM_CHECKSUM) {
   12251  1.281   msaitoh #ifdef WM_DEBUG
   12252  1.281   msaitoh 		printf("%s: NVM checksum mismatch (%04x != %04x)\n",
   12253  1.281   msaitoh 		    device_xname(sc->sc_dev), checksum, NVM_CHECKSUM);
   12254  1.281   msaitoh #endif
   12255  1.281   msaitoh 	}
   12256  1.139    bouyer 
   12257  1.281   msaitoh 	return 0;
   12258  1.139    bouyer }
   12259  1.139    bouyer 
   12260  1.328   msaitoh static void
   12261  1.347   msaitoh wm_nvm_version_invm(struct wm_softc *sc)
   12262  1.347   msaitoh {
   12263  1.347   msaitoh 	uint32_t dword;
   12264  1.347   msaitoh 
   12265  1.347   msaitoh 	/*
   12266  1.347   msaitoh 	 * Linux's code to decode version is very strange, so we don't
   12267  1.347   msaitoh 	 * obey that algorithm and just use word 61 as the document.
   12268  1.347   msaitoh 	 * Perhaps it's not perfect though...
   12269  1.347   msaitoh 	 *
   12270  1.347   msaitoh 	 * Example:
   12271  1.347   msaitoh 	 *
   12272  1.347   msaitoh 	 *   Word61: 00800030 -> Version 0.6 (I211 spec update notes about 0.6)
   12273  1.347   msaitoh 	 */
   12274  1.347   msaitoh 	dword = CSR_READ(sc, WM_INVM_DATA_REG(61));
   12275  1.347   msaitoh 	dword = __SHIFTOUT(dword, INVM_VER_1);
   12276  1.347   msaitoh 	sc->sc_nvm_ver_major = __SHIFTOUT(dword, INVM_MAJOR);
   12277  1.347   msaitoh 	sc->sc_nvm_ver_minor = __SHIFTOUT(dword, INVM_MINOR);
   12278  1.347   msaitoh }
   12279  1.347   msaitoh 
   12280  1.347   msaitoh static void
   12281  1.328   msaitoh wm_nvm_version(struct wm_softc *sc)
   12282  1.328   msaitoh {
   12283  1.331   msaitoh 	uint16_t major, minor, build, patch;
   12284  1.328   msaitoh 	uint16_t uid0, uid1;
   12285  1.328   msaitoh 	uint16_t nvm_data;
   12286  1.328   msaitoh 	uint16_t off;
   12287  1.330   msaitoh 	bool check_version = false;
   12288  1.330   msaitoh 	bool check_optionrom = false;
   12289  1.334   msaitoh 	bool have_build = false;
   12290  1.512   msaitoh 	bool have_uid = true;
   12291  1.328   msaitoh 
   12292  1.334   msaitoh 	/*
   12293  1.334   msaitoh 	 * Version format:
   12294  1.334   msaitoh 	 *
   12295  1.334   msaitoh 	 * XYYZ
   12296  1.334   msaitoh 	 * X0YZ
   12297  1.334   msaitoh 	 * X0YY
   12298  1.334   msaitoh 	 *
   12299  1.334   msaitoh 	 * Example:
   12300  1.334   msaitoh 	 *
   12301  1.334   msaitoh 	 *	82571	0x50a2	5.10.2?	(the spec update notes about 5.6-5.10)
   12302  1.334   msaitoh 	 *	82571	0x50a6	5.10.6?
   12303  1.334   msaitoh 	 *	82572	0x506a	5.6.10?
   12304  1.334   msaitoh 	 *	82572EI	0x5069	5.6.9?
   12305  1.334   msaitoh 	 *	82574L	0x1080	1.8.0?	(the spec update notes about 2.1.4)
   12306  1.334   msaitoh 	 *		0x2013	2.1.3?
   12307  1.334   msaitoh 	 *	82583	0x10a0	1.10.0? (document says it's default vaule)
   12308  1.334   msaitoh 	 */
   12309  1.328   msaitoh 	wm_nvm_read(sc, NVM_OFF_IMAGE_UID1, 1, &uid1);
   12310  1.328   msaitoh 	switch (sc->sc_type) {
   12311  1.334   msaitoh 	case WM_T_82571:
   12312  1.334   msaitoh 	case WM_T_82572:
   12313  1.334   msaitoh 	case WM_T_82574:
   12314  1.350   msaitoh 	case WM_T_82583:
   12315  1.334   msaitoh 		check_version = true;
   12316  1.334   msaitoh 		check_optionrom = true;
   12317  1.334   msaitoh 		have_build = true;
   12318  1.334   msaitoh 		break;
   12319  1.328   msaitoh 	case WM_T_82575:
   12320  1.328   msaitoh 	case WM_T_82576:
   12321  1.328   msaitoh 	case WM_T_82580:
   12322  1.330   msaitoh 		if ((uid1 & NVM_MAJOR_MASK) != NVM_UID_VALID)
   12323  1.330   msaitoh 			check_version = true;
   12324  1.328   msaitoh 		break;
   12325  1.328   msaitoh 	case WM_T_I211:
   12326  1.347   msaitoh 		wm_nvm_version_invm(sc);
   12327  1.512   msaitoh 		have_uid = false;
   12328  1.347   msaitoh 		goto printver;
   12329  1.328   msaitoh 	case WM_T_I210:
   12330  1.328   msaitoh 		if (!wm_nvm_get_flash_presence_i210(sc)) {
   12331  1.347   msaitoh 			wm_nvm_version_invm(sc);
   12332  1.512   msaitoh 			have_uid = false;
   12333  1.347   msaitoh 			goto printver;
   12334  1.328   msaitoh 		}
   12335  1.328   msaitoh 		/* FALLTHROUGH */
   12336  1.328   msaitoh 	case WM_T_I350:
   12337  1.328   msaitoh 	case WM_T_I354:
   12338  1.330   msaitoh 		check_version = true;
   12339  1.330   msaitoh 		check_optionrom = true;
   12340  1.330   msaitoh 		break;
   12341  1.330   msaitoh 	default:
   12342  1.330   msaitoh 		return;
   12343  1.330   msaitoh 	}
   12344  1.330   msaitoh 	if (check_version) {
   12345  1.330   msaitoh 		wm_nvm_read(sc, NVM_OFF_VERSION, 1, &nvm_data);
   12346  1.330   msaitoh 		major = (nvm_data & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
   12347  1.334   msaitoh 		if (have_build || ((nvm_data & 0x0f00) != 0x0000)) {
   12348  1.330   msaitoh 			minor = (nvm_data & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
   12349  1.330   msaitoh 			build = nvm_data & NVM_BUILD_MASK;
   12350  1.331   msaitoh 			have_build = true;
   12351  1.334   msaitoh 		} else
   12352  1.334   msaitoh 			minor = nvm_data & 0x00ff;
   12353  1.334   msaitoh 
   12354  1.330   msaitoh 		/* Decimal */
   12355  1.330   msaitoh 		minor = (minor / 16) * 10 + (minor % 16);
   12356  1.347   msaitoh 		sc->sc_nvm_ver_major = major;
   12357  1.347   msaitoh 		sc->sc_nvm_ver_minor = minor;
   12358  1.330   msaitoh 
   12359  1.347   msaitoh printver:
   12360  1.347   msaitoh 		aprint_verbose(", version %d.%d", sc->sc_nvm_ver_major,
   12361  1.347   msaitoh 		    sc->sc_nvm_ver_minor);
   12362  1.350   msaitoh 		if (have_build) {
   12363  1.350   msaitoh 			sc->sc_nvm_ver_build = build;
   12364  1.334   msaitoh 			aprint_verbose(".%d", build);
   12365  1.350   msaitoh 		}
   12366  1.330   msaitoh 	}
   12367  1.330   msaitoh 	if (check_optionrom) {
   12368  1.328   msaitoh 		wm_nvm_read(sc, NVM_OFF_COMB_VER_PTR, 1, &off);
   12369  1.328   msaitoh 		/* Option ROM Version */
   12370  1.328   msaitoh 		if ((off != 0x0000) && (off != 0xffff)) {
   12371  1.328   msaitoh 			off += NVM_COMBO_VER_OFF;
   12372  1.328   msaitoh 			wm_nvm_read(sc, off + 1, 1, &uid1);
   12373  1.328   msaitoh 			wm_nvm_read(sc, off, 1, &uid0);
   12374  1.328   msaitoh 			if ((uid0 != 0) && (uid0 != 0xffff)
   12375  1.328   msaitoh 			    && (uid1 != 0) && (uid1 != 0xffff)) {
   12376  1.331   msaitoh 				/* 16bits */
   12377  1.331   msaitoh 				major = uid0 >> 8;
   12378  1.331   msaitoh 				build = (uid0 << 8) | (uid1 >> 8);
   12379  1.331   msaitoh 				patch = uid1 & 0x00ff;
   12380  1.330   msaitoh 				aprint_verbose(", option ROM Version %d.%d.%d",
   12381  1.331   msaitoh 				    major, build, patch);
   12382  1.328   msaitoh 			}
   12383  1.328   msaitoh 		}
   12384  1.328   msaitoh 	}
   12385  1.328   msaitoh 
   12386  1.512   msaitoh 	if (have_uid) {
   12387  1.512   msaitoh 		wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0);
   12388  1.512   msaitoh 		aprint_verbose(", Image Unique ID %08x", (uid1 << 16) | uid0);
   12389  1.512   msaitoh 	}
   12390  1.328   msaitoh }
   12391  1.328   msaitoh 
   12392  1.281   msaitoh /*
   12393  1.281   msaitoh  * wm_nvm_read:
   12394  1.139    bouyer  *
   12395  1.281   msaitoh  *	Read data from the serial EEPROM.
   12396  1.281   msaitoh  */
   12397  1.169   msaitoh static int
   12398  1.281   msaitoh wm_nvm_read(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   12399  1.169   msaitoh {
   12400  1.169   msaitoh 	int rv;
   12401  1.169   msaitoh 
   12402  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12403  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12404  1.420   msaitoh 
   12405  1.281   msaitoh 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   12406  1.281   msaitoh 		return 1;
   12407  1.281   msaitoh 
   12408  1.281   msaitoh 	if (wm_nvm_acquire(sc))
   12409  1.281   msaitoh 		return 1;
   12410  1.281   msaitoh 
   12411  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   12412  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   12413  1.281   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
   12414  1.281   msaitoh 		rv = wm_nvm_read_ich8(sc, word, wordcnt, data);
   12415  1.392   msaitoh 	else if (sc->sc_type == WM_T_PCH_SPT)
   12416  1.392   msaitoh 		rv = wm_nvm_read_spt(sc, word, wordcnt, data);
   12417  1.321   msaitoh 	else if (sc->sc_flags & WM_F_EEPROM_INVM)
   12418  1.321   msaitoh 		rv = wm_nvm_read_invm(sc, word, wordcnt, data);
   12419  1.281   msaitoh 	else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR)
   12420  1.281   msaitoh 		rv = wm_nvm_read_eerd(sc, word, wordcnt, data);
   12421  1.281   msaitoh 	else if (sc->sc_flags & WM_F_EEPROM_SPI)
   12422  1.281   msaitoh 		rv = wm_nvm_read_spi(sc, word, wordcnt, data);
   12423  1.281   msaitoh 	else
   12424  1.281   msaitoh 		rv = wm_nvm_read_uwire(sc, word, wordcnt, data);
   12425  1.169   msaitoh 
   12426  1.281   msaitoh 	wm_nvm_release(sc);
   12427  1.169   msaitoh 	return rv;
   12428  1.169   msaitoh }
   12429  1.169   msaitoh 
   12430  1.281   msaitoh /*
   12431  1.281   msaitoh  * Hardware semaphores.
   12432  1.281   msaitoh  * Very complexed...
   12433  1.281   msaitoh  */
   12434  1.281   msaitoh 
   12435  1.169   msaitoh static int
   12436  1.424   msaitoh wm_get_null(struct wm_softc *sc)
   12437  1.424   msaitoh {
   12438  1.424   msaitoh 
   12439  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12440  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12441  1.424   msaitoh 	return 0;
   12442  1.424   msaitoh }
   12443  1.424   msaitoh 
   12444  1.424   msaitoh static void
   12445  1.424   msaitoh wm_put_null(struct wm_softc *sc)
   12446  1.424   msaitoh {
   12447  1.424   msaitoh 
   12448  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12449  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12450  1.424   msaitoh 	return;
   12451  1.424   msaitoh }
   12452  1.424   msaitoh 
   12453  1.424   msaitoh /*
   12454  1.424   msaitoh  * Get hardware semaphore.
   12455  1.424   msaitoh  * Same as e1000_get_hw_semaphore_generic()
   12456  1.424   msaitoh  */
   12457  1.424   msaitoh static int
   12458  1.281   msaitoh wm_get_swsm_semaphore(struct wm_softc *sc)
   12459  1.169   msaitoh {
   12460  1.281   msaitoh 	int32_t timeout;
   12461  1.281   msaitoh 	uint32_t swsm;
   12462  1.281   msaitoh 
   12463  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12464  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   12465  1.424   msaitoh 	KASSERT(sc->sc_nvm_wordsize > 0);
   12466  1.421   msaitoh 
   12467  1.424   msaitoh 	/* Get the SW semaphore. */
   12468  1.424   msaitoh 	timeout = sc->sc_nvm_wordsize + 1;
   12469  1.424   msaitoh 	while (timeout) {
   12470  1.424   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   12471  1.281   msaitoh 
   12472  1.424   msaitoh 		if ((swsm & SWSM_SMBI) == 0)
   12473  1.424   msaitoh 			break;
   12474  1.169   msaitoh 
   12475  1.424   msaitoh 		delay(50);
   12476  1.424   msaitoh 		timeout--;
   12477  1.424   msaitoh 	}
   12478  1.169   msaitoh 
   12479  1.424   msaitoh 	if (timeout == 0) {
   12480  1.424   msaitoh 		aprint_error_dev(sc->sc_dev,
   12481  1.424   msaitoh 		    "could not acquire SWSM SMBI\n");
   12482  1.424   msaitoh 		return 1;
   12483  1.281   msaitoh 	}
   12484  1.281   msaitoh 
   12485  1.281   msaitoh 	/* Get the FW semaphore. */
   12486  1.294   msaitoh 	timeout = sc->sc_nvm_wordsize + 1;
   12487  1.281   msaitoh 	while (timeout) {
   12488  1.281   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   12489  1.281   msaitoh 		swsm |= SWSM_SWESMBI;
   12490  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, swsm);
   12491  1.281   msaitoh 		/* If we managed to set the bit we got the semaphore. */
   12492  1.281   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   12493  1.281   msaitoh 		if (swsm & SWSM_SWESMBI)
   12494  1.281   msaitoh 			break;
   12495  1.169   msaitoh 
   12496  1.281   msaitoh 		delay(50);
   12497  1.281   msaitoh 		timeout--;
   12498  1.281   msaitoh 	}
   12499  1.281   msaitoh 
   12500  1.281   msaitoh 	if (timeout == 0) {
   12501  1.388   msaitoh 		aprint_error_dev(sc->sc_dev,
   12502  1.388   msaitoh 		    "could not acquire SWSM SWESMBI\n");
   12503  1.281   msaitoh 		/* Release semaphores */
   12504  1.281   msaitoh 		wm_put_swsm_semaphore(sc);
   12505  1.281   msaitoh 		return 1;
   12506  1.281   msaitoh 	}
   12507  1.169   msaitoh 	return 0;
   12508  1.169   msaitoh }
   12509  1.169   msaitoh 
   12510  1.420   msaitoh /*
   12511  1.420   msaitoh  * Put hardware semaphore.
   12512  1.420   msaitoh  * Same as e1000_put_hw_semaphore_generic()
   12513  1.420   msaitoh  */
   12514  1.281   msaitoh static void
   12515  1.281   msaitoh wm_put_swsm_semaphore(struct wm_softc *sc)
   12516  1.169   msaitoh {
   12517  1.281   msaitoh 	uint32_t swsm;
   12518  1.169   msaitoh 
   12519  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12520  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12521  1.420   msaitoh 
   12522  1.281   msaitoh 	swsm = CSR_READ(sc, WMREG_SWSM);
   12523  1.281   msaitoh 	swsm &= ~(SWSM_SMBI | SWSM_SWESMBI);
   12524  1.281   msaitoh 	CSR_WRITE(sc, WMREG_SWSM, swsm);
   12525  1.169   msaitoh }
   12526  1.169   msaitoh 
   12527  1.420   msaitoh /*
   12528  1.420   msaitoh  * Get SW/FW semaphore.
   12529  1.420   msaitoh  * Same as e1000_acquire_swfw_sync_82575().
   12530  1.420   msaitoh  */
   12531  1.169   msaitoh static int
   12532  1.281   msaitoh wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
   12533  1.169   msaitoh {
   12534  1.281   msaitoh 	uint32_t swfw_sync;
   12535  1.281   msaitoh 	uint32_t swmask = mask << SWFW_SOFT_SHIFT;
   12536  1.281   msaitoh 	uint32_t fwmask = mask << SWFW_FIRM_SHIFT;
   12537  1.281   msaitoh 	int timeout = 200;
   12538  1.169   msaitoh 
   12539  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12540  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12541  1.424   msaitoh 	KASSERT((sc->sc_flags & WM_F_LOCK_SWSM) != 0);
   12542  1.420   msaitoh 
   12543  1.281   msaitoh 	for (timeout = 0; timeout < 200; timeout++) {
   12544  1.281   msaitoh 		if (sc->sc_flags & WM_F_LOCK_SWSM) {
   12545  1.281   msaitoh 			if (wm_get_swsm_semaphore(sc)) {
   12546  1.281   msaitoh 				aprint_error_dev(sc->sc_dev,
   12547  1.281   msaitoh 				    "%s: failed to get semaphore\n",
   12548  1.281   msaitoh 				    __func__);
   12549  1.281   msaitoh 				return 1;
   12550  1.281   msaitoh 			}
   12551  1.281   msaitoh 		}
   12552  1.281   msaitoh 		swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
   12553  1.281   msaitoh 		if ((swfw_sync & (swmask | fwmask)) == 0) {
   12554  1.281   msaitoh 			swfw_sync |= swmask;
   12555  1.281   msaitoh 			CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
   12556  1.281   msaitoh 			if (sc->sc_flags & WM_F_LOCK_SWSM)
   12557  1.281   msaitoh 				wm_put_swsm_semaphore(sc);
   12558  1.281   msaitoh 			return 0;
   12559  1.281   msaitoh 		}
   12560  1.281   msaitoh 		if (sc->sc_flags & WM_F_LOCK_SWSM)
   12561  1.281   msaitoh 			wm_put_swsm_semaphore(sc);
   12562  1.281   msaitoh 		delay(5000);
   12563  1.281   msaitoh 	}
   12564  1.281   msaitoh 	printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n",
   12565  1.281   msaitoh 	    device_xname(sc->sc_dev), mask, swfw_sync);
   12566  1.281   msaitoh 	return 1;
   12567  1.281   msaitoh }
   12568  1.169   msaitoh 
   12569  1.281   msaitoh static void
   12570  1.281   msaitoh wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
   12571  1.281   msaitoh {
   12572  1.281   msaitoh 	uint32_t swfw_sync;
   12573  1.169   msaitoh 
   12574  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12575  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12576  1.424   msaitoh 	KASSERT((sc->sc_flags & WM_F_LOCK_SWSM) != 0);
   12577  1.420   msaitoh 
   12578  1.281   msaitoh 	if (sc->sc_flags & WM_F_LOCK_SWSM) {
   12579  1.281   msaitoh 		while (wm_get_swsm_semaphore(sc) != 0)
   12580  1.281   msaitoh 			continue;
   12581  1.281   msaitoh 	}
   12582  1.281   msaitoh 	swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
   12583  1.281   msaitoh 	swfw_sync &= ~(mask << SWFW_SOFT_SHIFT);
   12584  1.281   msaitoh 	CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
   12585  1.281   msaitoh 	if (sc->sc_flags & WM_F_LOCK_SWSM)
   12586  1.281   msaitoh 		wm_put_swsm_semaphore(sc);
   12587  1.169   msaitoh }
   12588  1.169   msaitoh 
   12589  1.189   msaitoh static int
   12590  1.424   msaitoh wm_get_phy_82575(struct wm_softc *sc)
   12591  1.424   msaitoh {
   12592  1.424   msaitoh 
   12593  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12594  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12595  1.424   msaitoh 	return wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
   12596  1.424   msaitoh }
   12597  1.424   msaitoh 
   12598  1.424   msaitoh static void
   12599  1.424   msaitoh wm_put_phy_82575(struct wm_softc *sc)
   12600  1.424   msaitoh {
   12601  1.424   msaitoh 
   12602  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12603  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12604  1.424   msaitoh 	return wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
   12605  1.424   msaitoh }
   12606  1.424   msaitoh 
   12607  1.424   msaitoh static int
   12608  1.281   msaitoh wm_get_swfwhw_semaphore(struct wm_softc *sc)
   12609  1.203   msaitoh {
   12610  1.281   msaitoh 	uint32_t ext_ctrl;
   12611  1.281   msaitoh 	int timeout = 200;
   12612  1.203   msaitoh 
   12613  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12614  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12615  1.420   msaitoh 
   12616  1.424   msaitoh 	mutex_enter(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   12617  1.281   msaitoh 	for (timeout = 0; timeout < 200; timeout++) {
   12618  1.281   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   12619  1.329   msaitoh 		ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
   12620  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   12621  1.203   msaitoh 
   12622  1.281   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   12623  1.329   msaitoh 		if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
   12624  1.281   msaitoh 			return 0;
   12625  1.281   msaitoh 		delay(5000);
   12626  1.281   msaitoh 	}
   12627  1.281   msaitoh 	printf("%s: failed to get swfwhw semaphore ext_ctrl 0x%x\n",
   12628  1.281   msaitoh 	    device_xname(sc->sc_dev), ext_ctrl);
   12629  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   12630  1.281   msaitoh 	return 1;
   12631  1.281   msaitoh }
   12632  1.203   msaitoh 
   12633  1.281   msaitoh static void
   12634  1.281   msaitoh wm_put_swfwhw_semaphore(struct wm_softc *sc)
   12635  1.281   msaitoh {
   12636  1.281   msaitoh 	uint32_t ext_ctrl;
   12637  1.388   msaitoh 
   12638  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12639  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12640  1.420   msaitoh 
   12641  1.281   msaitoh 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   12642  1.329   msaitoh 	ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   12643  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   12644  1.424   msaitoh 
   12645  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   12646  1.424   msaitoh }
   12647  1.424   msaitoh 
   12648  1.424   msaitoh static int
   12649  1.424   msaitoh wm_get_swflag_ich8lan(struct wm_softc *sc)
   12650  1.424   msaitoh {
   12651  1.424   msaitoh 	uint32_t ext_ctrl;
   12652  1.424   msaitoh 	int timeout;
   12653  1.424   msaitoh 
   12654  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12655  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12656  1.424   msaitoh 	mutex_enter(sc->sc_ich_phymtx);
   12657  1.424   msaitoh 	for (timeout = 0; timeout < WM_PHY_CFG_TIMEOUT; timeout++) {
   12658  1.424   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   12659  1.424   msaitoh 		if ((ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) == 0)
   12660  1.424   msaitoh 			break;
   12661  1.424   msaitoh 		delay(1000);
   12662  1.424   msaitoh 	}
   12663  1.424   msaitoh 	if (timeout >= WM_PHY_CFG_TIMEOUT) {
   12664  1.424   msaitoh 		printf("%s: SW has already locked the resource\n",
   12665  1.424   msaitoh 		    device_xname(sc->sc_dev));
   12666  1.424   msaitoh 		goto out;
   12667  1.424   msaitoh 	}
   12668  1.424   msaitoh 
   12669  1.424   msaitoh 	ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
   12670  1.424   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   12671  1.424   msaitoh 	for (timeout = 0; timeout < 1000; timeout++) {
   12672  1.424   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   12673  1.424   msaitoh 		if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
   12674  1.424   msaitoh 			break;
   12675  1.424   msaitoh 		delay(1000);
   12676  1.424   msaitoh 	}
   12677  1.424   msaitoh 	if (timeout >= 1000) {
   12678  1.424   msaitoh 		printf("%s: failed to acquire semaphore\n",
   12679  1.424   msaitoh 		    device_xname(sc->sc_dev));
   12680  1.424   msaitoh 		ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   12681  1.424   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   12682  1.424   msaitoh 		goto out;
   12683  1.424   msaitoh 	}
   12684  1.424   msaitoh 	return 0;
   12685  1.424   msaitoh 
   12686  1.424   msaitoh out:
   12687  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx);
   12688  1.424   msaitoh 	return 1;
   12689  1.424   msaitoh }
   12690  1.424   msaitoh 
   12691  1.424   msaitoh static void
   12692  1.424   msaitoh wm_put_swflag_ich8lan(struct wm_softc *sc)
   12693  1.424   msaitoh {
   12694  1.424   msaitoh 	uint32_t ext_ctrl;
   12695  1.424   msaitoh 
   12696  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12697  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12698  1.424   msaitoh 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   12699  1.424   msaitoh 	if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) {
   12700  1.424   msaitoh 		ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   12701  1.424   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   12702  1.424   msaitoh 	} else {
   12703  1.424   msaitoh 		printf("%s: Semaphore unexpectedly released\n",
   12704  1.424   msaitoh 		    device_xname(sc->sc_dev));
   12705  1.424   msaitoh 	}
   12706  1.424   msaitoh 
   12707  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx);
   12708  1.203   msaitoh }
   12709  1.203   msaitoh 
   12710  1.203   msaitoh static int
   12711  1.423   msaitoh wm_get_nvm_ich8lan(struct wm_softc *sc)
   12712  1.423   msaitoh {
   12713  1.423   msaitoh 
   12714  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12715  1.423   msaitoh 		device_xname(sc->sc_dev), __func__));
   12716  1.423   msaitoh 	mutex_enter(sc->sc_ich_nvmmtx);
   12717  1.423   msaitoh 
   12718  1.423   msaitoh 	return 0;
   12719  1.423   msaitoh }
   12720  1.423   msaitoh 
   12721  1.423   msaitoh static void
   12722  1.423   msaitoh wm_put_nvm_ich8lan(struct wm_softc *sc)
   12723  1.423   msaitoh {
   12724  1.423   msaitoh 
   12725  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12726  1.423   msaitoh 		device_xname(sc->sc_dev), __func__));
   12727  1.423   msaitoh 	mutex_exit(sc->sc_ich_nvmmtx);
   12728  1.423   msaitoh }
   12729  1.423   msaitoh 
   12730  1.423   msaitoh static int
   12731  1.281   msaitoh wm_get_hw_semaphore_82573(struct wm_softc *sc)
   12732  1.189   msaitoh {
   12733  1.281   msaitoh 	int i = 0;
   12734  1.189   msaitoh 	uint32_t reg;
   12735  1.189   msaitoh 
   12736  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12737  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12738  1.420   msaitoh 
   12739  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   12740  1.281   msaitoh 	do {
   12741  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR,
   12742  1.281   msaitoh 		    reg | EXTCNFCTR_MDIO_SW_OWNERSHIP);
   12743  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   12744  1.281   msaitoh 		if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0)
   12745  1.281   msaitoh 			break;
   12746  1.281   msaitoh 		delay(2*1000);
   12747  1.281   msaitoh 		i++;
   12748  1.281   msaitoh 	} while (i < WM_MDIO_OWNERSHIP_TIMEOUT);
   12749  1.281   msaitoh 
   12750  1.281   msaitoh 	if (i == WM_MDIO_OWNERSHIP_TIMEOUT) {
   12751  1.281   msaitoh 		wm_put_hw_semaphore_82573(sc);
   12752  1.281   msaitoh 		log(LOG_ERR, "%s: Driver can't access the PHY\n",
   12753  1.281   msaitoh 		    device_xname(sc->sc_dev));
   12754  1.281   msaitoh 		return -1;
   12755  1.189   msaitoh 	}
   12756  1.189   msaitoh 
   12757  1.189   msaitoh 	return 0;
   12758  1.189   msaitoh }
   12759  1.189   msaitoh 
   12760  1.169   msaitoh static void
   12761  1.281   msaitoh wm_put_hw_semaphore_82573(struct wm_softc *sc)
   12762  1.169   msaitoh {
   12763  1.169   msaitoh 	uint32_t reg;
   12764  1.169   msaitoh 
   12765  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12766  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12767  1.420   msaitoh 
   12768  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   12769  1.281   msaitoh 	reg &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   12770  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
   12771  1.281   msaitoh }
   12772  1.281   msaitoh 
   12773  1.281   msaitoh /*
   12774  1.281   msaitoh  * Management mode and power management related subroutines.
   12775  1.281   msaitoh  * BMC, AMT, suspend/resume and EEE.
   12776  1.281   msaitoh  */
   12777  1.281   msaitoh 
   12778  1.378   msaitoh #ifdef WM_WOL
   12779  1.281   msaitoh static int
   12780  1.281   msaitoh wm_check_mng_mode(struct wm_softc *sc)
   12781  1.281   msaitoh {
   12782  1.281   msaitoh 	int rv;
   12783  1.281   msaitoh 
   12784  1.169   msaitoh 	switch (sc->sc_type) {
   12785  1.169   msaitoh 	case WM_T_ICH8:
   12786  1.169   msaitoh 	case WM_T_ICH9:
   12787  1.169   msaitoh 	case WM_T_ICH10:
   12788  1.190   msaitoh 	case WM_T_PCH:
   12789  1.221   msaitoh 	case WM_T_PCH2:
   12790  1.249   msaitoh 	case WM_T_PCH_LPT:
   12791  1.392   msaitoh 	case WM_T_PCH_SPT:
   12792  1.281   msaitoh 		rv = wm_check_mng_mode_ich8lan(sc);
   12793  1.281   msaitoh 		break;
   12794  1.281   msaitoh 	case WM_T_82574:
   12795  1.281   msaitoh 	case WM_T_82583:
   12796  1.281   msaitoh 		rv = wm_check_mng_mode_82574(sc);
   12797  1.281   msaitoh 		break;
   12798  1.281   msaitoh 	case WM_T_82571:
   12799  1.281   msaitoh 	case WM_T_82572:
   12800  1.281   msaitoh 	case WM_T_82573:
   12801  1.281   msaitoh 	case WM_T_80003:
   12802  1.281   msaitoh 		rv = wm_check_mng_mode_generic(sc);
   12803  1.169   msaitoh 		break;
   12804  1.169   msaitoh 	default:
   12805  1.281   msaitoh 		/* noting to do */
   12806  1.281   msaitoh 		rv = 0;
   12807  1.169   msaitoh 		break;
   12808  1.169   msaitoh 	}
   12809  1.281   msaitoh 
   12810  1.281   msaitoh 	return rv;
   12811  1.169   msaitoh }
   12812  1.173   msaitoh 
   12813  1.281   msaitoh static int
   12814  1.281   msaitoh wm_check_mng_mode_ich8lan(struct wm_softc *sc)
   12815  1.203   msaitoh {
   12816  1.281   msaitoh 	uint32_t fwsm;
   12817  1.281   msaitoh 
   12818  1.281   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   12819  1.203   msaitoh 
   12820  1.386   msaitoh 	if (((fwsm & FWSM_FW_VALID) != 0)
   12821  1.386   msaitoh 	    && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))
   12822  1.281   msaitoh 		return 1;
   12823  1.246  christos 
   12824  1.281   msaitoh 	return 0;
   12825  1.203   msaitoh }
   12826  1.203   msaitoh 
   12827  1.173   msaitoh static int
   12828  1.281   msaitoh wm_check_mng_mode_82574(struct wm_softc *sc)
   12829  1.173   msaitoh {
   12830  1.281   msaitoh 	uint16_t data;
   12831  1.173   msaitoh 
   12832  1.293   msaitoh 	wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
   12833  1.279   msaitoh 
   12834  1.293   msaitoh 	if ((data & NVM_CFG2_MNGM_MASK) != 0)
   12835  1.281   msaitoh 		return 1;
   12836  1.173   msaitoh 
   12837  1.173   msaitoh 	return 0;
   12838  1.173   msaitoh }
   12839  1.192   msaitoh 
   12840  1.281   msaitoh static int
   12841  1.281   msaitoh wm_check_mng_mode_generic(struct wm_softc *sc)
   12842  1.202   msaitoh {
   12843  1.281   msaitoh 	uint32_t fwsm;
   12844  1.202   msaitoh 
   12845  1.281   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   12846  1.202   msaitoh 
   12847  1.386   msaitoh 	if (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_IAMT_MODE)
   12848  1.281   msaitoh 		return 1;
   12849  1.202   msaitoh 
   12850  1.281   msaitoh 	return 0;
   12851  1.202   msaitoh }
   12852  1.378   msaitoh #endif /* WM_WOL */
   12853  1.202   msaitoh 
   12854  1.281   msaitoh static int
   12855  1.281   msaitoh wm_enable_mng_pass_thru(struct wm_softc *sc)
   12856  1.202   msaitoh {
   12857  1.281   msaitoh 	uint32_t manc, fwsm, factps;
   12858  1.202   msaitoh 
   12859  1.281   msaitoh 	if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) == 0)
   12860  1.281   msaitoh 		return 0;
   12861  1.202   msaitoh 
   12862  1.281   msaitoh 	manc = CSR_READ(sc, WMREG_MANC);
   12863  1.203   msaitoh 
   12864  1.281   msaitoh 	DPRINTF(WM_DEBUG_MANAGE, ("%s: MANC (%08x)\n",
   12865  1.281   msaitoh 		device_xname(sc->sc_dev), manc));
   12866  1.281   msaitoh 	if ((manc & MANC_RECV_TCO_EN) == 0)
   12867  1.281   msaitoh 		return 0;
   12868  1.203   msaitoh 
   12869  1.281   msaitoh 	if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) {
   12870  1.281   msaitoh 		fwsm = CSR_READ(sc, WMREG_FWSM);
   12871  1.281   msaitoh 		factps = CSR_READ(sc, WMREG_FACTPS);
   12872  1.281   msaitoh 		if (((factps & FACTPS_MNGCG) == 0)
   12873  1.386   msaitoh 		    && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))
   12874  1.281   msaitoh 			return 1;
   12875  1.281   msaitoh 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
   12876  1.281   msaitoh 		uint16_t data;
   12877  1.203   msaitoh 
   12878  1.281   msaitoh 		factps = CSR_READ(sc, WMREG_FACTPS);
   12879  1.293   msaitoh 		wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
   12880  1.281   msaitoh 		DPRINTF(WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n",
   12881  1.281   msaitoh 			device_xname(sc->sc_dev), factps, data));
   12882  1.281   msaitoh 		if (((factps & FACTPS_MNGCG) == 0)
   12883  1.293   msaitoh 		    && ((data & NVM_CFG2_MNGM_MASK)
   12884  1.293   msaitoh 			== (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT)))
   12885  1.281   msaitoh 			return 1;
   12886  1.281   msaitoh 	} else if (((manc & MANC_SMBUS_EN) != 0)
   12887  1.281   msaitoh 	    && ((manc & MANC_ASF_EN) == 0))
   12888  1.281   msaitoh 		return 1;
   12889  1.203   msaitoh 
   12890  1.281   msaitoh 	return 0;
   12891  1.203   msaitoh }
   12892  1.203   msaitoh 
   12893  1.386   msaitoh static bool
   12894  1.386   msaitoh wm_phy_resetisblocked(struct wm_softc *sc)
   12895  1.192   msaitoh {
   12896  1.380   msaitoh 	bool blocked = false;
   12897  1.281   msaitoh 	uint32_t reg;
   12898  1.380   msaitoh 	int i = 0;
   12899  1.192   msaitoh 
   12900  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   12901  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12902  1.420   msaitoh 
   12903  1.281   msaitoh 	switch (sc->sc_type) {
   12904  1.281   msaitoh 	case WM_T_ICH8:
   12905  1.281   msaitoh 	case WM_T_ICH9:
   12906  1.281   msaitoh 	case WM_T_ICH10:
   12907  1.281   msaitoh 	case WM_T_PCH:
   12908  1.281   msaitoh 	case WM_T_PCH2:
   12909  1.281   msaitoh 	case WM_T_PCH_LPT:
   12910  1.392   msaitoh 	case WM_T_PCH_SPT:
   12911  1.380   msaitoh 		do {
   12912  1.380   msaitoh 			reg = CSR_READ(sc, WMREG_FWSM);
   12913  1.380   msaitoh 			if ((reg & FWSM_RSPCIPHY) == 0) {
   12914  1.380   msaitoh 				blocked = true;
   12915  1.380   msaitoh 				delay(10*1000);
   12916  1.380   msaitoh 				continue;
   12917  1.380   msaitoh 			}
   12918  1.380   msaitoh 			blocked = false;
   12919  1.424   msaitoh 		} while (blocked && (i++ < 30));
   12920  1.386   msaitoh 		return blocked;
   12921  1.281   msaitoh 		break;
   12922  1.281   msaitoh 	case WM_T_82571:
   12923  1.281   msaitoh 	case WM_T_82572:
   12924  1.281   msaitoh 	case WM_T_82573:
   12925  1.281   msaitoh 	case WM_T_82574:
   12926  1.281   msaitoh 	case WM_T_82583:
   12927  1.281   msaitoh 	case WM_T_80003:
   12928  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MANC);
   12929  1.281   msaitoh 		if ((reg & MANC_BLK_PHY_RST_ON_IDE) != 0)
   12930  1.386   msaitoh 			return true;
   12931  1.281   msaitoh 		else
   12932  1.386   msaitoh 			return false;
   12933  1.281   msaitoh 		break;
   12934  1.281   msaitoh 	default:
   12935  1.281   msaitoh 		/* no problem */
   12936  1.281   msaitoh 		break;
   12937  1.192   msaitoh 	}
   12938  1.192   msaitoh 
   12939  1.386   msaitoh 	return false;
   12940  1.192   msaitoh }
   12941  1.192   msaitoh 
   12942  1.192   msaitoh static void
   12943  1.281   msaitoh wm_get_hw_control(struct wm_softc *sc)
   12944  1.221   msaitoh {
   12945  1.281   msaitoh 	uint32_t reg;
   12946  1.221   msaitoh 
   12947  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12948  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12949  1.420   msaitoh 
   12950  1.446   msaitoh 	if (sc->sc_type == WM_T_82573) {
   12951  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   12952  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD);
   12953  1.446   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   12954  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   12955  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);
   12956  1.281   msaitoh 	}
   12957  1.221   msaitoh }
   12958  1.221   msaitoh 
   12959  1.221   msaitoh static void
   12960  1.281   msaitoh wm_release_hw_control(struct wm_softc *sc)
   12961  1.192   msaitoh {
   12962  1.281   msaitoh 	uint32_t reg;
   12963  1.192   msaitoh 
   12964  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12965  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12966  1.420   msaitoh 
   12967  1.281   msaitoh 	if (sc->sc_type == WM_T_82573) {
   12968  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   12969  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_DRV_LOAD);
   12970  1.446   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   12971  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   12972  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg & ~CTRL_EXT_DRV_LOAD);
   12973  1.192   msaitoh 	}
   12974  1.192   msaitoh }
   12975  1.192   msaitoh 
   12976  1.192   msaitoh static void
   12977  1.392   msaitoh wm_gate_hw_phy_config_ich8lan(struct wm_softc *sc, bool gate)
   12978  1.221   msaitoh {
   12979  1.221   msaitoh 	uint32_t reg;
   12980  1.221   msaitoh 
   12981  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   12982  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12983  1.420   msaitoh 
   12984  1.394   msaitoh 	if (sc->sc_type < WM_T_PCH2)
   12985  1.394   msaitoh 		return;
   12986  1.394   msaitoh 
   12987  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   12988  1.221   msaitoh 
   12989  1.392   msaitoh 	if (gate)
   12990  1.281   msaitoh 		reg |= EXTCNFCTR_GATE_PHY_CFG;
   12991  1.192   msaitoh 	else
   12992  1.281   msaitoh 		reg &= ~EXTCNFCTR_GATE_PHY_CFG;
   12993  1.192   msaitoh 
   12994  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
   12995  1.192   msaitoh }
   12996  1.199   msaitoh 
   12997  1.199   msaitoh static void
   12998  1.221   msaitoh wm_smbustopci(struct wm_softc *sc)
   12999  1.221   msaitoh {
   13000  1.394   msaitoh 	uint32_t fwsm, reg;
   13001  1.447   msaitoh 	int rv = 0;
   13002  1.394   msaitoh 
   13003  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13004  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13005  1.420   msaitoh 
   13006  1.394   msaitoh 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
   13007  1.394   msaitoh 	wm_gate_hw_phy_config_ich8lan(sc, true);
   13008  1.394   msaitoh 
   13009  1.447   msaitoh 	/* Disable ULP */
   13010  1.447   msaitoh 	wm_ulp_disable(sc);
   13011  1.447   msaitoh 
   13012  1.424   msaitoh 	/* Acquire PHY semaphore */
   13013  1.424   msaitoh 	sc->phy.acquire(sc);
   13014  1.221   msaitoh 
   13015  1.221   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   13016  1.447   msaitoh 	switch (sc->sc_type) {
   13017  1.447   msaitoh 	case WM_T_PCH_LPT:
   13018  1.447   msaitoh 	case WM_T_PCH_SPT:
   13019  1.447   msaitoh 		if (wm_phy_is_accessible_pchlan(sc))
   13020  1.447   msaitoh 			break;
   13021  1.447   msaitoh 
   13022  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13023  1.447   msaitoh 		reg |= CTRL_EXT_FORCE_SMBUS;
   13024  1.447   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13025  1.447   msaitoh #if 0
   13026  1.447   msaitoh 		/* XXX Isn't this required??? */
   13027  1.447   msaitoh 		CSR_WRITE_FLUSH(sc);
   13028  1.447   msaitoh #endif
   13029  1.447   msaitoh 		delay(50 * 1000);
   13030  1.447   msaitoh 		/* FALLTHROUGH */
   13031  1.447   msaitoh 	case WM_T_PCH2:
   13032  1.447   msaitoh 		if (wm_phy_is_accessible_pchlan(sc) == true)
   13033  1.447   msaitoh 			break;
   13034  1.447   msaitoh 		/* FALLTHROUGH */
   13035  1.447   msaitoh 	case WM_T_PCH:
   13036  1.452     joerg 		if (sc->sc_type == WM_T_PCH)
   13037  1.447   msaitoh 			if ((fwsm & FWSM_FW_VALID) != 0)
   13038  1.447   msaitoh 				break;
   13039  1.447   msaitoh 
   13040  1.447   msaitoh 		if (wm_phy_resetisblocked(sc) == true) {
   13041  1.447   msaitoh 			printf("XXX reset is blocked(3)\n");
   13042  1.447   msaitoh 			break;
   13043  1.394   msaitoh 		}
   13044  1.394   msaitoh 
   13045  1.447   msaitoh 		wm_toggle_lanphypc_pch_lpt(sc);
   13046  1.221   msaitoh 
   13047  1.394   msaitoh 		if (sc->sc_type >= WM_T_PCH_LPT) {
   13048  1.447   msaitoh 			if (wm_phy_is_accessible_pchlan(sc) == true)
   13049  1.447   msaitoh 				break;
   13050  1.447   msaitoh 
   13051  1.394   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13052  1.394   msaitoh 			reg &= ~CTRL_EXT_FORCE_SMBUS;
   13053  1.394   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13054  1.447   msaitoh 
   13055  1.447   msaitoh 			if (wm_phy_is_accessible_pchlan(sc) == true)
   13056  1.447   msaitoh 				break;
   13057  1.447   msaitoh 			rv = -1;
   13058  1.394   msaitoh 		}
   13059  1.447   msaitoh 		break;
   13060  1.447   msaitoh 	default:
   13061  1.447   msaitoh 		break;
   13062  1.221   msaitoh 	}
   13063  1.394   msaitoh 
   13064  1.394   msaitoh 	/* Release semaphore */
   13065  1.424   msaitoh 	sc->phy.release(sc);
   13066  1.394   msaitoh 
   13067  1.447   msaitoh 	if (rv == 0) {
   13068  1.447   msaitoh 		if (wm_phy_resetisblocked(sc)) {
   13069  1.447   msaitoh 			printf("XXX reset is blocked(4)\n");
   13070  1.447   msaitoh 			goto out;
   13071  1.447   msaitoh 		}
   13072  1.447   msaitoh 		wm_reset_phy(sc);
   13073  1.447   msaitoh 		if (wm_phy_resetisblocked(sc))
   13074  1.447   msaitoh 			printf("XXX reset is blocked(4)\n");
   13075  1.447   msaitoh 	}
   13076  1.447   msaitoh 
   13077  1.447   msaitoh out:
   13078  1.394   msaitoh 	/*
   13079  1.394   msaitoh 	 * Ungate automatic PHY configuration by hardware on non-managed 82579
   13080  1.394   msaitoh 	 */
   13081  1.447   msaitoh 	if ((sc->sc_type == WM_T_PCH2) && ((fwsm & FWSM_FW_VALID) == 0)) {
   13082  1.447   msaitoh 		delay(10*1000);
   13083  1.394   msaitoh 		wm_gate_hw_phy_config_ich8lan(sc, false);
   13084  1.447   msaitoh 	}
   13085  1.221   msaitoh }
   13086  1.221   msaitoh 
   13087  1.221   msaitoh static void
   13088  1.203   msaitoh wm_init_manageability(struct wm_softc *sc)
   13089  1.203   msaitoh {
   13090  1.203   msaitoh 
   13091  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13092  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   13093  1.203   msaitoh 	if (sc->sc_flags & WM_F_HAS_MANAGE) {
   13094  1.203   msaitoh 		uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H);
   13095  1.203   msaitoh 		uint32_t manc = CSR_READ(sc, WMREG_MANC);
   13096  1.203   msaitoh 
   13097  1.281   msaitoh 		/* Disable hardware interception of ARP */
   13098  1.203   msaitoh 		manc &= ~MANC_ARP_EN;
   13099  1.203   msaitoh 
   13100  1.281   msaitoh 		/* Enable receiving management packets to the host */
   13101  1.203   msaitoh 		if (sc->sc_type >= WM_T_82571) {
   13102  1.203   msaitoh 			manc |= MANC_EN_MNG2HOST;
   13103  1.203   msaitoh 			manc2h |= MANC2H_PORT_623| MANC2H_PORT_624;
   13104  1.203   msaitoh 			CSR_WRITE(sc, WMREG_MANC2H, manc2h);
   13105  1.203   msaitoh 		}
   13106  1.203   msaitoh 
   13107  1.203   msaitoh 		CSR_WRITE(sc, WMREG_MANC, manc);
   13108  1.203   msaitoh 	}
   13109  1.203   msaitoh }
   13110  1.203   msaitoh 
   13111  1.203   msaitoh static void
   13112  1.203   msaitoh wm_release_manageability(struct wm_softc *sc)
   13113  1.203   msaitoh {
   13114  1.203   msaitoh 
   13115  1.203   msaitoh 	if (sc->sc_flags & WM_F_HAS_MANAGE) {
   13116  1.203   msaitoh 		uint32_t manc = CSR_READ(sc, WMREG_MANC);
   13117  1.203   msaitoh 
   13118  1.260   msaitoh 		manc |= MANC_ARP_EN;
   13119  1.203   msaitoh 		if (sc->sc_type >= WM_T_82571)
   13120  1.203   msaitoh 			manc &= ~MANC_EN_MNG2HOST;
   13121  1.203   msaitoh 
   13122  1.203   msaitoh 		CSR_WRITE(sc, WMREG_MANC, manc);
   13123  1.203   msaitoh 	}
   13124  1.203   msaitoh }
   13125  1.203   msaitoh 
   13126  1.203   msaitoh static void
   13127  1.203   msaitoh wm_get_wakeup(struct wm_softc *sc)
   13128  1.203   msaitoh {
   13129  1.203   msaitoh 
   13130  1.203   msaitoh 	/* 0: HAS_AMT, ARC_SUBSYS_VALID, ASF_FIRMWARE_PRES */
   13131  1.203   msaitoh 	switch (sc->sc_type) {
   13132  1.203   msaitoh 	case WM_T_82573:
   13133  1.203   msaitoh 	case WM_T_82583:
   13134  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_AMT;
   13135  1.203   msaitoh 		/* FALLTHROUGH */
   13136  1.246  christos 	case WM_T_80003:
   13137  1.203   msaitoh 	case WM_T_82575:
   13138  1.203   msaitoh 	case WM_T_82576:
   13139  1.208   msaitoh 	case WM_T_82580:
   13140  1.228   msaitoh 	case WM_T_I350:
   13141  1.265   msaitoh 	case WM_T_I354:
   13142  1.386   msaitoh 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE) != 0)
   13143  1.203   msaitoh 			sc->sc_flags |= WM_F_ARC_SUBSYS_VALID;
   13144  1.449   msaitoh 		/* FALLTHROUGH */
   13145  1.449   msaitoh 	case WM_T_82541:
   13146  1.449   msaitoh 	case WM_T_82541_2:
   13147  1.449   msaitoh 	case WM_T_82547:
   13148  1.449   msaitoh 	case WM_T_82547_2:
   13149  1.450   msaitoh 	case WM_T_82571:
   13150  1.450   msaitoh 	case WM_T_82572:
   13151  1.450   msaitoh 	case WM_T_82574:
   13152  1.203   msaitoh 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
   13153  1.203   msaitoh 		break;
   13154  1.203   msaitoh 	case WM_T_ICH8:
   13155  1.203   msaitoh 	case WM_T_ICH9:
   13156  1.203   msaitoh 	case WM_T_ICH10:
   13157  1.203   msaitoh 	case WM_T_PCH:
   13158  1.221   msaitoh 	case WM_T_PCH2:
   13159  1.249   msaitoh 	case WM_T_PCH_LPT:
   13160  1.449   msaitoh 	case WM_T_PCH_SPT:
   13161  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_AMT;
   13162  1.203   msaitoh 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
   13163  1.203   msaitoh 		break;
   13164  1.203   msaitoh 	default:
   13165  1.203   msaitoh 		break;
   13166  1.203   msaitoh 	}
   13167  1.203   msaitoh 
   13168  1.203   msaitoh 	/* 1: HAS_MANAGE */
   13169  1.203   msaitoh 	if (wm_enable_mng_pass_thru(sc) != 0)
   13170  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_MANAGE;
   13171  1.203   msaitoh 
   13172  1.203   msaitoh 	/*
   13173  1.203   msaitoh 	 * Note that the WOL flags is set after the resetting of the eeprom
   13174  1.203   msaitoh 	 * stuff
   13175  1.203   msaitoh 	 */
   13176  1.203   msaitoh }
   13177  1.203   msaitoh 
   13178  1.447   msaitoh /*
   13179  1.447   msaitoh  * Unconfigure Ultra Low Power mode.
   13180  1.447   msaitoh  * Only for I217 and newer (see below).
   13181  1.447   msaitoh  */
   13182  1.447   msaitoh static void
   13183  1.447   msaitoh wm_ulp_disable(struct wm_softc *sc)
   13184  1.447   msaitoh {
   13185  1.447   msaitoh 	uint32_t reg;
   13186  1.447   msaitoh 	int i = 0;
   13187  1.447   msaitoh 
   13188  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13189  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   13190  1.447   msaitoh 	/* Exclude old devices */
   13191  1.447   msaitoh 	if ((sc->sc_type < WM_T_PCH_LPT)
   13192  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I217_LM)
   13193  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I217_V)
   13194  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_LM2)
   13195  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_V2))
   13196  1.447   msaitoh 		return;
   13197  1.447   msaitoh 
   13198  1.447   msaitoh 	if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) != 0) {
   13199  1.447   msaitoh 		/* Request ME un-configure ULP mode in the PHY */
   13200  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_H2ME);
   13201  1.447   msaitoh 		reg &= ~H2ME_ULP;
   13202  1.447   msaitoh 		reg |= H2ME_ENFORCE_SETTINGS;
   13203  1.447   msaitoh 		CSR_WRITE(sc, WMREG_H2ME, reg);
   13204  1.447   msaitoh 
   13205  1.447   msaitoh 		/* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
   13206  1.447   msaitoh 		while ((CSR_READ(sc, WMREG_FWSM) & FWSM_ULP_CFG_DONE) != 0) {
   13207  1.447   msaitoh 			if (i++ == 30) {
   13208  1.447   msaitoh 				printf("%s timed out\n", __func__);
   13209  1.447   msaitoh 				return;
   13210  1.447   msaitoh 			}
   13211  1.447   msaitoh 			delay(10 * 1000);
   13212  1.447   msaitoh 		}
   13213  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_H2ME);
   13214  1.447   msaitoh 		reg &= ~H2ME_ENFORCE_SETTINGS;
   13215  1.447   msaitoh 		CSR_WRITE(sc, WMREG_H2ME, reg);
   13216  1.447   msaitoh 
   13217  1.447   msaitoh 		return;
   13218  1.447   msaitoh 	}
   13219  1.447   msaitoh 
   13220  1.447   msaitoh 	/* Acquire semaphore */
   13221  1.447   msaitoh 	sc->phy.acquire(sc);
   13222  1.447   msaitoh 
   13223  1.447   msaitoh 	/* Toggle LANPHYPC */
   13224  1.447   msaitoh 	wm_toggle_lanphypc_pch_lpt(sc);
   13225  1.447   msaitoh 
   13226  1.447   msaitoh 	/* Unforce SMBus mode in PHY */
   13227  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, CV_SMB_CTRL);
   13228  1.447   msaitoh 	if (reg == 0x0000 || reg == 0xffff) {
   13229  1.447   msaitoh 		uint32_t reg2;
   13230  1.447   msaitoh 
   13231  1.447   msaitoh 		printf("%s: Force SMBus first.\n", __func__);
   13232  1.447   msaitoh 		reg2 = CSR_READ(sc, WMREG_CTRL_EXT);
   13233  1.447   msaitoh 		reg2 |= CTRL_EXT_FORCE_SMBUS;
   13234  1.447   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg2);
   13235  1.447   msaitoh 		delay(50 * 1000);
   13236  1.447   msaitoh 
   13237  1.447   msaitoh 		reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, CV_SMB_CTRL);
   13238  1.447   msaitoh 	}
   13239  1.447   msaitoh 	reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
   13240  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, CV_SMB_CTRL, reg);
   13241  1.447   msaitoh 
   13242  1.447   msaitoh 	/* Unforce SMBus mode in MAC */
   13243  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13244  1.447   msaitoh 	reg &= ~CTRL_EXT_FORCE_SMBUS;
   13245  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13246  1.447   msaitoh 
   13247  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, HV_PM_CTRL);
   13248  1.447   msaitoh 	reg |= HV_PM_CTRL_K1_ENA;
   13249  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, HV_PM_CTRL, reg);
   13250  1.447   msaitoh 
   13251  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1);
   13252  1.447   msaitoh 	reg &= ~(I218_ULP_CONFIG1_IND
   13253  1.447   msaitoh 	    | I218_ULP_CONFIG1_STICKY_ULP
   13254  1.447   msaitoh 	    | I218_ULP_CONFIG1_RESET_TO_SMBUS
   13255  1.447   msaitoh 	    | I218_ULP_CONFIG1_WOL_HOST
   13256  1.447   msaitoh 	    | I218_ULP_CONFIG1_INBAND_EXIT
   13257  1.447   msaitoh 	    | I218_ULP_CONFIG1_EN_ULP_LANPHYPC
   13258  1.447   msaitoh 	    | I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST
   13259  1.447   msaitoh 	    | I218_ULP_CONFIG1_DIS_SMB_PERST);
   13260  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1, reg);
   13261  1.447   msaitoh 	reg |= I218_ULP_CONFIG1_START;
   13262  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1, reg);
   13263  1.447   msaitoh 
   13264  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM7);
   13265  1.447   msaitoh 	reg &= ~FEXTNVM7_DIS_SMB_PERST;
   13266  1.447   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM7, reg);
   13267  1.447   msaitoh 
   13268  1.447   msaitoh 	/* Release semaphore */
   13269  1.447   msaitoh 	sc->phy.release(sc);
   13270  1.447   msaitoh 	wm_gmii_reset(sc);
   13271  1.447   msaitoh 	delay(50 * 1000);
   13272  1.447   msaitoh }
   13273  1.447   msaitoh 
   13274  1.203   msaitoh /* WOL in the newer chipset interfaces (pchlan) */
   13275  1.203   msaitoh static void
   13276  1.203   msaitoh wm_enable_phy_wakeup(struct wm_softc *sc)
   13277  1.203   msaitoh {
   13278  1.203   msaitoh #if 0
   13279  1.203   msaitoh 	uint16_t preg;
   13280  1.203   msaitoh 
   13281  1.203   msaitoh 	/* Copy MAC RARs to PHY RARs */
   13282  1.203   msaitoh 
   13283  1.203   msaitoh 	/* Copy MAC MTA to PHY MTA */
   13284  1.203   msaitoh 
   13285  1.281   msaitoh 	/* Configure PHY Rx Control register */
   13286  1.281   msaitoh 
   13287  1.281   msaitoh 	/* Enable PHY wakeup in MAC register */
   13288  1.281   msaitoh 
   13289  1.281   msaitoh 	/* Configure and enable PHY wakeup in PHY registers */
   13290  1.281   msaitoh 
   13291  1.281   msaitoh 	/* Activate PHY wakeup */
   13292  1.281   msaitoh 
   13293  1.281   msaitoh 	/* XXX */
   13294  1.281   msaitoh #endif
   13295  1.281   msaitoh }
   13296  1.281   msaitoh 
   13297  1.281   msaitoh /* Power down workaround on D3 */
   13298  1.281   msaitoh static void
   13299  1.281   msaitoh wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *sc)
   13300  1.281   msaitoh {
   13301  1.281   msaitoh 	uint32_t reg;
   13302  1.281   msaitoh 	int i;
   13303  1.281   msaitoh 
   13304  1.281   msaitoh 	for (i = 0; i < 2; i++) {
   13305  1.281   msaitoh 		/* Disable link */
   13306  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13307  1.281   msaitoh 		reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
   13308  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13309  1.281   msaitoh 
   13310  1.281   msaitoh 		/*
   13311  1.281   msaitoh 		 * Call gig speed drop workaround on Gig disable before
   13312  1.281   msaitoh 		 * accessing any PHY registers
   13313  1.281   msaitoh 		 */
   13314  1.281   msaitoh 		if (sc->sc_type == WM_T_ICH8)
   13315  1.281   msaitoh 			wm_gig_downshift_workaround_ich8lan(sc);
   13316  1.203   msaitoh 
   13317  1.281   msaitoh 		/* Write VR power-down enable */
   13318  1.281   msaitoh 		reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL);
   13319  1.281   msaitoh 		reg &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
   13320  1.281   msaitoh 		reg |= IGP3_VR_CTRL_MODE_SHUTDOWN;
   13321  1.281   msaitoh 		sc->sc_mii.mii_writereg(sc->sc_dev, 1, IGP3_VR_CTRL, reg);
   13322  1.203   msaitoh 
   13323  1.281   msaitoh 		/* Read it back and test */
   13324  1.281   msaitoh 		reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL);
   13325  1.281   msaitoh 		reg &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
   13326  1.281   msaitoh 		if ((reg == IGP3_VR_CTRL_MODE_SHUTDOWN) || (i != 0))
   13327  1.281   msaitoh 			break;
   13328  1.203   msaitoh 
   13329  1.281   msaitoh 		/* Issue PHY reset and repeat at most one more time */
   13330  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   13331  1.281   msaitoh 	}
   13332  1.203   msaitoh }
   13333  1.203   msaitoh 
   13334  1.203   msaitoh static void
   13335  1.203   msaitoh wm_enable_wakeup(struct wm_softc *sc)
   13336  1.203   msaitoh {
   13337  1.203   msaitoh 	uint32_t reg, pmreg;
   13338  1.203   msaitoh 	pcireg_t pmode;
   13339  1.203   msaitoh 
   13340  1.425   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13341  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   13342  1.425   msaitoh 
   13343  1.203   msaitoh 	if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT,
   13344  1.203   msaitoh 		&pmreg, NULL) == 0)
   13345  1.203   msaitoh 		return;
   13346  1.203   msaitoh 
   13347  1.203   msaitoh 	/* Advertise the wakeup capability */
   13348  1.203   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_SWDPIN(2)
   13349  1.203   msaitoh 	    | CTRL_SWDPIN(3));
   13350  1.203   msaitoh 	CSR_WRITE(sc, WMREG_WUC, WUC_APME);
   13351  1.203   msaitoh 
   13352  1.203   msaitoh 	/* ICH workaround */
   13353  1.203   msaitoh 	switch (sc->sc_type) {
   13354  1.203   msaitoh 	case WM_T_ICH8:
   13355  1.203   msaitoh 	case WM_T_ICH9:
   13356  1.203   msaitoh 	case WM_T_ICH10:
   13357  1.203   msaitoh 	case WM_T_PCH:
   13358  1.221   msaitoh 	case WM_T_PCH2:
   13359  1.249   msaitoh 	case WM_T_PCH_LPT:
   13360  1.392   msaitoh 	case WM_T_PCH_SPT:
   13361  1.203   msaitoh 		/* Disable gig during WOL */
   13362  1.203   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13363  1.203   msaitoh 		reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS;
   13364  1.203   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13365  1.203   msaitoh 		if (sc->sc_type == WM_T_PCH)
   13366  1.203   msaitoh 			wm_gmii_reset(sc);
   13367  1.203   msaitoh 
   13368  1.203   msaitoh 		/* Power down workaround */
   13369  1.203   msaitoh 		if (sc->sc_phytype == WMPHY_82577) {
   13370  1.203   msaitoh 			struct mii_softc *child;
   13371  1.203   msaitoh 
   13372  1.203   msaitoh 			/* Assume that the PHY is copper */
   13373  1.203   msaitoh 			child = LIST_FIRST(&sc->sc_mii.mii_phys);
   13374  1.497    kardel 			if ((child != NULL) && (child->mii_mpd_rev <= 2))
   13375  1.203   msaitoh 				sc->sc_mii.mii_writereg(sc->sc_dev, 1,
   13376  1.203   msaitoh 				    (768 << 5) | 25, 0x0444); /* magic num */
   13377  1.203   msaitoh 		}
   13378  1.203   msaitoh 		break;
   13379  1.203   msaitoh 	default:
   13380  1.203   msaitoh 		break;
   13381  1.203   msaitoh 	}
   13382  1.203   msaitoh 
   13383  1.203   msaitoh 	/* Keep the laser running on fiber adapters */
   13384  1.311   msaitoh 	if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
   13385  1.311   msaitoh 	    || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) {
   13386  1.203   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13387  1.203   msaitoh 		reg |= CTRL_EXT_SWDPIN(3);
   13388  1.203   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13389  1.203   msaitoh 	}
   13390  1.203   msaitoh 
   13391  1.203   msaitoh 	reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG;
   13392  1.203   msaitoh #if 0	/* for the multicast packet */
   13393  1.203   msaitoh 	reg |= WUFC_MC;
   13394  1.203   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE);
   13395  1.203   msaitoh #endif
   13396  1.203   msaitoh 
   13397  1.442   msaitoh 	if (sc->sc_type >= WM_T_PCH)
   13398  1.203   msaitoh 		wm_enable_phy_wakeup(sc);
   13399  1.442   msaitoh 	else {
   13400  1.451   msaitoh 		CSR_WRITE(sc, WMREG_WUC, CSR_READ(sc, WMREG_WUC) | WUC_PME_EN);
   13401  1.203   msaitoh 		CSR_WRITE(sc, WMREG_WUFC, reg);
   13402  1.203   msaitoh 	}
   13403  1.203   msaitoh 
   13404  1.203   msaitoh 	if (((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   13405  1.221   msaitoh 		|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   13406  1.221   msaitoh 		|| (sc->sc_type == WM_T_PCH2))
   13407  1.203   msaitoh 		    && (sc->sc_phytype == WMPHY_IGP_3))
   13408  1.203   msaitoh 			wm_igp3_phy_powerdown_workaround_ich8lan(sc);
   13409  1.203   msaitoh 
   13410  1.203   msaitoh 	/* Request PME */
   13411  1.203   msaitoh 	pmode = pci_conf_read(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR);
   13412  1.203   msaitoh #if 0
   13413  1.203   msaitoh 	/* Disable WOL */
   13414  1.203   msaitoh 	pmode &= ~(PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN);
   13415  1.203   msaitoh #else
   13416  1.203   msaitoh 	/* For WOL */
   13417  1.203   msaitoh 	pmode |= PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN;
   13418  1.203   msaitoh #endif
   13419  1.203   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR, pmode);
   13420  1.203   msaitoh }
   13421  1.203   msaitoh 
   13422  1.377   msaitoh /* LPLU */
   13423  1.377   msaitoh 
   13424  1.377   msaitoh static void
   13425  1.377   msaitoh wm_lplu_d0_disable(struct wm_softc *sc)
   13426  1.377   msaitoh {
   13427  1.519   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   13428  1.377   msaitoh 	uint32_t reg;
   13429  1.377   msaitoh 
   13430  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13431  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   13432  1.430   msaitoh 
   13433  1.519   msaitoh 	if (sc->sc_phytype == WMPHY_IFE)
   13434  1.519   msaitoh 		return;
   13435  1.377   msaitoh 
   13436  1.519   msaitoh 	switch (sc->sc_type) {
   13437  1.519   msaitoh 	case WM_T_82571:
   13438  1.519   msaitoh 	case WM_T_82572:
   13439  1.519   msaitoh 	case WM_T_82573:
   13440  1.519   msaitoh 	case WM_T_82575:
   13441  1.519   msaitoh 	case WM_T_82576:
   13442  1.519   msaitoh 		reg = mii->mii_readreg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT);
   13443  1.519   msaitoh 		reg &= ~PMR_D0_LPLU;
   13444  1.519   msaitoh 		mii->mii_writereg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT, reg);
   13445  1.519   msaitoh 		break;
   13446  1.519   msaitoh 	case WM_T_82580:
   13447  1.519   msaitoh 	case WM_T_I350:
   13448  1.519   msaitoh 	case WM_T_I210:
   13449  1.519   msaitoh 	case WM_T_I211:
   13450  1.519   msaitoh 		reg = CSR_READ(sc, WMREG_PHPM);
   13451  1.519   msaitoh 		reg &= ~PHPM_D0A_LPLU;
   13452  1.519   msaitoh 		CSR_WRITE(sc, WMREG_PHPM, reg);
   13453  1.519   msaitoh 		break;
   13454  1.519   msaitoh 	case WM_T_82574:
   13455  1.519   msaitoh 	case WM_T_82583:
   13456  1.519   msaitoh 	case WM_T_ICH8:
   13457  1.519   msaitoh 	case WM_T_ICH9:
   13458  1.519   msaitoh 	case WM_T_ICH10:
   13459  1.519   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13460  1.519   msaitoh 		reg &= ~(PHY_CTRL_GBE_DIS | PHY_CTRL_D0A_LPLU);
   13461  1.519   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13462  1.519   msaitoh 		CSR_WRITE_FLUSH(sc);
   13463  1.519   msaitoh 		break;
   13464  1.519   msaitoh 	case WM_T_PCH:
   13465  1.519   msaitoh 	case WM_T_PCH2:
   13466  1.519   msaitoh 	case WM_T_PCH_LPT:
   13467  1.519   msaitoh 	case WM_T_PCH_SPT:
   13468  1.519   msaitoh 		reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_OEM_BITS);
   13469  1.519   msaitoh 		reg &= ~(HV_OEM_BITS_A1KDIS | HV_OEM_BITS_LPLU);
   13470  1.519   msaitoh 		if (wm_phy_resetisblocked(sc) == false)
   13471  1.519   msaitoh 			reg |= HV_OEM_BITS_ANEGNOW;
   13472  1.519   msaitoh 		wm_gmii_hv_writereg(sc->sc_dev, 1, HV_OEM_BITS, reg);
   13473  1.519   msaitoh 		break;
   13474  1.519   msaitoh 	default:
   13475  1.519   msaitoh 		break;
   13476  1.519   msaitoh 	}
   13477  1.377   msaitoh }
   13478  1.377   msaitoh 
   13479  1.281   msaitoh /* EEE */
   13480  1.228   msaitoh 
   13481  1.228   msaitoh static void
   13482  1.281   msaitoh wm_set_eee_i350(struct wm_softc *sc)
   13483  1.228   msaitoh {
   13484  1.228   msaitoh 	uint32_t ipcnfg, eeer;
   13485  1.228   msaitoh 
   13486  1.228   msaitoh 	ipcnfg = CSR_READ(sc, WMREG_IPCNFG);
   13487  1.228   msaitoh 	eeer = CSR_READ(sc, WMREG_EEER);
   13488  1.228   msaitoh 
   13489  1.228   msaitoh 	if ((sc->sc_flags & WM_F_EEE) != 0) {
   13490  1.228   msaitoh 		ipcnfg |= (IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN);
   13491  1.228   msaitoh 		eeer |= (EEER_TX_LPI_EN | EEER_RX_LPI_EN
   13492  1.228   msaitoh 		    | EEER_LPI_FC);
   13493  1.228   msaitoh 	} else {
   13494  1.228   msaitoh 		ipcnfg &= ~(IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN);
   13495  1.322   msaitoh 		ipcnfg &= ~IPCNFG_10BASE_TE;
   13496  1.228   msaitoh 		eeer &= ~(EEER_TX_LPI_EN | EEER_RX_LPI_EN
   13497  1.228   msaitoh 		    | EEER_LPI_FC);
   13498  1.228   msaitoh 	}
   13499  1.228   msaitoh 
   13500  1.228   msaitoh 	CSR_WRITE(sc, WMREG_IPCNFG, ipcnfg);
   13501  1.228   msaitoh 	CSR_WRITE(sc, WMREG_EEER, eeer);
   13502  1.228   msaitoh 	CSR_READ(sc, WMREG_IPCNFG); /* XXX flush? */
   13503  1.228   msaitoh 	CSR_READ(sc, WMREG_EEER); /* XXX flush? */
   13504  1.228   msaitoh }
   13505  1.281   msaitoh 
   13506  1.281   msaitoh /*
   13507  1.281   msaitoh  * Workarounds (mainly PHY related).
   13508  1.281   msaitoh  * Basically, PHY's workarounds are in the PHY drivers.
   13509  1.281   msaitoh  */
   13510  1.281   msaitoh 
   13511  1.281   msaitoh /* Work-around for 82566 Kumeran PCS lock loss */
   13512  1.281   msaitoh static void
   13513  1.281   msaitoh wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *sc)
   13514  1.281   msaitoh {
   13515  1.381   msaitoh #if 0
   13516  1.281   msaitoh 	int miistatus, active, i;
   13517  1.281   msaitoh 	int reg;
   13518  1.281   msaitoh 
   13519  1.281   msaitoh 	miistatus = sc->sc_mii.mii_media_status;
   13520  1.281   msaitoh 
   13521  1.281   msaitoh 	/* If the link is not up, do nothing */
   13522  1.381   msaitoh 	if ((miistatus & IFM_ACTIVE) == 0)
   13523  1.281   msaitoh 		return;
   13524  1.281   msaitoh 
   13525  1.281   msaitoh 	active = sc->sc_mii.mii_media_active;
   13526  1.281   msaitoh 
   13527  1.281   msaitoh 	/* Nothing to do if the link is other than 1Gbps */
   13528  1.281   msaitoh 	if (IFM_SUBTYPE(active) != IFM_1000_T)
   13529  1.281   msaitoh 		return;
   13530  1.281   msaitoh 
   13531  1.281   msaitoh 	for (i = 0; i < 10; i++) {
   13532  1.281   msaitoh 		/* read twice */
   13533  1.281   msaitoh 		reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
   13534  1.281   msaitoh 		reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
   13535  1.381   msaitoh 		if ((reg & IGP3_KMRN_DIAG_PCS_LOCK_LOSS) == 0)
   13536  1.281   msaitoh 			goto out;	/* GOOD! */
   13537  1.281   msaitoh 
   13538  1.281   msaitoh 		/* Reset the PHY */
   13539  1.281   msaitoh 		wm_gmii_reset(sc);
   13540  1.281   msaitoh 		delay(5*1000);
   13541  1.281   msaitoh 	}
   13542  1.281   msaitoh 
   13543  1.281   msaitoh 	/* Disable GigE link negotiation */
   13544  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13545  1.281   msaitoh 	reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
   13546  1.281   msaitoh 	CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13547  1.281   msaitoh 
   13548  1.281   msaitoh 	/*
   13549  1.281   msaitoh 	 * Call gig speed drop workaround on Gig disable before accessing
   13550  1.281   msaitoh 	 * any PHY registers.
   13551  1.281   msaitoh 	 */
   13552  1.281   msaitoh 	wm_gig_downshift_workaround_ich8lan(sc);
   13553  1.281   msaitoh 
   13554  1.281   msaitoh out:
   13555  1.281   msaitoh 	return;
   13556  1.381   msaitoh #endif
   13557  1.281   msaitoh }
   13558  1.281   msaitoh 
   13559  1.281   msaitoh /* WOL from S5 stops working */
   13560  1.281   msaitoh static void
   13561  1.281   msaitoh wm_gig_downshift_workaround_ich8lan(struct wm_softc *sc)
   13562  1.281   msaitoh {
   13563  1.281   msaitoh 	uint16_t kmrn_reg;
   13564  1.281   msaitoh 
   13565  1.281   msaitoh 	/* Only for igp3 */
   13566  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_IGP_3) {
   13567  1.281   msaitoh 		kmrn_reg = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_DIAG);
   13568  1.281   msaitoh 		kmrn_reg |= KUMCTRLSTA_DIAG_NELPBK;
   13569  1.281   msaitoh 		wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg);
   13570  1.281   msaitoh 		kmrn_reg &= ~KUMCTRLSTA_DIAG_NELPBK;
   13571  1.281   msaitoh 		wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg);
   13572  1.281   msaitoh 	}
   13573  1.281   msaitoh }
   13574  1.281   msaitoh 
   13575  1.281   msaitoh /*
   13576  1.281   msaitoh  * Workaround for pch's PHYs
   13577  1.281   msaitoh  * XXX should be moved to new PHY driver?
   13578  1.281   msaitoh  */
   13579  1.281   msaitoh static void
   13580  1.281   msaitoh wm_hv_phy_workaround_ich8lan(struct wm_softc *sc)
   13581  1.281   msaitoh {
   13582  1.420   msaitoh 
   13583  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13584  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   13585  1.420   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH);
   13586  1.420   msaitoh 
   13587  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_82577)
   13588  1.281   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   13589  1.281   msaitoh 
   13590  1.281   msaitoh 	/* (PCH rev.2) && (82577 && (phy rev 2 or 3)) */
   13591  1.281   msaitoh 
   13592  1.281   msaitoh 	/* (82577 && (phy rev 1 or 2)) || (82578 & phy rev 1)*/
   13593  1.281   msaitoh 
   13594  1.281   msaitoh 	/* 82578 */
   13595  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_82578) {
   13596  1.430   msaitoh 		struct mii_softc *child;
   13597  1.430   msaitoh 
   13598  1.430   msaitoh 		/*
   13599  1.430   msaitoh 		 * Return registers to default by doing a soft reset then
   13600  1.430   msaitoh 		 * writing 0x3140 to the control register
   13601  1.430   msaitoh 		 * 0x3140 == BMCR_SPEED0 | BMCR_AUTOEN | BMCR_FDX | BMCR_SPEED1
   13602  1.430   msaitoh 		 */
   13603  1.430   msaitoh 		child = LIST_FIRST(&sc->sc_mii.mii_phys);
   13604  1.430   msaitoh 		if ((child != NULL) && (child->mii_mpd_rev < 2)) {
   13605  1.430   msaitoh 			PHY_RESET(child);
   13606  1.430   msaitoh 			sc->sc_mii.mii_writereg(sc->sc_dev, 2, MII_BMCR,
   13607  1.430   msaitoh 			    0x3140);
   13608  1.281   msaitoh 		}
   13609  1.281   msaitoh 	}
   13610  1.281   msaitoh 
   13611  1.281   msaitoh 	/* Select page 0 */
   13612  1.424   msaitoh 	sc->phy.acquire(sc);
   13613  1.424   msaitoh 	wm_gmii_mdic_writereg(sc->sc_dev, 1, MII_IGPHY_PAGE_SELECT, 0);
   13614  1.424   msaitoh 	sc->phy.release(sc);
   13615  1.281   msaitoh 
   13616  1.281   msaitoh 	/*
   13617  1.281   msaitoh 	 * Configure the K1 Si workaround during phy reset assuming there is
   13618  1.281   msaitoh 	 * link so that it disables K1 if link is in 1Gbps.
   13619  1.281   msaitoh 	 */
   13620  1.281   msaitoh 	wm_k1_gig_workaround_hv(sc, 1);
   13621  1.281   msaitoh }
   13622  1.281   msaitoh 
   13623  1.281   msaitoh static void
   13624  1.281   msaitoh wm_lv_phy_workaround_ich8lan(struct wm_softc *sc)
   13625  1.281   msaitoh {
   13626  1.281   msaitoh 
   13627  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13628  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   13629  1.420   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH2);
   13630  1.420   msaitoh 
   13631  1.281   msaitoh 	wm_set_mdio_slow_mode_hv(sc);
   13632  1.281   msaitoh }
   13633  1.281   msaitoh 
   13634  1.424   msaitoh static int
   13635  1.281   msaitoh wm_k1_gig_workaround_hv(struct wm_softc *sc, int link)
   13636  1.281   msaitoh {
   13637  1.281   msaitoh 	int k1_enable = sc->sc_nvm_k1_enabled;
   13638  1.281   msaitoh 
   13639  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13640  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13641  1.420   msaitoh 
   13642  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0)
   13643  1.424   msaitoh 		return -1;
   13644  1.281   msaitoh 
   13645  1.281   msaitoh 	if (link) {
   13646  1.281   msaitoh 		k1_enable = 0;
   13647  1.281   msaitoh 
   13648  1.281   msaitoh 		/* Link stall fix for link up */
   13649  1.424   msaitoh 		wm_gmii_hv_writereg_locked(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x0100);
   13650  1.281   msaitoh 	} else {
   13651  1.281   msaitoh 		/* Link stall fix for link down */
   13652  1.424   msaitoh 		wm_gmii_hv_writereg_locked(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x4100);
   13653  1.281   msaitoh 	}
   13654  1.281   msaitoh 
   13655  1.281   msaitoh 	wm_configure_k1_ich8lan(sc, k1_enable);
   13656  1.424   msaitoh 	sc->phy.release(sc);
   13657  1.281   msaitoh 
   13658  1.424   msaitoh 	return 0;
   13659  1.281   msaitoh }
   13660  1.281   msaitoh 
   13661  1.281   msaitoh static void
   13662  1.281   msaitoh wm_set_mdio_slow_mode_hv(struct wm_softc *sc)
   13663  1.281   msaitoh {
   13664  1.281   msaitoh 	uint32_t reg;
   13665  1.281   msaitoh 
   13666  1.281   msaitoh 	reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL);
   13667  1.281   msaitoh 	wm_gmii_hv_writereg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL,
   13668  1.281   msaitoh 	    reg | HV_KMRN_MDIO_SLOW);
   13669  1.281   msaitoh }
   13670  1.281   msaitoh 
   13671  1.281   msaitoh static void
   13672  1.281   msaitoh wm_configure_k1_ich8lan(struct wm_softc *sc, int k1_enable)
   13673  1.281   msaitoh {
   13674  1.281   msaitoh 	uint32_t ctrl, ctrl_ext, tmp;
   13675  1.281   msaitoh 	uint16_t kmrn_reg;
   13676  1.281   msaitoh 
   13677  1.424   msaitoh 	kmrn_reg = wm_kmrn_readreg_locked(sc, KUMCTRLSTA_OFFSET_K1_CONFIG);
   13678  1.281   msaitoh 
   13679  1.281   msaitoh 	if (k1_enable)
   13680  1.281   msaitoh 		kmrn_reg |= KUMCTRLSTA_K1_ENABLE;
   13681  1.281   msaitoh 	else
   13682  1.281   msaitoh 		kmrn_reg &= ~KUMCTRLSTA_K1_ENABLE;
   13683  1.281   msaitoh 
   13684  1.424   msaitoh 	wm_kmrn_writereg_locked(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, kmrn_reg);
   13685  1.281   msaitoh 
   13686  1.281   msaitoh 	delay(20);
   13687  1.281   msaitoh 
   13688  1.281   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   13689  1.281   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   13690  1.281   msaitoh 
   13691  1.281   msaitoh 	tmp = ctrl & ~(CTRL_SPEED_1000 | CTRL_SPEED_100);
   13692  1.281   msaitoh 	tmp |= CTRL_FRCSPD;
   13693  1.281   msaitoh 
   13694  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, tmp);
   13695  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_SPD_BYPS);
   13696  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   13697  1.281   msaitoh 	delay(20);
   13698  1.281   msaitoh 
   13699  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, ctrl);
   13700  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   13701  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   13702  1.281   msaitoh 	delay(20);
   13703  1.281   msaitoh }
   13704  1.281   msaitoh 
   13705  1.281   msaitoh /* special case - for 82575 - need to do manual init ... */
   13706  1.281   msaitoh static void
   13707  1.281   msaitoh wm_reset_init_script_82575(struct wm_softc *sc)
   13708  1.281   msaitoh {
   13709  1.281   msaitoh 	/*
   13710  1.281   msaitoh 	 * remark: this is untested code - we have no board without EEPROM
   13711  1.312   msaitoh 	 *  same setup as mentioned int the FreeBSD driver for the i82575
   13712  1.281   msaitoh 	 */
   13713  1.281   msaitoh 
   13714  1.281   msaitoh 	/* SerDes configuration via SERDESCTRL */
   13715  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x00, 0x0c);
   13716  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x01, 0x78);
   13717  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x1b, 0x23);
   13718  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x23, 0x15);
   13719  1.281   msaitoh 
   13720  1.281   msaitoh 	/* CCM configuration via CCMCTL register */
   13721  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x14, 0x00);
   13722  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x10, 0x00);
   13723  1.281   msaitoh 
   13724  1.281   msaitoh 	/* PCIe lanes configuration */
   13725  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x00, 0xec);
   13726  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x61, 0xdf);
   13727  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x34, 0x05);
   13728  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x2f, 0x81);
   13729  1.281   msaitoh 
   13730  1.281   msaitoh 	/* PCIe PLL Configuration */
   13731  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x02, 0x47);
   13732  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x14, 0x00);
   13733  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x10, 0x00);
   13734  1.281   msaitoh }
   13735  1.325   msaitoh 
   13736  1.325   msaitoh static void
   13737  1.325   msaitoh wm_reset_mdicnfg_82580(struct wm_softc *sc)
   13738  1.325   msaitoh {
   13739  1.325   msaitoh 	uint32_t reg;
   13740  1.325   msaitoh 	uint16_t nvmword;
   13741  1.325   msaitoh 	int rv;
   13742  1.325   msaitoh 
   13743  1.325   msaitoh 	if ((sc->sc_flags & WM_F_SGMII) == 0)
   13744  1.325   msaitoh 		return;
   13745  1.325   msaitoh 
   13746  1.325   msaitoh 	rv = wm_nvm_read(sc, NVM_OFF_LAN_FUNC_82580(sc->sc_funcid)
   13747  1.325   msaitoh 	    + NVM_OFF_CFG3_PORTA, 1, &nvmword);
   13748  1.325   msaitoh 	if (rv != 0) {
   13749  1.325   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to read NVM\n",
   13750  1.325   msaitoh 		    __func__);
   13751  1.325   msaitoh 		return;
   13752  1.325   msaitoh 	}
   13753  1.325   msaitoh 
   13754  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_MDICNFG);
   13755  1.325   msaitoh 	if (nvmword & NVM_CFG3_PORTA_EXT_MDIO)
   13756  1.325   msaitoh 		reg |= MDICNFG_DEST;
   13757  1.325   msaitoh 	if (nvmword & NVM_CFG3_PORTA_COM_MDIO)
   13758  1.325   msaitoh 		reg |= MDICNFG_COM_MDIO;
   13759  1.325   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, reg);
   13760  1.325   msaitoh }
   13761  1.329   msaitoh 
   13762  1.447   msaitoh #define MII_INVALIDID(x)	(((x) == 0x0000) || ((x) == 0xffff))
   13763  1.447   msaitoh 
   13764  1.447   msaitoh static bool
   13765  1.447   msaitoh wm_phy_is_accessible_pchlan(struct wm_softc *sc)
   13766  1.447   msaitoh {
   13767  1.447   msaitoh 	int i;
   13768  1.447   msaitoh 	uint32_t reg;
   13769  1.447   msaitoh 	uint16_t id1, id2;
   13770  1.447   msaitoh 
   13771  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13772  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   13773  1.447   msaitoh 	id1 = id2 = 0xffff;
   13774  1.447   msaitoh 	for (i = 0; i < 2; i++) {
   13775  1.447   msaitoh 		id1 = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, MII_PHYIDR1);
   13776  1.447   msaitoh 		if (MII_INVALIDID(id1))
   13777  1.447   msaitoh 			continue;
   13778  1.447   msaitoh 		id2 = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, MII_PHYIDR2);
   13779  1.447   msaitoh 		if (MII_INVALIDID(id2))
   13780  1.447   msaitoh 			continue;
   13781  1.447   msaitoh 		break;
   13782  1.447   msaitoh 	}
   13783  1.447   msaitoh 	if (!MII_INVALIDID(id1) && !MII_INVALIDID(id2)) {
   13784  1.447   msaitoh 		goto out;
   13785  1.447   msaitoh 	}
   13786  1.447   msaitoh 
   13787  1.447   msaitoh 	if (sc->sc_type < WM_T_PCH_LPT) {
   13788  1.447   msaitoh 		sc->phy.release(sc);
   13789  1.447   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   13790  1.447   msaitoh 		id1 = wm_gmii_hv_readreg(sc->sc_dev, 2, MII_PHYIDR1);
   13791  1.447   msaitoh 		id2 = wm_gmii_hv_readreg(sc->sc_dev, 2, MII_PHYIDR2);
   13792  1.447   msaitoh 		sc->phy.acquire(sc);
   13793  1.447   msaitoh 	}
   13794  1.447   msaitoh 	if (MII_INVALIDID(id1) || MII_INVALIDID(id2)) {
   13795  1.447   msaitoh 		printf("XXX return with false\n");
   13796  1.447   msaitoh 		return false;
   13797  1.447   msaitoh 	}
   13798  1.447   msaitoh out:
   13799  1.447   msaitoh 	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
   13800  1.447   msaitoh 		/* Only unforce SMBus if ME is not active */
   13801  1.447   msaitoh 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) == 0) {
   13802  1.447   msaitoh 			/* Unforce SMBus mode in PHY */
   13803  1.447   msaitoh 			reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2,
   13804  1.447   msaitoh 			    CV_SMB_CTRL);
   13805  1.447   msaitoh 			reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
   13806  1.447   msaitoh 			wm_gmii_hv_writereg_locked(sc->sc_dev, 2,
   13807  1.447   msaitoh 			    CV_SMB_CTRL, reg);
   13808  1.447   msaitoh 
   13809  1.447   msaitoh 			/* Unforce SMBus mode in MAC */
   13810  1.447   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13811  1.447   msaitoh 			reg &= ~CTRL_EXT_FORCE_SMBUS;
   13812  1.447   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13813  1.447   msaitoh 		}
   13814  1.447   msaitoh 	}
   13815  1.447   msaitoh 	return true;
   13816  1.447   msaitoh }
   13817  1.447   msaitoh 
   13818  1.447   msaitoh static void
   13819  1.447   msaitoh wm_toggle_lanphypc_pch_lpt(struct wm_softc *sc)
   13820  1.447   msaitoh {
   13821  1.447   msaitoh 	uint32_t reg;
   13822  1.447   msaitoh 	int i;
   13823  1.447   msaitoh 
   13824  1.447   msaitoh 	/* Set PHY Config Counter to 50msec */
   13825  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM3);
   13826  1.447   msaitoh 	reg &= ~FEXTNVM3_PHY_CFG_COUNTER_MASK;
   13827  1.447   msaitoh 	reg |= FEXTNVM3_PHY_CFG_COUNTER_50MS;
   13828  1.447   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM3, reg);
   13829  1.447   msaitoh 
   13830  1.447   msaitoh 	/* Toggle LANPHYPC */
   13831  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL);
   13832  1.447   msaitoh 	reg |= CTRL_LANPHYPC_OVERRIDE;
   13833  1.447   msaitoh 	reg &= ~CTRL_LANPHYPC_VALUE;
   13834  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   13835  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   13836  1.447   msaitoh 	delay(1000);
   13837  1.447   msaitoh 	reg &= ~CTRL_LANPHYPC_OVERRIDE;
   13838  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   13839  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   13840  1.447   msaitoh 
   13841  1.447   msaitoh 	if (sc->sc_type < WM_T_PCH_LPT)
   13842  1.447   msaitoh 		delay(50 * 1000);
   13843  1.447   msaitoh 	else {
   13844  1.447   msaitoh 		i = 20;
   13845  1.447   msaitoh 
   13846  1.447   msaitoh 		do {
   13847  1.447   msaitoh 			delay(5 * 1000);
   13848  1.447   msaitoh 		} while (((CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_LPCD) == 0)
   13849  1.447   msaitoh 		    && i--);
   13850  1.447   msaitoh 
   13851  1.447   msaitoh 		delay(30 * 1000);
   13852  1.447   msaitoh 	}
   13853  1.447   msaitoh }
   13854  1.447   msaitoh 
   13855  1.445   msaitoh static int
   13856  1.445   msaitoh wm_platform_pm_pch_lpt(struct wm_softc *sc, bool link)
   13857  1.445   msaitoh {
   13858  1.445   msaitoh 	uint32_t reg = __SHIFTIN(link, LTRV_NONSNOOP_REQ)
   13859  1.445   msaitoh 	    | __SHIFTIN(link, LTRV_SNOOP_REQ) | LTRV_SEND;
   13860  1.445   msaitoh 	uint32_t rxa;
   13861  1.445   msaitoh 	uint16_t scale = 0, lat_enc = 0;
   13862  1.517   msaitoh 	int32_t obff_hwm = 0;
   13863  1.445   msaitoh 	int64_t lat_ns, value;
   13864  1.445   msaitoh 
   13865  1.445   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13866  1.445   msaitoh 		device_xname(sc->sc_dev), __func__));
   13867  1.445   msaitoh 
   13868  1.445   msaitoh 	if (link) {
   13869  1.517   msaitoh 		uint16_t max_snoop, max_nosnoop, max_ltr_enc;
   13870  1.517   msaitoh 		uint32_t status;
   13871  1.517   msaitoh 		uint16_t speed;
   13872  1.445   msaitoh 		pcireg_t preg;
   13873  1.445   msaitoh 
   13874  1.517   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   13875  1.517   msaitoh 		switch (__SHIFTOUT(status, STATUS_SPEED)) {
   13876  1.517   msaitoh 		case STATUS_SPEED_10:
   13877  1.517   msaitoh 			speed = 10;
   13878  1.517   msaitoh 			break;
   13879  1.517   msaitoh 		case STATUS_SPEED_100:
   13880  1.517   msaitoh 			speed = 100;
   13881  1.517   msaitoh 			break;
   13882  1.517   msaitoh 		case STATUS_SPEED_1000:
   13883  1.517   msaitoh 			speed = 1000;
   13884  1.517   msaitoh 			break;
   13885  1.517   msaitoh 		default:
   13886  1.517   msaitoh 			device_printf(sc->sc_dev, "Unknown speed "
   13887  1.517   msaitoh 			    "(status = %08x)\n", status);
   13888  1.517   msaitoh 			return -1;
   13889  1.517   msaitoh 		}
   13890  1.517   msaitoh 
   13891  1.517   msaitoh 		/* Rx Packet Buffer Allocation size (KB) */
   13892  1.445   msaitoh 		rxa = CSR_READ(sc, WMREG_PBA) & PBA_RXA_MASK;
   13893  1.445   msaitoh 
   13894  1.445   msaitoh 		/*
   13895  1.445   msaitoh 		 * Determine the maximum latency tolerated by the device.
   13896  1.445   msaitoh 		 *
   13897  1.445   msaitoh 		 * Per the PCIe spec, the tolerated latencies are encoded as
   13898  1.445   msaitoh 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
   13899  1.445   msaitoh 		 * a 10-bit value (0-1023) to provide a range from 1 ns to
   13900  1.445   msaitoh 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
   13901  1.445   msaitoh 		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
   13902  1.445   msaitoh 		 */
   13903  1.445   msaitoh 		lat_ns = ((int64_t)rxa * 1024 -
   13904  1.517   msaitoh 		    (2 * ((int64_t)sc->sc_ethercom.ec_if.if_mtu
   13905  1.517   msaitoh 			+ ETHER_HDR_LEN))) * 8 * 1000;
   13906  1.445   msaitoh 		if (lat_ns < 0)
   13907  1.445   msaitoh 			lat_ns = 0;
   13908  1.517   msaitoh 		else
   13909  1.445   msaitoh 			lat_ns /= speed;
   13910  1.445   msaitoh 		value = lat_ns;
   13911  1.445   msaitoh 
   13912  1.445   msaitoh 		while (value > LTRV_VALUE) {
   13913  1.445   msaitoh 			scale ++;
   13914  1.445   msaitoh 			value = howmany(value, __BIT(5));
   13915  1.445   msaitoh 		}
   13916  1.445   msaitoh 		if (scale > LTRV_SCALE_MAX) {
   13917  1.445   msaitoh 			printf("%s: Invalid LTR latency scale %d\n",
   13918  1.445   msaitoh 			    device_xname(sc->sc_dev), scale);
   13919  1.445   msaitoh 			return -1;
   13920  1.445   msaitoh 		}
   13921  1.445   msaitoh 		lat_enc = (uint16_t)(__SHIFTIN(scale, LTRV_SCALE) | value);
   13922  1.445   msaitoh 
   13923  1.511   msaitoh 		/* Determine the maximum latency tolerated by the platform */
   13924  1.445   msaitoh 		preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   13925  1.445   msaitoh 		    WM_PCI_LTR_CAP_LPT);
   13926  1.445   msaitoh 		max_snoop = preg & 0xffff;
   13927  1.445   msaitoh 		max_nosnoop = preg >> 16;
   13928  1.445   msaitoh 
   13929  1.445   msaitoh 		max_ltr_enc = MAX(max_snoop, max_nosnoop);
   13930  1.445   msaitoh 
   13931  1.445   msaitoh 		if (lat_enc > max_ltr_enc) {
   13932  1.445   msaitoh 			lat_enc = max_ltr_enc;
   13933  1.517   msaitoh 			lat_ns = __SHIFTOUT(lat_enc, PCI_LTR_MAXSNOOPLAT_VAL)
   13934  1.517   msaitoh 			    * PCI_LTR_SCALETONS(
   13935  1.517   msaitoh 				    __SHIFTOUT(lat_enc,
   13936  1.517   msaitoh 					PCI_LTR_MAXSNOOPLAT_SCALE));
   13937  1.517   msaitoh 		}
   13938  1.517   msaitoh 
   13939  1.517   msaitoh 		if (lat_ns) {
   13940  1.517   msaitoh 			lat_ns *= speed * 1000;
   13941  1.517   msaitoh 			lat_ns /= 8;
   13942  1.517   msaitoh 			lat_ns /= 1000000000;
   13943  1.517   msaitoh 			obff_hwm = (int32_t)(rxa - lat_ns);
   13944  1.517   msaitoh 		}
   13945  1.517   msaitoh 		if ((obff_hwm < 0) || (obff_hwm > SVT_OFF_HWM)) {
   13946  1.517   msaitoh 			device_printf(sc->sc_dev, "Invalid high water mark %d"
   13947  1.517   msaitoh 			    "(rxa = %d, lat_ns = %d)\n",
   13948  1.517   msaitoh 			    obff_hwm, (int32_t)rxa, (int32_t)lat_ns);
   13949  1.517   msaitoh 			return -1;
   13950  1.445   msaitoh 		}
   13951  1.445   msaitoh 	}
   13952  1.445   msaitoh 	/* Snoop and No-Snoop latencies the same */
   13953  1.445   msaitoh 	reg |= lat_enc | __SHIFTIN(lat_enc, LTRV_NONSNOOP);
   13954  1.445   msaitoh 	CSR_WRITE(sc, WMREG_LTRV, reg);
   13955  1.445   msaitoh 
   13956  1.517   msaitoh 	/* Set OBFF high water mark */
   13957  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_SVT) & ~SVT_OFF_HWM;
   13958  1.517   msaitoh 	reg |= obff_hwm;
   13959  1.517   msaitoh 	CSR_WRITE(sc, WMREG_SVT, reg);
   13960  1.517   msaitoh 
   13961  1.517   msaitoh 	/* Enable OBFF */
   13962  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_SVCR);
   13963  1.517   msaitoh 	reg |= SVCR_OFF_EN | SVCR_OFF_MASKINT;
   13964  1.517   msaitoh 	CSR_WRITE(sc, WMREG_SVCR, reg);
   13965  1.517   msaitoh 
   13966  1.445   msaitoh 	return 0;
   13967  1.445   msaitoh }
   13968  1.445   msaitoh 
   13969  1.329   msaitoh /*
   13970  1.329   msaitoh  * I210 Errata 25 and I211 Errata 10
   13971  1.329   msaitoh  * Slow System Clock.
   13972  1.329   msaitoh  */
   13973  1.329   msaitoh static void
   13974  1.329   msaitoh wm_pll_workaround_i210(struct wm_softc *sc)
   13975  1.329   msaitoh {
   13976  1.329   msaitoh 	uint32_t mdicnfg, wuc;
   13977  1.329   msaitoh 	uint32_t reg;
   13978  1.329   msaitoh 	pcireg_t pcireg;
   13979  1.329   msaitoh 	uint32_t pmreg;
   13980  1.329   msaitoh 	uint16_t nvmword, tmp_nvmword;
   13981  1.329   msaitoh 	int phyval;
   13982  1.329   msaitoh 	bool wa_done = false;
   13983  1.329   msaitoh 	int i;
   13984  1.329   msaitoh 
   13985  1.329   msaitoh 	/* Save WUC and MDICNFG registers */
   13986  1.329   msaitoh 	wuc = CSR_READ(sc, WMREG_WUC);
   13987  1.329   msaitoh 	mdicnfg = CSR_READ(sc, WMREG_MDICNFG);
   13988  1.329   msaitoh 
   13989  1.329   msaitoh 	reg = mdicnfg & ~MDICNFG_DEST;
   13990  1.329   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, reg);
   13991  1.329   msaitoh 
   13992  1.329   msaitoh 	if (wm_nvm_read(sc, INVM_AUTOLOAD, 1, &nvmword) != 0)
   13993  1.329   msaitoh 		nvmword = INVM_DEFAULT_AL;
   13994  1.329   msaitoh 	tmp_nvmword = nvmword | INVM_PLL_WO_VAL;
   13995  1.329   msaitoh 
   13996  1.329   msaitoh 	/* Get Power Management cap offset */
   13997  1.329   msaitoh 	if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT,
   13998  1.329   msaitoh 		&pmreg, NULL) == 0)
   13999  1.329   msaitoh 		return;
   14000  1.329   msaitoh 	for (i = 0; i < WM_MAX_PLL_TRIES; i++) {
   14001  1.329   msaitoh 		phyval = wm_gmii_gs40g_readreg(sc->sc_dev, 1,
   14002  1.329   msaitoh 		    GS40G_PHY_PLL_FREQ_PAGE | GS40G_PHY_PLL_FREQ_REG);
   14003  1.332   msaitoh 
   14004  1.329   msaitoh 		if ((phyval & GS40G_PHY_PLL_UNCONF) != GS40G_PHY_PLL_UNCONF) {
   14005  1.329   msaitoh 			break; /* OK */
   14006  1.329   msaitoh 		}
   14007  1.329   msaitoh 
   14008  1.329   msaitoh 		wa_done = true;
   14009  1.329   msaitoh 		/* Directly reset the internal PHY */
   14010  1.329   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL);
   14011  1.329   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);
   14012  1.329   msaitoh 
   14013  1.329   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   14014  1.329   msaitoh 		reg |= CTRL_EXT_PHYPDEN | CTRL_EXT_SDLPE;
   14015  1.329   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   14016  1.329   msaitoh 
   14017  1.329   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   14018  1.329   msaitoh 		reg = (INVM_AUTOLOAD << 4) | (tmp_nvmword << 16);
   14019  1.329   msaitoh 		CSR_WRITE(sc, WMREG_EEARBC_I210, reg);
   14020  1.332   msaitoh 
   14021  1.329   msaitoh 		pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   14022  1.329   msaitoh 		    pmreg + PCI_PMCSR);
   14023  1.329   msaitoh 		pcireg |= PCI_PMCSR_STATE_D3;
   14024  1.329   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   14025  1.329   msaitoh 		    pmreg + PCI_PMCSR, pcireg);
   14026  1.329   msaitoh 		delay(1000);
   14027  1.329   msaitoh 		pcireg &= ~PCI_PMCSR_STATE_D3;
   14028  1.329   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   14029  1.329   msaitoh 		    pmreg + PCI_PMCSR, pcireg);
   14030  1.329   msaitoh 
   14031  1.329   msaitoh 		reg = (INVM_AUTOLOAD << 4) | (nvmword << 16);
   14032  1.329   msaitoh 		CSR_WRITE(sc, WMREG_EEARBC_I210, reg);
   14033  1.332   msaitoh 
   14034  1.329   msaitoh 		/* Restore WUC register */
   14035  1.329   msaitoh 		CSR_WRITE(sc, WMREG_WUC, wuc);
   14036  1.329   msaitoh 	}
   14037  1.332   msaitoh 
   14038  1.329   msaitoh 	/* Restore MDICNFG setting */
   14039  1.329   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, mdicnfg);
   14040  1.329   msaitoh 	if (wa_done)
   14041  1.329   msaitoh 		aprint_verbose_dev(sc->sc_dev, "I210 workaround done\n");
   14042  1.329   msaitoh }
   14043  1.517   msaitoh 
   14044  1.517   msaitoh static void
   14045  1.517   msaitoh wm_legacy_irq_quirk_spt(struct wm_softc *sc)
   14046  1.517   msaitoh {
   14047  1.517   msaitoh 	uint32_t reg;
   14048  1.517   msaitoh 
   14049  1.517   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14050  1.517   msaitoh 		device_xname(sc->sc_dev), __func__));
   14051  1.517   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH_SPT);
   14052  1.517   msaitoh 
   14053  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM7);
   14054  1.517   msaitoh 	reg |= FEXTNVM7_SIDE_CLK_UNGATE;
   14055  1.517   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM7, reg);
   14056  1.517   msaitoh 
   14057  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM9);
   14058  1.517   msaitoh 	reg |= FEXTNVM9_IOSFSB_CLKGATE_DIS | FEXTNVM9_IOSFSB_CLKREQ_DIS;
   14059  1.517   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM9, reg);
   14060  1.517   msaitoh }
   14061