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if_wm.c revision 1.553
      1  1.553  knakahar /*	$NetBSD: if_wm.c,v 1.553 2018/01/15 04:09:58 knakahara Exp $	*/
      2    1.1   thorpej 
      3    1.1   thorpej /*
      4   1.69   thorpej  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
      5    1.1   thorpej  * All rights reserved.
      6    1.1   thorpej  *
      7    1.1   thorpej  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8    1.1   thorpej  *
      9    1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     10    1.1   thorpej  * modification, are permitted provided that the following conditions
     11    1.1   thorpej  * are met:
     12    1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     13    1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     14    1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     15    1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     16    1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     17    1.1   thorpej  * 3. All advertising materials mentioning features or use of this software
     18    1.1   thorpej  *    must display the following acknowledgement:
     19    1.1   thorpej  *	This product includes software developed for the NetBSD Project by
     20    1.1   thorpej  *	Wasabi Systems, Inc.
     21    1.1   thorpej  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22    1.1   thorpej  *    or promote products derived from this software without specific prior
     23    1.1   thorpej  *    written permission.
     24    1.1   thorpej  *
     25    1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26    1.1   thorpej  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27    1.1   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28    1.1   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29    1.1   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30    1.1   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31    1.1   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32    1.1   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33    1.1   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34    1.1   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35    1.1   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     36    1.1   thorpej  */
     37    1.1   thorpej 
     38  1.139    bouyer /*******************************************************************************
     39  1.139    bouyer 
     40  1.246  christos   Copyright (c) 2001-2005, Intel Corporation
     41  1.139    bouyer   All rights reserved.
     42  1.246  christos 
     43  1.246  christos   Redistribution and use in source and binary forms, with or without
     44  1.139    bouyer   modification, are permitted provided that the following conditions are met:
     45  1.246  christos 
     46  1.246  christos    1. Redistributions of source code must retain the above copyright notice,
     47  1.139    bouyer       this list of conditions and the following disclaimer.
     48  1.246  christos 
     49  1.246  christos    2. Redistributions in binary form must reproduce the above copyright
     50  1.246  christos       notice, this list of conditions and the following disclaimer in the
     51  1.139    bouyer       documentation and/or other materials provided with the distribution.
     52  1.246  christos 
     53  1.246  christos    3. Neither the name of the Intel Corporation nor the names of its
     54  1.246  christos       contributors may be used to endorse or promote products derived from
     55  1.139    bouyer       this software without specific prior written permission.
     56  1.246  christos 
     57  1.139    bouyer   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     58  1.246  christos   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     59  1.246  christos   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     60  1.246  christos   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     61  1.246  christos   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     62  1.246  christos   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     63  1.246  christos   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     64  1.246  christos   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     65  1.246  christos   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     66  1.139    bouyer   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     67  1.139    bouyer   POSSIBILITY OF SUCH DAMAGE.
     68  1.139    bouyer 
     69  1.139    bouyer *******************************************************************************/
     70    1.1   thorpej /*
     71   1.11   thorpej  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
     72    1.1   thorpej  *
     73    1.1   thorpej  * TODO (in order of importance):
     74    1.1   thorpej  *
     75  1.288   msaitoh  *	- Check XXX'ed comments
     76  1.407  knakahar  *	- TX Multi queue improvement (refine queue selection logic)
     77  1.467  knakahar  *	- Split header buffer for newer descriptors
     78  1.286   msaitoh  *	- EEE (Energy Efficiency Ethernet)
     79  1.286   msaitoh  *	- Virtual Function
     80  1.286   msaitoh  *	- Set LED correctly (based on contents in EEPROM)
     81   1.61   thorpej  *	- Rework how parameters are loaded from the EEPROM.
     82  1.371   msaitoh  *	- Image Unique ID
     83    1.1   thorpej  */
     84   1.38     lukem 
     85   1.38     lukem #include <sys/cdefs.h>
     86  1.553  knakahar __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.553 2018/01/15 04:09:58 knakahara Exp $");
     87  1.309     ozaki 
     88  1.309     ozaki #ifdef _KERNEL_OPT
     89  1.309     ozaki #include "opt_net_mpsafe.h"
     90  1.494  knakahar #include "opt_if_wm.h"
     91  1.309     ozaki #endif
     92    1.1   thorpej 
     93    1.1   thorpej #include <sys/param.h>
     94    1.1   thorpej #include <sys/systm.h>
     95   1.96     perry #include <sys/callout.h>
     96    1.1   thorpej #include <sys/mbuf.h>
     97    1.1   thorpej #include <sys/malloc.h>
     98  1.356  knakahar #include <sys/kmem.h>
     99    1.1   thorpej #include <sys/kernel.h>
    100    1.1   thorpej #include <sys/socket.h>
    101    1.1   thorpej #include <sys/ioctl.h>
    102    1.1   thorpej #include <sys/errno.h>
    103    1.1   thorpej #include <sys/device.h>
    104    1.1   thorpej #include <sys/queue.h>
    105   1.84   thorpej #include <sys/syslog.h>
    106  1.346  knakahar #include <sys/interrupt.h>
    107  1.403  knakahar #include <sys/cpu.h>
    108  1.403  knakahar #include <sys/pcq.h>
    109    1.1   thorpej 
    110  1.315  riastrad #include <sys/rndsource.h>
    111   1.21    itojun 
    112    1.1   thorpej #include <net/if.h>
    113   1.96     perry #include <net/if_dl.h>
    114    1.1   thorpej #include <net/if_media.h>
    115    1.1   thorpej #include <net/if_ether.h>
    116    1.1   thorpej 
    117    1.1   thorpej #include <net/bpf.h>
    118    1.1   thorpej 
    119    1.1   thorpej #include <netinet/in.h>			/* XXX for struct ip */
    120    1.1   thorpej #include <netinet/in_systm.h>		/* XXX for struct ip */
    121    1.1   thorpej #include <netinet/ip.h>			/* XXX for struct ip */
    122  1.131      yamt #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
    123   1.13   thorpej #include <netinet/tcp.h>		/* XXX for struct tcphdr */
    124    1.1   thorpej 
    125  1.147        ad #include <sys/bus.h>
    126  1.147        ad #include <sys/intr.h>
    127    1.1   thorpej #include <machine/endian.h>
    128    1.1   thorpej 
    129    1.1   thorpej #include <dev/mii/mii.h>
    130    1.1   thorpej #include <dev/mii/miivar.h>
    131  1.202   msaitoh #include <dev/mii/miidevs.h>
    132    1.1   thorpej #include <dev/mii/mii_bitbang.h>
    133  1.127    bouyer #include <dev/mii/ikphyreg.h>
    134  1.191   msaitoh #include <dev/mii/igphyreg.h>
    135  1.202   msaitoh #include <dev/mii/igphyvar.h>
    136  1.192   msaitoh #include <dev/mii/inbmphyreg.h>
    137  1.528   msaitoh #include <dev/mii/ihphyreg.h>
    138    1.1   thorpej 
    139    1.1   thorpej #include <dev/pci/pcireg.h>
    140    1.1   thorpej #include <dev/pci/pcivar.h>
    141    1.1   thorpej #include <dev/pci/pcidevs.h>
    142    1.1   thorpej 
    143    1.1   thorpej #include <dev/pci/if_wmreg.h>
    144  1.182   msaitoh #include <dev/pci/if_wmvar.h>
    145    1.1   thorpej 
    146    1.1   thorpej #ifdef WM_DEBUG
    147  1.420   msaitoh #define	WM_DEBUG_LINK		__BIT(0)
    148  1.420   msaitoh #define	WM_DEBUG_TX		__BIT(1)
    149  1.420   msaitoh #define	WM_DEBUG_RX		__BIT(2)
    150  1.420   msaitoh #define	WM_DEBUG_GMII		__BIT(3)
    151  1.420   msaitoh #define	WM_DEBUG_MANAGE		__BIT(4)
    152  1.420   msaitoh #define	WM_DEBUG_NVM		__BIT(5)
    153  1.420   msaitoh #define	WM_DEBUG_INIT		__BIT(6)
    154  1.420   msaitoh #define	WM_DEBUG_LOCK		__BIT(7)
    155  1.203   msaitoh int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
    156  1.420   msaitoh     | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT | WM_DEBUG_LOCK;
    157    1.1   thorpej 
    158    1.1   thorpej #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
    159    1.1   thorpej #else
    160    1.1   thorpej #define	DPRINTF(x, y)	/* nothing */
    161    1.1   thorpej #endif /* WM_DEBUG */
    162    1.1   thorpej 
    163  1.272     ozaki #ifdef NET_MPSAFE
    164  1.272     ozaki #define WM_MPSAFE	1
    165  1.492  knakahar #define CALLOUT_FLAGS	CALLOUT_MPSAFE
    166  1.492  knakahar #else
    167  1.492  knakahar #define CALLOUT_FLAGS	0
    168  1.272     ozaki #endif
    169  1.272     ozaki 
    170  1.335   msaitoh /*
    171  1.364  knakahar  * This device driver's max interrupt numbers.
    172  1.335   msaitoh  */
    173  1.405  knakahar #define WM_MAX_NQUEUEINTR	16
    174  1.405  knakahar #define WM_MAX_NINTR		(WM_MAX_NQUEUEINTR + 1)
    175  1.335   msaitoh 
    176  1.508  knakahar #ifndef WM_DISABLE_MSI
    177  1.508  knakahar #define	WM_DISABLE_MSI 0
    178  1.508  knakahar #endif
    179  1.508  knakahar #ifndef WM_DISABLE_MSIX
    180  1.508  knakahar #define	WM_DISABLE_MSIX 0
    181  1.508  knakahar #endif
    182  1.508  knakahar 
    183  1.508  knakahar int wm_disable_msi = WM_DISABLE_MSI;
    184  1.508  knakahar int wm_disable_msix = WM_DISABLE_MSIX;
    185  1.508  knakahar 
    186    1.1   thorpej /*
    187    1.2   thorpej  * Transmit descriptor list size.  Due to errata, we can only have
    188   1.75   thorpej  * 256 hardware descriptors in the ring on < 82544, but we use 4096
    189   1.75   thorpej  * on >= 82544.  We tell the upper layers that they can queue a lot
    190   1.75   thorpej  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
    191   1.75   thorpej  * of them at a time.
    192   1.75   thorpej  *
    193   1.75   thorpej  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
    194   1.75   thorpej  * chains containing many small mbufs have been observed in zero-copy
    195   1.75   thorpej  * situations with jumbo frames.
    196    1.1   thorpej  */
    197   1.75   thorpej #define	WM_NTXSEGS		256
    198    1.2   thorpej #define	WM_IFQUEUELEN		256
    199   1.74      tron #define	WM_TXQUEUELEN_MAX	64
    200   1.74      tron #define	WM_TXQUEUELEN_MAX_82547	16
    201  1.356  knakahar #define	WM_TXQUEUELEN(txq)	((txq)->txq_num)
    202  1.356  knakahar #define	WM_TXQUEUELEN_MASK(txq)	(WM_TXQUEUELEN(txq) - 1)
    203  1.356  knakahar #define	WM_TXQUEUE_GC(txq)	(WM_TXQUEUELEN(txq) / 8)
    204   1.75   thorpej #define	WM_NTXDESC_82542	256
    205   1.75   thorpej #define	WM_NTXDESC_82544	4096
    206  1.356  knakahar #define	WM_NTXDESC(txq)		((txq)->txq_ndesc)
    207  1.356  knakahar #define	WM_NTXDESC_MASK(txq)	(WM_NTXDESC(txq) - 1)
    208  1.398  knakahar #define	WM_TXDESCS_SIZE(txq)	(WM_NTXDESC(txq) * (txq)->txq_descsize)
    209  1.356  knakahar #define	WM_NEXTTX(txq, x)	(((x) + 1) & WM_NTXDESC_MASK(txq))
    210  1.356  knakahar #define	WM_NEXTTXS(txq, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(txq))
    211    1.1   thorpej 
    212  1.269       tls #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
    213   1.82   thorpej 
    214  1.403  knakahar #define	WM_TXINTERQSIZE		256
    215  1.403  knakahar 
    216    1.1   thorpej /*
    217    1.1   thorpej  * Receive descriptor list size.  We have one Rx buffer for normal
    218    1.1   thorpej  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
    219   1.10   thorpej  * packet.  We allocate 256 receive descriptors, each with a 2k
    220   1.10   thorpej  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
    221    1.1   thorpej  */
    222   1.10   thorpej #define	WM_NRXDESC		256
    223    1.1   thorpej #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
    224    1.1   thorpej #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
    225    1.1   thorpej #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
    226    1.1   thorpej 
    227  1.494  knakahar #ifndef WM_RX_PROCESS_LIMIT_DEFAULT
    228  1.493  knakahar #define	WM_RX_PROCESS_LIMIT_DEFAULT		100U
    229  1.494  knakahar #endif
    230  1.494  knakahar #ifndef WM_RX_INTR_PROCESS_LIMIT_DEFAULT
    231  1.493  knakahar #define	WM_RX_INTR_PROCESS_LIMIT_DEFAULT	0U
    232  1.494  knakahar #endif
    233  1.493  knakahar 
    234  1.354  knakahar typedef union txdescs {
    235  1.354  knakahar 	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
    236  1.354  knakahar 	nq_txdesc_t      sctxu_nq_txdescs[WM_NTXDESC_82544];
    237  1.354  knakahar } txdescs_t;
    238    1.1   thorpej 
    239  1.466  knakahar typedef union rxdescs {
    240  1.466  knakahar 	wiseman_rxdesc_t sctxu_rxdescs[WM_NRXDESC];
    241  1.466  knakahar 	ext_rxdesc_t      sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
    242  1.466  knakahar 	nq_rxdesc_t      sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
    243  1.466  knakahar } rxdescs_t;
    244  1.466  knakahar 
    245  1.398  knakahar #define	WM_CDTXOFF(txq, x)	((txq)->txq_descsize * (x))
    246  1.466  knakahar #define	WM_CDRXOFF(rxq, x)	((rxq)->rxq_descsize * (x))
    247    1.1   thorpej 
    248    1.1   thorpej /*
    249    1.1   thorpej  * Software state for transmit jobs.
    250    1.1   thorpej  */
    251    1.1   thorpej struct wm_txsoft {
    252    1.1   thorpej 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
    253    1.1   thorpej 	bus_dmamap_t txs_dmamap;	/* our DMA map */
    254    1.1   thorpej 	int txs_firstdesc;		/* first descriptor in packet */
    255    1.1   thorpej 	int txs_lastdesc;		/* last descriptor in packet */
    256    1.4   thorpej 	int txs_ndesc;			/* # of descriptors used */
    257    1.1   thorpej };
    258    1.1   thorpej 
    259    1.1   thorpej /*
    260    1.1   thorpej  * Software state for receive buffers.  Each descriptor gets a
    261    1.1   thorpej  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
    262    1.1   thorpej  * more than one buffer, we chain them together.
    263    1.1   thorpej  */
    264    1.1   thorpej struct wm_rxsoft {
    265    1.1   thorpej 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
    266    1.1   thorpej 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
    267    1.1   thorpej };
    268    1.1   thorpej 
    269  1.173   msaitoh #define WM_LINKUP_TIMEOUT	50
    270  1.173   msaitoh 
    271  1.199   msaitoh static uint16_t swfwphysem[] = {
    272  1.199   msaitoh 	SWFW_PHY0_SM,
    273  1.199   msaitoh 	SWFW_PHY1_SM,
    274  1.199   msaitoh 	SWFW_PHY2_SM,
    275  1.199   msaitoh 	SWFW_PHY3_SM
    276  1.199   msaitoh };
    277  1.199   msaitoh 
    278  1.320   msaitoh static const uint32_t wm_82580_rxpbs_table[] = {
    279  1.320   msaitoh 	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
    280  1.320   msaitoh };
    281  1.320   msaitoh 
    282  1.356  knakahar struct wm_softc;
    283  1.356  knakahar 
    284  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    285  1.417  knakahar #define WM_Q_EVCNT_DEFINE(qname, evname)				\
    286  1.417  knakahar 	char qname##_##evname##_evcnt_name[sizeof("qname##XX##evname")]; \
    287  1.417  knakahar 	struct evcnt qname##_ev_##evname;
    288  1.417  knakahar 
    289  1.417  knakahar #define WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, evtype)	\
    290  1.417  knakahar 	do{								\
    291  1.417  knakahar 		snprintf((q)->qname##_##evname##_evcnt_name,		\
    292  1.417  knakahar 		    sizeof((q)->qname##_##evname##_evcnt_name),		\
    293  1.417  knakahar 		    "%s%02d%s", #qname, (qnum), #evname);		\
    294  1.417  knakahar 		evcnt_attach_dynamic(&(q)->qname##_ev_##evname,		\
    295  1.417  knakahar 		    (evtype), NULL, (xname),				\
    296  1.417  knakahar 		    (q)->qname##_##evname##_evcnt_name);		\
    297  1.417  knakahar 	}while(0)
    298  1.417  knakahar 
    299  1.417  knakahar #define WM_Q_MISC_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
    300  1.417  knakahar 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_MISC)
    301  1.417  knakahar 
    302  1.417  knakahar #define WM_Q_INTR_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
    303  1.417  knakahar 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_INTR)
    304  1.477  knakahar 
    305  1.477  knakahar #define WM_Q_EVCNT_DETACH(qname, evname, q, qnum)	\
    306  1.477  knakahar 	evcnt_detach(&(q)->qname##_ev_##evname);
    307  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
    308  1.417  knakahar 
    309  1.356  knakahar struct wm_txqueue {
    310  1.357  knakahar 	kmutex_t *txq_lock;		/* lock for tx operations */
    311  1.356  knakahar 
    312  1.405  knakahar 	struct wm_softc *txq_sc;	/* shortcut (skip struct wm_queue) */
    313  1.364  knakahar 
    314  1.356  knakahar 	/* Software state for the transmit descriptors. */
    315  1.356  knakahar 	int txq_num;			/* must be a power of two */
    316  1.356  knakahar 	struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
    317  1.356  knakahar 
    318  1.356  knakahar 	/* TX control data structures. */
    319  1.356  knakahar 	int txq_ndesc;			/* must be a power of two */
    320  1.398  knakahar 	size_t txq_descsize;		/* a tx descriptor size */
    321  1.356  knakahar 	txdescs_t *txq_descs_u;
    322  1.356  knakahar         bus_dmamap_t txq_desc_dmamap;	/* control data DMA map */
    323  1.356  knakahar 	bus_dma_segment_t txq_desc_seg;	/* control data segment */
    324  1.356  knakahar 	int txq_desc_rseg;		/* real number of control segment */
    325  1.356  knakahar #define	txq_desc_dma	txq_desc_dmamap->dm_segs[0].ds_addr
    326  1.356  knakahar #define	txq_descs	txq_descs_u->sctxu_txdescs
    327  1.356  knakahar #define	txq_nq_descs	txq_descs_u->sctxu_nq_txdescs
    328  1.356  knakahar 
    329  1.356  knakahar 	bus_addr_t txq_tdt_reg;		/* offset of TDT register */
    330  1.356  knakahar 
    331  1.356  knakahar 	int txq_free;			/* number of free Tx descriptors */
    332  1.356  knakahar 	int txq_next;			/* next ready Tx descriptor */
    333  1.356  knakahar 
    334  1.356  knakahar 	int txq_sfree;			/* number of free Tx jobs */
    335  1.356  knakahar 	int txq_snext;			/* next free Tx job */
    336  1.356  knakahar 	int txq_sdirty;			/* dirty Tx jobs */
    337  1.356  knakahar 
    338  1.356  knakahar 	/* These 4 variables are used only on the 82547. */
    339  1.356  knakahar 	int txq_fifo_size;		/* Tx FIFO size */
    340  1.356  knakahar 	int txq_fifo_head;		/* current head of FIFO */
    341  1.356  knakahar 	uint32_t txq_fifo_addr;		/* internal address of start of FIFO */
    342  1.356  knakahar 	int txq_fifo_stall;		/* Tx FIFO is stalled */
    343  1.356  knakahar 
    344  1.400  knakahar 	/*
    345  1.403  knakahar 	 * When ncpu > number of Tx queues, a Tx queue is shared by multiple
    346  1.403  knakahar 	 * CPUs. This queue intermediate them without block.
    347  1.403  knakahar 	 */
    348  1.403  knakahar 	pcq_t *txq_interq;
    349  1.403  knakahar 
    350  1.403  knakahar 	/*
    351  1.400  knakahar 	 * NEWQUEUE devices must use not ifp->if_flags but txq->txq_flags
    352  1.400  knakahar 	 * to manage Tx H/W queue's busy flag.
    353  1.400  knakahar 	 */
    354  1.400  knakahar 	int txq_flags;			/* flags for H/W queue, see below */
    355  1.401  knakahar #define	WM_TXQ_NO_SPACE	0x1
    356  1.400  knakahar 
    357  1.429  knakahar 	bool txq_stopping;
    358  1.429  knakahar 
    359  1.495  knakahar 	uint32_t txq_packets;		/* for AIM */
    360  1.495  knakahar 	uint32_t txq_bytes;		/* for AIM */
    361  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    362  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txsstall)	/* Tx stalled due to no txs */
    363  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdstall)	/* Tx stalled due to no txd */
    364  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txfifo_stall)	/* Tx FIFO stalls (82547) */
    365  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdw)		/* Tx descriptor interrupts */
    366  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txqe)		/* Tx queue empty interrupts */
    367  1.417  knakahar 						/* XXX not used? */
    368  1.417  knakahar 
    369  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txipsum)		/* IP checksums comp. out-bound */
    370  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq,txtusum)		/* TCP/UDP cksums comp. out-bound */
    371  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtusum6)	/* TCP/UDP v6 cksums comp. out-bound */
    372  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtso)		/* TCP seg offload out-bound (IPv4) */
    373  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtso6)		/* TCP seg offload out-bound (IPv6) */
    374  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtsopain)	/* painful header manip. for TSO */
    375  1.417  knakahar 
    376  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdrop)		/* Tx packets dropped(too many segs) */
    377  1.417  knakahar 
    378  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, tu)		/* Tx underrun */
    379  1.417  knakahar 
    380  1.417  knakahar 	char txq_txseg_evcnt_names[WM_NTXSEGS][sizeof("txqXXtxsegXXX")];
    381  1.417  knakahar 	struct evcnt txq_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
    382  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
    383  1.356  knakahar };
    384  1.356  knakahar 
    385  1.356  knakahar struct wm_rxqueue {
    386  1.357  knakahar 	kmutex_t *rxq_lock;		/* lock for rx operations */
    387  1.356  knakahar 
    388  1.405  knakahar 	struct wm_softc *rxq_sc;	/* shortcut (skip struct wm_queue) */
    389  1.364  knakahar 
    390  1.356  knakahar 	/* Software state for the receive descriptors. */
    391  1.466  knakahar 	struct wm_rxsoft rxq_soft[WM_NRXDESC];
    392  1.356  knakahar 
    393  1.356  knakahar 	/* RX control data structures. */
    394  1.466  knakahar 	int rxq_ndesc;			/* must be a power of two */
    395  1.466  knakahar 	size_t rxq_descsize;		/* a rx descriptor size */
    396  1.466  knakahar 	rxdescs_t *rxq_descs_u;
    397  1.356  knakahar 	bus_dmamap_t rxq_desc_dmamap;	/* control data DMA map */
    398  1.356  knakahar 	bus_dma_segment_t rxq_desc_seg;	/* control data segment */
    399  1.356  knakahar 	int rxq_desc_rseg;		/* real number of control segment */
    400  1.356  knakahar #define	rxq_desc_dma	rxq_desc_dmamap->dm_segs[0].ds_addr
    401  1.466  knakahar #define	rxq_descs	rxq_descs_u->sctxu_rxdescs
    402  1.466  knakahar #define	rxq_ext_descs	rxq_descs_u->sctxu_ext_rxdescs
    403  1.466  knakahar #define	rxq_nq_descs	rxq_descs_u->sctxu_nq_rxdescs
    404  1.356  knakahar 
    405  1.356  knakahar 	bus_addr_t rxq_rdt_reg;		/* offset of RDT register */
    406  1.356  knakahar 
    407  1.388   msaitoh 	int rxq_ptr;			/* next ready Rx desc/queue ent */
    408  1.356  knakahar 	int rxq_discard;
    409  1.356  knakahar 	int rxq_len;
    410  1.356  knakahar 	struct mbuf *rxq_head;
    411  1.356  knakahar 	struct mbuf *rxq_tail;
    412  1.356  knakahar 	struct mbuf **rxq_tailp;
    413  1.356  knakahar 
    414  1.429  knakahar 	bool rxq_stopping;
    415  1.429  knakahar 
    416  1.495  knakahar 	uint32_t rxq_packets;		/* for AIM */
    417  1.495  knakahar 	uint32_t rxq_bytes;		/* for AIM */
    418  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    419  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxintr);		/* Rx interrupts */
    420  1.417  knakahar 
    421  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxipsum);	/* IP checksums checked in-bound */
    422  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxtusum);	/* TCP/UDP cksums checked in-bound */
    423  1.417  knakahar #endif
    424  1.356  knakahar };
    425  1.356  knakahar 
    426  1.405  knakahar struct wm_queue {
    427  1.405  knakahar 	int wmq_id;			/* index of transmit and receive queues */
    428  1.405  knakahar 	int wmq_intr_idx;		/* index of MSI-X tables */
    429  1.405  knakahar 
    430  1.490  knakahar 	uint32_t wmq_itr;		/* interrupt interval per queue. */
    431  1.495  knakahar 	bool wmq_set_itr;
    432  1.490  knakahar 
    433  1.405  knakahar 	struct wm_txqueue wmq_txq;
    434  1.405  knakahar 	struct wm_rxqueue wmq_rxq;
    435  1.484  knakahar 
    436  1.484  knakahar 	void *wmq_si;
    437  1.405  knakahar };
    438  1.405  knakahar 
    439  1.424   msaitoh struct wm_phyop {
    440  1.424   msaitoh 	int (*acquire)(struct wm_softc *);
    441  1.424   msaitoh 	void (*release)(struct wm_softc *);
    442  1.447   msaitoh 	int reset_delay_us;
    443  1.424   msaitoh };
    444  1.424   msaitoh 
    445  1.530   msaitoh struct wm_nvmop {
    446  1.530   msaitoh 	int (*acquire)(struct wm_softc *);
    447  1.530   msaitoh 	void (*release)(struct wm_softc *);
    448  1.530   msaitoh 	int (*read)(struct wm_softc *, int, int, uint16_t *);
    449  1.530   msaitoh };
    450  1.530   msaitoh 
    451    1.1   thorpej /*
    452    1.1   thorpej  * Software state per device.
    453    1.1   thorpej  */
    454    1.1   thorpej struct wm_softc {
    455  1.160  christos 	device_t sc_dev;		/* generic device information */
    456    1.1   thorpej 	bus_space_tag_t sc_st;		/* bus space tag */
    457    1.1   thorpej 	bus_space_handle_t sc_sh;	/* bus space handle */
    458  1.204   msaitoh 	bus_size_t sc_ss;		/* bus space size */
    459   1.53   thorpej 	bus_space_tag_t sc_iot;		/* I/O space tag */
    460   1.53   thorpej 	bus_space_handle_t sc_ioh;	/* I/O space handle */
    461  1.212  jakllsch 	bus_size_t sc_ios;		/* I/O space size */
    462  1.139    bouyer 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
    463  1.139    bouyer 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
    464  1.336   msaitoh 	bus_size_t sc_flashs;		/* flash registers space size */
    465  1.392   msaitoh 	off_t sc_flashreg_offset;	/*
    466  1.392   msaitoh 					 * offset to flash registers from
    467  1.392   msaitoh 					 * start of BAR
    468  1.392   msaitoh 					 */
    469    1.1   thorpej 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
    470  1.199   msaitoh 
    471    1.1   thorpej 	struct ethercom sc_ethercom;	/* ethernet common data */
    472  1.199   msaitoh 	struct mii_data sc_mii;		/* MII/media information */
    473  1.199   msaitoh 
    474  1.123  jmcneill 	pci_chipset_tag_t sc_pc;
    475  1.123  jmcneill 	pcitag_t sc_pcitag;
    476  1.199   msaitoh 	int sc_bus_speed;		/* PCI/PCIX bus speed */
    477  1.281   msaitoh 	int sc_pcixe_capoff;		/* PCI[Xe] capability reg offset */
    478    1.1   thorpej 
    479  1.304   msaitoh 	uint16_t sc_pcidevid;		/* PCI device ID */
    480  1.192   msaitoh 	wm_chip_type sc_type;		/* MAC type */
    481  1.192   msaitoh 	int sc_rev;			/* MAC revision */
    482  1.192   msaitoh 	wm_phy_type sc_phytype;		/* PHY type */
    483  1.292   msaitoh 	uint32_t sc_mediatype;		/* Media type (Copper, Fiber, SERDES)*/
    484  1.311   msaitoh #define	WM_MEDIATYPE_UNKNOWN		0x00
    485  1.311   msaitoh #define	WM_MEDIATYPE_FIBER		0x01
    486  1.311   msaitoh #define	WM_MEDIATYPE_COPPER		0x02
    487  1.311   msaitoh #define	WM_MEDIATYPE_SERDES		0x03 /* Internal SERDES */
    488  1.199   msaitoh 	int sc_funcid;			/* unit number of the chip (0 to 3) */
    489    1.1   thorpej 	int sc_flags;			/* flags; see below */
    490  1.179   msaitoh 	int sc_if_flags;		/* last if_flags */
    491   1.71   thorpej 	int sc_flowflags;		/* 802.3x flow control flags */
    492  1.199   msaitoh 	int sc_align_tweak;
    493    1.1   thorpej 
    494  1.335   msaitoh 	void *sc_ihs[WM_MAX_NINTR];	/*
    495  1.335   msaitoh 					 * interrupt cookie.
    496  1.507  knakahar 					 * - legacy and msi use sc_ihs[0] only
    497  1.507  knakahar 					 * - msix use sc_ihs[0] to sc_ihs[nintrs-1]
    498  1.507  knakahar 					 */
    499  1.507  knakahar 	pci_intr_handle_t *sc_intrs;	/*
    500  1.507  knakahar 					 * legacy and msi use sc_intrs[0] only
    501  1.507  knakahar 					 * msix use sc_intrs[0] to sc_ihs[nintrs-1]
    502  1.335   msaitoh 					 */
    503  1.335   msaitoh 	int sc_nintrs;			/* number of interrupts */
    504  1.335   msaitoh 
    505  1.364  knakahar 	int sc_link_intr_idx;		/* index of MSI-X tables */
    506  1.364  knakahar 
    507  1.199   msaitoh 	callout_t sc_tick_ch;		/* tick callout */
    508  1.429  knakahar 	bool sc_core_stopping;
    509    1.1   thorpej 
    510  1.328   msaitoh 	int sc_nvm_ver_major;
    511  1.328   msaitoh 	int sc_nvm_ver_minor;
    512  1.350   msaitoh 	int sc_nvm_ver_build;
    513  1.294   msaitoh 	int sc_nvm_addrbits;		/* NVM address bits */
    514  1.328   msaitoh 	unsigned int sc_nvm_wordsize;	/* NVM word size */
    515  1.199   msaitoh 	int sc_ich8_flash_base;
    516  1.199   msaitoh 	int sc_ich8_flash_bank_size;
    517  1.199   msaitoh 	int sc_nvm_k1_enabled;
    518   1.42   thorpej 
    519  1.405  knakahar 	int sc_nqueues;
    520  1.405  knakahar 	struct wm_queue *sc_queue;
    521  1.493  knakahar 	u_int sc_rx_process_limit;	/* Rx processing repeat limit in softint */
    522  1.493  knakahar 	u_int sc_rx_intr_process_limit;	/* Rx processing repeat limit in H/W intr */
    523    1.1   thorpej 
    524  1.404  knakahar 	int sc_affinity_offset;
    525  1.404  knakahar 
    526    1.1   thorpej #ifdef WM_EVENT_COUNTERS
    527    1.1   thorpej 	/* Event counters. */
    528    1.1   thorpej 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
    529    1.1   thorpej 
    530  1.417  knakahar         /* WM_T_82542_2_1 only */
    531   1.71   thorpej 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
    532   1.71   thorpej 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
    533   1.71   thorpej 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
    534   1.71   thorpej 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
    535   1.71   thorpej 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
    536    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
    537    1.1   thorpej 
    538  1.356  knakahar 	/* This variable are used only on the 82547. */
    539  1.142        ad 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
    540   1.78   thorpej 
    541    1.1   thorpej 	uint32_t sc_ctrl;		/* prototype CTRL register */
    542    1.1   thorpej #if 0
    543    1.1   thorpej 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
    544    1.1   thorpej #endif
    545    1.1   thorpej 	uint32_t sc_icr;		/* prototype interrupt bits */
    546  1.490  knakahar 	uint32_t sc_itr_init;		/* prototype intr throttling reg */
    547    1.1   thorpej 	uint32_t sc_tctl;		/* prototype TCTL register */
    548    1.1   thorpej 	uint32_t sc_rctl;		/* prototype RCTL register */
    549    1.1   thorpej 	uint32_t sc_txcw;		/* prototype TXCW register */
    550    1.1   thorpej 	uint32_t sc_tipg;		/* prototype TIPG register */
    551   1.71   thorpej 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
    552   1.78   thorpej 	uint32_t sc_pba;		/* prototype PBA register */
    553    1.1   thorpej 
    554    1.1   thorpej 	int sc_tbi_linkup;		/* TBI link status */
    555  1.325   msaitoh 	int sc_tbi_serdes_anegticks;	/* autonegotiation ticks */
    556  1.325   msaitoh 	int sc_tbi_serdes_ticks;	/* tbi ticks */
    557    1.1   thorpej 
    558    1.1   thorpej 	int sc_mchash_type;		/* multicast filter offset */
    559   1.21    itojun 
    560  1.224       tls 	krndsource_t rnd_source;	/* random source */
    561  1.272     ozaki 
    562  1.424   msaitoh 	struct if_percpuq *sc_ipq;	/* softint-based input queues */
    563  1.424   msaitoh 
    564  1.357  knakahar 	kmutex_t *sc_core_lock;		/* lock for softc operations */
    565  1.424   msaitoh 	kmutex_t *sc_ich_phymtx;	/*
    566  1.424   msaitoh 					 * 82574/82583/ICH/PCH specific PHY
    567  1.424   msaitoh 					 * mutex. For 82574/82583, the mutex
    568  1.424   msaitoh 					 * is used for both PHY and NVM.
    569  1.424   msaitoh 					 */
    570  1.423   msaitoh 	kmutex_t *sc_ich_nvmmtx;	/* ICH/PCH specific NVM mutex */
    571  1.391     ozaki 
    572  1.424   msaitoh 	struct wm_phyop phy;
    573  1.530   msaitoh 	struct wm_nvmop nvm;
    574    1.1   thorpej };
    575    1.1   thorpej 
    576  1.357  knakahar #define WM_CORE_LOCK(_sc)	if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
    577  1.357  knakahar #define WM_CORE_UNLOCK(_sc)	if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
    578  1.357  knakahar #define WM_CORE_LOCKED(_sc)	(!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
    579  1.272     ozaki 
    580  1.356  knakahar #define	WM_RXCHAIN_RESET(rxq)						\
    581    1.1   thorpej do {									\
    582  1.356  knakahar 	(rxq)->rxq_tailp = &(rxq)->rxq_head;				\
    583  1.356  knakahar 	*(rxq)->rxq_tailp = NULL;					\
    584  1.356  knakahar 	(rxq)->rxq_len = 0;						\
    585    1.1   thorpej } while (/*CONSTCOND*/0)
    586    1.1   thorpej 
    587  1.356  knakahar #define	WM_RXCHAIN_LINK(rxq, m)						\
    588    1.1   thorpej do {									\
    589  1.356  knakahar 	*(rxq)->rxq_tailp = (rxq)->rxq_tail = (m);			\
    590  1.356  knakahar 	(rxq)->rxq_tailp = &(m)->m_next;				\
    591    1.1   thorpej } while (/*CONSTCOND*/0)
    592    1.1   thorpej 
    593    1.1   thorpej #ifdef WM_EVENT_COUNTERS
    594    1.1   thorpej #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
    595   1.71   thorpej #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
    596  1.417  knakahar 
    597  1.417  knakahar #define WM_Q_EVCNT_INCR(qname, evname)			\
    598  1.417  knakahar 	WM_EVCNT_INCR(&(qname)->qname##_ev_##evname)
    599  1.417  knakahar #define WM_Q_EVCNT_ADD(qname, evname, val)		\
    600  1.417  knakahar 	WM_EVCNT_ADD(&(qname)->qname##_ev_##evname, (val))
    601  1.417  knakahar #else /* !WM_EVENT_COUNTERS */
    602    1.1   thorpej #define	WM_EVCNT_INCR(ev)	/* nothing */
    603   1.71   thorpej #define	WM_EVCNT_ADD(ev, val)	/* nothing */
    604  1.417  knakahar 
    605  1.417  knakahar #define WM_Q_EVCNT_INCR(qname, evname)		/* nothing */
    606  1.417  knakahar #define WM_Q_EVCNT_ADD(qname, evname, val)	/* nothing */
    607  1.417  knakahar #endif /* !WM_EVENT_COUNTERS */
    608    1.1   thorpej 
    609    1.1   thorpej #define	CSR_READ(sc, reg)						\
    610    1.1   thorpej 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
    611    1.1   thorpej #define	CSR_WRITE(sc, reg, val)						\
    612    1.1   thorpej 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
    613   1.78   thorpej #define	CSR_WRITE_FLUSH(sc)						\
    614   1.78   thorpej 	(void) CSR_READ((sc), WMREG_STATUS)
    615    1.1   thorpej 
    616  1.392   msaitoh #define ICH8_FLASH_READ32(sc, reg)					\
    617  1.392   msaitoh 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh,		\
    618  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset)
    619  1.392   msaitoh #define ICH8_FLASH_WRITE32(sc, reg, data)				\
    620  1.392   msaitoh 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh,		\
    621  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset, (data))
    622  1.392   msaitoh 
    623  1.392   msaitoh #define ICH8_FLASH_READ16(sc, reg)					\
    624  1.392   msaitoh 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh,		\
    625  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset)
    626  1.392   msaitoh #define ICH8_FLASH_WRITE16(sc, reg, data)				\
    627  1.392   msaitoh 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh,		\
    628  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset, (data))
    629  1.139    bouyer 
    630  1.398  knakahar #define	WM_CDTXADDR(txq, x)	((txq)->txq_desc_dma + WM_CDTXOFF((txq), (x)))
    631  1.466  knakahar #define	WM_CDRXADDR(rxq, x)	((rxq)->rxq_desc_dma + WM_CDRXOFF((rxq), (x)))
    632    1.1   thorpej 
    633  1.356  knakahar #define	WM_CDTXADDR_LO(txq, x)	(WM_CDTXADDR((txq), (x)) & 0xffffffffU)
    634  1.356  knakahar #define	WM_CDTXADDR_HI(txq, x)						\
    635   1.69   thorpej 	(sizeof(bus_addr_t) == 8 ?					\
    636  1.356  knakahar 	 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
    637   1.69   thorpej 
    638  1.356  knakahar #define	WM_CDRXADDR_LO(rxq, x)	(WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
    639  1.356  knakahar #define	WM_CDRXADDR_HI(rxq, x)						\
    640   1.69   thorpej 	(sizeof(bus_addr_t) == 8 ?					\
    641  1.356  knakahar 	 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
    642   1.69   thorpej 
    643  1.280   msaitoh /*
    644  1.280   msaitoh  * Register read/write functions.
    645  1.280   msaitoh  * Other than CSR_{READ|WRITE}().
    646  1.280   msaitoh  */
    647  1.280   msaitoh #if 0
    648  1.280   msaitoh static inline uint32_t wm_io_read(struct wm_softc *, int);
    649  1.280   msaitoh #endif
    650  1.280   msaitoh static inline void wm_io_write(struct wm_softc *, int, uint32_t);
    651  1.280   msaitoh static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
    652  1.280   msaitoh 	uint32_t, uint32_t);
    653  1.280   msaitoh static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
    654  1.280   msaitoh 
    655  1.280   msaitoh /*
    656  1.352  knakahar  * Descriptor sync/init functions.
    657  1.352  knakahar  */
    658  1.362  knakahar static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int);
    659  1.362  knakahar static inline void wm_cdrxsync(struct wm_rxqueue *, int, int);
    660  1.362  knakahar static inline void wm_init_rxdesc(struct wm_rxqueue *, int);
    661  1.352  knakahar 
    662  1.352  knakahar /*
    663  1.280   msaitoh  * Device driver interface functions and commonly used functions.
    664  1.280   msaitoh  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
    665  1.280   msaitoh  */
    666  1.280   msaitoh static const struct wm_product *wm_lookup(const struct pci_attach_args *);
    667  1.280   msaitoh static int	wm_match(device_t, cfdata_t, void *);
    668  1.280   msaitoh static void	wm_attach(device_t, device_t, void *);
    669  1.280   msaitoh static int	wm_detach(device_t, int);
    670  1.280   msaitoh static bool	wm_suspend(device_t, const pmf_qual_t *);
    671  1.280   msaitoh static bool	wm_resume(device_t, const pmf_qual_t *);
    672   1.47   thorpej static void	wm_watchdog(struct ifnet *);
    673  1.403  knakahar static void	wm_watchdog_txq(struct ifnet *, struct wm_txqueue *);
    674  1.280   msaitoh static void	wm_tick(void *);
    675  1.213   msaitoh static int	wm_ifflags_cb(struct ethercom *);
    676  1.135  christos static int	wm_ioctl(struct ifnet *, u_long, void *);
    677  1.280   msaitoh /* MAC address related */
    678  1.306   msaitoh static uint16_t	wm_check_alt_mac_addr(struct wm_softc *);
    679  1.280   msaitoh static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
    680  1.280   msaitoh static void	wm_set_ral(struct wm_softc *, const uint8_t *, int);
    681  1.280   msaitoh static uint32_t	wm_mchash(struct wm_softc *, const uint8_t *);
    682  1.280   msaitoh static void	wm_set_filter(struct wm_softc *);
    683  1.280   msaitoh /* Reset and init related */
    684  1.280   msaitoh static void	wm_set_vlan(struct wm_softc *);
    685  1.280   msaitoh static void	wm_set_pcie_completion_timeout(struct wm_softc *);
    686  1.280   msaitoh static void	wm_get_auto_rd_done(struct wm_softc *);
    687  1.280   msaitoh static void	wm_lan_init_done(struct wm_softc *);
    688  1.280   msaitoh static void	wm_get_cfg_done(struct wm_softc *);
    689  1.517   msaitoh static void	wm_phy_post_reset(struct wm_softc *);
    690  1.528   msaitoh static void	wm_write_smbus_addr(struct wm_softc *);
    691  1.523   msaitoh static void	wm_init_lcd_from_nvm(struct wm_softc *);
    692  1.312   msaitoh static void	wm_initialize_hardware_bits(struct wm_softc *);
    693  1.320   msaitoh static uint32_t	wm_rxpbs_adjust_82580(uint32_t);
    694  1.447   msaitoh static void	wm_reset_phy(struct wm_softc *);
    695  1.443   msaitoh static void	wm_flush_desc_rings(struct wm_softc *);
    696  1.280   msaitoh static void	wm_reset(struct wm_softc *);
    697  1.362  knakahar static int	wm_add_rxbuf(struct wm_rxqueue *, int);
    698  1.362  knakahar static void	wm_rxdrain(struct wm_rxqueue *);
    699  1.372  knakahar static void	wm_rss_getkey(uint8_t *);
    700  1.365  knakahar static void	wm_init_rss(struct wm_softc *);
    701  1.371   msaitoh static void	wm_adjust_qnum(struct wm_softc *, int);
    702  1.502  knakahar static inline bool	wm_is_using_msix(struct wm_softc *);
    703  1.502  knakahar static inline bool	wm_is_using_multiqueue(struct wm_softc *);
    704  1.501  knakahar static int	wm_softint_establish(struct wm_softc *, int, int);
    705  1.371   msaitoh static int	wm_setup_legacy(struct wm_softc *);
    706  1.371   msaitoh static int	wm_setup_msix(struct wm_softc *);
    707   1.47   thorpej static int	wm_init(struct ifnet *);
    708  1.272     ozaki static int	wm_init_locked(struct ifnet *);
    709  1.537  knakahar static void	wm_unset_stopping_flags(struct wm_softc *);
    710  1.537  knakahar static void	wm_set_stopping_flags(struct wm_softc *);
    711   1.47   thorpej static void	wm_stop(struct ifnet *, int);
    712  1.272     ozaki static void	wm_stop_locked(struct ifnet *, int);
    713  1.280   msaitoh static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
    714  1.280   msaitoh static void	wm_82547_txfifo_stall(void *);
    715  1.280   msaitoh static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
    716  1.491  knakahar static void	wm_itrs_writereg(struct wm_softc *, struct wm_queue *);
    717  1.353  knakahar /* DMA related */
    718  1.362  knakahar static int	wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *);
    719  1.362  knakahar static void	wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *);
    720  1.362  knakahar static void	wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *);
    721  1.405  knakahar static void	wm_init_tx_regs(struct wm_softc *, struct wm_queue *,
    722  1.405  knakahar     struct wm_txqueue *);
    723  1.362  knakahar static int	wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *);
    724  1.362  knakahar static void	wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *);
    725  1.405  knakahar static void	wm_init_rx_regs(struct wm_softc *, struct wm_queue *,
    726  1.405  knakahar     struct wm_rxqueue *);
    727  1.362  knakahar static int	wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    728  1.362  knakahar static void	wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    729  1.362  knakahar static void	wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    730  1.362  knakahar static int	wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    731  1.362  knakahar static void	wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    732  1.362  knakahar static int	wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    733  1.405  knakahar static void	wm_init_tx_queue(struct wm_softc *, struct wm_queue *,
    734  1.405  knakahar     struct wm_txqueue *);
    735  1.405  knakahar static int	wm_init_rx_queue(struct wm_softc *, struct wm_queue *,
    736  1.405  knakahar     struct wm_rxqueue *);
    737  1.353  knakahar static int	wm_alloc_txrx_queues(struct wm_softc *);
    738  1.353  knakahar static void	wm_free_txrx_queues(struct wm_softc *);
    739  1.355  knakahar static int	wm_init_txrx_queues(struct wm_softc *);
    740  1.280   msaitoh /* Start */
    741  1.498  knakahar static int	wm_tx_offload(struct wm_softc *, struct wm_txqueue *,
    742  1.498  knakahar     struct wm_txsoft *, uint32_t *, uint8_t *);
    743  1.454  knakahar static inline int	wm_select_txqueue(struct ifnet *, struct mbuf *);
    744  1.280   msaitoh static void	wm_start(struct ifnet *);
    745  1.280   msaitoh static void	wm_start_locked(struct ifnet *);
    746  1.454  knakahar static int	wm_transmit(struct ifnet *, struct mbuf *);
    747  1.454  knakahar static void	wm_transmit_locked(struct ifnet *, struct wm_txqueue *);
    748  1.454  knakahar static void	wm_send_common_locked(struct ifnet *, struct wm_txqueue *, bool);
    749  1.403  knakahar static int	wm_nq_tx_offload(struct wm_softc *, struct wm_txqueue *,
    750  1.403  knakahar     struct wm_txsoft *, uint32_t *, uint32_t *, bool *);
    751  1.280   msaitoh static void	wm_nq_start(struct ifnet *);
    752  1.280   msaitoh static void	wm_nq_start_locked(struct ifnet *);
    753  1.403  knakahar static int	wm_nq_transmit(struct ifnet *, struct mbuf *);
    754  1.403  knakahar static void	wm_nq_transmit_locked(struct ifnet *, struct wm_txqueue *);
    755  1.403  knakahar static void	wm_nq_send_common_locked(struct ifnet *, struct wm_txqueue *, bool);
    756  1.481  knakahar static void	wm_deferred_start_locked(struct wm_txqueue *);
    757  1.484  knakahar static void	wm_handle_queue(void *);
    758  1.280   msaitoh /* Interrupt */
    759  1.403  knakahar static int	wm_txeof(struct wm_softc *, struct wm_txqueue *);
    760  1.493  knakahar static void	wm_rxeof(struct wm_rxqueue *, u_int);
    761  1.280   msaitoh static void	wm_linkintr_gmii(struct wm_softc *, uint32_t);
    762  1.280   msaitoh static void	wm_linkintr_tbi(struct wm_softc *, uint32_t);
    763  1.325   msaitoh static void	wm_linkintr_serdes(struct wm_softc *, uint32_t);
    764   1.47   thorpej static void	wm_linkintr(struct wm_softc *, uint32_t);
    765  1.335   msaitoh static int	wm_intr_legacy(void *);
    766  1.480  knakahar static inline void	wm_txrxintr_disable(struct wm_queue *);
    767  1.480  knakahar static inline void	wm_txrxintr_enable(struct wm_queue *);
    768  1.495  knakahar static void	wm_itrs_calculate(struct wm_softc *, struct wm_queue *);
    769  1.405  knakahar static int	wm_txrxintr_msix(void *);
    770  1.335   msaitoh static int	wm_linkintr_msix(void *);
    771    1.1   thorpej 
    772  1.280   msaitoh /*
    773  1.280   msaitoh  * Media related.
    774  1.292   msaitoh  * GMII, SGMII, TBI, SERDES and SFP.
    775  1.280   msaitoh  */
    776  1.325   msaitoh /* Common */
    777  1.325   msaitoh static void	wm_tbi_serdes_set_linkled(struct wm_softc *);
    778  1.280   msaitoh /* GMII related */
    779   1.47   thorpej static void	wm_gmii_reset(struct wm_softc *);
    780  1.475   msaitoh static void	wm_gmii_setup_phytype(struct wm_softc *sc, uint32_t, uint16_t);
    781  1.280   msaitoh static int	wm_get_phy_id_82575(struct wm_softc *);
    782  1.280   msaitoh static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
    783  1.324   msaitoh static int	wm_gmii_mediachange(struct ifnet *);
    784  1.280   msaitoh static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
    785  1.280   msaitoh static void	wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
    786  1.280   msaitoh static uint32_t	wm_i82543_mii_recvbits(struct wm_softc *);
    787  1.157    dyoung static int	wm_gmii_i82543_readreg(device_t, int, int);
    788  1.157    dyoung static void	wm_gmii_i82543_writereg(device_t, int, int, int);
    789  1.424   msaitoh static int	wm_gmii_mdic_readreg(device_t, int, int);
    790  1.424   msaitoh static void	wm_gmii_mdic_writereg(device_t, int, int, int);
    791  1.157    dyoung static int	wm_gmii_i82544_readreg(device_t, int, int);
    792  1.157    dyoung static void	wm_gmii_i82544_writereg(device_t, int, int, int);
    793  1.157    dyoung static int	wm_gmii_i80003_readreg(device_t, int, int);
    794  1.157    dyoung static void	wm_gmii_i80003_writereg(device_t, int, int, int);
    795  1.167   msaitoh static int	wm_gmii_bm_readreg(device_t, int, int);
    796  1.167   msaitoh static void	wm_gmii_bm_writereg(device_t, int, int, int);
    797  1.280   msaitoh static void	wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int);
    798  1.192   msaitoh static int	wm_gmii_hv_readreg(device_t, int, int);
    799  1.424   msaitoh static int	wm_gmii_hv_readreg_locked(device_t, int, int);
    800  1.192   msaitoh static void	wm_gmii_hv_writereg(device_t, int, int, int);
    801  1.424   msaitoh static void	wm_gmii_hv_writereg_locked(device_t, int, int, int);
    802  1.243   msaitoh static int	wm_gmii_82580_readreg(device_t, int, int);
    803  1.243   msaitoh static void	wm_gmii_82580_writereg(device_t, int, int, int);
    804  1.329   msaitoh static int	wm_gmii_gs40g_readreg(device_t, int, int);
    805  1.329   msaitoh static void	wm_gmii_gs40g_writereg(device_t, int, int, int);
    806  1.280   msaitoh static void	wm_gmii_statchg(struct ifnet *);
    807  1.453   msaitoh /*
    808  1.453   msaitoh  * kumeran related (80003, ICH* and PCH*).
    809  1.453   msaitoh  * These functions are not for accessing MII registers but for accessing
    810  1.453   msaitoh  * kumeran specific registers.
    811  1.453   msaitoh  */
    812  1.531   msaitoh static int	wm_kmrn_readreg(struct wm_softc *, int, uint16_t *);
    813  1.531   msaitoh static int	wm_kmrn_readreg_locked(struct wm_softc *, int, uint16_t *);
    814  1.531   msaitoh static int	wm_kmrn_writereg(struct wm_softc *, int, uint16_t);
    815  1.531   msaitoh static int	wm_kmrn_writereg_locked(struct wm_softc *, int, uint16_t);
    816  1.280   msaitoh /* SGMII */
    817  1.265   msaitoh static bool	wm_sgmii_uses_mdio(struct wm_softc *);
    818  1.199   msaitoh static int	wm_sgmii_readreg(device_t, int, int);
    819  1.199   msaitoh static void	wm_sgmii_writereg(device_t, int, int, int);
    820  1.280   msaitoh /* TBI related */
    821  1.280   msaitoh static void	wm_tbi_mediainit(struct wm_softc *);
    822  1.324   msaitoh static int	wm_tbi_mediachange(struct ifnet *);
    823  1.280   msaitoh static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
    824  1.325   msaitoh static int	wm_check_for_link(struct wm_softc *);
    825  1.325   msaitoh static void	wm_tbi_tick(struct wm_softc *);
    826  1.325   msaitoh /* SERDES related */
    827  1.325   msaitoh static void	wm_serdes_power_up_link_82575(struct wm_softc *);
    828  1.325   msaitoh static int	wm_serdes_mediachange(struct ifnet *);
    829  1.325   msaitoh static void	wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
    830  1.325   msaitoh static void	wm_serdes_tick(struct wm_softc *);
    831  1.292   msaitoh /* SFP related */
    832  1.295   msaitoh static int	wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
    833  1.295   msaitoh static uint32_t	wm_sfp_get_media_type(struct wm_softc *);
    834  1.167   msaitoh 
    835  1.280   msaitoh /*
    836  1.280   msaitoh  * NVM related.
    837  1.280   msaitoh  * Microwire, SPI (w/wo EERD) and Flash.
    838  1.280   msaitoh  */
    839  1.294   msaitoh /* Misc functions */
    840  1.280   msaitoh static void	wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
    841  1.280   msaitoh static void	wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
    842  1.294   msaitoh static int	wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
    843  1.280   msaitoh /* Microwire */
    844  1.280   msaitoh static int	wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
    845  1.280   msaitoh /* SPI */
    846  1.280   msaitoh static int	wm_nvm_ready_spi(struct wm_softc *);
    847  1.280   msaitoh static int	wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
    848  1.280   msaitoh /* Using with EERD */
    849  1.280   msaitoh static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
    850  1.280   msaitoh static int	wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
    851  1.280   msaitoh /* Flash */
    852  1.280   msaitoh static int	wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
    853  1.280   msaitoh     unsigned int *);
    854  1.280   msaitoh static int32_t	wm_ich8_cycle_init(struct wm_softc *);
    855  1.280   msaitoh static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
    856  1.280   msaitoh static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
    857  1.392   msaitoh 	uint32_t *);
    858  1.280   msaitoh static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
    859  1.280   msaitoh static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
    860  1.392   msaitoh static int32_t	wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
    861  1.280   msaitoh static int	wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
    862  1.392   msaitoh static int	wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *);
    863  1.321   msaitoh /* iNVM */
    864  1.321   msaitoh static int	wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
    865  1.321   msaitoh static int	wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
    866  1.327   msaitoh /* Lock, detecting NVM type, validate checksum and read */
    867  1.280   msaitoh static int	wm_nvm_is_onboard_eeprom(struct wm_softc *);
    868  1.321   msaitoh static int	wm_nvm_get_flash_presence_i210(struct wm_softc *);
    869  1.280   msaitoh static int	wm_nvm_validate_checksum(struct wm_softc *);
    870  1.347   msaitoh static void	wm_nvm_version_invm(struct wm_softc *);
    871  1.328   msaitoh static void	wm_nvm_version(struct wm_softc *);
    872  1.280   msaitoh static int	wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
    873    1.1   thorpej 
    874  1.280   msaitoh /*
    875  1.280   msaitoh  * Hardware semaphores.
    876  1.280   msaitoh  * Very complexed...
    877  1.280   msaitoh  */
    878  1.424   msaitoh static int	wm_get_null(struct wm_softc *);
    879  1.424   msaitoh static void	wm_put_null(struct wm_softc *);
    880  1.530   msaitoh static int	wm_get_eecd(struct wm_softc *);
    881  1.530   msaitoh static void	wm_put_eecd(struct wm_softc *);
    882  1.424   msaitoh static int	wm_get_swsm_semaphore(struct wm_softc *); /* 8257[123] */
    883  1.127    bouyer static void	wm_put_swsm_semaphore(struct wm_softc *);
    884  1.127    bouyer static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
    885  1.127    bouyer static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
    886  1.530   msaitoh static int	wm_get_nvm_80003(struct wm_softc *);
    887  1.530   msaitoh static void	wm_put_nvm_80003(struct wm_softc *);
    888  1.530   msaitoh static int	wm_get_nvm_82571(struct wm_softc *);
    889  1.530   msaitoh static void	wm_put_nvm_82571(struct wm_softc *);
    890  1.424   msaitoh static int	wm_get_phy_82575(struct wm_softc *);
    891  1.424   msaitoh static void	wm_put_phy_82575(struct wm_softc *);
    892  1.424   msaitoh static int	wm_get_swfwhw_semaphore(struct wm_softc *); /* For 574/583 */
    893  1.139    bouyer static void	wm_put_swfwhw_semaphore(struct wm_softc *);
    894  1.424   msaitoh static int	wm_get_swflag_ich8lan(struct wm_softc *);	/* For PHY */
    895  1.424   msaitoh static void	wm_put_swflag_ich8lan(struct wm_softc *);
    896  1.530   msaitoh static int	wm_get_nvm_ich8lan(struct wm_softc *);
    897  1.423   msaitoh static void	wm_put_nvm_ich8lan(struct wm_softc *);
    898  1.259   msaitoh static int	wm_get_hw_semaphore_82573(struct wm_softc *);
    899  1.259   msaitoh static void	wm_put_hw_semaphore_82573(struct wm_softc *);
    900  1.139    bouyer 
    901  1.280   msaitoh /*
    902  1.280   msaitoh  * Management mode and power management related subroutines.
    903  1.280   msaitoh  * BMC, AMT, suspend/resume and EEE.
    904  1.280   msaitoh  */
    905  1.439   msaitoh #if 0
    906  1.169   msaitoh static int	wm_check_mng_mode(struct wm_softc *);
    907  1.169   msaitoh static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
    908  1.169   msaitoh static int	wm_check_mng_mode_82574(struct wm_softc *);
    909  1.169   msaitoh static int	wm_check_mng_mode_generic(struct wm_softc *);
    910  1.378   msaitoh #endif
    911  1.203   msaitoh static int	wm_enable_mng_pass_thru(struct wm_softc *);
    912  1.386   msaitoh static bool	wm_phy_resetisblocked(struct wm_softc *);
    913  1.169   msaitoh static void	wm_get_hw_control(struct wm_softc *);
    914  1.280   msaitoh static void	wm_release_hw_control(struct wm_softc *);
    915  1.392   msaitoh static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool);
    916  1.280   msaitoh static void	wm_smbustopci(struct wm_softc *);
    917  1.280   msaitoh static void	wm_init_manageability(struct wm_softc *);
    918  1.280   msaitoh static void	wm_release_manageability(struct wm_softc *);
    919  1.280   msaitoh static void	wm_get_wakeup(struct wm_softc *);
    920  1.447   msaitoh static void	wm_ulp_disable(struct wm_softc *);
    921  1.280   msaitoh static void	wm_enable_phy_wakeup(struct wm_softc *);
    922  1.203   msaitoh static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
    923  1.280   msaitoh static void	wm_enable_wakeup(struct wm_softc *);
    924  1.552   msaitoh static void	wm_disable_aspm(struct wm_softc *);
    925  1.377   msaitoh /* LPLU (Low Power Link Up) */
    926  1.377   msaitoh static void	wm_lplu_d0_disable(struct wm_softc *);
    927  1.280   msaitoh /* EEE */
    928  1.280   msaitoh static void	wm_set_eee_i350(struct wm_softc *);
    929  1.280   msaitoh 
    930  1.280   msaitoh /*
    931  1.280   msaitoh  * Workarounds (mainly PHY related).
    932  1.280   msaitoh  * Basically, PHY's workarounds are in the PHY drivers.
    933  1.280   msaitoh  */
    934  1.280   msaitoh static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
    935  1.280   msaitoh static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
    936  1.192   msaitoh static void	wm_hv_phy_workaround_ich8lan(struct wm_softc *);
    937  1.221   msaitoh static void	wm_lv_phy_workaround_ich8lan(struct wm_softc *);
    938  1.424   msaitoh static int	wm_k1_gig_workaround_hv(struct wm_softc *, int);
    939  1.221   msaitoh static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
    940  1.192   msaitoh static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
    941  1.199   msaitoh static void	wm_reset_init_script_82575(struct wm_softc *);
    942  1.325   msaitoh static void	wm_reset_mdicnfg_82580(struct wm_softc *);
    943  1.447   msaitoh static bool	wm_phy_is_accessible_pchlan(struct wm_softc *);
    944  1.447   msaitoh static void	wm_toggle_lanphypc_pch_lpt(struct wm_softc *);
    945  1.445   msaitoh static int	wm_platform_pm_pch_lpt(struct wm_softc *, bool);
    946  1.329   msaitoh static void	wm_pll_workaround_i210(struct wm_softc *);
    947  1.517   msaitoh static void	wm_legacy_irq_quirk_spt(struct wm_softc *);
    948    1.1   thorpej 
    949  1.201   msaitoh CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
    950  1.201   msaitoh     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
    951    1.1   thorpej 
    952    1.1   thorpej /*
    953    1.1   thorpej  * Devices supported by this driver.
    954    1.1   thorpej  */
    955   1.76   thorpej static const struct wm_product {
    956    1.1   thorpej 	pci_vendor_id_t		wmp_vendor;
    957    1.1   thorpej 	pci_product_id_t	wmp_product;
    958    1.1   thorpej 	const char		*wmp_name;
    959   1.43   thorpej 	wm_chip_type		wmp_type;
    960  1.292   msaitoh 	uint32_t		wmp_flags;
    961  1.311   msaitoh #define	WMP_F_UNKNOWN		WM_MEDIATYPE_UNKNOWN
    962  1.311   msaitoh #define	WMP_F_FIBER		WM_MEDIATYPE_FIBER
    963  1.311   msaitoh #define	WMP_F_COPPER		WM_MEDIATYPE_COPPER
    964  1.311   msaitoh #define	WMP_F_SERDES		WM_MEDIATYPE_SERDES
    965  1.292   msaitoh #define WMP_MEDIATYPE(x)	((x) & 0x03)
    966    1.1   thorpej } wm_products[] = {
    967    1.1   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
    968    1.1   thorpej 	  "Intel i82542 1000BASE-X Ethernet",
    969  1.291   msaitoh 	  WM_T_82542_2_1,	WMP_F_FIBER },
    970    1.1   thorpej 
    971   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
    972   1.11   thorpej 	  "Intel i82543GC 1000BASE-X Ethernet",
    973  1.291   msaitoh 	  WM_T_82543,		WMP_F_FIBER },
    974    1.1   thorpej 
    975   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
    976   1.11   thorpej 	  "Intel i82543GC 1000BASE-T Ethernet",
    977  1.291   msaitoh 	  WM_T_82543,		WMP_F_COPPER },
    978    1.1   thorpej 
    979   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
    980   1.11   thorpej 	  "Intel i82544EI 1000BASE-T Ethernet",
    981  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
    982    1.1   thorpej 
    983   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
    984   1.11   thorpej 	  "Intel i82544EI 1000BASE-X Ethernet",
    985  1.291   msaitoh 	  WM_T_82544,		WMP_F_FIBER },
    986    1.1   thorpej 
    987   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
    988    1.1   thorpej 	  "Intel i82544GC 1000BASE-T Ethernet",
    989  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
    990    1.1   thorpej 
    991   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
    992   1.11   thorpej 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
    993  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
    994    1.1   thorpej 
    995   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
    996   1.17   thorpej 	  "Intel i82540EM 1000BASE-T Ethernet",
    997  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
    998   1.34      kent 
    999   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
   1000   1.55   thorpej 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
   1001  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1002   1.55   thorpej 
   1003   1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
   1004   1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
   1005  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1006   1.34      kent 
   1007   1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
   1008   1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
   1009  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1010   1.33      kent 
   1011   1.33      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
   1012   1.33      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
   1013  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1014   1.17   thorpej 
   1015   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
   1016   1.17   thorpej 	  "Intel i82545EM 1000BASE-T Ethernet",
   1017  1.291   msaitoh 	  WM_T_82545,		WMP_F_COPPER },
   1018   1.17   thorpej 
   1019   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
   1020   1.55   thorpej 	  "Intel i82545GM 1000BASE-T Ethernet",
   1021  1.291   msaitoh 	  WM_T_82545_3,		WMP_F_COPPER },
   1022   1.55   thorpej 
   1023   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
   1024   1.55   thorpej 	  "Intel i82545GM 1000BASE-X Ethernet",
   1025  1.291   msaitoh 	  WM_T_82545_3,		WMP_F_FIBER },
   1026  1.279   msaitoh 
   1027   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
   1028   1.55   thorpej 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
   1029   1.55   thorpej 	  WM_T_82545_3,		WMP_F_SERDES },
   1030  1.279   msaitoh 
   1031   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
   1032   1.39   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
   1033  1.291   msaitoh 	  WM_T_82546,		WMP_F_COPPER },
   1034   1.39   thorpej 
   1035  1.198   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_QUAD,
   1036   1.17   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
   1037  1.291   msaitoh 	  WM_T_82546,		WMP_F_COPPER },
   1038   1.17   thorpej 
   1039   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
   1040   1.17   thorpej 	  "Intel i82545EM 1000BASE-X Ethernet",
   1041  1.291   msaitoh 	  WM_T_82545,		WMP_F_FIBER },
   1042   1.17   thorpej 
   1043   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
   1044   1.17   thorpej 	  "Intel i82546EB 1000BASE-X Ethernet",
   1045  1.291   msaitoh 	  WM_T_82546,		WMP_F_FIBER },
   1046   1.17   thorpej 
   1047   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
   1048   1.55   thorpej 	  "Intel i82546GB 1000BASE-T Ethernet",
   1049  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1050   1.55   thorpej 
   1051   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
   1052   1.55   thorpej 	  "Intel i82546GB 1000BASE-X Ethernet",
   1053  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_FIBER },
   1054  1.279   msaitoh 
   1055   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
   1056   1.55   thorpej 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
   1057   1.55   thorpej 	  WM_T_82546_3,		WMP_F_SERDES },
   1058  1.279   msaitoh 
   1059  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
   1060  1.127    bouyer 	  "i82546GB quad-port Gigabit Ethernet",
   1061  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1062  1.127    bouyer 
   1063  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
   1064  1.127    bouyer 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
   1065  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1066  1.127    bouyer 
   1067  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
   1068  1.116   msaitoh 	  "Intel PRO/1000MT (82546GB)",
   1069  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1070  1.116   msaitoh 
   1071   1.63   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
   1072   1.63   thorpej 	  "Intel i82541EI 1000BASE-T Ethernet",
   1073  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1074   1.63   thorpej 
   1075  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
   1076  1.116   msaitoh 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
   1077  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1078  1.116   msaitoh 
   1079   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
   1080   1.57   thorpej 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
   1081  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1082   1.57   thorpej 
   1083   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
   1084   1.57   thorpej 	  "Intel i82541ER 1000BASE-T Ethernet",
   1085  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1086   1.57   thorpej 
   1087   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
   1088   1.57   thorpej 	  "Intel i82541GI 1000BASE-T Ethernet",
   1089  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1090   1.57   thorpej 
   1091   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
   1092   1.57   thorpej 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
   1093  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1094   1.57   thorpej 
   1095  1.101      tron 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
   1096  1.101      tron 	  "Intel i82541PI 1000BASE-T Ethernet",
   1097  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1098  1.101      tron 
   1099   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
   1100   1.57   thorpej 	  "Intel i82547EI 1000BASE-T Ethernet",
   1101  1.291   msaitoh 	  WM_T_82547,		WMP_F_COPPER },
   1102   1.57   thorpej 
   1103  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
   1104  1.141    simonb 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
   1105  1.291   msaitoh 	  WM_T_82547,		WMP_F_COPPER },
   1106  1.116   msaitoh 
   1107   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
   1108   1.57   thorpej 	  "Intel i82547GI 1000BASE-T Ethernet",
   1109  1.291   msaitoh 	  WM_T_82547_2,		WMP_F_COPPER },
   1110  1.116   msaitoh 
   1111  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
   1112  1.116   msaitoh 	  "Intel PRO/1000 PT (82571EB)",
   1113  1.291   msaitoh 	  WM_T_82571,		WMP_F_COPPER },
   1114  1.116   msaitoh 
   1115  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
   1116  1.116   msaitoh 	  "Intel PRO/1000 PF (82571EB)",
   1117  1.291   msaitoh 	  WM_T_82571,		WMP_F_FIBER },
   1118  1.279   msaitoh 
   1119  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
   1120  1.116   msaitoh 	  "Intel PRO/1000 PB (82571EB)",
   1121  1.116   msaitoh 	  WM_T_82571,		WMP_F_SERDES },
   1122  1.279   msaitoh 
   1123  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
   1124  1.127    bouyer 	  "Intel PRO/1000 QT (82571EB)",
   1125  1.291   msaitoh 	  WM_T_82571,		WMP_F_COPPER },
   1126  1.127    bouyer 
   1127  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
   1128  1.299   msaitoh 	  "Intel PRO/1000 PT Quad Port Server Adapter",
   1129  1.299   msaitoh 	  WM_T_82571,		WMP_F_COPPER, },
   1130  1.299   msaitoh 
   1131  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER,
   1132  1.299   msaitoh 	  "Intel Gigabit PT Quad Port Server ExpressModule",
   1133  1.299   msaitoh 	  WM_T_82571,		WMP_F_COPPER, },
   1134  1.299   msaitoh 
   1135  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES,
   1136  1.299   msaitoh 	  "Intel 82571EB Dual Gigabit Ethernet (SERDES)",
   1137  1.299   msaitoh 	  WM_T_82571,		WMP_F_SERDES, },
   1138  1.299   msaitoh 
   1139  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES,
   1140  1.299   msaitoh 	  "Intel 82571EB Quad Gigabit Ethernet (SERDES)",
   1141  1.299   msaitoh 	  WM_T_82571,		WMP_F_SERDES, },
   1142  1.299   msaitoh 
   1143  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER,
   1144  1.299   msaitoh 	  "Intel 82571EB Quad 1000baseX Ethernet",
   1145  1.299   msaitoh 	  WM_T_82571,		WMP_F_FIBER, },
   1146  1.299   msaitoh 
   1147  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
   1148  1.116   msaitoh 	  "Intel i82572EI 1000baseT Ethernet",
   1149  1.291   msaitoh 	  WM_T_82572,		WMP_F_COPPER },
   1150  1.116   msaitoh 
   1151  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
   1152  1.116   msaitoh 	  "Intel i82572EI 1000baseX Ethernet",
   1153  1.291   msaitoh 	  WM_T_82572,		WMP_F_FIBER },
   1154  1.279   msaitoh 
   1155  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
   1156  1.116   msaitoh 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
   1157  1.116   msaitoh 	  WM_T_82572,		WMP_F_SERDES },
   1158  1.116   msaitoh 
   1159  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
   1160  1.116   msaitoh 	  "Intel i82572EI 1000baseT Ethernet",
   1161  1.291   msaitoh 	  WM_T_82572,		WMP_F_COPPER },
   1162  1.116   msaitoh 
   1163  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
   1164  1.116   msaitoh 	  "Intel i82573E",
   1165  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1166  1.116   msaitoh 
   1167  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
   1168  1.117   msaitoh 	  "Intel i82573E IAMT",
   1169  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1170  1.116   msaitoh 
   1171  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
   1172  1.116   msaitoh 	  "Intel i82573L Gigabit Ethernet",
   1173  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1174  1.116   msaitoh 
   1175  1.165  sborrill 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
   1176  1.165  sborrill 	  "Intel i82574L",
   1177  1.291   msaitoh 	  WM_T_82574,		WMP_F_COPPER },
   1178  1.165  sborrill 
   1179  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574LA,
   1180  1.299   msaitoh 	  "Intel i82574L",
   1181  1.299   msaitoh 	  WM_T_82574,		WMP_F_COPPER },
   1182  1.299   msaitoh 
   1183  1.185   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82583V,
   1184  1.185   msaitoh 	  "Intel i82583V",
   1185  1.291   msaitoh 	  WM_T_82583,		WMP_F_COPPER },
   1186  1.185   msaitoh 
   1187  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
   1188  1.127    bouyer 	  "i80003 dual 1000baseT Ethernet",
   1189  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1190  1.127    bouyer 
   1191  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
   1192  1.127    bouyer 	  "i80003 dual 1000baseX Ethernet",
   1193  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1194  1.279   msaitoh 
   1195  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
   1196  1.127    bouyer 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
   1197  1.127    bouyer 	  WM_T_80003,		WMP_F_SERDES },
   1198  1.127    bouyer 
   1199  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
   1200  1.127    bouyer 	  "Intel i80003 1000baseT Ethernet",
   1201  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1202  1.279   msaitoh 
   1203  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
   1204  1.127    bouyer 	  "Intel i80003 Gigabit Ethernet (SERDES)",
   1205  1.127    bouyer 	  WM_T_80003,		WMP_F_SERDES },
   1206  1.279   msaitoh 
   1207  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
   1208  1.139    bouyer 	  "Intel i82801H (M_AMT) LAN Controller",
   1209  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1210  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
   1211  1.139    bouyer 	  "Intel i82801H (AMT) LAN Controller",
   1212  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1213  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
   1214  1.139    bouyer 	  "Intel i82801H LAN Controller",
   1215  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1216  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
   1217  1.438   msaitoh 	  "Intel i82801H (IFE) 10/100 LAN Controller",
   1218  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1219  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
   1220  1.139    bouyer 	  "Intel i82801H (M) LAN Controller",
   1221  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1222  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
   1223  1.438   msaitoh 	  "Intel i82801H IFE (GT) 10/100 LAN Controller",
   1224  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1225  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
   1226  1.438   msaitoh 	  "Intel i82801H IFE (G) 10/100 LAN Controller",
   1227  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1228  1.426   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_82567V_3,
   1229  1.426   msaitoh 	  "82567V-3 LAN Controller",
   1230  1.426   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1231  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
   1232  1.144   msaitoh 	  "82801I (AMT) LAN Controller",
   1233  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1234  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
   1235  1.438   msaitoh 	  "82801I 10/100 LAN Controller",
   1236  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1237  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
   1238  1.438   msaitoh 	  "82801I (G) 10/100 LAN Controller",
   1239  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1240  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
   1241  1.438   msaitoh 	  "82801I (GT) 10/100 LAN Controller",
   1242  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1243  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
   1244  1.144   msaitoh 	  "82801I (C) LAN Controller",
   1245  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1246  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
   1247  1.162    bouyer 	  "82801I mobile LAN Controller",
   1248  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1249  1.459   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_V,
   1250  1.162    bouyer 	  "82801I mobile (V) LAN Controller",
   1251  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1252  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
   1253  1.162    bouyer 	  "82801I mobile (AMT) LAN Controller",
   1254  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1255  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_BM,
   1256  1.191   msaitoh 	  "82567LM-4 LAN Controller",
   1257  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1258  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LM,
   1259  1.191   msaitoh 	  "82567LM-2 LAN Controller",
   1260  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1261  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LF,
   1262  1.191   msaitoh 	  "82567LF-2 LAN Controller",
   1263  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1264  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LM,
   1265  1.164     markd 	  "82567LM-3 LAN Controller",
   1266  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1267  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LF,
   1268  1.167   msaitoh 	  "82567LF-3 LAN Controller",
   1269  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1270  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_V,
   1271  1.191   msaitoh 	  "82567V-2 LAN Controller",
   1272  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1273  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_V,
   1274  1.221   msaitoh 	  "82567V-3? LAN Controller",
   1275  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1276  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_HANKSVILLE,
   1277  1.221   msaitoh 	  "HANKSVILLE LAN Controller",
   1278  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1279  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LM,
   1280  1.207   msaitoh 	  "PCH LAN (82577LM) Controller",
   1281  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1282  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LC,
   1283  1.207   msaitoh 	  "PCH LAN (82577LC) Controller",
   1284  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1285  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DM,
   1286  1.190   msaitoh 	  "PCH LAN (82578DM) Controller",
   1287  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1288  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DC,
   1289  1.190   msaitoh 	  "PCH LAN (82578DC) Controller",
   1290  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1291  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_LM,
   1292  1.221   msaitoh 	  "PCH2 LAN (82579LM) Controller",
   1293  1.291   msaitoh 	  WM_T_PCH2,		WMP_F_COPPER },
   1294  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_V,
   1295  1.221   msaitoh 	  "PCH2 LAN (82579V) Controller",
   1296  1.291   msaitoh 	  WM_T_PCH2,		WMP_F_COPPER },
   1297  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_COPPER,
   1298  1.199   msaitoh 	  "82575EB dual-1000baseT Ethernet",
   1299  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1300  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES,
   1301  1.199   msaitoh 	  "82575EB dual-1000baseX Ethernet (SERDES)",
   1302  1.199   msaitoh 	  WM_T_82575,		WMP_F_SERDES },
   1303  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER,
   1304  1.199   msaitoh 	  "82575GB quad-1000baseT Ethernet",
   1305  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1306  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM,
   1307  1.199   msaitoh 	  "82575GB quad-1000baseT Ethernet (PM)",
   1308  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1309  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_COPPER,
   1310  1.199   msaitoh 	  "82576 1000BaseT Ethernet",
   1311  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1312  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_FIBER,
   1313  1.199   msaitoh 	  "82576 1000BaseX Ethernet",
   1314  1.291   msaitoh 	  WM_T_82576,		WMP_F_FIBER },
   1315  1.279   msaitoh 
   1316  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES,
   1317  1.199   msaitoh 	  "82576 gigabit Ethernet (SERDES)",
   1318  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1319  1.279   msaitoh 
   1320  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_QUAD_COPPER,
   1321  1.199   msaitoh 	  "82576 quad-1000BaseT Ethernet",
   1322  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1323  1.299   msaitoh 
   1324  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2,
   1325  1.299   msaitoh 	  "82576 Gigabit ET2 Quad Port Server Adapter",
   1326  1.299   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1327  1.299   msaitoh 
   1328  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS,
   1329  1.199   msaitoh 	  "82576 gigabit Ethernet",
   1330  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1331  1.279   msaitoh 
   1332  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS_SERDES,
   1333  1.199   msaitoh 	  "82576 gigabit Ethernet (SERDES)",
   1334  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1335  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES_QUAD,
   1336  1.199   msaitoh 	  "82576 quad-gigabit Ethernet (SERDES)",
   1337  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1338  1.279   msaitoh 
   1339  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER,
   1340  1.199   msaitoh 	  "82580 1000BaseT Ethernet",
   1341  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1342  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_FIBER,
   1343  1.199   msaitoh 	  "82580 1000BaseX Ethernet",
   1344  1.291   msaitoh 	  WM_T_82580,		WMP_F_FIBER },
   1345  1.279   msaitoh 
   1346  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SERDES,
   1347  1.199   msaitoh 	  "82580 1000BaseT Ethernet (SERDES)",
   1348  1.199   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1349  1.279   msaitoh 
   1350  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SGMII,
   1351  1.199   msaitoh 	  "82580 gigabit Ethernet (SGMII)",
   1352  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1353  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER_DUAL,
   1354  1.199   msaitoh 	  "82580 dual-1000BaseT Ethernet",
   1355  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1356  1.300   msaitoh 
   1357  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_QUAD_FIBER,
   1358  1.221   msaitoh 	  "82580 quad-1000BaseX Ethernet",
   1359  1.291   msaitoh 	  WM_T_82580,		WMP_F_FIBER },
   1360  1.300   msaitoh 
   1361  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SGMII,
   1362  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SGMII)",
   1363  1.304   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1364  1.304   msaitoh 
   1365  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SERDES,
   1366  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SERDES)",
   1367  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1368  1.304   msaitoh 
   1369  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_BPLANE,
   1370  1.304   msaitoh 	  "DH89XXCC 1000BASE-KX Ethernet",
   1371  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1372  1.304   msaitoh 
   1373  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SFP,
   1374  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SFP)",
   1375  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1376  1.304   msaitoh 
   1377  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_COPPER,
   1378  1.228   msaitoh 	  "I350 Gigabit Network Connection",
   1379  1.291   msaitoh 	  WM_T_I350,		WMP_F_COPPER },
   1380  1.304   msaitoh 
   1381  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_FIBER,
   1382  1.228   msaitoh 	  "I350 Gigabit Fiber Network Connection",
   1383  1.291   msaitoh 	  WM_T_I350,		WMP_F_FIBER },
   1384  1.279   msaitoh 
   1385  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SERDES,
   1386  1.228   msaitoh 	  "I350 Gigabit Backplane Connection",
   1387  1.228   msaitoh 	  WM_T_I350,		WMP_F_SERDES },
   1388  1.292   msaitoh 
   1389  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_DA4,
   1390  1.299   msaitoh 	  "I350 Quad Port Gigabit Ethernet",
   1391  1.299   msaitoh 	  WM_T_I350,		WMP_F_SERDES },
   1392  1.299   msaitoh 
   1393  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SGMII,
   1394  1.228   msaitoh 	  "I350 Gigabit Connection",
   1395  1.291   msaitoh 	  WM_T_I350,		WMP_F_COPPER },
   1396  1.292   msaitoh 
   1397  1.308   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_1000KX,
   1398  1.308   msaitoh 	  "I354 Gigabit Ethernet (KX)",
   1399  1.308   msaitoh 	  WM_T_I354,		WMP_F_SERDES },
   1400  1.308   msaitoh 
   1401  1.265   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_SGMII,
   1402  1.308   msaitoh 	  "I354 Gigabit Ethernet (SGMII)",
   1403  1.308   msaitoh 	  WM_T_I354,		WMP_F_COPPER },
   1404  1.308   msaitoh 
   1405  1.308   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_25GBE,
   1406  1.308   msaitoh 	  "I354 Gigabit Ethernet (2.5G)",
   1407  1.291   msaitoh 	  WM_T_I354,		WMP_F_COPPER },
   1408  1.308   msaitoh 
   1409  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_T1,
   1410  1.247   msaitoh 	  "I210-T1 Ethernet Server Adapter",
   1411  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1412  1.299   msaitoh 
   1413  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_OEM1,
   1414  1.247   msaitoh 	  "I210 Ethernet (Copper OEM)",
   1415  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1416  1.299   msaitoh 
   1417  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_IT,
   1418  1.247   msaitoh 	  "I210 Ethernet (Copper IT)",
   1419  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1420  1.299   msaitoh 
   1421  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_WOF,
   1422  1.299   msaitoh 	  "I210 Ethernet (FLASH less)",
   1423  1.299   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1424  1.299   msaitoh 
   1425  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_FIBER,
   1426  1.247   msaitoh 	  "I210 Gigabit Ethernet (Fiber)",
   1427  1.291   msaitoh 	  WM_T_I210,		WMP_F_FIBER },
   1428  1.279   msaitoh 
   1429  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES,
   1430  1.247   msaitoh 	  "I210 Gigabit Ethernet (SERDES)",
   1431  1.247   msaitoh 	  WM_T_I210,		WMP_F_SERDES },
   1432  1.292   msaitoh 
   1433  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES_WOF,
   1434  1.299   msaitoh 	  "I210 Gigabit Ethernet (FLASH less)",
   1435  1.299   msaitoh 	  WM_T_I210,		WMP_F_SERDES },
   1436  1.299   msaitoh 
   1437  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SGMII,
   1438  1.247   msaitoh 	  "I210 Gigabit Ethernet (SGMII)",
   1439  1.292   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1440  1.292   msaitoh 
   1441  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I211_COPPER,
   1442  1.247   msaitoh 	  "I211 Ethernet (COPPER)",
   1443  1.291   msaitoh 	  WM_T_I211,		WMP_F_COPPER },
   1444  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_V,
   1445  1.249   msaitoh 	  "I217 V Ethernet Connection",
   1446  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1447  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_LM,
   1448  1.249   msaitoh 	  "I217 LM Ethernet Connection",
   1449  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1450  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V,
   1451  1.249   msaitoh 	  "I218 V Ethernet Connection",
   1452  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1453  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V2,
   1454  1.298   msaitoh 	  "I218 V Ethernet Connection",
   1455  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1456  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V3,
   1457  1.298   msaitoh 	  "I218 V Ethernet Connection",
   1458  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1459  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM,
   1460  1.249   msaitoh 	  "I218 LM Ethernet Connection",
   1461  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1462  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM2,
   1463  1.298   msaitoh 	  "I218 LM Ethernet Connection",
   1464  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1465  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM3,
   1466  1.298   msaitoh 	  "I218 LM Ethernet Connection",
   1467  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1468  1.392   msaitoh #if 0
   1469  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V,
   1470  1.392   msaitoh 	  "I219 V Ethernet Connection",
   1471  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1472  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V2,
   1473  1.392   msaitoh 	  "I219 V Ethernet Connection",
   1474  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1475  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V4,
   1476  1.422   msaitoh 	  "I219 V Ethernet Connection",
   1477  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1478  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V5,
   1479  1.422   msaitoh 	  "I219 V Ethernet Connection",
   1480  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1481  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM,
   1482  1.392   msaitoh 	  "I219 LM Ethernet Connection",
   1483  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1484  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM2,
   1485  1.392   msaitoh 	  "I219 LM Ethernet Connection",
   1486  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1487  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM3,
   1488  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1489  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1490  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM4,
   1491  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1492  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1493  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM5,
   1494  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1495  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1496  1.392   msaitoh #endif
   1497    1.1   thorpej 	{ 0,			0,
   1498    1.1   thorpej 	  NULL,
   1499    1.1   thorpej 	  0,			0 },
   1500    1.1   thorpej };
   1501    1.1   thorpej 
   1502  1.280   msaitoh /*
   1503  1.280   msaitoh  * Register read/write functions.
   1504  1.280   msaitoh  * Other than CSR_{READ|WRITE}().
   1505  1.280   msaitoh  */
   1506  1.280   msaitoh 
   1507   1.53   thorpej #if 0 /* Not currently used */
   1508  1.110     perry static inline uint32_t
   1509   1.53   thorpej wm_io_read(struct wm_softc *sc, int reg)
   1510   1.53   thorpej {
   1511   1.53   thorpej 
   1512   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
   1513   1.53   thorpej 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
   1514   1.53   thorpej }
   1515   1.53   thorpej #endif
   1516   1.53   thorpej 
   1517  1.110     perry static inline void
   1518   1.53   thorpej wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
   1519   1.53   thorpej {
   1520   1.53   thorpej 
   1521   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
   1522   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
   1523   1.53   thorpej }
   1524   1.53   thorpej 
   1525  1.110     perry static inline void
   1526  1.199   msaitoh wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off,
   1527  1.199   msaitoh     uint32_t data)
   1528  1.199   msaitoh {
   1529  1.199   msaitoh 	uint32_t regval;
   1530  1.199   msaitoh 	int i;
   1531  1.199   msaitoh 
   1532  1.199   msaitoh 	regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT);
   1533  1.199   msaitoh 
   1534  1.199   msaitoh 	CSR_WRITE(sc, reg, regval);
   1535  1.199   msaitoh 
   1536  1.199   msaitoh 	for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) {
   1537  1.199   msaitoh 		delay(5);
   1538  1.199   msaitoh 		if (CSR_READ(sc, reg) & SCTL_CTL_READY)
   1539  1.199   msaitoh 			break;
   1540  1.199   msaitoh 	}
   1541  1.199   msaitoh 	if (i == SCTL_CTL_POLL_TIMEOUT) {
   1542  1.280   msaitoh 		aprint_error("%s: WARNING:"
   1543  1.280   msaitoh 		    " i82575 reg 0x%08x setup did not indicate ready\n",
   1544  1.199   msaitoh 		    device_xname(sc->sc_dev), reg);
   1545  1.199   msaitoh 	}
   1546  1.199   msaitoh }
   1547  1.199   msaitoh 
   1548  1.199   msaitoh static inline void
   1549  1.110     perry wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
   1550   1.69   thorpej {
   1551   1.69   thorpej 	wa->wa_low = htole32(v & 0xffffffffU);
   1552   1.69   thorpej 	if (sizeof(bus_addr_t) == 8)
   1553   1.69   thorpej 		wa->wa_high = htole32((uint64_t) v >> 32);
   1554   1.69   thorpej 	else
   1555   1.69   thorpej 		wa->wa_high = 0;
   1556   1.69   thorpej }
   1557   1.69   thorpej 
   1558  1.280   msaitoh /*
   1559  1.352  knakahar  * Descriptor sync/init functions.
   1560  1.352  knakahar  */
   1561  1.352  knakahar static inline void
   1562  1.362  knakahar wm_cdtxsync(struct wm_txqueue *txq, int start, int num, int ops)
   1563  1.352  knakahar {
   1564  1.362  knakahar 	struct wm_softc *sc = txq->txq_sc;
   1565  1.352  knakahar 
   1566  1.352  knakahar 	/* If it will wrap around, sync to the end of the ring. */
   1567  1.356  knakahar 	if ((start + num) > WM_NTXDESC(txq)) {
   1568  1.356  knakahar 		bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
   1569  1.398  knakahar 		    WM_CDTXOFF(txq, start), txq->txq_descsize *
   1570  1.356  knakahar 		    (WM_NTXDESC(txq) - start), ops);
   1571  1.356  knakahar 		num -= (WM_NTXDESC(txq) - start);
   1572  1.352  knakahar 		start = 0;
   1573  1.352  knakahar 	}
   1574  1.352  knakahar 
   1575  1.352  knakahar 	/* Now sync whatever is left. */
   1576  1.356  knakahar 	bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
   1577  1.398  knakahar 	    WM_CDTXOFF(txq, start), txq->txq_descsize * num, ops);
   1578  1.352  knakahar }
   1579  1.352  knakahar 
   1580  1.352  knakahar static inline void
   1581  1.362  knakahar wm_cdrxsync(struct wm_rxqueue *rxq, int start, int ops)
   1582  1.352  knakahar {
   1583  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   1584  1.352  knakahar 
   1585  1.356  knakahar 	bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap,
   1586  1.466  knakahar 	    WM_CDRXOFF(rxq, start), rxq->rxq_descsize, ops);
   1587  1.352  knakahar }
   1588  1.352  knakahar 
   1589  1.352  knakahar static inline void
   1590  1.362  knakahar wm_init_rxdesc(struct wm_rxqueue *rxq, int start)
   1591  1.352  knakahar {
   1592  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   1593  1.356  knakahar 	struct wm_rxsoft *rxs = &rxq->rxq_soft[start];
   1594  1.352  knakahar 	struct mbuf *m = rxs->rxs_mbuf;
   1595  1.352  knakahar 
   1596  1.352  knakahar 	/*
   1597  1.352  knakahar 	 * Note: We scoot the packet forward 2 bytes in the buffer
   1598  1.352  knakahar 	 * so that the payload after the Ethernet header is aligned
   1599  1.352  knakahar 	 * to a 4-byte boundary.
   1600  1.352  knakahar 
   1601  1.352  knakahar 	 * XXX BRAINDAMAGE ALERT!
   1602  1.352  knakahar 	 * The stupid chip uses the same size for every buffer, which
   1603  1.352  knakahar 	 * is set in the Receive Control register.  We are using the 2K
   1604  1.352  knakahar 	 * size option, but what we REALLY want is (2K - 2)!  For this
   1605  1.352  knakahar 	 * reason, we can't "scoot" packets longer than the standard
   1606  1.352  knakahar 	 * Ethernet MTU.  On strict-alignment platforms, if the total
   1607  1.352  knakahar 	 * size exceeds (2K - 2) we set align_tweak to 0 and let
   1608  1.352  knakahar 	 * the upper layer copy the headers.
   1609  1.352  knakahar 	 */
   1610  1.352  knakahar 	m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak;
   1611  1.352  knakahar 
   1612  1.466  knakahar 	if (sc->sc_type == WM_T_82574) {
   1613  1.466  knakahar 		ext_rxdesc_t *rxd = &rxq->rxq_ext_descs[start];
   1614  1.466  knakahar 		rxd->erx_data.erxd_addr =
   1615  1.466  knakahar 			htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1616  1.466  knakahar 		rxd->erx_data.erxd_dd = 0;
   1617  1.466  knakahar 	} else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   1618  1.466  knakahar 		nq_rxdesc_t *rxd = &rxq->rxq_nq_descs[start];
   1619  1.466  knakahar 
   1620  1.466  knakahar 		rxd->nqrx_data.nrxd_paddr =
   1621  1.466  knakahar 			htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1622  1.466  knakahar 		/* Currently, split header is not supported. */
   1623  1.466  knakahar 		rxd->nqrx_data.nrxd_haddr = 0;
   1624  1.466  knakahar 	} else {
   1625  1.466  knakahar 		wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start];
   1626  1.466  knakahar 
   1627  1.466  knakahar 		wm_set_dma_addr(&rxd->wrx_addr,
   1628  1.466  knakahar 		    rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1629  1.466  knakahar 		rxd->wrx_len = 0;
   1630  1.466  knakahar 		rxd->wrx_cksum = 0;
   1631  1.466  knakahar 		rxd->wrx_status = 0;
   1632  1.466  knakahar 		rxd->wrx_errors = 0;
   1633  1.466  knakahar 		rxd->wrx_special = 0;
   1634  1.466  knakahar 	}
   1635  1.388   msaitoh 	wm_cdrxsync(rxq, start, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   1636  1.352  knakahar 
   1637  1.356  knakahar 	CSR_WRITE(sc, rxq->rxq_rdt_reg, start);
   1638  1.352  knakahar }
   1639  1.352  knakahar 
   1640  1.352  knakahar /*
   1641  1.280   msaitoh  * Device driver interface functions and commonly used functions.
   1642  1.280   msaitoh  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
   1643  1.280   msaitoh  */
   1644  1.280   msaitoh 
   1645  1.280   msaitoh /* Lookup supported device table */
   1646    1.1   thorpej static const struct wm_product *
   1647    1.1   thorpej wm_lookup(const struct pci_attach_args *pa)
   1648    1.1   thorpej {
   1649    1.1   thorpej 	const struct wm_product *wmp;
   1650    1.1   thorpej 
   1651    1.1   thorpej 	for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
   1652    1.1   thorpej 		if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
   1653    1.1   thorpej 		    PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
   1654  1.194   msaitoh 			return wmp;
   1655    1.1   thorpej 	}
   1656  1.194   msaitoh 	return NULL;
   1657    1.1   thorpej }
   1658    1.1   thorpej 
   1659  1.280   msaitoh /* The match function (ca_match) */
   1660   1.47   thorpej static int
   1661  1.160  christos wm_match(device_t parent, cfdata_t cf, void *aux)
   1662    1.1   thorpej {
   1663    1.1   thorpej 	struct pci_attach_args *pa = aux;
   1664    1.1   thorpej 
   1665    1.1   thorpej 	if (wm_lookup(pa) != NULL)
   1666  1.194   msaitoh 		return 1;
   1667    1.1   thorpej 
   1668  1.194   msaitoh 	return 0;
   1669    1.1   thorpej }
   1670    1.1   thorpej 
   1671  1.280   msaitoh /* The attach function (ca_attach) */
   1672   1.47   thorpej static void
   1673  1.157    dyoung wm_attach(device_t parent, device_t self, void *aux)
   1674    1.1   thorpej {
   1675  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   1676    1.1   thorpej 	struct pci_attach_args *pa = aux;
   1677  1.182   msaitoh 	prop_dictionary_t dict;
   1678    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1679    1.1   thorpej 	pci_chipset_tag_t pc = pa->pa_pc;
   1680  1.340  knakahar 	int counts[PCI_INTR_TYPE_SIZE];
   1681  1.340  knakahar 	pci_intr_type_t max_type;
   1682  1.160  christos 	const char *eetype, *xname;
   1683    1.1   thorpej 	bus_space_tag_t memt;
   1684    1.1   thorpej 	bus_space_handle_t memh;
   1685  1.201   msaitoh 	bus_size_t memsize;
   1686    1.1   thorpej 	int memh_valid;
   1687  1.201   msaitoh 	int i, error;
   1688    1.1   thorpej 	const struct wm_product *wmp;
   1689  1.115   thorpej 	prop_data_t ea;
   1690  1.115   thorpej 	prop_number_t pn;
   1691    1.1   thorpej 	uint8_t enaddr[ETHER_ADDR_LEN];
   1692  1.513   msaitoh 	char buf[256];
   1693  1.325   msaitoh 	uint16_t cfg1, cfg2, swdpin, nvmword;
   1694    1.1   thorpej 	pcireg_t preg, memtype;
   1695  1.203   msaitoh 	uint16_t eeprom_data, apme_mask;
   1696  1.273   msaitoh 	bool force_clear_smbi;
   1697  1.292   msaitoh 	uint32_t link_mode;
   1698   1.44   thorpej 	uint32_t reg;
   1699    1.1   thorpej 
   1700  1.160  christos 	sc->sc_dev = self;
   1701  1.272     ozaki 	callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS);
   1702  1.429  knakahar 	sc->sc_core_stopping = false;
   1703    1.1   thorpej 
   1704  1.292   msaitoh 	wmp = wm_lookup(pa);
   1705  1.292   msaitoh #ifdef DIAGNOSTIC
   1706    1.1   thorpej 	if (wmp == NULL) {
   1707    1.1   thorpej 		printf("\n");
   1708    1.1   thorpej 		panic("wm_attach: impossible");
   1709    1.1   thorpej 	}
   1710  1.292   msaitoh #endif
   1711  1.292   msaitoh 	sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags);
   1712    1.1   thorpej 
   1713  1.123  jmcneill 	sc->sc_pc = pa->pa_pc;
   1714  1.123  jmcneill 	sc->sc_pcitag = pa->pa_tag;
   1715  1.123  jmcneill 
   1716   1.69   thorpej 	if (pci_dma64_available(pa))
   1717   1.69   thorpej 		sc->sc_dmat = pa->pa_dmat64;
   1718   1.69   thorpej 	else
   1719   1.69   thorpej 		sc->sc_dmat = pa->pa_dmat;
   1720    1.1   thorpej 
   1721  1.304   msaitoh 	sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id);
   1722  1.388   msaitoh 	sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag,PCI_CLASS_REG));
   1723  1.226  drochner 	pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1);
   1724    1.1   thorpej 
   1725    1.1   thorpej 	sc->sc_type = wmp->wmp_type;
   1726  1.424   msaitoh 
   1727  1.424   msaitoh 	/* Set default function pointers */
   1728  1.530   msaitoh 	sc->phy.acquire = sc->nvm.acquire = wm_get_null;
   1729  1.530   msaitoh 	sc->phy.release = sc->nvm.release = wm_put_null;
   1730  1.447   msaitoh 	sc->phy.reset_delay_us = (sc->sc_type >= WM_T_82571) ? 100 : 10000;
   1731  1.424   msaitoh 
   1732   1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
   1733  1.192   msaitoh 		if (sc->sc_rev < 2) {
   1734  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1735  1.160  christos 			    "i82542 must be at least rev. 2\n");
   1736    1.1   thorpej 			return;
   1737    1.1   thorpej 		}
   1738  1.192   msaitoh 		if (sc->sc_rev < 3)
   1739   1.11   thorpej 			sc->sc_type = WM_T_82542_2_0;
   1740    1.1   thorpej 	}
   1741    1.1   thorpej 
   1742  1.335   msaitoh 	/*
   1743  1.335   msaitoh 	 * Disable MSI for Errata:
   1744  1.335   msaitoh 	 * "Message Signaled Interrupt Feature May Corrupt Write Transactions"
   1745  1.335   msaitoh 	 *
   1746  1.335   msaitoh 	 *  82544: Errata 25
   1747  1.335   msaitoh 	 *  82540: Errata  6 (easy to reproduce device timeout)
   1748  1.335   msaitoh 	 *  82545: Errata  4 (easy to reproduce device timeout)
   1749  1.335   msaitoh 	 *  82546: Errata 26 (easy to reproduce device timeout)
   1750  1.335   msaitoh 	 *  82541: Errata  7 (easy to reproduce device timeout)
   1751  1.337   msaitoh 	 *
   1752  1.337   msaitoh 	 * "Byte Enables 2 and 3 are not set on MSI writes"
   1753  1.337   msaitoh 	 *
   1754  1.337   msaitoh 	 *  82571 & 82572: Errata 63
   1755  1.335   msaitoh 	 */
   1756  1.337   msaitoh 	if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571)
   1757  1.337   msaitoh 	    || (sc->sc_type == WM_T_82572))
   1758  1.335   msaitoh 		pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY;
   1759  1.335   msaitoh 
   1760  1.199   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   1761  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   1762  1.265   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   1763  1.265   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
   1764  1.203   msaitoh 		sc->sc_flags |= WM_F_NEWQUEUE;
   1765  1.199   msaitoh 
   1766  1.184   msaitoh 	/* Set device properties (mactype) */
   1767  1.182   msaitoh 	dict = device_properties(sc->sc_dev);
   1768  1.182   msaitoh 	prop_dictionary_set_uint32(dict, "mactype", sc->sc_type);
   1769  1.182   msaitoh 
   1770    1.1   thorpej 	/*
   1771   1.53   thorpej 	 * Map the device.  All devices support memory-mapped acccess,
   1772   1.53   thorpej 	 * and it is really required for normal operation.
   1773    1.1   thorpej 	 */
   1774    1.1   thorpej 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
   1775    1.1   thorpej 	switch (memtype) {
   1776    1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
   1777    1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
   1778    1.1   thorpej 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
   1779  1.201   msaitoh 		    memtype, 0, &memt, &memh, NULL, &memsize) == 0);
   1780    1.1   thorpej 		break;
   1781    1.1   thorpej 	default:
   1782    1.1   thorpej 		memh_valid = 0;
   1783  1.189   msaitoh 		break;
   1784    1.1   thorpej 	}
   1785    1.1   thorpej 
   1786    1.1   thorpej 	if (memh_valid) {
   1787    1.1   thorpej 		sc->sc_st = memt;
   1788    1.1   thorpej 		sc->sc_sh = memh;
   1789  1.201   msaitoh 		sc->sc_ss = memsize;
   1790    1.1   thorpej 	} else {
   1791  1.160  christos 		aprint_error_dev(sc->sc_dev,
   1792  1.160  christos 		    "unable to map device registers\n");
   1793    1.1   thorpej 		return;
   1794    1.1   thorpej 	}
   1795    1.1   thorpej 
   1796   1.53   thorpej 	/*
   1797   1.53   thorpej 	 * In addition, i82544 and later support I/O mapped indirect
   1798   1.53   thorpej 	 * register access.  It is not desirable (nor supported in
   1799   1.53   thorpej 	 * this driver) to use it for normal operation, though it is
   1800   1.53   thorpej 	 * required to work around bugs in some chip versions.
   1801   1.53   thorpej 	 */
   1802   1.53   thorpej 	if (sc->sc_type >= WM_T_82544) {
   1803   1.53   thorpej 		/* First we have to find the I/O BAR. */
   1804   1.53   thorpej 		for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
   1805  1.241   msaitoh 			memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
   1806  1.241   msaitoh 			if (memtype == PCI_MAPREG_TYPE_IO)
   1807   1.53   thorpej 				break;
   1808  1.241   msaitoh 			if (PCI_MAPREG_MEM_TYPE(memtype) ==
   1809  1.241   msaitoh 			    PCI_MAPREG_MEM_TYPE_64BIT)
   1810  1.241   msaitoh 				i += 4;	/* skip high bits, too */
   1811   1.53   thorpej 		}
   1812  1.241   msaitoh 		if (i < PCI_MAPREG_END) {
   1813   1.88    briggs 			/*
   1814  1.218   msaitoh 			 * We found PCI_MAPREG_TYPE_IO. Note that 82580
   1815  1.218   msaitoh 			 * (and newer?) chip has no PCI_MAPREG_TYPE_IO.
   1816  1.218   msaitoh 			 * It's no problem because newer chips has no this
   1817  1.218   msaitoh 			 * bug.
   1818  1.218   msaitoh 			 *
   1819   1.88    briggs 			 * The i8254x doesn't apparently respond when the
   1820   1.88    briggs 			 * I/O BAR is 0, which looks somewhat like it's not
   1821   1.88    briggs 			 * been configured.
   1822   1.88    briggs 			 */
   1823   1.88    briggs 			preg = pci_conf_read(pc, pa->pa_tag, i);
   1824   1.88    briggs 			if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
   1825  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1826  1.160  christos 				    "WARNING: I/O BAR at zero.\n");
   1827   1.88    briggs 			} else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
   1828   1.53   thorpej 					0, &sc->sc_iot, &sc->sc_ioh,
   1829  1.212  jakllsch 					NULL, &sc->sc_ios) == 0) {
   1830   1.88    briggs 				sc->sc_flags |= WM_F_IOH_VALID;
   1831   1.88    briggs 			} else {
   1832  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1833  1.160  christos 				    "WARNING: unable to map I/O space\n");
   1834   1.88    briggs 			}
   1835   1.88    briggs 		}
   1836   1.88    briggs 
   1837   1.53   thorpej 	}
   1838   1.53   thorpej 
   1839   1.11   thorpej 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
   1840    1.1   thorpej 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
   1841    1.1   thorpej 	preg |= PCI_COMMAND_MASTER_ENABLE;
   1842   1.11   thorpej 	if (sc->sc_type < WM_T_82542_2_1)
   1843    1.1   thorpej 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
   1844    1.1   thorpej 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
   1845    1.1   thorpej 
   1846  1.122  christos 	/* power up chip */
   1847  1.157    dyoung 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
   1848  1.122  christos 	    NULL)) && error != EOPNOTSUPP) {
   1849  1.160  christos 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
   1850  1.122  christos 		return;
   1851    1.1   thorpej 	}
   1852    1.1   thorpej 
   1853  1.365  knakahar 	wm_adjust_qnum(sc, pci_msix_count(pa->pa_pc, pa->pa_tag));
   1854  1.550   msaitoh 	/*
   1855  1.550   msaitoh 	 *  Don't use MSI-X if we can use only one queue to save interrupt
   1856  1.550   msaitoh 	 * resource.
   1857  1.550   msaitoh 	 */
   1858  1.550   msaitoh 	if (sc->sc_nqueues > 1) {
   1859  1.550   msaitoh 		max_type = PCI_INTR_TYPE_MSIX;
   1860  1.550   msaitoh 		/*
   1861  1.550   msaitoh 		 *  82583 has a MSI-X capability in the PCI configuration space
   1862  1.550   msaitoh 		 * but it doesn't support it. At least the document doesn't
   1863  1.550   msaitoh 		 * say anything about MSI-X.
   1864  1.550   msaitoh 		 */
   1865  1.550   msaitoh 		counts[PCI_INTR_TYPE_MSIX]
   1866  1.550   msaitoh 		    = (sc->sc_type == WM_T_82583) ? 0 : sc->sc_nqueues + 1;
   1867  1.550   msaitoh 	} else {
   1868  1.550   msaitoh 		max_type = PCI_INTR_TYPE_MSI;
   1869  1.550   msaitoh 		counts[PCI_INTR_TYPE_MSIX] = 0;
   1870  1.550   msaitoh 	}
   1871  1.365  knakahar 
   1872  1.340  knakahar 	/* Allocation settings */
   1873  1.340  knakahar 	counts[PCI_INTR_TYPE_MSI] = 1;
   1874  1.340  knakahar 	counts[PCI_INTR_TYPE_INTX] = 1;
   1875  1.508  knakahar 	/* overridden by disable flags */
   1876  1.508  knakahar 	if (wm_disable_msi != 0) {
   1877  1.508  knakahar 		counts[PCI_INTR_TYPE_MSI] = 0;
   1878  1.508  knakahar 		if (wm_disable_msix != 0) {
   1879  1.508  knakahar 			max_type = PCI_INTR_TYPE_INTX;
   1880  1.508  knakahar 			counts[PCI_INTR_TYPE_MSIX] = 0;
   1881  1.508  knakahar 		}
   1882  1.508  knakahar 	} else if (wm_disable_msix != 0) {
   1883  1.508  knakahar 		max_type = PCI_INTR_TYPE_MSI;
   1884  1.508  knakahar 		counts[PCI_INTR_TYPE_MSIX] = 0;
   1885  1.508  knakahar 	}
   1886  1.340  knakahar 
   1887  1.340  knakahar alloc_retry:
   1888  1.340  knakahar 	if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) {
   1889  1.340  knakahar 		aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n");
   1890  1.340  knakahar 		return;
   1891  1.340  knakahar 	}
   1892  1.340  knakahar 
   1893  1.416  knakahar 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) {
   1894  1.360  knakahar 		error = wm_setup_msix(sc);
   1895  1.360  knakahar 		if (error) {
   1896  1.360  knakahar 			pci_intr_release(pc, sc->sc_intrs,
   1897  1.360  knakahar 			    counts[PCI_INTR_TYPE_MSIX]);
   1898  1.360  knakahar 
   1899  1.360  knakahar 			/* Setup for MSI: Disable MSI-X */
   1900  1.360  knakahar 			max_type = PCI_INTR_TYPE_MSI;
   1901  1.360  knakahar 			counts[PCI_INTR_TYPE_MSI] = 1;
   1902  1.360  knakahar 			counts[PCI_INTR_TYPE_INTX] = 1;
   1903  1.360  knakahar 			goto alloc_retry;
   1904  1.335   msaitoh 		}
   1905  1.416  knakahar 	} else 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
   1906  1.375   msaitoh 		wm_adjust_qnum(sc, 0);	/* must not use multiqueue */
   1907  1.360  knakahar 		error = wm_setup_legacy(sc);
   1908  1.360  knakahar 		if (error) {
   1909  1.360  knakahar 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
   1910  1.360  knakahar 			    counts[PCI_INTR_TYPE_MSI]);
   1911  1.335   msaitoh 
   1912  1.360  knakahar 			/* The next try is for INTx: Disable MSI */
   1913  1.360  knakahar 			max_type = PCI_INTR_TYPE_INTX;
   1914  1.360  knakahar 			counts[PCI_INTR_TYPE_INTX] = 1;
   1915  1.360  knakahar 			goto alloc_retry;
   1916  1.360  knakahar 		}
   1917  1.340  knakahar 	} else {
   1918  1.375   msaitoh 		wm_adjust_qnum(sc, 0);	/* must not use multiqueue */
   1919  1.360  knakahar 		error = wm_setup_legacy(sc);
   1920  1.360  knakahar 		if (error) {
   1921  1.360  knakahar 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
   1922  1.360  knakahar 			    counts[PCI_INTR_TYPE_INTX]);
   1923  1.360  knakahar 			return;
   1924  1.335   msaitoh 		}
   1925  1.335   msaitoh 	}
   1926   1.52   thorpej 
   1927   1.52   thorpej 	/*
   1928  1.199   msaitoh 	 * Check the function ID (unit number of the chip).
   1929  1.199   msaitoh 	 */
   1930  1.199   msaitoh 	if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
   1931  1.199   msaitoh 	    || (sc->sc_type ==  WM_T_82571) || (sc->sc_type == WM_T_80003)
   1932  1.208   msaitoh 	    || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   1933  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   1934  1.265   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   1935  1.199   msaitoh 		sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
   1936  1.199   msaitoh 		    >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;
   1937  1.199   msaitoh 	else
   1938  1.199   msaitoh 		sc->sc_funcid = 0;
   1939  1.199   msaitoh 
   1940  1.199   msaitoh 	/*
   1941   1.52   thorpej 	 * Determine a few things about the bus we're connected to.
   1942   1.52   thorpej 	 */
   1943   1.52   thorpej 	if (sc->sc_type < WM_T_82543) {
   1944   1.52   thorpej 		/* We don't really know the bus characteristics here. */
   1945   1.52   thorpej 		sc->sc_bus_speed = 33;
   1946   1.73      tron 	} else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
   1947   1.73      tron 		/*
   1948   1.73      tron 		 * CSA (Communication Streaming Architecture) is about as fast
   1949   1.73      tron 		 * a 32-bit 66MHz PCI Bus.
   1950   1.73      tron 		 */
   1951   1.73      tron 		sc->sc_flags |= WM_F_CSA;
   1952   1.73      tron 		sc->sc_bus_speed = 66;
   1953  1.160  christos 		aprint_verbose_dev(sc->sc_dev,
   1954  1.160  christos 		    "Communication Streaming Architecture\n");
   1955   1.78   thorpej 		if (sc->sc_type == WM_T_82547) {
   1956  1.272     ozaki 			callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS);
   1957   1.78   thorpej 			callout_setfunc(&sc->sc_txfifo_ch,
   1958   1.78   thorpej 					wm_82547_txfifo_stall, sc);
   1959  1.160  christos 			aprint_verbose_dev(sc->sc_dev,
   1960  1.160  christos 			    "using 82547 Tx FIFO stall work-around\n");
   1961   1.78   thorpej 		}
   1962  1.116   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   1963  1.139    bouyer 		sc->sc_flags |= WM_F_PCIE;
   1964  1.167   msaitoh 		if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
   1965  1.190   msaitoh 		    && (sc->sc_type != WM_T_ICH10)
   1966  1.221   msaitoh 		    && (sc->sc_type != WM_T_PCH)
   1967  1.249   msaitoh 		    && (sc->sc_type != WM_T_PCH2)
   1968  1.392   msaitoh 		    && (sc->sc_type != WM_T_PCH_LPT)
   1969  1.392   msaitoh 		    && (sc->sc_type != WM_T_PCH_SPT)) {
   1970  1.221   msaitoh 			/* ICH* and PCH* have no PCIe capability registers */
   1971  1.199   msaitoh 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
   1972  1.199   msaitoh 				PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
   1973  1.199   msaitoh 				NULL) == 0)
   1974  1.199   msaitoh 				aprint_error_dev(sc->sc_dev,
   1975  1.199   msaitoh 				    "unable to find PCIe capability\n");
   1976  1.199   msaitoh 		}
   1977  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
   1978   1.73      tron 	} else {
   1979   1.52   thorpej 		reg = CSR_READ(sc, WMREG_STATUS);
   1980   1.52   thorpej 		if (reg & STATUS_BUS64)
   1981   1.52   thorpej 			sc->sc_flags |= WM_F_BUS64;
   1982  1.176   msaitoh 		if ((reg & STATUS_PCIX_MODE) != 0) {
   1983   1.54   thorpej 			pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
   1984   1.54   thorpej 
   1985   1.52   thorpej 			sc->sc_flags |= WM_F_PCIX;
   1986   1.54   thorpej 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
   1987  1.199   msaitoh 				PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0)
   1988  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1989  1.160  christos 				    "unable to find PCIX capability\n");
   1990   1.54   thorpej 			else if (sc->sc_type != WM_T_82545_3 &&
   1991   1.54   thorpej 				 sc->sc_type != WM_T_82546_3) {
   1992   1.54   thorpej 				/*
   1993   1.54   thorpej 				 * Work around a problem caused by the BIOS
   1994   1.54   thorpej 				 * setting the max memory read byte count
   1995   1.54   thorpej 				 * incorrectly.
   1996   1.54   thorpej 				 */
   1997   1.54   thorpej 				pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
   1998  1.248   msaitoh 				    sc->sc_pcixe_capoff + PCIX_CMD);
   1999   1.54   thorpej 				pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
   2000  1.248   msaitoh 				    sc->sc_pcixe_capoff + PCIX_STATUS);
   2001   1.54   thorpej 
   2002  1.388   msaitoh 				bytecnt = (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >>
   2003  1.248   msaitoh 				    PCIX_CMD_BYTECNT_SHIFT;
   2004  1.388   msaitoh 				maxb = (pcix_sts & PCIX_STATUS_MAXB_MASK) >>
   2005  1.248   msaitoh 				    PCIX_STATUS_MAXB_SHIFT;
   2006   1.54   thorpej 				if (bytecnt > maxb) {
   2007  1.160  christos 					aprint_verbose_dev(sc->sc_dev,
   2008  1.160  christos 					    "resetting PCI-X MMRBC: %d -> %d\n",
   2009   1.54   thorpej 					    512 << bytecnt, 512 << maxb);
   2010   1.54   thorpej 					pcix_cmd = (pcix_cmd &
   2011  1.248   msaitoh 					    ~PCIX_CMD_BYTECNT_MASK) |
   2012  1.248   msaitoh 					   (maxb << PCIX_CMD_BYTECNT_SHIFT);
   2013   1.54   thorpej 					pci_conf_write(pa->pa_pc, pa->pa_tag,
   2014  1.248   msaitoh 					    sc->sc_pcixe_capoff + PCIX_CMD,
   2015   1.54   thorpej 					    pcix_cmd);
   2016   1.54   thorpej 				}
   2017   1.54   thorpej 			}
   2018   1.54   thorpej 		}
   2019   1.52   thorpej 		/*
   2020   1.52   thorpej 		 * The quad port adapter is special; it has a PCIX-PCIX
   2021   1.52   thorpej 		 * bridge on the board, and can run the secondary bus at
   2022   1.52   thorpej 		 * a higher speed.
   2023   1.52   thorpej 		 */
   2024   1.52   thorpej 		if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
   2025   1.52   thorpej 			sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
   2026   1.52   thorpej 								      : 66;
   2027   1.52   thorpej 		} else if (sc->sc_flags & WM_F_PCIX) {
   2028   1.62   thorpej 			switch (reg & STATUS_PCIXSPD_MASK) {
   2029   1.52   thorpej 			case STATUS_PCIXSPD_50_66:
   2030   1.52   thorpej 				sc->sc_bus_speed = 66;
   2031   1.52   thorpej 				break;
   2032   1.52   thorpej 			case STATUS_PCIXSPD_66_100:
   2033   1.52   thorpej 				sc->sc_bus_speed = 100;
   2034   1.52   thorpej 				break;
   2035   1.52   thorpej 			case STATUS_PCIXSPD_100_133:
   2036   1.52   thorpej 				sc->sc_bus_speed = 133;
   2037   1.52   thorpej 				break;
   2038   1.52   thorpej 			default:
   2039  1.160  christos 				aprint_error_dev(sc->sc_dev,
   2040  1.158    cegger 				    "unknown PCIXSPD %d; assuming 66MHz\n",
   2041   1.62   thorpej 				    reg & STATUS_PCIXSPD_MASK);
   2042   1.52   thorpej 				sc->sc_bus_speed = 66;
   2043  1.189   msaitoh 				break;
   2044   1.52   thorpej 			}
   2045   1.52   thorpej 		} else
   2046   1.52   thorpej 			sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
   2047  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n",
   2048   1.52   thorpej 		    (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
   2049   1.52   thorpej 		    (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
   2050   1.52   thorpej 	}
   2051    1.1   thorpej 
   2052  1.552   msaitoh 	/* Disable ASPM L0s and/or L1 for workaround */
   2053  1.552   msaitoh 	wm_disable_aspm(sc);
   2054  1.552   msaitoh 
   2055  1.127    bouyer 	/* clear interesting stat counters */
   2056  1.127    bouyer 	CSR_READ(sc, WMREG_COLC);
   2057  1.127    bouyer 	CSR_READ(sc, WMREG_RXERRC);
   2058  1.127    bouyer 
   2059  1.424   msaitoh 	if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)
   2060  1.424   msaitoh 	    || (sc->sc_type >= WM_T_ICH8))
   2061  1.424   msaitoh 		sc->sc_ich_phymtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2062  1.423   msaitoh 	if (sc->sc_type >= WM_T_ICH8)
   2063  1.423   msaitoh 		sc->sc_ich_nvmmtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2064    1.1   thorpej 
   2065  1.423   msaitoh 	/* Set PHY, NVM mutex related stuff */
   2066  1.185   msaitoh 	switch (sc->sc_type) {
   2067  1.185   msaitoh 	case WM_T_82542_2_0:
   2068  1.185   msaitoh 	case WM_T_82542_2_1:
   2069  1.185   msaitoh 	case WM_T_82543:
   2070  1.185   msaitoh 	case WM_T_82544:
   2071  1.185   msaitoh 		/* Microwire */
   2072  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_uwire;
   2073  1.294   msaitoh 		sc->sc_nvm_wordsize = 64;
   2074  1.294   msaitoh 		sc->sc_nvm_addrbits = 6;
   2075  1.185   msaitoh 		break;
   2076  1.185   msaitoh 	case WM_T_82540:
   2077  1.185   msaitoh 	case WM_T_82545:
   2078  1.185   msaitoh 	case WM_T_82545_3:
   2079  1.185   msaitoh 	case WM_T_82546:
   2080  1.185   msaitoh 	case WM_T_82546_3:
   2081  1.185   msaitoh 		/* Microwire */
   2082  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_uwire;
   2083  1.185   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   2084  1.294   msaitoh 		if (reg & EECD_EE_SIZE) {
   2085  1.294   msaitoh 			sc->sc_nvm_wordsize = 256;
   2086  1.294   msaitoh 			sc->sc_nvm_addrbits = 8;
   2087  1.294   msaitoh 		} else {
   2088  1.294   msaitoh 			sc->sc_nvm_wordsize = 64;
   2089  1.294   msaitoh 			sc->sc_nvm_addrbits = 6;
   2090  1.294   msaitoh 		}
   2091  1.275   msaitoh 		sc->sc_flags |= WM_F_LOCK_EECD;
   2092  1.530   msaitoh 		sc->nvm.acquire = wm_get_eecd;
   2093  1.530   msaitoh 		sc->nvm.release = wm_put_eecd;
   2094  1.185   msaitoh 		break;
   2095  1.185   msaitoh 	case WM_T_82541:
   2096  1.185   msaitoh 	case WM_T_82541_2:
   2097  1.185   msaitoh 	case WM_T_82547:
   2098  1.185   msaitoh 	case WM_T_82547_2:
   2099  1.185   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   2100  1.532   msaitoh 		/*
   2101  1.532   msaitoh 		 * wm_nvm_set_addrbits_size_eecd() accesses SPI in it only
   2102  1.532   msaitoh 		 * on 8254[17], so set flags and functios before calling it.
   2103  1.532   msaitoh 		 */
   2104  1.532   msaitoh 		sc->sc_flags |= WM_F_LOCK_EECD;
   2105  1.532   msaitoh 		sc->nvm.acquire = wm_get_eecd;
   2106  1.532   msaitoh 		sc->nvm.release = wm_put_eecd;
   2107  1.185   msaitoh 		if (reg & EECD_EE_TYPE) {
   2108  1.185   msaitoh 			/* SPI */
   2109  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_spi;
   2110  1.294   msaitoh 			sc->sc_flags |= WM_F_EEPROM_SPI;
   2111  1.294   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2112  1.294   msaitoh 		} else {
   2113  1.185   msaitoh 			/* Microwire */
   2114  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_uwire;
   2115  1.294   msaitoh 			if ((reg & EECD_EE_ABITS) != 0) {
   2116  1.294   msaitoh 				sc->sc_nvm_wordsize = 256;
   2117  1.294   msaitoh 				sc->sc_nvm_addrbits = 8;
   2118  1.294   msaitoh 			} else {
   2119  1.294   msaitoh 				sc->sc_nvm_wordsize = 64;
   2120  1.294   msaitoh 				sc->sc_nvm_addrbits = 6;
   2121  1.294   msaitoh 			}
   2122  1.294   msaitoh 		}
   2123  1.185   msaitoh 		break;
   2124  1.185   msaitoh 	case WM_T_82571:
   2125  1.185   msaitoh 	case WM_T_82572:
   2126  1.185   msaitoh 		/* SPI */
   2127  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_eerd;
   2128  1.530   msaitoh 		/* Not use WM_F_LOCK_EECD because we use EERD */
   2129  1.294   msaitoh 		sc->sc_flags |= WM_F_EEPROM_SPI;
   2130  1.294   msaitoh 		wm_nvm_set_addrbits_size_eecd(sc);
   2131  1.424   msaitoh 		sc->phy.acquire = wm_get_swsm_semaphore;
   2132  1.424   msaitoh 		sc->phy.release = wm_put_swsm_semaphore;
   2133  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_82571;
   2134  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_82571;
   2135  1.185   msaitoh 		break;
   2136  1.185   msaitoh 	case WM_T_82573:
   2137  1.185   msaitoh 	case WM_T_82574:
   2138  1.185   msaitoh 	case WM_T_82583:
   2139  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_eerd;
   2140  1.530   msaitoh 		/* Not use WM_F_LOCK_EECD because we use EERD */
   2141  1.424   msaitoh 		if (sc->sc_type == WM_T_82573) {
   2142  1.424   msaitoh 			sc->phy.acquire = wm_get_swsm_semaphore;
   2143  1.424   msaitoh 			sc->phy.release = wm_put_swsm_semaphore;
   2144  1.530   msaitoh 			sc->nvm.acquire = wm_get_nvm_82571;
   2145  1.530   msaitoh 			sc->nvm.release = wm_put_nvm_82571;
   2146  1.424   msaitoh 		} else {
   2147  1.424   msaitoh 			/* Both PHY and NVM use the same semaphore. */
   2148  1.530   msaitoh 			sc->phy.acquire = sc->nvm.acquire
   2149  1.424   msaitoh 			    = wm_get_swfwhw_semaphore;
   2150  1.530   msaitoh 			sc->phy.release = sc->nvm.release
   2151  1.424   msaitoh 			    = wm_put_swfwhw_semaphore;
   2152  1.424   msaitoh 		}
   2153  1.294   msaitoh 		if (wm_nvm_is_onboard_eeprom(sc) == 0) {
   2154  1.185   msaitoh 			sc->sc_flags |= WM_F_EEPROM_FLASH;
   2155  1.294   msaitoh 			sc->sc_nvm_wordsize = 2048;
   2156  1.294   msaitoh 		} else {
   2157  1.185   msaitoh 			/* SPI */
   2158  1.294   msaitoh 			sc->sc_flags |= WM_F_EEPROM_SPI;
   2159  1.294   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2160  1.185   msaitoh 		}
   2161  1.185   msaitoh 		break;
   2162  1.199   msaitoh 	case WM_T_82575:
   2163  1.199   msaitoh 	case WM_T_82576:
   2164  1.199   msaitoh 	case WM_T_82580:
   2165  1.228   msaitoh 	case WM_T_I350:
   2166  1.278   msaitoh 	case WM_T_I354:
   2167  1.185   msaitoh 	case WM_T_80003:
   2168  1.185   msaitoh 		/* SPI */
   2169  1.294   msaitoh 		sc->sc_flags |= WM_F_EEPROM_SPI;
   2170  1.294   msaitoh 		wm_nvm_set_addrbits_size_eecd(sc);
   2171  1.530   msaitoh 		if((sc->sc_type == WM_T_80003)
   2172  1.530   msaitoh 		    || (sc->sc_nvm_wordsize < (1 << 15))) {
   2173  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_eerd;
   2174  1.530   msaitoh 			/* Don't use WM_F_LOCK_EECD because we use EERD */
   2175  1.530   msaitoh 		} else {
   2176  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_spi;
   2177  1.530   msaitoh 			sc->sc_flags |= WM_F_LOCK_EECD;
   2178  1.530   msaitoh 		}
   2179  1.424   msaitoh 		sc->phy.acquire = wm_get_phy_82575;
   2180  1.424   msaitoh 		sc->phy.release = wm_put_phy_82575;
   2181  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_80003;
   2182  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_80003;
   2183  1.185   msaitoh 		break;
   2184  1.185   msaitoh 	case WM_T_ICH8:
   2185  1.185   msaitoh 	case WM_T_ICH9:
   2186  1.185   msaitoh 	case WM_T_ICH10:
   2187  1.190   msaitoh 	case WM_T_PCH:
   2188  1.221   msaitoh 	case WM_T_PCH2:
   2189  1.249   msaitoh 	case WM_T_PCH_LPT:
   2190  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_ich8;
   2191  1.185   msaitoh 		/* FLASH */
   2192  1.530   msaitoh 		sc->sc_flags |= WM_F_EEPROM_FLASH;
   2193  1.294   msaitoh 		sc->sc_nvm_wordsize = 2048;
   2194  1.388   msaitoh 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,WM_ICH8_FLASH);
   2195  1.139    bouyer 		if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
   2196  1.336   msaitoh 		    &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) {
   2197  1.160  christos 			aprint_error_dev(sc->sc_dev,
   2198  1.160  christos 			    "can't map FLASH registers\n");
   2199  1.353  knakahar 			goto out;
   2200  1.139    bouyer 		}
   2201  1.185   msaitoh 		reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
   2202  1.185   msaitoh 		sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *
   2203  1.388   msaitoh 		    ICH_FLASH_SECTOR_SIZE;
   2204  1.199   msaitoh 		sc->sc_ich8_flash_bank_size =
   2205  1.199   msaitoh 		    ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
   2206  1.388   msaitoh 		sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK);
   2207  1.139    bouyer 		sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
   2208  1.139    bouyer 		sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
   2209  1.392   msaitoh 		sc->sc_flashreg_offset = 0;
   2210  1.424   msaitoh 		sc->phy.acquire = wm_get_swflag_ich8lan;
   2211  1.424   msaitoh 		sc->phy.release = wm_put_swflag_ich8lan;
   2212  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_ich8lan;
   2213  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_ich8lan;
   2214  1.392   msaitoh 		break;
   2215  1.392   msaitoh 	case WM_T_PCH_SPT:
   2216  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_spt;
   2217  1.392   msaitoh 		/* SPT has no GFPREG; flash registers mapped through BAR0 */
   2218  1.530   msaitoh 		sc->sc_flags |= WM_F_EEPROM_FLASH;
   2219  1.392   msaitoh 		sc->sc_flasht = sc->sc_st;
   2220  1.392   msaitoh 		sc->sc_flashh = sc->sc_sh;
   2221  1.392   msaitoh 		sc->sc_ich8_flash_base = 0;
   2222  1.392   msaitoh 		sc->sc_nvm_wordsize =
   2223  1.392   msaitoh 			(((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
   2224  1.392   msaitoh 			* NVM_SIZE_MULTIPLIER;
   2225  1.392   msaitoh 		/* It is size in bytes, we want words */
   2226  1.392   msaitoh 		sc->sc_nvm_wordsize /= 2;
   2227  1.392   msaitoh 		/* assume 2 banks */
   2228  1.392   msaitoh 		sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2;
   2229  1.392   msaitoh 		sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET;
   2230  1.424   msaitoh 		sc->phy.acquire = wm_get_swflag_ich8lan;
   2231  1.424   msaitoh 		sc->phy.release = wm_put_swflag_ich8lan;
   2232  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_ich8lan;
   2233  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_ich8lan;
   2234  1.185   msaitoh 		break;
   2235  1.247   msaitoh 	case WM_T_I210:
   2236  1.247   msaitoh 	case WM_T_I211:
   2237  1.533   msaitoh 		/* Allow a single clear of the SW semaphore on I210 and newer*/
   2238  1.533   msaitoh 		sc->sc_flags |= WM_F_WA_I210_CLSEM;
   2239  1.321   msaitoh 		if (wm_nvm_get_flash_presence_i210(sc)) {
   2240  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_eerd;
   2241  1.530   msaitoh 			/* Don't use WM_F_LOCK_EECD because we use EERD */
   2242  1.530   msaitoh 			sc->sc_flags |= WM_F_EEPROM_FLASH_HW;
   2243  1.321   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2244  1.321   msaitoh 		} else {
   2245  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_invm;
   2246  1.530   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVM;
   2247  1.321   msaitoh 			sc->sc_nvm_wordsize = INVM_SIZE;
   2248  1.321   msaitoh 		}
   2249  1.424   msaitoh 		sc->phy.acquire = wm_get_phy_82575;
   2250  1.424   msaitoh 		sc->phy.release = wm_put_phy_82575;
   2251  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_80003;
   2252  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_80003;
   2253  1.247   msaitoh 		break;
   2254  1.185   msaitoh 	default:
   2255  1.185   msaitoh 		break;
   2256   1.44   thorpej 	}
   2257  1.112     gavan 
   2258  1.273   msaitoh 	/* Ensure the SMBI bit is clear before first NVM or PHY access */
   2259  1.273   msaitoh 	switch (sc->sc_type) {
   2260  1.273   msaitoh 	case WM_T_82571:
   2261  1.273   msaitoh 	case WM_T_82572:
   2262  1.273   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM2);
   2263  1.310   msaitoh 		if ((reg & SWSM2_LOCK) == 0) {
   2264  1.273   msaitoh 			CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);
   2265  1.273   msaitoh 			force_clear_smbi = true;
   2266  1.273   msaitoh 		} else
   2267  1.273   msaitoh 			force_clear_smbi = false;
   2268  1.273   msaitoh 		break;
   2269  1.284   msaitoh 	case WM_T_82573:
   2270  1.284   msaitoh 	case WM_T_82574:
   2271  1.284   msaitoh 	case WM_T_82583:
   2272  1.284   msaitoh 		force_clear_smbi = true;
   2273  1.284   msaitoh 		break;
   2274  1.273   msaitoh 	default:
   2275  1.284   msaitoh 		force_clear_smbi = false;
   2276  1.273   msaitoh 		break;
   2277  1.273   msaitoh 	}
   2278  1.273   msaitoh 	if (force_clear_smbi) {
   2279  1.273   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   2280  1.284   msaitoh 		if ((reg & SWSM_SMBI) != 0)
   2281  1.273   msaitoh 			aprint_error_dev(sc->sc_dev,
   2282  1.273   msaitoh 			    "Please update the Bootagent\n");
   2283  1.273   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI);
   2284  1.273   msaitoh 	}
   2285  1.273   msaitoh 
   2286  1.112     gavan 	/*
   2287  1.112     gavan 	 * Defer printing the EEPROM type until after verifying the checksum
   2288  1.112     gavan 	 * This allows the EEPROM type to be printed correctly in the case
   2289  1.112     gavan 	 * that no EEPROM is attached.
   2290  1.112     gavan 	 */
   2291  1.185   msaitoh 	/*
   2292  1.185   msaitoh 	 * Validate the EEPROM checksum. If the checksum fails, flag
   2293  1.185   msaitoh 	 * this for later, so we can fail future reads from the EEPROM.
   2294  1.185   msaitoh 	 */
   2295  1.280   msaitoh 	if (wm_nvm_validate_checksum(sc)) {
   2296  1.169   msaitoh 		/*
   2297  1.185   msaitoh 		 * Read twice again because some PCI-e parts fail the
   2298  1.185   msaitoh 		 * first check due to the link being in sleep state.
   2299  1.169   msaitoh 		 */
   2300  1.280   msaitoh 		if (wm_nvm_validate_checksum(sc))
   2301  1.185   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVALID;
   2302  1.169   msaitoh 	}
   2303  1.185   msaitoh 
   2304  1.113     gavan 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   2305  1.328   msaitoh 		aprint_verbose_dev(sc->sc_dev, "No EEPROM");
   2306  1.294   msaitoh 	else {
   2307  1.294   msaitoh 		aprint_verbose_dev(sc->sc_dev, "%u words ",
   2308  1.294   msaitoh 		    sc->sc_nvm_wordsize);
   2309  1.321   msaitoh 		if (sc->sc_flags & WM_F_EEPROM_INVM)
   2310  1.328   msaitoh 			aprint_verbose("iNVM");
   2311  1.321   msaitoh 		else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW)
   2312  1.328   msaitoh 			aprint_verbose("FLASH(HW)");
   2313  1.321   msaitoh 		else if (sc->sc_flags & WM_F_EEPROM_FLASH)
   2314  1.328   msaitoh 			aprint_verbose("FLASH");
   2315  1.321   msaitoh 		else {
   2316  1.294   msaitoh 			if (sc->sc_flags & WM_F_EEPROM_SPI)
   2317  1.294   msaitoh 				eetype = "SPI";
   2318  1.294   msaitoh 			else
   2319  1.294   msaitoh 				eetype = "MicroWire";
   2320  1.328   msaitoh 			aprint_verbose("(%d address bits) %s EEPROM",
   2321  1.294   msaitoh 			    sc->sc_nvm_addrbits, eetype);
   2322  1.294   msaitoh 		}
   2323  1.112     gavan 	}
   2324  1.328   msaitoh 	wm_nvm_version(sc);
   2325  1.328   msaitoh 	aprint_verbose("\n");
   2326  1.112     gavan 
   2327  1.527   msaitoh 	/*
   2328  1.527   msaitoh 	 * XXX The first call of wm_gmii_setup_phytype. The result might be
   2329  1.527   msaitoh 	 * incorrect.
   2330  1.527   msaitoh 	 */
   2331  1.527   msaitoh 	wm_gmii_setup_phytype(sc, 0, 0);
   2332  1.527   msaitoh 
   2333  1.527   msaitoh 	/* Reset the chip to a known state. */
   2334  1.527   msaitoh 	wm_reset(sc);
   2335  1.527   msaitoh 
   2336  1.329   msaitoh 	/* Check for I21[01] PLL workaround */
   2337  1.329   msaitoh 	if (sc->sc_type == WM_T_I210)
   2338  1.329   msaitoh 		sc->sc_flags |= WM_F_PLL_WA_I210;
   2339  1.329   msaitoh 	if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) {
   2340  1.329   msaitoh 		/* NVM image release 3.25 has a workaround */
   2341  1.344   msaitoh 		if ((sc->sc_nvm_ver_major < 3)
   2342  1.329   msaitoh 		    || ((sc->sc_nvm_ver_major == 3)
   2343  1.344   msaitoh 			&& (sc->sc_nvm_ver_minor < 25))) {
   2344  1.329   msaitoh 			aprint_verbose_dev(sc->sc_dev,
   2345  1.329   msaitoh 			    "ROM image version %d.%d is older than 3.25\n",
   2346  1.329   msaitoh 			    sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor);
   2347  1.329   msaitoh 			sc->sc_flags |= WM_F_PLL_WA_I210;
   2348  1.329   msaitoh 		}
   2349  1.329   msaitoh 	}
   2350  1.329   msaitoh 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
   2351  1.329   msaitoh 		wm_pll_workaround_i210(sc);
   2352  1.329   msaitoh 
   2353  1.379   msaitoh 	wm_get_wakeup(sc);
   2354  1.446   msaitoh 
   2355  1.446   msaitoh 	/* Non-AMT based hardware can now take control from firmware */
   2356  1.446   msaitoh 	if ((sc->sc_flags & WM_F_HAS_AMT) == 0)
   2357  1.446   msaitoh 		wm_get_hw_control(sc);
   2358  1.379   msaitoh 
   2359  1.113     gavan 	/*
   2360  1.113     gavan 	 * Read the Ethernet address from the EEPROM, if not first found
   2361  1.113     gavan 	 * in device properties.
   2362  1.113     gavan 	 */
   2363  1.195    martin 	ea = prop_dictionary_get(dict, "mac-address");
   2364  1.115   thorpej 	if (ea != NULL) {
   2365  1.115   thorpej 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
   2366  1.115   thorpej 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
   2367  1.115   thorpej 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
   2368  1.115   thorpej 	} else {
   2369  1.210   msaitoh 		if (wm_read_mac_addr(sc, enaddr) != 0) {
   2370  1.160  christos 			aprint_error_dev(sc->sc_dev,
   2371  1.160  christos 			    "unable to read Ethernet address\n");
   2372  1.353  knakahar 			goto out;
   2373  1.210   msaitoh 		}
   2374   1.17   thorpej 	}
   2375   1.17   thorpej 
   2376  1.160  christos 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
   2377    1.1   thorpej 	    ether_sprintf(enaddr));
   2378    1.1   thorpej 
   2379    1.1   thorpej 	/*
   2380    1.1   thorpej 	 * Read the config info from the EEPROM, and set up various
   2381    1.1   thorpej 	 * bits in the control registers based on their contents.
   2382    1.1   thorpej 	 */
   2383  1.182   msaitoh 	pn = prop_dictionary_get(dict, "i82543-cfg1");
   2384  1.115   thorpej 	if (pn != NULL) {
   2385  1.115   thorpej 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2386  1.115   thorpej 		cfg1 = (uint16_t) prop_number_integer_value(pn);
   2387  1.115   thorpej 	} else {
   2388  1.293   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {
   2389  1.160  christos 			aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
   2390  1.353  knakahar 			goto out;
   2391  1.113     gavan 		}
   2392   1.51   thorpej 	}
   2393  1.115   thorpej 
   2394  1.182   msaitoh 	pn = prop_dictionary_get(dict, "i82543-cfg2");
   2395  1.115   thorpej 	if (pn != NULL) {
   2396  1.115   thorpej 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2397  1.115   thorpej 		cfg2 = (uint16_t) prop_number_integer_value(pn);
   2398  1.115   thorpej 	} else {
   2399  1.293   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) {
   2400  1.160  christos 			aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
   2401  1.353  knakahar 			goto out;
   2402  1.113     gavan 		}
   2403   1.51   thorpej 	}
   2404  1.115   thorpej 
   2405  1.203   msaitoh 	/* check for WM_F_WOL */
   2406  1.203   msaitoh 	switch (sc->sc_type) {
   2407  1.203   msaitoh 	case WM_T_82542_2_0:
   2408  1.203   msaitoh 	case WM_T_82542_2_1:
   2409  1.203   msaitoh 	case WM_T_82543:
   2410  1.203   msaitoh 		/* dummy? */
   2411  1.203   msaitoh 		eeprom_data = 0;
   2412  1.293   msaitoh 		apme_mask = NVM_CFG3_APME;
   2413  1.203   msaitoh 		break;
   2414  1.203   msaitoh 	case WM_T_82544:
   2415  1.293   msaitoh 		apme_mask = NVM_CFG2_82544_APM_EN;
   2416  1.203   msaitoh 		eeprom_data = cfg2;
   2417  1.203   msaitoh 		break;
   2418  1.203   msaitoh 	case WM_T_82546:
   2419  1.203   msaitoh 	case WM_T_82546_3:
   2420  1.203   msaitoh 	case WM_T_82571:
   2421  1.203   msaitoh 	case WM_T_82572:
   2422  1.203   msaitoh 	case WM_T_82573:
   2423  1.203   msaitoh 	case WM_T_82574:
   2424  1.203   msaitoh 	case WM_T_82583:
   2425  1.203   msaitoh 	case WM_T_80003:
   2426  1.203   msaitoh 	default:
   2427  1.293   msaitoh 		apme_mask = NVM_CFG3_APME;
   2428  1.293   msaitoh 		wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB
   2429  1.293   msaitoh 		    : NVM_OFF_CFG3_PORTA, 1, &eeprom_data);
   2430  1.203   msaitoh 		break;
   2431  1.203   msaitoh 	case WM_T_82575:
   2432  1.203   msaitoh 	case WM_T_82576:
   2433  1.203   msaitoh 	case WM_T_82580:
   2434  1.228   msaitoh 	case WM_T_I350:
   2435  1.265   msaitoh 	case WM_T_I354: /* XXX ok? */
   2436  1.203   msaitoh 	case WM_T_ICH8:
   2437  1.203   msaitoh 	case WM_T_ICH9:
   2438  1.203   msaitoh 	case WM_T_ICH10:
   2439  1.203   msaitoh 	case WM_T_PCH:
   2440  1.221   msaitoh 	case WM_T_PCH2:
   2441  1.249   msaitoh 	case WM_T_PCH_LPT:
   2442  1.392   msaitoh 	case WM_T_PCH_SPT:
   2443  1.228   msaitoh 		/* XXX The funcid should be checked on some devices */
   2444  1.203   msaitoh 		apme_mask = WUC_APME;
   2445  1.203   msaitoh 		eeprom_data = CSR_READ(sc, WMREG_WUC);
   2446  1.203   msaitoh 		break;
   2447  1.203   msaitoh 	}
   2448  1.203   msaitoh 
   2449  1.203   msaitoh 	/* Check for WM_F_WOL flag after the setting of the EEPROM stuff */
   2450  1.203   msaitoh 	if ((eeprom_data & apme_mask) != 0)
   2451  1.203   msaitoh 		sc->sc_flags |= WM_F_WOL;
   2452  1.203   msaitoh 
   2453  1.325   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) {
   2454  1.325   msaitoh 		/* Check NVM for autonegotiation */
   2455  1.325   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) {
   2456  1.325   msaitoh 			if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0)
   2457  1.325   msaitoh 				sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO;
   2458  1.325   msaitoh 		}
   2459  1.325   msaitoh 	}
   2460  1.325   msaitoh 
   2461  1.203   msaitoh 	/*
   2462  1.203   msaitoh 	 * XXX need special handling for some multiple port cards
   2463  1.203   msaitoh 	 * to disable a paticular port.
   2464  1.203   msaitoh 	 */
   2465  1.203   msaitoh 
   2466   1.51   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2467  1.182   msaitoh 		pn = prop_dictionary_get(dict, "i82543-swdpin");
   2468  1.115   thorpej 		if (pn != NULL) {
   2469  1.115   thorpej 			KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2470  1.115   thorpej 			swdpin = (uint16_t) prop_number_integer_value(pn);
   2471  1.115   thorpej 		} else {
   2472  1.293   msaitoh 			if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) {
   2473  1.160  christos 				aprint_error_dev(sc->sc_dev,
   2474  1.160  christos 				    "unable to read SWDPIN\n");
   2475  1.353  knakahar 				goto out;
   2476  1.113     gavan 			}
   2477   1.51   thorpej 		}
   2478   1.51   thorpej 	}
   2479    1.1   thorpej 
   2480  1.293   msaitoh 	if (cfg1 & NVM_CFG1_ILOS)
   2481    1.1   thorpej 		sc->sc_ctrl |= CTRL_ILOS;
   2482  1.325   msaitoh 
   2483  1.325   msaitoh 	/*
   2484  1.325   msaitoh 	 * XXX
   2485  1.325   msaitoh 	 * This code isn't correct because pin 2 and 3 are located
   2486  1.325   msaitoh 	 * in different position on newer chips. Check all datasheet.
   2487  1.325   msaitoh 	 *
   2488  1.325   msaitoh 	 * Until resolve this problem, check if a chip < 82580
   2489  1.325   msaitoh 	 */
   2490  1.325   msaitoh 	if (sc->sc_type <= WM_T_82580) {
   2491  1.325   msaitoh 		if (sc->sc_type >= WM_T_82544) {
   2492  1.325   msaitoh 			sc->sc_ctrl |=
   2493  1.325   msaitoh 			    ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
   2494  1.325   msaitoh 			    CTRL_SWDPIO_SHIFT;
   2495  1.325   msaitoh 			sc->sc_ctrl |=
   2496  1.325   msaitoh 			    ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
   2497  1.325   msaitoh 			    CTRL_SWDPINS_SHIFT;
   2498  1.325   msaitoh 		} else {
   2499  1.325   msaitoh 			sc->sc_ctrl |=
   2500  1.325   msaitoh 			    ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<
   2501  1.325   msaitoh 			    CTRL_SWDPIO_SHIFT;
   2502  1.325   msaitoh 		}
   2503  1.325   msaitoh 	}
   2504  1.325   msaitoh 
   2505  1.325   msaitoh 	/* XXX For other than 82580? */
   2506  1.325   msaitoh 	if (sc->sc_type == WM_T_82580) {
   2507  1.325   msaitoh 		wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword);
   2508  1.389   msaitoh 		if (nvmword & __BIT(13))
   2509  1.325   msaitoh 			sc->sc_ctrl |= CTRL_ILOS;
   2510    1.1   thorpej 	}
   2511    1.1   thorpej 
   2512    1.1   thorpej #if 0
   2513   1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2514  1.293   msaitoh 		if (cfg1 & NVM_CFG1_IPS0)
   2515    1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
   2516  1.293   msaitoh 		if (cfg1 & NVM_CFG1_IPS1)
   2517    1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
   2518    1.1   thorpej 		sc->sc_ctrl_ext |=
   2519  1.293   msaitoh 		    ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
   2520    1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
   2521    1.1   thorpej 		sc->sc_ctrl_ext |=
   2522  1.293   msaitoh 		    ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
   2523    1.1   thorpej 		    CTRL_EXT_SWDPINS_SHIFT;
   2524    1.1   thorpej 	} else {
   2525    1.1   thorpej 		sc->sc_ctrl_ext |=
   2526  1.293   msaitoh 		    ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) <<
   2527    1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
   2528    1.1   thorpej 	}
   2529    1.1   thorpej #endif
   2530    1.1   thorpej 
   2531    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2532    1.1   thorpej #if 0
   2533    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   2534    1.1   thorpej #endif
   2535    1.1   thorpej 
   2536  1.192   msaitoh 	if (sc->sc_type == WM_T_PCH) {
   2537  1.192   msaitoh 		uint16_t val;
   2538  1.192   msaitoh 
   2539  1.192   msaitoh 		/* Save the NVM K1 bit setting */
   2540  1.293   msaitoh 		wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val);
   2541  1.192   msaitoh 
   2542  1.293   msaitoh 		if ((val & NVM_K1_CONFIG_ENABLE) != 0)
   2543  1.192   msaitoh 			sc->sc_nvm_k1_enabled = 1;
   2544  1.192   msaitoh 		else
   2545  1.192   msaitoh 			sc->sc_nvm_k1_enabled = 0;
   2546  1.192   msaitoh 	}
   2547  1.192   msaitoh 
   2548  1.529   msaitoh 	/* Determine if we're GMII, TBI, SERDES or SGMII mode */
   2549  1.144   msaitoh 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
   2550  1.190   msaitoh 	    || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
   2551  1.249   msaitoh 	    || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
   2552  1.392   msaitoh 	    || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573
   2553  1.185   msaitoh 	    || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
   2554  1.529   msaitoh 		/* Copper only */
   2555  1.457   msaitoh 	} else if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   2556  1.457   msaitoh 	    || (sc->sc_type ==WM_T_82580) || (sc->sc_type ==WM_T_I350)
   2557  1.457   msaitoh 	    || (sc->sc_type ==WM_T_I354) || (sc->sc_type ==WM_T_I210)
   2558  1.457   msaitoh 	    || (sc->sc_type ==WM_T_I211)) {
   2559  1.457   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   2560  1.457   msaitoh 		link_mode = reg & CTRL_EXT_LINK_MODE_MASK;
   2561  1.457   msaitoh 		switch (link_mode) {
   2562  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_1000KX:
   2563  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "1000KX\n");
   2564  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_SERDES;
   2565  1.457   msaitoh 			break;
   2566  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_SGMII:
   2567  1.457   msaitoh 			if (wm_sgmii_uses_mdio(sc)) {
   2568  1.457   msaitoh 				aprint_verbose_dev(sc->sc_dev,
   2569  1.457   msaitoh 				    "SGMII(MDIO)\n");
   2570  1.457   msaitoh 				sc->sc_flags |= WM_F_SGMII;
   2571  1.457   msaitoh 				sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2572  1.199   msaitoh 				break;
   2573  1.457   msaitoh 			}
   2574  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n");
   2575  1.457   msaitoh 			/*FALLTHROUGH*/
   2576  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_PCIE_SERDES:
   2577  1.457   msaitoh 			sc->sc_mediatype = wm_sfp_get_media_type(sc);
   2578  1.457   msaitoh 			if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) {
   2579  1.457   msaitoh 				if (link_mode
   2580  1.457   msaitoh 				    == CTRL_EXT_LINK_MODE_SGMII) {
   2581  1.457   msaitoh 					sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2582  1.265   msaitoh 					sc->sc_flags |= WM_F_SGMII;
   2583  1.457   msaitoh 				} else {
   2584  1.457   msaitoh 					sc->sc_mediatype = WM_MEDIATYPE_SERDES;
   2585  1.292   msaitoh 					aprint_verbose_dev(sc->sc_dev,
   2586  1.292   msaitoh 					    "SERDES\n");
   2587  1.457   msaitoh 				}
   2588  1.457   msaitoh 				break;
   2589  1.457   msaitoh 			}
   2590  1.457   msaitoh 			if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   2591  1.457   msaitoh 				aprint_verbose_dev(sc->sc_dev, "SERDES\n");
   2592  1.292   msaitoh 
   2593  1.457   msaitoh 			/* Change current link mode setting */
   2594  1.457   msaitoh 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
   2595  1.457   msaitoh 			switch (sc->sc_mediatype) {
   2596  1.457   msaitoh 			case WM_MEDIATYPE_COPPER:
   2597  1.457   msaitoh 				reg |= CTRL_EXT_LINK_MODE_SGMII;
   2598  1.457   msaitoh 				break;
   2599  1.457   msaitoh 			case WM_MEDIATYPE_SERDES:
   2600  1.457   msaitoh 				reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES;
   2601  1.199   msaitoh 				break;
   2602  1.199   msaitoh 			default:
   2603  1.199   msaitoh 				break;
   2604  1.199   msaitoh 			}
   2605  1.292   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   2606  1.199   msaitoh 			break;
   2607  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_GMII:
   2608  1.199   msaitoh 		default:
   2609  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "Copper\n");
   2610  1.311   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2611  1.457   msaitoh 			break;
   2612  1.457   msaitoh 		}
   2613  1.457   msaitoh 
   2614  1.457   msaitoh 		reg &= ~CTRL_EXT_I2C_ENA;
   2615  1.457   msaitoh 		if ((sc->sc_flags & WM_F_SGMII) != 0)
   2616  1.457   msaitoh 			reg |= CTRL_EXT_I2C_ENA;
   2617  1.457   msaitoh 		else
   2618  1.457   msaitoh 			reg &= ~CTRL_EXT_I2C_ENA;
   2619  1.457   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   2620  1.457   msaitoh 	} else if (sc->sc_type < WM_T_82543 ||
   2621  1.457   msaitoh 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
   2622  1.457   msaitoh 		if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) {
   2623  1.457   msaitoh 			aprint_error_dev(sc->sc_dev,
   2624  1.457   msaitoh 			    "WARNING: TBIMODE set on 1000BASE-T product!\n");
   2625  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_FIBER;
   2626  1.457   msaitoh 		}
   2627  1.457   msaitoh 	} else {
   2628  1.457   msaitoh 		if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) {
   2629  1.457   msaitoh 			aprint_error_dev(sc->sc_dev,
   2630  1.457   msaitoh 			    "WARNING: TBIMODE clear on 1000BASE-X product!\n");
   2631  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2632  1.199   msaitoh 		}
   2633    1.1   thorpej 	}
   2634  1.513   msaitoh 	snprintb(buf, sizeof(buf), WM_FLAGS, sc->sc_flags);
   2635  1.513   msaitoh 	aprint_verbose_dev(sc->sc_dev, "%s\n", buf);
   2636    1.1   thorpej 
   2637  1.527   msaitoh 	/* Set device properties (macflags) */
   2638  1.527   msaitoh 	prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags);
   2639  1.527   msaitoh 
   2640  1.529   msaitoh 	/* Initialize the media structures accordingly. */
   2641  1.529   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)
   2642  1.529   msaitoh 		wm_gmii_mediainit(sc, wmp->wmp_product);
   2643  1.529   msaitoh 	else
   2644  1.529   msaitoh 		wm_tbi_mediainit(sc); /* All others */
   2645  1.529   msaitoh 
   2646    1.1   thorpej 	ifp = &sc->sc_ethercom.ec_if;
   2647  1.160  christos 	xname = device_xname(sc->sc_dev);
   2648  1.160  christos 	strlcpy(ifp->if_xname, xname, IFNAMSIZ);
   2649    1.1   thorpej 	ifp->if_softc = sc;
   2650    1.1   thorpej 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   2651  1.492  knakahar #ifdef WM_MPSAFE
   2652  1.543     ozaki 	ifp->if_extflags = IFEF_MPSAFE;
   2653  1.492  knakahar #endif
   2654    1.1   thorpej 	ifp->if_ioctl = wm_ioctl;
   2655  1.403  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   2656  1.232    bouyer 		ifp->if_start = wm_nq_start;
   2657  1.503  knakahar 		/*
   2658  1.503  knakahar 		 * When the number of CPUs is one and the controller can use
   2659  1.505  knakahar 		 * MSI-X, wm(4) use MSI-X but *does not* use multiqueue.
   2660  1.503  knakahar 		 * That is, wm(4) use two interrupts, one is used for Tx/Rx
   2661  1.503  knakahar 		 * and the other is used for link status changing.
   2662  1.503  knakahar 		 * In this situation, wm_nq_transmit() is disadvantageous
   2663  1.503  knakahar 		 * because of wm_select_txqueue() and pcq(9) overhead.
   2664  1.503  knakahar 		 */
   2665  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   2666  1.403  knakahar 			ifp->if_transmit = wm_nq_transmit;
   2667  1.454  knakahar 	} else {
   2668  1.232    bouyer 		ifp->if_start = wm_start;
   2669  1.503  knakahar 		/*
   2670  1.503  knakahar 		 * wm_transmit() has the same disadvantage as wm_transmit().
   2671  1.503  knakahar 		 */
   2672  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   2673  1.454  knakahar 			ifp->if_transmit = wm_transmit;
   2674  1.454  knakahar 	}
   2675    1.1   thorpej 	ifp->if_watchdog = wm_watchdog;
   2676    1.1   thorpej 	ifp->if_init = wm_init;
   2677    1.1   thorpej 	ifp->if_stop = wm_stop;
   2678   1.58     ragge 	IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
   2679    1.1   thorpej 	IFQ_SET_READY(&ifp->if_snd);
   2680    1.1   thorpej 
   2681  1.187   msaitoh 	/* Check for jumbo frame */
   2682  1.187   msaitoh 	switch (sc->sc_type) {
   2683  1.187   msaitoh 	case WM_T_82573:
   2684  1.187   msaitoh 		/* XXX limited to 9234 if ASPM is disabled */
   2685  1.325   msaitoh 		wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword);
   2686  1.325   msaitoh 		if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0)
   2687  1.187   msaitoh 			sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2688  1.187   msaitoh 		break;
   2689  1.187   msaitoh 	case WM_T_82571:
   2690  1.187   msaitoh 	case WM_T_82572:
   2691  1.187   msaitoh 	case WM_T_82574:
   2692  1.546   msaitoh 	case WM_T_82583:
   2693  1.199   msaitoh 	case WM_T_82575:
   2694  1.199   msaitoh 	case WM_T_82576:
   2695  1.199   msaitoh 	case WM_T_82580:
   2696  1.228   msaitoh 	case WM_T_I350:
   2697  1.546   msaitoh 	case WM_T_I354:
   2698  1.247   msaitoh 	case WM_T_I210:
   2699  1.247   msaitoh 	case WM_T_I211:
   2700  1.187   msaitoh 	case WM_T_80003:
   2701  1.187   msaitoh 	case WM_T_ICH9:
   2702  1.187   msaitoh 	case WM_T_ICH10:
   2703  1.221   msaitoh 	case WM_T_PCH2:	/* PCH2 supports 9K frame size */
   2704  1.249   msaitoh 	case WM_T_PCH_LPT:
   2705  1.392   msaitoh 	case WM_T_PCH_SPT:
   2706  1.187   msaitoh 		/* XXX limited to 9234 */
   2707  1.120   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2708  1.187   msaitoh 		break;
   2709  1.190   msaitoh 	case WM_T_PCH:
   2710  1.190   msaitoh 		/* XXX limited to 4096 */
   2711  1.190   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2712  1.190   msaitoh 		break;
   2713  1.187   msaitoh 	case WM_T_82542_2_0:
   2714  1.187   msaitoh 	case WM_T_82542_2_1:
   2715  1.187   msaitoh 	case WM_T_ICH8:
   2716  1.187   msaitoh 		/* No support for jumbo frame */
   2717  1.187   msaitoh 		break;
   2718  1.187   msaitoh 	default:
   2719  1.187   msaitoh 		/* ETHER_MAX_LEN_JUMBO */
   2720  1.187   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2721  1.187   msaitoh 		break;
   2722  1.187   msaitoh 	}
   2723   1.41       tls 
   2724  1.281   msaitoh 	/* If we're a i82543 or greater, we can support VLANs. */
   2725  1.233   msaitoh 	if (sc->sc_type >= WM_T_82543)
   2726    1.1   thorpej 		sc->sc_ethercom.ec_capabilities |=
   2727  1.172    darran 		    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
   2728    1.1   thorpej 
   2729    1.1   thorpej 	/*
   2730    1.1   thorpej 	 * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
   2731   1.11   thorpej 	 * on i82543 and later.
   2732    1.1   thorpej 	 */
   2733  1.130      yamt 	if (sc->sc_type >= WM_T_82543) {
   2734    1.1   thorpej 		ifp->if_capabilities |=
   2735  1.103      yamt 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
   2736  1.103      yamt 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   2737  1.107      yamt 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
   2738  1.107      yamt 		    IFCAP_CSUM_TCPv6_Tx |
   2739  1.107      yamt 		    IFCAP_CSUM_UDPv6_Tx;
   2740  1.130      yamt 	}
   2741  1.130      yamt 
   2742  1.130      yamt 	/*
   2743  1.130      yamt 	 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL.
   2744  1.130      yamt 	 *
   2745  1.130      yamt 	 *	82541GI (8086:1076) ... no
   2746  1.130      yamt 	 *	82572EI (8086:10b9) ... yes
   2747  1.130      yamt 	 */
   2748  1.130      yamt 	if (sc->sc_type >= WM_T_82571) {
   2749  1.130      yamt 		ifp->if_capabilities |=
   2750  1.130      yamt 		    IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
   2751  1.130      yamt 	}
   2752    1.1   thorpej 
   2753  1.198   msaitoh 	/*
   2754   1.99      matt 	 * If we're a i82544 or greater (except i82547), we can do
   2755   1.99      matt 	 * TCP segmentation offload.
   2756   1.99      matt 	 */
   2757  1.131      yamt 	if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) {
   2758   1.99      matt 		ifp->if_capabilities |= IFCAP_TSOv4;
   2759  1.131      yamt 	}
   2760  1.131      yamt 
   2761  1.131      yamt 	if (sc->sc_type >= WM_T_82571) {
   2762  1.131      yamt 		ifp->if_capabilities |= IFCAP_TSOv6;
   2763  1.131      yamt 	}
   2764   1.99      matt 
   2765  1.493  knakahar 	sc->sc_rx_process_limit = WM_RX_PROCESS_LIMIT_DEFAULT;
   2766  1.493  knakahar 	sc->sc_rx_intr_process_limit = WM_RX_INTR_PROCESS_LIMIT_DEFAULT;
   2767  1.493  knakahar 
   2768  1.272     ozaki #ifdef WM_MPSAFE
   2769  1.357  knakahar 	sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2770  1.272     ozaki #else
   2771  1.357  knakahar 	sc->sc_core_lock = NULL;
   2772  1.272     ozaki #endif
   2773  1.272     ozaki 
   2774  1.281   msaitoh 	/* Attach the interface. */
   2775  1.541   msaitoh 	error = if_initialize(ifp);
   2776  1.541   msaitoh 	if (error != 0) {
   2777  1.541   msaitoh 		aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n",
   2778  1.541   msaitoh 		    error);
   2779  1.541   msaitoh 		return; /* Error */
   2780  1.541   msaitoh 	}
   2781  1.391     ozaki 	sc->sc_ipq = if_percpuq_create(&sc->sc_ethercom.ec_if);
   2782    1.1   thorpej 	ether_ifattach(ifp, enaddr);
   2783  1.391     ozaki 	if_register(ifp);
   2784  1.213   msaitoh 	ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb);
   2785  1.289       tls 	rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET,
   2786  1.289       tls 			  RND_FLAG_DEFAULT);
   2787    1.1   thorpej 
   2788    1.1   thorpej #ifdef WM_EVENT_COUNTERS
   2789    1.1   thorpej 	/* Attach event counters. */
   2790    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
   2791  1.160  christos 	    NULL, xname, "linkintr");
   2792    1.1   thorpej 
   2793   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
   2794  1.160  christos 	    NULL, xname, "tx_xoff");
   2795   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
   2796  1.160  christos 	    NULL, xname, "tx_xon");
   2797   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
   2798  1.160  christos 	    NULL, xname, "rx_xoff");
   2799   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
   2800  1.160  christos 	    NULL, xname, "rx_xon");
   2801   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
   2802  1.160  christos 	    NULL, xname, "rx_macctl");
   2803    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
   2804    1.1   thorpej 
   2805  1.203   msaitoh 	if (pmf_device_register(self, wm_suspend, wm_resume))
   2806  1.180   tsutsui 		pmf_class_network_register(self, ifp);
   2807  1.180   tsutsui 	else
   2808  1.149  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
   2809  1.123  jmcneill 
   2810  1.290   msaitoh 	sc->sc_flags |= WM_F_ATTACHED;
   2811  1.353  knakahar  out:
   2812    1.1   thorpej 	return;
   2813    1.1   thorpej }
   2814    1.1   thorpej 
   2815  1.280   msaitoh /* The detach function (ca_detach) */
   2816  1.201   msaitoh static int
   2817  1.201   msaitoh wm_detach(device_t self, int flags __unused)
   2818  1.201   msaitoh {
   2819  1.201   msaitoh 	struct wm_softc *sc = device_private(self);
   2820  1.201   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2821  1.272     ozaki 	int i;
   2822  1.201   msaitoh 
   2823  1.290   msaitoh 	if ((sc->sc_flags & WM_F_ATTACHED) == 0)
   2824  1.290   msaitoh 		return 0;
   2825  1.290   msaitoh 
   2826  1.201   msaitoh 	/* Stop the interface. Callouts are stopped in it. */
   2827  1.201   msaitoh 	wm_stop(ifp, 1);
   2828  1.272     ozaki 
   2829  1.201   msaitoh 	pmf_device_deregister(self);
   2830  1.201   msaitoh 
   2831  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   2832  1.477  knakahar 	evcnt_detach(&sc->sc_ev_linkintr);
   2833  1.477  knakahar 
   2834  1.477  knakahar 	evcnt_detach(&sc->sc_ev_tx_xoff);
   2835  1.477  knakahar 	evcnt_detach(&sc->sc_ev_tx_xon);
   2836  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_xoff);
   2837  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_xon);
   2838  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_macctl);
   2839  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   2840  1.477  knakahar 
   2841  1.201   msaitoh 	/* Tell the firmware about the release */
   2842  1.357  knakahar 	WM_CORE_LOCK(sc);
   2843  1.201   msaitoh 	wm_release_manageability(sc);
   2844  1.212  jakllsch 	wm_release_hw_control(sc);
   2845  1.439   msaitoh 	wm_enable_wakeup(sc);
   2846  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   2847  1.201   msaitoh 
   2848  1.201   msaitoh 	mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
   2849  1.201   msaitoh 
   2850  1.201   msaitoh 	/* Delete all remaining media. */
   2851  1.201   msaitoh 	ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
   2852  1.201   msaitoh 
   2853  1.201   msaitoh 	ether_ifdetach(ifp);
   2854  1.201   msaitoh 	if_detach(ifp);
   2855  1.391     ozaki 	if_percpuq_destroy(sc->sc_ipq);
   2856  1.201   msaitoh 
   2857  1.246  christos 	/* Unload RX dmamaps and free mbufs */
   2858  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   2859  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   2860  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   2861  1.364  knakahar 		wm_rxdrain(rxq);
   2862  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   2863  1.364  knakahar 	}
   2864  1.272     ozaki 	/* Must unlock here */
   2865  1.201   msaitoh 
   2866  1.201   msaitoh 	/* Disestablish the interrupt handler */
   2867  1.335   msaitoh 	for (i = 0; i < sc->sc_nintrs; i++) {
   2868  1.335   msaitoh 		if (sc->sc_ihs[i] != NULL) {
   2869  1.335   msaitoh 			pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
   2870  1.335   msaitoh 			sc->sc_ihs[i] = NULL;
   2871  1.335   msaitoh 		}
   2872  1.201   msaitoh 	}
   2873  1.335   msaitoh 	pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs);
   2874  1.201   msaitoh 
   2875  1.396  knakahar 	wm_free_txrx_queues(sc);
   2876  1.396  knakahar 
   2877  1.212  jakllsch 	/* Unmap the registers */
   2878  1.201   msaitoh 	if (sc->sc_ss) {
   2879  1.201   msaitoh 		bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss);
   2880  1.201   msaitoh 		sc->sc_ss = 0;
   2881  1.201   msaitoh 	}
   2882  1.212  jakllsch 	if (sc->sc_ios) {
   2883  1.212  jakllsch 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
   2884  1.212  jakllsch 		sc->sc_ios = 0;
   2885  1.212  jakllsch 	}
   2886  1.336   msaitoh 	if (sc->sc_flashs) {
   2887  1.336   msaitoh 		bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs);
   2888  1.336   msaitoh 		sc->sc_flashs = 0;
   2889  1.336   msaitoh 	}
   2890  1.201   msaitoh 
   2891  1.357  knakahar 	if (sc->sc_core_lock)
   2892  1.357  knakahar 		mutex_obj_free(sc->sc_core_lock);
   2893  1.424   msaitoh 	if (sc->sc_ich_phymtx)
   2894  1.424   msaitoh 		mutex_obj_free(sc->sc_ich_phymtx);
   2895  1.423   msaitoh 	if (sc->sc_ich_nvmmtx)
   2896  1.423   msaitoh 		mutex_obj_free(sc->sc_ich_nvmmtx);
   2897  1.272     ozaki 
   2898  1.201   msaitoh 	return 0;
   2899  1.201   msaitoh }
   2900  1.201   msaitoh 
   2901  1.281   msaitoh static bool
   2902  1.281   msaitoh wm_suspend(device_t self, const pmf_qual_t *qual)
   2903  1.281   msaitoh {
   2904  1.281   msaitoh 	struct wm_softc *sc = device_private(self);
   2905  1.281   msaitoh 
   2906  1.281   msaitoh 	wm_release_manageability(sc);
   2907  1.281   msaitoh 	wm_release_hw_control(sc);
   2908  1.281   msaitoh 	wm_enable_wakeup(sc);
   2909  1.281   msaitoh 
   2910  1.281   msaitoh 	return true;
   2911  1.281   msaitoh }
   2912  1.281   msaitoh 
   2913  1.281   msaitoh static bool
   2914  1.281   msaitoh wm_resume(device_t self, const pmf_qual_t *qual)
   2915  1.281   msaitoh {
   2916  1.281   msaitoh 	struct wm_softc *sc = device_private(self);
   2917  1.281   msaitoh 
   2918  1.552   msaitoh 	/* Disable ASPM L0s and/or L1 for workaround */
   2919  1.552   msaitoh 	wm_disable_aspm(sc);
   2920  1.281   msaitoh 	wm_init_manageability(sc);
   2921  1.281   msaitoh 
   2922  1.281   msaitoh 	return true;
   2923  1.281   msaitoh }
   2924  1.281   msaitoh 
   2925    1.1   thorpej /*
   2926  1.281   msaitoh  * wm_watchdog:		[ifnet interface function]
   2927    1.1   thorpej  *
   2928  1.281   msaitoh  *	Watchdog timer handler.
   2929    1.1   thorpej  */
   2930  1.281   msaitoh static void
   2931  1.281   msaitoh wm_watchdog(struct ifnet *ifp)
   2932    1.1   thorpej {
   2933  1.403  knakahar 	int qid;
   2934  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   2935  1.403  knakahar 
   2936  1.405  knakahar 	for (qid = 0; qid < sc->sc_nqueues; qid++) {
   2937  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[qid].wmq_txq;
   2938  1.403  knakahar 
   2939  1.403  knakahar 		wm_watchdog_txq(ifp, txq);
   2940  1.403  knakahar 	}
   2941  1.403  knakahar 
   2942  1.403  knakahar 	/* Reset the interface. */
   2943  1.403  knakahar 	(void) wm_init(ifp);
   2944  1.403  knakahar 
   2945  1.403  knakahar 	/*
   2946  1.403  knakahar 	 * There are still some upper layer processing which call
   2947  1.503  knakahar 	 * ifp->if_start(). e.g. ALTQ or one CPU system
   2948  1.403  knakahar 	 */
   2949  1.403  knakahar 	/* Try to get more packets going. */
   2950  1.403  knakahar 	ifp->if_start(ifp);
   2951  1.403  knakahar }
   2952  1.403  knakahar 
   2953  1.403  knakahar static void
   2954  1.403  knakahar wm_watchdog_txq(struct ifnet *ifp, struct wm_txqueue *txq)
   2955  1.403  knakahar {
   2956  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   2957    1.1   thorpej 
   2958    1.1   thorpej 	/*
   2959  1.281   msaitoh 	 * Since we're using delayed interrupts, sweep up
   2960  1.281   msaitoh 	 * before we report an error.
   2961    1.1   thorpej 	 */
   2962  1.413     skrll 	mutex_enter(txq->txq_lock);
   2963  1.403  knakahar 	wm_txeof(sc, txq);
   2964  1.413     skrll 	mutex_exit(txq->txq_lock);
   2965  1.281   msaitoh 
   2966  1.356  knakahar 	if (txq->txq_free != WM_NTXDESC(txq)) {
   2967  1.281   msaitoh #ifdef WM_DEBUG
   2968  1.281   msaitoh 		int i, j;
   2969  1.281   msaitoh 		struct wm_txsoft *txs;
   2970  1.281   msaitoh #endif
   2971  1.281   msaitoh 		log(LOG_ERR,
   2972  1.281   msaitoh 		    "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
   2973  1.356  knakahar 		    device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree,
   2974  1.356  knakahar 		    txq->txq_next);
   2975  1.281   msaitoh 		ifp->if_oerrors++;
   2976  1.281   msaitoh #ifdef WM_DEBUG
   2977  1.366  knakahar 		for (i = txq->txq_sdirty; i != txq->txq_snext ;
   2978  1.356  knakahar 		    i = WM_NEXTTXS(txq, i)) {
   2979  1.366  knakahar 		    txs = &txq->txq_soft[i];
   2980  1.281   msaitoh 		    printf("txs %d tx %d -> %d\n",
   2981  1.281   msaitoh 			i, txs->txs_firstdesc, txs->txs_lastdesc);
   2982  1.281   msaitoh 		    for (j = txs->txs_firstdesc; ;
   2983  1.356  knakahar 			j = WM_NEXTTX(txq, j)) {
   2984  1.553  knakahar 			    if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   2985  1.553  knakahar 				    printf("\tdesc %d: 0x%" PRIx64 "\n", j,
   2986  1.553  knakahar 					txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
   2987  1.553  knakahar 				    printf("\t %#08x%08x\n",
   2988  1.553  knakahar 					txq->txq_nq_descs[j].nqtx_data.nqtxd_fields,
   2989  1.553  knakahar 					txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen);
   2990  1.553  knakahar 			    } else {
   2991  1.553  knakahar 				    printf("\tdesc %d: 0x%" PRIx64 "\n", j,
   2992  1.553  knakahar 					(uint64_t)txq->txq_descs[j].wtx_addr.wa_high << 32 |
   2993  1.553  knakahar 					txq->txq_descs[j].wtx_addr.wa_low);
   2994  1.553  knakahar 				    printf("\t %#04x%02x%02x%08x\n",
   2995  1.553  knakahar 					txq->txq_descs[j].wtx_fields.wtxu_vlan,
   2996  1.553  knakahar 					txq->txq_descs[j].wtx_fields.wtxu_options,
   2997  1.553  knakahar 					txq->txq_descs[j].wtx_fields.wtxu_status,
   2998  1.553  knakahar 					txq->txq_descs[j].wtx_cmdlen);
   2999  1.553  knakahar 			    }
   3000  1.281   msaitoh 			if (j == txs->txs_lastdesc)
   3001  1.281   msaitoh 				break;
   3002  1.281   msaitoh 			}
   3003  1.281   msaitoh 		}
   3004  1.281   msaitoh #endif
   3005  1.281   msaitoh 	}
   3006  1.281   msaitoh }
   3007    1.1   thorpej 
   3008  1.281   msaitoh /*
   3009  1.281   msaitoh  * wm_tick:
   3010  1.281   msaitoh  *
   3011  1.281   msaitoh  *	One second timer, used to check link status, sweep up
   3012  1.281   msaitoh  *	completed transmit jobs, etc.
   3013  1.281   msaitoh  */
   3014  1.281   msaitoh static void
   3015  1.281   msaitoh wm_tick(void *arg)
   3016  1.281   msaitoh {
   3017  1.281   msaitoh 	struct wm_softc *sc = arg;
   3018  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   3019  1.281   msaitoh #ifndef WM_MPSAFE
   3020  1.413     skrll 	int s = splnet();
   3021  1.281   msaitoh #endif
   3022   1.35   thorpej 
   3023  1.357  knakahar 	WM_CORE_LOCK(sc);
   3024   1.13   thorpej 
   3025  1.429  knakahar 	if (sc->sc_core_stopping)
   3026  1.281   msaitoh 		goto out;
   3027    1.1   thorpej 
   3028  1.281   msaitoh 	if (sc->sc_type >= WM_T_82542_2_1) {
   3029  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
   3030  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
   3031  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
   3032  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
   3033  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
   3034  1.107      yamt 	}
   3035    1.1   thorpej 
   3036  1.281   msaitoh 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
   3037  1.504  knakahar 	ifp->if_ierrors += 0ULL /* ensure quad_t */
   3038  1.281   msaitoh 	    + CSR_READ(sc, WMREG_CRCERRS)
   3039  1.281   msaitoh 	    + CSR_READ(sc, WMREG_ALGNERRC)
   3040  1.281   msaitoh 	    + CSR_READ(sc, WMREG_SYMERRC)
   3041  1.281   msaitoh 	    + CSR_READ(sc, WMREG_RXERRC)
   3042  1.281   msaitoh 	    + CSR_READ(sc, WMREG_SEC)
   3043  1.281   msaitoh 	    + CSR_READ(sc, WMREG_CEXTERR)
   3044  1.281   msaitoh 	    + CSR_READ(sc, WMREG_RLEC);
   3045  1.431  knakahar 	/*
   3046  1.431  knakahar 	 * WMREG_RNBC is incremented when there is no available buffers in host
   3047  1.431  knakahar 	 * memory. It does not mean the number of dropped packet. Because
   3048  1.431  knakahar 	 * ethernet controller can receive packets in such case if there is
   3049  1.431  knakahar 	 * space in phy's FIFO.
   3050  1.431  knakahar 	 *
   3051  1.431  knakahar 	 * If you want to know the nubmer of WMREG_RMBC, you should use such as
   3052  1.431  knakahar 	 * own EVCNT instead of if_iqdrops.
   3053  1.431  knakahar 	 */
   3054  1.431  knakahar 	ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC);
   3055   1.98   thorpej 
   3056  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   3057  1.281   msaitoh 		mii_tick(&sc->sc_mii);
   3058  1.325   msaitoh 	else if ((sc->sc_type >= WM_T_82575)
   3059  1.325   msaitoh 	    && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   3060  1.325   msaitoh 		wm_serdes_tick(sc);
   3061  1.281   msaitoh 	else
   3062  1.325   msaitoh 		wm_tbi_tick(sc);
   3063  1.131      yamt 
   3064  1.463  knakahar 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   3065  1.281   msaitoh out:
   3066  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   3067  1.281   msaitoh #ifndef WM_MPSAFE
   3068  1.281   msaitoh 	splx(s);
   3069  1.281   msaitoh #endif
   3070  1.281   msaitoh }
   3071   1.99      matt 
   3072  1.281   msaitoh static int
   3073  1.281   msaitoh wm_ifflags_cb(struct ethercom *ec)
   3074  1.281   msaitoh {
   3075  1.281   msaitoh 	struct ifnet *ifp = &ec->ec_if;
   3076  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   3077  1.281   msaitoh 	int rc = 0;
   3078   1.99      matt 
   3079  1.511   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3080  1.511   msaitoh 		device_xname(sc->sc_dev), __func__));
   3081  1.511   msaitoh 
   3082  1.357  knakahar 	WM_CORE_LOCK(sc);
   3083   1.99      matt 
   3084  1.418     skrll 	int change = ifp->if_flags ^ sc->sc_if_flags;
   3085  1.418     skrll 	sc->sc_if_flags = ifp->if_flags;
   3086   1.99      matt 
   3087  1.388   msaitoh 	if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
   3088  1.281   msaitoh 		rc = ENETRESET;
   3089  1.281   msaitoh 		goto out;
   3090  1.281   msaitoh 	}
   3091   1.99      matt 
   3092  1.281   msaitoh 	if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
   3093  1.281   msaitoh 		wm_set_filter(sc);
   3094  1.131      yamt 
   3095  1.281   msaitoh 	wm_set_vlan(sc);
   3096  1.131      yamt 
   3097  1.281   msaitoh out:
   3098  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   3099   1.99      matt 
   3100  1.281   msaitoh 	return rc;
   3101   1.75   thorpej }
   3102   1.75   thorpej 
   3103    1.1   thorpej /*
   3104  1.281   msaitoh  * wm_ioctl:		[ifnet interface function]
   3105   1.78   thorpej  *
   3106  1.281   msaitoh  *	Handle control requests from the operator.
   3107   1.78   thorpej  */
   3108  1.281   msaitoh static int
   3109  1.281   msaitoh wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
   3110   1.78   thorpej {
   3111  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   3112  1.281   msaitoh 	struct ifreq *ifr = (struct ifreq *) data;
   3113  1.281   msaitoh 	struct ifaddr *ifa = (struct ifaddr *)data;
   3114  1.281   msaitoh 	struct sockaddr_dl *sdl;
   3115  1.281   msaitoh 	int s, error;
   3116  1.281   msaitoh 
   3117  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3118  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3119  1.420   msaitoh 
   3120  1.272     ozaki #ifndef WM_MPSAFE
   3121   1.78   thorpej 	s = splnet();
   3122  1.272     ozaki #endif
   3123  1.281   msaitoh 	switch (cmd) {
   3124  1.281   msaitoh 	case SIOCSIFMEDIA:
   3125  1.281   msaitoh 	case SIOCGIFMEDIA:
   3126  1.357  knakahar 		WM_CORE_LOCK(sc);
   3127  1.281   msaitoh 		/* Flow control requires full-duplex mode. */
   3128  1.327   msaitoh 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
   3129  1.281   msaitoh 		    (ifr->ifr_media & IFM_FDX) == 0)
   3130  1.281   msaitoh 			ifr->ifr_media &= ~IFM_ETH_FMASK;
   3131  1.281   msaitoh 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
   3132  1.281   msaitoh 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
   3133  1.281   msaitoh 				/* We can do both TXPAUSE and RXPAUSE. */
   3134  1.281   msaitoh 				ifr->ifr_media |=
   3135  1.281   msaitoh 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   3136  1.281   msaitoh 			}
   3137  1.281   msaitoh 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
   3138  1.281   msaitoh 		}
   3139  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   3140  1.302     ozaki #ifdef WM_MPSAFE
   3141  1.302     ozaki 		s = splnet();
   3142  1.302     ozaki #endif
   3143  1.281   msaitoh 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
   3144  1.302     ozaki #ifdef WM_MPSAFE
   3145  1.302     ozaki 		splx(s);
   3146  1.302     ozaki #endif
   3147  1.281   msaitoh 		break;
   3148  1.281   msaitoh 	case SIOCINITIFADDR:
   3149  1.357  knakahar 		WM_CORE_LOCK(sc);
   3150  1.281   msaitoh 		if (ifa->ifa_addr->sa_family == AF_LINK) {
   3151  1.281   msaitoh 			sdl = satosdl(ifp->if_dl->ifa_addr);
   3152  1.281   msaitoh 			(void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
   3153  1.281   msaitoh 			    LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen);
   3154  1.281   msaitoh 			/* unicast address is first multicast entry */
   3155  1.281   msaitoh 			wm_set_filter(sc);
   3156  1.281   msaitoh 			error = 0;
   3157  1.357  knakahar 			WM_CORE_UNLOCK(sc);
   3158  1.281   msaitoh 			break;
   3159  1.281   msaitoh 		}
   3160  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   3161  1.281   msaitoh 		/*FALLTHROUGH*/
   3162  1.281   msaitoh 	default:
   3163  1.281   msaitoh #ifdef WM_MPSAFE
   3164  1.281   msaitoh 		s = splnet();
   3165  1.281   msaitoh #endif
   3166  1.281   msaitoh 		/* It may call wm_start, so unlock here */
   3167  1.281   msaitoh 		error = ether_ioctl(ifp, cmd, data);
   3168  1.281   msaitoh #ifdef WM_MPSAFE
   3169  1.281   msaitoh 		splx(s);
   3170  1.281   msaitoh #endif
   3171  1.281   msaitoh 		if (error != ENETRESET)
   3172  1.281   msaitoh 			break;
   3173   1.78   thorpej 
   3174  1.281   msaitoh 		error = 0;
   3175   1.78   thorpej 
   3176  1.281   msaitoh 		if (cmd == SIOCSIFCAP) {
   3177  1.281   msaitoh 			error = (*ifp->if_init)(ifp);
   3178  1.281   msaitoh 		} else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
   3179  1.281   msaitoh 			;
   3180  1.281   msaitoh 		else if (ifp->if_flags & IFF_RUNNING) {
   3181   1.78   thorpej 			/*
   3182  1.281   msaitoh 			 * Multicast list has changed; set the hardware filter
   3183  1.281   msaitoh 			 * accordingly.
   3184   1.78   thorpej 			 */
   3185  1.357  knakahar 			WM_CORE_LOCK(sc);
   3186  1.281   msaitoh 			wm_set_filter(sc);
   3187  1.357  knakahar 			WM_CORE_UNLOCK(sc);
   3188   1.78   thorpej 		}
   3189  1.281   msaitoh 		break;
   3190   1.78   thorpej 	}
   3191   1.78   thorpej 
   3192  1.272     ozaki #ifndef WM_MPSAFE
   3193   1.78   thorpej 	splx(s);
   3194  1.272     ozaki #endif
   3195  1.281   msaitoh 	return error;
   3196   1.78   thorpej }
   3197   1.78   thorpej 
   3198  1.281   msaitoh /* MAC address related */
   3199  1.281   msaitoh 
   3200  1.306   msaitoh /*
   3201  1.306   msaitoh  * Get the offset of MAC address and return it.
   3202  1.306   msaitoh  * If error occured, use offset 0.
   3203  1.306   msaitoh  */
   3204  1.306   msaitoh static uint16_t
   3205  1.281   msaitoh wm_check_alt_mac_addr(struct wm_softc *sc)
   3206  1.221   msaitoh {
   3207  1.281   msaitoh 	uint16_t myea[ETHER_ADDR_LEN / 2];
   3208  1.293   msaitoh 	uint16_t offset = NVM_OFF_MACADDR;
   3209  1.281   msaitoh 
   3210  1.281   msaitoh 	/* Try to read alternative MAC address pointer */
   3211  1.293   msaitoh 	if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0)
   3212  1.306   msaitoh 		return 0;
   3213  1.221   msaitoh 
   3214  1.306   msaitoh 	/* Check pointer if it's valid or not. */
   3215  1.306   msaitoh 	if ((offset == 0x0000) || (offset == 0xffff))
   3216  1.306   msaitoh 		return 0;
   3217  1.221   msaitoh 
   3218  1.306   msaitoh 	offset += NVM_OFF_MACADDR_82571(sc->sc_funcid);
   3219  1.281   msaitoh 	/*
   3220  1.281   msaitoh 	 * Check whether alternative MAC address is valid or not.
   3221  1.281   msaitoh 	 * Some cards have non 0xffff pointer but those don't use
   3222  1.281   msaitoh 	 * alternative MAC address in reality.
   3223  1.281   msaitoh 	 *
   3224  1.281   msaitoh 	 * Check whether the broadcast bit is set or not.
   3225  1.281   msaitoh 	 */
   3226  1.281   msaitoh 	if (wm_nvm_read(sc, offset, 1, myea) == 0)
   3227  1.281   msaitoh 		if (((myea[0] & 0xff) & 0x01) == 0)
   3228  1.306   msaitoh 			return offset; /* Found */
   3229  1.221   msaitoh 
   3230  1.306   msaitoh 	/* Not found */
   3231  1.306   msaitoh 	return 0;
   3232  1.221   msaitoh }
   3233  1.221   msaitoh 
   3234   1.78   thorpej static int
   3235  1.281   msaitoh wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)
   3236   1.78   thorpej {
   3237  1.281   msaitoh 	uint16_t myea[ETHER_ADDR_LEN / 2];
   3238  1.293   msaitoh 	uint16_t offset = NVM_OFF_MACADDR;
   3239  1.281   msaitoh 	int do_invert = 0;
   3240   1.78   thorpej 
   3241  1.281   msaitoh 	switch (sc->sc_type) {
   3242  1.281   msaitoh 	case WM_T_82580:
   3243  1.281   msaitoh 	case WM_T_I350:
   3244  1.281   msaitoh 	case WM_T_I354:
   3245  1.307   msaitoh 		/* EEPROM Top Level Partitioning */
   3246  1.307   msaitoh 		offset = NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + 0;
   3247  1.281   msaitoh 		break;
   3248  1.281   msaitoh 	case WM_T_82571:
   3249  1.281   msaitoh 	case WM_T_82575:
   3250  1.281   msaitoh 	case WM_T_82576:
   3251  1.281   msaitoh 	case WM_T_80003:
   3252  1.281   msaitoh 	case WM_T_I210:
   3253  1.281   msaitoh 	case WM_T_I211:
   3254  1.306   msaitoh 		offset = wm_check_alt_mac_addr(sc);
   3255  1.306   msaitoh 		if (offset == 0)
   3256  1.281   msaitoh 			if ((sc->sc_funcid & 0x01) == 1)
   3257  1.281   msaitoh 				do_invert = 1;
   3258  1.281   msaitoh 		break;
   3259  1.281   msaitoh 	default:
   3260  1.281   msaitoh 		if ((sc->sc_funcid & 0x01) == 1)
   3261  1.281   msaitoh 			do_invert = 1;
   3262  1.281   msaitoh 		break;
   3263  1.281   msaitoh 	}
   3264   1.78   thorpej 
   3265  1.424   msaitoh 	if (wm_nvm_read(sc, offset, sizeof(myea) / sizeof(myea[0]), myea) != 0)
   3266  1.281   msaitoh 		goto bad;
   3267   1.78   thorpej 
   3268  1.281   msaitoh 	enaddr[0] = myea[0] & 0xff;
   3269  1.281   msaitoh 	enaddr[1] = myea[0] >> 8;
   3270  1.281   msaitoh 	enaddr[2] = myea[1] & 0xff;
   3271  1.281   msaitoh 	enaddr[3] = myea[1] >> 8;
   3272  1.281   msaitoh 	enaddr[4] = myea[2] & 0xff;
   3273  1.281   msaitoh 	enaddr[5] = myea[2] >> 8;
   3274   1.78   thorpej 
   3275  1.281   msaitoh 	/*
   3276  1.281   msaitoh 	 * Toggle the LSB of the MAC address on the second port
   3277  1.281   msaitoh 	 * of some dual port cards.
   3278  1.281   msaitoh 	 */
   3279  1.281   msaitoh 	if (do_invert != 0)
   3280  1.281   msaitoh 		enaddr[5] ^= 1;
   3281   1.78   thorpej 
   3282  1.194   msaitoh 	return 0;
   3283  1.281   msaitoh 
   3284  1.281   msaitoh  bad:
   3285  1.281   msaitoh 	return -1;
   3286   1.78   thorpej }
   3287   1.78   thorpej 
   3288   1.78   thorpej /*
   3289  1.281   msaitoh  * wm_set_ral:
   3290    1.1   thorpej  *
   3291  1.281   msaitoh  *	Set an entery in the receive address list.
   3292    1.1   thorpej  */
   3293   1.47   thorpej static void
   3294  1.281   msaitoh wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
   3295  1.281   msaitoh {
   3296  1.514   msaitoh 	uint32_t ral_lo, ral_hi, addrl, addrh;
   3297  1.514   msaitoh 	uint32_t wlock_mac;
   3298  1.514   msaitoh 	int rv;
   3299  1.281   msaitoh 
   3300  1.281   msaitoh 	if (enaddr != NULL) {
   3301  1.281   msaitoh 		ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
   3302  1.281   msaitoh 		    (enaddr[3] << 24);
   3303  1.281   msaitoh 		ral_hi = enaddr[4] | (enaddr[5] << 8);
   3304  1.281   msaitoh 		ral_hi |= RAL_AV;
   3305  1.281   msaitoh 	} else {
   3306  1.281   msaitoh 		ral_lo = 0;
   3307  1.281   msaitoh 		ral_hi = 0;
   3308  1.281   msaitoh 	}
   3309  1.281   msaitoh 
   3310  1.514   msaitoh 	switch (sc->sc_type) {
   3311  1.514   msaitoh 	case WM_T_82542_2_0:
   3312  1.514   msaitoh 	case WM_T_82542_2_1:
   3313  1.514   msaitoh 	case WM_T_82543:
   3314  1.514   msaitoh 		CSR_WRITE(sc, WMREG_RAL(idx), ral_lo);
   3315  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3316  1.514   msaitoh 		CSR_WRITE(sc, WMREG_RAH(idx), ral_hi);
   3317  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3318  1.514   msaitoh 		break;
   3319  1.514   msaitoh 	case WM_T_PCH2:
   3320  1.514   msaitoh 	case WM_T_PCH_LPT:
   3321  1.514   msaitoh 	case WM_T_PCH_SPT:
   3322  1.514   msaitoh 		if (idx == 0) {
   3323  1.514   msaitoh 			CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
   3324  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3325  1.514   msaitoh 			CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
   3326  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3327  1.514   msaitoh 			return;
   3328  1.514   msaitoh 		}
   3329  1.514   msaitoh 		if (sc->sc_type != WM_T_PCH2) {
   3330  1.514   msaitoh 			wlock_mac = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM),
   3331  1.514   msaitoh 			    FWSM_WLOCK_MAC);
   3332  1.514   msaitoh 			addrl = WMREG_SHRAL(idx - 1);
   3333  1.514   msaitoh 			addrh = WMREG_SHRAH(idx - 1);
   3334  1.514   msaitoh 		} else {
   3335  1.514   msaitoh 			wlock_mac = 0;
   3336  1.514   msaitoh 			addrl = WMREG_PCH_LPT_SHRAL(idx - 1);
   3337  1.514   msaitoh 			addrh = WMREG_PCH_LPT_SHRAH(idx - 1);
   3338  1.514   msaitoh 		}
   3339  1.514   msaitoh 
   3340  1.514   msaitoh 		if ((wlock_mac == 0) || (idx <= wlock_mac)) {
   3341  1.514   msaitoh 			rv = wm_get_swflag_ich8lan(sc);
   3342  1.514   msaitoh 			if (rv != 0)
   3343  1.514   msaitoh 				return;
   3344  1.514   msaitoh 			CSR_WRITE(sc, addrl, ral_lo);
   3345  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3346  1.514   msaitoh 			CSR_WRITE(sc, addrh, ral_hi);
   3347  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3348  1.514   msaitoh 			wm_put_swflag_ich8lan(sc);
   3349  1.514   msaitoh 		}
   3350  1.514   msaitoh 
   3351  1.514   msaitoh 		break;
   3352  1.514   msaitoh 	default:
   3353  1.514   msaitoh 		CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
   3354  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3355  1.514   msaitoh 		CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
   3356  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3357  1.514   msaitoh 		break;
   3358  1.281   msaitoh 	}
   3359  1.281   msaitoh }
   3360  1.281   msaitoh 
   3361  1.281   msaitoh /*
   3362  1.281   msaitoh  * wm_mchash:
   3363  1.281   msaitoh  *
   3364  1.281   msaitoh  *	Compute the hash of the multicast address for the 4096-bit
   3365  1.281   msaitoh  *	multicast filter.
   3366  1.281   msaitoh  */
   3367  1.281   msaitoh static uint32_t
   3368  1.281   msaitoh wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
   3369    1.1   thorpej {
   3370  1.281   msaitoh 	static const int lo_shift[4] = { 4, 3, 2, 0 };
   3371  1.281   msaitoh 	static const int hi_shift[4] = { 4, 5, 6, 8 };
   3372  1.281   msaitoh 	static const int ich8_lo_shift[4] = { 6, 5, 4, 2 };
   3373  1.281   msaitoh 	static const int ich8_hi_shift[4] = { 2, 3, 4, 6 };
   3374  1.281   msaitoh 	uint32_t hash;
   3375  1.281   msaitoh 
   3376  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3377  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3378  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   3379  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT)) {
   3380  1.281   msaitoh 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
   3381  1.281   msaitoh 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
   3382  1.281   msaitoh 		return (hash & 0x3ff);
   3383  1.281   msaitoh 	}
   3384  1.281   msaitoh 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
   3385  1.281   msaitoh 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
   3386  1.272     ozaki 
   3387  1.281   msaitoh 	return (hash & 0xfff);
   3388  1.272     ozaki }
   3389  1.272     ozaki 
   3390  1.281   msaitoh /*
   3391  1.281   msaitoh  * wm_set_filter:
   3392  1.281   msaitoh  *
   3393  1.281   msaitoh  *	Set up the receive filter.
   3394  1.281   msaitoh  */
   3395  1.272     ozaki static void
   3396  1.281   msaitoh wm_set_filter(struct wm_softc *sc)
   3397  1.272     ozaki {
   3398  1.281   msaitoh 	struct ethercom *ec = &sc->sc_ethercom;
   3399  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   3400  1.281   msaitoh 	struct ether_multi *enm;
   3401  1.281   msaitoh 	struct ether_multistep step;
   3402  1.281   msaitoh 	bus_addr_t mta_reg;
   3403  1.281   msaitoh 	uint32_t hash, reg, bit;
   3404  1.390   msaitoh 	int i, size, ralmax;
   3405  1.281   msaitoh 
   3406  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3407  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3408  1.420   msaitoh 
   3409  1.281   msaitoh 	if (sc->sc_type >= WM_T_82544)
   3410  1.281   msaitoh 		mta_reg = WMREG_CORDOVA_MTA;
   3411  1.281   msaitoh 	else
   3412  1.281   msaitoh 		mta_reg = WMREG_MTA;
   3413    1.1   thorpej 
   3414  1.281   msaitoh 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
   3415  1.272     ozaki 
   3416  1.281   msaitoh 	if (ifp->if_flags & IFF_BROADCAST)
   3417  1.281   msaitoh 		sc->sc_rctl |= RCTL_BAM;
   3418  1.281   msaitoh 	if (ifp->if_flags & IFF_PROMISC) {
   3419  1.281   msaitoh 		sc->sc_rctl |= RCTL_UPE;
   3420  1.281   msaitoh 		goto allmulti;
   3421  1.281   msaitoh 	}
   3422    1.1   thorpej 
   3423    1.1   thorpej 	/*
   3424  1.281   msaitoh 	 * Set the station address in the first RAL slot, and
   3425  1.281   msaitoh 	 * clear the remaining slots.
   3426    1.1   thorpej 	 */
   3427  1.281   msaitoh 	if (sc->sc_type == WM_T_ICH8)
   3428  1.281   msaitoh 		size = WM_RAL_TABSIZE_ICH8 -1;
   3429  1.281   msaitoh 	else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10)
   3430  1.386   msaitoh 	    || (sc->sc_type == WM_T_PCH))
   3431  1.281   msaitoh 		size = WM_RAL_TABSIZE_ICH8;
   3432  1.386   msaitoh 	else if (sc->sc_type == WM_T_PCH2)
   3433  1.386   msaitoh 		size = WM_RAL_TABSIZE_PCH2;
   3434  1.392   msaitoh 	else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT))
   3435  1.386   msaitoh 		size = WM_RAL_TABSIZE_PCH_LPT;
   3436  1.281   msaitoh 	else if (sc->sc_type == WM_T_82575)
   3437  1.281   msaitoh 		size = WM_RAL_TABSIZE_82575;
   3438  1.281   msaitoh 	else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580))
   3439  1.281   msaitoh 		size = WM_RAL_TABSIZE_82576;
   3440  1.281   msaitoh 	else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   3441  1.281   msaitoh 		size = WM_RAL_TABSIZE_I350;
   3442  1.281   msaitoh 	else
   3443  1.281   msaitoh 		size = WM_RAL_TABSIZE;
   3444  1.281   msaitoh 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
   3445  1.386   msaitoh 
   3446  1.392   msaitoh 	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
   3447  1.386   msaitoh 		i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
   3448  1.386   msaitoh 		switch (i) {
   3449  1.386   msaitoh 		case 0:
   3450  1.386   msaitoh 			/* We can use all entries */
   3451  1.390   msaitoh 			ralmax = size;
   3452  1.386   msaitoh 			break;
   3453  1.386   msaitoh 		case 1:
   3454  1.386   msaitoh 			/* Only RAR[0] */
   3455  1.390   msaitoh 			ralmax = 1;
   3456  1.386   msaitoh 			break;
   3457  1.386   msaitoh 		default:
   3458  1.386   msaitoh 			/* available SHRA + RAR[0] */
   3459  1.390   msaitoh 			ralmax = i + 1;
   3460  1.386   msaitoh 		}
   3461  1.386   msaitoh 	} else
   3462  1.390   msaitoh 		ralmax = size;
   3463  1.386   msaitoh 	for (i = 1; i < size; i++) {
   3464  1.390   msaitoh 		if (i < ralmax)
   3465  1.386   msaitoh 			wm_set_ral(sc, NULL, i);
   3466  1.386   msaitoh 	}
   3467    1.1   thorpej 
   3468  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3469  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3470  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   3471  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT))
   3472  1.281   msaitoh 		size = WM_ICH8_MC_TABSIZE;
   3473  1.281   msaitoh 	else
   3474  1.281   msaitoh 		size = WM_MC_TABSIZE;
   3475  1.281   msaitoh 	/* Clear out the multicast table. */
   3476  1.515   msaitoh 	for (i = 0; i < size; i++) {
   3477  1.281   msaitoh 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
   3478  1.515   msaitoh 		CSR_WRITE_FLUSH(sc);
   3479  1.515   msaitoh 	}
   3480    1.1   thorpej 
   3481  1.460     ozaki 	ETHER_LOCK(ec);
   3482  1.281   msaitoh 	ETHER_FIRST_MULTI(step, ec, enm);
   3483  1.281   msaitoh 	while (enm != NULL) {
   3484  1.281   msaitoh 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   3485  1.460     ozaki 			ETHER_UNLOCK(ec);
   3486  1.281   msaitoh 			/*
   3487  1.281   msaitoh 			 * We must listen to a range of multicast addresses.
   3488  1.281   msaitoh 			 * For now, just accept all multicasts, rather than
   3489  1.281   msaitoh 			 * trying to set only those filter bits needed to match
   3490  1.281   msaitoh 			 * the range.  (At this time, the only use of address
   3491  1.281   msaitoh 			 * ranges is for IP multicast routing, for which the
   3492  1.281   msaitoh 			 * range is big enough to require all bits set.)
   3493  1.281   msaitoh 			 */
   3494  1.281   msaitoh 			goto allmulti;
   3495    1.1   thorpej 		}
   3496    1.1   thorpej 
   3497  1.281   msaitoh 		hash = wm_mchash(sc, enm->enm_addrlo);
   3498  1.272     ozaki 
   3499  1.281   msaitoh 		reg = (hash >> 5);
   3500  1.281   msaitoh 		if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3501  1.281   msaitoh 		    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3502  1.281   msaitoh 		    || (sc->sc_type == WM_T_PCH2)
   3503  1.392   msaitoh 		    || (sc->sc_type == WM_T_PCH_LPT)
   3504  1.392   msaitoh 		    || (sc->sc_type == WM_T_PCH_SPT))
   3505  1.281   msaitoh 			reg &= 0x1f;
   3506  1.281   msaitoh 		else
   3507  1.281   msaitoh 			reg &= 0x7f;
   3508  1.281   msaitoh 		bit = hash & 0x1f;
   3509  1.272     ozaki 
   3510  1.281   msaitoh 		hash = CSR_READ(sc, mta_reg + (reg << 2));
   3511  1.281   msaitoh 		hash |= 1U << bit;
   3512    1.1   thorpej 
   3513  1.382  christos 		if (sc->sc_type == WM_T_82544 && (reg & 1) != 0) {
   3514  1.387   msaitoh 			/*
   3515  1.387   msaitoh 			 * 82544 Errata 9: Certain register cannot be written
   3516  1.387   msaitoh 			 * with particular alignments in PCI-X bus operation
   3517  1.387   msaitoh 			 * (FCAH, MTA and VFTA).
   3518  1.387   msaitoh 			 */
   3519  1.281   msaitoh 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
   3520  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   3521  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3522  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
   3523  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3524  1.515   msaitoh 		} else {
   3525  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   3526  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3527  1.515   msaitoh 		}
   3528   1.99      matt 
   3529  1.281   msaitoh 		ETHER_NEXT_MULTI(step, enm);
   3530  1.281   msaitoh 	}
   3531  1.460     ozaki 	ETHER_UNLOCK(ec);
   3532   1.99      matt 
   3533  1.281   msaitoh 	ifp->if_flags &= ~IFF_ALLMULTI;
   3534  1.281   msaitoh 	goto setit;
   3535    1.1   thorpej 
   3536  1.281   msaitoh  allmulti:
   3537  1.281   msaitoh 	ifp->if_flags |= IFF_ALLMULTI;
   3538  1.281   msaitoh 	sc->sc_rctl |= RCTL_MPE;
   3539   1.80   thorpej 
   3540  1.281   msaitoh  setit:
   3541  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
   3542  1.281   msaitoh }
   3543    1.1   thorpej 
   3544  1.281   msaitoh /* Reset and init related */
   3545   1.78   thorpej 
   3546  1.281   msaitoh static void
   3547  1.281   msaitoh wm_set_vlan(struct wm_softc *sc)
   3548  1.281   msaitoh {
   3549  1.392   msaitoh 
   3550  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3551  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3552  1.420   msaitoh 
   3553  1.281   msaitoh 	/* Deal with VLAN enables. */
   3554  1.281   msaitoh 	if (VLAN_ATTACHED(&sc->sc_ethercom))
   3555  1.281   msaitoh 		sc->sc_ctrl |= CTRL_VME;
   3556  1.281   msaitoh 	else
   3557  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_VME;
   3558    1.1   thorpej 
   3559  1.281   msaitoh 	/* Write the control registers. */
   3560  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3561  1.281   msaitoh }
   3562    1.1   thorpej 
   3563  1.281   msaitoh static void
   3564  1.281   msaitoh wm_set_pcie_completion_timeout(struct wm_softc *sc)
   3565  1.281   msaitoh {
   3566  1.281   msaitoh 	uint32_t gcr;
   3567  1.281   msaitoh 	pcireg_t ctrl2;
   3568    1.1   thorpej 
   3569  1.281   msaitoh 	gcr = CSR_READ(sc, WMREG_GCR);
   3570    1.4   thorpej 
   3571  1.281   msaitoh 	/* Only take action if timeout value is defaulted to 0 */
   3572  1.281   msaitoh 	if ((gcr & GCR_CMPL_TMOUT_MASK) != 0)
   3573  1.281   msaitoh 		goto out;
   3574    1.1   thorpej 
   3575  1.281   msaitoh 	if ((gcr & GCR_CAP_VER2) == 0) {
   3576  1.281   msaitoh 		gcr |= GCR_CMPL_TMOUT_10MS;
   3577  1.281   msaitoh 		goto out;
   3578  1.281   msaitoh 	}
   3579    1.6   thorpej 
   3580  1.281   msaitoh 	ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   3581  1.281   msaitoh 	    sc->sc_pcixe_capoff + PCIE_DCSR2);
   3582  1.281   msaitoh 	ctrl2 |= WM_PCIE_DCSR2_16MS;
   3583  1.281   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   3584  1.281   msaitoh 	    sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2);
   3585   1.81   thorpej 
   3586  1.281   msaitoh out:
   3587  1.281   msaitoh 	/* Disable completion timeout resend */
   3588  1.281   msaitoh 	gcr &= ~GCR_CMPL_TMOUT_RESEND;
   3589   1.80   thorpej 
   3590  1.281   msaitoh 	CSR_WRITE(sc, WMREG_GCR, gcr);
   3591  1.281   msaitoh }
   3592   1.99      matt 
   3593  1.281   msaitoh void
   3594  1.281   msaitoh wm_get_auto_rd_done(struct wm_softc *sc)
   3595  1.281   msaitoh {
   3596  1.281   msaitoh 	int i;
   3597    1.1   thorpej 
   3598  1.281   msaitoh 	/* wait for eeprom to reload */
   3599  1.281   msaitoh 	switch (sc->sc_type) {
   3600  1.281   msaitoh 	case WM_T_82571:
   3601  1.281   msaitoh 	case WM_T_82572:
   3602  1.281   msaitoh 	case WM_T_82573:
   3603  1.281   msaitoh 	case WM_T_82574:
   3604  1.281   msaitoh 	case WM_T_82583:
   3605  1.281   msaitoh 	case WM_T_82575:
   3606  1.281   msaitoh 	case WM_T_82576:
   3607  1.281   msaitoh 	case WM_T_82580:
   3608  1.281   msaitoh 	case WM_T_I350:
   3609  1.281   msaitoh 	case WM_T_I354:
   3610  1.281   msaitoh 	case WM_T_I210:
   3611  1.281   msaitoh 	case WM_T_I211:
   3612  1.281   msaitoh 	case WM_T_80003:
   3613  1.281   msaitoh 	case WM_T_ICH8:
   3614  1.281   msaitoh 	case WM_T_ICH9:
   3615  1.281   msaitoh 		for (i = 0; i < 10; i++) {
   3616  1.281   msaitoh 			if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
   3617  1.281   msaitoh 				break;
   3618  1.281   msaitoh 			delay(1000);
   3619    1.1   thorpej 		}
   3620  1.281   msaitoh 		if (i == 10) {
   3621  1.281   msaitoh 			log(LOG_ERR, "%s: auto read from eeprom failed to "
   3622  1.281   msaitoh 			    "complete\n", device_xname(sc->sc_dev));
   3623  1.281   msaitoh 		}
   3624  1.281   msaitoh 		break;
   3625  1.281   msaitoh 	default:
   3626  1.281   msaitoh 		break;
   3627  1.281   msaitoh 	}
   3628  1.281   msaitoh }
   3629   1.59  christos 
   3630  1.281   msaitoh void
   3631  1.281   msaitoh wm_lan_init_done(struct wm_softc *sc)
   3632  1.281   msaitoh {
   3633  1.281   msaitoh 	uint32_t reg = 0;
   3634  1.281   msaitoh 	int i;
   3635    1.1   thorpej 
   3636  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3637  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   3638  1.420   msaitoh 
   3639  1.420   msaitoh 	/* Wait for eeprom to reload */
   3640  1.281   msaitoh 	switch (sc->sc_type) {
   3641  1.281   msaitoh 	case WM_T_ICH10:
   3642  1.281   msaitoh 	case WM_T_PCH:
   3643  1.281   msaitoh 	case WM_T_PCH2:
   3644  1.281   msaitoh 	case WM_T_PCH_LPT:
   3645  1.392   msaitoh 	case WM_T_PCH_SPT:
   3646  1.281   msaitoh 		for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
   3647  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_STATUS);
   3648  1.281   msaitoh 			if ((reg & STATUS_LAN_INIT_DONE) != 0)
   3649  1.281   msaitoh 				break;
   3650  1.281   msaitoh 			delay(100);
   3651  1.281   msaitoh 		}
   3652  1.281   msaitoh 		if (i >= WM_ICH8_LAN_INIT_TIMEOUT) {
   3653  1.281   msaitoh 			log(LOG_ERR, "%s: %s: lan_init_done failed to "
   3654  1.281   msaitoh 			    "complete\n", device_xname(sc->sc_dev), __func__);
   3655    1.1   thorpej 		}
   3656  1.281   msaitoh 		break;
   3657  1.281   msaitoh 	default:
   3658  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   3659  1.281   msaitoh 		    __func__);
   3660  1.281   msaitoh 		break;
   3661  1.281   msaitoh 	}
   3662    1.1   thorpej 
   3663  1.281   msaitoh 	reg &= ~STATUS_LAN_INIT_DONE;
   3664  1.281   msaitoh 	CSR_WRITE(sc, WMREG_STATUS, reg);
   3665  1.281   msaitoh }
   3666    1.6   thorpej 
   3667  1.281   msaitoh void
   3668  1.281   msaitoh wm_get_cfg_done(struct wm_softc *sc)
   3669  1.281   msaitoh {
   3670  1.281   msaitoh 	int mask;
   3671  1.281   msaitoh 	uint32_t reg;
   3672  1.281   msaitoh 	int i;
   3673    1.1   thorpej 
   3674  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3675  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   3676  1.420   msaitoh 
   3677  1.420   msaitoh 	/* Wait for eeprom to reload */
   3678  1.281   msaitoh 	switch (sc->sc_type) {
   3679  1.281   msaitoh 	case WM_T_82542_2_0:
   3680  1.281   msaitoh 	case WM_T_82542_2_1:
   3681  1.281   msaitoh 		/* null */
   3682  1.281   msaitoh 		break;
   3683  1.281   msaitoh 	case WM_T_82543:
   3684  1.281   msaitoh 	case WM_T_82544:
   3685  1.281   msaitoh 	case WM_T_82540:
   3686  1.281   msaitoh 	case WM_T_82545:
   3687  1.281   msaitoh 	case WM_T_82545_3:
   3688  1.281   msaitoh 	case WM_T_82546:
   3689  1.281   msaitoh 	case WM_T_82546_3:
   3690  1.281   msaitoh 	case WM_T_82541:
   3691  1.281   msaitoh 	case WM_T_82541_2:
   3692  1.281   msaitoh 	case WM_T_82547:
   3693  1.281   msaitoh 	case WM_T_82547_2:
   3694  1.281   msaitoh 	case WM_T_82573:
   3695  1.281   msaitoh 	case WM_T_82574:
   3696  1.281   msaitoh 	case WM_T_82583:
   3697  1.281   msaitoh 		/* generic */
   3698  1.281   msaitoh 		delay(10*1000);
   3699  1.281   msaitoh 		break;
   3700  1.281   msaitoh 	case WM_T_80003:
   3701  1.281   msaitoh 	case WM_T_82571:
   3702  1.281   msaitoh 	case WM_T_82572:
   3703  1.281   msaitoh 	case WM_T_82575:
   3704  1.281   msaitoh 	case WM_T_82576:
   3705  1.281   msaitoh 	case WM_T_82580:
   3706  1.281   msaitoh 	case WM_T_I350:
   3707  1.281   msaitoh 	case WM_T_I354:
   3708  1.281   msaitoh 	case WM_T_I210:
   3709  1.281   msaitoh 	case WM_T_I211:
   3710  1.281   msaitoh 		if (sc->sc_type == WM_T_82571) {
   3711  1.281   msaitoh 			/* Only 82571 shares port 0 */
   3712  1.281   msaitoh 			mask = EEMNGCTL_CFGDONE_0;
   3713  1.281   msaitoh 		} else
   3714  1.281   msaitoh 			mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid;
   3715  1.281   msaitoh 		for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) {
   3716  1.281   msaitoh 			if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
   3717  1.281   msaitoh 				break;
   3718  1.281   msaitoh 			delay(1000);
   3719  1.281   msaitoh 		}
   3720  1.281   msaitoh 		if (i >= WM_PHY_CFG_TIMEOUT) {
   3721  1.281   msaitoh 			DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n",
   3722  1.281   msaitoh 				device_xname(sc->sc_dev), __func__));
   3723  1.281   msaitoh 		}
   3724  1.281   msaitoh 		break;
   3725  1.281   msaitoh 	case WM_T_ICH8:
   3726  1.281   msaitoh 	case WM_T_ICH9:
   3727  1.281   msaitoh 	case WM_T_ICH10:
   3728  1.281   msaitoh 	case WM_T_PCH:
   3729  1.281   msaitoh 	case WM_T_PCH2:
   3730  1.281   msaitoh 	case WM_T_PCH_LPT:
   3731  1.392   msaitoh 	case WM_T_PCH_SPT:
   3732  1.281   msaitoh 		delay(10*1000);
   3733  1.281   msaitoh 		if (sc->sc_type >= WM_T_ICH10)
   3734  1.281   msaitoh 			wm_lan_init_done(sc);
   3735  1.281   msaitoh 		else
   3736  1.281   msaitoh 			wm_get_auto_rd_done(sc);
   3737    1.1   thorpej 
   3738  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_STATUS);
   3739  1.281   msaitoh 		if ((reg & STATUS_PHYRA) != 0)
   3740  1.281   msaitoh 			CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA);
   3741  1.281   msaitoh 		break;
   3742  1.281   msaitoh 	default:
   3743  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   3744  1.281   msaitoh 		    __func__);
   3745  1.281   msaitoh 		break;
   3746    1.1   thorpej 	}
   3747    1.1   thorpej }
   3748    1.1   thorpej 
   3749  1.517   msaitoh void
   3750  1.517   msaitoh wm_phy_post_reset(struct wm_softc *sc)
   3751  1.517   msaitoh {
   3752  1.517   msaitoh 	uint32_t reg;
   3753  1.517   msaitoh 
   3754  1.517   msaitoh 	/* This function is only for ICH8 and newer. */
   3755  1.517   msaitoh 	if (sc->sc_type < WM_T_ICH8)
   3756  1.517   msaitoh 		return;
   3757  1.517   msaitoh 
   3758  1.517   msaitoh 	if (wm_phy_resetisblocked(sc)) {
   3759  1.517   msaitoh 		/* XXX */
   3760  1.530   msaitoh 		device_printf(sc->sc_dev, "PHY is blocked\n");
   3761  1.517   msaitoh 		return;
   3762  1.517   msaitoh 	}
   3763  1.517   msaitoh 
   3764  1.517   msaitoh 	/* Allow time for h/w to get to quiescent state after reset */
   3765  1.517   msaitoh 	delay(10*1000);
   3766  1.517   msaitoh 
   3767  1.517   msaitoh 	/* Perform any necessary post-reset workarounds */
   3768  1.517   msaitoh 	if (sc->sc_type == WM_T_PCH)
   3769  1.517   msaitoh 		wm_hv_phy_workaround_ich8lan(sc);
   3770  1.517   msaitoh 	if (sc->sc_type == WM_T_PCH2)
   3771  1.517   msaitoh 		wm_lv_phy_workaround_ich8lan(sc);
   3772  1.517   msaitoh 
   3773  1.517   msaitoh 	/* Clear the host wakeup bit after lcd reset */
   3774  1.517   msaitoh 	if (sc->sc_type >= WM_T_PCH) {
   3775  1.517   msaitoh 		reg = wm_gmii_hv_readreg(sc->sc_dev, 2,
   3776  1.517   msaitoh 		    BM_PORT_GEN_CFG);
   3777  1.517   msaitoh 		reg &= ~BM_WUC_HOST_WU_BIT;
   3778  1.517   msaitoh 		wm_gmii_hv_writereg(sc->sc_dev, 2,
   3779  1.517   msaitoh 		    BM_PORT_GEN_CFG, reg);
   3780  1.517   msaitoh 	}
   3781  1.517   msaitoh 
   3782  1.523   msaitoh 	/* Configure the LCD with the extended configuration region in NVM */
   3783  1.523   msaitoh 	wm_init_lcd_from_nvm(sc);
   3784  1.523   msaitoh 
   3785  1.523   msaitoh 	/* Configure the LCD with the OEM bits in NVM */
   3786  1.523   msaitoh }
   3787  1.523   msaitoh 
   3788  1.528   msaitoh /* Only for PCH and newer */
   3789  1.528   msaitoh static void
   3790  1.528   msaitoh wm_write_smbus_addr(struct wm_softc *sc)
   3791  1.528   msaitoh {
   3792  1.528   msaitoh 	uint32_t strap, freq;
   3793  1.528   msaitoh 	uint32_t phy_data;
   3794  1.528   msaitoh 
   3795  1.528   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3796  1.528   msaitoh 		device_xname(sc->sc_dev), __func__));
   3797  1.528   msaitoh 
   3798  1.528   msaitoh 	strap = CSR_READ(sc, WMREG_STRAP);
   3799  1.528   msaitoh 	freq = __SHIFTOUT(strap, STRAP_FREQ);
   3800  1.528   msaitoh 
   3801  1.528   msaitoh 	phy_data = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, HV_SMB_ADDR);
   3802  1.528   msaitoh 
   3803  1.528   msaitoh 	phy_data &= ~HV_SMB_ADDR_ADDR;
   3804  1.528   msaitoh 	phy_data |= __SHIFTOUT(strap, STRAP_SMBUSADDR);
   3805  1.528   msaitoh 	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
   3806  1.528   msaitoh 
   3807  1.528   msaitoh 	if (sc->sc_phytype == WMPHY_I217) {
   3808  1.528   msaitoh 		/* Restore SMBus frequency */
   3809  1.528   msaitoh 		if (freq --) {
   3810  1.528   msaitoh 			phy_data &= ~(HV_SMB_ADDR_FREQ_LOW
   3811  1.528   msaitoh 			    | HV_SMB_ADDR_FREQ_HIGH);
   3812  1.528   msaitoh 			phy_data |= __SHIFTIN((freq & 0x01) != 0,
   3813  1.528   msaitoh 			    HV_SMB_ADDR_FREQ_LOW);
   3814  1.528   msaitoh 			phy_data |= __SHIFTIN((freq & 0x02) != 0,
   3815  1.528   msaitoh 			    HV_SMB_ADDR_FREQ_HIGH);
   3816  1.528   msaitoh 		} else {
   3817  1.528   msaitoh 			DPRINTF(WM_DEBUG_INIT,
   3818  1.528   msaitoh 			    ("%s: %s Unsupported SMB frequency in PHY\n",
   3819  1.528   msaitoh 				device_xname(sc->sc_dev), __func__));
   3820  1.528   msaitoh 		}
   3821  1.528   msaitoh 	}
   3822  1.528   msaitoh 
   3823  1.528   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, HV_SMB_ADDR, phy_data);
   3824  1.528   msaitoh }
   3825  1.528   msaitoh 
   3826  1.523   msaitoh void
   3827  1.523   msaitoh wm_init_lcd_from_nvm(struct wm_softc *sc)
   3828  1.523   msaitoh {
   3829  1.523   msaitoh 	uint32_t extcnfctr, sw_cfg_mask, cnf_size, word_addr, i, reg;
   3830  1.523   msaitoh 	uint16_t phy_page = 0;
   3831  1.523   msaitoh 
   3832  1.528   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3833  1.528   msaitoh 		device_xname(sc->sc_dev), __func__));
   3834  1.528   msaitoh 
   3835  1.523   msaitoh 	switch (sc->sc_type) {
   3836  1.523   msaitoh 	case WM_T_ICH8:
   3837  1.528   msaitoh 		if ((sc->sc_phytype == WMPHY_UNKNOWN)
   3838  1.528   msaitoh 		    || (sc->sc_phytype != WMPHY_IGP_3))
   3839  1.523   msaitoh 			return;
   3840  1.523   msaitoh 
   3841  1.523   msaitoh 		if ((sc->sc_pcidevid == PCI_PRODUCT_INTEL_82801H_AMT)
   3842  1.523   msaitoh 		    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_82801H_LAN)) {
   3843  1.523   msaitoh 			sw_cfg_mask = FEXTNVM_SW_CONFIG;
   3844  1.523   msaitoh 			break;
   3845  1.523   msaitoh 		}
   3846  1.523   msaitoh 		/* FALLTHROUGH */
   3847  1.523   msaitoh 	case WM_T_PCH:
   3848  1.523   msaitoh 	case WM_T_PCH2:
   3849  1.523   msaitoh 	case WM_T_PCH_LPT:
   3850  1.523   msaitoh 	case WM_T_PCH_SPT:
   3851  1.523   msaitoh 		sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
   3852  1.523   msaitoh 		break;
   3853  1.523   msaitoh 	default:
   3854  1.523   msaitoh 		return;
   3855  1.523   msaitoh 	}
   3856  1.523   msaitoh 
   3857  1.523   msaitoh 	sc->phy.acquire(sc);
   3858  1.523   msaitoh 
   3859  1.523   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM);
   3860  1.523   msaitoh 	if ((reg & sw_cfg_mask) == 0)
   3861  1.523   msaitoh 		goto release;
   3862  1.523   msaitoh 
   3863  1.517   msaitoh 	/*
   3864  1.523   msaitoh 	 * Make sure HW does not configure LCD from PHY extended configuration
   3865  1.523   msaitoh 	 * before SW configuration
   3866  1.517   msaitoh 	 */
   3867  1.523   msaitoh 	extcnfctr = CSR_READ(sc, WMREG_EXTCNFCTR);
   3868  1.523   msaitoh 	if ((sc->sc_type < WM_T_PCH2)
   3869  1.523   msaitoh 	    && ((extcnfctr & EXTCNFCTR_PCIE_WRITE_ENABLE) != 0))
   3870  1.523   msaitoh 		goto release;
   3871  1.523   msaitoh 
   3872  1.528   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s: Configure LCD by software\n",
   3873  1.528   msaitoh 		device_xname(sc->sc_dev), __func__));
   3874  1.523   msaitoh 	/* word_addr is in DWORD */
   3875  1.523   msaitoh 	word_addr = __SHIFTOUT(extcnfctr, EXTCNFCTR_EXT_CNF_POINTER) << 1;
   3876  1.523   msaitoh 
   3877  1.523   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFSIZE);
   3878  1.523   msaitoh 	cnf_size = __SHIFTOUT(reg, EXTCNFSIZE_LENGTH);
   3879  1.523   msaitoh 
   3880  1.523   msaitoh 	if (((sc->sc_type == WM_T_PCH)
   3881  1.523   msaitoh 		&& ((extcnfctr & EXTCNFCTR_OEM_WRITE_ENABLE) == 0))
   3882  1.523   msaitoh 	    || (sc->sc_type > WM_T_PCH)) {
   3883  1.523   msaitoh 		/*
   3884  1.523   msaitoh 		 * HW configures the SMBus address and LEDs when the OEM and
   3885  1.523   msaitoh 		 * LCD Write Enable bits are set in the NVM. When both NVM bits
   3886  1.523   msaitoh 		 * are cleared, SW will configure them instead.
   3887  1.523   msaitoh 		 */
   3888  1.528   msaitoh 		DPRINTF(WM_DEBUG_INIT, ("%s: %s: Configure SMBus and LED\n",
   3889  1.528   msaitoh 			device_xname(sc->sc_dev), __func__));
   3890  1.528   msaitoh 		wm_write_smbus_addr(sc);
   3891  1.517   msaitoh 
   3892  1.523   msaitoh 		reg = CSR_READ(sc, WMREG_LEDCTL);
   3893  1.523   msaitoh 		wm_gmii_hv_writereg_locked(sc->sc_dev, 1, HV_LED_CONFIG, reg);
   3894  1.523   msaitoh 	}
   3895  1.523   msaitoh 
   3896  1.523   msaitoh 	/* Configure LCD from extended configuration region. */
   3897  1.523   msaitoh 	for (i = 0; i < cnf_size; i++) {
   3898  1.523   msaitoh 		uint16_t reg_data, reg_addr;
   3899  1.523   msaitoh 
   3900  1.523   msaitoh 		if (wm_nvm_read(sc, (word_addr + i * 2), 1, &reg_data) != 0)
   3901  1.523   msaitoh 			goto release;
   3902  1.523   msaitoh 
   3903  1.523   msaitoh 		if (wm_nvm_read(sc, (word_addr + i * 2 + 1), 1, &reg_addr) !=0)
   3904  1.523   msaitoh 			goto release;
   3905  1.523   msaitoh 
   3906  1.523   msaitoh 		if (reg_addr == MII_IGPHY_PAGE_SELECT)
   3907  1.523   msaitoh 			phy_page = reg_data;
   3908  1.523   msaitoh 
   3909  1.523   msaitoh 		reg_addr &= IGPHY_MAXREGADDR;
   3910  1.523   msaitoh 		reg_addr |= phy_page;
   3911  1.523   msaitoh 
   3912  1.523   msaitoh 		sc->phy.release(sc); /* XXX */
   3913  1.523   msaitoh 		sc->sc_mii.mii_writereg(sc->sc_dev, 1, reg_addr, reg_data);
   3914  1.523   msaitoh 		sc->phy.acquire(sc); /* XXX */
   3915  1.523   msaitoh 	}
   3916  1.523   msaitoh 
   3917  1.523   msaitoh release:
   3918  1.523   msaitoh 	sc->phy.release(sc);
   3919  1.523   msaitoh 	return;
   3920  1.517   msaitoh }
   3921  1.523   msaitoh 
   3922  1.517   msaitoh 
   3923  1.312   msaitoh /* Init hardware bits */
   3924  1.312   msaitoh void
   3925  1.312   msaitoh wm_initialize_hardware_bits(struct wm_softc *sc)
   3926  1.312   msaitoh {
   3927  1.312   msaitoh 	uint32_t tarc0, tarc1, reg;
   3928  1.332   msaitoh 
   3929  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3930  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3931  1.420   msaitoh 
   3932  1.312   msaitoh 	/* For 82571 variant, 80003 and ICHs */
   3933  1.312   msaitoh 	if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583))
   3934  1.312   msaitoh 	    || (sc->sc_type >= WM_T_80003)) {
   3935  1.312   msaitoh 
   3936  1.312   msaitoh 		/* Transmit Descriptor Control 0 */
   3937  1.312   msaitoh 		reg = CSR_READ(sc, WMREG_TXDCTL(0));
   3938  1.312   msaitoh 		reg |= TXDCTL_COUNT_DESC;
   3939  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TXDCTL(0), reg);
   3940  1.312   msaitoh 
   3941  1.312   msaitoh 		/* Transmit Descriptor Control 1 */
   3942  1.312   msaitoh 		reg = CSR_READ(sc, WMREG_TXDCTL(1));
   3943  1.312   msaitoh 		reg |= TXDCTL_COUNT_DESC;
   3944  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TXDCTL(1), reg);
   3945  1.312   msaitoh 
   3946  1.312   msaitoh 		/* TARC0 */
   3947  1.312   msaitoh 		tarc0 = CSR_READ(sc, WMREG_TARC0);
   3948  1.312   msaitoh 		switch (sc->sc_type) {
   3949  1.312   msaitoh 		case WM_T_82571:
   3950  1.312   msaitoh 		case WM_T_82572:
   3951  1.312   msaitoh 		case WM_T_82573:
   3952  1.312   msaitoh 		case WM_T_82574:
   3953  1.312   msaitoh 		case WM_T_82583:
   3954  1.312   msaitoh 		case WM_T_80003:
   3955  1.312   msaitoh 			/* Clear bits 30..27 */
   3956  1.312   msaitoh 			tarc0 &= ~__BITS(30, 27);
   3957  1.312   msaitoh 			break;
   3958  1.312   msaitoh 		default:
   3959  1.312   msaitoh 			break;
   3960  1.312   msaitoh 		}
   3961  1.312   msaitoh 
   3962  1.312   msaitoh 		switch (sc->sc_type) {
   3963  1.312   msaitoh 		case WM_T_82571:
   3964  1.312   msaitoh 		case WM_T_82572:
   3965  1.312   msaitoh 			tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */
   3966  1.312   msaitoh 
   3967  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   3968  1.312   msaitoh 			tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */
   3969  1.312   msaitoh 			tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */
   3970  1.312   msaitoh 			/* 8257[12] Errata No.7 */
   3971  1.312   msaitoh 			tarc1 |= __BIT(22); /* TARC1 bits 22 */
   3972  1.312   msaitoh 
   3973  1.312   msaitoh 			/* TARC1 bit 28 */
   3974  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   3975  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   3976  1.312   msaitoh 			else
   3977  1.312   msaitoh 				tarc1 |= __BIT(28);
   3978  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   3979  1.312   msaitoh 
   3980  1.312   msaitoh 			/*
   3981  1.312   msaitoh 			 * 8257[12] Errata No.13
   3982  1.312   msaitoh 			 * Disable Dyamic Clock Gating.
   3983  1.312   msaitoh 			 */
   3984  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   3985  1.312   msaitoh 			reg &= ~CTRL_EXT_DMA_DYN_CLK;
   3986  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   3987  1.312   msaitoh 			break;
   3988  1.312   msaitoh 		case WM_T_82573:
   3989  1.312   msaitoh 		case WM_T_82574:
   3990  1.312   msaitoh 		case WM_T_82583:
   3991  1.312   msaitoh 			if ((sc->sc_type == WM_T_82574)
   3992  1.312   msaitoh 			    || (sc->sc_type == WM_T_82583))
   3993  1.312   msaitoh 				tarc0 |= __BIT(26); /* TARC0 bit 26 */
   3994  1.312   msaitoh 
   3995  1.312   msaitoh 			/* Extended Device Control */
   3996  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   3997  1.312   msaitoh 			reg &= ~__BIT(23);	/* Clear bit 23 */
   3998  1.312   msaitoh 			reg |= __BIT(22);	/* Set bit 22 */
   3999  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4000  1.312   msaitoh 
   4001  1.312   msaitoh 			/* Device Control */
   4002  1.312   msaitoh 			sc->sc_ctrl &= ~__BIT(29);	/* Clear bit 29 */
   4003  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4004  1.312   msaitoh 
   4005  1.312   msaitoh 			/* PCIe Control Register */
   4006  1.350   msaitoh 			/*
   4007  1.350   msaitoh 			 * 82573 Errata (unknown).
   4008  1.350   msaitoh 			 *
   4009  1.350   msaitoh 			 * 82574 Errata 25 and 82583 Errata 12
   4010  1.350   msaitoh 			 * "Dropped Rx Packets":
   4011  1.350   msaitoh 			 *   NVM Image Version 2.1.4 and newer has no this bug.
   4012  1.350   msaitoh 			 */
   4013  1.350   msaitoh 			reg = CSR_READ(sc, WMREG_GCR);
   4014  1.350   msaitoh 			reg |= GCR_L1_ACT_WITHOUT_L0S_RX;
   4015  1.350   msaitoh 			CSR_WRITE(sc, WMREG_GCR, reg);
   4016  1.350   msaitoh 
   4017  1.312   msaitoh 			if ((sc->sc_type == WM_T_82574)
   4018  1.312   msaitoh 			    || (sc->sc_type == WM_T_82583)) {
   4019  1.312   msaitoh 				/*
   4020  1.312   msaitoh 				 * Document says this bit must be set for
   4021  1.312   msaitoh 				 * proper operation.
   4022  1.312   msaitoh 				 */
   4023  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_GCR);
   4024  1.312   msaitoh 				reg |= __BIT(22);
   4025  1.312   msaitoh 				CSR_WRITE(sc, WMREG_GCR, reg);
   4026  1.312   msaitoh 
   4027  1.312   msaitoh 				/*
   4028  1.312   msaitoh 				 * Apply workaround for hardware errata
   4029  1.312   msaitoh 				 * documented in errata docs Fixes issue where
   4030  1.312   msaitoh 				 * some error prone or unreliable PCIe
   4031  1.312   msaitoh 				 * completions are occurring, particularly
   4032  1.312   msaitoh 				 * with ASPM enabled. Without fix, issue can
   4033  1.312   msaitoh 				 * cause Tx timeouts.
   4034  1.312   msaitoh 				 */
   4035  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_GCR2);
   4036  1.312   msaitoh 				reg |= __BIT(0);
   4037  1.312   msaitoh 				CSR_WRITE(sc, WMREG_GCR2, reg);
   4038  1.312   msaitoh 			}
   4039  1.312   msaitoh 			break;
   4040  1.312   msaitoh 		case WM_T_80003:
   4041  1.312   msaitoh 			/* TARC0 */
   4042  1.312   msaitoh 			if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
   4043  1.312   msaitoh 			    || (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   4044  1.312   msaitoh 				tarc0 &= ~__BIT(20); /* Clear bits 20 */
   4045  1.312   msaitoh 
   4046  1.312   msaitoh 			/* TARC1 bit 28 */
   4047  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   4048  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   4049  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   4050  1.312   msaitoh 			else
   4051  1.312   msaitoh 				tarc1 |= __BIT(28);
   4052  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   4053  1.312   msaitoh 			break;
   4054  1.312   msaitoh 		case WM_T_ICH8:
   4055  1.312   msaitoh 		case WM_T_ICH9:
   4056  1.312   msaitoh 		case WM_T_ICH10:
   4057  1.312   msaitoh 		case WM_T_PCH:
   4058  1.312   msaitoh 		case WM_T_PCH2:
   4059  1.312   msaitoh 		case WM_T_PCH_LPT:
   4060  1.393   msaitoh 		case WM_T_PCH_SPT:
   4061  1.393   msaitoh 			/* TARC0 */
   4062  1.540   msaitoh 			if (sc->sc_type == WM_T_ICH8) {
   4063  1.312   msaitoh 				/* Set TARC0 bits 29 and 28 */
   4064  1.312   msaitoh 				tarc0 |= __BITS(29, 28);
   4065  1.540   msaitoh 			} else if (sc->sc_type == WM_T_PCH_SPT) {
   4066  1.540   msaitoh 				tarc0 |= __BIT(29);
   4067  1.540   msaitoh 				/*
   4068  1.540   msaitoh 				 *  Drop bit 28. From Linux.
   4069  1.540   msaitoh 				 * See I218/I219 spec update
   4070  1.540   msaitoh 				 * "5. Buffer Overrun While the I219 is
   4071  1.540   msaitoh 				 * Processing DMA Transactions"
   4072  1.540   msaitoh 				 */
   4073  1.540   msaitoh 				tarc0 &= ~__BIT(28);
   4074  1.312   msaitoh 			}
   4075  1.312   msaitoh 			/* Set TARC0 bits 23,24,26,27 */
   4076  1.312   msaitoh 			tarc0 |= __BITS(27, 26) | __BITS(24, 23);
   4077  1.312   msaitoh 
   4078  1.312   msaitoh 			/* CTRL_EXT */
   4079  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   4080  1.312   msaitoh 			reg |= __BIT(22);	/* Set bit 22 */
   4081  1.312   msaitoh 			/*
   4082  1.312   msaitoh 			 * Enable PHY low-power state when MAC is at D3
   4083  1.312   msaitoh 			 * w/o WoL
   4084  1.312   msaitoh 			 */
   4085  1.312   msaitoh 			if (sc->sc_type >= WM_T_PCH)
   4086  1.312   msaitoh 				reg |= CTRL_EXT_PHYPDEN;
   4087  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4088  1.312   msaitoh 
   4089  1.312   msaitoh 			/* TARC1 */
   4090  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   4091  1.312   msaitoh 			/* bit 28 */
   4092  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   4093  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   4094  1.312   msaitoh 			else
   4095  1.312   msaitoh 				tarc1 |= __BIT(28);
   4096  1.312   msaitoh 			tarc1 |= __BIT(24) | __BIT(26) | __BIT(30);
   4097  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   4098  1.312   msaitoh 
   4099  1.312   msaitoh 			/* Device Status */
   4100  1.312   msaitoh 			if (sc->sc_type == WM_T_ICH8) {
   4101  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_STATUS);
   4102  1.312   msaitoh 				reg &= ~__BIT(31);
   4103  1.312   msaitoh 				CSR_WRITE(sc, WMREG_STATUS, reg);
   4104  1.312   msaitoh 
   4105  1.312   msaitoh 			}
   4106  1.312   msaitoh 
   4107  1.393   msaitoh 			/* IOSFPC */
   4108  1.393   msaitoh 			if (sc->sc_type == WM_T_PCH_SPT) {
   4109  1.393   msaitoh 				reg = CSR_READ(sc, WMREG_IOSFPC);
   4110  1.393   msaitoh 				reg |= RCTL_RDMTS_HEX; /* XXX RTCL bit? */
   4111  1.393   msaitoh 				CSR_WRITE(sc, WMREG_IOSFPC, reg);
   4112  1.393   msaitoh 			}
   4113  1.312   msaitoh 			/*
   4114  1.312   msaitoh 			 * Work-around descriptor data corruption issue during
   4115  1.312   msaitoh 			 * NFS v2 UDP traffic, just disable the NFS filtering
   4116  1.312   msaitoh 			 * capability.
   4117  1.312   msaitoh 			 */
   4118  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_RFCTL);
   4119  1.312   msaitoh 			reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS;
   4120  1.312   msaitoh 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   4121  1.312   msaitoh 			break;
   4122  1.312   msaitoh 		default:
   4123  1.312   msaitoh 			break;
   4124  1.312   msaitoh 		}
   4125  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TARC0, tarc0);
   4126  1.312   msaitoh 
   4127  1.462   msaitoh 		switch (sc->sc_type) {
   4128  1.312   msaitoh 		/*
   4129  1.462   msaitoh 		 * 8257[12] Errata No.52, 82573 Errata No.43 and some others.
   4130  1.312   msaitoh 		 * Avoid RSS Hash Value bug.
   4131  1.312   msaitoh 		 */
   4132  1.312   msaitoh 		case WM_T_82571:
   4133  1.312   msaitoh 		case WM_T_82572:
   4134  1.312   msaitoh 		case WM_T_82573:
   4135  1.312   msaitoh 		case WM_T_80003:
   4136  1.312   msaitoh 		case WM_T_ICH8:
   4137  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_RFCTL);
   4138  1.312   msaitoh 			reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS;
   4139  1.312   msaitoh 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   4140  1.312   msaitoh 			break;
   4141  1.466  knakahar 		case WM_T_82574:
   4142  1.466  knakahar 			/* use extened Rx descriptor. */
   4143  1.466  knakahar 			reg = CSR_READ(sc, WMREG_RFCTL);
   4144  1.466  knakahar 			reg |= WMREG_RFCTL_EXSTEN;
   4145  1.466  knakahar 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   4146  1.466  knakahar 			break;
   4147  1.464   msaitoh 		default:
   4148  1.464   msaitoh 			break;
   4149  1.464   msaitoh 		}
   4150  1.464   msaitoh 	} else if ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211)) {
   4151  1.462   msaitoh 		/*
   4152  1.462   msaitoh 		 * 82575 Errata XXX, 82576 Errata 46, 82580 Errata 24,
   4153  1.462   msaitoh 		 * I350 Errata 37, I210 Errata No. 31 and I211 Errata No. 11:
   4154  1.462   msaitoh 		 * "Certain Malformed IPv6 Extension Headers are Not Processed
   4155  1.462   msaitoh 		 * Correctly by the Device"
   4156  1.462   msaitoh 		 *
   4157  1.462   msaitoh 		 * I354(C2000) Errata AVR53:
   4158  1.462   msaitoh 		 * "Malformed IPv6 Extension Headers May Result in LAN Device
   4159  1.462   msaitoh 		 * Hang"
   4160  1.462   msaitoh 		 */
   4161  1.464   msaitoh 		reg = CSR_READ(sc, WMREG_RFCTL);
   4162  1.464   msaitoh 		reg |= WMREG_RFCTL_IPV6EXDIS;
   4163  1.464   msaitoh 		CSR_WRITE(sc, WMREG_RFCTL, reg);
   4164  1.312   msaitoh 	}
   4165  1.312   msaitoh }
   4166  1.312   msaitoh 
   4167  1.320   msaitoh static uint32_t
   4168  1.320   msaitoh wm_rxpbs_adjust_82580(uint32_t val)
   4169  1.320   msaitoh {
   4170  1.320   msaitoh 	uint32_t rv = 0;
   4171  1.320   msaitoh 
   4172  1.320   msaitoh 	if (val < __arraycount(wm_82580_rxpbs_table))
   4173  1.320   msaitoh 		rv = wm_82580_rxpbs_table[val];
   4174  1.320   msaitoh 
   4175  1.320   msaitoh 	return rv;
   4176  1.320   msaitoh }
   4177  1.320   msaitoh 
   4178  1.447   msaitoh /*
   4179  1.447   msaitoh  * wm_reset_phy:
   4180  1.447   msaitoh  *
   4181  1.447   msaitoh  *	generic PHY reset function.
   4182  1.447   msaitoh  *	Same as e1000_phy_hw_reset_generic()
   4183  1.447   msaitoh  */
   4184  1.447   msaitoh static void
   4185  1.447   msaitoh wm_reset_phy(struct wm_softc *sc)
   4186  1.447   msaitoh {
   4187  1.447   msaitoh 	uint32_t reg;
   4188  1.447   msaitoh 
   4189  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   4190  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   4191  1.447   msaitoh 	if (wm_phy_resetisblocked(sc))
   4192  1.447   msaitoh 		return;
   4193  1.447   msaitoh 
   4194  1.447   msaitoh 	sc->phy.acquire(sc);
   4195  1.447   msaitoh 
   4196  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL);
   4197  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);
   4198  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   4199  1.447   msaitoh 
   4200  1.447   msaitoh 	delay(sc->phy.reset_delay_us);
   4201  1.447   msaitoh 
   4202  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   4203  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   4204  1.447   msaitoh 
   4205  1.447   msaitoh 	delay(150);
   4206  1.447   msaitoh 
   4207  1.447   msaitoh 	sc->phy.release(sc);
   4208  1.447   msaitoh 
   4209  1.447   msaitoh 	wm_get_cfg_done(sc);
   4210  1.517   msaitoh 	wm_phy_post_reset(sc);
   4211  1.447   msaitoh }
   4212  1.447   msaitoh 
   4213  1.443   msaitoh static void
   4214  1.443   msaitoh wm_flush_desc_rings(struct wm_softc *sc)
   4215  1.443   msaitoh {
   4216  1.443   msaitoh 	pcireg_t preg;
   4217  1.443   msaitoh 	uint32_t reg;
   4218  1.524   msaitoh 	struct wm_txqueue *txq;
   4219  1.524   msaitoh 	wiseman_txdesc_t *txd;
   4220  1.443   msaitoh 	int nexttx;
   4221  1.524   msaitoh 	uint32_t rctl;
   4222  1.443   msaitoh 
   4223  1.443   msaitoh 	/* First, disable MULR fix in FEXTNVM11 */
   4224  1.443   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM11);
   4225  1.443   msaitoh 	reg |= FEXTNVM11_DIS_MULRFIX;
   4226  1.443   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM11, reg);
   4227  1.443   msaitoh 
   4228  1.443   msaitoh 	preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, WM_PCI_DESCRING_STATUS);
   4229  1.443   msaitoh 	reg = CSR_READ(sc, WMREG_TDLEN(0));
   4230  1.524   msaitoh 	if (((preg & DESCRING_STATUS_FLUSH_REQ) == 0) || (reg == 0))
   4231  1.524   msaitoh 		return;
   4232  1.443   msaitoh 
   4233  1.524   msaitoh 	/* TX */
   4234  1.524   msaitoh 	printf("%s: Need TX flush (reg = %08x, len = %u)\n",
   4235  1.524   msaitoh 	    device_xname(sc->sc_dev), preg, reg);
   4236  1.524   msaitoh 	reg = CSR_READ(sc, WMREG_TCTL);
   4237  1.524   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, reg | TCTL_EN);
   4238  1.524   msaitoh 
   4239  1.524   msaitoh 	txq = &sc->sc_queue[0].wmq_txq;
   4240  1.524   msaitoh 	nexttx = txq->txq_next;
   4241  1.524   msaitoh 	txd = &txq->txq_descs[nexttx];
   4242  1.524   msaitoh 	wm_set_dma_addr(&txd->wtx_addr, WM_CDTXADDR(txq, nexttx));
   4243  1.524   msaitoh 	txd->wtx_cmdlen = htole32(WTX_CMD_IFCS| 512);
   4244  1.524   msaitoh 	txd->wtx_fields.wtxu_status = 0;
   4245  1.524   msaitoh 	txd->wtx_fields.wtxu_options = 0;
   4246  1.524   msaitoh 	txd->wtx_fields.wtxu_vlan = 0;
   4247  1.443   msaitoh 
   4248  1.524   msaitoh 	bus_space_barrier(sc->sc_st, sc->sc_sh, 0, 0,
   4249  1.524   msaitoh 	    BUS_SPACE_BARRIER_WRITE);
   4250  1.443   msaitoh 
   4251  1.524   msaitoh 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   4252  1.524   msaitoh 	CSR_WRITE(sc, WMREG_TDT(0), txq->txq_next);
   4253  1.524   msaitoh 	bus_space_barrier(sc->sc_st, sc->sc_sh, 0, 0,
   4254  1.524   msaitoh 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
   4255  1.524   msaitoh 	delay(250);
   4256  1.524   msaitoh 
   4257  1.443   msaitoh 	preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, WM_PCI_DESCRING_STATUS);
   4258  1.524   msaitoh 	if ((preg & DESCRING_STATUS_FLUSH_REQ) == 0)
   4259  1.524   msaitoh 		return;
   4260  1.443   msaitoh 
   4261  1.524   msaitoh 	/* RX */
   4262  1.524   msaitoh 	printf("%s: Need RX flush (reg = %08x)\n",
   4263  1.524   msaitoh 	    device_xname(sc->sc_dev), preg);
   4264  1.524   msaitoh 	rctl = CSR_READ(sc, WMREG_RCTL);
   4265  1.524   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, rctl & ~RCTL_EN);
   4266  1.524   msaitoh 	CSR_WRITE_FLUSH(sc);
   4267  1.524   msaitoh 	delay(150);
   4268  1.443   msaitoh 
   4269  1.524   msaitoh 	reg = CSR_READ(sc, WMREG_RXDCTL(0));
   4270  1.524   msaitoh 	/* zero the lower 14 bits (prefetch and host thresholds) */
   4271  1.524   msaitoh 	reg &= 0xffffc000;
   4272  1.524   msaitoh 	/*
   4273  1.524   msaitoh 	 * update thresholds: prefetch threshold to 31, host threshold
   4274  1.524   msaitoh 	 * to 1 and make sure the granularity is "descriptors" and not
   4275  1.524   msaitoh 	 * "cache lines"
   4276  1.524   msaitoh 	 */
   4277  1.524   msaitoh 	reg |= (0x1f | (1 << 8) | RXDCTL_GRAN);
   4278  1.524   msaitoh 	CSR_WRITE(sc, WMREG_RXDCTL(0), reg);
   4279  1.443   msaitoh 
   4280  1.524   msaitoh 	/*
   4281  1.524   msaitoh 	 * momentarily enable the RX ring for the changes to take
   4282  1.524   msaitoh 	 * effect
   4283  1.524   msaitoh 	 */
   4284  1.524   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, rctl | RCTL_EN);
   4285  1.524   msaitoh 	CSR_WRITE_FLUSH(sc);
   4286  1.524   msaitoh 	delay(150);
   4287  1.524   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, rctl & ~RCTL_EN);
   4288  1.443   msaitoh }
   4289  1.443   msaitoh 
   4290    1.1   thorpej /*
   4291  1.281   msaitoh  * wm_reset:
   4292  1.232    bouyer  *
   4293  1.281   msaitoh  *	Reset the i82542 chip.
   4294  1.232    bouyer  */
   4295  1.281   msaitoh static void
   4296  1.281   msaitoh wm_reset(struct wm_softc *sc)
   4297  1.232    bouyer {
   4298  1.281   msaitoh 	int phy_reset = 0;
   4299  1.364  knakahar 	int i, error = 0;
   4300  1.424   msaitoh 	uint32_t reg;
   4301  1.531   msaitoh 	uint16_t kmreg;
   4302  1.531   msaitoh 	int rv;
   4303  1.232    bouyer 
   4304  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   4305  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   4306  1.420   msaitoh 	KASSERT(sc->sc_type != 0);
   4307  1.420   msaitoh 
   4308  1.232    bouyer 	/*
   4309  1.281   msaitoh 	 * Allocate on-chip memory according to the MTU size.
   4310  1.281   msaitoh 	 * The Packet Buffer Allocation register must be written
   4311  1.281   msaitoh 	 * before the chip is reset.
   4312  1.232    bouyer 	 */
   4313  1.281   msaitoh 	switch (sc->sc_type) {
   4314  1.281   msaitoh 	case WM_T_82547:
   4315  1.281   msaitoh 	case WM_T_82547_2:
   4316  1.281   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   4317  1.281   msaitoh 		    PBA_22K : PBA_30K;
   4318  1.405  knakahar 		for (i = 0; i < sc->sc_nqueues; i++) {
   4319  1.405  knakahar 			struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   4320  1.364  knakahar 			txq->txq_fifo_head = 0;
   4321  1.364  knakahar 			txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
   4322  1.364  knakahar 			txq->txq_fifo_size =
   4323  1.364  knakahar 				(PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
   4324  1.364  knakahar 			txq->txq_fifo_stall = 0;
   4325  1.364  knakahar 		}
   4326  1.281   msaitoh 		break;
   4327  1.281   msaitoh 	case WM_T_82571:
   4328  1.281   msaitoh 	case WM_T_82572:
   4329  1.281   msaitoh 	case WM_T_82575:	/* XXX need special handing for jumbo frames */
   4330  1.281   msaitoh 	case WM_T_80003:
   4331  1.281   msaitoh 		sc->sc_pba = PBA_32K;
   4332  1.281   msaitoh 		break;
   4333  1.281   msaitoh 	case WM_T_82573:
   4334  1.281   msaitoh 		sc->sc_pba = PBA_12K;
   4335  1.281   msaitoh 		break;
   4336  1.281   msaitoh 	case WM_T_82574:
   4337  1.281   msaitoh 	case WM_T_82583:
   4338  1.281   msaitoh 		sc->sc_pba = PBA_20K;
   4339  1.281   msaitoh 		break;
   4340  1.320   msaitoh 	case WM_T_82576:
   4341  1.320   msaitoh 		sc->sc_pba = CSR_READ(sc, WMREG_RXPBS);
   4342  1.320   msaitoh 		sc->sc_pba &= RXPBS_SIZE_MASK_82576;
   4343  1.320   msaitoh 		break;
   4344  1.320   msaitoh 	case WM_T_82580:
   4345  1.320   msaitoh 	case WM_T_I350:
   4346  1.320   msaitoh 	case WM_T_I354:
   4347  1.320   msaitoh 		sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS));
   4348  1.320   msaitoh 		break;
   4349  1.320   msaitoh 	case WM_T_I210:
   4350  1.320   msaitoh 	case WM_T_I211:
   4351  1.320   msaitoh 		sc->sc_pba = PBA_34K;
   4352  1.320   msaitoh 		break;
   4353  1.281   msaitoh 	case WM_T_ICH8:
   4354  1.312   msaitoh 		/* Workaround for a bit corruption issue in FIFO memory */
   4355  1.281   msaitoh 		sc->sc_pba = PBA_8K;
   4356  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBS, PBA_16K);
   4357  1.281   msaitoh 		break;
   4358  1.281   msaitoh 	case WM_T_ICH9:
   4359  1.281   msaitoh 	case WM_T_ICH10:
   4360  1.318   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ?
   4361  1.318   msaitoh 		    PBA_14K : PBA_10K;
   4362  1.232    bouyer 		break;
   4363  1.281   msaitoh 	case WM_T_PCH:
   4364  1.281   msaitoh 	case WM_T_PCH2:
   4365  1.281   msaitoh 	case WM_T_PCH_LPT:
   4366  1.392   msaitoh 	case WM_T_PCH_SPT:
   4367  1.281   msaitoh 		sc->sc_pba = PBA_26K;
   4368  1.232    bouyer 		break;
   4369  1.232    bouyer 	default:
   4370  1.281   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   4371  1.281   msaitoh 		    PBA_40K : PBA_48K;
   4372  1.281   msaitoh 		break;
   4373  1.232    bouyer 	}
   4374  1.320   msaitoh 	/*
   4375  1.320   msaitoh 	 * Only old or non-multiqueue devices have the PBA register
   4376  1.320   msaitoh 	 * XXX Need special handling for 82575.
   4377  1.320   msaitoh 	 */
   4378  1.320   msaitoh 	if (((sc->sc_flags & WM_F_NEWQUEUE) == 0)
   4379  1.320   msaitoh 	    || (sc->sc_type == WM_T_82575))
   4380  1.320   msaitoh 		CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
   4381  1.232    bouyer 
   4382  1.281   msaitoh 	/* Prevent the PCI-E bus from sticking */
   4383  1.281   msaitoh 	if (sc->sc_flags & WM_F_PCIE) {
   4384  1.281   msaitoh 		int timeout = 800;
   4385  1.232    bouyer 
   4386  1.281   msaitoh 		sc->sc_ctrl |= CTRL_GIO_M_DIS;
   4387  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4388  1.232    bouyer 
   4389  1.281   msaitoh 		while (timeout--) {
   4390  1.281   msaitoh 			if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA)
   4391  1.281   msaitoh 			    == 0)
   4392  1.281   msaitoh 				break;
   4393  1.281   msaitoh 			delay(100);
   4394  1.281   msaitoh 		}
   4395  1.511   msaitoh 		if (timeout == 0)
   4396  1.511   msaitoh 			device_printf(sc->sc_dev,
   4397  1.511   msaitoh 			    "failed to disable busmastering\n");
   4398  1.232    bouyer 	}
   4399  1.232    bouyer 
   4400  1.281   msaitoh 	/* Set the completion timeout for interface */
   4401  1.281   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   4402  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   4403  1.282   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   4404  1.282   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
   4405  1.281   msaitoh 		wm_set_pcie_completion_timeout(sc);
   4406  1.232    bouyer 
   4407  1.281   msaitoh 	/* Clear interrupt */
   4408  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   4409  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   4410  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   4411  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   4412  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   4413  1.335   msaitoh 		} else {
   4414  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   4415  1.335   msaitoh 		}
   4416  1.335   msaitoh 	}
   4417  1.232    bouyer 
   4418  1.281   msaitoh 	/* Stop the transmit and receive processes. */
   4419  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, 0);
   4420  1.281   msaitoh 	sc->sc_rctl &= ~RCTL_EN;
   4421  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP);
   4422  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   4423  1.232    bouyer 
   4424  1.281   msaitoh 	/* XXX set_tbi_sbp_82543() */
   4425  1.232    bouyer 
   4426  1.281   msaitoh 	delay(10*1000);
   4427  1.232    bouyer 
   4428  1.281   msaitoh 	/* Must acquire the MDIO ownership before MAC reset */
   4429  1.281   msaitoh 	switch (sc->sc_type) {
   4430  1.281   msaitoh 	case WM_T_82573:
   4431  1.281   msaitoh 	case WM_T_82574:
   4432  1.281   msaitoh 	case WM_T_82583:
   4433  1.281   msaitoh 		error = wm_get_hw_semaphore_82573(sc);
   4434  1.281   msaitoh 		break;
   4435  1.281   msaitoh 	default:
   4436  1.281   msaitoh 		break;
   4437  1.281   msaitoh 	}
   4438  1.232    bouyer 
   4439  1.281   msaitoh 	/*
   4440  1.281   msaitoh 	 * 82541 Errata 29? & 82547 Errata 28?
   4441  1.281   msaitoh 	 * See also the description about PHY_RST bit in CTRL register
   4442  1.281   msaitoh 	 * in 8254x_GBe_SDM.pdf.
   4443  1.281   msaitoh 	 */
   4444  1.281   msaitoh 	if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) {
   4445  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL,
   4446  1.281   msaitoh 		    CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
   4447  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   4448  1.281   msaitoh 		delay(5000);
   4449  1.281   msaitoh 	}
   4450  1.232    bouyer 
   4451  1.281   msaitoh 	switch (sc->sc_type) {
   4452  1.281   msaitoh 	case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */
   4453  1.281   msaitoh 	case WM_T_82541:
   4454  1.281   msaitoh 	case WM_T_82541_2:
   4455  1.281   msaitoh 	case WM_T_82547:
   4456  1.281   msaitoh 	case WM_T_82547_2:
   4457  1.281   msaitoh 		/*
   4458  1.281   msaitoh 		 * On some chipsets, a reset through a memory-mapped write
   4459  1.281   msaitoh 		 * cycle can cause the chip to reset before completing the
   4460  1.281   msaitoh 		 * write cycle.  This causes major headache that can be
   4461  1.281   msaitoh 		 * avoided by issuing the reset via indirect register writes
   4462  1.281   msaitoh 		 * through I/O space.
   4463  1.281   msaitoh 		 *
   4464  1.281   msaitoh 		 * So, if we successfully mapped the I/O BAR at attach time,
   4465  1.281   msaitoh 		 * use that.  Otherwise, try our luck with a memory-mapped
   4466  1.281   msaitoh 		 * reset.
   4467  1.281   msaitoh 		 */
   4468  1.281   msaitoh 		if (sc->sc_flags & WM_F_IOH_VALID)
   4469  1.281   msaitoh 			wm_io_write(sc, WMREG_CTRL, CTRL_RST);
   4470  1.281   msaitoh 		else
   4471  1.281   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
   4472  1.281   msaitoh 		break;
   4473  1.281   msaitoh 	case WM_T_82545_3:
   4474  1.281   msaitoh 	case WM_T_82546_3:
   4475  1.281   msaitoh 		/* Use the shadow control register on these chips. */
   4476  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
   4477  1.281   msaitoh 		break;
   4478  1.281   msaitoh 	case WM_T_80003:
   4479  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
   4480  1.424   msaitoh 		sc->phy.acquire(sc);
   4481  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg);
   4482  1.424   msaitoh 		sc->phy.release(sc);
   4483  1.281   msaitoh 		break;
   4484  1.281   msaitoh 	case WM_T_ICH8:
   4485  1.281   msaitoh 	case WM_T_ICH9:
   4486  1.281   msaitoh 	case WM_T_ICH10:
   4487  1.281   msaitoh 	case WM_T_PCH:
   4488  1.281   msaitoh 	case WM_T_PCH2:
   4489  1.281   msaitoh 	case WM_T_PCH_LPT:
   4490  1.392   msaitoh 	case WM_T_PCH_SPT:
   4491  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
   4492  1.386   msaitoh 		if (wm_phy_resetisblocked(sc) == false) {
   4493  1.232    bouyer 			/*
   4494  1.281   msaitoh 			 * Gate automatic PHY configuration by hardware on
   4495  1.281   msaitoh 			 * non-managed 82579
   4496  1.232    bouyer 			 */
   4497  1.281   msaitoh 			if ((sc->sc_type == WM_T_PCH2)
   4498  1.281   msaitoh 			    && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
   4499  1.380   msaitoh 				== 0))
   4500  1.392   msaitoh 				wm_gate_hw_phy_config_ich8lan(sc, true);
   4501  1.232    bouyer 
   4502  1.281   msaitoh 			reg |= CTRL_PHY_RESET;
   4503  1.281   msaitoh 			phy_reset = 1;
   4504  1.394   msaitoh 		} else
   4505  1.394   msaitoh 			printf("XXX reset is blocked!!!\n");
   4506  1.424   msaitoh 		sc->phy.acquire(sc);
   4507  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg);
   4508  1.281   msaitoh 		/* Don't insert a completion barrier when reset */
   4509  1.281   msaitoh 		delay(20*1000);
   4510  1.424   msaitoh 		mutex_exit(sc->sc_ich_phymtx);
   4511  1.281   msaitoh 		break;
   4512  1.304   msaitoh 	case WM_T_82580:
   4513  1.304   msaitoh 	case WM_T_I350:
   4514  1.304   msaitoh 	case WM_T_I354:
   4515  1.304   msaitoh 	case WM_T_I210:
   4516  1.304   msaitoh 	case WM_T_I211:
   4517  1.304   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
   4518  1.304   msaitoh 		if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII)
   4519  1.304   msaitoh 			CSR_WRITE_FLUSH(sc);
   4520  1.304   msaitoh 		delay(5000);
   4521  1.304   msaitoh 		break;
   4522  1.281   msaitoh 	case WM_T_82542_2_0:
   4523  1.281   msaitoh 	case WM_T_82542_2_1:
   4524  1.281   msaitoh 	case WM_T_82543:
   4525  1.281   msaitoh 	case WM_T_82540:
   4526  1.281   msaitoh 	case WM_T_82545:
   4527  1.281   msaitoh 	case WM_T_82546:
   4528  1.281   msaitoh 	case WM_T_82571:
   4529  1.281   msaitoh 	case WM_T_82572:
   4530  1.281   msaitoh 	case WM_T_82573:
   4531  1.281   msaitoh 	case WM_T_82574:
   4532  1.281   msaitoh 	case WM_T_82575:
   4533  1.281   msaitoh 	case WM_T_82576:
   4534  1.281   msaitoh 	case WM_T_82583:
   4535  1.281   msaitoh 	default:
   4536  1.281   msaitoh 		/* Everything else can safely use the documented method. */
   4537  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
   4538  1.281   msaitoh 		break;
   4539  1.281   msaitoh 	}
   4540  1.232    bouyer 
   4541  1.281   msaitoh 	/* Must release the MDIO ownership after MAC reset */
   4542  1.281   msaitoh 	switch (sc->sc_type) {
   4543  1.281   msaitoh 	case WM_T_82573:
   4544  1.281   msaitoh 	case WM_T_82574:
   4545  1.281   msaitoh 	case WM_T_82583:
   4546  1.281   msaitoh 		if (error == 0)
   4547  1.281   msaitoh 			wm_put_hw_semaphore_82573(sc);
   4548  1.281   msaitoh 		break;
   4549  1.281   msaitoh 	default:
   4550  1.281   msaitoh 		break;
   4551  1.232    bouyer 	}
   4552  1.232    bouyer 
   4553  1.437   msaitoh 	if (phy_reset != 0)
   4554  1.281   msaitoh 		wm_get_cfg_done(sc);
   4555  1.232    bouyer 
   4556  1.281   msaitoh 	/* reload EEPROM */
   4557  1.281   msaitoh 	switch (sc->sc_type) {
   4558  1.281   msaitoh 	case WM_T_82542_2_0:
   4559  1.281   msaitoh 	case WM_T_82542_2_1:
   4560  1.281   msaitoh 	case WM_T_82543:
   4561  1.281   msaitoh 	case WM_T_82544:
   4562  1.281   msaitoh 		delay(10);
   4563  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
   4564  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4565  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   4566  1.281   msaitoh 		delay(2000);
   4567  1.281   msaitoh 		break;
   4568  1.281   msaitoh 	case WM_T_82540:
   4569  1.281   msaitoh 	case WM_T_82545:
   4570  1.281   msaitoh 	case WM_T_82545_3:
   4571  1.281   msaitoh 	case WM_T_82546:
   4572  1.281   msaitoh 	case WM_T_82546_3:
   4573  1.281   msaitoh 		delay(5*1000);
   4574  1.281   msaitoh 		/* XXX Disable HW ARPs on ASF enabled adapters */
   4575  1.281   msaitoh 		break;
   4576  1.281   msaitoh 	case WM_T_82541:
   4577  1.281   msaitoh 	case WM_T_82541_2:
   4578  1.281   msaitoh 	case WM_T_82547:
   4579  1.281   msaitoh 	case WM_T_82547_2:
   4580  1.281   msaitoh 		delay(20000);
   4581  1.281   msaitoh 		/* XXX Disable HW ARPs on ASF enabled adapters */
   4582  1.281   msaitoh 		break;
   4583  1.281   msaitoh 	case WM_T_82571:
   4584  1.281   msaitoh 	case WM_T_82572:
   4585  1.281   msaitoh 	case WM_T_82573:
   4586  1.281   msaitoh 	case WM_T_82574:
   4587  1.281   msaitoh 	case WM_T_82583:
   4588  1.281   msaitoh 		if (sc->sc_flags & WM_F_EEPROM_FLASH) {
   4589  1.281   msaitoh 			delay(10);
   4590  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
   4591  1.281   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4592  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   4593  1.232    bouyer 		}
   4594  1.281   msaitoh 		/* check EECD_EE_AUTORD */
   4595  1.281   msaitoh 		wm_get_auto_rd_done(sc);
   4596  1.281   msaitoh 		/*
   4597  1.281   msaitoh 		 * Phy configuration from NVM just starts after EECD_AUTO_RD
   4598  1.281   msaitoh 		 * is set.
   4599  1.281   msaitoh 		 */
   4600  1.281   msaitoh 		if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574)
   4601  1.281   msaitoh 		    || (sc->sc_type == WM_T_82583))
   4602  1.281   msaitoh 			delay(25*1000);
   4603  1.281   msaitoh 		break;
   4604  1.281   msaitoh 	case WM_T_82575:
   4605  1.281   msaitoh 	case WM_T_82576:
   4606  1.281   msaitoh 	case WM_T_82580:
   4607  1.281   msaitoh 	case WM_T_I350:
   4608  1.281   msaitoh 	case WM_T_I354:
   4609  1.281   msaitoh 	case WM_T_I210:
   4610  1.281   msaitoh 	case WM_T_I211:
   4611  1.281   msaitoh 	case WM_T_80003:
   4612  1.281   msaitoh 		/* check EECD_EE_AUTORD */
   4613  1.281   msaitoh 		wm_get_auto_rd_done(sc);
   4614  1.281   msaitoh 		break;
   4615  1.281   msaitoh 	case WM_T_ICH8:
   4616  1.281   msaitoh 	case WM_T_ICH9:
   4617  1.281   msaitoh 	case WM_T_ICH10:
   4618  1.281   msaitoh 	case WM_T_PCH:
   4619  1.281   msaitoh 	case WM_T_PCH2:
   4620  1.281   msaitoh 	case WM_T_PCH_LPT:
   4621  1.392   msaitoh 	case WM_T_PCH_SPT:
   4622  1.281   msaitoh 		break;
   4623  1.281   msaitoh 	default:
   4624  1.281   msaitoh 		panic("%s: unknown type\n", __func__);
   4625  1.232    bouyer 	}
   4626  1.281   msaitoh 
   4627  1.281   msaitoh 	/* Check whether EEPROM is present or not */
   4628  1.281   msaitoh 	switch (sc->sc_type) {
   4629  1.281   msaitoh 	case WM_T_82575:
   4630  1.281   msaitoh 	case WM_T_82576:
   4631  1.281   msaitoh 	case WM_T_82580:
   4632  1.281   msaitoh 	case WM_T_I350:
   4633  1.281   msaitoh 	case WM_T_I354:
   4634  1.281   msaitoh 	case WM_T_ICH8:
   4635  1.281   msaitoh 	case WM_T_ICH9:
   4636  1.281   msaitoh 		if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
   4637  1.281   msaitoh 			/* Not found */
   4638  1.281   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVALID;
   4639  1.325   msaitoh 			if (sc->sc_type == WM_T_82575)
   4640  1.281   msaitoh 				wm_reset_init_script_82575(sc);
   4641  1.232    bouyer 		}
   4642  1.281   msaitoh 		break;
   4643  1.281   msaitoh 	default:
   4644  1.281   msaitoh 		break;
   4645  1.281   msaitoh 	}
   4646  1.281   msaitoh 
   4647  1.517   msaitoh 	if (phy_reset != 0)
   4648  1.517   msaitoh 		wm_phy_post_reset(sc);
   4649  1.517   msaitoh 
   4650  1.300   msaitoh 	if ((sc->sc_type == WM_T_82580)
   4651  1.281   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
   4652  1.281   msaitoh 		/* clear global device reset status bit */
   4653  1.281   msaitoh 		CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
   4654  1.281   msaitoh 	}
   4655  1.281   msaitoh 
   4656  1.281   msaitoh 	/* Clear any pending interrupt events. */
   4657  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   4658  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_ICR);
   4659  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   4660  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   4661  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   4662  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   4663  1.335   msaitoh 		} else
   4664  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   4665  1.335   msaitoh 	}
   4666  1.281   msaitoh 
   4667  1.510   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4668  1.510   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   4669  1.510   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   4670  1.510   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT)) {
   4671  1.510   msaitoh 		reg = CSR_READ(sc, WMREG_KABGTXD);
   4672  1.510   msaitoh 		reg |= KABGTXD_BGSQLBIAS;
   4673  1.510   msaitoh 		CSR_WRITE(sc, WMREG_KABGTXD, reg);
   4674  1.510   msaitoh 	}
   4675  1.510   msaitoh 
   4676  1.281   msaitoh 	/* reload sc_ctrl */
   4677  1.281   msaitoh 	sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   4678  1.281   msaitoh 
   4679  1.322   msaitoh 	if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
   4680  1.281   msaitoh 		wm_set_eee_i350(sc);
   4681  1.281   msaitoh 
   4682  1.281   msaitoh 	/*
   4683  1.281   msaitoh 	 * For PCH, this write will make sure that any noise will be detected
   4684  1.281   msaitoh 	 * as a CRC error and be dropped rather than show up as a bad packet
   4685  1.281   msaitoh 	 * to the DMA engine
   4686  1.281   msaitoh 	 */
   4687  1.281   msaitoh 	if (sc->sc_type == WM_T_PCH)
   4688  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565);
   4689  1.281   msaitoh 
   4690  1.380   msaitoh 	if (sc->sc_type >= WM_T_82544)
   4691  1.281   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   4692  1.281   msaitoh 
   4693  1.325   msaitoh 	wm_reset_mdicnfg_82580(sc);
   4694  1.332   msaitoh 
   4695  1.332   msaitoh 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
   4696  1.332   msaitoh 		wm_pll_workaround_i210(sc);
   4697  1.531   msaitoh 
   4698  1.531   msaitoh 	if (sc->sc_type == WM_T_80003) {
   4699  1.531   msaitoh 		/* default to TRUE to enable the MDIC W/A */
   4700  1.531   msaitoh 		sc->sc_flags |= WM_F_80003_MDIC_WA;
   4701  1.531   msaitoh 
   4702  1.531   msaitoh 		rv = wm_kmrn_readreg(sc,
   4703  1.531   msaitoh 		    KUMCTRLSTA_OFFSET >> KUMCTRLSTA_OFFSET_SHIFT, &kmreg);
   4704  1.531   msaitoh 		if (rv == 0) {
   4705  1.531   msaitoh 			if ((kmreg & KUMCTRLSTA_OPMODE_MASK)
   4706  1.531   msaitoh 			    == KUMCTRLSTA_OPMODE_INBAND_MDIO)
   4707  1.531   msaitoh 				sc->sc_flags &= ~WM_F_80003_MDIC_WA;
   4708  1.531   msaitoh 			else
   4709  1.531   msaitoh 				sc->sc_flags |= WM_F_80003_MDIC_WA;
   4710  1.531   msaitoh 		}
   4711  1.531   msaitoh 	}
   4712  1.281   msaitoh }
   4713  1.281   msaitoh 
   4714  1.281   msaitoh /*
   4715  1.281   msaitoh  * wm_add_rxbuf:
   4716  1.281   msaitoh  *
   4717  1.281   msaitoh  *	Add a receive buffer to the indiciated descriptor.
   4718  1.281   msaitoh  */
   4719  1.281   msaitoh static int
   4720  1.362  knakahar wm_add_rxbuf(struct wm_rxqueue *rxq, int idx)
   4721  1.281   msaitoh {
   4722  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   4723  1.356  knakahar 	struct wm_rxsoft *rxs = &rxq->rxq_soft[idx];
   4724  1.281   msaitoh 	struct mbuf *m;
   4725  1.281   msaitoh 	int error;
   4726  1.281   msaitoh 
   4727  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   4728  1.281   msaitoh 
   4729  1.281   msaitoh 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   4730  1.281   msaitoh 	if (m == NULL)
   4731  1.281   msaitoh 		return ENOBUFS;
   4732  1.281   msaitoh 
   4733  1.281   msaitoh 	MCLGET(m, M_DONTWAIT);
   4734  1.281   msaitoh 	if ((m->m_flags & M_EXT) == 0) {
   4735  1.281   msaitoh 		m_freem(m);
   4736  1.281   msaitoh 		return ENOBUFS;
   4737  1.281   msaitoh 	}
   4738  1.281   msaitoh 
   4739  1.281   msaitoh 	if (rxs->rxs_mbuf != NULL)
   4740  1.281   msaitoh 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   4741  1.281   msaitoh 
   4742  1.281   msaitoh 	rxs->rxs_mbuf = m;
   4743  1.281   msaitoh 
   4744  1.281   msaitoh 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
   4745  1.281   msaitoh 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
   4746  1.388   msaitoh 	    BUS_DMA_READ | BUS_DMA_NOWAIT);
   4747  1.281   msaitoh 	if (error) {
   4748  1.281   msaitoh 		/* XXX XXX XXX */
   4749  1.281   msaitoh 		aprint_error_dev(sc->sc_dev,
   4750  1.281   msaitoh 		    "unable to load rx DMA map %d, error = %d\n",
   4751  1.281   msaitoh 		    idx, error);
   4752  1.281   msaitoh 		panic("wm_add_rxbuf");
   4753  1.232    bouyer 	}
   4754  1.232    bouyer 
   4755  1.281   msaitoh 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   4756  1.281   msaitoh 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   4757  1.281   msaitoh 
   4758  1.281   msaitoh 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   4759  1.281   msaitoh 		if ((sc->sc_rctl & RCTL_EN) != 0)
   4760  1.362  knakahar 			wm_init_rxdesc(rxq, idx);
   4761  1.281   msaitoh 	} else
   4762  1.362  knakahar 		wm_init_rxdesc(rxq, idx);
   4763  1.281   msaitoh 
   4764  1.232    bouyer 	return 0;
   4765  1.232    bouyer }
   4766  1.232    bouyer 
   4767  1.232    bouyer /*
   4768  1.281   msaitoh  * wm_rxdrain:
   4769  1.232    bouyer  *
   4770  1.281   msaitoh  *	Drain the receive queue.
   4771  1.232    bouyer  */
   4772  1.232    bouyer static void
   4773  1.362  knakahar wm_rxdrain(struct wm_rxqueue *rxq)
   4774  1.281   msaitoh {
   4775  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   4776  1.281   msaitoh 	struct wm_rxsoft *rxs;
   4777  1.281   msaitoh 	int i;
   4778  1.281   msaitoh 
   4779  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   4780  1.281   msaitoh 
   4781  1.281   msaitoh 	for (i = 0; i < WM_NRXDESC; i++) {
   4782  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   4783  1.281   msaitoh 		if (rxs->rxs_mbuf != NULL) {
   4784  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   4785  1.281   msaitoh 			m_freem(rxs->rxs_mbuf);
   4786  1.281   msaitoh 			rxs->rxs_mbuf = NULL;
   4787  1.281   msaitoh 		}
   4788  1.281   msaitoh 	}
   4789  1.281   msaitoh }
   4790  1.281   msaitoh 
   4791  1.372  knakahar 
   4792  1.372  knakahar /*
   4793  1.372  knakahar  * XXX copy from FreeBSD's sys/net/rss_config.c
   4794  1.372  knakahar  */
   4795  1.372  knakahar /*
   4796  1.372  knakahar  * RSS secret key, intended to prevent attacks on load-balancing.  Its
   4797  1.372  knakahar  * effectiveness may be limited by algorithm choice and available entropy
   4798  1.372  knakahar  * during the boot.
   4799  1.372  knakahar  *
   4800  1.372  knakahar  * XXXRW: And that we don't randomize it yet!
   4801  1.372  knakahar  *
   4802  1.372  knakahar  * This is the default Microsoft RSS specification key which is also
   4803  1.372  knakahar  * the Chelsio T5 firmware default key.
   4804  1.372  knakahar  */
   4805  1.372  knakahar #define RSS_KEYSIZE 40
   4806  1.372  knakahar static uint8_t wm_rss_key[RSS_KEYSIZE] = {
   4807  1.372  knakahar 	0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
   4808  1.372  knakahar 	0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
   4809  1.372  knakahar 	0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
   4810  1.372  knakahar 	0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
   4811  1.372  knakahar 	0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa,
   4812  1.372  knakahar };
   4813  1.372  knakahar 
   4814  1.372  knakahar /*
   4815  1.372  knakahar  * Caller must pass an array of size sizeof(rss_key).
   4816  1.372  knakahar  *
   4817  1.372  knakahar  * XXX
   4818  1.372  knakahar  * As if_ixgbe may use this function, this function should not be
   4819  1.372  knakahar  * if_wm specific function.
   4820  1.372  knakahar  */
   4821  1.372  knakahar static void
   4822  1.372  knakahar wm_rss_getkey(uint8_t *key)
   4823  1.372  knakahar {
   4824  1.373  knakahar 
   4825  1.372  knakahar 	memcpy(key, wm_rss_key, sizeof(wm_rss_key));
   4826  1.372  knakahar }
   4827  1.372  knakahar 
   4828  1.365  knakahar /*
   4829  1.367  knakahar  * Setup registers for RSS.
   4830  1.367  knakahar  *
   4831  1.367  knakahar  * XXX not yet VMDq support
   4832  1.367  knakahar  */
   4833  1.367  knakahar static void
   4834  1.367  knakahar wm_init_rss(struct wm_softc *sc)
   4835  1.367  knakahar {
   4836  1.372  knakahar 	uint32_t mrqc, reta_reg, rss_key[RSSRK_NUM_REGS];
   4837  1.367  knakahar 	int i;
   4838  1.367  knakahar 
   4839  1.373  knakahar 	CTASSERT(sizeof(rss_key) == sizeof(wm_rss_key));
   4840  1.373  knakahar 
   4841  1.367  knakahar 	for (i = 0; i < RETA_NUM_ENTRIES; i++) {
   4842  1.367  knakahar 		int qid, reta_ent;
   4843  1.367  knakahar 
   4844  1.405  knakahar 		qid  = i % sc->sc_nqueues;
   4845  1.367  knakahar 		switch(sc->sc_type) {
   4846  1.367  knakahar 		case WM_T_82574:
   4847  1.367  knakahar 			reta_ent = __SHIFTIN(qid,
   4848  1.367  knakahar 			    RETA_ENT_QINDEX_MASK_82574);
   4849  1.367  knakahar 			break;
   4850  1.367  knakahar 		case WM_T_82575:
   4851  1.367  knakahar 			reta_ent = __SHIFTIN(qid,
   4852  1.367  knakahar 			    RETA_ENT_QINDEX1_MASK_82575);
   4853  1.367  knakahar 			break;
   4854  1.367  knakahar 		default:
   4855  1.367  knakahar 			reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK);
   4856  1.367  knakahar 			break;
   4857  1.367  knakahar 		}
   4858  1.367  knakahar 
   4859  1.367  knakahar 		reta_reg = CSR_READ(sc, WMREG_RETA_Q(i));
   4860  1.367  knakahar 		reta_reg &= ~RETA_ENTRY_MASK_Q(i);
   4861  1.367  knakahar 		reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i));
   4862  1.367  knakahar 		CSR_WRITE(sc, WMREG_RETA_Q(i), reta_reg);
   4863  1.367  knakahar 	}
   4864  1.367  knakahar 
   4865  1.372  knakahar 	wm_rss_getkey((uint8_t *)rss_key);
   4866  1.367  knakahar 	for (i = 0; i < RSSRK_NUM_REGS; i++)
   4867  1.372  knakahar 		CSR_WRITE(sc, WMREG_RSSRK(i), rss_key[i]);
   4868  1.367  knakahar 
   4869  1.367  knakahar 	if (sc->sc_type == WM_T_82574)
   4870  1.367  knakahar 		mrqc = MRQC_ENABLE_RSS_MQ_82574;
   4871  1.367  knakahar 	else
   4872  1.367  knakahar 		mrqc = MRQC_ENABLE_RSS_MQ;
   4873  1.367  knakahar 
   4874  1.462   msaitoh 	/*
   4875  1.462   msaitoh 	 * MRQC_RSS_FIELD_IPV6_EX is not set because of an errata.
   4876  1.462   msaitoh 	 * See IPV6EXDIS bit in wm_initialize_hardware_bits().
   4877  1.367  knakahar 	 */
   4878  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV4 | MRQC_RSS_FIELD_IPV4_TCP);
   4879  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV6 | MRQC_RSS_FIELD_IPV6_TCP);
   4880  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV4_UDP | MRQC_RSS_FIELD_IPV6_UDP);
   4881  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV6_UDP_EX | MRQC_RSS_FIELD_IPV6_TCP_EX);
   4882  1.367  knakahar 
   4883  1.367  knakahar 	CSR_WRITE(sc, WMREG_MRQC, mrqc);
   4884  1.367  knakahar }
   4885  1.367  knakahar 
   4886  1.367  knakahar /*
   4887  1.365  knakahar  * Adjust TX and RX queue numbers which the system actulally uses.
   4888  1.365  knakahar  *
   4889  1.365  knakahar  * The numbers are affected by below parameters.
   4890  1.365  knakahar  *     - The nubmer of hardware queues
   4891  1.365  knakahar  *     - The number of MSI-X vectors (= "nvectors" argument)
   4892  1.365  knakahar  *     - ncpu
   4893  1.365  knakahar  */
   4894  1.365  knakahar static void
   4895  1.365  knakahar wm_adjust_qnum(struct wm_softc *sc, int nvectors)
   4896  1.365  knakahar {
   4897  1.405  knakahar 	int hw_ntxqueues, hw_nrxqueues, hw_nqueues;
   4898  1.365  knakahar 
   4899  1.405  knakahar 	if (nvectors < 2) {
   4900  1.405  knakahar 		sc->sc_nqueues = 1;
   4901  1.365  knakahar 		return;
   4902  1.365  knakahar 	}
   4903  1.365  knakahar 
   4904  1.365  knakahar 	switch(sc->sc_type) {
   4905  1.365  knakahar 	case WM_T_82572:
   4906  1.365  knakahar 		hw_ntxqueues = 2;
   4907  1.365  knakahar 		hw_nrxqueues = 2;
   4908  1.365  knakahar 		break;
   4909  1.365  knakahar 	case WM_T_82574:
   4910  1.365  knakahar 		hw_ntxqueues = 2;
   4911  1.365  knakahar 		hw_nrxqueues = 2;
   4912  1.365  knakahar 		break;
   4913  1.365  knakahar 	case WM_T_82575:
   4914  1.365  knakahar 		hw_ntxqueues = 4;
   4915  1.365  knakahar 		hw_nrxqueues = 4;
   4916  1.365  knakahar 		break;
   4917  1.365  knakahar 	case WM_T_82576:
   4918  1.365  knakahar 		hw_ntxqueues = 16;
   4919  1.365  knakahar 		hw_nrxqueues = 16;
   4920  1.365  knakahar 		break;
   4921  1.365  knakahar 	case WM_T_82580:
   4922  1.365  knakahar 	case WM_T_I350:
   4923  1.365  knakahar 	case WM_T_I354:
   4924  1.365  knakahar 		hw_ntxqueues = 8;
   4925  1.365  knakahar 		hw_nrxqueues = 8;
   4926  1.365  knakahar 		break;
   4927  1.365  knakahar 	case WM_T_I210:
   4928  1.365  knakahar 		hw_ntxqueues = 4;
   4929  1.365  knakahar 		hw_nrxqueues = 4;
   4930  1.365  knakahar 		break;
   4931  1.365  knakahar 	case WM_T_I211:
   4932  1.365  knakahar 		hw_ntxqueues = 2;
   4933  1.365  knakahar 		hw_nrxqueues = 2;
   4934  1.365  knakahar 		break;
   4935  1.365  knakahar 		/*
   4936  1.365  knakahar 		 * As below ethernet controllers does not support MSI-X,
   4937  1.365  knakahar 		 * this driver let them not use multiqueue.
   4938  1.365  knakahar 		 *     - WM_T_80003
   4939  1.365  knakahar 		 *     - WM_T_ICH8
   4940  1.365  knakahar 		 *     - WM_T_ICH9
   4941  1.365  knakahar 		 *     - WM_T_ICH10
   4942  1.365  knakahar 		 *     - WM_T_PCH
   4943  1.365  knakahar 		 *     - WM_T_PCH2
   4944  1.365  knakahar 		 *     - WM_T_PCH_LPT
   4945  1.365  knakahar 		 */
   4946  1.365  knakahar 	default:
   4947  1.365  knakahar 		hw_ntxqueues = 1;
   4948  1.365  knakahar 		hw_nrxqueues = 1;
   4949  1.365  knakahar 		break;
   4950  1.365  knakahar 	}
   4951  1.365  knakahar 
   4952  1.405  knakahar 	hw_nqueues = min(hw_ntxqueues, hw_nrxqueues);
   4953  1.405  knakahar 
   4954  1.365  knakahar 	/*
   4955  1.405  knakahar 	 * As queues more than MSI-X vectors cannot improve scaling, we limit
   4956  1.365  knakahar 	 * the number of queues used actually.
   4957  1.405  knakahar 	 */
   4958  1.405  knakahar 	if (nvectors < hw_nqueues + 1) {
   4959  1.405  knakahar 		sc->sc_nqueues = nvectors - 1;
   4960  1.365  knakahar 	} else {
   4961  1.405  knakahar 		sc->sc_nqueues = hw_nqueues;
   4962  1.365  knakahar 	}
   4963  1.365  knakahar 
   4964  1.365  knakahar 	/*
   4965  1.365  knakahar 	 * As queues more then cpus cannot improve scaling, we limit
   4966  1.365  knakahar 	 * the number of queues used actually.
   4967  1.365  knakahar 	 */
   4968  1.405  knakahar 	if (ncpu < sc->sc_nqueues)
   4969  1.405  knakahar 		sc->sc_nqueues = ncpu;
   4970  1.365  knakahar }
   4971  1.365  knakahar 
   4972  1.502  knakahar static inline bool
   4973  1.502  knakahar wm_is_using_msix(struct wm_softc *sc)
   4974  1.502  knakahar {
   4975  1.502  knakahar 
   4976  1.502  knakahar 	return (sc->sc_nintrs > 1);
   4977  1.502  knakahar }
   4978  1.502  knakahar 
   4979  1.502  knakahar static inline bool
   4980  1.502  knakahar wm_is_using_multiqueue(struct wm_softc *sc)
   4981  1.502  knakahar {
   4982  1.502  knakahar 
   4983  1.502  knakahar 	return (sc->sc_nqueues > 1);
   4984  1.502  knakahar }
   4985  1.502  knakahar 
   4986  1.485  christos static int
   4987  1.485  christos wm_softint_establish(struct wm_softc *sc, int qidx, int intr_idx)
   4988  1.485  christos {
   4989  1.485  christos 	struct wm_queue *wmq = &sc->sc_queue[qidx];
   4990  1.485  christos 	wmq->wmq_id = qidx;
   4991  1.485  christos 	wmq->wmq_intr_idx = intr_idx;
   4992  1.485  christos 	wmq->wmq_si = softint_establish(SOFTINT_NET
   4993  1.485  christos #ifdef WM_MPSAFE
   4994  1.485  christos 	    | SOFTINT_MPSAFE
   4995  1.485  christos #endif
   4996  1.485  christos 	    , wm_handle_queue, wmq);
   4997  1.485  christos 	if (wmq->wmq_si != NULL)
   4998  1.485  christos 		return 0;
   4999  1.485  christos 
   5000  1.485  christos 	aprint_error_dev(sc->sc_dev, "unable to establish queue[%d] handler\n",
   5001  1.485  christos 	    wmq->wmq_id);
   5002  1.485  christos 
   5003  1.485  christos 	pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[wmq->wmq_intr_idx]);
   5004  1.485  christos 	sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
   5005  1.485  christos 	return ENOMEM;
   5006  1.485  christos }
   5007  1.485  christos 
   5008  1.365  knakahar /*
   5009  1.360  knakahar  * Both single interrupt MSI and INTx can use this function.
   5010  1.360  knakahar  */
   5011  1.360  knakahar static int
   5012  1.360  knakahar wm_setup_legacy(struct wm_softc *sc)
   5013  1.360  knakahar {
   5014  1.360  knakahar 	pci_chipset_tag_t pc = sc->sc_pc;
   5015  1.360  knakahar 	const char *intrstr = NULL;
   5016  1.360  knakahar 	char intrbuf[PCI_INTRSTR_LEN];
   5017  1.375   msaitoh 	int error;
   5018  1.360  knakahar 
   5019  1.375   msaitoh 	error = wm_alloc_txrx_queues(sc);
   5020  1.375   msaitoh 	if (error) {
   5021  1.375   msaitoh 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
   5022  1.375   msaitoh 		    error);
   5023  1.375   msaitoh 		return ENOMEM;
   5024  1.375   msaitoh 	}
   5025  1.360  knakahar 	intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf,
   5026  1.360  knakahar 	    sizeof(intrbuf));
   5027  1.360  knakahar #ifdef WM_MPSAFE
   5028  1.360  knakahar 	pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true);
   5029  1.360  knakahar #endif
   5030  1.360  knakahar 	sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0],
   5031  1.360  knakahar 	    IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev));
   5032  1.360  knakahar 	if (sc->sc_ihs[0] == NULL) {
   5033  1.360  knakahar 		aprint_error_dev(sc->sc_dev,"unable to establish %s\n",
   5034  1.416  knakahar 		    (pci_intr_type(pc, sc->sc_intrs[0])
   5035  1.360  knakahar 			== PCI_INTR_TYPE_MSI) ? "MSI" : "INTx");
   5036  1.360  knakahar 		return ENOMEM;
   5037  1.360  knakahar 	}
   5038  1.360  knakahar 
   5039  1.360  knakahar 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
   5040  1.360  knakahar 	sc->sc_nintrs = 1;
   5041  1.485  christos 
   5042  1.485  christos 	return wm_softint_establish(sc, 0, 0);
   5043  1.360  knakahar }
   5044  1.360  knakahar 
   5045  1.360  knakahar static int
   5046  1.360  knakahar wm_setup_msix(struct wm_softc *sc)
   5047  1.360  knakahar {
   5048  1.360  knakahar 	void *vih;
   5049  1.360  knakahar 	kcpuset_t *affinity;
   5050  1.405  knakahar 	int qidx, error, intr_idx, txrx_established;
   5051  1.360  knakahar 	pci_chipset_tag_t pc = sc->sc_pc;
   5052  1.360  knakahar 	const char *intrstr = NULL;
   5053  1.360  knakahar 	char intrbuf[PCI_INTRSTR_LEN];
   5054  1.360  knakahar 	char intr_xname[INTRDEVNAMEBUF];
   5055  1.404  knakahar 
   5056  1.405  knakahar 	if (sc->sc_nqueues < ncpu) {
   5057  1.404  knakahar 		/*
   5058  1.404  knakahar 		 * To avoid other devices' interrupts, the affinity of Tx/Rx
   5059  1.404  knakahar 		 * interrupts start from CPU#1.
   5060  1.404  knakahar 		 */
   5061  1.404  knakahar 		sc->sc_affinity_offset = 1;
   5062  1.404  knakahar 	} else {
   5063  1.404  knakahar 		/*
   5064  1.404  knakahar 		 * In this case, this device use all CPUs. So, we unify
   5065  1.404  knakahar 		 * affinitied cpu_index to msix vector number for readability.
   5066  1.404  knakahar 		 */
   5067  1.404  knakahar 		sc->sc_affinity_offset = 0;
   5068  1.404  knakahar 	}
   5069  1.360  knakahar 
   5070  1.375   msaitoh 	error = wm_alloc_txrx_queues(sc);
   5071  1.375   msaitoh 	if (error) {
   5072  1.375   msaitoh 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
   5073  1.375   msaitoh 		    error);
   5074  1.375   msaitoh 		return ENOMEM;
   5075  1.375   msaitoh 	}
   5076  1.375   msaitoh 
   5077  1.364  knakahar 	kcpuset_create(&affinity, false);
   5078  1.364  knakahar 	intr_idx = 0;
   5079  1.363  knakahar 
   5080  1.364  knakahar 	/*
   5081  1.405  knakahar 	 * TX and RX
   5082  1.364  knakahar 	 */
   5083  1.405  knakahar 	txrx_established = 0;
   5084  1.405  knakahar 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5085  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   5086  1.404  knakahar 		int affinity_to = (sc->sc_affinity_offset + intr_idx) % ncpu;
   5087  1.364  knakahar 
   5088  1.364  knakahar 		intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
   5089  1.364  knakahar 		    sizeof(intrbuf));
   5090  1.364  knakahar #ifdef WM_MPSAFE
   5091  1.364  knakahar 		pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
   5092  1.364  knakahar 		    PCI_INTR_MPSAFE, true);
   5093  1.364  knakahar #endif
   5094  1.364  knakahar 		memset(intr_xname, 0, sizeof(intr_xname));
   5095  1.405  knakahar 		snprintf(intr_xname, sizeof(intr_xname), "%sTXRX%d",
   5096  1.364  knakahar 		    device_xname(sc->sc_dev), qidx);
   5097  1.364  knakahar 		vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
   5098  1.405  knakahar 		    IPL_NET, wm_txrxintr_msix, wmq, intr_xname);
   5099  1.364  knakahar 		if (vih == NULL) {
   5100  1.364  knakahar 			aprint_error_dev(sc->sc_dev,
   5101  1.405  knakahar 			    "unable to establish MSI-X(for TX and RX)%s%s\n",
   5102  1.364  knakahar 			    intrstr ? " at " : "",
   5103  1.364  knakahar 			    intrstr ? intrstr : "");
   5104  1.364  knakahar 
   5105  1.405  knakahar 			goto fail;
   5106  1.360  knakahar 		}
   5107  1.360  knakahar 		kcpuset_zero(affinity);
   5108  1.360  knakahar 		/* Round-robin affinity */
   5109  1.383  knakahar 		kcpuset_set(affinity, affinity_to);
   5110  1.360  knakahar 		error = interrupt_distribute(vih, affinity, NULL);
   5111  1.360  knakahar 		if (error == 0) {
   5112  1.360  knakahar 			aprint_normal_dev(sc->sc_dev,
   5113  1.405  knakahar 			    "for TX and RX interrupting at %s affinity to %u\n",
   5114  1.383  knakahar 			    intrstr, affinity_to);
   5115  1.360  knakahar 		} else {
   5116  1.360  knakahar 			aprint_normal_dev(sc->sc_dev,
   5117  1.405  knakahar 			    "for TX and RX interrupting at %s\n", intrstr);
   5118  1.360  knakahar 		}
   5119  1.364  knakahar 		sc->sc_ihs[intr_idx] = vih;
   5120  1.485  christos 		if (wm_softint_establish(sc, qidx, intr_idx) != 0)
   5121  1.484  knakahar 			goto fail;
   5122  1.405  knakahar 		txrx_established++;
   5123  1.364  knakahar 		intr_idx++;
   5124  1.364  knakahar 	}
   5125  1.364  knakahar 
   5126  1.364  knakahar 	/*
   5127  1.364  knakahar 	 * LINK
   5128  1.364  knakahar 	 */
   5129  1.364  knakahar 	intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
   5130  1.364  knakahar 	    sizeof(intrbuf));
   5131  1.364  knakahar #ifdef WM_MPSAFE
   5132  1.388   msaitoh 	pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], PCI_INTR_MPSAFE, true);
   5133  1.364  knakahar #endif
   5134  1.364  knakahar 	memset(intr_xname, 0, sizeof(intr_xname));
   5135  1.364  knakahar 	snprintf(intr_xname, sizeof(intr_xname), "%sLINK",
   5136  1.364  knakahar 	    device_xname(sc->sc_dev));
   5137  1.364  knakahar 	vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
   5138  1.364  knakahar 		    IPL_NET, wm_linkintr_msix, sc, intr_xname);
   5139  1.364  knakahar 	if (vih == NULL) {
   5140  1.364  knakahar 		aprint_error_dev(sc->sc_dev,
   5141  1.364  knakahar 		    "unable to establish MSI-X(for LINK)%s%s\n",
   5142  1.364  knakahar 		    intrstr ? " at " : "",
   5143  1.364  knakahar 		    intrstr ? intrstr : "");
   5144  1.364  knakahar 
   5145  1.405  knakahar 		goto fail;
   5146  1.360  knakahar 	}
   5147  1.364  knakahar 	/* keep default affinity to LINK interrupt */
   5148  1.364  knakahar 	aprint_normal_dev(sc->sc_dev,
   5149  1.364  knakahar 	    "for LINK interrupting at %s\n", intrstr);
   5150  1.364  knakahar 	sc->sc_ihs[intr_idx] = vih;
   5151  1.364  knakahar 	sc->sc_link_intr_idx = intr_idx;
   5152  1.360  knakahar 
   5153  1.405  knakahar 	sc->sc_nintrs = sc->sc_nqueues + 1;
   5154  1.360  knakahar 	kcpuset_destroy(affinity);
   5155  1.360  knakahar 	return 0;
   5156  1.364  knakahar 
   5157  1.405  knakahar  fail:
   5158  1.405  knakahar 	for (qidx = 0; qidx < txrx_established; qidx++) {
   5159  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   5160  1.405  knakahar 		pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[wmq->wmq_intr_idx]);
   5161  1.405  knakahar 		sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
   5162  1.364  knakahar 	}
   5163  1.364  knakahar 
   5164  1.364  knakahar 	kcpuset_destroy(affinity);
   5165  1.364  knakahar 	return ENOMEM;
   5166  1.360  knakahar }
   5167  1.360  knakahar 
   5168  1.429  knakahar static void
   5169  1.537  knakahar wm_unset_stopping_flags(struct wm_softc *sc)
   5170  1.429  knakahar {
   5171  1.429  knakahar 	int i;
   5172  1.429  knakahar 
   5173  1.436  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5174  1.436  knakahar 
   5175  1.476  knakahar 	/*
   5176  1.476  knakahar 	 * must unset stopping flags in ascending order.
   5177  1.476  knakahar 	 */
   5178  1.429  knakahar 	for(i = 0; i < sc->sc_nqueues; i++) {
   5179  1.429  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   5180  1.429  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   5181  1.429  knakahar 
   5182  1.429  knakahar 		mutex_enter(txq->txq_lock);
   5183  1.429  knakahar 		txq->txq_stopping = false;
   5184  1.429  knakahar 		mutex_exit(txq->txq_lock);
   5185  1.429  knakahar 
   5186  1.429  knakahar 		mutex_enter(rxq->rxq_lock);
   5187  1.429  knakahar 		rxq->rxq_stopping = false;
   5188  1.429  knakahar 		mutex_exit(rxq->rxq_lock);
   5189  1.429  knakahar 	}
   5190  1.429  knakahar 
   5191  1.429  knakahar 	sc->sc_core_stopping = false;
   5192  1.429  knakahar }
   5193  1.429  knakahar 
   5194  1.429  knakahar static void
   5195  1.537  knakahar wm_set_stopping_flags(struct wm_softc *sc)
   5196  1.429  knakahar {
   5197  1.429  knakahar 	int i;
   5198  1.429  knakahar 
   5199  1.436  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5200  1.436  knakahar 
   5201  1.429  knakahar 	sc->sc_core_stopping = true;
   5202  1.429  knakahar 
   5203  1.476  knakahar 	/*
   5204  1.476  knakahar 	 * must set stopping flags in ascending order.
   5205  1.476  knakahar 	 */
   5206  1.429  knakahar 	for(i = 0; i < sc->sc_nqueues; i++) {
   5207  1.429  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   5208  1.429  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   5209  1.429  knakahar 
   5210  1.429  knakahar 		mutex_enter(rxq->rxq_lock);
   5211  1.429  knakahar 		rxq->rxq_stopping = true;
   5212  1.429  knakahar 		mutex_exit(rxq->rxq_lock);
   5213  1.429  knakahar 
   5214  1.429  knakahar 		mutex_enter(txq->txq_lock);
   5215  1.429  knakahar 		txq->txq_stopping = true;
   5216  1.429  knakahar 		mutex_exit(txq->txq_lock);
   5217  1.429  knakahar 	}
   5218  1.429  knakahar }
   5219  1.429  knakahar 
   5220  1.281   msaitoh /*
   5221  1.491  knakahar  * write interrupt interval value to ITR or EITR
   5222  1.491  knakahar  */
   5223  1.491  knakahar static void
   5224  1.491  knakahar wm_itrs_writereg(struct wm_softc *sc, struct wm_queue *wmq)
   5225  1.491  knakahar {
   5226  1.491  knakahar 
   5227  1.495  knakahar 	if (!wmq->wmq_set_itr)
   5228  1.495  knakahar 		return;
   5229  1.495  knakahar 
   5230  1.491  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   5231  1.491  knakahar 		uint32_t eitr = __SHIFTIN(wmq->wmq_itr, EITR_ITR_INT_MASK);
   5232  1.491  knakahar 
   5233  1.491  knakahar 		/*
   5234  1.491  knakahar 		 * 82575 doesn't have CNT_INGR field.
   5235  1.491  knakahar 		 * So, overwrite counter field by software.
   5236  1.491  knakahar 		 */
   5237  1.491  knakahar 		if (sc->sc_type == WM_T_82575)
   5238  1.491  knakahar 			eitr |= __SHIFTIN(wmq->wmq_itr, EITR_COUNTER_MASK_82575);
   5239  1.491  knakahar 		else
   5240  1.491  knakahar 			eitr |= EITR_CNT_INGR;
   5241  1.491  knakahar 
   5242  1.491  knakahar 		CSR_WRITE(sc, WMREG_EITR(wmq->wmq_intr_idx), eitr);
   5243  1.502  knakahar 	} else if (sc->sc_type == WM_T_82574 && wm_is_using_msix(sc)) {
   5244  1.491  knakahar 		/*
   5245  1.491  knakahar 		 * 82574 has both ITR and EITR. SET EITR when we use
   5246  1.491  knakahar 		 * the multi queue function with MSI-X.
   5247  1.491  knakahar 		 */
   5248  1.491  knakahar 		CSR_WRITE(sc, WMREG_EITR_82574(wmq->wmq_intr_idx),
   5249  1.491  knakahar 			    wmq->wmq_itr & EITR_ITR_INT_MASK_82574);
   5250  1.491  knakahar 	} else {
   5251  1.491  knakahar 		KASSERT(wmq->wmq_id == 0);
   5252  1.491  knakahar 		CSR_WRITE(sc, WMREG_ITR, wmq->wmq_itr);
   5253  1.491  knakahar 	}
   5254  1.495  knakahar 
   5255  1.495  knakahar 	wmq->wmq_set_itr = false;
   5256  1.495  knakahar }
   5257  1.495  knakahar 
   5258  1.495  knakahar /*
   5259  1.495  knakahar  * TODO
   5260  1.495  knakahar  * Below dynamic calculation of itr is almost the same as linux igb,
   5261  1.495  knakahar  * however it does not fit to wm(4). So, we will have been disable AIM
   5262  1.495  knakahar  * until we will find appropriate calculation of itr.
   5263  1.495  knakahar  */
   5264  1.495  knakahar /*
   5265  1.495  knakahar  * calculate interrupt interval value to be going to write register in
   5266  1.495  knakahar  * wm_itrs_writereg(). This function does not write ITR/EITR register.
   5267  1.495  knakahar  */
   5268  1.495  knakahar static void
   5269  1.495  knakahar wm_itrs_calculate(struct wm_softc *sc, struct wm_queue *wmq)
   5270  1.495  knakahar {
   5271  1.495  knakahar #ifdef NOTYET
   5272  1.495  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   5273  1.495  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   5274  1.495  knakahar 	uint32_t avg_size = 0;
   5275  1.495  knakahar 	uint32_t new_itr;
   5276  1.495  knakahar 
   5277  1.495  knakahar 	if (rxq->rxq_packets)
   5278  1.495  knakahar 		avg_size =  rxq->rxq_bytes / rxq->rxq_packets;
   5279  1.495  knakahar 	if (txq->txq_packets)
   5280  1.495  knakahar 		avg_size = max(avg_size, txq->txq_bytes / txq->txq_packets);
   5281  1.495  knakahar 
   5282  1.495  knakahar 	if (avg_size == 0) {
   5283  1.495  knakahar 		new_itr = 450; /* restore default value */
   5284  1.495  knakahar 		goto out;
   5285  1.495  knakahar 	}
   5286  1.495  knakahar 
   5287  1.495  knakahar 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
   5288  1.495  knakahar 	avg_size += 24;
   5289  1.495  knakahar 
   5290  1.495  knakahar 	/* Don't starve jumbo frames */
   5291  1.495  knakahar 	avg_size = min(avg_size, 3000);
   5292  1.495  knakahar 
   5293  1.495  knakahar 	/* Give a little boost to mid-size frames */
   5294  1.495  knakahar 	if ((avg_size > 300) && (avg_size < 1200))
   5295  1.495  knakahar 		new_itr = avg_size / 3;
   5296  1.495  knakahar 	else
   5297  1.495  knakahar 		new_itr = avg_size / 2;
   5298  1.495  knakahar 
   5299  1.495  knakahar out:
   5300  1.495  knakahar 	/*
   5301  1.495  knakahar 	 * The usage of 82574 and 82575 EITR is different from otther NEWQUEUE
   5302  1.495  knakahar 	 * controllers. See sc->sc_itr_init setting in wm_init_locked().
   5303  1.495  knakahar 	 */
   5304  1.495  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) == 0 || sc->sc_type != WM_T_82575)
   5305  1.495  knakahar 		new_itr *= 4;
   5306  1.495  knakahar 
   5307  1.495  knakahar 	if (new_itr != wmq->wmq_itr) {
   5308  1.495  knakahar 		wmq->wmq_itr = new_itr;
   5309  1.495  knakahar 		wmq->wmq_set_itr = true;
   5310  1.495  knakahar 	} else
   5311  1.495  knakahar 		wmq->wmq_set_itr = false;
   5312  1.495  knakahar 
   5313  1.495  knakahar 	rxq->rxq_packets = 0;
   5314  1.495  knakahar 	rxq->rxq_bytes = 0;
   5315  1.495  knakahar 	txq->txq_packets = 0;
   5316  1.495  knakahar 	txq->txq_bytes = 0;
   5317  1.495  knakahar #endif
   5318  1.491  knakahar }
   5319  1.491  knakahar 
   5320  1.491  knakahar /*
   5321  1.281   msaitoh  * wm_init:		[ifnet interface function]
   5322  1.281   msaitoh  *
   5323  1.281   msaitoh  *	Initialize the interface.
   5324  1.281   msaitoh  */
   5325  1.281   msaitoh static int
   5326  1.281   msaitoh wm_init(struct ifnet *ifp)
   5327  1.232    bouyer {
   5328  1.232    bouyer 	struct wm_softc *sc = ifp->if_softc;
   5329  1.281   msaitoh 	int ret;
   5330  1.272     ozaki 
   5331  1.357  knakahar 	WM_CORE_LOCK(sc);
   5332  1.281   msaitoh 	ret = wm_init_locked(ifp);
   5333  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   5334  1.281   msaitoh 
   5335  1.281   msaitoh 	return ret;
   5336  1.272     ozaki }
   5337  1.272     ozaki 
   5338  1.281   msaitoh static int
   5339  1.281   msaitoh wm_init_locked(struct ifnet *ifp)
   5340  1.272     ozaki {
   5341  1.272     ozaki 	struct wm_softc *sc = ifp->if_softc;
   5342  1.281   msaitoh 	int i, j, trynum, error = 0;
   5343  1.281   msaitoh 	uint32_t reg;
   5344  1.232    bouyer 
   5345  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   5346  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   5347  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5348  1.420   msaitoh 
   5349  1.232    bouyer 	/*
   5350  1.281   msaitoh 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
   5351  1.281   msaitoh 	 * There is a small but measurable benefit to avoiding the adjusment
   5352  1.281   msaitoh 	 * of the descriptor so that the headers are aligned, for normal mtu,
   5353  1.281   msaitoh 	 * on such platforms.  One possibility is that the DMA itself is
   5354  1.281   msaitoh 	 * slightly more efficient if the front of the entire packet (instead
   5355  1.281   msaitoh 	 * of the front of the headers) is aligned.
   5356  1.281   msaitoh 	 *
   5357  1.281   msaitoh 	 * Note we must always set align_tweak to 0 if we are using
   5358  1.281   msaitoh 	 * jumbo frames.
   5359  1.232    bouyer 	 */
   5360  1.281   msaitoh #ifdef __NO_STRICT_ALIGNMENT
   5361  1.281   msaitoh 	sc->sc_align_tweak = 0;
   5362  1.281   msaitoh #else
   5363  1.281   msaitoh 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
   5364  1.281   msaitoh 		sc->sc_align_tweak = 0;
   5365  1.281   msaitoh 	else
   5366  1.281   msaitoh 		sc->sc_align_tweak = 2;
   5367  1.281   msaitoh #endif /* __NO_STRICT_ALIGNMENT */
   5368  1.281   msaitoh 
   5369  1.281   msaitoh 	/* Cancel any pending I/O. */
   5370  1.281   msaitoh 	wm_stop_locked(ifp, 0);
   5371  1.281   msaitoh 
   5372  1.281   msaitoh 	/* update statistics before reset */
   5373  1.281   msaitoh 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
   5374  1.281   msaitoh 	ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
   5375  1.281   msaitoh 
   5376  1.443   msaitoh 	/* PCH_SPT hardware workaround */
   5377  1.443   msaitoh 	if (sc->sc_type == WM_T_PCH_SPT)
   5378  1.443   msaitoh 		wm_flush_desc_rings(sc);
   5379  1.443   msaitoh 
   5380  1.281   msaitoh 	/* Reset the chip to a known state. */
   5381  1.281   msaitoh 	wm_reset(sc);
   5382  1.281   msaitoh 
   5383  1.518   msaitoh 	/*
   5384  1.518   msaitoh 	 * AMT based hardware can now take control from firmware
   5385  1.518   msaitoh 	 * Do this after reset.
   5386  1.518   msaitoh 	 */
   5387  1.518   msaitoh 	if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
   5388  1.518   msaitoh 		wm_get_hw_control(sc);
   5389  1.518   msaitoh 
   5390  1.517   msaitoh 	if ((sc->sc_type == WM_T_PCH_SPT) &&
   5391  1.517   msaitoh 	    pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
   5392  1.517   msaitoh 		wm_legacy_irq_quirk_spt(sc);
   5393  1.232    bouyer 
   5394  1.312   msaitoh 	/* Init hardware bits */
   5395  1.312   msaitoh 	wm_initialize_hardware_bits(sc);
   5396  1.312   msaitoh 
   5397  1.281   msaitoh 	/* Reset the PHY. */
   5398  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   5399  1.281   msaitoh 		wm_gmii_reset(sc);
   5400  1.232    bouyer 
   5401  1.319   msaitoh 	/* Calculate (E)ITR value */
   5402  1.489  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0 && sc->sc_type != WM_T_82575) {
   5403  1.489  knakahar 		/*
   5404  1.489  knakahar 		 * For NEWQUEUE's EITR (except for 82575).
   5405  1.489  knakahar 		 * 82575's EITR should be set same throttling value as other
   5406  1.489  knakahar 		 * old controllers' ITR because the interrupt/sec calculation
   5407  1.489  knakahar 		 * is the same, that is, 1,000,000,000 / (N * 256).
   5408  1.489  knakahar 		 *
   5409  1.489  knakahar 		 * 82574's EITR should be set same throttling value as ITR.
   5410  1.489  knakahar 		 *
   5411  1.489  knakahar 		 * For N interrupts/sec, set this value to:
   5412  1.489  knakahar 		 * 1,000,000 / N in contrast to ITR throttoling value.
   5413  1.489  knakahar 		 */
   5414  1.490  knakahar 		sc->sc_itr_init = 450;
   5415  1.319   msaitoh 	} else if (sc->sc_type >= WM_T_82543) {
   5416  1.319   msaitoh 		/*
   5417  1.319   msaitoh 		 * Set up the interrupt throttling register (units of 256ns)
   5418  1.319   msaitoh 		 * Note that a footnote in Intel's documentation says this
   5419  1.319   msaitoh 		 * ticker runs at 1/4 the rate when the chip is in 100Mbit
   5420  1.319   msaitoh 		 * or 10Mbit mode.  Empirically, it appears to be the case
   5421  1.319   msaitoh 		 * that that is also true for the 1024ns units of the other
   5422  1.319   msaitoh 		 * interrupt-related timer registers -- so, really, we ought
   5423  1.319   msaitoh 		 * to divide this value by 4 when the link speed is low.
   5424  1.319   msaitoh 		 *
   5425  1.319   msaitoh 		 * XXX implement this division at link speed change!
   5426  1.319   msaitoh 		 */
   5427  1.319   msaitoh 
   5428  1.319   msaitoh 		/*
   5429  1.319   msaitoh 		 * For N interrupts/sec, set this value to:
   5430  1.489  knakahar 		 * 1,000,000,000 / (N * 256).  Note that we set the
   5431  1.319   msaitoh 		 * absolute and packet timer values to this value
   5432  1.319   msaitoh 		 * divided by 4 to get "simple timer" behavior.
   5433  1.319   msaitoh 		 */
   5434  1.490  knakahar 		sc->sc_itr_init = 1500;		/* 2604 ints/sec */
   5435  1.319   msaitoh 	}
   5436  1.319   msaitoh 
   5437  1.355  knakahar 	error = wm_init_txrx_queues(sc);
   5438  1.355  knakahar 	if (error)
   5439  1.355  knakahar 		goto out;
   5440  1.232    bouyer 
   5441  1.281   msaitoh 	/*
   5442  1.281   msaitoh 	 * Clear out the VLAN table -- we don't use it (yet).
   5443  1.281   msaitoh 	 */
   5444  1.281   msaitoh 	CSR_WRITE(sc, WMREG_VET, 0);
   5445  1.281   msaitoh 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   5446  1.281   msaitoh 		trynum = 10; /* Due to hw errata */
   5447  1.281   msaitoh 	else
   5448  1.281   msaitoh 		trynum = 1;
   5449  1.281   msaitoh 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
   5450  1.281   msaitoh 		for (j = 0; j < trynum; j++)
   5451  1.281   msaitoh 			CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
   5452  1.232    bouyer 
   5453  1.281   msaitoh 	/*
   5454  1.281   msaitoh 	 * Set up flow-control parameters.
   5455  1.281   msaitoh 	 *
   5456  1.281   msaitoh 	 * XXX Values could probably stand some tuning.
   5457  1.281   msaitoh 	 */
   5458  1.281   msaitoh 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
   5459  1.281   msaitoh 	    && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
   5460  1.392   msaitoh 	    && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)
   5461  1.392   msaitoh 	    && (sc->sc_type != WM_T_PCH_SPT)) {
   5462  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
   5463  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
   5464  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
   5465  1.281   msaitoh 	}
   5466  1.232    bouyer 
   5467  1.281   msaitoh 	sc->sc_fcrtl = FCRTL_DFLT;
   5468  1.281   msaitoh 	if (sc->sc_type < WM_T_82543) {
   5469  1.281   msaitoh 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
   5470  1.281   msaitoh 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
   5471  1.281   msaitoh 	} else {
   5472  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
   5473  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
   5474  1.281   msaitoh 	}
   5475  1.232    bouyer 
   5476  1.281   msaitoh 	if (sc->sc_type == WM_T_80003)
   5477  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
   5478  1.281   msaitoh 	else
   5479  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
   5480  1.232    bouyer 
   5481  1.281   msaitoh 	/* Writes the control register. */
   5482  1.281   msaitoh 	wm_set_vlan(sc);
   5483  1.232    bouyer 
   5484  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII) {
   5485  1.531   msaitoh 		uint16_t kmreg;
   5486  1.232    bouyer 
   5487  1.281   msaitoh 		switch (sc->sc_type) {
   5488  1.281   msaitoh 		case WM_T_80003:
   5489  1.281   msaitoh 		case WM_T_ICH8:
   5490  1.281   msaitoh 		case WM_T_ICH9:
   5491  1.281   msaitoh 		case WM_T_ICH10:
   5492  1.281   msaitoh 		case WM_T_PCH:
   5493  1.281   msaitoh 		case WM_T_PCH2:
   5494  1.281   msaitoh 		case WM_T_PCH_LPT:
   5495  1.392   msaitoh 		case WM_T_PCH_SPT:
   5496  1.281   msaitoh 			/*
   5497  1.281   msaitoh 			 * Set the mac to wait the maximum time between each
   5498  1.281   msaitoh 			 * iteration and increase the max iterations when
   5499  1.281   msaitoh 			 * polling the phy; this fixes erroneous timeouts at
   5500  1.281   msaitoh 			 * 10Mbps.
   5501  1.281   msaitoh 			 */
   5502  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
   5503  1.281   msaitoh 			    0xFFFF);
   5504  1.531   msaitoh 			wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM,
   5505  1.531   msaitoh 			    &kmreg);
   5506  1.531   msaitoh 			kmreg |= 0x3F;
   5507  1.531   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_PARAM,
   5508  1.531   msaitoh 			    kmreg);
   5509  1.281   msaitoh 			break;
   5510  1.281   msaitoh 		default:
   5511  1.281   msaitoh 			break;
   5512  1.232    bouyer 		}
   5513  1.232    bouyer 
   5514  1.281   msaitoh 		if (sc->sc_type == WM_T_80003) {
   5515  1.531   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5516  1.531   msaitoh 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
   5517  1.531   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   5518  1.232    bouyer 
   5519  1.281   msaitoh 			/* Bypass RX and TX FIFO's */
   5520  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
   5521  1.281   msaitoh 			    KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
   5522  1.281   msaitoh 			    | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
   5523  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
   5524  1.281   msaitoh 			    KUMCTRLSTA_INB_CTRL_DIS_PADDING |
   5525  1.281   msaitoh 			    KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
   5526  1.232    bouyer 		}
   5527  1.281   msaitoh 	}
   5528  1.281   msaitoh #if 0
   5529  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   5530  1.281   msaitoh #endif
   5531  1.232    bouyer 
   5532  1.281   msaitoh 	/* Set up checksum offload parameters. */
   5533  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_RXCSUM);
   5534  1.281   msaitoh 	reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
   5535  1.281   msaitoh 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
   5536  1.281   msaitoh 		reg |= RXCSUM_IPOFL;
   5537  1.281   msaitoh 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
   5538  1.281   msaitoh 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
   5539  1.281   msaitoh 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
   5540  1.281   msaitoh 		reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
   5541  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
   5542  1.232    bouyer 
   5543  1.502  knakahar 	/* Set registers about MSI-X */
   5544  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   5545  1.335   msaitoh 		uint32_t ivar;
   5546  1.405  knakahar 		struct wm_queue *wmq;
   5547  1.405  knakahar 		int qid, qintr_idx;
   5548  1.335   msaitoh 
   5549  1.335   msaitoh 		if (sc->sc_type == WM_T_82575) {
   5550  1.335   msaitoh 			/* Interrupt control */
   5551  1.335   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5552  1.335   msaitoh 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;
   5553  1.335   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   5554  1.335   msaitoh 
   5555  1.405  knakahar 			/* TX and RX */
   5556  1.405  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5557  1.405  knakahar 				wmq = &sc->sc_queue[i];
   5558  1.405  knakahar 				CSR_WRITE(sc, WMREG_MSIXBM(wmq->wmq_intr_idx),
   5559  1.405  knakahar 				    EITR_TX_QUEUE(wmq->wmq_id)
   5560  1.405  knakahar 				    | EITR_RX_QUEUE(wmq->wmq_id));
   5561  1.364  knakahar 			}
   5562  1.335   msaitoh 			/* Link status */
   5563  1.364  knakahar 			CSR_WRITE(sc, WMREG_MSIXBM(sc->sc_link_intr_idx),
   5564  1.335   msaitoh 			    EITR_OTHER);
   5565  1.335   msaitoh 		} else if (sc->sc_type == WM_T_82574) {
   5566  1.335   msaitoh 			/* Interrupt control */
   5567  1.335   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5568  1.335   msaitoh 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;
   5569  1.335   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   5570  1.335   msaitoh 
   5571  1.487  knakahar 			/*
   5572  1.487  knakahar 			 * workaround issue with spurious interrupts
   5573  1.487  knakahar 			 * in MSI-X mode.
   5574  1.487  knakahar 			 * At wm_initialize_hardware_bits(), sc_nintrs has not
   5575  1.487  knakahar 			 * initialized yet. So re-initialize WMREG_RFCTL here.
   5576  1.487  knakahar 			 */
   5577  1.487  knakahar 			reg = CSR_READ(sc, WMREG_RFCTL);
   5578  1.487  knakahar 			reg |= WMREG_RFCTL_ACKDIS;
   5579  1.487  knakahar 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   5580  1.487  knakahar 
   5581  1.364  knakahar 			ivar = 0;
   5582  1.405  knakahar 			/* TX and RX */
   5583  1.405  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5584  1.405  knakahar 				wmq = &sc->sc_queue[i];
   5585  1.405  knakahar 				qid = wmq->wmq_id;
   5586  1.405  knakahar 				qintr_idx = wmq->wmq_intr_idx;
   5587  1.405  knakahar 
   5588  1.405  knakahar 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
   5589  1.405  knakahar 				    IVAR_TX_MASK_Q_82574(qid));
   5590  1.405  knakahar 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
   5591  1.405  knakahar 				    IVAR_RX_MASK_Q_82574(qid));
   5592  1.364  knakahar 			}
   5593  1.364  knakahar 			/* Link status */
   5594  1.388   msaitoh 			ivar |= __SHIFTIN((IVAR_VALID_82574
   5595  1.388   msaitoh 				| sc->sc_link_intr_idx), IVAR_OTHER_MASK);
   5596  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
   5597  1.335   msaitoh 		} else {
   5598  1.335   msaitoh 			/* Interrupt control */
   5599  1.388   msaitoh 			CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | GPIE_MULTI_MSIX
   5600  1.388   msaitoh 			    | GPIE_EIAME | GPIE_PBA);
   5601  1.335   msaitoh 
   5602  1.335   msaitoh 			switch (sc->sc_type) {
   5603  1.335   msaitoh 			case WM_T_82580:
   5604  1.335   msaitoh 			case WM_T_I350:
   5605  1.335   msaitoh 			case WM_T_I354:
   5606  1.335   msaitoh 			case WM_T_I210:
   5607  1.335   msaitoh 			case WM_T_I211:
   5608  1.405  knakahar 				/* TX and RX */
   5609  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5610  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5611  1.405  knakahar 					qid = wmq->wmq_id;
   5612  1.405  knakahar 					qintr_idx = wmq->wmq_intr_idx;
   5613  1.405  knakahar 
   5614  1.364  knakahar 					ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
   5615  1.364  knakahar 					ivar &= ~IVAR_TX_MASK_Q(qid);
   5616  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5617  1.388   msaitoh 						| IVAR_VALID),
   5618  1.388   msaitoh 					    IVAR_TX_MASK_Q(qid));
   5619  1.364  knakahar 					ivar &= ~IVAR_RX_MASK_Q(qid);
   5620  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5621  1.388   msaitoh 						| IVAR_VALID),
   5622  1.388   msaitoh 					    IVAR_RX_MASK_Q(qid));
   5623  1.364  knakahar 					CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
   5624  1.364  knakahar 				}
   5625  1.335   msaitoh 				break;
   5626  1.335   msaitoh 			case WM_T_82576:
   5627  1.405  knakahar 				/* TX and RX */
   5628  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5629  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5630  1.405  knakahar 					qid = wmq->wmq_id;
   5631  1.405  knakahar 					qintr_idx = wmq->wmq_intr_idx;
   5632  1.405  knakahar 
   5633  1.388   msaitoh 					ivar = CSR_READ(sc,
   5634  1.388   msaitoh 					    WMREG_IVAR_Q_82576(qid));
   5635  1.364  knakahar 					ivar &= ~IVAR_TX_MASK_Q_82576(qid);
   5636  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5637  1.388   msaitoh 						| IVAR_VALID),
   5638  1.388   msaitoh 					    IVAR_TX_MASK_Q_82576(qid));
   5639  1.364  knakahar 					ivar &= ~IVAR_RX_MASK_Q_82576(qid);
   5640  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5641  1.388   msaitoh 						| IVAR_VALID),
   5642  1.388   msaitoh 					    IVAR_RX_MASK_Q_82576(qid));
   5643  1.388   msaitoh 					CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid),
   5644  1.388   msaitoh 					    ivar);
   5645  1.364  knakahar 				}
   5646  1.335   msaitoh 				break;
   5647  1.335   msaitoh 			default:
   5648  1.335   msaitoh 				break;
   5649  1.335   msaitoh 			}
   5650  1.335   msaitoh 
   5651  1.335   msaitoh 			/* Link status */
   5652  1.364  knakahar 			ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID),
   5653  1.335   msaitoh 			    IVAR_MISC_OTHER);
   5654  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IVAR_MISC, ivar);
   5655  1.335   msaitoh 		}
   5656  1.365  knakahar 
   5657  1.502  knakahar 		if (wm_is_using_multiqueue(sc)) {
   5658  1.365  knakahar 			wm_init_rss(sc);
   5659  1.365  knakahar 
   5660  1.365  knakahar 			/*
   5661  1.365  knakahar 			** NOTE: Receive Full-Packet Checksum Offload
   5662  1.365  knakahar 			** is mutually exclusive with Multiqueue. However
   5663  1.365  knakahar 			** this is not the same as TCP/IP checksums which
   5664  1.365  knakahar 			** still work.
   5665  1.365  knakahar 			*/
   5666  1.365  knakahar 			reg = CSR_READ(sc, WMREG_RXCSUM);
   5667  1.365  knakahar 			reg |= RXCSUM_PCSD;
   5668  1.365  knakahar 			CSR_WRITE(sc, WMREG_RXCSUM, reg);
   5669  1.365  knakahar 		}
   5670  1.335   msaitoh 	}
   5671  1.335   msaitoh 
   5672  1.281   msaitoh 	/* Set up the interrupt registers. */
   5673  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   5674  1.281   msaitoh 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
   5675  1.281   msaitoh 	    ICR_RXO | ICR_RXT0;
   5676  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   5677  1.335   msaitoh 		uint32_t mask;
   5678  1.405  knakahar 		struct wm_queue *wmq;
   5679  1.388   msaitoh 
   5680  1.335   msaitoh 		switch (sc->sc_type) {
   5681  1.335   msaitoh 		case WM_T_82574:
   5682  1.486  knakahar 			mask = 0;
   5683  1.486  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5684  1.486  knakahar 				wmq = &sc->sc_queue[i];
   5685  1.486  knakahar 				mask |= ICR_TXQ(wmq->wmq_id);
   5686  1.486  knakahar 				mask |= ICR_RXQ(wmq->wmq_id);
   5687  1.486  knakahar 			}
   5688  1.486  knakahar 			mask |= ICR_OTHER;
   5689  1.486  knakahar 			CSR_WRITE(sc, WMREG_EIAC_82574, mask);
   5690  1.486  knakahar 			CSR_WRITE(sc, WMREG_IMS, mask | ICR_LSC);
   5691  1.335   msaitoh 			break;
   5692  1.335   msaitoh 		default:
   5693  1.364  knakahar 			if (sc->sc_type == WM_T_82575) {
   5694  1.364  knakahar 				mask = 0;
   5695  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5696  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5697  1.405  knakahar 					mask |= EITR_TX_QUEUE(wmq->wmq_id);
   5698  1.405  knakahar 					mask |= EITR_RX_QUEUE(wmq->wmq_id);
   5699  1.364  knakahar 				}
   5700  1.364  knakahar 				mask |= EITR_OTHER;
   5701  1.364  knakahar 			} else {
   5702  1.364  knakahar 				mask = 0;
   5703  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5704  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5705  1.405  knakahar 					mask |= 1 << wmq->wmq_intr_idx;
   5706  1.364  knakahar 				}
   5707  1.364  knakahar 				mask |= 1 << sc->sc_link_intr_idx;
   5708  1.364  knakahar 			}
   5709  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, mask);
   5710  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAM, mask);
   5711  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMS, mask);
   5712  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
   5713  1.335   msaitoh 			break;
   5714  1.335   msaitoh 		}
   5715  1.335   msaitoh 	} else
   5716  1.335   msaitoh 		CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
   5717  1.232    bouyer 
   5718  1.281   msaitoh 	/* Set up the inter-packet gap. */
   5719  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   5720  1.232    bouyer 
   5721  1.281   msaitoh 	if (sc->sc_type >= WM_T_82543) {
   5722  1.491  knakahar 		for (int qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5723  1.491  knakahar 			struct wm_queue *wmq = &sc->sc_queue[qidx];
   5724  1.491  knakahar 			wm_itrs_writereg(sc, wmq);
   5725  1.491  knakahar 		}
   5726  1.491  knakahar 		/*
   5727  1.491  knakahar 		 * Link interrupts occur much less than TX
   5728  1.491  knakahar 		 * interrupts and RX interrupts. So, we don't
   5729  1.491  knakahar 		 * tune EINTR(WM_MSIX_LINKINTR_IDX) value like
   5730  1.491  knakahar 		 * FreeBSD's if_igb.
   5731  1.491  knakahar 		 */
   5732  1.281   msaitoh 	}
   5733  1.232    bouyer 
   5734  1.281   msaitoh 	/* Set the VLAN ethernetype. */
   5735  1.281   msaitoh 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
   5736  1.232    bouyer 
   5737  1.281   msaitoh 	/*
   5738  1.281   msaitoh 	 * Set up the transmit control register; we start out with
   5739  1.281   msaitoh 	 * a collision distance suitable for FDX, but update it whe
   5740  1.281   msaitoh 	 * we resolve the media type.
   5741  1.281   msaitoh 	 */
   5742  1.281   msaitoh 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
   5743  1.281   msaitoh 	    | TCTL_CT(TX_COLLISION_THRESHOLD)
   5744  1.281   msaitoh 	    | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   5745  1.281   msaitoh 	if (sc->sc_type >= WM_T_82571)
   5746  1.281   msaitoh 		sc->sc_tctl |= TCTL_MULR;
   5747  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   5748  1.232    bouyer 
   5749  1.281   msaitoh 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   5750  1.281   msaitoh 		/* Write TDT after TCTL.EN is set. See the document. */
   5751  1.361  knakahar 		CSR_WRITE(sc, WMREG_TDT(0), 0);
   5752  1.232    bouyer 	}
   5753  1.232    bouyer 
   5754  1.281   msaitoh 	if (sc->sc_type == WM_T_80003) {
   5755  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_TCTL_EXT);
   5756  1.281   msaitoh 		reg &= ~TCTL_EXT_GCEX_MASK;
   5757  1.281   msaitoh 		reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
   5758  1.281   msaitoh 		CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
   5759  1.272     ozaki 	}
   5760  1.272     ozaki 
   5761  1.281   msaitoh 	/* Set the media. */
   5762  1.281   msaitoh 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
   5763  1.281   msaitoh 		goto out;
   5764  1.281   msaitoh 
   5765  1.281   msaitoh 	/* Configure for OS presence */
   5766  1.281   msaitoh 	wm_init_manageability(sc);
   5767  1.232    bouyer 
   5768  1.281   msaitoh 	/*
   5769  1.281   msaitoh 	 * Set up the receive control register; we actually program
   5770  1.281   msaitoh 	 * the register when we set the receive filter.  Use multicast
   5771  1.281   msaitoh 	 * address offset type 0.
   5772  1.281   msaitoh 	 *
   5773  1.281   msaitoh 	 * Only the i82544 has the ability to strip the incoming
   5774  1.281   msaitoh 	 * CRC, so we don't enable that feature.
   5775  1.281   msaitoh 	 */
   5776  1.281   msaitoh 	sc->sc_mchash_type = 0;
   5777  1.281   msaitoh 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
   5778  1.281   msaitoh 	    | RCTL_MO(sc->sc_mchash_type);
   5779  1.281   msaitoh 
   5780  1.281   msaitoh 	/*
   5781  1.466  knakahar 	 * 82574 use one buffer extended Rx descriptor.
   5782  1.466  knakahar 	 */
   5783  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   5784  1.466  knakahar 		sc->sc_rctl |= RCTL_DTYP_ONEBUF;
   5785  1.466  knakahar 
   5786  1.466  knakahar 	/*
   5787  1.281   msaitoh 	 * The I350 has a bug where it always strips the CRC whether
   5788  1.281   msaitoh 	 * asked to or not. So ask for stripped CRC here and cope in rxeof
   5789  1.281   msaitoh 	 */
   5790  1.281   msaitoh 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   5791  1.281   msaitoh 	    || (sc->sc_type == WM_T_I210))
   5792  1.281   msaitoh 		sc->sc_rctl |= RCTL_SECRC;
   5793  1.281   msaitoh 
   5794  1.281   msaitoh 	if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
   5795  1.281   msaitoh 	    && (ifp->if_mtu > ETHERMTU)) {
   5796  1.281   msaitoh 		sc->sc_rctl |= RCTL_LPE;
   5797  1.281   msaitoh 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   5798  1.281   msaitoh 			CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
   5799  1.281   msaitoh 	}
   5800  1.281   msaitoh 
   5801  1.281   msaitoh 	if (MCLBYTES == 2048) {
   5802  1.281   msaitoh 		sc->sc_rctl |= RCTL_2k;
   5803  1.281   msaitoh 	} else {
   5804  1.281   msaitoh 		if (sc->sc_type >= WM_T_82543) {
   5805  1.281   msaitoh 			switch (MCLBYTES) {
   5806  1.281   msaitoh 			case 4096:
   5807  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
   5808  1.281   msaitoh 				break;
   5809  1.281   msaitoh 			case 8192:
   5810  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
   5811  1.281   msaitoh 				break;
   5812  1.281   msaitoh 			case 16384:
   5813  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
   5814  1.281   msaitoh 				break;
   5815  1.281   msaitoh 			default:
   5816  1.281   msaitoh 				panic("wm_init: MCLBYTES %d unsupported",
   5817  1.281   msaitoh 				    MCLBYTES);
   5818  1.281   msaitoh 				break;
   5819  1.281   msaitoh 			}
   5820  1.281   msaitoh 		} else panic("wm_init: i82542 requires MCLBYTES = 2048");
   5821  1.281   msaitoh 	}
   5822  1.281   msaitoh 
   5823  1.281   msaitoh 	/* Enable ECC */
   5824  1.281   msaitoh 	switch (sc->sc_type) {
   5825  1.281   msaitoh 	case WM_T_82571:
   5826  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PBA_ECC);
   5827  1.281   msaitoh 		reg |= PBA_ECC_CORR_EN;
   5828  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBA_ECC, reg);
   5829  1.281   msaitoh 		break;
   5830  1.281   msaitoh 	case WM_T_PCH_LPT:
   5831  1.392   msaitoh 	case WM_T_PCH_SPT:
   5832  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PBECCSTS);
   5833  1.281   msaitoh 		reg |= PBECCSTS_UNCORR_ECC_ENABLE;
   5834  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBECCSTS, reg);
   5835  1.281   msaitoh 
   5836  1.444   msaitoh 		sc->sc_ctrl |= CTRL_MEHE;
   5837  1.444   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   5838  1.281   msaitoh 		break;
   5839  1.281   msaitoh 	default:
   5840  1.281   msaitoh 		break;
   5841  1.232    bouyer 	}
   5842  1.281   msaitoh 
   5843  1.548   msaitoh 	/*
   5844  1.548   msaitoh 	 * Set the receive filter.
   5845  1.548   msaitoh 	 *
   5846  1.548   msaitoh 	 * For 82575 and 82576, the RX descriptors must be initialized after
   5847  1.548   msaitoh 	 * the setting of RCTL.EN in wm_set_filter()
   5848  1.548   msaitoh 	 */
   5849  1.548   msaitoh 	wm_set_filter(sc);
   5850  1.548   msaitoh 
   5851  1.281   msaitoh 	/* On 575 and later set RDT only if RX enabled */
   5852  1.362  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   5853  1.364  knakahar 		int qidx;
   5854  1.405  knakahar 		for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5855  1.405  knakahar 			struct wm_rxqueue *rxq = &sc->sc_queue[qidx].wmq_rxq;
   5856  1.364  knakahar 			for (i = 0; i < WM_NRXDESC; i++) {
   5857  1.413     skrll 				mutex_enter(rxq->rxq_lock);
   5858  1.364  knakahar 				wm_init_rxdesc(rxq, i);
   5859  1.413     skrll 				mutex_exit(rxq->rxq_lock);
   5860  1.364  knakahar 
   5861  1.364  knakahar 			}
   5862  1.364  knakahar 		}
   5863  1.362  knakahar 	}
   5864  1.281   msaitoh 
   5865  1.537  knakahar 	wm_unset_stopping_flags(sc);
   5866  1.281   msaitoh 
   5867  1.281   msaitoh 	/* Start the one second link check clock. */
   5868  1.281   msaitoh 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   5869  1.281   msaitoh 
   5870  1.281   msaitoh 	/* ...all done! */
   5871  1.281   msaitoh 	ifp->if_flags |= IFF_RUNNING;
   5872  1.281   msaitoh 	ifp->if_flags &= ~IFF_OACTIVE;
   5873  1.281   msaitoh 
   5874  1.281   msaitoh  out:
   5875  1.281   msaitoh 	sc->sc_if_flags = ifp->if_flags;
   5876  1.281   msaitoh 	if (error)
   5877  1.281   msaitoh 		log(LOG_ERR, "%s: interface not running\n",
   5878  1.281   msaitoh 		    device_xname(sc->sc_dev));
   5879  1.281   msaitoh 	return error;
   5880  1.232    bouyer }
   5881  1.232    bouyer 
   5882  1.232    bouyer /*
   5883  1.281   msaitoh  * wm_stop:		[ifnet interface function]
   5884    1.1   thorpej  *
   5885  1.281   msaitoh  *	Stop transmission on the interface.
   5886    1.1   thorpej  */
   5887   1.47   thorpej static void
   5888  1.281   msaitoh wm_stop(struct ifnet *ifp, int disable)
   5889    1.1   thorpej {
   5890    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   5891    1.1   thorpej 
   5892  1.357  knakahar 	WM_CORE_LOCK(sc);
   5893  1.281   msaitoh 	wm_stop_locked(ifp, disable);
   5894  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   5895    1.1   thorpej }
   5896    1.1   thorpej 
   5897  1.281   msaitoh static void
   5898  1.281   msaitoh wm_stop_locked(struct ifnet *ifp, int disable)
   5899  1.213   msaitoh {
   5900  1.213   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   5901  1.281   msaitoh 	struct wm_txsoft *txs;
   5902  1.364  knakahar 	int i, qidx;
   5903  1.281   msaitoh 
   5904  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   5905  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   5906  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5907  1.281   msaitoh 
   5908  1.537  knakahar 	wm_set_stopping_flags(sc);
   5909  1.272     ozaki 
   5910  1.281   msaitoh 	/* Stop the one second clock. */
   5911  1.281   msaitoh 	callout_stop(&sc->sc_tick_ch);
   5912  1.213   msaitoh 
   5913  1.281   msaitoh 	/* Stop the 82547 Tx FIFO stall check timer. */
   5914  1.281   msaitoh 	if (sc->sc_type == WM_T_82547)
   5915  1.281   msaitoh 		callout_stop(&sc->sc_txfifo_ch);
   5916  1.217    dyoung 
   5917  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII) {
   5918  1.281   msaitoh 		/* Down the MII. */
   5919  1.281   msaitoh 		mii_down(&sc->sc_mii);
   5920  1.281   msaitoh 	} else {
   5921  1.281   msaitoh #if 0
   5922  1.281   msaitoh 		/* Should we clear PHY's status properly? */
   5923  1.281   msaitoh 		wm_reset(sc);
   5924  1.281   msaitoh #endif
   5925  1.272     ozaki 	}
   5926  1.213   msaitoh 
   5927  1.281   msaitoh 	/* Stop the transmit and receive processes. */
   5928  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, 0);
   5929  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, 0);
   5930  1.281   msaitoh 	sc->sc_rctl &= ~RCTL_EN;
   5931  1.281   msaitoh 
   5932  1.281   msaitoh 	/*
   5933  1.281   msaitoh 	 * Clear the interrupt mask to ensure the device cannot assert its
   5934  1.281   msaitoh 	 * interrupt line.
   5935  1.335   msaitoh 	 * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to
   5936  1.335   msaitoh 	 * service any currently pending or shared interrupt.
   5937  1.281   msaitoh 	 */
   5938  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   5939  1.281   msaitoh 	sc->sc_icr = 0;
   5940  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   5941  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   5942  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   5943  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   5944  1.335   msaitoh 		} else
   5945  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   5946  1.335   msaitoh 	}
   5947  1.281   msaitoh 
   5948  1.281   msaitoh 	/* Release any queued transmit buffers. */
   5949  1.405  knakahar 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5950  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   5951  1.405  knakahar 		struct wm_txqueue *txq = &wmq->wmq_txq;
   5952  1.413     skrll 		mutex_enter(txq->txq_lock);
   5953  1.364  knakahar 		for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   5954  1.364  knakahar 			txs = &txq->txq_soft[i];
   5955  1.364  knakahar 			if (txs->txs_mbuf != NULL) {
   5956  1.388   msaitoh 				bus_dmamap_unload(sc->sc_dmat,txs->txs_dmamap);
   5957  1.364  knakahar 				m_freem(txs->txs_mbuf);
   5958  1.364  knakahar 				txs->txs_mbuf = NULL;
   5959  1.364  knakahar 			}
   5960  1.281   msaitoh 		}
   5961  1.413     skrll 		mutex_exit(txq->txq_lock);
   5962  1.281   msaitoh 	}
   5963  1.217    dyoung 
   5964  1.281   msaitoh 	/* Mark the interface as down and cancel the watchdog timer. */
   5965  1.281   msaitoh 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   5966  1.549     ozaki 	ifp->if_timer = 0;
   5967  1.213   msaitoh 
   5968  1.357  knakahar 	if (disable) {
   5969  1.405  knakahar 		for (i = 0; i < sc->sc_nqueues; i++) {
   5970  1.405  knakahar 			struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   5971  1.413     skrll 			mutex_enter(rxq->rxq_lock);
   5972  1.364  knakahar 			wm_rxdrain(rxq);
   5973  1.413     skrll 			mutex_exit(rxq->rxq_lock);
   5974  1.364  knakahar 		}
   5975  1.357  knakahar 	}
   5976  1.272     ozaki 
   5977  1.281   msaitoh #if 0 /* notyet */
   5978  1.281   msaitoh 	if (sc->sc_type >= WM_T_82544)
   5979  1.281   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   5980  1.281   msaitoh #endif
   5981  1.213   msaitoh }
   5982  1.213   msaitoh 
   5983   1.47   thorpej static void
   5984  1.281   msaitoh wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
   5985    1.1   thorpej {
   5986  1.281   msaitoh 	struct mbuf *m;
   5987    1.1   thorpej 	int i;
   5988    1.1   thorpej 
   5989  1.281   msaitoh 	log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev));
   5990  1.281   msaitoh 	for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
   5991  1.281   msaitoh 		log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
   5992  1.281   msaitoh 		    "m_flags = 0x%08x\n", device_xname(sc->sc_dev),
   5993  1.281   msaitoh 		    m->m_data, m->m_len, m->m_flags);
   5994  1.281   msaitoh 	log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev),
   5995  1.281   msaitoh 	    i, i == 1 ? "" : "s");
   5996  1.281   msaitoh }
   5997  1.272     ozaki 
   5998  1.281   msaitoh /*
   5999  1.281   msaitoh  * wm_82547_txfifo_stall:
   6000  1.281   msaitoh  *
   6001  1.281   msaitoh  *	Callout used to wait for the 82547 Tx FIFO to drain,
   6002  1.281   msaitoh  *	reset the FIFO pointers, and restart packet transmission.
   6003  1.281   msaitoh  */
   6004  1.281   msaitoh static void
   6005  1.281   msaitoh wm_82547_txfifo_stall(void *arg)
   6006  1.281   msaitoh {
   6007  1.281   msaitoh 	struct wm_softc *sc = arg;
   6008  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   6009    1.1   thorpej 
   6010  1.413     skrll 	mutex_enter(txq->txq_lock);
   6011    1.1   thorpej 
   6012  1.429  knakahar 	if (txq->txq_stopping)
   6013  1.281   msaitoh 		goto out;
   6014    1.1   thorpej 
   6015  1.356  knakahar 	if (txq->txq_fifo_stall) {
   6016  1.361  knakahar 		if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) &&
   6017  1.281   msaitoh 		    CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
   6018  1.281   msaitoh 		    CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
   6019  1.281   msaitoh 			/*
   6020  1.281   msaitoh 			 * Packets have drained.  Stop transmitter, reset
   6021  1.281   msaitoh 			 * FIFO pointers, restart transmitter, and kick
   6022  1.281   msaitoh 			 * the packet queue.
   6023  1.281   msaitoh 			 */
   6024  1.281   msaitoh 			uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
   6025  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
   6026  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr);
   6027  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr);
   6028  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr);
   6029  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr);
   6030  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, tctl);
   6031  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   6032    1.1   thorpej 
   6033  1.356  knakahar 			txq->txq_fifo_head = 0;
   6034  1.356  knakahar 			txq->txq_fifo_stall = 0;
   6035  1.281   msaitoh 			wm_start_locked(&sc->sc_ethercom.ec_if);
   6036  1.281   msaitoh 		} else {
   6037  1.281   msaitoh 			/*
   6038  1.281   msaitoh 			 * Still waiting for packets to drain; try again in
   6039  1.281   msaitoh 			 * another tick.
   6040  1.281   msaitoh 			 */
   6041  1.281   msaitoh 			callout_schedule(&sc->sc_txfifo_ch, 1);
   6042   1.20   thorpej 		}
   6043  1.281   msaitoh 	}
   6044    1.1   thorpej 
   6045  1.281   msaitoh out:
   6046  1.413     skrll 	mutex_exit(txq->txq_lock);
   6047  1.281   msaitoh }
   6048    1.1   thorpej 
   6049  1.281   msaitoh /*
   6050  1.281   msaitoh  * wm_82547_txfifo_bugchk:
   6051  1.281   msaitoh  *
   6052  1.281   msaitoh  *	Check for bug condition in the 82547 Tx FIFO.  We need to
   6053  1.281   msaitoh  *	prevent enqueueing a packet that would wrap around the end
   6054  1.281   msaitoh  *	if the Tx FIFO ring buffer, otherwise the chip will croak.
   6055  1.281   msaitoh  *
   6056  1.281   msaitoh  *	We do this by checking the amount of space before the end
   6057  1.281   msaitoh  *	of the Tx FIFO buffer.  If the packet will not fit, we "stall"
   6058  1.281   msaitoh  *	the Tx FIFO, wait for all remaining packets to drain, reset
   6059  1.281   msaitoh  *	the internal FIFO pointers to the beginning, and restart
   6060  1.281   msaitoh  *	transmission on the interface.
   6061  1.281   msaitoh  */
   6062  1.281   msaitoh #define	WM_FIFO_HDR		0x10
   6063  1.281   msaitoh #define	WM_82547_PAD_LEN	0x3e0
   6064  1.281   msaitoh static int
   6065  1.281   msaitoh wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
   6066  1.281   msaitoh {
   6067  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   6068  1.356  knakahar 	int space = txq->txq_fifo_size - txq->txq_fifo_head;
   6069  1.281   msaitoh 	int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
   6070    1.1   thorpej 
   6071  1.281   msaitoh 	/* Just return if already stalled. */
   6072  1.356  knakahar 	if (txq->txq_fifo_stall)
   6073  1.281   msaitoh 		return 1;
   6074    1.1   thorpej 
   6075  1.281   msaitoh 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   6076  1.281   msaitoh 		/* Stall only occurs in half-duplex mode. */
   6077  1.281   msaitoh 		goto send_packet;
   6078  1.281   msaitoh 	}
   6079    1.1   thorpej 
   6080  1.281   msaitoh 	if (len >= WM_82547_PAD_LEN + space) {
   6081  1.356  knakahar 		txq->txq_fifo_stall = 1;
   6082  1.281   msaitoh 		callout_schedule(&sc->sc_txfifo_ch, 1);
   6083  1.281   msaitoh 		return 1;
   6084    1.1   thorpej 	}
   6085    1.1   thorpej 
   6086  1.281   msaitoh  send_packet:
   6087  1.356  knakahar 	txq->txq_fifo_head += len;
   6088  1.356  knakahar 	if (txq->txq_fifo_head >= txq->txq_fifo_size)
   6089  1.356  knakahar 		txq->txq_fifo_head -= txq->txq_fifo_size;
   6090    1.1   thorpej 
   6091  1.281   msaitoh 	return 0;
   6092    1.1   thorpej }
   6093    1.1   thorpej 
   6094  1.353  knakahar static int
   6095  1.362  knakahar wm_alloc_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
   6096  1.354  knakahar {
   6097  1.354  knakahar 	int error;
   6098  1.354  knakahar 
   6099  1.354  knakahar 	/*
   6100  1.354  knakahar 	 * Allocate the control data structures, and create and load the
   6101  1.354  knakahar 	 * DMA map for it.
   6102  1.354  knakahar 	 *
   6103  1.354  knakahar 	 * NOTE: All Tx descriptors must be in the same 4G segment of
   6104  1.354  knakahar 	 * memory.  So must Rx descriptors.  We simplify by allocating
   6105  1.354  knakahar 	 * both sets within the same 4G segment.
   6106  1.354  knakahar 	 */
   6107  1.399  knakahar 	if (sc->sc_type < WM_T_82544)
   6108  1.356  knakahar 		WM_NTXDESC(txq) = WM_NTXDESC_82542;
   6109  1.399  knakahar 	else
   6110  1.356  knakahar 		WM_NTXDESC(txq) = WM_NTXDESC_82544;
   6111  1.398  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   6112  1.398  knakahar 		txq->txq_descsize = sizeof(nq_txdesc_t);
   6113  1.398  knakahar 	else
   6114  1.398  knakahar 		txq->txq_descsize = sizeof(wiseman_txdesc_t);
   6115  1.354  knakahar 
   6116  1.399  knakahar 	if ((error = bus_dmamem_alloc(sc->sc_dmat, WM_TXDESCS_SIZE(txq),
   6117  1.388   msaitoh 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg,
   6118  1.388   msaitoh 		    1, &txq->txq_desc_rseg, 0)) != 0) {
   6119  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   6120  1.354  knakahar 		    "unable to allocate TX control data, error = %d\n",
   6121  1.354  knakahar 		    error);
   6122  1.354  knakahar 		goto fail_0;
   6123  1.354  knakahar 	}
   6124  1.354  knakahar 
   6125  1.356  knakahar 	if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg,
   6126  1.399  knakahar 		    txq->txq_desc_rseg, WM_TXDESCS_SIZE(txq),
   6127  1.356  knakahar 		    (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) {
   6128  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   6129  1.354  knakahar 		    "unable to map TX control data, error = %d\n", error);
   6130  1.354  knakahar 		goto fail_1;
   6131  1.354  knakahar 	}
   6132  1.354  knakahar 
   6133  1.399  knakahar 	if ((error = bus_dmamap_create(sc->sc_dmat, WM_TXDESCS_SIZE(txq), 1,
   6134  1.399  knakahar 		    WM_TXDESCS_SIZE(txq), 0, 0, &txq->txq_desc_dmamap)) != 0) {
   6135  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   6136  1.354  knakahar 		    "unable to create TX control data DMA map, error = %d\n",
   6137  1.354  knakahar 		    error);
   6138  1.354  knakahar 		goto fail_2;
   6139  1.354  knakahar 	}
   6140  1.354  knakahar 
   6141  1.356  knakahar 	if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap,
   6142  1.399  knakahar 		    txq->txq_descs_u, WM_TXDESCS_SIZE(txq), NULL, 0)) != 0) {
   6143  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   6144  1.354  knakahar 		    "unable to load TX control data DMA map, error = %d\n",
   6145  1.354  knakahar 		    error);
   6146  1.354  knakahar 		goto fail_3;
   6147  1.354  knakahar 	}
   6148  1.354  knakahar 
   6149  1.354  knakahar 	return 0;
   6150  1.354  knakahar 
   6151  1.354  knakahar  fail_3:
   6152  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
   6153  1.354  knakahar  fail_2:
   6154  1.356  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
   6155  1.399  knakahar 	    WM_TXDESCS_SIZE(txq));
   6156  1.354  knakahar  fail_1:
   6157  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
   6158  1.354  knakahar  fail_0:
   6159  1.354  knakahar 	return error;
   6160  1.354  knakahar }
   6161  1.354  knakahar 
   6162  1.354  knakahar static void
   6163  1.362  knakahar wm_free_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
   6164  1.354  knakahar {
   6165  1.354  knakahar 
   6166  1.356  knakahar 	bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap);
   6167  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
   6168  1.356  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
   6169  1.399  knakahar 	    WM_TXDESCS_SIZE(txq));
   6170  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
   6171  1.354  knakahar }
   6172  1.354  knakahar 
   6173  1.354  knakahar static int
   6174  1.362  knakahar wm_alloc_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6175  1.353  knakahar {
   6176  1.353  knakahar 	int error;
   6177  1.466  knakahar 	size_t rxq_descs_size;
   6178  1.353  knakahar 
   6179  1.353  knakahar 	/*
   6180  1.353  knakahar 	 * Allocate the control data structures, and create and load the
   6181  1.353  knakahar 	 * DMA map for it.
   6182  1.353  knakahar 	 *
   6183  1.353  knakahar 	 * NOTE: All Tx descriptors must be in the same 4G segment of
   6184  1.353  knakahar 	 * memory.  So must Rx descriptors.  We simplify by allocating
   6185  1.353  knakahar 	 * both sets within the same 4G segment.
   6186  1.353  knakahar 	 */
   6187  1.466  knakahar 	rxq->rxq_ndesc = WM_NRXDESC;
   6188  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   6189  1.466  knakahar 		rxq->rxq_descsize = sizeof(ext_rxdesc_t);
   6190  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   6191  1.466  knakahar 		rxq->rxq_descsize = sizeof(nq_rxdesc_t);
   6192  1.466  knakahar 	else
   6193  1.466  knakahar 		rxq->rxq_descsize = sizeof(wiseman_rxdesc_t);
   6194  1.466  knakahar 	rxq_descs_size = rxq->rxq_descsize * rxq->rxq_ndesc;
   6195  1.466  knakahar 
   6196  1.466  knakahar 	if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq_descs_size,
   6197  1.388   msaitoh 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &rxq->rxq_desc_seg,
   6198  1.388   msaitoh 		    1, &rxq->rxq_desc_rseg, 0)) != 0) {
   6199  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   6200  1.354  knakahar 		    "unable to allocate RX control data, error = %d\n",
   6201  1.353  knakahar 		    error);
   6202  1.353  knakahar 		goto fail_0;
   6203  1.353  knakahar 	}
   6204  1.353  knakahar 
   6205  1.356  knakahar 	if ((error = bus_dmamem_map(sc->sc_dmat, &rxq->rxq_desc_seg,
   6206  1.466  knakahar 		    rxq->rxq_desc_rseg, rxq_descs_size,
   6207  1.466  knakahar 		    (void **)&rxq->rxq_descs_u, BUS_DMA_COHERENT)) != 0) {
   6208  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   6209  1.354  knakahar 		    "unable to map RX control data, error = %d\n", error);
   6210  1.353  knakahar 		goto fail_1;
   6211  1.353  knakahar 	}
   6212  1.353  knakahar 
   6213  1.466  knakahar 	if ((error = bus_dmamap_create(sc->sc_dmat, rxq_descs_size, 1,
   6214  1.466  knakahar 		    rxq_descs_size, 0, 0, &rxq->rxq_desc_dmamap)) != 0) {
   6215  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   6216  1.354  knakahar 		    "unable to create RX control data DMA map, error = %d\n",
   6217  1.353  knakahar 		    error);
   6218  1.353  knakahar 		goto fail_2;
   6219  1.353  knakahar 	}
   6220  1.353  knakahar 
   6221  1.356  knakahar 	if ((error = bus_dmamap_load(sc->sc_dmat, rxq->rxq_desc_dmamap,
   6222  1.466  knakahar 		    rxq->rxq_descs_u, rxq_descs_size, NULL, 0)) != 0) {
   6223  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   6224  1.354  knakahar 		    "unable to load RX control data DMA map, error = %d\n",
   6225  1.353  knakahar 		    error);
   6226  1.353  knakahar 		goto fail_3;
   6227  1.353  knakahar 	}
   6228  1.353  knakahar 
   6229  1.353  knakahar 	return 0;
   6230  1.353  knakahar 
   6231  1.353  knakahar  fail_3:
   6232  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
   6233  1.353  knakahar  fail_2:
   6234  1.466  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
   6235  1.466  knakahar 	    rxq_descs_size);
   6236  1.353  knakahar  fail_1:
   6237  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
   6238  1.353  knakahar  fail_0:
   6239  1.353  knakahar 	return error;
   6240  1.353  knakahar }
   6241  1.353  knakahar 
   6242  1.353  knakahar static void
   6243  1.362  knakahar wm_free_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6244  1.353  knakahar {
   6245  1.353  knakahar 
   6246  1.356  knakahar 	bus_dmamap_unload(sc->sc_dmat, rxq->rxq_desc_dmamap);
   6247  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
   6248  1.466  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
   6249  1.466  knakahar 	    rxq->rxq_descsize * rxq->rxq_ndesc);
   6250  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
   6251  1.353  knakahar }
   6252  1.353  knakahar 
   6253  1.354  knakahar 
   6254  1.353  knakahar static int
   6255  1.362  knakahar wm_alloc_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
   6256  1.353  knakahar {
   6257  1.353  knakahar 	int i, error;
   6258  1.353  knakahar 
   6259  1.353  knakahar 	/* Create the transmit buffer DMA maps. */
   6260  1.356  knakahar 	WM_TXQUEUELEN(txq) =
   6261  1.353  knakahar 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
   6262  1.353  knakahar 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
   6263  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6264  1.353  knakahar 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
   6265  1.353  knakahar 			    WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
   6266  1.356  knakahar 			    &txq->txq_soft[i].txs_dmamap)) != 0) {
   6267  1.353  knakahar 			aprint_error_dev(sc->sc_dev,
   6268  1.353  knakahar 			    "unable to create Tx DMA map %d, error = %d\n",
   6269  1.353  knakahar 			    i, error);
   6270  1.353  knakahar 			goto fail;
   6271  1.353  knakahar 		}
   6272  1.353  knakahar 	}
   6273  1.353  knakahar 
   6274  1.353  knakahar 	return 0;
   6275  1.353  knakahar 
   6276  1.353  knakahar  fail:
   6277  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6278  1.356  knakahar 		if (txq->txq_soft[i].txs_dmamap != NULL)
   6279  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6280  1.356  knakahar 			    txq->txq_soft[i].txs_dmamap);
   6281  1.353  knakahar 	}
   6282  1.353  knakahar 	return error;
   6283  1.353  knakahar }
   6284  1.353  knakahar 
   6285  1.353  knakahar static void
   6286  1.362  knakahar wm_free_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
   6287  1.353  knakahar {
   6288  1.353  knakahar 	int i;
   6289  1.353  knakahar 
   6290  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6291  1.356  knakahar 		if (txq->txq_soft[i].txs_dmamap != NULL)
   6292  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6293  1.356  knakahar 			    txq->txq_soft[i].txs_dmamap);
   6294  1.353  knakahar 	}
   6295  1.353  knakahar }
   6296  1.353  knakahar 
   6297  1.353  knakahar static int
   6298  1.362  knakahar wm_alloc_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6299  1.353  knakahar {
   6300  1.353  knakahar 	int i, error;
   6301  1.353  knakahar 
   6302  1.353  knakahar 	/* Create the receive buffer DMA maps. */
   6303  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6304  1.353  knakahar 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
   6305  1.353  knakahar 			    MCLBYTES, 0, 0,
   6306  1.356  knakahar 			    &rxq->rxq_soft[i].rxs_dmamap)) != 0) {
   6307  1.353  knakahar 			aprint_error_dev(sc->sc_dev,
   6308  1.353  knakahar 			    "unable to create Rx DMA map %d error = %d\n",
   6309  1.353  knakahar 			    i, error);
   6310  1.353  knakahar 			goto fail;
   6311  1.353  knakahar 		}
   6312  1.356  knakahar 		rxq->rxq_soft[i].rxs_mbuf = NULL;
   6313  1.353  knakahar 	}
   6314  1.353  knakahar 
   6315  1.353  knakahar 	return 0;
   6316  1.353  knakahar 
   6317  1.353  knakahar  fail:
   6318  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6319  1.356  knakahar 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
   6320  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6321  1.356  knakahar 			    rxq->rxq_soft[i].rxs_dmamap);
   6322  1.353  knakahar 	}
   6323  1.353  knakahar 	return error;
   6324  1.353  knakahar }
   6325  1.353  knakahar 
   6326  1.353  knakahar static void
   6327  1.362  knakahar wm_free_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6328  1.353  knakahar {
   6329  1.353  knakahar 	int i;
   6330  1.353  knakahar 
   6331  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6332  1.356  knakahar 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
   6333  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6334  1.356  knakahar 			    rxq->rxq_soft[i].rxs_dmamap);
   6335  1.353  knakahar 	}
   6336  1.353  knakahar }
   6337  1.353  knakahar 
   6338  1.353  knakahar /*
   6339  1.353  knakahar  * wm_alloc_quques:
   6340  1.353  knakahar  *	Allocate {tx,rx}descs and {tx,rx} buffers
   6341  1.353  knakahar  */
   6342  1.353  knakahar static int
   6343  1.353  knakahar wm_alloc_txrx_queues(struct wm_softc *sc)
   6344  1.353  knakahar {
   6345  1.364  knakahar 	int i, error, tx_done, rx_done;
   6346  1.353  knakahar 
   6347  1.405  knakahar 	sc->sc_queue = kmem_zalloc(sizeof(struct wm_queue) * sc->sc_nqueues,
   6348  1.356  knakahar 	    KM_SLEEP);
   6349  1.405  knakahar 	if (sc->sc_queue == NULL) {
   6350  1.405  knakahar 		aprint_error_dev(sc->sc_dev,"unable to allocate wm_queue\n");
   6351  1.356  knakahar 		error = ENOMEM;
   6352  1.356  knakahar 		goto fail_0;
   6353  1.356  knakahar 	}
   6354  1.364  knakahar 
   6355  1.405  knakahar 	/*
   6356  1.405  knakahar 	 * For transmission
   6357  1.405  knakahar 	 */
   6358  1.364  knakahar 	error = 0;
   6359  1.364  knakahar 	tx_done = 0;
   6360  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6361  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6362  1.417  knakahar 		int j;
   6363  1.417  knakahar 		const char *xname;
   6364  1.417  knakahar #endif
   6365  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6366  1.364  knakahar 		txq->txq_sc = sc;
   6367  1.362  knakahar 		txq->txq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   6368  1.408  knakahar 
   6369  1.362  knakahar 		error = wm_alloc_tx_descs(sc, txq);
   6370  1.364  knakahar 		if (error)
   6371  1.364  knakahar 			break;
   6372  1.364  knakahar 		error = wm_alloc_tx_buffer(sc, txq);
   6373  1.364  knakahar 		if (error) {
   6374  1.364  knakahar 			wm_free_tx_descs(sc, txq);
   6375  1.364  knakahar 			break;
   6376  1.364  knakahar 		}
   6377  1.403  knakahar 		txq->txq_interq = pcq_create(WM_TXINTERQSIZE, KM_SLEEP);
   6378  1.403  knakahar 		if (txq->txq_interq == NULL) {
   6379  1.403  knakahar 			wm_free_tx_descs(sc, txq);
   6380  1.403  knakahar 			wm_free_tx_buffer(sc, txq);
   6381  1.403  knakahar 			error = ENOMEM;
   6382  1.403  knakahar 			break;
   6383  1.403  knakahar 		}
   6384  1.417  knakahar 
   6385  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6386  1.417  knakahar 		xname = device_xname(sc->sc_dev);
   6387  1.417  knakahar 
   6388  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txsstall, txq, i, xname);
   6389  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txdstall, txq, i, xname);
   6390  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txfifo_stall, txq, i, xname);
   6391  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(txq, txdw, txq, i, xname);
   6392  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(txq, txqe, txq, i, xname);
   6393  1.417  knakahar 
   6394  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txipsum, txq, i, xname);
   6395  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtusum, txq, i, xname);
   6396  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtusum6, txq, i, xname);
   6397  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtso, txq, i, xname);
   6398  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtso6, txq, i, xname);
   6399  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtsopain, txq, i, xname);
   6400  1.417  knakahar 
   6401  1.417  knakahar 		for (j = 0; j < WM_NTXSEGS; j++) {
   6402  1.417  knakahar 			snprintf(txq->txq_txseg_evcnt_names[j],
   6403  1.417  knakahar 			    sizeof(txq->txq_txseg_evcnt_names[j]), "txq%02dtxseg%d", i, j);
   6404  1.417  knakahar 			evcnt_attach_dynamic(&txq->txq_ev_txseg[j], EVCNT_TYPE_MISC,
   6405  1.417  knakahar 			    NULL, xname, txq->txq_txseg_evcnt_names[j]);
   6406  1.417  knakahar 		}
   6407  1.417  knakahar 
   6408  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txdrop, txq, i, xname);
   6409  1.417  knakahar 
   6410  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, tu, txq, i, xname);
   6411  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
   6412  1.417  knakahar 
   6413  1.364  knakahar 		tx_done++;
   6414  1.364  knakahar 	}
   6415  1.353  knakahar 	if (error)
   6416  1.356  knakahar 		goto fail_1;
   6417  1.353  knakahar 
   6418  1.354  knakahar 	/*
   6419  1.354  knakahar 	 * For recieve
   6420  1.354  knakahar 	 */
   6421  1.364  knakahar 	error = 0;
   6422  1.364  knakahar 	rx_done = 0;
   6423  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6424  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6425  1.417  knakahar 		const char *xname;
   6426  1.417  knakahar #endif
   6427  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6428  1.364  knakahar 		rxq->rxq_sc = sc;
   6429  1.362  knakahar 		rxq->rxq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   6430  1.414  knakahar 
   6431  1.364  knakahar 		error = wm_alloc_rx_descs(sc, rxq);
   6432  1.364  knakahar 		if (error)
   6433  1.364  knakahar 			break;
   6434  1.356  knakahar 
   6435  1.364  knakahar 		error = wm_alloc_rx_buffer(sc, rxq);
   6436  1.364  knakahar 		if (error) {
   6437  1.364  knakahar 			wm_free_rx_descs(sc, rxq);
   6438  1.364  knakahar 			break;
   6439  1.364  knakahar 		}
   6440  1.354  knakahar 
   6441  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6442  1.417  knakahar 		xname = device_xname(sc->sc_dev);
   6443  1.417  knakahar 
   6444  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxintr, rxq, i, xname);
   6445  1.417  knakahar 
   6446  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxipsum, rxq, i, xname);
   6447  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxtusum, rxq, i, xname);
   6448  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
   6449  1.417  knakahar 
   6450  1.364  knakahar 		rx_done++;
   6451  1.364  knakahar 	}
   6452  1.353  knakahar 	if (error)
   6453  1.364  knakahar 		goto fail_2;
   6454  1.353  knakahar 
   6455  1.353  knakahar 	return 0;
   6456  1.353  knakahar 
   6457  1.356  knakahar  fail_2:
   6458  1.364  knakahar 	for (i = 0; i < rx_done; i++) {
   6459  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6460  1.364  knakahar 		wm_free_rx_buffer(sc, rxq);
   6461  1.364  knakahar 		wm_free_rx_descs(sc, rxq);
   6462  1.364  knakahar 		if (rxq->rxq_lock)
   6463  1.364  knakahar 			mutex_obj_free(rxq->rxq_lock);
   6464  1.364  knakahar 	}
   6465  1.356  knakahar  fail_1:
   6466  1.364  knakahar 	for (i = 0; i < tx_done; i++) {
   6467  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6468  1.403  knakahar 		pcq_destroy(txq->txq_interq);
   6469  1.364  knakahar 		wm_free_tx_buffer(sc, txq);
   6470  1.364  knakahar 		wm_free_tx_descs(sc, txq);
   6471  1.364  knakahar 		if (txq->txq_lock)
   6472  1.364  knakahar 			mutex_obj_free(txq->txq_lock);
   6473  1.364  knakahar 	}
   6474  1.405  knakahar 
   6475  1.405  knakahar 	kmem_free(sc->sc_queue,
   6476  1.405  knakahar 	    sizeof(struct wm_queue) * sc->sc_nqueues);
   6477  1.356  knakahar  fail_0:
   6478  1.353  knakahar 	return error;
   6479  1.353  knakahar }
   6480  1.353  knakahar 
   6481  1.353  knakahar /*
   6482  1.353  knakahar  * wm_free_quques:
   6483  1.353  knakahar  *	Free {tx,rx}descs and {tx,rx} buffers
   6484  1.353  knakahar  */
   6485  1.353  knakahar static void
   6486  1.353  knakahar wm_free_txrx_queues(struct wm_softc *sc)
   6487  1.353  knakahar {
   6488  1.364  knakahar 	int i;
   6489  1.362  knakahar 
   6490  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6491  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6492  1.477  knakahar 
   6493  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   6494  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxintr, rxq, i);
   6495  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxipsum, rxq, i);
   6496  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxtusum, rxq, i);
   6497  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   6498  1.477  knakahar 
   6499  1.364  knakahar 		wm_free_rx_buffer(sc, rxq);
   6500  1.364  knakahar 		wm_free_rx_descs(sc, rxq);
   6501  1.364  knakahar 		if (rxq->rxq_lock)
   6502  1.364  knakahar 			mutex_obj_free(rxq->rxq_lock);
   6503  1.364  knakahar 	}
   6504  1.364  knakahar 
   6505  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6506  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6507  1.469  knakahar 		struct mbuf *m;
   6508  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   6509  1.477  knakahar 		int j;
   6510  1.477  knakahar 
   6511  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txsstall, txq, i);
   6512  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdstall, txq, i);
   6513  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txfifo_stall, txq, i);
   6514  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdw, txq, i);
   6515  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txqe, txq, i);
   6516  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txipsum, txq, i);
   6517  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtusum, txq, i);
   6518  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtusum6, txq, i);
   6519  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtso, txq, i);
   6520  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtso6, txq, i);
   6521  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtsopain, txq, i);
   6522  1.477  knakahar 
   6523  1.477  knakahar 		for (j = 0; j < WM_NTXSEGS; j++)
   6524  1.477  knakahar 			evcnt_detach(&txq->txq_ev_txseg[j]);
   6525  1.477  knakahar 
   6526  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdrop, txq, i);
   6527  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, tu, txq, i);
   6528  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   6529  1.469  knakahar 
   6530  1.469  knakahar 		/* drain txq_interq */
   6531  1.469  knakahar 		while ((m = pcq_get(txq->txq_interq)) != NULL)
   6532  1.469  knakahar 			m_freem(m);
   6533  1.469  knakahar 		pcq_destroy(txq->txq_interq);
   6534  1.469  knakahar 
   6535  1.364  knakahar 		wm_free_tx_buffer(sc, txq);
   6536  1.364  knakahar 		wm_free_tx_descs(sc, txq);
   6537  1.364  knakahar 		if (txq->txq_lock)
   6538  1.364  knakahar 			mutex_obj_free(txq->txq_lock);
   6539  1.364  knakahar 	}
   6540  1.405  knakahar 
   6541  1.405  knakahar 	kmem_free(sc->sc_queue, sizeof(struct wm_queue) * sc->sc_nqueues);
   6542  1.353  knakahar }
   6543  1.353  knakahar 
   6544  1.355  knakahar static void
   6545  1.362  knakahar wm_init_tx_descs(struct wm_softc *sc __unused, struct wm_txqueue *txq)
   6546  1.355  knakahar {
   6547  1.355  knakahar 
   6548  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6549  1.355  knakahar 
   6550  1.355  knakahar 	/* Initialize the transmit descriptor ring. */
   6551  1.398  knakahar 	memset(txq->txq_descs, 0, WM_TXDESCS_SIZE(txq));
   6552  1.362  knakahar 	wm_cdtxsync(txq, 0, WM_NTXDESC(txq),
   6553  1.388   msaitoh 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   6554  1.356  knakahar 	txq->txq_free = WM_NTXDESC(txq);
   6555  1.356  knakahar 	txq->txq_next = 0;
   6556  1.358  knakahar }
   6557  1.358  knakahar 
   6558  1.358  knakahar static void
   6559  1.405  knakahar wm_init_tx_regs(struct wm_softc *sc, struct wm_queue *wmq,
   6560  1.405  knakahar     struct wm_txqueue *txq)
   6561  1.358  knakahar {
   6562  1.358  knakahar 
   6563  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   6564  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   6565  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6566  1.355  knakahar 
   6567  1.355  knakahar 	if (sc->sc_type < WM_T_82543) {
   6568  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(txq, 0));
   6569  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(txq, 0));
   6570  1.398  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCS_SIZE(txq));
   6571  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
   6572  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
   6573  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
   6574  1.355  knakahar 	} else {
   6575  1.405  knakahar 		int qid = wmq->wmq_id;
   6576  1.364  knakahar 
   6577  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDBAH(qid), WM_CDTXADDR_HI(txq, 0));
   6578  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDBAL(qid), WM_CDTXADDR_LO(txq, 0));
   6579  1.398  knakahar 		CSR_WRITE(sc, WMREG_TDLEN(qid), WM_TXDESCS_SIZE(txq));
   6580  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDH(qid), 0);
   6581  1.355  knakahar 
   6582  1.355  knakahar 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   6583  1.355  knakahar 			/*
   6584  1.355  knakahar 			 * Don't write TDT before TCTL.EN is set.
   6585  1.355  knakahar 			 * See the document.
   6586  1.355  knakahar 			 */
   6587  1.364  knakahar 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_QUEUE_ENABLE
   6588  1.355  knakahar 			    | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0)
   6589  1.355  knakahar 			    | TXDCTL_WTHRESH(0));
   6590  1.355  knakahar 		else {
   6591  1.490  knakahar 			/* XXX should update with AIM? */
   6592  1.490  knakahar 			CSR_WRITE(sc, WMREG_TIDV, wmq->wmq_itr / 4);
   6593  1.355  knakahar 			if (sc->sc_type >= WM_T_82540) {
   6594  1.355  knakahar 				/* should be same */
   6595  1.490  knakahar 				CSR_WRITE(sc, WMREG_TADV, wmq->wmq_itr / 4);
   6596  1.355  knakahar 			}
   6597  1.355  knakahar 
   6598  1.364  knakahar 			CSR_WRITE(sc, WMREG_TDT(qid), 0);
   6599  1.364  knakahar 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_PTHRESH(0) |
   6600  1.355  knakahar 			    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
   6601  1.355  knakahar 		}
   6602  1.355  knakahar 	}
   6603  1.355  knakahar }
   6604  1.355  knakahar 
   6605  1.355  knakahar static void
   6606  1.362  knakahar wm_init_tx_buffer(struct wm_softc *sc __unused, struct wm_txqueue *txq)
   6607  1.355  knakahar {
   6608  1.355  knakahar 	int i;
   6609  1.355  knakahar 
   6610  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6611  1.355  knakahar 
   6612  1.355  knakahar 	/* Initialize the transmit job descriptors. */
   6613  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++)
   6614  1.356  knakahar 		txq->txq_soft[i].txs_mbuf = NULL;
   6615  1.356  knakahar 	txq->txq_sfree = WM_TXQUEUELEN(txq);
   6616  1.356  knakahar 	txq->txq_snext = 0;
   6617  1.356  knakahar 	txq->txq_sdirty = 0;
   6618  1.355  knakahar }
   6619  1.355  knakahar 
   6620  1.355  knakahar static void
   6621  1.405  knakahar wm_init_tx_queue(struct wm_softc *sc, struct wm_queue *wmq,
   6622  1.405  knakahar     struct wm_txqueue *txq)
   6623  1.355  knakahar {
   6624  1.355  knakahar 
   6625  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6626  1.355  knakahar 
   6627  1.355  knakahar 	/*
   6628  1.355  knakahar 	 * Set up some register offsets that are different between
   6629  1.355  knakahar 	 * the i82542 and the i82543 and later chips.
   6630  1.355  knakahar 	 */
   6631  1.388   msaitoh 	if (sc->sc_type < WM_T_82543)
   6632  1.356  knakahar 		txq->txq_tdt_reg = WMREG_OLD_TDT;
   6633  1.388   msaitoh 	else
   6634  1.405  knakahar 		txq->txq_tdt_reg = WMREG_TDT(wmq->wmq_id);
   6635  1.355  knakahar 
   6636  1.362  knakahar 	wm_init_tx_descs(sc, txq);
   6637  1.405  knakahar 	wm_init_tx_regs(sc, wmq, txq);
   6638  1.362  knakahar 	wm_init_tx_buffer(sc, txq);
   6639  1.355  knakahar }
   6640  1.355  knakahar 
   6641  1.355  knakahar static void
   6642  1.405  knakahar wm_init_rx_regs(struct wm_softc *sc, struct wm_queue *wmq,
   6643  1.405  knakahar     struct wm_rxqueue *rxq)
   6644  1.355  knakahar {
   6645  1.355  knakahar 
   6646  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6647  1.355  knakahar 
   6648  1.355  knakahar 	/*
   6649  1.355  knakahar 	 * Initialize the receive descriptor and receive job
   6650  1.355  knakahar 	 * descriptor rings.
   6651  1.355  knakahar 	 */
   6652  1.355  knakahar 	if (sc->sc_type < WM_T_82543) {
   6653  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(rxq, 0));
   6654  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(rxq, 0));
   6655  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDLEN0,
   6656  1.466  knakahar 		    rxq->rxq_descsize * rxq->rxq_ndesc);
   6657  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
   6658  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
   6659  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
   6660  1.355  knakahar 
   6661  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
   6662  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
   6663  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
   6664  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
   6665  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
   6666  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
   6667  1.355  knakahar 	} else {
   6668  1.405  knakahar 		int qid = wmq->wmq_id;
   6669  1.364  knakahar 
   6670  1.364  knakahar 		CSR_WRITE(sc, WMREG_RDBAH(qid), WM_CDRXADDR_HI(rxq, 0));
   6671  1.364  knakahar 		CSR_WRITE(sc, WMREG_RDBAL(qid), WM_CDRXADDR_LO(rxq, 0));
   6672  1.466  knakahar 		CSR_WRITE(sc, WMREG_RDLEN(qid), rxq->rxq_descsize * rxq->rxq_ndesc);
   6673  1.355  knakahar 
   6674  1.355  knakahar 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   6675  1.355  knakahar 			if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
   6676  1.478  knakahar 				panic("%s: MCLBYTES %d unsupported for 82575 or higher\n", __func__, MCLBYTES);
   6677  1.466  knakahar 
   6678  1.466  knakahar 			/* Currently, support SRRCTL_DESCTYPE_ADV_ONEBUF only. */
   6679  1.466  knakahar 			CSR_WRITE(sc, WMREG_SRRCTL(qid), SRRCTL_DESCTYPE_ADV_ONEBUF
   6680  1.355  knakahar 			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
   6681  1.364  knakahar 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_QUEUE_ENABLE
   6682  1.355  knakahar 			    | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
   6683  1.355  knakahar 			    | RXDCTL_WTHRESH(1));
   6684  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
   6685  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
   6686  1.355  knakahar 		} else {
   6687  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
   6688  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
   6689  1.490  knakahar 			/* XXX should update with AIM? */
   6690  1.490  knakahar 			CSR_WRITE(sc, WMREG_RDTR, (wmq->wmq_itr / 4) | RDTR_FPD);
   6691  1.368  knakahar 			/* MUST be same */
   6692  1.490  knakahar 			CSR_WRITE(sc, WMREG_RADV, wmq->wmq_itr / 4);
   6693  1.364  knakahar 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_PTHRESH(0) |
   6694  1.358  knakahar 			    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
   6695  1.355  knakahar 		}
   6696  1.355  knakahar 	}
   6697  1.355  knakahar }
   6698  1.355  knakahar 
   6699  1.355  knakahar static int
   6700  1.362  knakahar wm_init_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6701  1.355  knakahar {
   6702  1.355  knakahar 	struct wm_rxsoft *rxs;
   6703  1.355  knakahar 	int error, i;
   6704  1.355  knakahar 
   6705  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6706  1.355  knakahar 
   6707  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6708  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   6709  1.355  knakahar 		if (rxs->rxs_mbuf == NULL) {
   6710  1.362  knakahar 			if ((error = wm_add_rxbuf(rxq, i)) != 0) {
   6711  1.355  knakahar 				log(LOG_ERR, "%s: unable to allocate or map "
   6712  1.355  knakahar 				    "rx buffer %d, error = %d\n",
   6713  1.355  knakahar 				    device_xname(sc->sc_dev), i, error);
   6714  1.355  knakahar 				/*
   6715  1.355  knakahar 				 * XXX Should attempt to run with fewer receive
   6716  1.355  knakahar 				 * XXX buffers instead of just failing.
   6717  1.355  knakahar 				 */
   6718  1.362  knakahar 				wm_rxdrain(rxq);
   6719  1.355  knakahar 				return ENOMEM;
   6720  1.355  knakahar 			}
   6721  1.355  knakahar 		} else {
   6722  1.355  knakahar 			/*
   6723  1.548   msaitoh 			 * For 82575 and 82576, the RX descriptors must be
   6724  1.548   msaitoh 			 * initialized after the setting of RCTL.EN in
   6725  1.355  knakahar 			 * wm_set_filter()
   6726  1.355  knakahar 			 */
   6727  1.548   msaitoh 			if ((sc->sc_flags & WM_F_NEWQUEUE) == 0)
   6728  1.548   msaitoh 				wm_init_rxdesc(rxq, i);
   6729  1.355  knakahar 		}
   6730  1.355  knakahar 	}
   6731  1.356  knakahar 	rxq->rxq_ptr = 0;
   6732  1.356  knakahar 	rxq->rxq_discard = 0;
   6733  1.356  knakahar 	WM_RXCHAIN_RESET(rxq);
   6734  1.355  knakahar 
   6735  1.355  knakahar 	return 0;
   6736  1.355  knakahar }
   6737  1.355  knakahar 
   6738  1.355  knakahar static int
   6739  1.405  knakahar wm_init_rx_queue(struct wm_softc *sc, struct wm_queue *wmq,
   6740  1.405  knakahar     struct wm_rxqueue *rxq)
   6741  1.355  knakahar {
   6742  1.355  knakahar 
   6743  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6744  1.355  knakahar 
   6745  1.355  knakahar 	/*
   6746  1.355  knakahar 	 * Set up some register offsets that are different between
   6747  1.355  knakahar 	 * the i82542 and the i82543 and later chips.
   6748  1.355  knakahar 	 */
   6749  1.388   msaitoh 	if (sc->sc_type < WM_T_82543)
   6750  1.356  knakahar 		rxq->rxq_rdt_reg = WMREG_OLD_RDT0;
   6751  1.388   msaitoh 	else
   6752  1.405  knakahar 		rxq->rxq_rdt_reg = WMREG_RDT(wmq->wmq_id);
   6753  1.355  knakahar 
   6754  1.405  knakahar 	wm_init_rx_regs(sc, wmq, rxq);
   6755  1.362  knakahar 	return wm_init_rx_buffer(sc, rxq);
   6756  1.355  knakahar }
   6757  1.355  knakahar 
   6758  1.355  knakahar /*
   6759  1.355  knakahar  * wm_init_quques:
   6760  1.355  knakahar  *	Initialize {tx,rx}descs and {tx,rx} buffers
   6761  1.355  knakahar  */
   6762  1.355  knakahar static int
   6763  1.355  knakahar wm_init_txrx_queues(struct wm_softc *sc)
   6764  1.355  knakahar {
   6765  1.406  knakahar 	int i, error = 0;
   6766  1.355  knakahar 
   6767  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   6768  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   6769  1.420   msaitoh 
   6770  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6771  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[i];
   6772  1.405  knakahar 		struct wm_txqueue *txq = &wmq->wmq_txq;
   6773  1.405  knakahar 		struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   6774  1.405  knakahar 
   6775  1.495  knakahar 		/*
   6776  1.495  knakahar 		 * TODO
   6777  1.495  knakahar 		 * Currently, use constant variable instead of AIM.
   6778  1.495  knakahar 		 * Furthermore, the interrupt interval of multiqueue which use
   6779  1.495  knakahar 		 * polling mode is less than default value.
   6780  1.495  knakahar 		 * More tuning and AIM are required.
   6781  1.495  knakahar 		 */
   6782  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   6783  1.495  knakahar 			wmq->wmq_itr = 50;
   6784  1.495  knakahar 		else
   6785  1.495  knakahar 			wmq->wmq_itr = sc->sc_itr_init;
   6786  1.495  knakahar 		wmq->wmq_set_itr = true;
   6787  1.490  knakahar 
   6788  1.413     skrll 		mutex_enter(txq->txq_lock);
   6789  1.405  knakahar 		wm_init_tx_queue(sc, wmq, txq);
   6790  1.413     skrll 		mutex_exit(txq->txq_lock);
   6791  1.355  knakahar 
   6792  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   6793  1.405  knakahar 		error = wm_init_rx_queue(sc, wmq, rxq);
   6794  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   6795  1.364  knakahar 		if (error)
   6796  1.364  knakahar 			break;
   6797  1.364  knakahar 	}
   6798  1.355  knakahar 
   6799  1.355  knakahar 	return error;
   6800  1.355  knakahar }
   6801  1.355  knakahar 
   6802    1.1   thorpej /*
   6803  1.371   msaitoh  * wm_tx_offload:
   6804  1.371   msaitoh  *
   6805  1.371   msaitoh  *	Set up TCP/IP checksumming parameters for the
   6806  1.371   msaitoh  *	specified packet.
   6807  1.371   msaitoh  */
   6808  1.371   msaitoh static int
   6809  1.498  knakahar wm_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
   6810  1.498  knakahar     struct wm_txsoft *txs, uint32_t *cmdp, uint8_t *fieldsp)
   6811  1.371   msaitoh {
   6812  1.371   msaitoh 	struct mbuf *m0 = txs->txs_mbuf;
   6813  1.371   msaitoh 	struct livengood_tcpip_ctxdesc *t;
   6814  1.371   msaitoh 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
   6815  1.371   msaitoh 	uint32_t ipcse;
   6816  1.371   msaitoh 	struct ether_header *eh;
   6817  1.371   msaitoh 	int offset, iphl;
   6818  1.371   msaitoh 	uint8_t fields;
   6819  1.371   msaitoh 
   6820  1.371   msaitoh 	/*
   6821  1.371   msaitoh 	 * XXX It would be nice if the mbuf pkthdr had offset
   6822  1.371   msaitoh 	 * fields for the protocol headers.
   6823  1.371   msaitoh 	 */
   6824  1.371   msaitoh 
   6825  1.371   msaitoh 	eh = mtod(m0, struct ether_header *);
   6826  1.371   msaitoh 	switch (htons(eh->ether_type)) {
   6827  1.371   msaitoh 	case ETHERTYPE_IP:
   6828  1.371   msaitoh 	case ETHERTYPE_IPV6:
   6829  1.371   msaitoh 		offset = ETHER_HDR_LEN;
   6830  1.371   msaitoh 		break;
   6831  1.371   msaitoh 
   6832  1.371   msaitoh 	case ETHERTYPE_VLAN:
   6833  1.371   msaitoh 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   6834  1.371   msaitoh 		break;
   6835  1.371   msaitoh 
   6836  1.371   msaitoh 	default:
   6837  1.371   msaitoh 		/*
   6838  1.371   msaitoh 		 * Don't support this protocol or encapsulation.
   6839  1.371   msaitoh 		 */
   6840  1.371   msaitoh 		*fieldsp = 0;
   6841  1.371   msaitoh 		*cmdp = 0;
   6842  1.371   msaitoh 		return 0;
   6843  1.371   msaitoh 	}
   6844  1.371   msaitoh 
   6845  1.371   msaitoh 	if ((m0->m_pkthdr.csum_flags &
   6846  1.499  knakahar 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
   6847  1.371   msaitoh 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   6848  1.371   msaitoh 	} else {
   6849  1.371   msaitoh 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
   6850  1.371   msaitoh 	}
   6851  1.371   msaitoh 	ipcse = offset + iphl - 1;
   6852  1.371   msaitoh 
   6853  1.371   msaitoh 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
   6854  1.371   msaitoh 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
   6855  1.371   msaitoh 	seg = 0;
   6856  1.371   msaitoh 	fields = 0;
   6857  1.371   msaitoh 
   6858  1.371   msaitoh 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
   6859  1.371   msaitoh 		int hlen = offset + iphl;
   6860  1.371   msaitoh 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   6861  1.371   msaitoh 
   6862  1.371   msaitoh 		if (__predict_false(m0->m_len <
   6863  1.371   msaitoh 				    (hlen + sizeof(struct tcphdr)))) {
   6864  1.371   msaitoh 			/*
   6865  1.371   msaitoh 			 * TCP/IP headers are not in the first mbuf; we need
   6866  1.371   msaitoh 			 * to do this the slow and painful way.  Let's just
   6867  1.371   msaitoh 			 * hope this doesn't happen very often.
   6868  1.371   msaitoh 			 */
   6869  1.371   msaitoh 			struct tcphdr th;
   6870  1.371   msaitoh 
   6871  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtsopain);
   6872  1.371   msaitoh 
   6873  1.371   msaitoh 			m_copydata(m0, hlen, sizeof(th), &th);
   6874  1.371   msaitoh 			if (v4) {
   6875  1.371   msaitoh 				struct ip ip;
   6876  1.371   msaitoh 
   6877  1.371   msaitoh 				m_copydata(m0, offset, sizeof(ip), &ip);
   6878  1.371   msaitoh 				ip.ip_len = 0;
   6879  1.371   msaitoh 				m_copyback(m0,
   6880  1.371   msaitoh 				    offset + offsetof(struct ip, ip_len),
   6881  1.371   msaitoh 				    sizeof(ip.ip_len), &ip.ip_len);
   6882  1.371   msaitoh 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   6883  1.371   msaitoh 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   6884  1.371   msaitoh 			} else {
   6885  1.371   msaitoh 				struct ip6_hdr ip6;
   6886  1.371   msaitoh 
   6887  1.371   msaitoh 				m_copydata(m0, offset, sizeof(ip6), &ip6);
   6888  1.371   msaitoh 				ip6.ip6_plen = 0;
   6889  1.371   msaitoh 				m_copyback(m0,
   6890  1.371   msaitoh 				    offset + offsetof(struct ip6_hdr, ip6_plen),
   6891  1.371   msaitoh 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
   6892  1.371   msaitoh 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
   6893  1.371   msaitoh 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
   6894  1.371   msaitoh 			}
   6895  1.371   msaitoh 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   6896  1.371   msaitoh 			    sizeof(th.th_sum), &th.th_sum);
   6897  1.371   msaitoh 
   6898  1.371   msaitoh 			hlen += th.th_off << 2;
   6899  1.371   msaitoh 		} else {
   6900  1.371   msaitoh 			/*
   6901  1.371   msaitoh 			 * TCP/IP headers are in the first mbuf; we can do
   6902  1.371   msaitoh 			 * this the easy way.
   6903  1.371   msaitoh 			 */
   6904  1.371   msaitoh 			struct tcphdr *th;
   6905  1.371   msaitoh 
   6906  1.371   msaitoh 			if (v4) {
   6907  1.371   msaitoh 				struct ip *ip =
   6908  1.371   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   6909  1.371   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   6910  1.371   msaitoh 
   6911  1.371   msaitoh 				ip->ip_len = 0;
   6912  1.371   msaitoh 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   6913  1.371   msaitoh 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   6914  1.371   msaitoh 			} else {
   6915  1.371   msaitoh 				struct ip6_hdr *ip6 =
   6916  1.371   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   6917  1.371   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   6918  1.371   msaitoh 
   6919  1.371   msaitoh 				ip6->ip6_plen = 0;
   6920  1.371   msaitoh 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
   6921  1.371   msaitoh 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
   6922  1.371   msaitoh 			}
   6923  1.371   msaitoh 			hlen += th->th_off << 2;
   6924  1.371   msaitoh 		}
   6925  1.371   msaitoh 
   6926  1.371   msaitoh 		if (v4) {
   6927  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso);
   6928  1.371   msaitoh 			cmdlen |= WTX_TCPIP_CMD_IP;
   6929  1.371   msaitoh 		} else {
   6930  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso6);
   6931  1.371   msaitoh 			ipcse = 0;
   6932  1.371   msaitoh 		}
   6933  1.371   msaitoh 		cmd |= WTX_TCPIP_CMD_TSE;
   6934  1.371   msaitoh 		cmdlen |= WTX_TCPIP_CMD_TSE |
   6935  1.371   msaitoh 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
   6936  1.371   msaitoh 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
   6937  1.371   msaitoh 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
   6938  1.371   msaitoh 	}
   6939  1.371   msaitoh 
   6940  1.371   msaitoh 	/*
   6941  1.371   msaitoh 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
   6942  1.371   msaitoh 	 * offload feature, if we load the context descriptor, we
   6943  1.371   msaitoh 	 * MUST provide valid values for IPCSS and TUCSS fields.
   6944  1.371   msaitoh 	 */
   6945  1.371   msaitoh 
   6946  1.371   msaitoh 	ipcs = WTX_TCPIP_IPCSS(offset) |
   6947  1.371   msaitoh 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
   6948  1.371   msaitoh 	    WTX_TCPIP_IPCSE(ipcse);
   6949  1.388   msaitoh 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4 | M_CSUM_TSOv4)) {
   6950  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txipsum);
   6951  1.371   msaitoh 		fields |= WTX_IXSM;
   6952  1.371   msaitoh 	}
   6953  1.371   msaitoh 
   6954  1.371   msaitoh 	offset += iphl;
   6955  1.371   msaitoh 
   6956  1.371   msaitoh 	if (m0->m_pkthdr.csum_flags &
   6957  1.388   msaitoh 	    (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TSOv4)) {
   6958  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum);
   6959  1.371   msaitoh 		fields |= WTX_TXSM;
   6960  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   6961  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset +
   6962  1.371   msaitoh 		    M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
   6963  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   6964  1.371   msaitoh 	} else if ((m0->m_pkthdr.csum_flags &
   6965  1.388   msaitoh 	    (M_CSUM_TCPv6 | M_CSUM_UDPv6 | M_CSUM_TSOv6)) != 0) {
   6966  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum6);
   6967  1.371   msaitoh 		fields |= WTX_TXSM;
   6968  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   6969  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset +
   6970  1.371   msaitoh 		    M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
   6971  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   6972  1.371   msaitoh 	} else {
   6973  1.371   msaitoh 		/* Just initialize it to a valid TCP context. */
   6974  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   6975  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
   6976  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   6977  1.371   msaitoh 	}
   6978  1.371   msaitoh 
   6979  1.500  knakahar 	/*
   6980  1.500  knakahar 	 * We don't have to write context descriptor for every packet
   6981  1.500  knakahar 	 * except for 82574. For 82574, we must write context descriptor
   6982  1.500  knakahar 	 * for every packet when we use two descriptor queues.
   6983  1.500  knakahar 	 * It would be overhead to write context descriptor for every packet,
   6984  1.500  knakahar 	 * however it does not cause problems.
   6985  1.500  knakahar 	 */
   6986  1.371   msaitoh 	/* Fill in the context descriptor. */
   6987  1.371   msaitoh 	t = (struct livengood_tcpip_ctxdesc *)
   6988  1.371   msaitoh 	    &txq->txq_descs[txq->txq_next];
   6989  1.371   msaitoh 	t->tcpip_ipcs = htole32(ipcs);
   6990  1.371   msaitoh 	t->tcpip_tucs = htole32(tucs);
   6991  1.371   msaitoh 	t->tcpip_cmdlen = htole32(cmdlen);
   6992  1.371   msaitoh 	t->tcpip_seg = htole32(seg);
   6993  1.371   msaitoh 	wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE);
   6994  1.371   msaitoh 
   6995  1.371   msaitoh 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   6996  1.371   msaitoh 	txs->txs_ndesc++;
   6997  1.371   msaitoh 
   6998  1.371   msaitoh 	*cmdp = cmd;
   6999  1.371   msaitoh 	*fieldsp = fields;
   7000  1.371   msaitoh 
   7001  1.371   msaitoh 	return 0;
   7002  1.371   msaitoh }
   7003  1.371   msaitoh 
   7004  1.454  knakahar static inline int
   7005  1.454  knakahar wm_select_txqueue(struct ifnet *ifp, struct mbuf *m)
   7006  1.454  knakahar {
   7007  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7008  1.454  knakahar 	u_int cpuid = cpu_index(curcpu());
   7009  1.454  knakahar 
   7010  1.454  knakahar 	/*
   7011  1.454  knakahar 	 * Currently, simple distribute strategy.
   7012  1.454  knakahar 	 * TODO:
   7013  1.461  knakahar 	 * distribute by flowid(RSS has value).
   7014  1.454  knakahar 	 */
   7015  1.488  knakahar         return (cpuid + ncpu - sc->sc_affinity_offset) % sc->sc_nqueues;
   7016  1.454  knakahar }
   7017  1.454  knakahar 
   7018  1.371   msaitoh /*
   7019  1.281   msaitoh  * wm_start:		[ifnet interface function]
   7020    1.1   thorpej  *
   7021  1.281   msaitoh  *	Start packet transmission on the interface.
   7022    1.1   thorpej  */
   7023   1.47   thorpej static void
   7024  1.281   msaitoh wm_start(struct ifnet *ifp)
   7025    1.1   thorpej {
   7026  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   7027  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7028  1.281   msaitoh 
   7029  1.496  knakahar #ifdef WM_MPSAFE
   7030  1.543     ozaki 	KASSERT(if_is_mpsafe(ifp));
   7031  1.496  knakahar #endif
   7032  1.455  knakahar 	/*
   7033  1.455  knakahar 	 * ifp->if_obytes and ifp->if_omcasts are added in if_transmit()@if.c.
   7034  1.455  knakahar 	 */
   7035  1.455  knakahar 
   7036  1.413     skrll 	mutex_enter(txq->txq_lock);
   7037  1.429  knakahar 	if (!txq->txq_stopping)
   7038  1.281   msaitoh 		wm_start_locked(ifp);
   7039  1.413     skrll 	mutex_exit(txq->txq_lock);
   7040  1.281   msaitoh }
   7041    1.1   thorpej 
   7042  1.281   msaitoh static void
   7043  1.281   msaitoh wm_start_locked(struct ifnet *ifp)
   7044  1.281   msaitoh {
   7045  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   7046  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7047  1.454  knakahar 
   7048  1.454  knakahar 	wm_send_common_locked(ifp, txq, false);
   7049  1.454  knakahar }
   7050  1.454  knakahar 
   7051  1.454  knakahar static int
   7052  1.454  knakahar wm_transmit(struct ifnet *ifp, struct mbuf *m)
   7053  1.454  knakahar {
   7054  1.454  knakahar 	int qid;
   7055  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7056  1.454  knakahar 	struct wm_txqueue *txq;
   7057  1.454  knakahar 
   7058  1.454  knakahar 	qid = wm_select_txqueue(ifp, m);
   7059  1.454  knakahar 	txq = &sc->sc_queue[qid].wmq_txq;
   7060  1.454  knakahar 
   7061  1.454  knakahar 	if (__predict_false(!pcq_put(txq->txq_interq, m))) {
   7062  1.454  knakahar 		m_freem(m);
   7063  1.454  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7064  1.454  knakahar 		return ENOBUFS;
   7065  1.454  knakahar 	}
   7066  1.454  knakahar 
   7067  1.455  knakahar 	/*
   7068  1.455  knakahar 	 * XXXX NOMPSAFE: ifp->if_data should be percpu.
   7069  1.455  knakahar 	 */
   7070  1.455  knakahar 	ifp->if_obytes += m->m_pkthdr.len;
   7071  1.455  knakahar 	if (m->m_flags & M_MCAST)
   7072  1.455  knakahar 		ifp->if_omcasts++;
   7073  1.455  knakahar 
   7074  1.454  knakahar 	if (mutex_tryenter(txq->txq_lock)) {
   7075  1.454  knakahar 		if (!txq->txq_stopping)
   7076  1.454  knakahar 			wm_transmit_locked(ifp, txq);
   7077  1.454  knakahar 		mutex_exit(txq->txq_lock);
   7078  1.454  knakahar 	}
   7079  1.454  knakahar 
   7080  1.454  knakahar 	return 0;
   7081  1.454  knakahar }
   7082  1.454  knakahar 
   7083  1.454  knakahar static void
   7084  1.454  knakahar wm_transmit_locked(struct ifnet *ifp, struct wm_txqueue *txq)
   7085  1.454  knakahar {
   7086  1.454  knakahar 
   7087  1.454  knakahar 	wm_send_common_locked(ifp, txq, true);
   7088  1.454  knakahar }
   7089  1.454  knakahar 
   7090  1.454  knakahar static void
   7091  1.454  knakahar wm_send_common_locked(struct ifnet *ifp, struct wm_txqueue *txq,
   7092  1.454  knakahar     bool is_transmit)
   7093  1.454  knakahar {
   7094  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7095  1.281   msaitoh 	struct mbuf *m0;
   7096  1.281   msaitoh 	struct wm_txsoft *txs;
   7097  1.281   msaitoh 	bus_dmamap_t dmamap;
   7098  1.281   msaitoh 	int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
   7099  1.281   msaitoh 	bus_addr_t curaddr;
   7100  1.281   msaitoh 	bus_size_t seglen, curlen;
   7101  1.281   msaitoh 	uint32_t cksumcmd;
   7102  1.281   msaitoh 	uint8_t cksumfields;
   7103    1.1   thorpej 
   7104  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   7105    1.1   thorpej 
   7106  1.482  knakahar 	if ((ifp->if_flags & IFF_RUNNING) == 0)
   7107  1.482  knakahar 		return;
   7108  1.482  knakahar 	if ((ifp->if_flags & IFF_OACTIVE) != 0 && !is_transmit)
   7109  1.281   msaitoh 		return;
   7110  1.479  knakahar 	if ((txq->txq_flags & WM_TXQ_NO_SPACE) != 0)
   7111  1.479  knakahar 		return;
   7112    1.1   thorpej 
   7113  1.281   msaitoh 	/* Remember the previous number of free descriptors. */
   7114  1.356  knakahar 	ofree = txq->txq_free;
   7115    1.1   thorpej 
   7116  1.281   msaitoh 	/*
   7117  1.281   msaitoh 	 * Loop through the send queue, setting up transmit descriptors
   7118  1.281   msaitoh 	 * until we drain the queue, or use up all available transmit
   7119  1.281   msaitoh 	 * descriptors.
   7120  1.281   msaitoh 	 */
   7121  1.281   msaitoh 	for (;;) {
   7122  1.281   msaitoh 		m0 = NULL;
   7123    1.1   thorpej 
   7124  1.281   msaitoh 		/* Get a work queue entry. */
   7125  1.356  knakahar 		if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) {
   7126  1.403  knakahar 			wm_txeof(sc, txq);
   7127  1.356  knakahar 			if (txq->txq_sfree == 0) {
   7128  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   7129  1.281   msaitoh 				    ("%s: TX: no free job descriptors\n",
   7130  1.281   msaitoh 					device_xname(sc->sc_dev)));
   7131  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txsstall);
   7132  1.281   msaitoh 				break;
   7133    1.1   thorpej 			}
   7134    1.1   thorpej 		}
   7135    1.1   thorpej 
   7136  1.281   msaitoh 		/* Grab a packet off the queue. */
   7137  1.454  knakahar 		if (is_transmit)
   7138  1.454  knakahar 			m0 = pcq_get(txq->txq_interq);
   7139  1.454  knakahar 		else
   7140  1.454  knakahar 			IFQ_DEQUEUE(&ifp->if_snd, m0);
   7141  1.281   msaitoh 		if (m0 == NULL)
   7142  1.281   msaitoh 			break;
   7143  1.281   msaitoh 
   7144  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7145  1.281   msaitoh 		    ("%s: TX: have packet to transmit: %p\n",
   7146  1.281   msaitoh 		    device_xname(sc->sc_dev), m0));
   7147  1.281   msaitoh 
   7148  1.356  knakahar 		txs = &txq->txq_soft[txq->txq_snext];
   7149  1.281   msaitoh 		dmamap = txs->txs_dmamap;
   7150    1.1   thorpej 
   7151  1.281   msaitoh 		use_tso = (m0->m_pkthdr.csum_flags &
   7152  1.281   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0;
   7153    1.1   thorpej 
   7154    1.1   thorpej 		/*
   7155  1.281   msaitoh 		 * So says the Linux driver:
   7156  1.281   msaitoh 		 * The controller does a simple calculation to make sure
   7157  1.281   msaitoh 		 * there is enough room in the FIFO before initiating the
   7158  1.281   msaitoh 		 * DMA for each buffer.  The calc is:
   7159  1.281   msaitoh 		 *	4 = ceil(buffer len / MSS)
   7160  1.281   msaitoh 		 * To make sure we don't overrun the FIFO, adjust the max
   7161  1.281   msaitoh 		 * buffer len if the MSS drops.
   7162  1.281   msaitoh 		 */
   7163  1.281   msaitoh 		dmamap->dm_maxsegsz =
   7164  1.281   msaitoh 		    (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
   7165  1.281   msaitoh 		    ? m0->m_pkthdr.segsz << 2
   7166  1.281   msaitoh 		    : WTX_MAX_LEN;
   7167  1.281   msaitoh 
   7168  1.281   msaitoh 		/*
   7169  1.281   msaitoh 		 * Load the DMA map.  If this fails, the packet either
   7170  1.281   msaitoh 		 * didn't fit in the allotted number of segments, or we
   7171  1.281   msaitoh 		 * were short on resources.  For the too-many-segments
   7172  1.281   msaitoh 		 * case, we simply report an error and drop the packet,
   7173  1.281   msaitoh 		 * since we can't sanely copy a jumbo packet to a single
   7174  1.281   msaitoh 		 * buffer.
   7175    1.1   thorpej 		 */
   7176  1.281   msaitoh 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   7177  1.388   msaitoh 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
   7178  1.281   msaitoh 		if (error) {
   7179  1.281   msaitoh 			if (error == EFBIG) {
   7180  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txdrop);
   7181  1.281   msaitoh 				log(LOG_ERR, "%s: Tx packet consumes too many "
   7182  1.281   msaitoh 				    "DMA segments, dropping...\n",
   7183  1.281   msaitoh 				    device_xname(sc->sc_dev));
   7184  1.281   msaitoh 				wm_dump_mbuf_chain(sc, m0);
   7185  1.281   msaitoh 				m_freem(m0);
   7186  1.281   msaitoh 				continue;
   7187  1.281   msaitoh 			}
   7188  1.281   msaitoh 			/*  Short on resources, just stop for now. */
   7189  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7190  1.281   msaitoh 			    ("%s: TX: dmamap load failed: %d\n",
   7191  1.281   msaitoh 			    device_xname(sc->sc_dev), error));
   7192  1.281   msaitoh 			break;
   7193    1.1   thorpej 		}
   7194    1.1   thorpej 
   7195  1.281   msaitoh 		segs_needed = dmamap->dm_nsegs;
   7196  1.281   msaitoh 		if (use_tso) {
   7197  1.281   msaitoh 			/* For sentinel descriptor; see below. */
   7198  1.281   msaitoh 			segs_needed++;
   7199  1.281   msaitoh 		}
   7200    1.1   thorpej 
   7201    1.1   thorpej 		/*
   7202  1.281   msaitoh 		 * Ensure we have enough descriptors free to describe
   7203  1.281   msaitoh 		 * the packet.  Note, we always reserve one descriptor
   7204  1.281   msaitoh 		 * at the end of the ring due to the semantics of the
   7205  1.281   msaitoh 		 * TDT register, plus one more in the event we need
   7206  1.281   msaitoh 		 * to load offload context.
   7207    1.1   thorpej 		 */
   7208  1.356  knakahar 		if (segs_needed > txq->txq_free - 2) {
   7209  1.281   msaitoh 			/*
   7210  1.281   msaitoh 			 * Not enough free descriptors to transmit this
   7211  1.281   msaitoh 			 * packet.  We haven't committed anything yet,
   7212  1.281   msaitoh 			 * so just unload the DMA map, put the packet
   7213  1.281   msaitoh 			 * pack on the queue, and punt.  Notify the upper
   7214  1.281   msaitoh 			 * layer that there are no more slots left.
   7215  1.281   msaitoh 			 */
   7216  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7217  1.281   msaitoh 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
   7218  1.281   msaitoh 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
   7219  1.366  knakahar 			    segs_needed, txq->txq_free - 1));
   7220  1.482  knakahar 			if (!is_transmit)
   7221  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   7222  1.479  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   7223  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   7224  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdstall);
   7225  1.281   msaitoh 			break;
   7226    1.1   thorpej 		}
   7227    1.1   thorpej 
   7228    1.1   thorpej 		/*
   7229  1.281   msaitoh 		 * Check for 82547 Tx FIFO bug.  We need to do this
   7230  1.281   msaitoh 		 * once we know we can transmit the packet, since we
   7231  1.281   msaitoh 		 * do some internal FIFO space accounting here.
   7232    1.1   thorpej 		 */
   7233  1.281   msaitoh 		if (sc->sc_type == WM_T_82547 &&
   7234  1.281   msaitoh 		    wm_82547_txfifo_bugchk(sc, m0)) {
   7235  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7236  1.281   msaitoh 			    ("%s: TX: 82547 Tx FIFO bug detected\n",
   7237  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   7238  1.482  knakahar 			if (!is_transmit)
   7239  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   7240  1.479  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   7241  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   7242  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txfifo_stall);
   7243  1.281   msaitoh 			break;
   7244  1.281   msaitoh 		}
   7245   1.93   thorpej 
   7246  1.281   msaitoh 		/* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
   7247    1.1   thorpej 
   7248  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7249  1.281   msaitoh 		    ("%s: TX: packet has %d (%d) DMA segments\n",
   7250  1.281   msaitoh 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
   7251    1.1   thorpej 
   7252  1.417  knakahar 		WM_EVCNT_INCR(&txq->txq_ev_txseg[dmamap->dm_nsegs - 1]);
   7253    1.1   thorpej 
   7254    1.1   thorpej 		/*
   7255  1.281   msaitoh 		 * Store a pointer to the packet so that we can free it
   7256  1.281   msaitoh 		 * later.
   7257  1.281   msaitoh 		 *
   7258  1.281   msaitoh 		 * Initially, we consider the number of descriptors the
   7259  1.281   msaitoh 		 * packet uses the number of DMA segments.  This may be
   7260  1.281   msaitoh 		 * incremented by 1 if we do checksum offload (a descriptor
   7261  1.281   msaitoh 		 * is used to set the checksum context).
   7262    1.1   thorpej 		 */
   7263  1.281   msaitoh 		txs->txs_mbuf = m0;
   7264  1.356  knakahar 		txs->txs_firstdesc = txq->txq_next;
   7265  1.281   msaitoh 		txs->txs_ndesc = segs_needed;
   7266  1.281   msaitoh 
   7267  1.281   msaitoh 		/* Set up offload parameters for this packet. */
   7268  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags &
   7269  1.388   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6 |
   7270  1.388   msaitoh 		    M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   7271  1.388   msaitoh 		    M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
   7272  1.498  knakahar 			if (wm_tx_offload(sc, txq, txs, &cksumcmd,
   7273  1.281   msaitoh 					  &cksumfields) != 0) {
   7274  1.281   msaitoh 				/* Error message already displayed. */
   7275  1.281   msaitoh 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   7276  1.281   msaitoh 				continue;
   7277  1.281   msaitoh 			}
   7278  1.281   msaitoh 		} else {
   7279  1.281   msaitoh 			cksumcmd = 0;
   7280  1.281   msaitoh 			cksumfields = 0;
   7281    1.1   thorpej 		}
   7282    1.1   thorpej 
   7283  1.281   msaitoh 		cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
   7284  1.281   msaitoh 
   7285  1.281   msaitoh 		/* Sync the DMA map. */
   7286  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   7287  1.281   msaitoh 		    BUS_DMASYNC_PREWRITE);
   7288    1.1   thorpej 
   7289  1.281   msaitoh 		/* Initialize the transmit descriptor. */
   7290  1.356  knakahar 		for (nexttx = txq->txq_next, seg = 0;
   7291  1.281   msaitoh 		     seg < dmamap->dm_nsegs; seg++) {
   7292  1.281   msaitoh 			for (seglen = dmamap->dm_segs[seg].ds_len,
   7293  1.281   msaitoh 			     curaddr = dmamap->dm_segs[seg].ds_addr;
   7294  1.281   msaitoh 			     seglen != 0;
   7295  1.281   msaitoh 			     curaddr += curlen, seglen -= curlen,
   7296  1.356  knakahar 			     nexttx = WM_NEXTTX(txq, nexttx)) {
   7297  1.281   msaitoh 				curlen = seglen;
   7298    1.1   thorpej 
   7299  1.106      yamt 				/*
   7300  1.281   msaitoh 				 * So says the Linux driver:
   7301  1.281   msaitoh 				 * Work around for premature descriptor
   7302  1.281   msaitoh 				 * write-backs in TSO mode.  Append a
   7303  1.281   msaitoh 				 * 4-byte sentinel descriptor.
   7304  1.106      yamt 				 */
   7305  1.388   msaitoh 				if (use_tso && seg == dmamap->dm_nsegs - 1 &&
   7306  1.281   msaitoh 				    curlen > 8)
   7307  1.281   msaitoh 					curlen -= 4;
   7308  1.281   msaitoh 
   7309  1.281   msaitoh 				wm_set_dma_addr(
   7310  1.388   msaitoh 				    &txq->txq_descs[nexttx].wtx_addr, curaddr);
   7311  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_cmdlen
   7312  1.388   msaitoh 				    = htole32(cksumcmd | curlen);
   7313  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_status
   7314  1.388   msaitoh 				    = 0;
   7315  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_options
   7316  1.388   msaitoh 				    = cksumfields;
   7317  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
   7318  1.281   msaitoh 				lasttx = nexttx;
   7319  1.281   msaitoh 
   7320  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   7321  1.281   msaitoh 				    ("%s: TX: desc %d: low %#" PRIx64 ", "
   7322  1.281   msaitoh 				     "len %#04zx\n",
   7323  1.281   msaitoh 				    device_xname(sc->sc_dev), nexttx,
   7324  1.281   msaitoh 				    (uint64_t)curaddr, curlen));
   7325  1.106      yamt 			}
   7326    1.1   thorpej 		}
   7327    1.1   thorpej 
   7328  1.281   msaitoh 		KASSERT(lasttx != -1);
   7329    1.1   thorpej 
   7330  1.281   msaitoh 		/*
   7331  1.281   msaitoh 		 * Set up the command byte on the last descriptor of
   7332  1.281   msaitoh 		 * the packet.  If we're in the interrupt delay window,
   7333  1.281   msaitoh 		 * delay the interrupt.
   7334  1.281   msaitoh 		 */
   7335  1.356  knakahar 		txq->txq_descs[lasttx].wtx_cmdlen |=
   7336  1.281   msaitoh 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
   7337  1.281   msaitoh 
   7338  1.281   msaitoh 		/*
   7339  1.281   msaitoh 		 * If VLANs are enabled and the packet has a VLAN tag, set
   7340  1.281   msaitoh 		 * up the descriptor to encapsulate the packet for us.
   7341  1.281   msaitoh 		 *
   7342  1.281   msaitoh 		 * This is only valid on the last descriptor of the packet.
   7343  1.281   msaitoh 		 */
   7344  1.538  knakahar 		if (vlan_has_tag(m0)) {
   7345  1.356  knakahar 			txq->txq_descs[lasttx].wtx_cmdlen |=
   7346  1.281   msaitoh 			    htole32(WTX_CMD_VLE);
   7347  1.356  knakahar 			txq->txq_descs[lasttx].wtx_fields.wtxu_vlan
   7348  1.538  knakahar 			    = htole16(vlan_get_tag(m0));
   7349  1.281   msaitoh 		}
   7350  1.281   msaitoh 
   7351  1.281   msaitoh 		txs->txs_lastdesc = lasttx;
   7352  1.281   msaitoh 
   7353  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7354  1.281   msaitoh 		    ("%s: TX: desc %d: cmdlen 0x%08x\n",
   7355  1.281   msaitoh 		    device_xname(sc->sc_dev),
   7356  1.366  knakahar 		    lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
   7357  1.281   msaitoh 
   7358  1.281   msaitoh 		/* Sync the descriptors we're using. */
   7359  1.362  knakahar 		wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc,
   7360  1.388   msaitoh 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   7361  1.281   msaitoh 
   7362  1.281   msaitoh 		/* Give the packet to the chip. */
   7363  1.356  knakahar 		CSR_WRITE(sc, txq->txq_tdt_reg, nexttx);
   7364  1.281   msaitoh 
   7365  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7366  1.281   msaitoh 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
   7367  1.281   msaitoh 
   7368  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7369  1.281   msaitoh 		    ("%s: TX: finished transmitting packet, job %d\n",
   7370  1.366  knakahar 		    device_xname(sc->sc_dev), txq->txq_snext));
   7371  1.272     ozaki 
   7372  1.281   msaitoh 		/* Advance the tx pointer. */
   7373  1.356  knakahar 		txq->txq_free -= txs->txs_ndesc;
   7374  1.356  knakahar 		txq->txq_next = nexttx;
   7375    1.1   thorpej 
   7376  1.356  knakahar 		txq->txq_sfree--;
   7377  1.356  knakahar 		txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext);
   7378  1.272     ozaki 
   7379  1.281   msaitoh 		/* Pass the packet to any BPF listeners. */
   7380  1.281   msaitoh 		bpf_mtap(ifp, m0);
   7381  1.281   msaitoh 	}
   7382  1.272     ozaki 
   7383  1.281   msaitoh 	if (m0 != NULL) {
   7384  1.482  knakahar 		if (!is_transmit)
   7385  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7386  1.479  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7387  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7388  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n",
   7389  1.388   msaitoh 			__func__));
   7390  1.281   msaitoh 		m_freem(m0);
   7391    1.1   thorpej 	}
   7392    1.1   thorpej 
   7393  1.356  knakahar 	if (txq->txq_sfree == 0 || txq->txq_free <= 2) {
   7394  1.281   msaitoh 		/* No more slots; notify upper layer. */
   7395  1.482  knakahar 		if (!is_transmit)
   7396  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7397  1.479  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7398  1.281   msaitoh 	}
   7399    1.1   thorpej 
   7400  1.356  knakahar 	if (txq->txq_free != ofree) {
   7401  1.281   msaitoh 		/* Set a watchdog timer in case the chip flakes out. */
   7402  1.549     ozaki 		ifp->if_timer = 5;
   7403  1.281   msaitoh 	}
   7404    1.1   thorpej }
   7405    1.1   thorpej 
   7406    1.1   thorpej /*
   7407  1.281   msaitoh  * wm_nq_tx_offload:
   7408    1.1   thorpej  *
   7409  1.281   msaitoh  *	Set up TCP/IP checksumming parameters for the
   7410  1.281   msaitoh  *	specified packet, for NEWQUEUE devices
   7411    1.1   thorpej  */
   7412  1.281   msaitoh static int
   7413  1.403  knakahar wm_nq_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
   7414  1.403  knakahar     struct wm_txsoft *txs, uint32_t *cmdlenp, uint32_t *fieldsp, bool *do_csum)
   7415    1.1   thorpej {
   7416  1.281   msaitoh 	struct mbuf *m0 = txs->txs_mbuf;
   7417  1.281   msaitoh 	uint32_t vl_len, mssidx, cmdc;
   7418  1.281   msaitoh 	struct ether_header *eh;
   7419  1.281   msaitoh 	int offset, iphl;
   7420  1.281   msaitoh 
   7421  1.281   msaitoh 	/*
   7422  1.281   msaitoh 	 * XXX It would be nice if the mbuf pkthdr had offset
   7423  1.281   msaitoh 	 * fields for the protocol headers.
   7424  1.281   msaitoh 	 */
   7425  1.281   msaitoh 	*cmdlenp = 0;
   7426  1.281   msaitoh 	*fieldsp = 0;
   7427  1.281   msaitoh 
   7428  1.281   msaitoh 	eh = mtod(m0, struct ether_header *);
   7429  1.281   msaitoh 	switch (htons(eh->ether_type)) {
   7430  1.281   msaitoh 	case ETHERTYPE_IP:
   7431  1.281   msaitoh 	case ETHERTYPE_IPV6:
   7432  1.281   msaitoh 		offset = ETHER_HDR_LEN;
   7433  1.281   msaitoh 		break;
   7434  1.281   msaitoh 
   7435  1.281   msaitoh 	case ETHERTYPE_VLAN:
   7436  1.281   msaitoh 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   7437  1.281   msaitoh 		break;
   7438  1.281   msaitoh 
   7439  1.281   msaitoh 	default:
   7440  1.281   msaitoh 		/* Don't support this protocol or encapsulation. */
   7441  1.281   msaitoh 		*do_csum = false;
   7442  1.281   msaitoh 		return 0;
   7443  1.281   msaitoh 	}
   7444  1.281   msaitoh 	*do_csum = true;
   7445  1.281   msaitoh 	*cmdlenp = NQTX_DTYP_D | NQTX_CMD_DEXT | NQTX_CMD_IFCS;
   7446  1.281   msaitoh 	cmdc = NQTX_DTYP_C | NQTX_CMD_DEXT;
   7447    1.1   thorpej 
   7448  1.281   msaitoh 	vl_len = (offset << NQTXC_VLLEN_MACLEN_SHIFT);
   7449  1.281   msaitoh 	KASSERT((offset & ~NQTXC_VLLEN_MACLEN_MASK) == 0);
   7450  1.281   msaitoh 
   7451  1.281   msaitoh 	if ((m0->m_pkthdr.csum_flags &
   7452  1.388   msaitoh 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
   7453  1.281   msaitoh 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   7454  1.281   msaitoh 	} else {
   7455  1.281   msaitoh 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
   7456  1.281   msaitoh 	}
   7457  1.281   msaitoh 	vl_len |= (iphl << NQTXC_VLLEN_IPLEN_SHIFT);
   7458  1.281   msaitoh 	KASSERT((iphl & ~NQTXC_VLLEN_IPLEN_MASK) == 0);
   7459  1.281   msaitoh 
   7460  1.538  knakahar 	if (vlan_has_tag(m0)) {
   7461  1.538  knakahar 		vl_len |= ((vlan_get_tag(m0) & NQTXC_VLLEN_VLAN_MASK)
   7462  1.281   msaitoh 		     << NQTXC_VLLEN_VLAN_SHIFT);
   7463  1.281   msaitoh 		*cmdlenp |= NQTX_CMD_VLE;
   7464  1.281   msaitoh 	}
   7465  1.272     ozaki 
   7466  1.281   msaitoh 	mssidx = 0;
   7467  1.170   msaitoh 
   7468  1.281   msaitoh 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
   7469  1.281   msaitoh 		int hlen = offset + iphl;
   7470  1.281   msaitoh 		int tcp_hlen;
   7471  1.281   msaitoh 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   7472  1.192   msaitoh 
   7473  1.281   msaitoh 		if (__predict_false(m0->m_len <
   7474  1.281   msaitoh 				    (hlen + sizeof(struct tcphdr)))) {
   7475  1.192   msaitoh 			/*
   7476  1.281   msaitoh 			 * TCP/IP headers are not in the first mbuf; we need
   7477  1.281   msaitoh 			 * to do this the slow and painful way.  Let's just
   7478  1.281   msaitoh 			 * hope this doesn't happen very often.
   7479  1.192   msaitoh 			 */
   7480  1.281   msaitoh 			struct tcphdr th;
   7481  1.170   msaitoh 
   7482  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtsopain);
   7483  1.192   msaitoh 
   7484  1.281   msaitoh 			m_copydata(m0, hlen, sizeof(th), &th);
   7485  1.281   msaitoh 			if (v4) {
   7486  1.281   msaitoh 				struct ip ip;
   7487  1.192   msaitoh 
   7488  1.281   msaitoh 				m_copydata(m0, offset, sizeof(ip), &ip);
   7489  1.281   msaitoh 				ip.ip_len = 0;
   7490  1.281   msaitoh 				m_copyback(m0,
   7491  1.281   msaitoh 				    offset + offsetof(struct ip, ip_len),
   7492  1.281   msaitoh 				    sizeof(ip.ip_len), &ip.ip_len);
   7493  1.281   msaitoh 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   7494  1.281   msaitoh 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   7495  1.281   msaitoh 			} else {
   7496  1.281   msaitoh 				struct ip6_hdr ip6;
   7497  1.192   msaitoh 
   7498  1.281   msaitoh 				m_copydata(m0, offset, sizeof(ip6), &ip6);
   7499  1.281   msaitoh 				ip6.ip6_plen = 0;
   7500  1.281   msaitoh 				m_copyback(m0,
   7501  1.281   msaitoh 				    offset + offsetof(struct ip6_hdr, ip6_plen),
   7502  1.281   msaitoh 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
   7503  1.281   msaitoh 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
   7504  1.281   msaitoh 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
   7505  1.170   msaitoh 			}
   7506  1.281   msaitoh 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   7507  1.281   msaitoh 			    sizeof(th.th_sum), &th.th_sum);
   7508  1.192   msaitoh 
   7509  1.281   msaitoh 			tcp_hlen = th.th_off << 2;
   7510  1.281   msaitoh 		} else {
   7511  1.173   msaitoh 			/*
   7512  1.281   msaitoh 			 * TCP/IP headers are in the first mbuf; we can do
   7513  1.281   msaitoh 			 * this the easy way.
   7514  1.173   msaitoh 			 */
   7515  1.281   msaitoh 			struct tcphdr *th;
   7516  1.198   msaitoh 
   7517  1.281   msaitoh 			if (v4) {
   7518  1.281   msaitoh 				struct ip *ip =
   7519  1.281   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   7520  1.281   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   7521    1.1   thorpej 
   7522  1.281   msaitoh 				ip->ip_len = 0;
   7523  1.281   msaitoh 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   7524  1.281   msaitoh 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   7525  1.281   msaitoh 			} else {
   7526  1.281   msaitoh 				struct ip6_hdr *ip6 =
   7527  1.281   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   7528  1.281   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   7529  1.192   msaitoh 
   7530  1.281   msaitoh 				ip6->ip6_plen = 0;
   7531  1.281   msaitoh 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
   7532  1.281   msaitoh 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
   7533  1.281   msaitoh 			}
   7534  1.281   msaitoh 			tcp_hlen = th->th_off << 2;
   7535  1.144   msaitoh 		}
   7536  1.281   msaitoh 		hlen += tcp_hlen;
   7537  1.281   msaitoh 		*cmdlenp |= NQTX_CMD_TSE;
   7538  1.144   msaitoh 
   7539  1.281   msaitoh 		if (v4) {
   7540  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso);
   7541  1.281   msaitoh 			*fieldsp |= NQTXD_FIELDS_IXSM | NQTXD_FIELDS_TUXSM;
   7542  1.281   msaitoh 		} else {
   7543  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso6);
   7544  1.281   msaitoh 			*fieldsp |= NQTXD_FIELDS_TUXSM;
   7545  1.189   msaitoh 		}
   7546  1.281   msaitoh 		*fieldsp |= ((m0->m_pkthdr.len - hlen) << NQTXD_FIELDS_PAYLEN_SHIFT);
   7547  1.281   msaitoh 		KASSERT(((m0->m_pkthdr.len - hlen) & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
   7548  1.281   msaitoh 		mssidx |= (m0->m_pkthdr.segsz << NQTXC_MSSIDX_MSS_SHIFT);
   7549  1.281   msaitoh 		KASSERT((m0->m_pkthdr.segsz & ~NQTXC_MSSIDX_MSS_MASK) == 0);
   7550  1.281   msaitoh 		mssidx |= (tcp_hlen << NQTXC_MSSIDX_L4LEN_SHIFT);
   7551  1.281   msaitoh 		KASSERT((tcp_hlen & ~NQTXC_MSSIDX_L4LEN_MASK) == 0);
   7552  1.281   msaitoh 	} else {
   7553  1.281   msaitoh 		*fieldsp |= (m0->m_pkthdr.len << NQTXD_FIELDS_PAYLEN_SHIFT);
   7554  1.281   msaitoh 		KASSERT((m0->m_pkthdr.len & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
   7555  1.208   msaitoh 	}
   7556  1.208   msaitoh 
   7557  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
   7558  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_IXSM;
   7559  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP4;
   7560  1.281   msaitoh 	}
   7561  1.144   msaitoh 
   7562  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags &
   7563  1.281   msaitoh 	    (M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
   7564  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum);
   7565  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
   7566  1.281   msaitoh 			cmdc |= NQTXC_CMD_TCP;
   7567  1.281   msaitoh 		} else {
   7568  1.281   msaitoh 			cmdc |= NQTXC_CMD_UDP;
   7569  1.281   msaitoh 		}
   7570  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP4;
   7571  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_TUXSM;
   7572  1.281   msaitoh 	}
   7573  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags &
   7574  1.281   msaitoh 	    (M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
   7575  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum6);
   7576  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
   7577  1.281   msaitoh 			cmdc |= NQTXC_CMD_TCP;
   7578  1.281   msaitoh 		} else {
   7579  1.281   msaitoh 			cmdc |= NQTXC_CMD_UDP;
   7580  1.281   msaitoh 		}
   7581  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP6;
   7582  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_TUXSM;
   7583  1.281   msaitoh 	}
   7584    1.1   thorpej 
   7585  1.500  knakahar 	/*
   7586  1.500  knakahar 	 * We don't have to write context descriptor for every packet to
   7587  1.500  knakahar 	 * NEWQUEUE controllers, that is 82575, 82576, 82580, I350, I354,
   7588  1.500  knakahar 	 * I210 and I211. It is enough to write once per a Tx queue for these
   7589  1.500  knakahar 	 * controllers.
   7590  1.500  knakahar 	 * It would be overhead to write context descriptor for every packet,
   7591  1.500  knakahar 	 * however it does not cause problems.
   7592  1.500  knakahar 	 */
   7593  1.281   msaitoh 	/* Fill in the context descriptor. */
   7594  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_vl_len =
   7595  1.281   msaitoh 	    htole32(vl_len);
   7596  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_sn = 0;
   7597  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_cmd =
   7598  1.281   msaitoh 	    htole32(cmdc);
   7599  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_mssidx =
   7600  1.281   msaitoh 	    htole32(mssidx);
   7601  1.362  knakahar 	wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE);
   7602  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX,
   7603  1.281   msaitoh 	    ("%s: TX: context desc %d 0x%08x%08x\n", device_xname(sc->sc_dev),
   7604  1.366  knakahar 	    txq->txq_next, 0, vl_len));
   7605  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX, ("\t0x%08x%08x\n", mssidx, cmdc));
   7606  1.356  knakahar 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   7607  1.281   msaitoh 	txs->txs_ndesc++;
   7608  1.281   msaitoh 	return 0;
   7609  1.217    dyoung }
   7610  1.217    dyoung 
   7611    1.1   thorpej /*
   7612  1.281   msaitoh  * wm_nq_start:		[ifnet interface function]
   7613    1.1   thorpej  *
   7614  1.281   msaitoh  *	Start packet transmission on the interface for NEWQUEUE devices
   7615    1.1   thorpej  */
   7616  1.281   msaitoh static void
   7617  1.281   msaitoh wm_nq_start(struct ifnet *ifp)
   7618    1.1   thorpej {
   7619    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   7620  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7621  1.272     ozaki 
   7622  1.496  knakahar #ifdef WM_MPSAFE
   7623  1.543     ozaki 	KASSERT(if_is_mpsafe(ifp));
   7624  1.496  knakahar #endif
   7625  1.455  knakahar 	/*
   7626  1.455  knakahar 	 * ifp->if_obytes and ifp->if_omcasts are added in if_transmit()@if.c.
   7627  1.455  knakahar 	 */
   7628  1.455  knakahar 
   7629  1.413     skrll 	mutex_enter(txq->txq_lock);
   7630  1.429  knakahar 	if (!txq->txq_stopping)
   7631  1.281   msaitoh 		wm_nq_start_locked(ifp);
   7632  1.413     skrll 	mutex_exit(txq->txq_lock);
   7633  1.272     ozaki }
   7634  1.272     ozaki 
   7635  1.281   msaitoh static void
   7636  1.281   msaitoh wm_nq_start_locked(struct ifnet *ifp)
   7637  1.272     ozaki {
   7638  1.272     ozaki 	struct wm_softc *sc = ifp->if_softc;
   7639  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7640  1.403  knakahar 
   7641  1.403  knakahar 	wm_nq_send_common_locked(ifp, txq, false);
   7642  1.403  knakahar }
   7643  1.403  knakahar 
   7644  1.403  knakahar static int
   7645  1.403  knakahar wm_nq_transmit(struct ifnet *ifp, struct mbuf *m)
   7646  1.403  knakahar {
   7647  1.403  knakahar 	int qid;
   7648  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7649  1.403  knakahar 	struct wm_txqueue *txq;
   7650  1.403  knakahar 
   7651  1.454  knakahar 	qid = wm_select_txqueue(ifp, m);
   7652  1.405  knakahar 	txq = &sc->sc_queue[qid].wmq_txq;
   7653  1.403  knakahar 
   7654  1.403  knakahar 	if (__predict_false(!pcq_put(txq->txq_interq, m))) {
   7655  1.403  knakahar 		m_freem(m);
   7656  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7657  1.403  knakahar 		return ENOBUFS;
   7658  1.403  knakahar 	}
   7659  1.403  knakahar 
   7660  1.455  knakahar 	/*
   7661  1.455  knakahar 	 * XXXX NOMPSAFE: ifp->if_data should be percpu.
   7662  1.455  knakahar 	 */
   7663  1.455  knakahar 	ifp->if_obytes += m->m_pkthdr.len;
   7664  1.455  knakahar 	if (m->m_flags & M_MCAST)
   7665  1.455  knakahar 		ifp->if_omcasts++;
   7666  1.455  knakahar 
   7667  1.470  knakahar 	/*
   7668  1.470  knakahar 	 * The situations which this mutex_tryenter() fails at running time
   7669  1.470  knakahar 	 * are below two patterns.
   7670  1.470  knakahar 	 *     (1) contention with interrupt handler(wm_txrxintr_msix())
   7671  1.484  knakahar 	 *     (2) contention with deferred if_start softint(wm_handle_queue())
   7672  1.470  knakahar 	 * In the case of (1), the last packet enqueued to txq->txq_interq is
   7673  1.484  knakahar 	 * dequeued by wm_deferred_start_locked(). So, it does not get stuck.
   7674  1.470  knakahar 	 * In the case of (2), the last packet enqueued to txq->txq_interq is also
   7675  1.484  knakahar 	 * dequeued by wm_deferred_start_locked(). So, it does not get stuck, either.
   7676  1.470  knakahar 	 */
   7677  1.413     skrll 	if (mutex_tryenter(txq->txq_lock)) {
   7678  1.429  knakahar 		if (!txq->txq_stopping)
   7679  1.403  knakahar 			wm_nq_transmit_locked(ifp, txq);
   7680  1.413     skrll 		mutex_exit(txq->txq_lock);
   7681  1.403  knakahar 	}
   7682  1.403  knakahar 
   7683  1.403  knakahar 	return 0;
   7684  1.403  knakahar }
   7685  1.403  knakahar 
   7686  1.403  knakahar static void
   7687  1.403  knakahar wm_nq_transmit_locked(struct ifnet *ifp, struct wm_txqueue *txq)
   7688  1.403  knakahar {
   7689  1.403  knakahar 
   7690  1.403  knakahar 	wm_nq_send_common_locked(ifp, txq, true);
   7691  1.403  knakahar }
   7692  1.403  knakahar 
   7693  1.403  knakahar static void
   7694  1.403  knakahar wm_nq_send_common_locked(struct ifnet *ifp, struct wm_txqueue *txq,
   7695  1.403  knakahar     bool is_transmit)
   7696  1.403  knakahar {
   7697  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7698  1.281   msaitoh 	struct mbuf *m0;
   7699  1.281   msaitoh 	struct wm_txsoft *txs;
   7700  1.281   msaitoh 	bus_dmamap_t dmamap;
   7701  1.281   msaitoh 	int error, nexttx, lasttx = -1, seg, segs_needed;
   7702  1.281   msaitoh 	bool do_csum, sent;
   7703    1.1   thorpej 
   7704  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   7705   1.41       tls 
   7706  1.482  knakahar 	if ((ifp->if_flags & IFF_RUNNING) == 0)
   7707  1.482  knakahar 		return;
   7708  1.482  knakahar 	if ((ifp->if_flags & IFF_OACTIVE) != 0 && !is_transmit)
   7709  1.281   msaitoh 		return;
   7710  1.401  knakahar 	if ((txq->txq_flags & WM_TXQ_NO_SPACE) != 0)
   7711  1.400  knakahar 		return;
   7712    1.1   thorpej 
   7713  1.281   msaitoh 	sent = false;
   7714    1.1   thorpej 
   7715    1.1   thorpej 	/*
   7716  1.281   msaitoh 	 * Loop through the send queue, setting up transmit descriptors
   7717  1.281   msaitoh 	 * until we drain the queue, or use up all available transmit
   7718  1.281   msaitoh 	 * descriptors.
   7719    1.1   thorpej 	 */
   7720  1.281   msaitoh 	for (;;) {
   7721  1.281   msaitoh 		m0 = NULL;
   7722  1.281   msaitoh 
   7723  1.281   msaitoh 		/* Get a work queue entry. */
   7724  1.356  knakahar 		if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) {
   7725  1.403  knakahar 			wm_txeof(sc, txq);
   7726  1.356  knakahar 			if (txq->txq_sfree == 0) {
   7727  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   7728  1.281   msaitoh 				    ("%s: TX: no free job descriptors\n",
   7729  1.281   msaitoh 					device_xname(sc->sc_dev)));
   7730  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txsstall);
   7731  1.281   msaitoh 				break;
   7732  1.281   msaitoh 			}
   7733  1.281   msaitoh 		}
   7734    1.1   thorpej 
   7735  1.281   msaitoh 		/* Grab a packet off the queue. */
   7736  1.403  knakahar 		if (is_transmit)
   7737  1.403  knakahar 			m0 = pcq_get(txq->txq_interq);
   7738  1.403  knakahar 		else
   7739  1.403  knakahar 			IFQ_DEQUEUE(&ifp->if_snd, m0);
   7740  1.281   msaitoh 		if (m0 == NULL)
   7741  1.281   msaitoh 			break;
   7742   1.71   thorpej 
   7743  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7744  1.281   msaitoh 		    ("%s: TX: have packet to transmit: %p\n",
   7745  1.281   msaitoh 		    device_xname(sc->sc_dev), m0));
   7746  1.177   msaitoh 
   7747  1.356  knakahar 		txs = &txq->txq_soft[txq->txq_snext];
   7748  1.281   msaitoh 		dmamap = txs->txs_dmamap;
   7749    1.1   thorpej 
   7750  1.281   msaitoh 		/*
   7751  1.281   msaitoh 		 * Load the DMA map.  If this fails, the packet either
   7752  1.281   msaitoh 		 * didn't fit in the allotted number of segments, or we
   7753  1.281   msaitoh 		 * were short on resources.  For the too-many-segments
   7754  1.281   msaitoh 		 * case, we simply report an error and drop the packet,
   7755  1.281   msaitoh 		 * since we can't sanely copy a jumbo packet to a single
   7756  1.281   msaitoh 		 * buffer.
   7757  1.281   msaitoh 		 */
   7758  1.281   msaitoh 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   7759  1.388   msaitoh 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
   7760  1.281   msaitoh 		if (error) {
   7761  1.281   msaitoh 			if (error == EFBIG) {
   7762  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txdrop);
   7763  1.281   msaitoh 				log(LOG_ERR, "%s: Tx packet consumes too many "
   7764  1.281   msaitoh 				    "DMA segments, dropping...\n",
   7765  1.281   msaitoh 				    device_xname(sc->sc_dev));
   7766  1.281   msaitoh 				wm_dump_mbuf_chain(sc, m0);
   7767  1.281   msaitoh 				m_freem(m0);
   7768  1.281   msaitoh 				continue;
   7769  1.281   msaitoh 			}
   7770  1.281   msaitoh 			/* Short on resources, just stop for now. */
   7771  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7772  1.281   msaitoh 			    ("%s: TX: dmamap load failed: %d\n",
   7773  1.281   msaitoh 			    device_xname(sc->sc_dev), error));
   7774  1.281   msaitoh 			break;
   7775  1.281   msaitoh 		}
   7776  1.177   msaitoh 
   7777  1.281   msaitoh 		segs_needed = dmamap->dm_nsegs;
   7778  1.177   msaitoh 
   7779  1.281   msaitoh 		/*
   7780  1.281   msaitoh 		 * Ensure we have enough descriptors free to describe
   7781  1.281   msaitoh 		 * the packet.  Note, we always reserve one descriptor
   7782  1.281   msaitoh 		 * at the end of the ring due to the semantics of the
   7783  1.281   msaitoh 		 * TDT register, plus one more in the event we need
   7784  1.281   msaitoh 		 * to load offload context.
   7785  1.281   msaitoh 		 */
   7786  1.356  knakahar 		if (segs_needed > txq->txq_free - 2) {
   7787  1.177   msaitoh 			/*
   7788  1.281   msaitoh 			 * Not enough free descriptors to transmit this
   7789  1.281   msaitoh 			 * packet.  We haven't committed anything yet,
   7790  1.281   msaitoh 			 * so just unload the DMA map, put the packet
   7791  1.281   msaitoh 			 * pack on the queue, and punt.  Notify the upper
   7792  1.281   msaitoh 			 * layer that there are no more slots left.
   7793  1.177   msaitoh 			 */
   7794  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7795  1.281   msaitoh 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
   7796  1.281   msaitoh 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
   7797  1.366  knakahar 			    segs_needed, txq->txq_free - 1));
   7798  1.482  knakahar 			if (!is_transmit)
   7799  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   7800  1.401  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   7801  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   7802  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdstall);
   7803  1.177   msaitoh 			break;
   7804  1.177   msaitoh 		}
   7805  1.177   msaitoh 
   7806  1.281   msaitoh 		/* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
   7807  1.281   msaitoh 
   7808  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7809  1.281   msaitoh 		    ("%s: TX: packet has %d (%d) DMA segments\n",
   7810  1.281   msaitoh 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
   7811  1.177   msaitoh 
   7812  1.417  knakahar 		WM_EVCNT_INCR(&txq->txq_ev_txseg[dmamap->dm_nsegs - 1]);
   7813    1.1   thorpej 
   7814  1.281   msaitoh 		/*
   7815  1.281   msaitoh 		 * Store a pointer to the packet so that we can free it
   7816  1.281   msaitoh 		 * later.
   7817  1.281   msaitoh 		 *
   7818  1.281   msaitoh 		 * Initially, we consider the number of descriptors the
   7819  1.281   msaitoh 		 * packet uses the number of DMA segments.  This may be
   7820  1.281   msaitoh 		 * incremented by 1 if we do checksum offload (a descriptor
   7821  1.281   msaitoh 		 * is used to set the checksum context).
   7822  1.281   msaitoh 		 */
   7823  1.281   msaitoh 		txs->txs_mbuf = m0;
   7824  1.356  knakahar 		txs->txs_firstdesc = txq->txq_next;
   7825  1.281   msaitoh 		txs->txs_ndesc = segs_needed;
   7826    1.1   thorpej 
   7827  1.281   msaitoh 		/* Set up offload parameters for this packet. */
   7828  1.281   msaitoh 		uint32_t cmdlen, fields, dcmdlen;
   7829  1.388   msaitoh 		if (m0->m_pkthdr.csum_flags &
   7830  1.388   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6 |
   7831  1.388   msaitoh 			M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   7832  1.388   msaitoh 			M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
   7833  1.403  knakahar 			if (wm_nq_tx_offload(sc, txq, txs, &cmdlen, &fields,
   7834  1.281   msaitoh 			    &do_csum) != 0) {
   7835  1.281   msaitoh 				/* Error message already displayed. */
   7836  1.281   msaitoh 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   7837  1.281   msaitoh 				continue;
   7838  1.281   msaitoh 			}
   7839  1.281   msaitoh 		} else {
   7840  1.281   msaitoh 			do_csum = false;
   7841  1.281   msaitoh 			cmdlen = 0;
   7842  1.281   msaitoh 			fields = 0;
   7843  1.281   msaitoh 		}
   7844  1.173   msaitoh 
   7845  1.281   msaitoh 		/* Sync the DMA map. */
   7846  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   7847  1.281   msaitoh 		    BUS_DMASYNC_PREWRITE);
   7848    1.1   thorpej 
   7849  1.281   msaitoh 		/* Initialize the first transmit descriptor. */
   7850  1.356  knakahar 		nexttx = txq->txq_next;
   7851  1.281   msaitoh 		if (!do_csum) {
   7852  1.281   msaitoh 			/* setup a legacy descriptor */
   7853  1.388   msaitoh 			wm_set_dma_addr(&txq->txq_descs[nexttx].wtx_addr,
   7854  1.281   msaitoh 			    dmamap->dm_segs[0].ds_addr);
   7855  1.356  knakahar 			txq->txq_descs[nexttx].wtx_cmdlen =
   7856  1.281   msaitoh 			    htole32(WTX_CMD_IFCS | dmamap->dm_segs[0].ds_len);
   7857  1.356  knakahar 			txq->txq_descs[nexttx].wtx_fields.wtxu_status = 0;
   7858  1.356  knakahar 			txq->txq_descs[nexttx].wtx_fields.wtxu_options = 0;
   7859  1.538  knakahar 			if (vlan_has_tag(m0)) {
   7860  1.356  knakahar 				txq->txq_descs[nexttx].wtx_cmdlen |=
   7861  1.281   msaitoh 				    htole32(WTX_CMD_VLE);
   7862  1.356  knakahar 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =
   7863  1.538  knakahar 				    htole16(vlan_get_tag(m0));
   7864  1.281   msaitoh 			} else {
   7865  1.356  knakahar 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
   7866  1.281   msaitoh 			}
   7867  1.281   msaitoh 			dcmdlen = 0;
   7868  1.281   msaitoh 		} else {
   7869  1.281   msaitoh 			/* setup an advanced data descriptor */
   7870  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr =
   7871  1.281   msaitoh 			    htole64(dmamap->dm_segs[0].ds_addr);
   7872  1.281   msaitoh 			KASSERT((dmamap->dm_segs[0].ds_len & cmdlen) == 0);
   7873  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen =
   7874  1.281   msaitoh 			    htole32(dmamap->dm_segs[0].ds_len | cmdlen );
   7875  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields =
   7876  1.281   msaitoh 			    htole32(fields);
   7877  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7878  1.281   msaitoh 			    ("%s: TX: adv data desc %d 0x%" PRIx64 "\n",
   7879  1.281   msaitoh 			    device_xname(sc->sc_dev), nexttx,
   7880  1.281   msaitoh 			    (uint64_t)dmamap->dm_segs[0].ds_addr));
   7881  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7882  1.281   msaitoh 			    ("\t 0x%08x%08x\n", fields,
   7883  1.281   msaitoh 			    (uint32_t)dmamap->dm_segs[0].ds_len | cmdlen));
   7884  1.281   msaitoh 			dcmdlen = NQTX_DTYP_D | NQTX_CMD_DEXT;
   7885  1.281   msaitoh 		}
   7886  1.177   msaitoh 
   7887  1.281   msaitoh 		lasttx = nexttx;
   7888  1.356  knakahar 		nexttx = WM_NEXTTX(txq, nexttx);
   7889  1.150       tls 		/*
   7890  1.551   jnemeth 		 * fill in the next descriptors. legacy or advanced format
   7891  1.281   msaitoh 		 * is the same here
   7892  1.150       tls 		 */
   7893  1.281   msaitoh 		for (seg = 1; seg < dmamap->dm_nsegs;
   7894  1.356  knakahar 		    seg++, nexttx = WM_NEXTTX(txq, nexttx)) {
   7895  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr =
   7896  1.281   msaitoh 			    htole64(dmamap->dm_segs[seg].ds_addr);
   7897  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen =
   7898  1.281   msaitoh 			    htole32(dcmdlen | dmamap->dm_segs[seg].ds_len);
   7899  1.281   msaitoh 			KASSERT((dcmdlen & dmamap->dm_segs[seg].ds_len) == 0);
   7900  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields = 0;
   7901  1.281   msaitoh 			lasttx = nexttx;
   7902  1.153       tls 
   7903  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7904  1.281   msaitoh 			    ("%s: TX: desc %d: %#" PRIx64 ", "
   7905  1.281   msaitoh 			     "len %#04zx\n",
   7906  1.281   msaitoh 			    device_xname(sc->sc_dev), nexttx,
   7907  1.281   msaitoh 			    (uint64_t)dmamap->dm_segs[seg].ds_addr,
   7908  1.281   msaitoh 			    dmamap->dm_segs[seg].ds_len));
   7909  1.281   msaitoh 		}
   7910  1.153       tls 
   7911  1.281   msaitoh 		KASSERT(lasttx != -1);
   7912    1.1   thorpej 
   7913  1.211   msaitoh 		/*
   7914  1.281   msaitoh 		 * Set up the command byte on the last descriptor of
   7915  1.281   msaitoh 		 * the packet.  If we're in the interrupt delay window,
   7916  1.281   msaitoh 		 * delay the interrupt.
   7917  1.211   msaitoh 		 */
   7918  1.281   msaitoh 		KASSERT((WTX_CMD_EOP | WTX_CMD_RS) ==
   7919  1.281   msaitoh 		    (NQTX_CMD_EOP | NQTX_CMD_RS));
   7920  1.356  knakahar 		txq->txq_descs[lasttx].wtx_cmdlen |=
   7921  1.281   msaitoh 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
   7922  1.211   msaitoh 
   7923  1.281   msaitoh 		txs->txs_lastdesc = lasttx;
   7924  1.177   msaitoh 
   7925  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: desc %d: cmdlen 0x%08x\n",
   7926  1.281   msaitoh 		    device_xname(sc->sc_dev),
   7927  1.366  knakahar 		    lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
   7928    1.1   thorpej 
   7929  1.281   msaitoh 		/* Sync the descriptors we're using. */
   7930  1.362  knakahar 		wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc,
   7931  1.388   msaitoh 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   7932  1.203   msaitoh 
   7933  1.281   msaitoh 		/* Give the packet to the chip. */
   7934  1.356  knakahar 		CSR_WRITE(sc, txq->txq_tdt_reg, nexttx);
   7935  1.281   msaitoh 		sent = true;
   7936  1.120   msaitoh 
   7937  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7938  1.281   msaitoh 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
   7939  1.228   msaitoh 
   7940  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7941  1.281   msaitoh 		    ("%s: TX: finished transmitting packet, job %d\n",
   7942  1.366  knakahar 		    device_xname(sc->sc_dev), txq->txq_snext));
   7943   1.41       tls 
   7944  1.281   msaitoh 		/* Advance the tx pointer. */
   7945  1.356  knakahar 		txq->txq_free -= txs->txs_ndesc;
   7946  1.356  knakahar 		txq->txq_next = nexttx;
   7947    1.1   thorpej 
   7948  1.356  knakahar 		txq->txq_sfree--;
   7949  1.356  knakahar 		txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext);
   7950    1.1   thorpej 
   7951  1.281   msaitoh 		/* Pass the packet to any BPF listeners. */
   7952  1.281   msaitoh 		bpf_mtap(ifp, m0);
   7953  1.281   msaitoh 	}
   7954  1.257   msaitoh 
   7955  1.281   msaitoh 	if (m0 != NULL) {
   7956  1.482  knakahar 		if (!is_transmit)
   7957  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7958  1.401  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7959  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7960  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n",
   7961  1.388   msaitoh 			__func__));
   7962  1.281   msaitoh 		m_freem(m0);
   7963  1.257   msaitoh 	}
   7964  1.257   msaitoh 
   7965  1.356  knakahar 	if (txq->txq_sfree == 0 || txq->txq_free <= 2) {
   7966  1.281   msaitoh 		/* No more slots; notify upper layer. */
   7967  1.482  knakahar 		if (!is_transmit)
   7968  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7969  1.401  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7970  1.281   msaitoh 	}
   7971  1.199   msaitoh 
   7972  1.281   msaitoh 	if (sent) {
   7973  1.281   msaitoh 		/* Set a watchdog timer in case the chip flakes out. */
   7974  1.549     ozaki 		ifp->if_timer = 5;
   7975  1.281   msaitoh 	}
   7976  1.281   msaitoh }
   7977  1.272     ozaki 
   7978  1.456     ozaki static void
   7979  1.481  knakahar wm_deferred_start_locked(struct wm_txqueue *txq)
   7980  1.481  knakahar {
   7981  1.481  knakahar 	struct wm_softc *sc = txq->txq_sc;
   7982  1.481  knakahar 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   7983  1.481  knakahar 	struct wm_queue *wmq = container_of(txq, struct wm_queue, wmq_txq);
   7984  1.481  knakahar 	int qid = wmq->wmq_id;
   7985  1.481  knakahar 
   7986  1.481  knakahar 	KASSERT(mutex_owned(txq->txq_lock));
   7987  1.456     ozaki 
   7988  1.481  knakahar 	if (txq->txq_stopping) {
   7989  1.456     ozaki 		mutex_exit(txq->txq_lock);
   7990  1.481  knakahar 		return;
   7991  1.481  knakahar 	}
   7992  1.481  knakahar 
   7993  1.481  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   7994  1.503  knakahar 		/* XXX need for ALTQ or one CPU system */
   7995  1.481  knakahar 		if (qid == 0)
   7996  1.481  knakahar 			wm_nq_start_locked(ifp);
   7997  1.481  knakahar 		wm_nq_transmit_locked(ifp, txq);
   7998  1.481  knakahar 	} else {
   7999  1.503  knakahar 		/* XXX need for ALTQ or one CPU system */
   8000  1.481  knakahar 		if (qid == 0)
   8001  1.481  knakahar 			wm_start_locked(ifp);
   8002  1.481  knakahar 		wm_transmit_locked(ifp, txq);
   8003  1.456     ozaki 	}
   8004  1.456     ozaki }
   8005  1.456     ozaki 
   8006  1.281   msaitoh /* Interrupt */
   8007    1.1   thorpej 
   8008    1.1   thorpej /*
   8009  1.335   msaitoh  * wm_txeof:
   8010    1.1   thorpej  *
   8011  1.281   msaitoh  *	Helper; handle transmit interrupts.
   8012    1.1   thorpej  */
   8013  1.335   msaitoh static int
   8014  1.403  knakahar wm_txeof(struct wm_softc *sc, struct wm_txqueue *txq)
   8015    1.1   thorpej {
   8016  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8017  1.281   msaitoh 	struct wm_txsoft *txs;
   8018  1.335   msaitoh 	bool processed = false;
   8019  1.335   msaitoh 	int count = 0;
   8020  1.335   msaitoh 	int i;
   8021  1.281   msaitoh 	uint8_t status;
   8022  1.479  knakahar 	struct wm_queue *wmq = container_of(txq, struct wm_queue, wmq_txq);
   8023    1.1   thorpej 
   8024  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   8025  1.405  knakahar 
   8026  1.429  knakahar 	if (txq->txq_stopping)
   8027  1.335   msaitoh 		return 0;
   8028  1.281   msaitoh 
   8029  1.479  knakahar 	txq->txq_flags &= ~WM_TXQ_NO_SPACE;
   8030  1.479  knakahar 	/* for ALTQ and legacy(not use multiqueue) ethernet controller */
   8031  1.479  knakahar 	if (wmq->wmq_id == 0)
   8032  1.411  knakahar 		ifp->if_flags &= ~IFF_OACTIVE;
   8033  1.272     ozaki 
   8034  1.281   msaitoh 	/*
   8035  1.281   msaitoh 	 * Go through the Tx list and free mbufs for those
   8036  1.281   msaitoh 	 * frames which have been transmitted.
   8037  1.281   msaitoh 	 */
   8038  1.356  knakahar 	for (i = txq->txq_sdirty; txq->txq_sfree != WM_TXQUEUELEN(txq);
   8039  1.356  knakahar 	     i = WM_NEXTTXS(txq, i), txq->txq_sfree++) {
   8040  1.356  knakahar 		txs = &txq->txq_soft[i];
   8041    1.1   thorpej 
   8042  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: checking job %d\n",
   8043  1.388   msaitoh 			device_xname(sc->sc_dev), i));
   8044  1.272     ozaki 
   8045  1.362  knakahar 		wm_cdtxsync(txq, txs->txs_firstdesc, txs->txs_ndesc,
   8046  1.388   msaitoh 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
   8047  1.272     ozaki 
   8048  1.281   msaitoh 		status =
   8049  1.356  knakahar 		    txq->txq_descs[txs->txs_lastdesc].wtx_fields.wtxu_status;
   8050  1.281   msaitoh 		if ((status & WTX_ST_DD) == 0) {
   8051  1.362  knakahar 			wm_cdtxsync(txq, txs->txs_lastdesc, 1,
   8052  1.281   msaitoh 			    BUS_DMASYNC_PREREAD);
   8053  1.281   msaitoh 			break;
   8054  1.281   msaitoh 		}
   8055    1.1   thorpej 
   8056  1.335   msaitoh 		processed = true;
   8057  1.335   msaitoh 		count++;
   8058  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   8059  1.281   msaitoh 		    ("%s: TX: job %d done: descs %d..%d\n",
   8060  1.281   msaitoh 		    device_xname(sc->sc_dev), i, txs->txs_firstdesc,
   8061  1.281   msaitoh 		    txs->txs_lastdesc));
   8062  1.272     ozaki 
   8063  1.281   msaitoh 		/*
   8064  1.281   msaitoh 		 * XXX We should probably be using the statistics
   8065  1.281   msaitoh 		 * XXX registers, but I don't know if they exist
   8066  1.281   msaitoh 		 * XXX on chips before the i82544.
   8067  1.281   msaitoh 		 */
   8068  1.272     ozaki 
   8069  1.281   msaitoh #ifdef WM_EVENT_COUNTERS
   8070  1.281   msaitoh 		if (status & WTX_ST_TU)
   8071  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, tu);
   8072  1.281   msaitoh #endif /* WM_EVENT_COUNTERS */
   8073    1.1   thorpej 
   8074  1.388   msaitoh 		if (status & (WTX_ST_EC | WTX_ST_LC)) {
   8075  1.281   msaitoh 			ifp->if_oerrors++;
   8076  1.281   msaitoh 			if (status & WTX_ST_LC)
   8077  1.281   msaitoh 				log(LOG_WARNING, "%s: late collision\n",
   8078  1.281   msaitoh 				    device_xname(sc->sc_dev));
   8079  1.281   msaitoh 			else if (status & WTX_ST_EC) {
   8080  1.281   msaitoh 				ifp->if_collisions += 16;
   8081  1.281   msaitoh 				log(LOG_WARNING, "%s: excessive collisions\n",
   8082  1.281   msaitoh 				    device_xname(sc->sc_dev));
   8083  1.281   msaitoh 			}
   8084  1.281   msaitoh 		} else
   8085  1.281   msaitoh 			ifp->if_opackets++;
   8086   1.78   thorpej 
   8087  1.495  knakahar 		txq->txq_packets++;
   8088  1.495  knakahar 		txq->txq_bytes += txs->txs_mbuf->m_pkthdr.len;
   8089  1.495  knakahar 
   8090  1.356  knakahar 		txq->txq_free += txs->txs_ndesc;
   8091  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
   8092  1.281   msaitoh 		    0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   8093  1.281   msaitoh 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   8094  1.281   msaitoh 		m_freem(txs->txs_mbuf);
   8095  1.281   msaitoh 		txs->txs_mbuf = NULL;
   8096    1.1   thorpej 	}
   8097    1.1   thorpej 
   8098  1.281   msaitoh 	/* Update the dirty transmit buffer pointer. */
   8099  1.356  knakahar 	txq->txq_sdirty = i;
   8100  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX,
   8101  1.281   msaitoh 	    ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i));
   8102    1.1   thorpej 
   8103  1.335   msaitoh 	if (count != 0)
   8104  1.335   msaitoh 		rnd_add_uint32(&sc->rnd_source, count);
   8105  1.335   msaitoh 
   8106  1.102       scw 	/*
   8107  1.281   msaitoh 	 * If there are no more pending transmissions, cancel the watchdog
   8108  1.281   msaitoh 	 * timer.
   8109  1.102       scw 	 */
   8110  1.356  knakahar 	if (txq->txq_sfree == WM_TXQUEUELEN(txq))
   8111  1.549     ozaki 		ifp->if_timer = 0;
   8112  1.335   msaitoh 
   8113  1.335   msaitoh 	return processed;
   8114  1.281   msaitoh }
   8115  1.102       scw 
   8116  1.466  knakahar static inline uint32_t
   8117  1.466  knakahar wm_rxdesc_get_status(struct wm_rxqueue *rxq, int idx)
   8118  1.466  knakahar {
   8119  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8120  1.466  knakahar 
   8121  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8122  1.466  knakahar 		return EXTRXC_STATUS(rxq->rxq_ext_descs[idx].erx_ctx.erxc_err_stat);
   8123  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8124  1.466  knakahar 		return NQRXC_STATUS(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_err_stat);
   8125  1.466  knakahar 	else
   8126  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_status;
   8127  1.466  knakahar }
   8128  1.466  knakahar 
   8129  1.466  knakahar static inline uint32_t
   8130  1.466  knakahar wm_rxdesc_get_errors(struct wm_rxqueue *rxq, int idx)
   8131  1.466  knakahar {
   8132  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8133  1.466  knakahar 
   8134  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8135  1.466  knakahar 		return EXTRXC_ERROR(rxq->rxq_ext_descs[idx].erx_ctx.erxc_err_stat);
   8136  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8137  1.466  knakahar 		return NQRXC_ERROR(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_err_stat);
   8138  1.466  knakahar 	else
   8139  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_errors;
   8140  1.466  knakahar }
   8141  1.466  knakahar 
   8142  1.466  knakahar static inline uint16_t
   8143  1.466  knakahar wm_rxdesc_get_vlantag(struct wm_rxqueue *rxq, int idx)
   8144  1.466  knakahar {
   8145  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8146  1.466  knakahar 
   8147  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8148  1.544   msaitoh 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_vlan;
   8149  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8150  1.544   msaitoh 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_vlan;
   8151  1.466  knakahar 	else
   8152  1.544   msaitoh 		return rxq->rxq_descs[idx].wrx_special;
   8153  1.466  knakahar }
   8154  1.466  knakahar 
   8155  1.466  knakahar static inline int
   8156  1.466  knakahar wm_rxdesc_get_pktlen(struct wm_rxqueue *rxq, int idx)
   8157  1.466  knakahar {
   8158  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8159  1.466  knakahar 
   8160  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8161  1.466  knakahar 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_pktlen;
   8162  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8163  1.466  knakahar 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_pktlen;
   8164  1.466  knakahar 	else
   8165  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_len;
   8166  1.466  knakahar }
   8167  1.466  knakahar 
   8168  1.466  knakahar #ifdef WM_DEBUG
   8169  1.466  knakahar static inline uint32_t
   8170  1.466  knakahar wm_rxdesc_get_rsshash(struct wm_rxqueue *rxq, int idx)
   8171  1.466  knakahar {
   8172  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8173  1.466  knakahar 
   8174  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8175  1.466  knakahar 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_rsshash;
   8176  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8177  1.466  knakahar 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_rsshash;
   8178  1.466  knakahar 	else
   8179  1.466  knakahar 		return 0;
   8180  1.466  knakahar }
   8181  1.466  knakahar 
   8182  1.466  knakahar static inline uint8_t
   8183  1.466  knakahar wm_rxdesc_get_rsstype(struct wm_rxqueue *rxq, int idx)
   8184  1.466  knakahar {
   8185  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8186  1.466  knakahar 
   8187  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8188  1.466  knakahar 		return EXTRXC_RSS_TYPE(rxq->rxq_ext_descs[idx].erx_ctx.erxc_mrq);
   8189  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8190  1.466  knakahar 		return NQRXC_RSS_TYPE(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_misc);
   8191  1.466  knakahar 	else
   8192  1.466  knakahar 		return 0;
   8193  1.466  knakahar }
   8194  1.466  knakahar #endif /* WM_DEBUG */
   8195  1.466  knakahar 
   8196  1.466  knakahar static inline bool
   8197  1.466  knakahar wm_rxdesc_is_set_status(struct wm_softc *sc, uint32_t status,
   8198  1.466  knakahar     uint32_t legacy_bit, uint32_t ext_bit, uint32_t nq_bit)
   8199  1.466  knakahar {
   8200  1.466  knakahar 
   8201  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8202  1.466  knakahar 		return (status & ext_bit) != 0;
   8203  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8204  1.466  knakahar 		return (status & nq_bit) != 0;
   8205  1.466  knakahar 	else
   8206  1.466  knakahar 		return (status & legacy_bit) != 0;
   8207  1.466  knakahar }
   8208  1.466  knakahar 
   8209  1.466  knakahar static inline bool
   8210  1.466  knakahar wm_rxdesc_is_set_error(struct wm_softc *sc, uint32_t error,
   8211  1.466  knakahar     uint32_t legacy_bit, uint32_t ext_bit, uint32_t nq_bit)
   8212  1.466  knakahar {
   8213  1.466  knakahar 
   8214  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8215  1.466  knakahar 		return (error & ext_bit) != 0;
   8216  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8217  1.466  knakahar 		return (error & nq_bit) != 0;
   8218  1.466  knakahar 	else
   8219  1.466  knakahar 		return (error & legacy_bit) != 0;
   8220  1.466  knakahar }
   8221  1.466  knakahar 
   8222  1.466  knakahar static inline bool
   8223  1.466  knakahar wm_rxdesc_is_eop(struct wm_rxqueue *rxq, uint32_t status)
   8224  1.466  knakahar {
   8225  1.466  knakahar 
   8226  1.466  knakahar 	if (wm_rxdesc_is_set_status(rxq->rxq_sc, status,
   8227  1.466  knakahar 		WRX_ST_EOP, EXTRXC_STATUS_EOP, NQRXC_STATUS_EOP))
   8228  1.466  knakahar 		return true;
   8229  1.466  knakahar 	else
   8230  1.466  knakahar 		return false;
   8231  1.466  knakahar }
   8232  1.466  knakahar 
   8233  1.466  knakahar static inline bool
   8234  1.466  knakahar wm_rxdesc_has_errors(struct wm_rxqueue *rxq, uint32_t errors)
   8235  1.466  knakahar {
   8236  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8237  1.466  knakahar 
   8238  1.466  knakahar 	/* XXXX missing error bit for newqueue? */
   8239  1.466  knakahar 	if (wm_rxdesc_is_set_error(sc, errors,
   8240  1.466  knakahar 		WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE,
   8241  1.466  knakahar 		EXTRXC_ERROR_CE|EXTRXC_ERROR_SE|EXTRXC_ERROR_SEQ|EXTRXC_ERROR_CXE|EXTRXC_ERROR_RXE,
   8242  1.466  knakahar 		NQRXC_ERROR_RXE)) {
   8243  1.466  knakahar 		if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_SE, EXTRXC_ERROR_SE, 0))
   8244  1.466  knakahar 			log(LOG_WARNING, "%s: symbol error\n",
   8245  1.466  knakahar 			    device_xname(sc->sc_dev));
   8246  1.466  knakahar 		else if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_SEQ, EXTRXC_ERROR_SEQ, 0))
   8247  1.466  knakahar 			log(LOG_WARNING, "%s: receive sequence error\n",
   8248  1.466  knakahar 			    device_xname(sc->sc_dev));
   8249  1.466  knakahar 		else if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_CE, EXTRXC_ERROR_CE, 0))
   8250  1.466  knakahar 			log(LOG_WARNING, "%s: CRC error\n",
   8251  1.466  knakahar 			    device_xname(sc->sc_dev));
   8252  1.466  knakahar 		return true;
   8253  1.466  knakahar 	}
   8254  1.466  knakahar 
   8255  1.466  knakahar 	return false;
   8256  1.466  knakahar }
   8257  1.466  knakahar 
   8258  1.466  knakahar static inline bool
   8259  1.466  knakahar wm_rxdesc_dd(struct wm_rxqueue *rxq, int idx, uint32_t status)
   8260  1.466  knakahar {
   8261  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8262  1.466  knakahar 
   8263  1.466  knakahar 	if (!wm_rxdesc_is_set_status(sc, status, WRX_ST_DD, EXTRXC_STATUS_DD,
   8264  1.466  knakahar 		NQRXC_STATUS_DD)) {
   8265  1.466  knakahar 		/* We have processed all of the receive descriptors. */
   8266  1.466  knakahar 		wm_cdrxsync(rxq, idx, BUS_DMASYNC_PREREAD);
   8267  1.466  knakahar 		return false;
   8268  1.466  knakahar 	}
   8269  1.466  knakahar 
   8270  1.466  knakahar 	return true;
   8271  1.466  knakahar }
   8272  1.466  knakahar 
   8273  1.466  knakahar static inline bool
   8274  1.466  knakahar wm_rxdesc_input_vlantag(struct wm_rxqueue *rxq, uint32_t status, uint16_t vlantag,
   8275  1.466  knakahar     struct mbuf *m)
   8276  1.466  knakahar {
   8277  1.466  knakahar 
   8278  1.466  knakahar 	if (wm_rxdesc_is_set_status(rxq->rxq_sc, status,
   8279  1.466  knakahar 		WRX_ST_VP, EXTRXC_STATUS_VP, NQRXC_STATUS_VP)) {
   8280  1.538  knakahar 		vlan_set_tag(m, le16toh(vlantag));
   8281  1.466  knakahar 	}
   8282  1.466  knakahar 
   8283  1.466  knakahar 	return true;
   8284  1.466  knakahar }
   8285  1.466  knakahar 
   8286  1.466  knakahar static inline void
   8287  1.466  knakahar wm_rxdesc_ensure_checksum(struct wm_rxqueue *rxq, uint32_t status,
   8288  1.466  knakahar     uint32_t errors, struct mbuf *m)
   8289  1.466  knakahar {
   8290  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8291  1.466  knakahar 
   8292  1.466  knakahar 	if (!wm_rxdesc_is_set_status(sc, status, WRX_ST_IXSM, 0, 0)) {
   8293  1.466  knakahar 		if (wm_rxdesc_is_set_status(sc, status,
   8294  1.466  knakahar 			WRX_ST_IPCS, EXTRXC_STATUS_IPCS, NQRXC_STATUS_IPCS)) {
   8295  1.466  knakahar 			WM_Q_EVCNT_INCR(rxq, rxipsum);
   8296  1.466  knakahar 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
   8297  1.466  knakahar 			if (wm_rxdesc_is_set_error(sc, errors,
   8298  1.466  knakahar 				WRX_ER_IPE, EXTRXC_ERROR_IPE, NQRXC_ERROR_IPE))
   8299  1.466  knakahar 				m->m_pkthdr.csum_flags |=
   8300  1.466  knakahar 					M_CSUM_IPv4_BAD;
   8301  1.466  knakahar 		}
   8302  1.466  knakahar 		if (wm_rxdesc_is_set_status(sc, status,
   8303  1.466  knakahar 			WRX_ST_TCPCS, EXTRXC_STATUS_TCPCS, NQRXC_STATUS_L4I)) {
   8304  1.466  knakahar 			/*
   8305  1.466  knakahar 			 * Note: we don't know if this was TCP or UDP,
   8306  1.466  knakahar 			 * so we just set both bits, and expect the
   8307  1.466  knakahar 			 * upper layers to deal.
   8308  1.466  knakahar 			 */
   8309  1.466  knakahar 			WM_Q_EVCNT_INCR(rxq, rxtusum);
   8310  1.466  knakahar 			m->m_pkthdr.csum_flags |=
   8311  1.466  knakahar 				M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   8312  1.466  knakahar 				M_CSUM_TCPv6 | M_CSUM_UDPv6;
   8313  1.466  knakahar 			if (wm_rxdesc_is_set_error(sc, errors,
   8314  1.466  knakahar 				WRX_ER_TCPE, EXTRXC_ERROR_TCPE, NQRXC_ERROR_L4E))
   8315  1.466  knakahar 				m->m_pkthdr.csum_flags |=
   8316  1.466  knakahar 					M_CSUM_TCP_UDP_BAD;
   8317  1.466  knakahar 		}
   8318  1.466  knakahar 	}
   8319  1.466  knakahar }
   8320  1.466  knakahar 
   8321  1.281   msaitoh /*
   8322  1.335   msaitoh  * wm_rxeof:
   8323  1.281   msaitoh  *
   8324  1.281   msaitoh  *	Helper; handle receive interrupts.
   8325  1.281   msaitoh  */
   8326  1.281   msaitoh static void
   8327  1.493  knakahar wm_rxeof(struct wm_rxqueue *rxq, u_int limit)
   8328  1.281   msaitoh {
   8329  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8330  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8331  1.281   msaitoh 	struct wm_rxsoft *rxs;
   8332  1.281   msaitoh 	struct mbuf *m;
   8333  1.281   msaitoh 	int i, len;
   8334  1.335   msaitoh 	int count = 0;
   8335  1.466  knakahar 	uint32_t status, errors;
   8336  1.281   msaitoh 	uint16_t vlantag;
   8337    1.1   thorpej 
   8338  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   8339  1.405  knakahar 
   8340  1.356  knakahar 	for (i = rxq->rxq_ptr;; i = WM_NEXTRX(i)) {
   8341  1.493  knakahar 		if (limit-- == 0) {
   8342  1.493  knakahar 			rxq->rxq_ptr = i;
   8343  1.493  knakahar 			break;
   8344  1.493  knakahar 		}
   8345  1.493  knakahar 
   8346  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   8347  1.156    dyoung 
   8348  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8349  1.281   msaitoh 		    ("%s: RX: checking descriptor %d\n",
   8350  1.281   msaitoh 		    device_xname(sc->sc_dev), i));
   8351  1.466  knakahar 		wm_cdrxsync(rxq, i,BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   8352  1.199   msaitoh 
   8353  1.466  knakahar 		status = wm_rxdesc_get_status(rxq, i);
   8354  1.466  knakahar 		errors = wm_rxdesc_get_errors(rxq, i);
   8355  1.466  knakahar 		len = le16toh(wm_rxdesc_get_pktlen(rxq, i));
   8356  1.466  knakahar 		vlantag = wm_rxdesc_get_vlantag(rxq, i);
   8357  1.466  knakahar #ifdef WM_DEBUG
   8358  1.471  knakahar 		uint32_t rsshash = le32toh(wm_rxdesc_get_rsshash(rxq, i));
   8359  1.468      maya 		uint8_t rsstype = wm_rxdesc_get_rsstype(rxq, i);
   8360  1.466  knakahar #endif
   8361    1.1   thorpej 
   8362  1.483  knakahar 		if (!wm_rxdesc_dd(rxq, i, status)) {
   8363  1.483  knakahar 			/*
   8364  1.483  knakahar 			 * Update the receive pointer holding rxq_lock
   8365  1.483  knakahar 			 * consistent with increment counter.
   8366  1.483  knakahar 			 */
   8367  1.483  knakahar 			rxq->rxq_ptr = i;
   8368  1.281   msaitoh 			break;
   8369  1.483  knakahar 		}
   8370  1.189   msaitoh 
   8371  1.335   msaitoh 		count++;
   8372  1.356  knakahar 		if (__predict_false(rxq->rxq_discard)) {
   8373  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8374  1.281   msaitoh 			    ("%s: RX: discarding contents of descriptor %d\n",
   8375  1.281   msaitoh 			    device_xname(sc->sc_dev), i));
   8376  1.362  knakahar 			wm_init_rxdesc(rxq, i);
   8377  1.466  knakahar 			if (wm_rxdesc_is_eop(rxq, status)) {
   8378  1.281   msaitoh 				/* Reset our state. */
   8379  1.281   msaitoh 				DPRINTF(WM_DEBUG_RX,
   8380  1.281   msaitoh 				    ("%s: RX: resetting rxdiscard -> 0\n",
   8381  1.281   msaitoh 				    device_xname(sc->sc_dev)));
   8382  1.356  knakahar 				rxq->rxq_discard = 0;
   8383  1.281   msaitoh 			}
   8384  1.281   msaitoh 			continue;
   8385  1.189   msaitoh 		}
   8386  1.189   msaitoh 
   8387  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   8388  1.281   msaitoh 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   8389  1.189   msaitoh 
   8390  1.281   msaitoh 		m = rxs->rxs_mbuf;
   8391  1.189   msaitoh 
   8392  1.281   msaitoh 		/*
   8393  1.281   msaitoh 		 * Add a new receive buffer to the ring, unless of
   8394  1.281   msaitoh 		 * course the length is zero. Treat the latter as a
   8395  1.281   msaitoh 		 * failed mapping.
   8396  1.281   msaitoh 		 */
   8397  1.362  knakahar 		if ((len == 0) || (wm_add_rxbuf(rxq, i) != 0)) {
   8398  1.281   msaitoh 			/*
   8399  1.281   msaitoh 			 * Failed, throw away what we've done so
   8400  1.281   msaitoh 			 * far, and discard the rest of the packet.
   8401  1.281   msaitoh 			 */
   8402  1.281   msaitoh 			ifp->if_ierrors++;
   8403  1.281   msaitoh 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   8404  1.281   msaitoh 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   8405  1.362  knakahar 			wm_init_rxdesc(rxq, i);
   8406  1.466  knakahar 			if (!wm_rxdesc_is_eop(rxq, status))
   8407  1.356  knakahar 				rxq->rxq_discard = 1;
   8408  1.356  knakahar 			if (rxq->rxq_head != NULL)
   8409  1.356  knakahar 				m_freem(rxq->rxq_head);
   8410  1.356  knakahar 			WM_RXCHAIN_RESET(rxq);
   8411  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8412  1.281   msaitoh 			    ("%s: RX: Rx buffer allocation failed, "
   8413  1.281   msaitoh 			    "dropping packet%s\n", device_xname(sc->sc_dev),
   8414  1.366  knakahar 			    rxq->rxq_discard ? " (discard)" : ""));
   8415  1.281   msaitoh 			continue;
   8416  1.189   msaitoh 		}
   8417  1.253   msaitoh 
   8418  1.281   msaitoh 		m->m_len = len;
   8419  1.356  knakahar 		rxq->rxq_len += len;
   8420  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8421  1.281   msaitoh 		    ("%s: RX: buffer at %p len %d\n",
   8422  1.281   msaitoh 		    device_xname(sc->sc_dev), m->m_data, len));
   8423  1.145   msaitoh 
   8424  1.281   msaitoh 		/* If this is not the end of the packet, keep looking. */
   8425  1.466  knakahar 		if (!wm_rxdesc_is_eop(rxq, status)) {
   8426  1.356  knakahar 			WM_RXCHAIN_LINK(rxq, m);
   8427  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8428  1.281   msaitoh 			    ("%s: RX: not yet EOP, rxlen -> %d\n",
   8429  1.366  knakahar 			    device_xname(sc->sc_dev), rxq->rxq_len));
   8430  1.281   msaitoh 			continue;
   8431  1.281   msaitoh 		}
   8432   1.45   thorpej 
   8433  1.281   msaitoh 		/*
   8434  1.281   msaitoh 		 * Okay, we have the entire packet now.  The chip is
   8435  1.281   msaitoh 		 * configured to include the FCS except I350 and I21[01]
   8436  1.281   msaitoh 		 * (not all chips can be configured to strip it),
   8437  1.281   msaitoh 		 * so we need to trim it.
   8438  1.281   msaitoh 		 * May need to adjust length of previous mbuf in the
   8439  1.281   msaitoh 		 * chain if the current mbuf is too short.
   8440  1.281   msaitoh 		 * For an eratta, the RCTL_SECRC bit in RCTL register
   8441  1.281   msaitoh 		 * is always set in I350, so we don't trim it.
   8442  1.281   msaitoh 		 */
   8443  1.281   msaitoh 		if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I354)
   8444  1.281   msaitoh 		    && (sc->sc_type != WM_T_I210)
   8445  1.281   msaitoh 		    && (sc->sc_type != WM_T_I211)) {
   8446  1.281   msaitoh 			if (m->m_len < ETHER_CRC_LEN) {
   8447  1.356  knakahar 				rxq->rxq_tail->m_len
   8448  1.281   msaitoh 				    -= (ETHER_CRC_LEN - m->m_len);
   8449  1.281   msaitoh 				m->m_len = 0;
   8450  1.281   msaitoh 			} else
   8451  1.281   msaitoh 				m->m_len -= ETHER_CRC_LEN;
   8452  1.356  knakahar 			len = rxq->rxq_len - ETHER_CRC_LEN;
   8453  1.281   msaitoh 		} else
   8454  1.356  knakahar 			len = rxq->rxq_len;
   8455  1.117   msaitoh 
   8456  1.356  knakahar 		WM_RXCHAIN_LINK(rxq, m);
   8457  1.127    bouyer 
   8458  1.356  knakahar 		*rxq->rxq_tailp = NULL;
   8459  1.356  knakahar 		m = rxq->rxq_head;
   8460  1.117   msaitoh 
   8461  1.356  knakahar 		WM_RXCHAIN_RESET(rxq);
   8462   1.45   thorpej 
   8463  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8464  1.281   msaitoh 		    ("%s: RX: have entire packet, len -> %d\n",
   8465  1.281   msaitoh 		    device_xname(sc->sc_dev), len));
   8466   1.45   thorpej 
   8467  1.281   msaitoh 		/* If an error occurred, update stats and drop the packet. */
   8468  1.466  knakahar 		if (wm_rxdesc_has_errors(rxq, errors)) {
   8469  1.281   msaitoh 			m_freem(m);
   8470  1.281   msaitoh 			continue;
   8471   1.45   thorpej 		}
   8472   1.45   thorpej 
   8473  1.281   msaitoh 		/* No errors.  Receive the packet. */
   8474  1.412     ozaki 		m_set_rcvif(m, ifp);
   8475  1.281   msaitoh 		m->m_pkthdr.len = len;
   8476  1.471  knakahar 		/*
   8477  1.471  knakahar 		 * TODO
   8478  1.471  knakahar 		 * should be save rsshash and rsstype to this mbuf.
   8479  1.471  knakahar 		 */
   8480  1.471  knakahar 		DPRINTF(WM_DEBUG_RX,
   8481  1.471  knakahar 		    ("%s: RX: RSS type=%" PRIu8 ", RSS hash=%" PRIu32 "\n",
   8482  1.471  knakahar 			device_xname(sc->sc_dev), rsstype, rsshash));
   8483   1.45   thorpej 
   8484  1.281   msaitoh 		/*
   8485  1.281   msaitoh 		 * If VLANs are enabled, VLAN packets have been unwrapped
   8486  1.281   msaitoh 		 * for us.  Associate the tag with the packet.
   8487  1.281   msaitoh 		 */
   8488  1.466  knakahar 		if (!wm_rxdesc_input_vlantag(rxq, status, vlantag, m))
   8489  1.466  knakahar 			continue;
   8490   1.45   thorpej 
   8491  1.281   msaitoh 		/* Set up checksum info for this packet. */
   8492  1.466  knakahar 		wm_rxdesc_ensure_checksum(rxq, status, errors, m);
   8493  1.483  knakahar 		/*
   8494  1.483  knakahar 		 * Update the receive pointer holding rxq_lock consistent with
   8495  1.483  knakahar 		 * increment counter.
   8496  1.483  knakahar 		 */
   8497  1.483  knakahar 		rxq->rxq_ptr = i;
   8498  1.495  knakahar 		rxq->rxq_packets++;
   8499  1.495  knakahar 		rxq->rxq_bytes += len;
   8500  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   8501   1.45   thorpej 
   8502  1.281   msaitoh 		/* Pass it on. */
   8503  1.391     ozaki 		if_percpuq_enqueue(sc->sc_ipq, m);
   8504   1.46   thorpej 
   8505  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   8506   1.46   thorpej 
   8507  1.429  knakahar 		if (rxq->rxq_stopping)
   8508  1.281   msaitoh 			break;
   8509   1.48   thorpej 	}
   8510  1.281   msaitoh 
   8511  1.335   msaitoh 	if (count != 0)
   8512  1.335   msaitoh 		rnd_add_uint32(&sc->rnd_source, count);
   8513  1.281   msaitoh 
   8514  1.281   msaitoh 	DPRINTF(WM_DEBUG_RX,
   8515  1.281   msaitoh 	    ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i));
   8516   1.48   thorpej }
   8517   1.48   thorpej 
   8518   1.48   thorpej /*
   8519  1.281   msaitoh  * wm_linkintr_gmii:
   8520   1.50   thorpej  *
   8521  1.281   msaitoh  *	Helper; handle link interrupts for GMII.
   8522   1.50   thorpej  */
   8523  1.281   msaitoh static void
   8524  1.281   msaitoh wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
   8525   1.50   thorpej {
   8526   1.51   thorpej 
   8527  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   8528  1.281   msaitoh 
   8529  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8530  1.281   msaitoh 		__func__));
   8531  1.281   msaitoh 
   8532  1.281   msaitoh 	if (icr & ICR_LSC) {
   8533  1.445   msaitoh 		uint32_t reg;
   8534  1.381   msaitoh 		uint32_t status = CSR_READ(sc, WMREG_STATUS);
   8535  1.381   msaitoh 
   8536  1.523   msaitoh 		if ((status & STATUS_LU) != 0) {
   8537  1.523   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
   8538  1.523   msaitoh 				device_xname(sc->sc_dev),
   8539  1.523   msaitoh 				(status & STATUS_FD) ? "FDX" : "HDX"));
   8540  1.523   msaitoh 		} else {
   8541  1.523   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   8542  1.523   msaitoh 				device_xname(sc->sc_dev)));
   8543  1.523   msaitoh 		}
   8544  1.381   msaitoh 		if ((sc->sc_type == WM_T_ICH8) && ((status & STATUS_LU) == 0))
   8545  1.381   msaitoh 			wm_gig_downshift_workaround_ich8lan(sc);
   8546  1.381   msaitoh 
   8547  1.523   msaitoh 		if ((sc->sc_type == WM_T_ICH8)
   8548  1.523   msaitoh 		    && (sc->sc_phytype == WMPHY_IGP_3)) {
   8549  1.523   msaitoh 			wm_kmrn_lock_loss_workaround_ich8lan(sc);
   8550  1.523   msaitoh 		}
   8551  1.381   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> mii_pollstat\n",
   8552  1.281   msaitoh 			device_xname(sc->sc_dev)));
   8553  1.281   msaitoh 		mii_pollstat(&sc->sc_mii);
   8554  1.281   msaitoh 		if (sc->sc_type == WM_T_82543) {
   8555  1.281   msaitoh 			int miistatus, active;
   8556  1.281   msaitoh 
   8557  1.281   msaitoh 			/*
   8558  1.281   msaitoh 			 * With 82543, we need to force speed and
   8559  1.281   msaitoh 			 * duplex on the MAC equal to what the PHY
   8560  1.281   msaitoh 			 * speed and duplex configuration is.
   8561  1.281   msaitoh 			 */
   8562  1.281   msaitoh 			miistatus = sc->sc_mii.mii_media_status;
   8563   1.50   thorpej 
   8564  1.281   msaitoh 			if (miistatus & IFM_ACTIVE) {
   8565  1.281   msaitoh 				active = sc->sc_mii.mii_media_active;
   8566  1.281   msaitoh 				sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
   8567  1.281   msaitoh 				switch (IFM_SUBTYPE(active)) {
   8568  1.281   msaitoh 				case IFM_10_T:
   8569  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_10;
   8570  1.281   msaitoh 					break;
   8571  1.281   msaitoh 				case IFM_100_TX:
   8572  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_100;
   8573  1.281   msaitoh 					break;
   8574  1.281   msaitoh 				case IFM_1000_T:
   8575  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_1000;
   8576  1.281   msaitoh 					break;
   8577  1.281   msaitoh 				default:
   8578  1.281   msaitoh 					/*
   8579  1.281   msaitoh 					 * fiber?
   8580  1.281   msaitoh 					 * Shoud not enter here.
   8581  1.281   msaitoh 					 */
   8582  1.388   msaitoh 					printf("unknown media (%x)\n", active);
   8583  1.281   msaitoh 					break;
   8584  1.281   msaitoh 				}
   8585  1.281   msaitoh 				if (active & IFM_FDX)
   8586  1.281   msaitoh 					sc->sc_ctrl |= CTRL_FD;
   8587  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   8588  1.281   msaitoh 			}
   8589  1.281   msaitoh 		} else if (sc->sc_type == WM_T_PCH) {
   8590  1.281   msaitoh 			wm_k1_gig_workaround_hv(sc,
   8591  1.281   msaitoh 			    ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
   8592  1.230   msaitoh 		}
   8593   1.51   thorpej 
   8594  1.281   msaitoh 		if ((sc->sc_phytype == WMPHY_82578)
   8595  1.281   msaitoh 		    && (IFM_SUBTYPE(sc->sc_mii.mii_media_active)
   8596  1.281   msaitoh 			== IFM_1000_T)) {
   8597   1.51   thorpej 
   8598  1.281   msaitoh 			if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0) {
   8599  1.281   msaitoh 				delay(200*1000); /* XXX too big */
   8600   1.51   thorpej 
   8601  1.281   msaitoh 				/* Link stall fix for link up */
   8602  1.281   msaitoh 				wm_gmii_hv_writereg(sc->sc_dev, 1,
   8603  1.281   msaitoh 				    HV_MUX_DATA_CTRL,
   8604  1.281   msaitoh 				    HV_MUX_DATA_CTRL_GEN_TO_MAC
   8605  1.281   msaitoh 				    | HV_MUX_DATA_CTRL_FORCE_SPEED);
   8606  1.281   msaitoh 				wm_gmii_hv_writereg(sc->sc_dev, 1,
   8607  1.281   msaitoh 				    HV_MUX_DATA_CTRL,
   8608  1.281   msaitoh 				    HV_MUX_DATA_CTRL_GEN_TO_MAC);
   8609  1.281   msaitoh 			}
   8610  1.281   msaitoh 		}
   8611  1.445   msaitoh 		/*
   8612  1.445   msaitoh 		 * I217 Packet Loss issue:
   8613  1.445   msaitoh 		 * ensure that FEXTNVM4 Beacon Duration is set correctly
   8614  1.445   msaitoh 		 * on power up.
   8615  1.445   msaitoh 		 * Set the Beacon Duration for I217 to 8 usec
   8616  1.445   msaitoh 		 */
   8617  1.445   msaitoh 		if ((sc->sc_type == WM_T_PCH_LPT)
   8618  1.445   msaitoh 		    || (sc->sc_type == WM_T_PCH_SPT)) {
   8619  1.445   msaitoh 			reg = CSR_READ(sc, WMREG_FEXTNVM4);
   8620  1.445   msaitoh 			reg &= ~FEXTNVM4_BEACON_DURATION;
   8621  1.445   msaitoh 			reg |= FEXTNVM4_BEACON_DURATION_8US;
   8622  1.445   msaitoh 			CSR_WRITE(sc, WMREG_FEXTNVM4, reg);
   8623  1.445   msaitoh 		}
   8624  1.445   msaitoh 
   8625  1.445   msaitoh 		/* XXX Work-around I218 hang issue */
   8626  1.445   msaitoh 		/* e1000_k1_workaround_lpt_lp() */
   8627  1.445   msaitoh 
   8628  1.445   msaitoh 		if ((sc->sc_type == WM_T_PCH_LPT)
   8629  1.445   msaitoh 		    || (sc->sc_type == WM_T_PCH_SPT)) {
   8630  1.445   msaitoh 			/*
   8631  1.445   msaitoh 			 * Set platform power management values for Latency
   8632  1.445   msaitoh 			 * Tolerance Reporting (LTR)
   8633  1.445   msaitoh 			 */
   8634  1.445   msaitoh 			wm_platform_pm_pch_lpt(sc,
   8635  1.445   msaitoh 				((sc->sc_mii.mii_media_status & IFM_ACTIVE)
   8636  1.445   msaitoh 				    != 0));
   8637  1.445   msaitoh 		}
   8638  1.445   msaitoh 
   8639  1.445   msaitoh 		/* FEXTNVM6 K1-off workaround */
   8640  1.445   msaitoh 		if (sc->sc_type == WM_T_PCH_SPT) {
   8641  1.445   msaitoh 			reg = CSR_READ(sc, WMREG_FEXTNVM6);
   8642  1.445   msaitoh 			if (CSR_READ(sc, WMREG_PCIEANACFG)
   8643  1.445   msaitoh 			    & FEXTNVM6_K1_OFF_ENABLE)
   8644  1.445   msaitoh 				reg |= FEXTNVM6_K1_OFF_ENABLE;
   8645  1.445   msaitoh 			else
   8646  1.445   msaitoh 				reg &= ~FEXTNVM6_K1_OFF_ENABLE;
   8647  1.445   msaitoh 			CSR_WRITE(sc, WMREG_FEXTNVM6, reg);
   8648  1.445   msaitoh 		}
   8649  1.281   msaitoh 	} else if (icr & ICR_RXSEQ) {
   8650  1.388   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK Receive sequence error\n",
   8651  1.281   msaitoh 			device_xname(sc->sc_dev)));
   8652   1.51   thorpej 	}
   8653   1.50   thorpej }
   8654   1.50   thorpej 
   8655   1.50   thorpej /*
   8656  1.281   msaitoh  * wm_linkintr_tbi:
   8657   1.57   thorpej  *
   8658  1.281   msaitoh  *	Helper; handle link interrupts for TBI mode.
   8659   1.57   thorpej  */
   8660  1.281   msaitoh static void
   8661  1.281   msaitoh wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
   8662   1.57   thorpej {
   8663  1.506   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8664  1.281   msaitoh 	uint32_t status;
   8665  1.281   msaitoh 
   8666  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8667  1.281   msaitoh 		__func__));
   8668  1.281   msaitoh 
   8669  1.281   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   8670  1.281   msaitoh 	if (icr & ICR_LSC) {
   8671  1.281   msaitoh 		if (status & STATUS_LU) {
   8672  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
   8673  1.281   msaitoh 			    device_xname(sc->sc_dev),
   8674  1.281   msaitoh 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   8675  1.281   msaitoh 			/*
   8676  1.281   msaitoh 			 * NOTE: CTRL will update TFCE and RFCE automatically,
   8677  1.281   msaitoh 			 * so we should update sc->sc_ctrl
   8678  1.281   msaitoh 			 */
   8679   1.57   thorpej 
   8680  1.281   msaitoh 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   8681  1.281   msaitoh 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   8682  1.281   msaitoh 			sc->sc_fcrtl &= ~FCRTL_XONE;
   8683  1.281   msaitoh 			if (status & STATUS_FD)
   8684  1.281   msaitoh 				sc->sc_tctl |=
   8685  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   8686  1.281   msaitoh 			else
   8687  1.281   msaitoh 				sc->sc_tctl |=
   8688  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   8689  1.281   msaitoh 			if (sc->sc_ctrl & CTRL_TFCE)
   8690  1.281   msaitoh 				sc->sc_fcrtl |= FCRTL_XONE;
   8691  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   8692  1.281   msaitoh 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   8693  1.281   msaitoh 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   8694  1.281   msaitoh 				      sc->sc_fcrtl);
   8695  1.281   msaitoh 			sc->sc_tbi_linkup = 1;
   8696  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_UP);
   8697  1.281   msaitoh 		} else {
   8698  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   8699  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   8700  1.281   msaitoh 			sc->sc_tbi_linkup = 0;
   8701  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_DOWN);
   8702  1.281   msaitoh 		}
   8703  1.325   msaitoh 		/* Update LED */
   8704  1.325   msaitoh 		wm_tbi_serdes_set_linkled(sc);
   8705  1.281   msaitoh 	} else if (icr & ICR_RXSEQ) {
   8706  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   8707  1.281   msaitoh 		    ("%s: LINK: Receive sequence error\n",
   8708  1.281   msaitoh 		    device_xname(sc->sc_dev)));
   8709   1.57   thorpej 	}
   8710   1.57   thorpej }
   8711   1.57   thorpej 
   8712   1.57   thorpej /*
   8713  1.325   msaitoh  * wm_linkintr_serdes:
   8714  1.325   msaitoh  *
   8715  1.325   msaitoh  *	Helper; handle link interrupts for TBI mode.
   8716  1.325   msaitoh  */
   8717  1.325   msaitoh static void
   8718  1.325   msaitoh wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
   8719  1.325   msaitoh {
   8720  1.506   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8721  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   8722  1.325   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   8723  1.325   msaitoh 	uint32_t pcs_adv, pcs_lpab, reg;
   8724  1.325   msaitoh 
   8725  1.325   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8726  1.325   msaitoh 		__func__));
   8727  1.325   msaitoh 
   8728  1.325   msaitoh 	if (icr & ICR_LSC) {
   8729  1.325   msaitoh 		/* Check PCS */
   8730  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_LSTS);
   8731  1.325   msaitoh 		if ((reg & PCS_LSTS_LINKOK) != 0) {
   8732  1.506   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up\n",
   8733  1.506   msaitoh 				device_xname(sc->sc_dev)));
   8734  1.325   msaitoh 			mii->mii_media_status |= IFM_ACTIVE;
   8735  1.325   msaitoh 			sc->sc_tbi_linkup = 1;
   8736  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_UP);
   8737  1.325   msaitoh 		} else {
   8738  1.506   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   8739  1.506   msaitoh 				device_xname(sc->sc_dev)));
   8740  1.325   msaitoh 			mii->mii_media_status |= IFM_NONE;
   8741  1.325   msaitoh 			sc->sc_tbi_linkup = 0;
   8742  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_DOWN);
   8743  1.325   msaitoh 			wm_tbi_serdes_set_linkled(sc);
   8744  1.325   msaitoh 			return;
   8745  1.325   msaitoh 		}
   8746  1.325   msaitoh 		mii->mii_media_active |= IFM_1000_SX;
   8747  1.325   msaitoh 		if ((reg & PCS_LSTS_FDX) != 0)
   8748  1.325   msaitoh 			mii->mii_media_active |= IFM_FDX;
   8749  1.325   msaitoh 		else
   8750  1.325   msaitoh 			mii->mii_media_active |= IFM_HDX;
   8751  1.325   msaitoh 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   8752  1.325   msaitoh 			/* Check flow */
   8753  1.325   msaitoh 			reg = CSR_READ(sc, WMREG_PCS_LSTS);
   8754  1.325   msaitoh 			if ((reg & PCS_LSTS_AN_COMP) == 0) {
   8755  1.325   msaitoh 				DPRINTF(WM_DEBUG_LINK,
   8756  1.325   msaitoh 				    ("XXX LINKOK but not ACOMP\n"));
   8757  1.325   msaitoh 				return;
   8758  1.325   msaitoh 			}
   8759  1.325   msaitoh 			pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
   8760  1.325   msaitoh 			pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
   8761  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   8762  1.325   msaitoh 			    ("XXX AN result %08x, %08x\n", pcs_adv, pcs_lpab));
   8763  1.325   msaitoh 			if ((pcs_adv & TXCW_SYM_PAUSE)
   8764  1.325   msaitoh 			    && (pcs_lpab & TXCW_SYM_PAUSE)) {
   8765  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8766  1.325   msaitoh 				    | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   8767  1.325   msaitoh 			} else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
   8768  1.325   msaitoh 			    && (pcs_adv & TXCW_ASYM_PAUSE)
   8769  1.325   msaitoh 			    && (pcs_lpab & TXCW_SYM_PAUSE)
   8770  1.325   msaitoh 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
   8771  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8772  1.325   msaitoh 				    | IFM_ETH_TXPAUSE;
   8773  1.325   msaitoh 			else if ((pcs_adv & TXCW_SYM_PAUSE)
   8774  1.325   msaitoh 			    && (pcs_adv & TXCW_ASYM_PAUSE)
   8775  1.325   msaitoh 			    && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
   8776  1.325   msaitoh 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
   8777  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8778  1.325   msaitoh 				    | IFM_ETH_RXPAUSE;
   8779  1.325   msaitoh 		}
   8780  1.325   msaitoh 		/* Update LED */
   8781  1.325   msaitoh 		wm_tbi_serdes_set_linkled(sc);
   8782  1.325   msaitoh 	} else {
   8783  1.325   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   8784  1.325   msaitoh 		    ("%s: LINK: Receive sequence error\n",
   8785  1.325   msaitoh 		    device_xname(sc->sc_dev)));
   8786  1.325   msaitoh 	}
   8787  1.325   msaitoh }
   8788  1.325   msaitoh 
   8789  1.325   msaitoh /*
   8790  1.281   msaitoh  * wm_linkintr:
   8791   1.57   thorpej  *
   8792  1.281   msaitoh  *	Helper; handle link interrupts.
   8793   1.57   thorpej  */
   8794  1.281   msaitoh static void
   8795  1.281   msaitoh wm_linkintr(struct wm_softc *sc, uint32_t icr)
   8796   1.57   thorpej {
   8797   1.57   thorpej 
   8798  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   8799  1.357  knakahar 
   8800  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   8801  1.281   msaitoh 		wm_linkintr_gmii(sc, icr);
   8802  1.325   msaitoh 	else if ((sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   8803  1.332   msaitoh 	    && (sc->sc_type >= WM_T_82575))
   8804  1.325   msaitoh 		wm_linkintr_serdes(sc, icr);
   8805  1.281   msaitoh 	else
   8806  1.281   msaitoh 		wm_linkintr_tbi(sc, icr);
   8807   1.57   thorpej }
   8808   1.57   thorpej 
   8809  1.112     gavan /*
   8810  1.335   msaitoh  * wm_intr_legacy:
   8811  1.112     gavan  *
   8812  1.335   msaitoh  *	Interrupt service routine for INTx and MSI.
   8813  1.112     gavan  */
   8814  1.112     gavan static int
   8815  1.335   msaitoh wm_intr_legacy(void *arg)
   8816  1.198   msaitoh {
   8817  1.281   msaitoh 	struct wm_softc *sc = arg;
   8818  1.484  knakahar 	struct wm_queue *wmq = &sc->sc_queue[0];
   8819  1.484  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   8820  1.484  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   8821  1.335   msaitoh 	uint32_t icr, rndval = 0;
   8822  1.281   msaitoh 	int handled = 0;
   8823  1.281   msaitoh 
   8824  1.281   msaitoh 	while (1 /* CONSTCOND */) {
   8825  1.281   msaitoh 		icr = CSR_READ(sc, WMREG_ICR);
   8826  1.281   msaitoh 		if ((icr & sc->sc_icr) == 0)
   8827  1.281   msaitoh 			break;
   8828  1.511   msaitoh 		if (handled == 0) {
   8829  1.511   msaitoh 			DPRINTF(WM_DEBUG_TX,
   8830  1.517   msaitoh 			    ("%s: INTx: got intr\n",device_xname(sc->sc_dev)));
   8831  1.511   msaitoh 		}
   8832  1.335   msaitoh 		if (rndval == 0)
   8833  1.335   msaitoh 			rndval = icr;
   8834  1.112     gavan 
   8835  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   8836  1.112     gavan 
   8837  1.429  knakahar 		if (rxq->rxq_stopping) {
   8838  1.413     skrll 			mutex_exit(rxq->rxq_lock);
   8839  1.281   msaitoh 			break;
   8840  1.281   msaitoh 		}
   8841  1.247   msaitoh 
   8842  1.281   msaitoh 		handled = 1;
   8843  1.249   msaitoh 
   8844  1.281   msaitoh #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   8845  1.388   msaitoh 		if (icr & (ICR_RXDMT0 | ICR_RXT0)) {
   8846  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8847  1.281   msaitoh 			    ("%s: RX: got Rx intr 0x%08x\n",
   8848  1.281   msaitoh 			    device_xname(sc->sc_dev),
   8849  1.388   msaitoh 			    icr & (ICR_RXDMT0 | ICR_RXT0)));
   8850  1.417  knakahar 			WM_Q_EVCNT_INCR(rxq, rxintr);
   8851  1.240   msaitoh 		}
   8852  1.281   msaitoh #endif
   8853  1.536  knakahar 		/*
   8854  1.536  knakahar 		 * wm_rxeof() does *not* call upper layer functions directly,
   8855  1.536  knakahar 		 * as if_percpuq_enqueue() just call softint_schedule().
   8856  1.536  knakahar 		 * So, we can call wm_rxeof() in interrupt context.
   8857  1.536  knakahar 		 */
   8858  1.493  knakahar 		wm_rxeof(rxq, UINT_MAX);
   8859  1.240   msaitoh 
   8860  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   8861  1.413     skrll 		mutex_enter(txq->txq_lock);
   8862  1.283     ozaki 
   8863  1.429  knakahar 		if (txq->txq_stopping) {
   8864  1.429  knakahar 			mutex_exit(txq->txq_lock);
   8865  1.429  knakahar 			break;
   8866  1.429  knakahar 		}
   8867  1.429  knakahar 
   8868  1.281   msaitoh #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   8869  1.281   msaitoh 		if (icr & ICR_TXDW) {
   8870  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   8871  1.281   msaitoh 			    ("%s: TX: got TXDW interrupt\n",
   8872  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   8873  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdw);
   8874  1.240   msaitoh 		}
   8875  1.281   msaitoh #endif
   8876  1.403  knakahar 		wm_txeof(sc, txq);
   8877  1.240   msaitoh 
   8878  1.413     skrll 		mutex_exit(txq->txq_lock);
   8879  1.357  knakahar 		WM_CORE_LOCK(sc);
   8880  1.357  knakahar 
   8881  1.429  knakahar 		if (sc->sc_core_stopping) {
   8882  1.429  knakahar 			WM_CORE_UNLOCK(sc);
   8883  1.429  knakahar 			break;
   8884  1.429  knakahar 		}
   8885  1.429  knakahar 
   8886  1.388   msaitoh 		if (icr & (ICR_LSC | ICR_RXSEQ)) {
   8887  1.281   msaitoh 			WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   8888  1.281   msaitoh 			wm_linkintr(sc, icr);
   8889  1.281   msaitoh 		}
   8890  1.240   msaitoh 
   8891  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   8892  1.112     gavan 
   8893  1.281   msaitoh 		if (icr & ICR_RXO) {
   8894  1.281   msaitoh #if defined(WM_DEBUG)
   8895  1.281   msaitoh 			log(LOG_WARNING, "%s: Receive overrun\n",
   8896  1.281   msaitoh 			    device_xname(sc->sc_dev));
   8897  1.281   msaitoh #endif /* defined(WM_DEBUG) */
   8898  1.281   msaitoh 		}
   8899  1.249   msaitoh 	}
   8900  1.112     gavan 
   8901  1.335   msaitoh 	rnd_add_uint32(&sc->rnd_source, rndval);
   8902  1.335   msaitoh 
   8903  1.335   msaitoh 	if (handled) {
   8904  1.335   msaitoh 		/* Try to get more packets going. */
   8905  1.484  knakahar 		softint_schedule(wmq->wmq_si);
   8906  1.335   msaitoh 	}
   8907  1.335   msaitoh 
   8908  1.335   msaitoh 	return handled;
   8909  1.335   msaitoh }
   8910  1.335   msaitoh 
   8911  1.480  knakahar static inline void
   8912  1.480  knakahar wm_txrxintr_disable(struct wm_queue *wmq)
   8913  1.480  knakahar {
   8914  1.480  knakahar 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
   8915  1.480  knakahar 
   8916  1.480  knakahar 	if (sc->sc_type == WM_T_82574)
   8917  1.480  knakahar 		CSR_WRITE(sc, WMREG_IMC, ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id));
   8918  1.480  knakahar 	else if (sc->sc_type == WM_T_82575)
   8919  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMC, EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
   8920  1.480  knakahar 	else
   8921  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMC, 1 << wmq->wmq_intr_idx);
   8922  1.480  knakahar }
   8923  1.480  knakahar 
   8924  1.480  knakahar static inline void
   8925  1.480  knakahar wm_txrxintr_enable(struct wm_queue *wmq)
   8926  1.480  knakahar {
   8927  1.480  knakahar 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
   8928  1.480  knakahar 
   8929  1.495  knakahar 	wm_itrs_calculate(sc, wmq);
   8930  1.495  knakahar 
   8931  1.480  knakahar 	if (sc->sc_type == WM_T_82574)
   8932  1.480  knakahar 		CSR_WRITE(sc, WMREG_IMS, ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id));
   8933  1.480  knakahar 	else if (sc->sc_type == WM_T_82575)
   8934  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMS, EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
   8935  1.480  knakahar 	else
   8936  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMS, 1 << wmq->wmq_intr_idx);
   8937  1.480  knakahar }
   8938  1.480  knakahar 
   8939  1.335   msaitoh static int
   8940  1.405  knakahar wm_txrxintr_msix(void *arg)
   8941  1.335   msaitoh {
   8942  1.405  knakahar 	struct wm_queue *wmq = arg;
   8943  1.405  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   8944  1.405  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   8945  1.363  knakahar 	struct wm_softc *sc = txq->txq_sc;
   8946  1.493  knakahar 	u_int limit = sc->sc_rx_intr_process_limit;
   8947  1.335   msaitoh 
   8948  1.405  knakahar 	KASSERT(wmq->wmq_intr_idx == wmq->wmq_id);
   8949  1.405  knakahar 
   8950  1.335   msaitoh 	DPRINTF(WM_DEBUG_TX,
   8951  1.335   msaitoh 	    ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev)));
   8952  1.335   msaitoh 
   8953  1.480  knakahar 	wm_txrxintr_disable(wmq);
   8954  1.335   msaitoh 
   8955  1.429  knakahar 	mutex_enter(txq->txq_lock);
   8956  1.429  knakahar 
   8957  1.429  knakahar 	if (txq->txq_stopping) {
   8958  1.429  knakahar 		mutex_exit(txq->txq_lock);
   8959  1.429  knakahar 		return 0;
   8960  1.429  knakahar 	}
   8961  1.335   msaitoh 
   8962  1.429  knakahar 	WM_Q_EVCNT_INCR(txq, txdw);
   8963  1.429  knakahar 	wm_txeof(sc, txq);
   8964  1.484  knakahar 	/* wm_deferred start() is done in wm_handle_queue(). */
   8965  1.429  knakahar 	mutex_exit(txq->txq_lock);
   8966  1.429  knakahar 
   8967  1.364  knakahar 	DPRINTF(WM_DEBUG_RX,
   8968  1.335   msaitoh 	    ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev)));
   8969  1.429  knakahar 	mutex_enter(rxq->rxq_lock);
   8970  1.335   msaitoh 
   8971  1.429  knakahar 	if (rxq->rxq_stopping) {
   8972  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   8973  1.429  knakahar 		return 0;
   8974  1.405  knakahar 	}
   8975  1.335   msaitoh 
   8976  1.429  knakahar 	WM_Q_EVCNT_INCR(rxq, rxintr);
   8977  1.493  knakahar 	wm_rxeof(rxq, limit);
   8978  1.429  knakahar 	mutex_exit(rxq->rxq_lock);
   8979  1.429  knakahar 
   8980  1.495  knakahar 	wm_itrs_writereg(sc, wmq);
   8981  1.495  knakahar 
   8982  1.484  knakahar 	softint_schedule(wmq->wmq_si);
   8983  1.484  knakahar 
   8984  1.335   msaitoh 	return 1;
   8985  1.335   msaitoh }
   8986  1.335   msaitoh 
   8987  1.484  knakahar static void
   8988  1.484  knakahar wm_handle_queue(void *arg)
   8989  1.484  knakahar {
   8990  1.484  knakahar 	struct wm_queue *wmq = arg;
   8991  1.484  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   8992  1.484  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   8993  1.484  knakahar 	struct wm_softc *sc = txq->txq_sc;
   8994  1.493  knakahar 	u_int limit = sc->sc_rx_process_limit;
   8995  1.484  knakahar 
   8996  1.484  knakahar 	mutex_enter(txq->txq_lock);
   8997  1.484  knakahar 	if (txq->txq_stopping) {
   8998  1.484  knakahar 		mutex_exit(txq->txq_lock);
   8999  1.484  knakahar 		return;
   9000  1.484  knakahar 	}
   9001  1.484  knakahar 	wm_txeof(sc, txq);
   9002  1.484  knakahar 	wm_deferred_start_locked(txq);
   9003  1.484  knakahar 	mutex_exit(txq->txq_lock);
   9004  1.484  knakahar 
   9005  1.484  knakahar 	mutex_enter(rxq->rxq_lock);
   9006  1.484  knakahar 	if (rxq->rxq_stopping) {
   9007  1.484  knakahar 		mutex_exit(rxq->rxq_lock);
   9008  1.484  knakahar 		return;
   9009  1.484  knakahar 	}
   9010  1.484  knakahar 	WM_Q_EVCNT_INCR(rxq, rxintr);
   9011  1.493  knakahar 	wm_rxeof(rxq, limit);
   9012  1.484  knakahar 	mutex_exit(rxq->rxq_lock);
   9013  1.493  knakahar 
   9014  1.493  knakahar 	wm_txrxintr_enable(wmq);
   9015  1.484  knakahar }
   9016  1.484  knakahar 
   9017  1.335   msaitoh /*
   9018  1.335   msaitoh  * wm_linkintr_msix:
   9019  1.335   msaitoh  *
   9020  1.335   msaitoh  *	Interrupt service routine for link status change for MSI-X.
   9021  1.335   msaitoh  */
   9022  1.335   msaitoh static int
   9023  1.335   msaitoh wm_linkintr_msix(void *arg)
   9024  1.335   msaitoh {
   9025  1.335   msaitoh 	struct wm_softc *sc = arg;
   9026  1.351   msaitoh 	uint32_t reg;
   9027  1.335   msaitoh 
   9028  1.369  knakahar 	DPRINTF(WM_DEBUG_LINK,
   9029  1.335   msaitoh 	    ("%s: LINK: got link intr\n", device_xname(sc->sc_dev)));
   9030  1.335   msaitoh 
   9031  1.351   msaitoh 	reg = CSR_READ(sc, WMREG_ICR);
   9032  1.357  knakahar 	WM_CORE_LOCK(sc);
   9033  1.429  knakahar 	if ((sc->sc_core_stopping) || ((reg & ICR_LSC) == 0))
   9034  1.335   msaitoh 		goto out;
   9035  1.335   msaitoh 
   9036  1.335   msaitoh 	WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   9037  1.335   msaitoh 	wm_linkintr(sc, ICR_LSC);
   9038  1.335   msaitoh 
   9039  1.335   msaitoh out:
   9040  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   9041  1.335   msaitoh 
   9042  1.335   msaitoh 	if (sc->sc_type == WM_T_82574)
   9043  1.388   msaitoh 		CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC);
   9044  1.335   msaitoh 	else if (sc->sc_type == WM_T_82575)
   9045  1.335   msaitoh 		CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER);
   9046  1.335   msaitoh 	else
   9047  1.364  knakahar 		CSR_WRITE(sc, WMREG_EIMS, 1 << sc->sc_link_intr_idx);
   9048  1.335   msaitoh 
   9049  1.335   msaitoh 	return 1;
   9050  1.335   msaitoh }
   9051  1.335   msaitoh 
   9052  1.335   msaitoh /*
   9053  1.281   msaitoh  * Media related.
   9054  1.281   msaitoh  * GMII, SGMII, TBI (and SERDES)
   9055  1.281   msaitoh  */
   9056  1.117   msaitoh 
   9057  1.325   msaitoh /* Common */
   9058  1.325   msaitoh 
   9059  1.325   msaitoh /*
   9060  1.325   msaitoh  * wm_tbi_serdes_set_linkled:
   9061  1.325   msaitoh  *
   9062  1.325   msaitoh  *	Update the link LED on TBI and SERDES devices.
   9063  1.325   msaitoh  */
   9064  1.325   msaitoh static void
   9065  1.325   msaitoh wm_tbi_serdes_set_linkled(struct wm_softc *sc)
   9066  1.325   msaitoh {
   9067  1.325   msaitoh 
   9068  1.325   msaitoh 	if (sc->sc_tbi_linkup)
   9069  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SWDPIN(0);
   9070  1.325   msaitoh 	else
   9071  1.325   msaitoh 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
   9072  1.325   msaitoh 
   9073  1.325   msaitoh 	/* 82540 or newer devices are active low */
   9074  1.325   msaitoh 	sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0;
   9075  1.325   msaitoh 
   9076  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9077  1.325   msaitoh }
   9078  1.325   msaitoh 
   9079  1.281   msaitoh /* GMII related */
   9080  1.117   msaitoh 
   9081  1.280   msaitoh /*
   9082  1.281   msaitoh  * wm_gmii_reset:
   9083  1.280   msaitoh  *
   9084  1.281   msaitoh  *	Reset the PHY.
   9085  1.280   msaitoh  */
   9086  1.281   msaitoh static void
   9087  1.281   msaitoh wm_gmii_reset(struct wm_softc *sc)
   9088  1.280   msaitoh {
   9089  1.281   msaitoh 	uint32_t reg;
   9090  1.280   msaitoh 	int rv;
   9091  1.280   msaitoh 
   9092  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   9093  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   9094  1.420   msaitoh 
   9095  1.424   msaitoh 	rv = sc->phy.acquire(sc);
   9096  1.281   msaitoh 	if (rv != 0) {
   9097  1.281   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   9098  1.281   msaitoh 		    __func__);
   9099  1.281   msaitoh 		return;
   9100  1.281   msaitoh 	}
   9101  1.280   msaitoh 
   9102  1.281   msaitoh 	switch (sc->sc_type) {
   9103  1.281   msaitoh 	case WM_T_82542_2_0:
   9104  1.281   msaitoh 	case WM_T_82542_2_1:
   9105  1.281   msaitoh 		/* null */
   9106  1.281   msaitoh 		break;
   9107  1.281   msaitoh 	case WM_T_82543:
   9108  1.281   msaitoh 		/*
   9109  1.281   msaitoh 		 * With 82543, we need to force speed and duplex on the MAC
   9110  1.281   msaitoh 		 * equal to what the PHY speed and duplex configuration is.
   9111  1.281   msaitoh 		 * In addition, we need to perform a hardware reset on the PHY
   9112  1.281   msaitoh 		 * to take it out of reset.
   9113  1.281   msaitoh 		 */
   9114  1.281   msaitoh 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
   9115  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9116  1.280   msaitoh 
   9117  1.281   msaitoh 		/* The PHY reset pin is active-low. */
   9118  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   9119  1.281   msaitoh 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
   9120  1.281   msaitoh 		    CTRL_EXT_SWDPIN(4));
   9121  1.281   msaitoh 		reg |= CTRL_EXT_SWDPIO(4);
   9122  1.218   msaitoh 
   9123  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   9124  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9125  1.281   msaitoh 		delay(10*1000);
   9126  1.218   msaitoh 
   9127  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   9128  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9129  1.281   msaitoh 		delay(150);
   9130  1.281   msaitoh #if 0
   9131  1.281   msaitoh 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
   9132  1.281   msaitoh #endif
   9133  1.281   msaitoh 		delay(20*1000);	/* XXX extra delay to get PHY ID? */
   9134  1.281   msaitoh 		break;
   9135  1.281   msaitoh 	case WM_T_82544:	/* reset 10000us */
   9136  1.281   msaitoh 	case WM_T_82540:
   9137  1.281   msaitoh 	case WM_T_82545:
   9138  1.281   msaitoh 	case WM_T_82545_3:
   9139  1.281   msaitoh 	case WM_T_82546:
   9140  1.281   msaitoh 	case WM_T_82546_3:
   9141  1.281   msaitoh 	case WM_T_82541:
   9142  1.281   msaitoh 	case WM_T_82541_2:
   9143  1.281   msaitoh 	case WM_T_82547:
   9144  1.281   msaitoh 	case WM_T_82547_2:
   9145  1.281   msaitoh 	case WM_T_82571:	/* reset 100us */
   9146  1.281   msaitoh 	case WM_T_82572:
   9147  1.281   msaitoh 	case WM_T_82573:
   9148  1.281   msaitoh 	case WM_T_82574:
   9149  1.281   msaitoh 	case WM_T_82575:
   9150  1.281   msaitoh 	case WM_T_82576:
   9151  1.218   msaitoh 	case WM_T_82580:
   9152  1.228   msaitoh 	case WM_T_I350:
   9153  1.265   msaitoh 	case WM_T_I354:
   9154  1.281   msaitoh 	case WM_T_I210:
   9155  1.281   msaitoh 	case WM_T_I211:
   9156  1.281   msaitoh 	case WM_T_82583:
   9157  1.281   msaitoh 	case WM_T_80003:
   9158  1.281   msaitoh 		/* generic reset */
   9159  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   9160  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9161  1.281   msaitoh 		delay(20000);
   9162  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9163  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9164  1.281   msaitoh 		delay(20000);
   9165  1.281   msaitoh 
   9166  1.281   msaitoh 		if ((sc->sc_type == WM_T_82541)
   9167  1.281   msaitoh 		    || (sc->sc_type == WM_T_82541_2)
   9168  1.281   msaitoh 		    || (sc->sc_type == WM_T_82547)
   9169  1.281   msaitoh 		    || (sc->sc_type == WM_T_82547_2)) {
   9170  1.281   msaitoh 			/* workaround for igp are done in igp_reset() */
   9171  1.281   msaitoh 			/* XXX add code to set LED after phy reset */
   9172  1.218   msaitoh 		}
   9173  1.218   msaitoh 		break;
   9174  1.281   msaitoh 	case WM_T_ICH8:
   9175  1.281   msaitoh 	case WM_T_ICH9:
   9176  1.281   msaitoh 	case WM_T_ICH10:
   9177  1.281   msaitoh 	case WM_T_PCH:
   9178  1.281   msaitoh 	case WM_T_PCH2:
   9179  1.281   msaitoh 	case WM_T_PCH_LPT:
   9180  1.392   msaitoh 	case WM_T_PCH_SPT:
   9181  1.281   msaitoh 		/* generic reset */
   9182  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   9183  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9184  1.281   msaitoh 		delay(100);
   9185  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9186  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9187  1.281   msaitoh 		delay(150);
   9188  1.281   msaitoh 		break;
   9189  1.281   msaitoh 	default:
   9190  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   9191  1.281   msaitoh 		    __func__);
   9192  1.281   msaitoh 		break;
   9193  1.281   msaitoh 	}
   9194  1.281   msaitoh 
   9195  1.424   msaitoh 	sc->phy.release(sc);
   9196  1.210   msaitoh 
   9197  1.281   msaitoh 	/* get_cfg_done */
   9198  1.281   msaitoh 	wm_get_cfg_done(sc);
   9199  1.208   msaitoh 
   9200  1.281   msaitoh 	/* extra setup */
   9201  1.281   msaitoh 	switch (sc->sc_type) {
   9202  1.281   msaitoh 	case WM_T_82542_2_0:
   9203  1.281   msaitoh 	case WM_T_82542_2_1:
   9204  1.281   msaitoh 	case WM_T_82543:
   9205  1.281   msaitoh 	case WM_T_82544:
   9206  1.281   msaitoh 	case WM_T_82540:
   9207  1.281   msaitoh 	case WM_T_82545:
   9208  1.281   msaitoh 	case WM_T_82545_3:
   9209  1.281   msaitoh 	case WM_T_82546:
   9210  1.281   msaitoh 	case WM_T_82546_3:
   9211  1.281   msaitoh 	case WM_T_82541_2:
   9212  1.281   msaitoh 	case WM_T_82547_2:
   9213  1.281   msaitoh 	case WM_T_82571:
   9214  1.281   msaitoh 	case WM_T_82572:
   9215  1.281   msaitoh 	case WM_T_82573:
   9216  1.519   msaitoh 	case WM_T_82574:
   9217  1.519   msaitoh 	case WM_T_82583:
   9218  1.281   msaitoh 	case WM_T_82575:
   9219  1.281   msaitoh 	case WM_T_82576:
   9220  1.281   msaitoh 	case WM_T_82580:
   9221  1.281   msaitoh 	case WM_T_I350:
   9222  1.281   msaitoh 	case WM_T_I354:
   9223  1.281   msaitoh 	case WM_T_I210:
   9224  1.281   msaitoh 	case WM_T_I211:
   9225  1.281   msaitoh 	case WM_T_80003:
   9226  1.281   msaitoh 		/* null */
   9227  1.281   msaitoh 		break;
   9228  1.281   msaitoh 	case WM_T_82541:
   9229  1.281   msaitoh 	case WM_T_82547:
   9230  1.281   msaitoh 		/* XXX Configure actively LED after PHY reset */
   9231  1.281   msaitoh 		break;
   9232  1.281   msaitoh 	case WM_T_ICH8:
   9233  1.281   msaitoh 	case WM_T_ICH9:
   9234  1.281   msaitoh 	case WM_T_ICH10:
   9235  1.281   msaitoh 	case WM_T_PCH:
   9236  1.281   msaitoh 	case WM_T_PCH2:
   9237  1.281   msaitoh 	case WM_T_PCH_LPT:
   9238  1.392   msaitoh 	case WM_T_PCH_SPT:
   9239  1.517   msaitoh 		wm_phy_post_reset(sc);
   9240  1.281   msaitoh 		break;
   9241  1.281   msaitoh 	default:
   9242  1.281   msaitoh 		panic("%s: unknown type\n", __func__);
   9243  1.281   msaitoh 		break;
   9244    1.1   thorpej 	}
   9245    1.1   thorpej }
   9246    1.1   thorpej 
   9247    1.1   thorpej /*
   9248  1.475   msaitoh  * Setup sc_phytype and mii_{read|write}reg.
   9249  1.475   msaitoh  *
   9250  1.475   msaitoh  *  To identify PHY type, correct read/write function should be selected.
   9251  1.475   msaitoh  * To select correct read/write function, PCI ID or MAC type are required
   9252  1.475   msaitoh  * without accessing PHY registers.
   9253  1.475   msaitoh  *
   9254  1.475   msaitoh  *  On the first call of this function, PHY ID is not known yet. Check
   9255  1.475   msaitoh  * PCI ID or MAC type. The list of the PCI ID may not be perfect, so the
   9256  1.475   msaitoh  * result might be incorrect.
   9257  1.475   msaitoh  *
   9258  1.475   msaitoh  *  In the second call, PHY OUI and model is used to identify PHY type.
   9259  1.475   msaitoh  * It might not be perfpect because of the lack of compared entry, but it
   9260  1.475   msaitoh  * would be better than the first call.
   9261  1.475   msaitoh  *
   9262  1.475   msaitoh  *  If the detected new result and previous assumption is different,
   9263  1.475   msaitoh  * diagnous message will be printed.
   9264  1.475   msaitoh  */
   9265  1.475   msaitoh static void
   9266  1.475   msaitoh wm_gmii_setup_phytype(struct wm_softc *sc, uint32_t phy_oui,
   9267  1.475   msaitoh     uint16_t phy_model)
   9268  1.475   msaitoh {
   9269  1.475   msaitoh 	device_t dev = sc->sc_dev;
   9270  1.475   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   9271  1.475   msaitoh 	uint16_t new_phytype = WMPHY_UNKNOWN;
   9272  1.475   msaitoh 	uint16_t doubt_phytype = WMPHY_UNKNOWN;
   9273  1.475   msaitoh 	mii_readreg_t new_readreg;
   9274  1.475   msaitoh 	mii_writereg_t new_writereg;
   9275  1.475   msaitoh 
   9276  1.521   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   9277  1.521   msaitoh 		device_xname(sc->sc_dev), __func__));
   9278  1.521   msaitoh 
   9279  1.475   msaitoh 	if (mii->mii_readreg == NULL) {
   9280  1.475   msaitoh 		/*
   9281  1.475   msaitoh 		 *  This is the first call of this function. For ICH and PCH
   9282  1.475   msaitoh 		 * variants, it's difficult to determine the PHY access method
   9283  1.475   msaitoh 		 * by sc_type, so use the PCI product ID for some devices.
   9284  1.475   msaitoh 		 */
   9285  1.475   msaitoh 
   9286  1.475   msaitoh 		switch (sc->sc_pcidevid) {
   9287  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_M_LM:
   9288  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_M_LC:
   9289  1.475   msaitoh 			/* 82577 */
   9290  1.475   msaitoh 			new_phytype = WMPHY_82577;
   9291  1.475   msaitoh 			break;
   9292  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_D_DM:
   9293  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_D_DC:
   9294  1.475   msaitoh 			/* 82578 */
   9295  1.475   msaitoh 			new_phytype = WMPHY_82578;
   9296  1.475   msaitoh 			break;
   9297  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH2_LV_LM:
   9298  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH2_LV_V:
   9299  1.475   msaitoh 			/* 82579 */
   9300  1.475   msaitoh 			new_phytype = WMPHY_82579;
   9301  1.475   msaitoh 			break;
   9302  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801H_82567V_3:
   9303  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801I_BM:
   9304  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801I_IGP_M_AMT: /* Not IGP but BM */
   9305  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_LM:
   9306  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_LF:
   9307  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_D_BM_LM:
   9308  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_D_BM_LF:
   9309  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_V:
   9310  1.475   msaitoh 			/* ICH8, 9, 10 with 82567 */
   9311  1.475   msaitoh 			new_phytype = WMPHY_BM;
   9312  1.475   msaitoh 			break;
   9313  1.475   msaitoh 		default:
   9314  1.475   msaitoh 			break;
   9315  1.475   msaitoh 		}
   9316  1.475   msaitoh 	} else {
   9317  1.475   msaitoh 		/* It's not the first call. Use PHY OUI and model */
   9318  1.475   msaitoh 		switch (phy_oui) {
   9319  1.475   msaitoh 		case MII_OUI_ATHEROS: /* XXX ??? */
   9320  1.475   msaitoh 			switch (phy_model) {
   9321  1.475   msaitoh 			case 0x0004: /* XXX */
   9322  1.475   msaitoh 				new_phytype = WMPHY_82578;
   9323  1.475   msaitoh 				break;
   9324  1.475   msaitoh 			default:
   9325  1.475   msaitoh 				break;
   9326  1.475   msaitoh 			}
   9327  1.475   msaitoh 			break;
   9328  1.475   msaitoh 		case MII_OUI_xxMARVELL:
   9329  1.475   msaitoh 			switch (phy_model) {
   9330  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I210:
   9331  1.475   msaitoh 				new_phytype = WMPHY_I210;
   9332  1.475   msaitoh 				break;
   9333  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1011:
   9334  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1000_3:
   9335  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1000_5:
   9336  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1112:
   9337  1.475   msaitoh 				new_phytype = WMPHY_M88;
   9338  1.475   msaitoh 				break;
   9339  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1149:
   9340  1.475   msaitoh 				new_phytype = WMPHY_BM;
   9341  1.475   msaitoh 				break;
   9342  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1111:
   9343  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I347:
   9344  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1512:
   9345  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1340M:
   9346  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1543:
   9347  1.475   msaitoh 				new_phytype = WMPHY_M88;
   9348  1.475   msaitoh 				break;
   9349  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I82563:
   9350  1.475   msaitoh 				new_phytype = WMPHY_GG82563;
   9351  1.475   msaitoh 				break;
   9352  1.475   msaitoh 			default:
   9353  1.475   msaitoh 				break;
   9354  1.475   msaitoh 			}
   9355  1.475   msaitoh 			break;
   9356  1.475   msaitoh 		case MII_OUI_INTEL:
   9357  1.475   msaitoh 			switch (phy_model) {
   9358  1.475   msaitoh 			case MII_MODEL_INTEL_I82577:
   9359  1.475   msaitoh 				new_phytype = WMPHY_82577;
   9360  1.475   msaitoh 				break;
   9361  1.475   msaitoh 			case MII_MODEL_INTEL_I82579:
   9362  1.475   msaitoh 				new_phytype = WMPHY_82579;
   9363  1.475   msaitoh 				break;
   9364  1.475   msaitoh 			case MII_MODEL_INTEL_I217:
   9365  1.475   msaitoh 				new_phytype = WMPHY_I217;
   9366  1.475   msaitoh 				break;
   9367  1.475   msaitoh 			case MII_MODEL_INTEL_I82580:
   9368  1.475   msaitoh 			case MII_MODEL_INTEL_I350:
   9369  1.475   msaitoh 				new_phytype = WMPHY_82580;
   9370  1.475   msaitoh 				break;
   9371  1.475   msaitoh 			default:
   9372  1.475   msaitoh 				break;
   9373  1.475   msaitoh 			}
   9374  1.475   msaitoh 			break;
   9375  1.475   msaitoh 		case MII_OUI_yyINTEL:
   9376  1.475   msaitoh 			switch (phy_model) {
   9377  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562G:
   9378  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562EM:
   9379  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562ET:
   9380  1.475   msaitoh 				new_phytype = WMPHY_IFE;
   9381  1.475   msaitoh 				break;
   9382  1.475   msaitoh 			case MII_MODEL_yyINTEL_IGP01E1000:
   9383  1.475   msaitoh 				new_phytype = WMPHY_IGP;
   9384  1.475   msaitoh 				break;
   9385  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82566:
   9386  1.475   msaitoh 				new_phytype = WMPHY_IGP_3;
   9387  1.475   msaitoh 				break;
   9388  1.475   msaitoh 			default:
   9389  1.475   msaitoh 				break;
   9390  1.475   msaitoh 			}
   9391  1.475   msaitoh 			break;
   9392  1.475   msaitoh 		default:
   9393  1.475   msaitoh 			break;
   9394  1.475   msaitoh 		}
   9395  1.475   msaitoh 		if (new_phytype == WMPHY_UNKNOWN)
   9396  1.475   msaitoh 			aprint_verbose_dev(dev, "%s: unknown PHY model\n",
   9397  1.475   msaitoh 			    __func__);
   9398  1.475   msaitoh 
   9399  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9400  1.475   msaitoh 		    && (sc->sc_phytype != new_phytype )) {
   9401  1.475   msaitoh 			aprint_error_dev(dev, "Previously assumed PHY type(%u)"
   9402  1.475   msaitoh 			    "was incorrect. PHY type from PHY ID = %u\n",
   9403  1.475   msaitoh 			    sc->sc_phytype, new_phytype);
   9404  1.475   msaitoh 		}
   9405  1.475   msaitoh 	}
   9406  1.475   msaitoh 
   9407  1.475   msaitoh 	/* Next, use sc->sc_flags and sc->sc_type to set read/write funcs. */
   9408  1.475   msaitoh 	if (((sc->sc_flags & WM_F_SGMII) != 0) && !wm_sgmii_uses_mdio(sc)) {
   9409  1.475   msaitoh 		/* SGMII */
   9410  1.475   msaitoh 		new_readreg = wm_sgmii_readreg;
   9411  1.475   msaitoh 		new_writereg = wm_sgmii_writereg;
   9412  1.475   msaitoh 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
   9413  1.475   msaitoh 		/* BM2 (phyaddr == 1) */
   9414  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9415  1.475   msaitoh 		    && (new_phytype != WMPHY_BM)
   9416  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9417  1.475   msaitoh 			doubt_phytype = new_phytype;
   9418  1.475   msaitoh 		new_phytype = WMPHY_BM;
   9419  1.475   msaitoh 		new_readreg = wm_gmii_bm_readreg;
   9420  1.475   msaitoh 		new_writereg = wm_gmii_bm_writereg;
   9421  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_PCH) {
   9422  1.475   msaitoh 		/* All PCH* use _hv_ */
   9423  1.475   msaitoh 		new_readreg = wm_gmii_hv_readreg;
   9424  1.475   msaitoh 		new_writereg = wm_gmii_hv_writereg;
   9425  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_ICH8) {
   9426  1.475   msaitoh 		/* non-82567 ICH8, 9 and 10 */
   9427  1.475   msaitoh 		new_readreg = wm_gmii_i82544_readreg;
   9428  1.475   msaitoh 		new_writereg = wm_gmii_i82544_writereg;
   9429  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_80003) {
   9430  1.475   msaitoh 		/* 80003 */
   9431  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9432  1.475   msaitoh 		    && (new_phytype != WMPHY_GG82563)
   9433  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9434  1.475   msaitoh 			doubt_phytype = new_phytype;
   9435  1.475   msaitoh 		new_phytype = WMPHY_GG82563;
   9436  1.475   msaitoh 		new_readreg = wm_gmii_i80003_readreg;
   9437  1.475   msaitoh 		new_writereg = wm_gmii_i80003_writereg;
   9438  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_I210) {
   9439  1.475   msaitoh 		/* I210 and I211 */
   9440  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9441  1.475   msaitoh 		    && (new_phytype != WMPHY_I210)
   9442  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9443  1.475   msaitoh 			doubt_phytype = new_phytype;
   9444  1.475   msaitoh 		new_phytype = WMPHY_I210;
   9445  1.475   msaitoh 		new_readreg = wm_gmii_gs40g_readreg;
   9446  1.475   msaitoh 		new_writereg = wm_gmii_gs40g_writereg;
   9447  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_82580) {
   9448  1.475   msaitoh 		/* 82580, I350 and I354 */
   9449  1.475   msaitoh 		new_readreg = wm_gmii_82580_readreg;
   9450  1.475   msaitoh 		new_writereg = wm_gmii_82580_writereg;
   9451  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_82544) {
   9452  1.475   msaitoh 		/* 82544, 0, [56], [17], 8257[1234] and 82583 */
   9453  1.475   msaitoh 		new_readreg = wm_gmii_i82544_readreg;
   9454  1.475   msaitoh 		new_writereg = wm_gmii_i82544_writereg;
   9455  1.475   msaitoh 	} else {
   9456  1.475   msaitoh 		new_readreg = wm_gmii_i82543_readreg;
   9457  1.475   msaitoh 		new_writereg = wm_gmii_i82543_writereg;
   9458  1.475   msaitoh 	}
   9459  1.475   msaitoh 
   9460  1.475   msaitoh 	if (new_phytype == WMPHY_BM) {
   9461  1.475   msaitoh 		/* All BM use _bm_ */
   9462  1.475   msaitoh 		new_readreg = wm_gmii_bm_readreg;
   9463  1.475   msaitoh 		new_writereg = wm_gmii_bm_writereg;
   9464  1.475   msaitoh 	}
   9465  1.475   msaitoh 	if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_SPT)) {
   9466  1.475   msaitoh 		/* All PCH* use _hv_ */
   9467  1.475   msaitoh 		new_readreg = wm_gmii_hv_readreg;
   9468  1.475   msaitoh 		new_writereg = wm_gmii_hv_writereg;
   9469  1.475   msaitoh 	}
   9470  1.475   msaitoh 
   9471  1.475   msaitoh 	/* Diag output */
   9472  1.475   msaitoh 	if (doubt_phytype != WMPHY_UNKNOWN)
   9473  1.475   msaitoh 		aprint_error_dev(dev, "Assumed new PHY type was "
   9474  1.475   msaitoh 		    "incorrect. old = %u, new = %u\n", sc->sc_phytype,
   9475  1.475   msaitoh 		    new_phytype);
   9476  1.475   msaitoh 	else if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9477  1.475   msaitoh 	    && (sc->sc_phytype != new_phytype ))
   9478  1.475   msaitoh 		aprint_error_dev(dev, "Previously assumed PHY type(%u)"
   9479  1.475   msaitoh 		    "was incorrect. New PHY type = %u\n",
   9480  1.475   msaitoh 		    sc->sc_phytype, new_phytype);
   9481  1.475   msaitoh 
   9482  1.475   msaitoh 	if ((mii->mii_readreg != NULL) && (new_phytype == WMPHY_UNKNOWN))
   9483  1.475   msaitoh 		aprint_error_dev(dev, "PHY type is still unknown.\n");
   9484  1.475   msaitoh 
   9485  1.475   msaitoh 	if ((mii->mii_readreg != NULL) && (mii->mii_readreg != new_readreg))
   9486  1.475   msaitoh 		aprint_error_dev(dev, "Previously assumed PHY read/write "
   9487  1.475   msaitoh 		    "function was incorrect.\n");
   9488  1.475   msaitoh 
   9489  1.475   msaitoh 	/* Update now */
   9490  1.475   msaitoh 	sc->sc_phytype = new_phytype;
   9491  1.475   msaitoh 	mii->mii_readreg = new_readreg;
   9492  1.475   msaitoh 	mii->mii_writereg = new_writereg;
   9493  1.475   msaitoh }
   9494  1.475   msaitoh 
   9495  1.475   msaitoh /*
   9496  1.281   msaitoh  * wm_get_phy_id_82575:
   9497    1.1   thorpej  *
   9498  1.281   msaitoh  * Return PHY ID. Return -1 if it failed.
   9499    1.1   thorpej  */
   9500  1.281   msaitoh static int
   9501  1.281   msaitoh wm_get_phy_id_82575(struct wm_softc *sc)
   9502    1.1   thorpej {
   9503  1.281   msaitoh 	uint32_t reg;
   9504  1.281   msaitoh 	int phyid = -1;
   9505  1.281   msaitoh 
   9506  1.281   msaitoh 	/* XXX */
   9507  1.281   msaitoh 	if ((sc->sc_flags & WM_F_SGMII) == 0)
   9508  1.281   msaitoh 		return -1;
   9509    1.1   thorpej 
   9510  1.281   msaitoh 	if (wm_sgmii_uses_mdio(sc)) {
   9511  1.281   msaitoh 		switch (sc->sc_type) {
   9512  1.281   msaitoh 		case WM_T_82575:
   9513  1.281   msaitoh 		case WM_T_82576:
   9514  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_MDIC);
   9515  1.281   msaitoh 			phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT;
   9516  1.281   msaitoh 			break;
   9517  1.281   msaitoh 		case WM_T_82580:
   9518  1.281   msaitoh 		case WM_T_I350:
   9519  1.281   msaitoh 		case WM_T_I354:
   9520  1.281   msaitoh 		case WM_T_I210:
   9521  1.281   msaitoh 		case WM_T_I211:
   9522  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_MDICNFG);
   9523  1.281   msaitoh 			phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT;
   9524  1.281   msaitoh 			break;
   9525  1.281   msaitoh 		default:
   9526  1.281   msaitoh 			return -1;
   9527  1.281   msaitoh 		}
   9528  1.139    bouyer 	}
   9529    1.1   thorpej 
   9530  1.281   msaitoh 	return phyid;
   9531    1.1   thorpej }
   9532    1.1   thorpej 
   9533  1.281   msaitoh 
   9534    1.1   thorpej /*
   9535  1.281   msaitoh  * wm_gmii_mediainit:
   9536    1.1   thorpej  *
   9537  1.281   msaitoh  *	Initialize media for use on 1000BASE-T devices.
   9538    1.1   thorpej  */
   9539   1.47   thorpej static void
   9540  1.281   msaitoh wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
   9541    1.1   thorpej {
   9542  1.475   msaitoh 	device_t dev = sc->sc_dev;
   9543    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   9544  1.281   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   9545  1.282   msaitoh 	uint32_t reg;
   9546  1.281   msaitoh 
   9547  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   9548  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   9549  1.425   msaitoh 
   9550  1.292   msaitoh 	/* We have GMII. */
   9551  1.281   msaitoh 	sc->sc_flags |= WM_F_HAS_MII;
   9552    1.1   thorpej 
   9553  1.281   msaitoh 	if (sc->sc_type == WM_T_80003)
   9554  1.281   msaitoh 		sc->sc_tipg =  TIPG_1000T_80003_DFLT;
   9555    1.1   thorpej 	else
   9556  1.281   msaitoh 		sc->sc_tipg = TIPG_1000T_DFLT;
   9557    1.1   thorpej 
   9558  1.282   msaitoh 	/* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */
   9559  1.300   msaitoh 	if ((sc->sc_type == WM_T_82580)
   9560  1.282   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210)
   9561  1.282   msaitoh 	    || (sc->sc_type == WM_T_I211)) {
   9562  1.282   msaitoh 		reg = CSR_READ(sc, WMREG_PHPM);
   9563  1.282   msaitoh 		reg &= ~PHPM_GO_LINK_D;
   9564  1.282   msaitoh 		CSR_WRITE(sc, WMREG_PHPM, reg);
   9565  1.282   msaitoh 	}
   9566  1.282   msaitoh 
   9567  1.281   msaitoh 	/*
   9568  1.281   msaitoh 	 * Let the chip set speed/duplex on its own based on
   9569  1.281   msaitoh 	 * signals from the PHY.
   9570  1.281   msaitoh 	 * XXXbouyer - I'm not sure this is right for the 80003,
   9571  1.281   msaitoh 	 * the em driver only sets CTRL_SLU here - but it seems to work.
   9572  1.281   msaitoh 	 */
   9573  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   9574  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9575    1.1   thorpej 
   9576  1.281   msaitoh 	/* Initialize our media structures and probe the GMII. */
   9577  1.281   msaitoh 	mii->mii_ifp = ifp;
   9578    1.1   thorpej 
   9579  1.281   msaitoh 	mii->mii_statchg = wm_gmii_statchg;
   9580    1.1   thorpej 
   9581  1.448   msaitoh 	/* get PHY control from SMBus to PCIe */
   9582  1.448   msaitoh 	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
   9583  1.448   msaitoh 	    || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT))
   9584  1.448   msaitoh 		wm_smbustopci(sc);
   9585  1.448   msaitoh 
   9586  1.281   msaitoh 	wm_gmii_reset(sc);
   9587    1.1   thorpej 
   9588  1.281   msaitoh 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   9589  1.327   msaitoh 	ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange,
   9590  1.327   msaitoh 	    wm_gmii_mediastatus);
   9591    1.1   thorpej 
   9592  1.281   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   9593  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   9594  1.281   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   9595  1.281   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) {
   9596  1.281   msaitoh 		if ((sc->sc_flags & WM_F_SGMII) == 0) {
   9597  1.281   msaitoh 			/* Attach only one port */
   9598  1.281   msaitoh 			mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
   9599  1.281   msaitoh 			    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9600  1.281   msaitoh 		} else {
   9601  1.281   msaitoh 			int i, id;
   9602  1.281   msaitoh 			uint32_t ctrl_ext;
   9603    1.1   thorpej 
   9604  1.281   msaitoh 			id = wm_get_phy_id_82575(sc);
   9605  1.281   msaitoh 			if (id != -1) {
   9606  1.281   msaitoh 				mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
   9607  1.281   msaitoh 				    id, MII_OFFSET_ANY, MIIF_DOPAUSE);
   9608  1.281   msaitoh 			}
   9609  1.281   msaitoh 			if ((id == -1)
   9610  1.281   msaitoh 			    || (LIST_FIRST(&mii->mii_phys) == NULL)) {
   9611  1.281   msaitoh 				/* Power on sgmii phy if it is disabled */
   9612  1.281   msaitoh 				ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   9613  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL_EXT,
   9614  1.281   msaitoh 				    ctrl_ext &~ CTRL_EXT_SWDPIN(3));
   9615  1.281   msaitoh 				CSR_WRITE_FLUSH(sc);
   9616  1.281   msaitoh 				delay(300*1000); /* XXX too long */
   9617    1.1   thorpej 
   9618  1.281   msaitoh 				/* from 1 to 8 */
   9619  1.281   msaitoh 				for (i = 1; i < 8; i++)
   9620  1.281   msaitoh 					mii_attach(sc->sc_dev, &sc->sc_mii,
   9621  1.281   msaitoh 					    0xffffffff, i, MII_OFFSET_ANY,
   9622  1.281   msaitoh 					    MIIF_DOPAUSE);
   9623    1.1   thorpej 
   9624  1.281   msaitoh 				/* restore previous sfp cage power state */
   9625  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   9626  1.281   msaitoh 			}
   9627  1.281   msaitoh 		}
   9628  1.281   msaitoh 	} else {
   9629  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9630  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9631  1.281   msaitoh 	}
   9632  1.173   msaitoh 
   9633  1.281   msaitoh 	/*
   9634  1.281   msaitoh 	 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
   9635  1.281   msaitoh 	 * wm_set_mdio_slow_mode_hv() for a workaround and retry.
   9636  1.281   msaitoh 	 */
   9637  1.281   msaitoh 	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) &&
   9638  1.281   msaitoh 	    (LIST_FIRST(&mii->mii_phys) == NULL)) {
   9639  1.281   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   9640  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9641  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9642  1.281   msaitoh 	}
   9643    1.1   thorpej 
   9644    1.1   thorpej 	/*
   9645  1.281   msaitoh 	 * (For ICH8 variants)
   9646  1.281   msaitoh 	 * If PHY detection failed, use BM's r/w function and retry.
   9647    1.1   thorpej 	 */
   9648  1.281   msaitoh 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
   9649  1.281   msaitoh 		/* if failed, retry with *_bm_* */
   9650  1.475   msaitoh 		aprint_verbose_dev(dev, "Assumed PHY access function "
   9651  1.475   msaitoh 		    "(type = %d) might be incorrect. Use BM and retry.\n",
   9652  1.475   msaitoh 		    sc->sc_phytype);
   9653  1.475   msaitoh 		sc->sc_phytype = WMPHY_BM;
   9654  1.281   msaitoh 		mii->mii_readreg = wm_gmii_bm_readreg;
   9655  1.281   msaitoh 		mii->mii_writereg = wm_gmii_bm_writereg;
   9656    1.1   thorpej 
   9657  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9658  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9659  1.281   msaitoh 	}
   9660    1.1   thorpej 
   9661  1.281   msaitoh 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
   9662  1.281   msaitoh 		/* Any PHY wasn't find */
   9663  1.388   msaitoh 		ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
   9664  1.388   msaitoh 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
   9665  1.281   msaitoh 		sc->sc_phytype = WMPHY_NONE;
   9666  1.281   msaitoh 	} else {
   9667  1.475   msaitoh 		struct mii_softc *child = LIST_FIRST(&mii->mii_phys);
   9668  1.475   msaitoh 
   9669  1.281   msaitoh 		/*
   9670  1.475   msaitoh 		 * PHY Found! Check PHY type again by the second call of
   9671  1.527   msaitoh 		 * wm_gmii_setup_phytype.
   9672  1.281   msaitoh 		 */
   9673  1.475   msaitoh 		wm_gmii_setup_phytype(sc, child->mii_mpd_oui,
   9674  1.475   msaitoh 		    child->mii_mpd_model);
   9675    1.1   thorpej 
   9676  1.281   msaitoh 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
   9677  1.281   msaitoh 	}
   9678    1.1   thorpej }
   9679    1.1   thorpej 
   9680    1.1   thorpej /*
   9681  1.281   msaitoh  * wm_gmii_mediachange:	[ifmedia interface function]
   9682    1.1   thorpej  *
   9683  1.281   msaitoh  *	Set hardware to newly-selected media on a 1000BASE-T device.
   9684    1.1   thorpej  */
   9685   1.47   thorpej static int
   9686  1.281   msaitoh wm_gmii_mediachange(struct ifnet *ifp)
   9687    1.1   thorpej {
   9688    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   9689    1.1   thorpej 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   9690  1.281   msaitoh 	int rc;
   9691    1.1   thorpej 
   9692  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   9693  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   9694  1.281   msaitoh 	if ((ifp->if_flags & IFF_UP) == 0)
   9695  1.279   msaitoh 		return 0;
   9696  1.279   msaitoh 
   9697  1.517   msaitoh 	/* Disable D0 LPLU. */
   9698  1.519   msaitoh 	wm_lplu_d0_disable(sc);
   9699  1.517   msaitoh 
   9700  1.281   msaitoh 	sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
   9701  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   9702  1.281   msaitoh 	if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   9703  1.281   msaitoh 	    || (sc->sc_type > WM_T_82543)) {
   9704  1.281   msaitoh 		sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX);
   9705  1.134   msaitoh 	} else {
   9706  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_ASDE;
   9707  1.281   msaitoh 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
   9708  1.281   msaitoh 		if (ife->ifm_media & IFM_FDX)
   9709  1.281   msaitoh 			sc->sc_ctrl |= CTRL_FD;
   9710  1.281   msaitoh 		switch (IFM_SUBTYPE(ife->ifm_media)) {
   9711  1.281   msaitoh 		case IFM_10_T:
   9712  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_10;
   9713  1.281   msaitoh 			break;
   9714  1.281   msaitoh 		case IFM_100_TX:
   9715  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_100;
   9716  1.281   msaitoh 			break;
   9717  1.281   msaitoh 		case IFM_1000_T:
   9718  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_1000;
   9719  1.281   msaitoh 			break;
   9720  1.281   msaitoh 		default:
   9721  1.281   msaitoh 			panic("wm_gmii_mediachange: bad media 0x%x",
   9722  1.281   msaitoh 			    ife->ifm_media);
   9723  1.281   msaitoh 		}
   9724  1.134   msaitoh 	}
   9725  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9726  1.515   msaitoh 	CSR_WRITE_FLUSH(sc);
   9727  1.281   msaitoh 	if (sc->sc_type <= WM_T_82543)
   9728  1.281   msaitoh 		wm_gmii_reset(sc);
   9729  1.281   msaitoh 
   9730  1.281   msaitoh 	if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
   9731  1.281   msaitoh 		return 0;
   9732  1.281   msaitoh 	return rc;
   9733  1.281   msaitoh }
   9734    1.1   thorpej 
   9735  1.324   msaitoh /*
   9736  1.324   msaitoh  * wm_gmii_mediastatus:	[ifmedia interface function]
   9737  1.324   msaitoh  *
   9738  1.324   msaitoh  *	Get the current interface media status on a 1000BASE-T device.
   9739  1.324   msaitoh  */
   9740  1.324   msaitoh static void
   9741  1.324   msaitoh wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   9742  1.324   msaitoh {
   9743  1.324   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   9744  1.324   msaitoh 
   9745  1.324   msaitoh 	ether_mediastatus(ifp, ifmr);
   9746  1.324   msaitoh 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
   9747  1.324   msaitoh 	    | sc->sc_flowflags;
   9748  1.324   msaitoh }
   9749  1.324   msaitoh 
   9750  1.281   msaitoh #define	MDI_IO		CTRL_SWDPIN(2)
   9751  1.281   msaitoh #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
   9752  1.281   msaitoh #define	MDI_CLK		CTRL_SWDPIN(3)
   9753    1.1   thorpej 
   9754  1.281   msaitoh static void
   9755  1.281   msaitoh wm_i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
   9756  1.281   msaitoh {
   9757  1.281   msaitoh 	uint32_t i, v;
   9758  1.134   msaitoh 
   9759  1.281   msaitoh 	v = CSR_READ(sc, WMREG_CTRL);
   9760  1.388   msaitoh 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   9761  1.281   msaitoh 	v |= MDI_DIR | CTRL_SWDPIO(3);
   9762  1.134   msaitoh 
   9763  1.281   msaitoh 	for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
   9764  1.281   msaitoh 		if (data & i)
   9765  1.281   msaitoh 			v |= MDI_IO;
   9766  1.281   msaitoh 		else
   9767  1.281   msaitoh 			v &= ~MDI_IO;
   9768  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9769  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9770  1.281   msaitoh 		delay(10);
   9771  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9772  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9773  1.281   msaitoh 		delay(10);
   9774  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9775  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9776  1.281   msaitoh 		delay(10);
   9777  1.281   msaitoh 	}
   9778  1.281   msaitoh }
   9779  1.134   msaitoh 
   9780  1.281   msaitoh static uint32_t
   9781  1.281   msaitoh wm_i82543_mii_recvbits(struct wm_softc *sc)
   9782  1.281   msaitoh {
   9783  1.281   msaitoh 	uint32_t v, i, data = 0;
   9784    1.1   thorpej 
   9785  1.281   msaitoh 	v = CSR_READ(sc, WMREG_CTRL);
   9786  1.388   msaitoh 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   9787  1.281   msaitoh 	v |= CTRL_SWDPIO(3);
   9788  1.134   msaitoh 
   9789  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9790  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9791  1.281   msaitoh 	delay(10);
   9792  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9793  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9794  1.281   msaitoh 	delay(10);
   9795  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9796  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9797  1.281   msaitoh 	delay(10);
   9798  1.173   msaitoh 
   9799  1.281   msaitoh 	for (i = 0; i < 16; i++) {
   9800  1.281   msaitoh 		data <<= 1;
   9801  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9802  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9803  1.281   msaitoh 		delay(10);
   9804  1.281   msaitoh 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
   9805  1.281   msaitoh 			data |= 1;
   9806  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9807  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9808  1.281   msaitoh 		delay(10);
   9809    1.1   thorpej 	}
   9810    1.1   thorpej 
   9811  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9812  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9813  1.281   msaitoh 	delay(10);
   9814  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9815  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9816  1.281   msaitoh 	delay(10);
   9817    1.1   thorpej 
   9818  1.281   msaitoh 	return data;
   9819    1.1   thorpej }
   9820    1.1   thorpej 
   9821  1.281   msaitoh #undef MDI_IO
   9822  1.281   msaitoh #undef MDI_DIR
   9823  1.281   msaitoh #undef MDI_CLK
   9824  1.281   msaitoh 
   9825    1.1   thorpej /*
   9826  1.281   msaitoh  * wm_gmii_i82543_readreg:	[mii interface function]
   9827    1.1   thorpej  *
   9828  1.281   msaitoh  *	Read a PHY register on the GMII (i82543 version).
   9829    1.1   thorpej  */
   9830  1.281   msaitoh static int
   9831  1.521   msaitoh wm_gmii_i82543_readreg(device_t dev, int phy, int reg)
   9832    1.1   thorpej {
   9833  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9834  1.281   msaitoh 	int rv;
   9835    1.1   thorpej 
   9836  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
   9837  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, reg | (phy << 5) |
   9838  1.281   msaitoh 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
   9839  1.281   msaitoh 	rv = wm_i82543_mii_recvbits(sc) & 0xffff;
   9840    1.1   thorpej 
   9841  1.388   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
   9842  1.521   msaitoh 	    device_xname(dev), phy, reg, rv));
   9843  1.173   msaitoh 
   9844  1.281   msaitoh 	return rv;
   9845    1.1   thorpej }
   9846    1.1   thorpej 
   9847    1.1   thorpej /*
   9848  1.281   msaitoh  * wm_gmii_i82543_writereg:	[mii interface function]
   9849    1.1   thorpej  *
   9850  1.281   msaitoh  *	Write a PHY register on the GMII (i82543 version).
   9851    1.1   thorpej  */
   9852   1.47   thorpej static void
   9853  1.521   msaitoh wm_gmii_i82543_writereg(device_t dev, int phy, int reg, int val)
   9854    1.1   thorpej {
   9855  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9856    1.1   thorpej 
   9857  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
   9858  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
   9859  1.281   msaitoh 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
   9860  1.281   msaitoh 	    (MII_COMMAND_START << 30), 32);
   9861  1.281   msaitoh }
   9862  1.272     ozaki 
   9863  1.281   msaitoh /*
   9864  1.424   msaitoh  * wm_gmii_mdic_readreg:	[mii interface function]
   9865  1.281   msaitoh  *
   9866  1.281   msaitoh  *	Read a PHY register on the GMII.
   9867  1.281   msaitoh  */
   9868  1.281   msaitoh static int
   9869  1.521   msaitoh wm_gmii_mdic_readreg(device_t dev, int phy, int reg)
   9870  1.281   msaitoh {
   9871  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9872  1.281   msaitoh 	uint32_t mdic = 0;
   9873  1.281   msaitoh 	int i, rv;
   9874  1.279   msaitoh 
   9875  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   9876  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   9877  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   9878  1.522   msaitoh 		reg &= MII_ADDRMASK;
   9879  1.522   msaitoh 	}
   9880  1.522   msaitoh 
   9881  1.281   msaitoh 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
   9882  1.281   msaitoh 	    MDIC_REGADD(reg));
   9883    1.1   thorpej 
   9884  1.281   msaitoh 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
   9885  1.281   msaitoh 		mdic = CSR_READ(sc, WMREG_MDIC);
   9886  1.281   msaitoh 		if (mdic & MDIC_READY)
   9887  1.281   msaitoh 			break;
   9888  1.327   msaitoh 		delay(50);
   9889    1.1   thorpej 	}
   9890    1.1   thorpej 
   9891  1.281   msaitoh 	if ((mdic & MDIC_READY) == 0) {
   9892  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
   9893  1.521   msaitoh 		    device_xname(dev), phy, reg);
   9894  1.281   msaitoh 		rv = 0;
   9895  1.281   msaitoh 	} else if (mdic & MDIC_E) {
   9896  1.281   msaitoh #if 0 /* This is normal if no PHY is present. */
   9897  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
   9898  1.521   msaitoh 		    device_xname(dev), phy, reg);
   9899  1.281   msaitoh #endif
   9900  1.281   msaitoh 		rv = 0;
   9901  1.281   msaitoh 	} else {
   9902  1.281   msaitoh 		rv = MDIC_DATA(mdic);
   9903  1.281   msaitoh 		if (rv == 0xffff)
   9904  1.281   msaitoh 			rv = 0;
   9905  1.173   msaitoh 	}
   9906  1.173   msaitoh 
   9907  1.281   msaitoh 	return rv;
   9908    1.1   thorpej }
   9909    1.1   thorpej 
   9910    1.1   thorpej /*
   9911  1.424   msaitoh  * wm_gmii_mdic_writereg:	[mii interface function]
   9912    1.1   thorpej  *
   9913  1.281   msaitoh  *	Write a PHY register on the GMII.
   9914    1.1   thorpej  */
   9915   1.47   thorpej static void
   9916  1.521   msaitoh wm_gmii_mdic_writereg(device_t dev, int phy, int reg, int val)
   9917    1.1   thorpej {
   9918  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9919  1.281   msaitoh 	uint32_t mdic = 0;
   9920  1.281   msaitoh 	int i;
   9921  1.281   msaitoh 
   9922  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   9923  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   9924  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   9925  1.522   msaitoh 		reg &= MII_ADDRMASK;
   9926  1.522   msaitoh 	}
   9927  1.522   msaitoh 
   9928  1.281   msaitoh 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
   9929  1.281   msaitoh 	    MDIC_REGADD(reg) | MDIC_DATA(val));
   9930    1.1   thorpej 
   9931  1.281   msaitoh 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
   9932  1.281   msaitoh 		mdic = CSR_READ(sc, WMREG_MDIC);
   9933  1.281   msaitoh 		if (mdic & MDIC_READY)
   9934  1.281   msaitoh 			break;
   9935  1.327   msaitoh 		delay(50);
   9936  1.127    bouyer 	}
   9937    1.1   thorpej 
   9938  1.281   msaitoh 	if ((mdic & MDIC_READY) == 0)
   9939  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n",
   9940  1.521   msaitoh 		    device_xname(dev), phy, reg);
   9941  1.281   msaitoh 	else if (mdic & MDIC_E)
   9942  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n",
   9943  1.521   msaitoh 		    device_xname(dev), phy, reg);
   9944  1.281   msaitoh }
   9945  1.133   msaitoh 
   9946  1.281   msaitoh /*
   9947  1.424   msaitoh  * wm_gmii_i82544_readreg:	[mii interface function]
   9948  1.424   msaitoh  *
   9949  1.424   msaitoh  *	Read a PHY register on the GMII.
   9950  1.424   msaitoh  */
   9951  1.424   msaitoh static int
   9952  1.521   msaitoh wm_gmii_i82544_readreg(device_t dev, int phy, int reg)
   9953  1.424   msaitoh {
   9954  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9955  1.424   msaitoh 	int rv;
   9956  1.424   msaitoh 
   9957  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   9958  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   9959  1.424   msaitoh 		return 0;
   9960  1.424   msaitoh 	}
   9961  1.522   msaitoh 
   9962  1.522   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   9963  1.522   msaitoh 		switch (sc->sc_phytype) {
   9964  1.522   msaitoh 		case WMPHY_IGP:
   9965  1.522   msaitoh 		case WMPHY_IGP_2:
   9966  1.522   msaitoh 		case WMPHY_IGP_3:
   9967  1.522   msaitoh 			wm_gmii_mdic_writereg(dev, phy, MII_IGPHY_PAGE_SELECT, reg);
   9968  1.522   msaitoh 			break;
   9969  1.522   msaitoh 		default:
   9970  1.522   msaitoh #ifdef WM_DEBUG
   9971  1.522   msaitoh 			device_printf(dev, "%s: PHYTYPE = 0x%x, addr = %02x\n",
   9972  1.522   msaitoh 			    __func__, sc->sc_phytype, reg);
   9973  1.522   msaitoh #endif
   9974  1.522   msaitoh 			break;
   9975  1.522   msaitoh 		}
   9976  1.522   msaitoh 	}
   9977  1.522   msaitoh 
   9978  1.522   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   9979  1.424   msaitoh 	sc->phy.release(sc);
   9980  1.424   msaitoh 
   9981  1.424   msaitoh 	return rv;
   9982  1.424   msaitoh }
   9983  1.424   msaitoh 
   9984  1.424   msaitoh /*
   9985  1.424   msaitoh  * wm_gmii_i82544_writereg:	[mii interface function]
   9986  1.424   msaitoh  *
   9987  1.424   msaitoh  *	Write a PHY register on the GMII.
   9988  1.424   msaitoh  */
   9989  1.424   msaitoh static void
   9990  1.521   msaitoh wm_gmii_i82544_writereg(device_t dev, int phy, int reg, int val)
   9991  1.424   msaitoh {
   9992  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9993  1.424   msaitoh 
   9994  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   9995  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   9996  1.521   msaitoh 		return;
   9997  1.424   msaitoh 	}
   9998  1.522   msaitoh 
   9999  1.522   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   10000  1.522   msaitoh 		switch (sc->sc_phytype) {
   10001  1.522   msaitoh 		case WMPHY_IGP:
   10002  1.522   msaitoh 		case WMPHY_IGP_2:
   10003  1.522   msaitoh 		case WMPHY_IGP_3:
   10004  1.522   msaitoh 			wm_gmii_mdic_writereg(dev, phy, MII_IGPHY_PAGE_SELECT, reg);
   10005  1.522   msaitoh 			break;
   10006  1.522   msaitoh 		default:
   10007  1.522   msaitoh #ifdef WM_DEBUG
   10008  1.522   msaitoh 			device_printf(dev, "%s: PHYTYPE == 0x%x, addr = %02x",
   10009  1.522   msaitoh 			    __func__, sc->sc_phytype, reg);
   10010  1.522   msaitoh #endif
   10011  1.522   msaitoh 			break;
   10012  1.522   msaitoh 		}
   10013  1.522   msaitoh 	}
   10014  1.522   msaitoh 
   10015  1.522   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   10016  1.424   msaitoh 	sc->phy.release(sc);
   10017  1.424   msaitoh }
   10018  1.424   msaitoh 
   10019  1.424   msaitoh /*
   10020  1.281   msaitoh  * wm_gmii_i80003_readreg:	[mii interface function]
   10021  1.281   msaitoh  *
   10022  1.281   msaitoh  *	Read a PHY register on the kumeran
   10023  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10024  1.281   msaitoh  * ressource ...
   10025  1.281   msaitoh  */
   10026  1.281   msaitoh static int
   10027  1.521   msaitoh wm_gmii_i80003_readreg(device_t dev, int phy, int reg)
   10028  1.281   msaitoh {
   10029  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10030  1.531   msaitoh 	int page_select, temp;
   10031  1.281   msaitoh 	int rv;
   10032    1.1   thorpej 
   10033  1.281   msaitoh 	if (phy != 1) /* only one PHY on kumeran bus */
   10034  1.281   msaitoh 		return 0;
   10035    1.1   thorpej 
   10036  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10037  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10038  1.281   msaitoh 		return 0;
   10039    1.1   thorpej 	}
   10040  1.186   msaitoh 
   10041  1.531   msaitoh 	if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG)
   10042  1.531   msaitoh 		page_select = GG82563_PHY_PAGE_SELECT;
   10043  1.531   msaitoh 	else {
   10044  1.531   msaitoh 		/*
   10045  1.531   msaitoh 		 * Use Alternative Page Select register to access registers
   10046  1.531   msaitoh 		 * 30 and 31.
   10047  1.531   msaitoh 		 */
   10048  1.531   msaitoh 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
   10049  1.189   msaitoh 	}
   10050  1.531   msaitoh 	temp = (uint16_t)reg >> GG82563_PAGE_SHIFT;
   10051  1.531   msaitoh 	wm_gmii_mdic_writereg(dev, phy, page_select, temp);
   10052  1.531   msaitoh 	if ((sc->sc_flags & WM_F_80003_MDIC_WA) != 0) {
   10053  1.531   msaitoh 		/*
   10054  1.531   msaitoh 		 * Wait more 200us for a bug of the ready bit in the MDIC
   10055  1.531   msaitoh 		 * register.
   10056  1.531   msaitoh 		 */
   10057  1.531   msaitoh 		delay(200);
   10058  1.531   msaitoh 		if (wm_gmii_mdic_readreg(dev, phy, page_select) != temp) {
   10059  1.531   msaitoh 			device_printf(dev, "%s failed\n", __func__);
   10060  1.531   msaitoh 			rv = 0; /* XXX */
   10061  1.531   msaitoh 			goto out;
   10062  1.531   msaitoh 		}
   10063  1.531   msaitoh 		rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   10064  1.531   msaitoh 		delay(200);
   10065  1.531   msaitoh 	} else
   10066  1.531   msaitoh 		rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   10067  1.531   msaitoh 
   10068  1.531   msaitoh out:
   10069  1.424   msaitoh 	sc->phy.release(sc);
   10070  1.281   msaitoh 	return rv;
   10071  1.281   msaitoh }
   10072  1.190   msaitoh 
   10073  1.281   msaitoh /*
   10074  1.281   msaitoh  * wm_gmii_i80003_writereg:	[mii interface function]
   10075  1.281   msaitoh  *
   10076  1.281   msaitoh  *	Write a PHY register on the kumeran.
   10077  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10078  1.281   msaitoh  * ressource ...
   10079  1.281   msaitoh  */
   10080  1.281   msaitoh static void
   10081  1.521   msaitoh wm_gmii_i80003_writereg(device_t dev, int phy, int reg, int val)
   10082  1.281   msaitoh {
   10083  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10084  1.531   msaitoh 	int page_select, temp;
   10085  1.221   msaitoh 
   10086  1.281   msaitoh 	if (phy != 1) /* only one PHY on kumeran bus */
   10087  1.281   msaitoh 		return;
   10088  1.190   msaitoh 
   10089  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10090  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10091  1.281   msaitoh 		return;
   10092  1.281   msaitoh 	}
   10093  1.192   msaitoh 
   10094  1.531   msaitoh 	if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG)
   10095  1.531   msaitoh 		page_select = GG82563_PHY_PAGE_SELECT;
   10096  1.531   msaitoh 	else {
   10097  1.531   msaitoh 		/*
   10098  1.531   msaitoh 		 * Use Alternative Page Select register to access registers
   10099  1.531   msaitoh 		 * 30 and 31.
   10100  1.531   msaitoh 		 */
   10101  1.531   msaitoh 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
   10102  1.189   msaitoh 	}
   10103  1.531   msaitoh 	temp = (uint16_t)reg >> GG82563_PAGE_SHIFT;
   10104  1.531   msaitoh 	wm_gmii_mdic_writereg(dev, phy, page_select, temp);
   10105  1.531   msaitoh 	if ((sc->sc_flags & WM_F_80003_MDIC_WA) != 0) {
   10106  1.531   msaitoh 		/*
   10107  1.531   msaitoh 		 * Wait more 200us for a bug of the ready bit in the MDIC
   10108  1.531   msaitoh 		 * register.
   10109  1.531   msaitoh 		 */
   10110  1.531   msaitoh 		delay(200);
   10111  1.531   msaitoh 		if (wm_gmii_mdic_readreg(dev, phy, page_select) != temp) {
   10112  1.531   msaitoh 			device_printf(dev, "%s failed\n", __func__);
   10113  1.531   msaitoh 			goto out;
   10114  1.531   msaitoh 		}
   10115  1.531   msaitoh 		wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   10116  1.531   msaitoh 		delay(200);
   10117  1.531   msaitoh 	} else
   10118  1.531   msaitoh 		wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   10119  1.281   msaitoh 
   10120  1.531   msaitoh out:
   10121  1.424   msaitoh 	sc->phy.release(sc);
   10122    1.1   thorpej }
   10123    1.1   thorpej 
   10124    1.1   thorpej /*
   10125  1.281   msaitoh  * wm_gmii_bm_readreg:	[mii interface function]
   10126  1.265   msaitoh  *
   10127  1.281   msaitoh  *	Read a PHY register on the kumeran
   10128  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10129  1.281   msaitoh  * ressource ...
   10130  1.265   msaitoh  */
   10131  1.265   msaitoh static int
   10132  1.521   msaitoh wm_gmii_bm_readreg(device_t dev, int phy, int reg)
   10133  1.265   msaitoh {
   10134  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10135  1.435   msaitoh 	uint16_t page = reg >> BME1000_PAGE_SHIFT;
   10136  1.435   msaitoh 	uint16_t val;
   10137  1.281   msaitoh 	int rv;
   10138  1.265   msaitoh 
   10139  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10140  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10141  1.281   msaitoh 		return 0;
   10142  1.281   msaitoh 	}
   10143  1.265   msaitoh 
   10144  1.435   msaitoh 	if ((sc->sc_type != WM_T_82574) && (sc->sc_type != WM_T_82583))
   10145  1.435   msaitoh 		phy = ((page >= 768) || ((page == 0) && (reg == 25))
   10146  1.435   msaitoh 		    || (reg == 31)) ? 1 : phy;
   10147  1.435   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10148  1.435   msaitoh 	if (page == BM_WUC_PAGE) {
   10149  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &val, 1);
   10150  1.435   msaitoh 		rv = val;
   10151  1.435   msaitoh 		goto release;
   10152  1.435   msaitoh 	}
   10153  1.435   msaitoh 
   10154  1.281   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   10155  1.435   msaitoh 		if ((phy == 1) && (sc->sc_type != WM_T_82574)
   10156  1.435   msaitoh 		    && (sc->sc_type != WM_T_82583))
   10157  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   10158  1.435   msaitoh 			    MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
   10159  1.281   msaitoh 		else
   10160  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   10161  1.435   msaitoh 			    BME1000_PHY_PAGE_SELECT, page);
   10162  1.265   msaitoh 	}
   10163  1.265   msaitoh 
   10164  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   10165  1.435   msaitoh 
   10166  1.435   msaitoh release:
   10167  1.424   msaitoh 	sc->phy.release(sc);
   10168  1.281   msaitoh 	return rv;
   10169  1.265   msaitoh }
   10170  1.265   msaitoh 
   10171  1.265   msaitoh /*
   10172  1.281   msaitoh  * wm_gmii_bm_writereg:	[mii interface function]
   10173    1.1   thorpej  *
   10174  1.281   msaitoh  *	Write a PHY register on the kumeran.
   10175  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10176  1.281   msaitoh  * ressource ...
   10177    1.1   thorpej  */
   10178   1.47   thorpej static void
   10179  1.521   msaitoh wm_gmii_bm_writereg(device_t dev, int phy, int reg, int val)
   10180  1.281   msaitoh {
   10181  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10182  1.435   msaitoh 	uint16_t page = reg >> BME1000_PAGE_SHIFT;
   10183  1.281   msaitoh 
   10184  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10185  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10186  1.281   msaitoh 		return;
   10187  1.281   msaitoh 	}
   10188  1.281   msaitoh 
   10189  1.435   msaitoh 	if ((sc->sc_type != WM_T_82574) && (sc->sc_type != WM_T_82583))
   10190  1.435   msaitoh 		phy = ((page >= 768) || ((page == 0) && (reg == 25))
   10191  1.435   msaitoh 		    || (reg == 31)) ? 1 : phy;
   10192  1.435   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10193  1.435   msaitoh 	if (page == BM_WUC_PAGE) {
   10194  1.435   msaitoh 		uint16_t tmp;
   10195  1.435   msaitoh 
   10196  1.435   msaitoh 		tmp = val;
   10197  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &tmp, 0);
   10198  1.435   msaitoh 		goto release;
   10199  1.435   msaitoh 	}
   10200  1.435   msaitoh 
   10201  1.281   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   10202  1.435   msaitoh 		if ((phy == 1) && (sc->sc_type != WM_T_82574)
   10203  1.435   msaitoh 		    && (sc->sc_type != WM_T_82583))
   10204  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   10205  1.435   msaitoh 			    MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
   10206  1.281   msaitoh 		else
   10207  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   10208  1.435   msaitoh 			    BME1000_PHY_PAGE_SELECT, page);
   10209  1.281   msaitoh 	}
   10210  1.281   msaitoh 
   10211  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   10212  1.435   msaitoh 
   10213  1.435   msaitoh release:
   10214  1.424   msaitoh 	sc->phy.release(sc);
   10215  1.281   msaitoh }
   10216  1.281   msaitoh 
   10217  1.281   msaitoh static void
   10218  1.521   msaitoh wm_access_phy_wakeup_reg_bm(device_t dev, int offset, int16_t *val, int rd)
   10219    1.1   thorpej {
   10220  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10221  1.281   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(offset);
   10222  1.441   msaitoh 	uint16_t wuce, reg;
   10223  1.281   msaitoh 
   10224  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   10225  1.521   msaitoh 		device_xname(dev), __func__));
   10226  1.281   msaitoh 	/* XXX Gig must be disabled for MDIO accesses to page 800 */
   10227  1.281   msaitoh 	if (sc->sc_type == WM_T_PCH) {
   10228  1.281   msaitoh 		/* XXX e1000 driver do nothing... why? */
   10229  1.281   msaitoh 	}
   10230  1.281   msaitoh 
   10231  1.441   msaitoh 	/*
   10232  1.441   msaitoh 	 * 1) Enable PHY wakeup register first.
   10233  1.441   msaitoh 	 * See e1000_enable_phy_wakeup_reg_access_bm().
   10234  1.441   msaitoh 	 */
   10235  1.441   msaitoh 
   10236  1.281   msaitoh 	/* Set page 769 */
   10237  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10238  1.281   msaitoh 	    BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
   10239  1.281   msaitoh 
   10240  1.441   msaitoh 	/* Read WUCE and save it */
   10241  1.521   msaitoh 	wuce = wm_gmii_mdic_readreg(dev, 1, BM_WUC_ENABLE_REG);
   10242  1.281   msaitoh 
   10243  1.441   msaitoh 	reg = wuce | BM_WUC_ENABLE_BIT;
   10244  1.441   msaitoh 	reg &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
   10245  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ENABLE_REG, reg);
   10246  1.281   msaitoh 
   10247  1.281   msaitoh 	/* Select page 800 */
   10248  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10249  1.281   msaitoh 	    BM_WUC_PAGE << BME1000_PAGE_SHIFT);
   10250    1.1   thorpej 
   10251  1.441   msaitoh 	/*
   10252  1.441   msaitoh 	 * 2) Access PHY wakeup register.
   10253  1.441   msaitoh 	 * See e1000_access_phy_wakeup_reg_bm.
   10254  1.441   msaitoh 	 */
   10255  1.441   msaitoh 
   10256  1.281   msaitoh 	/* Write page 800 */
   10257  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ADDRESS_OPCODE, regnum);
   10258    1.1   thorpej 
   10259  1.281   msaitoh 	if (rd)
   10260  1.521   msaitoh 		*val = wm_gmii_mdic_readreg(dev, 1, BM_WUC_DATA_OPCODE);
   10261  1.127    bouyer 	else
   10262  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, 1, BM_WUC_DATA_OPCODE, *val);
   10263  1.281   msaitoh 
   10264  1.441   msaitoh 	/*
   10265  1.441   msaitoh 	 * 3) Disable PHY wakeup register.
   10266  1.441   msaitoh 	 * See e1000_disable_phy_wakeup_reg_access_bm().
   10267  1.441   msaitoh 	 */
   10268  1.281   msaitoh 	/* Set page 769 */
   10269  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10270  1.281   msaitoh 	    BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
   10271  1.281   msaitoh 
   10272  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ENABLE_REG, wuce);
   10273  1.281   msaitoh }
   10274  1.281   msaitoh 
   10275  1.281   msaitoh /*
   10276  1.281   msaitoh  * wm_gmii_hv_readreg:	[mii interface function]
   10277  1.281   msaitoh  *
   10278  1.281   msaitoh  *	Read a PHY register on the kumeran
   10279  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10280  1.281   msaitoh  * ressource ...
   10281  1.281   msaitoh  */
   10282  1.281   msaitoh static int
   10283  1.521   msaitoh wm_gmii_hv_readreg(device_t dev, int phy, int reg)
   10284  1.281   msaitoh {
   10285  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10286  1.281   msaitoh 	int rv;
   10287  1.281   msaitoh 
   10288  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   10289  1.521   msaitoh 		device_xname(dev), __func__));
   10290  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10291  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10292  1.281   msaitoh 		return 0;
   10293  1.281   msaitoh 	}
   10294  1.281   msaitoh 
   10295  1.521   msaitoh 	rv = wm_gmii_hv_readreg_locked(dev, phy, reg);
   10296  1.424   msaitoh 	sc->phy.release(sc);
   10297  1.424   msaitoh 	return rv;
   10298  1.424   msaitoh }
   10299  1.424   msaitoh 
   10300  1.424   msaitoh static int
   10301  1.521   msaitoh wm_gmii_hv_readreg_locked(device_t dev, int phy, int reg)
   10302  1.424   msaitoh {
   10303  1.424   msaitoh 	uint16_t page = BM_PHY_REG_PAGE(reg);
   10304  1.424   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(reg);
   10305  1.424   msaitoh 	uint16_t val;
   10306  1.424   msaitoh 	int rv;
   10307  1.424   msaitoh 
   10308  1.437   msaitoh 	phy = (page >= HV_INTC_FC_PAGE_START) ? 1 : phy;
   10309    1.1   thorpej 
   10310  1.281   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10311  1.281   msaitoh 	if (page == BM_WUC_PAGE) {
   10312  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &val, 1);
   10313  1.281   msaitoh 		return val;
   10314  1.281   msaitoh 	}
   10315    1.1   thorpej 
   10316  1.244   msaitoh 	/*
   10317  1.281   msaitoh 	 * Lower than page 768 works differently than the rest so it has its
   10318  1.281   msaitoh 	 * own func
   10319  1.244   msaitoh 	 */
   10320  1.281   msaitoh 	if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
   10321  1.281   msaitoh 		printf("gmii_hv_readreg!!!\n");
   10322  1.281   msaitoh 		return 0;
   10323  1.281   msaitoh 	}
   10324  1.281   msaitoh 
   10325  1.528   msaitoh 	/*
   10326  1.528   msaitoh 	 * XXX I21[789] documents say that the SMBus Address register is at
   10327  1.528   msaitoh 	 * PHY address 01, Page 0 (not 768), Register 26.
   10328  1.528   msaitoh 	 */
   10329  1.528   msaitoh 	if (page == HV_INTC_FC_PAGE_START)
   10330  1.528   msaitoh 		page = 0;
   10331  1.528   msaitoh 
   10332  1.281   msaitoh 	if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
   10333  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10334  1.281   msaitoh 		    page << BME1000_PAGE_SHIFT);
   10335    1.1   thorpej 	}
   10336    1.1   thorpej 
   10337  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, regnum & MII_ADDRMASK);
   10338  1.281   msaitoh 	return rv;
   10339  1.281   msaitoh }
   10340    1.1   thorpej 
   10341  1.281   msaitoh /*
   10342  1.281   msaitoh  * wm_gmii_hv_writereg:	[mii interface function]
   10343  1.281   msaitoh  *
   10344  1.281   msaitoh  *	Write a PHY register on the kumeran.
   10345  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10346  1.281   msaitoh  * ressource ...
   10347  1.281   msaitoh  */
   10348  1.281   msaitoh static void
   10349  1.521   msaitoh wm_gmii_hv_writereg(device_t dev, int phy, int reg, int val)
   10350  1.281   msaitoh {
   10351  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10352    1.1   thorpej 
   10353  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   10354  1.521   msaitoh 		device_xname(dev), __func__));
   10355  1.425   msaitoh 
   10356  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10357  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10358  1.281   msaitoh 		return;
   10359  1.281   msaitoh 	}
   10360  1.208   msaitoh 
   10361  1.521   msaitoh 	wm_gmii_hv_writereg_locked(dev, phy, reg, val);
   10362  1.424   msaitoh 	sc->phy.release(sc);
   10363  1.424   msaitoh }
   10364  1.424   msaitoh 
   10365  1.424   msaitoh static void
   10366  1.521   msaitoh wm_gmii_hv_writereg_locked(device_t dev, int phy, int reg, int val)
   10367  1.424   msaitoh {
   10368  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10369  1.424   msaitoh 	uint16_t page = BM_PHY_REG_PAGE(reg);
   10370  1.424   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(reg);
   10371  1.424   msaitoh 
   10372  1.437   msaitoh 	phy = (page >= HV_INTC_FC_PAGE_START) ? 1 : phy;
   10373  1.265   msaitoh 
   10374  1.281   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10375  1.281   msaitoh 	if (page == BM_WUC_PAGE) {
   10376  1.281   msaitoh 		uint16_t tmp;
   10377  1.208   msaitoh 
   10378  1.281   msaitoh 		tmp = val;
   10379  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &tmp, 0);
   10380  1.281   msaitoh 		return;
   10381  1.208   msaitoh 	}
   10382  1.184   msaitoh 
   10383  1.244   msaitoh 	/*
   10384  1.281   msaitoh 	 * Lower than page 768 works differently than the rest so it has its
   10385  1.281   msaitoh 	 * own func
   10386  1.244   msaitoh 	 */
   10387  1.281   msaitoh 	if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
   10388  1.281   msaitoh 		printf("gmii_hv_writereg!!!\n");
   10389  1.281   msaitoh 		return;
   10390  1.221   msaitoh 	}
   10391  1.244   msaitoh 
   10392  1.437   msaitoh 	{
   10393  1.437   msaitoh 		/*
   10394  1.528   msaitoh 		 * XXX I21[789] documents say that the SMBus Address register
   10395  1.528   msaitoh 		 * is at PHY address 01, Page 0 (not 768), Register 26.
   10396  1.528   msaitoh 		 */
   10397  1.528   msaitoh 		if (page == HV_INTC_FC_PAGE_START)
   10398  1.528   msaitoh 			page = 0;
   10399  1.528   msaitoh 
   10400  1.528   msaitoh 		/*
   10401  1.437   msaitoh 		 * XXX Workaround MDIO accesses being disabled after entering
   10402  1.437   msaitoh 		 * IEEE Power Down (whenever bit 11 of the PHY control
   10403  1.437   msaitoh 		 * register is set)
   10404  1.437   msaitoh 		 */
   10405  1.437   msaitoh 		if (sc->sc_phytype == WMPHY_82578) {
   10406  1.437   msaitoh 			struct mii_softc *child;
   10407  1.437   msaitoh 
   10408  1.437   msaitoh 			child = LIST_FIRST(&sc->sc_mii.mii_phys);
   10409  1.437   msaitoh 			if ((child != NULL) && (child->mii_mpd_rev >= 1)
   10410  1.437   msaitoh 			    && (phy == 2) && ((regnum & MII_ADDRMASK) == 0)
   10411  1.437   msaitoh 			    && ((val & (1 << 11)) != 0)) {
   10412  1.437   msaitoh 				printf("XXX need workaround\n");
   10413  1.437   msaitoh 			}
   10414  1.437   msaitoh 		}
   10415  1.184   msaitoh 
   10416  1.437   msaitoh 		if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
   10417  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10418  1.437   msaitoh 			    page << BME1000_PAGE_SHIFT);
   10419  1.437   msaitoh 		}
   10420  1.281   msaitoh 	}
   10421  1.281   msaitoh 
   10422  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, regnum & MII_ADDRMASK, val);
   10423  1.281   msaitoh }
   10424  1.281   msaitoh 
   10425  1.281   msaitoh /*
   10426  1.281   msaitoh  * wm_gmii_82580_readreg:	[mii interface function]
   10427  1.281   msaitoh  *
   10428  1.281   msaitoh  *	Read a PHY register on the 82580 and I350.
   10429  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10430  1.281   msaitoh  * ressource ...
   10431  1.281   msaitoh  */
   10432  1.281   msaitoh static int
   10433  1.521   msaitoh wm_gmii_82580_readreg(device_t dev, int phy, int reg)
   10434  1.281   msaitoh {
   10435  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10436  1.281   msaitoh 	int rv;
   10437  1.281   msaitoh 
   10438  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10439  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10440  1.281   msaitoh 		return 0;
   10441  1.184   msaitoh 	}
   10442  1.244   msaitoh 
   10443  1.522   msaitoh #ifdef DIAGNOSTIC
   10444  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   10445  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   10446  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   10447  1.522   msaitoh 		reg &= MII_ADDRMASK;
   10448  1.522   msaitoh 	}
   10449  1.522   msaitoh #endif
   10450  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg);
   10451  1.202   msaitoh 
   10452  1.424   msaitoh 	sc->phy.release(sc);
   10453  1.281   msaitoh 	return rv;
   10454  1.281   msaitoh }
   10455  1.202   msaitoh 
   10456  1.281   msaitoh /*
   10457  1.281   msaitoh  * wm_gmii_82580_writereg:	[mii interface function]
   10458  1.281   msaitoh  *
   10459  1.281   msaitoh  *	Write a PHY register on the 82580 and I350.
   10460  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10461  1.281   msaitoh  * ressource ...
   10462  1.281   msaitoh  */
   10463  1.281   msaitoh static void
   10464  1.521   msaitoh wm_gmii_82580_writereg(device_t dev, int phy, int reg, int val)
   10465  1.281   msaitoh {
   10466  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10467  1.202   msaitoh 
   10468  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10469  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10470  1.281   msaitoh 		return;
   10471  1.192   msaitoh 	}
   10472  1.281   msaitoh 
   10473  1.522   msaitoh #ifdef DIAGNOSTIC
   10474  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   10475  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   10476  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   10477  1.522   msaitoh 		reg &= MII_ADDRMASK;
   10478  1.522   msaitoh 	}
   10479  1.522   msaitoh #endif
   10480  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg, val);
   10481  1.281   msaitoh 
   10482  1.424   msaitoh 	sc->phy.release(sc);
   10483    1.1   thorpej }
   10484    1.1   thorpej 
   10485    1.1   thorpej /*
   10486  1.329   msaitoh  * wm_gmii_gs40g_readreg:	[mii interface function]
   10487  1.329   msaitoh  *
   10488  1.329   msaitoh  *	Read a PHY register on the I2100 and I211.
   10489  1.329   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10490  1.329   msaitoh  * ressource ...
   10491  1.329   msaitoh  */
   10492  1.329   msaitoh static int
   10493  1.521   msaitoh wm_gmii_gs40g_readreg(device_t dev, int phy, int reg)
   10494  1.329   msaitoh {
   10495  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10496  1.329   msaitoh 	int page, offset;
   10497  1.329   msaitoh 	int rv;
   10498  1.329   msaitoh 
   10499  1.329   msaitoh 	/* Acquire semaphore */
   10500  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10501  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10502  1.329   msaitoh 		return 0;
   10503  1.329   msaitoh 	}
   10504  1.329   msaitoh 
   10505  1.329   msaitoh 	/* Page select */
   10506  1.329   msaitoh 	page = reg >> GS40G_PAGE_SHIFT;
   10507  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, GS40G_PAGE_SELECT, page);
   10508  1.329   msaitoh 
   10509  1.329   msaitoh 	/* Read reg */
   10510  1.329   msaitoh 	offset = reg & GS40G_OFFSET_MASK;
   10511  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, offset);
   10512  1.329   msaitoh 
   10513  1.424   msaitoh 	sc->phy.release(sc);
   10514  1.329   msaitoh 	return rv;
   10515  1.329   msaitoh }
   10516  1.329   msaitoh 
   10517  1.329   msaitoh /*
   10518  1.329   msaitoh  * wm_gmii_gs40g_writereg:	[mii interface function]
   10519  1.329   msaitoh  *
   10520  1.329   msaitoh  *	Write a PHY register on the I210 and I211.
   10521  1.329   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10522  1.329   msaitoh  * ressource ...
   10523  1.329   msaitoh  */
   10524  1.329   msaitoh static void
   10525  1.521   msaitoh wm_gmii_gs40g_writereg(device_t dev, int phy, int reg, int val)
   10526  1.329   msaitoh {
   10527  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10528  1.329   msaitoh 	int page, offset;
   10529  1.329   msaitoh 
   10530  1.329   msaitoh 	/* Acquire semaphore */
   10531  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10532  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10533  1.329   msaitoh 		return;
   10534  1.329   msaitoh 	}
   10535  1.329   msaitoh 
   10536  1.329   msaitoh 	/* Page select */
   10537  1.329   msaitoh 	page = reg >> GS40G_PAGE_SHIFT;
   10538  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, GS40G_PAGE_SELECT, page);
   10539  1.329   msaitoh 
   10540  1.329   msaitoh 	/* Write reg */
   10541  1.329   msaitoh 	offset = reg & GS40G_OFFSET_MASK;
   10542  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, offset, val);
   10543  1.329   msaitoh 
   10544  1.329   msaitoh 	/* Release semaphore */
   10545  1.424   msaitoh 	sc->phy.release(sc);
   10546  1.329   msaitoh }
   10547  1.329   msaitoh 
   10548  1.329   msaitoh /*
   10549  1.281   msaitoh  * wm_gmii_statchg:	[mii interface function]
   10550    1.1   thorpej  *
   10551  1.281   msaitoh  *	Callback from MII layer when media changes.
   10552    1.1   thorpej  */
   10553   1.47   thorpej static void
   10554  1.281   msaitoh wm_gmii_statchg(struct ifnet *ifp)
   10555    1.1   thorpej {
   10556    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   10557  1.281   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   10558    1.1   thorpej 
   10559  1.281   msaitoh 	sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
   10560  1.281   msaitoh 	sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   10561  1.281   msaitoh 	sc->sc_fcrtl &= ~FCRTL_XONE;
   10562    1.1   thorpej 
   10563  1.281   msaitoh 	/*
   10564  1.281   msaitoh 	 * Get flow control negotiation result.
   10565  1.281   msaitoh 	 */
   10566  1.281   msaitoh 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
   10567  1.281   msaitoh 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
   10568  1.281   msaitoh 		sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
   10569  1.281   msaitoh 		mii->mii_media_active &= ~IFM_ETH_FMASK;
   10570  1.281   msaitoh 	}
   10571    1.1   thorpej 
   10572  1.281   msaitoh 	if (sc->sc_flowflags & IFM_FLOW) {
   10573  1.281   msaitoh 		if (sc->sc_flowflags & IFM_ETH_TXPAUSE) {
   10574  1.281   msaitoh 			sc->sc_ctrl |= CTRL_TFCE;
   10575  1.281   msaitoh 			sc->sc_fcrtl |= FCRTL_XONE;
   10576  1.281   msaitoh 		}
   10577  1.281   msaitoh 		if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
   10578  1.281   msaitoh 			sc->sc_ctrl |= CTRL_RFCE;
   10579  1.281   msaitoh 	}
   10580  1.152    dyoung 
   10581  1.281   msaitoh 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   10582  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10583  1.281   msaitoh 		    ("%s: LINK: statchg: FDX\n", ifp->if_xname));
   10584  1.281   msaitoh 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   10585  1.152    dyoung 	} else {
   10586  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10587  1.281   msaitoh 		    ("%s: LINK: statchg: HDX\n", ifp->if_xname));
   10588  1.281   msaitoh 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   10589  1.281   msaitoh 	}
   10590  1.281   msaitoh 
   10591  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10592  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   10593  1.281   msaitoh 	CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
   10594  1.281   msaitoh 						 : WMREG_FCRTL, sc->sc_fcrtl);
   10595  1.281   msaitoh 	if (sc->sc_type == WM_T_80003) {
   10596  1.281   msaitoh 		switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
   10597  1.152    dyoung 		case IFM_1000_T:
   10598  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
   10599  1.281   msaitoh 			    KUMCTRLSTA_HD_CTRL_1000_DEFAULT);
   10600  1.281   msaitoh 			sc->sc_tipg =  TIPG_1000T_80003_DFLT;
   10601  1.152    dyoung 			break;
   10602  1.152    dyoung 		default:
   10603  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
   10604  1.281   msaitoh 			    KUMCTRLSTA_HD_CTRL_10_100_DEFAULT);
   10605  1.281   msaitoh 			sc->sc_tipg =  TIPG_10_100_80003_DFLT;
   10606  1.281   msaitoh 			break;
   10607  1.127    bouyer 		}
   10608  1.281   msaitoh 		CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   10609  1.127    bouyer 	}
   10610    1.1   thorpej }
   10611    1.1   thorpej 
   10612  1.453   msaitoh /* kumeran related (80003, ICH* and PCH*) */
   10613  1.453   msaitoh 
   10614  1.281   msaitoh /*
   10615  1.281   msaitoh  * wm_kmrn_readreg:
   10616  1.281   msaitoh  *
   10617  1.281   msaitoh  *	Read a kumeran register
   10618  1.281   msaitoh  */
   10619  1.281   msaitoh static int
   10620  1.531   msaitoh wm_kmrn_readreg(struct wm_softc *sc, int reg, uint16_t *val)
   10621    1.1   thorpej {
   10622  1.281   msaitoh 	int rv;
   10623    1.1   thorpej 
   10624  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10625  1.424   msaitoh 		rv = wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10626  1.424   msaitoh 	else
   10627  1.424   msaitoh 		rv = sc->phy.acquire(sc);
   10628  1.424   msaitoh 	if (rv != 0) {
   10629  1.521   msaitoh 		device_printf(sc->sc_dev, "%s: failed to get semaphore\n",
   10630  1.521   msaitoh 		    __func__);
   10631  1.531   msaitoh 		return rv;
   10632    1.1   thorpej 	}
   10633    1.1   thorpej 
   10634  1.531   msaitoh 	rv = wm_kmrn_readreg_locked(sc, reg, val);
   10635  1.424   msaitoh 
   10636  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10637  1.424   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10638  1.424   msaitoh 	else
   10639  1.424   msaitoh 		sc->phy.release(sc);
   10640  1.424   msaitoh 
   10641  1.424   msaitoh 	return rv;
   10642  1.424   msaitoh }
   10643  1.424   msaitoh 
   10644  1.424   msaitoh static int
   10645  1.531   msaitoh wm_kmrn_readreg_locked(struct wm_softc *sc, int reg, uint16_t *val)
   10646  1.424   msaitoh {
   10647  1.424   msaitoh 
   10648  1.281   msaitoh 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
   10649  1.281   msaitoh 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
   10650  1.281   msaitoh 	    KUMCTRLSTA_REN);
   10651  1.266   msaitoh 	CSR_WRITE_FLUSH(sc);
   10652  1.281   msaitoh 	delay(2);
   10653    1.1   thorpej 
   10654  1.531   msaitoh 	*val = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
   10655    1.1   thorpej 
   10656  1.531   msaitoh 	return 0;
   10657    1.1   thorpej }
   10658    1.1   thorpej 
   10659    1.1   thorpej /*
   10660  1.281   msaitoh  * wm_kmrn_writereg:
   10661    1.1   thorpej  *
   10662  1.281   msaitoh  *	Write a kumeran register
   10663    1.1   thorpej  */
   10664  1.531   msaitoh static int
   10665  1.531   msaitoh wm_kmrn_writereg(struct wm_softc *sc, int reg, uint16_t val)
   10666    1.1   thorpej {
   10667  1.424   msaitoh 	int rv;
   10668    1.1   thorpej 
   10669  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10670  1.424   msaitoh 		rv = wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10671  1.424   msaitoh 	else
   10672  1.424   msaitoh 		rv = sc->phy.acquire(sc);
   10673  1.424   msaitoh 	if (rv != 0) {
   10674  1.521   msaitoh 		device_printf(sc->sc_dev, "%s: failed to get semaphore\n",
   10675  1.521   msaitoh 		    __func__);
   10676  1.531   msaitoh 		return rv;
   10677  1.281   msaitoh 	}
   10678    1.1   thorpej 
   10679  1.531   msaitoh 	rv = wm_kmrn_writereg_locked(sc, reg, val);
   10680  1.424   msaitoh 
   10681  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10682  1.424   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10683  1.424   msaitoh 	else
   10684  1.424   msaitoh 		sc->phy.release(sc);
   10685  1.531   msaitoh 
   10686  1.531   msaitoh 	return rv;
   10687  1.424   msaitoh }
   10688  1.424   msaitoh 
   10689  1.531   msaitoh static int
   10690  1.531   msaitoh wm_kmrn_writereg_locked(struct wm_softc *sc, int reg, uint16_t val)
   10691  1.424   msaitoh {
   10692  1.424   msaitoh 
   10693  1.281   msaitoh 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
   10694  1.531   msaitoh 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | val);
   10695  1.531   msaitoh 
   10696  1.531   msaitoh 	return 0;
   10697    1.1   thorpej }
   10698    1.1   thorpej 
   10699  1.281   msaitoh /* SGMII related */
   10700  1.281   msaitoh 
   10701    1.1   thorpej /*
   10702  1.281   msaitoh  * wm_sgmii_uses_mdio
   10703    1.1   thorpej  *
   10704  1.281   msaitoh  * Check whether the transaction is to the internal PHY or the external
   10705  1.281   msaitoh  * MDIO interface. Return true if it's MDIO.
   10706  1.281   msaitoh  */
   10707  1.281   msaitoh static bool
   10708  1.281   msaitoh wm_sgmii_uses_mdio(struct wm_softc *sc)
   10709  1.281   msaitoh {
   10710  1.281   msaitoh 	uint32_t reg;
   10711  1.281   msaitoh 	bool ismdio = false;
   10712  1.281   msaitoh 
   10713  1.281   msaitoh 	switch (sc->sc_type) {
   10714  1.281   msaitoh 	case WM_T_82575:
   10715  1.281   msaitoh 	case WM_T_82576:
   10716  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MDIC);
   10717  1.281   msaitoh 		ismdio = ((reg & MDIC_DEST) != 0);
   10718  1.281   msaitoh 		break;
   10719  1.281   msaitoh 	case WM_T_82580:
   10720  1.281   msaitoh 	case WM_T_I350:
   10721  1.281   msaitoh 	case WM_T_I354:
   10722  1.281   msaitoh 	case WM_T_I210:
   10723  1.281   msaitoh 	case WM_T_I211:
   10724  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MDICNFG);
   10725  1.281   msaitoh 		ismdio = ((reg & MDICNFG_DEST) != 0);
   10726  1.281   msaitoh 		break;
   10727  1.281   msaitoh 	default:
   10728  1.281   msaitoh 		break;
   10729  1.281   msaitoh 	}
   10730    1.1   thorpej 
   10731  1.281   msaitoh 	return ismdio;
   10732    1.1   thorpej }
   10733    1.1   thorpej 
   10734    1.1   thorpej /*
   10735  1.281   msaitoh  * wm_sgmii_readreg:	[mii interface function]
   10736    1.1   thorpej  *
   10737  1.281   msaitoh  *	Read a PHY register on the SGMII
   10738  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10739  1.281   msaitoh  * ressource ...
   10740    1.1   thorpej  */
   10741   1.47   thorpej static int
   10742  1.521   msaitoh wm_sgmii_readreg(device_t dev, int phy, int reg)
   10743    1.1   thorpej {
   10744  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10745  1.281   msaitoh 	uint32_t i2ccmd;
   10746    1.1   thorpej 	int i, rv;
   10747    1.1   thorpej 
   10748  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10749  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10750  1.281   msaitoh 		return 0;
   10751  1.281   msaitoh 	}
   10752  1.281   msaitoh 
   10753  1.281   msaitoh 	i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
   10754  1.281   msaitoh 	    | (phy << I2CCMD_PHY_ADDR_SHIFT)
   10755  1.281   msaitoh 	    | I2CCMD_OPCODE_READ;
   10756  1.281   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   10757    1.1   thorpej 
   10758  1.281   msaitoh 	/* Poll the ready bit */
   10759  1.281   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   10760  1.281   msaitoh 		delay(50);
   10761  1.281   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   10762  1.281   msaitoh 		if (i2ccmd & I2CCMD_READY)
   10763    1.1   thorpej 			break;
   10764    1.1   thorpej 	}
   10765  1.281   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   10766  1.521   msaitoh 		device_printf(dev, "I2CCMD Read did not complete\n");
   10767  1.281   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   10768  1.521   msaitoh 		device_printf(dev, "I2CCMD Error bit set\n");
   10769    1.1   thorpej 
   10770  1.281   msaitoh 	rv = ((i2ccmd >> 8) & 0x00ff) | ((i2ccmd << 8) & 0xff00);
   10771    1.1   thorpej 
   10772  1.424   msaitoh 	sc->phy.release(sc);
   10773  1.194   msaitoh 	return rv;
   10774    1.1   thorpej }
   10775    1.1   thorpej 
   10776    1.1   thorpej /*
   10777  1.281   msaitoh  * wm_sgmii_writereg:	[mii interface function]
   10778    1.1   thorpej  *
   10779  1.281   msaitoh  *	Write a PHY register on the SGMII.
   10780  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10781  1.281   msaitoh  * ressource ...
   10782    1.1   thorpej  */
   10783   1.47   thorpej static void
   10784  1.521   msaitoh wm_sgmii_writereg(device_t dev, int phy, int reg, int val)
   10785    1.1   thorpej {
   10786  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10787  1.281   msaitoh 	uint32_t i2ccmd;
   10788    1.1   thorpej 	int i;
   10789  1.314   msaitoh 	int val_swapped;
   10790    1.1   thorpej 
   10791  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10792  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10793  1.281   msaitoh 		return;
   10794  1.281   msaitoh 	}
   10795  1.314   msaitoh 	/* Swap the data bytes for the I2C interface */
   10796  1.314   msaitoh 	val_swapped = ((val >> 8) & 0x00FF) | ((val << 8) & 0xFF00);
   10797  1.281   msaitoh 	i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
   10798  1.281   msaitoh 	    | (phy << I2CCMD_PHY_ADDR_SHIFT)
   10799  1.314   msaitoh 	    | I2CCMD_OPCODE_WRITE | val_swapped;
   10800  1.281   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   10801    1.1   thorpej 
   10802  1.281   msaitoh 	/* Poll the ready bit */
   10803  1.281   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   10804  1.281   msaitoh 		delay(50);
   10805  1.281   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   10806  1.281   msaitoh 		if (i2ccmd & I2CCMD_READY)
   10807    1.1   thorpej 			break;
   10808    1.1   thorpej 	}
   10809  1.281   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   10810  1.521   msaitoh 		device_printf(dev, "I2CCMD Write did not complete\n");
   10811  1.281   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   10812  1.521   msaitoh 		device_printf(dev, "I2CCMD Error bit set\n");
   10813    1.1   thorpej 
   10814  1.424   msaitoh 	sc->phy.release(sc);
   10815    1.1   thorpej }
   10816    1.1   thorpej 
   10817  1.281   msaitoh /* TBI related */
   10818  1.281   msaitoh 
   10819  1.127    bouyer /*
   10820  1.281   msaitoh  * wm_tbi_mediainit:
   10821  1.127    bouyer  *
   10822  1.281   msaitoh  *	Initialize media for use on 1000BASE-X devices.
   10823  1.127    bouyer  */
   10824  1.127    bouyer static void
   10825  1.281   msaitoh wm_tbi_mediainit(struct wm_softc *sc)
   10826  1.127    bouyer {
   10827  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   10828  1.281   msaitoh 	const char *sep = "";
   10829  1.281   msaitoh 
   10830  1.281   msaitoh 	if (sc->sc_type < WM_T_82543)
   10831  1.281   msaitoh 		sc->sc_tipg = TIPG_WM_DFLT;
   10832  1.281   msaitoh 	else
   10833  1.281   msaitoh 		sc->sc_tipg = TIPG_LG_DFLT;
   10834  1.281   msaitoh 
   10835  1.325   msaitoh 	sc->sc_tbi_serdes_anegticks = 5;
   10836  1.281   msaitoh 
   10837  1.281   msaitoh 	/* Initialize our media structures */
   10838  1.281   msaitoh 	sc->sc_mii.mii_ifp = ifp;
   10839  1.325   msaitoh 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   10840  1.281   msaitoh 
   10841  1.325   msaitoh 	if ((sc->sc_type >= WM_T_82575)
   10842  1.325   msaitoh 	    && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   10843  1.327   msaitoh 		ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
   10844  1.325   msaitoh 		    wm_serdes_mediachange, wm_serdes_mediastatus);
   10845  1.325   msaitoh 	else
   10846  1.327   msaitoh 		ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
   10847  1.325   msaitoh 		    wm_tbi_mediachange, wm_tbi_mediastatus);
   10848  1.281   msaitoh 
   10849  1.281   msaitoh 	/*
   10850  1.281   msaitoh 	 * SWD Pins:
   10851  1.281   msaitoh 	 *
   10852  1.281   msaitoh 	 *	0 = Link LED (output)
   10853  1.281   msaitoh 	 *	1 = Loss Of Signal (input)
   10854  1.281   msaitoh 	 */
   10855  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SWDPIO(0);
   10856  1.325   msaitoh 
   10857  1.325   msaitoh 	/* XXX Perhaps this is only for TBI */
   10858  1.325   msaitoh 	if (sc->sc_mediatype != WM_MEDIATYPE_SERDES)
   10859  1.325   msaitoh 		sc->sc_ctrl &= ~CTRL_SWDPIO(1);
   10860  1.325   msaitoh 
   10861  1.311   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   10862  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_LRST;
   10863  1.281   msaitoh 
   10864  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10865  1.127    bouyer 
   10866  1.281   msaitoh #define	ADD(ss, mm, dd)							\
   10867  1.281   msaitoh do {									\
   10868  1.281   msaitoh 	aprint_normal("%s%s", sep, ss);					\
   10869  1.388   msaitoh 	ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | (mm), (dd), NULL); \
   10870  1.281   msaitoh 	sep = ", ";							\
   10871  1.281   msaitoh } while (/*CONSTCOND*/0)
   10872  1.127    bouyer 
   10873  1.281   msaitoh 	aprint_normal_dev(sc->sc_dev, "");
   10874  1.285   msaitoh 
   10875  1.457   msaitoh 	if (sc->sc_type == WM_T_I354) {
   10876  1.457   msaitoh 		uint32_t status;
   10877  1.457   msaitoh 
   10878  1.457   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   10879  1.457   msaitoh 		if (((status & STATUS_2P5_SKU) != 0)
   10880  1.457   msaitoh 		    && ((status & STATUS_2P5_SKU_OVER) == 0)) {
   10881  1.509   msaitoh 			ADD("2500baseKX-FDX", IFM_2500_KX | IFM_FDX,ANAR_X_FD);
   10882  1.457   msaitoh 		} else
   10883  1.509   msaitoh 			ADD("1000baseKX-FDX", IFM_1000_KX | IFM_FDX,ANAR_X_FD);
   10884  1.457   msaitoh 	} else if (sc->sc_type == WM_T_82545) {
   10885  1.457   msaitoh 		/* Only 82545 is LX (XXX except SFP) */
   10886  1.285   msaitoh 		ADD("1000baseLX", IFM_1000_LX, ANAR_X_HD);
   10887  1.388   msaitoh 		ADD("1000baseLX-FDX", IFM_1000_LX | IFM_FDX, ANAR_X_FD);
   10888  1.285   msaitoh 	} else {
   10889  1.285   msaitoh 		ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
   10890  1.388   msaitoh 		ADD("1000baseSX-FDX", IFM_1000_SX | IFM_FDX, ANAR_X_FD);
   10891  1.285   msaitoh 	}
   10892  1.388   msaitoh 	ADD("auto", IFM_AUTO, ANAR_X_FD | ANAR_X_HD);
   10893  1.281   msaitoh 	aprint_normal("\n");
   10894  1.127    bouyer 
   10895  1.281   msaitoh #undef ADD
   10896  1.127    bouyer 
   10897  1.281   msaitoh 	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
   10898  1.127    bouyer }
   10899  1.127    bouyer 
   10900  1.127    bouyer /*
   10901  1.281   msaitoh  * wm_tbi_mediachange:	[ifmedia interface function]
   10902  1.167   msaitoh  *
   10903  1.281   msaitoh  *	Set hardware to newly-selected media on a 1000BASE-X device.
   10904  1.167   msaitoh  */
   10905  1.281   msaitoh static int
   10906  1.281   msaitoh wm_tbi_mediachange(struct ifnet *ifp)
   10907  1.167   msaitoh {
   10908  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   10909  1.281   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   10910  1.281   msaitoh 	uint32_t status;
   10911  1.281   msaitoh 	int i;
   10912  1.167   msaitoh 
   10913  1.325   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {
   10914  1.325   msaitoh 		/* XXX need some work for >= 82571 and < 82575 */
   10915  1.325   msaitoh 		if (sc->sc_type < WM_T_82575)
   10916  1.325   msaitoh 			return 0;
   10917  1.325   msaitoh 	}
   10918  1.167   msaitoh 
   10919  1.285   msaitoh 	if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)
   10920  1.285   msaitoh 	    || (sc->sc_type >= WM_T_82575))
   10921  1.285   msaitoh 		CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK);
   10922  1.285   msaitoh 
   10923  1.285   msaitoh 	sc->sc_ctrl &= ~CTRL_LRST;
   10924  1.285   msaitoh 	sc->sc_txcw = TXCW_ANE;
   10925  1.285   msaitoh 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   10926  1.285   msaitoh 		sc->sc_txcw |= TXCW_FD | TXCW_HD;
   10927  1.285   msaitoh 	else if (ife->ifm_media & IFM_FDX)
   10928  1.285   msaitoh 		sc->sc_txcw |= TXCW_FD;
   10929  1.285   msaitoh 	else
   10930  1.285   msaitoh 		sc->sc_txcw |= TXCW_HD;
   10931  1.285   msaitoh 
   10932  1.327   msaitoh 	if ((sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
   10933  1.281   msaitoh 		sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE;
   10934  1.167   msaitoh 
   10935  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n",
   10936  1.285   msaitoh 		    device_xname(sc->sc_dev), sc->sc_txcw));
   10937  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   10938  1.285   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10939  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   10940  1.285   msaitoh 	delay(1000);
   10941  1.167   msaitoh 
   10942  1.281   msaitoh 	i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1);
   10943  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i));
   10944  1.192   msaitoh 
   10945  1.281   msaitoh 	/*
   10946  1.281   msaitoh 	 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the
   10947  1.281   msaitoh 	 * optics detect a signal, 0 if they don't.
   10948  1.281   msaitoh 	 */
   10949  1.281   msaitoh 	if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) {
   10950  1.281   msaitoh 		/* Have signal; wait for the link to come up. */
   10951  1.281   msaitoh 		for (i = 0; i < WM_LINKUP_TIMEOUT; i++) {
   10952  1.281   msaitoh 			delay(10000);
   10953  1.281   msaitoh 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
   10954  1.281   msaitoh 				break;
   10955  1.281   msaitoh 		}
   10956  1.192   msaitoh 
   10957  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n",
   10958  1.281   msaitoh 			    device_xname(sc->sc_dev),i));
   10959  1.192   msaitoh 
   10960  1.281   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   10961  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10962  1.281   msaitoh 		    ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n",
   10963  1.281   msaitoh 			device_xname(sc->sc_dev),status, STATUS_LU));
   10964  1.281   msaitoh 		if (status & STATUS_LU) {
   10965  1.281   msaitoh 			/* Link is up. */
   10966  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   10967  1.281   msaitoh 			    ("%s: LINK: set media -> link up %s\n",
   10968  1.281   msaitoh 			    device_xname(sc->sc_dev),
   10969  1.281   msaitoh 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   10970  1.192   msaitoh 
   10971  1.281   msaitoh 			/*
   10972  1.281   msaitoh 			 * NOTE: CTRL will update TFCE and RFCE automatically,
   10973  1.281   msaitoh 			 * so we should update sc->sc_ctrl
   10974  1.281   msaitoh 			 */
   10975  1.281   msaitoh 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   10976  1.281   msaitoh 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   10977  1.281   msaitoh 			sc->sc_fcrtl &= ~FCRTL_XONE;
   10978  1.281   msaitoh 			if (status & STATUS_FD)
   10979  1.281   msaitoh 				sc->sc_tctl |=
   10980  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   10981  1.281   msaitoh 			else
   10982  1.281   msaitoh 				sc->sc_tctl |=
   10983  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   10984  1.281   msaitoh 			if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
   10985  1.281   msaitoh 				sc->sc_fcrtl |= FCRTL_XONE;
   10986  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   10987  1.281   msaitoh 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   10988  1.281   msaitoh 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   10989  1.281   msaitoh 				      sc->sc_fcrtl);
   10990  1.281   msaitoh 			sc->sc_tbi_linkup = 1;
   10991  1.281   msaitoh 		} else {
   10992  1.281   msaitoh 			if (i == WM_LINKUP_TIMEOUT)
   10993  1.281   msaitoh 				wm_check_for_link(sc);
   10994  1.281   msaitoh 			/* Link is down. */
   10995  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   10996  1.281   msaitoh 			    ("%s: LINK: set media -> link down\n",
   10997  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   10998  1.281   msaitoh 			sc->sc_tbi_linkup = 0;
   10999  1.281   msaitoh 		}
   11000  1.281   msaitoh 	} else {
   11001  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
   11002  1.281   msaitoh 		    device_xname(sc->sc_dev)));
   11003  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   11004  1.281   msaitoh 	}
   11005  1.198   msaitoh 
   11006  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11007  1.192   msaitoh 
   11008  1.281   msaitoh 	return 0;
   11009  1.192   msaitoh }
   11010  1.192   msaitoh 
   11011  1.167   msaitoh /*
   11012  1.324   msaitoh  * wm_tbi_mediastatus:	[ifmedia interface function]
   11013  1.324   msaitoh  *
   11014  1.324   msaitoh  *	Get the current interface media status on a 1000BASE-X device.
   11015  1.324   msaitoh  */
   11016  1.324   msaitoh static void
   11017  1.324   msaitoh wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   11018  1.324   msaitoh {
   11019  1.324   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   11020  1.324   msaitoh 	uint32_t ctrl, status;
   11021  1.324   msaitoh 
   11022  1.324   msaitoh 	ifmr->ifm_status = IFM_AVALID;
   11023  1.324   msaitoh 	ifmr->ifm_active = IFM_ETHER;
   11024  1.324   msaitoh 
   11025  1.324   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   11026  1.324   msaitoh 	if ((status & STATUS_LU) == 0) {
   11027  1.324   msaitoh 		ifmr->ifm_active |= IFM_NONE;
   11028  1.324   msaitoh 		return;
   11029  1.324   msaitoh 	}
   11030  1.324   msaitoh 
   11031  1.324   msaitoh 	ifmr->ifm_status |= IFM_ACTIVE;
   11032  1.324   msaitoh 	/* Only 82545 is LX */
   11033  1.324   msaitoh 	if (sc->sc_type == WM_T_82545)
   11034  1.324   msaitoh 		ifmr->ifm_active |= IFM_1000_LX;
   11035  1.324   msaitoh 	else
   11036  1.324   msaitoh 		ifmr->ifm_active |= IFM_1000_SX;
   11037  1.324   msaitoh 	if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
   11038  1.324   msaitoh 		ifmr->ifm_active |= IFM_FDX;
   11039  1.324   msaitoh 	else
   11040  1.324   msaitoh 		ifmr->ifm_active |= IFM_HDX;
   11041  1.324   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   11042  1.324   msaitoh 	if (ctrl & CTRL_RFCE)
   11043  1.324   msaitoh 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE;
   11044  1.324   msaitoh 	if (ctrl & CTRL_TFCE)
   11045  1.324   msaitoh 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE;
   11046  1.324   msaitoh }
   11047  1.324   msaitoh 
   11048  1.325   msaitoh /* XXX TBI only */
   11049  1.324   msaitoh static int
   11050  1.324   msaitoh wm_check_for_link(struct wm_softc *sc)
   11051  1.324   msaitoh {
   11052  1.324   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   11053  1.324   msaitoh 	uint32_t rxcw;
   11054  1.324   msaitoh 	uint32_t ctrl;
   11055  1.324   msaitoh 	uint32_t status;
   11056  1.324   msaitoh 	uint32_t sig;
   11057  1.324   msaitoh 
   11058  1.324   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {
   11059  1.325   msaitoh 		/* XXX need some work for >= 82571 */
   11060  1.325   msaitoh 		if (sc->sc_type >= WM_T_82571) {
   11061  1.325   msaitoh 			sc->sc_tbi_linkup = 1;
   11062  1.325   msaitoh 			return 0;
   11063  1.325   msaitoh 		}
   11064  1.324   msaitoh 	}
   11065  1.324   msaitoh 
   11066  1.324   msaitoh 	rxcw = CSR_READ(sc, WMREG_RXCW);
   11067  1.324   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   11068  1.324   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   11069  1.324   msaitoh 
   11070  1.324   msaitoh 	sig = (sc->sc_type > WM_T_82544) ? CTRL_SWDPIN(1) : 0;
   11071  1.324   msaitoh 
   11072  1.388   msaitoh 	DPRINTF(WM_DEBUG_LINK,
   11073  1.388   msaitoh 	    ("%s: %s: sig = %d, status_lu = %d, rxcw_c = %d\n",
   11074  1.324   msaitoh 		device_xname(sc->sc_dev), __func__,
   11075  1.324   msaitoh 		((ctrl & CTRL_SWDPIN(1)) == sig),
   11076  1.388   msaitoh 		((status & STATUS_LU) != 0), ((rxcw & RXCW_C) != 0)));
   11077  1.324   msaitoh 
   11078  1.324   msaitoh 	/*
   11079  1.324   msaitoh 	 * SWDPIN   LU RXCW
   11080  1.324   msaitoh 	 *      0    0    0
   11081  1.324   msaitoh 	 *      0    0    1	(should not happen)
   11082  1.324   msaitoh 	 *      0    1    0	(should not happen)
   11083  1.324   msaitoh 	 *      0    1    1	(should not happen)
   11084  1.324   msaitoh 	 *      1    0    0	Disable autonego and force linkup
   11085  1.324   msaitoh 	 *      1    0    1	got /C/ but not linkup yet
   11086  1.324   msaitoh 	 *      1    1    0	(linkup)
   11087  1.324   msaitoh 	 *      1    1    1	If IFM_AUTO, back to autonego
   11088  1.324   msaitoh 	 *
   11089  1.324   msaitoh 	 */
   11090  1.324   msaitoh 	if (((ctrl & CTRL_SWDPIN(1)) == sig)
   11091  1.324   msaitoh 	    && ((status & STATUS_LU) == 0)
   11092  1.324   msaitoh 	    && ((rxcw & RXCW_C) == 0)) {
   11093  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: force linkup and fullduplex\n",
   11094  1.324   msaitoh 			__func__));
   11095  1.324   msaitoh 		sc->sc_tbi_linkup = 0;
   11096  1.324   msaitoh 		/* Disable auto-negotiation in the TXCW register */
   11097  1.324   msaitoh 		CSR_WRITE(sc, WMREG_TXCW, (sc->sc_txcw & ~TXCW_ANE));
   11098  1.324   msaitoh 
   11099  1.324   msaitoh 		/*
   11100  1.324   msaitoh 		 * Force link-up and also force full-duplex.
   11101  1.324   msaitoh 		 *
   11102  1.324   msaitoh 		 * NOTE: CTRL was updated TFCE and RFCE automatically,
   11103  1.324   msaitoh 		 * so we should update sc->sc_ctrl
   11104  1.324   msaitoh 		 */
   11105  1.324   msaitoh 		sc->sc_ctrl = ctrl | CTRL_SLU | CTRL_FD;
   11106  1.324   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11107  1.324   msaitoh 	} else if (((status & STATUS_LU) != 0)
   11108  1.324   msaitoh 	    && ((rxcw & RXCW_C) != 0)
   11109  1.324   msaitoh 	    && (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)) {
   11110  1.324   msaitoh 		sc->sc_tbi_linkup = 1;
   11111  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: go back to autonego\n",
   11112  1.324   msaitoh 			__func__));
   11113  1.324   msaitoh 		CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   11114  1.324   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, (ctrl & ~CTRL_SLU));
   11115  1.324   msaitoh 	} else if (((ctrl & CTRL_SWDPIN(1)) == sig)
   11116  1.324   msaitoh 	    && ((rxcw & RXCW_C) != 0)) {
   11117  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("/C/"));
   11118  1.324   msaitoh 	} else {
   11119  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: %x,%x,%x\n", __func__, rxcw, ctrl,
   11120  1.324   msaitoh 			status));
   11121  1.324   msaitoh 	}
   11122  1.324   msaitoh 
   11123  1.324   msaitoh 	return 0;
   11124  1.324   msaitoh }
   11125  1.324   msaitoh 
   11126  1.324   msaitoh /*
   11127  1.325   msaitoh  * wm_tbi_tick:
   11128  1.191   msaitoh  *
   11129  1.325   msaitoh  *	Check the link on TBI devices.
   11130  1.325   msaitoh  *	This function acts as mii_tick().
   11131  1.191   msaitoh  */
   11132  1.281   msaitoh static void
   11133  1.325   msaitoh wm_tbi_tick(struct wm_softc *sc)
   11134  1.191   msaitoh {
   11135  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   11136  1.325   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
   11137  1.281   msaitoh 	uint32_t status;
   11138  1.281   msaitoh 
   11139  1.384  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   11140  1.191   msaitoh 
   11141  1.281   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   11142  1.192   msaitoh 
   11143  1.281   msaitoh 	/* XXX is this needed? */
   11144  1.281   msaitoh 	(void)CSR_READ(sc, WMREG_RXCW);
   11145  1.281   msaitoh 	(void)CSR_READ(sc, WMREG_CTRL);
   11146  1.192   msaitoh 
   11147  1.281   msaitoh 	/* set link status */
   11148  1.281   msaitoh 	if ((status & STATUS_LU) == 0) {
   11149  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   11150  1.281   msaitoh 		    ("%s: LINK: checklink -> down\n",
   11151  1.281   msaitoh 			device_xname(sc->sc_dev)));
   11152  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   11153  1.281   msaitoh 	} else if (sc->sc_tbi_linkup == 0) {
   11154  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   11155  1.281   msaitoh 		    ("%s: LINK: checklink -> up %s\n",
   11156  1.281   msaitoh 			device_xname(sc->sc_dev),
   11157  1.281   msaitoh 			(status & STATUS_FD) ? "FDX" : "HDX"));
   11158  1.281   msaitoh 		sc->sc_tbi_linkup = 1;
   11159  1.325   msaitoh 		sc->sc_tbi_serdes_ticks = 0;
   11160  1.325   msaitoh 	}
   11161  1.325   msaitoh 
   11162  1.325   msaitoh 	if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) == 0)
   11163  1.325   msaitoh 		goto setled;
   11164  1.325   msaitoh 
   11165  1.325   msaitoh 	if ((status & STATUS_LU) == 0) {
   11166  1.325   msaitoh 		sc->sc_tbi_linkup = 0;
   11167  1.325   msaitoh 		/* If the timer expired, retry autonegotiation */
   11168  1.325   msaitoh 		if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   11169  1.325   msaitoh 		    && (++sc->sc_tbi_serdes_ticks
   11170  1.325   msaitoh 			>= sc->sc_tbi_serdes_anegticks)) {
   11171  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
   11172  1.325   msaitoh 			sc->sc_tbi_serdes_ticks = 0;
   11173  1.325   msaitoh 			/*
   11174  1.325   msaitoh 			 * Reset the link, and let autonegotiation do
   11175  1.325   msaitoh 			 * its thing
   11176  1.325   msaitoh 			 */
   11177  1.325   msaitoh 			sc->sc_ctrl |= CTRL_LRST;
   11178  1.325   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11179  1.325   msaitoh 			CSR_WRITE_FLUSH(sc);
   11180  1.325   msaitoh 			delay(1000);
   11181  1.325   msaitoh 			sc->sc_ctrl &= ~CTRL_LRST;
   11182  1.325   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11183  1.325   msaitoh 			CSR_WRITE_FLUSH(sc);
   11184  1.325   msaitoh 			delay(1000);
   11185  1.325   msaitoh 			CSR_WRITE(sc, WMREG_TXCW,
   11186  1.325   msaitoh 			    sc->sc_txcw & ~TXCW_ANE);
   11187  1.325   msaitoh 			CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   11188  1.325   msaitoh 		}
   11189  1.192   msaitoh 	}
   11190  1.192   msaitoh 
   11191  1.325   msaitoh setled:
   11192  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11193  1.325   msaitoh }
   11194  1.325   msaitoh 
   11195  1.325   msaitoh /* SERDES related */
   11196  1.325   msaitoh static void
   11197  1.325   msaitoh wm_serdes_power_up_link_82575(struct wm_softc *sc)
   11198  1.325   msaitoh {
   11199  1.325   msaitoh 	uint32_t reg;
   11200  1.325   msaitoh 
   11201  1.325   msaitoh 	if ((sc->sc_mediatype != WM_MEDIATYPE_SERDES)
   11202  1.325   msaitoh 	    && ((sc->sc_flags & WM_F_SGMII) == 0))
   11203  1.325   msaitoh 		return;
   11204  1.325   msaitoh 
   11205  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_CFG);
   11206  1.325   msaitoh 	reg |= PCS_CFG_PCS_EN;
   11207  1.325   msaitoh 	CSR_WRITE(sc, WMREG_PCS_CFG, reg);
   11208  1.325   msaitoh 
   11209  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL_EXT);
   11210  1.325   msaitoh 	reg &= ~CTRL_EXT_SWDPIN(3);
   11211  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   11212  1.325   msaitoh 	CSR_WRITE_FLUSH(sc);
   11213  1.325   msaitoh }
   11214  1.325   msaitoh 
   11215  1.325   msaitoh static int
   11216  1.325   msaitoh wm_serdes_mediachange(struct ifnet *ifp)
   11217  1.325   msaitoh {
   11218  1.325   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   11219  1.325   msaitoh 	bool pcs_autoneg = true; /* XXX */
   11220  1.325   msaitoh 	uint32_t ctrl_ext, pcs_lctl, reg;
   11221  1.325   msaitoh 
   11222  1.325   msaitoh 	/* XXX Currently, this function is not called on 8257[12] */
   11223  1.325   msaitoh 	if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)
   11224  1.325   msaitoh 	    || (sc->sc_type >= WM_T_82575))
   11225  1.325   msaitoh 		CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK);
   11226  1.325   msaitoh 
   11227  1.325   msaitoh 	wm_serdes_power_up_link_82575(sc);
   11228  1.325   msaitoh 
   11229  1.325   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   11230  1.325   msaitoh 
   11231  1.325   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576))
   11232  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SWDPIN(0) | CTRL_SWDPIN(1);
   11233  1.325   msaitoh 
   11234  1.325   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   11235  1.325   msaitoh 	pcs_lctl = CSR_READ(sc, WMREG_PCS_LCTL);
   11236  1.325   msaitoh 	switch (ctrl_ext & CTRL_EXT_LINK_MODE_MASK) {
   11237  1.325   msaitoh 	case CTRL_EXT_LINK_MODE_SGMII:
   11238  1.325   msaitoh 		pcs_autoneg = true;
   11239  1.325   msaitoh 		pcs_lctl &= ~PCS_LCTL_AN_TIMEOUT;
   11240  1.325   msaitoh 		break;
   11241  1.325   msaitoh 	case CTRL_EXT_LINK_MODE_1000KX:
   11242  1.325   msaitoh 		pcs_autoneg = false;
   11243  1.325   msaitoh 		/* FALLTHROUGH */
   11244  1.325   msaitoh 	default:
   11245  1.388   msaitoh 		if ((sc->sc_type == WM_T_82575)
   11246  1.388   msaitoh 		    || (sc->sc_type == WM_T_82576)) {
   11247  1.325   msaitoh 			if ((sc->sc_flags & WM_F_PCS_DIS_AUTONEGO) != 0)
   11248  1.325   msaitoh 				pcs_autoneg = false;
   11249  1.325   msaitoh 		}
   11250  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SPEED_1000 | CTRL_FRCSPD | CTRL_FD
   11251  1.325   msaitoh 		    | CTRL_FRCFDX;
   11252  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_FSV_1000 | PCS_LCTL_FDV_FULL;
   11253  1.325   msaitoh 	}
   11254  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11255  1.325   msaitoh 
   11256  1.325   msaitoh 	if (pcs_autoneg) {
   11257  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_AN_ENABLE | PCS_LCTL_AN_RESTART;
   11258  1.325   msaitoh 		pcs_lctl &= ~PCS_LCTL_FORCE_FC;
   11259  1.325   msaitoh 
   11260  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_ANADV);
   11261  1.325   msaitoh 		reg &= ~(TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE);
   11262  1.327   msaitoh 		reg |= TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE;
   11263  1.325   msaitoh 		CSR_WRITE(sc, WMREG_PCS_ANADV, reg);
   11264  1.325   msaitoh 	} else
   11265  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_FSD | PCS_LCTL_FORCE_FC;
   11266  1.325   msaitoh 
   11267  1.325   msaitoh 	CSR_WRITE(sc, WMREG_PCS_LCTL, pcs_lctl);
   11268  1.325   msaitoh 
   11269  1.325   msaitoh 
   11270  1.325   msaitoh 	return 0;
   11271  1.325   msaitoh }
   11272  1.325   msaitoh 
   11273  1.325   msaitoh static void
   11274  1.325   msaitoh wm_serdes_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   11275  1.325   msaitoh {
   11276  1.325   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   11277  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   11278  1.325   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   11279  1.325   msaitoh 	uint32_t pcs_adv, pcs_lpab, reg;
   11280  1.325   msaitoh 
   11281  1.325   msaitoh 	ifmr->ifm_status = IFM_AVALID;
   11282  1.325   msaitoh 	ifmr->ifm_active = IFM_ETHER;
   11283  1.325   msaitoh 
   11284  1.325   msaitoh 	/* Check PCS */
   11285  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_LSTS);
   11286  1.325   msaitoh 	if ((reg & PCS_LSTS_LINKOK) == 0) {
   11287  1.325   msaitoh 		ifmr->ifm_active |= IFM_NONE;
   11288  1.325   msaitoh 		sc->sc_tbi_linkup = 0;
   11289  1.325   msaitoh 		goto setled;
   11290  1.325   msaitoh 	}
   11291  1.325   msaitoh 
   11292  1.325   msaitoh 	sc->sc_tbi_linkup = 1;
   11293  1.325   msaitoh 	ifmr->ifm_status |= IFM_ACTIVE;
   11294  1.457   msaitoh 	if (sc->sc_type == WM_T_I354) {
   11295  1.457   msaitoh 		uint32_t status;
   11296  1.457   msaitoh 
   11297  1.457   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   11298  1.457   msaitoh 		if (((status & STATUS_2P5_SKU) != 0)
   11299  1.457   msaitoh 		    && ((status & STATUS_2P5_SKU_OVER) == 0)) {
   11300  1.457   msaitoh 			ifmr->ifm_active |= IFM_2500_SX; /* XXX KX */
   11301  1.457   msaitoh 		} else
   11302  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX KX */
   11303  1.457   msaitoh 	} else {
   11304  1.457   msaitoh 		switch (__SHIFTOUT(reg, PCS_LSTS_SPEED)) {
   11305  1.457   msaitoh 		case PCS_LSTS_SPEED_10:
   11306  1.457   msaitoh 			ifmr->ifm_active |= IFM_10_T; /* XXX */
   11307  1.457   msaitoh 			break;
   11308  1.457   msaitoh 		case PCS_LSTS_SPEED_100:
   11309  1.457   msaitoh 			ifmr->ifm_active |= IFM_100_FX; /* XXX */
   11310  1.457   msaitoh 			break;
   11311  1.457   msaitoh 		case PCS_LSTS_SPEED_1000:
   11312  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX */
   11313  1.457   msaitoh 			break;
   11314  1.457   msaitoh 		default:
   11315  1.457   msaitoh 			device_printf(sc->sc_dev, "Unknown speed\n");
   11316  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX */
   11317  1.457   msaitoh 			break;
   11318  1.457   msaitoh 		}
   11319  1.457   msaitoh 	}
   11320  1.325   msaitoh 	if ((reg & PCS_LSTS_FDX) != 0)
   11321  1.325   msaitoh 		ifmr->ifm_active |= IFM_FDX;
   11322  1.325   msaitoh 	else
   11323  1.325   msaitoh 		ifmr->ifm_active |= IFM_HDX;
   11324  1.325   msaitoh 	mii->mii_media_active &= ~IFM_ETH_FMASK;
   11325  1.325   msaitoh 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   11326  1.325   msaitoh 		/* Check flow */
   11327  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_LSTS);
   11328  1.325   msaitoh 		if ((reg & PCS_LSTS_AN_COMP) == 0) {
   11329  1.388   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("XXX LINKOK but not ACOMP\n"));
   11330  1.325   msaitoh 			goto setled;
   11331  1.325   msaitoh 		}
   11332  1.325   msaitoh 		pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
   11333  1.325   msaitoh 		pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
   11334  1.388   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   11335  1.388   msaitoh 		    ("XXX AN result(2) %08x, %08x\n", pcs_adv, pcs_lpab));
   11336  1.325   msaitoh 		if ((pcs_adv & TXCW_SYM_PAUSE)
   11337  1.325   msaitoh 		    && (pcs_lpab & TXCW_SYM_PAUSE)) {
   11338  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11339  1.325   msaitoh 			    | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   11340  1.325   msaitoh 		} else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
   11341  1.325   msaitoh 		    && (pcs_adv & TXCW_ASYM_PAUSE)
   11342  1.325   msaitoh 		    && (pcs_lpab & TXCW_SYM_PAUSE)
   11343  1.325   msaitoh 		    && (pcs_lpab & TXCW_ASYM_PAUSE)) {
   11344  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11345  1.325   msaitoh 			    | IFM_ETH_TXPAUSE;
   11346  1.325   msaitoh 		} else if ((pcs_adv & TXCW_SYM_PAUSE)
   11347  1.325   msaitoh 		    && (pcs_adv & TXCW_ASYM_PAUSE)
   11348  1.325   msaitoh 		    && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
   11349  1.325   msaitoh 		    && (pcs_lpab & TXCW_ASYM_PAUSE)) {
   11350  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11351  1.325   msaitoh 			    | IFM_ETH_RXPAUSE;
   11352  1.325   msaitoh 		}
   11353  1.325   msaitoh 	}
   11354  1.325   msaitoh 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
   11355  1.325   msaitoh 	    | (mii->mii_media_active & IFM_ETH_FMASK);
   11356  1.325   msaitoh setled:
   11357  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11358  1.325   msaitoh }
   11359  1.325   msaitoh 
   11360  1.325   msaitoh /*
   11361  1.325   msaitoh  * wm_serdes_tick:
   11362  1.325   msaitoh  *
   11363  1.325   msaitoh  *	Check the link on serdes devices.
   11364  1.325   msaitoh  */
   11365  1.325   msaitoh static void
   11366  1.325   msaitoh wm_serdes_tick(struct wm_softc *sc)
   11367  1.325   msaitoh {
   11368  1.325   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   11369  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   11370  1.325   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
   11371  1.325   msaitoh 	uint32_t reg;
   11372  1.325   msaitoh 
   11373  1.384  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   11374  1.325   msaitoh 
   11375  1.325   msaitoh 	mii->mii_media_status = IFM_AVALID;
   11376  1.325   msaitoh 	mii->mii_media_active = IFM_ETHER;
   11377  1.325   msaitoh 
   11378  1.325   msaitoh 	/* Check PCS */
   11379  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_LSTS);
   11380  1.325   msaitoh 	if ((reg & PCS_LSTS_LINKOK) != 0) {
   11381  1.325   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
   11382  1.325   msaitoh 		sc->sc_tbi_linkup = 1;
   11383  1.325   msaitoh 		sc->sc_tbi_serdes_ticks = 0;
   11384  1.325   msaitoh 		mii->mii_media_active |= IFM_1000_SX; /* XXX */
   11385  1.325   msaitoh 		if ((reg & PCS_LSTS_FDX) != 0)
   11386  1.325   msaitoh 			mii->mii_media_active |= IFM_FDX;
   11387  1.325   msaitoh 		else
   11388  1.325   msaitoh 			mii->mii_media_active |= IFM_HDX;
   11389  1.325   msaitoh 	} else {
   11390  1.325   msaitoh 		mii->mii_media_status |= IFM_NONE;
   11391  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   11392  1.457   msaitoh 		/* If the timer expired, retry autonegotiation */
   11393  1.325   msaitoh 		if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   11394  1.325   msaitoh 		    && (++sc->sc_tbi_serdes_ticks
   11395  1.325   msaitoh 			>= sc->sc_tbi_serdes_anegticks)) {
   11396  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
   11397  1.325   msaitoh 			sc->sc_tbi_serdes_ticks = 0;
   11398  1.325   msaitoh 			/* XXX */
   11399  1.325   msaitoh 			wm_serdes_mediachange(ifp);
   11400  1.281   msaitoh 		}
   11401  1.192   msaitoh 	}
   11402  1.192   msaitoh 
   11403  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11404  1.191   msaitoh }
   11405  1.191   msaitoh 
   11406  1.292   msaitoh /* SFP related */
   11407  1.295   msaitoh 
   11408  1.295   msaitoh static int
   11409  1.295   msaitoh wm_sfp_read_data_byte(struct wm_softc *sc, uint16_t offset, uint8_t *data)
   11410  1.295   msaitoh {
   11411  1.295   msaitoh 	uint32_t i2ccmd;
   11412  1.295   msaitoh 	int i;
   11413  1.295   msaitoh 
   11414  1.295   msaitoh 	i2ccmd = (offset << I2CCMD_REG_ADDR_SHIFT) | I2CCMD_OPCODE_READ;
   11415  1.295   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   11416  1.295   msaitoh 
   11417  1.295   msaitoh 	/* Poll the ready bit */
   11418  1.295   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   11419  1.295   msaitoh 		delay(50);
   11420  1.295   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   11421  1.295   msaitoh 		if (i2ccmd & I2CCMD_READY)
   11422  1.295   msaitoh 			break;
   11423  1.295   msaitoh 	}
   11424  1.295   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   11425  1.295   msaitoh 		return -1;
   11426  1.295   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   11427  1.295   msaitoh 		return -1;
   11428  1.295   msaitoh 
   11429  1.295   msaitoh 	*data = i2ccmd & 0x00ff;
   11430  1.295   msaitoh 
   11431  1.295   msaitoh 	return 0;
   11432  1.295   msaitoh }
   11433  1.295   msaitoh 
   11434  1.292   msaitoh static uint32_t
   11435  1.295   msaitoh wm_sfp_get_media_type(struct wm_softc *sc)
   11436  1.292   msaitoh {
   11437  1.295   msaitoh 	uint32_t ctrl_ext;
   11438  1.295   msaitoh 	uint8_t val = 0;
   11439  1.295   msaitoh 	int timeout = 3;
   11440  1.311   msaitoh 	uint32_t mediatype = WM_MEDIATYPE_UNKNOWN;
   11441  1.295   msaitoh 	int rv = -1;
   11442  1.292   msaitoh 
   11443  1.295   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   11444  1.295   msaitoh 	ctrl_ext &= ~CTRL_EXT_SWDPIN(3);
   11445  1.295   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_I2C_ENA);
   11446  1.295   msaitoh 	CSR_WRITE_FLUSH(sc);
   11447  1.295   msaitoh 
   11448  1.295   msaitoh 	/* Read SFP module data */
   11449  1.295   msaitoh 	while (timeout) {
   11450  1.295   msaitoh 		rv = wm_sfp_read_data_byte(sc, SFF_SFP_ID_OFF, &val);
   11451  1.295   msaitoh 		if (rv == 0)
   11452  1.295   msaitoh 			break;
   11453  1.295   msaitoh 		delay(100*1000); /* XXX too big */
   11454  1.295   msaitoh 		timeout--;
   11455  1.295   msaitoh 	}
   11456  1.295   msaitoh 	if (rv != 0)
   11457  1.295   msaitoh 		goto out;
   11458  1.295   msaitoh 	switch (val) {
   11459  1.295   msaitoh 	case SFF_SFP_ID_SFF:
   11460  1.295   msaitoh 		aprint_normal_dev(sc->sc_dev,
   11461  1.295   msaitoh 		    "Module/Connector soldered to board\n");
   11462  1.295   msaitoh 		break;
   11463  1.295   msaitoh 	case SFF_SFP_ID_SFP:
   11464  1.295   msaitoh 		aprint_normal_dev(sc->sc_dev, "SFP\n");
   11465  1.295   msaitoh 		break;
   11466  1.295   msaitoh 	case SFF_SFP_ID_UNKNOWN:
   11467  1.295   msaitoh 		goto out;
   11468  1.295   msaitoh 	default:
   11469  1.295   msaitoh 		break;
   11470  1.295   msaitoh 	}
   11471  1.295   msaitoh 
   11472  1.295   msaitoh 	rv = wm_sfp_read_data_byte(sc, SFF_SFP_ETH_FLAGS_OFF, &val);
   11473  1.295   msaitoh 	if (rv != 0) {
   11474  1.295   msaitoh 		goto out;
   11475  1.295   msaitoh 	}
   11476  1.295   msaitoh 
   11477  1.295   msaitoh 	if ((val & (SFF_SFP_ETH_FLAGS_1000SX | SFF_SFP_ETH_FLAGS_1000LX)) != 0)
   11478  1.311   msaitoh 		mediatype = WM_MEDIATYPE_SERDES;
   11479  1.295   msaitoh 	else if ((val & SFF_SFP_ETH_FLAGS_1000T) != 0){
   11480  1.295   msaitoh 		sc->sc_flags |= WM_F_SGMII;
   11481  1.311   msaitoh 		mediatype = WM_MEDIATYPE_COPPER;
   11482  1.295   msaitoh 	} else if ((val & SFF_SFP_ETH_FLAGS_100FX) != 0){
   11483  1.295   msaitoh 		sc->sc_flags |= WM_F_SGMII;
   11484  1.311   msaitoh 		mediatype = WM_MEDIATYPE_SERDES;
   11485  1.295   msaitoh 	}
   11486  1.295   msaitoh 
   11487  1.295   msaitoh out:
   11488  1.295   msaitoh 	/* Restore I2C interface setting */
   11489  1.295   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   11490  1.295   msaitoh 
   11491  1.295   msaitoh 	return mediatype;
   11492  1.292   msaitoh }
   11493  1.453   msaitoh 
   11494  1.191   msaitoh /*
   11495  1.281   msaitoh  * NVM related.
   11496  1.281   msaitoh  * Microwire, SPI (w/wo EERD) and Flash.
   11497  1.265   msaitoh  */
   11498  1.265   msaitoh 
   11499  1.281   msaitoh /* Both spi and uwire */
   11500  1.265   msaitoh 
   11501  1.265   msaitoh /*
   11502  1.281   msaitoh  * wm_eeprom_sendbits:
   11503  1.199   msaitoh  *
   11504  1.281   msaitoh  *	Send a series of bits to the EEPROM.
   11505  1.199   msaitoh  */
   11506  1.281   msaitoh static void
   11507  1.281   msaitoh wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
   11508  1.199   msaitoh {
   11509  1.281   msaitoh 	uint32_t reg;
   11510  1.281   msaitoh 	int x;
   11511  1.199   msaitoh 
   11512  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   11513  1.199   msaitoh 
   11514  1.281   msaitoh 	for (x = nbits; x > 0; x--) {
   11515  1.281   msaitoh 		if (bits & (1U << (x - 1)))
   11516  1.281   msaitoh 			reg |= EECD_DI;
   11517  1.281   msaitoh 		else
   11518  1.281   msaitoh 			reg &= ~EECD_DI;
   11519  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11520  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11521  1.281   msaitoh 		delay(2);
   11522  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   11523  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11524  1.281   msaitoh 		delay(2);
   11525  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11526  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11527  1.281   msaitoh 		delay(2);
   11528  1.199   msaitoh 	}
   11529  1.199   msaitoh }
   11530  1.199   msaitoh 
   11531  1.199   msaitoh /*
   11532  1.281   msaitoh  * wm_eeprom_recvbits:
   11533  1.199   msaitoh  *
   11534  1.281   msaitoh  *	Receive a series of bits from the EEPROM.
   11535  1.199   msaitoh  */
   11536  1.199   msaitoh static void
   11537  1.281   msaitoh wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
   11538  1.199   msaitoh {
   11539  1.281   msaitoh 	uint32_t reg, val;
   11540  1.281   msaitoh 	int x;
   11541  1.199   msaitoh 
   11542  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
   11543  1.199   msaitoh 
   11544  1.281   msaitoh 	val = 0;
   11545  1.281   msaitoh 	for (x = nbits; x > 0; x--) {
   11546  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   11547  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11548  1.281   msaitoh 		delay(2);
   11549  1.281   msaitoh 		if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
   11550  1.281   msaitoh 			val |= (1U << (x - 1));
   11551  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11552  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11553  1.281   msaitoh 		delay(2);
   11554  1.199   msaitoh 	}
   11555  1.281   msaitoh 	*valp = val;
   11556  1.281   msaitoh }
   11557  1.199   msaitoh 
   11558  1.281   msaitoh /* Microwire */
   11559  1.199   msaitoh 
   11560  1.199   msaitoh /*
   11561  1.281   msaitoh  * wm_nvm_read_uwire:
   11562  1.243   msaitoh  *
   11563  1.281   msaitoh  *	Read a word from the EEPROM using the MicroWire protocol.
   11564  1.243   msaitoh  */
   11565  1.243   msaitoh static int
   11566  1.281   msaitoh wm_nvm_read_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   11567  1.243   msaitoh {
   11568  1.281   msaitoh 	uint32_t reg, val;
   11569  1.281   msaitoh 	int i;
   11570  1.281   msaitoh 
   11571  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11572  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11573  1.420   msaitoh 
   11574  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   11575  1.530   msaitoh 		return -1;
   11576  1.530   msaitoh 
   11577  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11578  1.281   msaitoh 		/* Clear SK and DI. */
   11579  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
   11580  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11581  1.281   msaitoh 
   11582  1.281   msaitoh 		/*
   11583  1.281   msaitoh 		 * XXX: workaround for a bug in qemu-0.12.x and prior
   11584  1.281   msaitoh 		 * and Xen.
   11585  1.281   msaitoh 		 *
   11586  1.281   msaitoh 		 * We use this workaround only for 82540 because qemu's
   11587  1.281   msaitoh 		 * e1000 act as 82540.
   11588  1.281   msaitoh 		 */
   11589  1.281   msaitoh 		if (sc->sc_type == WM_T_82540) {
   11590  1.281   msaitoh 			reg |= EECD_SK;
   11591  1.281   msaitoh 			CSR_WRITE(sc, WMREG_EECD, reg);
   11592  1.281   msaitoh 			reg &= ~EECD_SK;
   11593  1.281   msaitoh 			CSR_WRITE(sc, WMREG_EECD, reg);
   11594  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   11595  1.281   msaitoh 			delay(2);
   11596  1.281   msaitoh 		}
   11597  1.281   msaitoh 		/* XXX: end of workaround */
   11598  1.332   msaitoh 
   11599  1.281   msaitoh 		/* Set CHIP SELECT. */
   11600  1.281   msaitoh 		reg |= EECD_CS;
   11601  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11602  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11603  1.281   msaitoh 		delay(2);
   11604  1.281   msaitoh 
   11605  1.281   msaitoh 		/* Shift in the READ command. */
   11606  1.281   msaitoh 		wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
   11607  1.281   msaitoh 
   11608  1.281   msaitoh 		/* Shift in address. */
   11609  1.294   msaitoh 		wm_eeprom_sendbits(sc, word + i, sc->sc_nvm_addrbits);
   11610  1.281   msaitoh 
   11611  1.281   msaitoh 		/* Shift out the data. */
   11612  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 16);
   11613  1.281   msaitoh 		data[i] = val & 0xffff;
   11614  1.243   msaitoh 
   11615  1.281   msaitoh 		/* Clear CHIP SELECT. */
   11616  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
   11617  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11618  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11619  1.281   msaitoh 		delay(2);
   11620  1.243   msaitoh 	}
   11621  1.243   msaitoh 
   11622  1.530   msaitoh 	sc->nvm.release(sc);
   11623  1.281   msaitoh 	return 0;
   11624  1.281   msaitoh }
   11625  1.243   msaitoh 
   11626  1.281   msaitoh /* SPI */
   11627  1.243   msaitoh 
   11628  1.294   msaitoh /*
   11629  1.294   msaitoh  * Set SPI and FLASH related information from the EECD register.
   11630  1.294   msaitoh  * For 82541 and 82547, the word size is taken from EEPROM.
   11631  1.294   msaitoh  */
   11632  1.294   msaitoh static int
   11633  1.294   msaitoh wm_nvm_set_addrbits_size_eecd(struct wm_softc *sc)
   11634  1.243   msaitoh {
   11635  1.294   msaitoh 	int size;
   11636  1.281   msaitoh 	uint32_t reg;
   11637  1.294   msaitoh 	uint16_t data;
   11638  1.243   msaitoh 
   11639  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   11640  1.294   msaitoh 	sc->sc_nvm_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
   11641  1.294   msaitoh 
   11642  1.294   msaitoh 	/* Read the size of NVM from EECD by default */
   11643  1.294   msaitoh 	size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);
   11644  1.294   msaitoh 	switch (sc->sc_type) {
   11645  1.294   msaitoh 	case WM_T_82541:
   11646  1.294   msaitoh 	case WM_T_82541_2:
   11647  1.294   msaitoh 	case WM_T_82547:
   11648  1.294   msaitoh 	case WM_T_82547_2:
   11649  1.294   msaitoh 		/* Set dummy value to access EEPROM */
   11650  1.294   msaitoh 		sc->sc_nvm_wordsize = 64;
   11651  1.535   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_EEPROM_SIZE, 1, &data) != 0) {
   11652  1.535   msaitoh 			aprint_error_dev(sc->sc_dev,
   11653  1.535   msaitoh 			    "%s: failed to read EEPROM size\n", __func__);
   11654  1.535   msaitoh 		}
   11655  1.294   msaitoh 		reg = data;
   11656  1.294   msaitoh 		size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);
   11657  1.294   msaitoh 		if (size == 0)
   11658  1.294   msaitoh 			size = 6; /* 64 word size */
   11659  1.294   msaitoh 		else
   11660  1.294   msaitoh 			size += NVM_WORD_SIZE_BASE_SHIFT + 1;
   11661  1.294   msaitoh 		break;
   11662  1.294   msaitoh 	case WM_T_80003:
   11663  1.294   msaitoh 	case WM_T_82571:
   11664  1.294   msaitoh 	case WM_T_82572:
   11665  1.294   msaitoh 	case WM_T_82573: /* SPI case */
   11666  1.294   msaitoh 	case WM_T_82574: /* SPI case */
   11667  1.294   msaitoh 	case WM_T_82583: /* SPI case */
   11668  1.294   msaitoh 		size += NVM_WORD_SIZE_BASE_SHIFT;
   11669  1.294   msaitoh 		if (size > 14)
   11670  1.294   msaitoh 			size = 14;
   11671  1.294   msaitoh 		break;
   11672  1.294   msaitoh 	case WM_T_82575:
   11673  1.294   msaitoh 	case WM_T_82576:
   11674  1.294   msaitoh 	case WM_T_82580:
   11675  1.294   msaitoh 	case WM_T_I350:
   11676  1.294   msaitoh 	case WM_T_I354:
   11677  1.294   msaitoh 	case WM_T_I210:
   11678  1.294   msaitoh 	case WM_T_I211:
   11679  1.294   msaitoh 		size += NVM_WORD_SIZE_BASE_SHIFT;
   11680  1.294   msaitoh 		if (size > 15)
   11681  1.294   msaitoh 			size = 15;
   11682  1.294   msaitoh 		break;
   11683  1.294   msaitoh 	default:
   11684  1.294   msaitoh 		aprint_error_dev(sc->sc_dev,
   11685  1.294   msaitoh 		    "%s: unknown device(%d)?\n", __func__, sc->sc_type);
   11686  1.294   msaitoh 		return -1;
   11687  1.294   msaitoh 		break;
   11688  1.294   msaitoh 	}
   11689  1.294   msaitoh 
   11690  1.294   msaitoh 	sc->sc_nvm_wordsize = 1 << size;
   11691  1.294   msaitoh 
   11692  1.294   msaitoh 	return 0;
   11693  1.243   msaitoh }
   11694  1.243   msaitoh 
   11695  1.243   msaitoh /*
   11696  1.281   msaitoh  * wm_nvm_ready_spi:
   11697    1.1   thorpej  *
   11698  1.281   msaitoh  *	Wait for a SPI EEPROM to be ready for commands.
   11699    1.1   thorpej  */
   11700  1.281   msaitoh static int
   11701  1.281   msaitoh wm_nvm_ready_spi(struct wm_softc *sc)
   11702    1.1   thorpej {
   11703  1.281   msaitoh 	uint32_t val;
   11704  1.281   msaitoh 	int usec;
   11705    1.1   thorpej 
   11706  1.421   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11707  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   11708  1.421   msaitoh 
   11709  1.281   msaitoh 	for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) {
   11710  1.281   msaitoh 		wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8);
   11711  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 8);
   11712  1.281   msaitoh 		if ((val & SPI_SR_RDY) == 0)
   11713  1.281   msaitoh 			break;
   11714   1.71   thorpej 	}
   11715  1.281   msaitoh 	if (usec >= SPI_MAX_RETRIES) {
   11716  1.388   msaitoh 		aprint_error_dev(sc->sc_dev,"EEPROM failed to become ready\n");
   11717  1.530   msaitoh 		return -1;
   11718  1.127    bouyer 	}
   11719  1.281   msaitoh 	return 0;
   11720  1.127    bouyer }
   11721  1.127    bouyer 
   11722  1.127    bouyer /*
   11723  1.281   msaitoh  * wm_nvm_read_spi:
   11724  1.127    bouyer  *
   11725  1.281   msaitoh  *	Read a work from the EEPROM using the SPI protocol.
   11726  1.127    bouyer  */
   11727  1.127    bouyer static int
   11728  1.281   msaitoh wm_nvm_read_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   11729  1.127    bouyer {
   11730  1.281   msaitoh 	uint32_t reg, val;
   11731  1.281   msaitoh 	int i;
   11732  1.281   msaitoh 	uint8_t opc;
   11733  1.530   msaitoh 	int rv = 0;
   11734  1.281   msaitoh 
   11735  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11736  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11737  1.420   msaitoh 
   11738  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   11739  1.530   msaitoh 		return -1;
   11740  1.530   msaitoh 
   11741  1.281   msaitoh 	/* Clear SK and CS. */
   11742  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
   11743  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11744  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11745  1.281   msaitoh 	delay(2);
   11746  1.127    bouyer 
   11747  1.530   msaitoh 	if ((rv = wm_nvm_ready_spi(sc)) != 0)
   11748  1.530   msaitoh 		goto out;
   11749  1.127    bouyer 
   11750  1.281   msaitoh 	/* Toggle CS to flush commands. */
   11751  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
   11752  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11753  1.281   msaitoh 	delay(2);
   11754  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11755  1.266   msaitoh 	CSR_WRITE_FLUSH(sc);
   11756  1.127    bouyer 	delay(2);
   11757  1.127    bouyer 
   11758  1.281   msaitoh 	opc = SPI_OPC_READ;
   11759  1.294   msaitoh 	if (sc->sc_nvm_addrbits == 8 && word >= 128)
   11760  1.281   msaitoh 		opc |= SPI_OPC_A8;
   11761  1.281   msaitoh 
   11762  1.281   msaitoh 	wm_eeprom_sendbits(sc, opc, 8);
   11763  1.294   msaitoh 	wm_eeprom_sendbits(sc, word << 1, sc->sc_nvm_addrbits);
   11764  1.281   msaitoh 
   11765  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11766  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 16);
   11767  1.281   msaitoh 		data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
   11768  1.281   msaitoh 	}
   11769  1.178   msaitoh 
   11770  1.281   msaitoh 	/* Raise CS and clear SK. */
   11771  1.281   msaitoh 	reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
   11772  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11773  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11774  1.281   msaitoh 	delay(2);
   11775  1.178   msaitoh 
   11776  1.530   msaitoh out:
   11777  1.530   msaitoh 	sc->nvm.release(sc);
   11778  1.530   msaitoh 	return rv;
   11779  1.127    bouyer }
   11780  1.127    bouyer 
   11781  1.281   msaitoh /* Using with EERD */
   11782  1.281   msaitoh 
   11783  1.281   msaitoh static int
   11784  1.281   msaitoh wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
   11785  1.127    bouyer {
   11786  1.281   msaitoh 	uint32_t attempts = 100000;
   11787  1.281   msaitoh 	uint32_t i, reg = 0;
   11788  1.281   msaitoh 	int32_t done = -1;
   11789  1.281   msaitoh 
   11790  1.281   msaitoh 	for (i = 0; i < attempts; i++) {
   11791  1.281   msaitoh 		reg = CSR_READ(sc, rw);
   11792  1.127    bouyer 
   11793  1.281   msaitoh 		if (reg & EERD_DONE) {
   11794  1.281   msaitoh 			done = 0;
   11795  1.281   msaitoh 			break;
   11796  1.178   msaitoh 		}
   11797  1.281   msaitoh 		delay(5);
   11798  1.169   msaitoh 	}
   11799  1.127    bouyer 
   11800  1.281   msaitoh 	return done;
   11801    1.1   thorpej }
   11802  1.117   msaitoh 
   11803  1.117   msaitoh static int
   11804  1.281   msaitoh wm_nvm_read_eerd(struct wm_softc *sc, int offset, int wordcnt,
   11805  1.281   msaitoh     uint16_t *data)
   11806  1.117   msaitoh {
   11807  1.281   msaitoh 	int i, eerd = 0;
   11808  1.530   msaitoh 	int rv = 0;
   11809  1.117   msaitoh 
   11810  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11811  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11812  1.420   msaitoh 
   11813  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   11814  1.530   msaitoh 		return -1;
   11815  1.530   msaitoh 
   11816  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11817  1.281   msaitoh 		eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
   11818  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EERD, eerd);
   11819  1.530   msaitoh 		rv = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
   11820  1.530   msaitoh 		if (rv != 0) {
   11821  1.539   msaitoh 			aprint_error_dev(sc->sc_dev, "EERD polling failed: "
   11822  1.539   msaitoh 			    "offset=%d. wordcnt=%d\n", offset, wordcnt);
   11823  1.281   msaitoh 			break;
   11824  1.530   msaitoh 		}
   11825  1.281   msaitoh 		data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
   11826  1.117   msaitoh 	}
   11827  1.281   msaitoh 
   11828  1.530   msaitoh 	sc->nvm.release(sc);
   11829  1.530   msaitoh 	return rv;
   11830  1.117   msaitoh }
   11831  1.117   msaitoh 
   11832  1.281   msaitoh /* Flash */
   11833  1.281   msaitoh 
   11834  1.117   msaitoh static int
   11835  1.281   msaitoh wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank)
   11836  1.117   msaitoh {
   11837  1.281   msaitoh 	uint32_t eecd;
   11838  1.281   msaitoh 	uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1;
   11839  1.281   msaitoh 	uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t);
   11840  1.281   msaitoh 	uint8_t sig_byte = 0;
   11841  1.117   msaitoh 
   11842  1.281   msaitoh 	switch (sc->sc_type) {
   11843  1.392   msaitoh 	case WM_T_PCH_SPT:
   11844  1.392   msaitoh 		/*
   11845  1.392   msaitoh 		 * In SPT, read from the CTRL_EXT reg instead of accessing the
   11846  1.392   msaitoh 		 * sector valid bits from the NVM.
   11847  1.392   msaitoh 		 */
   11848  1.392   msaitoh 		*bank = CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_NVMVS;
   11849  1.392   msaitoh 		if ((*bank == 0) || (*bank == 1)) {
   11850  1.392   msaitoh 			aprint_error_dev(sc->sc_dev,
   11851  1.424   msaitoh 			    "%s: no valid NVM bank present (%u)\n", __func__,
   11852  1.424   msaitoh 				*bank);
   11853  1.392   msaitoh 			return -1;
   11854  1.392   msaitoh 		} else {
   11855  1.392   msaitoh 			*bank = *bank - 2;
   11856  1.392   msaitoh 			return 0;
   11857  1.392   msaitoh 		}
   11858  1.281   msaitoh 	case WM_T_ICH8:
   11859  1.281   msaitoh 	case WM_T_ICH9:
   11860  1.281   msaitoh 		eecd = CSR_READ(sc, WMREG_EECD);
   11861  1.281   msaitoh 		if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) {
   11862  1.281   msaitoh 			*bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0;
   11863  1.281   msaitoh 			return 0;
   11864  1.281   msaitoh 		}
   11865  1.281   msaitoh 		/* FALLTHROUGH */
   11866  1.281   msaitoh 	default:
   11867  1.281   msaitoh 		/* Default to 0 */
   11868  1.281   msaitoh 		*bank = 0;
   11869  1.271     ozaki 
   11870  1.281   msaitoh 		/* Check bank 0 */
   11871  1.281   msaitoh 		wm_read_ich8_byte(sc, act_offset, &sig_byte);
   11872  1.281   msaitoh 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
   11873  1.281   msaitoh 			*bank = 0;
   11874  1.281   msaitoh 			return 0;
   11875  1.281   msaitoh 		}
   11876  1.271     ozaki 
   11877  1.281   msaitoh 		/* Check bank 1 */
   11878  1.281   msaitoh 		wm_read_ich8_byte(sc, act_offset + bank1_offset,
   11879  1.281   msaitoh 		    &sig_byte);
   11880  1.281   msaitoh 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
   11881  1.281   msaitoh 			*bank = 1;
   11882  1.281   msaitoh 			return 0;
   11883  1.281   msaitoh 		}
   11884  1.271     ozaki 	}
   11885  1.271     ozaki 
   11886  1.281   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: No valid NVM bank present\n",
   11887  1.281   msaitoh 		device_xname(sc->sc_dev)));
   11888  1.281   msaitoh 	return -1;
   11889  1.281   msaitoh }
   11890  1.281   msaitoh 
   11891  1.281   msaitoh /******************************************************************************
   11892  1.281   msaitoh  * This function does initial flash setup so that a new read/write/erase cycle
   11893  1.281   msaitoh  * can be started.
   11894  1.281   msaitoh  *
   11895  1.281   msaitoh  * sc - The pointer to the hw structure
   11896  1.281   msaitoh  ****************************************************************************/
   11897  1.281   msaitoh static int32_t
   11898  1.281   msaitoh wm_ich8_cycle_init(struct wm_softc *sc)
   11899  1.281   msaitoh {
   11900  1.281   msaitoh 	uint16_t hsfsts;
   11901  1.281   msaitoh 	int32_t error = 1;
   11902  1.281   msaitoh 	int32_t i     = 0;
   11903  1.271     ozaki 
   11904  1.281   msaitoh 	hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   11905  1.117   msaitoh 
   11906  1.281   msaitoh 	/* May be check the Flash Des Valid bit in Hw status */
   11907  1.281   msaitoh 	if ((hsfsts & HSFSTS_FLDVAL) == 0) {
   11908  1.281   msaitoh 		return error;
   11909  1.117   msaitoh 	}
   11910  1.117   msaitoh 
   11911  1.281   msaitoh 	/* Clear FCERR in Hw status by writing 1 */
   11912  1.281   msaitoh 	/* Clear DAEL in Hw status by writing a 1 */
   11913  1.281   msaitoh 	hsfsts |= HSFSTS_ERR | HSFSTS_DAEL;
   11914  1.117   msaitoh 
   11915  1.281   msaitoh 	ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   11916  1.117   msaitoh 
   11917  1.281   msaitoh 	/*
   11918  1.281   msaitoh 	 * Either we should have a hardware SPI cycle in progress bit to check
   11919  1.281   msaitoh 	 * against, in order to start a new cycle or FDONE bit should be
   11920  1.281   msaitoh 	 * changed in the hardware so that it is 1 after harware reset, which
   11921  1.281   msaitoh 	 * can then be used as an indication whether a cycle is in progress or
   11922  1.281   msaitoh 	 * has been completed .. we should also have some software semaphore
   11923  1.281   msaitoh 	 * mechanism to guard FDONE or the cycle in progress bit so that two
   11924  1.281   msaitoh 	 * threads access to those bits can be sequentiallized or a way so that
   11925  1.281   msaitoh 	 * 2 threads dont start the cycle at the same time
   11926  1.281   msaitoh 	 */
   11927  1.127    bouyer 
   11928  1.281   msaitoh 	if ((hsfsts & HSFSTS_FLINPRO) == 0) {
   11929  1.281   msaitoh 		/*
   11930  1.281   msaitoh 		 * There is no cycle running at present, so we can start a
   11931  1.281   msaitoh 		 * cycle
   11932  1.281   msaitoh 		 */
   11933  1.127    bouyer 
   11934  1.281   msaitoh 		/* Begin by setting Flash Cycle Done. */
   11935  1.281   msaitoh 		hsfsts |= HSFSTS_DONE;
   11936  1.281   msaitoh 		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   11937  1.281   msaitoh 		error = 0;
   11938  1.281   msaitoh 	} else {
   11939  1.281   msaitoh 		/*
   11940  1.281   msaitoh 		 * otherwise poll for sometime so the current cycle has a
   11941  1.281   msaitoh 		 * chance to end before giving up.
   11942  1.281   msaitoh 		 */
   11943  1.281   msaitoh 		for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
   11944  1.281   msaitoh 			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   11945  1.281   msaitoh 			if ((hsfsts & HSFSTS_FLINPRO) == 0) {
   11946  1.281   msaitoh 				error = 0;
   11947  1.281   msaitoh 				break;
   11948  1.169   msaitoh 			}
   11949  1.281   msaitoh 			delay(1);
   11950  1.127    bouyer 		}
   11951  1.281   msaitoh 		if (error == 0) {
   11952  1.281   msaitoh 			/*
   11953  1.281   msaitoh 			 * Successful in waiting for previous cycle to timeout,
   11954  1.281   msaitoh 			 * now set the Flash Cycle Done.
   11955  1.281   msaitoh 			 */
   11956  1.281   msaitoh 			hsfsts |= HSFSTS_DONE;
   11957  1.281   msaitoh 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   11958  1.127    bouyer 		}
   11959  1.127    bouyer 	}
   11960  1.281   msaitoh 	return error;
   11961  1.127    bouyer }
   11962  1.127    bouyer 
   11963  1.281   msaitoh /******************************************************************************
   11964  1.281   msaitoh  * This function starts a flash cycle and waits for its completion
   11965  1.281   msaitoh  *
   11966  1.281   msaitoh  * sc - The pointer to the hw structure
   11967  1.281   msaitoh  ****************************************************************************/
   11968  1.281   msaitoh static int32_t
   11969  1.281   msaitoh wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout)
   11970  1.136   msaitoh {
   11971  1.281   msaitoh 	uint16_t hsflctl;
   11972  1.281   msaitoh 	uint16_t hsfsts;
   11973  1.281   msaitoh 	int32_t error = 1;
   11974  1.281   msaitoh 	uint32_t i = 0;
   11975  1.127    bouyer 
   11976  1.281   msaitoh 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
   11977  1.281   msaitoh 	hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
   11978  1.281   msaitoh 	hsflctl |= HSFCTL_GO;
   11979  1.281   msaitoh 	ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
   11980  1.139    bouyer 
   11981  1.281   msaitoh 	/* Wait till FDONE bit is set to 1 */
   11982  1.281   msaitoh 	do {
   11983  1.281   msaitoh 		hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   11984  1.281   msaitoh 		if (hsfsts & HSFSTS_DONE)
   11985  1.281   msaitoh 			break;
   11986  1.281   msaitoh 		delay(1);
   11987  1.281   msaitoh 		i++;
   11988  1.281   msaitoh 	} while (i < timeout);
   11989  1.281   msaitoh 	if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0)
   11990  1.281   msaitoh 		error = 0;
   11991  1.139    bouyer 
   11992  1.281   msaitoh 	return error;
   11993  1.139    bouyer }
   11994  1.139    bouyer 
   11995  1.281   msaitoh /******************************************************************************
   11996  1.392   msaitoh  * Reads a byte or (d)word from the NVM using the ICH8 flash access registers.
   11997  1.281   msaitoh  *
   11998  1.281   msaitoh  * sc - The pointer to the hw structure
   11999  1.281   msaitoh  * index - The index of the byte or word to read.
   12000  1.392   msaitoh  * size - Size of data to read, 1=byte 2=word, 4=dword
   12001  1.281   msaitoh  * data - Pointer to the word to store the value read.
   12002  1.281   msaitoh  *****************************************************************************/
   12003  1.281   msaitoh static int32_t
   12004  1.281   msaitoh wm_read_ich8_data(struct wm_softc *sc, uint32_t index,
   12005  1.392   msaitoh     uint32_t size, uint32_t *data)
   12006  1.139    bouyer {
   12007  1.281   msaitoh 	uint16_t hsfsts;
   12008  1.281   msaitoh 	uint16_t hsflctl;
   12009  1.281   msaitoh 	uint32_t flash_linear_address;
   12010  1.281   msaitoh 	uint32_t flash_data = 0;
   12011  1.281   msaitoh 	int32_t error = 1;
   12012  1.281   msaitoh 	int32_t count = 0;
   12013  1.281   msaitoh 
   12014  1.392   msaitoh 	if (size < 1  || size > 4 || data == 0x0 ||
   12015  1.281   msaitoh 	    index > ICH_FLASH_LINEAR_ADDR_MASK)
   12016  1.281   msaitoh 		return error;
   12017  1.139    bouyer 
   12018  1.281   msaitoh 	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
   12019  1.281   msaitoh 	    sc->sc_ich8_flash_base;
   12020  1.259   msaitoh 
   12021  1.259   msaitoh 	do {
   12022  1.281   msaitoh 		delay(1);
   12023  1.281   msaitoh 		/* Steps */
   12024  1.281   msaitoh 		error = wm_ich8_cycle_init(sc);
   12025  1.281   msaitoh 		if (error)
   12026  1.259   msaitoh 			break;
   12027  1.259   msaitoh 
   12028  1.281   msaitoh 		hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
   12029  1.281   msaitoh 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
   12030  1.281   msaitoh 		hsflctl |=  ((size - 1) << HSFCTL_BCOUNT_SHIFT)
   12031  1.281   msaitoh 		    & HSFCTL_BCOUNT_MASK;
   12032  1.281   msaitoh 		hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT;
   12033  1.392   msaitoh 		if (sc->sc_type == WM_T_PCH_SPT) {
   12034  1.392   msaitoh 			/*
   12035  1.392   msaitoh 			 * In SPT, This register is in Lan memory space, not
   12036  1.392   msaitoh 			 * flash. Therefore, only 32 bit access is supported.
   12037  1.392   msaitoh 			 */
   12038  1.392   msaitoh 			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFCTL,
   12039  1.392   msaitoh 			    (uint32_t)hsflctl);
   12040  1.392   msaitoh 		} else
   12041  1.392   msaitoh 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
   12042  1.281   msaitoh 
   12043  1.281   msaitoh 		/*
   12044  1.281   msaitoh 		 * Write the last 24 bits of index into Flash Linear address
   12045  1.281   msaitoh 		 * field in Flash Address
   12046  1.281   msaitoh 		 */
   12047  1.281   msaitoh 		/* TODO: TBD maybe check the index against the size of flash */
   12048  1.281   msaitoh 
   12049  1.281   msaitoh 		ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address);
   12050  1.259   msaitoh 
   12051  1.281   msaitoh 		error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT);
   12052  1.259   msaitoh 
   12053  1.281   msaitoh 		/*
   12054  1.281   msaitoh 		 * Check if FCERR is set to 1, if set to 1, clear it and try
   12055  1.281   msaitoh 		 * the whole sequence a few more times, else read in (shift in)
   12056  1.281   msaitoh 		 * the Flash Data0, the order is least significant byte first
   12057  1.281   msaitoh 		 * msb to lsb
   12058  1.281   msaitoh 		 */
   12059  1.281   msaitoh 		if (error == 0) {
   12060  1.281   msaitoh 			flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0);
   12061  1.281   msaitoh 			if (size == 1)
   12062  1.281   msaitoh 				*data = (uint8_t)(flash_data & 0x000000FF);
   12063  1.281   msaitoh 			else if (size == 2)
   12064  1.281   msaitoh 				*data = (uint16_t)(flash_data & 0x0000FFFF);
   12065  1.392   msaitoh 			else if (size == 4)
   12066  1.392   msaitoh 				*data = (uint32_t)flash_data;
   12067  1.281   msaitoh 			break;
   12068  1.281   msaitoh 		} else {
   12069  1.281   msaitoh 			/*
   12070  1.281   msaitoh 			 * If we've gotten here, then things are probably
   12071  1.281   msaitoh 			 * completely hosed, but if the error condition is
   12072  1.281   msaitoh 			 * detected, it won't hurt to give it another try...
   12073  1.281   msaitoh 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
   12074  1.281   msaitoh 			 */
   12075  1.281   msaitoh 			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   12076  1.281   msaitoh 			if (hsfsts & HSFSTS_ERR) {
   12077  1.281   msaitoh 				/* Repeat for some time before giving up. */
   12078  1.281   msaitoh 				continue;
   12079  1.281   msaitoh 			} else if ((hsfsts & HSFSTS_DONE) == 0)
   12080  1.281   msaitoh 				break;
   12081  1.281   msaitoh 		}
   12082  1.281   msaitoh 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
   12083  1.259   msaitoh 
   12084  1.281   msaitoh 	return error;
   12085  1.259   msaitoh }
   12086  1.259   msaitoh 
   12087  1.281   msaitoh /******************************************************************************
   12088  1.281   msaitoh  * Reads a single byte from the NVM using the ICH8 flash access registers.
   12089  1.281   msaitoh  *
   12090  1.281   msaitoh  * sc - pointer to wm_hw structure
   12091  1.281   msaitoh  * index - The index of the byte to read.
   12092  1.281   msaitoh  * data - Pointer to a byte to store the value read.
   12093  1.281   msaitoh  *****************************************************************************/
   12094  1.281   msaitoh static int32_t
   12095  1.281   msaitoh wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data)
   12096  1.169   msaitoh {
   12097  1.281   msaitoh 	int32_t status;
   12098  1.392   msaitoh 	uint32_t word = 0;
   12099  1.250   msaitoh 
   12100  1.281   msaitoh 	status = wm_read_ich8_data(sc, index, 1, &word);
   12101  1.281   msaitoh 	if (status == 0)
   12102  1.281   msaitoh 		*data = (uint8_t)word;
   12103  1.281   msaitoh 	else
   12104  1.281   msaitoh 		*data = 0;
   12105  1.169   msaitoh 
   12106  1.281   msaitoh 	return status;
   12107  1.281   msaitoh }
   12108  1.250   msaitoh 
   12109  1.281   msaitoh /******************************************************************************
   12110  1.281   msaitoh  * Reads a word from the NVM using the ICH8 flash access registers.
   12111  1.281   msaitoh  *
   12112  1.281   msaitoh  * sc - pointer to wm_hw structure
   12113  1.281   msaitoh  * index - The starting byte index of the word to read.
   12114  1.281   msaitoh  * data - Pointer to a word to store the value read.
   12115  1.281   msaitoh  *****************************************************************************/
   12116  1.281   msaitoh static int32_t
   12117  1.281   msaitoh wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data)
   12118  1.281   msaitoh {
   12119  1.281   msaitoh 	int32_t status;
   12120  1.392   msaitoh 	uint32_t word = 0;
   12121  1.392   msaitoh 
   12122  1.392   msaitoh 	status = wm_read_ich8_data(sc, index, 2, &word);
   12123  1.392   msaitoh 	if (status == 0)
   12124  1.392   msaitoh 		*data = (uint16_t)word;
   12125  1.392   msaitoh 	else
   12126  1.392   msaitoh 		*data = 0;
   12127  1.392   msaitoh 
   12128  1.392   msaitoh 	return status;
   12129  1.392   msaitoh }
   12130  1.392   msaitoh 
   12131  1.392   msaitoh /******************************************************************************
   12132  1.392   msaitoh  * Reads a dword from the NVM using the ICH8 flash access registers.
   12133  1.392   msaitoh  *
   12134  1.392   msaitoh  * sc - pointer to wm_hw structure
   12135  1.392   msaitoh  * index - The starting byte index of the word to read.
   12136  1.392   msaitoh  * data - Pointer to a word to store the value read.
   12137  1.392   msaitoh  *****************************************************************************/
   12138  1.392   msaitoh static int32_t
   12139  1.392   msaitoh wm_read_ich8_dword(struct wm_softc *sc, uint32_t index, uint32_t *data)
   12140  1.392   msaitoh {
   12141  1.392   msaitoh 	int32_t status;
   12142  1.169   msaitoh 
   12143  1.392   msaitoh 	status = wm_read_ich8_data(sc, index, 4, data);
   12144  1.281   msaitoh 	return status;
   12145  1.169   msaitoh }
   12146  1.169   msaitoh 
   12147  1.139    bouyer /******************************************************************************
   12148  1.139    bouyer  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
   12149  1.139    bouyer  * register.
   12150  1.139    bouyer  *
   12151  1.139    bouyer  * sc - Struct containing variables accessed by shared code
   12152  1.139    bouyer  * offset - offset of word in the EEPROM to read
   12153  1.139    bouyer  * data - word read from the EEPROM
   12154  1.139    bouyer  * words - number of words to read
   12155  1.139    bouyer  *****************************************************************************/
   12156  1.139    bouyer static int
   12157  1.280   msaitoh wm_nvm_read_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data)
   12158  1.139    bouyer {
   12159  1.530   msaitoh 	int32_t  rv = 0;
   12160  1.194   msaitoh 	uint32_t flash_bank = 0;
   12161  1.194   msaitoh 	uint32_t act_offset = 0;
   12162  1.194   msaitoh 	uint32_t bank_offset = 0;
   12163  1.194   msaitoh 	uint16_t word = 0;
   12164  1.194   msaitoh 	uint16_t i = 0;
   12165  1.194   msaitoh 
   12166  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12167  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12168  1.420   msaitoh 
   12169  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   12170  1.530   msaitoh 		return -1;
   12171  1.530   msaitoh 
   12172  1.281   msaitoh 	/*
   12173  1.281   msaitoh 	 * We need to know which is the valid flash bank.  In the event
   12174  1.194   msaitoh 	 * that we didn't allocate eeprom_shadow_ram, we may not be
   12175  1.194   msaitoh 	 * managing flash_bank.  So it cannot be trusted and needs
   12176  1.194   msaitoh 	 * to be updated with each read.
   12177  1.194   msaitoh 	 */
   12178  1.530   msaitoh 	rv = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
   12179  1.530   msaitoh 	if (rv) {
   12180  1.297   msaitoh 		DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
   12181  1.297   msaitoh 			device_xname(sc->sc_dev)));
   12182  1.262   msaitoh 		flash_bank = 0;
   12183  1.194   msaitoh 	}
   12184  1.139    bouyer 
   12185  1.238   msaitoh 	/*
   12186  1.238   msaitoh 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
   12187  1.238   msaitoh 	 * size
   12188  1.238   msaitoh 	 */
   12189  1.194   msaitoh 	bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
   12190  1.139    bouyer 
   12191  1.194   msaitoh 	for (i = 0; i < words; i++) {
   12192  1.194   msaitoh 		/* The NVM part needs a byte offset, hence * 2 */
   12193  1.194   msaitoh 		act_offset = bank_offset + ((offset + i) * 2);
   12194  1.530   msaitoh 		rv = wm_read_ich8_word(sc, act_offset, &word);
   12195  1.530   msaitoh 		if (rv) {
   12196  1.238   msaitoh 			aprint_error_dev(sc->sc_dev,
   12197  1.238   msaitoh 			    "%s: failed to read NVM\n", __func__);
   12198  1.194   msaitoh 			break;
   12199  1.194   msaitoh 		}
   12200  1.194   msaitoh 		data[i] = word;
   12201  1.194   msaitoh 	}
   12202  1.194   msaitoh 
   12203  1.530   msaitoh 	sc->nvm.release(sc);
   12204  1.530   msaitoh 	return rv;
   12205  1.139    bouyer }
   12206  1.139    bouyer 
   12207  1.392   msaitoh /******************************************************************************
   12208  1.392   msaitoh  * Reads a 16 bit word or words from the EEPROM using the SPT's flash access
   12209  1.392   msaitoh  * register.
   12210  1.392   msaitoh  *
   12211  1.392   msaitoh  * sc - Struct containing variables accessed by shared code
   12212  1.392   msaitoh  * offset - offset of word in the EEPROM to read
   12213  1.392   msaitoh  * data - word read from the EEPROM
   12214  1.392   msaitoh  * words - number of words to read
   12215  1.392   msaitoh  *****************************************************************************/
   12216  1.392   msaitoh static int
   12217  1.392   msaitoh wm_nvm_read_spt(struct wm_softc *sc, int offset, int words, uint16_t *data)
   12218  1.392   msaitoh {
   12219  1.530   msaitoh 	int32_t  rv = 0;
   12220  1.392   msaitoh 	uint32_t flash_bank = 0;
   12221  1.392   msaitoh 	uint32_t act_offset = 0;
   12222  1.392   msaitoh 	uint32_t bank_offset = 0;
   12223  1.392   msaitoh 	uint32_t dword = 0;
   12224  1.392   msaitoh 	uint16_t i = 0;
   12225  1.392   msaitoh 
   12226  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12227  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12228  1.420   msaitoh 
   12229  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   12230  1.530   msaitoh 		return -1;
   12231  1.530   msaitoh 
   12232  1.392   msaitoh 	/*
   12233  1.392   msaitoh 	 * We need to know which is the valid flash bank.  In the event
   12234  1.392   msaitoh 	 * that we didn't allocate eeprom_shadow_ram, we may not be
   12235  1.392   msaitoh 	 * managing flash_bank.  So it cannot be trusted and needs
   12236  1.392   msaitoh 	 * to be updated with each read.
   12237  1.392   msaitoh 	 */
   12238  1.530   msaitoh 	rv = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
   12239  1.530   msaitoh 	if (rv) {
   12240  1.392   msaitoh 		DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
   12241  1.392   msaitoh 			device_xname(sc->sc_dev)));
   12242  1.392   msaitoh 		flash_bank = 0;
   12243  1.392   msaitoh 	}
   12244  1.392   msaitoh 
   12245  1.392   msaitoh 	/*
   12246  1.392   msaitoh 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
   12247  1.392   msaitoh 	 * size
   12248  1.392   msaitoh 	 */
   12249  1.392   msaitoh 	bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
   12250  1.392   msaitoh 
   12251  1.392   msaitoh 	for (i = 0; i < words; i++) {
   12252  1.392   msaitoh 		/* The NVM part needs a byte offset, hence * 2 */
   12253  1.392   msaitoh 		act_offset = bank_offset + ((offset + i) * 2);
   12254  1.392   msaitoh 		/* but we must read dword aligned, so mask ... */
   12255  1.530   msaitoh 		rv = wm_read_ich8_dword(sc, act_offset & ~0x3, &dword);
   12256  1.530   msaitoh 		if (rv) {
   12257  1.392   msaitoh 			aprint_error_dev(sc->sc_dev,
   12258  1.392   msaitoh 			    "%s: failed to read NVM\n", __func__);
   12259  1.392   msaitoh 			break;
   12260  1.392   msaitoh 		}
   12261  1.392   msaitoh 		/* ... and pick out low or high word */
   12262  1.392   msaitoh 		if ((act_offset & 0x2) == 0)
   12263  1.392   msaitoh 			data[i] = (uint16_t)(dword & 0xFFFF);
   12264  1.392   msaitoh 		else
   12265  1.392   msaitoh 			data[i] = (uint16_t)((dword >> 16) & 0xFFFF);
   12266  1.392   msaitoh 	}
   12267  1.392   msaitoh 
   12268  1.530   msaitoh 	sc->nvm.release(sc);
   12269  1.530   msaitoh 	return rv;
   12270  1.392   msaitoh }
   12271  1.392   msaitoh 
   12272  1.321   msaitoh /* iNVM */
   12273  1.321   msaitoh 
   12274  1.321   msaitoh static int
   12275  1.321   msaitoh wm_nvm_read_word_invm(struct wm_softc *sc, uint16_t address, uint16_t *data)
   12276  1.321   msaitoh {
   12277  1.321   msaitoh 	int32_t  rv = 0;
   12278  1.321   msaitoh 	uint32_t invm_dword;
   12279  1.321   msaitoh 	uint16_t i;
   12280  1.321   msaitoh 	uint8_t record_type, word_address;
   12281  1.321   msaitoh 
   12282  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12283  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12284  1.420   msaitoh 
   12285  1.321   msaitoh 	for (i = 0; i < INVM_SIZE; i++) {
   12286  1.329   msaitoh 		invm_dword = CSR_READ(sc, WM_INVM_DATA_REG(i));
   12287  1.321   msaitoh 		/* Get record type */
   12288  1.321   msaitoh 		record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
   12289  1.321   msaitoh 		if (record_type == INVM_UNINITIALIZED_STRUCTURE)
   12290  1.321   msaitoh 			break;
   12291  1.321   msaitoh 		if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE)
   12292  1.321   msaitoh 			i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
   12293  1.321   msaitoh 		if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE)
   12294  1.321   msaitoh 			i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
   12295  1.321   msaitoh 		if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) {
   12296  1.321   msaitoh 			word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
   12297  1.321   msaitoh 			if (word_address == address) {
   12298  1.321   msaitoh 				*data = INVM_DWORD_TO_WORD_DATA(invm_dword);
   12299  1.321   msaitoh 				rv = 0;
   12300  1.321   msaitoh 				break;
   12301  1.321   msaitoh 			}
   12302  1.321   msaitoh 		}
   12303  1.321   msaitoh 	}
   12304  1.321   msaitoh 
   12305  1.321   msaitoh 	return rv;
   12306  1.321   msaitoh }
   12307  1.321   msaitoh 
   12308  1.321   msaitoh static int
   12309  1.321   msaitoh wm_nvm_read_invm(struct wm_softc *sc, int offset, int words, uint16_t *data)
   12310  1.321   msaitoh {
   12311  1.321   msaitoh 	int rv = 0;
   12312  1.321   msaitoh 	int i;
   12313  1.421   msaitoh 
   12314  1.421   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12315  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   12316  1.321   msaitoh 
   12317  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   12318  1.530   msaitoh 		return -1;
   12319  1.530   msaitoh 
   12320  1.321   msaitoh 	for (i = 0; i < words; i++) {
   12321  1.321   msaitoh 		switch (offset + i) {
   12322  1.321   msaitoh 		case NVM_OFF_MACADDR:
   12323  1.321   msaitoh 		case NVM_OFF_MACADDR1:
   12324  1.321   msaitoh 		case NVM_OFF_MACADDR2:
   12325  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset + i, &data[i]);
   12326  1.321   msaitoh 			if (rv != 0) {
   12327  1.321   msaitoh 				data[i] = 0xffff;
   12328  1.321   msaitoh 				rv = -1;
   12329  1.321   msaitoh 			}
   12330  1.321   msaitoh 			break;
   12331  1.321   msaitoh 		case NVM_OFF_CFG2:
   12332  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12333  1.321   msaitoh 			if (rv != 0) {
   12334  1.321   msaitoh 				*data = NVM_INIT_CTRL_2_DEFAULT_I211;
   12335  1.321   msaitoh 				rv = 0;
   12336  1.321   msaitoh 			}
   12337  1.321   msaitoh 			break;
   12338  1.321   msaitoh 		case NVM_OFF_CFG4:
   12339  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12340  1.321   msaitoh 			if (rv != 0) {
   12341  1.321   msaitoh 				*data = NVM_INIT_CTRL_4_DEFAULT_I211;
   12342  1.321   msaitoh 				rv = 0;
   12343  1.321   msaitoh 			}
   12344  1.321   msaitoh 			break;
   12345  1.321   msaitoh 		case NVM_OFF_LED_1_CFG:
   12346  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12347  1.321   msaitoh 			if (rv != 0) {
   12348  1.321   msaitoh 				*data = NVM_LED_1_CFG_DEFAULT_I211;
   12349  1.321   msaitoh 				rv = 0;
   12350  1.321   msaitoh 			}
   12351  1.321   msaitoh 			break;
   12352  1.321   msaitoh 		case NVM_OFF_LED_0_2_CFG:
   12353  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12354  1.321   msaitoh 			if (rv != 0) {
   12355  1.321   msaitoh 				*data = NVM_LED_0_2_CFG_DEFAULT_I211;
   12356  1.321   msaitoh 				rv = 0;
   12357  1.321   msaitoh 			}
   12358  1.321   msaitoh 			break;
   12359  1.321   msaitoh 		case NVM_OFF_ID_LED_SETTINGS:
   12360  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12361  1.321   msaitoh 			if (rv != 0) {
   12362  1.321   msaitoh 				*data = ID_LED_RESERVED_FFFF;
   12363  1.321   msaitoh 				rv = 0;
   12364  1.321   msaitoh 			}
   12365  1.321   msaitoh 			break;
   12366  1.321   msaitoh 		default:
   12367  1.321   msaitoh 			DPRINTF(WM_DEBUG_NVM,
   12368  1.321   msaitoh 			    ("NVM word 0x%02x is not mapped.\n", offset));
   12369  1.321   msaitoh 			*data = NVM_RESERVED_WORD;
   12370  1.321   msaitoh 			break;
   12371  1.321   msaitoh 		}
   12372  1.321   msaitoh 	}
   12373  1.321   msaitoh 
   12374  1.530   msaitoh 	sc->nvm.release(sc);
   12375  1.321   msaitoh 	return rv;
   12376  1.321   msaitoh }
   12377  1.321   msaitoh 
   12378  1.328   msaitoh /* Lock, detecting NVM type, validate checksum, version and read */
   12379  1.281   msaitoh 
   12380  1.281   msaitoh static int
   12381  1.281   msaitoh wm_nvm_is_onboard_eeprom(struct wm_softc *sc)
   12382  1.139    bouyer {
   12383  1.281   msaitoh 	uint32_t eecd = 0;
   12384  1.281   msaitoh 
   12385  1.281   msaitoh 	if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574
   12386  1.281   msaitoh 	    || sc->sc_type == WM_T_82583) {
   12387  1.281   msaitoh 		eecd = CSR_READ(sc, WMREG_EECD);
   12388  1.281   msaitoh 
   12389  1.281   msaitoh 		/* Isolate bits 15 & 16 */
   12390  1.281   msaitoh 		eecd = ((eecd >> 15) & 0x03);
   12391  1.194   msaitoh 
   12392  1.281   msaitoh 		/* If both bits are set, device is Flash type */
   12393  1.281   msaitoh 		if (eecd == 0x03)
   12394  1.281   msaitoh 			return 0;
   12395  1.281   msaitoh 	}
   12396  1.281   msaitoh 	return 1;
   12397  1.281   msaitoh }
   12398  1.194   msaitoh 
   12399  1.321   msaitoh static int
   12400  1.321   msaitoh wm_nvm_get_flash_presence_i210(struct wm_softc *sc)
   12401  1.321   msaitoh {
   12402  1.321   msaitoh 	uint32_t eec;
   12403  1.321   msaitoh 
   12404  1.321   msaitoh 	eec = CSR_READ(sc, WMREG_EEC);
   12405  1.321   msaitoh 	if ((eec & EEC_FLASH_DETECTED) != 0)
   12406  1.321   msaitoh 		return 1;
   12407  1.321   msaitoh 
   12408  1.321   msaitoh 	return 0;
   12409  1.321   msaitoh }
   12410  1.321   msaitoh 
   12411  1.281   msaitoh /*
   12412  1.281   msaitoh  * wm_nvm_validate_checksum
   12413  1.281   msaitoh  *
   12414  1.281   msaitoh  * The checksum is defined as the sum of the first 64 (16 bit) words.
   12415  1.281   msaitoh  */
   12416  1.281   msaitoh static int
   12417  1.281   msaitoh wm_nvm_validate_checksum(struct wm_softc *sc)
   12418  1.281   msaitoh {
   12419  1.281   msaitoh 	uint16_t checksum;
   12420  1.281   msaitoh 	uint16_t eeprom_data;
   12421  1.281   msaitoh #ifdef WM_DEBUG
   12422  1.281   msaitoh 	uint16_t csum_wordaddr, valid_checksum;
   12423  1.281   msaitoh #endif
   12424  1.281   msaitoh 	int i;
   12425  1.194   msaitoh 
   12426  1.281   msaitoh 	checksum = 0;
   12427  1.139    bouyer 
   12428  1.281   msaitoh 	/* Don't check for I211 */
   12429  1.281   msaitoh 	if (sc->sc_type == WM_T_I211)
   12430  1.281   msaitoh 		return 0;
   12431  1.194   msaitoh 
   12432  1.281   msaitoh #ifdef WM_DEBUG
   12433  1.281   msaitoh 	if (sc->sc_type == WM_T_PCH_LPT) {
   12434  1.293   msaitoh 		csum_wordaddr = NVM_OFF_COMPAT;
   12435  1.281   msaitoh 		valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
   12436  1.281   msaitoh 	} else {
   12437  1.293   msaitoh 		csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1;
   12438  1.281   msaitoh 		valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;
   12439  1.281   msaitoh 	}
   12440  1.194   msaitoh 
   12441  1.281   msaitoh 	/* Dump EEPROM image for debug */
   12442  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   12443  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   12444  1.281   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
   12445  1.392   msaitoh 		/* XXX PCH_SPT? */
   12446  1.281   msaitoh 		wm_nvm_read(sc, csum_wordaddr, 1, &eeprom_data);
   12447  1.281   msaitoh 		if ((eeprom_data & valid_checksum) == 0) {
   12448  1.281   msaitoh 			DPRINTF(WM_DEBUG_NVM,
   12449  1.281   msaitoh 			    ("%s: NVM need to be updated (%04x != %04x)\n",
   12450  1.281   msaitoh 				device_xname(sc->sc_dev), eeprom_data,
   12451  1.281   msaitoh 				    valid_checksum));
   12452  1.281   msaitoh 		}
   12453  1.281   msaitoh 	}
   12454  1.194   msaitoh 
   12455  1.281   msaitoh 	if ((wm_debug & WM_DEBUG_NVM) != 0) {
   12456  1.281   msaitoh 		printf("%s: NVM dump:\n", device_xname(sc->sc_dev));
   12457  1.293   msaitoh 		for (i = 0; i < NVM_SIZE; i++) {
   12458  1.281   msaitoh 			if (wm_nvm_read(sc, i, 1, &eeprom_data))
   12459  1.301   msaitoh 				printf("XXXX ");
   12460  1.281   msaitoh 			else
   12461  1.301   msaitoh 				printf("%04hx ", eeprom_data);
   12462  1.281   msaitoh 			if (i % 8 == 7)
   12463  1.281   msaitoh 				printf("\n");
   12464  1.194   msaitoh 		}
   12465  1.281   msaitoh 	}
   12466  1.194   msaitoh 
   12467  1.281   msaitoh #endif /* WM_DEBUG */
   12468  1.139    bouyer 
   12469  1.293   msaitoh 	for (i = 0; i < NVM_SIZE; i++) {
   12470  1.281   msaitoh 		if (wm_nvm_read(sc, i, 1, &eeprom_data))
   12471  1.281   msaitoh 			return 1;
   12472  1.281   msaitoh 		checksum += eeprom_data;
   12473  1.281   msaitoh 	}
   12474  1.139    bouyer 
   12475  1.281   msaitoh 	if (checksum != (uint16_t) NVM_CHECKSUM) {
   12476  1.281   msaitoh #ifdef WM_DEBUG
   12477  1.281   msaitoh 		printf("%s: NVM checksum mismatch (%04x != %04x)\n",
   12478  1.281   msaitoh 		    device_xname(sc->sc_dev), checksum, NVM_CHECKSUM);
   12479  1.281   msaitoh #endif
   12480  1.281   msaitoh 	}
   12481  1.139    bouyer 
   12482  1.281   msaitoh 	return 0;
   12483  1.139    bouyer }
   12484  1.139    bouyer 
   12485  1.328   msaitoh static void
   12486  1.347   msaitoh wm_nvm_version_invm(struct wm_softc *sc)
   12487  1.347   msaitoh {
   12488  1.347   msaitoh 	uint32_t dword;
   12489  1.347   msaitoh 
   12490  1.347   msaitoh 	/*
   12491  1.347   msaitoh 	 * Linux's code to decode version is very strange, so we don't
   12492  1.347   msaitoh 	 * obey that algorithm and just use word 61 as the document.
   12493  1.347   msaitoh 	 * Perhaps it's not perfect though...
   12494  1.347   msaitoh 	 *
   12495  1.347   msaitoh 	 * Example:
   12496  1.347   msaitoh 	 *
   12497  1.347   msaitoh 	 *   Word61: 00800030 -> Version 0.6 (I211 spec update notes about 0.6)
   12498  1.347   msaitoh 	 */
   12499  1.347   msaitoh 	dword = CSR_READ(sc, WM_INVM_DATA_REG(61));
   12500  1.347   msaitoh 	dword = __SHIFTOUT(dword, INVM_VER_1);
   12501  1.347   msaitoh 	sc->sc_nvm_ver_major = __SHIFTOUT(dword, INVM_MAJOR);
   12502  1.347   msaitoh 	sc->sc_nvm_ver_minor = __SHIFTOUT(dword, INVM_MINOR);
   12503  1.347   msaitoh }
   12504  1.347   msaitoh 
   12505  1.347   msaitoh static void
   12506  1.328   msaitoh wm_nvm_version(struct wm_softc *sc)
   12507  1.328   msaitoh {
   12508  1.331   msaitoh 	uint16_t major, minor, build, patch;
   12509  1.328   msaitoh 	uint16_t uid0, uid1;
   12510  1.328   msaitoh 	uint16_t nvm_data;
   12511  1.328   msaitoh 	uint16_t off;
   12512  1.330   msaitoh 	bool check_version = false;
   12513  1.330   msaitoh 	bool check_optionrom = false;
   12514  1.334   msaitoh 	bool have_build = false;
   12515  1.512   msaitoh 	bool have_uid = true;
   12516  1.328   msaitoh 
   12517  1.334   msaitoh 	/*
   12518  1.334   msaitoh 	 * Version format:
   12519  1.334   msaitoh 	 *
   12520  1.334   msaitoh 	 * XYYZ
   12521  1.334   msaitoh 	 * X0YZ
   12522  1.334   msaitoh 	 * X0YY
   12523  1.334   msaitoh 	 *
   12524  1.334   msaitoh 	 * Example:
   12525  1.334   msaitoh 	 *
   12526  1.334   msaitoh 	 *	82571	0x50a2	5.10.2?	(the spec update notes about 5.6-5.10)
   12527  1.334   msaitoh 	 *	82571	0x50a6	5.10.6?
   12528  1.334   msaitoh 	 *	82572	0x506a	5.6.10?
   12529  1.334   msaitoh 	 *	82572EI	0x5069	5.6.9?
   12530  1.334   msaitoh 	 *	82574L	0x1080	1.8.0?	(the spec update notes about 2.1.4)
   12531  1.334   msaitoh 	 *		0x2013	2.1.3?
   12532  1.334   msaitoh 	 *	82583	0x10a0	1.10.0? (document says it's default vaule)
   12533  1.334   msaitoh 	 */
   12534  1.534   msaitoh 
   12535  1.534   msaitoh 	/*
   12536  1.534   msaitoh 	 * XXX
   12537  1.534   msaitoh 	 * Qemu's e1000e emulation (82574L)'s SPI has only 64 words.
   12538  1.534   msaitoh 	 * I've never seen on real 82574 hardware with such small SPI ROM.
   12539  1.534   msaitoh 	 */
   12540  1.535   msaitoh 	if ((sc->sc_nvm_wordsize < NVM_OFF_IMAGE_UID1)
   12541  1.535   msaitoh 	    || (wm_nvm_read(sc, NVM_OFF_IMAGE_UID1, 1, &uid1) != 0))
   12542  1.534   msaitoh 		have_uid = false;
   12543  1.534   msaitoh 
   12544  1.328   msaitoh 	switch (sc->sc_type) {
   12545  1.334   msaitoh 	case WM_T_82571:
   12546  1.334   msaitoh 	case WM_T_82572:
   12547  1.334   msaitoh 	case WM_T_82574:
   12548  1.350   msaitoh 	case WM_T_82583:
   12549  1.334   msaitoh 		check_version = true;
   12550  1.334   msaitoh 		check_optionrom = true;
   12551  1.334   msaitoh 		have_build = true;
   12552  1.334   msaitoh 		break;
   12553  1.328   msaitoh 	case WM_T_82575:
   12554  1.328   msaitoh 	case WM_T_82576:
   12555  1.328   msaitoh 	case WM_T_82580:
   12556  1.330   msaitoh 		if ((uid1 & NVM_MAJOR_MASK) != NVM_UID_VALID)
   12557  1.330   msaitoh 			check_version = true;
   12558  1.328   msaitoh 		break;
   12559  1.328   msaitoh 	case WM_T_I211:
   12560  1.347   msaitoh 		wm_nvm_version_invm(sc);
   12561  1.512   msaitoh 		have_uid = false;
   12562  1.347   msaitoh 		goto printver;
   12563  1.328   msaitoh 	case WM_T_I210:
   12564  1.328   msaitoh 		if (!wm_nvm_get_flash_presence_i210(sc)) {
   12565  1.347   msaitoh 			wm_nvm_version_invm(sc);
   12566  1.512   msaitoh 			have_uid = false;
   12567  1.347   msaitoh 			goto printver;
   12568  1.328   msaitoh 		}
   12569  1.328   msaitoh 		/* FALLTHROUGH */
   12570  1.328   msaitoh 	case WM_T_I350:
   12571  1.328   msaitoh 	case WM_T_I354:
   12572  1.330   msaitoh 		check_version = true;
   12573  1.330   msaitoh 		check_optionrom = true;
   12574  1.330   msaitoh 		break;
   12575  1.330   msaitoh 	default:
   12576  1.330   msaitoh 		return;
   12577  1.330   msaitoh 	}
   12578  1.535   msaitoh 	if (check_version
   12579  1.535   msaitoh 	    && (wm_nvm_read(sc, NVM_OFF_VERSION, 1, &nvm_data) == 0)) {
   12580  1.330   msaitoh 		major = (nvm_data & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
   12581  1.334   msaitoh 		if (have_build || ((nvm_data & 0x0f00) != 0x0000)) {
   12582  1.330   msaitoh 			minor = (nvm_data & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
   12583  1.330   msaitoh 			build = nvm_data & NVM_BUILD_MASK;
   12584  1.331   msaitoh 			have_build = true;
   12585  1.334   msaitoh 		} else
   12586  1.334   msaitoh 			minor = nvm_data & 0x00ff;
   12587  1.334   msaitoh 
   12588  1.330   msaitoh 		/* Decimal */
   12589  1.330   msaitoh 		minor = (minor / 16) * 10 + (minor % 16);
   12590  1.347   msaitoh 		sc->sc_nvm_ver_major = major;
   12591  1.347   msaitoh 		sc->sc_nvm_ver_minor = minor;
   12592  1.330   msaitoh 
   12593  1.347   msaitoh printver:
   12594  1.347   msaitoh 		aprint_verbose(", version %d.%d", sc->sc_nvm_ver_major,
   12595  1.347   msaitoh 		    sc->sc_nvm_ver_minor);
   12596  1.350   msaitoh 		if (have_build) {
   12597  1.350   msaitoh 			sc->sc_nvm_ver_build = build;
   12598  1.334   msaitoh 			aprint_verbose(".%d", build);
   12599  1.350   msaitoh 		}
   12600  1.330   msaitoh 	}
   12601  1.534   msaitoh 
   12602  1.534   msaitoh 	/* Assume the Option ROM area is at avove NVM_SIZE */
   12603  1.539   msaitoh 	if ((sc->sc_nvm_wordsize > NVM_SIZE) && check_optionrom
   12604  1.535   msaitoh 	    && (wm_nvm_read(sc, NVM_OFF_COMB_VER_PTR, 1, &off) == 0)) {
   12605  1.328   msaitoh 		/* Option ROM Version */
   12606  1.328   msaitoh 		if ((off != 0x0000) && (off != 0xffff)) {
   12607  1.535   msaitoh 			int rv;
   12608  1.535   msaitoh 
   12609  1.328   msaitoh 			off += NVM_COMBO_VER_OFF;
   12610  1.535   msaitoh 			rv = wm_nvm_read(sc, off + 1, 1, &uid1);
   12611  1.535   msaitoh 			rv |= wm_nvm_read(sc, off, 1, &uid0);
   12612  1.535   msaitoh 			if ((rv == 0) && (uid0 != 0) && (uid0 != 0xffff)
   12613  1.328   msaitoh 			    && (uid1 != 0) && (uid1 != 0xffff)) {
   12614  1.331   msaitoh 				/* 16bits */
   12615  1.331   msaitoh 				major = uid0 >> 8;
   12616  1.331   msaitoh 				build = (uid0 << 8) | (uid1 >> 8);
   12617  1.331   msaitoh 				patch = uid1 & 0x00ff;
   12618  1.330   msaitoh 				aprint_verbose(", option ROM Version %d.%d.%d",
   12619  1.331   msaitoh 				    major, build, patch);
   12620  1.328   msaitoh 			}
   12621  1.328   msaitoh 		}
   12622  1.328   msaitoh 	}
   12623  1.328   msaitoh 
   12624  1.535   msaitoh 	if (have_uid && (wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0) == 0))
   12625  1.512   msaitoh 		aprint_verbose(", Image Unique ID %08x", (uid1 << 16) | uid0);
   12626  1.328   msaitoh }
   12627  1.328   msaitoh 
   12628  1.281   msaitoh /*
   12629  1.281   msaitoh  * wm_nvm_read:
   12630  1.139    bouyer  *
   12631  1.281   msaitoh  *	Read data from the serial EEPROM.
   12632  1.281   msaitoh  */
   12633  1.169   msaitoh static int
   12634  1.281   msaitoh wm_nvm_read(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   12635  1.169   msaitoh {
   12636  1.169   msaitoh 	int rv;
   12637  1.169   msaitoh 
   12638  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12639  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12640  1.420   msaitoh 
   12641  1.281   msaitoh 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   12642  1.530   msaitoh 		return -1;
   12643  1.281   msaitoh 
   12644  1.530   msaitoh 	rv = sc->nvm.read(sc, word, wordcnt, data);
   12645  1.530   msaitoh 
   12646  1.169   msaitoh 	return rv;
   12647  1.169   msaitoh }
   12648  1.169   msaitoh 
   12649  1.281   msaitoh /*
   12650  1.281   msaitoh  * Hardware semaphores.
   12651  1.281   msaitoh  * Very complexed...
   12652  1.281   msaitoh  */
   12653  1.281   msaitoh 
   12654  1.169   msaitoh static int
   12655  1.424   msaitoh wm_get_null(struct wm_softc *sc)
   12656  1.424   msaitoh {
   12657  1.424   msaitoh 
   12658  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12659  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12660  1.424   msaitoh 	return 0;
   12661  1.424   msaitoh }
   12662  1.424   msaitoh 
   12663  1.424   msaitoh static void
   12664  1.424   msaitoh wm_put_null(struct wm_softc *sc)
   12665  1.424   msaitoh {
   12666  1.424   msaitoh 
   12667  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12668  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12669  1.424   msaitoh 	return;
   12670  1.424   msaitoh }
   12671  1.424   msaitoh 
   12672  1.530   msaitoh static int
   12673  1.530   msaitoh wm_get_eecd(struct wm_softc *sc)
   12674  1.530   msaitoh {
   12675  1.530   msaitoh 	uint32_t reg;
   12676  1.530   msaitoh 	int x;
   12677  1.530   msaitoh 
   12678  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK | WM_DEBUG_NVM, ("%s: %s called\n",
   12679  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   12680  1.530   msaitoh 
   12681  1.530   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   12682  1.530   msaitoh 
   12683  1.530   msaitoh 	/* Request EEPROM access. */
   12684  1.530   msaitoh 	reg |= EECD_EE_REQ;
   12685  1.530   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   12686  1.530   msaitoh 
   12687  1.530   msaitoh 	/* ..and wait for it to be granted. */
   12688  1.530   msaitoh 	for (x = 0; x < 1000; x++) {
   12689  1.530   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   12690  1.530   msaitoh 		if (reg & EECD_EE_GNT)
   12691  1.530   msaitoh 			break;
   12692  1.530   msaitoh 		delay(5);
   12693  1.530   msaitoh 	}
   12694  1.530   msaitoh 	if ((reg & EECD_EE_GNT) == 0) {
   12695  1.530   msaitoh 		aprint_error_dev(sc->sc_dev,
   12696  1.530   msaitoh 		    "could not acquire EEPROM GNT\n");
   12697  1.530   msaitoh 		reg &= ~EECD_EE_REQ;
   12698  1.530   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   12699  1.530   msaitoh 		return -1;
   12700  1.530   msaitoh 	}
   12701  1.530   msaitoh 
   12702  1.530   msaitoh 	return 0;
   12703  1.530   msaitoh }
   12704  1.530   msaitoh 
   12705  1.530   msaitoh static void
   12706  1.530   msaitoh wm_nvm_eec_clock_raise(struct wm_softc *sc, uint32_t *eecd)
   12707  1.530   msaitoh {
   12708  1.530   msaitoh 
   12709  1.530   msaitoh 	*eecd |= EECD_SK;
   12710  1.530   msaitoh 	CSR_WRITE(sc, WMREG_EECD, *eecd);
   12711  1.530   msaitoh 	CSR_WRITE_FLUSH(sc);
   12712  1.530   msaitoh 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0)
   12713  1.530   msaitoh 		delay(1);
   12714  1.530   msaitoh 	else
   12715  1.530   msaitoh 		delay(50);
   12716  1.530   msaitoh }
   12717  1.530   msaitoh 
   12718  1.530   msaitoh static void
   12719  1.530   msaitoh wm_nvm_eec_clock_lower(struct wm_softc *sc, uint32_t *eecd)
   12720  1.530   msaitoh {
   12721  1.530   msaitoh 
   12722  1.530   msaitoh 	*eecd &= ~EECD_SK;
   12723  1.530   msaitoh 	CSR_WRITE(sc, WMREG_EECD, *eecd);
   12724  1.530   msaitoh 	CSR_WRITE_FLUSH(sc);
   12725  1.530   msaitoh 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0)
   12726  1.530   msaitoh 		delay(1);
   12727  1.530   msaitoh 	else
   12728  1.530   msaitoh 		delay(50);
   12729  1.530   msaitoh }
   12730  1.530   msaitoh 
   12731  1.530   msaitoh static void
   12732  1.530   msaitoh wm_put_eecd(struct wm_softc *sc)
   12733  1.530   msaitoh {
   12734  1.530   msaitoh 	uint32_t reg;
   12735  1.530   msaitoh 
   12736  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12737  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   12738  1.530   msaitoh 
   12739  1.530   msaitoh 	/* Stop nvm */
   12740  1.530   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   12741  1.530   msaitoh 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0) {
   12742  1.530   msaitoh 		/* Pull CS high */
   12743  1.530   msaitoh 		reg |= EECD_CS;
   12744  1.530   msaitoh 		wm_nvm_eec_clock_lower(sc, &reg);
   12745  1.530   msaitoh 	} else {
   12746  1.530   msaitoh 		/* CS on Microwire is active-high */
   12747  1.530   msaitoh 		reg &= ~(EECD_CS | EECD_DI);
   12748  1.530   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   12749  1.530   msaitoh 		wm_nvm_eec_clock_raise(sc, &reg);
   12750  1.530   msaitoh 		wm_nvm_eec_clock_lower(sc, &reg);
   12751  1.530   msaitoh 	}
   12752  1.530   msaitoh 
   12753  1.530   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   12754  1.530   msaitoh 	reg &= ~EECD_EE_REQ;
   12755  1.530   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   12756  1.530   msaitoh 
   12757  1.530   msaitoh 	return;
   12758  1.530   msaitoh }
   12759  1.530   msaitoh 
   12760  1.424   msaitoh /*
   12761  1.424   msaitoh  * Get hardware semaphore.
   12762  1.424   msaitoh  * Same as e1000_get_hw_semaphore_generic()
   12763  1.424   msaitoh  */
   12764  1.424   msaitoh static int
   12765  1.281   msaitoh wm_get_swsm_semaphore(struct wm_softc *sc)
   12766  1.169   msaitoh {
   12767  1.281   msaitoh 	int32_t timeout;
   12768  1.281   msaitoh 	uint32_t swsm;
   12769  1.281   msaitoh 
   12770  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12771  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   12772  1.424   msaitoh 	KASSERT(sc->sc_nvm_wordsize > 0);
   12773  1.421   msaitoh 
   12774  1.533   msaitoh retry:
   12775  1.424   msaitoh 	/* Get the SW semaphore. */
   12776  1.424   msaitoh 	timeout = sc->sc_nvm_wordsize + 1;
   12777  1.424   msaitoh 	while (timeout) {
   12778  1.424   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   12779  1.281   msaitoh 
   12780  1.424   msaitoh 		if ((swsm & SWSM_SMBI) == 0)
   12781  1.424   msaitoh 			break;
   12782  1.169   msaitoh 
   12783  1.424   msaitoh 		delay(50);
   12784  1.424   msaitoh 		timeout--;
   12785  1.424   msaitoh 	}
   12786  1.169   msaitoh 
   12787  1.424   msaitoh 	if (timeout == 0) {
   12788  1.533   msaitoh 		if ((sc->sc_flags & WM_F_WA_I210_CLSEM) != 0) {
   12789  1.533   msaitoh 			/*
   12790  1.533   msaitoh 			 * In rare circumstances, the SW semaphore may already
   12791  1.533   msaitoh 			 * be held unintentionally. Clear the semaphore once
   12792  1.533   msaitoh 			 * before giving up.
   12793  1.533   msaitoh 			 */
   12794  1.533   msaitoh 			sc->sc_flags &= ~WM_F_WA_I210_CLSEM;
   12795  1.533   msaitoh 			wm_put_swsm_semaphore(sc);
   12796  1.533   msaitoh 			goto retry;
   12797  1.533   msaitoh 		}
   12798  1.424   msaitoh 		aprint_error_dev(sc->sc_dev,
   12799  1.424   msaitoh 		    "could not acquire SWSM SMBI\n");
   12800  1.424   msaitoh 		return 1;
   12801  1.281   msaitoh 	}
   12802  1.281   msaitoh 
   12803  1.281   msaitoh 	/* Get the FW semaphore. */
   12804  1.294   msaitoh 	timeout = sc->sc_nvm_wordsize + 1;
   12805  1.281   msaitoh 	while (timeout) {
   12806  1.281   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   12807  1.281   msaitoh 		swsm |= SWSM_SWESMBI;
   12808  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, swsm);
   12809  1.281   msaitoh 		/* If we managed to set the bit we got the semaphore. */
   12810  1.281   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   12811  1.281   msaitoh 		if (swsm & SWSM_SWESMBI)
   12812  1.281   msaitoh 			break;
   12813  1.169   msaitoh 
   12814  1.281   msaitoh 		delay(50);
   12815  1.281   msaitoh 		timeout--;
   12816  1.281   msaitoh 	}
   12817  1.281   msaitoh 
   12818  1.281   msaitoh 	if (timeout == 0) {
   12819  1.388   msaitoh 		aprint_error_dev(sc->sc_dev,
   12820  1.388   msaitoh 		    "could not acquire SWSM SWESMBI\n");
   12821  1.281   msaitoh 		/* Release semaphores */
   12822  1.281   msaitoh 		wm_put_swsm_semaphore(sc);
   12823  1.281   msaitoh 		return 1;
   12824  1.281   msaitoh 	}
   12825  1.169   msaitoh 	return 0;
   12826  1.169   msaitoh }
   12827  1.169   msaitoh 
   12828  1.420   msaitoh /*
   12829  1.420   msaitoh  * Put hardware semaphore.
   12830  1.420   msaitoh  * Same as e1000_put_hw_semaphore_generic()
   12831  1.420   msaitoh  */
   12832  1.281   msaitoh static void
   12833  1.281   msaitoh wm_put_swsm_semaphore(struct wm_softc *sc)
   12834  1.169   msaitoh {
   12835  1.281   msaitoh 	uint32_t swsm;
   12836  1.169   msaitoh 
   12837  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12838  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12839  1.420   msaitoh 
   12840  1.281   msaitoh 	swsm = CSR_READ(sc, WMREG_SWSM);
   12841  1.281   msaitoh 	swsm &= ~(SWSM_SMBI | SWSM_SWESMBI);
   12842  1.281   msaitoh 	CSR_WRITE(sc, WMREG_SWSM, swsm);
   12843  1.169   msaitoh }
   12844  1.169   msaitoh 
   12845  1.420   msaitoh /*
   12846  1.420   msaitoh  * Get SW/FW semaphore.
   12847  1.530   msaitoh  * Same as e1000_acquire_swfw_sync_{80003es2lan,82575}().
   12848  1.420   msaitoh  */
   12849  1.169   msaitoh static int
   12850  1.281   msaitoh wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
   12851  1.169   msaitoh {
   12852  1.281   msaitoh 	uint32_t swfw_sync;
   12853  1.281   msaitoh 	uint32_t swmask = mask << SWFW_SOFT_SHIFT;
   12854  1.281   msaitoh 	uint32_t fwmask = mask << SWFW_FIRM_SHIFT;
   12855  1.530   msaitoh 	int timeout;
   12856  1.169   msaitoh 
   12857  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12858  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12859  1.530   msaitoh 
   12860  1.530   msaitoh 	if (sc->sc_type == WM_T_80003)
   12861  1.530   msaitoh 		timeout = 50;
   12862  1.530   msaitoh 	else
   12863  1.530   msaitoh 		timeout = 200;
   12864  1.420   msaitoh 
   12865  1.281   msaitoh 	for (timeout = 0; timeout < 200; timeout++) {
   12866  1.530   msaitoh 		if (wm_get_swsm_semaphore(sc)) {
   12867  1.530   msaitoh 			aprint_error_dev(sc->sc_dev,
   12868  1.530   msaitoh 			    "%s: failed to get semaphore\n",
   12869  1.530   msaitoh 			    __func__);
   12870  1.530   msaitoh 			return 1;
   12871  1.281   msaitoh 		}
   12872  1.281   msaitoh 		swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
   12873  1.281   msaitoh 		if ((swfw_sync & (swmask | fwmask)) == 0) {
   12874  1.281   msaitoh 			swfw_sync |= swmask;
   12875  1.281   msaitoh 			CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
   12876  1.530   msaitoh 			wm_put_swsm_semaphore(sc);
   12877  1.281   msaitoh 			return 0;
   12878  1.281   msaitoh 		}
   12879  1.530   msaitoh 		wm_put_swsm_semaphore(sc);
   12880  1.281   msaitoh 		delay(5000);
   12881  1.281   msaitoh 	}
   12882  1.281   msaitoh 	printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n",
   12883  1.281   msaitoh 	    device_xname(sc->sc_dev), mask, swfw_sync);
   12884  1.281   msaitoh 	return 1;
   12885  1.281   msaitoh }
   12886  1.169   msaitoh 
   12887  1.281   msaitoh static void
   12888  1.281   msaitoh wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
   12889  1.281   msaitoh {
   12890  1.281   msaitoh 	uint32_t swfw_sync;
   12891  1.169   msaitoh 
   12892  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12893  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12894  1.420   msaitoh 
   12895  1.530   msaitoh 	while (wm_get_swsm_semaphore(sc) != 0)
   12896  1.530   msaitoh 		continue;
   12897  1.530   msaitoh 
   12898  1.281   msaitoh 	swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
   12899  1.281   msaitoh 	swfw_sync &= ~(mask << SWFW_SOFT_SHIFT);
   12900  1.281   msaitoh 	CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
   12901  1.530   msaitoh 
   12902  1.530   msaitoh 	wm_put_swsm_semaphore(sc);
   12903  1.530   msaitoh }
   12904  1.530   msaitoh 
   12905  1.530   msaitoh static int
   12906  1.530   msaitoh wm_get_nvm_80003(struct wm_softc *sc)
   12907  1.530   msaitoh {
   12908  1.530   msaitoh 	int rv;
   12909  1.530   msaitoh 
   12910  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK | WM_DEBUG_NVM, ("%s: %s called\n",
   12911  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   12912  1.530   msaitoh 
   12913  1.530   msaitoh 	if ((rv = wm_get_swfw_semaphore(sc, SWFW_EEP_SM)) != 0) {
   12914  1.530   msaitoh 		aprint_error_dev(sc->sc_dev,
   12915  1.530   msaitoh 		    "%s: failed to get semaphore(SWFW)\n",
   12916  1.530   msaitoh 		    __func__);
   12917  1.530   msaitoh 		return rv;
   12918  1.530   msaitoh 	}
   12919  1.530   msaitoh 
   12920  1.530   msaitoh 	if (((sc->sc_flags & WM_F_LOCK_EECD) != 0)
   12921  1.530   msaitoh 	    && (rv = wm_get_eecd(sc)) != 0) {
   12922  1.530   msaitoh 		aprint_error_dev(sc->sc_dev,
   12923  1.530   msaitoh 		    "%s: failed to get semaphore(EECD)\n",
   12924  1.530   msaitoh 		    __func__);
   12925  1.530   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
   12926  1.530   msaitoh 		return rv;
   12927  1.530   msaitoh 	}
   12928  1.530   msaitoh 
   12929  1.530   msaitoh 	return 0;
   12930  1.530   msaitoh }
   12931  1.530   msaitoh 
   12932  1.530   msaitoh static void
   12933  1.530   msaitoh wm_put_nvm_80003(struct wm_softc *sc)
   12934  1.530   msaitoh {
   12935  1.530   msaitoh 
   12936  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12937  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   12938  1.530   msaitoh 
   12939  1.530   msaitoh 	if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
   12940  1.530   msaitoh 		wm_put_eecd(sc);
   12941  1.530   msaitoh 	wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
   12942  1.530   msaitoh }
   12943  1.530   msaitoh 
   12944  1.530   msaitoh static int
   12945  1.530   msaitoh wm_get_nvm_82571(struct wm_softc *sc)
   12946  1.530   msaitoh {
   12947  1.530   msaitoh 	int rv;
   12948  1.530   msaitoh 
   12949  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12950  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   12951  1.530   msaitoh 
   12952  1.530   msaitoh 	if ((rv = wm_get_swsm_semaphore(sc)) != 0)
   12953  1.530   msaitoh 		return rv;
   12954  1.530   msaitoh 
   12955  1.530   msaitoh 	switch (sc->sc_type) {
   12956  1.530   msaitoh 	case WM_T_82573:
   12957  1.530   msaitoh 		break;
   12958  1.530   msaitoh 	default:
   12959  1.530   msaitoh 		if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
   12960  1.530   msaitoh 			rv = wm_get_eecd(sc);
   12961  1.530   msaitoh 		break;
   12962  1.530   msaitoh 	}
   12963  1.530   msaitoh 
   12964  1.530   msaitoh 	if (rv != 0) {
   12965  1.530   msaitoh 		aprint_error_dev(sc->sc_dev,
   12966  1.530   msaitoh 		    "%s: failed to get semaphore\n",
   12967  1.530   msaitoh 		    __func__);
   12968  1.281   msaitoh 		wm_put_swsm_semaphore(sc);
   12969  1.530   msaitoh 	}
   12970  1.530   msaitoh 
   12971  1.530   msaitoh 	return rv;
   12972  1.530   msaitoh }
   12973  1.530   msaitoh 
   12974  1.530   msaitoh static void
   12975  1.530   msaitoh wm_put_nvm_82571(struct wm_softc *sc)
   12976  1.530   msaitoh {
   12977  1.530   msaitoh 
   12978  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12979  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   12980  1.530   msaitoh 
   12981  1.530   msaitoh 	switch (sc->sc_type) {
   12982  1.530   msaitoh 	case WM_T_82573:
   12983  1.530   msaitoh 		break;
   12984  1.530   msaitoh 	default:
   12985  1.530   msaitoh 		if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
   12986  1.530   msaitoh 			wm_put_eecd(sc);
   12987  1.530   msaitoh 		break;
   12988  1.530   msaitoh 	}
   12989  1.530   msaitoh 
   12990  1.530   msaitoh 	wm_put_swsm_semaphore(sc);
   12991  1.169   msaitoh }
   12992  1.169   msaitoh 
   12993  1.189   msaitoh static int
   12994  1.424   msaitoh wm_get_phy_82575(struct wm_softc *sc)
   12995  1.424   msaitoh {
   12996  1.424   msaitoh 
   12997  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12998  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12999  1.424   msaitoh 	return wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
   13000  1.424   msaitoh }
   13001  1.424   msaitoh 
   13002  1.424   msaitoh static void
   13003  1.424   msaitoh wm_put_phy_82575(struct wm_softc *sc)
   13004  1.424   msaitoh {
   13005  1.424   msaitoh 
   13006  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13007  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   13008  1.424   msaitoh 	return wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
   13009  1.424   msaitoh }
   13010  1.424   msaitoh 
   13011  1.424   msaitoh static int
   13012  1.281   msaitoh wm_get_swfwhw_semaphore(struct wm_softc *sc)
   13013  1.203   msaitoh {
   13014  1.281   msaitoh 	uint32_t ext_ctrl;
   13015  1.281   msaitoh 	int timeout = 200;
   13016  1.203   msaitoh 
   13017  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13018  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13019  1.420   msaitoh 
   13020  1.424   msaitoh 	mutex_enter(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   13021  1.281   msaitoh 	for (timeout = 0; timeout < 200; timeout++) {
   13022  1.281   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13023  1.329   msaitoh 		ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13024  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13025  1.203   msaitoh 
   13026  1.281   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13027  1.329   msaitoh 		if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
   13028  1.281   msaitoh 			return 0;
   13029  1.281   msaitoh 		delay(5000);
   13030  1.281   msaitoh 	}
   13031  1.281   msaitoh 	printf("%s: failed to get swfwhw semaphore ext_ctrl 0x%x\n",
   13032  1.281   msaitoh 	    device_xname(sc->sc_dev), ext_ctrl);
   13033  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   13034  1.281   msaitoh 	return 1;
   13035  1.281   msaitoh }
   13036  1.203   msaitoh 
   13037  1.281   msaitoh static void
   13038  1.281   msaitoh wm_put_swfwhw_semaphore(struct wm_softc *sc)
   13039  1.281   msaitoh {
   13040  1.281   msaitoh 	uint32_t ext_ctrl;
   13041  1.388   msaitoh 
   13042  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13043  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13044  1.420   msaitoh 
   13045  1.281   msaitoh 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13046  1.329   msaitoh 	ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13047  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13048  1.424   msaitoh 
   13049  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   13050  1.424   msaitoh }
   13051  1.424   msaitoh 
   13052  1.424   msaitoh static int
   13053  1.424   msaitoh wm_get_swflag_ich8lan(struct wm_softc *sc)
   13054  1.424   msaitoh {
   13055  1.424   msaitoh 	uint32_t ext_ctrl;
   13056  1.424   msaitoh 	int timeout;
   13057  1.424   msaitoh 
   13058  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13059  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   13060  1.424   msaitoh 	mutex_enter(sc->sc_ich_phymtx);
   13061  1.424   msaitoh 	for (timeout = 0; timeout < WM_PHY_CFG_TIMEOUT; timeout++) {
   13062  1.424   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13063  1.424   msaitoh 		if ((ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) == 0)
   13064  1.424   msaitoh 			break;
   13065  1.424   msaitoh 		delay(1000);
   13066  1.424   msaitoh 	}
   13067  1.424   msaitoh 	if (timeout >= WM_PHY_CFG_TIMEOUT) {
   13068  1.424   msaitoh 		printf("%s: SW has already locked the resource\n",
   13069  1.424   msaitoh 		    device_xname(sc->sc_dev));
   13070  1.424   msaitoh 		goto out;
   13071  1.424   msaitoh 	}
   13072  1.424   msaitoh 
   13073  1.424   msaitoh 	ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13074  1.424   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13075  1.424   msaitoh 	for (timeout = 0; timeout < 1000; timeout++) {
   13076  1.424   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13077  1.424   msaitoh 		if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
   13078  1.424   msaitoh 			break;
   13079  1.424   msaitoh 		delay(1000);
   13080  1.424   msaitoh 	}
   13081  1.424   msaitoh 	if (timeout >= 1000) {
   13082  1.424   msaitoh 		printf("%s: failed to acquire semaphore\n",
   13083  1.424   msaitoh 		    device_xname(sc->sc_dev));
   13084  1.424   msaitoh 		ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13085  1.424   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13086  1.424   msaitoh 		goto out;
   13087  1.424   msaitoh 	}
   13088  1.424   msaitoh 	return 0;
   13089  1.424   msaitoh 
   13090  1.424   msaitoh out:
   13091  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx);
   13092  1.424   msaitoh 	return 1;
   13093  1.424   msaitoh }
   13094  1.424   msaitoh 
   13095  1.424   msaitoh static void
   13096  1.424   msaitoh wm_put_swflag_ich8lan(struct wm_softc *sc)
   13097  1.424   msaitoh {
   13098  1.424   msaitoh 	uint32_t ext_ctrl;
   13099  1.424   msaitoh 
   13100  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13101  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   13102  1.424   msaitoh 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13103  1.424   msaitoh 	if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) {
   13104  1.424   msaitoh 		ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13105  1.424   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13106  1.424   msaitoh 	} else {
   13107  1.424   msaitoh 		printf("%s: Semaphore unexpectedly released\n",
   13108  1.424   msaitoh 		    device_xname(sc->sc_dev));
   13109  1.424   msaitoh 	}
   13110  1.424   msaitoh 
   13111  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx);
   13112  1.203   msaitoh }
   13113  1.203   msaitoh 
   13114  1.203   msaitoh static int
   13115  1.423   msaitoh wm_get_nvm_ich8lan(struct wm_softc *sc)
   13116  1.423   msaitoh {
   13117  1.423   msaitoh 
   13118  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13119  1.423   msaitoh 		device_xname(sc->sc_dev), __func__));
   13120  1.423   msaitoh 	mutex_enter(sc->sc_ich_nvmmtx);
   13121  1.423   msaitoh 
   13122  1.423   msaitoh 	return 0;
   13123  1.423   msaitoh }
   13124  1.423   msaitoh 
   13125  1.423   msaitoh static void
   13126  1.423   msaitoh wm_put_nvm_ich8lan(struct wm_softc *sc)
   13127  1.423   msaitoh {
   13128  1.423   msaitoh 
   13129  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13130  1.423   msaitoh 		device_xname(sc->sc_dev), __func__));
   13131  1.423   msaitoh 	mutex_exit(sc->sc_ich_nvmmtx);
   13132  1.423   msaitoh }
   13133  1.423   msaitoh 
   13134  1.423   msaitoh static int
   13135  1.281   msaitoh wm_get_hw_semaphore_82573(struct wm_softc *sc)
   13136  1.189   msaitoh {
   13137  1.281   msaitoh 	int i = 0;
   13138  1.189   msaitoh 	uint32_t reg;
   13139  1.189   msaitoh 
   13140  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13141  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13142  1.420   msaitoh 
   13143  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   13144  1.281   msaitoh 	do {
   13145  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR,
   13146  1.281   msaitoh 		    reg | EXTCNFCTR_MDIO_SW_OWNERSHIP);
   13147  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   13148  1.281   msaitoh 		if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0)
   13149  1.281   msaitoh 			break;
   13150  1.281   msaitoh 		delay(2*1000);
   13151  1.281   msaitoh 		i++;
   13152  1.281   msaitoh 	} while (i < WM_MDIO_OWNERSHIP_TIMEOUT);
   13153  1.281   msaitoh 
   13154  1.281   msaitoh 	if (i == WM_MDIO_OWNERSHIP_TIMEOUT) {
   13155  1.281   msaitoh 		wm_put_hw_semaphore_82573(sc);
   13156  1.281   msaitoh 		log(LOG_ERR, "%s: Driver can't access the PHY\n",
   13157  1.281   msaitoh 		    device_xname(sc->sc_dev));
   13158  1.281   msaitoh 		return -1;
   13159  1.189   msaitoh 	}
   13160  1.189   msaitoh 
   13161  1.189   msaitoh 	return 0;
   13162  1.189   msaitoh }
   13163  1.189   msaitoh 
   13164  1.169   msaitoh static void
   13165  1.281   msaitoh wm_put_hw_semaphore_82573(struct wm_softc *sc)
   13166  1.169   msaitoh {
   13167  1.169   msaitoh 	uint32_t reg;
   13168  1.169   msaitoh 
   13169  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13170  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13171  1.420   msaitoh 
   13172  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   13173  1.281   msaitoh 	reg &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13174  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
   13175  1.281   msaitoh }
   13176  1.281   msaitoh 
   13177  1.281   msaitoh /*
   13178  1.281   msaitoh  * Management mode and power management related subroutines.
   13179  1.281   msaitoh  * BMC, AMT, suspend/resume and EEE.
   13180  1.281   msaitoh  */
   13181  1.281   msaitoh 
   13182  1.378   msaitoh #ifdef WM_WOL
   13183  1.281   msaitoh static int
   13184  1.281   msaitoh wm_check_mng_mode(struct wm_softc *sc)
   13185  1.281   msaitoh {
   13186  1.281   msaitoh 	int rv;
   13187  1.281   msaitoh 
   13188  1.169   msaitoh 	switch (sc->sc_type) {
   13189  1.169   msaitoh 	case WM_T_ICH8:
   13190  1.169   msaitoh 	case WM_T_ICH9:
   13191  1.169   msaitoh 	case WM_T_ICH10:
   13192  1.190   msaitoh 	case WM_T_PCH:
   13193  1.221   msaitoh 	case WM_T_PCH2:
   13194  1.249   msaitoh 	case WM_T_PCH_LPT:
   13195  1.392   msaitoh 	case WM_T_PCH_SPT:
   13196  1.281   msaitoh 		rv = wm_check_mng_mode_ich8lan(sc);
   13197  1.281   msaitoh 		break;
   13198  1.281   msaitoh 	case WM_T_82574:
   13199  1.281   msaitoh 	case WM_T_82583:
   13200  1.281   msaitoh 		rv = wm_check_mng_mode_82574(sc);
   13201  1.281   msaitoh 		break;
   13202  1.281   msaitoh 	case WM_T_82571:
   13203  1.281   msaitoh 	case WM_T_82572:
   13204  1.281   msaitoh 	case WM_T_82573:
   13205  1.281   msaitoh 	case WM_T_80003:
   13206  1.281   msaitoh 		rv = wm_check_mng_mode_generic(sc);
   13207  1.169   msaitoh 		break;
   13208  1.169   msaitoh 	default:
   13209  1.281   msaitoh 		/* noting to do */
   13210  1.281   msaitoh 		rv = 0;
   13211  1.169   msaitoh 		break;
   13212  1.169   msaitoh 	}
   13213  1.281   msaitoh 
   13214  1.281   msaitoh 	return rv;
   13215  1.169   msaitoh }
   13216  1.173   msaitoh 
   13217  1.281   msaitoh static int
   13218  1.281   msaitoh wm_check_mng_mode_ich8lan(struct wm_softc *sc)
   13219  1.203   msaitoh {
   13220  1.281   msaitoh 	uint32_t fwsm;
   13221  1.281   msaitoh 
   13222  1.281   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   13223  1.203   msaitoh 
   13224  1.386   msaitoh 	if (((fwsm & FWSM_FW_VALID) != 0)
   13225  1.386   msaitoh 	    && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))
   13226  1.281   msaitoh 		return 1;
   13227  1.246  christos 
   13228  1.281   msaitoh 	return 0;
   13229  1.203   msaitoh }
   13230  1.203   msaitoh 
   13231  1.173   msaitoh static int
   13232  1.281   msaitoh wm_check_mng_mode_82574(struct wm_softc *sc)
   13233  1.173   msaitoh {
   13234  1.281   msaitoh 	uint16_t data;
   13235  1.173   msaitoh 
   13236  1.293   msaitoh 	wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
   13237  1.279   msaitoh 
   13238  1.293   msaitoh 	if ((data & NVM_CFG2_MNGM_MASK) != 0)
   13239  1.281   msaitoh 		return 1;
   13240  1.173   msaitoh 
   13241  1.173   msaitoh 	return 0;
   13242  1.173   msaitoh }
   13243  1.192   msaitoh 
   13244  1.281   msaitoh static int
   13245  1.281   msaitoh wm_check_mng_mode_generic(struct wm_softc *sc)
   13246  1.202   msaitoh {
   13247  1.281   msaitoh 	uint32_t fwsm;
   13248  1.202   msaitoh 
   13249  1.281   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   13250  1.202   msaitoh 
   13251  1.386   msaitoh 	if (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_IAMT_MODE)
   13252  1.281   msaitoh 		return 1;
   13253  1.202   msaitoh 
   13254  1.281   msaitoh 	return 0;
   13255  1.202   msaitoh }
   13256  1.378   msaitoh #endif /* WM_WOL */
   13257  1.202   msaitoh 
   13258  1.281   msaitoh static int
   13259  1.281   msaitoh wm_enable_mng_pass_thru(struct wm_softc *sc)
   13260  1.202   msaitoh {
   13261  1.281   msaitoh 	uint32_t manc, fwsm, factps;
   13262  1.202   msaitoh 
   13263  1.281   msaitoh 	if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) == 0)
   13264  1.281   msaitoh 		return 0;
   13265  1.202   msaitoh 
   13266  1.281   msaitoh 	manc = CSR_READ(sc, WMREG_MANC);
   13267  1.203   msaitoh 
   13268  1.281   msaitoh 	DPRINTF(WM_DEBUG_MANAGE, ("%s: MANC (%08x)\n",
   13269  1.281   msaitoh 		device_xname(sc->sc_dev), manc));
   13270  1.281   msaitoh 	if ((manc & MANC_RECV_TCO_EN) == 0)
   13271  1.281   msaitoh 		return 0;
   13272  1.203   msaitoh 
   13273  1.281   msaitoh 	if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) {
   13274  1.281   msaitoh 		fwsm = CSR_READ(sc, WMREG_FWSM);
   13275  1.281   msaitoh 		factps = CSR_READ(sc, WMREG_FACTPS);
   13276  1.281   msaitoh 		if (((factps & FACTPS_MNGCG) == 0)
   13277  1.386   msaitoh 		    && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))
   13278  1.281   msaitoh 			return 1;
   13279  1.281   msaitoh 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
   13280  1.281   msaitoh 		uint16_t data;
   13281  1.203   msaitoh 
   13282  1.281   msaitoh 		factps = CSR_READ(sc, WMREG_FACTPS);
   13283  1.293   msaitoh 		wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
   13284  1.281   msaitoh 		DPRINTF(WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n",
   13285  1.281   msaitoh 			device_xname(sc->sc_dev), factps, data));
   13286  1.281   msaitoh 		if (((factps & FACTPS_MNGCG) == 0)
   13287  1.293   msaitoh 		    && ((data & NVM_CFG2_MNGM_MASK)
   13288  1.293   msaitoh 			== (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT)))
   13289  1.281   msaitoh 			return 1;
   13290  1.281   msaitoh 	} else if (((manc & MANC_SMBUS_EN) != 0)
   13291  1.281   msaitoh 	    && ((manc & MANC_ASF_EN) == 0))
   13292  1.281   msaitoh 		return 1;
   13293  1.203   msaitoh 
   13294  1.281   msaitoh 	return 0;
   13295  1.203   msaitoh }
   13296  1.203   msaitoh 
   13297  1.386   msaitoh static bool
   13298  1.386   msaitoh wm_phy_resetisblocked(struct wm_softc *sc)
   13299  1.192   msaitoh {
   13300  1.380   msaitoh 	bool blocked = false;
   13301  1.281   msaitoh 	uint32_t reg;
   13302  1.380   msaitoh 	int i = 0;
   13303  1.192   msaitoh 
   13304  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13305  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13306  1.420   msaitoh 
   13307  1.281   msaitoh 	switch (sc->sc_type) {
   13308  1.281   msaitoh 	case WM_T_ICH8:
   13309  1.281   msaitoh 	case WM_T_ICH9:
   13310  1.281   msaitoh 	case WM_T_ICH10:
   13311  1.281   msaitoh 	case WM_T_PCH:
   13312  1.281   msaitoh 	case WM_T_PCH2:
   13313  1.281   msaitoh 	case WM_T_PCH_LPT:
   13314  1.392   msaitoh 	case WM_T_PCH_SPT:
   13315  1.380   msaitoh 		do {
   13316  1.380   msaitoh 			reg = CSR_READ(sc, WMREG_FWSM);
   13317  1.380   msaitoh 			if ((reg & FWSM_RSPCIPHY) == 0) {
   13318  1.380   msaitoh 				blocked = true;
   13319  1.380   msaitoh 				delay(10*1000);
   13320  1.380   msaitoh 				continue;
   13321  1.380   msaitoh 			}
   13322  1.380   msaitoh 			blocked = false;
   13323  1.424   msaitoh 		} while (blocked && (i++ < 30));
   13324  1.386   msaitoh 		return blocked;
   13325  1.281   msaitoh 		break;
   13326  1.281   msaitoh 	case WM_T_82571:
   13327  1.281   msaitoh 	case WM_T_82572:
   13328  1.281   msaitoh 	case WM_T_82573:
   13329  1.281   msaitoh 	case WM_T_82574:
   13330  1.281   msaitoh 	case WM_T_82583:
   13331  1.281   msaitoh 	case WM_T_80003:
   13332  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MANC);
   13333  1.281   msaitoh 		if ((reg & MANC_BLK_PHY_RST_ON_IDE) != 0)
   13334  1.386   msaitoh 			return true;
   13335  1.281   msaitoh 		else
   13336  1.386   msaitoh 			return false;
   13337  1.281   msaitoh 		break;
   13338  1.281   msaitoh 	default:
   13339  1.281   msaitoh 		/* no problem */
   13340  1.281   msaitoh 		break;
   13341  1.192   msaitoh 	}
   13342  1.192   msaitoh 
   13343  1.386   msaitoh 	return false;
   13344  1.192   msaitoh }
   13345  1.192   msaitoh 
   13346  1.192   msaitoh static void
   13347  1.281   msaitoh wm_get_hw_control(struct wm_softc *sc)
   13348  1.221   msaitoh {
   13349  1.281   msaitoh 	uint32_t reg;
   13350  1.221   msaitoh 
   13351  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13352  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13353  1.420   msaitoh 
   13354  1.446   msaitoh 	if (sc->sc_type == WM_T_82573) {
   13355  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   13356  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD);
   13357  1.446   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   13358  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13359  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);
   13360  1.281   msaitoh 	}
   13361  1.221   msaitoh }
   13362  1.221   msaitoh 
   13363  1.221   msaitoh static void
   13364  1.281   msaitoh wm_release_hw_control(struct wm_softc *sc)
   13365  1.192   msaitoh {
   13366  1.281   msaitoh 	uint32_t reg;
   13367  1.192   msaitoh 
   13368  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13369  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13370  1.420   msaitoh 
   13371  1.281   msaitoh 	if (sc->sc_type == WM_T_82573) {
   13372  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   13373  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_DRV_LOAD);
   13374  1.446   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   13375  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13376  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg & ~CTRL_EXT_DRV_LOAD);
   13377  1.192   msaitoh 	}
   13378  1.192   msaitoh }
   13379  1.192   msaitoh 
   13380  1.192   msaitoh static void
   13381  1.392   msaitoh wm_gate_hw_phy_config_ich8lan(struct wm_softc *sc, bool gate)
   13382  1.221   msaitoh {
   13383  1.221   msaitoh 	uint32_t reg;
   13384  1.221   msaitoh 
   13385  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13386  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13387  1.420   msaitoh 
   13388  1.394   msaitoh 	if (sc->sc_type < WM_T_PCH2)
   13389  1.394   msaitoh 		return;
   13390  1.394   msaitoh 
   13391  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   13392  1.221   msaitoh 
   13393  1.392   msaitoh 	if (gate)
   13394  1.281   msaitoh 		reg |= EXTCNFCTR_GATE_PHY_CFG;
   13395  1.192   msaitoh 	else
   13396  1.281   msaitoh 		reg &= ~EXTCNFCTR_GATE_PHY_CFG;
   13397  1.192   msaitoh 
   13398  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
   13399  1.192   msaitoh }
   13400  1.199   msaitoh 
   13401  1.199   msaitoh static void
   13402  1.221   msaitoh wm_smbustopci(struct wm_softc *sc)
   13403  1.221   msaitoh {
   13404  1.394   msaitoh 	uint32_t fwsm, reg;
   13405  1.447   msaitoh 	int rv = 0;
   13406  1.394   msaitoh 
   13407  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13408  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13409  1.420   msaitoh 
   13410  1.394   msaitoh 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
   13411  1.394   msaitoh 	wm_gate_hw_phy_config_ich8lan(sc, true);
   13412  1.394   msaitoh 
   13413  1.447   msaitoh 	/* Disable ULP */
   13414  1.447   msaitoh 	wm_ulp_disable(sc);
   13415  1.447   msaitoh 
   13416  1.424   msaitoh 	/* Acquire PHY semaphore */
   13417  1.424   msaitoh 	sc->phy.acquire(sc);
   13418  1.221   msaitoh 
   13419  1.221   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   13420  1.447   msaitoh 	switch (sc->sc_type) {
   13421  1.447   msaitoh 	case WM_T_PCH_LPT:
   13422  1.447   msaitoh 	case WM_T_PCH_SPT:
   13423  1.447   msaitoh 		if (wm_phy_is_accessible_pchlan(sc))
   13424  1.447   msaitoh 			break;
   13425  1.447   msaitoh 
   13426  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13427  1.447   msaitoh 		reg |= CTRL_EXT_FORCE_SMBUS;
   13428  1.447   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13429  1.447   msaitoh #if 0
   13430  1.447   msaitoh 		/* XXX Isn't this required??? */
   13431  1.447   msaitoh 		CSR_WRITE_FLUSH(sc);
   13432  1.447   msaitoh #endif
   13433  1.447   msaitoh 		delay(50 * 1000);
   13434  1.447   msaitoh 		/* FALLTHROUGH */
   13435  1.447   msaitoh 	case WM_T_PCH2:
   13436  1.447   msaitoh 		if (wm_phy_is_accessible_pchlan(sc) == true)
   13437  1.447   msaitoh 			break;
   13438  1.447   msaitoh 		/* FALLTHROUGH */
   13439  1.447   msaitoh 	case WM_T_PCH:
   13440  1.452     joerg 		if (sc->sc_type == WM_T_PCH)
   13441  1.447   msaitoh 			if ((fwsm & FWSM_FW_VALID) != 0)
   13442  1.447   msaitoh 				break;
   13443  1.447   msaitoh 
   13444  1.447   msaitoh 		if (wm_phy_resetisblocked(sc) == true) {
   13445  1.447   msaitoh 			printf("XXX reset is blocked(3)\n");
   13446  1.447   msaitoh 			break;
   13447  1.394   msaitoh 		}
   13448  1.394   msaitoh 
   13449  1.447   msaitoh 		wm_toggle_lanphypc_pch_lpt(sc);
   13450  1.221   msaitoh 
   13451  1.394   msaitoh 		if (sc->sc_type >= WM_T_PCH_LPT) {
   13452  1.447   msaitoh 			if (wm_phy_is_accessible_pchlan(sc) == true)
   13453  1.447   msaitoh 				break;
   13454  1.447   msaitoh 
   13455  1.394   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13456  1.394   msaitoh 			reg &= ~CTRL_EXT_FORCE_SMBUS;
   13457  1.394   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13458  1.447   msaitoh 
   13459  1.447   msaitoh 			if (wm_phy_is_accessible_pchlan(sc) == true)
   13460  1.447   msaitoh 				break;
   13461  1.447   msaitoh 			rv = -1;
   13462  1.394   msaitoh 		}
   13463  1.447   msaitoh 		break;
   13464  1.447   msaitoh 	default:
   13465  1.447   msaitoh 		break;
   13466  1.221   msaitoh 	}
   13467  1.394   msaitoh 
   13468  1.394   msaitoh 	/* Release semaphore */
   13469  1.424   msaitoh 	sc->phy.release(sc);
   13470  1.394   msaitoh 
   13471  1.447   msaitoh 	if (rv == 0) {
   13472  1.447   msaitoh 		if (wm_phy_resetisblocked(sc)) {
   13473  1.447   msaitoh 			printf("XXX reset is blocked(4)\n");
   13474  1.447   msaitoh 			goto out;
   13475  1.447   msaitoh 		}
   13476  1.447   msaitoh 		wm_reset_phy(sc);
   13477  1.447   msaitoh 		if (wm_phy_resetisblocked(sc))
   13478  1.447   msaitoh 			printf("XXX reset is blocked(4)\n");
   13479  1.447   msaitoh 	}
   13480  1.447   msaitoh 
   13481  1.447   msaitoh out:
   13482  1.394   msaitoh 	/*
   13483  1.394   msaitoh 	 * Ungate automatic PHY configuration by hardware on non-managed 82579
   13484  1.394   msaitoh 	 */
   13485  1.447   msaitoh 	if ((sc->sc_type == WM_T_PCH2) && ((fwsm & FWSM_FW_VALID) == 0)) {
   13486  1.447   msaitoh 		delay(10*1000);
   13487  1.394   msaitoh 		wm_gate_hw_phy_config_ich8lan(sc, false);
   13488  1.447   msaitoh 	}
   13489  1.221   msaitoh }
   13490  1.221   msaitoh 
   13491  1.221   msaitoh static void
   13492  1.203   msaitoh wm_init_manageability(struct wm_softc *sc)
   13493  1.203   msaitoh {
   13494  1.203   msaitoh 
   13495  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13496  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   13497  1.203   msaitoh 	if (sc->sc_flags & WM_F_HAS_MANAGE) {
   13498  1.203   msaitoh 		uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H);
   13499  1.203   msaitoh 		uint32_t manc = CSR_READ(sc, WMREG_MANC);
   13500  1.203   msaitoh 
   13501  1.281   msaitoh 		/* Disable hardware interception of ARP */
   13502  1.203   msaitoh 		manc &= ~MANC_ARP_EN;
   13503  1.203   msaitoh 
   13504  1.281   msaitoh 		/* Enable receiving management packets to the host */
   13505  1.203   msaitoh 		if (sc->sc_type >= WM_T_82571) {
   13506  1.203   msaitoh 			manc |= MANC_EN_MNG2HOST;
   13507  1.203   msaitoh 			manc2h |= MANC2H_PORT_623| MANC2H_PORT_624;
   13508  1.203   msaitoh 			CSR_WRITE(sc, WMREG_MANC2H, manc2h);
   13509  1.203   msaitoh 		}
   13510  1.203   msaitoh 
   13511  1.203   msaitoh 		CSR_WRITE(sc, WMREG_MANC, manc);
   13512  1.203   msaitoh 	}
   13513  1.203   msaitoh }
   13514  1.203   msaitoh 
   13515  1.203   msaitoh static void
   13516  1.203   msaitoh wm_release_manageability(struct wm_softc *sc)
   13517  1.203   msaitoh {
   13518  1.203   msaitoh 
   13519  1.203   msaitoh 	if (sc->sc_flags & WM_F_HAS_MANAGE) {
   13520  1.203   msaitoh 		uint32_t manc = CSR_READ(sc, WMREG_MANC);
   13521  1.203   msaitoh 
   13522  1.260   msaitoh 		manc |= MANC_ARP_EN;
   13523  1.203   msaitoh 		if (sc->sc_type >= WM_T_82571)
   13524  1.203   msaitoh 			manc &= ~MANC_EN_MNG2HOST;
   13525  1.203   msaitoh 
   13526  1.203   msaitoh 		CSR_WRITE(sc, WMREG_MANC, manc);
   13527  1.203   msaitoh 	}
   13528  1.203   msaitoh }
   13529  1.203   msaitoh 
   13530  1.203   msaitoh static void
   13531  1.203   msaitoh wm_get_wakeup(struct wm_softc *sc)
   13532  1.203   msaitoh {
   13533  1.203   msaitoh 
   13534  1.203   msaitoh 	/* 0: HAS_AMT, ARC_SUBSYS_VALID, ASF_FIRMWARE_PRES */
   13535  1.203   msaitoh 	switch (sc->sc_type) {
   13536  1.203   msaitoh 	case WM_T_82573:
   13537  1.203   msaitoh 	case WM_T_82583:
   13538  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_AMT;
   13539  1.203   msaitoh 		/* FALLTHROUGH */
   13540  1.246  christos 	case WM_T_80003:
   13541  1.203   msaitoh 	case WM_T_82575:
   13542  1.203   msaitoh 	case WM_T_82576:
   13543  1.208   msaitoh 	case WM_T_82580:
   13544  1.228   msaitoh 	case WM_T_I350:
   13545  1.265   msaitoh 	case WM_T_I354:
   13546  1.386   msaitoh 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE) != 0)
   13547  1.203   msaitoh 			sc->sc_flags |= WM_F_ARC_SUBSYS_VALID;
   13548  1.449   msaitoh 		/* FALLTHROUGH */
   13549  1.449   msaitoh 	case WM_T_82541:
   13550  1.449   msaitoh 	case WM_T_82541_2:
   13551  1.449   msaitoh 	case WM_T_82547:
   13552  1.449   msaitoh 	case WM_T_82547_2:
   13553  1.450   msaitoh 	case WM_T_82571:
   13554  1.450   msaitoh 	case WM_T_82572:
   13555  1.450   msaitoh 	case WM_T_82574:
   13556  1.203   msaitoh 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
   13557  1.203   msaitoh 		break;
   13558  1.203   msaitoh 	case WM_T_ICH8:
   13559  1.203   msaitoh 	case WM_T_ICH9:
   13560  1.203   msaitoh 	case WM_T_ICH10:
   13561  1.203   msaitoh 	case WM_T_PCH:
   13562  1.221   msaitoh 	case WM_T_PCH2:
   13563  1.249   msaitoh 	case WM_T_PCH_LPT:
   13564  1.449   msaitoh 	case WM_T_PCH_SPT:
   13565  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_AMT;
   13566  1.203   msaitoh 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
   13567  1.203   msaitoh 		break;
   13568  1.203   msaitoh 	default:
   13569  1.203   msaitoh 		break;
   13570  1.203   msaitoh 	}
   13571  1.203   msaitoh 
   13572  1.203   msaitoh 	/* 1: HAS_MANAGE */
   13573  1.203   msaitoh 	if (wm_enable_mng_pass_thru(sc) != 0)
   13574  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_MANAGE;
   13575  1.203   msaitoh 
   13576  1.203   msaitoh 	/*
   13577  1.203   msaitoh 	 * Note that the WOL flags is set after the resetting of the eeprom
   13578  1.203   msaitoh 	 * stuff
   13579  1.203   msaitoh 	 */
   13580  1.203   msaitoh }
   13581  1.203   msaitoh 
   13582  1.447   msaitoh /*
   13583  1.447   msaitoh  * Unconfigure Ultra Low Power mode.
   13584  1.447   msaitoh  * Only for I217 and newer (see below).
   13585  1.447   msaitoh  */
   13586  1.447   msaitoh static void
   13587  1.447   msaitoh wm_ulp_disable(struct wm_softc *sc)
   13588  1.447   msaitoh {
   13589  1.447   msaitoh 	uint32_t reg;
   13590  1.447   msaitoh 	int i = 0;
   13591  1.447   msaitoh 
   13592  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13593  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   13594  1.447   msaitoh 	/* Exclude old devices */
   13595  1.447   msaitoh 	if ((sc->sc_type < WM_T_PCH_LPT)
   13596  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I217_LM)
   13597  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I217_V)
   13598  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_LM2)
   13599  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_V2))
   13600  1.447   msaitoh 		return;
   13601  1.447   msaitoh 
   13602  1.447   msaitoh 	if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) != 0) {
   13603  1.447   msaitoh 		/* Request ME un-configure ULP mode in the PHY */
   13604  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_H2ME);
   13605  1.447   msaitoh 		reg &= ~H2ME_ULP;
   13606  1.447   msaitoh 		reg |= H2ME_ENFORCE_SETTINGS;
   13607  1.447   msaitoh 		CSR_WRITE(sc, WMREG_H2ME, reg);
   13608  1.447   msaitoh 
   13609  1.447   msaitoh 		/* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
   13610  1.447   msaitoh 		while ((CSR_READ(sc, WMREG_FWSM) & FWSM_ULP_CFG_DONE) != 0) {
   13611  1.447   msaitoh 			if (i++ == 30) {
   13612  1.447   msaitoh 				printf("%s timed out\n", __func__);
   13613  1.447   msaitoh 				return;
   13614  1.447   msaitoh 			}
   13615  1.447   msaitoh 			delay(10 * 1000);
   13616  1.447   msaitoh 		}
   13617  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_H2ME);
   13618  1.447   msaitoh 		reg &= ~H2ME_ENFORCE_SETTINGS;
   13619  1.447   msaitoh 		CSR_WRITE(sc, WMREG_H2ME, reg);
   13620  1.447   msaitoh 
   13621  1.447   msaitoh 		return;
   13622  1.447   msaitoh 	}
   13623  1.447   msaitoh 
   13624  1.447   msaitoh 	/* Acquire semaphore */
   13625  1.447   msaitoh 	sc->phy.acquire(sc);
   13626  1.447   msaitoh 
   13627  1.447   msaitoh 	/* Toggle LANPHYPC */
   13628  1.447   msaitoh 	wm_toggle_lanphypc_pch_lpt(sc);
   13629  1.447   msaitoh 
   13630  1.447   msaitoh 	/* Unforce SMBus mode in PHY */
   13631  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, CV_SMB_CTRL);
   13632  1.447   msaitoh 	if (reg == 0x0000 || reg == 0xffff) {
   13633  1.447   msaitoh 		uint32_t reg2;
   13634  1.447   msaitoh 
   13635  1.447   msaitoh 		printf("%s: Force SMBus first.\n", __func__);
   13636  1.447   msaitoh 		reg2 = CSR_READ(sc, WMREG_CTRL_EXT);
   13637  1.447   msaitoh 		reg2 |= CTRL_EXT_FORCE_SMBUS;
   13638  1.447   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg2);
   13639  1.447   msaitoh 		delay(50 * 1000);
   13640  1.447   msaitoh 
   13641  1.447   msaitoh 		reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, CV_SMB_CTRL);
   13642  1.447   msaitoh 	}
   13643  1.447   msaitoh 	reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
   13644  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, CV_SMB_CTRL, reg);
   13645  1.447   msaitoh 
   13646  1.447   msaitoh 	/* Unforce SMBus mode in MAC */
   13647  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13648  1.447   msaitoh 	reg &= ~CTRL_EXT_FORCE_SMBUS;
   13649  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13650  1.447   msaitoh 
   13651  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, HV_PM_CTRL);
   13652  1.447   msaitoh 	reg |= HV_PM_CTRL_K1_ENA;
   13653  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, HV_PM_CTRL, reg);
   13654  1.447   msaitoh 
   13655  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1);
   13656  1.447   msaitoh 	reg &= ~(I218_ULP_CONFIG1_IND
   13657  1.447   msaitoh 	    | I218_ULP_CONFIG1_STICKY_ULP
   13658  1.447   msaitoh 	    | I218_ULP_CONFIG1_RESET_TO_SMBUS
   13659  1.447   msaitoh 	    | I218_ULP_CONFIG1_WOL_HOST
   13660  1.447   msaitoh 	    | I218_ULP_CONFIG1_INBAND_EXIT
   13661  1.447   msaitoh 	    | I218_ULP_CONFIG1_EN_ULP_LANPHYPC
   13662  1.447   msaitoh 	    | I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST
   13663  1.447   msaitoh 	    | I218_ULP_CONFIG1_DIS_SMB_PERST);
   13664  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1, reg);
   13665  1.447   msaitoh 	reg |= I218_ULP_CONFIG1_START;
   13666  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1, reg);
   13667  1.447   msaitoh 
   13668  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM7);
   13669  1.447   msaitoh 	reg &= ~FEXTNVM7_DIS_SMB_PERST;
   13670  1.447   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM7, reg);
   13671  1.447   msaitoh 
   13672  1.447   msaitoh 	/* Release semaphore */
   13673  1.447   msaitoh 	sc->phy.release(sc);
   13674  1.447   msaitoh 	wm_gmii_reset(sc);
   13675  1.447   msaitoh 	delay(50 * 1000);
   13676  1.447   msaitoh }
   13677  1.447   msaitoh 
   13678  1.203   msaitoh /* WOL in the newer chipset interfaces (pchlan) */
   13679  1.203   msaitoh static void
   13680  1.203   msaitoh wm_enable_phy_wakeup(struct wm_softc *sc)
   13681  1.203   msaitoh {
   13682  1.203   msaitoh #if 0
   13683  1.203   msaitoh 	uint16_t preg;
   13684  1.203   msaitoh 
   13685  1.203   msaitoh 	/* Copy MAC RARs to PHY RARs */
   13686  1.203   msaitoh 
   13687  1.203   msaitoh 	/* Copy MAC MTA to PHY MTA */
   13688  1.203   msaitoh 
   13689  1.281   msaitoh 	/* Configure PHY Rx Control register */
   13690  1.281   msaitoh 
   13691  1.281   msaitoh 	/* Enable PHY wakeup in MAC register */
   13692  1.281   msaitoh 
   13693  1.281   msaitoh 	/* Configure and enable PHY wakeup in PHY registers */
   13694  1.281   msaitoh 
   13695  1.281   msaitoh 	/* Activate PHY wakeup */
   13696  1.281   msaitoh 
   13697  1.281   msaitoh 	/* XXX */
   13698  1.281   msaitoh #endif
   13699  1.281   msaitoh }
   13700  1.281   msaitoh 
   13701  1.281   msaitoh /* Power down workaround on D3 */
   13702  1.281   msaitoh static void
   13703  1.281   msaitoh wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *sc)
   13704  1.281   msaitoh {
   13705  1.281   msaitoh 	uint32_t reg;
   13706  1.281   msaitoh 	int i;
   13707  1.281   msaitoh 
   13708  1.281   msaitoh 	for (i = 0; i < 2; i++) {
   13709  1.281   msaitoh 		/* Disable link */
   13710  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13711  1.281   msaitoh 		reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
   13712  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13713  1.281   msaitoh 
   13714  1.281   msaitoh 		/*
   13715  1.281   msaitoh 		 * Call gig speed drop workaround on Gig disable before
   13716  1.281   msaitoh 		 * accessing any PHY registers
   13717  1.281   msaitoh 		 */
   13718  1.281   msaitoh 		if (sc->sc_type == WM_T_ICH8)
   13719  1.281   msaitoh 			wm_gig_downshift_workaround_ich8lan(sc);
   13720  1.203   msaitoh 
   13721  1.281   msaitoh 		/* Write VR power-down enable */
   13722  1.281   msaitoh 		reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL);
   13723  1.281   msaitoh 		reg &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
   13724  1.281   msaitoh 		reg |= IGP3_VR_CTRL_MODE_SHUTDOWN;
   13725  1.281   msaitoh 		sc->sc_mii.mii_writereg(sc->sc_dev, 1, IGP3_VR_CTRL, reg);
   13726  1.203   msaitoh 
   13727  1.281   msaitoh 		/* Read it back and test */
   13728  1.281   msaitoh 		reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL);
   13729  1.281   msaitoh 		reg &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
   13730  1.281   msaitoh 		if ((reg == IGP3_VR_CTRL_MODE_SHUTDOWN) || (i != 0))
   13731  1.281   msaitoh 			break;
   13732  1.203   msaitoh 
   13733  1.281   msaitoh 		/* Issue PHY reset and repeat at most one more time */
   13734  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   13735  1.281   msaitoh 	}
   13736  1.203   msaitoh }
   13737  1.203   msaitoh 
   13738  1.203   msaitoh static void
   13739  1.203   msaitoh wm_enable_wakeup(struct wm_softc *sc)
   13740  1.203   msaitoh {
   13741  1.203   msaitoh 	uint32_t reg, pmreg;
   13742  1.203   msaitoh 	pcireg_t pmode;
   13743  1.203   msaitoh 
   13744  1.425   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13745  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   13746  1.425   msaitoh 
   13747  1.203   msaitoh 	if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT,
   13748  1.203   msaitoh 		&pmreg, NULL) == 0)
   13749  1.203   msaitoh 		return;
   13750  1.203   msaitoh 
   13751  1.203   msaitoh 	/* Advertise the wakeup capability */
   13752  1.203   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_SWDPIN(2)
   13753  1.203   msaitoh 	    | CTRL_SWDPIN(3));
   13754  1.203   msaitoh 	CSR_WRITE(sc, WMREG_WUC, WUC_APME);
   13755  1.203   msaitoh 
   13756  1.203   msaitoh 	/* ICH workaround */
   13757  1.203   msaitoh 	switch (sc->sc_type) {
   13758  1.203   msaitoh 	case WM_T_ICH8:
   13759  1.203   msaitoh 	case WM_T_ICH9:
   13760  1.203   msaitoh 	case WM_T_ICH10:
   13761  1.203   msaitoh 	case WM_T_PCH:
   13762  1.221   msaitoh 	case WM_T_PCH2:
   13763  1.249   msaitoh 	case WM_T_PCH_LPT:
   13764  1.392   msaitoh 	case WM_T_PCH_SPT:
   13765  1.203   msaitoh 		/* Disable gig during WOL */
   13766  1.203   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13767  1.203   msaitoh 		reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS;
   13768  1.203   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13769  1.203   msaitoh 		if (sc->sc_type == WM_T_PCH)
   13770  1.203   msaitoh 			wm_gmii_reset(sc);
   13771  1.203   msaitoh 
   13772  1.203   msaitoh 		/* Power down workaround */
   13773  1.203   msaitoh 		if (sc->sc_phytype == WMPHY_82577) {
   13774  1.203   msaitoh 			struct mii_softc *child;
   13775  1.203   msaitoh 
   13776  1.203   msaitoh 			/* Assume that the PHY is copper */
   13777  1.203   msaitoh 			child = LIST_FIRST(&sc->sc_mii.mii_phys);
   13778  1.497    kardel 			if ((child != NULL) && (child->mii_mpd_rev <= 2))
   13779  1.203   msaitoh 				sc->sc_mii.mii_writereg(sc->sc_dev, 1,
   13780  1.203   msaitoh 				    (768 << 5) | 25, 0x0444); /* magic num */
   13781  1.203   msaitoh 		}
   13782  1.203   msaitoh 		break;
   13783  1.203   msaitoh 	default:
   13784  1.203   msaitoh 		break;
   13785  1.203   msaitoh 	}
   13786  1.203   msaitoh 
   13787  1.203   msaitoh 	/* Keep the laser running on fiber adapters */
   13788  1.311   msaitoh 	if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
   13789  1.311   msaitoh 	    || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) {
   13790  1.203   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13791  1.203   msaitoh 		reg |= CTRL_EXT_SWDPIN(3);
   13792  1.203   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13793  1.203   msaitoh 	}
   13794  1.203   msaitoh 
   13795  1.203   msaitoh 	reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG;
   13796  1.203   msaitoh #if 0	/* for the multicast packet */
   13797  1.203   msaitoh 	reg |= WUFC_MC;
   13798  1.203   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE);
   13799  1.203   msaitoh #endif
   13800  1.203   msaitoh 
   13801  1.442   msaitoh 	if (sc->sc_type >= WM_T_PCH)
   13802  1.203   msaitoh 		wm_enable_phy_wakeup(sc);
   13803  1.442   msaitoh 	else {
   13804  1.451   msaitoh 		CSR_WRITE(sc, WMREG_WUC, CSR_READ(sc, WMREG_WUC) | WUC_PME_EN);
   13805  1.203   msaitoh 		CSR_WRITE(sc, WMREG_WUFC, reg);
   13806  1.203   msaitoh 	}
   13807  1.203   msaitoh 
   13808  1.203   msaitoh 	if (((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   13809  1.221   msaitoh 		|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   13810  1.221   msaitoh 		|| (sc->sc_type == WM_T_PCH2))
   13811  1.203   msaitoh 		    && (sc->sc_phytype == WMPHY_IGP_3))
   13812  1.203   msaitoh 			wm_igp3_phy_powerdown_workaround_ich8lan(sc);
   13813  1.203   msaitoh 
   13814  1.203   msaitoh 	/* Request PME */
   13815  1.203   msaitoh 	pmode = pci_conf_read(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR);
   13816  1.203   msaitoh #if 0
   13817  1.203   msaitoh 	/* Disable WOL */
   13818  1.203   msaitoh 	pmode &= ~(PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN);
   13819  1.203   msaitoh #else
   13820  1.203   msaitoh 	/* For WOL */
   13821  1.203   msaitoh 	pmode |= PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN;
   13822  1.203   msaitoh #endif
   13823  1.203   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR, pmode);
   13824  1.203   msaitoh }
   13825  1.203   msaitoh 
   13826  1.552   msaitoh /* Disable ASPM L0s and/or L1 for workaround */
   13827  1.552   msaitoh static void
   13828  1.552   msaitoh wm_disable_aspm(struct wm_softc *sc)
   13829  1.552   msaitoh {
   13830  1.552   msaitoh 	pcireg_t reg, mask = 0;
   13831  1.552   msaitoh 	unsigned const char *str = "";
   13832  1.552   msaitoh 
   13833  1.552   msaitoh 	/*
   13834  1.552   msaitoh 	 *  Only for PCIe device which has PCIe capability in the PCI config
   13835  1.552   msaitoh 	 * space.
   13836  1.552   msaitoh 	 */
   13837  1.552   msaitoh 	if (((sc->sc_flags & WM_F_PCIE) == 0) || (sc->sc_pcixe_capoff == 0))
   13838  1.552   msaitoh 		return;
   13839  1.552   msaitoh 
   13840  1.552   msaitoh 	switch (sc->sc_type) {
   13841  1.552   msaitoh 	case WM_T_82571:
   13842  1.552   msaitoh 	case WM_T_82572:
   13843  1.552   msaitoh 		/*
   13844  1.552   msaitoh 		 * 8257[12] Errata 13: Device Does Not Support PCIe Active
   13845  1.552   msaitoh 		 * State Power management L1 State (ASPM L1).
   13846  1.552   msaitoh 		 */
   13847  1.552   msaitoh 		mask = PCIE_LCSR_ASPM_L1;
   13848  1.552   msaitoh 		str = "L1 is";
   13849  1.552   msaitoh 		break;
   13850  1.552   msaitoh 	case WM_T_82573:
   13851  1.552   msaitoh 	case WM_T_82574:
   13852  1.552   msaitoh 	case WM_T_82583:
   13853  1.552   msaitoh 		/*
   13854  1.552   msaitoh 		 * The 82573 disappears when PCIe ASPM L0s is enabled.
   13855  1.552   msaitoh 		 *
   13856  1.552   msaitoh 		 * The 82574 and 82583 does not support PCIe ASPM L0s with
   13857  1.552   msaitoh 		 * some chipset.  The document of 82574 and 82583 says that
   13858  1.552   msaitoh 		 * disabling L0s with some specific chipset is sufficient,
   13859  1.552   msaitoh 		 * but we follow as of the Intel em driver does.
   13860  1.552   msaitoh 		 *
   13861  1.552   msaitoh 		 * References:
   13862  1.552   msaitoh 		 * Errata 8 of the Specification Update of i82573.
   13863  1.552   msaitoh 		 * Errata 20 of the Specification Update of i82574.
   13864  1.552   msaitoh 		 * Errata 9 of the Specification Update of i82583.
   13865  1.552   msaitoh 		 */
   13866  1.552   msaitoh 		mask = PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S;
   13867  1.552   msaitoh 		str = "L0s and L1 are";
   13868  1.552   msaitoh 		break;
   13869  1.552   msaitoh 	default:
   13870  1.552   msaitoh 		return;
   13871  1.552   msaitoh 	}
   13872  1.552   msaitoh 
   13873  1.552   msaitoh 	reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   13874  1.552   msaitoh 	    sc->sc_pcixe_capoff + PCIE_LCSR);
   13875  1.552   msaitoh 	reg &= ~mask;
   13876  1.552   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   13877  1.552   msaitoh 	    sc->sc_pcixe_capoff + PCIE_LCSR, reg);
   13878  1.552   msaitoh 
   13879  1.552   msaitoh 	/* Print only in wm_attach() */
   13880  1.552   msaitoh 	if ((sc->sc_flags & WM_F_ATTACHED) == 0)
   13881  1.552   msaitoh 		aprint_verbose_dev(sc->sc_dev,
   13882  1.552   msaitoh 		    "ASPM %s disabled to workaround the errata.\n",
   13883  1.552   msaitoh 			str);
   13884  1.552   msaitoh }
   13885  1.552   msaitoh 
   13886  1.377   msaitoh /* LPLU */
   13887  1.377   msaitoh 
   13888  1.377   msaitoh static void
   13889  1.377   msaitoh wm_lplu_d0_disable(struct wm_softc *sc)
   13890  1.377   msaitoh {
   13891  1.519   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   13892  1.377   msaitoh 	uint32_t reg;
   13893  1.377   msaitoh 
   13894  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13895  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   13896  1.430   msaitoh 
   13897  1.519   msaitoh 	if (sc->sc_phytype == WMPHY_IFE)
   13898  1.519   msaitoh 		return;
   13899  1.377   msaitoh 
   13900  1.519   msaitoh 	switch (sc->sc_type) {
   13901  1.519   msaitoh 	case WM_T_82571:
   13902  1.519   msaitoh 	case WM_T_82572:
   13903  1.519   msaitoh 	case WM_T_82573:
   13904  1.519   msaitoh 	case WM_T_82575:
   13905  1.519   msaitoh 	case WM_T_82576:
   13906  1.519   msaitoh 		reg = mii->mii_readreg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT);
   13907  1.519   msaitoh 		reg &= ~PMR_D0_LPLU;
   13908  1.519   msaitoh 		mii->mii_writereg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT, reg);
   13909  1.519   msaitoh 		break;
   13910  1.519   msaitoh 	case WM_T_82580:
   13911  1.519   msaitoh 	case WM_T_I350:
   13912  1.519   msaitoh 	case WM_T_I210:
   13913  1.519   msaitoh 	case WM_T_I211:
   13914  1.519   msaitoh 		reg = CSR_READ(sc, WMREG_PHPM);
   13915  1.519   msaitoh 		reg &= ~PHPM_D0A_LPLU;
   13916  1.519   msaitoh 		CSR_WRITE(sc, WMREG_PHPM, reg);
   13917  1.519   msaitoh 		break;
   13918  1.519   msaitoh 	case WM_T_82574:
   13919  1.519   msaitoh 	case WM_T_82583:
   13920  1.519   msaitoh 	case WM_T_ICH8:
   13921  1.519   msaitoh 	case WM_T_ICH9:
   13922  1.519   msaitoh 	case WM_T_ICH10:
   13923  1.519   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13924  1.519   msaitoh 		reg &= ~(PHY_CTRL_GBE_DIS | PHY_CTRL_D0A_LPLU);
   13925  1.519   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13926  1.519   msaitoh 		CSR_WRITE_FLUSH(sc);
   13927  1.519   msaitoh 		break;
   13928  1.519   msaitoh 	case WM_T_PCH:
   13929  1.519   msaitoh 	case WM_T_PCH2:
   13930  1.519   msaitoh 	case WM_T_PCH_LPT:
   13931  1.519   msaitoh 	case WM_T_PCH_SPT:
   13932  1.519   msaitoh 		reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_OEM_BITS);
   13933  1.519   msaitoh 		reg &= ~(HV_OEM_BITS_A1KDIS | HV_OEM_BITS_LPLU);
   13934  1.519   msaitoh 		if (wm_phy_resetisblocked(sc) == false)
   13935  1.519   msaitoh 			reg |= HV_OEM_BITS_ANEGNOW;
   13936  1.519   msaitoh 		wm_gmii_hv_writereg(sc->sc_dev, 1, HV_OEM_BITS, reg);
   13937  1.519   msaitoh 		break;
   13938  1.519   msaitoh 	default:
   13939  1.519   msaitoh 		break;
   13940  1.519   msaitoh 	}
   13941  1.377   msaitoh }
   13942  1.377   msaitoh 
   13943  1.281   msaitoh /* EEE */
   13944  1.228   msaitoh 
   13945  1.228   msaitoh static void
   13946  1.281   msaitoh wm_set_eee_i350(struct wm_softc *sc)
   13947  1.228   msaitoh {
   13948  1.228   msaitoh 	uint32_t ipcnfg, eeer;
   13949  1.228   msaitoh 
   13950  1.228   msaitoh 	ipcnfg = CSR_READ(sc, WMREG_IPCNFG);
   13951  1.228   msaitoh 	eeer = CSR_READ(sc, WMREG_EEER);
   13952  1.228   msaitoh 
   13953  1.228   msaitoh 	if ((sc->sc_flags & WM_F_EEE) != 0) {
   13954  1.228   msaitoh 		ipcnfg |= (IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN);
   13955  1.228   msaitoh 		eeer |= (EEER_TX_LPI_EN | EEER_RX_LPI_EN
   13956  1.228   msaitoh 		    | EEER_LPI_FC);
   13957  1.228   msaitoh 	} else {
   13958  1.228   msaitoh 		ipcnfg &= ~(IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN);
   13959  1.322   msaitoh 		ipcnfg &= ~IPCNFG_10BASE_TE;
   13960  1.228   msaitoh 		eeer &= ~(EEER_TX_LPI_EN | EEER_RX_LPI_EN
   13961  1.228   msaitoh 		    | EEER_LPI_FC);
   13962  1.228   msaitoh 	}
   13963  1.228   msaitoh 
   13964  1.228   msaitoh 	CSR_WRITE(sc, WMREG_IPCNFG, ipcnfg);
   13965  1.228   msaitoh 	CSR_WRITE(sc, WMREG_EEER, eeer);
   13966  1.228   msaitoh 	CSR_READ(sc, WMREG_IPCNFG); /* XXX flush? */
   13967  1.228   msaitoh 	CSR_READ(sc, WMREG_EEER); /* XXX flush? */
   13968  1.228   msaitoh }
   13969  1.281   msaitoh 
   13970  1.281   msaitoh /*
   13971  1.281   msaitoh  * Workarounds (mainly PHY related).
   13972  1.281   msaitoh  * Basically, PHY's workarounds are in the PHY drivers.
   13973  1.281   msaitoh  */
   13974  1.281   msaitoh 
   13975  1.281   msaitoh /* Work-around for 82566 Kumeran PCS lock loss */
   13976  1.281   msaitoh static void
   13977  1.281   msaitoh wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *sc)
   13978  1.281   msaitoh {
   13979  1.523   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   13980  1.523   msaitoh 	uint32_t status = CSR_READ(sc, WMREG_STATUS);
   13981  1.523   msaitoh 	int i;
   13982  1.281   msaitoh 	int reg;
   13983  1.281   msaitoh 
   13984  1.523   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13985  1.523   msaitoh 		device_xname(sc->sc_dev), __func__));
   13986  1.281   msaitoh 
   13987  1.281   msaitoh 	/* If the link is not up, do nothing */
   13988  1.523   msaitoh 	if ((status & STATUS_LU) == 0)
   13989  1.281   msaitoh 		return;
   13990  1.281   msaitoh 
   13991  1.281   msaitoh 	/* Nothing to do if the link is other than 1Gbps */
   13992  1.523   msaitoh 	if (__SHIFTOUT(status, STATUS_SPEED) != STATUS_SPEED_1000)
   13993  1.281   msaitoh 		return;
   13994  1.281   msaitoh 
   13995  1.523   msaitoh 	reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13996  1.281   msaitoh 	for (i = 0; i < 10; i++) {
   13997  1.281   msaitoh 		/* read twice */
   13998  1.523   msaitoh 		reg = mii->mii_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
   13999  1.523   msaitoh 		reg = mii->mii_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
   14000  1.381   msaitoh 		if ((reg & IGP3_KMRN_DIAG_PCS_LOCK_LOSS) == 0)
   14001  1.281   msaitoh 			goto out;	/* GOOD! */
   14002  1.281   msaitoh 
   14003  1.281   msaitoh 		/* Reset the PHY */
   14004  1.523   msaitoh 		wm_reset_phy(sc);
   14005  1.281   msaitoh 		delay(5*1000);
   14006  1.281   msaitoh 	}
   14007  1.281   msaitoh 
   14008  1.281   msaitoh 	/* Disable GigE link negotiation */
   14009  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_PHY_CTRL);
   14010  1.281   msaitoh 	reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
   14011  1.281   msaitoh 	CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   14012  1.281   msaitoh 
   14013  1.281   msaitoh 	/*
   14014  1.281   msaitoh 	 * Call gig speed drop workaround on Gig disable before accessing
   14015  1.281   msaitoh 	 * any PHY registers.
   14016  1.281   msaitoh 	 */
   14017  1.281   msaitoh 	wm_gig_downshift_workaround_ich8lan(sc);
   14018  1.281   msaitoh 
   14019  1.281   msaitoh out:
   14020  1.281   msaitoh 	return;
   14021  1.281   msaitoh }
   14022  1.281   msaitoh 
   14023  1.281   msaitoh /* WOL from S5 stops working */
   14024  1.281   msaitoh static void
   14025  1.281   msaitoh wm_gig_downshift_workaround_ich8lan(struct wm_softc *sc)
   14026  1.281   msaitoh {
   14027  1.531   msaitoh 	uint16_t kmreg;
   14028  1.281   msaitoh 
   14029  1.281   msaitoh 	/* Only for igp3 */
   14030  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_IGP_3) {
   14031  1.531   msaitoh 		if (wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_DIAG, &kmreg) != 0)
   14032  1.531   msaitoh 			return;
   14033  1.531   msaitoh 		kmreg |= KUMCTRLSTA_DIAG_NELPBK;
   14034  1.531   msaitoh 		if (wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmreg) != 0)
   14035  1.531   msaitoh 			return;
   14036  1.531   msaitoh 		kmreg &= ~KUMCTRLSTA_DIAG_NELPBK;
   14037  1.531   msaitoh 		wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmreg);
   14038  1.281   msaitoh 	}
   14039  1.281   msaitoh }
   14040  1.281   msaitoh 
   14041  1.281   msaitoh /*
   14042  1.281   msaitoh  * Workaround for pch's PHYs
   14043  1.281   msaitoh  * XXX should be moved to new PHY driver?
   14044  1.281   msaitoh  */
   14045  1.281   msaitoh static void
   14046  1.281   msaitoh wm_hv_phy_workaround_ich8lan(struct wm_softc *sc)
   14047  1.281   msaitoh {
   14048  1.420   msaitoh 
   14049  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14050  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   14051  1.420   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH);
   14052  1.420   msaitoh 
   14053  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_82577)
   14054  1.281   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   14055  1.281   msaitoh 
   14056  1.281   msaitoh 	/* (PCH rev.2) && (82577 && (phy rev 2 or 3)) */
   14057  1.281   msaitoh 
   14058  1.281   msaitoh 	/* (82577 && (phy rev 1 or 2)) || (82578 & phy rev 1)*/
   14059  1.281   msaitoh 
   14060  1.281   msaitoh 	/* 82578 */
   14061  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_82578) {
   14062  1.430   msaitoh 		struct mii_softc *child;
   14063  1.430   msaitoh 
   14064  1.430   msaitoh 		/*
   14065  1.430   msaitoh 		 * Return registers to default by doing a soft reset then
   14066  1.430   msaitoh 		 * writing 0x3140 to the control register
   14067  1.430   msaitoh 		 * 0x3140 == BMCR_SPEED0 | BMCR_AUTOEN | BMCR_FDX | BMCR_SPEED1
   14068  1.430   msaitoh 		 */
   14069  1.430   msaitoh 		child = LIST_FIRST(&sc->sc_mii.mii_phys);
   14070  1.430   msaitoh 		if ((child != NULL) && (child->mii_mpd_rev < 2)) {
   14071  1.430   msaitoh 			PHY_RESET(child);
   14072  1.430   msaitoh 			sc->sc_mii.mii_writereg(sc->sc_dev, 2, MII_BMCR,
   14073  1.430   msaitoh 			    0x3140);
   14074  1.281   msaitoh 		}
   14075  1.281   msaitoh 	}
   14076  1.281   msaitoh 
   14077  1.281   msaitoh 	/* Select page 0 */
   14078  1.424   msaitoh 	sc->phy.acquire(sc);
   14079  1.424   msaitoh 	wm_gmii_mdic_writereg(sc->sc_dev, 1, MII_IGPHY_PAGE_SELECT, 0);
   14080  1.424   msaitoh 	sc->phy.release(sc);
   14081  1.281   msaitoh 
   14082  1.281   msaitoh 	/*
   14083  1.281   msaitoh 	 * Configure the K1 Si workaround during phy reset assuming there is
   14084  1.281   msaitoh 	 * link so that it disables K1 if link is in 1Gbps.
   14085  1.281   msaitoh 	 */
   14086  1.281   msaitoh 	wm_k1_gig_workaround_hv(sc, 1);
   14087  1.281   msaitoh }
   14088  1.281   msaitoh 
   14089  1.281   msaitoh static void
   14090  1.281   msaitoh wm_lv_phy_workaround_ich8lan(struct wm_softc *sc)
   14091  1.281   msaitoh {
   14092  1.281   msaitoh 
   14093  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14094  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   14095  1.420   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH2);
   14096  1.420   msaitoh 
   14097  1.281   msaitoh 	wm_set_mdio_slow_mode_hv(sc);
   14098  1.281   msaitoh }
   14099  1.281   msaitoh 
   14100  1.424   msaitoh static int
   14101  1.281   msaitoh wm_k1_gig_workaround_hv(struct wm_softc *sc, int link)
   14102  1.281   msaitoh {
   14103  1.281   msaitoh 	int k1_enable = sc->sc_nvm_k1_enabled;
   14104  1.281   msaitoh 
   14105  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14106  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   14107  1.420   msaitoh 
   14108  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0)
   14109  1.424   msaitoh 		return -1;
   14110  1.281   msaitoh 
   14111  1.281   msaitoh 	if (link) {
   14112  1.281   msaitoh 		k1_enable = 0;
   14113  1.281   msaitoh 
   14114  1.281   msaitoh 		/* Link stall fix for link up */
   14115  1.424   msaitoh 		wm_gmii_hv_writereg_locked(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x0100);
   14116  1.281   msaitoh 	} else {
   14117  1.281   msaitoh 		/* Link stall fix for link down */
   14118  1.424   msaitoh 		wm_gmii_hv_writereg_locked(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x4100);
   14119  1.281   msaitoh 	}
   14120  1.281   msaitoh 
   14121  1.281   msaitoh 	wm_configure_k1_ich8lan(sc, k1_enable);
   14122  1.424   msaitoh 	sc->phy.release(sc);
   14123  1.281   msaitoh 
   14124  1.424   msaitoh 	return 0;
   14125  1.281   msaitoh }
   14126  1.281   msaitoh 
   14127  1.281   msaitoh static void
   14128  1.281   msaitoh wm_set_mdio_slow_mode_hv(struct wm_softc *sc)
   14129  1.281   msaitoh {
   14130  1.281   msaitoh 	uint32_t reg;
   14131  1.281   msaitoh 
   14132  1.281   msaitoh 	reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL);
   14133  1.281   msaitoh 	wm_gmii_hv_writereg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL,
   14134  1.281   msaitoh 	    reg | HV_KMRN_MDIO_SLOW);
   14135  1.281   msaitoh }
   14136  1.281   msaitoh 
   14137  1.281   msaitoh static void
   14138  1.281   msaitoh wm_configure_k1_ich8lan(struct wm_softc *sc, int k1_enable)
   14139  1.281   msaitoh {
   14140  1.281   msaitoh 	uint32_t ctrl, ctrl_ext, tmp;
   14141  1.531   msaitoh 	uint16_t kmreg;
   14142  1.531   msaitoh 	int rv;
   14143  1.281   msaitoh 
   14144  1.531   msaitoh 	rv = wm_kmrn_readreg_locked(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, &kmreg);
   14145  1.531   msaitoh 	if (rv != 0)
   14146  1.531   msaitoh 		return;
   14147  1.281   msaitoh 
   14148  1.281   msaitoh 	if (k1_enable)
   14149  1.531   msaitoh 		kmreg |= KUMCTRLSTA_K1_ENABLE;
   14150  1.281   msaitoh 	else
   14151  1.531   msaitoh 		kmreg &= ~KUMCTRLSTA_K1_ENABLE;
   14152  1.281   msaitoh 
   14153  1.531   msaitoh 	rv = wm_kmrn_writereg_locked(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, kmreg);
   14154  1.531   msaitoh 	if (rv != 0)
   14155  1.531   msaitoh 		return;
   14156  1.281   msaitoh 
   14157  1.281   msaitoh 	delay(20);
   14158  1.281   msaitoh 
   14159  1.281   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   14160  1.281   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   14161  1.281   msaitoh 
   14162  1.281   msaitoh 	tmp = ctrl & ~(CTRL_SPEED_1000 | CTRL_SPEED_100);
   14163  1.281   msaitoh 	tmp |= CTRL_FRCSPD;
   14164  1.281   msaitoh 
   14165  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, tmp);
   14166  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_SPD_BYPS);
   14167  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   14168  1.281   msaitoh 	delay(20);
   14169  1.281   msaitoh 
   14170  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, ctrl);
   14171  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   14172  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   14173  1.281   msaitoh 	delay(20);
   14174  1.531   msaitoh 
   14175  1.531   msaitoh 	return;
   14176  1.281   msaitoh }
   14177  1.281   msaitoh 
   14178  1.281   msaitoh /* special case - for 82575 - need to do manual init ... */
   14179  1.281   msaitoh static void
   14180  1.281   msaitoh wm_reset_init_script_82575(struct wm_softc *sc)
   14181  1.281   msaitoh {
   14182  1.281   msaitoh 	/*
   14183  1.281   msaitoh 	 * remark: this is untested code - we have no board without EEPROM
   14184  1.312   msaitoh 	 *  same setup as mentioned int the FreeBSD driver for the i82575
   14185  1.281   msaitoh 	 */
   14186  1.281   msaitoh 
   14187  1.281   msaitoh 	/* SerDes configuration via SERDESCTRL */
   14188  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x00, 0x0c);
   14189  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x01, 0x78);
   14190  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x1b, 0x23);
   14191  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x23, 0x15);
   14192  1.281   msaitoh 
   14193  1.281   msaitoh 	/* CCM configuration via CCMCTL register */
   14194  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x14, 0x00);
   14195  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x10, 0x00);
   14196  1.281   msaitoh 
   14197  1.281   msaitoh 	/* PCIe lanes configuration */
   14198  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x00, 0xec);
   14199  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x61, 0xdf);
   14200  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x34, 0x05);
   14201  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x2f, 0x81);
   14202  1.281   msaitoh 
   14203  1.281   msaitoh 	/* PCIe PLL Configuration */
   14204  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x02, 0x47);
   14205  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x14, 0x00);
   14206  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x10, 0x00);
   14207  1.281   msaitoh }
   14208  1.325   msaitoh 
   14209  1.325   msaitoh static void
   14210  1.325   msaitoh wm_reset_mdicnfg_82580(struct wm_softc *sc)
   14211  1.325   msaitoh {
   14212  1.325   msaitoh 	uint32_t reg;
   14213  1.325   msaitoh 	uint16_t nvmword;
   14214  1.325   msaitoh 	int rv;
   14215  1.325   msaitoh 
   14216  1.325   msaitoh 	if ((sc->sc_flags & WM_F_SGMII) == 0)
   14217  1.325   msaitoh 		return;
   14218  1.325   msaitoh 
   14219  1.325   msaitoh 	rv = wm_nvm_read(sc, NVM_OFF_LAN_FUNC_82580(sc->sc_funcid)
   14220  1.325   msaitoh 	    + NVM_OFF_CFG3_PORTA, 1, &nvmword);
   14221  1.325   msaitoh 	if (rv != 0) {
   14222  1.325   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to read NVM\n",
   14223  1.325   msaitoh 		    __func__);
   14224  1.325   msaitoh 		return;
   14225  1.325   msaitoh 	}
   14226  1.325   msaitoh 
   14227  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_MDICNFG);
   14228  1.325   msaitoh 	if (nvmword & NVM_CFG3_PORTA_EXT_MDIO)
   14229  1.325   msaitoh 		reg |= MDICNFG_DEST;
   14230  1.325   msaitoh 	if (nvmword & NVM_CFG3_PORTA_COM_MDIO)
   14231  1.325   msaitoh 		reg |= MDICNFG_COM_MDIO;
   14232  1.325   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, reg);
   14233  1.325   msaitoh }
   14234  1.329   msaitoh 
   14235  1.447   msaitoh #define MII_INVALIDID(x)	(((x) == 0x0000) || ((x) == 0xffff))
   14236  1.447   msaitoh 
   14237  1.447   msaitoh static bool
   14238  1.447   msaitoh wm_phy_is_accessible_pchlan(struct wm_softc *sc)
   14239  1.447   msaitoh {
   14240  1.447   msaitoh 	int i;
   14241  1.447   msaitoh 	uint32_t reg;
   14242  1.447   msaitoh 	uint16_t id1, id2;
   14243  1.447   msaitoh 
   14244  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14245  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   14246  1.447   msaitoh 	id1 = id2 = 0xffff;
   14247  1.447   msaitoh 	for (i = 0; i < 2; i++) {
   14248  1.447   msaitoh 		id1 = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, MII_PHYIDR1);
   14249  1.447   msaitoh 		if (MII_INVALIDID(id1))
   14250  1.447   msaitoh 			continue;
   14251  1.447   msaitoh 		id2 = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, MII_PHYIDR2);
   14252  1.447   msaitoh 		if (MII_INVALIDID(id2))
   14253  1.447   msaitoh 			continue;
   14254  1.447   msaitoh 		break;
   14255  1.447   msaitoh 	}
   14256  1.447   msaitoh 	if (!MII_INVALIDID(id1) && !MII_INVALIDID(id2)) {
   14257  1.447   msaitoh 		goto out;
   14258  1.447   msaitoh 	}
   14259  1.447   msaitoh 
   14260  1.447   msaitoh 	if (sc->sc_type < WM_T_PCH_LPT) {
   14261  1.447   msaitoh 		sc->phy.release(sc);
   14262  1.447   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   14263  1.447   msaitoh 		id1 = wm_gmii_hv_readreg(sc->sc_dev, 2, MII_PHYIDR1);
   14264  1.447   msaitoh 		id2 = wm_gmii_hv_readreg(sc->sc_dev, 2, MII_PHYIDR2);
   14265  1.447   msaitoh 		sc->phy.acquire(sc);
   14266  1.447   msaitoh 	}
   14267  1.447   msaitoh 	if (MII_INVALIDID(id1) || MII_INVALIDID(id2)) {
   14268  1.447   msaitoh 		printf("XXX return with false\n");
   14269  1.447   msaitoh 		return false;
   14270  1.447   msaitoh 	}
   14271  1.447   msaitoh out:
   14272  1.447   msaitoh 	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) {
   14273  1.447   msaitoh 		/* Only unforce SMBus if ME is not active */
   14274  1.447   msaitoh 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) == 0) {
   14275  1.447   msaitoh 			/* Unforce SMBus mode in PHY */
   14276  1.447   msaitoh 			reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2,
   14277  1.447   msaitoh 			    CV_SMB_CTRL);
   14278  1.447   msaitoh 			reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
   14279  1.447   msaitoh 			wm_gmii_hv_writereg_locked(sc->sc_dev, 2,
   14280  1.447   msaitoh 			    CV_SMB_CTRL, reg);
   14281  1.447   msaitoh 
   14282  1.447   msaitoh 			/* Unforce SMBus mode in MAC */
   14283  1.447   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   14284  1.447   msaitoh 			reg &= ~CTRL_EXT_FORCE_SMBUS;
   14285  1.447   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   14286  1.447   msaitoh 		}
   14287  1.447   msaitoh 	}
   14288  1.447   msaitoh 	return true;
   14289  1.447   msaitoh }
   14290  1.447   msaitoh 
   14291  1.447   msaitoh static void
   14292  1.447   msaitoh wm_toggle_lanphypc_pch_lpt(struct wm_softc *sc)
   14293  1.447   msaitoh {
   14294  1.447   msaitoh 	uint32_t reg;
   14295  1.447   msaitoh 	int i;
   14296  1.447   msaitoh 
   14297  1.447   msaitoh 	/* Set PHY Config Counter to 50msec */
   14298  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM3);
   14299  1.447   msaitoh 	reg &= ~FEXTNVM3_PHY_CFG_COUNTER_MASK;
   14300  1.447   msaitoh 	reg |= FEXTNVM3_PHY_CFG_COUNTER_50MS;
   14301  1.447   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM3, reg);
   14302  1.447   msaitoh 
   14303  1.447   msaitoh 	/* Toggle LANPHYPC */
   14304  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL);
   14305  1.447   msaitoh 	reg |= CTRL_LANPHYPC_OVERRIDE;
   14306  1.447   msaitoh 	reg &= ~CTRL_LANPHYPC_VALUE;
   14307  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   14308  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   14309  1.447   msaitoh 	delay(1000);
   14310  1.447   msaitoh 	reg &= ~CTRL_LANPHYPC_OVERRIDE;
   14311  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   14312  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   14313  1.447   msaitoh 
   14314  1.447   msaitoh 	if (sc->sc_type < WM_T_PCH_LPT)
   14315  1.447   msaitoh 		delay(50 * 1000);
   14316  1.447   msaitoh 	else {
   14317  1.447   msaitoh 		i = 20;
   14318  1.447   msaitoh 
   14319  1.447   msaitoh 		do {
   14320  1.447   msaitoh 			delay(5 * 1000);
   14321  1.447   msaitoh 		} while (((CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_LPCD) == 0)
   14322  1.447   msaitoh 		    && i--);
   14323  1.447   msaitoh 
   14324  1.447   msaitoh 		delay(30 * 1000);
   14325  1.447   msaitoh 	}
   14326  1.447   msaitoh }
   14327  1.447   msaitoh 
   14328  1.445   msaitoh static int
   14329  1.445   msaitoh wm_platform_pm_pch_lpt(struct wm_softc *sc, bool link)
   14330  1.445   msaitoh {
   14331  1.445   msaitoh 	uint32_t reg = __SHIFTIN(link, LTRV_NONSNOOP_REQ)
   14332  1.445   msaitoh 	    | __SHIFTIN(link, LTRV_SNOOP_REQ) | LTRV_SEND;
   14333  1.445   msaitoh 	uint32_t rxa;
   14334  1.445   msaitoh 	uint16_t scale = 0, lat_enc = 0;
   14335  1.517   msaitoh 	int32_t obff_hwm = 0;
   14336  1.445   msaitoh 	int64_t lat_ns, value;
   14337  1.445   msaitoh 
   14338  1.445   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14339  1.445   msaitoh 		device_xname(sc->sc_dev), __func__));
   14340  1.445   msaitoh 
   14341  1.445   msaitoh 	if (link) {
   14342  1.517   msaitoh 		uint16_t max_snoop, max_nosnoop, max_ltr_enc;
   14343  1.517   msaitoh 		uint32_t status;
   14344  1.517   msaitoh 		uint16_t speed;
   14345  1.445   msaitoh 		pcireg_t preg;
   14346  1.445   msaitoh 
   14347  1.517   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   14348  1.517   msaitoh 		switch (__SHIFTOUT(status, STATUS_SPEED)) {
   14349  1.517   msaitoh 		case STATUS_SPEED_10:
   14350  1.517   msaitoh 			speed = 10;
   14351  1.517   msaitoh 			break;
   14352  1.517   msaitoh 		case STATUS_SPEED_100:
   14353  1.517   msaitoh 			speed = 100;
   14354  1.517   msaitoh 			break;
   14355  1.517   msaitoh 		case STATUS_SPEED_1000:
   14356  1.517   msaitoh 			speed = 1000;
   14357  1.517   msaitoh 			break;
   14358  1.517   msaitoh 		default:
   14359  1.517   msaitoh 			device_printf(sc->sc_dev, "Unknown speed "
   14360  1.517   msaitoh 			    "(status = %08x)\n", status);
   14361  1.517   msaitoh 			return -1;
   14362  1.517   msaitoh 		}
   14363  1.517   msaitoh 
   14364  1.517   msaitoh 		/* Rx Packet Buffer Allocation size (KB) */
   14365  1.445   msaitoh 		rxa = CSR_READ(sc, WMREG_PBA) & PBA_RXA_MASK;
   14366  1.445   msaitoh 
   14367  1.445   msaitoh 		/*
   14368  1.445   msaitoh 		 * Determine the maximum latency tolerated by the device.
   14369  1.445   msaitoh 		 *
   14370  1.445   msaitoh 		 * Per the PCIe spec, the tolerated latencies are encoded as
   14371  1.445   msaitoh 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
   14372  1.445   msaitoh 		 * a 10-bit value (0-1023) to provide a range from 1 ns to
   14373  1.445   msaitoh 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
   14374  1.445   msaitoh 		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
   14375  1.445   msaitoh 		 */
   14376  1.445   msaitoh 		lat_ns = ((int64_t)rxa * 1024 -
   14377  1.517   msaitoh 		    (2 * ((int64_t)sc->sc_ethercom.ec_if.if_mtu
   14378  1.517   msaitoh 			+ ETHER_HDR_LEN))) * 8 * 1000;
   14379  1.445   msaitoh 		if (lat_ns < 0)
   14380  1.445   msaitoh 			lat_ns = 0;
   14381  1.517   msaitoh 		else
   14382  1.445   msaitoh 			lat_ns /= speed;
   14383  1.445   msaitoh 		value = lat_ns;
   14384  1.445   msaitoh 
   14385  1.445   msaitoh 		while (value > LTRV_VALUE) {
   14386  1.445   msaitoh 			scale ++;
   14387  1.445   msaitoh 			value = howmany(value, __BIT(5));
   14388  1.445   msaitoh 		}
   14389  1.445   msaitoh 		if (scale > LTRV_SCALE_MAX) {
   14390  1.445   msaitoh 			printf("%s: Invalid LTR latency scale %d\n",
   14391  1.445   msaitoh 			    device_xname(sc->sc_dev), scale);
   14392  1.445   msaitoh 			return -1;
   14393  1.445   msaitoh 		}
   14394  1.445   msaitoh 		lat_enc = (uint16_t)(__SHIFTIN(scale, LTRV_SCALE) | value);
   14395  1.445   msaitoh 
   14396  1.511   msaitoh 		/* Determine the maximum latency tolerated by the platform */
   14397  1.445   msaitoh 		preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   14398  1.445   msaitoh 		    WM_PCI_LTR_CAP_LPT);
   14399  1.445   msaitoh 		max_snoop = preg & 0xffff;
   14400  1.445   msaitoh 		max_nosnoop = preg >> 16;
   14401  1.445   msaitoh 
   14402  1.445   msaitoh 		max_ltr_enc = MAX(max_snoop, max_nosnoop);
   14403  1.445   msaitoh 
   14404  1.445   msaitoh 		if (lat_enc > max_ltr_enc) {
   14405  1.445   msaitoh 			lat_enc = max_ltr_enc;
   14406  1.517   msaitoh 			lat_ns = __SHIFTOUT(lat_enc, PCI_LTR_MAXSNOOPLAT_VAL)
   14407  1.517   msaitoh 			    * PCI_LTR_SCALETONS(
   14408  1.517   msaitoh 				    __SHIFTOUT(lat_enc,
   14409  1.517   msaitoh 					PCI_LTR_MAXSNOOPLAT_SCALE));
   14410  1.517   msaitoh 		}
   14411  1.517   msaitoh 
   14412  1.517   msaitoh 		if (lat_ns) {
   14413  1.517   msaitoh 			lat_ns *= speed * 1000;
   14414  1.517   msaitoh 			lat_ns /= 8;
   14415  1.517   msaitoh 			lat_ns /= 1000000000;
   14416  1.517   msaitoh 			obff_hwm = (int32_t)(rxa - lat_ns);
   14417  1.517   msaitoh 		}
   14418  1.517   msaitoh 		if ((obff_hwm < 0) || (obff_hwm > SVT_OFF_HWM)) {
   14419  1.517   msaitoh 			device_printf(sc->sc_dev, "Invalid high water mark %d"
   14420  1.517   msaitoh 			    "(rxa = %d, lat_ns = %d)\n",
   14421  1.517   msaitoh 			    obff_hwm, (int32_t)rxa, (int32_t)lat_ns);
   14422  1.517   msaitoh 			return -1;
   14423  1.445   msaitoh 		}
   14424  1.445   msaitoh 	}
   14425  1.445   msaitoh 	/* Snoop and No-Snoop latencies the same */
   14426  1.445   msaitoh 	reg |= lat_enc | __SHIFTIN(lat_enc, LTRV_NONSNOOP);
   14427  1.445   msaitoh 	CSR_WRITE(sc, WMREG_LTRV, reg);
   14428  1.445   msaitoh 
   14429  1.517   msaitoh 	/* Set OBFF high water mark */
   14430  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_SVT) & ~SVT_OFF_HWM;
   14431  1.517   msaitoh 	reg |= obff_hwm;
   14432  1.517   msaitoh 	CSR_WRITE(sc, WMREG_SVT, reg);
   14433  1.517   msaitoh 
   14434  1.517   msaitoh 	/* Enable OBFF */
   14435  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_SVCR);
   14436  1.517   msaitoh 	reg |= SVCR_OFF_EN | SVCR_OFF_MASKINT;
   14437  1.517   msaitoh 	CSR_WRITE(sc, WMREG_SVCR, reg);
   14438  1.517   msaitoh 
   14439  1.445   msaitoh 	return 0;
   14440  1.445   msaitoh }
   14441  1.445   msaitoh 
   14442  1.329   msaitoh /*
   14443  1.329   msaitoh  * I210 Errata 25 and I211 Errata 10
   14444  1.329   msaitoh  * Slow System Clock.
   14445  1.329   msaitoh  */
   14446  1.329   msaitoh static void
   14447  1.329   msaitoh wm_pll_workaround_i210(struct wm_softc *sc)
   14448  1.329   msaitoh {
   14449  1.329   msaitoh 	uint32_t mdicnfg, wuc;
   14450  1.329   msaitoh 	uint32_t reg;
   14451  1.329   msaitoh 	pcireg_t pcireg;
   14452  1.329   msaitoh 	uint32_t pmreg;
   14453  1.329   msaitoh 	uint16_t nvmword, tmp_nvmword;
   14454  1.329   msaitoh 	int phyval;
   14455  1.329   msaitoh 	bool wa_done = false;
   14456  1.329   msaitoh 	int i;
   14457  1.329   msaitoh 
   14458  1.329   msaitoh 	/* Save WUC and MDICNFG registers */
   14459  1.329   msaitoh 	wuc = CSR_READ(sc, WMREG_WUC);
   14460  1.329   msaitoh 	mdicnfg = CSR_READ(sc, WMREG_MDICNFG);
   14461  1.329   msaitoh 
   14462  1.329   msaitoh 	reg = mdicnfg & ~MDICNFG_DEST;
   14463  1.329   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, reg);
   14464  1.329   msaitoh 
   14465  1.329   msaitoh 	if (wm_nvm_read(sc, INVM_AUTOLOAD, 1, &nvmword) != 0)
   14466  1.329   msaitoh 		nvmword = INVM_DEFAULT_AL;
   14467  1.329   msaitoh 	tmp_nvmword = nvmword | INVM_PLL_WO_VAL;
   14468  1.329   msaitoh 
   14469  1.329   msaitoh 	/* Get Power Management cap offset */
   14470  1.329   msaitoh 	if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT,
   14471  1.329   msaitoh 		&pmreg, NULL) == 0)
   14472  1.329   msaitoh 		return;
   14473  1.329   msaitoh 	for (i = 0; i < WM_MAX_PLL_TRIES; i++) {
   14474  1.329   msaitoh 		phyval = wm_gmii_gs40g_readreg(sc->sc_dev, 1,
   14475  1.329   msaitoh 		    GS40G_PHY_PLL_FREQ_PAGE | GS40G_PHY_PLL_FREQ_REG);
   14476  1.332   msaitoh 
   14477  1.329   msaitoh 		if ((phyval & GS40G_PHY_PLL_UNCONF) != GS40G_PHY_PLL_UNCONF) {
   14478  1.329   msaitoh 			break; /* OK */
   14479  1.329   msaitoh 		}
   14480  1.329   msaitoh 
   14481  1.329   msaitoh 		wa_done = true;
   14482  1.329   msaitoh 		/* Directly reset the internal PHY */
   14483  1.329   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL);
   14484  1.329   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);
   14485  1.329   msaitoh 
   14486  1.329   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   14487  1.329   msaitoh 		reg |= CTRL_EXT_PHYPDEN | CTRL_EXT_SDLPE;
   14488  1.329   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   14489  1.329   msaitoh 
   14490  1.329   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   14491  1.329   msaitoh 		reg = (INVM_AUTOLOAD << 4) | (tmp_nvmword << 16);
   14492  1.329   msaitoh 		CSR_WRITE(sc, WMREG_EEARBC_I210, reg);
   14493  1.332   msaitoh 
   14494  1.329   msaitoh 		pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   14495  1.329   msaitoh 		    pmreg + PCI_PMCSR);
   14496  1.329   msaitoh 		pcireg |= PCI_PMCSR_STATE_D3;
   14497  1.329   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   14498  1.329   msaitoh 		    pmreg + PCI_PMCSR, pcireg);
   14499  1.329   msaitoh 		delay(1000);
   14500  1.329   msaitoh 		pcireg &= ~PCI_PMCSR_STATE_D3;
   14501  1.329   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   14502  1.329   msaitoh 		    pmreg + PCI_PMCSR, pcireg);
   14503  1.329   msaitoh 
   14504  1.329   msaitoh 		reg = (INVM_AUTOLOAD << 4) | (nvmword << 16);
   14505  1.329   msaitoh 		CSR_WRITE(sc, WMREG_EEARBC_I210, reg);
   14506  1.332   msaitoh 
   14507  1.329   msaitoh 		/* Restore WUC register */
   14508  1.329   msaitoh 		CSR_WRITE(sc, WMREG_WUC, wuc);
   14509  1.329   msaitoh 	}
   14510  1.332   msaitoh 
   14511  1.329   msaitoh 	/* Restore MDICNFG setting */
   14512  1.329   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, mdicnfg);
   14513  1.329   msaitoh 	if (wa_done)
   14514  1.329   msaitoh 		aprint_verbose_dev(sc->sc_dev, "I210 workaround done\n");
   14515  1.329   msaitoh }
   14516  1.517   msaitoh 
   14517  1.517   msaitoh static void
   14518  1.517   msaitoh wm_legacy_irq_quirk_spt(struct wm_softc *sc)
   14519  1.517   msaitoh {
   14520  1.517   msaitoh 	uint32_t reg;
   14521  1.517   msaitoh 
   14522  1.517   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14523  1.517   msaitoh 		device_xname(sc->sc_dev), __func__));
   14524  1.517   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH_SPT);
   14525  1.517   msaitoh 
   14526  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM7);
   14527  1.517   msaitoh 	reg |= FEXTNVM7_SIDE_CLK_UNGATE;
   14528  1.517   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM7, reg);
   14529  1.517   msaitoh 
   14530  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM9);
   14531  1.517   msaitoh 	reg |= FEXTNVM9_IOSFSB_CLKGATE_DIS | FEXTNVM9_IOSFSB_CLKREQ_DIS;
   14532  1.517   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM9, reg);
   14533  1.517   msaitoh }
   14534