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if_wm.c revision 1.576
      1  1.576   msaitoh /*	$NetBSD: if_wm.c,v 1.576 2018/04/23 01:35:25 msaitoh Exp $	*/
      2    1.1   thorpej 
      3    1.1   thorpej /*
      4   1.69   thorpej  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
      5    1.1   thorpej  * All rights reserved.
      6    1.1   thorpej  *
      7    1.1   thorpej  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8    1.1   thorpej  *
      9    1.1   thorpej  * Redistribution and use in source and binary forms, with or without
     10    1.1   thorpej  * modification, are permitted provided that the following conditions
     11    1.1   thorpej  * are met:
     12    1.1   thorpej  * 1. Redistributions of source code must retain the above copyright
     13    1.1   thorpej  *    notice, this list of conditions and the following disclaimer.
     14    1.1   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     15    1.1   thorpej  *    notice, this list of conditions and the following disclaimer in the
     16    1.1   thorpej  *    documentation and/or other materials provided with the distribution.
     17    1.1   thorpej  * 3. All advertising materials mentioning features or use of this software
     18    1.1   thorpej  *    must display the following acknowledgement:
     19    1.1   thorpej  *	This product includes software developed for the NetBSD Project by
     20    1.1   thorpej  *	Wasabi Systems, Inc.
     21    1.1   thorpej  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22    1.1   thorpej  *    or promote products derived from this software without specific prior
     23    1.1   thorpej  *    written permission.
     24    1.1   thorpej  *
     25    1.1   thorpej  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26    1.1   thorpej  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27    1.1   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28    1.1   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29    1.1   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30    1.1   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31    1.1   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32    1.1   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33    1.1   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34    1.1   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35    1.1   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     36    1.1   thorpej  */
     37    1.1   thorpej 
     38  1.139    bouyer /*******************************************************************************
     39  1.139    bouyer 
     40  1.246  christos   Copyright (c) 2001-2005, Intel Corporation
     41  1.139    bouyer   All rights reserved.
     42  1.246  christos 
     43  1.246  christos   Redistribution and use in source and binary forms, with or without
     44  1.139    bouyer   modification, are permitted provided that the following conditions are met:
     45  1.246  christos 
     46  1.246  christos    1. Redistributions of source code must retain the above copyright notice,
     47  1.139    bouyer       this list of conditions and the following disclaimer.
     48  1.246  christos 
     49  1.246  christos    2. Redistributions in binary form must reproduce the above copyright
     50  1.246  christos       notice, this list of conditions and the following disclaimer in the
     51  1.139    bouyer       documentation and/or other materials provided with the distribution.
     52  1.246  christos 
     53  1.246  christos    3. Neither the name of the Intel Corporation nor the names of its
     54  1.246  christos       contributors may be used to endorse or promote products derived from
     55  1.139    bouyer       this software without specific prior written permission.
     56  1.246  christos 
     57  1.139    bouyer   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     58  1.246  christos   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     59  1.246  christos   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     60  1.246  christos   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
     61  1.246  christos   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     62  1.246  christos   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     63  1.246  christos   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     64  1.246  christos   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     65  1.246  christos   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     66  1.139    bouyer   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     67  1.139    bouyer   POSSIBILITY OF SUCH DAMAGE.
     68  1.139    bouyer 
     69  1.139    bouyer *******************************************************************************/
     70    1.1   thorpej /*
     71   1.11   thorpej  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
     72    1.1   thorpej  *
     73    1.1   thorpej  * TODO (in order of importance):
     74    1.1   thorpej  *
     75  1.288   msaitoh  *	- Check XXX'ed comments
     76  1.407  knakahar  *	- TX Multi queue improvement (refine queue selection logic)
     77  1.467  knakahar  *	- Split header buffer for newer descriptors
     78  1.286   msaitoh  *	- EEE (Energy Efficiency Ethernet)
     79  1.286   msaitoh  *	- Virtual Function
     80  1.286   msaitoh  *	- Set LED correctly (based on contents in EEPROM)
     81   1.61   thorpej  *	- Rework how parameters are loaded from the EEPROM.
     82  1.371   msaitoh  *	- Image Unique ID
     83    1.1   thorpej  */
     84   1.38     lukem 
     85   1.38     lukem #include <sys/cdefs.h>
     86  1.576   msaitoh __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.576 2018/04/23 01:35:25 msaitoh Exp $");
     87  1.309     ozaki 
     88  1.309     ozaki #ifdef _KERNEL_OPT
     89  1.309     ozaki #include "opt_net_mpsafe.h"
     90  1.494  knakahar #include "opt_if_wm.h"
     91  1.309     ozaki #endif
     92    1.1   thorpej 
     93    1.1   thorpej #include <sys/param.h>
     94    1.1   thorpej #include <sys/systm.h>
     95   1.96     perry #include <sys/callout.h>
     96    1.1   thorpej #include <sys/mbuf.h>
     97    1.1   thorpej #include <sys/malloc.h>
     98  1.356  knakahar #include <sys/kmem.h>
     99    1.1   thorpej #include <sys/kernel.h>
    100    1.1   thorpej #include <sys/socket.h>
    101    1.1   thorpej #include <sys/ioctl.h>
    102    1.1   thorpej #include <sys/errno.h>
    103    1.1   thorpej #include <sys/device.h>
    104    1.1   thorpej #include <sys/queue.h>
    105   1.84   thorpej #include <sys/syslog.h>
    106  1.346  knakahar #include <sys/interrupt.h>
    107  1.403  knakahar #include <sys/cpu.h>
    108  1.403  knakahar #include <sys/pcq.h>
    109    1.1   thorpej 
    110  1.315  riastrad #include <sys/rndsource.h>
    111   1.21    itojun 
    112    1.1   thorpej #include <net/if.h>
    113   1.96     perry #include <net/if_dl.h>
    114    1.1   thorpej #include <net/if_media.h>
    115    1.1   thorpej #include <net/if_ether.h>
    116    1.1   thorpej 
    117    1.1   thorpej #include <net/bpf.h>
    118    1.1   thorpej 
    119  1.564  knakahar #include <net/rss_config.h>
    120  1.564  knakahar 
    121    1.1   thorpej #include <netinet/in.h>			/* XXX for struct ip */
    122    1.1   thorpej #include <netinet/in_systm.h>		/* XXX for struct ip */
    123    1.1   thorpej #include <netinet/ip.h>			/* XXX for struct ip */
    124  1.131      yamt #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
    125   1.13   thorpej #include <netinet/tcp.h>		/* XXX for struct tcphdr */
    126    1.1   thorpej 
    127  1.147        ad #include <sys/bus.h>
    128  1.147        ad #include <sys/intr.h>
    129    1.1   thorpej #include <machine/endian.h>
    130    1.1   thorpej 
    131    1.1   thorpej #include <dev/mii/mii.h>
    132    1.1   thorpej #include <dev/mii/miivar.h>
    133  1.202   msaitoh #include <dev/mii/miidevs.h>
    134    1.1   thorpej #include <dev/mii/mii_bitbang.h>
    135  1.127    bouyer #include <dev/mii/ikphyreg.h>
    136  1.191   msaitoh #include <dev/mii/igphyreg.h>
    137  1.202   msaitoh #include <dev/mii/igphyvar.h>
    138  1.192   msaitoh #include <dev/mii/inbmphyreg.h>
    139  1.528   msaitoh #include <dev/mii/ihphyreg.h>
    140    1.1   thorpej 
    141    1.1   thorpej #include <dev/pci/pcireg.h>
    142    1.1   thorpej #include <dev/pci/pcivar.h>
    143    1.1   thorpej #include <dev/pci/pcidevs.h>
    144    1.1   thorpej 
    145    1.1   thorpej #include <dev/pci/if_wmreg.h>
    146  1.182   msaitoh #include <dev/pci/if_wmvar.h>
    147    1.1   thorpej 
    148    1.1   thorpej #ifdef WM_DEBUG
    149  1.420   msaitoh #define	WM_DEBUG_LINK		__BIT(0)
    150  1.420   msaitoh #define	WM_DEBUG_TX		__BIT(1)
    151  1.420   msaitoh #define	WM_DEBUG_RX		__BIT(2)
    152  1.420   msaitoh #define	WM_DEBUG_GMII		__BIT(3)
    153  1.420   msaitoh #define	WM_DEBUG_MANAGE		__BIT(4)
    154  1.420   msaitoh #define	WM_DEBUG_NVM		__BIT(5)
    155  1.420   msaitoh #define	WM_DEBUG_INIT		__BIT(6)
    156  1.420   msaitoh #define	WM_DEBUG_LOCK		__BIT(7)
    157  1.203   msaitoh int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
    158  1.420   msaitoh     | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT | WM_DEBUG_LOCK;
    159    1.1   thorpej 
    160    1.1   thorpej #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
    161    1.1   thorpej #else
    162    1.1   thorpej #define	DPRINTF(x, y)	/* nothing */
    163    1.1   thorpej #endif /* WM_DEBUG */
    164    1.1   thorpej 
    165  1.272     ozaki #ifdef NET_MPSAFE
    166  1.272     ozaki #define WM_MPSAFE	1
    167  1.492  knakahar #define CALLOUT_FLAGS	CALLOUT_MPSAFE
    168  1.492  knakahar #else
    169  1.492  knakahar #define CALLOUT_FLAGS	0
    170  1.272     ozaki #endif
    171  1.272     ozaki 
    172  1.335   msaitoh /*
    173  1.364  knakahar  * This device driver's max interrupt numbers.
    174  1.335   msaitoh  */
    175  1.405  knakahar #define WM_MAX_NQUEUEINTR	16
    176  1.405  knakahar #define WM_MAX_NINTR		(WM_MAX_NQUEUEINTR + 1)
    177  1.335   msaitoh 
    178  1.508  knakahar #ifndef WM_DISABLE_MSI
    179  1.508  knakahar #define	WM_DISABLE_MSI 0
    180  1.508  knakahar #endif
    181  1.508  knakahar #ifndef WM_DISABLE_MSIX
    182  1.508  knakahar #define	WM_DISABLE_MSIX 0
    183  1.508  knakahar #endif
    184  1.508  knakahar 
    185  1.508  knakahar int wm_disable_msi = WM_DISABLE_MSI;
    186  1.508  knakahar int wm_disable_msix = WM_DISABLE_MSIX;
    187  1.508  knakahar 
    188  1.562  knakahar #ifndef WM_WATCHDOG_TIMEOUT
    189  1.562  knakahar #define WM_WATCHDOG_TIMEOUT 5
    190  1.562  knakahar #endif
    191  1.562  knakahar static int wm_watchdog_timeout = WM_WATCHDOG_TIMEOUT;
    192  1.562  knakahar 
    193    1.1   thorpej /*
    194    1.2   thorpej  * Transmit descriptor list size.  Due to errata, we can only have
    195   1.75   thorpej  * 256 hardware descriptors in the ring on < 82544, but we use 4096
    196   1.75   thorpej  * on >= 82544.  We tell the upper layers that they can queue a lot
    197   1.75   thorpej  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
    198   1.75   thorpej  * of them at a time.
    199   1.75   thorpej  *
    200   1.75   thorpej  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
    201   1.75   thorpej  * chains containing many small mbufs have been observed in zero-copy
    202   1.75   thorpej  * situations with jumbo frames.
    203    1.1   thorpej  */
    204   1.75   thorpej #define	WM_NTXSEGS		256
    205    1.2   thorpej #define	WM_IFQUEUELEN		256
    206   1.74      tron #define	WM_TXQUEUELEN_MAX	64
    207   1.74      tron #define	WM_TXQUEUELEN_MAX_82547	16
    208  1.356  knakahar #define	WM_TXQUEUELEN(txq)	((txq)->txq_num)
    209  1.356  knakahar #define	WM_TXQUEUELEN_MASK(txq)	(WM_TXQUEUELEN(txq) - 1)
    210  1.356  knakahar #define	WM_TXQUEUE_GC(txq)	(WM_TXQUEUELEN(txq) / 8)
    211   1.75   thorpej #define	WM_NTXDESC_82542	256
    212   1.75   thorpej #define	WM_NTXDESC_82544	4096
    213  1.356  knakahar #define	WM_NTXDESC(txq)		((txq)->txq_ndesc)
    214  1.356  knakahar #define	WM_NTXDESC_MASK(txq)	(WM_NTXDESC(txq) - 1)
    215  1.398  knakahar #define	WM_TXDESCS_SIZE(txq)	(WM_NTXDESC(txq) * (txq)->txq_descsize)
    216  1.356  knakahar #define	WM_NEXTTX(txq, x)	(((x) + 1) & WM_NTXDESC_MASK(txq))
    217  1.356  knakahar #define	WM_NEXTTXS(txq, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(txq))
    218    1.1   thorpej 
    219  1.269       tls #define	WM_MAXTXDMA		 (2 * round_page(IP_MAXPACKET)) /* for TSO */
    220   1.82   thorpej 
    221  1.403  knakahar #define	WM_TXINTERQSIZE		256
    222  1.403  knakahar 
    223  1.557  knakahar #ifndef WM_TX_PROCESS_LIMIT_DEFAULT
    224  1.557  knakahar #define	WM_TX_PROCESS_LIMIT_DEFAULT		100U
    225  1.557  knakahar #endif
    226  1.557  knakahar #ifndef WM_TX_INTR_PROCESS_LIMIT_DEFAULT
    227  1.557  knakahar #define	WM_TX_INTR_PROCESS_LIMIT_DEFAULT	0U
    228  1.557  knakahar #endif
    229  1.557  knakahar 
    230    1.1   thorpej /*
    231    1.1   thorpej  * Receive descriptor list size.  We have one Rx buffer for normal
    232    1.1   thorpej  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
    233   1.10   thorpej  * packet.  We allocate 256 receive descriptors, each with a 2k
    234   1.10   thorpej  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
    235    1.1   thorpej  */
    236   1.10   thorpej #define	WM_NRXDESC		256
    237    1.1   thorpej #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
    238    1.1   thorpej #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
    239    1.1   thorpej #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
    240    1.1   thorpej 
    241  1.494  knakahar #ifndef WM_RX_PROCESS_LIMIT_DEFAULT
    242  1.493  knakahar #define	WM_RX_PROCESS_LIMIT_DEFAULT		100U
    243  1.494  knakahar #endif
    244  1.494  knakahar #ifndef WM_RX_INTR_PROCESS_LIMIT_DEFAULT
    245  1.493  knakahar #define	WM_RX_INTR_PROCESS_LIMIT_DEFAULT	0U
    246  1.494  knakahar #endif
    247  1.493  knakahar 
    248  1.354  knakahar typedef union txdescs {
    249  1.354  knakahar 	wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544];
    250  1.354  knakahar 	nq_txdesc_t      sctxu_nq_txdescs[WM_NTXDESC_82544];
    251  1.354  knakahar } txdescs_t;
    252    1.1   thorpej 
    253  1.466  knakahar typedef union rxdescs {
    254  1.466  knakahar 	wiseman_rxdesc_t sctxu_rxdescs[WM_NRXDESC];
    255  1.466  knakahar 	ext_rxdesc_t      sctxu_ext_rxdescs[WM_NRXDESC]; /* 82574 only */
    256  1.466  knakahar 	nq_rxdesc_t      sctxu_nq_rxdescs[WM_NRXDESC]; /* 82575 and newer */
    257  1.466  knakahar } rxdescs_t;
    258  1.466  knakahar 
    259  1.398  knakahar #define	WM_CDTXOFF(txq, x)	((txq)->txq_descsize * (x))
    260  1.466  knakahar #define	WM_CDRXOFF(rxq, x)	((rxq)->rxq_descsize * (x))
    261    1.1   thorpej 
    262    1.1   thorpej /*
    263    1.1   thorpej  * Software state for transmit jobs.
    264    1.1   thorpej  */
    265    1.1   thorpej struct wm_txsoft {
    266    1.1   thorpej 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
    267    1.1   thorpej 	bus_dmamap_t txs_dmamap;	/* our DMA map */
    268    1.1   thorpej 	int txs_firstdesc;		/* first descriptor in packet */
    269    1.1   thorpej 	int txs_lastdesc;		/* last descriptor in packet */
    270    1.4   thorpej 	int txs_ndesc;			/* # of descriptors used */
    271    1.1   thorpej };
    272    1.1   thorpej 
    273    1.1   thorpej /*
    274    1.1   thorpej  * Software state for receive buffers.  Each descriptor gets a
    275    1.1   thorpej  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
    276    1.1   thorpej  * more than one buffer, we chain them together.
    277    1.1   thorpej  */
    278    1.1   thorpej struct wm_rxsoft {
    279    1.1   thorpej 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
    280    1.1   thorpej 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
    281    1.1   thorpej };
    282    1.1   thorpej 
    283  1.173   msaitoh #define WM_LINKUP_TIMEOUT	50
    284  1.173   msaitoh 
    285  1.199   msaitoh static uint16_t swfwphysem[] = {
    286  1.199   msaitoh 	SWFW_PHY0_SM,
    287  1.199   msaitoh 	SWFW_PHY1_SM,
    288  1.199   msaitoh 	SWFW_PHY2_SM,
    289  1.199   msaitoh 	SWFW_PHY3_SM
    290  1.199   msaitoh };
    291  1.199   msaitoh 
    292  1.320   msaitoh static const uint32_t wm_82580_rxpbs_table[] = {
    293  1.320   msaitoh 	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
    294  1.320   msaitoh };
    295  1.320   msaitoh 
    296  1.356  knakahar struct wm_softc;
    297  1.356  knakahar 
    298  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    299  1.417  knakahar #define WM_Q_EVCNT_DEFINE(qname, evname)				\
    300  1.417  knakahar 	char qname##_##evname##_evcnt_name[sizeof("qname##XX##evname")]; \
    301  1.417  knakahar 	struct evcnt qname##_ev_##evname;
    302  1.417  knakahar 
    303  1.417  knakahar #define WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, evtype)	\
    304  1.417  knakahar 	do{								\
    305  1.417  knakahar 		snprintf((q)->qname##_##evname##_evcnt_name,		\
    306  1.417  knakahar 		    sizeof((q)->qname##_##evname##_evcnt_name),		\
    307  1.417  knakahar 		    "%s%02d%s", #qname, (qnum), #evname);		\
    308  1.417  knakahar 		evcnt_attach_dynamic(&(q)->qname##_ev_##evname,		\
    309  1.417  knakahar 		    (evtype), NULL, (xname),				\
    310  1.417  knakahar 		    (q)->qname##_##evname##_evcnt_name);		\
    311  1.417  knakahar 	}while(0)
    312  1.417  knakahar 
    313  1.417  knakahar #define WM_Q_MISC_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
    314  1.417  knakahar 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_MISC)
    315  1.417  knakahar 
    316  1.417  knakahar #define WM_Q_INTR_EVCNT_ATTACH(qname, evname, q, qnum, xname)		\
    317  1.417  knakahar 	WM_Q_EVCNT_ATTACH(qname, evname, q, qnum, xname, EVCNT_TYPE_INTR)
    318  1.477  knakahar 
    319  1.477  knakahar #define WM_Q_EVCNT_DETACH(qname, evname, q, qnum)	\
    320  1.477  knakahar 	evcnt_detach(&(q)->qname##_ev_##evname);
    321  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
    322  1.417  knakahar 
    323  1.356  knakahar struct wm_txqueue {
    324  1.357  knakahar 	kmutex_t *txq_lock;		/* lock for tx operations */
    325  1.356  knakahar 
    326  1.405  knakahar 	struct wm_softc *txq_sc;	/* shortcut (skip struct wm_queue) */
    327  1.364  knakahar 
    328  1.356  knakahar 	/* Software state for the transmit descriptors. */
    329  1.356  knakahar 	int txq_num;			/* must be a power of two */
    330  1.356  knakahar 	struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX];
    331  1.356  knakahar 
    332  1.356  knakahar 	/* TX control data structures. */
    333  1.356  knakahar 	int txq_ndesc;			/* must be a power of two */
    334  1.398  knakahar 	size_t txq_descsize;		/* a tx descriptor size */
    335  1.356  knakahar 	txdescs_t *txq_descs_u;
    336  1.356  knakahar         bus_dmamap_t txq_desc_dmamap;	/* control data DMA map */
    337  1.356  knakahar 	bus_dma_segment_t txq_desc_seg;	/* control data segment */
    338  1.356  knakahar 	int txq_desc_rseg;		/* real number of control segment */
    339  1.356  knakahar #define	txq_desc_dma	txq_desc_dmamap->dm_segs[0].ds_addr
    340  1.356  knakahar #define	txq_descs	txq_descs_u->sctxu_txdescs
    341  1.356  knakahar #define	txq_nq_descs	txq_descs_u->sctxu_nq_txdescs
    342  1.356  knakahar 
    343  1.356  knakahar 	bus_addr_t txq_tdt_reg;		/* offset of TDT register */
    344  1.356  knakahar 
    345  1.356  knakahar 	int txq_free;			/* number of free Tx descriptors */
    346  1.356  knakahar 	int txq_next;			/* next ready Tx descriptor */
    347  1.356  knakahar 
    348  1.356  knakahar 	int txq_sfree;			/* number of free Tx jobs */
    349  1.356  knakahar 	int txq_snext;			/* next free Tx job */
    350  1.356  knakahar 	int txq_sdirty;			/* dirty Tx jobs */
    351  1.356  knakahar 
    352  1.356  knakahar 	/* These 4 variables are used only on the 82547. */
    353  1.356  knakahar 	int txq_fifo_size;		/* Tx FIFO size */
    354  1.356  knakahar 	int txq_fifo_head;		/* current head of FIFO */
    355  1.356  knakahar 	uint32_t txq_fifo_addr;		/* internal address of start of FIFO */
    356  1.356  knakahar 	int txq_fifo_stall;		/* Tx FIFO is stalled */
    357  1.356  knakahar 
    358  1.400  knakahar 	/*
    359  1.403  knakahar 	 * When ncpu > number of Tx queues, a Tx queue is shared by multiple
    360  1.403  knakahar 	 * CPUs. This queue intermediate them without block.
    361  1.403  knakahar 	 */
    362  1.403  knakahar 	pcq_t *txq_interq;
    363  1.403  knakahar 
    364  1.403  knakahar 	/*
    365  1.400  knakahar 	 * NEWQUEUE devices must use not ifp->if_flags but txq->txq_flags
    366  1.400  knakahar 	 * to manage Tx H/W queue's busy flag.
    367  1.400  knakahar 	 */
    368  1.400  knakahar 	int txq_flags;			/* flags for H/W queue, see below */
    369  1.401  knakahar #define	WM_TXQ_NO_SPACE	0x1
    370  1.400  knakahar 
    371  1.429  knakahar 	bool txq_stopping;
    372  1.429  knakahar 
    373  1.576   msaitoh 	bool txq_sending;
    374  1.562  knakahar 	time_t txq_lastsent;
    375  1.562  knakahar 
    376  1.495  knakahar 	uint32_t txq_packets;		/* for AIM */
    377  1.495  knakahar 	uint32_t txq_bytes;		/* for AIM */
    378  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    379  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txsstall)	/* Tx stalled due to no txs */
    380  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdstall)	/* Tx stalled due to no txd */
    381  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txfifo_stall)	/* Tx FIFO stalls (82547) */
    382  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdw)		/* Tx descriptor interrupts */
    383  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txqe)		/* Tx queue empty interrupts */
    384  1.417  knakahar 						/* XXX not used? */
    385  1.417  knakahar 
    386  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txipsum)		/* IP checksums comp. out-bound */
    387  1.573   msaitoh 	WM_Q_EVCNT_DEFINE(txq, txtusum)		/* TCP/UDP cksums comp. out-bound */
    388  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtusum6)	/* TCP/UDP v6 cksums comp. out-bound */
    389  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtso)		/* TCP seg offload out-bound (IPv4) */
    390  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtso6)		/* TCP seg offload out-bound (IPv6) */
    391  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txtsopain)	/* painful header manip. for TSO */
    392  1.417  knakahar 
    393  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, txdrop)		/* Tx packets dropped(too many segs) */
    394  1.417  knakahar 
    395  1.417  knakahar 	WM_Q_EVCNT_DEFINE(txq, tu)		/* Tx underrun */
    396  1.417  knakahar 
    397  1.417  knakahar 	char txq_txseg_evcnt_names[WM_NTXSEGS][sizeof("txqXXtxsegXXX")];
    398  1.417  knakahar 	struct evcnt txq_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
    399  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
    400  1.356  knakahar };
    401  1.356  knakahar 
    402  1.356  knakahar struct wm_rxqueue {
    403  1.357  knakahar 	kmutex_t *rxq_lock;		/* lock for rx operations */
    404  1.356  knakahar 
    405  1.405  knakahar 	struct wm_softc *rxq_sc;	/* shortcut (skip struct wm_queue) */
    406  1.364  knakahar 
    407  1.356  knakahar 	/* Software state for the receive descriptors. */
    408  1.466  knakahar 	struct wm_rxsoft rxq_soft[WM_NRXDESC];
    409  1.356  knakahar 
    410  1.356  knakahar 	/* RX control data structures. */
    411  1.466  knakahar 	int rxq_ndesc;			/* must be a power of two */
    412  1.466  knakahar 	size_t rxq_descsize;		/* a rx descriptor size */
    413  1.466  knakahar 	rxdescs_t *rxq_descs_u;
    414  1.356  knakahar 	bus_dmamap_t rxq_desc_dmamap;	/* control data DMA map */
    415  1.356  knakahar 	bus_dma_segment_t rxq_desc_seg;	/* control data segment */
    416  1.356  knakahar 	int rxq_desc_rseg;		/* real number of control segment */
    417  1.356  knakahar #define	rxq_desc_dma	rxq_desc_dmamap->dm_segs[0].ds_addr
    418  1.466  knakahar #define	rxq_descs	rxq_descs_u->sctxu_rxdescs
    419  1.466  knakahar #define	rxq_ext_descs	rxq_descs_u->sctxu_ext_rxdescs
    420  1.466  knakahar #define	rxq_nq_descs	rxq_descs_u->sctxu_nq_rxdescs
    421  1.356  knakahar 
    422  1.356  knakahar 	bus_addr_t rxq_rdt_reg;		/* offset of RDT register */
    423  1.356  knakahar 
    424  1.388   msaitoh 	int rxq_ptr;			/* next ready Rx desc/queue ent */
    425  1.356  knakahar 	int rxq_discard;
    426  1.356  knakahar 	int rxq_len;
    427  1.356  knakahar 	struct mbuf *rxq_head;
    428  1.356  knakahar 	struct mbuf *rxq_tail;
    429  1.356  knakahar 	struct mbuf **rxq_tailp;
    430  1.356  knakahar 
    431  1.429  knakahar 	bool rxq_stopping;
    432  1.429  knakahar 
    433  1.495  knakahar 	uint32_t rxq_packets;		/* for AIM */
    434  1.495  knakahar 	uint32_t rxq_bytes;		/* for AIM */
    435  1.417  knakahar #ifdef WM_EVENT_COUNTERS
    436  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxintr);		/* Rx interrupts */
    437  1.556  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxdefer);	/* Rx deferred processing */
    438  1.417  knakahar 
    439  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxipsum);	/* IP checksums checked in-bound */
    440  1.417  knakahar 	WM_Q_EVCNT_DEFINE(rxq, rxtusum);	/* TCP/UDP cksums checked in-bound */
    441  1.417  knakahar #endif
    442  1.356  knakahar };
    443  1.356  knakahar 
    444  1.405  knakahar struct wm_queue {
    445  1.573   msaitoh 	int wmq_id;			/* index of TX/RX queues */
    446  1.405  knakahar 	int wmq_intr_idx;		/* index of MSI-X tables */
    447  1.405  knakahar 
    448  1.490  knakahar 	uint32_t wmq_itr;		/* interrupt interval per queue. */
    449  1.495  knakahar 	bool wmq_set_itr;
    450  1.490  knakahar 
    451  1.405  knakahar 	struct wm_txqueue wmq_txq;
    452  1.405  knakahar 	struct wm_rxqueue wmq_rxq;
    453  1.484  knakahar 
    454  1.484  knakahar 	void *wmq_si;
    455  1.405  knakahar };
    456  1.405  knakahar 
    457  1.424   msaitoh struct wm_phyop {
    458  1.424   msaitoh 	int (*acquire)(struct wm_softc *);
    459  1.424   msaitoh 	void (*release)(struct wm_softc *);
    460  1.447   msaitoh 	int reset_delay_us;
    461  1.424   msaitoh };
    462  1.424   msaitoh 
    463  1.530   msaitoh struct wm_nvmop {
    464  1.530   msaitoh 	int (*acquire)(struct wm_softc *);
    465  1.530   msaitoh 	void (*release)(struct wm_softc *);
    466  1.530   msaitoh 	int (*read)(struct wm_softc *, int, int, uint16_t *);
    467  1.530   msaitoh };
    468  1.530   msaitoh 
    469    1.1   thorpej /*
    470    1.1   thorpej  * Software state per device.
    471    1.1   thorpej  */
    472    1.1   thorpej struct wm_softc {
    473  1.160  christos 	device_t sc_dev;		/* generic device information */
    474    1.1   thorpej 	bus_space_tag_t sc_st;		/* bus space tag */
    475    1.1   thorpej 	bus_space_handle_t sc_sh;	/* bus space handle */
    476  1.204   msaitoh 	bus_size_t sc_ss;		/* bus space size */
    477   1.53   thorpej 	bus_space_tag_t sc_iot;		/* I/O space tag */
    478   1.53   thorpej 	bus_space_handle_t sc_ioh;	/* I/O space handle */
    479  1.212  jakllsch 	bus_size_t sc_ios;		/* I/O space size */
    480  1.139    bouyer 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
    481  1.139    bouyer 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
    482  1.336   msaitoh 	bus_size_t sc_flashs;		/* flash registers space size */
    483  1.392   msaitoh 	off_t sc_flashreg_offset;	/*
    484  1.392   msaitoh 					 * offset to flash registers from
    485  1.392   msaitoh 					 * start of BAR
    486  1.392   msaitoh 					 */
    487    1.1   thorpej 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
    488  1.199   msaitoh 
    489    1.1   thorpej 	struct ethercom sc_ethercom;	/* ethernet common data */
    490  1.199   msaitoh 	struct mii_data sc_mii;		/* MII/media information */
    491  1.199   msaitoh 
    492  1.123  jmcneill 	pci_chipset_tag_t sc_pc;
    493  1.123  jmcneill 	pcitag_t sc_pcitag;
    494  1.199   msaitoh 	int sc_bus_speed;		/* PCI/PCIX bus speed */
    495  1.281   msaitoh 	int sc_pcixe_capoff;		/* PCI[Xe] capability reg offset */
    496    1.1   thorpej 
    497  1.304   msaitoh 	uint16_t sc_pcidevid;		/* PCI device ID */
    498  1.192   msaitoh 	wm_chip_type sc_type;		/* MAC type */
    499  1.192   msaitoh 	int sc_rev;			/* MAC revision */
    500  1.192   msaitoh 	wm_phy_type sc_phytype;		/* PHY type */
    501  1.292   msaitoh 	uint32_t sc_mediatype;		/* Media type (Copper, Fiber, SERDES)*/
    502  1.311   msaitoh #define	WM_MEDIATYPE_UNKNOWN		0x00
    503  1.311   msaitoh #define	WM_MEDIATYPE_FIBER		0x01
    504  1.311   msaitoh #define	WM_MEDIATYPE_COPPER		0x02
    505  1.311   msaitoh #define	WM_MEDIATYPE_SERDES		0x03 /* Internal SERDES */
    506  1.199   msaitoh 	int sc_funcid;			/* unit number of the chip (0 to 3) */
    507    1.1   thorpej 	int sc_flags;			/* flags; see below */
    508  1.179   msaitoh 	int sc_if_flags;		/* last if_flags */
    509   1.71   thorpej 	int sc_flowflags;		/* 802.3x flow control flags */
    510  1.199   msaitoh 	int sc_align_tweak;
    511    1.1   thorpej 
    512  1.335   msaitoh 	void *sc_ihs[WM_MAX_NINTR];	/*
    513  1.335   msaitoh 					 * interrupt cookie.
    514  1.507  knakahar 					 * - legacy and msi use sc_ihs[0] only
    515  1.507  knakahar 					 * - msix use sc_ihs[0] to sc_ihs[nintrs-1]
    516  1.507  knakahar 					 */
    517  1.507  knakahar 	pci_intr_handle_t *sc_intrs;	/*
    518  1.507  knakahar 					 * legacy and msi use sc_intrs[0] only
    519  1.507  knakahar 					 * msix use sc_intrs[0] to sc_ihs[nintrs-1]
    520  1.335   msaitoh 					 */
    521  1.335   msaitoh 	int sc_nintrs;			/* number of interrupts */
    522  1.335   msaitoh 
    523  1.364  knakahar 	int sc_link_intr_idx;		/* index of MSI-X tables */
    524  1.364  knakahar 
    525  1.199   msaitoh 	callout_t sc_tick_ch;		/* tick callout */
    526  1.429  knakahar 	bool sc_core_stopping;
    527    1.1   thorpej 
    528  1.328   msaitoh 	int sc_nvm_ver_major;
    529  1.328   msaitoh 	int sc_nvm_ver_minor;
    530  1.350   msaitoh 	int sc_nvm_ver_build;
    531  1.294   msaitoh 	int sc_nvm_addrbits;		/* NVM address bits */
    532  1.328   msaitoh 	unsigned int sc_nvm_wordsize;	/* NVM word size */
    533  1.199   msaitoh 	int sc_ich8_flash_base;
    534  1.199   msaitoh 	int sc_ich8_flash_bank_size;
    535  1.199   msaitoh 	int sc_nvm_k1_enabled;
    536   1.42   thorpej 
    537  1.405  knakahar 	int sc_nqueues;
    538  1.405  knakahar 	struct wm_queue *sc_queue;
    539  1.557  knakahar 	u_int sc_tx_process_limit;	/* Tx processing repeat limit in softint */
    540  1.557  knakahar 	u_int sc_tx_intr_process_limit;	/* Tx processing repeat limit in H/W intr */
    541  1.493  knakahar 	u_int sc_rx_process_limit;	/* Rx processing repeat limit in softint */
    542  1.493  knakahar 	u_int sc_rx_intr_process_limit;	/* Rx processing repeat limit in H/W intr */
    543    1.1   thorpej 
    544  1.404  knakahar 	int sc_affinity_offset;
    545  1.404  knakahar 
    546    1.1   thorpej #ifdef WM_EVENT_COUNTERS
    547    1.1   thorpej 	/* Event counters. */
    548    1.1   thorpej 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
    549    1.1   thorpej 
    550  1.417  knakahar         /* WM_T_82542_2_1 only */
    551   1.71   thorpej 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
    552   1.71   thorpej 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
    553   1.71   thorpej 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
    554   1.71   thorpej 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
    555   1.71   thorpej 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
    556    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
    557    1.1   thorpej 
    558  1.356  knakahar 	/* This variable are used only on the 82547. */
    559  1.142        ad 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
    560   1.78   thorpej 
    561    1.1   thorpej 	uint32_t sc_ctrl;		/* prototype CTRL register */
    562    1.1   thorpej #if 0
    563    1.1   thorpej 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
    564    1.1   thorpej #endif
    565    1.1   thorpej 	uint32_t sc_icr;		/* prototype interrupt bits */
    566  1.490  knakahar 	uint32_t sc_itr_init;		/* prototype intr throttling reg */
    567    1.1   thorpej 	uint32_t sc_tctl;		/* prototype TCTL register */
    568    1.1   thorpej 	uint32_t sc_rctl;		/* prototype RCTL register */
    569    1.1   thorpej 	uint32_t sc_txcw;		/* prototype TXCW register */
    570    1.1   thorpej 	uint32_t sc_tipg;		/* prototype TIPG register */
    571   1.71   thorpej 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
    572   1.78   thorpej 	uint32_t sc_pba;		/* prototype PBA register */
    573    1.1   thorpej 
    574    1.1   thorpej 	int sc_tbi_linkup;		/* TBI link status */
    575  1.325   msaitoh 	int sc_tbi_serdes_anegticks;	/* autonegotiation ticks */
    576  1.325   msaitoh 	int sc_tbi_serdes_ticks;	/* tbi ticks */
    577    1.1   thorpej 
    578    1.1   thorpej 	int sc_mchash_type;		/* multicast filter offset */
    579   1.21    itojun 
    580  1.224       tls 	krndsource_t rnd_source;	/* random source */
    581  1.272     ozaki 
    582  1.424   msaitoh 	struct if_percpuq *sc_ipq;	/* softint-based input queues */
    583  1.424   msaitoh 
    584  1.357  knakahar 	kmutex_t *sc_core_lock;		/* lock for softc operations */
    585  1.424   msaitoh 	kmutex_t *sc_ich_phymtx;	/*
    586  1.424   msaitoh 					 * 82574/82583/ICH/PCH specific PHY
    587  1.424   msaitoh 					 * mutex. For 82574/82583, the mutex
    588  1.424   msaitoh 					 * is used for both PHY and NVM.
    589  1.424   msaitoh 					 */
    590  1.423   msaitoh 	kmutex_t *sc_ich_nvmmtx;	/* ICH/PCH specific NVM mutex */
    591  1.391     ozaki 
    592  1.424   msaitoh 	struct wm_phyop phy;
    593  1.530   msaitoh 	struct wm_nvmop nvm;
    594    1.1   thorpej };
    595    1.1   thorpej 
    596  1.357  knakahar #define WM_CORE_LOCK(_sc)	if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
    597  1.357  knakahar #define WM_CORE_UNLOCK(_sc)	if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
    598  1.357  knakahar #define WM_CORE_LOCKED(_sc)	(!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
    599  1.272     ozaki 
    600  1.356  knakahar #define	WM_RXCHAIN_RESET(rxq)						\
    601    1.1   thorpej do {									\
    602  1.356  knakahar 	(rxq)->rxq_tailp = &(rxq)->rxq_head;				\
    603  1.356  knakahar 	*(rxq)->rxq_tailp = NULL;					\
    604  1.356  knakahar 	(rxq)->rxq_len = 0;						\
    605    1.1   thorpej } while (/*CONSTCOND*/0)
    606    1.1   thorpej 
    607  1.356  knakahar #define	WM_RXCHAIN_LINK(rxq, m)						\
    608    1.1   thorpej do {									\
    609  1.356  knakahar 	*(rxq)->rxq_tailp = (rxq)->rxq_tail = (m);			\
    610  1.356  knakahar 	(rxq)->rxq_tailp = &(m)->m_next;				\
    611    1.1   thorpej } while (/*CONSTCOND*/0)
    612    1.1   thorpej 
    613    1.1   thorpej #ifdef WM_EVENT_COUNTERS
    614    1.1   thorpej #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
    615   1.71   thorpej #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
    616  1.417  knakahar 
    617  1.417  knakahar #define WM_Q_EVCNT_INCR(qname, evname)			\
    618  1.417  knakahar 	WM_EVCNT_INCR(&(qname)->qname##_ev_##evname)
    619  1.417  knakahar #define WM_Q_EVCNT_ADD(qname, evname, val)		\
    620  1.417  knakahar 	WM_EVCNT_ADD(&(qname)->qname##_ev_##evname, (val))
    621  1.417  knakahar #else /* !WM_EVENT_COUNTERS */
    622    1.1   thorpej #define	WM_EVCNT_INCR(ev)	/* nothing */
    623   1.71   thorpej #define	WM_EVCNT_ADD(ev, val)	/* nothing */
    624  1.417  knakahar 
    625  1.417  knakahar #define WM_Q_EVCNT_INCR(qname, evname)		/* nothing */
    626  1.417  knakahar #define WM_Q_EVCNT_ADD(qname, evname, val)	/* nothing */
    627  1.417  knakahar #endif /* !WM_EVENT_COUNTERS */
    628    1.1   thorpej 
    629    1.1   thorpej #define	CSR_READ(sc, reg)						\
    630    1.1   thorpej 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
    631    1.1   thorpej #define	CSR_WRITE(sc, reg, val)						\
    632    1.1   thorpej 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
    633   1.78   thorpej #define	CSR_WRITE_FLUSH(sc)						\
    634   1.78   thorpej 	(void) CSR_READ((sc), WMREG_STATUS)
    635    1.1   thorpej 
    636  1.392   msaitoh #define ICH8_FLASH_READ32(sc, reg)					\
    637  1.392   msaitoh 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh,		\
    638  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset)
    639  1.392   msaitoh #define ICH8_FLASH_WRITE32(sc, reg, data)				\
    640  1.392   msaitoh 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh,		\
    641  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset, (data))
    642  1.392   msaitoh 
    643  1.392   msaitoh #define ICH8_FLASH_READ16(sc, reg)					\
    644  1.392   msaitoh 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh,		\
    645  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset)
    646  1.392   msaitoh #define ICH8_FLASH_WRITE16(sc, reg, data)				\
    647  1.392   msaitoh 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh,		\
    648  1.392   msaitoh 	    (reg) + sc->sc_flashreg_offset, (data))
    649  1.139    bouyer 
    650  1.398  knakahar #define	WM_CDTXADDR(txq, x)	((txq)->txq_desc_dma + WM_CDTXOFF((txq), (x)))
    651  1.466  knakahar #define	WM_CDRXADDR(rxq, x)	((rxq)->rxq_desc_dma + WM_CDRXOFF((rxq), (x)))
    652    1.1   thorpej 
    653  1.356  knakahar #define	WM_CDTXADDR_LO(txq, x)	(WM_CDTXADDR((txq), (x)) & 0xffffffffU)
    654  1.356  knakahar #define	WM_CDTXADDR_HI(txq, x)						\
    655   1.69   thorpej 	(sizeof(bus_addr_t) == 8 ?					\
    656  1.356  knakahar 	 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0)
    657   1.69   thorpej 
    658  1.356  knakahar #define	WM_CDRXADDR_LO(rxq, x)	(WM_CDRXADDR((rxq), (x)) & 0xffffffffU)
    659  1.356  knakahar #define	WM_CDRXADDR_HI(rxq, x)						\
    660   1.69   thorpej 	(sizeof(bus_addr_t) == 8 ?					\
    661  1.356  knakahar 	 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0)
    662   1.69   thorpej 
    663  1.280   msaitoh /*
    664  1.280   msaitoh  * Register read/write functions.
    665  1.280   msaitoh  * Other than CSR_{READ|WRITE}().
    666  1.280   msaitoh  */
    667  1.280   msaitoh #if 0
    668  1.280   msaitoh static inline uint32_t wm_io_read(struct wm_softc *, int);
    669  1.280   msaitoh #endif
    670  1.280   msaitoh static inline void wm_io_write(struct wm_softc *, int, uint32_t);
    671  1.280   msaitoh static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t,
    672  1.280   msaitoh 	uint32_t, uint32_t);
    673  1.280   msaitoh static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t);
    674  1.280   msaitoh 
    675  1.280   msaitoh /*
    676  1.352  knakahar  * Descriptor sync/init functions.
    677  1.352  knakahar  */
    678  1.362  knakahar static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int);
    679  1.362  knakahar static inline void wm_cdrxsync(struct wm_rxqueue *, int, int);
    680  1.362  knakahar static inline void wm_init_rxdesc(struct wm_rxqueue *, int);
    681  1.352  knakahar 
    682  1.352  knakahar /*
    683  1.280   msaitoh  * Device driver interface functions and commonly used functions.
    684  1.280   msaitoh  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
    685  1.280   msaitoh  */
    686  1.280   msaitoh static const struct wm_product *wm_lookup(const struct pci_attach_args *);
    687  1.280   msaitoh static int	wm_match(device_t, cfdata_t, void *);
    688  1.280   msaitoh static void	wm_attach(device_t, device_t, void *);
    689  1.280   msaitoh static int	wm_detach(device_t, int);
    690  1.280   msaitoh static bool	wm_suspend(device_t, const pmf_qual_t *);
    691  1.280   msaitoh static bool	wm_resume(device_t, const pmf_qual_t *);
    692   1.47   thorpej static void	wm_watchdog(struct ifnet *);
    693  1.573   msaitoh static void	wm_watchdog_txq(struct ifnet *, struct wm_txqueue *,
    694  1.573   msaitoh     uint16_t *);
    695  1.573   msaitoh static void	wm_watchdog_txq_locked(struct ifnet *, struct wm_txqueue *,
    696  1.573   msaitoh     uint16_t *);
    697  1.280   msaitoh static void	wm_tick(void *);
    698  1.213   msaitoh static int	wm_ifflags_cb(struct ethercom *);
    699  1.135  christos static int	wm_ioctl(struct ifnet *, u_long, void *);
    700  1.280   msaitoh /* MAC address related */
    701  1.306   msaitoh static uint16_t	wm_check_alt_mac_addr(struct wm_softc *);
    702  1.280   msaitoh static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
    703  1.280   msaitoh static void	wm_set_ral(struct wm_softc *, const uint8_t *, int);
    704  1.280   msaitoh static uint32_t	wm_mchash(struct wm_softc *, const uint8_t *);
    705  1.280   msaitoh static void	wm_set_filter(struct wm_softc *);
    706  1.280   msaitoh /* Reset and init related */
    707  1.280   msaitoh static void	wm_set_vlan(struct wm_softc *);
    708  1.280   msaitoh static void	wm_set_pcie_completion_timeout(struct wm_softc *);
    709  1.280   msaitoh static void	wm_get_auto_rd_done(struct wm_softc *);
    710  1.280   msaitoh static void	wm_lan_init_done(struct wm_softc *);
    711  1.280   msaitoh static void	wm_get_cfg_done(struct wm_softc *);
    712  1.517   msaitoh static void	wm_phy_post_reset(struct wm_softc *);
    713  1.528   msaitoh static void	wm_write_smbus_addr(struct wm_softc *);
    714  1.523   msaitoh static void	wm_init_lcd_from_nvm(struct wm_softc *);
    715  1.312   msaitoh static void	wm_initialize_hardware_bits(struct wm_softc *);
    716  1.320   msaitoh static uint32_t	wm_rxpbs_adjust_82580(uint32_t);
    717  1.447   msaitoh static void	wm_reset_phy(struct wm_softc *);
    718  1.443   msaitoh static void	wm_flush_desc_rings(struct wm_softc *);
    719  1.280   msaitoh static void	wm_reset(struct wm_softc *);
    720  1.362  knakahar static int	wm_add_rxbuf(struct wm_rxqueue *, int);
    721  1.362  knakahar static void	wm_rxdrain(struct wm_rxqueue *);
    722  1.365  knakahar static void	wm_init_rss(struct wm_softc *);
    723  1.371   msaitoh static void	wm_adjust_qnum(struct wm_softc *, int);
    724  1.502  knakahar static inline bool	wm_is_using_msix(struct wm_softc *);
    725  1.502  knakahar static inline bool	wm_is_using_multiqueue(struct wm_softc *);
    726  1.501  knakahar static int	wm_softint_establish(struct wm_softc *, int, int);
    727  1.371   msaitoh static int	wm_setup_legacy(struct wm_softc *);
    728  1.371   msaitoh static int	wm_setup_msix(struct wm_softc *);
    729   1.47   thorpej static int	wm_init(struct ifnet *);
    730  1.272     ozaki static int	wm_init_locked(struct ifnet *);
    731  1.537  knakahar static void	wm_unset_stopping_flags(struct wm_softc *);
    732  1.537  knakahar static void	wm_set_stopping_flags(struct wm_softc *);
    733   1.47   thorpej static void	wm_stop(struct ifnet *, int);
    734  1.272     ozaki static void	wm_stop_locked(struct ifnet *, int);
    735  1.280   msaitoh static void	wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *);
    736  1.280   msaitoh static void	wm_82547_txfifo_stall(void *);
    737  1.280   msaitoh static int	wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *);
    738  1.491  knakahar static void	wm_itrs_writereg(struct wm_softc *, struct wm_queue *);
    739  1.353  knakahar /* DMA related */
    740  1.362  knakahar static int	wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *);
    741  1.362  knakahar static void	wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *);
    742  1.362  knakahar static void	wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *);
    743  1.405  knakahar static void	wm_init_tx_regs(struct wm_softc *, struct wm_queue *,
    744  1.405  knakahar     struct wm_txqueue *);
    745  1.362  knakahar static int	wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *);
    746  1.362  knakahar static void	wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *);
    747  1.405  knakahar static void	wm_init_rx_regs(struct wm_softc *, struct wm_queue *,
    748  1.405  knakahar     struct wm_rxqueue *);
    749  1.362  knakahar static int	wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    750  1.362  knakahar static void	wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    751  1.362  knakahar static void	wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *);
    752  1.362  knakahar static int	wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    753  1.362  knakahar static void	wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    754  1.362  knakahar static int	wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *);
    755  1.405  knakahar static void	wm_init_tx_queue(struct wm_softc *, struct wm_queue *,
    756  1.405  knakahar     struct wm_txqueue *);
    757  1.405  knakahar static int	wm_init_rx_queue(struct wm_softc *, struct wm_queue *,
    758  1.405  knakahar     struct wm_rxqueue *);
    759  1.353  knakahar static int	wm_alloc_txrx_queues(struct wm_softc *);
    760  1.353  knakahar static void	wm_free_txrx_queues(struct wm_softc *);
    761  1.355  knakahar static int	wm_init_txrx_queues(struct wm_softc *);
    762  1.280   msaitoh /* Start */
    763  1.498  knakahar static int	wm_tx_offload(struct wm_softc *, struct wm_txqueue *,
    764  1.498  knakahar     struct wm_txsoft *, uint32_t *, uint8_t *);
    765  1.454  knakahar static inline int	wm_select_txqueue(struct ifnet *, struct mbuf *);
    766  1.280   msaitoh static void	wm_start(struct ifnet *);
    767  1.280   msaitoh static void	wm_start_locked(struct ifnet *);
    768  1.454  knakahar static int	wm_transmit(struct ifnet *, struct mbuf *);
    769  1.454  knakahar static void	wm_transmit_locked(struct ifnet *, struct wm_txqueue *);
    770  1.573   msaitoh static void	wm_send_common_locked(struct ifnet *, struct wm_txqueue *,
    771  1.573   msaitoh     bool);
    772  1.403  knakahar static int	wm_nq_tx_offload(struct wm_softc *, struct wm_txqueue *,
    773  1.403  knakahar     struct wm_txsoft *, uint32_t *, uint32_t *, bool *);
    774  1.280   msaitoh static void	wm_nq_start(struct ifnet *);
    775  1.280   msaitoh static void	wm_nq_start_locked(struct ifnet *);
    776  1.403  knakahar static int	wm_nq_transmit(struct ifnet *, struct mbuf *);
    777  1.403  knakahar static void	wm_nq_transmit_locked(struct ifnet *, struct wm_txqueue *);
    778  1.573   msaitoh static void	wm_nq_send_common_locked(struct ifnet *, struct wm_txqueue *,
    779  1.573   msaitoh     bool);
    780  1.481  knakahar static void	wm_deferred_start_locked(struct wm_txqueue *);
    781  1.484  knakahar static void	wm_handle_queue(void *);
    782  1.280   msaitoh /* Interrupt */
    783  1.563  knakahar static bool	wm_txeof(struct wm_txqueue *, u_int);
    784  1.563  knakahar static bool	wm_rxeof(struct wm_rxqueue *, u_int);
    785  1.280   msaitoh static void	wm_linkintr_gmii(struct wm_softc *, uint32_t);
    786  1.280   msaitoh static void	wm_linkintr_tbi(struct wm_softc *, uint32_t);
    787  1.325   msaitoh static void	wm_linkintr_serdes(struct wm_softc *, uint32_t);
    788   1.47   thorpej static void	wm_linkintr(struct wm_softc *, uint32_t);
    789  1.335   msaitoh static int	wm_intr_legacy(void *);
    790  1.480  knakahar static inline void	wm_txrxintr_disable(struct wm_queue *);
    791  1.480  knakahar static inline void	wm_txrxintr_enable(struct wm_queue *);
    792  1.495  knakahar static void	wm_itrs_calculate(struct wm_softc *, struct wm_queue *);
    793  1.405  knakahar static int	wm_txrxintr_msix(void *);
    794  1.335   msaitoh static int	wm_linkintr_msix(void *);
    795    1.1   thorpej 
    796  1.280   msaitoh /*
    797  1.280   msaitoh  * Media related.
    798  1.292   msaitoh  * GMII, SGMII, TBI, SERDES and SFP.
    799  1.280   msaitoh  */
    800  1.325   msaitoh /* Common */
    801  1.325   msaitoh static void	wm_tbi_serdes_set_linkled(struct wm_softc *);
    802  1.280   msaitoh /* GMII related */
    803   1.47   thorpej static void	wm_gmii_reset(struct wm_softc *);
    804  1.573   msaitoh static void	wm_gmii_setup_phytype(struct wm_softc *, uint32_t, uint16_t);
    805  1.280   msaitoh static int	wm_get_phy_id_82575(struct wm_softc *);
    806  1.280   msaitoh static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
    807  1.324   msaitoh static int	wm_gmii_mediachange(struct ifnet *);
    808  1.280   msaitoh static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
    809  1.280   msaitoh static void	wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int);
    810  1.280   msaitoh static uint32_t	wm_i82543_mii_recvbits(struct wm_softc *);
    811  1.157    dyoung static int	wm_gmii_i82543_readreg(device_t, int, int);
    812  1.157    dyoung static void	wm_gmii_i82543_writereg(device_t, int, int, int);
    813  1.424   msaitoh static int	wm_gmii_mdic_readreg(device_t, int, int);
    814  1.424   msaitoh static void	wm_gmii_mdic_writereg(device_t, int, int, int);
    815  1.157    dyoung static int	wm_gmii_i82544_readreg(device_t, int, int);
    816  1.157    dyoung static void	wm_gmii_i82544_writereg(device_t, int, int, int);
    817  1.157    dyoung static int	wm_gmii_i80003_readreg(device_t, int, int);
    818  1.157    dyoung static void	wm_gmii_i80003_writereg(device_t, int, int, int);
    819  1.167   msaitoh static int	wm_gmii_bm_readreg(device_t, int, int);
    820  1.167   msaitoh static void	wm_gmii_bm_writereg(device_t, int, int, int);
    821  1.280   msaitoh static void	wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int);
    822  1.192   msaitoh static int	wm_gmii_hv_readreg(device_t, int, int);
    823  1.424   msaitoh static int	wm_gmii_hv_readreg_locked(device_t, int, int);
    824  1.192   msaitoh static void	wm_gmii_hv_writereg(device_t, int, int, int);
    825  1.424   msaitoh static void	wm_gmii_hv_writereg_locked(device_t, int, int, int);
    826  1.243   msaitoh static int	wm_gmii_82580_readreg(device_t, int, int);
    827  1.243   msaitoh static void	wm_gmii_82580_writereg(device_t, int, int, int);
    828  1.329   msaitoh static int	wm_gmii_gs40g_readreg(device_t, int, int);
    829  1.329   msaitoh static void	wm_gmii_gs40g_writereg(device_t, int, int, int);
    830  1.280   msaitoh static void	wm_gmii_statchg(struct ifnet *);
    831  1.453   msaitoh /*
    832  1.453   msaitoh  * kumeran related (80003, ICH* and PCH*).
    833  1.453   msaitoh  * These functions are not for accessing MII registers but for accessing
    834  1.453   msaitoh  * kumeran specific registers.
    835  1.453   msaitoh  */
    836  1.531   msaitoh static int	wm_kmrn_readreg(struct wm_softc *, int, uint16_t *);
    837  1.531   msaitoh static int	wm_kmrn_readreg_locked(struct wm_softc *, int, uint16_t *);
    838  1.531   msaitoh static int	wm_kmrn_writereg(struct wm_softc *, int, uint16_t);
    839  1.531   msaitoh static int	wm_kmrn_writereg_locked(struct wm_softc *, int, uint16_t);
    840  1.280   msaitoh /* SGMII */
    841  1.265   msaitoh static bool	wm_sgmii_uses_mdio(struct wm_softc *);
    842  1.199   msaitoh static int	wm_sgmii_readreg(device_t, int, int);
    843  1.199   msaitoh static void	wm_sgmii_writereg(device_t, int, int, int);
    844  1.280   msaitoh /* TBI related */
    845  1.280   msaitoh static void	wm_tbi_mediainit(struct wm_softc *);
    846  1.324   msaitoh static int	wm_tbi_mediachange(struct ifnet *);
    847  1.280   msaitoh static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
    848  1.325   msaitoh static int	wm_check_for_link(struct wm_softc *);
    849  1.325   msaitoh static void	wm_tbi_tick(struct wm_softc *);
    850  1.325   msaitoh /* SERDES related */
    851  1.325   msaitoh static void	wm_serdes_power_up_link_82575(struct wm_softc *);
    852  1.325   msaitoh static int	wm_serdes_mediachange(struct ifnet *);
    853  1.325   msaitoh static void	wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *);
    854  1.325   msaitoh static void	wm_serdes_tick(struct wm_softc *);
    855  1.292   msaitoh /* SFP related */
    856  1.295   msaitoh static int	wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *);
    857  1.295   msaitoh static uint32_t	wm_sfp_get_media_type(struct wm_softc *);
    858  1.167   msaitoh 
    859  1.280   msaitoh /*
    860  1.280   msaitoh  * NVM related.
    861  1.280   msaitoh  * Microwire, SPI (w/wo EERD) and Flash.
    862  1.280   msaitoh  */
    863  1.294   msaitoh /* Misc functions */
    864  1.280   msaitoh static void	wm_eeprom_sendbits(struct wm_softc *, uint32_t, int);
    865  1.280   msaitoh static void	wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int);
    866  1.294   msaitoh static int	wm_nvm_set_addrbits_size_eecd(struct wm_softc *);
    867  1.280   msaitoh /* Microwire */
    868  1.280   msaitoh static int	wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *);
    869  1.280   msaitoh /* SPI */
    870  1.280   msaitoh static int	wm_nvm_ready_spi(struct wm_softc *);
    871  1.280   msaitoh static int	wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *);
    872  1.280   msaitoh /* Using with EERD */
    873  1.280   msaitoh static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
    874  1.280   msaitoh static int	wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *);
    875  1.280   msaitoh /* Flash */
    876  1.280   msaitoh static int	wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *,
    877  1.280   msaitoh     unsigned int *);
    878  1.280   msaitoh static int32_t	wm_ich8_cycle_init(struct wm_softc *);
    879  1.280   msaitoh static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
    880  1.280   msaitoh static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t,
    881  1.392   msaitoh 	uint32_t *);
    882  1.280   msaitoh static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
    883  1.280   msaitoh static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
    884  1.392   msaitoh static int32_t	wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *);
    885  1.280   msaitoh static int	wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
    886  1.392   msaitoh static int	wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *);
    887  1.321   msaitoh /* iNVM */
    888  1.321   msaitoh static int	wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
    889  1.321   msaitoh static int	wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
    890  1.327   msaitoh /* Lock, detecting NVM type, validate checksum and read */
    891  1.280   msaitoh static int	wm_nvm_is_onboard_eeprom(struct wm_softc *);
    892  1.565   msaitoh static int	wm_nvm_flash_presence_i210(struct wm_softc *);
    893  1.280   msaitoh static int	wm_nvm_validate_checksum(struct wm_softc *);
    894  1.347   msaitoh static void	wm_nvm_version_invm(struct wm_softc *);
    895  1.328   msaitoh static void	wm_nvm_version(struct wm_softc *);
    896  1.280   msaitoh static int	wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
    897    1.1   thorpej 
    898  1.280   msaitoh /*
    899  1.280   msaitoh  * Hardware semaphores.
    900  1.280   msaitoh  * Very complexed...
    901  1.280   msaitoh  */
    902  1.424   msaitoh static int	wm_get_null(struct wm_softc *);
    903  1.424   msaitoh static void	wm_put_null(struct wm_softc *);
    904  1.530   msaitoh static int	wm_get_eecd(struct wm_softc *);
    905  1.530   msaitoh static void	wm_put_eecd(struct wm_softc *);
    906  1.424   msaitoh static int	wm_get_swsm_semaphore(struct wm_softc *); /* 8257[123] */
    907  1.127    bouyer static void	wm_put_swsm_semaphore(struct wm_softc *);
    908  1.127    bouyer static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
    909  1.127    bouyer static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
    910  1.530   msaitoh static int	wm_get_nvm_80003(struct wm_softc *);
    911  1.530   msaitoh static void	wm_put_nvm_80003(struct wm_softc *);
    912  1.530   msaitoh static int	wm_get_nvm_82571(struct wm_softc *);
    913  1.530   msaitoh static void	wm_put_nvm_82571(struct wm_softc *);
    914  1.424   msaitoh static int	wm_get_phy_82575(struct wm_softc *);
    915  1.424   msaitoh static void	wm_put_phy_82575(struct wm_softc *);
    916  1.424   msaitoh static int	wm_get_swfwhw_semaphore(struct wm_softc *); /* For 574/583 */
    917  1.139    bouyer static void	wm_put_swfwhw_semaphore(struct wm_softc *);
    918  1.424   msaitoh static int	wm_get_swflag_ich8lan(struct wm_softc *);	/* For PHY */
    919  1.424   msaitoh static void	wm_put_swflag_ich8lan(struct wm_softc *);
    920  1.530   msaitoh static int	wm_get_nvm_ich8lan(struct wm_softc *);
    921  1.423   msaitoh static void	wm_put_nvm_ich8lan(struct wm_softc *);
    922  1.259   msaitoh static int	wm_get_hw_semaphore_82573(struct wm_softc *);
    923  1.259   msaitoh static void	wm_put_hw_semaphore_82573(struct wm_softc *);
    924  1.139    bouyer 
    925  1.280   msaitoh /*
    926  1.280   msaitoh  * Management mode and power management related subroutines.
    927  1.280   msaitoh  * BMC, AMT, suspend/resume and EEE.
    928  1.280   msaitoh  */
    929  1.439   msaitoh #if 0
    930  1.169   msaitoh static int	wm_check_mng_mode(struct wm_softc *);
    931  1.169   msaitoh static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
    932  1.169   msaitoh static int	wm_check_mng_mode_82574(struct wm_softc *);
    933  1.169   msaitoh static int	wm_check_mng_mode_generic(struct wm_softc *);
    934  1.378   msaitoh #endif
    935  1.203   msaitoh static int	wm_enable_mng_pass_thru(struct wm_softc *);
    936  1.386   msaitoh static bool	wm_phy_resetisblocked(struct wm_softc *);
    937  1.169   msaitoh static void	wm_get_hw_control(struct wm_softc *);
    938  1.280   msaitoh static void	wm_release_hw_control(struct wm_softc *);
    939  1.392   msaitoh static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool);
    940  1.280   msaitoh static void	wm_smbustopci(struct wm_softc *);
    941  1.280   msaitoh static void	wm_init_manageability(struct wm_softc *);
    942  1.280   msaitoh static void	wm_release_manageability(struct wm_softc *);
    943  1.280   msaitoh static void	wm_get_wakeup(struct wm_softc *);
    944  1.447   msaitoh static void	wm_ulp_disable(struct wm_softc *);
    945  1.280   msaitoh static void	wm_enable_phy_wakeup(struct wm_softc *);
    946  1.203   msaitoh static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
    947  1.280   msaitoh static void	wm_enable_wakeup(struct wm_softc *);
    948  1.552   msaitoh static void	wm_disable_aspm(struct wm_softc *);
    949  1.377   msaitoh /* LPLU (Low Power Link Up) */
    950  1.377   msaitoh static void	wm_lplu_d0_disable(struct wm_softc *);
    951  1.280   msaitoh /* EEE */
    952  1.280   msaitoh static void	wm_set_eee_i350(struct wm_softc *);
    953  1.280   msaitoh 
    954  1.280   msaitoh /*
    955  1.280   msaitoh  * Workarounds (mainly PHY related).
    956  1.280   msaitoh  * Basically, PHY's workarounds are in the PHY drivers.
    957  1.280   msaitoh  */
    958  1.280   msaitoh static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
    959  1.280   msaitoh static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
    960  1.192   msaitoh static void	wm_hv_phy_workaround_ich8lan(struct wm_softc *);
    961  1.221   msaitoh static void	wm_lv_phy_workaround_ich8lan(struct wm_softc *);
    962  1.424   msaitoh static int	wm_k1_gig_workaround_hv(struct wm_softc *, int);
    963  1.221   msaitoh static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
    964  1.192   msaitoh static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
    965  1.199   msaitoh static void	wm_reset_init_script_82575(struct wm_softc *);
    966  1.325   msaitoh static void	wm_reset_mdicnfg_82580(struct wm_softc *);
    967  1.447   msaitoh static bool	wm_phy_is_accessible_pchlan(struct wm_softc *);
    968  1.447   msaitoh static void	wm_toggle_lanphypc_pch_lpt(struct wm_softc *);
    969  1.445   msaitoh static int	wm_platform_pm_pch_lpt(struct wm_softc *, bool);
    970  1.329   msaitoh static void	wm_pll_workaround_i210(struct wm_softc *);
    971  1.517   msaitoh static void	wm_legacy_irq_quirk_spt(struct wm_softc *);
    972    1.1   thorpej 
    973  1.201   msaitoh CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
    974  1.201   msaitoh     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
    975    1.1   thorpej 
    976    1.1   thorpej /*
    977    1.1   thorpej  * Devices supported by this driver.
    978    1.1   thorpej  */
    979   1.76   thorpej static const struct wm_product {
    980    1.1   thorpej 	pci_vendor_id_t		wmp_vendor;
    981    1.1   thorpej 	pci_product_id_t	wmp_product;
    982    1.1   thorpej 	const char		*wmp_name;
    983   1.43   thorpej 	wm_chip_type		wmp_type;
    984  1.292   msaitoh 	uint32_t		wmp_flags;
    985  1.311   msaitoh #define	WMP_F_UNKNOWN		WM_MEDIATYPE_UNKNOWN
    986  1.311   msaitoh #define	WMP_F_FIBER		WM_MEDIATYPE_FIBER
    987  1.311   msaitoh #define	WMP_F_COPPER		WM_MEDIATYPE_COPPER
    988  1.311   msaitoh #define	WMP_F_SERDES		WM_MEDIATYPE_SERDES
    989  1.292   msaitoh #define WMP_MEDIATYPE(x)	((x) & 0x03)
    990    1.1   thorpej } wm_products[] = {
    991    1.1   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
    992    1.1   thorpej 	  "Intel i82542 1000BASE-X Ethernet",
    993  1.291   msaitoh 	  WM_T_82542_2_1,	WMP_F_FIBER },
    994    1.1   thorpej 
    995   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
    996   1.11   thorpej 	  "Intel i82543GC 1000BASE-X Ethernet",
    997  1.291   msaitoh 	  WM_T_82543,		WMP_F_FIBER },
    998    1.1   thorpej 
    999   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
   1000   1.11   thorpej 	  "Intel i82543GC 1000BASE-T Ethernet",
   1001  1.291   msaitoh 	  WM_T_82543,		WMP_F_COPPER },
   1002    1.1   thorpej 
   1003   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
   1004   1.11   thorpej 	  "Intel i82544EI 1000BASE-T Ethernet",
   1005  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
   1006    1.1   thorpej 
   1007   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
   1008   1.11   thorpej 	  "Intel i82544EI 1000BASE-X Ethernet",
   1009  1.291   msaitoh 	  WM_T_82544,		WMP_F_FIBER },
   1010    1.1   thorpej 
   1011   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
   1012    1.1   thorpej 	  "Intel i82544GC 1000BASE-T Ethernet",
   1013  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
   1014    1.1   thorpej 
   1015   1.11   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
   1016   1.11   thorpej 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
   1017  1.291   msaitoh 	  WM_T_82544,		WMP_F_COPPER },
   1018    1.1   thorpej 
   1019   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
   1020   1.17   thorpej 	  "Intel i82540EM 1000BASE-T Ethernet",
   1021  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1022   1.34      kent 
   1023   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
   1024   1.55   thorpej 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
   1025  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1026   1.55   thorpej 
   1027   1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
   1028   1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
   1029  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1030   1.34      kent 
   1031   1.34      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
   1032   1.34      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
   1033  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1034   1.33      kent 
   1035   1.33      kent 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
   1036   1.33      kent 	  "Intel i82540EP 1000BASE-T Ethernet",
   1037  1.291   msaitoh 	  WM_T_82540,		WMP_F_COPPER },
   1038   1.17   thorpej 
   1039   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
   1040   1.17   thorpej 	  "Intel i82545EM 1000BASE-T Ethernet",
   1041  1.291   msaitoh 	  WM_T_82545,		WMP_F_COPPER },
   1042   1.17   thorpej 
   1043   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
   1044   1.55   thorpej 	  "Intel i82545GM 1000BASE-T Ethernet",
   1045  1.291   msaitoh 	  WM_T_82545_3,		WMP_F_COPPER },
   1046   1.55   thorpej 
   1047   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
   1048   1.55   thorpej 	  "Intel i82545GM 1000BASE-X Ethernet",
   1049  1.291   msaitoh 	  WM_T_82545_3,		WMP_F_FIBER },
   1050  1.279   msaitoh 
   1051   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
   1052   1.55   thorpej 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
   1053   1.55   thorpej 	  WM_T_82545_3,		WMP_F_SERDES },
   1054  1.279   msaitoh 
   1055   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
   1056   1.39   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
   1057  1.291   msaitoh 	  WM_T_82546,		WMP_F_COPPER },
   1058   1.39   thorpej 
   1059  1.198   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_QUAD,
   1060   1.17   thorpej 	  "Intel i82546EB 1000BASE-T Ethernet",
   1061  1.291   msaitoh 	  WM_T_82546,		WMP_F_COPPER },
   1062   1.17   thorpej 
   1063   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
   1064   1.17   thorpej 	  "Intel i82545EM 1000BASE-X Ethernet",
   1065  1.291   msaitoh 	  WM_T_82545,		WMP_F_FIBER },
   1066   1.17   thorpej 
   1067   1.17   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
   1068   1.17   thorpej 	  "Intel i82546EB 1000BASE-X Ethernet",
   1069  1.291   msaitoh 	  WM_T_82546,		WMP_F_FIBER },
   1070   1.17   thorpej 
   1071   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
   1072   1.55   thorpej 	  "Intel i82546GB 1000BASE-T Ethernet",
   1073  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1074   1.55   thorpej 
   1075   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
   1076   1.55   thorpej 	  "Intel i82546GB 1000BASE-X Ethernet",
   1077  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_FIBER },
   1078  1.279   msaitoh 
   1079   1.55   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
   1080   1.55   thorpej 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
   1081   1.55   thorpej 	  WM_T_82546_3,		WMP_F_SERDES },
   1082  1.279   msaitoh 
   1083  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
   1084  1.127    bouyer 	  "i82546GB quad-port Gigabit Ethernet",
   1085  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1086  1.127    bouyer 
   1087  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
   1088  1.127    bouyer 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
   1089  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1090  1.127    bouyer 
   1091  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
   1092  1.116   msaitoh 	  "Intel PRO/1000MT (82546GB)",
   1093  1.291   msaitoh 	  WM_T_82546_3,		WMP_F_COPPER },
   1094  1.116   msaitoh 
   1095   1.63   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
   1096   1.63   thorpej 	  "Intel i82541EI 1000BASE-T Ethernet",
   1097  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1098   1.63   thorpej 
   1099  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
   1100  1.116   msaitoh 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
   1101  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1102  1.116   msaitoh 
   1103   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
   1104   1.57   thorpej 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
   1105  1.291   msaitoh 	  WM_T_82541,		WMP_F_COPPER },
   1106   1.57   thorpej 
   1107   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
   1108   1.57   thorpej 	  "Intel i82541ER 1000BASE-T Ethernet",
   1109  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1110   1.57   thorpej 
   1111   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
   1112   1.57   thorpej 	  "Intel i82541GI 1000BASE-T Ethernet",
   1113  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1114   1.57   thorpej 
   1115   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
   1116   1.57   thorpej 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
   1117  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1118   1.57   thorpej 
   1119  1.101      tron 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
   1120  1.101      tron 	  "Intel i82541PI 1000BASE-T Ethernet",
   1121  1.291   msaitoh 	  WM_T_82541_2,		WMP_F_COPPER },
   1122  1.101      tron 
   1123   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
   1124   1.57   thorpej 	  "Intel i82547EI 1000BASE-T Ethernet",
   1125  1.291   msaitoh 	  WM_T_82547,		WMP_F_COPPER },
   1126   1.57   thorpej 
   1127  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
   1128  1.141    simonb 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
   1129  1.291   msaitoh 	  WM_T_82547,		WMP_F_COPPER },
   1130  1.116   msaitoh 
   1131   1.57   thorpej 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
   1132   1.57   thorpej 	  "Intel i82547GI 1000BASE-T Ethernet",
   1133  1.291   msaitoh 	  WM_T_82547_2,		WMP_F_COPPER },
   1134  1.116   msaitoh 
   1135  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
   1136  1.116   msaitoh 	  "Intel PRO/1000 PT (82571EB)",
   1137  1.291   msaitoh 	  WM_T_82571,		WMP_F_COPPER },
   1138  1.116   msaitoh 
   1139  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
   1140  1.116   msaitoh 	  "Intel PRO/1000 PF (82571EB)",
   1141  1.291   msaitoh 	  WM_T_82571,		WMP_F_FIBER },
   1142  1.279   msaitoh 
   1143  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
   1144  1.116   msaitoh 	  "Intel PRO/1000 PB (82571EB)",
   1145  1.116   msaitoh 	  WM_T_82571,		WMP_F_SERDES },
   1146  1.279   msaitoh 
   1147  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
   1148  1.127    bouyer 	  "Intel PRO/1000 QT (82571EB)",
   1149  1.291   msaitoh 	  WM_T_82571,		WMP_F_COPPER },
   1150  1.127    bouyer 
   1151  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
   1152  1.299   msaitoh 	  "Intel PRO/1000 PT Quad Port Server Adapter",
   1153  1.299   msaitoh 	  WM_T_82571,		WMP_F_COPPER, },
   1154  1.299   msaitoh 
   1155  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER,
   1156  1.299   msaitoh 	  "Intel Gigabit PT Quad Port Server ExpressModule",
   1157  1.299   msaitoh 	  WM_T_82571,		WMP_F_COPPER, },
   1158  1.299   msaitoh 
   1159  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES,
   1160  1.299   msaitoh 	  "Intel 82571EB Dual Gigabit Ethernet (SERDES)",
   1161  1.299   msaitoh 	  WM_T_82571,		WMP_F_SERDES, },
   1162  1.299   msaitoh 
   1163  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES,
   1164  1.299   msaitoh 	  "Intel 82571EB Quad Gigabit Ethernet (SERDES)",
   1165  1.299   msaitoh 	  WM_T_82571,		WMP_F_SERDES, },
   1166  1.299   msaitoh 
   1167  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER,
   1168  1.299   msaitoh 	  "Intel 82571EB Quad 1000baseX Ethernet",
   1169  1.299   msaitoh 	  WM_T_82571,		WMP_F_FIBER, },
   1170  1.299   msaitoh 
   1171  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
   1172  1.116   msaitoh 	  "Intel i82572EI 1000baseT Ethernet",
   1173  1.291   msaitoh 	  WM_T_82572,		WMP_F_COPPER },
   1174  1.116   msaitoh 
   1175  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
   1176  1.116   msaitoh 	  "Intel i82572EI 1000baseX Ethernet",
   1177  1.291   msaitoh 	  WM_T_82572,		WMP_F_FIBER },
   1178  1.279   msaitoh 
   1179  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
   1180  1.116   msaitoh 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
   1181  1.116   msaitoh 	  WM_T_82572,		WMP_F_SERDES },
   1182  1.116   msaitoh 
   1183  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
   1184  1.116   msaitoh 	  "Intel i82572EI 1000baseT Ethernet",
   1185  1.291   msaitoh 	  WM_T_82572,		WMP_F_COPPER },
   1186  1.116   msaitoh 
   1187  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
   1188  1.116   msaitoh 	  "Intel i82573E",
   1189  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1190  1.116   msaitoh 
   1191  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
   1192  1.117   msaitoh 	  "Intel i82573E IAMT",
   1193  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1194  1.116   msaitoh 
   1195  1.116   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
   1196  1.116   msaitoh 	  "Intel i82573L Gigabit Ethernet",
   1197  1.291   msaitoh 	  WM_T_82573,		WMP_F_COPPER },
   1198  1.116   msaitoh 
   1199  1.165  sborrill 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
   1200  1.165  sborrill 	  "Intel i82574L",
   1201  1.291   msaitoh 	  WM_T_82574,		WMP_F_COPPER },
   1202  1.165  sborrill 
   1203  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574LA,
   1204  1.299   msaitoh 	  "Intel i82574L",
   1205  1.299   msaitoh 	  WM_T_82574,		WMP_F_COPPER },
   1206  1.299   msaitoh 
   1207  1.185   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82583V,
   1208  1.185   msaitoh 	  "Intel i82583V",
   1209  1.291   msaitoh 	  WM_T_82583,		WMP_F_COPPER },
   1210  1.185   msaitoh 
   1211  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
   1212  1.127    bouyer 	  "i80003 dual 1000baseT Ethernet",
   1213  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1214  1.127    bouyer 
   1215  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
   1216  1.127    bouyer 	  "i80003 dual 1000baseX Ethernet",
   1217  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1218  1.279   msaitoh 
   1219  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
   1220  1.127    bouyer 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
   1221  1.127    bouyer 	  WM_T_80003,		WMP_F_SERDES },
   1222  1.127    bouyer 
   1223  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
   1224  1.127    bouyer 	  "Intel i80003 1000baseT Ethernet",
   1225  1.291   msaitoh 	  WM_T_80003,		WMP_F_COPPER },
   1226  1.279   msaitoh 
   1227  1.127    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
   1228  1.127    bouyer 	  "Intel i80003 Gigabit Ethernet (SERDES)",
   1229  1.127    bouyer 	  WM_T_80003,		WMP_F_SERDES },
   1230  1.279   msaitoh 
   1231  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
   1232  1.139    bouyer 	  "Intel i82801H (M_AMT) LAN Controller",
   1233  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1234  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
   1235  1.139    bouyer 	  "Intel i82801H (AMT) LAN Controller",
   1236  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1237  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
   1238  1.139    bouyer 	  "Intel i82801H LAN Controller",
   1239  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1240  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
   1241  1.438   msaitoh 	  "Intel i82801H (IFE) 10/100 LAN Controller",
   1242  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1243  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
   1244  1.139    bouyer 	  "Intel i82801H (M) LAN Controller",
   1245  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1246  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
   1247  1.438   msaitoh 	  "Intel i82801H IFE (GT) 10/100 LAN Controller",
   1248  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1249  1.139    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
   1250  1.438   msaitoh 	  "Intel i82801H IFE (G) 10/100 LAN Controller",
   1251  1.291   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1252  1.426   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_82567V_3,
   1253  1.426   msaitoh 	  "82567V-3 LAN Controller",
   1254  1.426   msaitoh 	  WM_T_ICH8,		WMP_F_COPPER },
   1255  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
   1256  1.144   msaitoh 	  "82801I (AMT) LAN Controller",
   1257  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1258  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
   1259  1.438   msaitoh 	  "82801I 10/100 LAN Controller",
   1260  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1261  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
   1262  1.438   msaitoh 	  "82801I (G) 10/100 LAN Controller",
   1263  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1264  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
   1265  1.438   msaitoh 	  "82801I (GT) 10/100 LAN Controller",
   1266  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1267  1.144   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
   1268  1.144   msaitoh 	  "82801I (C) LAN Controller",
   1269  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1270  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
   1271  1.162    bouyer 	  "82801I mobile LAN Controller",
   1272  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1273  1.459   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_V,
   1274  1.162    bouyer 	  "82801I mobile (V) LAN Controller",
   1275  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1276  1.162    bouyer 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
   1277  1.162    bouyer 	  "82801I mobile (AMT) LAN Controller",
   1278  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1279  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_BM,
   1280  1.191   msaitoh 	  "82567LM-4 LAN Controller",
   1281  1.291   msaitoh 	  WM_T_ICH9,		WMP_F_COPPER },
   1282  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LM,
   1283  1.191   msaitoh 	  "82567LM-2 LAN Controller",
   1284  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1285  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LF,
   1286  1.191   msaitoh 	  "82567LF-2 LAN Controller",
   1287  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1288  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LM,
   1289  1.164     markd 	  "82567LM-3 LAN Controller",
   1290  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1291  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LF,
   1292  1.167   msaitoh 	  "82567LF-3 LAN Controller",
   1293  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1294  1.191   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_V,
   1295  1.191   msaitoh 	  "82567V-2 LAN Controller",
   1296  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1297  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_V,
   1298  1.221   msaitoh 	  "82567V-3? LAN Controller",
   1299  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1300  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_HANKSVILLE,
   1301  1.221   msaitoh 	  "HANKSVILLE LAN Controller",
   1302  1.291   msaitoh 	  WM_T_ICH10,		WMP_F_COPPER },
   1303  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LM,
   1304  1.207   msaitoh 	  "PCH LAN (82577LM) Controller",
   1305  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1306  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LC,
   1307  1.207   msaitoh 	  "PCH LAN (82577LC) Controller",
   1308  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1309  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DM,
   1310  1.190   msaitoh 	  "PCH LAN (82578DM) Controller",
   1311  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1312  1.190   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DC,
   1313  1.190   msaitoh 	  "PCH LAN (82578DC) Controller",
   1314  1.291   msaitoh 	  WM_T_PCH,		WMP_F_COPPER },
   1315  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_LM,
   1316  1.221   msaitoh 	  "PCH2 LAN (82579LM) Controller",
   1317  1.291   msaitoh 	  WM_T_PCH2,		WMP_F_COPPER },
   1318  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_V,
   1319  1.221   msaitoh 	  "PCH2 LAN (82579V) Controller",
   1320  1.291   msaitoh 	  WM_T_PCH2,		WMP_F_COPPER },
   1321  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_COPPER,
   1322  1.199   msaitoh 	  "82575EB dual-1000baseT Ethernet",
   1323  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1324  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES,
   1325  1.199   msaitoh 	  "82575EB dual-1000baseX Ethernet (SERDES)",
   1326  1.199   msaitoh 	  WM_T_82575,		WMP_F_SERDES },
   1327  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER,
   1328  1.199   msaitoh 	  "82575GB quad-1000baseT Ethernet",
   1329  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1330  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM,
   1331  1.199   msaitoh 	  "82575GB quad-1000baseT Ethernet (PM)",
   1332  1.291   msaitoh 	  WM_T_82575,		WMP_F_COPPER },
   1333  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_COPPER,
   1334  1.199   msaitoh 	  "82576 1000BaseT Ethernet",
   1335  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1336  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_FIBER,
   1337  1.199   msaitoh 	  "82576 1000BaseX Ethernet",
   1338  1.291   msaitoh 	  WM_T_82576,		WMP_F_FIBER },
   1339  1.279   msaitoh 
   1340  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES,
   1341  1.199   msaitoh 	  "82576 gigabit Ethernet (SERDES)",
   1342  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1343  1.279   msaitoh 
   1344  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_QUAD_COPPER,
   1345  1.199   msaitoh 	  "82576 quad-1000BaseT Ethernet",
   1346  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1347  1.299   msaitoh 
   1348  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2,
   1349  1.299   msaitoh 	  "82576 Gigabit ET2 Quad Port Server Adapter",
   1350  1.299   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1351  1.299   msaitoh 
   1352  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS,
   1353  1.199   msaitoh 	  "82576 gigabit Ethernet",
   1354  1.291   msaitoh 	  WM_T_82576,		WMP_F_COPPER },
   1355  1.279   msaitoh 
   1356  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS_SERDES,
   1357  1.199   msaitoh 	  "82576 gigabit Ethernet (SERDES)",
   1358  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1359  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES_QUAD,
   1360  1.199   msaitoh 	  "82576 quad-gigabit Ethernet (SERDES)",
   1361  1.199   msaitoh 	  WM_T_82576,		WMP_F_SERDES },
   1362  1.279   msaitoh 
   1363  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER,
   1364  1.199   msaitoh 	  "82580 1000BaseT Ethernet",
   1365  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1366  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_FIBER,
   1367  1.199   msaitoh 	  "82580 1000BaseX Ethernet",
   1368  1.291   msaitoh 	  WM_T_82580,		WMP_F_FIBER },
   1369  1.279   msaitoh 
   1370  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SERDES,
   1371  1.199   msaitoh 	  "82580 1000BaseT Ethernet (SERDES)",
   1372  1.199   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1373  1.279   msaitoh 
   1374  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SGMII,
   1375  1.199   msaitoh 	  "82580 gigabit Ethernet (SGMII)",
   1376  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1377  1.199   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER_DUAL,
   1378  1.199   msaitoh 	  "82580 dual-1000BaseT Ethernet",
   1379  1.291   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1380  1.300   msaitoh 
   1381  1.221   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_QUAD_FIBER,
   1382  1.221   msaitoh 	  "82580 quad-1000BaseX Ethernet",
   1383  1.291   msaitoh 	  WM_T_82580,		WMP_F_FIBER },
   1384  1.300   msaitoh 
   1385  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SGMII,
   1386  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SGMII)",
   1387  1.304   msaitoh 	  WM_T_82580,		WMP_F_COPPER },
   1388  1.304   msaitoh 
   1389  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SERDES,
   1390  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SERDES)",
   1391  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1392  1.304   msaitoh 
   1393  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_BPLANE,
   1394  1.304   msaitoh 	  "DH89XXCC 1000BASE-KX Ethernet",
   1395  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1396  1.304   msaitoh 
   1397  1.304   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH89XXCC_SFP,
   1398  1.304   msaitoh 	  "DH89XXCC Gigabit Ethernet (SFP)",
   1399  1.304   msaitoh 	  WM_T_82580,		WMP_F_SERDES },
   1400  1.304   msaitoh 
   1401  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_COPPER,
   1402  1.228   msaitoh 	  "I350 Gigabit Network Connection",
   1403  1.291   msaitoh 	  WM_T_I350,		WMP_F_COPPER },
   1404  1.304   msaitoh 
   1405  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_FIBER,
   1406  1.228   msaitoh 	  "I350 Gigabit Fiber Network Connection",
   1407  1.291   msaitoh 	  WM_T_I350,		WMP_F_FIBER },
   1408  1.279   msaitoh 
   1409  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SERDES,
   1410  1.228   msaitoh 	  "I350 Gigabit Backplane Connection",
   1411  1.228   msaitoh 	  WM_T_I350,		WMP_F_SERDES },
   1412  1.292   msaitoh 
   1413  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_DA4,
   1414  1.299   msaitoh 	  "I350 Quad Port Gigabit Ethernet",
   1415  1.299   msaitoh 	  WM_T_I350,		WMP_F_SERDES },
   1416  1.299   msaitoh 
   1417  1.228   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SGMII,
   1418  1.228   msaitoh 	  "I350 Gigabit Connection",
   1419  1.291   msaitoh 	  WM_T_I350,		WMP_F_COPPER },
   1420  1.292   msaitoh 
   1421  1.308   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_1000KX,
   1422  1.308   msaitoh 	  "I354 Gigabit Ethernet (KX)",
   1423  1.308   msaitoh 	  WM_T_I354,		WMP_F_SERDES },
   1424  1.308   msaitoh 
   1425  1.265   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_SGMII,
   1426  1.308   msaitoh 	  "I354 Gigabit Ethernet (SGMII)",
   1427  1.308   msaitoh 	  WM_T_I354,		WMP_F_COPPER },
   1428  1.308   msaitoh 
   1429  1.308   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_25GBE,
   1430  1.308   msaitoh 	  "I354 Gigabit Ethernet (2.5G)",
   1431  1.291   msaitoh 	  WM_T_I354,		WMP_F_COPPER },
   1432  1.308   msaitoh 
   1433  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_T1,
   1434  1.247   msaitoh 	  "I210-T1 Ethernet Server Adapter",
   1435  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1436  1.299   msaitoh 
   1437  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_OEM1,
   1438  1.247   msaitoh 	  "I210 Ethernet (Copper OEM)",
   1439  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1440  1.299   msaitoh 
   1441  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_IT,
   1442  1.247   msaitoh 	  "I210 Ethernet (Copper IT)",
   1443  1.291   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1444  1.299   msaitoh 
   1445  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_WOF,
   1446  1.299   msaitoh 	  "I210 Ethernet (FLASH less)",
   1447  1.299   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1448  1.299   msaitoh 
   1449  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_FIBER,
   1450  1.247   msaitoh 	  "I210 Gigabit Ethernet (Fiber)",
   1451  1.291   msaitoh 	  WM_T_I210,		WMP_F_FIBER },
   1452  1.279   msaitoh 
   1453  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES,
   1454  1.247   msaitoh 	  "I210 Gigabit Ethernet (SERDES)",
   1455  1.247   msaitoh 	  WM_T_I210,		WMP_F_SERDES },
   1456  1.292   msaitoh 
   1457  1.299   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES_WOF,
   1458  1.299   msaitoh 	  "I210 Gigabit Ethernet (FLASH less)",
   1459  1.299   msaitoh 	  WM_T_I210,		WMP_F_SERDES },
   1460  1.299   msaitoh 
   1461  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SGMII,
   1462  1.247   msaitoh 	  "I210 Gigabit Ethernet (SGMII)",
   1463  1.292   msaitoh 	  WM_T_I210,		WMP_F_COPPER },
   1464  1.292   msaitoh 
   1465  1.247   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I211_COPPER,
   1466  1.247   msaitoh 	  "I211 Ethernet (COPPER)",
   1467  1.291   msaitoh 	  WM_T_I211,		WMP_F_COPPER },
   1468  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_V,
   1469  1.249   msaitoh 	  "I217 V Ethernet Connection",
   1470  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1471  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_LM,
   1472  1.249   msaitoh 	  "I217 LM Ethernet Connection",
   1473  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1474  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V,
   1475  1.249   msaitoh 	  "I218 V Ethernet Connection",
   1476  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1477  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V2,
   1478  1.298   msaitoh 	  "I218 V Ethernet Connection",
   1479  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1480  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V3,
   1481  1.298   msaitoh 	  "I218 V Ethernet Connection",
   1482  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1483  1.249   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM,
   1484  1.249   msaitoh 	  "I218 LM Ethernet Connection",
   1485  1.291   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1486  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM2,
   1487  1.298   msaitoh 	  "I218 LM Ethernet Connection",
   1488  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1489  1.298   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM3,
   1490  1.298   msaitoh 	  "I218 LM Ethernet Connection",
   1491  1.298   msaitoh 	  WM_T_PCH_LPT,		WMP_F_COPPER },
   1492  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V,
   1493  1.392   msaitoh 	  "I219 V Ethernet Connection",
   1494  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1495  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V2,
   1496  1.392   msaitoh 	  "I219 V Ethernet Connection",
   1497  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1498  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V4,
   1499  1.422   msaitoh 	  "I219 V Ethernet Connection",
   1500  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1501  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V5,
   1502  1.422   msaitoh 	  "I219 V Ethernet Connection",
   1503  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1504  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM,
   1505  1.392   msaitoh 	  "I219 LM Ethernet Connection",
   1506  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1507  1.392   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM2,
   1508  1.392   msaitoh 	  "I219 LM Ethernet Connection",
   1509  1.392   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1510  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM3,
   1511  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1512  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1513  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM4,
   1514  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1515  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1516  1.422   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM5,
   1517  1.422   msaitoh 	  "I219 LM Ethernet Connection",
   1518  1.422   msaitoh 	  WM_T_PCH_SPT,		WMP_F_COPPER },
   1519  1.570   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V6,
   1520  1.570   msaitoh 	  "I219 V Ethernet Connection",
   1521  1.570   msaitoh 	  WM_T_PCH_CNP,		WMP_F_COPPER },
   1522  1.570   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_V7,
   1523  1.570   msaitoh 	  "I219 V Ethernet Connection",
   1524  1.570   msaitoh 	  WM_T_PCH_CNP,		WMP_F_COPPER },
   1525  1.570   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM6,
   1526  1.570   msaitoh 	  "I219 LM Ethernet Connection",
   1527  1.570   msaitoh 	  WM_T_PCH_CNP,		WMP_F_COPPER },
   1528  1.570   msaitoh 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I219_LM7,
   1529  1.570   msaitoh 	  "I219 LM Ethernet Connection",
   1530  1.570   msaitoh 	  WM_T_PCH_CNP,		WMP_F_COPPER },
   1531    1.1   thorpej 	{ 0,			0,
   1532    1.1   thorpej 	  NULL,
   1533    1.1   thorpej 	  0,			0 },
   1534    1.1   thorpej };
   1535    1.1   thorpej 
   1536  1.280   msaitoh /*
   1537  1.280   msaitoh  * Register read/write functions.
   1538  1.280   msaitoh  * Other than CSR_{READ|WRITE}().
   1539  1.280   msaitoh  */
   1540  1.280   msaitoh 
   1541   1.53   thorpej #if 0 /* Not currently used */
   1542  1.110     perry static inline uint32_t
   1543   1.53   thorpej wm_io_read(struct wm_softc *sc, int reg)
   1544   1.53   thorpej {
   1545   1.53   thorpej 
   1546   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
   1547   1.53   thorpej 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
   1548   1.53   thorpej }
   1549   1.53   thorpej #endif
   1550   1.53   thorpej 
   1551  1.110     perry static inline void
   1552   1.53   thorpej wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
   1553   1.53   thorpej {
   1554   1.53   thorpej 
   1555   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
   1556   1.53   thorpej 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
   1557   1.53   thorpej }
   1558   1.53   thorpej 
   1559  1.110     perry static inline void
   1560  1.199   msaitoh wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off,
   1561  1.199   msaitoh     uint32_t data)
   1562  1.199   msaitoh {
   1563  1.199   msaitoh 	uint32_t regval;
   1564  1.199   msaitoh 	int i;
   1565  1.199   msaitoh 
   1566  1.199   msaitoh 	regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT);
   1567  1.199   msaitoh 
   1568  1.199   msaitoh 	CSR_WRITE(sc, reg, regval);
   1569  1.199   msaitoh 
   1570  1.199   msaitoh 	for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) {
   1571  1.199   msaitoh 		delay(5);
   1572  1.199   msaitoh 		if (CSR_READ(sc, reg) & SCTL_CTL_READY)
   1573  1.199   msaitoh 			break;
   1574  1.199   msaitoh 	}
   1575  1.199   msaitoh 	if (i == SCTL_CTL_POLL_TIMEOUT) {
   1576  1.280   msaitoh 		aprint_error("%s: WARNING:"
   1577  1.280   msaitoh 		    " i82575 reg 0x%08x setup did not indicate ready\n",
   1578  1.199   msaitoh 		    device_xname(sc->sc_dev), reg);
   1579  1.199   msaitoh 	}
   1580  1.199   msaitoh }
   1581  1.199   msaitoh 
   1582  1.199   msaitoh static inline void
   1583  1.110     perry wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
   1584   1.69   thorpej {
   1585   1.69   thorpej 	wa->wa_low = htole32(v & 0xffffffffU);
   1586   1.69   thorpej 	if (sizeof(bus_addr_t) == 8)
   1587   1.69   thorpej 		wa->wa_high = htole32((uint64_t) v >> 32);
   1588   1.69   thorpej 	else
   1589   1.69   thorpej 		wa->wa_high = 0;
   1590   1.69   thorpej }
   1591   1.69   thorpej 
   1592  1.280   msaitoh /*
   1593  1.352  knakahar  * Descriptor sync/init functions.
   1594  1.352  knakahar  */
   1595  1.352  knakahar static inline void
   1596  1.362  knakahar wm_cdtxsync(struct wm_txqueue *txq, int start, int num, int ops)
   1597  1.352  knakahar {
   1598  1.362  knakahar 	struct wm_softc *sc = txq->txq_sc;
   1599  1.352  knakahar 
   1600  1.352  knakahar 	/* If it will wrap around, sync to the end of the ring. */
   1601  1.356  knakahar 	if ((start + num) > WM_NTXDESC(txq)) {
   1602  1.356  knakahar 		bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
   1603  1.398  knakahar 		    WM_CDTXOFF(txq, start), txq->txq_descsize *
   1604  1.356  knakahar 		    (WM_NTXDESC(txq) - start), ops);
   1605  1.356  knakahar 		num -= (WM_NTXDESC(txq) - start);
   1606  1.352  knakahar 		start = 0;
   1607  1.352  knakahar 	}
   1608  1.352  knakahar 
   1609  1.352  knakahar 	/* Now sync whatever is left. */
   1610  1.356  knakahar 	bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap,
   1611  1.398  knakahar 	    WM_CDTXOFF(txq, start), txq->txq_descsize * num, ops);
   1612  1.352  knakahar }
   1613  1.352  knakahar 
   1614  1.352  knakahar static inline void
   1615  1.362  knakahar wm_cdrxsync(struct wm_rxqueue *rxq, int start, int ops)
   1616  1.352  knakahar {
   1617  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   1618  1.352  knakahar 
   1619  1.356  knakahar 	bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap,
   1620  1.466  knakahar 	    WM_CDRXOFF(rxq, start), rxq->rxq_descsize, ops);
   1621  1.352  knakahar }
   1622  1.352  knakahar 
   1623  1.352  knakahar static inline void
   1624  1.362  knakahar wm_init_rxdesc(struct wm_rxqueue *rxq, int start)
   1625  1.352  knakahar {
   1626  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   1627  1.356  knakahar 	struct wm_rxsoft *rxs = &rxq->rxq_soft[start];
   1628  1.352  knakahar 	struct mbuf *m = rxs->rxs_mbuf;
   1629  1.352  knakahar 
   1630  1.352  knakahar 	/*
   1631  1.352  knakahar 	 * Note: We scoot the packet forward 2 bytes in the buffer
   1632  1.352  knakahar 	 * so that the payload after the Ethernet header is aligned
   1633  1.352  knakahar 	 * to a 4-byte boundary.
   1634  1.352  knakahar 
   1635  1.352  knakahar 	 * XXX BRAINDAMAGE ALERT!
   1636  1.352  knakahar 	 * The stupid chip uses the same size for every buffer, which
   1637  1.352  knakahar 	 * is set in the Receive Control register.  We are using the 2K
   1638  1.352  knakahar 	 * size option, but what we REALLY want is (2K - 2)!  For this
   1639  1.352  knakahar 	 * reason, we can't "scoot" packets longer than the standard
   1640  1.352  knakahar 	 * Ethernet MTU.  On strict-alignment platforms, if the total
   1641  1.352  knakahar 	 * size exceeds (2K - 2) we set align_tweak to 0 and let
   1642  1.352  knakahar 	 * the upper layer copy the headers.
   1643  1.352  knakahar 	 */
   1644  1.352  knakahar 	m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak;
   1645  1.352  knakahar 
   1646  1.466  knakahar 	if (sc->sc_type == WM_T_82574) {
   1647  1.466  knakahar 		ext_rxdesc_t *rxd = &rxq->rxq_ext_descs[start];
   1648  1.466  knakahar 		rxd->erx_data.erxd_addr =
   1649  1.466  knakahar 			htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1650  1.466  knakahar 		rxd->erx_data.erxd_dd = 0;
   1651  1.466  knakahar 	} else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   1652  1.466  knakahar 		nq_rxdesc_t *rxd = &rxq->rxq_nq_descs[start];
   1653  1.466  knakahar 
   1654  1.466  knakahar 		rxd->nqrx_data.nrxd_paddr =
   1655  1.466  knakahar 			htole64(rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1656  1.466  knakahar 		/* Currently, split header is not supported. */
   1657  1.466  knakahar 		rxd->nqrx_data.nrxd_haddr = 0;
   1658  1.466  knakahar 	} else {
   1659  1.466  knakahar 		wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start];
   1660  1.466  knakahar 
   1661  1.466  knakahar 		wm_set_dma_addr(&rxd->wrx_addr,
   1662  1.466  knakahar 		    rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak);
   1663  1.466  knakahar 		rxd->wrx_len = 0;
   1664  1.466  knakahar 		rxd->wrx_cksum = 0;
   1665  1.466  knakahar 		rxd->wrx_status = 0;
   1666  1.466  knakahar 		rxd->wrx_errors = 0;
   1667  1.466  knakahar 		rxd->wrx_special = 0;
   1668  1.466  knakahar 	}
   1669  1.388   msaitoh 	wm_cdrxsync(rxq, start, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   1670  1.352  knakahar 
   1671  1.356  knakahar 	CSR_WRITE(sc, rxq->rxq_rdt_reg, start);
   1672  1.352  knakahar }
   1673  1.352  knakahar 
   1674  1.352  knakahar /*
   1675  1.280   msaitoh  * Device driver interface functions and commonly used functions.
   1676  1.280   msaitoh  * match, attach, detach, init, start, stop, ioctl, watchdog and so on.
   1677  1.280   msaitoh  */
   1678  1.280   msaitoh 
   1679  1.280   msaitoh /* Lookup supported device table */
   1680    1.1   thorpej static const struct wm_product *
   1681    1.1   thorpej wm_lookup(const struct pci_attach_args *pa)
   1682    1.1   thorpej {
   1683    1.1   thorpej 	const struct wm_product *wmp;
   1684    1.1   thorpej 
   1685    1.1   thorpej 	for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
   1686    1.1   thorpej 		if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
   1687    1.1   thorpej 		    PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
   1688  1.194   msaitoh 			return wmp;
   1689    1.1   thorpej 	}
   1690  1.194   msaitoh 	return NULL;
   1691    1.1   thorpej }
   1692    1.1   thorpej 
   1693  1.280   msaitoh /* The match function (ca_match) */
   1694   1.47   thorpej static int
   1695  1.160  christos wm_match(device_t parent, cfdata_t cf, void *aux)
   1696    1.1   thorpej {
   1697    1.1   thorpej 	struct pci_attach_args *pa = aux;
   1698    1.1   thorpej 
   1699    1.1   thorpej 	if (wm_lookup(pa) != NULL)
   1700  1.194   msaitoh 		return 1;
   1701    1.1   thorpej 
   1702  1.194   msaitoh 	return 0;
   1703    1.1   thorpej }
   1704    1.1   thorpej 
   1705  1.280   msaitoh /* The attach function (ca_attach) */
   1706   1.47   thorpej static void
   1707  1.157    dyoung wm_attach(device_t parent, device_t self, void *aux)
   1708    1.1   thorpej {
   1709  1.157    dyoung 	struct wm_softc *sc = device_private(self);
   1710    1.1   thorpej 	struct pci_attach_args *pa = aux;
   1711  1.182   msaitoh 	prop_dictionary_t dict;
   1712    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1713    1.1   thorpej 	pci_chipset_tag_t pc = pa->pa_pc;
   1714  1.340  knakahar 	int counts[PCI_INTR_TYPE_SIZE];
   1715  1.340  knakahar 	pci_intr_type_t max_type;
   1716  1.160  christos 	const char *eetype, *xname;
   1717    1.1   thorpej 	bus_space_tag_t memt;
   1718    1.1   thorpej 	bus_space_handle_t memh;
   1719  1.201   msaitoh 	bus_size_t memsize;
   1720    1.1   thorpej 	int memh_valid;
   1721  1.201   msaitoh 	int i, error;
   1722    1.1   thorpej 	const struct wm_product *wmp;
   1723  1.115   thorpej 	prop_data_t ea;
   1724  1.115   thorpej 	prop_number_t pn;
   1725    1.1   thorpej 	uint8_t enaddr[ETHER_ADDR_LEN];
   1726  1.513   msaitoh 	char buf[256];
   1727  1.325   msaitoh 	uint16_t cfg1, cfg2, swdpin, nvmword;
   1728    1.1   thorpej 	pcireg_t preg, memtype;
   1729  1.203   msaitoh 	uint16_t eeprom_data, apme_mask;
   1730  1.273   msaitoh 	bool force_clear_smbi;
   1731  1.292   msaitoh 	uint32_t link_mode;
   1732   1.44   thorpej 	uint32_t reg;
   1733    1.1   thorpej 
   1734  1.160  christos 	sc->sc_dev = self;
   1735  1.272     ozaki 	callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS);
   1736  1.429  knakahar 	sc->sc_core_stopping = false;
   1737    1.1   thorpej 
   1738  1.292   msaitoh 	wmp = wm_lookup(pa);
   1739  1.292   msaitoh #ifdef DIAGNOSTIC
   1740    1.1   thorpej 	if (wmp == NULL) {
   1741    1.1   thorpej 		printf("\n");
   1742    1.1   thorpej 		panic("wm_attach: impossible");
   1743    1.1   thorpej 	}
   1744  1.292   msaitoh #endif
   1745  1.292   msaitoh 	sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags);
   1746    1.1   thorpej 
   1747  1.123  jmcneill 	sc->sc_pc = pa->pa_pc;
   1748  1.123  jmcneill 	sc->sc_pcitag = pa->pa_tag;
   1749  1.123  jmcneill 
   1750   1.69   thorpej 	if (pci_dma64_available(pa))
   1751   1.69   thorpej 		sc->sc_dmat = pa->pa_dmat64;
   1752   1.69   thorpej 	else
   1753   1.69   thorpej 		sc->sc_dmat = pa->pa_dmat;
   1754    1.1   thorpej 
   1755  1.304   msaitoh 	sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id);
   1756  1.388   msaitoh 	sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag,PCI_CLASS_REG));
   1757  1.226  drochner 	pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1);
   1758    1.1   thorpej 
   1759    1.1   thorpej 	sc->sc_type = wmp->wmp_type;
   1760  1.424   msaitoh 
   1761  1.424   msaitoh 	/* Set default function pointers */
   1762  1.530   msaitoh 	sc->phy.acquire = sc->nvm.acquire = wm_get_null;
   1763  1.530   msaitoh 	sc->phy.release = sc->nvm.release = wm_put_null;
   1764  1.447   msaitoh 	sc->phy.reset_delay_us = (sc->sc_type >= WM_T_82571) ? 100 : 10000;
   1765  1.424   msaitoh 
   1766   1.11   thorpej 	if (sc->sc_type < WM_T_82543) {
   1767  1.192   msaitoh 		if (sc->sc_rev < 2) {
   1768  1.160  christos 			aprint_error_dev(sc->sc_dev,
   1769  1.160  christos 			    "i82542 must be at least rev. 2\n");
   1770    1.1   thorpej 			return;
   1771    1.1   thorpej 		}
   1772  1.192   msaitoh 		if (sc->sc_rev < 3)
   1773   1.11   thorpej 			sc->sc_type = WM_T_82542_2_0;
   1774    1.1   thorpej 	}
   1775    1.1   thorpej 
   1776  1.335   msaitoh 	/*
   1777  1.335   msaitoh 	 * Disable MSI for Errata:
   1778  1.335   msaitoh 	 * "Message Signaled Interrupt Feature May Corrupt Write Transactions"
   1779  1.335   msaitoh 	 *
   1780  1.335   msaitoh 	 *  82544: Errata 25
   1781  1.335   msaitoh 	 *  82540: Errata  6 (easy to reproduce device timeout)
   1782  1.335   msaitoh 	 *  82545: Errata  4 (easy to reproduce device timeout)
   1783  1.335   msaitoh 	 *  82546: Errata 26 (easy to reproduce device timeout)
   1784  1.335   msaitoh 	 *  82541: Errata  7 (easy to reproduce device timeout)
   1785  1.337   msaitoh 	 *
   1786  1.337   msaitoh 	 * "Byte Enables 2 and 3 are not set on MSI writes"
   1787  1.337   msaitoh 	 *
   1788  1.337   msaitoh 	 *  82571 & 82572: Errata 63
   1789  1.335   msaitoh 	 */
   1790  1.337   msaitoh 	if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571)
   1791  1.337   msaitoh 	    || (sc->sc_type == WM_T_82572))
   1792  1.335   msaitoh 		pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY;
   1793  1.335   msaitoh 
   1794  1.199   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   1795  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   1796  1.265   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   1797  1.265   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
   1798  1.203   msaitoh 		sc->sc_flags |= WM_F_NEWQUEUE;
   1799  1.199   msaitoh 
   1800  1.184   msaitoh 	/* Set device properties (mactype) */
   1801  1.182   msaitoh 	dict = device_properties(sc->sc_dev);
   1802  1.182   msaitoh 	prop_dictionary_set_uint32(dict, "mactype", sc->sc_type);
   1803  1.182   msaitoh 
   1804    1.1   thorpej 	/*
   1805   1.53   thorpej 	 * Map the device.  All devices support memory-mapped acccess,
   1806   1.53   thorpej 	 * and it is really required for normal operation.
   1807    1.1   thorpej 	 */
   1808    1.1   thorpej 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
   1809    1.1   thorpej 	switch (memtype) {
   1810    1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
   1811    1.1   thorpej 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
   1812    1.1   thorpej 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
   1813  1.201   msaitoh 		    memtype, 0, &memt, &memh, NULL, &memsize) == 0);
   1814    1.1   thorpej 		break;
   1815    1.1   thorpej 	default:
   1816    1.1   thorpej 		memh_valid = 0;
   1817  1.189   msaitoh 		break;
   1818    1.1   thorpej 	}
   1819    1.1   thorpej 
   1820    1.1   thorpej 	if (memh_valid) {
   1821    1.1   thorpej 		sc->sc_st = memt;
   1822    1.1   thorpej 		sc->sc_sh = memh;
   1823  1.201   msaitoh 		sc->sc_ss = memsize;
   1824    1.1   thorpej 	} else {
   1825  1.160  christos 		aprint_error_dev(sc->sc_dev,
   1826  1.160  christos 		    "unable to map device registers\n");
   1827    1.1   thorpej 		return;
   1828    1.1   thorpej 	}
   1829    1.1   thorpej 
   1830   1.53   thorpej 	/*
   1831   1.53   thorpej 	 * In addition, i82544 and later support I/O mapped indirect
   1832   1.53   thorpej 	 * register access.  It is not desirable (nor supported in
   1833   1.53   thorpej 	 * this driver) to use it for normal operation, though it is
   1834   1.53   thorpej 	 * required to work around bugs in some chip versions.
   1835   1.53   thorpej 	 */
   1836   1.53   thorpej 	if (sc->sc_type >= WM_T_82544) {
   1837   1.53   thorpej 		/* First we have to find the I/O BAR. */
   1838   1.53   thorpej 		for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
   1839  1.241   msaitoh 			memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
   1840  1.241   msaitoh 			if (memtype == PCI_MAPREG_TYPE_IO)
   1841   1.53   thorpej 				break;
   1842  1.241   msaitoh 			if (PCI_MAPREG_MEM_TYPE(memtype) ==
   1843  1.241   msaitoh 			    PCI_MAPREG_MEM_TYPE_64BIT)
   1844  1.241   msaitoh 				i += 4;	/* skip high bits, too */
   1845   1.53   thorpej 		}
   1846  1.241   msaitoh 		if (i < PCI_MAPREG_END) {
   1847   1.88    briggs 			/*
   1848  1.218   msaitoh 			 * We found PCI_MAPREG_TYPE_IO. Note that 82580
   1849  1.218   msaitoh 			 * (and newer?) chip has no PCI_MAPREG_TYPE_IO.
   1850  1.218   msaitoh 			 * It's no problem because newer chips has no this
   1851  1.218   msaitoh 			 * bug.
   1852  1.218   msaitoh 			 *
   1853   1.88    briggs 			 * The i8254x doesn't apparently respond when the
   1854   1.88    briggs 			 * I/O BAR is 0, which looks somewhat like it's not
   1855   1.88    briggs 			 * been configured.
   1856   1.88    briggs 			 */
   1857   1.88    briggs 			preg = pci_conf_read(pc, pa->pa_tag, i);
   1858   1.88    briggs 			if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
   1859  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1860  1.160  christos 				    "WARNING: I/O BAR at zero.\n");
   1861   1.88    briggs 			} else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
   1862   1.53   thorpej 					0, &sc->sc_iot, &sc->sc_ioh,
   1863  1.212  jakllsch 					NULL, &sc->sc_ios) == 0) {
   1864   1.88    briggs 				sc->sc_flags |= WM_F_IOH_VALID;
   1865   1.88    briggs 			} else {
   1866  1.160  christos 				aprint_error_dev(sc->sc_dev,
   1867  1.160  christos 				    "WARNING: unable to map I/O space\n");
   1868   1.88    briggs 			}
   1869   1.88    briggs 		}
   1870   1.88    briggs 
   1871   1.53   thorpej 	}
   1872   1.53   thorpej 
   1873   1.11   thorpej 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
   1874    1.1   thorpej 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
   1875    1.1   thorpej 	preg |= PCI_COMMAND_MASTER_ENABLE;
   1876   1.11   thorpej 	if (sc->sc_type < WM_T_82542_2_1)
   1877    1.1   thorpej 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
   1878    1.1   thorpej 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
   1879    1.1   thorpej 
   1880  1.122  christos 	/* power up chip */
   1881  1.157    dyoung 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
   1882  1.122  christos 	    NULL)) && error != EOPNOTSUPP) {
   1883  1.160  christos 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
   1884  1.122  christos 		return;
   1885    1.1   thorpej 	}
   1886    1.1   thorpej 
   1887  1.365  knakahar 	wm_adjust_qnum(sc, pci_msix_count(pa->pa_pc, pa->pa_tag));
   1888  1.550   msaitoh 	/*
   1889  1.550   msaitoh 	 *  Don't use MSI-X if we can use only one queue to save interrupt
   1890  1.550   msaitoh 	 * resource.
   1891  1.550   msaitoh 	 */
   1892  1.550   msaitoh 	if (sc->sc_nqueues > 1) {
   1893  1.550   msaitoh 		max_type = PCI_INTR_TYPE_MSIX;
   1894  1.550   msaitoh 		/*
   1895  1.550   msaitoh 		 *  82583 has a MSI-X capability in the PCI configuration space
   1896  1.550   msaitoh 		 * but it doesn't support it. At least the document doesn't
   1897  1.550   msaitoh 		 * say anything about MSI-X.
   1898  1.550   msaitoh 		 */
   1899  1.550   msaitoh 		counts[PCI_INTR_TYPE_MSIX]
   1900  1.550   msaitoh 		    = (sc->sc_type == WM_T_82583) ? 0 : sc->sc_nqueues + 1;
   1901  1.550   msaitoh 	} else {
   1902  1.550   msaitoh 		max_type = PCI_INTR_TYPE_MSI;
   1903  1.550   msaitoh 		counts[PCI_INTR_TYPE_MSIX] = 0;
   1904  1.550   msaitoh 	}
   1905  1.365  knakahar 
   1906  1.340  knakahar 	/* Allocation settings */
   1907  1.340  knakahar 	counts[PCI_INTR_TYPE_MSI] = 1;
   1908  1.340  knakahar 	counts[PCI_INTR_TYPE_INTX] = 1;
   1909  1.508  knakahar 	/* overridden by disable flags */
   1910  1.508  knakahar 	if (wm_disable_msi != 0) {
   1911  1.508  knakahar 		counts[PCI_INTR_TYPE_MSI] = 0;
   1912  1.508  knakahar 		if (wm_disable_msix != 0) {
   1913  1.508  knakahar 			max_type = PCI_INTR_TYPE_INTX;
   1914  1.508  knakahar 			counts[PCI_INTR_TYPE_MSIX] = 0;
   1915  1.508  knakahar 		}
   1916  1.508  knakahar 	} else if (wm_disable_msix != 0) {
   1917  1.508  knakahar 		max_type = PCI_INTR_TYPE_MSI;
   1918  1.508  knakahar 		counts[PCI_INTR_TYPE_MSIX] = 0;
   1919  1.508  knakahar 	}
   1920  1.340  knakahar 
   1921  1.340  knakahar alloc_retry:
   1922  1.340  knakahar 	if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) {
   1923  1.340  knakahar 		aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n");
   1924  1.340  knakahar 		return;
   1925  1.340  knakahar 	}
   1926  1.340  knakahar 
   1927  1.416  knakahar 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) {
   1928  1.360  knakahar 		error = wm_setup_msix(sc);
   1929  1.360  knakahar 		if (error) {
   1930  1.360  knakahar 			pci_intr_release(pc, sc->sc_intrs,
   1931  1.360  knakahar 			    counts[PCI_INTR_TYPE_MSIX]);
   1932  1.360  knakahar 
   1933  1.360  knakahar 			/* Setup for MSI: Disable MSI-X */
   1934  1.360  knakahar 			max_type = PCI_INTR_TYPE_MSI;
   1935  1.360  knakahar 			counts[PCI_INTR_TYPE_MSI] = 1;
   1936  1.360  knakahar 			counts[PCI_INTR_TYPE_INTX] = 1;
   1937  1.360  knakahar 			goto alloc_retry;
   1938  1.335   msaitoh 		}
   1939  1.416  knakahar 	} else 	if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
   1940  1.375   msaitoh 		wm_adjust_qnum(sc, 0);	/* must not use multiqueue */
   1941  1.360  knakahar 		error = wm_setup_legacy(sc);
   1942  1.360  knakahar 		if (error) {
   1943  1.360  knakahar 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
   1944  1.360  knakahar 			    counts[PCI_INTR_TYPE_MSI]);
   1945  1.335   msaitoh 
   1946  1.360  knakahar 			/* The next try is for INTx: Disable MSI */
   1947  1.360  knakahar 			max_type = PCI_INTR_TYPE_INTX;
   1948  1.360  knakahar 			counts[PCI_INTR_TYPE_INTX] = 1;
   1949  1.360  knakahar 			goto alloc_retry;
   1950  1.360  knakahar 		}
   1951  1.340  knakahar 	} else {
   1952  1.375   msaitoh 		wm_adjust_qnum(sc, 0);	/* must not use multiqueue */
   1953  1.360  knakahar 		error = wm_setup_legacy(sc);
   1954  1.360  knakahar 		if (error) {
   1955  1.360  knakahar 			pci_intr_release(sc->sc_pc, sc->sc_intrs,
   1956  1.360  knakahar 			    counts[PCI_INTR_TYPE_INTX]);
   1957  1.360  knakahar 			return;
   1958  1.335   msaitoh 		}
   1959  1.335   msaitoh 	}
   1960   1.52   thorpej 
   1961   1.52   thorpej 	/*
   1962  1.199   msaitoh 	 * Check the function ID (unit number of the chip).
   1963  1.199   msaitoh 	 */
   1964  1.199   msaitoh 	if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3)
   1965  1.199   msaitoh 	    || (sc->sc_type ==  WM_T_82571) || (sc->sc_type == WM_T_80003)
   1966  1.208   msaitoh 	    || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   1967  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   1968  1.265   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   1969  1.199   msaitoh 		sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
   1970  1.199   msaitoh 		    >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK;
   1971  1.199   msaitoh 	else
   1972  1.199   msaitoh 		sc->sc_funcid = 0;
   1973  1.199   msaitoh 
   1974  1.199   msaitoh 	/*
   1975   1.52   thorpej 	 * Determine a few things about the bus we're connected to.
   1976   1.52   thorpej 	 */
   1977   1.52   thorpej 	if (sc->sc_type < WM_T_82543) {
   1978   1.52   thorpej 		/* We don't really know the bus characteristics here. */
   1979   1.52   thorpej 		sc->sc_bus_speed = 33;
   1980   1.73      tron 	} else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
   1981   1.73      tron 		/*
   1982   1.73      tron 		 * CSA (Communication Streaming Architecture) is about as fast
   1983   1.73      tron 		 * a 32-bit 66MHz PCI Bus.
   1984   1.73      tron 		 */
   1985   1.73      tron 		sc->sc_flags |= WM_F_CSA;
   1986   1.73      tron 		sc->sc_bus_speed = 66;
   1987  1.160  christos 		aprint_verbose_dev(sc->sc_dev,
   1988  1.160  christos 		    "Communication Streaming Architecture\n");
   1989   1.78   thorpej 		if (sc->sc_type == WM_T_82547) {
   1990  1.272     ozaki 			callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS);
   1991   1.78   thorpej 			callout_setfunc(&sc->sc_txfifo_ch,
   1992   1.78   thorpej 					wm_82547_txfifo_stall, sc);
   1993  1.160  christos 			aprint_verbose_dev(sc->sc_dev,
   1994  1.160  christos 			    "using 82547 Tx FIFO stall work-around\n");
   1995   1.78   thorpej 		}
   1996  1.116   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   1997  1.139    bouyer 		sc->sc_flags |= WM_F_PCIE;
   1998  1.167   msaitoh 		if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
   1999  1.190   msaitoh 		    && (sc->sc_type != WM_T_ICH10)
   2000  1.221   msaitoh 		    && (sc->sc_type != WM_T_PCH)
   2001  1.249   msaitoh 		    && (sc->sc_type != WM_T_PCH2)
   2002  1.392   msaitoh 		    && (sc->sc_type != WM_T_PCH_LPT)
   2003  1.570   msaitoh 		    && (sc->sc_type != WM_T_PCH_SPT)
   2004  1.570   msaitoh 		    && (sc->sc_type != WM_T_PCH_CNP)) {
   2005  1.221   msaitoh 			/* ICH* and PCH* have no PCIe capability registers */
   2006  1.199   msaitoh 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
   2007  1.199   msaitoh 				PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
   2008  1.199   msaitoh 				NULL) == 0)
   2009  1.199   msaitoh 				aprint_error_dev(sc->sc_dev,
   2010  1.199   msaitoh 				    "unable to find PCIe capability\n");
   2011  1.199   msaitoh 		}
   2012  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
   2013   1.73      tron 	} else {
   2014   1.52   thorpej 		reg = CSR_READ(sc, WMREG_STATUS);
   2015   1.52   thorpej 		if (reg & STATUS_BUS64)
   2016   1.52   thorpej 			sc->sc_flags |= WM_F_BUS64;
   2017  1.176   msaitoh 		if ((reg & STATUS_PCIX_MODE) != 0) {
   2018   1.54   thorpej 			pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
   2019   1.54   thorpej 
   2020   1.52   thorpej 			sc->sc_flags |= WM_F_PCIX;
   2021   1.54   thorpej 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
   2022  1.199   msaitoh 				PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0)
   2023  1.160  christos 				aprint_error_dev(sc->sc_dev,
   2024  1.160  christos 				    "unable to find PCIX capability\n");
   2025   1.54   thorpej 			else if (sc->sc_type != WM_T_82545_3 &&
   2026   1.54   thorpej 				 sc->sc_type != WM_T_82546_3) {
   2027   1.54   thorpej 				/*
   2028   1.54   thorpej 				 * Work around a problem caused by the BIOS
   2029   1.54   thorpej 				 * setting the max memory read byte count
   2030   1.54   thorpej 				 * incorrectly.
   2031   1.54   thorpej 				 */
   2032   1.54   thorpej 				pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
   2033  1.248   msaitoh 				    sc->sc_pcixe_capoff + PCIX_CMD);
   2034   1.54   thorpej 				pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
   2035  1.248   msaitoh 				    sc->sc_pcixe_capoff + PCIX_STATUS);
   2036   1.54   thorpej 
   2037  1.388   msaitoh 				bytecnt = (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >>
   2038  1.248   msaitoh 				    PCIX_CMD_BYTECNT_SHIFT;
   2039  1.388   msaitoh 				maxb = (pcix_sts & PCIX_STATUS_MAXB_MASK) >>
   2040  1.248   msaitoh 				    PCIX_STATUS_MAXB_SHIFT;
   2041   1.54   thorpej 				if (bytecnt > maxb) {
   2042  1.160  christos 					aprint_verbose_dev(sc->sc_dev,
   2043  1.160  christos 					    "resetting PCI-X MMRBC: %d -> %d\n",
   2044   1.54   thorpej 					    512 << bytecnt, 512 << maxb);
   2045   1.54   thorpej 					pcix_cmd = (pcix_cmd &
   2046  1.248   msaitoh 					    ~PCIX_CMD_BYTECNT_MASK) |
   2047  1.248   msaitoh 					   (maxb << PCIX_CMD_BYTECNT_SHIFT);
   2048   1.54   thorpej 					pci_conf_write(pa->pa_pc, pa->pa_tag,
   2049  1.248   msaitoh 					    sc->sc_pcixe_capoff + PCIX_CMD,
   2050   1.54   thorpej 					    pcix_cmd);
   2051   1.54   thorpej 				}
   2052   1.54   thorpej 			}
   2053   1.54   thorpej 		}
   2054   1.52   thorpej 		/*
   2055   1.52   thorpej 		 * The quad port adapter is special; it has a PCIX-PCIX
   2056   1.52   thorpej 		 * bridge on the board, and can run the secondary bus at
   2057   1.52   thorpej 		 * a higher speed.
   2058   1.52   thorpej 		 */
   2059   1.52   thorpej 		if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
   2060   1.52   thorpej 			sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
   2061   1.52   thorpej 								      : 66;
   2062   1.52   thorpej 		} else if (sc->sc_flags & WM_F_PCIX) {
   2063   1.62   thorpej 			switch (reg & STATUS_PCIXSPD_MASK) {
   2064   1.52   thorpej 			case STATUS_PCIXSPD_50_66:
   2065   1.52   thorpej 				sc->sc_bus_speed = 66;
   2066   1.52   thorpej 				break;
   2067   1.52   thorpej 			case STATUS_PCIXSPD_66_100:
   2068   1.52   thorpej 				sc->sc_bus_speed = 100;
   2069   1.52   thorpej 				break;
   2070   1.52   thorpej 			case STATUS_PCIXSPD_100_133:
   2071   1.52   thorpej 				sc->sc_bus_speed = 133;
   2072   1.52   thorpej 				break;
   2073   1.52   thorpej 			default:
   2074  1.160  christos 				aprint_error_dev(sc->sc_dev,
   2075  1.158    cegger 				    "unknown PCIXSPD %d; assuming 66MHz\n",
   2076   1.62   thorpej 				    reg & STATUS_PCIXSPD_MASK);
   2077   1.52   thorpej 				sc->sc_bus_speed = 66;
   2078  1.189   msaitoh 				break;
   2079   1.52   thorpej 			}
   2080   1.52   thorpej 		} else
   2081   1.52   thorpej 			sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
   2082  1.160  christos 		aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n",
   2083   1.52   thorpej 		    (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
   2084   1.52   thorpej 		    (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
   2085   1.52   thorpej 	}
   2086    1.1   thorpej 
   2087  1.552   msaitoh 	/* Disable ASPM L0s and/or L1 for workaround */
   2088  1.552   msaitoh 	wm_disable_aspm(sc);
   2089  1.552   msaitoh 
   2090  1.127    bouyer 	/* clear interesting stat counters */
   2091  1.127    bouyer 	CSR_READ(sc, WMREG_COLC);
   2092  1.127    bouyer 	CSR_READ(sc, WMREG_RXERRC);
   2093  1.127    bouyer 
   2094  1.424   msaitoh 	if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)
   2095  1.424   msaitoh 	    || (sc->sc_type >= WM_T_ICH8))
   2096  1.424   msaitoh 		sc->sc_ich_phymtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2097  1.423   msaitoh 	if (sc->sc_type >= WM_T_ICH8)
   2098  1.423   msaitoh 		sc->sc_ich_nvmmtx = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2099    1.1   thorpej 
   2100  1.423   msaitoh 	/* Set PHY, NVM mutex related stuff */
   2101  1.185   msaitoh 	switch (sc->sc_type) {
   2102  1.185   msaitoh 	case WM_T_82542_2_0:
   2103  1.185   msaitoh 	case WM_T_82542_2_1:
   2104  1.185   msaitoh 	case WM_T_82543:
   2105  1.185   msaitoh 	case WM_T_82544:
   2106  1.185   msaitoh 		/* Microwire */
   2107  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_uwire;
   2108  1.294   msaitoh 		sc->sc_nvm_wordsize = 64;
   2109  1.294   msaitoh 		sc->sc_nvm_addrbits = 6;
   2110  1.185   msaitoh 		break;
   2111  1.185   msaitoh 	case WM_T_82540:
   2112  1.185   msaitoh 	case WM_T_82545:
   2113  1.185   msaitoh 	case WM_T_82545_3:
   2114  1.185   msaitoh 	case WM_T_82546:
   2115  1.185   msaitoh 	case WM_T_82546_3:
   2116  1.185   msaitoh 		/* Microwire */
   2117  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_uwire;
   2118  1.185   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   2119  1.294   msaitoh 		if (reg & EECD_EE_SIZE) {
   2120  1.294   msaitoh 			sc->sc_nvm_wordsize = 256;
   2121  1.294   msaitoh 			sc->sc_nvm_addrbits = 8;
   2122  1.294   msaitoh 		} else {
   2123  1.294   msaitoh 			sc->sc_nvm_wordsize = 64;
   2124  1.294   msaitoh 			sc->sc_nvm_addrbits = 6;
   2125  1.294   msaitoh 		}
   2126  1.275   msaitoh 		sc->sc_flags |= WM_F_LOCK_EECD;
   2127  1.530   msaitoh 		sc->nvm.acquire = wm_get_eecd;
   2128  1.530   msaitoh 		sc->nvm.release = wm_put_eecd;
   2129  1.185   msaitoh 		break;
   2130  1.185   msaitoh 	case WM_T_82541:
   2131  1.185   msaitoh 	case WM_T_82541_2:
   2132  1.185   msaitoh 	case WM_T_82547:
   2133  1.185   msaitoh 	case WM_T_82547_2:
   2134  1.185   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   2135  1.532   msaitoh 		/*
   2136  1.532   msaitoh 		 * wm_nvm_set_addrbits_size_eecd() accesses SPI in it only
   2137  1.532   msaitoh 		 * on 8254[17], so set flags and functios before calling it.
   2138  1.532   msaitoh 		 */
   2139  1.532   msaitoh 		sc->sc_flags |= WM_F_LOCK_EECD;
   2140  1.532   msaitoh 		sc->nvm.acquire = wm_get_eecd;
   2141  1.532   msaitoh 		sc->nvm.release = wm_put_eecd;
   2142  1.185   msaitoh 		if (reg & EECD_EE_TYPE) {
   2143  1.185   msaitoh 			/* SPI */
   2144  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_spi;
   2145  1.294   msaitoh 			sc->sc_flags |= WM_F_EEPROM_SPI;
   2146  1.294   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2147  1.294   msaitoh 		} else {
   2148  1.185   msaitoh 			/* Microwire */
   2149  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_uwire;
   2150  1.294   msaitoh 			if ((reg & EECD_EE_ABITS) != 0) {
   2151  1.294   msaitoh 				sc->sc_nvm_wordsize = 256;
   2152  1.294   msaitoh 				sc->sc_nvm_addrbits = 8;
   2153  1.294   msaitoh 			} else {
   2154  1.294   msaitoh 				sc->sc_nvm_wordsize = 64;
   2155  1.294   msaitoh 				sc->sc_nvm_addrbits = 6;
   2156  1.294   msaitoh 			}
   2157  1.294   msaitoh 		}
   2158  1.185   msaitoh 		break;
   2159  1.185   msaitoh 	case WM_T_82571:
   2160  1.185   msaitoh 	case WM_T_82572:
   2161  1.185   msaitoh 		/* SPI */
   2162  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_eerd;
   2163  1.530   msaitoh 		/* Not use WM_F_LOCK_EECD because we use EERD */
   2164  1.294   msaitoh 		sc->sc_flags |= WM_F_EEPROM_SPI;
   2165  1.294   msaitoh 		wm_nvm_set_addrbits_size_eecd(sc);
   2166  1.424   msaitoh 		sc->phy.acquire = wm_get_swsm_semaphore;
   2167  1.424   msaitoh 		sc->phy.release = wm_put_swsm_semaphore;
   2168  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_82571;
   2169  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_82571;
   2170  1.185   msaitoh 		break;
   2171  1.185   msaitoh 	case WM_T_82573:
   2172  1.185   msaitoh 	case WM_T_82574:
   2173  1.185   msaitoh 	case WM_T_82583:
   2174  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_eerd;
   2175  1.530   msaitoh 		/* Not use WM_F_LOCK_EECD because we use EERD */
   2176  1.424   msaitoh 		if (sc->sc_type == WM_T_82573) {
   2177  1.424   msaitoh 			sc->phy.acquire = wm_get_swsm_semaphore;
   2178  1.424   msaitoh 			sc->phy.release = wm_put_swsm_semaphore;
   2179  1.530   msaitoh 			sc->nvm.acquire = wm_get_nvm_82571;
   2180  1.530   msaitoh 			sc->nvm.release = wm_put_nvm_82571;
   2181  1.424   msaitoh 		} else {
   2182  1.424   msaitoh 			/* Both PHY and NVM use the same semaphore. */
   2183  1.530   msaitoh 			sc->phy.acquire = sc->nvm.acquire
   2184  1.424   msaitoh 			    = wm_get_swfwhw_semaphore;
   2185  1.530   msaitoh 			sc->phy.release = sc->nvm.release
   2186  1.424   msaitoh 			    = wm_put_swfwhw_semaphore;
   2187  1.424   msaitoh 		}
   2188  1.294   msaitoh 		if (wm_nvm_is_onboard_eeprom(sc) == 0) {
   2189  1.185   msaitoh 			sc->sc_flags |= WM_F_EEPROM_FLASH;
   2190  1.294   msaitoh 			sc->sc_nvm_wordsize = 2048;
   2191  1.294   msaitoh 		} else {
   2192  1.185   msaitoh 			/* SPI */
   2193  1.294   msaitoh 			sc->sc_flags |= WM_F_EEPROM_SPI;
   2194  1.294   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2195  1.185   msaitoh 		}
   2196  1.185   msaitoh 		break;
   2197  1.199   msaitoh 	case WM_T_82575:
   2198  1.199   msaitoh 	case WM_T_82576:
   2199  1.199   msaitoh 	case WM_T_82580:
   2200  1.228   msaitoh 	case WM_T_I350:
   2201  1.278   msaitoh 	case WM_T_I354:
   2202  1.185   msaitoh 	case WM_T_80003:
   2203  1.185   msaitoh 		/* SPI */
   2204  1.294   msaitoh 		sc->sc_flags |= WM_F_EEPROM_SPI;
   2205  1.294   msaitoh 		wm_nvm_set_addrbits_size_eecd(sc);
   2206  1.530   msaitoh 		if((sc->sc_type == WM_T_80003)
   2207  1.530   msaitoh 		    || (sc->sc_nvm_wordsize < (1 << 15))) {
   2208  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_eerd;
   2209  1.530   msaitoh 			/* Don't use WM_F_LOCK_EECD because we use EERD */
   2210  1.530   msaitoh 		} else {
   2211  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_spi;
   2212  1.530   msaitoh 			sc->sc_flags |= WM_F_LOCK_EECD;
   2213  1.530   msaitoh 		}
   2214  1.424   msaitoh 		sc->phy.acquire = wm_get_phy_82575;
   2215  1.424   msaitoh 		sc->phy.release = wm_put_phy_82575;
   2216  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_80003;
   2217  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_80003;
   2218  1.185   msaitoh 		break;
   2219  1.185   msaitoh 	case WM_T_ICH8:
   2220  1.185   msaitoh 	case WM_T_ICH9:
   2221  1.185   msaitoh 	case WM_T_ICH10:
   2222  1.190   msaitoh 	case WM_T_PCH:
   2223  1.221   msaitoh 	case WM_T_PCH2:
   2224  1.249   msaitoh 	case WM_T_PCH_LPT:
   2225  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_ich8;
   2226  1.185   msaitoh 		/* FLASH */
   2227  1.530   msaitoh 		sc->sc_flags |= WM_F_EEPROM_FLASH;
   2228  1.294   msaitoh 		sc->sc_nvm_wordsize = 2048;
   2229  1.388   msaitoh 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,WM_ICH8_FLASH);
   2230  1.139    bouyer 		if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
   2231  1.336   msaitoh 		    &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) {
   2232  1.160  christos 			aprint_error_dev(sc->sc_dev,
   2233  1.160  christos 			    "can't map FLASH registers\n");
   2234  1.353  knakahar 			goto out;
   2235  1.139    bouyer 		}
   2236  1.185   msaitoh 		reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
   2237  1.185   msaitoh 		sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *
   2238  1.388   msaitoh 		    ICH_FLASH_SECTOR_SIZE;
   2239  1.199   msaitoh 		sc->sc_ich8_flash_bank_size =
   2240  1.199   msaitoh 		    ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
   2241  1.388   msaitoh 		sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK);
   2242  1.139    bouyer 		sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
   2243  1.139    bouyer 		sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
   2244  1.392   msaitoh 		sc->sc_flashreg_offset = 0;
   2245  1.424   msaitoh 		sc->phy.acquire = wm_get_swflag_ich8lan;
   2246  1.424   msaitoh 		sc->phy.release = wm_put_swflag_ich8lan;
   2247  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_ich8lan;
   2248  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_ich8lan;
   2249  1.392   msaitoh 		break;
   2250  1.392   msaitoh 	case WM_T_PCH_SPT:
   2251  1.570   msaitoh 	case WM_T_PCH_CNP:
   2252  1.530   msaitoh 		sc->nvm.read = wm_nvm_read_spt;
   2253  1.392   msaitoh 		/* SPT has no GFPREG; flash registers mapped through BAR0 */
   2254  1.530   msaitoh 		sc->sc_flags |= WM_F_EEPROM_FLASH;
   2255  1.392   msaitoh 		sc->sc_flasht = sc->sc_st;
   2256  1.392   msaitoh 		sc->sc_flashh = sc->sc_sh;
   2257  1.392   msaitoh 		sc->sc_ich8_flash_base = 0;
   2258  1.392   msaitoh 		sc->sc_nvm_wordsize =
   2259  1.392   msaitoh 			(((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
   2260  1.392   msaitoh 			* NVM_SIZE_MULTIPLIER;
   2261  1.392   msaitoh 		/* It is size in bytes, we want words */
   2262  1.392   msaitoh 		sc->sc_nvm_wordsize /= 2;
   2263  1.392   msaitoh 		/* assume 2 banks */
   2264  1.392   msaitoh 		sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2;
   2265  1.392   msaitoh 		sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET;
   2266  1.424   msaitoh 		sc->phy.acquire = wm_get_swflag_ich8lan;
   2267  1.424   msaitoh 		sc->phy.release = wm_put_swflag_ich8lan;
   2268  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_ich8lan;
   2269  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_ich8lan;
   2270  1.185   msaitoh 		break;
   2271  1.247   msaitoh 	case WM_T_I210:
   2272  1.247   msaitoh 	case WM_T_I211:
   2273  1.533   msaitoh 		/* Allow a single clear of the SW semaphore on I210 and newer*/
   2274  1.533   msaitoh 		sc->sc_flags |= WM_F_WA_I210_CLSEM;
   2275  1.565   msaitoh 		if (wm_nvm_flash_presence_i210(sc)) {
   2276  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_eerd;
   2277  1.530   msaitoh 			/* Don't use WM_F_LOCK_EECD because we use EERD */
   2278  1.530   msaitoh 			sc->sc_flags |= WM_F_EEPROM_FLASH_HW;
   2279  1.321   msaitoh 			wm_nvm_set_addrbits_size_eecd(sc);
   2280  1.321   msaitoh 		} else {
   2281  1.530   msaitoh 			sc->nvm.read = wm_nvm_read_invm;
   2282  1.530   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVM;
   2283  1.321   msaitoh 			sc->sc_nvm_wordsize = INVM_SIZE;
   2284  1.321   msaitoh 		}
   2285  1.424   msaitoh 		sc->phy.acquire = wm_get_phy_82575;
   2286  1.424   msaitoh 		sc->phy.release = wm_put_phy_82575;
   2287  1.530   msaitoh 		sc->nvm.acquire = wm_get_nvm_80003;
   2288  1.530   msaitoh 		sc->nvm.release = wm_put_nvm_80003;
   2289  1.247   msaitoh 		break;
   2290  1.185   msaitoh 	default:
   2291  1.185   msaitoh 		break;
   2292   1.44   thorpej 	}
   2293  1.112     gavan 
   2294  1.273   msaitoh 	/* Ensure the SMBI bit is clear before first NVM or PHY access */
   2295  1.273   msaitoh 	switch (sc->sc_type) {
   2296  1.273   msaitoh 	case WM_T_82571:
   2297  1.273   msaitoh 	case WM_T_82572:
   2298  1.273   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM2);
   2299  1.310   msaitoh 		if ((reg & SWSM2_LOCK) == 0) {
   2300  1.273   msaitoh 			CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);
   2301  1.273   msaitoh 			force_clear_smbi = true;
   2302  1.273   msaitoh 		} else
   2303  1.273   msaitoh 			force_clear_smbi = false;
   2304  1.273   msaitoh 		break;
   2305  1.284   msaitoh 	case WM_T_82573:
   2306  1.284   msaitoh 	case WM_T_82574:
   2307  1.284   msaitoh 	case WM_T_82583:
   2308  1.284   msaitoh 		force_clear_smbi = true;
   2309  1.284   msaitoh 		break;
   2310  1.273   msaitoh 	default:
   2311  1.284   msaitoh 		force_clear_smbi = false;
   2312  1.273   msaitoh 		break;
   2313  1.273   msaitoh 	}
   2314  1.273   msaitoh 	if (force_clear_smbi) {
   2315  1.273   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   2316  1.284   msaitoh 		if ((reg & SWSM_SMBI) != 0)
   2317  1.273   msaitoh 			aprint_error_dev(sc->sc_dev,
   2318  1.273   msaitoh 			    "Please update the Bootagent\n");
   2319  1.273   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI);
   2320  1.273   msaitoh 	}
   2321  1.273   msaitoh 
   2322  1.112     gavan 	/*
   2323  1.112     gavan 	 * Defer printing the EEPROM type until after verifying the checksum
   2324  1.112     gavan 	 * This allows the EEPROM type to be printed correctly in the case
   2325  1.112     gavan 	 * that no EEPROM is attached.
   2326  1.112     gavan 	 */
   2327  1.185   msaitoh 	/*
   2328  1.185   msaitoh 	 * Validate the EEPROM checksum. If the checksum fails, flag
   2329  1.185   msaitoh 	 * this for later, so we can fail future reads from the EEPROM.
   2330  1.185   msaitoh 	 */
   2331  1.280   msaitoh 	if (wm_nvm_validate_checksum(sc)) {
   2332  1.169   msaitoh 		/*
   2333  1.185   msaitoh 		 * Read twice again because some PCI-e parts fail the
   2334  1.185   msaitoh 		 * first check due to the link being in sleep state.
   2335  1.169   msaitoh 		 */
   2336  1.280   msaitoh 		if (wm_nvm_validate_checksum(sc))
   2337  1.185   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVALID;
   2338  1.169   msaitoh 	}
   2339  1.185   msaitoh 
   2340  1.113     gavan 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   2341  1.328   msaitoh 		aprint_verbose_dev(sc->sc_dev, "No EEPROM");
   2342  1.294   msaitoh 	else {
   2343  1.294   msaitoh 		aprint_verbose_dev(sc->sc_dev, "%u words ",
   2344  1.294   msaitoh 		    sc->sc_nvm_wordsize);
   2345  1.321   msaitoh 		if (sc->sc_flags & WM_F_EEPROM_INVM)
   2346  1.328   msaitoh 			aprint_verbose("iNVM");
   2347  1.321   msaitoh 		else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW)
   2348  1.328   msaitoh 			aprint_verbose("FLASH(HW)");
   2349  1.321   msaitoh 		else if (sc->sc_flags & WM_F_EEPROM_FLASH)
   2350  1.328   msaitoh 			aprint_verbose("FLASH");
   2351  1.321   msaitoh 		else {
   2352  1.294   msaitoh 			if (sc->sc_flags & WM_F_EEPROM_SPI)
   2353  1.294   msaitoh 				eetype = "SPI";
   2354  1.294   msaitoh 			else
   2355  1.294   msaitoh 				eetype = "MicroWire";
   2356  1.328   msaitoh 			aprint_verbose("(%d address bits) %s EEPROM",
   2357  1.294   msaitoh 			    sc->sc_nvm_addrbits, eetype);
   2358  1.294   msaitoh 		}
   2359  1.112     gavan 	}
   2360  1.328   msaitoh 	wm_nvm_version(sc);
   2361  1.328   msaitoh 	aprint_verbose("\n");
   2362  1.112     gavan 
   2363  1.527   msaitoh 	/*
   2364  1.527   msaitoh 	 * XXX The first call of wm_gmii_setup_phytype. The result might be
   2365  1.527   msaitoh 	 * incorrect.
   2366  1.527   msaitoh 	 */
   2367  1.527   msaitoh 	wm_gmii_setup_phytype(sc, 0, 0);
   2368  1.527   msaitoh 
   2369  1.527   msaitoh 	/* Reset the chip to a known state. */
   2370  1.527   msaitoh 	wm_reset(sc);
   2371  1.527   msaitoh 
   2372  1.565   msaitoh 	/*
   2373  1.565   msaitoh 	 * Check for I21[01] PLL workaround.
   2374  1.565   msaitoh 	 *
   2375  1.565   msaitoh 	 * Three cases:
   2376  1.565   msaitoh 	 * a) Chip is I211.
   2377  1.565   msaitoh 	 * b) Chip is I210 and it uses INVM (not FLASH).
   2378  1.565   msaitoh 	 * c) Chip is I210 (and it uses FLASH) and the NVM image version < 3.25
   2379  1.565   msaitoh 	 */
   2380  1.565   msaitoh 	if (sc->sc_type == WM_T_I211)
   2381  1.329   msaitoh 		sc->sc_flags |= WM_F_PLL_WA_I210;
   2382  1.565   msaitoh 	if (sc->sc_type == WM_T_I210) {
   2383  1.565   msaitoh 		if (!wm_nvm_flash_presence_i210(sc))
   2384  1.565   msaitoh 			sc->sc_flags |= WM_F_PLL_WA_I210;
   2385  1.565   msaitoh 		else if ((sc->sc_nvm_ver_major < 3)
   2386  1.329   msaitoh 		    || ((sc->sc_nvm_ver_major == 3)
   2387  1.344   msaitoh 			&& (sc->sc_nvm_ver_minor < 25))) {
   2388  1.329   msaitoh 			aprint_verbose_dev(sc->sc_dev,
   2389  1.329   msaitoh 			    "ROM image version %d.%d is older than 3.25\n",
   2390  1.329   msaitoh 			    sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor);
   2391  1.329   msaitoh 			sc->sc_flags |= WM_F_PLL_WA_I210;
   2392  1.329   msaitoh 		}
   2393  1.329   msaitoh 	}
   2394  1.329   msaitoh 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
   2395  1.329   msaitoh 		wm_pll_workaround_i210(sc);
   2396  1.329   msaitoh 
   2397  1.379   msaitoh 	wm_get_wakeup(sc);
   2398  1.446   msaitoh 
   2399  1.446   msaitoh 	/* Non-AMT based hardware can now take control from firmware */
   2400  1.446   msaitoh 	if ((sc->sc_flags & WM_F_HAS_AMT) == 0)
   2401  1.446   msaitoh 		wm_get_hw_control(sc);
   2402  1.379   msaitoh 
   2403  1.113     gavan 	/*
   2404  1.113     gavan 	 * Read the Ethernet address from the EEPROM, if not first found
   2405  1.113     gavan 	 * in device properties.
   2406  1.113     gavan 	 */
   2407  1.195    martin 	ea = prop_dictionary_get(dict, "mac-address");
   2408  1.115   thorpej 	if (ea != NULL) {
   2409  1.115   thorpej 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
   2410  1.115   thorpej 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
   2411  1.115   thorpej 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
   2412  1.115   thorpej 	} else {
   2413  1.210   msaitoh 		if (wm_read_mac_addr(sc, enaddr) != 0) {
   2414  1.160  christos 			aprint_error_dev(sc->sc_dev,
   2415  1.160  christos 			    "unable to read Ethernet address\n");
   2416  1.353  knakahar 			goto out;
   2417  1.210   msaitoh 		}
   2418   1.17   thorpej 	}
   2419   1.17   thorpej 
   2420  1.160  christos 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
   2421    1.1   thorpej 	    ether_sprintf(enaddr));
   2422    1.1   thorpej 
   2423    1.1   thorpej 	/*
   2424    1.1   thorpej 	 * Read the config info from the EEPROM, and set up various
   2425    1.1   thorpej 	 * bits in the control registers based on their contents.
   2426    1.1   thorpej 	 */
   2427  1.182   msaitoh 	pn = prop_dictionary_get(dict, "i82543-cfg1");
   2428  1.115   thorpej 	if (pn != NULL) {
   2429  1.115   thorpej 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2430  1.115   thorpej 		cfg1 = (uint16_t) prop_number_integer_value(pn);
   2431  1.115   thorpej 	} else {
   2432  1.293   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) {
   2433  1.160  christos 			aprint_error_dev(sc->sc_dev, "unable to read CFG1\n");
   2434  1.353  knakahar 			goto out;
   2435  1.113     gavan 		}
   2436   1.51   thorpej 	}
   2437  1.115   thorpej 
   2438  1.182   msaitoh 	pn = prop_dictionary_get(dict, "i82543-cfg2");
   2439  1.115   thorpej 	if (pn != NULL) {
   2440  1.115   thorpej 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2441  1.115   thorpej 		cfg2 = (uint16_t) prop_number_integer_value(pn);
   2442  1.115   thorpej 	} else {
   2443  1.293   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) {
   2444  1.160  christos 			aprint_error_dev(sc->sc_dev, "unable to read CFG2\n");
   2445  1.353  knakahar 			goto out;
   2446  1.113     gavan 		}
   2447   1.51   thorpej 	}
   2448  1.115   thorpej 
   2449  1.203   msaitoh 	/* check for WM_F_WOL */
   2450  1.203   msaitoh 	switch (sc->sc_type) {
   2451  1.203   msaitoh 	case WM_T_82542_2_0:
   2452  1.203   msaitoh 	case WM_T_82542_2_1:
   2453  1.203   msaitoh 	case WM_T_82543:
   2454  1.203   msaitoh 		/* dummy? */
   2455  1.203   msaitoh 		eeprom_data = 0;
   2456  1.293   msaitoh 		apme_mask = NVM_CFG3_APME;
   2457  1.203   msaitoh 		break;
   2458  1.203   msaitoh 	case WM_T_82544:
   2459  1.293   msaitoh 		apme_mask = NVM_CFG2_82544_APM_EN;
   2460  1.203   msaitoh 		eeprom_data = cfg2;
   2461  1.203   msaitoh 		break;
   2462  1.203   msaitoh 	case WM_T_82546:
   2463  1.203   msaitoh 	case WM_T_82546_3:
   2464  1.203   msaitoh 	case WM_T_82571:
   2465  1.203   msaitoh 	case WM_T_82572:
   2466  1.203   msaitoh 	case WM_T_82573:
   2467  1.203   msaitoh 	case WM_T_82574:
   2468  1.203   msaitoh 	case WM_T_82583:
   2469  1.203   msaitoh 	case WM_T_80003:
   2470  1.203   msaitoh 	default:
   2471  1.293   msaitoh 		apme_mask = NVM_CFG3_APME;
   2472  1.293   msaitoh 		wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB
   2473  1.293   msaitoh 		    : NVM_OFF_CFG3_PORTA, 1, &eeprom_data);
   2474  1.203   msaitoh 		break;
   2475  1.203   msaitoh 	case WM_T_82575:
   2476  1.203   msaitoh 	case WM_T_82576:
   2477  1.203   msaitoh 	case WM_T_82580:
   2478  1.228   msaitoh 	case WM_T_I350:
   2479  1.265   msaitoh 	case WM_T_I354: /* XXX ok? */
   2480  1.203   msaitoh 	case WM_T_ICH8:
   2481  1.203   msaitoh 	case WM_T_ICH9:
   2482  1.203   msaitoh 	case WM_T_ICH10:
   2483  1.203   msaitoh 	case WM_T_PCH:
   2484  1.221   msaitoh 	case WM_T_PCH2:
   2485  1.249   msaitoh 	case WM_T_PCH_LPT:
   2486  1.392   msaitoh 	case WM_T_PCH_SPT:
   2487  1.570   msaitoh 	case WM_T_PCH_CNP:
   2488  1.228   msaitoh 		/* XXX The funcid should be checked on some devices */
   2489  1.203   msaitoh 		apme_mask = WUC_APME;
   2490  1.203   msaitoh 		eeprom_data = CSR_READ(sc, WMREG_WUC);
   2491  1.203   msaitoh 		break;
   2492  1.203   msaitoh 	}
   2493  1.203   msaitoh 
   2494  1.203   msaitoh 	/* Check for WM_F_WOL flag after the setting of the EEPROM stuff */
   2495  1.203   msaitoh 	if ((eeprom_data & apme_mask) != 0)
   2496  1.203   msaitoh 		sc->sc_flags |= WM_F_WOL;
   2497  1.203   msaitoh 
   2498  1.325   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) {
   2499  1.325   msaitoh 		/* Check NVM for autonegotiation */
   2500  1.325   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) {
   2501  1.325   msaitoh 			if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0)
   2502  1.325   msaitoh 				sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO;
   2503  1.325   msaitoh 		}
   2504  1.325   msaitoh 	}
   2505  1.325   msaitoh 
   2506  1.203   msaitoh 	/*
   2507  1.203   msaitoh 	 * XXX need special handling for some multiple port cards
   2508  1.203   msaitoh 	 * to disable a paticular port.
   2509  1.203   msaitoh 	 */
   2510  1.203   msaitoh 
   2511   1.51   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2512  1.182   msaitoh 		pn = prop_dictionary_get(dict, "i82543-swdpin");
   2513  1.115   thorpej 		if (pn != NULL) {
   2514  1.115   thorpej 			KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   2515  1.115   thorpej 			swdpin = (uint16_t) prop_number_integer_value(pn);
   2516  1.115   thorpej 		} else {
   2517  1.293   msaitoh 			if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) {
   2518  1.160  christos 				aprint_error_dev(sc->sc_dev,
   2519  1.160  christos 				    "unable to read SWDPIN\n");
   2520  1.353  knakahar 				goto out;
   2521  1.113     gavan 			}
   2522   1.51   thorpej 		}
   2523   1.51   thorpej 	}
   2524    1.1   thorpej 
   2525  1.293   msaitoh 	if (cfg1 & NVM_CFG1_ILOS)
   2526    1.1   thorpej 		sc->sc_ctrl |= CTRL_ILOS;
   2527  1.325   msaitoh 
   2528  1.325   msaitoh 	/*
   2529  1.325   msaitoh 	 * XXX
   2530  1.325   msaitoh 	 * This code isn't correct because pin 2 and 3 are located
   2531  1.325   msaitoh 	 * in different position on newer chips. Check all datasheet.
   2532  1.325   msaitoh 	 *
   2533  1.325   msaitoh 	 * Until resolve this problem, check if a chip < 82580
   2534  1.325   msaitoh 	 */
   2535  1.325   msaitoh 	if (sc->sc_type <= WM_T_82580) {
   2536  1.325   msaitoh 		if (sc->sc_type >= WM_T_82544) {
   2537  1.325   msaitoh 			sc->sc_ctrl |=
   2538  1.325   msaitoh 			    ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
   2539  1.325   msaitoh 			    CTRL_SWDPIO_SHIFT;
   2540  1.325   msaitoh 			sc->sc_ctrl |=
   2541  1.325   msaitoh 			    ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
   2542  1.325   msaitoh 			    CTRL_SWDPINS_SHIFT;
   2543  1.325   msaitoh 		} else {
   2544  1.325   msaitoh 			sc->sc_ctrl |=
   2545  1.325   msaitoh 			    ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) <<
   2546  1.325   msaitoh 			    CTRL_SWDPIO_SHIFT;
   2547  1.325   msaitoh 		}
   2548  1.325   msaitoh 	}
   2549  1.325   msaitoh 
   2550  1.325   msaitoh 	/* XXX For other than 82580? */
   2551  1.325   msaitoh 	if (sc->sc_type == WM_T_82580) {
   2552  1.325   msaitoh 		wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword);
   2553  1.389   msaitoh 		if (nvmword & __BIT(13))
   2554  1.325   msaitoh 			sc->sc_ctrl |= CTRL_ILOS;
   2555    1.1   thorpej 	}
   2556    1.1   thorpej 
   2557    1.1   thorpej #if 0
   2558   1.11   thorpej 	if (sc->sc_type >= WM_T_82544) {
   2559  1.293   msaitoh 		if (cfg1 & NVM_CFG1_IPS0)
   2560    1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
   2561  1.293   msaitoh 		if (cfg1 & NVM_CFG1_IPS1)
   2562    1.1   thorpej 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
   2563    1.1   thorpej 		sc->sc_ctrl_ext |=
   2564  1.293   msaitoh 		    ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
   2565    1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
   2566    1.1   thorpej 		sc->sc_ctrl_ext |=
   2567  1.293   msaitoh 		    ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
   2568    1.1   thorpej 		    CTRL_EXT_SWDPINS_SHIFT;
   2569    1.1   thorpej 	} else {
   2570    1.1   thorpej 		sc->sc_ctrl_ext |=
   2571  1.293   msaitoh 		    ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) <<
   2572    1.1   thorpej 		    CTRL_EXT_SWDPIO_SHIFT;
   2573    1.1   thorpej 	}
   2574    1.1   thorpej #endif
   2575    1.1   thorpej 
   2576    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2577    1.1   thorpej #if 0
   2578    1.1   thorpej 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   2579    1.1   thorpej #endif
   2580    1.1   thorpej 
   2581  1.192   msaitoh 	if (sc->sc_type == WM_T_PCH) {
   2582  1.192   msaitoh 		uint16_t val;
   2583  1.192   msaitoh 
   2584  1.192   msaitoh 		/* Save the NVM K1 bit setting */
   2585  1.293   msaitoh 		wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val);
   2586  1.192   msaitoh 
   2587  1.293   msaitoh 		if ((val & NVM_K1_CONFIG_ENABLE) != 0)
   2588  1.192   msaitoh 			sc->sc_nvm_k1_enabled = 1;
   2589  1.192   msaitoh 		else
   2590  1.192   msaitoh 			sc->sc_nvm_k1_enabled = 0;
   2591  1.192   msaitoh 	}
   2592  1.192   msaitoh 
   2593  1.529   msaitoh 	/* Determine if we're GMII, TBI, SERDES or SGMII mode */
   2594  1.144   msaitoh 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
   2595  1.190   msaitoh 	    || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
   2596  1.249   msaitoh 	    || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
   2597  1.570   msaitoh 	    || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_PCH_CNP
   2598  1.570   msaitoh 	    || sc->sc_type == WM_T_82573
   2599  1.185   msaitoh 	    || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
   2600  1.529   msaitoh 		/* Copper only */
   2601  1.457   msaitoh 	} else if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   2602  1.457   msaitoh 	    || (sc->sc_type ==WM_T_82580) || (sc->sc_type ==WM_T_I350)
   2603  1.457   msaitoh 	    || (sc->sc_type ==WM_T_I354) || (sc->sc_type ==WM_T_I210)
   2604  1.457   msaitoh 	    || (sc->sc_type ==WM_T_I211)) {
   2605  1.457   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   2606  1.457   msaitoh 		link_mode = reg & CTRL_EXT_LINK_MODE_MASK;
   2607  1.457   msaitoh 		switch (link_mode) {
   2608  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_1000KX:
   2609  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "1000KX\n");
   2610  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_SERDES;
   2611  1.457   msaitoh 			break;
   2612  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_SGMII:
   2613  1.457   msaitoh 			if (wm_sgmii_uses_mdio(sc)) {
   2614  1.457   msaitoh 				aprint_verbose_dev(sc->sc_dev,
   2615  1.457   msaitoh 				    "SGMII(MDIO)\n");
   2616  1.457   msaitoh 				sc->sc_flags |= WM_F_SGMII;
   2617  1.457   msaitoh 				sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2618  1.199   msaitoh 				break;
   2619  1.457   msaitoh 			}
   2620  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n");
   2621  1.457   msaitoh 			/*FALLTHROUGH*/
   2622  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_PCIE_SERDES:
   2623  1.457   msaitoh 			sc->sc_mediatype = wm_sfp_get_media_type(sc);
   2624  1.457   msaitoh 			if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) {
   2625  1.457   msaitoh 				if (link_mode
   2626  1.457   msaitoh 				    == CTRL_EXT_LINK_MODE_SGMII) {
   2627  1.457   msaitoh 					sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2628  1.265   msaitoh 					sc->sc_flags |= WM_F_SGMII;
   2629  1.457   msaitoh 				} else {
   2630  1.457   msaitoh 					sc->sc_mediatype = WM_MEDIATYPE_SERDES;
   2631  1.292   msaitoh 					aprint_verbose_dev(sc->sc_dev,
   2632  1.292   msaitoh 					    "SERDES\n");
   2633  1.457   msaitoh 				}
   2634  1.457   msaitoh 				break;
   2635  1.457   msaitoh 			}
   2636  1.457   msaitoh 			if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   2637  1.457   msaitoh 				aprint_verbose_dev(sc->sc_dev, "SERDES\n");
   2638  1.292   msaitoh 
   2639  1.457   msaitoh 			/* Change current link mode setting */
   2640  1.457   msaitoh 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
   2641  1.457   msaitoh 			switch (sc->sc_mediatype) {
   2642  1.457   msaitoh 			case WM_MEDIATYPE_COPPER:
   2643  1.457   msaitoh 				reg |= CTRL_EXT_LINK_MODE_SGMII;
   2644  1.457   msaitoh 				break;
   2645  1.457   msaitoh 			case WM_MEDIATYPE_SERDES:
   2646  1.457   msaitoh 				reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES;
   2647  1.199   msaitoh 				break;
   2648  1.199   msaitoh 			default:
   2649  1.199   msaitoh 				break;
   2650  1.199   msaitoh 			}
   2651  1.292   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   2652  1.199   msaitoh 			break;
   2653  1.457   msaitoh 		case CTRL_EXT_LINK_MODE_GMII:
   2654  1.199   msaitoh 		default:
   2655  1.457   msaitoh 			aprint_verbose_dev(sc->sc_dev, "Copper\n");
   2656  1.311   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2657  1.457   msaitoh 			break;
   2658  1.457   msaitoh 		}
   2659  1.457   msaitoh 
   2660  1.457   msaitoh 		reg &= ~CTRL_EXT_I2C_ENA;
   2661  1.457   msaitoh 		if ((sc->sc_flags & WM_F_SGMII) != 0)
   2662  1.457   msaitoh 			reg |= CTRL_EXT_I2C_ENA;
   2663  1.457   msaitoh 		else
   2664  1.457   msaitoh 			reg &= ~CTRL_EXT_I2C_ENA;
   2665  1.457   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   2666  1.457   msaitoh 	} else if (sc->sc_type < WM_T_82543 ||
   2667  1.457   msaitoh 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
   2668  1.457   msaitoh 		if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) {
   2669  1.457   msaitoh 			aprint_error_dev(sc->sc_dev,
   2670  1.457   msaitoh 			    "WARNING: TBIMODE set on 1000BASE-T product!\n");
   2671  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_FIBER;
   2672  1.457   msaitoh 		}
   2673  1.457   msaitoh 	} else {
   2674  1.457   msaitoh 		if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) {
   2675  1.457   msaitoh 			aprint_error_dev(sc->sc_dev,
   2676  1.457   msaitoh 			    "WARNING: TBIMODE clear on 1000BASE-X product!\n");
   2677  1.457   msaitoh 			sc->sc_mediatype = WM_MEDIATYPE_COPPER;
   2678  1.199   msaitoh 		}
   2679    1.1   thorpej 	}
   2680  1.513   msaitoh 	snprintb(buf, sizeof(buf), WM_FLAGS, sc->sc_flags);
   2681  1.513   msaitoh 	aprint_verbose_dev(sc->sc_dev, "%s\n", buf);
   2682    1.1   thorpej 
   2683  1.527   msaitoh 	/* Set device properties (macflags) */
   2684  1.527   msaitoh 	prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags);
   2685  1.527   msaitoh 
   2686  1.529   msaitoh 	/* Initialize the media structures accordingly. */
   2687  1.529   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_COPPER)
   2688  1.529   msaitoh 		wm_gmii_mediainit(sc, wmp->wmp_product);
   2689  1.529   msaitoh 	else
   2690  1.529   msaitoh 		wm_tbi_mediainit(sc); /* All others */
   2691  1.529   msaitoh 
   2692    1.1   thorpej 	ifp = &sc->sc_ethercom.ec_if;
   2693  1.160  christos 	xname = device_xname(sc->sc_dev);
   2694  1.160  christos 	strlcpy(ifp->if_xname, xname, IFNAMSIZ);
   2695    1.1   thorpej 	ifp->if_softc = sc;
   2696    1.1   thorpej 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   2697  1.492  knakahar #ifdef WM_MPSAFE
   2698  1.543     ozaki 	ifp->if_extflags = IFEF_MPSAFE;
   2699  1.492  knakahar #endif
   2700    1.1   thorpej 	ifp->if_ioctl = wm_ioctl;
   2701  1.403  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   2702  1.232    bouyer 		ifp->if_start = wm_nq_start;
   2703  1.503  knakahar 		/*
   2704  1.503  knakahar 		 * When the number of CPUs is one and the controller can use
   2705  1.505  knakahar 		 * MSI-X, wm(4) use MSI-X but *does not* use multiqueue.
   2706  1.503  knakahar 		 * That is, wm(4) use two interrupts, one is used for Tx/Rx
   2707  1.503  knakahar 		 * and the other is used for link status changing.
   2708  1.503  knakahar 		 * In this situation, wm_nq_transmit() is disadvantageous
   2709  1.503  knakahar 		 * because of wm_select_txqueue() and pcq(9) overhead.
   2710  1.503  knakahar 		 */
   2711  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   2712  1.403  knakahar 			ifp->if_transmit = wm_nq_transmit;
   2713  1.454  knakahar 	} else {
   2714  1.232    bouyer 		ifp->if_start = wm_start;
   2715  1.503  knakahar 		/*
   2716  1.503  knakahar 		 * wm_transmit() has the same disadvantage as wm_transmit().
   2717  1.503  knakahar 		 */
   2718  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   2719  1.454  knakahar 			ifp->if_transmit = wm_transmit;
   2720  1.454  knakahar 	}
   2721  1.562  knakahar 	/* wm(4) doest not use ifp->if_watchdog, use wm_tick as watchdog. */
   2722    1.1   thorpej 	ifp->if_init = wm_init;
   2723    1.1   thorpej 	ifp->if_stop = wm_stop;
   2724   1.58     ragge 	IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
   2725    1.1   thorpej 	IFQ_SET_READY(&ifp->if_snd);
   2726    1.1   thorpej 
   2727  1.187   msaitoh 	/* Check for jumbo frame */
   2728  1.187   msaitoh 	switch (sc->sc_type) {
   2729  1.187   msaitoh 	case WM_T_82573:
   2730  1.187   msaitoh 		/* XXX limited to 9234 if ASPM is disabled */
   2731  1.325   msaitoh 		wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword);
   2732  1.325   msaitoh 		if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0)
   2733  1.187   msaitoh 			sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2734  1.187   msaitoh 		break;
   2735  1.187   msaitoh 	case WM_T_82571:
   2736  1.187   msaitoh 	case WM_T_82572:
   2737  1.187   msaitoh 	case WM_T_82574:
   2738  1.546   msaitoh 	case WM_T_82583:
   2739  1.199   msaitoh 	case WM_T_82575:
   2740  1.199   msaitoh 	case WM_T_82576:
   2741  1.199   msaitoh 	case WM_T_82580:
   2742  1.228   msaitoh 	case WM_T_I350:
   2743  1.546   msaitoh 	case WM_T_I354:
   2744  1.247   msaitoh 	case WM_T_I210:
   2745  1.247   msaitoh 	case WM_T_I211:
   2746  1.187   msaitoh 	case WM_T_80003:
   2747  1.187   msaitoh 	case WM_T_ICH9:
   2748  1.187   msaitoh 	case WM_T_ICH10:
   2749  1.221   msaitoh 	case WM_T_PCH2:	/* PCH2 supports 9K frame size */
   2750  1.249   msaitoh 	case WM_T_PCH_LPT:
   2751  1.392   msaitoh 	case WM_T_PCH_SPT:
   2752  1.570   msaitoh 	case WM_T_PCH_CNP:
   2753  1.187   msaitoh 		/* XXX limited to 9234 */
   2754  1.120   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2755  1.187   msaitoh 		break;
   2756  1.190   msaitoh 	case WM_T_PCH:
   2757  1.190   msaitoh 		/* XXX limited to 4096 */
   2758  1.190   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2759  1.190   msaitoh 		break;
   2760  1.187   msaitoh 	case WM_T_82542_2_0:
   2761  1.187   msaitoh 	case WM_T_82542_2_1:
   2762  1.187   msaitoh 	case WM_T_ICH8:
   2763  1.187   msaitoh 		/* No support for jumbo frame */
   2764  1.187   msaitoh 		break;
   2765  1.187   msaitoh 	default:
   2766  1.187   msaitoh 		/* ETHER_MAX_LEN_JUMBO */
   2767  1.187   msaitoh 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   2768  1.187   msaitoh 		break;
   2769  1.187   msaitoh 	}
   2770   1.41       tls 
   2771  1.281   msaitoh 	/* If we're a i82543 or greater, we can support VLANs. */
   2772  1.233   msaitoh 	if (sc->sc_type >= WM_T_82543)
   2773    1.1   thorpej 		sc->sc_ethercom.ec_capabilities |=
   2774  1.172    darran 		    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
   2775    1.1   thorpej 
   2776    1.1   thorpej 	/*
   2777    1.1   thorpej 	 * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
   2778   1.11   thorpej 	 * on i82543 and later.
   2779    1.1   thorpej 	 */
   2780  1.130      yamt 	if (sc->sc_type >= WM_T_82543) {
   2781    1.1   thorpej 		ifp->if_capabilities |=
   2782  1.103      yamt 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
   2783  1.103      yamt 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   2784  1.107      yamt 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
   2785  1.107      yamt 		    IFCAP_CSUM_TCPv6_Tx |
   2786  1.107      yamt 		    IFCAP_CSUM_UDPv6_Tx;
   2787  1.130      yamt 	}
   2788  1.130      yamt 
   2789  1.130      yamt 	/*
   2790  1.130      yamt 	 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL.
   2791  1.130      yamt 	 *
   2792  1.130      yamt 	 *	82541GI (8086:1076) ... no
   2793  1.130      yamt 	 *	82572EI (8086:10b9) ... yes
   2794  1.130      yamt 	 */
   2795  1.130      yamt 	if (sc->sc_type >= WM_T_82571) {
   2796  1.130      yamt 		ifp->if_capabilities |=
   2797  1.130      yamt 		    IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx;
   2798  1.130      yamt 	}
   2799    1.1   thorpej 
   2800  1.198   msaitoh 	/*
   2801   1.99      matt 	 * If we're a i82544 or greater (except i82547), we can do
   2802   1.99      matt 	 * TCP segmentation offload.
   2803   1.99      matt 	 */
   2804  1.131      yamt 	if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) {
   2805   1.99      matt 		ifp->if_capabilities |= IFCAP_TSOv4;
   2806  1.131      yamt 	}
   2807  1.131      yamt 
   2808  1.131      yamt 	if (sc->sc_type >= WM_T_82571) {
   2809  1.131      yamt 		ifp->if_capabilities |= IFCAP_TSOv6;
   2810  1.131      yamt 	}
   2811   1.99      matt 
   2812  1.557  knakahar 	sc->sc_tx_process_limit = WM_TX_PROCESS_LIMIT_DEFAULT;
   2813  1.557  knakahar 	sc->sc_tx_intr_process_limit = WM_TX_INTR_PROCESS_LIMIT_DEFAULT;
   2814  1.493  knakahar 	sc->sc_rx_process_limit = WM_RX_PROCESS_LIMIT_DEFAULT;
   2815  1.493  knakahar 	sc->sc_rx_intr_process_limit = WM_RX_INTR_PROCESS_LIMIT_DEFAULT;
   2816  1.493  knakahar 
   2817  1.272     ozaki #ifdef WM_MPSAFE
   2818  1.357  knakahar 	sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   2819  1.272     ozaki #else
   2820  1.357  knakahar 	sc->sc_core_lock = NULL;
   2821  1.272     ozaki #endif
   2822  1.272     ozaki 
   2823  1.281   msaitoh 	/* Attach the interface. */
   2824  1.541   msaitoh 	error = if_initialize(ifp);
   2825  1.541   msaitoh 	if (error != 0) {
   2826  1.541   msaitoh 		aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n",
   2827  1.541   msaitoh 		    error);
   2828  1.541   msaitoh 		return; /* Error */
   2829  1.541   msaitoh 	}
   2830  1.391     ozaki 	sc->sc_ipq = if_percpuq_create(&sc->sc_ethercom.ec_if);
   2831    1.1   thorpej 	ether_ifattach(ifp, enaddr);
   2832  1.391     ozaki 	if_register(ifp);
   2833  1.213   msaitoh 	ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb);
   2834  1.289       tls 	rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET,
   2835  1.289       tls 			  RND_FLAG_DEFAULT);
   2836    1.1   thorpej 
   2837    1.1   thorpej #ifdef WM_EVENT_COUNTERS
   2838    1.1   thorpej 	/* Attach event counters. */
   2839    1.1   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
   2840  1.160  christos 	    NULL, xname, "linkintr");
   2841    1.1   thorpej 
   2842   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
   2843  1.160  christos 	    NULL, xname, "tx_xoff");
   2844   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
   2845  1.160  christos 	    NULL, xname, "tx_xon");
   2846   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
   2847  1.160  christos 	    NULL, xname, "rx_xoff");
   2848   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
   2849  1.160  christos 	    NULL, xname, "rx_xon");
   2850   1.71   thorpej 	evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
   2851  1.160  christos 	    NULL, xname, "rx_macctl");
   2852    1.1   thorpej #endif /* WM_EVENT_COUNTERS */
   2853    1.1   thorpej 
   2854  1.203   msaitoh 	if (pmf_device_register(self, wm_suspend, wm_resume))
   2855  1.180   tsutsui 		pmf_class_network_register(self, ifp);
   2856  1.180   tsutsui 	else
   2857  1.149  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
   2858  1.123  jmcneill 
   2859  1.290   msaitoh 	sc->sc_flags |= WM_F_ATTACHED;
   2860  1.353  knakahar  out:
   2861    1.1   thorpej 	return;
   2862    1.1   thorpej }
   2863    1.1   thorpej 
   2864  1.280   msaitoh /* The detach function (ca_detach) */
   2865  1.201   msaitoh static int
   2866  1.201   msaitoh wm_detach(device_t self, int flags __unused)
   2867  1.201   msaitoh {
   2868  1.201   msaitoh 	struct wm_softc *sc = device_private(self);
   2869  1.201   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2870  1.272     ozaki 	int i;
   2871  1.201   msaitoh 
   2872  1.290   msaitoh 	if ((sc->sc_flags & WM_F_ATTACHED) == 0)
   2873  1.290   msaitoh 		return 0;
   2874  1.290   msaitoh 
   2875  1.201   msaitoh 	/* Stop the interface. Callouts are stopped in it. */
   2876  1.201   msaitoh 	wm_stop(ifp, 1);
   2877  1.272     ozaki 
   2878  1.201   msaitoh 	pmf_device_deregister(self);
   2879  1.201   msaitoh 
   2880  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   2881  1.477  knakahar 	evcnt_detach(&sc->sc_ev_linkintr);
   2882  1.477  knakahar 
   2883  1.477  knakahar 	evcnt_detach(&sc->sc_ev_tx_xoff);
   2884  1.477  knakahar 	evcnt_detach(&sc->sc_ev_tx_xon);
   2885  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_xoff);
   2886  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_xon);
   2887  1.477  knakahar 	evcnt_detach(&sc->sc_ev_rx_macctl);
   2888  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   2889  1.477  knakahar 
   2890  1.201   msaitoh 	/* Tell the firmware about the release */
   2891  1.357  knakahar 	WM_CORE_LOCK(sc);
   2892  1.201   msaitoh 	wm_release_manageability(sc);
   2893  1.212  jakllsch 	wm_release_hw_control(sc);
   2894  1.439   msaitoh 	wm_enable_wakeup(sc);
   2895  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   2896  1.201   msaitoh 
   2897  1.201   msaitoh 	mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
   2898  1.201   msaitoh 
   2899  1.201   msaitoh 	/* Delete all remaining media. */
   2900  1.201   msaitoh 	ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
   2901  1.201   msaitoh 
   2902  1.201   msaitoh 	ether_ifdetach(ifp);
   2903  1.201   msaitoh 	if_detach(ifp);
   2904  1.391     ozaki 	if_percpuq_destroy(sc->sc_ipq);
   2905  1.201   msaitoh 
   2906  1.246  christos 	/* Unload RX dmamaps and free mbufs */
   2907  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   2908  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   2909  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   2910  1.364  knakahar 		wm_rxdrain(rxq);
   2911  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   2912  1.364  knakahar 	}
   2913  1.272     ozaki 	/* Must unlock here */
   2914  1.201   msaitoh 
   2915  1.201   msaitoh 	/* Disestablish the interrupt handler */
   2916  1.335   msaitoh 	for (i = 0; i < sc->sc_nintrs; i++) {
   2917  1.335   msaitoh 		if (sc->sc_ihs[i] != NULL) {
   2918  1.335   msaitoh 			pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]);
   2919  1.335   msaitoh 			sc->sc_ihs[i] = NULL;
   2920  1.335   msaitoh 		}
   2921  1.201   msaitoh 	}
   2922  1.335   msaitoh 	pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs);
   2923  1.201   msaitoh 
   2924  1.396  knakahar 	wm_free_txrx_queues(sc);
   2925  1.396  knakahar 
   2926  1.212  jakllsch 	/* Unmap the registers */
   2927  1.201   msaitoh 	if (sc->sc_ss) {
   2928  1.201   msaitoh 		bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss);
   2929  1.201   msaitoh 		sc->sc_ss = 0;
   2930  1.201   msaitoh 	}
   2931  1.212  jakllsch 	if (sc->sc_ios) {
   2932  1.212  jakllsch 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
   2933  1.212  jakllsch 		sc->sc_ios = 0;
   2934  1.212  jakllsch 	}
   2935  1.336   msaitoh 	if (sc->sc_flashs) {
   2936  1.336   msaitoh 		bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs);
   2937  1.336   msaitoh 		sc->sc_flashs = 0;
   2938  1.336   msaitoh 	}
   2939  1.201   msaitoh 
   2940  1.357  knakahar 	if (sc->sc_core_lock)
   2941  1.357  knakahar 		mutex_obj_free(sc->sc_core_lock);
   2942  1.424   msaitoh 	if (sc->sc_ich_phymtx)
   2943  1.424   msaitoh 		mutex_obj_free(sc->sc_ich_phymtx);
   2944  1.423   msaitoh 	if (sc->sc_ich_nvmmtx)
   2945  1.423   msaitoh 		mutex_obj_free(sc->sc_ich_nvmmtx);
   2946  1.272     ozaki 
   2947  1.201   msaitoh 	return 0;
   2948  1.201   msaitoh }
   2949  1.201   msaitoh 
   2950  1.281   msaitoh static bool
   2951  1.281   msaitoh wm_suspend(device_t self, const pmf_qual_t *qual)
   2952  1.281   msaitoh {
   2953  1.281   msaitoh 	struct wm_softc *sc = device_private(self);
   2954  1.281   msaitoh 
   2955  1.281   msaitoh 	wm_release_manageability(sc);
   2956  1.281   msaitoh 	wm_release_hw_control(sc);
   2957  1.281   msaitoh 	wm_enable_wakeup(sc);
   2958  1.281   msaitoh 
   2959  1.281   msaitoh 	return true;
   2960  1.281   msaitoh }
   2961  1.281   msaitoh 
   2962  1.281   msaitoh static bool
   2963  1.281   msaitoh wm_resume(device_t self, const pmf_qual_t *qual)
   2964  1.281   msaitoh {
   2965  1.281   msaitoh 	struct wm_softc *sc = device_private(self);
   2966  1.281   msaitoh 
   2967  1.552   msaitoh 	/* Disable ASPM L0s and/or L1 for workaround */
   2968  1.552   msaitoh 	wm_disable_aspm(sc);
   2969  1.281   msaitoh 	wm_init_manageability(sc);
   2970  1.281   msaitoh 
   2971  1.281   msaitoh 	return true;
   2972  1.281   msaitoh }
   2973  1.281   msaitoh 
   2974    1.1   thorpej /*
   2975  1.281   msaitoh  * wm_watchdog:		[ifnet interface function]
   2976    1.1   thorpej  *
   2977  1.281   msaitoh  *	Watchdog timer handler.
   2978    1.1   thorpej  */
   2979  1.281   msaitoh static void
   2980  1.281   msaitoh wm_watchdog(struct ifnet *ifp)
   2981    1.1   thorpej {
   2982  1.403  knakahar 	int qid;
   2983  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   2984  1.562  knakahar 	uint16_t hang_queue = 0; /* Max queue number of wm(4) is 82576's 16. */
   2985  1.403  knakahar 
   2986  1.405  knakahar 	for (qid = 0; qid < sc->sc_nqueues; qid++) {
   2987  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[qid].wmq_txq;
   2988  1.403  knakahar 
   2989  1.562  knakahar 		wm_watchdog_txq(ifp, txq, &hang_queue);
   2990  1.403  knakahar 	}
   2991  1.403  knakahar 
   2992  1.403  knakahar 	/*
   2993  1.562  knakahar 	 * IF any of queues hanged up, reset the interface.
   2994  1.403  knakahar 	 */
   2995  1.562  knakahar 	if (hang_queue != 0) {
   2996  1.562  knakahar 		(void) wm_init(ifp);
   2997  1.562  knakahar 
   2998  1.562  knakahar 		/*
   2999  1.562  knakahar 		 * There are still some upper layer processing which call
   3000  1.562  knakahar 		 * ifp->if_start(). e.g. ALTQ or one CPU system
   3001  1.562  knakahar 		 */
   3002  1.562  knakahar 		/* Try to get more packets going. */
   3003  1.562  knakahar 		ifp->if_start(ifp);
   3004  1.562  knakahar 	}
   3005  1.403  knakahar }
   3006  1.403  knakahar 
   3007  1.562  knakahar 
   3008  1.403  knakahar static void
   3009  1.562  knakahar wm_watchdog_txq(struct ifnet *ifp, struct wm_txqueue *txq, uint16_t *hang)
   3010  1.403  knakahar {
   3011  1.555  knakahar 
   3012  1.555  knakahar 	mutex_enter(txq->txq_lock);
   3013  1.576   msaitoh 	if (txq->txq_sending &&
   3014  1.562  knakahar 	    time_uptime - txq->txq_lastsent > wm_watchdog_timeout) {
   3015  1.562  knakahar 		wm_watchdog_txq_locked(ifp, txq, hang);
   3016  1.562  knakahar 	}
   3017  1.555  knakahar 	mutex_exit(txq->txq_lock);
   3018  1.555  knakahar }
   3019  1.555  knakahar 
   3020  1.555  knakahar static void
   3021  1.573   msaitoh wm_watchdog_txq_locked(struct ifnet *ifp, struct wm_txqueue *txq,
   3022  1.573   msaitoh     uint16_t *hang)
   3023  1.555  knakahar {
   3024  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   3025  1.562  knakahar 	struct wm_queue *wmq = container_of(txq, struct wm_queue, wmq_txq);
   3026    1.1   thorpej 
   3027  1.555  knakahar 	KASSERT(mutex_owned(txq->txq_lock));
   3028  1.555  knakahar 
   3029    1.1   thorpej 	/*
   3030  1.281   msaitoh 	 * Since we're using delayed interrupts, sweep up
   3031  1.281   msaitoh 	 * before we report an error.
   3032    1.1   thorpej 	 */
   3033  1.557  knakahar 	wm_txeof(txq, UINT_MAX);
   3034  1.281   msaitoh 
   3035  1.576   msaitoh 	if (txq->txq_sending)
   3036  1.576   msaitoh 		*hang |= __BIT(wmq->wmq_id);
   3037  1.576   msaitoh 
   3038  1.576   msaitoh 	if (txq->txq_free == WM_NTXDESC(txq)) {
   3039  1.576   msaitoh 		log(LOG_ERR, "%s: device timeout (lost interrupt)\n",
   3040  1.576   msaitoh 		    device_xname(sc->sc_dev));
   3041  1.576   msaitoh 	} else {
   3042  1.281   msaitoh #ifdef WM_DEBUG
   3043  1.281   msaitoh 		int i, j;
   3044  1.281   msaitoh 		struct wm_txsoft *txs;
   3045  1.281   msaitoh #endif
   3046  1.281   msaitoh 		log(LOG_ERR,
   3047  1.281   msaitoh 		    "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
   3048  1.356  knakahar 		    device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree,
   3049  1.356  knakahar 		    txq->txq_next);
   3050  1.281   msaitoh 		ifp->if_oerrors++;
   3051  1.281   msaitoh #ifdef WM_DEBUG
   3052  1.366  knakahar 		for (i = txq->txq_sdirty; i != txq->txq_snext ;
   3053  1.356  knakahar 		    i = WM_NEXTTXS(txq, i)) {
   3054  1.366  knakahar 		    txs = &txq->txq_soft[i];
   3055  1.281   msaitoh 		    printf("txs %d tx %d -> %d\n",
   3056  1.281   msaitoh 			i, txs->txs_firstdesc, txs->txs_lastdesc);
   3057  1.281   msaitoh 		    for (j = txs->txs_firstdesc; ;
   3058  1.356  knakahar 			j = WM_NEXTTX(txq, j)) {
   3059  1.553  knakahar 			    if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   3060  1.553  knakahar 				    printf("\tdesc %d: 0x%" PRIx64 "\n", j,
   3061  1.553  knakahar 					txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
   3062  1.553  knakahar 				    printf("\t %#08x%08x\n",
   3063  1.553  knakahar 					txq->txq_nq_descs[j].nqtx_data.nqtxd_fields,
   3064  1.553  knakahar 					txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen);
   3065  1.553  knakahar 			    } else {
   3066  1.553  knakahar 				    printf("\tdesc %d: 0x%" PRIx64 "\n", j,
   3067  1.553  knakahar 					(uint64_t)txq->txq_descs[j].wtx_addr.wa_high << 32 |
   3068  1.553  knakahar 					txq->txq_descs[j].wtx_addr.wa_low);
   3069  1.553  knakahar 				    printf("\t %#04x%02x%02x%08x\n",
   3070  1.553  knakahar 					txq->txq_descs[j].wtx_fields.wtxu_vlan,
   3071  1.553  knakahar 					txq->txq_descs[j].wtx_fields.wtxu_options,
   3072  1.553  knakahar 					txq->txq_descs[j].wtx_fields.wtxu_status,
   3073  1.553  knakahar 					txq->txq_descs[j].wtx_cmdlen);
   3074  1.553  knakahar 			    }
   3075  1.281   msaitoh 			if (j == txs->txs_lastdesc)
   3076  1.281   msaitoh 				break;
   3077  1.281   msaitoh 			}
   3078  1.281   msaitoh 		}
   3079  1.281   msaitoh #endif
   3080  1.281   msaitoh 	}
   3081  1.281   msaitoh }
   3082    1.1   thorpej 
   3083  1.281   msaitoh /*
   3084  1.281   msaitoh  * wm_tick:
   3085  1.281   msaitoh  *
   3086  1.281   msaitoh  *	One second timer, used to check link status, sweep up
   3087  1.281   msaitoh  *	completed transmit jobs, etc.
   3088  1.281   msaitoh  */
   3089  1.281   msaitoh static void
   3090  1.281   msaitoh wm_tick(void *arg)
   3091  1.281   msaitoh {
   3092  1.281   msaitoh 	struct wm_softc *sc = arg;
   3093  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   3094  1.281   msaitoh #ifndef WM_MPSAFE
   3095  1.413     skrll 	int s = splnet();
   3096  1.281   msaitoh #endif
   3097   1.35   thorpej 
   3098  1.357  knakahar 	WM_CORE_LOCK(sc);
   3099   1.13   thorpej 
   3100  1.562  knakahar 	if (sc->sc_core_stopping) {
   3101  1.562  knakahar 		WM_CORE_UNLOCK(sc);
   3102  1.562  knakahar #ifndef WM_MPSAFE
   3103  1.562  knakahar 		splx(s);
   3104  1.562  knakahar #endif
   3105  1.562  knakahar 		return;
   3106  1.562  knakahar 	}
   3107    1.1   thorpej 
   3108  1.281   msaitoh 	if (sc->sc_type >= WM_T_82542_2_1) {
   3109  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
   3110  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
   3111  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
   3112  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
   3113  1.281   msaitoh 		WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
   3114  1.107      yamt 	}
   3115    1.1   thorpej 
   3116  1.281   msaitoh 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
   3117  1.504  knakahar 	ifp->if_ierrors += 0ULL /* ensure quad_t */
   3118  1.281   msaitoh 	    + CSR_READ(sc, WMREG_CRCERRS)
   3119  1.281   msaitoh 	    + CSR_READ(sc, WMREG_ALGNERRC)
   3120  1.281   msaitoh 	    + CSR_READ(sc, WMREG_SYMERRC)
   3121  1.281   msaitoh 	    + CSR_READ(sc, WMREG_RXERRC)
   3122  1.281   msaitoh 	    + CSR_READ(sc, WMREG_SEC)
   3123  1.281   msaitoh 	    + CSR_READ(sc, WMREG_CEXTERR)
   3124  1.281   msaitoh 	    + CSR_READ(sc, WMREG_RLEC);
   3125  1.431  knakahar 	/*
   3126  1.431  knakahar 	 * WMREG_RNBC is incremented when there is no available buffers in host
   3127  1.431  knakahar 	 * memory. It does not mean the number of dropped packet. Because
   3128  1.431  knakahar 	 * ethernet controller can receive packets in such case if there is
   3129  1.431  knakahar 	 * space in phy's FIFO.
   3130  1.431  knakahar 	 *
   3131  1.431  knakahar 	 * If you want to know the nubmer of WMREG_RMBC, you should use such as
   3132  1.431  knakahar 	 * own EVCNT instead of if_iqdrops.
   3133  1.431  knakahar 	 */
   3134  1.431  knakahar 	ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC);
   3135   1.98   thorpej 
   3136  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   3137  1.281   msaitoh 		mii_tick(&sc->sc_mii);
   3138  1.325   msaitoh 	else if ((sc->sc_type >= WM_T_82575)
   3139  1.325   msaitoh 	    && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   3140  1.325   msaitoh 		wm_serdes_tick(sc);
   3141  1.281   msaitoh 	else
   3142  1.325   msaitoh 		wm_tbi_tick(sc);
   3143  1.131      yamt 
   3144  1.562  knakahar 	WM_CORE_UNLOCK(sc);
   3145  1.562  knakahar 
   3146  1.562  knakahar 	wm_watchdog(ifp);
   3147  1.562  knakahar 
   3148  1.463  knakahar 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   3149  1.281   msaitoh }
   3150   1.99      matt 
   3151  1.281   msaitoh static int
   3152  1.281   msaitoh wm_ifflags_cb(struct ethercom *ec)
   3153  1.281   msaitoh {
   3154  1.281   msaitoh 	struct ifnet *ifp = &ec->ec_if;
   3155  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   3156  1.281   msaitoh 	int rc = 0;
   3157   1.99      matt 
   3158  1.511   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3159  1.511   msaitoh 		device_xname(sc->sc_dev), __func__));
   3160  1.511   msaitoh 
   3161  1.357  knakahar 	WM_CORE_LOCK(sc);
   3162   1.99      matt 
   3163  1.418     skrll 	int change = ifp->if_flags ^ sc->sc_if_flags;
   3164  1.418     skrll 	sc->sc_if_flags = ifp->if_flags;
   3165   1.99      matt 
   3166  1.388   msaitoh 	if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
   3167  1.281   msaitoh 		rc = ENETRESET;
   3168  1.281   msaitoh 		goto out;
   3169  1.281   msaitoh 	}
   3170   1.99      matt 
   3171  1.281   msaitoh 	if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
   3172  1.281   msaitoh 		wm_set_filter(sc);
   3173  1.131      yamt 
   3174  1.281   msaitoh 	wm_set_vlan(sc);
   3175  1.131      yamt 
   3176  1.281   msaitoh out:
   3177  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   3178   1.99      matt 
   3179  1.281   msaitoh 	return rc;
   3180   1.75   thorpej }
   3181   1.75   thorpej 
   3182    1.1   thorpej /*
   3183  1.281   msaitoh  * wm_ioctl:		[ifnet interface function]
   3184   1.78   thorpej  *
   3185  1.281   msaitoh  *	Handle control requests from the operator.
   3186   1.78   thorpej  */
   3187  1.281   msaitoh static int
   3188  1.281   msaitoh wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
   3189   1.78   thorpej {
   3190  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   3191  1.281   msaitoh 	struct ifreq *ifr = (struct ifreq *) data;
   3192  1.281   msaitoh 	struct ifaddr *ifa = (struct ifaddr *)data;
   3193  1.281   msaitoh 	struct sockaddr_dl *sdl;
   3194  1.281   msaitoh 	int s, error;
   3195  1.281   msaitoh 
   3196  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3197  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3198  1.420   msaitoh 
   3199  1.272     ozaki #ifndef WM_MPSAFE
   3200   1.78   thorpej 	s = splnet();
   3201  1.272     ozaki #endif
   3202  1.281   msaitoh 	switch (cmd) {
   3203  1.281   msaitoh 	case SIOCSIFMEDIA:
   3204  1.281   msaitoh 	case SIOCGIFMEDIA:
   3205  1.357  knakahar 		WM_CORE_LOCK(sc);
   3206  1.281   msaitoh 		/* Flow control requires full-duplex mode. */
   3207  1.327   msaitoh 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
   3208  1.281   msaitoh 		    (ifr->ifr_media & IFM_FDX) == 0)
   3209  1.281   msaitoh 			ifr->ifr_media &= ~IFM_ETH_FMASK;
   3210  1.281   msaitoh 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
   3211  1.281   msaitoh 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
   3212  1.281   msaitoh 				/* We can do both TXPAUSE and RXPAUSE. */
   3213  1.281   msaitoh 				ifr->ifr_media |=
   3214  1.281   msaitoh 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   3215  1.281   msaitoh 			}
   3216  1.281   msaitoh 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
   3217  1.281   msaitoh 		}
   3218  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   3219  1.302     ozaki #ifdef WM_MPSAFE
   3220  1.302     ozaki 		s = splnet();
   3221  1.302     ozaki #endif
   3222  1.281   msaitoh 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
   3223  1.302     ozaki #ifdef WM_MPSAFE
   3224  1.302     ozaki 		splx(s);
   3225  1.302     ozaki #endif
   3226  1.281   msaitoh 		break;
   3227  1.281   msaitoh 	case SIOCINITIFADDR:
   3228  1.357  knakahar 		WM_CORE_LOCK(sc);
   3229  1.281   msaitoh 		if (ifa->ifa_addr->sa_family == AF_LINK) {
   3230  1.281   msaitoh 			sdl = satosdl(ifp->if_dl->ifa_addr);
   3231  1.281   msaitoh 			(void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
   3232  1.281   msaitoh 			    LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen);
   3233  1.281   msaitoh 			/* unicast address is first multicast entry */
   3234  1.281   msaitoh 			wm_set_filter(sc);
   3235  1.281   msaitoh 			error = 0;
   3236  1.357  knakahar 			WM_CORE_UNLOCK(sc);
   3237  1.281   msaitoh 			break;
   3238  1.281   msaitoh 		}
   3239  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   3240  1.281   msaitoh 		/*FALLTHROUGH*/
   3241  1.281   msaitoh 	default:
   3242  1.281   msaitoh #ifdef WM_MPSAFE
   3243  1.281   msaitoh 		s = splnet();
   3244  1.281   msaitoh #endif
   3245  1.281   msaitoh 		/* It may call wm_start, so unlock here */
   3246  1.281   msaitoh 		error = ether_ioctl(ifp, cmd, data);
   3247  1.281   msaitoh #ifdef WM_MPSAFE
   3248  1.281   msaitoh 		splx(s);
   3249  1.281   msaitoh #endif
   3250  1.281   msaitoh 		if (error != ENETRESET)
   3251  1.281   msaitoh 			break;
   3252   1.78   thorpej 
   3253  1.281   msaitoh 		error = 0;
   3254   1.78   thorpej 
   3255  1.281   msaitoh 		if (cmd == SIOCSIFCAP) {
   3256  1.281   msaitoh 			error = (*ifp->if_init)(ifp);
   3257  1.281   msaitoh 		} else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
   3258  1.281   msaitoh 			;
   3259  1.281   msaitoh 		else if (ifp->if_flags & IFF_RUNNING) {
   3260   1.78   thorpej 			/*
   3261  1.281   msaitoh 			 * Multicast list has changed; set the hardware filter
   3262  1.281   msaitoh 			 * accordingly.
   3263   1.78   thorpej 			 */
   3264  1.357  knakahar 			WM_CORE_LOCK(sc);
   3265  1.281   msaitoh 			wm_set_filter(sc);
   3266  1.357  knakahar 			WM_CORE_UNLOCK(sc);
   3267   1.78   thorpej 		}
   3268  1.281   msaitoh 		break;
   3269   1.78   thorpej 	}
   3270   1.78   thorpej 
   3271  1.272     ozaki #ifndef WM_MPSAFE
   3272   1.78   thorpej 	splx(s);
   3273  1.272     ozaki #endif
   3274  1.281   msaitoh 	return error;
   3275   1.78   thorpej }
   3276   1.78   thorpej 
   3277  1.281   msaitoh /* MAC address related */
   3278  1.281   msaitoh 
   3279  1.306   msaitoh /*
   3280  1.306   msaitoh  * Get the offset of MAC address and return it.
   3281  1.306   msaitoh  * If error occured, use offset 0.
   3282  1.306   msaitoh  */
   3283  1.306   msaitoh static uint16_t
   3284  1.281   msaitoh wm_check_alt_mac_addr(struct wm_softc *sc)
   3285  1.221   msaitoh {
   3286  1.281   msaitoh 	uint16_t myea[ETHER_ADDR_LEN / 2];
   3287  1.293   msaitoh 	uint16_t offset = NVM_OFF_MACADDR;
   3288  1.281   msaitoh 
   3289  1.281   msaitoh 	/* Try to read alternative MAC address pointer */
   3290  1.293   msaitoh 	if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0)
   3291  1.306   msaitoh 		return 0;
   3292  1.221   msaitoh 
   3293  1.306   msaitoh 	/* Check pointer if it's valid or not. */
   3294  1.306   msaitoh 	if ((offset == 0x0000) || (offset == 0xffff))
   3295  1.306   msaitoh 		return 0;
   3296  1.221   msaitoh 
   3297  1.306   msaitoh 	offset += NVM_OFF_MACADDR_82571(sc->sc_funcid);
   3298  1.281   msaitoh 	/*
   3299  1.281   msaitoh 	 * Check whether alternative MAC address is valid or not.
   3300  1.281   msaitoh 	 * Some cards have non 0xffff pointer but those don't use
   3301  1.281   msaitoh 	 * alternative MAC address in reality.
   3302  1.281   msaitoh 	 *
   3303  1.281   msaitoh 	 * Check whether the broadcast bit is set or not.
   3304  1.281   msaitoh 	 */
   3305  1.281   msaitoh 	if (wm_nvm_read(sc, offset, 1, myea) == 0)
   3306  1.281   msaitoh 		if (((myea[0] & 0xff) & 0x01) == 0)
   3307  1.306   msaitoh 			return offset; /* Found */
   3308  1.221   msaitoh 
   3309  1.306   msaitoh 	/* Not found */
   3310  1.306   msaitoh 	return 0;
   3311  1.221   msaitoh }
   3312  1.221   msaitoh 
   3313   1.78   thorpej static int
   3314  1.281   msaitoh wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)
   3315   1.78   thorpej {
   3316  1.281   msaitoh 	uint16_t myea[ETHER_ADDR_LEN / 2];
   3317  1.293   msaitoh 	uint16_t offset = NVM_OFF_MACADDR;
   3318  1.281   msaitoh 	int do_invert = 0;
   3319   1.78   thorpej 
   3320  1.281   msaitoh 	switch (sc->sc_type) {
   3321  1.281   msaitoh 	case WM_T_82580:
   3322  1.281   msaitoh 	case WM_T_I350:
   3323  1.281   msaitoh 	case WM_T_I354:
   3324  1.307   msaitoh 		/* EEPROM Top Level Partitioning */
   3325  1.307   msaitoh 		offset = NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + 0;
   3326  1.281   msaitoh 		break;
   3327  1.281   msaitoh 	case WM_T_82571:
   3328  1.281   msaitoh 	case WM_T_82575:
   3329  1.281   msaitoh 	case WM_T_82576:
   3330  1.281   msaitoh 	case WM_T_80003:
   3331  1.281   msaitoh 	case WM_T_I210:
   3332  1.281   msaitoh 	case WM_T_I211:
   3333  1.306   msaitoh 		offset = wm_check_alt_mac_addr(sc);
   3334  1.306   msaitoh 		if (offset == 0)
   3335  1.281   msaitoh 			if ((sc->sc_funcid & 0x01) == 1)
   3336  1.281   msaitoh 				do_invert = 1;
   3337  1.281   msaitoh 		break;
   3338  1.281   msaitoh 	default:
   3339  1.281   msaitoh 		if ((sc->sc_funcid & 0x01) == 1)
   3340  1.281   msaitoh 			do_invert = 1;
   3341  1.281   msaitoh 		break;
   3342  1.281   msaitoh 	}
   3343   1.78   thorpej 
   3344  1.424   msaitoh 	if (wm_nvm_read(sc, offset, sizeof(myea) / sizeof(myea[0]), myea) != 0)
   3345  1.281   msaitoh 		goto bad;
   3346   1.78   thorpej 
   3347  1.281   msaitoh 	enaddr[0] = myea[0] & 0xff;
   3348  1.281   msaitoh 	enaddr[1] = myea[0] >> 8;
   3349  1.281   msaitoh 	enaddr[2] = myea[1] & 0xff;
   3350  1.281   msaitoh 	enaddr[3] = myea[1] >> 8;
   3351  1.281   msaitoh 	enaddr[4] = myea[2] & 0xff;
   3352  1.281   msaitoh 	enaddr[5] = myea[2] >> 8;
   3353   1.78   thorpej 
   3354  1.281   msaitoh 	/*
   3355  1.281   msaitoh 	 * Toggle the LSB of the MAC address on the second port
   3356  1.281   msaitoh 	 * of some dual port cards.
   3357  1.281   msaitoh 	 */
   3358  1.281   msaitoh 	if (do_invert != 0)
   3359  1.281   msaitoh 		enaddr[5] ^= 1;
   3360   1.78   thorpej 
   3361  1.194   msaitoh 	return 0;
   3362  1.281   msaitoh 
   3363  1.281   msaitoh  bad:
   3364  1.281   msaitoh 	return -1;
   3365   1.78   thorpej }
   3366   1.78   thorpej 
   3367   1.78   thorpej /*
   3368  1.281   msaitoh  * wm_set_ral:
   3369    1.1   thorpej  *
   3370  1.281   msaitoh  *	Set an entery in the receive address list.
   3371    1.1   thorpej  */
   3372   1.47   thorpej static void
   3373  1.281   msaitoh wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
   3374  1.281   msaitoh {
   3375  1.514   msaitoh 	uint32_t ral_lo, ral_hi, addrl, addrh;
   3376  1.514   msaitoh 	uint32_t wlock_mac;
   3377  1.514   msaitoh 	int rv;
   3378  1.281   msaitoh 
   3379  1.281   msaitoh 	if (enaddr != NULL) {
   3380  1.281   msaitoh 		ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
   3381  1.281   msaitoh 		    (enaddr[3] << 24);
   3382  1.281   msaitoh 		ral_hi = enaddr[4] | (enaddr[5] << 8);
   3383  1.281   msaitoh 		ral_hi |= RAL_AV;
   3384  1.281   msaitoh 	} else {
   3385  1.281   msaitoh 		ral_lo = 0;
   3386  1.281   msaitoh 		ral_hi = 0;
   3387  1.281   msaitoh 	}
   3388  1.281   msaitoh 
   3389  1.514   msaitoh 	switch (sc->sc_type) {
   3390  1.514   msaitoh 	case WM_T_82542_2_0:
   3391  1.514   msaitoh 	case WM_T_82542_2_1:
   3392  1.514   msaitoh 	case WM_T_82543:
   3393  1.514   msaitoh 		CSR_WRITE(sc, WMREG_RAL(idx), ral_lo);
   3394  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3395  1.514   msaitoh 		CSR_WRITE(sc, WMREG_RAH(idx), ral_hi);
   3396  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3397  1.514   msaitoh 		break;
   3398  1.514   msaitoh 	case WM_T_PCH2:
   3399  1.514   msaitoh 	case WM_T_PCH_LPT:
   3400  1.514   msaitoh 	case WM_T_PCH_SPT:
   3401  1.570   msaitoh 	case WM_T_PCH_CNP:
   3402  1.514   msaitoh 		if (idx == 0) {
   3403  1.514   msaitoh 			CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
   3404  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3405  1.514   msaitoh 			CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
   3406  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3407  1.514   msaitoh 			return;
   3408  1.514   msaitoh 		}
   3409  1.514   msaitoh 		if (sc->sc_type != WM_T_PCH2) {
   3410  1.514   msaitoh 			wlock_mac = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM),
   3411  1.514   msaitoh 			    FWSM_WLOCK_MAC);
   3412  1.514   msaitoh 			addrl = WMREG_SHRAL(idx - 1);
   3413  1.514   msaitoh 			addrh = WMREG_SHRAH(idx - 1);
   3414  1.514   msaitoh 		} else {
   3415  1.514   msaitoh 			wlock_mac = 0;
   3416  1.514   msaitoh 			addrl = WMREG_PCH_LPT_SHRAL(idx - 1);
   3417  1.514   msaitoh 			addrh = WMREG_PCH_LPT_SHRAH(idx - 1);
   3418  1.514   msaitoh 		}
   3419  1.514   msaitoh 
   3420  1.514   msaitoh 		if ((wlock_mac == 0) || (idx <= wlock_mac)) {
   3421  1.514   msaitoh 			rv = wm_get_swflag_ich8lan(sc);
   3422  1.514   msaitoh 			if (rv != 0)
   3423  1.514   msaitoh 				return;
   3424  1.514   msaitoh 			CSR_WRITE(sc, addrl, ral_lo);
   3425  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3426  1.514   msaitoh 			CSR_WRITE(sc, addrh, ral_hi);
   3427  1.514   msaitoh 			CSR_WRITE_FLUSH(sc);
   3428  1.514   msaitoh 			wm_put_swflag_ich8lan(sc);
   3429  1.514   msaitoh 		}
   3430  1.514   msaitoh 
   3431  1.514   msaitoh 		break;
   3432  1.514   msaitoh 	default:
   3433  1.514   msaitoh 		CSR_WRITE(sc, WMREG_CORDOVA_RAL(idx), ral_lo);
   3434  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3435  1.514   msaitoh 		CSR_WRITE(sc, WMREG_CORDOVA_RAH(idx), ral_hi);
   3436  1.514   msaitoh 		CSR_WRITE_FLUSH(sc);
   3437  1.514   msaitoh 		break;
   3438  1.281   msaitoh 	}
   3439  1.281   msaitoh }
   3440  1.281   msaitoh 
   3441  1.281   msaitoh /*
   3442  1.281   msaitoh  * wm_mchash:
   3443  1.281   msaitoh  *
   3444  1.281   msaitoh  *	Compute the hash of the multicast address for the 4096-bit
   3445  1.281   msaitoh  *	multicast filter.
   3446  1.281   msaitoh  */
   3447  1.281   msaitoh static uint32_t
   3448  1.281   msaitoh wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
   3449    1.1   thorpej {
   3450  1.281   msaitoh 	static const int lo_shift[4] = { 4, 3, 2, 0 };
   3451  1.281   msaitoh 	static const int hi_shift[4] = { 4, 5, 6, 8 };
   3452  1.281   msaitoh 	static const int ich8_lo_shift[4] = { 6, 5, 4, 2 };
   3453  1.281   msaitoh 	static const int ich8_hi_shift[4] = { 2, 3, 4, 6 };
   3454  1.281   msaitoh 	uint32_t hash;
   3455  1.281   msaitoh 
   3456  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3457  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3458  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   3459  1.570   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
   3460  1.281   msaitoh 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
   3461  1.281   msaitoh 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
   3462  1.281   msaitoh 		return (hash & 0x3ff);
   3463  1.281   msaitoh 	}
   3464  1.281   msaitoh 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
   3465  1.281   msaitoh 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
   3466  1.272     ozaki 
   3467  1.281   msaitoh 	return (hash & 0xfff);
   3468  1.272     ozaki }
   3469  1.272     ozaki 
   3470  1.281   msaitoh /*
   3471  1.281   msaitoh  * wm_set_filter:
   3472  1.281   msaitoh  *
   3473  1.281   msaitoh  *	Set up the receive filter.
   3474  1.281   msaitoh  */
   3475  1.272     ozaki static void
   3476  1.281   msaitoh wm_set_filter(struct wm_softc *sc)
   3477  1.272     ozaki {
   3478  1.281   msaitoh 	struct ethercom *ec = &sc->sc_ethercom;
   3479  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   3480  1.281   msaitoh 	struct ether_multi *enm;
   3481  1.281   msaitoh 	struct ether_multistep step;
   3482  1.281   msaitoh 	bus_addr_t mta_reg;
   3483  1.281   msaitoh 	uint32_t hash, reg, bit;
   3484  1.390   msaitoh 	int i, size, ralmax;
   3485  1.281   msaitoh 
   3486  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3487  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3488  1.420   msaitoh 
   3489  1.281   msaitoh 	if (sc->sc_type >= WM_T_82544)
   3490  1.281   msaitoh 		mta_reg = WMREG_CORDOVA_MTA;
   3491  1.281   msaitoh 	else
   3492  1.281   msaitoh 		mta_reg = WMREG_MTA;
   3493    1.1   thorpej 
   3494  1.281   msaitoh 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
   3495  1.272     ozaki 
   3496  1.281   msaitoh 	if (ifp->if_flags & IFF_BROADCAST)
   3497  1.281   msaitoh 		sc->sc_rctl |= RCTL_BAM;
   3498  1.281   msaitoh 	if (ifp->if_flags & IFF_PROMISC) {
   3499  1.281   msaitoh 		sc->sc_rctl |= RCTL_UPE;
   3500  1.281   msaitoh 		goto allmulti;
   3501  1.281   msaitoh 	}
   3502    1.1   thorpej 
   3503    1.1   thorpej 	/*
   3504  1.281   msaitoh 	 * Set the station address in the first RAL slot, and
   3505  1.281   msaitoh 	 * clear the remaining slots.
   3506    1.1   thorpej 	 */
   3507  1.281   msaitoh 	if (sc->sc_type == WM_T_ICH8)
   3508  1.281   msaitoh 		size = WM_RAL_TABSIZE_ICH8 -1;
   3509  1.281   msaitoh 	else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10)
   3510  1.386   msaitoh 	    || (sc->sc_type == WM_T_PCH))
   3511  1.281   msaitoh 		size = WM_RAL_TABSIZE_ICH8;
   3512  1.386   msaitoh 	else if (sc->sc_type == WM_T_PCH2)
   3513  1.386   msaitoh 		size = WM_RAL_TABSIZE_PCH2;
   3514  1.570   msaitoh 	else if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
   3515  1.570   msaitoh 	    || (sc->sc_type == WM_T_PCH_CNP))
   3516  1.386   msaitoh 		size = WM_RAL_TABSIZE_PCH_LPT;
   3517  1.281   msaitoh 	else if (sc->sc_type == WM_T_82575)
   3518  1.281   msaitoh 		size = WM_RAL_TABSIZE_82575;
   3519  1.281   msaitoh 	else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580))
   3520  1.281   msaitoh 		size = WM_RAL_TABSIZE_82576;
   3521  1.281   msaitoh 	else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   3522  1.281   msaitoh 		size = WM_RAL_TABSIZE_I350;
   3523  1.281   msaitoh 	else
   3524  1.281   msaitoh 		size = WM_RAL_TABSIZE;
   3525  1.281   msaitoh 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
   3526  1.386   msaitoh 
   3527  1.570   msaitoh 	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
   3528  1.570   msaitoh 	    || (sc->sc_type == WM_T_PCH_CNP)) {
   3529  1.386   msaitoh 		i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
   3530  1.386   msaitoh 		switch (i) {
   3531  1.386   msaitoh 		case 0:
   3532  1.386   msaitoh 			/* We can use all entries */
   3533  1.390   msaitoh 			ralmax = size;
   3534  1.386   msaitoh 			break;
   3535  1.386   msaitoh 		case 1:
   3536  1.386   msaitoh 			/* Only RAR[0] */
   3537  1.390   msaitoh 			ralmax = 1;
   3538  1.386   msaitoh 			break;
   3539  1.386   msaitoh 		default:
   3540  1.386   msaitoh 			/* available SHRA + RAR[0] */
   3541  1.390   msaitoh 			ralmax = i + 1;
   3542  1.386   msaitoh 		}
   3543  1.386   msaitoh 	} else
   3544  1.390   msaitoh 		ralmax = size;
   3545  1.386   msaitoh 	for (i = 1; i < size; i++) {
   3546  1.390   msaitoh 		if (i < ralmax)
   3547  1.386   msaitoh 			wm_set_ral(sc, NULL, i);
   3548  1.386   msaitoh 	}
   3549    1.1   thorpej 
   3550  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3551  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3552  1.392   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   3553  1.570   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP))
   3554  1.281   msaitoh 		size = WM_ICH8_MC_TABSIZE;
   3555  1.281   msaitoh 	else
   3556  1.281   msaitoh 		size = WM_MC_TABSIZE;
   3557  1.281   msaitoh 	/* Clear out the multicast table. */
   3558  1.515   msaitoh 	for (i = 0; i < size; i++) {
   3559  1.281   msaitoh 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
   3560  1.515   msaitoh 		CSR_WRITE_FLUSH(sc);
   3561  1.515   msaitoh 	}
   3562    1.1   thorpej 
   3563  1.460     ozaki 	ETHER_LOCK(ec);
   3564  1.281   msaitoh 	ETHER_FIRST_MULTI(step, ec, enm);
   3565  1.281   msaitoh 	while (enm != NULL) {
   3566  1.281   msaitoh 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   3567  1.460     ozaki 			ETHER_UNLOCK(ec);
   3568  1.281   msaitoh 			/*
   3569  1.281   msaitoh 			 * We must listen to a range of multicast addresses.
   3570  1.281   msaitoh 			 * For now, just accept all multicasts, rather than
   3571  1.281   msaitoh 			 * trying to set only those filter bits needed to match
   3572  1.281   msaitoh 			 * the range.  (At this time, the only use of address
   3573  1.281   msaitoh 			 * ranges is for IP multicast routing, for which the
   3574  1.281   msaitoh 			 * range is big enough to require all bits set.)
   3575  1.281   msaitoh 			 */
   3576  1.281   msaitoh 			goto allmulti;
   3577    1.1   thorpej 		}
   3578    1.1   thorpej 
   3579  1.281   msaitoh 		hash = wm_mchash(sc, enm->enm_addrlo);
   3580  1.272     ozaki 
   3581  1.281   msaitoh 		reg = (hash >> 5);
   3582  1.281   msaitoh 		if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   3583  1.281   msaitoh 		    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   3584  1.281   msaitoh 		    || (sc->sc_type == WM_T_PCH2)
   3585  1.392   msaitoh 		    || (sc->sc_type == WM_T_PCH_LPT)
   3586  1.570   msaitoh 		    || (sc->sc_type == WM_T_PCH_SPT)
   3587  1.570   msaitoh 		    || (sc->sc_type == WM_T_PCH_CNP))
   3588  1.281   msaitoh 			reg &= 0x1f;
   3589  1.281   msaitoh 		else
   3590  1.281   msaitoh 			reg &= 0x7f;
   3591  1.281   msaitoh 		bit = hash & 0x1f;
   3592  1.272     ozaki 
   3593  1.281   msaitoh 		hash = CSR_READ(sc, mta_reg + (reg << 2));
   3594  1.281   msaitoh 		hash |= 1U << bit;
   3595    1.1   thorpej 
   3596  1.382  christos 		if (sc->sc_type == WM_T_82544 && (reg & 1) != 0) {
   3597  1.387   msaitoh 			/*
   3598  1.387   msaitoh 			 * 82544 Errata 9: Certain register cannot be written
   3599  1.387   msaitoh 			 * with particular alignments in PCI-X bus operation
   3600  1.387   msaitoh 			 * (FCAH, MTA and VFTA).
   3601  1.387   msaitoh 			 */
   3602  1.281   msaitoh 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
   3603  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   3604  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3605  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
   3606  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3607  1.515   msaitoh 		} else {
   3608  1.281   msaitoh 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   3609  1.515   msaitoh 			CSR_WRITE_FLUSH(sc);
   3610  1.515   msaitoh 		}
   3611   1.99      matt 
   3612  1.281   msaitoh 		ETHER_NEXT_MULTI(step, enm);
   3613  1.281   msaitoh 	}
   3614  1.460     ozaki 	ETHER_UNLOCK(ec);
   3615   1.99      matt 
   3616  1.281   msaitoh 	ifp->if_flags &= ~IFF_ALLMULTI;
   3617  1.281   msaitoh 	goto setit;
   3618    1.1   thorpej 
   3619  1.281   msaitoh  allmulti:
   3620  1.281   msaitoh 	ifp->if_flags |= IFF_ALLMULTI;
   3621  1.281   msaitoh 	sc->sc_rctl |= RCTL_MPE;
   3622   1.80   thorpej 
   3623  1.281   msaitoh  setit:
   3624  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
   3625  1.281   msaitoh }
   3626    1.1   thorpej 
   3627  1.281   msaitoh /* Reset and init related */
   3628   1.78   thorpej 
   3629  1.281   msaitoh static void
   3630  1.281   msaitoh wm_set_vlan(struct wm_softc *sc)
   3631  1.281   msaitoh {
   3632  1.392   msaitoh 
   3633  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3634  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   3635  1.420   msaitoh 
   3636  1.281   msaitoh 	/* Deal with VLAN enables. */
   3637  1.281   msaitoh 	if (VLAN_ATTACHED(&sc->sc_ethercom))
   3638  1.281   msaitoh 		sc->sc_ctrl |= CTRL_VME;
   3639  1.281   msaitoh 	else
   3640  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_VME;
   3641    1.1   thorpej 
   3642  1.281   msaitoh 	/* Write the control registers. */
   3643  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3644  1.281   msaitoh }
   3645    1.1   thorpej 
   3646  1.281   msaitoh static void
   3647  1.281   msaitoh wm_set_pcie_completion_timeout(struct wm_softc *sc)
   3648  1.281   msaitoh {
   3649  1.281   msaitoh 	uint32_t gcr;
   3650  1.281   msaitoh 	pcireg_t ctrl2;
   3651    1.1   thorpej 
   3652  1.281   msaitoh 	gcr = CSR_READ(sc, WMREG_GCR);
   3653    1.4   thorpej 
   3654  1.281   msaitoh 	/* Only take action if timeout value is defaulted to 0 */
   3655  1.281   msaitoh 	if ((gcr & GCR_CMPL_TMOUT_MASK) != 0)
   3656  1.281   msaitoh 		goto out;
   3657    1.1   thorpej 
   3658  1.281   msaitoh 	if ((gcr & GCR_CAP_VER2) == 0) {
   3659  1.281   msaitoh 		gcr |= GCR_CMPL_TMOUT_10MS;
   3660  1.281   msaitoh 		goto out;
   3661  1.281   msaitoh 	}
   3662    1.6   thorpej 
   3663  1.281   msaitoh 	ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   3664  1.281   msaitoh 	    sc->sc_pcixe_capoff + PCIE_DCSR2);
   3665  1.281   msaitoh 	ctrl2 |= WM_PCIE_DCSR2_16MS;
   3666  1.281   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   3667  1.281   msaitoh 	    sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2);
   3668   1.81   thorpej 
   3669  1.281   msaitoh out:
   3670  1.281   msaitoh 	/* Disable completion timeout resend */
   3671  1.281   msaitoh 	gcr &= ~GCR_CMPL_TMOUT_RESEND;
   3672   1.80   thorpej 
   3673  1.281   msaitoh 	CSR_WRITE(sc, WMREG_GCR, gcr);
   3674  1.281   msaitoh }
   3675   1.99      matt 
   3676  1.281   msaitoh void
   3677  1.281   msaitoh wm_get_auto_rd_done(struct wm_softc *sc)
   3678  1.281   msaitoh {
   3679  1.281   msaitoh 	int i;
   3680    1.1   thorpej 
   3681  1.281   msaitoh 	/* wait for eeprom to reload */
   3682  1.281   msaitoh 	switch (sc->sc_type) {
   3683  1.281   msaitoh 	case WM_T_82571:
   3684  1.281   msaitoh 	case WM_T_82572:
   3685  1.281   msaitoh 	case WM_T_82573:
   3686  1.281   msaitoh 	case WM_T_82574:
   3687  1.281   msaitoh 	case WM_T_82583:
   3688  1.281   msaitoh 	case WM_T_82575:
   3689  1.281   msaitoh 	case WM_T_82576:
   3690  1.281   msaitoh 	case WM_T_82580:
   3691  1.281   msaitoh 	case WM_T_I350:
   3692  1.281   msaitoh 	case WM_T_I354:
   3693  1.281   msaitoh 	case WM_T_I210:
   3694  1.281   msaitoh 	case WM_T_I211:
   3695  1.281   msaitoh 	case WM_T_80003:
   3696  1.281   msaitoh 	case WM_T_ICH8:
   3697  1.281   msaitoh 	case WM_T_ICH9:
   3698  1.281   msaitoh 		for (i = 0; i < 10; i++) {
   3699  1.281   msaitoh 			if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
   3700  1.281   msaitoh 				break;
   3701  1.281   msaitoh 			delay(1000);
   3702    1.1   thorpej 		}
   3703  1.281   msaitoh 		if (i == 10) {
   3704  1.281   msaitoh 			log(LOG_ERR, "%s: auto read from eeprom failed to "
   3705  1.281   msaitoh 			    "complete\n", device_xname(sc->sc_dev));
   3706  1.281   msaitoh 		}
   3707  1.281   msaitoh 		break;
   3708  1.281   msaitoh 	default:
   3709  1.281   msaitoh 		break;
   3710  1.281   msaitoh 	}
   3711  1.281   msaitoh }
   3712   1.59  christos 
   3713  1.281   msaitoh void
   3714  1.281   msaitoh wm_lan_init_done(struct wm_softc *sc)
   3715  1.281   msaitoh {
   3716  1.281   msaitoh 	uint32_t reg = 0;
   3717  1.281   msaitoh 	int i;
   3718    1.1   thorpej 
   3719  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3720  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   3721  1.420   msaitoh 
   3722  1.420   msaitoh 	/* Wait for eeprom to reload */
   3723  1.281   msaitoh 	switch (sc->sc_type) {
   3724  1.281   msaitoh 	case WM_T_ICH10:
   3725  1.281   msaitoh 	case WM_T_PCH:
   3726  1.281   msaitoh 	case WM_T_PCH2:
   3727  1.281   msaitoh 	case WM_T_PCH_LPT:
   3728  1.392   msaitoh 	case WM_T_PCH_SPT:
   3729  1.570   msaitoh 	case WM_T_PCH_CNP:
   3730  1.281   msaitoh 		for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
   3731  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_STATUS);
   3732  1.281   msaitoh 			if ((reg & STATUS_LAN_INIT_DONE) != 0)
   3733  1.281   msaitoh 				break;
   3734  1.281   msaitoh 			delay(100);
   3735  1.281   msaitoh 		}
   3736  1.281   msaitoh 		if (i >= WM_ICH8_LAN_INIT_TIMEOUT) {
   3737  1.281   msaitoh 			log(LOG_ERR, "%s: %s: lan_init_done failed to "
   3738  1.281   msaitoh 			    "complete\n", device_xname(sc->sc_dev), __func__);
   3739    1.1   thorpej 		}
   3740  1.281   msaitoh 		break;
   3741  1.281   msaitoh 	default:
   3742  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   3743  1.281   msaitoh 		    __func__);
   3744  1.281   msaitoh 		break;
   3745  1.281   msaitoh 	}
   3746    1.1   thorpej 
   3747  1.281   msaitoh 	reg &= ~STATUS_LAN_INIT_DONE;
   3748  1.281   msaitoh 	CSR_WRITE(sc, WMREG_STATUS, reg);
   3749  1.281   msaitoh }
   3750    1.6   thorpej 
   3751  1.281   msaitoh void
   3752  1.281   msaitoh wm_get_cfg_done(struct wm_softc *sc)
   3753  1.281   msaitoh {
   3754  1.281   msaitoh 	int mask;
   3755  1.281   msaitoh 	uint32_t reg;
   3756  1.281   msaitoh 	int i;
   3757    1.1   thorpej 
   3758  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3759  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   3760  1.420   msaitoh 
   3761  1.420   msaitoh 	/* Wait for eeprom to reload */
   3762  1.281   msaitoh 	switch (sc->sc_type) {
   3763  1.281   msaitoh 	case WM_T_82542_2_0:
   3764  1.281   msaitoh 	case WM_T_82542_2_1:
   3765  1.281   msaitoh 		/* null */
   3766  1.281   msaitoh 		break;
   3767  1.281   msaitoh 	case WM_T_82543:
   3768  1.281   msaitoh 	case WM_T_82544:
   3769  1.281   msaitoh 	case WM_T_82540:
   3770  1.281   msaitoh 	case WM_T_82545:
   3771  1.281   msaitoh 	case WM_T_82545_3:
   3772  1.281   msaitoh 	case WM_T_82546:
   3773  1.281   msaitoh 	case WM_T_82546_3:
   3774  1.281   msaitoh 	case WM_T_82541:
   3775  1.281   msaitoh 	case WM_T_82541_2:
   3776  1.281   msaitoh 	case WM_T_82547:
   3777  1.281   msaitoh 	case WM_T_82547_2:
   3778  1.281   msaitoh 	case WM_T_82573:
   3779  1.281   msaitoh 	case WM_T_82574:
   3780  1.281   msaitoh 	case WM_T_82583:
   3781  1.281   msaitoh 		/* generic */
   3782  1.281   msaitoh 		delay(10*1000);
   3783  1.281   msaitoh 		break;
   3784  1.281   msaitoh 	case WM_T_80003:
   3785  1.281   msaitoh 	case WM_T_82571:
   3786  1.281   msaitoh 	case WM_T_82572:
   3787  1.281   msaitoh 	case WM_T_82575:
   3788  1.281   msaitoh 	case WM_T_82576:
   3789  1.281   msaitoh 	case WM_T_82580:
   3790  1.281   msaitoh 	case WM_T_I350:
   3791  1.281   msaitoh 	case WM_T_I354:
   3792  1.281   msaitoh 	case WM_T_I210:
   3793  1.281   msaitoh 	case WM_T_I211:
   3794  1.281   msaitoh 		if (sc->sc_type == WM_T_82571) {
   3795  1.281   msaitoh 			/* Only 82571 shares port 0 */
   3796  1.281   msaitoh 			mask = EEMNGCTL_CFGDONE_0;
   3797  1.281   msaitoh 		} else
   3798  1.281   msaitoh 			mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid;
   3799  1.281   msaitoh 		for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) {
   3800  1.281   msaitoh 			if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
   3801  1.281   msaitoh 				break;
   3802  1.281   msaitoh 			delay(1000);
   3803  1.281   msaitoh 		}
   3804  1.281   msaitoh 		if (i >= WM_PHY_CFG_TIMEOUT) {
   3805  1.281   msaitoh 			DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n",
   3806  1.281   msaitoh 				device_xname(sc->sc_dev), __func__));
   3807  1.281   msaitoh 		}
   3808  1.281   msaitoh 		break;
   3809  1.281   msaitoh 	case WM_T_ICH8:
   3810  1.281   msaitoh 	case WM_T_ICH9:
   3811  1.281   msaitoh 	case WM_T_ICH10:
   3812  1.281   msaitoh 	case WM_T_PCH:
   3813  1.281   msaitoh 	case WM_T_PCH2:
   3814  1.281   msaitoh 	case WM_T_PCH_LPT:
   3815  1.392   msaitoh 	case WM_T_PCH_SPT:
   3816  1.570   msaitoh 	case WM_T_PCH_CNP:
   3817  1.281   msaitoh 		delay(10*1000);
   3818  1.281   msaitoh 		if (sc->sc_type >= WM_T_ICH10)
   3819  1.281   msaitoh 			wm_lan_init_done(sc);
   3820  1.281   msaitoh 		else
   3821  1.281   msaitoh 			wm_get_auto_rd_done(sc);
   3822    1.1   thorpej 
   3823  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_STATUS);
   3824  1.281   msaitoh 		if ((reg & STATUS_PHYRA) != 0)
   3825  1.281   msaitoh 			CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA);
   3826  1.281   msaitoh 		break;
   3827  1.281   msaitoh 	default:
   3828  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   3829  1.281   msaitoh 		    __func__);
   3830  1.281   msaitoh 		break;
   3831    1.1   thorpej 	}
   3832    1.1   thorpej }
   3833    1.1   thorpej 
   3834  1.517   msaitoh void
   3835  1.517   msaitoh wm_phy_post_reset(struct wm_softc *sc)
   3836  1.517   msaitoh {
   3837  1.517   msaitoh 	uint32_t reg;
   3838  1.517   msaitoh 
   3839  1.517   msaitoh 	/* This function is only for ICH8 and newer. */
   3840  1.517   msaitoh 	if (sc->sc_type < WM_T_ICH8)
   3841  1.517   msaitoh 		return;
   3842  1.517   msaitoh 
   3843  1.517   msaitoh 	if (wm_phy_resetisblocked(sc)) {
   3844  1.517   msaitoh 		/* XXX */
   3845  1.530   msaitoh 		device_printf(sc->sc_dev, "PHY is blocked\n");
   3846  1.517   msaitoh 		return;
   3847  1.517   msaitoh 	}
   3848  1.517   msaitoh 
   3849  1.517   msaitoh 	/* Allow time for h/w to get to quiescent state after reset */
   3850  1.517   msaitoh 	delay(10*1000);
   3851  1.517   msaitoh 
   3852  1.517   msaitoh 	/* Perform any necessary post-reset workarounds */
   3853  1.517   msaitoh 	if (sc->sc_type == WM_T_PCH)
   3854  1.517   msaitoh 		wm_hv_phy_workaround_ich8lan(sc);
   3855  1.517   msaitoh 	if (sc->sc_type == WM_T_PCH2)
   3856  1.517   msaitoh 		wm_lv_phy_workaround_ich8lan(sc);
   3857  1.517   msaitoh 
   3858  1.517   msaitoh 	/* Clear the host wakeup bit after lcd reset */
   3859  1.517   msaitoh 	if (sc->sc_type >= WM_T_PCH) {
   3860  1.517   msaitoh 		reg = wm_gmii_hv_readreg(sc->sc_dev, 2,
   3861  1.517   msaitoh 		    BM_PORT_GEN_CFG);
   3862  1.517   msaitoh 		reg &= ~BM_WUC_HOST_WU_BIT;
   3863  1.517   msaitoh 		wm_gmii_hv_writereg(sc->sc_dev, 2,
   3864  1.517   msaitoh 		    BM_PORT_GEN_CFG, reg);
   3865  1.517   msaitoh 	}
   3866  1.517   msaitoh 
   3867  1.523   msaitoh 	/* Configure the LCD with the extended configuration region in NVM */
   3868  1.523   msaitoh 	wm_init_lcd_from_nvm(sc);
   3869  1.523   msaitoh 
   3870  1.523   msaitoh 	/* Configure the LCD with the OEM bits in NVM */
   3871  1.523   msaitoh }
   3872  1.523   msaitoh 
   3873  1.528   msaitoh /* Only for PCH and newer */
   3874  1.528   msaitoh static void
   3875  1.528   msaitoh wm_write_smbus_addr(struct wm_softc *sc)
   3876  1.528   msaitoh {
   3877  1.528   msaitoh 	uint32_t strap, freq;
   3878  1.528   msaitoh 	uint32_t phy_data;
   3879  1.528   msaitoh 
   3880  1.528   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3881  1.528   msaitoh 		device_xname(sc->sc_dev), __func__));
   3882  1.528   msaitoh 
   3883  1.528   msaitoh 	strap = CSR_READ(sc, WMREG_STRAP);
   3884  1.528   msaitoh 	freq = __SHIFTOUT(strap, STRAP_FREQ);
   3885  1.528   msaitoh 
   3886  1.528   msaitoh 	phy_data = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, HV_SMB_ADDR);
   3887  1.528   msaitoh 
   3888  1.528   msaitoh 	phy_data &= ~HV_SMB_ADDR_ADDR;
   3889  1.528   msaitoh 	phy_data |= __SHIFTOUT(strap, STRAP_SMBUSADDR);
   3890  1.528   msaitoh 	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
   3891  1.528   msaitoh 
   3892  1.528   msaitoh 	if (sc->sc_phytype == WMPHY_I217) {
   3893  1.528   msaitoh 		/* Restore SMBus frequency */
   3894  1.528   msaitoh 		if (freq --) {
   3895  1.528   msaitoh 			phy_data &= ~(HV_SMB_ADDR_FREQ_LOW
   3896  1.528   msaitoh 			    | HV_SMB_ADDR_FREQ_HIGH);
   3897  1.528   msaitoh 			phy_data |= __SHIFTIN((freq & 0x01) != 0,
   3898  1.528   msaitoh 			    HV_SMB_ADDR_FREQ_LOW);
   3899  1.528   msaitoh 			phy_data |= __SHIFTIN((freq & 0x02) != 0,
   3900  1.528   msaitoh 			    HV_SMB_ADDR_FREQ_HIGH);
   3901  1.528   msaitoh 		} else {
   3902  1.528   msaitoh 			DPRINTF(WM_DEBUG_INIT,
   3903  1.528   msaitoh 			    ("%s: %s Unsupported SMB frequency in PHY\n",
   3904  1.528   msaitoh 				device_xname(sc->sc_dev), __func__));
   3905  1.528   msaitoh 		}
   3906  1.528   msaitoh 	}
   3907  1.528   msaitoh 
   3908  1.528   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, HV_SMB_ADDR, phy_data);
   3909  1.528   msaitoh }
   3910  1.528   msaitoh 
   3911  1.523   msaitoh void
   3912  1.523   msaitoh wm_init_lcd_from_nvm(struct wm_softc *sc)
   3913  1.523   msaitoh {
   3914  1.523   msaitoh 	uint32_t extcnfctr, sw_cfg_mask, cnf_size, word_addr, i, reg;
   3915  1.523   msaitoh 	uint16_t phy_page = 0;
   3916  1.523   msaitoh 
   3917  1.528   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   3918  1.528   msaitoh 		device_xname(sc->sc_dev), __func__));
   3919  1.528   msaitoh 
   3920  1.523   msaitoh 	switch (sc->sc_type) {
   3921  1.523   msaitoh 	case WM_T_ICH8:
   3922  1.528   msaitoh 		if ((sc->sc_phytype == WMPHY_UNKNOWN)
   3923  1.528   msaitoh 		    || (sc->sc_phytype != WMPHY_IGP_3))
   3924  1.523   msaitoh 			return;
   3925  1.523   msaitoh 
   3926  1.523   msaitoh 		if ((sc->sc_pcidevid == PCI_PRODUCT_INTEL_82801H_AMT)
   3927  1.523   msaitoh 		    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_82801H_LAN)) {
   3928  1.523   msaitoh 			sw_cfg_mask = FEXTNVM_SW_CONFIG;
   3929  1.523   msaitoh 			break;
   3930  1.523   msaitoh 		}
   3931  1.523   msaitoh 		/* FALLTHROUGH */
   3932  1.523   msaitoh 	case WM_T_PCH:
   3933  1.523   msaitoh 	case WM_T_PCH2:
   3934  1.523   msaitoh 	case WM_T_PCH_LPT:
   3935  1.523   msaitoh 	case WM_T_PCH_SPT:
   3936  1.570   msaitoh 	case WM_T_PCH_CNP:
   3937  1.523   msaitoh 		sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
   3938  1.523   msaitoh 		break;
   3939  1.523   msaitoh 	default:
   3940  1.523   msaitoh 		return;
   3941  1.523   msaitoh 	}
   3942  1.523   msaitoh 
   3943  1.523   msaitoh 	sc->phy.acquire(sc);
   3944  1.523   msaitoh 
   3945  1.523   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM);
   3946  1.523   msaitoh 	if ((reg & sw_cfg_mask) == 0)
   3947  1.523   msaitoh 		goto release;
   3948  1.523   msaitoh 
   3949  1.517   msaitoh 	/*
   3950  1.523   msaitoh 	 * Make sure HW does not configure LCD from PHY extended configuration
   3951  1.523   msaitoh 	 * before SW configuration
   3952  1.517   msaitoh 	 */
   3953  1.523   msaitoh 	extcnfctr = CSR_READ(sc, WMREG_EXTCNFCTR);
   3954  1.523   msaitoh 	if ((sc->sc_type < WM_T_PCH2)
   3955  1.523   msaitoh 	    && ((extcnfctr & EXTCNFCTR_PCIE_WRITE_ENABLE) != 0))
   3956  1.523   msaitoh 		goto release;
   3957  1.523   msaitoh 
   3958  1.528   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s: Configure LCD by software\n",
   3959  1.528   msaitoh 		device_xname(sc->sc_dev), __func__));
   3960  1.523   msaitoh 	/* word_addr is in DWORD */
   3961  1.523   msaitoh 	word_addr = __SHIFTOUT(extcnfctr, EXTCNFCTR_EXT_CNF_POINTER) << 1;
   3962  1.523   msaitoh 
   3963  1.523   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFSIZE);
   3964  1.523   msaitoh 	cnf_size = __SHIFTOUT(reg, EXTCNFSIZE_LENGTH);
   3965  1.569   msaitoh 	if (cnf_size == 0)
   3966  1.569   msaitoh 		goto release;
   3967  1.523   msaitoh 
   3968  1.523   msaitoh 	if (((sc->sc_type == WM_T_PCH)
   3969  1.523   msaitoh 		&& ((extcnfctr & EXTCNFCTR_OEM_WRITE_ENABLE) == 0))
   3970  1.523   msaitoh 	    || (sc->sc_type > WM_T_PCH)) {
   3971  1.523   msaitoh 		/*
   3972  1.523   msaitoh 		 * HW configures the SMBus address and LEDs when the OEM and
   3973  1.523   msaitoh 		 * LCD Write Enable bits are set in the NVM. When both NVM bits
   3974  1.523   msaitoh 		 * are cleared, SW will configure them instead.
   3975  1.523   msaitoh 		 */
   3976  1.528   msaitoh 		DPRINTF(WM_DEBUG_INIT, ("%s: %s: Configure SMBus and LED\n",
   3977  1.528   msaitoh 			device_xname(sc->sc_dev), __func__));
   3978  1.528   msaitoh 		wm_write_smbus_addr(sc);
   3979  1.517   msaitoh 
   3980  1.523   msaitoh 		reg = CSR_READ(sc, WMREG_LEDCTL);
   3981  1.523   msaitoh 		wm_gmii_hv_writereg_locked(sc->sc_dev, 1, HV_LED_CONFIG, reg);
   3982  1.523   msaitoh 	}
   3983  1.523   msaitoh 
   3984  1.523   msaitoh 	/* Configure LCD from extended configuration region. */
   3985  1.523   msaitoh 	for (i = 0; i < cnf_size; i++) {
   3986  1.523   msaitoh 		uint16_t reg_data, reg_addr;
   3987  1.523   msaitoh 
   3988  1.523   msaitoh 		if (wm_nvm_read(sc, (word_addr + i * 2), 1, &reg_data) != 0)
   3989  1.523   msaitoh 			goto release;
   3990  1.523   msaitoh 
   3991  1.523   msaitoh 		if (wm_nvm_read(sc, (word_addr + i * 2 + 1), 1, &reg_addr) !=0)
   3992  1.523   msaitoh 			goto release;
   3993  1.523   msaitoh 
   3994  1.523   msaitoh 		if (reg_addr == MII_IGPHY_PAGE_SELECT)
   3995  1.523   msaitoh 			phy_page = reg_data;
   3996  1.523   msaitoh 
   3997  1.523   msaitoh 		reg_addr &= IGPHY_MAXREGADDR;
   3998  1.523   msaitoh 		reg_addr |= phy_page;
   3999  1.523   msaitoh 
   4000  1.523   msaitoh 		sc->phy.release(sc); /* XXX */
   4001  1.523   msaitoh 		sc->sc_mii.mii_writereg(sc->sc_dev, 1, reg_addr, reg_data);
   4002  1.523   msaitoh 		sc->phy.acquire(sc); /* XXX */
   4003  1.523   msaitoh 	}
   4004  1.523   msaitoh 
   4005  1.523   msaitoh release:
   4006  1.523   msaitoh 	sc->phy.release(sc);
   4007  1.523   msaitoh 	return;
   4008  1.517   msaitoh }
   4009  1.523   msaitoh 
   4010  1.517   msaitoh 
   4011  1.312   msaitoh /* Init hardware bits */
   4012  1.312   msaitoh void
   4013  1.312   msaitoh wm_initialize_hardware_bits(struct wm_softc *sc)
   4014  1.312   msaitoh {
   4015  1.312   msaitoh 	uint32_t tarc0, tarc1, reg;
   4016  1.332   msaitoh 
   4017  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   4018  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   4019  1.420   msaitoh 
   4020  1.312   msaitoh 	/* For 82571 variant, 80003 and ICHs */
   4021  1.312   msaitoh 	if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583))
   4022  1.312   msaitoh 	    || (sc->sc_type >= WM_T_80003)) {
   4023  1.312   msaitoh 
   4024  1.312   msaitoh 		/* Transmit Descriptor Control 0 */
   4025  1.312   msaitoh 		reg = CSR_READ(sc, WMREG_TXDCTL(0));
   4026  1.312   msaitoh 		reg |= TXDCTL_COUNT_DESC;
   4027  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TXDCTL(0), reg);
   4028  1.312   msaitoh 
   4029  1.312   msaitoh 		/* Transmit Descriptor Control 1 */
   4030  1.312   msaitoh 		reg = CSR_READ(sc, WMREG_TXDCTL(1));
   4031  1.312   msaitoh 		reg |= TXDCTL_COUNT_DESC;
   4032  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TXDCTL(1), reg);
   4033  1.312   msaitoh 
   4034  1.312   msaitoh 		/* TARC0 */
   4035  1.312   msaitoh 		tarc0 = CSR_READ(sc, WMREG_TARC0);
   4036  1.312   msaitoh 		switch (sc->sc_type) {
   4037  1.312   msaitoh 		case WM_T_82571:
   4038  1.312   msaitoh 		case WM_T_82572:
   4039  1.312   msaitoh 		case WM_T_82573:
   4040  1.312   msaitoh 		case WM_T_82574:
   4041  1.312   msaitoh 		case WM_T_82583:
   4042  1.312   msaitoh 		case WM_T_80003:
   4043  1.312   msaitoh 			/* Clear bits 30..27 */
   4044  1.312   msaitoh 			tarc0 &= ~__BITS(30, 27);
   4045  1.312   msaitoh 			break;
   4046  1.312   msaitoh 		default:
   4047  1.312   msaitoh 			break;
   4048  1.312   msaitoh 		}
   4049  1.312   msaitoh 
   4050  1.312   msaitoh 		switch (sc->sc_type) {
   4051  1.312   msaitoh 		case WM_T_82571:
   4052  1.312   msaitoh 		case WM_T_82572:
   4053  1.312   msaitoh 			tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */
   4054  1.312   msaitoh 
   4055  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   4056  1.312   msaitoh 			tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */
   4057  1.312   msaitoh 			tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */
   4058  1.312   msaitoh 			/* 8257[12] Errata No.7 */
   4059  1.312   msaitoh 			tarc1 |= __BIT(22); /* TARC1 bits 22 */
   4060  1.312   msaitoh 
   4061  1.312   msaitoh 			/* TARC1 bit 28 */
   4062  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   4063  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   4064  1.312   msaitoh 			else
   4065  1.312   msaitoh 				tarc1 |= __BIT(28);
   4066  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   4067  1.312   msaitoh 
   4068  1.312   msaitoh 			/*
   4069  1.312   msaitoh 			 * 8257[12] Errata No.13
   4070  1.312   msaitoh 			 * Disable Dyamic Clock Gating.
   4071  1.312   msaitoh 			 */
   4072  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   4073  1.312   msaitoh 			reg &= ~CTRL_EXT_DMA_DYN_CLK;
   4074  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4075  1.312   msaitoh 			break;
   4076  1.312   msaitoh 		case WM_T_82573:
   4077  1.312   msaitoh 		case WM_T_82574:
   4078  1.312   msaitoh 		case WM_T_82583:
   4079  1.312   msaitoh 			if ((sc->sc_type == WM_T_82574)
   4080  1.312   msaitoh 			    || (sc->sc_type == WM_T_82583))
   4081  1.312   msaitoh 				tarc0 |= __BIT(26); /* TARC0 bit 26 */
   4082  1.312   msaitoh 
   4083  1.312   msaitoh 			/* Extended Device Control */
   4084  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   4085  1.312   msaitoh 			reg &= ~__BIT(23);	/* Clear bit 23 */
   4086  1.312   msaitoh 			reg |= __BIT(22);	/* Set bit 22 */
   4087  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4088  1.312   msaitoh 
   4089  1.312   msaitoh 			/* Device Control */
   4090  1.312   msaitoh 			sc->sc_ctrl &= ~__BIT(29);	/* Clear bit 29 */
   4091  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4092  1.312   msaitoh 
   4093  1.312   msaitoh 			/* PCIe Control Register */
   4094  1.350   msaitoh 			/*
   4095  1.350   msaitoh 			 * 82573 Errata (unknown).
   4096  1.350   msaitoh 			 *
   4097  1.350   msaitoh 			 * 82574 Errata 25 and 82583 Errata 12
   4098  1.350   msaitoh 			 * "Dropped Rx Packets":
   4099  1.350   msaitoh 			 *   NVM Image Version 2.1.4 and newer has no this bug.
   4100  1.350   msaitoh 			 */
   4101  1.350   msaitoh 			reg = CSR_READ(sc, WMREG_GCR);
   4102  1.350   msaitoh 			reg |= GCR_L1_ACT_WITHOUT_L0S_RX;
   4103  1.350   msaitoh 			CSR_WRITE(sc, WMREG_GCR, reg);
   4104  1.350   msaitoh 
   4105  1.312   msaitoh 			if ((sc->sc_type == WM_T_82574)
   4106  1.312   msaitoh 			    || (sc->sc_type == WM_T_82583)) {
   4107  1.312   msaitoh 				/*
   4108  1.312   msaitoh 				 * Document says this bit must be set for
   4109  1.312   msaitoh 				 * proper operation.
   4110  1.312   msaitoh 				 */
   4111  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_GCR);
   4112  1.312   msaitoh 				reg |= __BIT(22);
   4113  1.312   msaitoh 				CSR_WRITE(sc, WMREG_GCR, reg);
   4114  1.312   msaitoh 
   4115  1.312   msaitoh 				/*
   4116  1.312   msaitoh 				 * Apply workaround for hardware errata
   4117  1.312   msaitoh 				 * documented in errata docs Fixes issue where
   4118  1.312   msaitoh 				 * some error prone or unreliable PCIe
   4119  1.312   msaitoh 				 * completions are occurring, particularly
   4120  1.312   msaitoh 				 * with ASPM enabled. Without fix, issue can
   4121  1.312   msaitoh 				 * cause Tx timeouts.
   4122  1.312   msaitoh 				 */
   4123  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_GCR2);
   4124  1.312   msaitoh 				reg |= __BIT(0);
   4125  1.312   msaitoh 				CSR_WRITE(sc, WMREG_GCR2, reg);
   4126  1.312   msaitoh 			}
   4127  1.312   msaitoh 			break;
   4128  1.312   msaitoh 		case WM_T_80003:
   4129  1.312   msaitoh 			/* TARC0 */
   4130  1.312   msaitoh 			if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
   4131  1.312   msaitoh 			    || (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   4132  1.312   msaitoh 				tarc0 &= ~__BIT(20); /* Clear bits 20 */
   4133  1.312   msaitoh 
   4134  1.312   msaitoh 			/* TARC1 bit 28 */
   4135  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   4136  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   4137  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   4138  1.312   msaitoh 			else
   4139  1.312   msaitoh 				tarc1 |= __BIT(28);
   4140  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   4141  1.312   msaitoh 			break;
   4142  1.312   msaitoh 		case WM_T_ICH8:
   4143  1.312   msaitoh 		case WM_T_ICH9:
   4144  1.312   msaitoh 		case WM_T_ICH10:
   4145  1.312   msaitoh 		case WM_T_PCH:
   4146  1.312   msaitoh 		case WM_T_PCH2:
   4147  1.312   msaitoh 		case WM_T_PCH_LPT:
   4148  1.393   msaitoh 		case WM_T_PCH_SPT:
   4149  1.570   msaitoh 		case WM_T_PCH_CNP:
   4150  1.393   msaitoh 			/* TARC0 */
   4151  1.540   msaitoh 			if (sc->sc_type == WM_T_ICH8) {
   4152  1.312   msaitoh 				/* Set TARC0 bits 29 and 28 */
   4153  1.312   msaitoh 				tarc0 |= __BITS(29, 28);
   4154  1.540   msaitoh 			} else if (sc->sc_type == WM_T_PCH_SPT) {
   4155  1.540   msaitoh 				tarc0 |= __BIT(29);
   4156  1.540   msaitoh 				/*
   4157  1.540   msaitoh 				 *  Drop bit 28. From Linux.
   4158  1.540   msaitoh 				 * See I218/I219 spec update
   4159  1.540   msaitoh 				 * "5. Buffer Overrun While the I219 is
   4160  1.540   msaitoh 				 * Processing DMA Transactions"
   4161  1.540   msaitoh 				 */
   4162  1.540   msaitoh 				tarc0 &= ~__BIT(28);
   4163  1.312   msaitoh 			}
   4164  1.312   msaitoh 			/* Set TARC0 bits 23,24,26,27 */
   4165  1.312   msaitoh 			tarc0 |= __BITS(27, 26) | __BITS(24, 23);
   4166  1.312   msaitoh 
   4167  1.312   msaitoh 			/* CTRL_EXT */
   4168  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   4169  1.312   msaitoh 			reg |= __BIT(22);	/* Set bit 22 */
   4170  1.312   msaitoh 			/*
   4171  1.312   msaitoh 			 * Enable PHY low-power state when MAC is at D3
   4172  1.312   msaitoh 			 * w/o WoL
   4173  1.312   msaitoh 			 */
   4174  1.312   msaitoh 			if (sc->sc_type >= WM_T_PCH)
   4175  1.312   msaitoh 				reg |= CTRL_EXT_PHYPDEN;
   4176  1.312   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4177  1.312   msaitoh 
   4178  1.312   msaitoh 			/* TARC1 */
   4179  1.312   msaitoh 			tarc1 = CSR_READ(sc, WMREG_TARC1);
   4180  1.312   msaitoh 			/* bit 28 */
   4181  1.312   msaitoh 			if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
   4182  1.312   msaitoh 				tarc1 &= ~__BIT(28);
   4183  1.312   msaitoh 			else
   4184  1.312   msaitoh 				tarc1 |= __BIT(28);
   4185  1.312   msaitoh 			tarc1 |= __BIT(24) | __BIT(26) | __BIT(30);
   4186  1.312   msaitoh 			CSR_WRITE(sc, WMREG_TARC1, tarc1);
   4187  1.312   msaitoh 
   4188  1.312   msaitoh 			/* Device Status */
   4189  1.312   msaitoh 			if (sc->sc_type == WM_T_ICH8) {
   4190  1.312   msaitoh 				reg = CSR_READ(sc, WMREG_STATUS);
   4191  1.312   msaitoh 				reg &= ~__BIT(31);
   4192  1.312   msaitoh 				CSR_WRITE(sc, WMREG_STATUS, reg);
   4193  1.312   msaitoh 
   4194  1.312   msaitoh 			}
   4195  1.312   msaitoh 
   4196  1.393   msaitoh 			/* IOSFPC */
   4197  1.393   msaitoh 			if (sc->sc_type == WM_T_PCH_SPT) {
   4198  1.393   msaitoh 				reg = CSR_READ(sc, WMREG_IOSFPC);
   4199  1.393   msaitoh 				reg |= RCTL_RDMTS_HEX; /* XXX RTCL bit? */
   4200  1.393   msaitoh 				CSR_WRITE(sc, WMREG_IOSFPC, reg);
   4201  1.393   msaitoh 			}
   4202  1.312   msaitoh 			/*
   4203  1.312   msaitoh 			 * Work-around descriptor data corruption issue during
   4204  1.312   msaitoh 			 * NFS v2 UDP traffic, just disable the NFS filtering
   4205  1.312   msaitoh 			 * capability.
   4206  1.312   msaitoh 			 */
   4207  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_RFCTL);
   4208  1.312   msaitoh 			reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS;
   4209  1.312   msaitoh 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   4210  1.312   msaitoh 			break;
   4211  1.312   msaitoh 		default:
   4212  1.312   msaitoh 			break;
   4213  1.312   msaitoh 		}
   4214  1.312   msaitoh 		CSR_WRITE(sc, WMREG_TARC0, tarc0);
   4215  1.312   msaitoh 
   4216  1.462   msaitoh 		switch (sc->sc_type) {
   4217  1.312   msaitoh 		/*
   4218  1.462   msaitoh 		 * 8257[12] Errata No.52, 82573 Errata No.43 and some others.
   4219  1.312   msaitoh 		 * Avoid RSS Hash Value bug.
   4220  1.312   msaitoh 		 */
   4221  1.312   msaitoh 		case WM_T_82571:
   4222  1.312   msaitoh 		case WM_T_82572:
   4223  1.312   msaitoh 		case WM_T_82573:
   4224  1.312   msaitoh 		case WM_T_80003:
   4225  1.312   msaitoh 		case WM_T_ICH8:
   4226  1.312   msaitoh 			reg = CSR_READ(sc, WMREG_RFCTL);
   4227  1.312   msaitoh 			reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS;
   4228  1.312   msaitoh 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   4229  1.312   msaitoh 			break;
   4230  1.466  knakahar 		case WM_T_82574:
   4231  1.466  knakahar 			/* use extened Rx descriptor. */
   4232  1.466  knakahar 			reg = CSR_READ(sc, WMREG_RFCTL);
   4233  1.466  knakahar 			reg |= WMREG_RFCTL_EXSTEN;
   4234  1.466  knakahar 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   4235  1.466  knakahar 			break;
   4236  1.464   msaitoh 		default:
   4237  1.464   msaitoh 			break;
   4238  1.464   msaitoh 		}
   4239  1.464   msaitoh 	} else if ((sc->sc_type >= WM_T_82575) && (sc->sc_type <= WM_T_I211)) {
   4240  1.462   msaitoh 		/*
   4241  1.462   msaitoh 		 * 82575 Errata XXX, 82576 Errata 46, 82580 Errata 24,
   4242  1.462   msaitoh 		 * I350 Errata 37, I210 Errata No. 31 and I211 Errata No. 11:
   4243  1.462   msaitoh 		 * "Certain Malformed IPv6 Extension Headers are Not Processed
   4244  1.462   msaitoh 		 * Correctly by the Device"
   4245  1.462   msaitoh 		 *
   4246  1.462   msaitoh 		 * I354(C2000) Errata AVR53:
   4247  1.462   msaitoh 		 * "Malformed IPv6 Extension Headers May Result in LAN Device
   4248  1.462   msaitoh 		 * Hang"
   4249  1.462   msaitoh 		 */
   4250  1.464   msaitoh 		reg = CSR_READ(sc, WMREG_RFCTL);
   4251  1.464   msaitoh 		reg |= WMREG_RFCTL_IPV6EXDIS;
   4252  1.464   msaitoh 		CSR_WRITE(sc, WMREG_RFCTL, reg);
   4253  1.312   msaitoh 	}
   4254  1.312   msaitoh }
   4255  1.312   msaitoh 
   4256  1.320   msaitoh static uint32_t
   4257  1.320   msaitoh wm_rxpbs_adjust_82580(uint32_t val)
   4258  1.320   msaitoh {
   4259  1.320   msaitoh 	uint32_t rv = 0;
   4260  1.320   msaitoh 
   4261  1.320   msaitoh 	if (val < __arraycount(wm_82580_rxpbs_table))
   4262  1.320   msaitoh 		rv = wm_82580_rxpbs_table[val];
   4263  1.320   msaitoh 
   4264  1.320   msaitoh 	return rv;
   4265  1.320   msaitoh }
   4266  1.320   msaitoh 
   4267  1.447   msaitoh /*
   4268  1.447   msaitoh  * wm_reset_phy:
   4269  1.447   msaitoh  *
   4270  1.447   msaitoh  *	generic PHY reset function.
   4271  1.447   msaitoh  *	Same as e1000_phy_hw_reset_generic()
   4272  1.447   msaitoh  */
   4273  1.447   msaitoh static void
   4274  1.447   msaitoh wm_reset_phy(struct wm_softc *sc)
   4275  1.447   msaitoh {
   4276  1.447   msaitoh 	uint32_t reg;
   4277  1.447   msaitoh 
   4278  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   4279  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   4280  1.447   msaitoh 	if (wm_phy_resetisblocked(sc))
   4281  1.447   msaitoh 		return;
   4282  1.447   msaitoh 
   4283  1.447   msaitoh 	sc->phy.acquire(sc);
   4284  1.447   msaitoh 
   4285  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL);
   4286  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);
   4287  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   4288  1.447   msaitoh 
   4289  1.447   msaitoh 	delay(sc->phy.reset_delay_us);
   4290  1.447   msaitoh 
   4291  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   4292  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   4293  1.447   msaitoh 
   4294  1.447   msaitoh 	delay(150);
   4295  1.447   msaitoh 
   4296  1.447   msaitoh 	sc->phy.release(sc);
   4297  1.447   msaitoh 
   4298  1.447   msaitoh 	wm_get_cfg_done(sc);
   4299  1.517   msaitoh 	wm_phy_post_reset(sc);
   4300  1.447   msaitoh }
   4301  1.447   msaitoh 
   4302  1.554  knakahar /*
   4303  1.554  knakahar  * Only used by WM_T_PCH_SPT which does not use multiqueue,
   4304  1.554  knakahar  * so it is enough to check sc->sc_queue[0] only.
   4305  1.554  knakahar  */
   4306  1.443   msaitoh static void
   4307  1.443   msaitoh wm_flush_desc_rings(struct wm_softc *sc)
   4308  1.443   msaitoh {
   4309  1.443   msaitoh 	pcireg_t preg;
   4310  1.443   msaitoh 	uint32_t reg;
   4311  1.524   msaitoh 	struct wm_txqueue *txq;
   4312  1.524   msaitoh 	wiseman_txdesc_t *txd;
   4313  1.443   msaitoh 	int nexttx;
   4314  1.524   msaitoh 	uint32_t rctl;
   4315  1.443   msaitoh 
   4316  1.443   msaitoh 	/* First, disable MULR fix in FEXTNVM11 */
   4317  1.443   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM11);
   4318  1.443   msaitoh 	reg |= FEXTNVM11_DIS_MULRFIX;
   4319  1.443   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM11, reg);
   4320  1.443   msaitoh 
   4321  1.443   msaitoh 	preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, WM_PCI_DESCRING_STATUS);
   4322  1.443   msaitoh 	reg = CSR_READ(sc, WMREG_TDLEN(0));
   4323  1.524   msaitoh 	if (((preg & DESCRING_STATUS_FLUSH_REQ) == 0) || (reg == 0))
   4324  1.524   msaitoh 		return;
   4325  1.443   msaitoh 
   4326  1.524   msaitoh 	/* TX */
   4327  1.524   msaitoh 	printf("%s: Need TX flush (reg = %08x, len = %u)\n",
   4328  1.524   msaitoh 	    device_xname(sc->sc_dev), preg, reg);
   4329  1.524   msaitoh 	reg = CSR_READ(sc, WMREG_TCTL);
   4330  1.524   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, reg | TCTL_EN);
   4331  1.524   msaitoh 
   4332  1.524   msaitoh 	txq = &sc->sc_queue[0].wmq_txq;
   4333  1.524   msaitoh 	nexttx = txq->txq_next;
   4334  1.524   msaitoh 	txd = &txq->txq_descs[nexttx];
   4335  1.524   msaitoh 	wm_set_dma_addr(&txd->wtx_addr, WM_CDTXADDR(txq, nexttx));
   4336  1.573   msaitoh 	txd->wtx_cmdlen = htole32(WTX_CMD_IFCS | 512);
   4337  1.524   msaitoh 	txd->wtx_fields.wtxu_status = 0;
   4338  1.524   msaitoh 	txd->wtx_fields.wtxu_options = 0;
   4339  1.524   msaitoh 	txd->wtx_fields.wtxu_vlan = 0;
   4340  1.443   msaitoh 
   4341  1.524   msaitoh 	bus_space_barrier(sc->sc_st, sc->sc_sh, 0, 0,
   4342  1.524   msaitoh 	    BUS_SPACE_BARRIER_WRITE);
   4343  1.443   msaitoh 
   4344  1.524   msaitoh 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   4345  1.524   msaitoh 	CSR_WRITE(sc, WMREG_TDT(0), txq->txq_next);
   4346  1.524   msaitoh 	bus_space_barrier(sc->sc_st, sc->sc_sh, 0, 0,
   4347  1.524   msaitoh 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
   4348  1.524   msaitoh 	delay(250);
   4349  1.524   msaitoh 
   4350  1.443   msaitoh 	preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, WM_PCI_DESCRING_STATUS);
   4351  1.524   msaitoh 	if ((preg & DESCRING_STATUS_FLUSH_REQ) == 0)
   4352  1.524   msaitoh 		return;
   4353  1.443   msaitoh 
   4354  1.524   msaitoh 	/* RX */
   4355  1.524   msaitoh 	printf("%s: Need RX flush (reg = %08x)\n",
   4356  1.524   msaitoh 	    device_xname(sc->sc_dev), preg);
   4357  1.524   msaitoh 	rctl = CSR_READ(sc, WMREG_RCTL);
   4358  1.524   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, rctl & ~RCTL_EN);
   4359  1.524   msaitoh 	CSR_WRITE_FLUSH(sc);
   4360  1.524   msaitoh 	delay(150);
   4361  1.443   msaitoh 
   4362  1.524   msaitoh 	reg = CSR_READ(sc, WMREG_RXDCTL(0));
   4363  1.524   msaitoh 	/* zero the lower 14 bits (prefetch and host thresholds) */
   4364  1.524   msaitoh 	reg &= 0xffffc000;
   4365  1.524   msaitoh 	/*
   4366  1.524   msaitoh 	 * update thresholds: prefetch threshold to 31, host threshold
   4367  1.524   msaitoh 	 * to 1 and make sure the granularity is "descriptors" and not
   4368  1.524   msaitoh 	 * "cache lines"
   4369  1.524   msaitoh 	 */
   4370  1.524   msaitoh 	reg |= (0x1f | (1 << 8) | RXDCTL_GRAN);
   4371  1.524   msaitoh 	CSR_WRITE(sc, WMREG_RXDCTL(0), reg);
   4372  1.443   msaitoh 
   4373  1.524   msaitoh 	/*
   4374  1.524   msaitoh 	 * momentarily enable the RX ring for the changes to take
   4375  1.524   msaitoh 	 * effect
   4376  1.524   msaitoh 	 */
   4377  1.524   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, rctl | RCTL_EN);
   4378  1.524   msaitoh 	CSR_WRITE_FLUSH(sc);
   4379  1.524   msaitoh 	delay(150);
   4380  1.524   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, rctl & ~RCTL_EN);
   4381  1.443   msaitoh }
   4382  1.443   msaitoh 
   4383    1.1   thorpej /*
   4384  1.281   msaitoh  * wm_reset:
   4385  1.232    bouyer  *
   4386  1.281   msaitoh  *	Reset the i82542 chip.
   4387  1.232    bouyer  */
   4388  1.281   msaitoh static void
   4389  1.281   msaitoh wm_reset(struct wm_softc *sc)
   4390  1.232    bouyer {
   4391  1.281   msaitoh 	int phy_reset = 0;
   4392  1.364  knakahar 	int i, error = 0;
   4393  1.424   msaitoh 	uint32_t reg;
   4394  1.531   msaitoh 	uint16_t kmreg;
   4395  1.531   msaitoh 	int rv;
   4396  1.232    bouyer 
   4397  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   4398  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   4399  1.420   msaitoh 	KASSERT(sc->sc_type != 0);
   4400  1.420   msaitoh 
   4401  1.232    bouyer 	/*
   4402  1.281   msaitoh 	 * Allocate on-chip memory according to the MTU size.
   4403  1.281   msaitoh 	 * The Packet Buffer Allocation register must be written
   4404  1.281   msaitoh 	 * before the chip is reset.
   4405  1.232    bouyer 	 */
   4406  1.281   msaitoh 	switch (sc->sc_type) {
   4407  1.281   msaitoh 	case WM_T_82547:
   4408  1.281   msaitoh 	case WM_T_82547_2:
   4409  1.281   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   4410  1.281   msaitoh 		    PBA_22K : PBA_30K;
   4411  1.405  knakahar 		for (i = 0; i < sc->sc_nqueues; i++) {
   4412  1.405  knakahar 			struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   4413  1.364  knakahar 			txq->txq_fifo_head = 0;
   4414  1.364  knakahar 			txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
   4415  1.364  knakahar 			txq->txq_fifo_size =
   4416  1.364  knakahar 				(PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
   4417  1.364  knakahar 			txq->txq_fifo_stall = 0;
   4418  1.364  knakahar 		}
   4419  1.281   msaitoh 		break;
   4420  1.281   msaitoh 	case WM_T_82571:
   4421  1.281   msaitoh 	case WM_T_82572:
   4422  1.281   msaitoh 	case WM_T_82575:	/* XXX need special handing for jumbo frames */
   4423  1.281   msaitoh 	case WM_T_80003:
   4424  1.281   msaitoh 		sc->sc_pba = PBA_32K;
   4425  1.281   msaitoh 		break;
   4426  1.281   msaitoh 	case WM_T_82573:
   4427  1.281   msaitoh 		sc->sc_pba = PBA_12K;
   4428  1.281   msaitoh 		break;
   4429  1.281   msaitoh 	case WM_T_82574:
   4430  1.281   msaitoh 	case WM_T_82583:
   4431  1.281   msaitoh 		sc->sc_pba = PBA_20K;
   4432  1.281   msaitoh 		break;
   4433  1.320   msaitoh 	case WM_T_82576:
   4434  1.320   msaitoh 		sc->sc_pba = CSR_READ(sc, WMREG_RXPBS);
   4435  1.320   msaitoh 		sc->sc_pba &= RXPBS_SIZE_MASK_82576;
   4436  1.320   msaitoh 		break;
   4437  1.320   msaitoh 	case WM_T_82580:
   4438  1.320   msaitoh 	case WM_T_I350:
   4439  1.320   msaitoh 	case WM_T_I354:
   4440  1.320   msaitoh 		sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS));
   4441  1.320   msaitoh 		break;
   4442  1.320   msaitoh 	case WM_T_I210:
   4443  1.320   msaitoh 	case WM_T_I211:
   4444  1.320   msaitoh 		sc->sc_pba = PBA_34K;
   4445  1.320   msaitoh 		break;
   4446  1.281   msaitoh 	case WM_T_ICH8:
   4447  1.312   msaitoh 		/* Workaround for a bit corruption issue in FIFO memory */
   4448  1.281   msaitoh 		sc->sc_pba = PBA_8K;
   4449  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBS, PBA_16K);
   4450  1.281   msaitoh 		break;
   4451  1.281   msaitoh 	case WM_T_ICH9:
   4452  1.281   msaitoh 	case WM_T_ICH10:
   4453  1.318   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ?
   4454  1.318   msaitoh 		    PBA_14K : PBA_10K;
   4455  1.232    bouyer 		break;
   4456  1.281   msaitoh 	case WM_T_PCH:
   4457  1.570   msaitoh 	case WM_T_PCH2:	/* XXX 14K? */
   4458  1.281   msaitoh 	case WM_T_PCH_LPT:
   4459  1.392   msaitoh 	case WM_T_PCH_SPT:
   4460  1.570   msaitoh 	case WM_T_PCH_CNP:
   4461  1.281   msaitoh 		sc->sc_pba = PBA_26K;
   4462  1.232    bouyer 		break;
   4463  1.232    bouyer 	default:
   4464  1.281   msaitoh 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   4465  1.281   msaitoh 		    PBA_40K : PBA_48K;
   4466  1.281   msaitoh 		break;
   4467  1.232    bouyer 	}
   4468  1.320   msaitoh 	/*
   4469  1.320   msaitoh 	 * Only old or non-multiqueue devices have the PBA register
   4470  1.320   msaitoh 	 * XXX Need special handling for 82575.
   4471  1.320   msaitoh 	 */
   4472  1.320   msaitoh 	if (((sc->sc_flags & WM_F_NEWQUEUE) == 0)
   4473  1.320   msaitoh 	    || (sc->sc_type == WM_T_82575))
   4474  1.320   msaitoh 		CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
   4475  1.232    bouyer 
   4476  1.281   msaitoh 	/* Prevent the PCI-E bus from sticking */
   4477  1.281   msaitoh 	if (sc->sc_flags & WM_F_PCIE) {
   4478  1.281   msaitoh 		int timeout = 800;
   4479  1.232    bouyer 
   4480  1.281   msaitoh 		sc->sc_ctrl |= CTRL_GIO_M_DIS;
   4481  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4482  1.232    bouyer 
   4483  1.281   msaitoh 		while (timeout--) {
   4484  1.281   msaitoh 			if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA)
   4485  1.281   msaitoh 			    == 0)
   4486  1.281   msaitoh 				break;
   4487  1.281   msaitoh 			delay(100);
   4488  1.281   msaitoh 		}
   4489  1.511   msaitoh 		if (timeout == 0)
   4490  1.511   msaitoh 			device_printf(sc->sc_dev,
   4491  1.511   msaitoh 			    "failed to disable busmastering\n");
   4492  1.232    bouyer 	}
   4493  1.232    bouyer 
   4494  1.281   msaitoh 	/* Set the completion timeout for interface */
   4495  1.281   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   4496  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   4497  1.282   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   4498  1.282   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
   4499  1.281   msaitoh 		wm_set_pcie_completion_timeout(sc);
   4500  1.232    bouyer 
   4501  1.281   msaitoh 	/* Clear interrupt */
   4502  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   4503  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   4504  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   4505  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   4506  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   4507  1.335   msaitoh 		} else {
   4508  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   4509  1.335   msaitoh 		}
   4510  1.335   msaitoh 	}
   4511  1.232    bouyer 
   4512  1.281   msaitoh 	/* Stop the transmit and receive processes. */
   4513  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, 0);
   4514  1.281   msaitoh 	sc->sc_rctl &= ~RCTL_EN;
   4515  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP);
   4516  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   4517  1.232    bouyer 
   4518  1.281   msaitoh 	/* XXX set_tbi_sbp_82543() */
   4519  1.232    bouyer 
   4520  1.281   msaitoh 	delay(10*1000);
   4521  1.232    bouyer 
   4522  1.281   msaitoh 	/* Must acquire the MDIO ownership before MAC reset */
   4523  1.281   msaitoh 	switch (sc->sc_type) {
   4524  1.281   msaitoh 	case WM_T_82573:
   4525  1.281   msaitoh 	case WM_T_82574:
   4526  1.281   msaitoh 	case WM_T_82583:
   4527  1.281   msaitoh 		error = wm_get_hw_semaphore_82573(sc);
   4528  1.281   msaitoh 		break;
   4529  1.281   msaitoh 	default:
   4530  1.281   msaitoh 		break;
   4531  1.281   msaitoh 	}
   4532  1.232    bouyer 
   4533  1.281   msaitoh 	/*
   4534  1.281   msaitoh 	 * 82541 Errata 29? & 82547 Errata 28?
   4535  1.281   msaitoh 	 * See also the description about PHY_RST bit in CTRL register
   4536  1.281   msaitoh 	 * in 8254x_GBe_SDM.pdf.
   4537  1.281   msaitoh 	 */
   4538  1.281   msaitoh 	if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) {
   4539  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL,
   4540  1.281   msaitoh 		    CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
   4541  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   4542  1.281   msaitoh 		delay(5000);
   4543  1.281   msaitoh 	}
   4544  1.232    bouyer 
   4545  1.281   msaitoh 	switch (sc->sc_type) {
   4546  1.281   msaitoh 	case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */
   4547  1.281   msaitoh 	case WM_T_82541:
   4548  1.281   msaitoh 	case WM_T_82541_2:
   4549  1.281   msaitoh 	case WM_T_82547:
   4550  1.281   msaitoh 	case WM_T_82547_2:
   4551  1.281   msaitoh 		/*
   4552  1.281   msaitoh 		 * On some chipsets, a reset through a memory-mapped write
   4553  1.281   msaitoh 		 * cycle can cause the chip to reset before completing the
   4554  1.281   msaitoh 		 * write cycle.  This causes major headache that can be
   4555  1.281   msaitoh 		 * avoided by issuing the reset via indirect register writes
   4556  1.281   msaitoh 		 * through I/O space.
   4557  1.281   msaitoh 		 *
   4558  1.281   msaitoh 		 * So, if we successfully mapped the I/O BAR at attach time,
   4559  1.281   msaitoh 		 * use that.  Otherwise, try our luck with a memory-mapped
   4560  1.281   msaitoh 		 * reset.
   4561  1.281   msaitoh 		 */
   4562  1.281   msaitoh 		if (sc->sc_flags & WM_F_IOH_VALID)
   4563  1.281   msaitoh 			wm_io_write(sc, WMREG_CTRL, CTRL_RST);
   4564  1.281   msaitoh 		else
   4565  1.281   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
   4566  1.281   msaitoh 		break;
   4567  1.281   msaitoh 	case WM_T_82545_3:
   4568  1.281   msaitoh 	case WM_T_82546_3:
   4569  1.281   msaitoh 		/* Use the shadow control register on these chips. */
   4570  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
   4571  1.281   msaitoh 		break;
   4572  1.281   msaitoh 	case WM_T_80003:
   4573  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
   4574  1.424   msaitoh 		sc->phy.acquire(sc);
   4575  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg);
   4576  1.424   msaitoh 		sc->phy.release(sc);
   4577  1.281   msaitoh 		break;
   4578  1.281   msaitoh 	case WM_T_ICH8:
   4579  1.281   msaitoh 	case WM_T_ICH9:
   4580  1.281   msaitoh 	case WM_T_ICH10:
   4581  1.281   msaitoh 	case WM_T_PCH:
   4582  1.281   msaitoh 	case WM_T_PCH2:
   4583  1.281   msaitoh 	case WM_T_PCH_LPT:
   4584  1.392   msaitoh 	case WM_T_PCH_SPT:
   4585  1.570   msaitoh 	case WM_T_PCH_CNP:
   4586  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
   4587  1.386   msaitoh 		if (wm_phy_resetisblocked(sc) == false) {
   4588  1.232    bouyer 			/*
   4589  1.281   msaitoh 			 * Gate automatic PHY configuration by hardware on
   4590  1.281   msaitoh 			 * non-managed 82579
   4591  1.232    bouyer 			 */
   4592  1.281   msaitoh 			if ((sc->sc_type == WM_T_PCH2)
   4593  1.281   msaitoh 			    && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
   4594  1.380   msaitoh 				== 0))
   4595  1.392   msaitoh 				wm_gate_hw_phy_config_ich8lan(sc, true);
   4596  1.232    bouyer 
   4597  1.281   msaitoh 			reg |= CTRL_PHY_RESET;
   4598  1.281   msaitoh 			phy_reset = 1;
   4599  1.394   msaitoh 		} else
   4600  1.394   msaitoh 			printf("XXX reset is blocked!!!\n");
   4601  1.424   msaitoh 		sc->phy.acquire(sc);
   4602  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg);
   4603  1.281   msaitoh 		/* Don't insert a completion barrier when reset */
   4604  1.281   msaitoh 		delay(20*1000);
   4605  1.424   msaitoh 		mutex_exit(sc->sc_ich_phymtx);
   4606  1.281   msaitoh 		break;
   4607  1.304   msaitoh 	case WM_T_82580:
   4608  1.304   msaitoh 	case WM_T_I350:
   4609  1.304   msaitoh 	case WM_T_I354:
   4610  1.304   msaitoh 	case WM_T_I210:
   4611  1.304   msaitoh 	case WM_T_I211:
   4612  1.304   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
   4613  1.304   msaitoh 		if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII)
   4614  1.304   msaitoh 			CSR_WRITE_FLUSH(sc);
   4615  1.304   msaitoh 		delay(5000);
   4616  1.304   msaitoh 		break;
   4617  1.281   msaitoh 	case WM_T_82542_2_0:
   4618  1.281   msaitoh 	case WM_T_82542_2_1:
   4619  1.281   msaitoh 	case WM_T_82543:
   4620  1.281   msaitoh 	case WM_T_82540:
   4621  1.281   msaitoh 	case WM_T_82545:
   4622  1.281   msaitoh 	case WM_T_82546:
   4623  1.281   msaitoh 	case WM_T_82571:
   4624  1.281   msaitoh 	case WM_T_82572:
   4625  1.281   msaitoh 	case WM_T_82573:
   4626  1.281   msaitoh 	case WM_T_82574:
   4627  1.281   msaitoh 	case WM_T_82575:
   4628  1.281   msaitoh 	case WM_T_82576:
   4629  1.281   msaitoh 	case WM_T_82583:
   4630  1.281   msaitoh 	default:
   4631  1.281   msaitoh 		/* Everything else can safely use the documented method. */
   4632  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
   4633  1.281   msaitoh 		break;
   4634  1.281   msaitoh 	}
   4635  1.232    bouyer 
   4636  1.281   msaitoh 	/* Must release the MDIO ownership after MAC reset */
   4637  1.281   msaitoh 	switch (sc->sc_type) {
   4638  1.281   msaitoh 	case WM_T_82573:
   4639  1.281   msaitoh 	case WM_T_82574:
   4640  1.281   msaitoh 	case WM_T_82583:
   4641  1.281   msaitoh 		if (error == 0)
   4642  1.281   msaitoh 			wm_put_hw_semaphore_82573(sc);
   4643  1.281   msaitoh 		break;
   4644  1.281   msaitoh 	default:
   4645  1.281   msaitoh 		break;
   4646  1.232    bouyer 	}
   4647  1.232    bouyer 
   4648  1.437   msaitoh 	if (phy_reset != 0)
   4649  1.281   msaitoh 		wm_get_cfg_done(sc);
   4650  1.232    bouyer 
   4651  1.281   msaitoh 	/* reload EEPROM */
   4652  1.281   msaitoh 	switch (sc->sc_type) {
   4653  1.281   msaitoh 	case WM_T_82542_2_0:
   4654  1.281   msaitoh 	case WM_T_82542_2_1:
   4655  1.281   msaitoh 	case WM_T_82543:
   4656  1.281   msaitoh 	case WM_T_82544:
   4657  1.281   msaitoh 		delay(10);
   4658  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
   4659  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4660  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   4661  1.281   msaitoh 		delay(2000);
   4662  1.281   msaitoh 		break;
   4663  1.281   msaitoh 	case WM_T_82540:
   4664  1.281   msaitoh 	case WM_T_82545:
   4665  1.281   msaitoh 	case WM_T_82545_3:
   4666  1.281   msaitoh 	case WM_T_82546:
   4667  1.281   msaitoh 	case WM_T_82546_3:
   4668  1.281   msaitoh 		delay(5*1000);
   4669  1.281   msaitoh 		/* XXX Disable HW ARPs on ASF enabled adapters */
   4670  1.281   msaitoh 		break;
   4671  1.281   msaitoh 	case WM_T_82541:
   4672  1.281   msaitoh 	case WM_T_82541_2:
   4673  1.281   msaitoh 	case WM_T_82547:
   4674  1.281   msaitoh 	case WM_T_82547_2:
   4675  1.281   msaitoh 		delay(20000);
   4676  1.281   msaitoh 		/* XXX Disable HW ARPs on ASF enabled adapters */
   4677  1.281   msaitoh 		break;
   4678  1.281   msaitoh 	case WM_T_82571:
   4679  1.281   msaitoh 	case WM_T_82572:
   4680  1.281   msaitoh 	case WM_T_82573:
   4681  1.281   msaitoh 	case WM_T_82574:
   4682  1.281   msaitoh 	case WM_T_82583:
   4683  1.281   msaitoh 		if (sc->sc_flags & WM_F_EEPROM_FLASH) {
   4684  1.281   msaitoh 			delay(10);
   4685  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
   4686  1.281   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   4687  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   4688  1.232    bouyer 		}
   4689  1.281   msaitoh 		/* check EECD_EE_AUTORD */
   4690  1.281   msaitoh 		wm_get_auto_rd_done(sc);
   4691  1.281   msaitoh 		/*
   4692  1.281   msaitoh 		 * Phy configuration from NVM just starts after EECD_AUTO_RD
   4693  1.281   msaitoh 		 * is set.
   4694  1.281   msaitoh 		 */
   4695  1.281   msaitoh 		if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574)
   4696  1.281   msaitoh 		    || (sc->sc_type == WM_T_82583))
   4697  1.281   msaitoh 			delay(25*1000);
   4698  1.281   msaitoh 		break;
   4699  1.281   msaitoh 	case WM_T_82575:
   4700  1.281   msaitoh 	case WM_T_82576:
   4701  1.281   msaitoh 	case WM_T_82580:
   4702  1.281   msaitoh 	case WM_T_I350:
   4703  1.281   msaitoh 	case WM_T_I354:
   4704  1.281   msaitoh 	case WM_T_I210:
   4705  1.281   msaitoh 	case WM_T_I211:
   4706  1.281   msaitoh 	case WM_T_80003:
   4707  1.281   msaitoh 		/* check EECD_EE_AUTORD */
   4708  1.281   msaitoh 		wm_get_auto_rd_done(sc);
   4709  1.281   msaitoh 		break;
   4710  1.281   msaitoh 	case WM_T_ICH8:
   4711  1.281   msaitoh 	case WM_T_ICH9:
   4712  1.281   msaitoh 	case WM_T_ICH10:
   4713  1.281   msaitoh 	case WM_T_PCH:
   4714  1.281   msaitoh 	case WM_T_PCH2:
   4715  1.281   msaitoh 	case WM_T_PCH_LPT:
   4716  1.392   msaitoh 	case WM_T_PCH_SPT:
   4717  1.570   msaitoh 	case WM_T_PCH_CNP:
   4718  1.281   msaitoh 		break;
   4719  1.281   msaitoh 	default:
   4720  1.281   msaitoh 		panic("%s: unknown type\n", __func__);
   4721  1.232    bouyer 	}
   4722  1.281   msaitoh 
   4723  1.281   msaitoh 	/* Check whether EEPROM is present or not */
   4724  1.281   msaitoh 	switch (sc->sc_type) {
   4725  1.281   msaitoh 	case WM_T_82575:
   4726  1.281   msaitoh 	case WM_T_82576:
   4727  1.281   msaitoh 	case WM_T_82580:
   4728  1.281   msaitoh 	case WM_T_I350:
   4729  1.281   msaitoh 	case WM_T_I354:
   4730  1.281   msaitoh 	case WM_T_ICH8:
   4731  1.281   msaitoh 	case WM_T_ICH9:
   4732  1.281   msaitoh 		if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
   4733  1.281   msaitoh 			/* Not found */
   4734  1.281   msaitoh 			sc->sc_flags |= WM_F_EEPROM_INVALID;
   4735  1.325   msaitoh 			if (sc->sc_type == WM_T_82575)
   4736  1.281   msaitoh 				wm_reset_init_script_82575(sc);
   4737  1.232    bouyer 		}
   4738  1.281   msaitoh 		break;
   4739  1.281   msaitoh 	default:
   4740  1.281   msaitoh 		break;
   4741  1.281   msaitoh 	}
   4742  1.281   msaitoh 
   4743  1.517   msaitoh 	if (phy_reset != 0)
   4744  1.517   msaitoh 		wm_phy_post_reset(sc);
   4745  1.517   msaitoh 
   4746  1.300   msaitoh 	if ((sc->sc_type == WM_T_82580)
   4747  1.281   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
   4748  1.281   msaitoh 		/* clear global device reset status bit */
   4749  1.281   msaitoh 		CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
   4750  1.281   msaitoh 	}
   4751  1.281   msaitoh 
   4752  1.281   msaitoh 	/* Clear any pending interrupt events. */
   4753  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   4754  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_ICR);
   4755  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   4756  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   4757  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   4758  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   4759  1.335   msaitoh 		} else
   4760  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   4761  1.335   msaitoh 	}
   4762  1.281   msaitoh 
   4763  1.510   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   4764  1.510   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   4765  1.510   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   4766  1.570   msaitoh 	    || (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
   4767  1.510   msaitoh 		reg = CSR_READ(sc, WMREG_KABGTXD);
   4768  1.510   msaitoh 		reg |= KABGTXD_BGSQLBIAS;
   4769  1.510   msaitoh 		CSR_WRITE(sc, WMREG_KABGTXD, reg);
   4770  1.510   msaitoh 	}
   4771  1.510   msaitoh 
   4772  1.281   msaitoh 	/* reload sc_ctrl */
   4773  1.281   msaitoh 	sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   4774  1.281   msaitoh 
   4775  1.572   msaitoh 	if (sc->sc_type == WM_T_I354) {
   4776  1.572   msaitoh #if 0
   4777  1.572   msaitoh 		/* I354 uses an external PHY */
   4778  1.572   msaitoh 		wm_set_eee_i354(sc);
   4779  1.572   msaitoh #endif
   4780  1.572   msaitoh 	} else if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211))
   4781  1.281   msaitoh 		wm_set_eee_i350(sc);
   4782  1.281   msaitoh 
   4783  1.281   msaitoh 	/*
   4784  1.281   msaitoh 	 * For PCH, this write will make sure that any noise will be detected
   4785  1.281   msaitoh 	 * as a CRC error and be dropped rather than show up as a bad packet
   4786  1.281   msaitoh 	 * to the DMA engine
   4787  1.281   msaitoh 	 */
   4788  1.281   msaitoh 	if (sc->sc_type == WM_T_PCH)
   4789  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565);
   4790  1.281   msaitoh 
   4791  1.380   msaitoh 	if (sc->sc_type >= WM_T_82544)
   4792  1.281   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   4793  1.281   msaitoh 
   4794  1.325   msaitoh 	wm_reset_mdicnfg_82580(sc);
   4795  1.332   msaitoh 
   4796  1.332   msaitoh 	if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0)
   4797  1.332   msaitoh 		wm_pll_workaround_i210(sc);
   4798  1.531   msaitoh 
   4799  1.531   msaitoh 	if (sc->sc_type == WM_T_80003) {
   4800  1.531   msaitoh 		/* default to TRUE to enable the MDIC W/A */
   4801  1.531   msaitoh 		sc->sc_flags |= WM_F_80003_MDIC_WA;
   4802  1.531   msaitoh 
   4803  1.531   msaitoh 		rv = wm_kmrn_readreg(sc,
   4804  1.531   msaitoh 		    KUMCTRLSTA_OFFSET >> KUMCTRLSTA_OFFSET_SHIFT, &kmreg);
   4805  1.531   msaitoh 		if (rv == 0) {
   4806  1.531   msaitoh 			if ((kmreg & KUMCTRLSTA_OPMODE_MASK)
   4807  1.531   msaitoh 			    == KUMCTRLSTA_OPMODE_INBAND_MDIO)
   4808  1.531   msaitoh 				sc->sc_flags &= ~WM_F_80003_MDIC_WA;
   4809  1.531   msaitoh 			else
   4810  1.531   msaitoh 				sc->sc_flags |= WM_F_80003_MDIC_WA;
   4811  1.531   msaitoh 		}
   4812  1.531   msaitoh 	}
   4813  1.281   msaitoh }
   4814  1.281   msaitoh 
   4815  1.281   msaitoh /*
   4816  1.281   msaitoh  * wm_add_rxbuf:
   4817  1.281   msaitoh  *
   4818  1.281   msaitoh  *	Add a receive buffer to the indiciated descriptor.
   4819  1.281   msaitoh  */
   4820  1.281   msaitoh static int
   4821  1.362  knakahar wm_add_rxbuf(struct wm_rxqueue *rxq, int idx)
   4822  1.281   msaitoh {
   4823  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   4824  1.356  knakahar 	struct wm_rxsoft *rxs = &rxq->rxq_soft[idx];
   4825  1.281   msaitoh 	struct mbuf *m;
   4826  1.281   msaitoh 	int error;
   4827  1.281   msaitoh 
   4828  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   4829  1.281   msaitoh 
   4830  1.281   msaitoh 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   4831  1.281   msaitoh 	if (m == NULL)
   4832  1.281   msaitoh 		return ENOBUFS;
   4833  1.281   msaitoh 
   4834  1.281   msaitoh 	MCLGET(m, M_DONTWAIT);
   4835  1.281   msaitoh 	if ((m->m_flags & M_EXT) == 0) {
   4836  1.281   msaitoh 		m_freem(m);
   4837  1.281   msaitoh 		return ENOBUFS;
   4838  1.281   msaitoh 	}
   4839  1.281   msaitoh 
   4840  1.281   msaitoh 	if (rxs->rxs_mbuf != NULL)
   4841  1.281   msaitoh 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   4842  1.281   msaitoh 
   4843  1.281   msaitoh 	rxs->rxs_mbuf = m;
   4844  1.281   msaitoh 
   4845  1.281   msaitoh 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
   4846  1.281   msaitoh 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
   4847  1.388   msaitoh 	    BUS_DMA_READ | BUS_DMA_NOWAIT);
   4848  1.281   msaitoh 	if (error) {
   4849  1.281   msaitoh 		/* XXX XXX XXX */
   4850  1.281   msaitoh 		aprint_error_dev(sc->sc_dev,
   4851  1.573   msaitoh 		    "unable to load rx DMA map %d, error = %d\n", idx, error);
   4852  1.281   msaitoh 		panic("wm_add_rxbuf");
   4853  1.232    bouyer 	}
   4854  1.232    bouyer 
   4855  1.281   msaitoh 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   4856  1.281   msaitoh 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   4857  1.281   msaitoh 
   4858  1.281   msaitoh 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   4859  1.281   msaitoh 		if ((sc->sc_rctl & RCTL_EN) != 0)
   4860  1.362  knakahar 			wm_init_rxdesc(rxq, idx);
   4861  1.281   msaitoh 	} else
   4862  1.362  knakahar 		wm_init_rxdesc(rxq, idx);
   4863  1.281   msaitoh 
   4864  1.232    bouyer 	return 0;
   4865  1.232    bouyer }
   4866  1.232    bouyer 
   4867  1.232    bouyer /*
   4868  1.281   msaitoh  * wm_rxdrain:
   4869  1.232    bouyer  *
   4870  1.281   msaitoh  *	Drain the receive queue.
   4871  1.232    bouyer  */
   4872  1.232    bouyer static void
   4873  1.362  knakahar wm_rxdrain(struct wm_rxqueue *rxq)
   4874  1.281   msaitoh {
   4875  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   4876  1.281   msaitoh 	struct wm_rxsoft *rxs;
   4877  1.281   msaitoh 	int i;
   4878  1.281   msaitoh 
   4879  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   4880  1.281   msaitoh 
   4881  1.281   msaitoh 	for (i = 0; i < WM_NRXDESC; i++) {
   4882  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   4883  1.281   msaitoh 		if (rxs->rxs_mbuf != NULL) {
   4884  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   4885  1.281   msaitoh 			m_freem(rxs->rxs_mbuf);
   4886  1.281   msaitoh 			rxs->rxs_mbuf = NULL;
   4887  1.281   msaitoh 		}
   4888  1.281   msaitoh 	}
   4889  1.281   msaitoh }
   4890  1.281   msaitoh 
   4891  1.365  knakahar /*
   4892  1.367  knakahar  * Setup registers for RSS.
   4893  1.367  knakahar  *
   4894  1.367  knakahar  * XXX not yet VMDq support
   4895  1.367  knakahar  */
   4896  1.367  knakahar static void
   4897  1.367  knakahar wm_init_rss(struct wm_softc *sc)
   4898  1.367  knakahar {
   4899  1.372  knakahar 	uint32_t mrqc, reta_reg, rss_key[RSSRK_NUM_REGS];
   4900  1.367  knakahar 	int i;
   4901  1.367  knakahar 
   4902  1.564  knakahar 	CTASSERT(sizeof(rss_key) == RSS_KEYSIZE);
   4903  1.373  knakahar 
   4904  1.367  knakahar 	for (i = 0; i < RETA_NUM_ENTRIES; i++) {
   4905  1.367  knakahar 		int qid, reta_ent;
   4906  1.367  knakahar 
   4907  1.405  knakahar 		qid  = i % sc->sc_nqueues;
   4908  1.367  knakahar 		switch(sc->sc_type) {
   4909  1.367  knakahar 		case WM_T_82574:
   4910  1.367  knakahar 			reta_ent = __SHIFTIN(qid,
   4911  1.367  knakahar 			    RETA_ENT_QINDEX_MASK_82574);
   4912  1.367  knakahar 			break;
   4913  1.367  knakahar 		case WM_T_82575:
   4914  1.367  knakahar 			reta_ent = __SHIFTIN(qid,
   4915  1.367  knakahar 			    RETA_ENT_QINDEX1_MASK_82575);
   4916  1.367  knakahar 			break;
   4917  1.367  knakahar 		default:
   4918  1.367  knakahar 			reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK);
   4919  1.367  knakahar 			break;
   4920  1.367  knakahar 		}
   4921  1.367  knakahar 
   4922  1.367  knakahar 		reta_reg = CSR_READ(sc, WMREG_RETA_Q(i));
   4923  1.367  knakahar 		reta_reg &= ~RETA_ENTRY_MASK_Q(i);
   4924  1.367  knakahar 		reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i));
   4925  1.367  knakahar 		CSR_WRITE(sc, WMREG_RETA_Q(i), reta_reg);
   4926  1.367  knakahar 	}
   4927  1.367  knakahar 
   4928  1.564  knakahar 	rss_getkey((uint8_t *)rss_key);
   4929  1.367  knakahar 	for (i = 0; i < RSSRK_NUM_REGS; i++)
   4930  1.372  knakahar 		CSR_WRITE(sc, WMREG_RSSRK(i), rss_key[i]);
   4931  1.367  knakahar 
   4932  1.367  knakahar 	if (sc->sc_type == WM_T_82574)
   4933  1.367  knakahar 		mrqc = MRQC_ENABLE_RSS_MQ_82574;
   4934  1.367  knakahar 	else
   4935  1.367  knakahar 		mrqc = MRQC_ENABLE_RSS_MQ;
   4936  1.367  knakahar 
   4937  1.462   msaitoh 	/*
   4938  1.462   msaitoh 	 * MRQC_RSS_FIELD_IPV6_EX is not set because of an errata.
   4939  1.462   msaitoh 	 * See IPV6EXDIS bit in wm_initialize_hardware_bits().
   4940  1.367  knakahar 	 */
   4941  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV4 | MRQC_RSS_FIELD_IPV4_TCP);
   4942  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV6 | MRQC_RSS_FIELD_IPV6_TCP);
   4943  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV4_UDP | MRQC_RSS_FIELD_IPV6_UDP);
   4944  1.367  knakahar 	mrqc |= (MRQC_RSS_FIELD_IPV6_UDP_EX | MRQC_RSS_FIELD_IPV6_TCP_EX);
   4945  1.367  knakahar 
   4946  1.367  knakahar 	CSR_WRITE(sc, WMREG_MRQC, mrqc);
   4947  1.367  knakahar }
   4948  1.367  knakahar 
   4949  1.367  knakahar /*
   4950  1.365  knakahar  * Adjust TX and RX queue numbers which the system actulally uses.
   4951  1.365  knakahar  *
   4952  1.365  knakahar  * The numbers are affected by below parameters.
   4953  1.365  knakahar  *     - The nubmer of hardware queues
   4954  1.365  knakahar  *     - The number of MSI-X vectors (= "nvectors" argument)
   4955  1.365  knakahar  *     - ncpu
   4956  1.365  knakahar  */
   4957  1.365  knakahar static void
   4958  1.365  knakahar wm_adjust_qnum(struct wm_softc *sc, int nvectors)
   4959  1.365  knakahar {
   4960  1.405  knakahar 	int hw_ntxqueues, hw_nrxqueues, hw_nqueues;
   4961  1.365  knakahar 
   4962  1.405  knakahar 	if (nvectors < 2) {
   4963  1.405  knakahar 		sc->sc_nqueues = 1;
   4964  1.365  knakahar 		return;
   4965  1.365  knakahar 	}
   4966  1.365  knakahar 
   4967  1.365  knakahar 	switch(sc->sc_type) {
   4968  1.365  knakahar 	case WM_T_82572:
   4969  1.365  knakahar 		hw_ntxqueues = 2;
   4970  1.365  knakahar 		hw_nrxqueues = 2;
   4971  1.365  knakahar 		break;
   4972  1.365  knakahar 	case WM_T_82574:
   4973  1.365  knakahar 		hw_ntxqueues = 2;
   4974  1.365  knakahar 		hw_nrxqueues = 2;
   4975  1.365  knakahar 		break;
   4976  1.365  knakahar 	case WM_T_82575:
   4977  1.365  knakahar 		hw_ntxqueues = 4;
   4978  1.365  knakahar 		hw_nrxqueues = 4;
   4979  1.365  knakahar 		break;
   4980  1.365  knakahar 	case WM_T_82576:
   4981  1.365  knakahar 		hw_ntxqueues = 16;
   4982  1.365  knakahar 		hw_nrxqueues = 16;
   4983  1.365  knakahar 		break;
   4984  1.365  knakahar 	case WM_T_82580:
   4985  1.365  knakahar 	case WM_T_I350:
   4986  1.365  knakahar 	case WM_T_I354:
   4987  1.365  knakahar 		hw_ntxqueues = 8;
   4988  1.365  knakahar 		hw_nrxqueues = 8;
   4989  1.365  knakahar 		break;
   4990  1.365  knakahar 	case WM_T_I210:
   4991  1.365  knakahar 		hw_ntxqueues = 4;
   4992  1.365  knakahar 		hw_nrxqueues = 4;
   4993  1.365  knakahar 		break;
   4994  1.365  knakahar 	case WM_T_I211:
   4995  1.365  knakahar 		hw_ntxqueues = 2;
   4996  1.365  knakahar 		hw_nrxqueues = 2;
   4997  1.365  knakahar 		break;
   4998  1.365  knakahar 		/*
   4999  1.365  knakahar 		 * As below ethernet controllers does not support MSI-X,
   5000  1.365  knakahar 		 * this driver let them not use multiqueue.
   5001  1.365  knakahar 		 *     - WM_T_80003
   5002  1.365  knakahar 		 *     - WM_T_ICH8
   5003  1.365  knakahar 		 *     - WM_T_ICH9
   5004  1.365  knakahar 		 *     - WM_T_ICH10
   5005  1.365  knakahar 		 *     - WM_T_PCH
   5006  1.365  knakahar 		 *     - WM_T_PCH2
   5007  1.365  knakahar 		 *     - WM_T_PCH_LPT
   5008  1.365  knakahar 		 */
   5009  1.365  knakahar 	default:
   5010  1.365  knakahar 		hw_ntxqueues = 1;
   5011  1.365  knakahar 		hw_nrxqueues = 1;
   5012  1.365  knakahar 		break;
   5013  1.365  knakahar 	}
   5014  1.365  knakahar 
   5015  1.405  knakahar 	hw_nqueues = min(hw_ntxqueues, hw_nrxqueues);
   5016  1.405  knakahar 
   5017  1.365  knakahar 	/*
   5018  1.405  knakahar 	 * As queues more than MSI-X vectors cannot improve scaling, we limit
   5019  1.365  knakahar 	 * the number of queues used actually.
   5020  1.405  knakahar 	 */
   5021  1.573   msaitoh 	if (nvectors < hw_nqueues + 1)
   5022  1.405  knakahar 		sc->sc_nqueues = nvectors - 1;
   5023  1.573   msaitoh 	else
   5024  1.405  knakahar 		sc->sc_nqueues = hw_nqueues;
   5025  1.365  knakahar 
   5026  1.365  knakahar 	/*
   5027  1.365  knakahar 	 * As queues more then cpus cannot improve scaling, we limit
   5028  1.365  knakahar 	 * the number of queues used actually.
   5029  1.365  knakahar 	 */
   5030  1.405  knakahar 	if (ncpu < sc->sc_nqueues)
   5031  1.405  knakahar 		sc->sc_nqueues = ncpu;
   5032  1.365  knakahar }
   5033  1.365  knakahar 
   5034  1.502  knakahar static inline bool
   5035  1.502  knakahar wm_is_using_msix(struct wm_softc *sc)
   5036  1.502  knakahar {
   5037  1.502  knakahar 
   5038  1.502  knakahar 	return (sc->sc_nintrs > 1);
   5039  1.502  knakahar }
   5040  1.502  knakahar 
   5041  1.502  knakahar static inline bool
   5042  1.502  knakahar wm_is_using_multiqueue(struct wm_softc *sc)
   5043  1.502  knakahar {
   5044  1.502  knakahar 
   5045  1.502  knakahar 	return (sc->sc_nqueues > 1);
   5046  1.502  knakahar }
   5047  1.502  knakahar 
   5048  1.485  christos static int
   5049  1.485  christos wm_softint_establish(struct wm_softc *sc, int qidx, int intr_idx)
   5050  1.485  christos {
   5051  1.485  christos 	struct wm_queue *wmq = &sc->sc_queue[qidx];
   5052  1.485  christos 	wmq->wmq_id = qidx;
   5053  1.485  christos 	wmq->wmq_intr_idx = intr_idx;
   5054  1.485  christos 	wmq->wmq_si = softint_establish(SOFTINT_NET
   5055  1.485  christos #ifdef WM_MPSAFE
   5056  1.485  christos 	    | SOFTINT_MPSAFE
   5057  1.485  christos #endif
   5058  1.485  christos 	    , wm_handle_queue, wmq);
   5059  1.485  christos 	if (wmq->wmq_si != NULL)
   5060  1.485  christos 		return 0;
   5061  1.485  christos 
   5062  1.485  christos 	aprint_error_dev(sc->sc_dev, "unable to establish queue[%d] handler\n",
   5063  1.485  christos 	    wmq->wmq_id);
   5064  1.485  christos 
   5065  1.485  christos 	pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[wmq->wmq_intr_idx]);
   5066  1.485  christos 	sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
   5067  1.485  christos 	return ENOMEM;
   5068  1.485  christos }
   5069  1.485  christos 
   5070  1.365  knakahar /*
   5071  1.360  knakahar  * Both single interrupt MSI and INTx can use this function.
   5072  1.360  knakahar  */
   5073  1.360  knakahar static int
   5074  1.360  knakahar wm_setup_legacy(struct wm_softc *sc)
   5075  1.360  knakahar {
   5076  1.360  knakahar 	pci_chipset_tag_t pc = sc->sc_pc;
   5077  1.360  knakahar 	const char *intrstr = NULL;
   5078  1.360  knakahar 	char intrbuf[PCI_INTRSTR_LEN];
   5079  1.375   msaitoh 	int error;
   5080  1.360  knakahar 
   5081  1.375   msaitoh 	error = wm_alloc_txrx_queues(sc);
   5082  1.375   msaitoh 	if (error) {
   5083  1.375   msaitoh 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
   5084  1.375   msaitoh 		    error);
   5085  1.375   msaitoh 		return ENOMEM;
   5086  1.375   msaitoh 	}
   5087  1.360  knakahar 	intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf,
   5088  1.360  knakahar 	    sizeof(intrbuf));
   5089  1.360  knakahar #ifdef WM_MPSAFE
   5090  1.360  knakahar 	pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true);
   5091  1.360  knakahar #endif
   5092  1.360  knakahar 	sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0],
   5093  1.360  knakahar 	    IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev));
   5094  1.360  knakahar 	if (sc->sc_ihs[0] == NULL) {
   5095  1.360  knakahar 		aprint_error_dev(sc->sc_dev,"unable to establish %s\n",
   5096  1.416  knakahar 		    (pci_intr_type(pc, sc->sc_intrs[0])
   5097  1.360  knakahar 			== PCI_INTR_TYPE_MSI) ? "MSI" : "INTx");
   5098  1.360  knakahar 		return ENOMEM;
   5099  1.360  knakahar 	}
   5100  1.360  knakahar 
   5101  1.360  knakahar 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
   5102  1.360  knakahar 	sc->sc_nintrs = 1;
   5103  1.485  christos 
   5104  1.485  christos 	return wm_softint_establish(sc, 0, 0);
   5105  1.360  knakahar }
   5106  1.360  knakahar 
   5107  1.360  knakahar static int
   5108  1.360  knakahar wm_setup_msix(struct wm_softc *sc)
   5109  1.360  knakahar {
   5110  1.360  knakahar 	void *vih;
   5111  1.360  knakahar 	kcpuset_t *affinity;
   5112  1.405  knakahar 	int qidx, error, intr_idx, txrx_established;
   5113  1.360  knakahar 	pci_chipset_tag_t pc = sc->sc_pc;
   5114  1.360  knakahar 	const char *intrstr = NULL;
   5115  1.360  knakahar 	char intrbuf[PCI_INTRSTR_LEN];
   5116  1.360  knakahar 	char intr_xname[INTRDEVNAMEBUF];
   5117  1.404  knakahar 
   5118  1.405  knakahar 	if (sc->sc_nqueues < ncpu) {
   5119  1.404  knakahar 		/*
   5120  1.404  knakahar 		 * To avoid other devices' interrupts, the affinity of Tx/Rx
   5121  1.404  knakahar 		 * interrupts start from CPU#1.
   5122  1.404  knakahar 		 */
   5123  1.404  knakahar 		sc->sc_affinity_offset = 1;
   5124  1.404  knakahar 	} else {
   5125  1.404  knakahar 		/*
   5126  1.404  knakahar 		 * In this case, this device use all CPUs. So, we unify
   5127  1.404  knakahar 		 * affinitied cpu_index to msix vector number for readability.
   5128  1.404  knakahar 		 */
   5129  1.404  knakahar 		sc->sc_affinity_offset = 0;
   5130  1.404  knakahar 	}
   5131  1.360  knakahar 
   5132  1.375   msaitoh 	error = wm_alloc_txrx_queues(sc);
   5133  1.375   msaitoh 	if (error) {
   5134  1.375   msaitoh 		aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n",
   5135  1.375   msaitoh 		    error);
   5136  1.375   msaitoh 		return ENOMEM;
   5137  1.375   msaitoh 	}
   5138  1.375   msaitoh 
   5139  1.364  knakahar 	kcpuset_create(&affinity, false);
   5140  1.364  knakahar 	intr_idx = 0;
   5141  1.363  knakahar 
   5142  1.364  knakahar 	/*
   5143  1.405  knakahar 	 * TX and RX
   5144  1.364  knakahar 	 */
   5145  1.405  knakahar 	txrx_established = 0;
   5146  1.405  knakahar 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5147  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   5148  1.404  knakahar 		int affinity_to = (sc->sc_affinity_offset + intr_idx) % ncpu;
   5149  1.364  knakahar 
   5150  1.364  knakahar 		intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
   5151  1.364  knakahar 		    sizeof(intrbuf));
   5152  1.364  knakahar #ifdef WM_MPSAFE
   5153  1.364  knakahar 		pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
   5154  1.364  knakahar 		    PCI_INTR_MPSAFE, true);
   5155  1.364  knakahar #endif
   5156  1.364  knakahar 		memset(intr_xname, 0, sizeof(intr_xname));
   5157  1.405  knakahar 		snprintf(intr_xname, sizeof(intr_xname), "%sTXRX%d",
   5158  1.364  knakahar 		    device_xname(sc->sc_dev), qidx);
   5159  1.364  knakahar 		vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
   5160  1.405  knakahar 		    IPL_NET, wm_txrxintr_msix, wmq, intr_xname);
   5161  1.364  knakahar 		if (vih == NULL) {
   5162  1.364  knakahar 			aprint_error_dev(sc->sc_dev,
   5163  1.405  knakahar 			    "unable to establish MSI-X(for TX and RX)%s%s\n",
   5164  1.364  knakahar 			    intrstr ? " at " : "",
   5165  1.364  knakahar 			    intrstr ? intrstr : "");
   5166  1.364  knakahar 
   5167  1.405  knakahar 			goto fail;
   5168  1.360  knakahar 		}
   5169  1.360  knakahar 		kcpuset_zero(affinity);
   5170  1.360  knakahar 		/* Round-robin affinity */
   5171  1.383  knakahar 		kcpuset_set(affinity, affinity_to);
   5172  1.360  knakahar 		error = interrupt_distribute(vih, affinity, NULL);
   5173  1.360  knakahar 		if (error == 0) {
   5174  1.360  knakahar 			aprint_normal_dev(sc->sc_dev,
   5175  1.405  knakahar 			    "for TX and RX interrupting at %s affinity to %u\n",
   5176  1.383  knakahar 			    intrstr, affinity_to);
   5177  1.360  knakahar 		} else {
   5178  1.360  knakahar 			aprint_normal_dev(sc->sc_dev,
   5179  1.405  knakahar 			    "for TX and RX interrupting at %s\n", intrstr);
   5180  1.360  knakahar 		}
   5181  1.364  knakahar 		sc->sc_ihs[intr_idx] = vih;
   5182  1.485  christos 		if (wm_softint_establish(sc, qidx, intr_idx) != 0)
   5183  1.484  knakahar 			goto fail;
   5184  1.405  knakahar 		txrx_established++;
   5185  1.364  knakahar 		intr_idx++;
   5186  1.364  knakahar 	}
   5187  1.364  knakahar 
   5188  1.364  knakahar 	/*
   5189  1.364  knakahar 	 * LINK
   5190  1.364  knakahar 	 */
   5191  1.364  knakahar 	intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
   5192  1.364  knakahar 	    sizeof(intrbuf));
   5193  1.364  knakahar #ifdef WM_MPSAFE
   5194  1.388   msaitoh 	pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], PCI_INTR_MPSAFE, true);
   5195  1.364  knakahar #endif
   5196  1.364  knakahar 	memset(intr_xname, 0, sizeof(intr_xname));
   5197  1.364  knakahar 	snprintf(intr_xname, sizeof(intr_xname), "%sLINK",
   5198  1.364  knakahar 	    device_xname(sc->sc_dev));
   5199  1.364  knakahar 	vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx],
   5200  1.364  knakahar 		    IPL_NET, wm_linkintr_msix, sc, intr_xname);
   5201  1.364  knakahar 	if (vih == NULL) {
   5202  1.364  knakahar 		aprint_error_dev(sc->sc_dev,
   5203  1.364  knakahar 		    "unable to establish MSI-X(for LINK)%s%s\n",
   5204  1.364  knakahar 		    intrstr ? " at " : "",
   5205  1.364  knakahar 		    intrstr ? intrstr : "");
   5206  1.364  knakahar 
   5207  1.405  knakahar 		goto fail;
   5208  1.360  knakahar 	}
   5209  1.364  knakahar 	/* keep default affinity to LINK interrupt */
   5210  1.364  knakahar 	aprint_normal_dev(sc->sc_dev,
   5211  1.364  knakahar 	    "for LINK interrupting at %s\n", intrstr);
   5212  1.364  knakahar 	sc->sc_ihs[intr_idx] = vih;
   5213  1.364  knakahar 	sc->sc_link_intr_idx = intr_idx;
   5214  1.360  knakahar 
   5215  1.405  knakahar 	sc->sc_nintrs = sc->sc_nqueues + 1;
   5216  1.360  knakahar 	kcpuset_destroy(affinity);
   5217  1.360  knakahar 	return 0;
   5218  1.364  knakahar 
   5219  1.405  knakahar  fail:
   5220  1.405  knakahar 	for (qidx = 0; qidx < txrx_established; qidx++) {
   5221  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   5222  1.405  knakahar 		pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[wmq->wmq_intr_idx]);
   5223  1.405  knakahar 		sc->sc_ihs[wmq->wmq_intr_idx] = NULL;
   5224  1.364  knakahar 	}
   5225  1.364  knakahar 
   5226  1.364  knakahar 	kcpuset_destroy(affinity);
   5227  1.364  knakahar 	return ENOMEM;
   5228  1.360  knakahar }
   5229  1.360  knakahar 
   5230  1.429  knakahar static void
   5231  1.537  knakahar wm_unset_stopping_flags(struct wm_softc *sc)
   5232  1.429  knakahar {
   5233  1.429  knakahar 	int i;
   5234  1.429  knakahar 
   5235  1.436  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5236  1.436  knakahar 
   5237  1.476  knakahar 	/*
   5238  1.476  knakahar 	 * must unset stopping flags in ascending order.
   5239  1.476  knakahar 	 */
   5240  1.429  knakahar 	for(i = 0; i < sc->sc_nqueues; i++) {
   5241  1.429  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   5242  1.429  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   5243  1.429  knakahar 
   5244  1.429  knakahar 		mutex_enter(txq->txq_lock);
   5245  1.429  knakahar 		txq->txq_stopping = false;
   5246  1.429  knakahar 		mutex_exit(txq->txq_lock);
   5247  1.429  knakahar 
   5248  1.429  knakahar 		mutex_enter(rxq->rxq_lock);
   5249  1.429  knakahar 		rxq->rxq_stopping = false;
   5250  1.429  knakahar 		mutex_exit(rxq->rxq_lock);
   5251  1.429  knakahar 	}
   5252  1.429  knakahar 
   5253  1.429  knakahar 	sc->sc_core_stopping = false;
   5254  1.429  knakahar }
   5255  1.429  knakahar 
   5256  1.429  knakahar static void
   5257  1.537  knakahar wm_set_stopping_flags(struct wm_softc *sc)
   5258  1.429  knakahar {
   5259  1.429  knakahar 	int i;
   5260  1.429  knakahar 
   5261  1.436  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5262  1.436  knakahar 
   5263  1.429  knakahar 	sc->sc_core_stopping = true;
   5264  1.429  knakahar 
   5265  1.476  knakahar 	/*
   5266  1.476  knakahar 	 * must set stopping flags in ascending order.
   5267  1.476  knakahar 	 */
   5268  1.429  knakahar 	for(i = 0; i < sc->sc_nqueues; i++) {
   5269  1.429  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   5270  1.429  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   5271  1.429  knakahar 
   5272  1.429  knakahar 		mutex_enter(rxq->rxq_lock);
   5273  1.429  knakahar 		rxq->rxq_stopping = true;
   5274  1.429  knakahar 		mutex_exit(rxq->rxq_lock);
   5275  1.429  knakahar 
   5276  1.429  knakahar 		mutex_enter(txq->txq_lock);
   5277  1.429  knakahar 		txq->txq_stopping = true;
   5278  1.429  knakahar 		mutex_exit(txq->txq_lock);
   5279  1.429  knakahar 	}
   5280  1.429  knakahar }
   5281  1.429  knakahar 
   5282  1.281   msaitoh /*
   5283  1.491  knakahar  * write interrupt interval value to ITR or EITR
   5284  1.491  knakahar  */
   5285  1.491  knakahar static void
   5286  1.491  knakahar wm_itrs_writereg(struct wm_softc *sc, struct wm_queue *wmq)
   5287  1.491  knakahar {
   5288  1.491  knakahar 
   5289  1.495  knakahar 	if (!wmq->wmq_set_itr)
   5290  1.495  knakahar 		return;
   5291  1.495  knakahar 
   5292  1.491  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   5293  1.491  knakahar 		uint32_t eitr = __SHIFTIN(wmq->wmq_itr, EITR_ITR_INT_MASK);
   5294  1.491  knakahar 
   5295  1.491  knakahar 		/*
   5296  1.491  knakahar 		 * 82575 doesn't have CNT_INGR field.
   5297  1.491  knakahar 		 * So, overwrite counter field by software.
   5298  1.491  knakahar 		 */
   5299  1.491  knakahar 		if (sc->sc_type == WM_T_82575)
   5300  1.491  knakahar 			eitr |= __SHIFTIN(wmq->wmq_itr, EITR_COUNTER_MASK_82575);
   5301  1.491  knakahar 		else
   5302  1.491  knakahar 			eitr |= EITR_CNT_INGR;
   5303  1.491  knakahar 
   5304  1.491  knakahar 		CSR_WRITE(sc, WMREG_EITR(wmq->wmq_intr_idx), eitr);
   5305  1.502  knakahar 	} else if (sc->sc_type == WM_T_82574 && wm_is_using_msix(sc)) {
   5306  1.491  knakahar 		/*
   5307  1.491  knakahar 		 * 82574 has both ITR and EITR. SET EITR when we use
   5308  1.491  knakahar 		 * the multi queue function with MSI-X.
   5309  1.491  knakahar 		 */
   5310  1.491  knakahar 		CSR_WRITE(sc, WMREG_EITR_82574(wmq->wmq_intr_idx),
   5311  1.491  knakahar 			    wmq->wmq_itr & EITR_ITR_INT_MASK_82574);
   5312  1.491  knakahar 	} else {
   5313  1.491  knakahar 		KASSERT(wmq->wmq_id == 0);
   5314  1.491  knakahar 		CSR_WRITE(sc, WMREG_ITR, wmq->wmq_itr);
   5315  1.491  knakahar 	}
   5316  1.495  knakahar 
   5317  1.495  knakahar 	wmq->wmq_set_itr = false;
   5318  1.495  knakahar }
   5319  1.495  knakahar 
   5320  1.495  knakahar /*
   5321  1.495  knakahar  * TODO
   5322  1.495  knakahar  * Below dynamic calculation of itr is almost the same as linux igb,
   5323  1.495  knakahar  * however it does not fit to wm(4). So, we will have been disable AIM
   5324  1.495  knakahar  * until we will find appropriate calculation of itr.
   5325  1.495  knakahar  */
   5326  1.495  knakahar /*
   5327  1.495  knakahar  * calculate interrupt interval value to be going to write register in
   5328  1.495  knakahar  * wm_itrs_writereg(). This function does not write ITR/EITR register.
   5329  1.495  knakahar  */
   5330  1.495  knakahar static void
   5331  1.495  knakahar wm_itrs_calculate(struct wm_softc *sc, struct wm_queue *wmq)
   5332  1.495  knakahar {
   5333  1.495  knakahar #ifdef NOTYET
   5334  1.495  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   5335  1.495  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   5336  1.495  knakahar 	uint32_t avg_size = 0;
   5337  1.495  knakahar 	uint32_t new_itr;
   5338  1.495  knakahar 
   5339  1.495  knakahar 	if (rxq->rxq_packets)
   5340  1.495  knakahar 		avg_size =  rxq->rxq_bytes / rxq->rxq_packets;
   5341  1.495  knakahar 	if (txq->txq_packets)
   5342  1.495  knakahar 		avg_size = max(avg_size, txq->txq_bytes / txq->txq_packets);
   5343  1.495  knakahar 
   5344  1.495  knakahar 	if (avg_size == 0) {
   5345  1.495  knakahar 		new_itr = 450; /* restore default value */
   5346  1.495  knakahar 		goto out;
   5347  1.495  knakahar 	}
   5348  1.495  knakahar 
   5349  1.495  knakahar 	/* Add 24 bytes to size to account for CRC, preamble, and gap */
   5350  1.495  knakahar 	avg_size += 24;
   5351  1.495  knakahar 
   5352  1.495  knakahar 	/* Don't starve jumbo frames */
   5353  1.495  knakahar 	avg_size = min(avg_size, 3000);
   5354  1.495  knakahar 
   5355  1.495  knakahar 	/* Give a little boost to mid-size frames */
   5356  1.495  knakahar 	if ((avg_size > 300) && (avg_size < 1200))
   5357  1.495  knakahar 		new_itr = avg_size / 3;
   5358  1.495  knakahar 	else
   5359  1.495  knakahar 		new_itr = avg_size / 2;
   5360  1.495  knakahar 
   5361  1.495  knakahar out:
   5362  1.495  knakahar 	/*
   5363  1.495  knakahar 	 * The usage of 82574 and 82575 EITR is different from otther NEWQUEUE
   5364  1.495  knakahar 	 * controllers. See sc->sc_itr_init setting in wm_init_locked().
   5365  1.495  knakahar 	 */
   5366  1.495  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) == 0 || sc->sc_type != WM_T_82575)
   5367  1.495  knakahar 		new_itr *= 4;
   5368  1.495  knakahar 
   5369  1.495  knakahar 	if (new_itr != wmq->wmq_itr) {
   5370  1.495  knakahar 		wmq->wmq_itr = new_itr;
   5371  1.495  knakahar 		wmq->wmq_set_itr = true;
   5372  1.495  knakahar 	} else
   5373  1.495  knakahar 		wmq->wmq_set_itr = false;
   5374  1.495  knakahar 
   5375  1.495  knakahar 	rxq->rxq_packets = 0;
   5376  1.495  knakahar 	rxq->rxq_bytes = 0;
   5377  1.495  knakahar 	txq->txq_packets = 0;
   5378  1.495  knakahar 	txq->txq_bytes = 0;
   5379  1.495  knakahar #endif
   5380  1.491  knakahar }
   5381  1.491  knakahar 
   5382  1.491  knakahar /*
   5383  1.281   msaitoh  * wm_init:		[ifnet interface function]
   5384  1.281   msaitoh  *
   5385  1.281   msaitoh  *	Initialize the interface.
   5386  1.281   msaitoh  */
   5387  1.281   msaitoh static int
   5388  1.281   msaitoh wm_init(struct ifnet *ifp)
   5389  1.232    bouyer {
   5390  1.232    bouyer 	struct wm_softc *sc = ifp->if_softc;
   5391  1.281   msaitoh 	int ret;
   5392  1.272     ozaki 
   5393  1.357  knakahar 	WM_CORE_LOCK(sc);
   5394  1.281   msaitoh 	ret = wm_init_locked(ifp);
   5395  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   5396  1.281   msaitoh 
   5397  1.281   msaitoh 	return ret;
   5398  1.272     ozaki }
   5399  1.272     ozaki 
   5400  1.281   msaitoh static int
   5401  1.281   msaitoh wm_init_locked(struct ifnet *ifp)
   5402  1.272     ozaki {
   5403  1.272     ozaki 	struct wm_softc *sc = ifp->if_softc;
   5404  1.281   msaitoh 	int i, j, trynum, error = 0;
   5405  1.281   msaitoh 	uint32_t reg;
   5406  1.232    bouyer 
   5407  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   5408  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   5409  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5410  1.420   msaitoh 
   5411  1.232    bouyer 	/*
   5412  1.281   msaitoh 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
   5413  1.281   msaitoh 	 * There is a small but measurable benefit to avoiding the adjusment
   5414  1.281   msaitoh 	 * of the descriptor so that the headers are aligned, for normal mtu,
   5415  1.281   msaitoh 	 * on such platforms.  One possibility is that the DMA itself is
   5416  1.281   msaitoh 	 * slightly more efficient if the front of the entire packet (instead
   5417  1.281   msaitoh 	 * of the front of the headers) is aligned.
   5418  1.281   msaitoh 	 *
   5419  1.281   msaitoh 	 * Note we must always set align_tweak to 0 if we are using
   5420  1.281   msaitoh 	 * jumbo frames.
   5421  1.232    bouyer 	 */
   5422  1.281   msaitoh #ifdef __NO_STRICT_ALIGNMENT
   5423  1.281   msaitoh 	sc->sc_align_tweak = 0;
   5424  1.281   msaitoh #else
   5425  1.281   msaitoh 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
   5426  1.281   msaitoh 		sc->sc_align_tweak = 0;
   5427  1.281   msaitoh 	else
   5428  1.281   msaitoh 		sc->sc_align_tweak = 2;
   5429  1.281   msaitoh #endif /* __NO_STRICT_ALIGNMENT */
   5430  1.281   msaitoh 
   5431  1.281   msaitoh 	/* Cancel any pending I/O. */
   5432  1.281   msaitoh 	wm_stop_locked(ifp, 0);
   5433  1.281   msaitoh 
   5434  1.281   msaitoh 	/* update statistics before reset */
   5435  1.281   msaitoh 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
   5436  1.281   msaitoh 	ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
   5437  1.281   msaitoh 
   5438  1.443   msaitoh 	/* PCH_SPT hardware workaround */
   5439  1.443   msaitoh 	if (sc->sc_type == WM_T_PCH_SPT)
   5440  1.443   msaitoh 		wm_flush_desc_rings(sc);
   5441  1.443   msaitoh 
   5442  1.281   msaitoh 	/* Reset the chip to a known state. */
   5443  1.281   msaitoh 	wm_reset(sc);
   5444  1.281   msaitoh 
   5445  1.518   msaitoh 	/*
   5446  1.518   msaitoh 	 * AMT based hardware can now take control from firmware
   5447  1.518   msaitoh 	 * Do this after reset.
   5448  1.518   msaitoh 	 */
   5449  1.518   msaitoh 	if ((sc->sc_flags & WM_F_HAS_AMT) != 0)
   5450  1.518   msaitoh 		wm_get_hw_control(sc);
   5451  1.518   msaitoh 
   5452  1.570   msaitoh 	if ((sc->sc_type >= WM_T_PCH_SPT) &&
   5453  1.517   msaitoh 	    pci_intr_type(sc->sc_pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_INTX)
   5454  1.517   msaitoh 		wm_legacy_irq_quirk_spt(sc);
   5455  1.232    bouyer 
   5456  1.312   msaitoh 	/* Init hardware bits */
   5457  1.312   msaitoh 	wm_initialize_hardware_bits(sc);
   5458  1.312   msaitoh 
   5459  1.281   msaitoh 	/* Reset the PHY. */
   5460  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   5461  1.281   msaitoh 		wm_gmii_reset(sc);
   5462  1.232    bouyer 
   5463  1.319   msaitoh 	/* Calculate (E)ITR value */
   5464  1.489  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0 && sc->sc_type != WM_T_82575) {
   5465  1.489  knakahar 		/*
   5466  1.489  knakahar 		 * For NEWQUEUE's EITR (except for 82575).
   5467  1.489  knakahar 		 * 82575's EITR should be set same throttling value as other
   5468  1.489  knakahar 		 * old controllers' ITR because the interrupt/sec calculation
   5469  1.489  knakahar 		 * is the same, that is, 1,000,000,000 / (N * 256).
   5470  1.489  knakahar 		 *
   5471  1.489  knakahar 		 * 82574's EITR should be set same throttling value as ITR.
   5472  1.489  knakahar 		 *
   5473  1.489  knakahar 		 * For N interrupts/sec, set this value to:
   5474  1.489  knakahar 		 * 1,000,000 / N in contrast to ITR throttoling value.
   5475  1.489  knakahar 		 */
   5476  1.490  knakahar 		sc->sc_itr_init = 450;
   5477  1.319   msaitoh 	} else if (sc->sc_type >= WM_T_82543) {
   5478  1.319   msaitoh 		/*
   5479  1.319   msaitoh 		 * Set up the interrupt throttling register (units of 256ns)
   5480  1.319   msaitoh 		 * Note that a footnote in Intel's documentation says this
   5481  1.319   msaitoh 		 * ticker runs at 1/4 the rate when the chip is in 100Mbit
   5482  1.319   msaitoh 		 * or 10Mbit mode.  Empirically, it appears to be the case
   5483  1.319   msaitoh 		 * that that is also true for the 1024ns units of the other
   5484  1.319   msaitoh 		 * interrupt-related timer registers -- so, really, we ought
   5485  1.319   msaitoh 		 * to divide this value by 4 when the link speed is low.
   5486  1.319   msaitoh 		 *
   5487  1.319   msaitoh 		 * XXX implement this division at link speed change!
   5488  1.319   msaitoh 		 */
   5489  1.319   msaitoh 
   5490  1.319   msaitoh 		/*
   5491  1.319   msaitoh 		 * For N interrupts/sec, set this value to:
   5492  1.489  knakahar 		 * 1,000,000,000 / (N * 256).  Note that we set the
   5493  1.319   msaitoh 		 * absolute and packet timer values to this value
   5494  1.319   msaitoh 		 * divided by 4 to get "simple timer" behavior.
   5495  1.319   msaitoh 		 */
   5496  1.490  knakahar 		sc->sc_itr_init = 1500;		/* 2604 ints/sec */
   5497  1.319   msaitoh 	}
   5498  1.319   msaitoh 
   5499  1.355  knakahar 	error = wm_init_txrx_queues(sc);
   5500  1.355  knakahar 	if (error)
   5501  1.355  knakahar 		goto out;
   5502  1.232    bouyer 
   5503  1.281   msaitoh 	/*
   5504  1.281   msaitoh 	 * Clear out the VLAN table -- we don't use it (yet).
   5505  1.281   msaitoh 	 */
   5506  1.281   msaitoh 	CSR_WRITE(sc, WMREG_VET, 0);
   5507  1.281   msaitoh 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354))
   5508  1.281   msaitoh 		trynum = 10; /* Due to hw errata */
   5509  1.281   msaitoh 	else
   5510  1.281   msaitoh 		trynum = 1;
   5511  1.281   msaitoh 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
   5512  1.281   msaitoh 		for (j = 0; j < trynum; j++)
   5513  1.281   msaitoh 			CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
   5514  1.232    bouyer 
   5515  1.281   msaitoh 	/*
   5516  1.281   msaitoh 	 * Set up flow-control parameters.
   5517  1.281   msaitoh 	 *
   5518  1.281   msaitoh 	 * XXX Values could probably stand some tuning.
   5519  1.281   msaitoh 	 */
   5520  1.281   msaitoh 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
   5521  1.281   msaitoh 	    && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
   5522  1.392   msaitoh 	    && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT)
   5523  1.570   msaitoh 	    && (sc->sc_type != WM_T_PCH_SPT) && (sc->sc_type != WM_T_PCH_CNP)){
   5524  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
   5525  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
   5526  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
   5527  1.281   msaitoh 	}
   5528  1.232    bouyer 
   5529  1.281   msaitoh 	sc->sc_fcrtl = FCRTL_DFLT;
   5530  1.281   msaitoh 	if (sc->sc_type < WM_T_82543) {
   5531  1.281   msaitoh 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
   5532  1.281   msaitoh 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
   5533  1.281   msaitoh 	} else {
   5534  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
   5535  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
   5536  1.281   msaitoh 	}
   5537  1.232    bouyer 
   5538  1.281   msaitoh 	if (sc->sc_type == WM_T_80003)
   5539  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
   5540  1.281   msaitoh 	else
   5541  1.281   msaitoh 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
   5542  1.232    bouyer 
   5543  1.281   msaitoh 	/* Writes the control register. */
   5544  1.281   msaitoh 	wm_set_vlan(sc);
   5545  1.232    bouyer 
   5546  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII) {
   5547  1.531   msaitoh 		uint16_t kmreg;
   5548  1.232    bouyer 
   5549  1.281   msaitoh 		switch (sc->sc_type) {
   5550  1.281   msaitoh 		case WM_T_80003:
   5551  1.281   msaitoh 		case WM_T_ICH8:
   5552  1.281   msaitoh 		case WM_T_ICH9:
   5553  1.281   msaitoh 		case WM_T_ICH10:
   5554  1.281   msaitoh 		case WM_T_PCH:
   5555  1.281   msaitoh 		case WM_T_PCH2:
   5556  1.281   msaitoh 		case WM_T_PCH_LPT:
   5557  1.392   msaitoh 		case WM_T_PCH_SPT:
   5558  1.570   msaitoh 		case WM_T_PCH_CNP:
   5559  1.281   msaitoh 			/*
   5560  1.281   msaitoh 			 * Set the mac to wait the maximum time between each
   5561  1.281   msaitoh 			 * iteration and increase the max iterations when
   5562  1.281   msaitoh 			 * polling the phy; this fixes erroneous timeouts at
   5563  1.281   msaitoh 			 * 10Mbps.
   5564  1.281   msaitoh 			 */
   5565  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
   5566  1.281   msaitoh 			    0xFFFF);
   5567  1.531   msaitoh 			wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM,
   5568  1.531   msaitoh 			    &kmreg);
   5569  1.531   msaitoh 			kmreg |= 0x3F;
   5570  1.531   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_PARAM,
   5571  1.531   msaitoh 			    kmreg);
   5572  1.281   msaitoh 			break;
   5573  1.281   msaitoh 		default:
   5574  1.281   msaitoh 			break;
   5575  1.232    bouyer 		}
   5576  1.232    bouyer 
   5577  1.281   msaitoh 		if (sc->sc_type == WM_T_80003) {
   5578  1.531   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5579  1.531   msaitoh 			reg &= ~CTRL_EXT_LINK_MODE_MASK;
   5580  1.531   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   5581  1.232    bouyer 
   5582  1.281   msaitoh 			/* Bypass RX and TX FIFO's */
   5583  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
   5584  1.281   msaitoh 			    KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
   5585  1.281   msaitoh 			    | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
   5586  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
   5587  1.281   msaitoh 			    KUMCTRLSTA_INB_CTRL_DIS_PADDING |
   5588  1.281   msaitoh 			    KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
   5589  1.232    bouyer 		}
   5590  1.281   msaitoh 	}
   5591  1.281   msaitoh #if 0
   5592  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   5593  1.281   msaitoh #endif
   5594  1.232    bouyer 
   5595  1.281   msaitoh 	/* Set up checksum offload parameters. */
   5596  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_RXCSUM);
   5597  1.281   msaitoh 	reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
   5598  1.281   msaitoh 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
   5599  1.281   msaitoh 		reg |= RXCSUM_IPOFL;
   5600  1.281   msaitoh 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
   5601  1.281   msaitoh 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
   5602  1.281   msaitoh 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
   5603  1.281   msaitoh 		reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
   5604  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
   5605  1.232    bouyer 
   5606  1.502  knakahar 	/* Set registers about MSI-X */
   5607  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   5608  1.335   msaitoh 		uint32_t ivar;
   5609  1.405  knakahar 		struct wm_queue *wmq;
   5610  1.405  knakahar 		int qid, qintr_idx;
   5611  1.335   msaitoh 
   5612  1.335   msaitoh 		if (sc->sc_type == WM_T_82575) {
   5613  1.335   msaitoh 			/* Interrupt control */
   5614  1.335   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5615  1.335   msaitoh 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;
   5616  1.335   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   5617  1.335   msaitoh 
   5618  1.405  knakahar 			/* TX and RX */
   5619  1.405  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5620  1.405  knakahar 				wmq = &sc->sc_queue[i];
   5621  1.405  knakahar 				CSR_WRITE(sc, WMREG_MSIXBM(wmq->wmq_intr_idx),
   5622  1.405  knakahar 				    EITR_TX_QUEUE(wmq->wmq_id)
   5623  1.405  knakahar 				    | EITR_RX_QUEUE(wmq->wmq_id));
   5624  1.364  knakahar 			}
   5625  1.335   msaitoh 			/* Link status */
   5626  1.364  knakahar 			CSR_WRITE(sc, WMREG_MSIXBM(sc->sc_link_intr_idx),
   5627  1.335   msaitoh 			    EITR_OTHER);
   5628  1.335   msaitoh 		} else if (sc->sc_type == WM_T_82574) {
   5629  1.335   msaitoh 			/* Interrupt control */
   5630  1.335   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   5631  1.335   msaitoh 			reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;
   5632  1.335   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   5633  1.335   msaitoh 
   5634  1.487  knakahar 			/*
   5635  1.487  knakahar 			 * workaround issue with spurious interrupts
   5636  1.487  knakahar 			 * in MSI-X mode.
   5637  1.487  knakahar 			 * At wm_initialize_hardware_bits(), sc_nintrs has not
   5638  1.487  knakahar 			 * initialized yet. So re-initialize WMREG_RFCTL here.
   5639  1.487  knakahar 			 */
   5640  1.487  knakahar 			reg = CSR_READ(sc, WMREG_RFCTL);
   5641  1.487  knakahar 			reg |= WMREG_RFCTL_ACKDIS;
   5642  1.487  knakahar 			CSR_WRITE(sc, WMREG_RFCTL, reg);
   5643  1.487  knakahar 
   5644  1.364  knakahar 			ivar = 0;
   5645  1.405  knakahar 			/* TX and RX */
   5646  1.405  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5647  1.405  knakahar 				wmq = &sc->sc_queue[i];
   5648  1.405  knakahar 				qid = wmq->wmq_id;
   5649  1.405  knakahar 				qintr_idx = wmq->wmq_intr_idx;
   5650  1.405  knakahar 
   5651  1.405  knakahar 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
   5652  1.405  knakahar 				    IVAR_TX_MASK_Q_82574(qid));
   5653  1.405  knakahar 				ivar |= __SHIFTIN((IVAR_VALID_82574|qintr_idx),
   5654  1.405  knakahar 				    IVAR_RX_MASK_Q_82574(qid));
   5655  1.364  knakahar 			}
   5656  1.364  knakahar 			/* Link status */
   5657  1.388   msaitoh 			ivar |= __SHIFTIN((IVAR_VALID_82574
   5658  1.388   msaitoh 				| sc->sc_link_intr_idx), IVAR_OTHER_MASK);
   5659  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
   5660  1.335   msaitoh 		} else {
   5661  1.335   msaitoh 			/* Interrupt control */
   5662  1.388   msaitoh 			CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | GPIE_MULTI_MSIX
   5663  1.388   msaitoh 			    | GPIE_EIAME | GPIE_PBA);
   5664  1.335   msaitoh 
   5665  1.335   msaitoh 			switch (sc->sc_type) {
   5666  1.335   msaitoh 			case WM_T_82580:
   5667  1.335   msaitoh 			case WM_T_I350:
   5668  1.335   msaitoh 			case WM_T_I354:
   5669  1.335   msaitoh 			case WM_T_I210:
   5670  1.335   msaitoh 			case WM_T_I211:
   5671  1.405  knakahar 				/* TX and RX */
   5672  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5673  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5674  1.405  knakahar 					qid = wmq->wmq_id;
   5675  1.405  knakahar 					qintr_idx = wmq->wmq_intr_idx;
   5676  1.405  knakahar 
   5677  1.364  knakahar 					ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
   5678  1.364  knakahar 					ivar &= ~IVAR_TX_MASK_Q(qid);
   5679  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5680  1.388   msaitoh 						| IVAR_VALID),
   5681  1.388   msaitoh 					    IVAR_TX_MASK_Q(qid));
   5682  1.364  knakahar 					ivar &= ~IVAR_RX_MASK_Q(qid);
   5683  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5684  1.388   msaitoh 						| IVAR_VALID),
   5685  1.388   msaitoh 					    IVAR_RX_MASK_Q(qid));
   5686  1.364  knakahar 					CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
   5687  1.364  knakahar 				}
   5688  1.335   msaitoh 				break;
   5689  1.335   msaitoh 			case WM_T_82576:
   5690  1.405  knakahar 				/* TX and RX */
   5691  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5692  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5693  1.405  knakahar 					qid = wmq->wmq_id;
   5694  1.405  knakahar 					qintr_idx = wmq->wmq_intr_idx;
   5695  1.405  knakahar 
   5696  1.388   msaitoh 					ivar = CSR_READ(sc,
   5697  1.388   msaitoh 					    WMREG_IVAR_Q_82576(qid));
   5698  1.364  knakahar 					ivar &= ~IVAR_TX_MASK_Q_82576(qid);
   5699  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5700  1.388   msaitoh 						| IVAR_VALID),
   5701  1.388   msaitoh 					    IVAR_TX_MASK_Q_82576(qid));
   5702  1.364  knakahar 					ivar &= ~IVAR_RX_MASK_Q_82576(qid);
   5703  1.405  knakahar 					ivar |= __SHIFTIN((qintr_idx
   5704  1.388   msaitoh 						| IVAR_VALID),
   5705  1.388   msaitoh 					    IVAR_RX_MASK_Q_82576(qid));
   5706  1.388   msaitoh 					CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid),
   5707  1.388   msaitoh 					    ivar);
   5708  1.364  knakahar 				}
   5709  1.335   msaitoh 				break;
   5710  1.335   msaitoh 			default:
   5711  1.335   msaitoh 				break;
   5712  1.335   msaitoh 			}
   5713  1.335   msaitoh 
   5714  1.335   msaitoh 			/* Link status */
   5715  1.364  knakahar 			ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID),
   5716  1.335   msaitoh 			    IVAR_MISC_OTHER);
   5717  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IVAR_MISC, ivar);
   5718  1.335   msaitoh 		}
   5719  1.365  knakahar 
   5720  1.502  knakahar 		if (wm_is_using_multiqueue(sc)) {
   5721  1.365  knakahar 			wm_init_rss(sc);
   5722  1.365  knakahar 
   5723  1.365  knakahar 			/*
   5724  1.365  knakahar 			** NOTE: Receive Full-Packet Checksum Offload
   5725  1.365  knakahar 			** is mutually exclusive with Multiqueue. However
   5726  1.365  knakahar 			** this is not the same as TCP/IP checksums which
   5727  1.365  knakahar 			** still work.
   5728  1.365  knakahar 			*/
   5729  1.365  knakahar 			reg = CSR_READ(sc, WMREG_RXCSUM);
   5730  1.365  knakahar 			reg |= RXCSUM_PCSD;
   5731  1.365  knakahar 			CSR_WRITE(sc, WMREG_RXCSUM, reg);
   5732  1.365  knakahar 		}
   5733  1.335   msaitoh 	}
   5734  1.335   msaitoh 
   5735  1.281   msaitoh 	/* Set up the interrupt registers. */
   5736  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   5737  1.281   msaitoh 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
   5738  1.281   msaitoh 	    ICR_RXO | ICR_RXT0;
   5739  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   5740  1.335   msaitoh 		uint32_t mask;
   5741  1.405  knakahar 		struct wm_queue *wmq;
   5742  1.388   msaitoh 
   5743  1.335   msaitoh 		switch (sc->sc_type) {
   5744  1.335   msaitoh 		case WM_T_82574:
   5745  1.486  knakahar 			mask = 0;
   5746  1.486  knakahar 			for (i = 0; i < sc->sc_nqueues; i++) {
   5747  1.486  knakahar 				wmq = &sc->sc_queue[i];
   5748  1.486  knakahar 				mask |= ICR_TXQ(wmq->wmq_id);
   5749  1.486  knakahar 				mask |= ICR_RXQ(wmq->wmq_id);
   5750  1.486  knakahar 			}
   5751  1.486  knakahar 			mask |= ICR_OTHER;
   5752  1.486  knakahar 			CSR_WRITE(sc, WMREG_EIAC_82574, mask);
   5753  1.486  knakahar 			CSR_WRITE(sc, WMREG_IMS, mask | ICR_LSC);
   5754  1.335   msaitoh 			break;
   5755  1.335   msaitoh 		default:
   5756  1.364  knakahar 			if (sc->sc_type == WM_T_82575) {
   5757  1.364  knakahar 				mask = 0;
   5758  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5759  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5760  1.405  knakahar 					mask |= EITR_TX_QUEUE(wmq->wmq_id);
   5761  1.405  knakahar 					mask |= EITR_RX_QUEUE(wmq->wmq_id);
   5762  1.364  knakahar 				}
   5763  1.364  knakahar 				mask |= EITR_OTHER;
   5764  1.364  knakahar 			} else {
   5765  1.364  knakahar 				mask = 0;
   5766  1.405  knakahar 				for (i = 0; i < sc->sc_nqueues; i++) {
   5767  1.405  knakahar 					wmq = &sc->sc_queue[i];
   5768  1.405  knakahar 					mask |= 1 << wmq->wmq_intr_idx;
   5769  1.364  knakahar 				}
   5770  1.364  knakahar 				mask |= 1 << sc->sc_link_intr_idx;
   5771  1.364  knakahar 			}
   5772  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, mask);
   5773  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAM, mask);
   5774  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMS, mask);
   5775  1.335   msaitoh 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
   5776  1.335   msaitoh 			break;
   5777  1.335   msaitoh 		}
   5778  1.335   msaitoh 	} else
   5779  1.335   msaitoh 		CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
   5780  1.232    bouyer 
   5781  1.281   msaitoh 	/* Set up the inter-packet gap. */
   5782  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   5783  1.232    bouyer 
   5784  1.281   msaitoh 	if (sc->sc_type >= WM_T_82543) {
   5785  1.491  knakahar 		for (int qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5786  1.491  knakahar 			struct wm_queue *wmq = &sc->sc_queue[qidx];
   5787  1.491  knakahar 			wm_itrs_writereg(sc, wmq);
   5788  1.491  knakahar 		}
   5789  1.491  knakahar 		/*
   5790  1.491  knakahar 		 * Link interrupts occur much less than TX
   5791  1.491  knakahar 		 * interrupts and RX interrupts. So, we don't
   5792  1.491  knakahar 		 * tune EINTR(WM_MSIX_LINKINTR_IDX) value like
   5793  1.491  knakahar 		 * FreeBSD's if_igb.
   5794  1.491  knakahar 		 */
   5795  1.281   msaitoh 	}
   5796  1.232    bouyer 
   5797  1.281   msaitoh 	/* Set the VLAN ethernetype. */
   5798  1.281   msaitoh 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
   5799  1.232    bouyer 
   5800  1.281   msaitoh 	/*
   5801  1.281   msaitoh 	 * Set up the transmit control register; we start out with
   5802  1.281   msaitoh 	 * a collision distance suitable for FDX, but update it whe
   5803  1.281   msaitoh 	 * we resolve the media type.
   5804  1.281   msaitoh 	 */
   5805  1.281   msaitoh 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
   5806  1.281   msaitoh 	    | TCTL_CT(TX_COLLISION_THRESHOLD)
   5807  1.281   msaitoh 	    | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   5808  1.281   msaitoh 	if (sc->sc_type >= WM_T_82571)
   5809  1.281   msaitoh 		sc->sc_tctl |= TCTL_MULR;
   5810  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   5811  1.232    bouyer 
   5812  1.281   msaitoh 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   5813  1.281   msaitoh 		/* Write TDT after TCTL.EN is set. See the document. */
   5814  1.361  knakahar 		CSR_WRITE(sc, WMREG_TDT(0), 0);
   5815  1.232    bouyer 	}
   5816  1.232    bouyer 
   5817  1.281   msaitoh 	if (sc->sc_type == WM_T_80003) {
   5818  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_TCTL_EXT);
   5819  1.281   msaitoh 		reg &= ~TCTL_EXT_GCEX_MASK;
   5820  1.281   msaitoh 		reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
   5821  1.281   msaitoh 		CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
   5822  1.272     ozaki 	}
   5823  1.272     ozaki 
   5824  1.281   msaitoh 	/* Set the media. */
   5825  1.281   msaitoh 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
   5826  1.281   msaitoh 		goto out;
   5827  1.281   msaitoh 
   5828  1.281   msaitoh 	/* Configure for OS presence */
   5829  1.281   msaitoh 	wm_init_manageability(sc);
   5830  1.232    bouyer 
   5831  1.281   msaitoh 	/*
   5832  1.281   msaitoh 	 * Set up the receive control register; we actually program
   5833  1.281   msaitoh 	 * the register when we set the receive filter.  Use multicast
   5834  1.281   msaitoh 	 * address offset type 0.
   5835  1.281   msaitoh 	 *
   5836  1.281   msaitoh 	 * Only the i82544 has the ability to strip the incoming
   5837  1.281   msaitoh 	 * CRC, so we don't enable that feature.
   5838  1.281   msaitoh 	 */
   5839  1.281   msaitoh 	sc->sc_mchash_type = 0;
   5840  1.281   msaitoh 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
   5841  1.281   msaitoh 	    | RCTL_MO(sc->sc_mchash_type);
   5842  1.281   msaitoh 
   5843  1.281   msaitoh 	/*
   5844  1.466  knakahar 	 * 82574 use one buffer extended Rx descriptor.
   5845  1.466  knakahar 	 */
   5846  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   5847  1.466  knakahar 		sc->sc_rctl |= RCTL_DTYP_ONEBUF;
   5848  1.466  knakahar 
   5849  1.466  knakahar 	/*
   5850  1.281   msaitoh 	 * The I350 has a bug where it always strips the CRC whether
   5851  1.281   msaitoh 	 * asked to or not. So ask for stripped CRC here and cope in rxeof
   5852  1.281   msaitoh 	 */
   5853  1.281   msaitoh 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   5854  1.281   msaitoh 	    || (sc->sc_type == WM_T_I210))
   5855  1.281   msaitoh 		sc->sc_rctl |= RCTL_SECRC;
   5856  1.281   msaitoh 
   5857  1.281   msaitoh 	if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
   5858  1.281   msaitoh 	    && (ifp->if_mtu > ETHERMTU)) {
   5859  1.281   msaitoh 		sc->sc_rctl |= RCTL_LPE;
   5860  1.281   msaitoh 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   5861  1.281   msaitoh 			CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
   5862  1.281   msaitoh 	}
   5863  1.281   msaitoh 
   5864  1.281   msaitoh 	if (MCLBYTES == 2048) {
   5865  1.281   msaitoh 		sc->sc_rctl |= RCTL_2k;
   5866  1.281   msaitoh 	} else {
   5867  1.281   msaitoh 		if (sc->sc_type >= WM_T_82543) {
   5868  1.281   msaitoh 			switch (MCLBYTES) {
   5869  1.281   msaitoh 			case 4096:
   5870  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
   5871  1.281   msaitoh 				break;
   5872  1.281   msaitoh 			case 8192:
   5873  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
   5874  1.281   msaitoh 				break;
   5875  1.281   msaitoh 			case 16384:
   5876  1.281   msaitoh 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
   5877  1.281   msaitoh 				break;
   5878  1.281   msaitoh 			default:
   5879  1.281   msaitoh 				panic("wm_init: MCLBYTES %d unsupported",
   5880  1.281   msaitoh 				    MCLBYTES);
   5881  1.281   msaitoh 				break;
   5882  1.281   msaitoh 			}
   5883  1.281   msaitoh 		} else panic("wm_init: i82542 requires MCLBYTES = 2048");
   5884  1.281   msaitoh 	}
   5885  1.281   msaitoh 
   5886  1.281   msaitoh 	/* Enable ECC */
   5887  1.281   msaitoh 	switch (sc->sc_type) {
   5888  1.281   msaitoh 	case WM_T_82571:
   5889  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PBA_ECC);
   5890  1.281   msaitoh 		reg |= PBA_ECC_CORR_EN;
   5891  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBA_ECC, reg);
   5892  1.281   msaitoh 		break;
   5893  1.281   msaitoh 	case WM_T_PCH_LPT:
   5894  1.392   msaitoh 	case WM_T_PCH_SPT:
   5895  1.570   msaitoh 	case WM_T_PCH_CNP:
   5896  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PBECCSTS);
   5897  1.281   msaitoh 		reg |= PBECCSTS_UNCORR_ECC_ENABLE;
   5898  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PBECCSTS, reg);
   5899  1.281   msaitoh 
   5900  1.444   msaitoh 		sc->sc_ctrl |= CTRL_MEHE;
   5901  1.444   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   5902  1.281   msaitoh 		break;
   5903  1.281   msaitoh 	default:
   5904  1.281   msaitoh 		break;
   5905  1.232    bouyer 	}
   5906  1.281   msaitoh 
   5907  1.548   msaitoh 	/*
   5908  1.548   msaitoh 	 * Set the receive filter.
   5909  1.548   msaitoh 	 *
   5910  1.548   msaitoh 	 * For 82575 and 82576, the RX descriptors must be initialized after
   5911  1.548   msaitoh 	 * the setting of RCTL.EN in wm_set_filter()
   5912  1.548   msaitoh 	 */
   5913  1.548   msaitoh 	wm_set_filter(sc);
   5914  1.548   msaitoh 
   5915  1.281   msaitoh 	/* On 575 and later set RDT only if RX enabled */
   5916  1.362  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   5917  1.364  knakahar 		int qidx;
   5918  1.405  knakahar 		for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   5919  1.405  knakahar 			struct wm_rxqueue *rxq = &sc->sc_queue[qidx].wmq_rxq;
   5920  1.364  knakahar 			for (i = 0; i < WM_NRXDESC; i++) {
   5921  1.413     skrll 				mutex_enter(rxq->rxq_lock);
   5922  1.364  knakahar 				wm_init_rxdesc(rxq, i);
   5923  1.413     skrll 				mutex_exit(rxq->rxq_lock);
   5924  1.364  knakahar 
   5925  1.364  knakahar 			}
   5926  1.364  knakahar 		}
   5927  1.362  knakahar 	}
   5928  1.281   msaitoh 
   5929  1.537  knakahar 	wm_unset_stopping_flags(sc);
   5930  1.281   msaitoh 
   5931  1.281   msaitoh 	/* Start the one second link check clock. */
   5932  1.281   msaitoh 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   5933  1.281   msaitoh 
   5934  1.281   msaitoh 	/* ...all done! */
   5935  1.281   msaitoh 	ifp->if_flags |= IFF_RUNNING;
   5936  1.281   msaitoh 	ifp->if_flags &= ~IFF_OACTIVE;
   5937  1.281   msaitoh 
   5938  1.281   msaitoh  out:
   5939  1.281   msaitoh 	sc->sc_if_flags = ifp->if_flags;
   5940  1.281   msaitoh 	if (error)
   5941  1.281   msaitoh 		log(LOG_ERR, "%s: interface not running\n",
   5942  1.281   msaitoh 		    device_xname(sc->sc_dev));
   5943  1.281   msaitoh 	return error;
   5944  1.232    bouyer }
   5945  1.232    bouyer 
   5946  1.232    bouyer /*
   5947  1.281   msaitoh  * wm_stop:		[ifnet interface function]
   5948    1.1   thorpej  *
   5949  1.281   msaitoh  *	Stop transmission on the interface.
   5950    1.1   thorpej  */
   5951   1.47   thorpej static void
   5952  1.281   msaitoh wm_stop(struct ifnet *ifp, int disable)
   5953    1.1   thorpej {
   5954    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   5955    1.1   thorpej 
   5956  1.357  knakahar 	WM_CORE_LOCK(sc);
   5957  1.281   msaitoh 	wm_stop_locked(ifp, disable);
   5958  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   5959    1.1   thorpej }
   5960    1.1   thorpej 
   5961  1.281   msaitoh static void
   5962  1.281   msaitoh wm_stop_locked(struct ifnet *ifp, int disable)
   5963  1.213   msaitoh {
   5964  1.213   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   5965  1.281   msaitoh 	struct wm_txsoft *txs;
   5966  1.364  knakahar 	int i, qidx;
   5967  1.281   msaitoh 
   5968  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   5969  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   5970  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   5971  1.281   msaitoh 
   5972  1.537  knakahar 	wm_set_stopping_flags(sc);
   5973  1.272     ozaki 
   5974  1.281   msaitoh 	/* Stop the one second clock. */
   5975  1.281   msaitoh 	callout_stop(&sc->sc_tick_ch);
   5976  1.213   msaitoh 
   5977  1.281   msaitoh 	/* Stop the 82547 Tx FIFO stall check timer. */
   5978  1.281   msaitoh 	if (sc->sc_type == WM_T_82547)
   5979  1.281   msaitoh 		callout_stop(&sc->sc_txfifo_ch);
   5980  1.217    dyoung 
   5981  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII) {
   5982  1.281   msaitoh 		/* Down the MII. */
   5983  1.281   msaitoh 		mii_down(&sc->sc_mii);
   5984  1.281   msaitoh 	} else {
   5985  1.281   msaitoh #if 0
   5986  1.281   msaitoh 		/* Should we clear PHY's status properly? */
   5987  1.281   msaitoh 		wm_reset(sc);
   5988  1.281   msaitoh #endif
   5989  1.272     ozaki 	}
   5990  1.213   msaitoh 
   5991  1.281   msaitoh 	/* Stop the transmit and receive processes. */
   5992  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, 0);
   5993  1.281   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, 0);
   5994  1.281   msaitoh 	sc->sc_rctl &= ~RCTL_EN;
   5995  1.281   msaitoh 
   5996  1.281   msaitoh 	/*
   5997  1.281   msaitoh 	 * Clear the interrupt mask to ensure the device cannot assert its
   5998  1.281   msaitoh 	 * interrupt line.
   5999  1.335   msaitoh 	 * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to
   6000  1.335   msaitoh 	 * service any currently pending or shared interrupt.
   6001  1.281   msaitoh 	 */
   6002  1.281   msaitoh 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   6003  1.281   msaitoh 	sc->sc_icr = 0;
   6004  1.502  knakahar 	if (wm_is_using_msix(sc)) {
   6005  1.335   msaitoh 		if (sc->sc_type != WM_T_82574) {
   6006  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU);
   6007  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC, 0);
   6008  1.335   msaitoh 		} else
   6009  1.335   msaitoh 			CSR_WRITE(sc, WMREG_EIAC_82574, 0);
   6010  1.335   msaitoh 	}
   6011  1.281   msaitoh 
   6012  1.281   msaitoh 	/* Release any queued transmit buffers. */
   6013  1.405  knakahar 	for (qidx = 0; qidx < sc->sc_nqueues; qidx++) {
   6014  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[qidx];
   6015  1.405  knakahar 		struct wm_txqueue *txq = &wmq->wmq_txq;
   6016  1.413     skrll 		mutex_enter(txq->txq_lock);
   6017  1.576   msaitoh 		txq->txq_sending = false; /* ensure watchdog disabled */
   6018  1.364  knakahar 		for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6019  1.364  knakahar 			txs = &txq->txq_soft[i];
   6020  1.364  knakahar 			if (txs->txs_mbuf != NULL) {
   6021  1.388   msaitoh 				bus_dmamap_unload(sc->sc_dmat,txs->txs_dmamap);
   6022  1.364  knakahar 				m_freem(txs->txs_mbuf);
   6023  1.364  knakahar 				txs->txs_mbuf = NULL;
   6024  1.364  knakahar 			}
   6025  1.281   msaitoh 		}
   6026  1.413     skrll 		mutex_exit(txq->txq_lock);
   6027  1.281   msaitoh 	}
   6028  1.217    dyoung 
   6029  1.281   msaitoh 	/* Mark the interface as down and cancel the watchdog timer. */
   6030  1.281   msaitoh 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   6031  1.213   msaitoh 
   6032  1.357  knakahar 	if (disable) {
   6033  1.405  knakahar 		for (i = 0; i < sc->sc_nqueues; i++) {
   6034  1.405  knakahar 			struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6035  1.413     skrll 			mutex_enter(rxq->rxq_lock);
   6036  1.364  knakahar 			wm_rxdrain(rxq);
   6037  1.413     skrll 			mutex_exit(rxq->rxq_lock);
   6038  1.364  knakahar 		}
   6039  1.357  knakahar 	}
   6040  1.272     ozaki 
   6041  1.281   msaitoh #if 0 /* notyet */
   6042  1.281   msaitoh 	if (sc->sc_type >= WM_T_82544)
   6043  1.281   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   6044  1.281   msaitoh #endif
   6045  1.213   msaitoh }
   6046  1.213   msaitoh 
   6047   1.47   thorpej static void
   6048  1.281   msaitoh wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
   6049    1.1   thorpej {
   6050  1.281   msaitoh 	struct mbuf *m;
   6051    1.1   thorpej 	int i;
   6052    1.1   thorpej 
   6053  1.281   msaitoh 	log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev));
   6054  1.281   msaitoh 	for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
   6055  1.281   msaitoh 		log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
   6056  1.281   msaitoh 		    "m_flags = 0x%08x\n", device_xname(sc->sc_dev),
   6057  1.281   msaitoh 		    m->m_data, m->m_len, m->m_flags);
   6058  1.281   msaitoh 	log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev),
   6059  1.281   msaitoh 	    i, i == 1 ? "" : "s");
   6060  1.281   msaitoh }
   6061  1.272     ozaki 
   6062  1.281   msaitoh /*
   6063  1.281   msaitoh  * wm_82547_txfifo_stall:
   6064  1.281   msaitoh  *
   6065  1.281   msaitoh  *	Callout used to wait for the 82547 Tx FIFO to drain,
   6066  1.281   msaitoh  *	reset the FIFO pointers, and restart packet transmission.
   6067  1.281   msaitoh  */
   6068  1.281   msaitoh static void
   6069  1.281   msaitoh wm_82547_txfifo_stall(void *arg)
   6070  1.281   msaitoh {
   6071  1.281   msaitoh 	struct wm_softc *sc = arg;
   6072  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   6073    1.1   thorpej 
   6074  1.413     skrll 	mutex_enter(txq->txq_lock);
   6075    1.1   thorpej 
   6076  1.429  knakahar 	if (txq->txq_stopping)
   6077  1.281   msaitoh 		goto out;
   6078    1.1   thorpej 
   6079  1.356  knakahar 	if (txq->txq_fifo_stall) {
   6080  1.361  knakahar 		if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) &&
   6081  1.281   msaitoh 		    CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
   6082  1.281   msaitoh 		    CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
   6083  1.281   msaitoh 			/*
   6084  1.281   msaitoh 			 * Packets have drained.  Stop transmitter, reset
   6085  1.281   msaitoh 			 * FIFO pointers, restart transmitter, and kick
   6086  1.281   msaitoh 			 * the packet queue.
   6087  1.281   msaitoh 			 */
   6088  1.281   msaitoh 			uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
   6089  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
   6090  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr);
   6091  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr);
   6092  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr);
   6093  1.356  knakahar 			CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr);
   6094  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, tctl);
   6095  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   6096    1.1   thorpej 
   6097  1.356  knakahar 			txq->txq_fifo_head = 0;
   6098  1.356  knakahar 			txq->txq_fifo_stall = 0;
   6099  1.281   msaitoh 			wm_start_locked(&sc->sc_ethercom.ec_if);
   6100  1.281   msaitoh 		} else {
   6101  1.281   msaitoh 			/*
   6102  1.281   msaitoh 			 * Still waiting for packets to drain; try again in
   6103  1.281   msaitoh 			 * another tick.
   6104  1.281   msaitoh 			 */
   6105  1.281   msaitoh 			callout_schedule(&sc->sc_txfifo_ch, 1);
   6106   1.20   thorpej 		}
   6107  1.281   msaitoh 	}
   6108    1.1   thorpej 
   6109  1.281   msaitoh out:
   6110  1.413     skrll 	mutex_exit(txq->txq_lock);
   6111  1.281   msaitoh }
   6112    1.1   thorpej 
   6113  1.281   msaitoh /*
   6114  1.281   msaitoh  * wm_82547_txfifo_bugchk:
   6115  1.281   msaitoh  *
   6116  1.281   msaitoh  *	Check for bug condition in the 82547 Tx FIFO.  We need to
   6117  1.281   msaitoh  *	prevent enqueueing a packet that would wrap around the end
   6118  1.281   msaitoh  *	if the Tx FIFO ring buffer, otherwise the chip will croak.
   6119  1.281   msaitoh  *
   6120  1.281   msaitoh  *	We do this by checking the amount of space before the end
   6121  1.281   msaitoh  *	of the Tx FIFO buffer.  If the packet will not fit, we "stall"
   6122  1.281   msaitoh  *	the Tx FIFO, wait for all remaining packets to drain, reset
   6123  1.281   msaitoh  *	the internal FIFO pointers to the beginning, and restart
   6124  1.281   msaitoh  *	transmission on the interface.
   6125  1.281   msaitoh  */
   6126  1.281   msaitoh #define	WM_FIFO_HDR		0x10
   6127  1.281   msaitoh #define	WM_82547_PAD_LEN	0x3e0
   6128  1.281   msaitoh static int
   6129  1.281   msaitoh wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
   6130  1.281   msaitoh {
   6131  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   6132  1.356  knakahar 	int space = txq->txq_fifo_size - txq->txq_fifo_head;
   6133  1.281   msaitoh 	int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
   6134    1.1   thorpej 
   6135  1.281   msaitoh 	/* Just return if already stalled. */
   6136  1.356  knakahar 	if (txq->txq_fifo_stall)
   6137  1.281   msaitoh 		return 1;
   6138    1.1   thorpej 
   6139  1.281   msaitoh 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   6140  1.281   msaitoh 		/* Stall only occurs in half-duplex mode. */
   6141  1.281   msaitoh 		goto send_packet;
   6142  1.281   msaitoh 	}
   6143    1.1   thorpej 
   6144  1.281   msaitoh 	if (len >= WM_82547_PAD_LEN + space) {
   6145  1.356  knakahar 		txq->txq_fifo_stall = 1;
   6146  1.281   msaitoh 		callout_schedule(&sc->sc_txfifo_ch, 1);
   6147  1.281   msaitoh 		return 1;
   6148    1.1   thorpej 	}
   6149    1.1   thorpej 
   6150  1.281   msaitoh  send_packet:
   6151  1.356  knakahar 	txq->txq_fifo_head += len;
   6152  1.356  knakahar 	if (txq->txq_fifo_head >= txq->txq_fifo_size)
   6153  1.356  knakahar 		txq->txq_fifo_head -= txq->txq_fifo_size;
   6154    1.1   thorpej 
   6155  1.281   msaitoh 	return 0;
   6156    1.1   thorpej }
   6157    1.1   thorpej 
   6158  1.353  knakahar static int
   6159  1.362  knakahar wm_alloc_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
   6160  1.354  knakahar {
   6161  1.354  knakahar 	int error;
   6162  1.354  knakahar 
   6163  1.354  knakahar 	/*
   6164  1.354  knakahar 	 * Allocate the control data structures, and create and load the
   6165  1.354  knakahar 	 * DMA map for it.
   6166  1.354  knakahar 	 *
   6167  1.354  knakahar 	 * NOTE: All Tx descriptors must be in the same 4G segment of
   6168  1.354  knakahar 	 * memory.  So must Rx descriptors.  We simplify by allocating
   6169  1.354  knakahar 	 * both sets within the same 4G segment.
   6170  1.354  knakahar 	 */
   6171  1.399  knakahar 	if (sc->sc_type < WM_T_82544)
   6172  1.356  knakahar 		WM_NTXDESC(txq) = WM_NTXDESC_82542;
   6173  1.399  knakahar 	else
   6174  1.356  knakahar 		WM_NTXDESC(txq) = WM_NTXDESC_82544;
   6175  1.398  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   6176  1.398  knakahar 		txq->txq_descsize = sizeof(nq_txdesc_t);
   6177  1.398  knakahar 	else
   6178  1.398  knakahar 		txq->txq_descsize = sizeof(wiseman_txdesc_t);
   6179  1.354  knakahar 
   6180  1.399  knakahar 	if ((error = bus_dmamem_alloc(sc->sc_dmat, WM_TXDESCS_SIZE(txq),
   6181  1.388   msaitoh 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg,
   6182  1.388   msaitoh 		    1, &txq->txq_desc_rseg, 0)) != 0) {
   6183  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   6184  1.354  knakahar 		    "unable to allocate TX control data, error = %d\n",
   6185  1.354  knakahar 		    error);
   6186  1.354  knakahar 		goto fail_0;
   6187  1.354  knakahar 	}
   6188  1.354  knakahar 
   6189  1.356  knakahar 	if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg,
   6190  1.399  knakahar 		    txq->txq_desc_rseg, WM_TXDESCS_SIZE(txq),
   6191  1.356  knakahar 		    (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) {
   6192  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   6193  1.354  knakahar 		    "unable to map TX control data, error = %d\n", error);
   6194  1.354  knakahar 		goto fail_1;
   6195  1.354  knakahar 	}
   6196  1.354  knakahar 
   6197  1.399  knakahar 	if ((error = bus_dmamap_create(sc->sc_dmat, WM_TXDESCS_SIZE(txq), 1,
   6198  1.399  knakahar 		    WM_TXDESCS_SIZE(txq), 0, 0, &txq->txq_desc_dmamap)) != 0) {
   6199  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   6200  1.354  knakahar 		    "unable to create TX control data DMA map, error = %d\n",
   6201  1.354  knakahar 		    error);
   6202  1.354  knakahar 		goto fail_2;
   6203  1.354  knakahar 	}
   6204  1.354  knakahar 
   6205  1.356  knakahar 	if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap,
   6206  1.399  knakahar 		    txq->txq_descs_u, WM_TXDESCS_SIZE(txq), NULL, 0)) != 0) {
   6207  1.354  knakahar 		aprint_error_dev(sc->sc_dev,
   6208  1.354  knakahar 		    "unable to load TX control data DMA map, error = %d\n",
   6209  1.354  knakahar 		    error);
   6210  1.354  knakahar 		goto fail_3;
   6211  1.354  knakahar 	}
   6212  1.354  knakahar 
   6213  1.354  knakahar 	return 0;
   6214  1.354  knakahar 
   6215  1.354  knakahar  fail_3:
   6216  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
   6217  1.354  knakahar  fail_2:
   6218  1.356  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
   6219  1.399  knakahar 	    WM_TXDESCS_SIZE(txq));
   6220  1.354  knakahar  fail_1:
   6221  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
   6222  1.354  knakahar  fail_0:
   6223  1.354  knakahar 	return error;
   6224  1.354  knakahar }
   6225  1.354  knakahar 
   6226  1.354  knakahar static void
   6227  1.362  knakahar wm_free_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq)
   6228  1.354  knakahar {
   6229  1.354  knakahar 
   6230  1.356  knakahar 	bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap);
   6231  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap);
   6232  1.356  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u,
   6233  1.399  knakahar 	    WM_TXDESCS_SIZE(txq));
   6234  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg);
   6235  1.354  knakahar }
   6236  1.354  knakahar 
   6237  1.354  knakahar static int
   6238  1.362  knakahar wm_alloc_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6239  1.353  knakahar {
   6240  1.353  knakahar 	int error;
   6241  1.466  knakahar 	size_t rxq_descs_size;
   6242  1.353  knakahar 
   6243  1.353  knakahar 	/*
   6244  1.353  knakahar 	 * Allocate the control data structures, and create and load the
   6245  1.353  knakahar 	 * DMA map for it.
   6246  1.353  knakahar 	 *
   6247  1.353  knakahar 	 * NOTE: All Tx descriptors must be in the same 4G segment of
   6248  1.353  knakahar 	 * memory.  So must Rx descriptors.  We simplify by allocating
   6249  1.353  knakahar 	 * both sets within the same 4G segment.
   6250  1.353  knakahar 	 */
   6251  1.466  knakahar 	rxq->rxq_ndesc = WM_NRXDESC;
   6252  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   6253  1.466  knakahar 		rxq->rxq_descsize = sizeof(ext_rxdesc_t);
   6254  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   6255  1.466  knakahar 		rxq->rxq_descsize = sizeof(nq_rxdesc_t);
   6256  1.466  knakahar 	else
   6257  1.466  knakahar 		rxq->rxq_descsize = sizeof(wiseman_rxdesc_t);
   6258  1.466  knakahar 	rxq_descs_size = rxq->rxq_descsize * rxq->rxq_ndesc;
   6259  1.466  knakahar 
   6260  1.466  knakahar 	if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq_descs_size,
   6261  1.388   msaitoh 		    PAGE_SIZE, (bus_size_t) 0x100000000ULL, &rxq->rxq_desc_seg,
   6262  1.388   msaitoh 		    1, &rxq->rxq_desc_rseg, 0)) != 0) {
   6263  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   6264  1.354  knakahar 		    "unable to allocate RX control data, error = %d\n",
   6265  1.353  knakahar 		    error);
   6266  1.353  knakahar 		goto fail_0;
   6267  1.353  knakahar 	}
   6268  1.353  knakahar 
   6269  1.356  knakahar 	if ((error = bus_dmamem_map(sc->sc_dmat, &rxq->rxq_desc_seg,
   6270  1.466  knakahar 		    rxq->rxq_desc_rseg, rxq_descs_size,
   6271  1.466  knakahar 		    (void **)&rxq->rxq_descs_u, BUS_DMA_COHERENT)) != 0) {
   6272  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   6273  1.354  knakahar 		    "unable to map RX control data, error = %d\n", error);
   6274  1.353  knakahar 		goto fail_1;
   6275  1.353  knakahar 	}
   6276  1.353  knakahar 
   6277  1.466  knakahar 	if ((error = bus_dmamap_create(sc->sc_dmat, rxq_descs_size, 1,
   6278  1.466  knakahar 		    rxq_descs_size, 0, 0, &rxq->rxq_desc_dmamap)) != 0) {
   6279  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   6280  1.354  knakahar 		    "unable to create RX control data DMA map, error = %d\n",
   6281  1.353  knakahar 		    error);
   6282  1.353  knakahar 		goto fail_2;
   6283  1.353  knakahar 	}
   6284  1.353  knakahar 
   6285  1.356  knakahar 	if ((error = bus_dmamap_load(sc->sc_dmat, rxq->rxq_desc_dmamap,
   6286  1.466  knakahar 		    rxq->rxq_descs_u, rxq_descs_size, NULL, 0)) != 0) {
   6287  1.353  knakahar 		aprint_error_dev(sc->sc_dev,
   6288  1.354  knakahar 		    "unable to load RX control data DMA map, error = %d\n",
   6289  1.353  knakahar 		    error);
   6290  1.353  knakahar 		goto fail_3;
   6291  1.353  knakahar 	}
   6292  1.353  knakahar 
   6293  1.353  knakahar 	return 0;
   6294  1.353  knakahar 
   6295  1.353  knakahar  fail_3:
   6296  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
   6297  1.353  knakahar  fail_2:
   6298  1.466  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
   6299  1.466  knakahar 	    rxq_descs_size);
   6300  1.353  knakahar  fail_1:
   6301  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
   6302  1.353  knakahar  fail_0:
   6303  1.353  knakahar 	return error;
   6304  1.353  knakahar }
   6305  1.353  knakahar 
   6306  1.353  knakahar static void
   6307  1.362  knakahar wm_free_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6308  1.353  knakahar {
   6309  1.353  knakahar 
   6310  1.356  knakahar 	bus_dmamap_unload(sc->sc_dmat, rxq->rxq_desc_dmamap);
   6311  1.356  knakahar 	bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap);
   6312  1.466  knakahar 	bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs_u,
   6313  1.466  knakahar 	    rxq->rxq_descsize * rxq->rxq_ndesc);
   6314  1.356  knakahar 	bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg);
   6315  1.353  knakahar }
   6316  1.353  knakahar 
   6317  1.354  knakahar 
   6318  1.353  knakahar static int
   6319  1.362  knakahar wm_alloc_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
   6320  1.353  knakahar {
   6321  1.353  knakahar 	int i, error;
   6322  1.353  knakahar 
   6323  1.353  knakahar 	/* Create the transmit buffer DMA maps. */
   6324  1.356  knakahar 	WM_TXQUEUELEN(txq) =
   6325  1.353  knakahar 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
   6326  1.353  knakahar 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
   6327  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6328  1.353  knakahar 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
   6329  1.353  knakahar 			    WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
   6330  1.356  knakahar 			    &txq->txq_soft[i].txs_dmamap)) != 0) {
   6331  1.353  knakahar 			aprint_error_dev(sc->sc_dev,
   6332  1.353  knakahar 			    "unable to create Tx DMA map %d, error = %d\n",
   6333  1.353  knakahar 			    i, error);
   6334  1.353  knakahar 			goto fail;
   6335  1.353  knakahar 		}
   6336  1.353  knakahar 	}
   6337  1.353  knakahar 
   6338  1.353  knakahar 	return 0;
   6339  1.353  knakahar 
   6340  1.353  knakahar  fail:
   6341  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6342  1.356  knakahar 		if (txq->txq_soft[i].txs_dmamap != NULL)
   6343  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6344  1.356  knakahar 			    txq->txq_soft[i].txs_dmamap);
   6345  1.353  knakahar 	}
   6346  1.353  knakahar 	return error;
   6347  1.353  knakahar }
   6348  1.353  knakahar 
   6349  1.353  knakahar static void
   6350  1.362  knakahar wm_free_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq)
   6351  1.353  knakahar {
   6352  1.353  knakahar 	int i;
   6353  1.353  knakahar 
   6354  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++) {
   6355  1.356  knakahar 		if (txq->txq_soft[i].txs_dmamap != NULL)
   6356  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6357  1.356  knakahar 			    txq->txq_soft[i].txs_dmamap);
   6358  1.353  knakahar 	}
   6359  1.353  knakahar }
   6360  1.353  knakahar 
   6361  1.353  knakahar static int
   6362  1.362  knakahar wm_alloc_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6363  1.353  knakahar {
   6364  1.353  knakahar 	int i, error;
   6365  1.353  knakahar 
   6366  1.353  knakahar 	/* Create the receive buffer DMA maps. */
   6367  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6368  1.353  knakahar 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
   6369  1.353  knakahar 			    MCLBYTES, 0, 0,
   6370  1.356  knakahar 			    &rxq->rxq_soft[i].rxs_dmamap)) != 0) {
   6371  1.353  knakahar 			aprint_error_dev(sc->sc_dev,
   6372  1.353  knakahar 			    "unable to create Rx DMA map %d error = %d\n",
   6373  1.353  knakahar 			    i, error);
   6374  1.353  knakahar 			goto fail;
   6375  1.353  knakahar 		}
   6376  1.356  knakahar 		rxq->rxq_soft[i].rxs_mbuf = NULL;
   6377  1.353  knakahar 	}
   6378  1.353  knakahar 
   6379  1.353  knakahar 	return 0;
   6380  1.353  knakahar 
   6381  1.353  knakahar  fail:
   6382  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6383  1.356  knakahar 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
   6384  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6385  1.356  knakahar 			    rxq->rxq_soft[i].rxs_dmamap);
   6386  1.353  knakahar 	}
   6387  1.353  knakahar 	return error;
   6388  1.353  knakahar }
   6389  1.353  knakahar 
   6390  1.353  knakahar static void
   6391  1.362  knakahar wm_free_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6392  1.353  knakahar {
   6393  1.353  knakahar 	int i;
   6394  1.353  knakahar 
   6395  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6396  1.356  knakahar 		if (rxq->rxq_soft[i].rxs_dmamap != NULL)
   6397  1.353  knakahar 			bus_dmamap_destroy(sc->sc_dmat,
   6398  1.356  knakahar 			    rxq->rxq_soft[i].rxs_dmamap);
   6399  1.353  knakahar 	}
   6400  1.353  knakahar }
   6401  1.353  knakahar 
   6402  1.353  knakahar /*
   6403  1.353  knakahar  * wm_alloc_quques:
   6404  1.353  knakahar  *	Allocate {tx,rx}descs and {tx,rx} buffers
   6405  1.353  knakahar  */
   6406  1.353  knakahar static int
   6407  1.353  knakahar wm_alloc_txrx_queues(struct wm_softc *sc)
   6408  1.353  knakahar {
   6409  1.364  knakahar 	int i, error, tx_done, rx_done;
   6410  1.353  knakahar 
   6411  1.405  knakahar 	sc->sc_queue = kmem_zalloc(sizeof(struct wm_queue) * sc->sc_nqueues,
   6412  1.356  knakahar 	    KM_SLEEP);
   6413  1.405  knakahar 	if (sc->sc_queue == NULL) {
   6414  1.405  knakahar 		aprint_error_dev(sc->sc_dev,"unable to allocate wm_queue\n");
   6415  1.356  knakahar 		error = ENOMEM;
   6416  1.356  knakahar 		goto fail_0;
   6417  1.356  knakahar 	}
   6418  1.364  knakahar 
   6419  1.405  knakahar 	/*
   6420  1.405  knakahar 	 * For transmission
   6421  1.405  knakahar 	 */
   6422  1.364  knakahar 	error = 0;
   6423  1.364  knakahar 	tx_done = 0;
   6424  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6425  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6426  1.417  knakahar 		int j;
   6427  1.417  knakahar 		const char *xname;
   6428  1.417  knakahar #endif
   6429  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6430  1.364  knakahar 		txq->txq_sc = sc;
   6431  1.362  knakahar 		txq->txq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   6432  1.408  knakahar 
   6433  1.362  knakahar 		error = wm_alloc_tx_descs(sc, txq);
   6434  1.364  knakahar 		if (error)
   6435  1.364  knakahar 			break;
   6436  1.364  knakahar 		error = wm_alloc_tx_buffer(sc, txq);
   6437  1.364  knakahar 		if (error) {
   6438  1.364  knakahar 			wm_free_tx_descs(sc, txq);
   6439  1.364  knakahar 			break;
   6440  1.364  knakahar 		}
   6441  1.403  knakahar 		txq->txq_interq = pcq_create(WM_TXINTERQSIZE, KM_SLEEP);
   6442  1.403  knakahar 		if (txq->txq_interq == NULL) {
   6443  1.403  knakahar 			wm_free_tx_descs(sc, txq);
   6444  1.403  knakahar 			wm_free_tx_buffer(sc, txq);
   6445  1.403  knakahar 			error = ENOMEM;
   6446  1.403  knakahar 			break;
   6447  1.403  knakahar 		}
   6448  1.417  knakahar 
   6449  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6450  1.417  knakahar 		xname = device_xname(sc->sc_dev);
   6451  1.417  knakahar 
   6452  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txsstall, txq, i, xname);
   6453  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txdstall, txq, i, xname);
   6454  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txfifo_stall, txq, i, xname);
   6455  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(txq, txdw, txq, i, xname);
   6456  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(txq, txqe, txq, i, xname);
   6457  1.417  knakahar 
   6458  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txipsum, txq, i, xname);
   6459  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtusum, txq, i, xname);
   6460  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtusum6, txq, i, xname);
   6461  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtso, txq, i, xname);
   6462  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtso6, txq, i, xname);
   6463  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txtsopain, txq, i, xname);
   6464  1.417  knakahar 
   6465  1.417  knakahar 		for (j = 0; j < WM_NTXSEGS; j++) {
   6466  1.417  knakahar 			snprintf(txq->txq_txseg_evcnt_names[j],
   6467  1.417  knakahar 			    sizeof(txq->txq_txseg_evcnt_names[j]), "txq%02dtxseg%d", i, j);
   6468  1.417  knakahar 			evcnt_attach_dynamic(&txq->txq_ev_txseg[j], EVCNT_TYPE_MISC,
   6469  1.417  knakahar 			    NULL, xname, txq->txq_txseg_evcnt_names[j]);
   6470  1.417  knakahar 		}
   6471  1.417  knakahar 
   6472  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, txdrop, txq, i, xname);
   6473  1.417  knakahar 
   6474  1.417  knakahar 		WM_Q_MISC_EVCNT_ATTACH(txq, tu, txq, i, xname);
   6475  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
   6476  1.417  knakahar 
   6477  1.364  knakahar 		tx_done++;
   6478  1.364  knakahar 	}
   6479  1.353  knakahar 	if (error)
   6480  1.356  knakahar 		goto fail_1;
   6481  1.353  knakahar 
   6482  1.354  knakahar 	/*
   6483  1.354  knakahar 	 * For recieve
   6484  1.354  knakahar 	 */
   6485  1.364  knakahar 	error = 0;
   6486  1.364  knakahar 	rx_done = 0;
   6487  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6488  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6489  1.417  knakahar 		const char *xname;
   6490  1.417  knakahar #endif
   6491  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6492  1.364  knakahar 		rxq->rxq_sc = sc;
   6493  1.362  knakahar 		rxq->rxq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
   6494  1.414  knakahar 
   6495  1.364  knakahar 		error = wm_alloc_rx_descs(sc, rxq);
   6496  1.364  knakahar 		if (error)
   6497  1.364  knakahar 			break;
   6498  1.356  knakahar 
   6499  1.364  knakahar 		error = wm_alloc_rx_buffer(sc, rxq);
   6500  1.364  knakahar 		if (error) {
   6501  1.364  knakahar 			wm_free_rx_descs(sc, rxq);
   6502  1.364  knakahar 			break;
   6503  1.364  knakahar 		}
   6504  1.354  knakahar 
   6505  1.417  knakahar #ifdef WM_EVENT_COUNTERS
   6506  1.417  knakahar 		xname = device_xname(sc->sc_dev);
   6507  1.417  knakahar 
   6508  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxintr, rxq, i, xname);
   6509  1.556  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxdefer, rxq, i, xname);
   6510  1.417  knakahar 
   6511  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxipsum, rxq, i, xname);
   6512  1.417  knakahar 		WM_Q_INTR_EVCNT_ATTACH(rxq, rxtusum, rxq, i, xname);
   6513  1.417  knakahar #endif /* WM_EVENT_COUNTERS */
   6514  1.417  knakahar 
   6515  1.364  knakahar 		rx_done++;
   6516  1.364  knakahar 	}
   6517  1.353  knakahar 	if (error)
   6518  1.364  knakahar 		goto fail_2;
   6519  1.353  knakahar 
   6520  1.353  knakahar 	return 0;
   6521  1.353  knakahar 
   6522  1.356  knakahar  fail_2:
   6523  1.364  knakahar 	for (i = 0; i < rx_done; i++) {
   6524  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6525  1.364  knakahar 		wm_free_rx_buffer(sc, rxq);
   6526  1.364  knakahar 		wm_free_rx_descs(sc, rxq);
   6527  1.364  knakahar 		if (rxq->rxq_lock)
   6528  1.364  knakahar 			mutex_obj_free(rxq->rxq_lock);
   6529  1.364  knakahar 	}
   6530  1.356  knakahar  fail_1:
   6531  1.364  knakahar 	for (i = 0; i < tx_done; i++) {
   6532  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6533  1.403  knakahar 		pcq_destroy(txq->txq_interq);
   6534  1.364  knakahar 		wm_free_tx_buffer(sc, txq);
   6535  1.364  knakahar 		wm_free_tx_descs(sc, txq);
   6536  1.364  knakahar 		if (txq->txq_lock)
   6537  1.364  knakahar 			mutex_obj_free(txq->txq_lock);
   6538  1.364  knakahar 	}
   6539  1.405  knakahar 
   6540  1.405  knakahar 	kmem_free(sc->sc_queue,
   6541  1.405  knakahar 	    sizeof(struct wm_queue) * sc->sc_nqueues);
   6542  1.356  knakahar  fail_0:
   6543  1.353  knakahar 	return error;
   6544  1.353  knakahar }
   6545  1.353  knakahar 
   6546  1.353  knakahar /*
   6547  1.353  knakahar  * wm_free_quques:
   6548  1.353  knakahar  *	Free {tx,rx}descs and {tx,rx} buffers
   6549  1.353  knakahar  */
   6550  1.353  knakahar static void
   6551  1.353  knakahar wm_free_txrx_queues(struct wm_softc *sc)
   6552  1.353  knakahar {
   6553  1.364  knakahar 	int i;
   6554  1.362  knakahar 
   6555  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6556  1.405  knakahar 		struct wm_rxqueue *rxq = &sc->sc_queue[i].wmq_rxq;
   6557  1.477  knakahar 
   6558  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   6559  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxintr, rxq, i);
   6560  1.556  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxdefer, rxq, i);
   6561  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxipsum, rxq, i);
   6562  1.477  knakahar 		WM_Q_EVCNT_DETACH(rxq, rxtusum, rxq, i);
   6563  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   6564  1.477  knakahar 
   6565  1.364  knakahar 		wm_free_rx_buffer(sc, rxq);
   6566  1.364  knakahar 		wm_free_rx_descs(sc, rxq);
   6567  1.364  knakahar 		if (rxq->rxq_lock)
   6568  1.364  knakahar 			mutex_obj_free(rxq->rxq_lock);
   6569  1.364  knakahar 	}
   6570  1.364  knakahar 
   6571  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6572  1.405  knakahar 		struct wm_txqueue *txq = &sc->sc_queue[i].wmq_txq;
   6573  1.469  knakahar 		struct mbuf *m;
   6574  1.477  knakahar #ifdef WM_EVENT_COUNTERS
   6575  1.477  knakahar 		int j;
   6576  1.477  knakahar 
   6577  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txsstall, txq, i);
   6578  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdstall, txq, i);
   6579  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txfifo_stall, txq, i);
   6580  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdw, txq, i);
   6581  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txqe, txq, i);
   6582  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txipsum, txq, i);
   6583  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtusum, txq, i);
   6584  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtusum6, txq, i);
   6585  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtso, txq, i);
   6586  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtso6, txq, i);
   6587  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txtsopain, txq, i);
   6588  1.477  knakahar 
   6589  1.477  knakahar 		for (j = 0; j < WM_NTXSEGS; j++)
   6590  1.477  knakahar 			evcnt_detach(&txq->txq_ev_txseg[j]);
   6591  1.477  knakahar 
   6592  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, txdrop, txq, i);
   6593  1.477  knakahar 		WM_Q_EVCNT_DETACH(txq, tu, txq, i);
   6594  1.477  knakahar #endif /* WM_EVENT_COUNTERS */
   6595  1.469  knakahar 
   6596  1.469  knakahar 		/* drain txq_interq */
   6597  1.469  knakahar 		while ((m = pcq_get(txq->txq_interq)) != NULL)
   6598  1.469  knakahar 			m_freem(m);
   6599  1.469  knakahar 		pcq_destroy(txq->txq_interq);
   6600  1.469  knakahar 
   6601  1.364  knakahar 		wm_free_tx_buffer(sc, txq);
   6602  1.364  knakahar 		wm_free_tx_descs(sc, txq);
   6603  1.364  knakahar 		if (txq->txq_lock)
   6604  1.364  knakahar 			mutex_obj_free(txq->txq_lock);
   6605  1.364  knakahar 	}
   6606  1.405  knakahar 
   6607  1.405  knakahar 	kmem_free(sc->sc_queue, sizeof(struct wm_queue) * sc->sc_nqueues);
   6608  1.353  knakahar }
   6609  1.353  knakahar 
   6610  1.355  knakahar static void
   6611  1.362  knakahar wm_init_tx_descs(struct wm_softc *sc __unused, struct wm_txqueue *txq)
   6612  1.355  knakahar {
   6613  1.355  knakahar 
   6614  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6615  1.355  knakahar 
   6616  1.355  knakahar 	/* Initialize the transmit descriptor ring. */
   6617  1.398  knakahar 	memset(txq->txq_descs, 0, WM_TXDESCS_SIZE(txq));
   6618  1.362  knakahar 	wm_cdtxsync(txq, 0, WM_NTXDESC(txq),
   6619  1.388   msaitoh 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   6620  1.356  knakahar 	txq->txq_free = WM_NTXDESC(txq);
   6621  1.356  knakahar 	txq->txq_next = 0;
   6622  1.358  knakahar }
   6623  1.358  knakahar 
   6624  1.358  knakahar static void
   6625  1.405  knakahar wm_init_tx_regs(struct wm_softc *sc, struct wm_queue *wmq,
   6626  1.405  knakahar     struct wm_txqueue *txq)
   6627  1.358  knakahar {
   6628  1.358  knakahar 
   6629  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   6630  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   6631  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6632  1.355  knakahar 
   6633  1.355  knakahar 	if (sc->sc_type < WM_T_82543) {
   6634  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(txq, 0));
   6635  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(txq, 0));
   6636  1.398  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCS_SIZE(txq));
   6637  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
   6638  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
   6639  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
   6640  1.355  knakahar 	} else {
   6641  1.405  knakahar 		int qid = wmq->wmq_id;
   6642  1.364  knakahar 
   6643  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDBAH(qid), WM_CDTXADDR_HI(txq, 0));
   6644  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDBAL(qid), WM_CDTXADDR_LO(txq, 0));
   6645  1.398  knakahar 		CSR_WRITE(sc, WMREG_TDLEN(qid), WM_TXDESCS_SIZE(txq));
   6646  1.364  knakahar 		CSR_WRITE(sc, WMREG_TDH(qid), 0);
   6647  1.355  knakahar 
   6648  1.355  knakahar 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   6649  1.355  knakahar 			/*
   6650  1.355  knakahar 			 * Don't write TDT before TCTL.EN is set.
   6651  1.355  knakahar 			 * See the document.
   6652  1.355  knakahar 			 */
   6653  1.364  knakahar 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_QUEUE_ENABLE
   6654  1.355  knakahar 			    | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0)
   6655  1.355  knakahar 			    | TXDCTL_WTHRESH(0));
   6656  1.355  knakahar 		else {
   6657  1.490  knakahar 			/* XXX should update with AIM? */
   6658  1.490  knakahar 			CSR_WRITE(sc, WMREG_TIDV, wmq->wmq_itr / 4);
   6659  1.355  knakahar 			if (sc->sc_type >= WM_T_82540) {
   6660  1.355  knakahar 				/* should be same */
   6661  1.490  knakahar 				CSR_WRITE(sc, WMREG_TADV, wmq->wmq_itr / 4);
   6662  1.355  knakahar 			}
   6663  1.355  knakahar 
   6664  1.364  knakahar 			CSR_WRITE(sc, WMREG_TDT(qid), 0);
   6665  1.364  knakahar 			CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_PTHRESH(0) |
   6666  1.355  knakahar 			    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
   6667  1.355  knakahar 		}
   6668  1.355  knakahar 	}
   6669  1.355  knakahar }
   6670  1.355  knakahar 
   6671  1.355  knakahar static void
   6672  1.362  knakahar wm_init_tx_buffer(struct wm_softc *sc __unused, struct wm_txqueue *txq)
   6673  1.355  knakahar {
   6674  1.355  knakahar 	int i;
   6675  1.355  knakahar 
   6676  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6677  1.355  knakahar 
   6678  1.355  knakahar 	/* Initialize the transmit job descriptors. */
   6679  1.356  knakahar 	for (i = 0; i < WM_TXQUEUELEN(txq); i++)
   6680  1.356  knakahar 		txq->txq_soft[i].txs_mbuf = NULL;
   6681  1.356  knakahar 	txq->txq_sfree = WM_TXQUEUELEN(txq);
   6682  1.356  knakahar 	txq->txq_snext = 0;
   6683  1.356  knakahar 	txq->txq_sdirty = 0;
   6684  1.355  knakahar }
   6685  1.355  knakahar 
   6686  1.355  knakahar static void
   6687  1.405  knakahar wm_init_tx_queue(struct wm_softc *sc, struct wm_queue *wmq,
   6688  1.405  knakahar     struct wm_txqueue *txq)
   6689  1.355  knakahar {
   6690  1.355  knakahar 
   6691  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   6692  1.355  knakahar 
   6693  1.355  knakahar 	/*
   6694  1.355  knakahar 	 * Set up some register offsets that are different between
   6695  1.355  knakahar 	 * the i82542 and the i82543 and later chips.
   6696  1.355  knakahar 	 */
   6697  1.388   msaitoh 	if (sc->sc_type < WM_T_82543)
   6698  1.356  knakahar 		txq->txq_tdt_reg = WMREG_OLD_TDT;
   6699  1.388   msaitoh 	else
   6700  1.405  knakahar 		txq->txq_tdt_reg = WMREG_TDT(wmq->wmq_id);
   6701  1.355  knakahar 
   6702  1.362  knakahar 	wm_init_tx_descs(sc, txq);
   6703  1.405  knakahar 	wm_init_tx_regs(sc, wmq, txq);
   6704  1.362  knakahar 	wm_init_tx_buffer(sc, txq);
   6705  1.562  knakahar 
   6706  1.576   msaitoh 	txq->txq_sending = false;
   6707  1.355  knakahar }
   6708  1.355  knakahar 
   6709  1.355  knakahar static void
   6710  1.405  knakahar wm_init_rx_regs(struct wm_softc *sc, struct wm_queue *wmq,
   6711  1.405  knakahar     struct wm_rxqueue *rxq)
   6712  1.355  knakahar {
   6713  1.355  knakahar 
   6714  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6715  1.355  knakahar 
   6716  1.355  knakahar 	/*
   6717  1.355  knakahar 	 * Initialize the receive descriptor and receive job
   6718  1.355  knakahar 	 * descriptor rings.
   6719  1.355  knakahar 	 */
   6720  1.355  knakahar 	if (sc->sc_type < WM_T_82543) {
   6721  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(rxq, 0));
   6722  1.356  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(rxq, 0));
   6723  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDLEN0,
   6724  1.466  knakahar 		    rxq->rxq_descsize * rxq->rxq_ndesc);
   6725  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
   6726  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
   6727  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
   6728  1.355  knakahar 
   6729  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
   6730  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
   6731  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
   6732  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
   6733  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
   6734  1.355  knakahar 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
   6735  1.355  knakahar 	} else {
   6736  1.405  knakahar 		int qid = wmq->wmq_id;
   6737  1.364  knakahar 
   6738  1.364  knakahar 		CSR_WRITE(sc, WMREG_RDBAH(qid), WM_CDRXADDR_HI(rxq, 0));
   6739  1.364  knakahar 		CSR_WRITE(sc, WMREG_RDBAL(qid), WM_CDRXADDR_LO(rxq, 0));
   6740  1.573   msaitoh 		CSR_WRITE(sc, WMREG_RDLEN(qid),
   6741  1.573   msaitoh 		    rxq->rxq_descsize * rxq->rxq_ndesc);
   6742  1.355  knakahar 
   6743  1.355  knakahar 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   6744  1.355  knakahar 			if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
   6745  1.478  knakahar 				panic("%s: MCLBYTES %d unsupported for 82575 or higher\n", __func__, MCLBYTES);
   6746  1.466  knakahar 
   6747  1.466  knakahar 			/* Currently, support SRRCTL_DESCTYPE_ADV_ONEBUF only. */
   6748  1.466  knakahar 			CSR_WRITE(sc, WMREG_SRRCTL(qid), SRRCTL_DESCTYPE_ADV_ONEBUF
   6749  1.355  knakahar 			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
   6750  1.364  knakahar 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_QUEUE_ENABLE
   6751  1.355  knakahar 			    | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
   6752  1.355  knakahar 			    | RXDCTL_WTHRESH(1));
   6753  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
   6754  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
   6755  1.355  knakahar 		} else {
   6756  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDH(qid), 0);
   6757  1.364  knakahar 			CSR_WRITE(sc, WMREG_RDT(qid), 0);
   6758  1.490  knakahar 			/* XXX should update with AIM? */
   6759  1.573   msaitoh 			CSR_WRITE(sc, WMREG_RDTR,
   6760  1.573   msaitoh 			    (wmq->wmq_itr / 4) | RDTR_FPD);
   6761  1.368  knakahar 			/* MUST be same */
   6762  1.490  knakahar 			CSR_WRITE(sc, WMREG_RADV, wmq->wmq_itr / 4);
   6763  1.364  knakahar 			CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_PTHRESH(0) |
   6764  1.358  knakahar 			    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
   6765  1.355  knakahar 		}
   6766  1.355  knakahar 	}
   6767  1.355  knakahar }
   6768  1.355  knakahar 
   6769  1.355  knakahar static int
   6770  1.362  knakahar wm_init_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq)
   6771  1.355  knakahar {
   6772  1.355  knakahar 	struct wm_rxsoft *rxs;
   6773  1.355  knakahar 	int error, i;
   6774  1.355  knakahar 
   6775  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6776  1.355  knakahar 
   6777  1.466  knakahar 	for (i = 0; i < rxq->rxq_ndesc; i++) {
   6778  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   6779  1.355  knakahar 		if (rxs->rxs_mbuf == NULL) {
   6780  1.362  knakahar 			if ((error = wm_add_rxbuf(rxq, i)) != 0) {
   6781  1.355  knakahar 				log(LOG_ERR, "%s: unable to allocate or map "
   6782  1.355  knakahar 				    "rx buffer %d, error = %d\n",
   6783  1.355  knakahar 				    device_xname(sc->sc_dev), i, error);
   6784  1.355  knakahar 				/*
   6785  1.355  knakahar 				 * XXX Should attempt to run with fewer receive
   6786  1.355  knakahar 				 * XXX buffers instead of just failing.
   6787  1.355  knakahar 				 */
   6788  1.362  knakahar 				wm_rxdrain(rxq);
   6789  1.355  knakahar 				return ENOMEM;
   6790  1.355  knakahar 			}
   6791  1.355  knakahar 		} else {
   6792  1.355  knakahar 			/*
   6793  1.548   msaitoh 			 * For 82575 and 82576, the RX descriptors must be
   6794  1.548   msaitoh 			 * initialized after the setting of RCTL.EN in
   6795  1.355  knakahar 			 * wm_set_filter()
   6796  1.355  knakahar 			 */
   6797  1.548   msaitoh 			if ((sc->sc_flags & WM_F_NEWQUEUE) == 0)
   6798  1.548   msaitoh 				wm_init_rxdesc(rxq, i);
   6799  1.355  knakahar 		}
   6800  1.355  knakahar 	}
   6801  1.356  knakahar 	rxq->rxq_ptr = 0;
   6802  1.356  knakahar 	rxq->rxq_discard = 0;
   6803  1.356  knakahar 	WM_RXCHAIN_RESET(rxq);
   6804  1.355  knakahar 
   6805  1.355  knakahar 	return 0;
   6806  1.355  knakahar }
   6807  1.355  knakahar 
   6808  1.355  knakahar static int
   6809  1.405  knakahar wm_init_rx_queue(struct wm_softc *sc, struct wm_queue *wmq,
   6810  1.405  knakahar     struct wm_rxqueue *rxq)
   6811  1.355  knakahar {
   6812  1.355  knakahar 
   6813  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   6814  1.355  knakahar 
   6815  1.355  knakahar 	/*
   6816  1.355  knakahar 	 * Set up some register offsets that are different between
   6817  1.355  knakahar 	 * the i82542 and the i82543 and later chips.
   6818  1.355  knakahar 	 */
   6819  1.388   msaitoh 	if (sc->sc_type < WM_T_82543)
   6820  1.356  knakahar 		rxq->rxq_rdt_reg = WMREG_OLD_RDT0;
   6821  1.388   msaitoh 	else
   6822  1.405  knakahar 		rxq->rxq_rdt_reg = WMREG_RDT(wmq->wmq_id);
   6823  1.355  knakahar 
   6824  1.405  knakahar 	wm_init_rx_regs(sc, wmq, rxq);
   6825  1.362  knakahar 	return wm_init_rx_buffer(sc, rxq);
   6826  1.355  knakahar }
   6827  1.355  knakahar 
   6828  1.355  knakahar /*
   6829  1.355  knakahar  * wm_init_quques:
   6830  1.355  knakahar  *	Initialize {tx,rx}descs and {tx,rx} buffers
   6831  1.355  knakahar  */
   6832  1.355  knakahar static int
   6833  1.355  knakahar wm_init_txrx_queues(struct wm_softc *sc)
   6834  1.355  knakahar {
   6835  1.406  knakahar 	int i, error = 0;
   6836  1.355  knakahar 
   6837  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   6838  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   6839  1.420   msaitoh 
   6840  1.405  knakahar 	for (i = 0; i < sc->sc_nqueues; i++) {
   6841  1.405  knakahar 		struct wm_queue *wmq = &sc->sc_queue[i];
   6842  1.405  knakahar 		struct wm_txqueue *txq = &wmq->wmq_txq;
   6843  1.405  knakahar 		struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   6844  1.405  knakahar 
   6845  1.495  knakahar 		/*
   6846  1.495  knakahar 		 * TODO
   6847  1.495  knakahar 		 * Currently, use constant variable instead of AIM.
   6848  1.495  knakahar 		 * Furthermore, the interrupt interval of multiqueue which use
   6849  1.495  knakahar 		 * polling mode is less than default value.
   6850  1.495  knakahar 		 * More tuning and AIM are required.
   6851  1.495  knakahar 		 */
   6852  1.502  knakahar 		if (wm_is_using_multiqueue(sc))
   6853  1.495  knakahar 			wmq->wmq_itr = 50;
   6854  1.495  knakahar 		else
   6855  1.495  knakahar 			wmq->wmq_itr = sc->sc_itr_init;
   6856  1.495  knakahar 		wmq->wmq_set_itr = true;
   6857  1.490  knakahar 
   6858  1.413     skrll 		mutex_enter(txq->txq_lock);
   6859  1.405  knakahar 		wm_init_tx_queue(sc, wmq, txq);
   6860  1.413     skrll 		mutex_exit(txq->txq_lock);
   6861  1.355  knakahar 
   6862  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   6863  1.405  knakahar 		error = wm_init_rx_queue(sc, wmq, rxq);
   6864  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   6865  1.364  knakahar 		if (error)
   6866  1.364  knakahar 			break;
   6867  1.364  knakahar 	}
   6868  1.355  knakahar 
   6869  1.355  knakahar 	return error;
   6870  1.355  knakahar }
   6871  1.355  knakahar 
   6872    1.1   thorpej /*
   6873  1.371   msaitoh  * wm_tx_offload:
   6874  1.371   msaitoh  *
   6875  1.371   msaitoh  *	Set up TCP/IP checksumming parameters for the
   6876  1.371   msaitoh  *	specified packet.
   6877  1.371   msaitoh  */
   6878  1.371   msaitoh static int
   6879  1.498  knakahar wm_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
   6880  1.498  knakahar     struct wm_txsoft *txs, uint32_t *cmdp, uint8_t *fieldsp)
   6881  1.371   msaitoh {
   6882  1.371   msaitoh 	struct mbuf *m0 = txs->txs_mbuf;
   6883  1.371   msaitoh 	struct livengood_tcpip_ctxdesc *t;
   6884  1.371   msaitoh 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
   6885  1.371   msaitoh 	uint32_t ipcse;
   6886  1.371   msaitoh 	struct ether_header *eh;
   6887  1.371   msaitoh 	int offset, iphl;
   6888  1.371   msaitoh 	uint8_t fields;
   6889  1.371   msaitoh 
   6890  1.371   msaitoh 	/*
   6891  1.371   msaitoh 	 * XXX It would be nice if the mbuf pkthdr had offset
   6892  1.371   msaitoh 	 * fields for the protocol headers.
   6893  1.371   msaitoh 	 */
   6894  1.371   msaitoh 
   6895  1.371   msaitoh 	eh = mtod(m0, struct ether_header *);
   6896  1.371   msaitoh 	switch (htons(eh->ether_type)) {
   6897  1.371   msaitoh 	case ETHERTYPE_IP:
   6898  1.371   msaitoh 	case ETHERTYPE_IPV6:
   6899  1.371   msaitoh 		offset = ETHER_HDR_LEN;
   6900  1.371   msaitoh 		break;
   6901  1.371   msaitoh 
   6902  1.371   msaitoh 	case ETHERTYPE_VLAN:
   6903  1.371   msaitoh 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   6904  1.371   msaitoh 		break;
   6905  1.371   msaitoh 
   6906  1.371   msaitoh 	default:
   6907  1.371   msaitoh 		/*
   6908  1.371   msaitoh 		 * Don't support this protocol or encapsulation.
   6909  1.371   msaitoh 		 */
   6910  1.371   msaitoh 		*fieldsp = 0;
   6911  1.371   msaitoh 		*cmdp = 0;
   6912  1.371   msaitoh 		return 0;
   6913  1.371   msaitoh 	}
   6914  1.371   msaitoh 
   6915  1.371   msaitoh 	if ((m0->m_pkthdr.csum_flags &
   6916  1.499  knakahar 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
   6917  1.371   msaitoh 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   6918  1.371   msaitoh 	} else {
   6919  1.371   msaitoh 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
   6920  1.371   msaitoh 	}
   6921  1.371   msaitoh 	ipcse = offset + iphl - 1;
   6922  1.371   msaitoh 
   6923  1.371   msaitoh 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
   6924  1.371   msaitoh 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
   6925  1.371   msaitoh 	seg = 0;
   6926  1.371   msaitoh 	fields = 0;
   6927  1.371   msaitoh 
   6928  1.371   msaitoh 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
   6929  1.371   msaitoh 		int hlen = offset + iphl;
   6930  1.371   msaitoh 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   6931  1.371   msaitoh 
   6932  1.371   msaitoh 		if (__predict_false(m0->m_len <
   6933  1.371   msaitoh 				    (hlen + sizeof(struct tcphdr)))) {
   6934  1.371   msaitoh 			/*
   6935  1.371   msaitoh 			 * TCP/IP headers are not in the first mbuf; we need
   6936  1.371   msaitoh 			 * to do this the slow and painful way.  Let's just
   6937  1.371   msaitoh 			 * hope this doesn't happen very often.
   6938  1.371   msaitoh 			 */
   6939  1.371   msaitoh 			struct tcphdr th;
   6940  1.371   msaitoh 
   6941  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtsopain);
   6942  1.371   msaitoh 
   6943  1.371   msaitoh 			m_copydata(m0, hlen, sizeof(th), &th);
   6944  1.371   msaitoh 			if (v4) {
   6945  1.371   msaitoh 				struct ip ip;
   6946  1.371   msaitoh 
   6947  1.371   msaitoh 				m_copydata(m0, offset, sizeof(ip), &ip);
   6948  1.371   msaitoh 				ip.ip_len = 0;
   6949  1.371   msaitoh 				m_copyback(m0,
   6950  1.371   msaitoh 				    offset + offsetof(struct ip, ip_len),
   6951  1.371   msaitoh 				    sizeof(ip.ip_len), &ip.ip_len);
   6952  1.371   msaitoh 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   6953  1.371   msaitoh 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   6954  1.371   msaitoh 			} else {
   6955  1.371   msaitoh 				struct ip6_hdr ip6;
   6956  1.371   msaitoh 
   6957  1.371   msaitoh 				m_copydata(m0, offset, sizeof(ip6), &ip6);
   6958  1.371   msaitoh 				ip6.ip6_plen = 0;
   6959  1.371   msaitoh 				m_copyback(m0,
   6960  1.371   msaitoh 				    offset + offsetof(struct ip6_hdr, ip6_plen),
   6961  1.371   msaitoh 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
   6962  1.371   msaitoh 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
   6963  1.371   msaitoh 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
   6964  1.371   msaitoh 			}
   6965  1.371   msaitoh 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   6966  1.371   msaitoh 			    sizeof(th.th_sum), &th.th_sum);
   6967  1.371   msaitoh 
   6968  1.371   msaitoh 			hlen += th.th_off << 2;
   6969  1.371   msaitoh 		} else {
   6970  1.371   msaitoh 			/*
   6971  1.371   msaitoh 			 * TCP/IP headers are in the first mbuf; we can do
   6972  1.371   msaitoh 			 * this the easy way.
   6973  1.371   msaitoh 			 */
   6974  1.371   msaitoh 			struct tcphdr *th;
   6975  1.371   msaitoh 
   6976  1.371   msaitoh 			if (v4) {
   6977  1.371   msaitoh 				struct ip *ip =
   6978  1.371   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   6979  1.371   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   6980  1.371   msaitoh 
   6981  1.371   msaitoh 				ip->ip_len = 0;
   6982  1.371   msaitoh 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   6983  1.371   msaitoh 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   6984  1.371   msaitoh 			} else {
   6985  1.371   msaitoh 				struct ip6_hdr *ip6 =
   6986  1.371   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   6987  1.371   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   6988  1.371   msaitoh 
   6989  1.371   msaitoh 				ip6->ip6_plen = 0;
   6990  1.371   msaitoh 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
   6991  1.371   msaitoh 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
   6992  1.371   msaitoh 			}
   6993  1.371   msaitoh 			hlen += th->th_off << 2;
   6994  1.371   msaitoh 		}
   6995  1.371   msaitoh 
   6996  1.371   msaitoh 		if (v4) {
   6997  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso);
   6998  1.371   msaitoh 			cmdlen |= WTX_TCPIP_CMD_IP;
   6999  1.371   msaitoh 		} else {
   7000  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso6);
   7001  1.371   msaitoh 			ipcse = 0;
   7002  1.371   msaitoh 		}
   7003  1.371   msaitoh 		cmd |= WTX_TCPIP_CMD_TSE;
   7004  1.371   msaitoh 		cmdlen |= WTX_TCPIP_CMD_TSE |
   7005  1.371   msaitoh 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
   7006  1.371   msaitoh 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
   7007  1.371   msaitoh 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
   7008  1.371   msaitoh 	}
   7009  1.371   msaitoh 
   7010  1.371   msaitoh 	/*
   7011  1.371   msaitoh 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
   7012  1.371   msaitoh 	 * offload feature, if we load the context descriptor, we
   7013  1.371   msaitoh 	 * MUST provide valid values for IPCSS and TUCSS fields.
   7014  1.371   msaitoh 	 */
   7015  1.371   msaitoh 
   7016  1.371   msaitoh 	ipcs = WTX_TCPIP_IPCSS(offset) |
   7017  1.371   msaitoh 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
   7018  1.371   msaitoh 	    WTX_TCPIP_IPCSE(ipcse);
   7019  1.388   msaitoh 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4 | M_CSUM_TSOv4)) {
   7020  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txipsum);
   7021  1.371   msaitoh 		fields |= WTX_IXSM;
   7022  1.371   msaitoh 	}
   7023  1.371   msaitoh 
   7024  1.371   msaitoh 	offset += iphl;
   7025  1.371   msaitoh 
   7026  1.371   msaitoh 	if (m0->m_pkthdr.csum_flags &
   7027  1.388   msaitoh 	    (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TSOv4)) {
   7028  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum);
   7029  1.371   msaitoh 		fields |= WTX_TXSM;
   7030  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   7031  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset +
   7032  1.371   msaitoh 		    M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
   7033  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   7034  1.371   msaitoh 	} else if ((m0->m_pkthdr.csum_flags &
   7035  1.388   msaitoh 	    (M_CSUM_TCPv6 | M_CSUM_UDPv6 | M_CSUM_TSOv6)) != 0) {
   7036  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum6);
   7037  1.371   msaitoh 		fields |= WTX_TXSM;
   7038  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   7039  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset +
   7040  1.371   msaitoh 		    M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
   7041  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   7042  1.371   msaitoh 	} else {
   7043  1.371   msaitoh 		/* Just initialize it to a valid TCP context. */
   7044  1.371   msaitoh 		tucs = WTX_TCPIP_TUCSS(offset) |
   7045  1.371   msaitoh 		    WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
   7046  1.371   msaitoh 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   7047  1.371   msaitoh 	}
   7048  1.371   msaitoh 
   7049  1.500  knakahar 	/*
   7050  1.500  knakahar 	 * We don't have to write context descriptor for every packet
   7051  1.500  knakahar 	 * except for 82574. For 82574, we must write context descriptor
   7052  1.500  knakahar 	 * for every packet when we use two descriptor queues.
   7053  1.500  knakahar 	 * It would be overhead to write context descriptor for every packet,
   7054  1.500  knakahar 	 * however it does not cause problems.
   7055  1.500  knakahar 	 */
   7056  1.371   msaitoh 	/* Fill in the context descriptor. */
   7057  1.371   msaitoh 	t = (struct livengood_tcpip_ctxdesc *)
   7058  1.371   msaitoh 	    &txq->txq_descs[txq->txq_next];
   7059  1.371   msaitoh 	t->tcpip_ipcs = htole32(ipcs);
   7060  1.371   msaitoh 	t->tcpip_tucs = htole32(tucs);
   7061  1.371   msaitoh 	t->tcpip_cmdlen = htole32(cmdlen);
   7062  1.371   msaitoh 	t->tcpip_seg = htole32(seg);
   7063  1.371   msaitoh 	wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE);
   7064  1.371   msaitoh 
   7065  1.371   msaitoh 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   7066  1.371   msaitoh 	txs->txs_ndesc++;
   7067  1.371   msaitoh 
   7068  1.371   msaitoh 	*cmdp = cmd;
   7069  1.371   msaitoh 	*fieldsp = fields;
   7070  1.371   msaitoh 
   7071  1.371   msaitoh 	return 0;
   7072  1.371   msaitoh }
   7073  1.371   msaitoh 
   7074  1.454  knakahar static inline int
   7075  1.454  knakahar wm_select_txqueue(struct ifnet *ifp, struct mbuf *m)
   7076  1.454  knakahar {
   7077  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7078  1.454  knakahar 	u_int cpuid = cpu_index(curcpu());
   7079  1.454  knakahar 
   7080  1.454  knakahar 	/*
   7081  1.454  knakahar 	 * Currently, simple distribute strategy.
   7082  1.454  knakahar 	 * TODO:
   7083  1.461  knakahar 	 * distribute by flowid(RSS has value).
   7084  1.454  knakahar 	 */
   7085  1.573   msaitoh         return (cpuid + ncpu - sc->sc_affinity_offset) % sc->sc_nqueues;
   7086  1.454  knakahar }
   7087  1.454  knakahar 
   7088  1.371   msaitoh /*
   7089  1.281   msaitoh  * wm_start:		[ifnet interface function]
   7090    1.1   thorpej  *
   7091  1.281   msaitoh  *	Start packet transmission on the interface.
   7092    1.1   thorpej  */
   7093   1.47   thorpej static void
   7094  1.281   msaitoh wm_start(struct ifnet *ifp)
   7095    1.1   thorpej {
   7096  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   7097  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7098  1.281   msaitoh 
   7099  1.496  knakahar #ifdef WM_MPSAFE
   7100  1.543     ozaki 	KASSERT(if_is_mpsafe(ifp));
   7101  1.496  knakahar #endif
   7102  1.455  knakahar 	/*
   7103  1.455  knakahar 	 * ifp->if_obytes and ifp->if_omcasts are added in if_transmit()@if.c.
   7104  1.455  knakahar 	 */
   7105  1.455  knakahar 
   7106  1.413     skrll 	mutex_enter(txq->txq_lock);
   7107  1.429  knakahar 	if (!txq->txq_stopping)
   7108  1.281   msaitoh 		wm_start_locked(ifp);
   7109  1.413     skrll 	mutex_exit(txq->txq_lock);
   7110  1.281   msaitoh }
   7111    1.1   thorpej 
   7112  1.281   msaitoh static void
   7113  1.281   msaitoh wm_start_locked(struct ifnet *ifp)
   7114  1.281   msaitoh {
   7115  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   7116  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7117  1.454  knakahar 
   7118  1.454  knakahar 	wm_send_common_locked(ifp, txq, false);
   7119  1.454  knakahar }
   7120  1.454  knakahar 
   7121  1.454  knakahar static int
   7122  1.454  knakahar wm_transmit(struct ifnet *ifp, struct mbuf *m)
   7123  1.454  knakahar {
   7124  1.454  knakahar 	int qid;
   7125  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7126  1.454  knakahar 	struct wm_txqueue *txq;
   7127  1.454  knakahar 
   7128  1.454  knakahar 	qid = wm_select_txqueue(ifp, m);
   7129  1.454  knakahar 	txq = &sc->sc_queue[qid].wmq_txq;
   7130  1.454  knakahar 
   7131  1.454  knakahar 	if (__predict_false(!pcq_put(txq->txq_interq, m))) {
   7132  1.454  knakahar 		m_freem(m);
   7133  1.454  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7134  1.454  knakahar 		return ENOBUFS;
   7135  1.454  knakahar 	}
   7136  1.454  knakahar 
   7137  1.455  knakahar 	/*
   7138  1.455  knakahar 	 * XXXX NOMPSAFE: ifp->if_data should be percpu.
   7139  1.455  knakahar 	 */
   7140  1.455  knakahar 	ifp->if_obytes += m->m_pkthdr.len;
   7141  1.455  knakahar 	if (m->m_flags & M_MCAST)
   7142  1.455  knakahar 		ifp->if_omcasts++;
   7143  1.455  knakahar 
   7144  1.454  knakahar 	if (mutex_tryenter(txq->txq_lock)) {
   7145  1.454  knakahar 		if (!txq->txq_stopping)
   7146  1.454  knakahar 			wm_transmit_locked(ifp, txq);
   7147  1.454  knakahar 		mutex_exit(txq->txq_lock);
   7148  1.454  knakahar 	}
   7149  1.454  knakahar 
   7150  1.454  knakahar 	return 0;
   7151  1.454  knakahar }
   7152  1.454  knakahar 
   7153  1.454  knakahar static void
   7154  1.454  knakahar wm_transmit_locked(struct ifnet *ifp, struct wm_txqueue *txq)
   7155  1.454  knakahar {
   7156  1.454  knakahar 
   7157  1.454  knakahar 	wm_send_common_locked(ifp, txq, true);
   7158  1.454  knakahar }
   7159  1.454  knakahar 
   7160  1.454  knakahar static void
   7161  1.454  knakahar wm_send_common_locked(struct ifnet *ifp, struct wm_txqueue *txq,
   7162  1.454  knakahar     bool is_transmit)
   7163  1.454  knakahar {
   7164  1.454  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7165  1.281   msaitoh 	struct mbuf *m0;
   7166  1.281   msaitoh 	struct wm_txsoft *txs;
   7167  1.281   msaitoh 	bus_dmamap_t dmamap;
   7168  1.281   msaitoh 	int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
   7169  1.281   msaitoh 	bus_addr_t curaddr;
   7170  1.281   msaitoh 	bus_size_t seglen, curlen;
   7171  1.281   msaitoh 	uint32_t cksumcmd;
   7172  1.281   msaitoh 	uint8_t cksumfields;
   7173    1.1   thorpej 
   7174  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   7175    1.1   thorpej 
   7176  1.482  knakahar 	if ((ifp->if_flags & IFF_RUNNING) == 0)
   7177  1.482  knakahar 		return;
   7178  1.482  knakahar 	if ((ifp->if_flags & IFF_OACTIVE) != 0 && !is_transmit)
   7179  1.281   msaitoh 		return;
   7180  1.479  knakahar 	if ((txq->txq_flags & WM_TXQ_NO_SPACE) != 0)
   7181  1.479  knakahar 		return;
   7182    1.1   thorpej 
   7183  1.281   msaitoh 	/* Remember the previous number of free descriptors. */
   7184  1.356  knakahar 	ofree = txq->txq_free;
   7185    1.1   thorpej 
   7186  1.281   msaitoh 	/*
   7187  1.281   msaitoh 	 * Loop through the send queue, setting up transmit descriptors
   7188  1.281   msaitoh 	 * until we drain the queue, or use up all available transmit
   7189  1.281   msaitoh 	 * descriptors.
   7190  1.281   msaitoh 	 */
   7191  1.281   msaitoh 	for (;;) {
   7192  1.281   msaitoh 		m0 = NULL;
   7193    1.1   thorpej 
   7194  1.281   msaitoh 		/* Get a work queue entry. */
   7195  1.356  knakahar 		if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) {
   7196  1.557  knakahar 			wm_txeof(txq, UINT_MAX);
   7197  1.356  knakahar 			if (txq->txq_sfree == 0) {
   7198  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   7199  1.281   msaitoh 				    ("%s: TX: no free job descriptors\n",
   7200  1.281   msaitoh 					device_xname(sc->sc_dev)));
   7201  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txsstall);
   7202  1.281   msaitoh 				break;
   7203    1.1   thorpej 			}
   7204    1.1   thorpej 		}
   7205    1.1   thorpej 
   7206  1.281   msaitoh 		/* Grab a packet off the queue. */
   7207  1.454  knakahar 		if (is_transmit)
   7208  1.454  knakahar 			m0 = pcq_get(txq->txq_interq);
   7209  1.454  knakahar 		else
   7210  1.454  knakahar 			IFQ_DEQUEUE(&ifp->if_snd, m0);
   7211  1.281   msaitoh 		if (m0 == NULL)
   7212  1.281   msaitoh 			break;
   7213  1.281   msaitoh 
   7214  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7215  1.281   msaitoh 		    ("%s: TX: have packet to transmit: %p\n",
   7216  1.281   msaitoh 		    device_xname(sc->sc_dev), m0));
   7217  1.281   msaitoh 
   7218  1.356  knakahar 		txs = &txq->txq_soft[txq->txq_snext];
   7219  1.281   msaitoh 		dmamap = txs->txs_dmamap;
   7220    1.1   thorpej 
   7221  1.281   msaitoh 		use_tso = (m0->m_pkthdr.csum_flags &
   7222  1.281   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0;
   7223    1.1   thorpej 
   7224    1.1   thorpej 		/*
   7225  1.281   msaitoh 		 * So says the Linux driver:
   7226  1.281   msaitoh 		 * The controller does a simple calculation to make sure
   7227  1.281   msaitoh 		 * there is enough room in the FIFO before initiating the
   7228  1.281   msaitoh 		 * DMA for each buffer.  The calc is:
   7229  1.281   msaitoh 		 *	4 = ceil(buffer len / MSS)
   7230  1.281   msaitoh 		 * To make sure we don't overrun the FIFO, adjust the max
   7231  1.281   msaitoh 		 * buffer len if the MSS drops.
   7232  1.281   msaitoh 		 */
   7233  1.281   msaitoh 		dmamap->dm_maxsegsz =
   7234  1.281   msaitoh 		    (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
   7235  1.281   msaitoh 		    ? m0->m_pkthdr.segsz << 2
   7236  1.281   msaitoh 		    : WTX_MAX_LEN;
   7237  1.281   msaitoh 
   7238  1.281   msaitoh 		/*
   7239  1.281   msaitoh 		 * Load the DMA map.  If this fails, the packet either
   7240  1.281   msaitoh 		 * didn't fit in the allotted number of segments, or we
   7241  1.281   msaitoh 		 * were short on resources.  For the too-many-segments
   7242  1.281   msaitoh 		 * case, we simply report an error and drop the packet,
   7243  1.281   msaitoh 		 * since we can't sanely copy a jumbo packet to a single
   7244  1.281   msaitoh 		 * buffer.
   7245    1.1   thorpej 		 */
   7246  1.281   msaitoh 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   7247  1.388   msaitoh 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
   7248  1.281   msaitoh 		if (error) {
   7249  1.281   msaitoh 			if (error == EFBIG) {
   7250  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txdrop);
   7251  1.281   msaitoh 				log(LOG_ERR, "%s: Tx packet consumes too many "
   7252  1.281   msaitoh 				    "DMA segments, dropping...\n",
   7253  1.281   msaitoh 				    device_xname(sc->sc_dev));
   7254  1.281   msaitoh 				wm_dump_mbuf_chain(sc, m0);
   7255  1.281   msaitoh 				m_freem(m0);
   7256  1.281   msaitoh 				continue;
   7257  1.281   msaitoh 			}
   7258  1.281   msaitoh 			/*  Short on resources, just stop for now. */
   7259  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7260  1.281   msaitoh 			    ("%s: TX: dmamap load failed: %d\n",
   7261  1.281   msaitoh 			    device_xname(sc->sc_dev), error));
   7262  1.281   msaitoh 			break;
   7263    1.1   thorpej 		}
   7264    1.1   thorpej 
   7265  1.281   msaitoh 		segs_needed = dmamap->dm_nsegs;
   7266  1.281   msaitoh 		if (use_tso) {
   7267  1.281   msaitoh 			/* For sentinel descriptor; see below. */
   7268  1.281   msaitoh 			segs_needed++;
   7269  1.281   msaitoh 		}
   7270    1.1   thorpej 
   7271    1.1   thorpej 		/*
   7272  1.281   msaitoh 		 * Ensure we have enough descriptors free to describe
   7273  1.281   msaitoh 		 * the packet.  Note, we always reserve one descriptor
   7274  1.281   msaitoh 		 * at the end of the ring due to the semantics of the
   7275  1.281   msaitoh 		 * TDT register, plus one more in the event we need
   7276  1.281   msaitoh 		 * to load offload context.
   7277    1.1   thorpej 		 */
   7278  1.356  knakahar 		if (segs_needed > txq->txq_free - 2) {
   7279  1.281   msaitoh 			/*
   7280  1.281   msaitoh 			 * Not enough free descriptors to transmit this
   7281  1.281   msaitoh 			 * packet.  We haven't committed anything yet,
   7282  1.281   msaitoh 			 * so just unload the DMA map, put the packet
   7283  1.281   msaitoh 			 * pack on the queue, and punt.  Notify the upper
   7284  1.281   msaitoh 			 * layer that there are no more slots left.
   7285  1.281   msaitoh 			 */
   7286  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7287  1.281   msaitoh 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
   7288  1.281   msaitoh 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
   7289  1.366  knakahar 			    segs_needed, txq->txq_free - 1));
   7290  1.482  knakahar 			if (!is_transmit)
   7291  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   7292  1.479  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   7293  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   7294  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdstall);
   7295  1.281   msaitoh 			break;
   7296    1.1   thorpej 		}
   7297    1.1   thorpej 
   7298    1.1   thorpej 		/*
   7299  1.281   msaitoh 		 * Check for 82547 Tx FIFO bug.  We need to do this
   7300  1.281   msaitoh 		 * once we know we can transmit the packet, since we
   7301  1.281   msaitoh 		 * do some internal FIFO space accounting here.
   7302    1.1   thorpej 		 */
   7303  1.281   msaitoh 		if (sc->sc_type == WM_T_82547 &&
   7304  1.281   msaitoh 		    wm_82547_txfifo_bugchk(sc, m0)) {
   7305  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7306  1.281   msaitoh 			    ("%s: TX: 82547 Tx FIFO bug detected\n",
   7307  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   7308  1.482  knakahar 			if (!is_transmit)
   7309  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   7310  1.479  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   7311  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   7312  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txfifo_stall);
   7313  1.281   msaitoh 			break;
   7314  1.281   msaitoh 		}
   7315   1.93   thorpej 
   7316  1.281   msaitoh 		/* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
   7317    1.1   thorpej 
   7318  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7319  1.281   msaitoh 		    ("%s: TX: packet has %d (%d) DMA segments\n",
   7320  1.281   msaitoh 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
   7321    1.1   thorpej 
   7322  1.417  knakahar 		WM_EVCNT_INCR(&txq->txq_ev_txseg[dmamap->dm_nsegs - 1]);
   7323    1.1   thorpej 
   7324    1.1   thorpej 		/*
   7325  1.281   msaitoh 		 * Store a pointer to the packet so that we can free it
   7326  1.281   msaitoh 		 * later.
   7327  1.281   msaitoh 		 *
   7328  1.281   msaitoh 		 * Initially, we consider the number of descriptors the
   7329  1.281   msaitoh 		 * packet uses the number of DMA segments.  This may be
   7330  1.281   msaitoh 		 * incremented by 1 if we do checksum offload (a descriptor
   7331  1.281   msaitoh 		 * is used to set the checksum context).
   7332    1.1   thorpej 		 */
   7333  1.281   msaitoh 		txs->txs_mbuf = m0;
   7334  1.356  knakahar 		txs->txs_firstdesc = txq->txq_next;
   7335  1.281   msaitoh 		txs->txs_ndesc = segs_needed;
   7336  1.281   msaitoh 
   7337  1.281   msaitoh 		/* Set up offload parameters for this packet. */
   7338  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags &
   7339  1.388   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6 |
   7340  1.388   msaitoh 		    M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   7341  1.388   msaitoh 		    M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
   7342  1.498  knakahar 			if (wm_tx_offload(sc, txq, txs, &cksumcmd,
   7343  1.281   msaitoh 					  &cksumfields) != 0) {
   7344  1.281   msaitoh 				/* Error message already displayed. */
   7345  1.281   msaitoh 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   7346  1.281   msaitoh 				continue;
   7347  1.281   msaitoh 			}
   7348  1.281   msaitoh 		} else {
   7349  1.281   msaitoh 			cksumcmd = 0;
   7350  1.281   msaitoh 			cksumfields = 0;
   7351    1.1   thorpej 		}
   7352    1.1   thorpej 
   7353  1.281   msaitoh 		cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
   7354  1.281   msaitoh 
   7355  1.281   msaitoh 		/* Sync the DMA map. */
   7356  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   7357  1.281   msaitoh 		    BUS_DMASYNC_PREWRITE);
   7358    1.1   thorpej 
   7359  1.281   msaitoh 		/* Initialize the transmit descriptor. */
   7360  1.356  knakahar 		for (nexttx = txq->txq_next, seg = 0;
   7361  1.281   msaitoh 		     seg < dmamap->dm_nsegs; seg++) {
   7362  1.281   msaitoh 			for (seglen = dmamap->dm_segs[seg].ds_len,
   7363  1.281   msaitoh 			     curaddr = dmamap->dm_segs[seg].ds_addr;
   7364  1.281   msaitoh 			     seglen != 0;
   7365  1.281   msaitoh 			     curaddr += curlen, seglen -= curlen,
   7366  1.356  knakahar 			     nexttx = WM_NEXTTX(txq, nexttx)) {
   7367  1.281   msaitoh 				curlen = seglen;
   7368    1.1   thorpej 
   7369  1.106      yamt 				/*
   7370  1.281   msaitoh 				 * So says the Linux driver:
   7371  1.281   msaitoh 				 * Work around for premature descriptor
   7372  1.281   msaitoh 				 * write-backs in TSO mode.  Append a
   7373  1.281   msaitoh 				 * 4-byte sentinel descriptor.
   7374  1.106      yamt 				 */
   7375  1.388   msaitoh 				if (use_tso && seg == dmamap->dm_nsegs - 1 &&
   7376  1.281   msaitoh 				    curlen > 8)
   7377  1.281   msaitoh 					curlen -= 4;
   7378  1.281   msaitoh 
   7379  1.281   msaitoh 				wm_set_dma_addr(
   7380  1.388   msaitoh 				    &txq->txq_descs[nexttx].wtx_addr, curaddr);
   7381  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_cmdlen
   7382  1.388   msaitoh 				    = htole32(cksumcmd | curlen);
   7383  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_status
   7384  1.388   msaitoh 				    = 0;
   7385  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_options
   7386  1.388   msaitoh 				    = cksumfields;
   7387  1.388   msaitoh 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
   7388  1.281   msaitoh 				lasttx = nexttx;
   7389  1.281   msaitoh 
   7390  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   7391  1.281   msaitoh 				    ("%s: TX: desc %d: low %#" PRIx64 ", "
   7392  1.281   msaitoh 				     "len %#04zx\n",
   7393  1.281   msaitoh 				    device_xname(sc->sc_dev), nexttx,
   7394  1.281   msaitoh 				    (uint64_t)curaddr, curlen));
   7395  1.106      yamt 			}
   7396    1.1   thorpej 		}
   7397    1.1   thorpej 
   7398  1.281   msaitoh 		KASSERT(lasttx != -1);
   7399    1.1   thorpej 
   7400  1.281   msaitoh 		/*
   7401  1.281   msaitoh 		 * Set up the command byte on the last descriptor of
   7402  1.281   msaitoh 		 * the packet.  If we're in the interrupt delay window,
   7403  1.281   msaitoh 		 * delay the interrupt.
   7404  1.281   msaitoh 		 */
   7405  1.356  knakahar 		txq->txq_descs[lasttx].wtx_cmdlen |=
   7406  1.281   msaitoh 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
   7407  1.281   msaitoh 
   7408  1.281   msaitoh 		/*
   7409  1.281   msaitoh 		 * If VLANs are enabled and the packet has a VLAN tag, set
   7410  1.281   msaitoh 		 * up the descriptor to encapsulate the packet for us.
   7411  1.281   msaitoh 		 *
   7412  1.281   msaitoh 		 * This is only valid on the last descriptor of the packet.
   7413  1.281   msaitoh 		 */
   7414  1.538  knakahar 		if (vlan_has_tag(m0)) {
   7415  1.356  knakahar 			txq->txq_descs[lasttx].wtx_cmdlen |=
   7416  1.281   msaitoh 			    htole32(WTX_CMD_VLE);
   7417  1.356  knakahar 			txq->txq_descs[lasttx].wtx_fields.wtxu_vlan
   7418  1.538  knakahar 			    = htole16(vlan_get_tag(m0));
   7419  1.281   msaitoh 		}
   7420  1.281   msaitoh 
   7421  1.281   msaitoh 		txs->txs_lastdesc = lasttx;
   7422  1.281   msaitoh 
   7423  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7424  1.281   msaitoh 		    ("%s: TX: desc %d: cmdlen 0x%08x\n",
   7425  1.281   msaitoh 		    device_xname(sc->sc_dev),
   7426  1.366  knakahar 		    lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
   7427  1.281   msaitoh 
   7428  1.281   msaitoh 		/* Sync the descriptors we're using. */
   7429  1.362  knakahar 		wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc,
   7430  1.388   msaitoh 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   7431  1.281   msaitoh 
   7432  1.281   msaitoh 		/* Give the packet to the chip. */
   7433  1.356  knakahar 		CSR_WRITE(sc, txq->txq_tdt_reg, nexttx);
   7434  1.281   msaitoh 
   7435  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7436  1.281   msaitoh 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
   7437  1.281   msaitoh 
   7438  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7439  1.281   msaitoh 		    ("%s: TX: finished transmitting packet, job %d\n",
   7440  1.366  knakahar 		    device_xname(sc->sc_dev), txq->txq_snext));
   7441  1.272     ozaki 
   7442  1.281   msaitoh 		/* Advance the tx pointer. */
   7443  1.356  knakahar 		txq->txq_free -= txs->txs_ndesc;
   7444  1.356  knakahar 		txq->txq_next = nexttx;
   7445    1.1   thorpej 
   7446  1.356  knakahar 		txq->txq_sfree--;
   7447  1.356  knakahar 		txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext);
   7448  1.272     ozaki 
   7449  1.281   msaitoh 		/* Pass the packet to any BPF listeners. */
   7450  1.281   msaitoh 		bpf_mtap(ifp, m0);
   7451  1.281   msaitoh 	}
   7452  1.272     ozaki 
   7453  1.281   msaitoh 	if (m0 != NULL) {
   7454  1.482  knakahar 		if (!is_transmit)
   7455  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7456  1.479  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7457  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7458  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n",
   7459  1.388   msaitoh 			__func__));
   7460  1.281   msaitoh 		m_freem(m0);
   7461    1.1   thorpej 	}
   7462    1.1   thorpej 
   7463  1.356  knakahar 	if (txq->txq_sfree == 0 || txq->txq_free <= 2) {
   7464  1.281   msaitoh 		/* No more slots; notify upper layer. */
   7465  1.482  knakahar 		if (!is_transmit)
   7466  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   7467  1.479  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   7468  1.281   msaitoh 	}
   7469    1.1   thorpej 
   7470  1.356  knakahar 	if (txq->txq_free != ofree) {
   7471  1.281   msaitoh 		/* Set a watchdog timer in case the chip flakes out. */
   7472  1.562  knakahar 		txq->txq_lastsent = time_uptime;
   7473  1.576   msaitoh 		txq->txq_sending = true;
   7474  1.281   msaitoh 	}
   7475    1.1   thorpej }
   7476    1.1   thorpej 
   7477    1.1   thorpej /*
   7478  1.281   msaitoh  * wm_nq_tx_offload:
   7479    1.1   thorpej  *
   7480  1.281   msaitoh  *	Set up TCP/IP checksumming parameters for the
   7481  1.281   msaitoh  *	specified packet, for NEWQUEUE devices
   7482    1.1   thorpej  */
   7483  1.281   msaitoh static int
   7484  1.403  knakahar wm_nq_tx_offload(struct wm_softc *sc, struct wm_txqueue *txq,
   7485  1.403  knakahar     struct wm_txsoft *txs, uint32_t *cmdlenp, uint32_t *fieldsp, bool *do_csum)
   7486    1.1   thorpej {
   7487  1.281   msaitoh 	struct mbuf *m0 = txs->txs_mbuf;
   7488  1.281   msaitoh 	uint32_t vl_len, mssidx, cmdc;
   7489  1.281   msaitoh 	struct ether_header *eh;
   7490  1.281   msaitoh 	int offset, iphl;
   7491  1.281   msaitoh 
   7492  1.281   msaitoh 	/*
   7493  1.281   msaitoh 	 * XXX It would be nice if the mbuf pkthdr had offset
   7494  1.281   msaitoh 	 * fields for the protocol headers.
   7495  1.281   msaitoh 	 */
   7496  1.281   msaitoh 	*cmdlenp = 0;
   7497  1.281   msaitoh 	*fieldsp = 0;
   7498  1.281   msaitoh 
   7499  1.281   msaitoh 	eh = mtod(m0, struct ether_header *);
   7500  1.281   msaitoh 	switch (htons(eh->ether_type)) {
   7501  1.281   msaitoh 	case ETHERTYPE_IP:
   7502  1.281   msaitoh 	case ETHERTYPE_IPV6:
   7503  1.281   msaitoh 		offset = ETHER_HDR_LEN;
   7504  1.281   msaitoh 		break;
   7505  1.281   msaitoh 
   7506  1.281   msaitoh 	case ETHERTYPE_VLAN:
   7507  1.281   msaitoh 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   7508  1.281   msaitoh 		break;
   7509  1.281   msaitoh 
   7510  1.281   msaitoh 	default:
   7511  1.281   msaitoh 		/* Don't support this protocol or encapsulation. */
   7512  1.281   msaitoh 		*do_csum = false;
   7513  1.281   msaitoh 		return 0;
   7514  1.281   msaitoh 	}
   7515  1.281   msaitoh 	*do_csum = true;
   7516  1.281   msaitoh 	*cmdlenp = NQTX_DTYP_D | NQTX_CMD_DEXT | NQTX_CMD_IFCS;
   7517  1.281   msaitoh 	cmdc = NQTX_DTYP_C | NQTX_CMD_DEXT;
   7518    1.1   thorpej 
   7519  1.281   msaitoh 	vl_len = (offset << NQTXC_VLLEN_MACLEN_SHIFT);
   7520  1.281   msaitoh 	KASSERT((offset & ~NQTXC_VLLEN_MACLEN_MASK) == 0);
   7521  1.281   msaitoh 
   7522  1.281   msaitoh 	if ((m0->m_pkthdr.csum_flags &
   7523  1.388   msaitoh 	    (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) {
   7524  1.281   msaitoh 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   7525  1.281   msaitoh 	} else {
   7526  1.281   msaitoh 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
   7527  1.281   msaitoh 	}
   7528  1.281   msaitoh 	vl_len |= (iphl << NQTXC_VLLEN_IPLEN_SHIFT);
   7529  1.281   msaitoh 	KASSERT((iphl & ~NQTXC_VLLEN_IPLEN_MASK) == 0);
   7530  1.281   msaitoh 
   7531  1.538  knakahar 	if (vlan_has_tag(m0)) {
   7532  1.538  knakahar 		vl_len |= ((vlan_get_tag(m0) & NQTXC_VLLEN_VLAN_MASK)
   7533  1.281   msaitoh 		     << NQTXC_VLLEN_VLAN_SHIFT);
   7534  1.281   msaitoh 		*cmdlenp |= NQTX_CMD_VLE;
   7535  1.281   msaitoh 	}
   7536  1.272     ozaki 
   7537  1.281   msaitoh 	mssidx = 0;
   7538  1.170   msaitoh 
   7539  1.281   msaitoh 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
   7540  1.281   msaitoh 		int hlen = offset + iphl;
   7541  1.281   msaitoh 		int tcp_hlen;
   7542  1.281   msaitoh 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   7543  1.192   msaitoh 
   7544  1.281   msaitoh 		if (__predict_false(m0->m_len <
   7545  1.281   msaitoh 				    (hlen + sizeof(struct tcphdr)))) {
   7546  1.192   msaitoh 			/*
   7547  1.281   msaitoh 			 * TCP/IP headers are not in the first mbuf; we need
   7548  1.281   msaitoh 			 * to do this the slow and painful way.  Let's just
   7549  1.281   msaitoh 			 * hope this doesn't happen very often.
   7550  1.192   msaitoh 			 */
   7551  1.281   msaitoh 			struct tcphdr th;
   7552  1.170   msaitoh 
   7553  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtsopain);
   7554  1.192   msaitoh 
   7555  1.281   msaitoh 			m_copydata(m0, hlen, sizeof(th), &th);
   7556  1.281   msaitoh 			if (v4) {
   7557  1.281   msaitoh 				struct ip ip;
   7558  1.192   msaitoh 
   7559  1.281   msaitoh 				m_copydata(m0, offset, sizeof(ip), &ip);
   7560  1.281   msaitoh 				ip.ip_len = 0;
   7561  1.281   msaitoh 				m_copyback(m0,
   7562  1.281   msaitoh 				    offset + offsetof(struct ip, ip_len),
   7563  1.281   msaitoh 				    sizeof(ip.ip_len), &ip.ip_len);
   7564  1.281   msaitoh 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   7565  1.281   msaitoh 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   7566  1.281   msaitoh 			} else {
   7567  1.281   msaitoh 				struct ip6_hdr ip6;
   7568  1.192   msaitoh 
   7569  1.281   msaitoh 				m_copydata(m0, offset, sizeof(ip6), &ip6);
   7570  1.281   msaitoh 				ip6.ip6_plen = 0;
   7571  1.281   msaitoh 				m_copyback(m0,
   7572  1.281   msaitoh 				    offset + offsetof(struct ip6_hdr, ip6_plen),
   7573  1.281   msaitoh 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
   7574  1.281   msaitoh 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
   7575  1.281   msaitoh 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
   7576  1.170   msaitoh 			}
   7577  1.281   msaitoh 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   7578  1.281   msaitoh 			    sizeof(th.th_sum), &th.th_sum);
   7579  1.192   msaitoh 
   7580  1.281   msaitoh 			tcp_hlen = th.th_off << 2;
   7581  1.281   msaitoh 		} else {
   7582  1.173   msaitoh 			/*
   7583  1.281   msaitoh 			 * TCP/IP headers are in the first mbuf; we can do
   7584  1.281   msaitoh 			 * this the easy way.
   7585  1.173   msaitoh 			 */
   7586  1.281   msaitoh 			struct tcphdr *th;
   7587  1.198   msaitoh 
   7588  1.281   msaitoh 			if (v4) {
   7589  1.281   msaitoh 				struct ip *ip =
   7590  1.281   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   7591  1.281   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   7592    1.1   thorpej 
   7593  1.281   msaitoh 				ip->ip_len = 0;
   7594  1.281   msaitoh 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   7595  1.281   msaitoh 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   7596  1.281   msaitoh 			} else {
   7597  1.281   msaitoh 				struct ip6_hdr *ip6 =
   7598  1.281   msaitoh 				    (void *)(mtod(m0, char *) + offset);
   7599  1.281   msaitoh 				th = (void *)(mtod(m0, char *) + hlen);
   7600  1.192   msaitoh 
   7601  1.281   msaitoh 				ip6->ip6_plen = 0;
   7602  1.281   msaitoh 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
   7603  1.281   msaitoh 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
   7604  1.281   msaitoh 			}
   7605  1.281   msaitoh 			tcp_hlen = th->th_off << 2;
   7606  1.144   msaitoh 		}
   7607  1.281   msaitoh 		hlen += tcp_hlen;
   7608  1.281   msaitoh 		*cmdlenp |= NQTX_CMD_TSE;
   7609  1.144   msaitoh 
   7610  1.281   msaitoh 		if (v4) {
   7611  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso);
   7612  1.281   msaitoh 			*fieldsp |= NQTXD_FIELDS_IXSM | NQTXD_FIELDS_TUXSM;
   7613  1.281   msaitoh 		} else {
   7614  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txtso6);
   7615  1.281   msaitoh 			*fieldsp |= NQTXD_FIELDS_TUXSM;
   7616  1.189   msaitoh 		}
   7617  1.281   msaitoh 		*fieldsp |= ((m0->m_pkthdr.len - hlen) << NQTXD_FIELDS_PAYLEN_SHIFT);
   7618  1.281   msaitoh 		KASSERT(((m0->m_pkthdr.len - hlen) & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
   7619  1.281   msaitoh 		mssidx |= (m0->m_pkthdr.segsz << NQTXC_MSSIDX_MSS_SHIFT);
   7620  1.281   msaitoh 		KASSERT((m0->m_pkthdr.segsz & ~NQTXC_MSSIDX_MSS_MASK) == 0);
   7621  1.281   msaitoh 		mssidx |= (tcp_hlen << NQTXC_MSSIDX_L4LEN_SHIFT);
   7622  1.281   msaitoh 		KASSERT((tcp_hlen & ~NQTXC_MSSIDX_L4LEN_MASK) == 0);
   7623  1.281   msaitoh 	} else {
   7624  1.281   msaitoh 		*fieldsp |= (m0->m_pkthdr.len << NQTXD_FIELDS_PAYLEN_SHIFT);
   7625  1.281   msaitoh 		KASSERT((m0->m_pkthdr.len & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
   7626  1.208   msaitoh 	}
   7627  1.208   msaitoh 
   7628  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
   7629  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_IXSM;
   7630  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP4;
   7631  1.281   msaitoh 	}
   7632  1.144   msaitoh 
   7633  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags &
   7634  1.281   msaitoh 	    (M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
   7635  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum);
   7636  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
   7637  1.281   msaitoh 			cmdc |= NQTXC_CMD_TCP;
   7638  1.281   msaitoh 		} else {
   7639  1.281   msaitoh 			cmdc |= NQTXC_CMD_UDP;
   7640  1.281   msaitoh 		}
   7641  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP4;
   7642  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_TUXSM;
   7643  1.281   msaitoh 	}
   7644  1.281   msaitoh 	if (m0->m_pkthdr.csum_flags &
   7645  1.281   msaitoh 	    (M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
   7646  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txtusum6);
   7647  1.281   msaitoh 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
   7648  1.281   msaitoh 			cmdc |= NQTXC_CMD_TCP;
   7649  1.281   msaitoh 		} else {
   7650  1.281   msaitoh 			cmdc |= NQTXC_CMD_UDP;
   7651  1.281   msaitoh 		}
   7652  1.281   msaitoh 		cmdc |= NQTXC_CMD_IP6;
   7653  1.281   msaitoh 		*fieldsp |= NQTXD_FIELDS_TUXSM;
   7654  1.281   msaitoh 	}
   7655    1.1   thorpej 
   7656  1.500  knakahar 	/*
   7657  1.500  knakahar 	 * We don't have to write context descriptor for every packet to
   7658  1.500  knakahar 	 * NEWQUEUE controllers, that is 82575, 82576, 82580, I350, I354,
   7659  1.500  knakahar 	 * I210 and I211. It is enough to write once per a Tx queue for these
   7660  1.500  knakahar 	 * controllers.
   7661  1.500  knakahar 	 * It would be overhead to write context descriptor for every packet,
   7662  1.500  knakahar 	 * however it does not cause problems.
   7663  1.500  knakahar 	 */
   7664  1.281   msaitoh 	/* Fill in the context descriptor. */
   7665  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_vl_len =
   7666  1.281   msaitoh 	    htole32(vl_len);
   7667  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_sn = 0;
   7668  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_cmd =
   7669  1.281   msaitoh 	    htole32(cmdc);
   7670  1.356  knakahar 	txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_mssidx =
   7671  1.281   msaitoh 	    htole32(mssidx);
   7672  1.362  knakahar 	wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE);
   7673  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX,
   7674  1.281   msaitoh 	    ("%s: TX: context desc %d 0x%08x%08x\n", device_xname(sc->sc_dev),
   7675  1.366  knakahar 	    txq->txq_next, 0, vl_len));
   7676  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX, ("\t0x%08x%08x\n", mssidx, cmdc));
   7677  1.356  knakahar 	txq->txq_next = WM_NEXTTX(txq, txq->txq_next);
   7678  1.281   msaitoh 	txs->txs_ndesc++;
   7679  1.281   msaitoh 	return 0;
   7680  1.217    dyoung }
   7681  1.217    dyoung 
   7682    1.1   thorpej /*
   7683  1.281   msaitoh  * wm_nq_start:		[ifnet interface function]
   7684    1.1   thorpej  *
   7685  1.281   msaitoh  *	Start packet transmission on the interface for NEWQUEUE devices
   7686    1.1   thorpej  */
   7687  1.281   msaitoh static void
   7688  1.281   msaitoh wm_nq_start(struct ifnet *ifp)
   7689    1.1   thorpej {
   7690    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   7691  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7692  1.272     ozaki 
   7693  1.496  knakahar #ifdef WM_MPSAFE
   7694  1.543     ozaki 	KASSERT(if_is_mpsafe(ifp));
   7695  1.496  knakahar #endif
   7696  1.455  knakahar 	/*
   7697  1.455  knakahar 	 * ifp->if_obytes and ifp->if_omcasts are added in if_transmit()@if.c.
   7698  1.455  knakahar 	 */
   7699  1.455  knakahar 
   7700  1.413     skrll 	mutex_enter(txq->txq_lock);
   7701  1.429  knakahar 	if (!txq->txq_stopping)
   7702  1.281   msaitoh 		wm_nq_start_locked(ifp);
   7703  1.413     skrll 	mutex_exit(txq->txq_lock);
   7704  1.272     ozaki }
   7705  1.272     ozaki 
   7706  1.281   msaitoh static void
   7707  1.281   msaitoh wm_nq_start_locked(struct ifnet *ifp)
   7708  1.272     ozaki {
   7709  1.272     ozaki 	struct wm_softc *sc = ifp->if_softc;
   7710  1.405  knakahar 	struct wm_txqueue *txq = &sc->sc_queue[0].wmq_txq;
   7711  1.403  knakahar 
   7712  1.403  knakahar 	wm_nq_send_common_locked(ifp, txq, false);
   7713  1.403  knakahar }
   7714  1.403  knakahar 
   7715  1.403  knakahar static int
   7716  1.403  knakahar wm_nq_transmit(struct ifnet *ifp, struct mbuf *m)
   7717  1.403  knakahar {
   7718  1.403  knakahar 	int qid;
   7719  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7720  1.403  knakahar 	struct wm_txqueue *txq;
   7721  1.403  knakahar 
   7722  1.454  knakahar 	qid = wm_select_txqueue(ifp, m);
   7723  1.405  knakahar 	txq = &sc->sc_queue[qid].wmq_txq;
   7724  1.403  knakahar 
   7725  1.403  knakahar 	if (__predict_false(!pcq_put(txq->txq_interq, m))) {
   7726  1.403  knakahar 		m_freem(m);
   7727  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   7728  1.403  knakahar 		return ENOBUFS;
   7729  1.403  knakahar 	}
   7730  1.403  knakahar 
   7731  1.455  knakahar 	/*
   7732  1.455  knakahar 	 * XXXX NOMPSAFE: ifp->if_data should be percpu.
   7733  1.455  knakahar 	 */
   7734  1.455  knakahar 	ifp->if_obytes += m->m_pkthdr.len;
   7735  1.455  knakahar 	if (m->m_flags & M_MCAST)
   7736  1.455  knakahar 		ifp->if_omcasts++;
   7737  1.455  knakahar 
   7738  1.470  knakahar 	/*
   7739  1.470  knakahar 	 * The situations which this mutex_tryenter() fails at running time
   7740  1.470  knakahar 	 * are below two patterns.
   7741  1.470  knakahar 	 *     (1) contention with interrupt handler(wm_txrxintr_msix())
   7742  1.484  knakahar 	 *     (2) contention with deferred if_start softint(wm_handle_queue())
   7743  1.470  knakahar 	 * In the case of (1), the last packet enqueued to txq->txq_interq is
   7744  1.484  knakahar 	 * dequeued by wm_deferred_start_locked(). So, it does not get stuck.
   7745  1.573   msaitoh 	 * In the case of (2), the last packet enqueued to txq->txq_interq is
   7746  1.573   msaitoh 	 * also dequeued by wm_deferred_start_locked(). So, it does not get
   7747  1.573   msaitoh 	 * stuck, either.
   7748  1.470  knakahar 	 */
   7749  1.413     skrll 	if (mutex_tryenter(txq->txq_lock)) {
   7750  1.429  knakahar 		if (!txq->txq_stopping)
   7751  1.403  knakahar 			wm_nq_transmit_locked(ifp, txq);
   7752  1.413     skrll 		mutex_exit(txq->txq_lock);
   7753  1.403  knakahar 	}
   7754  1.403  knakahar 
   7755  1.403  knakahar 	return 0;
   7756  1.403  knakahar }
   7757  1.403  knakahar 
   7758  1.403  knakahar static void
   7759  1.403  knakahar wm_nq_transmit_locked(struct ifnet *ifp, struct wm_txqueue *txq)
   7760  1.403  knakahar {
   7761  1.403  knakahar 
   7762  1.403  knakahar 	wm_nq_send_common_locked(ifp, txq, true);
   7763  1.403  knakahar }
   7764  1.403  knakahar 
   7765  1.403  knakahar static void
   7766  1.403  knakahar wm_nq_send_common_locked(struct ifnet *ifp, struct wm_txqueue *txq,
   7767  1.403  knakahar     bool is_transmit)
   7768  1.403  knakahar {
   7769  1.403  knakahar 	struct wm_softc *sc = ifp->if_softc;
   7770  1.281   msaitoh 	struct mbuf *m0;
   7771  1.281   msaitoh 	struct wm_txsoft *txs;
   7772  1.281   msaitoh 	bus_dmamap_t dmamap;
   7773  1.281   msaitoh 	int error, nexttx, lasttx = -1, seg, segs_needed;
   7774  1.281   msaitoh 	bool do_csum, sent;
   7775    1.1   thorpej 
   7776  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   7777   1.41       tls 
   7778  1.482  knakahar 	if ((ifp->if_flags & IFF_RUNNING) == 0)
   7779  1.482  knakahar 		return;
   7780  1.482  knakahar 	if ((ifp->if_flags & IFF_OACTIVE) != 0 && !is_transmit)
   7781  1.281   msaitoh 		return;
   7782  1.401  knakahar 	if ((txq->txq_flags & WM_TXQ_NO_SPACE) != 0)
   7783  1.400  knakahar 		return;
   7784    1.1   thorpej 
   7785  1.281   msaitoh 	sent = false;
   7786    1.1   thorpej 
   7787    1.1   thorpej 	/*
   7788  1.281   msaitoh 	 * Loop through the send queue, setting up transmit descriptors
   7789  1.281   msaitoh 	 * until we drain the queue, or use up all available transmit
   7790  1.281   msaitoh 	 * descriptors.
   7791    1.1   thorpej 	 */
   7792  1.281   msaitoh 	for (;;) {
   7793  1.281   msaitoh 		m0 = NULL;
   7794  1.281   msaitoh 
   7795  1.281   msaitoh 		/* Get a work queue entry. */
   7796  1.356  knakahar 		if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) {
   7797  1.557  knakahar 			wm_txeof(txq, UINT_MAX);
   7798  1.356  knakahar 			if (txq->txq_sfree == 0) {
   7799  1.281   msaitoh 				DPRINTF(WM_DEBUG_TX,
   7800  1.281   msaitoh 				    ("%s: TX: no free job descriptors\n",
   7801  1.281   msaitoh 					device_xname(sc->sc_dev)));
   7802  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txsstall);
   7803  1.281   msaitoh 				break;
   7804  1.281   msaitoh 			}
   7805  1.281   msaitoh 		}
   7806    1.1   thorpej 
   7807  1.281   msaitoh 		/* Grab a packet off the queue. */
   7808  1.403  knakahar 		if (is_transmit)
   7809  1.403  knakahar 			m0 = pcq_get(txq->txq_interq);
   7810  1.403  knakahar 		else
   7811  1.403  knakahar 			IFQ_DEQUEUE(&ifp->if_snd, m0);
   7812  1.281   msaitoh 		if (m0 == NULL)
   7813  1.281   msaitoh 			break;
   7814   1.71   thorpej 
   7815  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7816  1.281   msaitoh 		    ("%s: TX: have packet to transmit: %p\n",
   7817  1.281   msaitoh 		    device_xname(sc->sc_dev), m0));
   7818  1.177   msaitoh 
   7819  1.356  knakahar 		txs = &txq->txq_soft[txq->txq_snext];
   7820  1.281   msaitoh 		dmamap = txs->txs_dmamap;
   7821    1.1   thorpej 
   7822  1.281   msaitoh 		/*
   7823  1.281   msaitoh 		 * Load the DMA map.  If this fails, the packet either
   7824  1.281   msaitoh 		 * didn't fit in the allotted number of segments, or we
   7825  1.281   msaitoh 		 * were short on resources.  For the too-many-segments
   7826  1.281   msaitoh 		 * case, we simply report an error and drop the packet,
   7827  1.281   msaitoh 		 * since we can't sanely copy a jumbo packet to a single
   7828  1.281   msaitoh 		 * buffer.
   7829  1.281   msaitoh 		 */
   7830  1.281   msaitoh 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   7831  1.388   msaitoh 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
   7832  1.281   msaitoh 		if (error) {
   7833  1.281   msaitoh 			if (error == EFBIG) {
   7834  1.417  knakahar 				WM_Q_EVCNT_INCR(txq, txdrop);
   7835  1.281   msaitoh 				log(LOG_ERR, "%s: Tx packet consumes too many "
   7836  1.281   msaitoh 				    "DMA segments, dropping...\n",
   7837  1.281   msaitoh 				    device_xname(sc->sc_dev));
   7838  1.281   msaitoh 				wm_dump_mbuf_chain(sc, m0);
   7839  1.281   msaitoh 				m_freem(m0);
   7840  1.281   msaitoh 				continue;
   7841  1.281   msaitoh 			}
   7842  1.281   msaitoh 			/* Short on resources, just stop for now. */
   7843  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7844  1.281   msaitoh 			    ("%s: TX: dmamap load failed: %d\n",
   7845  1.281   msaitoh 			    device_xname(sc->sc_dev), error));
   7846  1.281   msaitoh 			break;
   7847  1.281   msaitoh 		}
   7848  1.177   msaitoh 
   7849  1.281   msaitoh 		segs_needed = dmamap->dm_nsegs;
   7850  1.177   msaitoh 
   7851  1.281   msaitoh 		/*
   7852  1.281   msaitoh 		 * Ensure we have enough descriptors free to describe
   7853  1.281   msaitoh 		 * the packet.  Note, we always reserve one descriptor
   7854  1.281   msaitoh 		 * at the end of the ring due to the semantics of the
   7855  1.281   msaitoh 		 * TDT register, plus one more in the event we need
   7856  1.281   msaitoh 		 * to load offload context.
   7857  1.281   msaitoh 		 */
   7858  1.356  knakahar 		if (segs_needed > txq->txq_free - 2) {
   7859  1.177   msaitoh 			/*
   7860  1.281   msaitoh 			 * Not enough free descriptors to transmit this
   7861  1.281   msaitoh 			 * packet.  We haven't committed anything yet,
   7862  1.281   msaitoh 			 * so just unload the DMA map, put the packet
   7863  1.281   msaitoh 			 * pack on the queue, and punt.  Notify the upper
   7864  1.281   msaitoh 			 * layer that there are no more slots left.
   7865  1.177   msaitoh 			 */
   7866  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7867  1.281   msaitoh 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
   7868  1.281   msaitoh 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
   7869  1.366  knakahar 			    segs_needed, txq->txq_free - 1));
   7870  1.482  knakahar 			if (!is_transmit)
   7871  1.479  knakahar 				ifp->if_flags |= IFF_OACTIVE;
   7872  1.401  knakahar 			txq->txq_flags |= WM_TXQ_NO_SPACE;
   7873  1.281   msaitoh 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   7874  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdstall);
   7875  1.177   msaitoh 			break;
   7876  1.177   msaitoh 		}
   7877  1.177   msaitoh 
   7878  1.281   msaitoh 		/* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
   7879  1.281   msaitoh 
   7880  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   7881  1.281   msaitoh 		    ("%s: TX: packet has %d (%d) DMA segments\n",
   7882  1.281   msaitoh 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
   7883  1.177   msaitoh 
   7884  1.417  knakahar 		WM_EVCNT_INCR(&txq->txq_ev_txseg[dmamap->dm_nsegs - 1]);
   7885    1.1   thorpej 
   7886  1.281   msaitoh 		/*
   7887  1.281   msaitoh 		 * Store a pointer to the packet so that we can free it
   7888  1.281   msaitoh 		 * later.
   7889  1.281   msaitoh 		 *
   7890  1.281   msaitoh 		 * Initially, we consider the number of descriptors the
   7891  1.281   msaitoh 		 * packet uses the number of DMA segments.  This may be
   7892  1.281   msaitoh 		 * incremented by 1 if we do checksum offload (a descriptor
   7893  1.281   msaitoh 		 * is used to set the checksum context).
   7894  1.281   msaitoh 		 */
   7895  1.281   msaitoh 		txs->txs_mbuf = m0;
   7896  1.356  knakahar 		txs->txs_firstdesc = txq->txq_next;
   7897  1.281   msaitoh 		txs->txs_ndesc = segs_needed;
   7898    1.1   thorpej 
   7899  1.281   msaitoh 		/* Set up offload parameters for this packet. */
   7900  1.281   msaitoh 		uint32_t cmdlen, fields, dcmdlen;
   7901  1.388   msaitoh 		if (m0->m_pkthdr.csum_flags &
   7902  1.388   msaitoh 		    (M_CSUM_TSOv4 | M_CSUM_TSOv6 |
   7903  1.388   msaitoh 			M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   7904  1.388   msaitoh 			M_CSUM_TCPv6 | M_CSUM_UDPv6)) {
   7905  1.403  knakahar 			if (wm_nq_tx_offload(sc, txq, txs, &cmdlen, &fields,
   7906  1.281   msaitoh 			    &do_csum) != 0) {
   7907  1.281   msaitoh 				/* Error message already displayed. */
   7908  1.281   msaitoh 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   7909  1.281   msaitoh 				continue;
   7910  1.281   msaitoh 			}
   7911  1.281   msaitoh 		} else {
   7912  1.281   msaitoh 			do_csum = false;
   7913  1.281   msaitoh 			cmdlen = 0;
   7914  1.281   msaitoh 			fields = 0;
   7915  1.281   msaitoh 		}
   7916  1.173   msaitoh 
   7917  1.281   msaitoh 		/* Sync the DMA map. */
   7918  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   7919  1.281   msaitoh 		    BUS_DMASYNC_PREWRITE);
   7920    1.1   thorpej 
   7921  1.281   msaitoh 		/* Initialize the first transmit descriptor. */
   7922  1.356  knakahar 		nexttx = txq->txq_next;
   7923  1.281   msaitoh 		if (!do_csum) {
   7924  1.281   msaitoh 			/* setup a legacy descriptor */
   7925  1.388   msaitoh 			wm_set_dma_addr(&txq->txq_descs[nexttx].wtx_addr,
   7926  1.281   msaitoh 			    dmamap->dm_segs[0].ds_addr);
   7927  1.356  knakahar 			txq->txq_descs[nexttx].wtx_cmdlen =
   7928  1.281   msaitoh 			    htole32(WTX_CMD_IFCS | dmamap->dm_segs[0].ds_len);
   7929  1.356  knakahar 			txq->txq_descs[nexttx].wtx_fields.wtxu_status = 0;
   7930  1.356  knakahar 			txq->txq_descs[nexttx].wtx_fields.wtxu_options = 0;
   7931  1.538  knakahar 			if (vlan_has_tag(m0)) {
   7932  1.356  knakahar 				txq->txq_descs[nexttx].wtx_cmdlen |=
   7933  1.281   msaitoh 				    htole32(WTX_CMD_VLE);
   7934  1.356  knakahar 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =
   7935  1.538  knakahar 				    htole16(vlan_get_tag(m0));
   7936  1.281   msaitoh 			} else {
   7937  1.356  knakahar 				txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0;
   7938  1.281   msaitoh 			}
   7939  1.281   msaitoh 			dcmdlen = 0;
   7940  1.281   msaitoh 		} else {
   7941  1.281   msaitoh 			/* setup an advanced data descriptor */
   7942  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr =
   7943  1.281   msaitoh 			    htole64(dmamap->dm_segs[0].ds_addr);
   7944  1.281   msaitoh 			KASSERT((dmamap->dm_segs[0].ds_len & cmdlen) == 0);
   7945  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen =
   7946  1.281   msaitoh 			    htole32(dmamap->dm_segs[0].ds_len | cmdlen );
   7947  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields =
   7948  1.281   msaitoh 			    htole32(fields);
   7949  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7950  1.281   msaitoh 			    ("%s: TX: adv data desc %d 0x%" PRIx64 "\n",
   7951  1.281   msaitoh 			    device_xname(sc->sc_dev), nexttx,
   7952  1.281   msaitoh 			    (uint64_t)dmamap->dm_segs[0].ds_addr));
   7953  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7954  1.281   msaitoh 			    ("\t 0x%08x%08x\n", fields,
   7955  1.281   msaitoh 			    (uint32_t)dmamap->dm_segs[0].ds_len | cmdlen));
   7956  1.281   msaitoh 			dcmdlen = NQTX_DTYP_D | NQTX_CMD_DEXT;
   7957  1.281   msaitoh 		}
   7958  1.177   msaitoh 
   7959  1.281   msaitoh 		lasttx = nexttx;
   7960  1.356  knakahar 		nexttx = WM_NEXTTX(txq, nexttx);
   7961  1.150       tls 		/*
   7962  1.551   jnemeth 		 * fill in the next descriptors. legacy or advanced format
   7963  1.281   msaitoh 		 * is the same here
   7964  1.150       tls 		 */
   7965  1.281   msaitoh 		for (seg = 1; seg < dmamap->dm_nsegs;
   7966  1.356  knakahar 		    seg++, nexttx = WM_NEXTTX(txq, nexttx)) {
   7967  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr =
   7968  1.281   msaitoh 			    htole64(dmamap->dm_segs[seg].ds_addr);
   7969  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen =
   7970  1.281   msaitoh 			    htole32(dcmdlen | dmamap->dm_segs[seg].ds_len);
   7971  1.281   msaitoh 			KASSERT((dcmdlen & dmamap->dm_segs[seg].ds_len) == 0);
   7972  1.356  knakahar 			txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields = 0;
   7973  1.281   msaitoh 			lasttx = nexttx;
   7974  1.153       tls 
   7975  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   7976  1.281   msaitoh 			    ("%s: TX: desc %d: %#" PRIx64 ", "
   7977  1.281   msaitoh 			     "len %#04zx\n",
   7978  1.281   msaitoh 			    device_xname(sc->sc_dev), nexttx,
   7979  1.281   msaitoh 			    (uint64_t)dmamap->dm_segs[seg].ds_addr,
   7980  1.281   msaitoh 			    dmamap->dm_segs[seg].ds_len));
   7981  1.281   msaitoh 		}
   7982  1.153       tls 
   7983  1.281   msaitoh 		KASSERT(lasttx != -1);
   7984    1.1   thorpej 
   7985  1.211   msaitoh 		/*
   7986  1.281   msaitoh 		 * Set up the command byte on the last descriptor of
   7987  1.281   msaitoh 		 * the packet.  If we're in the interrupt delay window,
   7988  1.281   msaitoh 		 * delay the interrupt.
   7989  1.211   msaitoh 		 */
   7990  1.281   msaitoh 		KASSERT((WTX_CMD_EOP | WTX_CMD_RS) ==
   7991  1.281   msaitoh 		    (NQTX_CMD_EOP | NQTX_CMD_RS));
   7992  1.356  knakahar 		txq->txq_descs[lasttx].wtx_cmdlen |=
   7993  1.281   msaitoh 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
   7994  1.211   msaitoh 
   7995  1.281   msaitoh 		txs->txs_lastdesc = lasttx;
   7996  1.177   msaitoh 
   7997  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: desc %d: cmdlen 0x%08x\n",
   7998  1.281   msaitoh 		    device_xname(sc->sc_dev),
   7999  1.366  knakahar 		    lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen)));
   8000    1.1   thorpej 
   8001  1.281   msaitoh 		/* Sync the descriptors we're using. */
   8002  1.362  knakahar 		wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc,
   8003  1.388   msaitoh 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   8004  1.203   msaitoh 
   8005  1.281   msaitoh 		/* Give the packet to the chip. */
   8006  1.356  knakahar 		CSR_WRITE(sc, txq->txq_tdt_reg, nexttx);
   8007  1.281   msaitoh 		sent = true;
   8008  1.120   msaitoh 
   8009  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   8010  1.281   msaitoh 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
   8011  1.228   msaitoh 
   8012  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   8013  1.281   msaitoh 		    ("%s: TX: finished transmitting packet, job %d\n",
   8014  1.366  knakahar 		    device_xname(sc->sc_dev), txq->txq_snext));
   8015   1.41       tls 
   8016  1.281   msaitoh 		/* Advance the tx pointer. */
   8017  1.356  knakahar 		txq->txq_free -= txs->txs_ndesc;
   8018  1.356  knakahar 		txq->txq_next = nexttx;
   8019    1.1   thorpej 
   8020  1.356  knakahar 		txq->txq_sfree--;
   8021  1.356  knakahar 		txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext);
   8022    1.1   thorpej 
   8023  1.281   msaitoh 		/* Pass the packet to any BPF listeners. */
   8024  1.281   msaitoh 		bpf_mtap(ifp, m0);
   8025  1.281   msaitoh 	}
   8026  1.257   msaitoh 
   8027  1.281   msaitoh 	if (m0 != NULL) {
   8028  1.482  knakahar 		if (!is_transmit)
   8029  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   8030  1.401  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   8031  1.417  knakahar 		WM_Q_EVCNT_INCR(txq, txdrop);
   8032  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n",
   8033  1.388   msaitoh 			__func__));
   8034  1.281   msaitoh 		m_freem(m0);
   8035  1.257   msaitoh 	}
   8036  1.257   msaitoh 
   8037  1.356  knakahar 	if (txq->txq_sfree == 0 || txq->txq_free <= 2) {
   8038  1.281   msaitoh 		/* No more slots; notify upper layer. */
   8039  1.482  knakahar 		if (!is_transmit)
   8040  1.479  knakahar 			ifp->if_flags |= IFF_OACTIVE;
   8041  1.401  knakahar 		txq->txq_flags |= WM_TXQ_NO_SPACE;
   8042  1.281   msaitoh 	}
   8043  1.199   msaitoh 
   8044  1.281   msaitoh 	if (sent) {
   8045  1.281   msaitoh 		/* Set a watchdog timer in case the chip flakes out. */
   8046  1.562  knakahar 		txq->txq_lastsent = time_uptime;
   8047  1.576   msaitoh 		txq->txq_sending = true;
   8048  1.281   msaitoh 	}
   8049  1.281   msaitoh }
   8050  1.272     ozaki 
   8051  1.456     ozaki static void
   8052  1.481  knakahar wm_deferred_start_locked(struct wm_txqueue *txq)
   8053  1.481  knakahar {
   8054  1.481  knakahar 	struct wm_softc *sc = txq->txq_sc;
   8055  1.481  knakahar 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8056  1.481  knakahar 	struct wm_queue *wmq = container_of(txq, struct wm_queue, wmq_txq);
   8057  1.481  knakahar 	int qid = wmq->wmq_id;
   8058  1.481  knakahar 
   8059  1.481  knakahar 	KASSERT(mutex_owned(txq->txq_lock));
   8060  1.456     ozaki 
   8061  1.481  knakahar 	if (txq->txq_stopping) {
   8062  1.456     ozaki 		mutex_exit(txq->txq_lock);
   8063  1.481  knakahar 		return;
   8064  1.481  knakahar 	}
   8065  1.481  knakahar 
   8066  1.481  knakahar 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
   8067  1.503  knakahar 		/* XXX need for ALTQ or one CPU system */
   8068  1.481  knakahar 		if (qid == 0)
   8069  1.481  knakahar 			wm_nq_start_locked(ifp);
   8070  1.481  knakahar 		wm_nq_transmit_locked(ifp, txq);
   8071  1.481  knakahar 	} else {
   8072  1.503  knakahar 		/* XXX need for ALTQ or one CPU system */
   8073  1.481  knakahar 		if (qid == 0)
   8074  1.481  knakahar 			wm_start_locked(ifp);
   8075  1.481  knakahar 		wm_transmit_locked(ifp, txq);
   8076  1.456     ozaki 	}
   8077  1.456     ozaki }
   8078  1.456     ozaki 
   8079  1.281   msaitoh /* Interrupt */
   8080    1.1   thorpej 
   8081    1.1   thorpej /*
   8082  1.335   msaitoh  * wm_txeof:
   8083    1.1   thorpej  *
   8084  1.281   msaitoh  *	Helper; handle transmit interrupts.
   8085    1.1   thorpej  */
   8086  1.563  knakahar static bool
   8087  1.557  knakahar wm_txeof(struct wm_txqueue *txq, u_int limit)
   8088    1.1   thorpej {
   8089  1.557  knakahar 	struct wm_softc *sc = txq->txq_sc;
   8090  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8091  1.281   msaitoh 	struct wm_txsoft *txs;
   8092  1.335   msaitoh 	int count = 0;
   8093  1.335   msaitoh 	int i;
   8094  1.281   msaitoh 	uint8_t status;
   8095  1.479  knakahar 	struct wm_queue *wmq = container_of(txq, struct wm_queue, wmq_txq);
   8096  1.563  knakahar 	bool more = false;
   8097    1.1   thorpej 
   8098  1.413     skrll 	KASSERT(mutex_owned(txq->txq_lock));
   8099  1.405  knakahar 
   8100  1.429  knakahar 	if (txq->txq_stopping)
   8101  1.563  knakahar 		return false;
   8102  1.281   msaitoh 
   8103  1.479  knakahar 	txq->txq_flags &= ~WM_TXQ_NO_SPACE;
   8104  1.479  knakahar 	/* for ALTQ and legacy(not use multiqueue) ethernet controller */
   8105  1.479  knakahar 	if (wmq->wmq_id == 0)
   8106  1.411  knakahar 		ifp->if_flags &= ~IFF_OACTIVE;
   8107  1.272     ozaki 
   8108  1.281   msaitoh 	/*
   8109  1.281   msaitoh 	 * Go through the Tx list and free mbufs for those
   8110  1.281   msaitoh 	 * frames which have been transmitted.
   8111  1.281   msaitoh 	 */
   8112  1.356  knakahar 	for (i = txq->txq_sdirty; txq->txq_sfree != WM_TXQUEUELEN(txq);
   8113  1.356  knakahar 	     i = WM_NEXTTXS(txq, i), txq->txq_sfree++) {
   8114  1.563  knakahar 		if (limit-- == 0) {
   8115  1.563  knakahar 			more = true;
   8116  1.563  knakahar 			DPRINTF(WM_DEBUG_TX,
   8117  1.563  knakahar 			    ("%s: TX: loop limited, job %d is not processed\n",
   8118  1.563  knakahar 				device_xname(sc->sc_dev), i));
   8119  1.557  knakahar 			break;
   8120  1.563  knakahar 		}
   8121  1.557  knakahar 
   8122  1.356  knakahar 		txs = &txq->txq_soft[i];
   8123    1.1   thorpej 
   8124  1.388   msaitoh 		DPRINTF(WM_DEBUG_TX, ("%s: TX: checking job %d\n",
   8125  1.388   msaitoh 			device_xname(sc->sc_dev), i));
   8126  1.272     ozaki 
   8127  1.362  knakahar 		wm_cdtxsync(txq, txs->txs_firstdesc, txs->txs_ndesc,
   8128  1.388   msaitoh 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
   8129  1.272     ozaki 
   8130  1.281   msaitoh 		status =
   8131  1.356  knakahar 		    txq->txq_descs[txs->txs_lastdesc].wtx_fields.wtxu_status;
   8132  1.281   msaitoh 		if ((status & WTX_ST_DD) == 0) {
   8133  1.362  knakahar 			wm_cdtxsync(txq, txs->txs_lastdesc, 1,
   8134  1.281   msaitoh 			    BUS_DMASYNC_PREREAD);
   8135  1.281   msaitoh 			break;
   8136  1.281   msaitoh 		}
   8137    1.1   thorpej 
   8138  1.335   msaitoh 		count++;
   8139  1.281   msaitoh 		DPRINTF(WM_DEBUG_TX,
   8140  1.281   msaitoh 		    ("%s: TX: job %d done: descs %d..%d\n",
   8141  1.281   msaitoh 		    device_xname(sc->sc_dev), i, txs->txs_firstdesc,
   8142  1.281   msaitoh 		    txs->txs_lastdesc));
   8143  1.272     ozaki 
   8144  1.281   msaitoh 		/*
   8145  1.281   msaitoh 		 * XXX We should probably be using the statistics
   8146  1.281   msaitoh 		 * XXX registers, but I don't know if they exist
   8147  1.281   msaitoh 		 * XXX on chips before the i82544.
   8148  1.281   msaitoh 		 */
   8149  1.272     ozaki 
   8150  1.281   msaitoh #ifdef WM_EVENT_COUNTERS
   8151  1.281   msaitoh 		if (status & WTX_ST_TU)
   8152  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, tu);
   8153  1.281   msaitoh #endif /* WM_EVENT_COUNTERS */
   8154    1.1   thorpej 
   8155  1.388   msaitoh 		if (status & (WTX_ST_EC | WTX_ST_LC)) {
   8156  1.281   msaitoh 			ifp->if_oerrors++;
   8157  1.281   msaitoh 			if (status & WTX_ST_LC)
   8158  1.281   msaitoh 				log(LOG_WARNING, "%s: late collision\n",
   8159  1.281   msaitoh 				    device_xname(sc->sc_dev));
   8160  1.281   msaitoh 			else if (status & WTX_ST_EC) {
   8161  1.281   msaitoh 				ifp->if_collisions += 16;
   8162  1.281   msaitoh 				log(LOG_WARNING, "%s: excessive collisions\n",
   8163  1.281   msaitoh 				    device_xname(sc->sc_dev));
   8164  1.281   msaitoh 			}
   8165  1.281   msaitoh 		} else
   8166  1.281   msaitoh 			ifp->if_opackets++;
   8167   1.78   thorpej 
   8168  1.495  knakahar 		txq->txq_packets++;
   8169  1.495  knakahar 		txq->txq_bytes += txs->txs_mbuf->m_pkthdr.len;
   8170  1.495  knakahar 
   8171  1.356  knakahar 		txq->txq_free += txs->txs_ndesc;
   8172  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
   8173  1.281   msaitoh 		    0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   8174  1.281   msaitoh 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   8175  1.281   msaitoh 		m_freem(txs->txs_mbuf);
   8176  1.281   msaitoh 		txs->txs_mbuf = NULL;
   8177    1.1   thorpej 	}
   8178    1.1   thorpej 
   8179  1.281   msaitoh 	/* Update the dirty transmit buffer pointer. */
   8180  1.356  knakahar 	txq->txq_sdirty = i;
   8181  1.281   msaitoh 	DPRINTF(WM_DEBUG_TX,
   8182  1.281   msaitoh 	    ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i));
   8183    1.1   thorpej 
   8184  1.335   msaitoh 	if (count != 0)
   8185  1.335   msaitoh 		rnd_add_uint32(&sc->rnd_source, count);
   8186  1.335   msaitoh 
   8187  1.102       scw 	/*
   8188  1.281   msaitoh 	 * If there are no more pending transmissions, cancel the watchdog
   8189  1.281   msaitoh 	 * timer.
   8190  1.102       scw 	 */
   8191  1.356  knakahar 	if (txq->txq_sfree == WM_TXQUEUELEN(txq))
   8192  1.576   msaitoh 		txq->txq_sending = false;
   8193  1.335   msaitoh 
   8194  1.563  knakahar 	return more;
   8195  1.281   msaitoh }
   8196  1.102       scw 
   8197  1.466  knakahar static inline uint32_t
   8198  1.466  knakahar wm_rxdesc_get_status(struct wm_rxqueue *rxq, int idx)
   8199  1.466  knakahar {
   8200  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8201  1.466  knakahar 
   8202  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8203  1.466  knakahar 		return EXTRXC_STATUS(rxq->rxq_ext_descs[idx].erx_ctx.erxc_err_stat);
   8204  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8205  1.466  knakahar 		return NQRXC_STATUS(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_err_stat);
   8206  1.466  knakahar 	else
   8207  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_status;
   8208  1.466  knakahar }
   8209  1.466  knakahar 
   8210  1.466  knakahar static inline uint32_t
   8211  1.466  knakahar wm_rxdesc_get_errors(struct wm_rxqueue *rxq, int idx)
   8212  1.466  knakahar {
   8213  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8214  1.466  knakahar 
   8215  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8216  1.466  knakahar 		return EXTRXC_ERROR(rxq->rxq_ext_descs[idx].erx_ctx.erxc_err_stat);
   8217  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8218  1.466  knakahar 		return NQRXC_ERROR(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_err_stat);
   8219  1.466  knakahar 	else
   8220  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_errors;
   8221  1.466  knakahar }
   8222  1.466  knakahar 
   8223  1.466  knakahar static inline uint16_t
   8224  1.466  knakahar wm_rxdesc_get_vlantag(struct wm_rxqueue *rxq, int idx)
   8225  1.466  knakahar {
   8226  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8227  1.466  knakahar 
   8228  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8229  1.544   msaitoh 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_vlan;
   8230  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8231  1.544   msaitoh 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_vlan;
   8232  1.466  knakahar 	else
   8233  1.544   msaitoh 		return rxq->rxq_descs[idx].wrx_special;
   8234  1.466  knakahar }
   8235  1.466  knakahar 
   8236  1.466  knakahar static inline int
   8237  1.466  knakahar wm_rxdesc_get_pktlen(struct wm_rxqueue *rxq, int idx)
   8238  1.466  knakahar {
   8239  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8240  1.466  knakahar 
   8241  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8242  1.466  knakahar 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_pktlen;
   8243  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8244  1.466  knakahar 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_pktlen;
   8245  1.466  knakahar 	else
   8246  1.466  knakahar 		return rxq->rxq_descs[idx].wrx_len;
   8247  1.466  knakahar }
   8248  1.466  knakahar 
   8249  1.466  knakahar #ifdef WM_DEBUG
   8250  1.466  knakahar static inline uint32_t
   8251  1.466  knakahar wm_rxdesc_get_rsshash(struct wm_rxqueue *rxq, int idx)
   8252  1.466  knakahar {
   8253  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8254  1.466  knakahar 
   8255  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8256  1.466  knakahar 		return rxq->rxq_ext_descs[idx].erx_ctx.erxc_rsshash;
   8257  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8258  1.466  knakahar 		return rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_rsshash;
   8259  1.466  knakahar 	else
   8260  1.466  knakahar 		return 0;
   8261  1.466  knakahar }
   8262  1.466  knakahar 
   8263  1.466  knakahar static inline uint8_t
   8264  1.466  knakahar wm_rxdesc_get_rsstype(struct wm_rxqueue *rxq, int idx)
   8265  1.466  knakahar {
   8266  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8267  1.466  knakahar 
   8268  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8269  1.466  knakahar 		return EXTRXC_RSS_TYPE(rxq->rxq_ext_descs[idx].erx_ctx.erxc_mrq);
   8270  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8271  1.466  knakahar 		return NQRXC_RSS_TYPE(rxq->rxq_nq_descs[idx].nqrx_ctx.nrxc_misc);
   8272  1.466  knakahar 	else
   8273  1.466  knakahar 		return 0;
   8274  1.466  knakahar }
   8275  1.466  knakahar #endif /* WM_DEBUG */
   8276  1.466  knakahar 
   8277  1.466  knakahar static inline bool
   8278  1.466  knakahar wm_rxdesc_is_set_status(struct wm_softc *sc, uint32_t status,
   8279  1.466  knakahar     uint32_t legacy_bit, uint32_t ext_bit, uint32_t nq_bit)
   8280  1.466  knakahar {
   8281  1.466  knakahar 
   8282  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8283  1.466  knakahar 		return (status & ext_bit) != 0;
   8284  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8285  1.466  knakahar 		return (status & nq_bit) != 0;
   8286  1.466  knakahar 	else
   8287  1.466  knakahar 		return (status & legacy_bit) != 0;
   8288  1.466  knakahar }
   8289  1.466  knakahar 
   8290  1.466  knakahar static inline bool
   8291  1.466  knakahar wm_rxdesc_is_set_error(struct wm_softc *sc, uint32_t error,
   8292  1.466  knakahar     uint32_t legacy_bit, uint32_t ext_bit, uint32_t nq_bit)
   8293  1.466  knakahar {
   8294  1.466  knakahar 
   8295  1.466  knakahar 	if (sc->sc_type == WM_T_82574)
   8296  1.466  knakahar 		return (error & ext_bit) != 0;
   8297  1.466  knakahar 	else if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
   8298  1.466  knakahar 		return (error & nq_bit) != 0;
   8299  1.466  knakahar 	else
   8300  1.466  knakahar 		return (error & legacy_bit) != 0;
   8301  1.466  knakahar }
   8302  1.466  knakahar 
   8303  1.466  knakahar static inline bool
   8304  1.466  knakahar wm_rxdesc_is_eop(struct wm_rxqueue *rxq, uint32_t status)
   8305  1.466  knakahar {
   8306  1.466  knakahar 
   8307  1.466  knakahar 	if (wm_rxdesc_is_set_status(rxq->rxq_sc, status,
   8308  1.466  knakahar 		WRX_ST_EOP, EXTRXC_STATUS_EOP, NQRXC_STATUS_EOP))
   8309  1.466  knakahar 		return true;
   8310  1.466  knakahar 	else
   8311  1.466  knakahar 		return false;
   8312  1.466  knakahar }
   8313  1.466  knakahar 
   8314  1.466  knakahar static inline bool
   8315  1.466  knakahar wm_rxdesc_has_errors(struct wm_rxqueue *rxq, uint32_t errors)
   8316  1.466  knakahar {
   8317  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8318  1.466  knakahar 
   8319  1.466  knakahar 	/* XXXX missing error bit for newqueue? */
   8320  1.466  knakahar 	if (wm_rxdesc_is_set_error(sc, errors,
   8321  1.573   msaitoh 		WRX_ER_CE | WRX_ER_SE | WRX_ER_SEQ | WRX_ER_CXE | WRX_ER_RXE,
   8322  1.573   msaitoh 		EXTRXC_ERROR_CE | EXTRXC_ERROR_SE | EXTRXC_ERROR_SEQ
   8323  1.573   msaitoh 		| EXTRXC_ERROR_CXE | EXTRXC_ERROR_RXE,
   8324  1.466  knakahar 		NQRXC_ERROR_RXE)) {
   8325  1.573   msaitoh 		if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_SE,
   8326  1.573   msaitoh 		    EXTRXC_ERROR_SE, 0))
   8327  1.466  knakahar 			log(LOG_WARNING, "%s: symbol error\n",
   8328  1.466  knakahar 			    device_xname(sc->sc_dev));
   8329  1.573   msaitoh 		else if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_SEQ,
   8330  1.573   msaitoh 		    EXTRXC_ERROR_SEQ, 0))
   8331  1.466  knakahar 			log(LOG_WARNING, "%s: receive sequence error\n",
   8332  1.466  knakahar 			    device_xname(sc->sc_dev));
   8333  1.573   msaitoh 		else if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_CE,
   8334  1.573   msaitoh 		    EXTRXC_ERROR_CE, 0))
   8335  1.466  knakahar 			log(LOG_WARNING, "%s: CRC error\n",
   8336  1.466  knakahar 			    device_xname(sc->sc_dev));
   8337  1.466  knakahar 		return true;
   8338  1.466  knakahar 	}
   8339  1.466  knakahar 
   8340  1.466  knakahar 	return false;
   8341  1.466  knakahar }
   8342  1.466  knakahar 
   8343  1.466  knakahar static inline bool
   8344  1.466  knakahar wm_rxdesc_dd(struct wm_rxqueue *rxq, int idx, uint32_t status)
   8345  1.466  knakahar {
   8346  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8347  1.466  knakahar 
   8348  1.466  knakahar 	if (!wm_rxdesc_is_set_status(sc, status, WRX_ST_DD, EXTRXC_STATUS_DD,
   8349  1.466  knakahar 		NQRXC_STATUS_DD)) {
   8350  1.466  knakahar 		/* We have processed all of the receive descriptors. */
   8351  1.466  knakahar 		wm_cdrxsync(rxq, idx, BUS_DMASYNC_PREREAD);
   8352  1.466  knakahar 		return false;
   8353  1.466  knakahar 	}
   8354  1.466  knakahar 
   8355  1.466  knakahar 	return true;
   8356  1.466  knakahar }
   8357  1.466  knakahar 
   8358  1.466  knakahar static inline bool
   8359  1.573   msaitoh wm_rxdesc_input_vlantag(struct wm_rxqueue *rxq, uint32_t status,
   8360  1.573   msaitoh     uint16_t vlantag, struct mbuf *m)
   8361  1.466  knakahar {
   8362  1.466  knakahar 
   8363  1.466  knakahar 	if (wm_rxdesc_is_set_status(rxq->rxq_sc, status,
   8364  1.466  knakahar 		WRX_ST_VP, EXTRXC_STATUS_VP, NQRXC_STATUS_VP)) {
   8365  1.538  knakahar 		vlan_set_tag(m, le16toh(vlantag));
   8366  1.466  knakahar 	}
   8367  1.466  knakahar 
   8368  1.466  knakahar 	return true;
   8369  1.466  knakahar }
   8370  1.466  knakahar 
   8371  1.466  knakahar static inline void
   8372  1.466  knakahar wm_rxdesc_ensure_checksum(struct wm_rxqueue *rxq, uint32_t status,
   8373  1.466  knakahar     uint32_t errors, struct mbuf *m)
   8374  1.466  knakahar {
   8375  1.466  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8376  1.466  knakahar 
   8377  1.466  knakahar 	if (!wm_rxdesc_is_set_status(sc, status, WRX_ST_IXSM, 0, 0)) {
   8378  1.466  knakahar 		if (wm_rxdesc_is_set_status(sc, status,
   8379  1.466  knakahar 			WRX_ST_IPCS, EXTRXC_STATUS_IPCS, NQRXC_STATUS_IPCS)) {
   8380  1.466  knakahar 			WM_Q_EVCNT_INCR(rxq, rxipsum);
   8381  1.466  knakahar 			m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
   8382  1.466  knakahar 			if (wm_rxdesc_is_set_error(sc, errors,
   8383  1.466  knakahar 				WRX_ER_IPE, EXTRXC_ERROR_IPE, NQRXC_ERROR_IPE))
   8384  1.466  knakahar 				m->m_pkthdr.csum_flags |=
   8385  1.466  knakahar 					M_CSUM_IPv4_BAD;
   8386  1.466  knakahar 		}
   8387  1.466  knakahar 		if (wm_rxdesc_is_set_status(sc, status,
   8388  1.466  knakahar 			WRX_ST_TCPCS, EXTRXC_STATUS_TCPCS, NQRXC_STATUS_L4I)) {
   8389  1.466  knakahar 			/*
   8390  1.466  knakahar 			 * Note: we don't know if this was TCP or UDP,
   8391  1.466  knakahar 			 * so we just set both bits, and expect the
   8392  1.466  knakahar 			 * upper layers to deal.
   8393  1.466  knakahar 			 */
   8394  1.466  knakahar 			WM_Q_EVCNT_INCR(rxq, rxtusum);
   8395  1.466  knakahar 			m->m_pkthdr.csum_flags |=
   8396  1.466  knakahar 				M_CSUM_TCPv4 | M_CSUM_UDPv4 |
   8397  1.466  knakahar 				M_CSUM_TCPv6 | M_CSUM_UDPv6;
   8398  1.573   msaitoh 			if (wm_rxdesc_is_set_error(sc, errors, WRX_ER_TCPE,
   8399  1.573   msaitoh 			    EXTRXC_ERROR_TCPE, NQRXC_ERROR_L4E))
   8400  1.466  knakahar 				m->m_pkthdr.csum_flags |=
   8401  1.466  knakahar 					M_CSUM_TCP_UDP_BAD;
   8402  1.466  knakahar 		}
   8403  1.466  knakahar 	}
   8404  1.466  knakahar }
   8405  1.466  knakahar 
   8406  1.281   msaitoh /*
   8407  1.335   msaitoh  * wm_rxeof:
   8408  1.281   msaitoh  *
   8409  1.281   msaitoh  *	Helper; handle receive interrupts.
   8410  1.281   msaitoh  */
   8411  1.563  knakahar static bool
   8412  1.493  knakahar wm_rxeof(struct wm_rxqueue *rxq, u_int limit)
   8413  1.281   msaitoh {
   8414  1.362  knakahar 	struct wm_softc *sc = rxq->rxq_sc;
   8415  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8416  1.281   msaitoh 	struct wm_rxsoft *rxs;
   8417  1.281   msaitoh 	struct mbuf *m;
   8418  1.281   msaitoh 	int i, len;
   8419  1.335   msaitoh 	int count = 0;
   8420  1.466  knakahar 	uint32_t status, errors;
   8421  1.281   msaitoh 	uint16_t vlantag;
   8422  1.563  knakahar 	bool more = false;
   8423    1.1   thorpej 
   8424  1.413     skrll 	KASSERT(mutex_owned(rxq->rxq_lock));
   8425  1.405  knakahar 
   8426  1.356  knakahar 	for (i = rxq->rxq_ptr;; i = WM_NEXTRX(i)) {
   8427  1.493  knakahar 		if (limit-- == 0) {
   8428  1.493  knakahar 			rxq->rxq_ptr = i;
   8429  1.563  knakahar 			more = true;
   8430  1.563  knakahar 			DPRINTF(WM_DEBUG_RX,
   8431  1.563  knakahar 			    ("%s: RX: loop limited, descriptor %d is not processed\n",
   8432  1.563  knakahar 				device_xname(sc->sc_dev), i));
   8433  1.493  knakahar 			break;
   8434  1.493  knakahar 		}
   8435  1.493  knakahar 
   8436  1.356  knakahar 		rxs = &rxq->rxq_soft[i];
   8437  1.156    dyoung 
   8438  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8439  1.281   msaitoh 		    ("%s: RX: checking descriptor %d\n",
   8440  1.281   msaitoh 		    device_xname(sc->sc_dev), i));
   8441  1.573   msaitoh 		wm_cdrxsync(rxq, i,
   8442  1.573   msaitoh 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
   8443  1.199   msaitoh 
   8444  1.466  knakahar 		status = wm_rxdesc_get_status(rxq, i);
   8445  1.466  knakahar 		errors = wm_rxdesc_get_errors(rxq, i);
   8446  1.466  knakahar 		len = le16toh(wm_rxdesc_get_pktlen(rxq, i));
   8447  1.466  knakahar 		vlantag = wm_rxdesc_get_vlantag(rxq, i);
   8448  1.466  knakahar #ifdef WM_DEBUG
   8449  1.471  knakahar 		uint32_t rsshash = le32toh(wm_rxdesc_get_rsshash(rxq, i));
   8450  1.468      maya 		uint8_t rsstype = wm_rxdesc_get_rsstype(rxq, i);
   8451  1.466  knakahar #endif
   8452    1.1   thorpej 
   8453  1.483  knakahar 		if (!wm_rxdesc_dd(rxq, i, status)) {
   8454  1.483  knakahar 			/*
   8455  1.483  knakahar 			 * Update the receive pointer holding rxq_lock
   8456  1.483  knakahar 			 * consistent with increment counter.
   8457  1.483  knakahar 			 */
   8458  1.483  knakahar 			rxq->rxq_ptr = i;
   8459  1.281   msaitoh 			break;
   8460  1.483  knakahar 		}
   8461  1.189   msaitoh 
   8462  1.335   msaitoh 		count++;
   8463  1.356  knakahar 		if (__predict_false(rxq->rxq_discard)) {
   8464  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8465  1.281   msaitoh 			    ("%s: RX: discarding contents of descriptor %d\n",
   8466  1.281   msaitoh 			    device_xname(sc->sc_dev), i));
   8467  1.362  knakahar 			wm_init_rxdesc(rxq, i);
   8468  1.466  knakahar 			if (wm_rxdesc_is_eop(rxq, status)) {
   8469  1.281   msaitoh 				/* Reset our state. */
   8470  1.281   msaitoh 				DPRINTF(WM_DEBUG_RX,
   8471  1.281   msaitoh 				    ("%s: RX: resetting rxdiscard -> 0\n",
   8472  1.281   msaitoh 				    device_xname(sc->sc_dev)));
   8473  1.356  knakahar 				rxq->rxq_discard = 0;
   8474  1.281   msaitoh 			}
   8475  1.281   msaitoh 			continue;
   8476  1.189   msaitoh 		}
   8477  1.189   msaitoh 
   8478  1.281   msaitoh 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   8479  1.281   msaitoh 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   8480  1.189   msaitoh 
   8481  1.281   msaitoh 		m = rxs->rxs_mbuf;
   8482  1.189   msaitoh 
   8483  1.281   msaitoh 		/*
   8484  1.281   msaitoh 		 * Add a new receive buffer to the ring, unless of
   8485  1.281   msaitoh 		 * course the length is zero. Treat the latter as a
   8486  1.281   msaitoh 		 * failed mapping.
   8487  1.281   msaitoh 		 */
   8488  1.362  knakahar 		if ((len == 0) || (wm_add_rxbuf(rxq, i) != 0)) {
   8489  1.281   msaitoh 			/*
   8490  1.281   msaitoh 			 * Failed, throw away what we've done so
   8491  1.281   msaitoh 			 * far, and discard the rest of the packet.
   8492  1.281   msaitoh 			 */
   8493  1.281   msaitoh 			ifp->if_ierrors++;
   8494  1.281   msaitoh 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   8495  1.281   msaitoh 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   8496  1.362  knakahar 			wm_init_rxdesc(rxq, i);
   8497  1.466  knakahar 			if (!wm_rxdesc_is_eop(rxq, status))
   8498  1.356  knakahar 				rxq->rxq_discard = 1;
   8499  1.356  knakahar 			if (rxq->rxq_head != NULL)
   8500  1.356  knakahar 				m_freem(rxq->rxq_head);
   8501  1.356  knakahar 			WM_RXCHAIN_RESET(rxq);
   8502  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8503  1.281   msaitoh 			    ("%s: RX: Rx buffer allocation failed, "
   8504  1.281   msaitoh 			    "dropping packet%s\n", device_xname(sc->sc_dev),
   8505  1.366  knakahar 			    rxq->rxq_discard ? " (discard)" : ""));
   8506  1.281   msaitoh 			continue;
   8507  1.189   msaitoh 		}
   8508  1.253   msaitoh 
   8509  1.281   msaitoh 		m->m_len = len;
   8510  1.356  knakahar 		rxq->rxq_len += len;
   8511  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8512  1.281   msaitoh 		    ("%s: RX: buffer at %p len %d\n",
   8513  1.281   msaitoh 		    device_xname(sc->sc_dev), m->m_data, len));
   8514  1.145   msaitoh 
   8515  1.281   msaitoh 		/* If this is not the end of the packet, keep looking. */
   8516  1.466  knakahar 		if (!wm_rxdesc_is_eop(rxq, status)) {
   8517  1.356  knakahar 			WM_RXCHAIN_LINK(rxq, m);
   8518  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8519  1.281   msaitoh 			    ("%s: RX: not yet EOP, rxlen -> %d\n",
   8520  1.366  knakahar 			    device_xname(sc->sc_dev), rxq->rxq_len));
   8521  1.281   msaitoh 			continue;
   8522  1.281   msaitoh 		}
   8523   1.45   thorpej 
   8524  1.281   msaitoh 		/*
   8525  1.281   msaitoh 		 * Okay, we have the entire packet now.  The chip is
   8526  1.281   msaitoh 		 * configured to include the FCS except I350 and I21[01]
   8527  1.281   msaitoh 		 * (not all chips can be configured to strip it),
   8528  1.281   msaitoh 		 * so we need to trim it.
   8529  1.281   msaitoh 		 * May need to adjust length of previous mbuf in the
   8530  1.281   msaitoh 		 * chain if the current mbuf is too short.
   8531  1.281   msaitoh 		 * For an eratta, the RCTL_SECRC bit in RCTL register
   8532  1.281   msaitoh 		 * is always set in I350, so we don't trim it.
   8533  1.281   msaitoh 		 */
   8534  1.281   msaitoh 		if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I354)
   8535  1.281   msaitoh 		    && (sc->sc_type != WM_T_I210)
   8536  1.281   msaitoh 		    && (sc->sc_type != WM_T_I211)) {
   8537  1.281   msaitoh 			if (m->m_len < ETHER_CRC_LEN) {
   8538  1.356  knakahar 				rxq->rxq_tail->m_len
   8539  1.281   msaitoh 				    -= (ETHER_CRC_LEN - m->m_len);
   8540  1.281   msaitoh 				m->m_len = 0;
   8541  1.281   msaitoh 			} else
   8542  1.281   msaitoh 				m->m_len -= ETHER_CRC_LEN;
   8543  1.356  knakahar 			len = rxq->rxq_len - ETHER_CRC_LEN;
   8544  1.281   msaitoh 		} else
   8545  1.356  knakahar 			len = rxq->rxq_len;
   8546  1.117   msaitoh 
   8547  1.356  knakahar 		WM_RXCHAIN_LINK(rxq, m);
   8548  1.127    bouyer 
   8549  1.356  knakahar 		*rxq->rxq_tailp = NULL;
   8550  1.356  knakahar 		m = rxq->rxq_head;
   8551  1.117   msaitoh 
   8552  1.356  knakahar 		WM_RXCHAIN_RESET(rxq);
   8553   1.45   thorpej 
   8554  1.281   msaitoh 		DPRINTF(WM_DEBUG_RX,
   8555  1.281   msaitoh 		    ("%s: RX: have entire packet, len -> %d\n",
   8556  1.281   msaitoh 		    device_xname(sc->sc_dev), len));
   8557   1.45   thorpej 
   8558  1.281   msaitoh 		/* If an error occurred, update stats and drop the packet. */
   8559  1.466  knakahar 		if (wm_rxdesc_has_errors(rxq, errors)) {
   8560  1.281   msaitoh 			m_freem(m);
   8561  1.281   msaitoh 			continue;
   8562   1.45   thorpej 		}
   8563   1.45   thorpej 
   8564  1.281   msaitoh 		/* No errors.  Receive the packet. */
   8565  1.412     ozaki 		m_set_rcvif(m, ifp);
   8566  1.281   msaitoh 		m->m_pkthdr.len = len;
   8567  1.471  knakahar 		/*
   8568  1.471  knakahar 		 * TODO
   8569  1.471  knakahar 		 * should be save rsshash and rsstype to this mbuf.
   8570  1.471  knakahar 		 */
   8571  1.471  knakahar 		DPRINTF(WM_DEBUG_RX,
   8572  1.471  knakahar 		    ("%s: RX: RSS type=%" PRIu8 ", RSS hash=%" PRIu32 "\n",
   8573  1.471  knakahar 			device_xname(sc->sc_dev), rsstype, rsshash));
   8574   1.45   thorpej 
   8575  1.281   msaitoh 		/*
   8576  1.281   msaitoh 		 * If VLANs are enabled, VLAN packets have been unwrapped
   8577  1.281   msaitoh 		 * for us.  Associate the tag with the packet.
   8578  1.281   msaitoh 		 */
   8579  1.466  knakahar 		if (!wm_rxdesc_input_vlantag(rxq, status, vlantag, m))
   8580  1.466  knakahar 			continue;
   8581   1.45   thorpej 
   8582  1.281   msaitoh 		/* Set up checksum info for this packet. */
   8583  1.466  knakahar 		wm_rxdesc_ensure_checksum(rxq, status, errors, m);
   8584  1.483  knakahar 		/*
   8585  1.483  knakahar 		 * Update the receive pointer holding rxq_lock consistent with
   8586  1.483  knakahar 		 * increment counter.
   8587  1.483  knakahar 		 */
   8588  1.483  knakahar 		rxq->rxq_ptr = i;
   8589  1.495  knakahar 		rxq->rxq_packets++;
   8590  1.495  knakahar 		rxq->rxq_bytes += len;
   8591  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   8592   1.45   thorpej 
   8593  1.281   msaitoh 		/* Pass it on. */
   8594  1.391     ozaki 		if_percpuq_enqueue(sc->sc_ipq, m);
   8595   1.46   thorpej 
   8596  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   8597   1.46   thorpej 
   8598  1.429  knakahar 		if (rxq->rxq_stopping)
   8599  1.281   msaitoh 			break;
   8600   1.48   thorpej 	}
   8601  1.281   msaitoh 
   8602  1.335   msaitoh 	if (count != 0)
   8603  1.335   msaitoh 		rnd_add_uint32(&sc->rnd_source, count);
   8604  1.281   msaitoh 
   8605  1.281   msaitoh 	DPRINTF(WM_DEBUG_RX,
   8606  1.281   msaitoh 	    ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i));
   8607  1.563  knakahar 
   8608  1.563  knakahar 	return more;
   8609   1.48   thorpej }
   8610   1.48   thorpej 
   8611   1.48   thorpej /*
   8612  1.281   msaitoh  * wm_linkintr_gmii:
   8613   1.50   thorpej  *
   8614  1.281   msaitoh  *	Helper; handle link interrupts for GMII.
   8615   1.50   thorpej  */
   8616  1.281   msaitoh static void
   8617  1.281   msaitoh wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
   8618   1.50   thorpej {
   8619   1.51   thorpej 
   8620  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   8621  1.281   msaitoh 
   8622  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8623  1.281   msaitoh 		__func__));
   8624  1.281   msaitoh 
   8625  1.281   msaitoh 	if (icr & ICR_LSC) {
   8626  1.445   msaitoh 		uint32_t reg;
   8627  1.381   msaitoh 		uint32_t status = CSR_READ(sc, WMREG_STATUS);
   8628  1.381   msaitoh 
   8629  1.523   msaitoh 		if ((status & STATUS_LU) != 0) {
   8630  1.523   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
   8631  1.523   msaitoh 				device_xname(sc->sc_dev),
   8632  1.523   msaitoh 				(status & STATUS_FD) ? "FDX" : "HDX"));
   8633  1.523   msaitoh 		} else {
   8634  1.523   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   8635  1.523   msaitoh 				device_xname(sc->sc_dev)));
   8636  1.523   msaitoh 		}
   8637  1.381   msaitoh 		if ((sc->sc_type == WM_T_ICH8) && ((status & STATUS_LU) == 0))
   8638  1.381   msaitoh 			wm_gig_downshift_workaround_ich8lan(sc);
   8639  1.381   msaitoh 
   8640  1.523   msaitoh 		if ((sc->sc_type == WM_T_ICH8)
   8641  1.523   msaitoh 		    && (sc->sc_phytype == WMPHY_IGP_3)) {
   8642  1.523   msaitoh 			wm_kmrn_lock_loss_workaround_ich8lan(sc);
   8643  1.523   msaitoh 		}
   8644  1.381   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> mii_pollstat\n",
   8645  1.281   msaitoh 			device_xname(sc->sc_dev)));
   8646  1.281   msaitoh 		mii_pollstat(&sc->sc_mii);
   8647  1.281   msaitoh 		if (sc->sc_type == WM_T_82543) {
   8648  1.281   msaitoh 			int miistatus, active;
   8649  1.281   msaitoh 
   8650  1.281   msaitoh 			/*
   8651  1.281   msaitoh 			 * With 82543, we need to force speed and
   8652  1.281   msaitoh 			 * duplex on the MAC equal to what the PHY
   8653  1.281   msaitoh 			 * speed and duplex configuration is.
   8654  1.281   msaitoh 			 */
   8655  1.281   msaitoh 			miistatus = sc->sc_mii.mii_media_status;
   8656   1.50   thorpej 
   8657  1.281   msaitoh 			if (miistatus & IFM_ACTIVE) {
   8658  1.281   msaitoh 				active = sc->sc_mii.mii_media_active;
   8659  1.281   msaitoh 				sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
   8660  1.281   msaitoh 				switch (IFM_SUBTYPE(active)) {
   8661  1.281   msaitoh 				case IFM_10_T:
   8662  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_10;
   8663  1.281   msaitoh 					break;
   8664  1.281   msaitoh 				case IFM_100_TX:
   8665  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_100;
   8666  1.281   msaitoh 					break;
   8667  1.281   msaitoh 				case IFM_1000_T:
   8668  1.281   msaitoh 					sc->sc_ctrl |= CTRL_SPEED_1000;
   8669  1.281   msaitoh 					break;
   8670  1.281   msaitoh 				default:
   8671  1.281   msaitoh 					/*
   8672  1.281   msaitoh 					 * fiber?
   8673  1.281   msaitoh 					 * Shoud not enter here.
   8674  1.281   msaitoh 					 */
   8675  1.388   msaitoh 					printf("unknown media (%x)\n", active);
   8676  1.281   msaitoh 					break;
   8677  1.281   msaitoh 				}
   8678  1.281   msaitoh 				if (active & IFM_FDX)
   8679  1.281   msaitoh 					sc->sc_ctrl |= CTRL_FD;
   8680  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   8681  1.281   msaitoh 			}
   8682  1.281   msaitoh 		} else if (sc->sc_type == WM_T_PCH) {
   8683  1.281   msaitoh 			wm_k1_gig_workaround_hv(sc,
   8684  1.281   msaitoh 			    ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
   8685  1.230   msaitoh 		}
   8686   1.51   thorpej 
   8687  1.281   msaitoh 		if ((sc->sc_phytype == WMPHY_82578)
   8688  1.281   msaitoh 		    && (IFM_SUBTYPE(sc->sc_mii.mii_media_active)
   8689  1.281   msaitoh 			== IFM_1000_T)) {
   8690   1.51   thorpej 
   8691  1.281   msaitoh 			if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0) {
   8692  1.281   msaitoh 				delay(200*1000); /* XXX too big */
   8693   1.51   thorpej 
   8694  1.281   msaitoh 				/* Link stall fix for link up */
   8695  1.281   msaitoh 				wm_gmii_hv_writereg(sc->sc_dev, 1,
   8696  1.281   msaitoh 				    HV_MUX_DATA_CTRL,
   8697  1.281   msaitoh 				    HV_MUX_DATA_CTRL_GEN_TO_MAC
   8698  1.281   msaitoh 				    | HV_MUX_DATA_CTRL_FORCE_SPEED);
   8699  1.281   msaitoh 				wm_gmii_hv_writereg(sc->sc_dev, 1,
   8700  1.281   msaitoh 				    HV_MUX_DATA_CTRL,
   8701  1.281   msaitoh 				    HV_MUX_DATA_CTRL_GEN_TO_MAC);
   8702  1.281   msaitoh 			}
   8703  1.281   msaitoh 		}
   8704  1.445   msaitoh 		/*
   8705  1.445   msaitoh 		 * I217 Packet Loss issue:
   8706  1.445   msaitoh 		 * ensure that FEXTNVM4 Beacon Duration is set correctly
   8707  1.445   msaitoh 		 * on power up.
   8708  1.445   msaitoh 		 * Set the Beacon Duration for I217 to 8 usec
   8709  1.445   msaitoh 		 */
   8710  1.570   msaitoh 		if (sc->sc_type >= WM_T_PCH_LPT) {
   8711  1.445   msaitoh 			reg = CSR_READ(sc, WMREG_FEXTNVM4);
   8712  1.445   msaitoh 			reg &= ~FEXTNVM4_BEACON_DURATION;
   8713  1.445   msaitoh 			reg |= FEXTNVM4_BEACON_DURATION_8US;
   8714  1.445   msaitoh 			CSR_WRITE(sc, WMREG_FEXTNVM4, reg);
   8715  1.445   msaitoh 		}
   8716  1.445   msaitoh 
   8717  1.445   msaitoh 		/* XXX Work-around I218 hang issue */
   8718  1.445   msaitoh 		/* e1000_k1_workaround_lpt_lp() */
   8719  1.445   msaitoh 
   8720  1.570   msaitoh 		if (sc->sc_type >= WM_T_PCH_LPT) {
   8721  1.445   msaitoh 			/*
   8722  1.445   msaitoh 			 * Set platform power management values for Latency
   8723  1.445   msaitoh 			 * Tolerance Reporting (LTR)
   8724  1.445   msaitoh 			 */
   8725  1.445   msaitoh 			wm_platform_pm_pch_lpt(sc,
   8726  1.445   msaitoh 				((sc->sc_mii.mii_media_status & IFM_ACTIVE)
   8727  1.445   msaitoh 				    != 0));
   8728  1.445   msaitoh 		}
   8729  1.445   msaitoh 
   8730  1.445   msaitoh 		/* FEXTNVM6 K1-off workaround */
   8731  1.445   msaitoh 		if (sc->sc_type == WM_T_PCH_SPT) {
   8732  1.445   msaitoh 			reg = CSR_READ(sc, WMREG_FEXTNVM6);
   8733  1.445   msaitoh 			if (CSR_READ(sc, WMREG_PCIEANACFG)
   8734  1.445   msaitoh 			    & FEXTNVM6_K1_OFF_ENABLE)
   8735  1.445   msaitoh 				reg |= FEXTNVM6_K1_OFF_ENABLE;
   8736  1.445   msaitoh 			else
   8737  1.445   msaitoh 				reg &= ~FEXTNVM6_K1_OFF_ENABLE;
   8738  1.445   msaitoh 			CSR_WRITE(sc, WMREG_FEXTNVM6, reg);
   8739  1.445   msaitoh 		}
   8740  1.281   msaitoh 	} else if (icr & ICR_RXSEQ) {
   8741  1.388   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK Receive sequence error\n",
   8742  1.281   msaitoh 			device_xname(sc->sc_dev)));
   8743   1.51   thorpej 	}
   8744   1.50   thorpej }
   8745   1.50   thorpej 
   8746   1.50   thorpej /*
   8747  1.281   msaitoh  * wm_linkintr_tbi:
   8748   1.57   thorpej  *
   8749  1.281   msaitoh  *	Helper; handle link interrupts for TBI mode.
   8750   1.57   thorpej  */
   8751  1.281   msaitoh static void
   8752  1.281   msaitoh wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
   8753   1.57   thorpej {
   8754  1.506   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8755  1.281   msaitoh 	uint32_t status;
   8756  1.281   msaitoh 
   8757  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8758  1.281   msaitoh 		__func__));
   8759  1.281   msaitoh 
   8760  1.281   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   8761  1.281   msaitoh 	if (icr & ICR_LSC) {
   8762  1.281   msaitoh 		if (status & STATUS_LU) {
   8763  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
   8764  1.281   msaitoh 			    device_xname(sc->sc_dev),
   8765  1.281   msaitoh 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   8766  1.281   msaitoh 			/*
   8767  1.281   msaitoh 			 * NOTE: CTRL will update TFCE and RFCE automatically,
   8768  1.281   msaitoh 			 * so we should update sc->sc_ctrl
   8769  1.281   msaitoh 			 */
   8770   1.57   thorpej 
   8771  1.281   msaitoh 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   8772  1.281   msaitoh 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   8773  1.281   msaitoh 			sc->sc_fcrtl &= ~FCRTL_XONE;
   8774  1.281   msaitoh 			if (status & STATUS_FD)
   8775  1.281   msaitoh 				sc->sc_tctl |=
   8776  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   8777  1.281   msaitoh 			else
   8778  1.281   msaitoh 				sc->sc_tctl |=
   8779  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   8780  1.281   msaitoh 			if (sc->sc_ctrl & CTRL_TFCE)
   8781  1.281   msaitoh 				sc->sc_fcrtl |= FCRTL_XONE;
   8782  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   8783  1.281   msaitoh 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   8784  1.281   msaitoh 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   8785  1.281   msaitoh 				      sc->sc_fcrtl);
   8786  1.281   msaitoh 			sc->sc_tbi_linkup = 1;
   8787  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_UP);
   8788  1.281   msaitoh 		} else {
   8789  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   8790  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   8791  1.281   msaitoh 			sc->sc_tbi_linkup = 0;
   8792  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_DOWN);
   8793  1.281   msaitoh 		}
   8794  1.325   msaitoh 		/* Update LED */
   8795  1.325   msaitoh 		wm_tbi_serdes_set_linkled(sc);
   8796  1.281   msaitoh 	} else if (icr & ICR_RXSEQ) {
   8797  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   8798  1.281   msaitoh 		    ("%s: LINK: Receive sequence error\n",
   8799  1.281   msaitoh 		    device_xname(sc->sc_dev)));
   8800   1.57   thorpej 	}
   8801   1.57   thorpej }
   8802   1.57   thorpej 
   8803   1.57   thorpej /*
   8804  1.325   msaitoh  * wm_linkintr_serdes:
   8805  1.325   msaitoh  *
   8806  1.325   msaitoh  *	Helper; handle link interrupts for TBI mode.
   8807  1.325   msaitoh  */
   8808  1.325   msaitoh static void
   8809  1.325   msaitoh wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
   8810  1.325   msaitoh {
   8811  1.506   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   8812  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   8813  1.325   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   8814  1.325   msaitoh 	uint32_t pcs_adv, pcs_lpab, reg;
   8815  1.325   msaitoh 
   8816  1.325   msaitoh 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
   8817  1.325   msaitoh 		__func__));
   8818  1.325   msaitoh 
   8819  1.325   msaitoh 	if (icr & ICR_LSC) {
   8820  1.325   msaitoh 		/* Check PCS */
   8821  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_LSTS);
   8822  1.325   msaitoh 		if ((reg & PCS_LSTS_LINKOK) != 0) {
   8823  1.506   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up\n",
   8824  1.506   msaitoh 				device_xname(sc->sc_dev)));
   8825  1.325   msaitoh 			mii->mii_media_status |= IFM_ACTIVE;
   8826  1.325   msaitoh 			sc->sc_tbi_linkup = 1;
   8827  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_UP);
   8828  1.325   msaitoh 		} else {
   8829  1.506   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   8830  1.506   msaitoh 				device_xname(sc->sc_dev)));
   8831  1.325   msaitoh 			mii->mii_media_status |= IFM_NONE;
   8832  1.325   msaitoh 			sc->sc_tbi_linkup = 0;
   8833  1.506   msaitoh 			if_link_state_change(ifp, LINK_STATE_DOWN);
   8834  1.325   msaitoh 			wm_tbi_serdes_set_linkled(sc);
   8835  1.325   msaitoh 			return;
   8836  1.325   msaitoh 		}
   8837  1.325   msaitoh 		mii->mii_media_active |= IFM_1000_SX;
   8838  1.325   msaitoh 		if ((reg & PCS_LSTS_FDX) != 0)
   8839  1.325   msaitoh 			mii->mii_media_active |= IFM_FDX;
   8840  1.325   msaitoh 		else
   8841  1.325   msaitoh 			mii->mii_media_active |= IFM_HDX;
   8842  1.325   msaitoh 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   8843  1.325   msaitoh 			/* Check flow */
   8844  1.325   msaitoh 			reg = CSR_READ(sc, WMREG_PCS_LSTS);
   8845  1.325   msaitoh 			if ((reg & PCS_LSTS_AN_COMP) == 0) {
   8846  1.325   msaitoh 				DPRINTF(WM_DEBUG_LINK,
   8847  1.325   msaitoh 				    ("XXX LINKOK but not ACOMP\n"));
   8848  1.325   msaitoh 				return;
   8849  1.325   msaitoh 			}
   8850  1.325   msaitoh 			pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
   8851  1.325   msaitoh 			pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
   8852  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   8853  1.325   msaitoh 			    ("XXX AN result %08x, %08x\n", pcs_adv, pcs_lpab));
   8854  1.325   msaitoh 			if ((pcs_adv & TXCW_SYM_PAUSE)
   8855  1.325   msaitoh 			    && (pcs_lpab & TXCW_SYM_PAUSE)) {
   8856  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8857  1.325   msaitoh 				    | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   8858  1.325   msaitoh 			} else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
   8859  1.325   msaitoh 			    && (pcs_adv & TXCW_ASYM_PAUSE)
   8860  1.325   msaitoh 			    && (pcs_lpab & TXCW_SYM_PAUSE)
   8861  1.325   msaitoh 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
   8862  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8863  1.325   msaitoh 				    | IFM_ETH_TXPAUSE;
   8864  1.325   msaitoh 			else if ((pcs_adv & TXCW_SYM_PAUSE)
   8865  1.325   msaitoh 			    && (pcs_adv & TXCW_ASYM_PAUSE)
   8866  1.325   msaitoh 			    && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
   8867  1.325   msaitoh 			    && (pcs_lpab & TXCW_ASYM_PAUSE))
   8868  1.325   msaitoh 				mii->mii_media_active |= IFM_FLOW
   8869  1.325   msaitoh 				    | IFM_ETH_RXPAUSE;
   8870  1.325   msaitoh 		}
   8871  1.325   msaitoh 		/* Update LED */
   8872  1.325   msaitoh 		wm_tbi_serdes_set_linkled(sc);
   8873  1.325   msaitoh 	} else {
   8874  1.325   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   8875  1.325   msaitoh 		    ("%s: LINK: Receive sequence error\n",
   8876  1.325   msaitoh 		    device_xname(sc->sc_dev)));
   8877  1.325   msaitoh 	}
   8878  1.325   msaitoh }
   8879  1.325   msaitoh 
   8880  1.325   msaitoh /*
   8881  1.281   msaitoh  * wm_linkintr:
   8882   1.57   thorpej  *
   8883  1.281   msaitoh  *	Helper; handle link interrupts.
   8884   1.57   thorpej  */
   8885  1.281   msaitoh static void
   8886  1.281   msaitoh wm_linkintr(struct wm_softc *sc, uint32_t icr)
   8887   1.57   thorpej {
   8888   1.57   thorpej 
   8889  1.357  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   8890  1.357  knakahar 
   8891  1.281   msaitoh 	if (sc->sc_flags & WM_F_HAS_MII)
   8892  1.281   msaitoh 		wm_linkintr_gmii(sc, icr);
   8893  1.325   msaitoh 	else if ((sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   8894  1.332   msaitoh 	    && (sc->sc_type >= WM_T_82575))
   8895  1.325   msaitoh 		wm_linkintr_serdes(sc, icr);
   8896  1.281   msaitoh 	else
   8897  1.281   msaitoh 		wm_linkintr_tbi(sc, icr);
   8898   1.57   thorpej }
   8899   1.57   thorpej 
   8900  1.112     gavan /*
   8901  1.335   msaitoh  * wm_intr_legacy:
   8902  1.112     gavan  *
   8903  1.335   msaitoh  *	Interrupt service routine for INTx and MSI.
   8904  1.112     gavan  */
   8905  1.112     gavan static int
   8906  1.335   msaitoh wm_intr_legacy(void *arg)
   8907  1.198   msaitoh {
   8908  1.281   msaitoh 	struct wm_softc *sc = arg;
   8909  1.484  knakahar 	struct wm_queue *wmq = &sc->sc_queue[0];
   8910  1.484  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   8911  1.484  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   8912  1.335   msaitoh 	uint32_t icr, rndval = 0;
   8913  1.281   msaitoh 	int handled = 0;
   8914  1.281   msaitoh 
   8915  1.281   msaitoh 	while (1 /* CONSTCOND */) {
   8916  1.281   msaitoh 		icr = CSR_READ(sc, WMREG_ICR);
   8917  1.281   msaitoh 		if ((icr & sc->sc_icr) == 0)
   8918  1.281   msaitoh 			break;
   8919  1.511   msaitoh 		if (handled == 0) {
   8920  1.511   msaitoh 			DPRINTF(WM_DEBUG_TX,
   8921  1.517   msaitoh 			    ("%s: INTx: got intr\n",device_xname(sc->sc_dev)));
   8922  1.511   msaitoh 		}
   8923  1.335   msaitoh 		if (rndval == 0)
   8924  1.335   msaitoh 			rndval = icr;
   8925  1.112     gavan 
   8926  1.413     skrll 		mutex_enter(rxq->rxq_lock);
   8927  1.112     gavan 
   8928  1.429  knakahar 		if (rxq->rxq_stopping) {
   8929  1.413     skrll 			mutex_exit(rxq->rxq_lock);
   8930  1.281   msaitoh 			break;
   8931  1.281   msaitoh 		}
   8932  1.247   msaitoh 
   8933  1.281   msaitoh 		handled = 1;
   8934  1.249   msaitoh 
   8935  1.281   msaitoh #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   8936  1.388   msaitoh 		if (icr & (ICR_RXDMT0 | ICR_RXT0)) {
   8937  1.281   msaitoh 			DPRINTF(WM_DEBUG_RX,
   8938  1.281   msaitoh 			    ("%s: RX: got Rx intr 0x%08x\n",
   8939  1.281   msaitoh 			    device_xname(sc->sc_dev),
   8940  1.388   msaitoh 			    icr & (ICR_RXDMT0 | ICR_RXT0)));
   8941  1.417  knakahar 			WM_Q_EVCNT_INCR(rxq, rxintr);
   8942  1.240   msaitoh 		}
   8943  1.281   msaitoh #endif
   8944  1.536  knakahar 		/*
   8945  1.536  knakahar 		 * wm_rxeof() does *not* call upper layer functions directly,
   8946  1.536  knakahar 		 * as if_percpuq_enqueue() just call softint_schedule().
   8947  1.536  knakahar 		 * So, we can call wm_rxeof() in interrupt context.
   8948  1.536  knakahar 		 */
   8949  1.493  knakahar 		wm_rxeof(rxq, UINT_MAX);
   8950  1.240   msaitoh 
   8951  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   8952  1.413     skrll 		mutex_enter(txq->txq_lock);
   8953  1.283     ozaki 
   8954  1.429  knakahar 		if (txq->txq_stopping) {
   8955  1.429  knakahar 			mutex_exit(txq->txq_lock);
   8956  1.429  knakahar 			break;
   8957  1.429  knakahar 		}
   8958  1.429  knakahar 
   8959  1.281   msaitoh #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   8960  1.281   msaitoh 		if (icr & ICR_TXDW) {
   8961  1.281   msaitoh 			DPRINTF(WM_DEBUG_TX,
   8962  1.281   msaitoh 			    ("%s: TX: got TXDW interrupt\n",
   8963  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   8964  1.417  knakahar 			WM_Q_EVCNT_INCR(txq, txdw);
   8965  1.240   msaitoh 		}
   8966  1.281   msaitoh #endif
   8967  1.557  knakahar 		wm_txeof(txq, UINT_MAX);
   8968  1.240   msaitoh 
   8969  1.413     skrll 		mutex_exit(txq->txq_lock);
   8970  1.357  knakahar 		WM_CORE_LOCK(sc);
   8971  1.357  knakahar 
   8972  1.429  knakahar 		if (sc->sc_core_stopping) {
   8973  1.429  knakahar 			WM_CORE_UNLOCK(sc);
   8974  1.429  knakahar 			break;
   8975  1.429  knakahar 		}
   8976  1.429  knakahar 
   8977  1.388   msaitoh 		if (icr & (ICR_LSC | ICR_RXSEQ)) {
   8978  1.281   msaitoh 			WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   8979  1.281   msaitoh 			wm_linkintr(sc, icr);
   8980  1.281   msaitoh 		}
   8981  1.240   msaitoh 
   8982  1.357  knakahar 		WM_CORE_UNLOCK(sc);
   8983  1.112     gavan 
   8984  1.281   msaitoh 		if (icr & ICR_RXO) {
   8985  1.281   msaitoh #if defined(WM_DEBUG)
   8986  1.281   msaitoh 			log(LOG_WARNING, "%s: Receive overrun\n",
   8987  1.281   msaitoh 			    device_xname(sc->sc_dev));
   8988  1.281   msaitoh #endif /* defined(WM_DEBUG) */
   8989  1.281   msaitoh 		}
   8990  1.249   msaitoh 	}
   8991  1.112     gavan 
   8992  1.335   msaitoh 	rnd_add_uint32(&sc->rnd_source, rndval);
   8993  1.335   msaitoh 
   8994  1.335   msaitoh 	if (handled) {
   8995  1.335   msaitoh 		/* Try to get more packets going. */
   8996  1.484  knakahar 		softint_schedule(wmq->wmq_si);
   8997  1.335   msaitoh 	}
   8998  1.335   msaitoh 
   8999  1.335   msaitoh 	return handled;
   9000  1.335   msaitoh }
   9001  1.335   msaitoh 
   9002  1.480  knakahar static inline void
   9003  1.480  knakahar wm_txrxintr_disable(struct wm_queue *wmq)
   9004  1.480  knakahar {
   9005  1.480  knakahar 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
   9006  1.480  knakahar 
   9007  1.480  knakahar 	if (sc->sc_type == WM_T_82574)
   9008  1.573   msaitoh 		CSR_WRITE(sc, WMREG_IMC,
   9009  1.573   msaitoh 		    ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id));
   9010  1.480  knakahar 	else if (sc->sc_type == WM_T_82575)
   9011  1.573   msaitoh 		CSR_WRITE(sc, WMREG_EIMC,
   9012  1.573   msaitoh 		    EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
   9013  1.480  knakahar 	else
   9014  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMC, 1 << wmq->wmq_intr_idx);
   9015  1.480  knakahar }
   9016  1.480  knakahar 
   9017  1.480  knakahar static inline void
   9018  1.480  knakahar wm_txrxintr_enable(struct wm_queue *wmq)
   9019  1.480  knakahar {
   9020  1.480  knakahar 	struct wm_softc *sc = wmq->wmq_txq.txq_sc;
   9021  1.480  knakahar 
   9022  1.495  knakahar 	wm_itrs_calculate(sc, wmq);
   9023  1.495  knakahar 
   9024  1.559  knakahar 	/*
   9025  1.559  knakahar 	 * ICR_OTHER which is disabled in wm_linkintr_msix() is enabled here.
   9026  1.559  knakahar 	 * There is no need to care about which of RXQ(0) and RXQ(1) enable
   9027  1.559  knakahar 	 * ICR_OTHER in first, because each RXQ/TXQ interrupt is disabled
   9028  1.559  knakahar 	 * while each wm_handle_queue(wmq) is runnig.
   9029  1.559  knakahar 	 */
   9030  1.480  knakahar 	if (sc->sc_type == WM_T_82574)
   9031  1.573   msaitoh 		CSR_WRITE(sc, WMREG_IMS,
   9032  1.573   msaitoh 		    ICR_TXQ(wmq->wmq_id) | ICR_RXQ(wmq->wmq_id) | ICR_OTHER);
   9033  1.480  knakahar 	else if (sc->sc_type == WM_T_82575)
   9034  1.573   msaitoh 		CSR_WRITE(sc, WMREG_EIMS,
   9035  1.573   msaitoh 		    EITR_TX_QUEUE(wmq->wmq_id) | EITR_RX_QUEUE(wmq->wmq_id));
   9036  1.480  knakahar 	else
   9037  1.480  knakahar 		CSR_WRITE(sc, WMREG_EIMS, 1 << wmq->wmq_intr_idx);
   9038  1.480  knakahar }
   9039  1.480  knakahar 
   9040  1.335   msaitoh static int
   9041  1.405  knakahar wm_txrxintr_msix(void *arg)
   9042  1.335   msaitoh {
   9043  1.405  knakahar 	struct wm_queue *wmq = arg;
   9044  1.405  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   9045  1.405  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   9046  1.363  knakahar 	struct wm_softc *sc = txq->txq_sc;
   9047  1.557  knakahar 	u_int txlimit = sc->sc_tx_intr_process_limit;
   9048  1.557  knakahar 	u_int rxlimit = sc->sc_rx_intr_process_limit;
   9049  1.563  knakahar 	bool txmore;
   9050  1.563  knakahar 	bool rxmore;
   9051  1.335   msaitoh 
   9052  1.405  knakahar 	KASSERT(wmq->wmq_intr_idx == wmq->wmq_id);
   9053  1.405  knakahar 
   9054  1.335   msaitoh 	DPRINTF(WM_DEBUG_TX,
   9055  1.335   msaitoh 	    ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev)));
   9056  1.335   msaitoh 
   9057  1.480  knakahar 	wm_txrxintr_disable(wmq);
   9058  1.335   msaitoh 
   9059  1.429  knakahar 	mutex_enter(txq->txq_lock);
   9060  1.429  knakahar 
   9061  1.429  knakahar 	if (txq->txq_stopping) {
   9062  1.429  knakahar 		mutex_exit(txq->txq_lock);
   9063  1.429  knakahar 		return 0;
   9064  1.429  knakahar 	}
   9065  1.335   msaitoh 
   9066  1.429  knakahar 	WM_Q_EVCNT_INCR(txq, txdw);
   9067  1.563  knakahar 	txmore = wm_txeof(txq, txlimit);
   9068  1.484  knakahar 	/* wm_deferred start() is done in wm_handle_queue(). */
   9069  1.429  knakahar 	mutex_exit(txq->txq_lock);
   9070  1.429  knakahar 
   9071  1.364  knakahar 	DPRINTF(WM_DEBUG_RX,
   9072  1.335   msaitoh 	    ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev)));
   9073  1.429  knakahar 	mutex_enter(rxq->rxq_lock);
   9074  1.335   msaitoh 
   9075  1.429  knakahar 	if (rxq->rxq_stopping) {
   9076  1.413     skrll 		mutex_exit(rxq->rxq_lock);
   9077  1.429  knakahar 		return 0;
   9078  1.405  knakahar 	}
   9079  1.335   msaitoh 
   9080  1.429  knakahar 	WM_Q_EVCNT_INCR(rxq, rxintr);
   9081  1.563  knakahar 	rxmore = wm_rxeof(rxq, rxlimit);
   9082  1.429  knakahar 	mutex_exit(rxq->rxq_lock);
   9083  1.429  knakahar 
   9084  1.495  knakahar 	wm_itrs_writereg(sc, wmq);
   9085  1.495  knakahar 
   9086  1.563  knakahar 	if (txmore || rxmore)
   9087  1.563  knakahar 		softint_schedule(wmq->wmq_si);
   9088  1.563  knakahar 	else
   9089  1.563  knakahar 		wm_txrxintr_enable(wmq);
   9090  1.484  knakahar 
   9091  1.335   msaitoh 	return 1;
   9092  1.335   msaitoh }
   9093  1.335   msaitoh 
   9094  1.484  knakahar static void
   9095  1.484  knakahar wm_handle_queue(void *arg)
   9096  1.484  knakahar {
   9097  1.484  knakahar 	struct wm_queue *wmq = arg;
   9098  1.484  knakahar 	struct wm_txqueue *txq = &wmq->wmq_txq;
   9099  1.484  knakahar 	struct wm_rxqueue *rxq = &wmq->wmq_rxq;
   9100  1.484  knakahar 	struct wm_softc *sc = txq->txq_sc;
   9101  1.557  knakahar 	u_int txlimit = sc->sc_tx_process_limit;
   9102  1.557  knakahar 	u_int rxlimit = sc->sc_rx_process_limit;
   9103  1.563  knakahar 	bool txmore;
   9104  1.563  knakahar 	bool rxmore;
   9105  1.484  knakahar 
   9106  1.484  knakahar 	mutex_enter(txq->txq_lock);
   9107  1.484  knakahar 	if (txq->txq_stopping) {
   9108  1.484  knakahar 		mutex_exit(txq->txq_lock);
   9109  1.484  knakahar 		return;
   9110  1.484  knakahar 	}
   9111  1.563  knakahar 	txmore = wm_txeof(txq, txlimit);
   9112  1.484  knakahar 	wm_deferred_start_locked(txq);
   9113  1.484  knakahar 	mutex_exit(txq->txq_lock);
   9114  1.484  knakahar 
   9115  1.484  knakahar 	mutex_enter(rxq->rxq_lock);
   9116  1.484  knakahar 	if (rxq->rxq_stopping) {
   9117  1.484  knakahar 		mutex_exit(rxq->rxq_lock);
   9118  1.484  knakahar 		return;
   9119  1.484  knakahar 	}
   9120  1.556  knakahar 	WM_Q_EVCNT_INCR(rxq, rxdefer);
   9121  1.563  knakahar 	rxmore = wm_rxeof(rxq, rxlimit);
   9122  1.484  knakahar 	mutex_exit(rxq->rxq_lock);
   9123  1.493  knakahar 
   9124  1.563  knakahar 	if (txmore || rxmore)
   9125  1.563  knakahar 		softint_schedule(wmq->wmq_si);
   9126  1.563  knakahar 	else
   9127  1.563  knakahar 		wm_txrxintr_enable(wmq);
   9128  1.484  knakahar }
   9129  1.484  knakahar 
   9130  1.335   msaitoh /*
   9131  1.335   msaitoh  * wm_linkintr_msix:
   9132  1.335   msaitoh  *
   9133  1.335   msaitoh  *	Interrupt service routine for link status change for MSI-X.
   9134  1.335   msaitoh  */
   9135  1.335   msaitoh static int
   9136  1.335   msaitoh wm_linkintr_msix(void *arg)
   9137  1.335   msaitoh {
   9138  1.335   msaitoh 	struct wm_softc *sc = arg;
   9139  1.351   msaitoh 	uint32_t reg;
   9140  1.559  knakahar 	bool has_rxo;
   9141  1.335   msaitoh 
   9142  1.369  knakahar 	DPRINTF(WM_DEBUG_LINK,
   9143  1.335   msaitoh 	    ("%s: LINK: got link intr\n", device_xname(sc->sc_dev)));
   9144  1.335   msaitoh 
   9145  1.351   msaitoh 	reg = CSR_READ(sc, WMREG_ICR);
   9146  1.357  knakahar 	WM_CORE_LOCK(sc);
   9147  1.559  knakahar 	if (sc->sc_core_stopping)
   9148  1.335   msaitoh 		goto out;
   9149  1.335   msaitoh 
   9150  1.559  knakahar 	if((reg & ICR_LSC) != 0) {
   9151  1.559  knakahar 		WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   9152  1.559  knakahar 		wm_linkintr(sc, ICR_LSC);
   9153  1.559  knakahar 	}
   9154  1.559  knakahar 
   9155  1.559  knakahar 	/*
   9156  1.559  knakahar 	 * XXX 82574 MSI-X mode workaround
   9157  1.559  knakahar 	 *
   9158  1.559  knakahar 	 * 82574 MSI-X mode causes receive overrun(RXO) interrupt as ICR_OTHER
   9159  1.559  knakahar 	 * MSI-X vector, furthermore it does not cause neigher ICR_RXQ(0) nor
   9160  1.559  knakahar 	 * ICR_RXQ(1) vector. So, we generate ICR_RXQ(0) and ICR_RXQ(1)
   9161  1.559  knakahar 	 * interrupts by writing WMREG_ICS to process receive packets.
   9162  1.559  knakahar 	 */
   9163  1.559  knakahar 	if (sc->sc_type == WM_T_82574 && ((reg & ICR_RXO) != 0)) {
   9164  1.559  knakahar #if defined(WM_DEBUG)
   9165  1.559  knakahar 		log(LOG_WARNING, "%s: Receive overrun\n",
   9166  1.559  knakahar 		    device_xname(sc->sc_dev));
   9167  1.559  knakahar #endif /* defined(WM_DEBUG) */
   9168  1.559  knakahar 
   9169  1.559  knakahar 		has_rxo = true;
   9170  1.559  knakahar 		/*
   9171  1.559  knakahar 		 * The RXO interrupt is very high rate when receive traffic is
   9172  1.559  knakahar 		 * high rate. We use polling mode for ICR_OTHER like Tx/Rx
   9173  1.559  knakahar 		 * interrupts. ICR_OTHER will be enabled at the end of
   9174  1.559  knakahar 		 * wm_txrxintr_msix() which is kicked by both ICR_RXQ(0) and
   9175  1.559  knakahar 		 * ICR_RXQ(1) interrupts.
   9176  1.559  knakahar 		 */
   9177  1.559  knakahar 		CSR_WRITE(sc, WMREG_IMC, ICR_OTHER);
   9178  1.559  knakahar 
   9179  1.559  knakahar 		CSR_WRITE(sc, WMREG_ICS, ICR_RXQ(0) | ICR_RXQ(1));
   9180  1.559  knakahar 	}
   9181  1.559  knakahar 
   9182  1.559  knakahar 
   9183  1.335   msaitoh 
   9184  1.335   msaitoh out:
   9185  1.357  knakahar 	WM_CORE_UNLOCK(sc);
   9186  1.335   msaitoh 
   9187  1.559  knakahar 	if (sc->sc_type == WM_T_82574) {
   9188  1.559  knakahar 		if (!has_rxo)
   9189  1.559  knakahar 			CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC);
   9190  1.559  knakahar 		else
   9191  1.559  knakahar 			CSR_WRITE(sc, WMREG_IMS, ICR_LSC);
   9192  1.559  knakahar 	} else if (sc->sc_type == WM_T_82575)
   9193  1.335   msaitoh 		CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER);
   9194  1.335   msaitoh 	else
   9195  1.364  knakahar 		CSR_WRITE(sc, WMREG_EIMS, 1 << sc->sc_link_intr_idx);
   9196  1.335   msaitoh 
   9197  1.335   msaitoh 	return 1;
   9198  1.335   msaitoh }
   9199  1.335   msaitoh 
   9200  1.335   msaitoh /*
   9201  1.281   msaitoh  * Media related.
   9202  1.281   msaitoh  * GMII, SGMII, TBI (and SERDES)
   9203  1.281   msaitoh  */
   9204  1.117   msaitoh 
   9205  1.325   msaitoh /* Common */
   9206  1.325   msaitoh 
   9207  1.325   msaitoh /*
   9208  1.325   msaitoh  * wm_tbi_serdes_set_linkled:
   9209  1.325   msaitoh  *
   9210  1.325   msaitoh  *	Update the link LED on TBI and SERDES devices.
   9211  1.325   msaitoh  */
   9212  1.325   msaitoh static void
   9213  1.325   msaitoh wm_tbi_serdes_set_linkled(struct wm_softc *sc)
   9214  1.325   msaitoh {
   9215  1.325   msaitoh 
   9216  1.325   msaitoh 	if (sc->sc_tbi_linkup)
   9217  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SWDPIN(0);
   9218  1.325   msaitoh 	else
   9219  1.325   msaitoh 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
   9220  1.325   msaitoh 
   9221  1.325   msaitoh 	/* 82540 or newer devices are active low */
   9222  1.325   msaitoh 	sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0;
   9223  1.325   msaitoh 
   9224  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9225  1.325   msaitoh }
   9226  1.325   msaitoh 
   9227  1.281   msaitoh /* GMII related */
   9228  1.117   msaitoh 
   9229  1.280   msaitoh /*
   9230  1.281   msaitoh  * wm_gmii_reset:
   9231  1.280   msaitoh  *
   9232  1.281   msaitoh  *	Reset the PHY.
   9233  1.280   msaitoh  */
   9234  1.281   msaitoh static void
   9235  1.281   msaitoh wm_gmii_reset(struct wm_softc *sc)
   9236  1.280   msaitoh {
   9237  1.281   msaitoh 	uint32_t reg;
   9238  1.280   msaitoh 	int rv;
   9239  1.280   msaitoh 
   9240  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   9241  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   9242  1.420   msaitoh 
   9243  1.424   msaitoh 	rv = sc->phy.acquire(sc);
   9244  1.281   msaitoh 	if (rv != 0) {
   9245  1.281   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
   9246  1.281   msaitoh 		    __func__);
   9247  1.281   msaitoh 		return;
   9248  1.281   msaitoh 	}
   9249  1.280   msaitoh 
   9250  1.281   msaitoh 	switch (sc->sc_type) {
   9251  1.281   msaitoh 	case WM_T_82542_2_0:
   9252  1.281   msaitoh 	case WM_T_82542_2_1:
   9253  1.281   msaitoh 		/* null */
   9254  1.281   msaitoh 		break;
   9255  1.281   msaitoh 	case WM_T_82543:
   9256  1.281   msaitoh 		/*
   9257  1.281   msaitoh 		 * With 82543, we need to force speed and duplex on the MAC
   9258  1.281   msaitoh 		 * equal to what the PHY speed and duplex configuration is.
   9259  1.281   msaitoh 		 * In addition, we need to perform a hardware reset on the PHY
   9260  1.281   msaitoh 		 * to take it out of reset.
   9261  1.281   msaitoh 		 */
   9262  1.281   msaitoh 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
   9263  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9264  1.280   msaitoh 
   9265  1.281   msaitoh 		/* The PHY reset pin is active-low. */
   9266  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   9267  1.281   msaitoh 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
   9268  1.281   msaitoh 		    CTRL_EXT_SWDPIN(4));
   9269  1.281   msaitoh 		reg |= CTRL_EXT_SWDPIO(4);
   9270  1.218   msaitoh 
   9271  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   9272  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9273  1.281   msaitoh 		delay(10*1000);
   9274  1.218   msaitoh 
   9275  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   9276  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9277  1.281   msaitoh 		delay(150);
   9278  1.281   msaitoh #if 0
   9279  1.281   msaitoh 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
   9280  1.281   msaitoh #endif
   9281  1.281   msaitoh 		delay(20*1000);	/* XXX extra delay to get PHY ID? */
   9282  1.281   msaitoh 		break;
   9283  1.281   msaitoh 	case WM_T_82544:	/* reset 10000us */
   9284  1.281   msaitoh 	case WM_T_82540:
   9285  1.281   msaitoh 	case WM_T_82545:
   9286  1.281   msaitoh 	case WM_T_82545_3:
   9287  1.281   msaitoh 	case WM_T_82546:
   9288  1.281   msaitoh 	case WM_T_82546_3:
   9289  1.281   msaitoh 	case WM_T_82541:
   9290  1.281   msaitoh 	case WM_T_82541_2:
   9291  1.281   msaitoh 	case WM_T_82547:
   9292  1.281   msaitoh 	case WM_T_82547_2:
   9293  1.281   msaitoh 	case WM_T_82571:	/* reset 100us */
   9294  1.281   msaitoh 	case WM_T_82572:
   9295  1.281   msaitoh 	case WM_T_82573:
   9296  1.281   msaitoh 	case WM_T_82574:
   9297  1.281   msaitoh 	case WM_T_82575:
   9298  1.281   msaitoh 	case WM_T_82576:
   9299  1.218   msaitoh 	case WM_T_82580:
   9300  1.228   msaitoh 	case WM_T_I350:
   9301  1.265   msaitoh 	case WM_T_I354:
   9302  1.281   msaitoh 	case WM_T_I210:
   9303  1.281   msaitoh 	case WM_T_I211:
   9304  1.281   msaitoh 	case WM_T_82583:
   9305  1.281   msaitoh 	case WM_T_80003:
   9306  1.281   msaitoh 		/* generic reset */
   9307  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   9308  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9309  1.281   msaitoh 		delay(20000);
   9310  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9311  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9312  1.281   msaitoh 		delay(20000);
   9313  1.281   msaitoh 
   9314  1.281   msaitoh 		if ((sc->sc_type == WM_T_82541)
   9315  1.281   msaitoh 		    || (sc->sc_type == WM_T_82541_2)
   9316  1.281   msaitoh 		    || (sc->sc_type == WM_T_82547)
   9317  1.281   msaitoh 		    || (sc->sc_type == WM_T_82547_2)) {
   9318  1.281   msaitoh 			/* workaround for igp are done in igp_reset() */
   9319  1.281   msaitoh 			/* XXX add code to set LED after phy reset */
   9320  1.218   msaitoh 		}
   9321  1.218   msaitoh 		break;
   9322  1.281   msaitoh 	case WM_T_ICH8:
   9323  1.281   msaitoh 	case WM_T_ICH9:
   9324  1.281   msaitoh 	case WM_T_ICH10:
   9325  1.281   msaitoh 	case WM_T_PCH:
   9326  1.281   msaitoh 	case WM_T_PCH2:
   9327  1.281   msaitoh 	case WM_T_PCH_LPT:
   9328  1.392   msaitoh 	case WM_T_PCH_SPT:
   9329  1.570   msaitoh 	case WM_T_PCH_CNP:
   9330  1.281   msaitoh 		/* generic reset */
   9331  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   9332  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9333  1.281   msaitoh 		delay(100);
   9334  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9335  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9336  1.281   msaitoh 		delay(150);
   9337  1.281   msaitoh 		break;
   9338  1.281   msaitoh 	default:
   9339  1.281   msaitoh 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
   9340  1.281   msaitoh 		    __func__);
   9341  1.281   msaitoh 		break;
   9342  1.281   msaitoh 	}
   9343  1.281   msaitoh 
   9344  1.424   msaitoh 	sc->phy.release(sc);
   9345  1.210   msaitoh 
   9346  1.281   msaitoh 	/* get_cfg_done */
   9347  1.281   msaitoh 	wm_get_cfg_done(sc);
   9348  1.208   msaitoh 
   9349  1.281   msaitoh 	/* extra setup */
   9350  1.281   msaitoh 	switch (sc->sc_type) {
   9351  1.281   msaitoh 	case WM_T_82542_2_0:
   9352  1.281   msaitoh 	case WM_T_82542_2_1:
   9353  1.281   msaitoh 	case WM_T_82543:
   9354  1.281   msaitoh 	case WM_T_82544:
   9355  1.281   msaitoh 	case WM_T_82540:
   9356  1.281   msaitoh 	case WM_T_82545:
   9357  1.281   msaitoh 	case WM_T_82545_3:
   9358  1.281   msaitoh 	case WM_T_82546:
   9359  1.281   msaitoh 	case WM_T_82546_3:
   9360  1.281   msaitoh 	case WM_T_82541_2:
   9361  1.281   msaitoh 	case WM_T_82547_2:
   9362  1.281   msaitoh 	case WM_T_82571:
   9363  1.281   msaitoh 	case WM_T_82572:
   9364  1.281   msaitoh 	case WM_T_82573:
   9365  1.519   msaitoh 	case WM_T_82574:
   9366  1.519   msaitoh 	case WM_T_82583:
   9367  1.281   msaitoh 	case WM_T_82575:
   9368  1.281   msaitoh 	case WM_T_82576:
   9369  1.281   msaitoh 	case WM_T_82580:
   9370  1.281   msaitoh 	case WM_T_I350:
   9371  1.281   msaitoh 	case WM_T_I354:
   9372  1.281   msaitoh 	case WM_T_I210:
   9373  1.281   msaitoh 	case WM_T_I211:
   9374  1.281   msaitoh 	case WM_T_80003:
   9375  1.281   msaitoh 		/* null */
   9376  1.281   msaitoh 		break;
   9377  1.281   msaitoh 	case WM_T_82541:
   9378  1.281   msaitoh 	case WM_T_82547:
   9379  1.281   msaitoh 		/* XXX Configure actively LED after PHY reset */
   9380  1.281   msaitoh 		break;
   9381  1.281   msaitoh 	case WM_T_ICH8:
   9382  1.281   msaitoh 	case WM_T_ICH9:
   9383  1.281   msaitoh 	case WM_T_ICH10:
   9384  1.281   msaitoh 	case WM_T_PCH:
   9385  1.281   msaitoh 	case WM_T_PCH2:
   9386  1.281   msaitoh 	case WM_T_PCH_LPT:
   9387  1.392   msaitoh 	case WM_T_PCH_SPT:
   9388  1.570   msaitoh 	case WM_T_PCH_CNP:
   9389  1.517   msaitoh 		wm_phy_post_reset(sc);
   9390  1.281   msaitoh 		break;
   9391  1.281   msaitoh 	default:
   9392  1.281   msaitoh 		panic("%s: unknown type\n", __func__);
   9393  1.281   msaitoh 		break;
   9394    1.1   thorpej 	}
   9395    1.1   thorpej }
   9396    1.1   thorpej 
   9397    1.1   thorpej /*
   9398  1.475   msaitoh  * Setup sc_phytype and mii_{read|write}reg.
   9399  1.475   msaitoh  *
   9400  1.475   msaitoh  *  To identify PHY type, correct read/write function should be selected.
   9401  1.475   msaitoh  * To select correct read/write function, PCI ID or MAC type are required
   9402  1.475   msaitoh  * without accessing PHY registers.
   9403  1.475   msaitoh  *
   9404  1.475   msaitoh  *  On the first call of this function, PHY ID is not known yet. Check
   9405  1.475   msaitoh  * PCI ID or MAC type. The list of the PCI ID may not be perfect, so the
   9406  1.475   msaitoh  * result might be incorrect.
   9407  1.475   msaitoh  *
   9408  1.475   msaitoh  *  In the second call, PHY OUI and model is used to identify PHY type.
   9409  1.475   msaitoh  * It might not be perfpect because of the lack of compared entry, but it
   9410  1.475   msaitoh  * would be better than the first call.
   9411  1.475   msaitoh  *
   9412  1.475   msaitoh  *  If the detected new result and previous assumption is different,
   9413  1.475   msaitoh  * diagnous message will be printed.
   9414  1.475   msaitoh  */
   9415  1.475   msaitoh static void
   9416  1.475   msaitoh wm_gmii_setup_phytype(struct wm_softc *sc, uint32_t phy_oui,
   9417  1.475   msaitoh     uint16_t phy_model)
   9418  1.475   msaitoh {
   9419  1.475   msaitoh 	device_t dev = sc->sc_dev;
   9420  1.475   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   9421  1.475   msaitoh 	uint16_t new_phytype = WMPHY_UNKNOWN;
   9422  1.475   msaitoh 	uint16_t doubt_phytype = WMPHY_UNKNOWN;
   9423  1.475   msaitoh 	mii_readreg_t new_readreg;
   9424  1.475   msaitoh 	mii_writereg_t new_writereg;
   9425  1.475   msaitoh 
   9426  1.521   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   9427  1.521   msaitoh 		device_xname(sc->sc_dev), __func__));
   9428  1.521   msaitoh 
   9429  1.475   msaitoh 	if (mii->mii_readreg == NULL) {
   9430  1.475   msaitoh 		/*
   9431  1.475   msaitoh 		 *  This is the first call of this function. For ICH and PCH
   9432  1.475   msaitoh 		 * variants, it's difficult to determine the PHY access method
   9433  1.475   msaitoh 		 * by sc_type, so use the PCI product ID for some devices.
   9434  1.475   msaitoh 		 */
   9435  1.475   msaitoh 
   9436  1.475   msaitoh 		switch (sc->sc_pcidevid) {
   9437  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_M_LM:
   9438  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_M_LC:
   9439  1.475   msaitoh 			/* 82577 */
   9440  1.475   msaitoh 			new_phytype = WMPHY_82577;
   9441  1.475   msaitoh 			break;
   9442  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_D_DM:
   9443  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH_D_DC:
   9444  1.475   msaitoh 			/* 82578 */
   9445  1.475   msaitoh 			new_phytype = WMPHY_82578;
   9446  1.475   msaitoh 			break;
   9447  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH2_LV_LM:
   9448  1.475   msaitoh 		case PCI_PRODUCT_INTEL_PCH2_LV_V:
   9449  1.475   msaitoh 			/* 82579 */
   9450  1.475   msaitoh 			new_phytype = WMPHY_82579;
   9451  1.475   msaitoh 			break;
   9452  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801H_82567V_3:
   9453  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801I_BM:
   9454  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801I_IGP_M_AMT: /* Not IGP but BM */
   9455  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_LM:
   9456  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_LF:
   9457  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_D_BM_LM:
   9458  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_D_BM_LF:
   9459  1.475   msaitoh 		case PCI_PRODUCT_INTEL_82801J_R_BM_V:
   9460  1.475   msaitoh 			/* ICH8, 9, 10 with 82567 */
   9461  1.475   msaitoh 			new_phytype = WMPHY_BM;
   9462  1.475   msaitoh 			break;
   9463  1.475   msaitoh 		default:
   9464  1.475   msaitoh 			break;
   9465  1.475   msaitoh 		}
   9466  1.475   msaitoh 	} else {
   9467  1.475   msaitoh 		/* It's not the first call. Use PHY OUI and model */
   9468  1.475   msaitoh 		switch (phy_oui) {
   9469  1.475   msaitoh 		case MII_OUI_ATHEROS: /* XXX ??? */
   9470  1.475   msaitoh 			switch (phy_model) {
   9471  1.475   msaitoh 			case 0x0004: /* XXX */
   9472  1.475   msaitoh 				new_phytype = WMPHY_82578;
   9473  1.475   msaitoh 				break;
   9474  1.475   msaitoh 			default:
   9475  1.475   msaitoh 				break;
   9476  1.475   msaitoh 			}
   9477  1.475   msaitoh 			break;
   9478  1.475   msaitoh 		case MII_OUI_xxMARVELL:
   9479  1.475   msaitoh 			switch (phy_model) {
   9480  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I210:
   9481  1.475   msaitoh 				new_phytype = WMPHY_I210;
   9482  1.475   msaitoh 				break;
   9483  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1011:
   9484  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1000_3:
   9485  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1000_5:
   9486  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1112:
   9487  1.475   msaitoh 				new_phytype = WMPHY_M88;
   9488  1.475   msaitoh 				break;
   9489  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1149:
   9490  1.475   msaitoh 				new_phytype = WMPHY_BM;
   9491  1.475   msaitoh 				break;
   9492  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1111:
   9493  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I347:
   9494  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1512:
   9495  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1340M:
   9496  1.475   msaitoh 			case MII_MODEL_xxMARVELL_E1543:
   9497  1.475   msaitoh 				new_phytype = WMPHY_M88;
   9498  1.475   msaitoh 				break;
   9499  1.475   msaitoh 			case MII_MODEL_xxMARVELL_I82563:
   9500  1.475   msaitoh 				new_phytype = WMPHY_GG82563;
   9501  1.475   msaitoh 				break;
   9502  1.475   msaitoh 			default:
   9503  1.475   msaitoh 				break;
   9504  1.475   msaitoh 			}
   9505  1.475   msaitoh 			break;
   9506  1.475   msaitoh 		case MII_OUI_INTEL:
   9507  1.475   msaitoh 			switch (phy_model) {
   9508  1.475   msaitoh 			case MII_MODEL_INTEL_I82577:
   9509  1.475   msaitoh 				new_phytype = WMPHY_82577;
   9510  1.475   msaitoh 				break;
   9511  1.475   msaitoh 			case MII_MODEL_INTEL_I82579:
   9512  1.475   msaitoh 				new_phytype = WMPHY_82579;
   9513  1.475   msaitoh 				break;
   9514  1.475   msaitoh 			case MII_MODEL_INTEL_I217:
   9515  1.475   msaitoh 				new_phytype = WMPHY_I217;
   9516  1.475   msaitoh 				break;
   9517  1.475   msaitoh 			case MII_MODEL_INTEL_I82580:
   9518  1.475   msaitoh 			case MII_MODEL_INTEL_I350:
   9519  1.475   msaitoh 				new_phytype = WMPHY_82580;
   9520  1.475   msaitoh 				break;
   9521  1.475   msaitoh 			default:
   9522  1.475   msaitoh 				break;
   9523  1.475   msaitoh 			}
   9524  1.475   msaitoh 			break;
   9525  1.475   msaitoh 		case MII_OUI_yyINTEL:
   9526  1.475   msaitoh 			switch (phy_model) {
   9527  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562G:
   9528  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562EM:
   9529  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82562ET:
   9530  1.475   msaitoh 				new_phytype = WMPHY_IFE;
   9531  1.475   msaitoh 				break;
   9532  1.475   msaitoh 			case MII_MODEL_yyINTEL_IGP01E1000:
   9533  1.475   msaitoh 				new_phytype = WMPHY_IGP;
   9534  1.475   msaitoh 				break;
   9535  1.475   msaitoh 			case MII_MODEL_yyINTEL_I82566:
   9536  1.475   msaitoh 				new_phytype = WMPHY_IGP_3;
   9537  1.475   msaitoh 				break;
   9538  1.475   msaitoh 			default:
   9539  1.475   msaitoh 				break;
   9540  1.475   msaitoh 			}
   9541  1.475   msaitoh 			break;
   9542  1.475   msaitoh 		default:
   9543  1.475   msaitoh 			break;
   9544  1.475   msaitoh 		}
   9545  1.475   msaitoh 		if (new_phytype == WMPHY_UNKNOWN)
   9546  1.475   msaitoh 			aprint_verbose_dev(dev, "%s: unknown PHY model\n",
   9547  1.475   msaitoh 			    __func__);
   9548  1.475   msaitoh 
   9549  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9550  1.475   msaitoh 		    && (sc->sc_phytype != new_phytype )) {
   9551  1.475   msaitoh 			aprint_error_dev(dev, "Previously assumed PHY type(%u)"
   9552  1.475   msaitoh 			    "was incorrect. PHY type from PHY ID = %u\n",
   9553  1.475   msaitoh 			    sc->sc_phytype, new_phytype);
   9554  1.475   msaitoh 		}
   9555  1.475   msaitoh 	}
   9556  1.475   msaitoh 
   9557  1.475   msaitoh 	/* Next, use sc->sc_flags and sc->sc_type to set read/write funcs. */
   9558  1.475   msaitoh 	if (((sc->sc_flags & WM_F_SGMII) != 0) && !wm_sgmii_uses_mdio(sc)) {
   9559  1.475   msaitoh 		/* SGMII */
   9560  1.475   msaitoh 		new_readreg = wm_sgmii_readreg;
   9561  1.475   msaitoh 		new_writereg = wm_sgmii_writereg;
   9562  1.475   msaitoh 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
   9563  1.475   msaitoh 		/* BM2 (phyaddr == 1) */
   9564  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9565  1.475   msaitoh 		    && (new_phytype != WMPHY_BM)
   9566  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9567  1.475   msaitoh 			doubt_phytype = new_phytype;
   9568  1.475   msaitoh 		new_phytype = WMPHY_BM;
   9569  1.475   msaitoh 		new_readreg = wm_gmii_bm_readreg;
   9570  1.475   msaitoh 		new_writereg = wm_gmii_bm_writereg;
   9571  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_PCH) {
   9572  1.475   msaitoh 		/* All PCH* use _hv_ */
   9573  1.475   msaitoh 		new_readreg = wm_gmii_hv_readreg;
   9574  1.475   msaitoh 		new_writereg = wm_gmii_hv_writereg;
   9575  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_ICH8) {
   9576  1.475   msaitoh 		/* non-82567 ICH8, 9 and 10 */
   9577  1.475   msaitoh 		new_readreg = wm_gmii_i82544_readreg;
   9578  1.475   msaitoh 		new_writereg = wm_gmii_i82544_writereg;
   9579  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_80003) {
   9580  1.475   msaitoh 		/* 80003 */
   9581  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9582  1.475   msaitoh 		    && (new_phytype != WMPHY_GG82563)
   9583  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9584  1.475   msaitoh 			doubt_phytype = new_phytype;
   9585  1.475   msaitoh 		new_phytype = WMPHY_GG82563;
   9586  1.475   msaitoh 		new_readreg = wm_gmii_i80003_readreg;
   9587  1.475   msaitoh 		new_writereg = wm_gmii_i80003_writereg;
   9588  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_I210) {
   9589  1.475   msaitoh 		/* I210 and I211 */
   9590  1.475   msaitoh 		if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9591  1.475   msaitoh 		    && (new_phytype != WMPHY_I210)
   9592  1.475   msaitoh 		    && (new_phytype != WMPHY_UNKNOWN))
   9593  1.475   msaitoh 			doubt_phytype = new_phytype;
   9594  1.475   msaitoh 		new_phytype = WMPHY_I210;
   9595  1.475   msaitoh 		new_readreg = wm_gmii_gs40g_readreg;
   9596  1.475   msaitoh 		new_writereg = wm_gmii_gs40g_writereg;
   9597  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_82580) {
   9598  1.475   msaitoh 		/* 82580, I350 and I354 */
   9599  1.475   msaitoh 		new_readreg = wm_gmii_82580_readreg;
   9600  1.475   msaitoh 		new_writereg = wm_gmii_82580_writereg;
   9601  1.475   msaitoh 	} else if (sc->sc_type >= WM_T_82544) {
   9602  1.475   msaitoh 		/* 82544, 0, [56], [17], 8257[1234] and 82583 */
   9603  1.475   msaitoh 		new_readreg = wm_gmii_i82544_readreg;
   9604  1.475   msaitoh 		new_writereg = wm_gmii_i82544_writereg;
   9605  1.475   msaitoh 	} else {
   9606  1.475   msaitoh 		new_readreg = wm_gmii_i82543_readreg;
   9607  1.475   msaitoh 		new_writereg = wm_gmii_i82543_writereg;
   9608  1.475   msaitoh 	}
   9609  1.475   msaitoh 
   9610  1.475   msaitoh 	if (new_phytype == WMPHY_BM) {
   9611  1.475   msaitoh 		/* All BM use _bm_ */
   9612  1.475   msaitoh 		new_readreg = wm_gmii_bm_readreg;
   9613  1.475   msaitoh 		new_writereg = wm_gmii_bm_writereg;
   9614  1.475   msaitoh 	}
   9615  1.570   msaitoh 	if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_CNP)) {
   9616  1.475   msaitoh 		/* All PCH* use _hv_ */
   9617  1.475   msaitoh 		new_readreg = wm_gmii_hv_readreg;
   9618  1.475   msaitoh 		new_writereg = wm_gmii_hv_writereg;
   9619  1.475   msaitoh 	}
   9620  1.475   msaitoh 
   9621  1.475   msaitoh 	/* Diag output */
   9622  1.475   msaitoh 	if (doubt_phytype != WMPHY_UNKNOWN)
   9623  1.475   msaitoh 		aprint_error_dev(dev, "Assumed new PHY type was "
   9624  1.475   msaitoh 		    "incorrect. old = %u, new = %u\n", sc->sc_phytype,
   9625  1.475   msaitoh 		    new_phytype);
   9626  1.475   msaitoh 	else if ((sc->sc_phytype != WMPHY_UNKNOWN)
   9627  1.475   msaitoh 	    && (sc->sc_phytype != new_phytype ))
   9628  1.475   msaitoh 		aprint_error_dev(dev, "Previously assumed PHY type(%u)"
   9629  1.475   msaitoh 		    "was incorrect. New PHY type = %u\n",
   9630  1.475   msaitoh 		    sc->sc_phytype, new_phytype);
   9631  1.475   msaitoh 
   9632  1.475   msaitoh 	if ((mii->mii_readreg != NULL) && (new_phytype == WMPHY_UNKNOWN))
   9633  1.475   msaitoh 		aprint_error_dev(dev, "PHY type is still unknown.\n");
   9634  1.475   msaitoh 
   9635  1.475   msaitoh 	if ((mii->mii_readreg != NULL) && (mii->mii_readreg != new_readreg))
   9636  1.475   msaitoh 		aprint_error_dev(dev, "Previously assumed PHY read/write "
   9637  1.475   msaitoh 		    "function was incorrect.\n");
   9638  1.475   msaitoh 
   9639  1.475   msaitoh 	/* Update now */
   9640  1.475   msaitoh 	sc->sc_phytype = new_phytype;
   9641  1.475   msaitoh 	mii->mii_readreg = new_readreg;
   9642  1.475   msaitoh 	mii->mii_writereg = new_writereg;
   9643  1.475   msaitoh }
   9644  1.475   msaitoh 
   9645  1.475   msaitoh /*
   9646  1.281   msaitoh  * wm_get_phy_id_82575:
   9647    1.1   thorpej  *
   9648  1.281   msaitoh  * Return PHY ID. Return -1 if it failed.
   9649    1.1   thorpej  */
   9650  1.281   msaitoh static int
   9651  1.281   msaitoh wm_get_phy_id_82575(struct wm_softc *sc)
   9652    1.1   thorpej {
   9653  1.281   msaitoh 	uint32_t reg;
   9654  1.281   msaitoh 	int phyid = -1;
   9655  1.281   msaitoh 
   9656  1.281   msaitoh 	/* XXX */
   9657  1.281   msaitoh 	if ((sc->sc_flags & WM_F_SGMII) == 0)
   9658  1.281   msaitoh 		return -1;
   9659    1.1   thorpej 
   9660  1.281   msaitoh 	if (wm_sgmii_uses_mdio(sc)) {
   9661  1.281   msaitoh 		switch (sc->sc_type) {
   9662  1.281   msaitoh 		case WM_T_82575:
   9663  1.281   msaitoh 		case WM_T_82576:
   9664  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_MDIC);
   9665  1.281   msaitoh 			phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT;
   9666  1.281   msaitoh 			break;
   9667  1.281   msaitoh 		case WM_T_82580:
   9668  1.281   msaitoh 		case WM_T_I350:
   9669  1.281   msaitoh 		case WM_T_I354:
   9670  1.281   msaitoh 		case WM_T_I210:
   9671  1.281   msaitoh 		case WM_T_I211:
   9672  1.281   msaitoh 			reg = CSR_READ(sc, WMREG_MDICNFG);
   9673  1.281   msaitoh 			phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT;
   9674  1.281   msaitoh 			break;
   9675  1.281   msaitoh 		default:
   9676  1.281   msaitoh 			return -1;
   9677  1.281   msaitoh 		}
   9678  1.139    bouyer 	}
   9679    1.1   thorpej 
   9680  1.281   msaitoh 	return phyid;
   9681    1.1   thorpej }
   9682    1.1   thorpej 
   9683  1.281   msaitoh 
   9684    1.1   thorpej /*
   9685  1.281   msaitoh  * wm_gmii_mediainit:
   9686    1.1   thorpej  *
   9687  1.281   msaitoh  *	Initialize media for use on 1000BASE-T devices.
   9688    1.1   thorpej  */
   9689   1.47   thorpej static void
   9690  1.281   msaitoh wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
   9691    1.1   thorpej {
   9692  1.475   msaitoh 	device_t dev = sc->sc_dev;
   9693    1.1   thorpej 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   9694  1.281   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   9695  1.282   msaitoh 	uint32_t reg;
   9696  1.281   msaitoh 
   9697  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   9698  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   9699  1.425   msaitoh 
   9700  1.292   msaitoh 	/* We have GMII. */
   9701  1.281   msaitoh 	sc->sc_flags |= WM_F_HAS_MII;
   9702    1.1   thorpej 
   9703  1.281   msaitoh 	if (sc->sc_type == WM_T_80003)
   9704  1.281   msaitoh 		sc->sc_tipg =  TIPG_1000T_80003_DFLT;
   9705    1.1   thorpej 	else
   9706  1.281   msaitoh 		sc->sc_tipg = TIPG_1000T_DFLT;
   9707    1.1   thorpej 
   9708  1.282   msaitoh 	/* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */
   9709  1.300   msaitoh 	if ((sc->sc_type == WM_T_82580)
   9710  1.282   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210)
   9711  1.282   msaitoh 	    || (sc->sc_type == WM_T_I211)) {
   9712  1.282   msaitoh 		reg = CSR_READ(sc, WMREG_PHPM);
   9713  1.282   msaitoh 		reg &= ~PHPM_GO_LINK_D;
   9714  1.282   msaitoh 		CSR_WRITE(sc, WMREG_PHPM, reg);
   9715  1.282   msaitoh 	}
   9716  1.282   msaitoh 
   9717  1.281   msaitoh 	/*
   9718  1.281   msaitoh 	 * Let the chip set speed/duplex on its own based on
   9719  1.281   msaitoh 	 * signals from the PHY.
   9720  1.281   msaitoh 	 * XXXbouyer - I'm not sure this is right for the 80003,
   9721  1.281   msaitoh 	 * the em driver only sets CTRL_SLU here - but it seems to work.
   9722  1.281   msaitoh 	 */
   9723  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   9724  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9725    1.1   thorpej 
   9726  1.281   msaitoh 	/* Initialize our media structures and probe the GMII. */
   9727  1.281   msaitoh 	mii->mii_ifp = ifp;
   9728    1.1   thorpej 
   9729  1.281   msaitoh 	mii->mii_statchg = wm_gmii_statchg;
   9730    1.1   thorpej 
   9731  1.448   msaitoh 	/* get PHY control from SMBus to PCIe */
   9732  1.448   msaitoh 	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
   9733  1.570   msaitoh 	    || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
   9734  1.570   msaitoh 	    || (sc->sc_type == WM_T_PCH_CNP))
   9735  1.448   msaitoh 		wm_smbustopci(sc);
   9736  1.448   msaitoh 
   9737  1.281   msaitoh 	wm_gmii_reset(sc);
   9738    1.1   thorpej 
   9739  1.281   msaitoh 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   9740  1.327   msaitoh 	ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange,
   9741  1.327   msaitoh 	    wm_gmii_mediastatus);
   9742    1.1   thorpej 
   9743  1.281   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
   9744  1.300   msaitoh 	    || (sc->sc_type == WM_T_82580)
   9745  1.281   msaitoh 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
   9746  1.281   msaitoh 	    || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) {
   9747  1.281   msaitoh 		if ((sc->sc_flags & WM_F_SGMII) == 0) {
   9748  1.281   msaitoh 			/* Attach only one port */
   9749  1.281   msaitoh 			mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
   9750  1.281   msaitoh 			    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9751  1.281   msaitoh 		} else {
   9752  1.281   msaitoh 			int i, id;
   9753  1.281   msaitoh 			uint32_t ctrl_ext;
   9754    1.1   thorpej 
   9755  1.281   msaitoh 			id = wm_get_phy_id_82575(sc);
   9756  1.281   msaitoh 			if (id != -1) {
   9757  1.281   msaitoh 				mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
   9758  1.281   msaitoh 				    id, MII_OFFSET_ANY, MIIF_DOPAUSE);
   9759  1.281   msaitoh 			}
   9760  1.281   msaitoh 			if ((id == -1)
   9761  1.281   msaitoh 			    || (LIST_FIRST(&mii->mii_phys) == NULL)) {
   9762  1.281   msaitoh 				/* Power on sgmii phy if it is disabled */
   9763  1.281   msaitoh 				ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   9764  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL_EXT,
   9765  1.281   msaitoh 				    ctrl_ext &~ CTRL_EXT_SWDPIN(3));
   9766  1.281   msaitoh 				CSR_WRITE_FLUSH(sc);
   9767  1.281   msaitoh 				delay(300*1000); /* XXX too long */
   9768    1.1   thorpej 
   9769  1.281   msaitoh 				/* from 1 to 8 */
   9770  1.281   msaitoh 				for (i = 1; i < 8; i++)
   9771  1.281   msaitoh 					mii_attach(sc->sc_dev, &sc->sc_mii,
   9772  1.281   msaitoh 					    0xffffffff, i, MII_OFFSET_ANY,
   9773  1.281   msaitoh 					    MIIF_DOPAUSE);
   9774    1.1   thorpej 
   9775  1.281   msaitoh 				/* restore previous sfp cage power state */
   9776  1.281   msaitoh 				CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   9777  1.281   msaitoh 			}
   9778  1.281   msaitoh 		}
   9779  1.281   msaitoh 	} else {
   9780  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9781  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9782  1.281   msaitoh 	}
   9783  1.173   msaitoh 
   9784  1.281   msaitoh 	/*
   9785  1.281   msaitoh 	 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
   9786  1.281   msaitoh 	 * wm_set_mdio_slow_mode_hv() for a workaround and retry.
   9787  1.281   msaitoh 	 */
   9788  1.570   msaitoh 	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
   9789  1.570   msaitoh 		|| (sc->sc_type == WM_T_PCH_SPT)
   9790  1.570   msaitoh 		|| (sc->sc_type == WM_T_PCH_CNP))
   9791  1.570   msaitoh 	    && (LIST_FIRST(&mii->mii_phys) == NULL)) {
   9792  1.281   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   9793  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9794  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9795  1.281   msaitoh 	}
   9796    1.1   thorpej 
   9797    1.1   thorpej 	/*
   9798  1.281   msaitoh 	 * (For ICH8 variants)
   9799  1.281   msaitoh 	 * If PHY detection failed, use BM's r/w function and retry.
   9800    1.1   thorpej 	 */
   9801  1.281   msaitoh 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
   9802  1.281   msaitoh 		/* if failed, retry with *_bm_* */
   9803  1.475   msaitoh 		aprint_verbose_dev(dev, "Assumed PHY access function "
   9804  1.475   msaitoh 		    "(type = %d) might be incorrect. Use BM and retry.\n",
   9805  1.475   msaitoh 		    sc->sc_phytype);
   9806  1.475   msaitoh 		sc->sc_phytype = WMPHY_BM;
   9807  1.281   msaitoh 		mii->mii_readreg = wm_gmii_bm_readreg;
   9808  1.281   msaitoh 		mii->mii_writereg = wm_gmii_bm_writereg;
   9809    1.1   thorpej 
   9810  1.281   msaitoh 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   9811  1.281   msaitoh 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
   9812  1.281   msaitoh 	}
   9813    1.1   thorpej 
   9814  1.281   msaitoh 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
   9815  1.281   msaitoh 		/* Any PHY wasn't find */
   9816  1.388   msaitoh 		ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
   9817  1.388   msaitoh 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
   9818  1.281   msaitoh 		sc->sc_phytype = WMPHY_NONE;
   9819  1.281   msaitoh 	} else {
   9820  1.475   msaitoh 		struct mii_softc *child = LIST_FIRST(&mii->mii_phys);
   9821  1.475   msaitoh 
   9822  1.281   msaitoh 		/*
   9823  1.475   msaitoh 		 * PHY Found! Check PHY type again by the second call of
   9824  1.527   msaitoh 		 * wm_gmii_setup_phytype.
   9825  1.281   msaitoh 		 */
   9826  1.475   msaitoh 		wm_gmii_setup_phytype(sc, child->mii_mpd_oui,
   9827  1.475   msaitoh 		    child->mii_mpd_model);
   9828    1.1   thorpej 
   9829  1.281   msaitoh 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
   9830  1.281   msaitoh 	}
   9831    1.1   thorpej }
   9832    1.1   thorpej 
   9833    1.1   thorpej /*
   9834  1.281   msaitoh  * wm_gmii_mediachange:	[ifmedia interface function]
   9835    1.1   thorpej  *
   9836  1.281   msaitoh  *	Set hardware to newly-selected media on a 1000BASE-T device.
   9837    1.1   thorpej  */
   9838   1.47   thorpej static int
   9839  1.281   msaitoh wm_gmii_mediachange(struct ifnet *ifp)
   9840    1.1   thorpej {
   9841    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   9842    1.1   thorpej 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   9843  1.281   msaitoh 	int rc;
   9844    1.1   thorpej 
   9845  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   9846  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   9847  1.281   msaitoh 	if ((ifp->if_flags & IFF_UP) == 0)
   9848  1.279   msaitoh 		return 0;
   9849  1.279   msaitoh 
   9850  1.517   msaitoh 	/* Disable D0 LPLU. */
   9851  1.519   msaitoh 	wm_lplu_d0_disable(sc);
   9852  1.517   msaitoh 
   9853  1.281   msaitoh 	sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
   9854  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   9855  1.281   msaitoh 	if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   9856  1.281   msaitoh 	    || (sc->sc_type > WM_T_82543)) {
   9857  1.281   msaitoh 		sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX);
   9858  1.134   msaitoh 	} else {
   9859  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_ASDE;
   9860  1.281   msaitoh 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
   9861  1.281   msaitoh 		if (ife->ifm_media & IFM_FDX)
   9862  1.281   msaitoh 			sc->sc_ctrl |= CTRL_FD;
   9863  1.281   msaitoh 		switch (IFM_SUBTYPE(ife->ifm_media)) {
   9864  1.281   msaitoh 		case IFM_10_T:
   9865  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_10;
   9866  1.281   msaitoh 			break;
   9867  1.281   msaitoh 		case IFM_100_TX:
   9868  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_100;
   9869  1.281   msaitoh 			break;
   9870  1.281   msaitoh 		case IFM_1000_T:
   9871  1.281   msaitoh 			sc->sc_ctrl |= CTRL_SPEED_1000;
   9872  1.281   msaitoh 			break;
   9873  1.281   msaitoh 		default:
   9874  1.281   msaitoh 			panic("wm_gmii_mediachange: bad media 0x%x",
   9875  1.281   msaitoh 			    ife->ifm_media);
   9876  1.281   msaitoh 		}
   9877  1.134   msaitoh 	}
   9878  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   9879  1.515   msaitoh 	CSR_WRITE_FLUSH(sc);
   9880  1.281   msaitoh 	if (sc->sc_type <= WM_T_82543)
   9881  1.281   msaitoh 		wm_gmii_reset(sc);
   9882  1.281   msaitoh 
   9883  1.281   msaitoh 	if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
   9884  1.281   msaitoh 		return 0;
   9885  1.281   msaitoh 	return rc;
   9886  1.281   msaitoh }
   9887    1.1   thorpej 
   9888  1.324   msaitoh /*
   9889  1.324   msaitoh  * wm_gmii_mediastatus:	[ifmedia interface function]
   9890  1.324   msaitoh  *
   9891  1.324   msaitoh  *	Get the current interface media status on a 1000BASE-T device.
   9892  1.324   msaitoh  */
   9893  1.324   msaitoh static void
   9894  1.324   msaitoh wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   9895  1.324   msaitoh {
   9896  1.324   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   9897  1.324   msaitoh 
   9898  1.324   msaitoh 	ether_mediastatus(ifp, ifmr);
   9899  1.324   msaitoh 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
   9900  1.324   msaitoh 	    | sc->sc_flowflags;
   9901  1.324   msaitoh }
   9902  1.324   msaitoh 
   9903  1.281   msaitoh #define	MDI_IO		CTRL_SWDPIN(2)
   9904  1.281   msaitoh #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
   9905  1.281   msaitoh #define	MDI_CLK		CTRL_SWDPIN(3)
   9906    1.1   thorpej 
   9907  1.281   msaitoh static void
   9908  1.281   msaitoh wm_i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
   9909  1.281   msaitoh {
   9910  1.281   msaitoh 	uint32_t i, v;
   9911  1.134   msaitoh 
   9912  1.281   msaitoh 	v = CSR_READ(sc, WMREG_CTRL);
   9913  1.388   msaitoh 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   9914  1.281   msaitoh 	v |= MDI_DIR | CTRL_SWDPIO(3);
   9915  1.134   msaitoh 
   9916  1.281   msaitoh 	for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
   9917  1.281   msaitoh 		if (data & i)
   9918  1.281   msaitoh 			v |= MDI_IO;
   9919  1.281   msaitoh 		else
   9920  1.281   msaitoh 			v &= ~MDI_IO;
   9921  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9922  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9923  1.281   msaitoh 		delay(10);
   9924  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9925  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9926  1.281   msaitoh 		delay(10);
   9927  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9928  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9929  1.281   msaitoh 		delay(10);
   9930  1.281   msaitoh 	}
   9931  1.281   msaitoh }
   9932  1.134   msaitoh 
   9933  1.281   msaitoh static uint32_t
   9934  1.281   msaitoh wm_i82543_mii_recvbits(struct wm_softc *sc)
   9935  1.281   msaitoh {
   9936  1.281   msaitoh 	uint32_t v, i, data = 0;
   9937    1.1   thorpej 
   9938  1.281   msaitoh 	v = CSR_READ(sc, WMREG_CTRL);
   9939  1.388   msaitoh 	v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   9940  1.281   msaitoh 	v |= CTRL_SWDPIO(3);
   9941  1.134   msaitoh 
   9942  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9943  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9944  1.281   msaitoh 	delay(10);
   9945  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9946  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9947  1.281   msaitoh 	delay(10);
   9948  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9949  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9950  1.281   msaitoh 	delay(10);
   9951  1.173   msaitoh 
   9952  1.281   msaitoh 	for (i = 0; i < 16; i++) {
   9953  1.281   msaitoh 		data <<= 1;
   9954  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9955  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9956  1.281   msaitoh 		delay(10);
   9957  1.281   msaitoh 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
   9958  1.281   msaitoh 			data |= 1;
   9959  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, v);
   9960  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   9961  1.281   msaitoh 		delay(10);
   9962    1.1   thorpej 	}
   9963    1.1   thorpej 
   9964  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   9965  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9966  1.281   msaitoh 	delay(10);
   9967  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, v);
   9968  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   9969  1.281   msaitoh 	delay(10);
   9970    1.1   thorpej 
   9971  1.281   msaitoh 	return data;
   9972    1.1   thorpej }
   9973    1.1   thorpej 
   9974  1.281   msaitoh #undef MDI_IO
   9975  1.281   msaitoh #undef MDI_DIR
   9976  1.281   msaitoh #undef MDI_CLK
   9977  1.281   msaitoh 
   9978    1.1   thorpej /*
   9979  1.281   msaitoh  * wm_gmii_i82543_readreg:	[mii interface function]
   9980    1.1   thorpej  *
   9981  1.281   msaitoh  *	Read a PHY register on the GMII (i82543 version).
   9982    1.1   thorpej  */
   9983  1.281   msaitoh static int
   9984  1.521   msaitoh wm_gmii_i82543_readreg(device_t dev, int phy, int reg)
   9985    1.1   thorpej {
   9986  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   9987  1.281   msaitoh 	int rv;
   9988    1.1   thorpej 
   9989  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
   9990  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, reg | (phy << 5) |
   9991  1.281   msaitoh 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
   9992  1.281   msaitoh 	rv = wm_i82543_mii_recvbits(sc) & 0xffff;
   9993    1.1   thorpej 
   9994  1.388   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
   9995  1.521   msaitoh 	    device_xname(dev), phy, reg, rv));
   9996  1.173   msaitoh 
   9997  1.281   msaitoh 	return rv;
   9998    1.1   thorpej }
   9999    1.1   thorpej 
   10000    1.1   thorpej /*
   10001  1.281   msaitoh  * wm_gmii_i82543_writereg:	[mii interface function]
   10002    1.1   thorpej  *
   10003  1.281   msaitoh  *	Write a PHY register on the GMII (i82543 version).
   10004    1.1   thorpej  */
   10005   1.47   thorpej static void
   10006  1.521   msaitoh wm_gmii_i82543_writereg(device_t dev, int phy, int reg, int val)
   10007    1.1   thorpej {
   10008  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10009    1.1   thorpej 
   10010  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, 0xffffffffU, 32);
   10011  1.281   msaitoh 	wm_i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
   10012  1.281   msaitoh 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
   10013  1.281   msaitoh 	    (MII_COMMAND_START << 30), 32);
   10014  1.281   msaitoh }
   10015  1.272     ozaki 
   10016  1.281   msaitoh /*
   10017  1.424   msaitoh  * wm_gmii_mdic_readreg:	[mii interface function]
   10018  1.281   msaitoh  *
   10019  1.281   msaitoh  *	Read a PHY register on the GMII.
   10020  1.281   msaitoh  */
   10021  1.281   msaitoh static int
   10022  1.521   msaitoh wm_gmii_mdic_readreg(device_t dev, int phy, int reg)
   10023  1.281   msaitoh {
   10024  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10025  1.281   msaitoh 	uint32_t mdic = 0;
   10026  1.281   msaitoh 	int i, rv;
   10027  1.279   msaitoh 
   10028  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   10029  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   10030  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   10031  1.522   msaitoh 		reg &= MII_ADDRMASK;
   10032  1.522   msaitoh 	}
   10033  1.522   msaitoh 
   10034  1.281   msaitoh 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
   10035  1.281   msaitoh 	    MDIC_REGADD(reg));
   10036    1.1   thorpej 
   10037  1.281   msaitoh 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
   10038  1.281   msaitoh 		mdic = CSR_READ(sc, WMREG_MDIC);
   10039  1.281   msaitoh 		if (mdic & MDIC_READY)
   10040  1.281   msaitoh 			break;
   10041  1.327   msaitoh 		delay(50);
   10042    1.1   thorpej 	}
   10043    1.1   thorpej 
   10044  1.281   msaitoh 	if ((mdic & MDIC_READY) == 0) {
   10045  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
   10046  1.521   msaitoh 		    device_xname(dev), phy, reg);
   10047  1.281   msaitoh 		rv = 0;
   10048  1.281   msaitoh 	} else if (mdic & MDIC_E) {
   10049  1.281   msaitoh #if 0 /* This is normal if no PHY is present. */
   10050  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
   10051  1.521   msaitoh 		    device_xname(dev), phy, reg);
   10052  1.281   msaitoh #endif
   10053  1.281   msaitoh 		rv = 0;
   10054  1.281   msaitoh 	} else {
   10055  1.281   msaitoh 		rv = MDIC_DATA(mdic);
   10056  1.281   msaitoh 		if (rv == 0xffff)
   10057  1.281   msaitoh 			rv = 0;
   10058  1.173   msaitoh 	}
   10059  1.173   msaitoh 
   10060  1.281   msaitoh 	return rv;
   10061    1.1   thorpej }
   10062    1.1   thorpej 
   10063    1.1   thorpej /*
   10064  1.424   msaitoh  * wm_gmii_mdic_writereg:	[mii interface function]
   10065    1.1   thorpej  *
   10066  1.281   msaitoh  *	Write a PHY register on the GMII.
   10067    1.1   thorpej  */
   10068   1.47   thorpej static void
   10069  1.521   msaitoh wm_gmii_mdic_writereg(device_t dev, int phy, int reg, int val)
   10070    1.1   thorpej {
   10071  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10072  1.281   msaitoh 	uint32_t mdic = 0;
   10073  1.281   msaitoh 	int i;
   10074  1.281   msaitoh 
   10075  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   10076  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   10077  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   10078  1.522   msaitoh 		reg &= MII_ADDRMASK;
   10079  1.522   msaitoh 	}
   10080  1.522   msaitoh 
   10081  1.281   msaitoh 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
   10082  1.281   msaitoh 	    MDIC_REGADD(reg) | MDIC_DATA(val));
   10083    1.1   thorpej 
   10084  1.281   msaitoh 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
   10085  1.281   msaitoh 		mdic = CSR_READ(sc, WMREG_MDIC);
   10086  1.281   msaitoh 		if (mdic & MDIC_READY)
   10087  1.281   msaitoh 			break;
   10088  1.327   msaitoh 		delay(50);
   10089  1.127    bouyer 	}
   10090    1.1   thorpej 
   10091  1.281   msaitoh 	if ((mdic & MDIC_READY) == 0)
   10092  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n",
   10093  1.521   msaitoh 		    device_xname(dev), phy, reg);
   10094  1.281   msaitoh 	else if (mdic & MDIC_E)
   10095  1.281   msaitoh 		log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n",
   10096  1.521   msaitoh 		    device_xname(dev), phy, reg);
   10097  1.281   msaitoh }
   10098  1.133   msaitoh 
   10099  1.281   msaitoh /*
   10100  1.424   msaitoh  * wm_gmii_i82544_readreg:	[mii interface function]
   10101  1.424   msaitoh  *
   10102  1.424   msaitoh  *	Read a PHY register on the GMII.
   10103  1.424   msaitoh  */
   10104  1.424   msaitoh static int
   10105  1.521   msaitoh wm_gmii_i82544_readreg(device_t dev, int phy, int reg)
   10106  1.424   msaitoh {
   10107  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10108  1.424   msaitoh 	int rv;
   10109  1.424   msaitoh 
   10110  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10111  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10112  1.424   msaitoh 		return 0;
   10113  1.424   msaitoh 	}
   10114  1.522   msaitoh 
   10115  1.522   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   10116  1.522   msaitoh 		switch (sc->sc_phytype) {
   10117  1.522   msaitoh 		case WMPHY_IGP:
   10118  1.522   msaitoh 		case WMPHY_IGP_2:
   10119  1.522   msaitoh 		case WMPHY_IGP_3:
   10120  1.573   msaitoh 			wm_gmii_mdic_writereg(dev, phy, MII_IGPHY_PAGE_SELECT,
   10121  1.573   msaitoh 			    reg);
   10122  1.522   msaitoh 			break;
   10123  1.522   msaitoh 		default:
   10124  1.522   msaitoh #ifdef WM_DEBUG
   10125  1.522   msaitoh 			device_printf(dev, "%s: PHYTYPE = 0x%x, addr = %02x\n",
   10126  1.522   msaitoh 			    __func__, sc->sc_phytype, reg);
   10127  1.522   msaitoh #endif
   10128  1.522   msaitoh 			break;
   10129  1.522   msaitoh 		}
   10130  1.522   msaitoh 	}
   10131  1.522   msaitoh 
   10132  1.522   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   10133  1.424   msaitoh 	sc->phy.release(sc);
   10134  1.424   msaitoh 
   10135  1.424   msaitoh 	return rv;
   10136  1.424   msaitoh }
   10137  1.424   msaitoh 
   10138  1.424   msaitoh /*
   10139  1.424   msaitoh  * wm_gmii_i82544_writereg:	[mii interface function]
   10140  1.424   msaitoh  *
   10141  1.424   msaitoh  *	Write a PHY register on the GMII.
   10142  1.424   msaitoh  */
   10143  1.424   msaitoh static void
   10144  1.521   msaitoh wm_gmii_i82544_writereg(device_t dev, int phy, int reg, int val)
   10145  1.424   msaitoh {
   10146  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10147  1.424   msaitoh 
   10148  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10149  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10150  1.521   msaitoh 		return;
   10151  1.424   msaitoh 	}
   10152  1.522   msaitoh 
   10153  1.522   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   10154  1.522   msaitoh 		switch (sc->sc_phytype) {
   10155  1.522   msaitoh 		case WMPHY_IGP:
   10156  1.522   msaitoh 		case WMPHY_IGP_2:
   10157  1.522   msaitoh 		case WMPHY_IGP_3:
   10158  1.573   msaitoh 			wm_gmii_mdic_writereg(dev, phy, MII_IGPHY_PAGE_SELECT,
   10159  1.573   msaitoh 			    reg);
   10160  1.522   msaitoh 			break;
   10161  1.522   msaitoh 		default:
   10162  1.522   msaitoh #ifdef WM_DEBUG
   10163  1.522   msaitoh 			device_printf(dev, "%s: PHYTYPE == 0x%x, addr = %02x",
   10164  1.522   msaitoh 			    __func__, sc->sc_phytype, reg);
   10165  1.522   msaitoh #endif
   10166  1.522   msaitoh 			break;
   10167  1.522   msaitoh 		}
   10168  1.522   msaitoh 	}
   10169  1.522   msaitoh 
   10170  1.522   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   10171  1.424   msaitoh 	sc->phy.release(sc);
   10172  1.424   msaitoh }
   10173  1.424   msaitoh 
   10174  1.424   msaitoh /*
   10175  1.281   msaitoh  * wm_gmii_i80003_readreg:	[mii interface function]
   10176  1.281   msaitoh  *
   10177  1.281   msaitoh  *	Read a PHY register on the kumeran
   10178  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10179  1.281   msaitoh  * ressource ...
   10180  1.281   msaitoh  */
   10181  1.281   msaitoh static int
   10182  1.521   msaitoh wm_gmii_i80003_readreg(device_t dev, int phy, int reg)
   10183  1.281   msaitoh {
   10184  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10185  1.531   msaitoh 	int page_select, temp;
   10186  1.281   msaitoh 	int rv;
   10187    1.1   thorpej 
   10188  1.281   msaitoh 	if (phy != 1) /* only one PHY on kumeran bus */
   10189  1.281   msaitoh 		return 0;
   10190    1.1   thorpej 
   10191  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10192  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10193  1.281   msaitoh 		return 0;
   10194    1.1   thorpej 	}
   10195  1.186   msaitoh 
   10196  1.531   msaitoh 	if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG)
   10197  1.531   msaitoh 		page_select = GG82563_PHY_PAGE_SELECT;
   10198  1.531   msaitoh 	else {
   10199  1.531   msaitoh 		/*
   10200  1.531   msaitoh 		 * Use Alternative Page Select register to access registers
   10201  1.531   msaitoh 		 * 30 and 31.
   10202  1.531   msaitoh 		 */
   10203  1.531   msaitoh 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
   10204  1.189   msaitoh 	}
   10205  1.531   msaitoh 	temp = (uint16_t)reg >> GG82563_PAGE_SHIFT;
   10206  1.531   msaitoh 	wm_gmii_mdic_writereg(dev, phy, page_select, temp);
   10207  1.531   msaitoh 	if ((sc->sc_flags & WM_F_80003_MDIC_WA) != 0) {
   10208  1.531   msaitoh 		/*
   10209  1.531   msaitoh 		 * Wait more 200us for a bug of the ready bit in the MDIC
   10210  1.531   msaitoh 		 * register.
   10211  1.531   msaitoh 		 */
   10212  1.531   msaitoh 		delay(200);
   10213  1.531   msaitoh 		if (wm_gmii_mdic_readreg(dev, phy, page_select) != temp) {
   10214  1.531   msaitoh 			device_printf(dev, "%s failed\n", __func__);
   10215  1.531   msaitoh 			rv = 0; /* XXX */
   10216  1.531   msaitoh 			goto out;
   10217  1.531   msaitoh 		}
   10218  1.531   msaitoh 		rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   10219  1.531   msaitoh 		delay(200);
   10220  1.531   msaitoh 	} else
   10221  1.531   msaitoh 		rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   10222  1.531   msaitoh 
   10223  1.531   msaitoh out:
   10224  1.424   msaitoh 	sc->phy.release(sc);
   10225  1.281   msaitoh 	return rv;
   10226  1.281   msaitoh }
   10227  1.190   msaitoh 
   10228  1.281   msaitoh /*
   10229  1.281   msaitoh  * wm_gmii_i80003_writereg:	[mii interface function]
   10230  1.281   msaitoh  *
   10231  1.281   msaitoh  *	Write a PHY register on the kumeran.
   10232  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10233  1.281   msaitoh  * ressource ...
   10234  1.281   msaitoh  */
   10235  1.281   msaitoh static void
   10236  1.521   msaitoh wm_gmii_i80003_writereg(device_t dev, int phy, int reg, int val)
   10237  1.281   msaitoh {
   10238  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10239  1.531   msaitoh 	int page_select, temp;
   10240  1.221   msaitoh 
   10241  1.281   msaitoh 	if (phy != 1) /* only one PHY on kumeran bus */
   10242  1.281   msaitoh 		return;
   10243  1.190   msaitoh 
   10244  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10245  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10246  1.281   msaitoh 		return;
   10247  1.281   msaitoh 	}
   10248  1.192   msaitoh 
   10249  1.531   msaitoh 	if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG)
   10250  1.531   msaitoh 		page_select = GG82563_PHY_PAGE_SELECT;
   10251  1.531   msaitoh 	else {
   10252  1.531   msaitoh 		/*
   10253  1.531   msaitoh 		 * Use Alternative Page Select register to access registers
   10254  1.531   msaitoh 		 * 30 and 31.
   10255  1.531   msaitoh 		 */
   10256  1.531   msaitoh 		page_select = GG82563_PHY_PAGE_SELECT_ALT;
   10257  1.189   msaitoh 	}
   10258  1.531   msaitoh 	temp = (uint16_t)reg >> GG82563_PAGE_SHIFT;
   10259  1.531   msaitoh 	wm_gmii_mdic_writereg(dev, phy, page_select, temp);
   10260  1.531   msaitoh 	if ((sc->sc_flags & WM_F_80003_MDIC_WA) != 0) {
   10261  1.531   msaitoh 		/*
   10262  1.531   msaitoh 		 * Wait more 200us for a bug of the ready bit in the MDIC
   10263  1.531   msaitoh 		 * register.
   10264  1.531   msaitoh 		 */
   10265  1.531   msaitoh 		delay(200);
   10266  1.531   msaitoh 		if (wm_gmii_mdic_readreg(dev, phy, page_select) != temp) {
   10267  1.531   msaitoh 			device_printf(dev, "%s failed\n", __func__);
   10268  1.531   msaitoh 			goto out;
   10269  1.531   msaitoh 		}
   10270  1.531   msaitoh 		wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   10271  1.531   msaitoh 		delay(200);
   10272  1.531   msaitoh 	} else
   10273  1.531   msaitoh 		wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   10274  1.281   msaitoh 
   10275  1.531   msaitoh out:
   10276  1.424   msaitoh 	sc->phy.release(sc);
   10277    1.1   thorpej }
   10278    1.1   thorpej 
   10279    1.1   thorpej /*
   10280  1.281   msaitoh  * wm_gmii_bm_readreg:	[mii interface function]
   10281  1.265   msaitoh  *
   10282  1.281   msaitoh  *	Read a PHY register on the kumeran
   10283  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10284  1.281   msaitoh  * ressource ...
   10285  1.265   msaitoh  */
   10286  1.265   msaitoh static int
   10287  1.521   msaitoh wm_gmii_bm_readreg(device_t dev, int phy, int reg)
   10288  1.265   msaitoh {
   10289  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10290  1.435   msaitoh 	uint16_t page = reg >> BME1000_PAGE_SHIFT;
   10291  1.435   msaitoh 	uint16_t val;
   10292  1.281   msaitoh 	int rv;
   10293  1.265   msaitoh 
   10294  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10295  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10296  1.281   msaitoh 		return 0;
   10297  1.281   msaitoh 	}
   10298  1.265   msaitoh 
   10299  1.435   msaitoh 	if ((sc->sc_type != WM_T_82574) && (sc->sc_type != WM_T_82583))
   10300  1.435   msaitoh 		phy = ((page >= 768) || ((page == 0) && (reg == 25))
   10301  1.435   msaitoh 		    || (reg == 31)) ? 1 : phy;
   10302  1.435   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10303  1.435   msaitoh 	if (page == BM_WUC_PAGE) {
   10304  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &val, 1);
   10305  1.435   msaitoh 		rv = val;
   10306  1.435   msaitoh 		goto release;
   10307  1.435   msaitoh 	}
   10308  1.435   msaitoh 
   10309  1.281   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   10310  1.435   msaitoh 		if ((phy == 1) && (sc->sc_type != WM_T_82574)
   10311  1.435   msaitoh 		    && (sc->sc_type != WM_T_82583))
   10312  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   10313  1.435   msaitoh 			    MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
   10314  1.281   msaitoh 		else
   10315  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   10316  1.435   msaitoh 			    BME1000_PHY_PAGE_SELECT, page);
   10317  1.265   msaitoh 	}
   10318  1.265   msaitoh 
   10319  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK);
   10320  1.435   msaitoh 
   10321  1.435   msaitoh release:
   10322  1.424   msaitoh 	sc->phy.release(sc);
   10323  1.281   msaitoh 	return rv;
   10324  1.265   msaitoh }
   10325  1.265   msaitoh 
   10326  1.265   msaitoh /*
   10327  1.281   msaitoh  * wm_gmii_bm_writereg:	[mii interface function]
   10328    1.1   thorpej  *
   10329  1.281   msaitoh  *	Write a PHY register on the kumeran.
   10330  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10331  1.281   msaitoh  * ressource ...
   10332    1.1   thorpej  */
   10333   1.47   thorpej static void
   10334  1.521   msaitoh wm_gmii_bm_writereg(device_t dev, int phy, int reg, int val)
   10335  1.281   msaitoh {
   10336  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10337  1.435   msaitoh 	uint16_t page = reg >> BME1000_PAGE_SHIFT;
   10338  1.281   msaitoh 
   10339  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10340  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10341  1.281   msaitoh 		return;
   10342  1.281   msaitoh 	}
   10343  1.281   msaitoh 
   10344  1.435   msaitoh 	if ((sc->sc_type != WM_T_82574) && (sc->sc_type != WM_T_82583))
   10345  1.435   msaitoh 		phy = ((page >= 768) || ((page == 0) && (reg == 25))
   10346  1.435   msaitoh 		    || (reg == 31)) ? 1 : phy;
   10347  1.435   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10348  1.435   msaitoh 	if (page == BM_WUC_PAGE) {
   10349  1.435   msaitoh 		uint16_t tmp;
   10350  1.435   msaitoh 
   10351  1.435   msaitoh 		tmp = val;
   10352  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &tmp, 0);
   10353  1.435   msaitoh 		goto release;
   10354  1.435   msaitoh 	}
   10355  1.435   msaitoh 
   10356  1.281   msaitoh 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
   10357  1.435   msaitoh 		if ((phy == 1) && (sc->sc_type != WM_T_82574)
   10358  1.435   msaitoh 		    && (sc->sc_type != WM_T_82583))
   10359  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   10360  1.435   msaitoh 			    MII_IGPHY_PAGE_SELECT, page << BME1000_PAGE_SHIFT);
   10361  1.281   msaitoh 		else
   10362  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, phy,
   10363  1.435   msaitoh 			    BME1000_PHY_PAGE_SELECT, page);
   10364  1.281   msaitoh 	}
   10365  1.281   msaitoh 
   10366  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);
   10367  1.435   msaitoh 
   10368  1.435   msaitoh release:
   10369  1.424   msaitoh 	sc->phy.release(sc);
   10370  1.281   msaitoh }
   10371  1.281   msaitoh 
   10372  1.281   msaitoh static void
   10373  1.521   msaitoh wm_access_phy_wakeup_reg_bm(device_t dev, int offset, int16_t *val, int rd)
   10374    1.1   thorpej {
   10375  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10376  1.281   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(offset);
   10377  1.441   msaitoh 	uint16_t wuce, reg;
   10378  1.281   msaitoh 
   10379  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   10380  1.521   msaitoh 		device_xname(dev), __func__));
   10381  1.281   msaitoh 	/* XXX Gig must be disabled for MDIO accesses to page 800 */
   10382  1.281   msaitoh 	if (sc->sc_type == WM_T_PCH) {
   10383  1.281   msaitoh 		/* XXX e1000 driver do nothing... why? */
   10384  1.281   msaitoh 	}
   10385  1.281   msaitoh 
   10386  1.441   msaitoh 	/*
   10387  1.441   msaitoh 	 * 1) Enable PHY wakeup register first.
   10388  1.441   msaitoh 	 * See e1000_enable_phy_wakeup_reg_access_bm().
   10389  1.441   msaitoh 	 */
   10390  1.441   msaitoh 
   10391  1.281   msaitoh 	/* Set page 769 */
   10392  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10393  1.281   msaitoh 	    BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
   10394  1.281   msaitoh 
   10395  1.441   msaitoh 	/* Read WUCE and save it */
   10396  1.521   msaitoh 	wuce = wm_gmii_mdic_readreg(dev, 1, BM_WUC_ENABLE_REG);
   10397  1.281   msaitoh 
   10398  1.441   msaitoh 	reg = wuce | BM_WUC_ENABLE_BIT;
   10399  1.441   msaitoh 	reg &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
   10400  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ENABLE_REG, reg);
   10401  1.281   msaitoh 
   10402  1.281   msaitoh 	/* Select page 800 */
   10403  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10404  1.281   msaitoh 	    BM_WUC_PAGE << BME1000_PAGE_SHIFT);
   10405    1.1   thorpej 
   10406  1.441   msaitoh 	/*
   10407  1.441   msaitoh 	 * 2) Access PHY wakeup register.
   10408  1.441   msaitoh 	 * See e1000_access_phy_wakeup_reg_bm.
   10409  1.441   msaitoh 	 */
   10410  1.441   msaitoh 
   10411  1.281   msaitoh 	/* Write page 800 */
   10412  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ADDRESS_OPCODE, regnum);
   10413    1.1   thorpej 
   10414  1.281   msaitoh 	if (rd)
   10415  1.521   msaitoh 		*val = wm_gmii_mdic_readreg(dev, 1, BM_WUC_DATA_OPCODE);
   10416  1.127    bouyer 	else
   10417  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, 1, BM_WUC_DATA_OPCODE, *val);
   10418  1.281   msaitoh 
   10419  1.441   msaitoh 	/*
   10420  1.441   msaitoh 	 * 3) Disable PHY wakeup register.
   10421  1.441   msaitoh 	 * See e1000_disable_phy_wakeup_reg_access_bm().
   10422  1.441   msaitoh 	 */
   10423  1.281   msaitoh 	/* Set page 769 */
   10424  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10425  1.281   msaitoh 	    BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
   10426  1.281   msaitoh 
   10427  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, 1, BM_WUC_ENABLE_REG, wuce);
   10428  1.281   msaitoh }
   10429  1.281   msaitoh 
   10430  1.281   msaitoh /*
   10431  1.281   msaitoh  * wm_gmii_hv_readreg:	[mii interface function]
   10432  1.281   msaitoh  *
   10433  1.281   msaitoh  *	Read a PHY register on the kumeran
   10434  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10435  1.281   msaitoh  * ressource ...
   10436  1.281   msaitoh  */
   10437  1.281   msaitoh static int
   10438  1.521   msaitoh wm_gmii_hv_readreg(device_t dev, int phy, int reg)
   10439  1.281   msaitoh {
   10440  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10441  1.281   msaitoh 	int rv;
   10442  1.281   msaitoh 
   10443  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   10444  1.521   msaitoh 		device_xname(dev), __func__));
   10445  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10446  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10447  1.281   msaitoh 		return 0;
   10448  1.281   msaitoh 	}
   10449  1.281   msaitoh 
   10450  1.521   msaitoh 	rv = wm_gmii_hv_readreg_locked(dev, phy, reg);
   10451  1.424   msaitoh 	sc->phy.release(sc);
   10452  1.424   msaitoh 	return rv;
   10453  1.424   msaitoh }
   10454  1.424   msaitoh 
   10455  1.424   msaitoh static int
   10456  1.521   msaitoh wm_gmii_hv_readreg_locked(device_t dev, int phy, int reg)
   10457  1.424   msaitoh {
   10458  1.424   msaitoh 	uint16_t page = BM_PHY_REG_PAGE(reg);
   10459  1.424   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(reg);
   10460  1.424   msaitoh 	uint16_t val;
   10461  1.424   msaitoh 	int rv;
   10462  1.424   msaitoh 
   10463  1.437   msaitoh 	phy = (page >= HV_INTC_FC_PAGE_START) ? 1 : phy;
   10464    1.1   thorpej 
   10465  1.281   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10466  1.281   msaitoh 	if (page == BM_WUC_PAGE) {
   10467  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &val, 1);
   10468  1.281   msaitoh 		return val;
   10469  1.281   msaitoh 	}
   10470    1.1   thorpej 
   10471  1.244   msaitoh 	/*
   10472  1.281   msaitoh 	 * Lower than page 768 works differently than the rest so it has its
   10473  1.281   msaitoh 	 * own func
   10474  1.244   msaitoh 	 */
   10475  1.281   msaitoh 	if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
   10476  1.281   msaitoh 		printf("gmii_hv_readreg!!!\n");
   10477  1.281   msaitoh 		return 0;
   10478  1.281   msaitoh 	}
   10479  1.281   msaitoh 
   10480  1.528   msaitoh 	/*
   10481  1.528   msaitoh 	 * XXX I21[789] documents say that the SMBus Address register is at
   10482  1.528   msaitoh 	 * PHY address 01, Page 0 (not 768), Register 26.
   10483  1.528   msaitoh 	 */
   10484  1.528   msaitoh 	if (page == HV_INTC_FC_PAGE_START)
   10485  1.528   msaitoh 		page = 0;
   10486  1.528   msaitoh 
   10487  1.281   msaitoh 	if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
   10488  1.521   msaitoh 		wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10489  1.281   msaitoh 		    page << BME1000_PAGE_SHIFT);
   10490    1.1   thorpej 	}
   10491    1.1   thorpej 
   10492  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, regnum & MII_ADDRMASK);
   10493  1.281   msaitoh 	return rv;
   10494  1.281   msaitoh }
   10495    1.1   thorpej 
   10496  1.281   msaitoh /*
   10497  1.281   msaitoh  * wm_gmii_hv_writereg:	[mii interface function]
   10498  1.281   msaitoh  *
   10499  1.281   msaitoh  *	Write a PHY register on the kumeran.
   10500  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10501  1.281   msaitoh  * ressource ...
   10502  1.281   msaitoh  */
   10503  1.281   msaitoh static void
   10504  1.521   msaitoh wm_gmii_hv_writereg(device_t dev, int phy, int reg, int val)
   10505  1.281   msaitoh {
   10506  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10507    1.1   thorpej 
   10508  1.434   msaitoh 	DPRINTF(WM_DEBUG_GMII, ("%s: %s called\n",
   10509  1.521   msaitoh 		device_xname(dev), __func__));
   10510  1.425   msaitoh 
   10511  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10512  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10513  1.281   msaitoh 		return;
   10514  1.281   msaitoh 	}
   10515  1.208   msaitoh 
   10516  1.521   msaitoh 	wm_gmii_hv_writereg_locked(dev, phy, reg, val);
   10517  1.424   msaitoh 	sc->phy.release(sc);
   10518  1.424   msaitoh }
   10519  1.424   msaitoh 
   10520  1.424   msaitoh static void
   10521  1.521   msaitoh wm_gmii_hv_writereg_locked(device_t dev, int phy, int reg, int val)
   10522  1.424   msaitoh {
   10523  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10524  1.424   msaitoh 	uint16_t page = BM_PHY_REG_PAGE(reg);
   10525  1.424   msaitoh 	uint16_t regnum = BM_PHY_REG_NUM(reg);
   10526  1.424   msaitoh 
   10527  1.437   msaitoh 	phy = (page >= HV_INTC_FC_PAGE_START) ? 1 : phy;
   10528  1.265   msaitoh 
   10529  1.281   msaitoh 	/* Page 800 works differently than the rest so it has its own func */
   10530  1.281   msaitoh 	if (page == BM_WUC_PAGE) {
   10531  1.281   msaitoh 		uint16_t tmp;
   10532  1.208   msaitoh 
   10533  1.281   msaitoh 		tmp = val;
   10534  1.521   msaitoh 		wm_access_phy_wakeup_reg_bm(dev, reg, &tmp, 0);
   10535  1.281   msaitoh 		return;
   10536  1.208   msaitoh 	}
   10537  1.184   msaitoh 
   10538  1.244   msaitoh 	/*
   10539  1.281   msaitoh 	 * Lower than page 768 works differently than the rest so it has its
   10540  1.281   msaitoh 	 * own func
   10541  1.244   msaitoh 	 */
   10542  1.281   msaitoh 	if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
   10543  1.281   msaitoh 		printf("gmii_hv_writereg!!!\n");
   10544  1.281   msaitoh 		return;
   10545  1.221   msaitoh 	}
   10546  1.244   msaitoh 
   10547  1.437   msaitoh 	{
   10548  1.437   msaitoh 		/*
   10549  1.528   msaitoh 		 * XXX I21[789] documents say that the SMBus Address register
   10550  1.528   msaitoh 		 * is at PHY address 01, Page 0 (not 768), Register 26.
   10551  1.528   msaitoh 		 */
   10552  1.528   msaitoh 		if (page == HV_INTC_FC_PAGE_START)
   10553  1.528   msaitoh 			page = 0;
   10554  1.528   msaitoh 
   10555  1.528   msaitoh 		/*
   10556  1.437   msaitoh 		 * XXX Workaround MDIO accesses being disabled after entering
   10557  1.437   msaitoh 		 * IEEE Power Down (whenever bit 11 of the PHY control
   10558  1.437   msaitoh 		 * register is set)
   10559  1.437   msaitoh 		 */
   10560  1.437   msaitoh 		if (sc->sc_phytype == WMPHY_82578) {
   10561  1.437   msaitoh 			struct mii_softc *child;
   10562  1.437   msaitoh 
   10563  1.437   msaitoh 			child = LIST_FIRST(&sc->sc_mii.mii_phys);
   10564  1.437   msaitoh 			if ((child != NULL) && (child->mii_mpd_rev >= 1)
   10565  1.437   msaitoh 			    && (phy == 2) && ((regnum & MII_ADDRMASK) == 0)
   10566  1.437   msaitoh 			    && ((val & (1 << 11)) != 0)) {
   10567  1.437   msaitoh 				printf("XXX need workaround\n");
   10568  1.437   msaitoh 			}
   10569  1.437   msaitoh 		}
   10570  1.184   msaitoh 
   10571  1.437   msaitoh 		if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
   10572  1.521   msaitoh 			wm_gmii_mdic_writereg(dev, 1, MII_IGPHY_PAGE_SELECT,
   10573  1.437   msaitoh 			    page << BME1000_PAGE_SHIFT);
   10574  1.437   msaitoh 		}
   10575  1.281   msaitoh 	}
   10576  1.281   msaitoh 
   10577  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, regnum & MII_ADDRMASK, val);
   10578  1.281   msaitoh }
   10579  1.281   msaitoh 
   10580  1.281   msaitoh /*
   10581  1.281   msaitoh  * wm_gmii_82580_readreg:	[mii interface function]
   10582  1.281   msaitoh  *
   10583  1.281   msaitoh  *	Read a PHY register on the 82580 and I350.
   10584  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10585  1.281   msaitoh  * ressource ...
   10586  1.281   msaitoh  */
   10587  1.281   msaitoh static int
   10588  1.521   msaitoh wm_gmii_82580_readreg(device_t dev, int phy, int reg)
   10589  1.281   msaitoh {
   10590  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10591  1.281   msaitoh 	int rv;
   10592  1.281   msaitoh 
   10593  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10594  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10595  1.281   msaitoh 		return 0;
   10596  1.184   msaitoh 	}
   10597  1.244   msaitoh 
   10598  1.522   msaitoh #ifdef DIAGNOSTIC
   10599  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   10600  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   10601  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   10602  1.522   msaitoh 		reg &= MII_ADDRMASK;
   10603  1.522   msaitoh 	}
   10604  1.522   msaitoh #endif
   10605  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, reg);
   10606  1.202   msaitoh 
   10607  1.424   msaitoh 	sc->phy.release(sc);
   10608  1.281   msaitoh 	return rv;
   10609  1.281   msaitoh }
   10610  1.202   msaitoh 
   10611  1.281   msaitoh /*
   10612  1.281   msaitoh  * wm_gmii_82580_writereg:	[mii interface function]
   10613  1.281   msaitoh  *
   10614  1.281   msaitoh  *	Write a PHY register on the 82580 and I350.
   10615  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10616  1.281   msaitoh  * ressource ...
   10617  1.281   msaitoh  */
   10618  1.281   msaitoh static void
   10619  1.521   msaitoh wm_gmii_82580_writereg(device_t dev, int phy, int reg, int val)
   10620  1.281   msaitoh {
   10621  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10622  1.202   msaitoh 
   10623  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10624  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10625  1.281   msaitoh 		return;
   10626  1.192   msaitoh 	}
   10627  1.281   msaitoh 
   10628  1.522   msaitoh #ifdef DIAGNOSTIC
   10629  1.522   msaitoh 	if (reg > MII_ADDRMASK) {
   10630  1.522   msaitoh 		device_printf(dev, "%s: PHYTYPE = %d, addr 0x%x > 0x1f\n",
   10631  1.522   msaitoh 		    __func__, sc->sc_phytype, reg);
   10632  1.522   msaitoh 		reg &= MII_ADDRMASK;
   10633  1.522   msaitoh 	}
   10634  1.522   msaitoh #endif
   10635  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, reg, val);
   10636  1.281   msaitoh 
   10637  1.424   msaitoh 	sc->phy.release(sc);
   10638    1.1   thorpej }
   10639    1.1   thorpej 
   10640    1.1   thorpej /*
   10641  1.329   msaitoh  * wm_gmii_gs40g_readreg:	[mii interface function]
   10642  1.329   msaitoh  *
   10643  1.329   msaitoh  *	Read a PHY register on the I2100 and I211.
   10644  1.329   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10645  1.329   msaitoh  * ressource ...
   10646  1.329   msaitoh  */
   10647  1.329   msaitoh static int
   10648  1.521   msaitoh wm_gmii_gs40g_readreg(device_t dev, int phy, int reg)
   10649  1.329   msaitoh {
   10650  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10651  1.329   msaitoh 	int page, offset;
   10652  1.329   msaitoh 	int rv;
   10653  1.329   msaitoh 
   10654  1.329   msaitoh 	/* Acquire semaphore */
   10655  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10656  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10657  1.329   msaitoh 		return 0;
   10658  1.329   msaitoh 	}
   10659  1.329   msaitoh 
   10660  1.329   msaitoh 	/* Page select */
   10661  1.329   msaitoh 	page = reg >> GS40G_PAGE_SHIFT;
   10662  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, GS40G_PAGE_SELECT, page);
   10663  1.329   msaitoh 
   10664  1.329   msaitoh 	/* Read reg */
   10665  1.329   msaitoh 	offset = reg & GS40G_OFFSET_MASK;
   10666  1.521   msaitoh 	rv = wm_gmii_mdic_readreg(dev, phy, offset);
   10667  1.329   msaitoh 
   10668  1.424   msaitoh 	sc->phy.release(sc);
   10669  1.329   msaitoh 	return rv;
   10670  1.329   msaitoh }
   10671  1.329   msaitoh 
   10672  1.329   msaitoh /*
   10673  1.329   msaitoh  * wm_gmii_gs40g_writereg:	[mii interface function]
   10674  1.329   msaitoh  *
   10675  1.329   msaitoh  *	Write a PHY register on the I210 and I211.
   10676  1.329   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10677  1.329   msaitoh  * ressource ...
   10678  1.329   msaitoh  */
   10679  1.329   msaitoh static void
   10680  1.521   msaitoh wm_gmii_gs40g_writereg(device_t dev, int phy, int reg, int val)
   10681  1.329   msaitoh {
   10682  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10683  1.329   msaitoh 	int page, offset;
   10684  1.329   msaitoh 
   10685  1.329   msaitoh 	/* Acquire semaphore */
   10686  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10687  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10688  1.329   msaitoh 		return;
   10689  1.329   msaitoh 	}
   10690  1.329   msaitoh 
   10691  1.329   msaitoh 	/* Page select */
   10692  1.329   msaitoh 	page = reg >> GS40G_PAGE_SHIFT;
   10693  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, GS40G_PAGE_SELECT, page);
   10694  1.329   msaitoh 
   10695  1.329   msaitoh 	/* Write reg */
   10696  1.329   msaitoh 	offset = reg & GS40G_OFFSET_MASK;
   10697  1.521   msaitoh 	wm_gmii_mdic_writereg(dev, phy, offset, val);
   10698  1.329   msaitoh 
   10699  1.329   msaitoh 	/* Release semaphore */
   10700  1.424   msaitoh 	sc->phy.release(sc);
   10701  1.329   msaitoh }
   10702  1.329   msaitoh 
   10703  1.329   msaitoh /*
   10704  1.281   msaitoh  * wm_gmii_statchg:	[mii interface function]
   10705    1.1   thorpej  *
   10706  1.281   msaitoh  *	Callback from MII layer when media changes.
   10707    1.1   thorpej  */
   10708   1.47   thorpej static void
   10709  1.281   msaitoh wm_gmii_statchg(struct ifnet *ifp)
   10710    1.1   thorpej {
   10711    1.1   thorpej 	struct wm_softc *sc = ifp->if_softc;
   10712  1.281   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   10713    1.1   thorpej 
   10714  1.281   msaitoh 	sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
   10715  1.281   msaitoh 	sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   10716  1.281   msaitoh 	sc->sc_fcrtl &= ~FCRTL_XONE;
   10717    1.1   thorpej 
   10718  1.281   msaitoh 	/*
   10719  1.281   msaitoh 	 * Get flow control negotiation result.
   10720  1.281   msaitoh 	 */
   10721  1.281   msaitoh 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
   10722  1.281   msaitoh 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
   10723  1.281   msaitoh 		sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
   10724  1.281   msaitoh 		mii->mii_media_active &= ~IFM_ETH_FMASK;
   10725  1.281   msaitoh 	}
   10726    1.1   thorpej 
   10727  1.281   msaitoh 	if (sc->sc_flowflags & IFM_FLOW) {
   10728  1.281   msaitoh 		if (sc->sc_flowflags & IFM_ETH_TXPAUSE) {
   10729  1.281   msaitoh 			sc->sc_ctrl |= CTRL_TFCE;
   10730  1.281   msaitoh 			sc->sc_fcrtl |= FCRTL_XONE;
   10731  1.281   msaitoh 		}
   10732  1.281   msaitoh 		if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
   10733  1.281   msaitoh 			sc->sc_ctrl |= CTRL_RFCE;
   10734  1.281   msaitoh 	}
   10735  1.152    dyoung 
   10736  1.281   msaitoh 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   10737  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10738  1.281   msaitoh 		    ("%s: LINK: statchg: FDX\n", ifp->if_xname));
   10739  1.281   msaitoh 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   10740  1.152    dyoung 	} else {
   10741  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   10742  1.281   msaitoh 		    ("%s: LINK: statchg: HDX\n", ifp->if_xname));
   10743  1.281   msaitoh 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   10744  1.281   msaitoh 	}
   10745  1.281   msaitoh 
   10746  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   10747  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   10748  1.281   msaitoh 	CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
   10749  1.281   msaitoh 						 : WMREG_FCRTL, sc->sc_fcrtl);
   10750  1.281   msaitoh 	if (sc->sc_type == WM_T_80003) {
   10751  1.281   msaitoh 		switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
   10752  1.152    dyoung 		case IFM_1000_T:
   10753  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
   10754  1.281   msaitoh 			    KUMCTRLSTA_HD_CTRL_1000_DEFAULT);
   10755  1.281   msaitoh 			sc->sc_tipg =  TIPG_1000T_80003_DFLT;
   10756  1.152    dyoung 			break;
   10757  1.152    dyoung 		default:
   10758  1.281   msaitoh 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
   10759  1.281   msaitoh 			    KUMCTRLSTA_HD_CTRL_10_100_DEFAULT);
   10760  1.281   msaitoh 			sc->sc_tipg =  TIPG_10_100_80003_DFLT;
   10761  1.281   msaitoh 			break;
   10762  1.127    bouyer 		}
   10763  1.281   msaitoh 		CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   10764  1.127    bouyer 	}
   10765    1.1   thorpej }
   10766    1.1   thorpej 
   10767  1.453   msaitoh /* kumeran related (80003, ICH* and PCH*) */
   10768  1.453   msaitoh 
   10769  1.281   msaitoh /*
   10770  1.281   msaitoh  * wm_kmrn_readreg:
   10771  1.281   msaitoh  *
   10772  1.281   msaitoh  *	Read a kumeran register
   10773  1.281   msaitoh  */
   10774  1.281   msaitoh static int
   10775  1.531   msaitoh wm_kmrn_readreg(struct wm_softc *sc, int reg, uint16_t *val)
   10776    1.1   thorpej {
   10777  1.281   msaitoh 	int rv;
   10778    1.1   thorpej 
   10779  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10780  1.424   msaitoh 		rv = wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10781  1.424   msaitoh 	else
   10782  1.424   msaitoh 		rv = sc->phy.acquire(sc);
   10783  1.424   msaitoh 	if (rv != 0) {
   10784  1.521   msaitoh 		device_printf(sc->sc_dev, "%s: failed to get semaphore\n",
   10785  1.521   msaitoh 		    __func__);
   10786  1.531   msaitoh 		return rv;
   10787    1.1   thorpej 	}
   10788    1.1   thorpej 
   10789  1.531   msaitoh 	rv = wm_kmrn_readreg_locked(sc, reg, val);
   10790  1.424   msaitoh 
   10791  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10792  1.424   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10793  1.424   msaitoh 	else
   10794  1.424   msaitoh 		sc->phy.release(sc);
   10795  1.424   msaitoh 
   10796  1.424   msaitoh 	return rv;
   10797  1.424   msaitoh }
   10798  1.424   msaitoh 
   10799  1.424   msaitoh static int
   10800  1.531   msaitoh wm_kmrn_readreg_locked(struct wm_softc *sc, int reg, uint16_t *val)
   10801  1.424   msaitoh {
   10802  1.424   msaitoh 
   10803  1.281   msaitoh 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
   10804  1.281   msaitoh 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
   10805  1.281   msaitoh 	    KUMCTRLSTA_REN);
   10806  1.266   msaitoh 	CSR_WRITE_FLUSH(sc);
   10807  1.281   msaitoh 	delay(2);
   10808    1.1   thorpej 
   10809  1.531   msaitoh 	*val = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
   10810    1.1   thorpej 
   10811  1.531   msaitoh 	return 0;
   10812    1.1   thorpej }
   10813    1.1   thorpej 
   10814    1.1   thorpej /*
   10815  1.281   msaitoh  * wm_kmrn_writereg:
   10816    1.1   thorpej  *
   10817  1.281   msaitoh  *	Write a kumeran register
   10818    1.1   thorpej  */
   10819  1.531   msaitoh static int
   10820  1.531   msaitoh wm_kmrn_writereg(struct wm_softc *sc, int reg, uint16_t val)
   10821    1.1   thorpej {
   10822  1.424   msaitoh 	int rv;
   10823    1.1   thorpej 
   10824  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10825  1.424   msaitoh 		rv = wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10826  1.424   msaitoh 	else
   10827  1.424   msaitoh 		rv = sc->phy.acquire(sc);
   10828  1.424   msaitoh 	if (rv != 0) {
   10829  1.521   msaitoh 		device_printf(sc->sc_dev, "%s: failed to get semaphore\n",
   10830  1.521   msaitoh 		    __func__);
   10831  1.531   msaitoh 		return rv;
   10832  1.281   msaitoh 	}
   10833    1.1   thorpej 
   10834  1.531   msaitoh 	rv = wm_kmrn_writereg_locked(sc, reg, val);
   10835  1.424   msaitoh 
   10836  1.424   msaitoh 	if (sc->sc_type == WM_T_80003)
   10837  1.424   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
   10838  1.424   msaitoh 	else
   10839  1.424   msaitoh 		sc->phy.release(sc);
   10840  1.531   msaitoh 
   10841  1.531   msaitoh 	return rv;
   10842  1.424   msaitoh }
   10843  1.424   msaitoh 
   10844  1.531   msaitoh static int
   10845  1.531   msaitoh wm_kmrn_writereg_locked(struct wm_softc *sc, int reg, uint16_t val)
   10846  1.424   msaitoh {
   10847  1.424   msaitoh 
   10848  1.281   msaitoh 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
   10849  1.531   msaitoh 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | val);
   10850  1.531   msaitoh 
   10851  1.531   msaitoh 	return 0;
   10852    1.1   thorpej }
   10853    1.1   thorpej 
   10854  1.281   msaitoh /* SGMII related */
   10855  1.281   msaitoh 
   10856    1.1   thorpej /*
   10857  1.281   msaitoh  * wm_sgmii_uses_mdio
   10858    1.1   thorpej  *
   10859  1.281   msaitoh  * Check whether the transaction is to the internal PHY or the external
   10860  1.281   msaitoh  * MDIO interface. Return true if it's MDIO.
   10861  1.281   msaitoh  */
   10862  1.281   msaitoh static bool
   10863  1.281   msaitoh wm_sgmii_uses_mdio(struct wm_softc *sc)
   10864  1.281   msaitoh {
   10865  1.281   msaitoh 	uint32_t reg;
   10866  1.281   msaitoh 	bool ismdio = false;
   10867  1.281   msaitoh 
   10868  1.281   msaitoh 	switch (sc->sc_type) {
   10869  1.281   msaitoh 	case WM_T_82575:
   10870  1.281   msaitoh 	case WM_T_82576:
   10871  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MDIC);
   10872  1.281   msaitoh 		ismdio = ((reg & MDIC_DEST) != 0);
   10873  1.281   msaitoh 		break;
   10874  1.281   msaitoh 	case WM_T_82580:
   10875  1.281   msaitoh 	case WM_T_I350:
   10876  1.281   msaitoh 	case WM_T_I354:
   10877  1.281   msaitoh 	case WM_T_I210:
   10878  1.281   msaitoh 	case WM_T_I211:
   10879  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MDICNFG);
   10880  1.281   msaitoh 		ismdio = ((reg & MDICNFG_DEST) != 0);
   10881  1.281   msaitoh 		break;
   10882  1.281   msaitoh 	default:
   10883  1.281   msaitoh 		break;
   10884  1.281   msaitoh 	}
   10885    1.1   thorpej 
   10886  1.281   msaitoh 	return ismdio;
   10887    1.1   thorpej }
   10888    1.1   thorpej 
   10889    1.1   thorpej /*
   10890  1.281   msaitoh  * wm_sgmii_readreg:	[mii interface function]
   10891    1.1   thorpej  *
   10892  1.281   msaitoh  *	Read a PHY register on the SGMII
   10893  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10894  1.281   msaitoh  * ressource ...
   10895    1.1   thorpej  */
   10896   1.47   thorpej static int
   10897  1.521   msaitoh wm_sgmii_readreg(device_t dev, int phy, int reg)
   10898    1.1   thorpej {
   10899  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10900  1.281   msaitoh 	uint32_t i2ccmd;
   10901    1.1   thorpej 	int i, rv;
   10902    1.1   thorpej 
   10903  1.424   msaitoh 	if (sc->phy.acquire(sc)) {
   10904  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10905  1.281   msaitoh 		return 0;
   10906  1.281   msaitoh 	}
   10907  1.281   msaitoh 
   10908  1.281   msaitoh 	i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
   10909  1.573   msaitoh 	    | (phy << I2CCMD_PHY_ADDR_SHIFT) | I2CCMD_OPCODE_READ;
   10910  1.281   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   10911    1.1   thorpej 
   10912  1.281   msaitoh 	/* Poll the ready bit */
   10913  1.281   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   10914  1.281   msaitoh 		delay(50);
   10915  1.281   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   10916  1.281   msaitoh 		if (i2ccmd & I2CCMD_READY)
   10917    1.1   thorpej 			break;
   10918    1.1   thorpej 	}
   10919  1.281   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   10920  1.521   msaitoh 		device_printf(dev, "I2CCMD Read did not complete\n");
   10921  1.281   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   10922  1.521   msaitoh 		device_printf(dev, "I2CCMD Error bit set\n");
   10923    1.1   thorpej 
   10924  1.281   msaitoh 	rv = ((i2ccmd >> 8) & 0x00ff) | ((i2ccmd << 8) & 0xff00);
   10925    1.1   thorpej 
   10926  1.424   msaitoh 	sc->phy.release(sc);
   10927  1.194   msaitoh 	return rv;
   10928    1.1   thorpej }
   10929    1.1   thorpej 
   10930    1.1   thorpej /*
   10931  1.281   msaitoh  * wm_sgmii_writereg:	[mii interface function]
   10932    1.1   thorpej  *
   10933  1.281   msaitoh  *	Write a PHY register on the SGMII.
   10934  1.281   msaitoh  * This could be handled by the PHY layer if we didn't have to lock the
   10935  1.281   msaitoh  * ressource ...
   10936    1.1   thorpej  */
   10937   1.47   thorpej static void
   10938  1.521   msaitoh wm_sgmii_writereg(device_t dev, int phy, int reg, int val)
   10939    1.1   thorpej {
   10940  1.521   msaitoh 	struct wm_softc *sc = device_private(dev);
   10941  1.281   msaitoh 	uint32_t i2ccmd;
   10942    1.1   thorpej 	int i;
   10943  1.573   msaitoh 	int swapdata;
   10944    1.1   thorpej 
   10945  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0) {
   10946  1.521   msaitoh 		device_printf(dev, "%s: failed to get semaphore\n", __func__);
   10947  1.281   msaitoh 		return;
   10948  1.281   msaitoh 	}
   10949  1.314   msaitoh 	/* Swap the data bytes for the I2C interface */
   10950  1.573   msaitoh 	swapdata = ((val >> 8) & 0x00FF) | ((val << 8) & 0xFF00);
   10951  1.281   msaitoh 	i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
   10952  1.573   msaitoh 	    | (phy << I2CCMD_PHY_ADDR_SHIFT) | I2CCMD_OPCODE_WRITE | swapdata;
   10953  1.281   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   10954    1.1   thorpej 
   10955  1.281   msaitoh 	/* Poll the ready bit */
   10956  1.281   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   10957  1.281   msaitoh 		delay(50);
   10958  1.281   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   10959  1.281   msaitoh 		if (i2ccmd & I2CCMD_READY)
   10960    1.1   thorpej 			break;
   10961    1.1   thorpej 	}
   10962  1.281   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   10963  1.521   msaitoh 		device_printf(dev, "I2CCMD Write did not complete\n");
   10964  1.281   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   10965  1.521   msaitoh 		device_printf(dev, "I2CCMD Error bit set\n");
   10966    1.1   thorpej 
   10967  1.424   msaitoh 	sc->phy.release(sc);
   10968    1.1   thorpej }
   10969    1.1   thorpej 
   10970  1.281   msaitoh /* TBI related */
   10971  1.281   msaitoh 
   10972  1.127    bouyer /*
   10973  1.281   msaitoh  * wm_tbi_mediainit:
   10974  1.127    bouyer  *
   10975  1.281   msaitoh  *	Initialize media for use on 1000BASE-X devices.
   10976  1.127    bouyer  */
   10977  1.127    bouyer static void
   10978  1.281   msaitoh wm_tbi_mediainit(struct wm_softc *sc)
   10979  1.127    bouyer {
   10980  1.281   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   10981  1.281   msaitoh 	const char *sep = "";
   10982  1.281   msaitoh 
   10983  1.281   msaitoh 	if (sc->sc_type < WM_T_82543)
   10984  1.281   msaitoh 		sc->sc_tipg = TIPG_WM_DFLT;
   10985  1.281   msaitoh 	else
   10986  1.281   msaitoh 		sc->sc_tipg = TIPG_LG_DFLT;
   10987  1.281   msaitoh 
   10988  1.325   msaitoh 	sc->sc_tbi_serdes_anegticks = 5;
   10989  1.281   msaitoh 
   10990  1.281   msaitoh 	/* Initialize our media structures */
   10991  1.281   msaitoh 	sc->sc_mii.mii_ifp = ifp;
   10992  1.325   msaitoh 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
   10993  1.281   msaitoh 
   10994  1.325   msaitoh 	if ((sc->sc_type >= WM_T_82575)
   10995  1.325   msaitoh 	    && (sc->sc_mediatype == WM_MEDIATYPE_SERDES))
   10996  1.327   msaitoh 		ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
   10997  1.325   msaitoh 		    wm_serdes_mediachange, wm_serdes_mediastatus);
   10998  1.325   msaitoh 	else
   10999  1.327   msaitoh 		ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK,
   11000  1.325   msaitoh 		    wm_tbi_mediachange, wm_tbi_mediastatus);
   11001  1.281   msaitoh 
   11002  1.281   msaitoh 	/*
   11003  1.281   msaitoh 	 * SWD Pins:
   11004  1.281   msaitoh 	 *
   11005  1.281   msaitoh 	 *	0 = Link LED (output)
   11006  1.281   msaitoh 	 *	1 = Loss Of Signal (input)
   11007  1.281   msaitoh 	 */
   11008  1.281   msaitoh 	sc->sc_ctrl |= CTRL_SWDPIO(0);
   11009  1.325   msaitoh 
   11010  1.325   msaitoh 	/* XXX Perhaps this is only for TBI */
   11011  1.325   msaitoh 	if (sc->sc_mediatype != WM_MEDIATYPE_SERDES)
   11012  1.325   msaitoh 		sc->sc_ctrl &= ~CTRL_SWDPIO(1);
   11013  1.325   msaitoh 
   11014  1.311   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES)
   11015  1.281   msaitoh 		sc->sc_ctrl &= ~CTRL_LRST;
   11016  1.281   msaitoh 
   11017  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11018  1.127    bouyer 
   11019  1.281   msaitoh #define	ADD(ss, mm, dd)							\
   11020  1.281   msaitoh do {									\
   11021  1.281   msaitoh 	aprint_normal("%s%s", sep, ss);					\
   11022  1.388   msaitoh 	ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | (mm), (dd), NULL); \
   11023  1.281   msaitoh 	sep = ", ";							\
   11024  1.281   msaitoh } while (/*CONSTCOND*/0)
   11025  1.127    bouyer 
   11026  1.281   msaitoh 	aprint_normal_dev(sc->sc_dev, "");
   11027  1.285   msaitoh 
   11028  1.457   msaitoh 	if (sc->sc_type == WM_T_I354) {
   11029  1.457   msaitoh 		uint32_t status;
   11030  1.457   msaitoh 
   11031  1.457   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   11032  1.457   msaitoh 		if (((status & STATUS_2P5_SKU) != 0)
   11033  1.457   msaitoh 		    && ((status & STATUS_2P5_SKU_OVER) == 0)) {
   11034  1.509   msaitoh 			ADD("2500baseKX-FDX", IFM_2500_KX | IFM_FDX,ANAR_X_FD);
   11035  1.457   msaitoh 		} else
   11036  1.509   msaitoh 			ADD("1000baseKX-FDX", IFM_1000_KX | IFM_FDX,ANAR_X_FD);
   11037  1.457   msaitoh 	} else if (sc->sc_type == WM_T_82545) {
   11038  1.457   msaitoh 		/* Only 82545 is LX (XXX except SFP) */
   11039  1.285   msaitoh 		ADD("1000baseLX", IFM_1000_LX, ANAR_X_HD);
   11040  1.388   msaitoh 		ADD("1000baseLX-FDX", IFM_1000_LX | IFM_FDX, ANAR_X_FD);
   11041  1.285   msaitoh 	} else {
   11042  1.285   msaitoh 		ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
   11043  1.388   msaitoh 		ADD("1000baseSX-FDX", IFM_1000_SX | IFM_FDX, ANAR_X_FD);
   11044  1.285   msaitoh 	}
   11045  1.388   msaitoh 	ADD("auto", IFM_AUTO, ANAR_X_FD | ANAR_X_HD);
   11046  1.281   msaitoh 	aprint_normal("\n");
   11047  1.127    bouyer 
   11048  1.281   msaitoh #undef ADD
   11049  1.127    bouyer 
   11050  1.281   msaitoh 	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
   11051  1.127    bouyer }
   11052  1.127    bouyer 
   11053  1.127    bouyer /*
   11054  1.281   msaitoh  * wm_tbi_mediachange:	[ifmedia interface function]
   11055  1.167   msaitoh  *
   11056  1.281   msaitoh  *	Set hardware to newly-selected media on a 1000BASE-X device.
   11057  1.167   msaitoh  */
   11058  1.281   msaitoh static int
   11059  1.281   msaitoh wm_tbi_mediachange(struct ifnet *ifp)
   11060  1.167   msaitoh {
   11061  1.281   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   11062  1.281   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   11063  1.281   msaitoh 	uint32_t status;
   11064  1.281   msaitoh 	int i;
   11065  1.167   msaitoh 
   11066  1.325   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {
   11067  1.325   msaitoh 		/* XXX need some work for >= 82571 and < 82575 */
   11068  1.325   msaitoh 		if (sc->sc_type < WM_T_82575)
   11069  1.325   msaitoh 			return 0;
   11070  1.325   msaitoh 	}
   11071  1.167   msaitoh 
   11072  1.285   msaitoh 	if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)
   11073  1.285   msaitoh 	    || (sc->sc_type >= WM_T_82575))
   11074  1.285   msaitoh 		CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK);
   11075  1.285   msaitoh 
   11076  1.285   msaitoh 	sc->sc_ctrl &= ~CTRL_LRST;
   11077  1.285   msaitoh 	sc->sc_txcw = TXCW_ANE;
   11078  1.285   msaitoh 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   11079  1.285   msaitoh 		sc->sc_txcw |= TXCW_FD | TXCW_HD;
   11080  1.285   msaitoh 	else if (ife->ifm_media & IFM_FDX)
   11081  1.285   msaitoh 		sc->sc_txcw |= TXCW_FD;
   11082  1.285   msaitoh 	else
   11083  1.285   msaitoh 		sc->sc_txcw |= TXCW_HD;
   11084  1.285   msaitoh 
   11085  1.327   msaitoh 	if ((sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
   11086  1.281   msaitoh 		sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE;
   11087  1.167   msaitoh 
   11088  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n",
   11089  1.285   msaitoh 		    device_xname(sc->sc_dev), sc->sc_txcw));
   11090  1.281   msaitoh 	CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   11091  1.285   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11092  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11093  1.285   msaitoh 	delay(1000);
   11094  1.167   msaitoh 
   11095  1.281   msaitoh 	i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1);
   11096  1.281   msaitoh 	DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i));
   11097  1.192   msaitoh 
   11098  1.281   msaitoh 	/*
   11099  1.281   msaitoh 	 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the
   11100  1.281   msaitoh 	 * optics detect a signal, 0 if they don't.
   11101  1.281   msaitoh 	 */
   11102  1.281   msaitoh 	if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) {
   11103  1.281   msaitoh 		/* Have signal; wait for the link to come up. */
   11104  1.281   msaitoh 		for (i = 0; i < WM_LINKUP_TIMEOUT; i++) {
   11105  1.281   msaitoh 			delay(10000);
   11106  1.281   msaitoh 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
   11107  1.281   msaitoh 				break;
   11108  1.281   msaitoh 		}
   11109  1.192   msaitoh 
   11110  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n",
   11111  1.281   msaitoh 			    device_xname(sc->sc_dev),i));
   11112  1.192   msaitoh 
   11113  1.281   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   11114  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   11115  1.281   msaitoh 		    ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n",
   11116  1.281   msaitoh 			device_xname(sc->sc_dev),status, STATUS_LU));
   11117  1.281   msaitoh 		if (status & STATUS_LU) {
   11118  1.281   msaitoh 			/* Link is up. */
   11119  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   11120  1.281   msaitoh 			    ("%s: LINK: set media -> link up %s\n",
   11121  1.281   msaitoh 			    device_xname(sc->sc_dev),
   11122  1.281   msaitoh 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   11123  1.192   msaitoh 
   11124  1.281   msaitoh 			/*
   11125  1.281   msaitoh 			 * NOTE: CTRL will update TFCE and RFCE automatically,
   11126  1.281   msaitoh 			 * so we should update sc->sc_ctrl
   11127  1.281   msaitoh 			 */
   11128  1.281   msaitoh 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
   11129  1.281   msaitoh 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   11130  1.281   msaitoh 			sc->sc_fcrtl &= ~FCRTL_XONE;
   11131  1.281   msaitoh 			if (status & STATUS_FD)
   11132  1.281   msaitoh 				sc->sc_tctl |=
   11133  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   11134  1.281   msaitoh 			else
   11135  1.281   msaitoh 				sc->sc_tctl |=
   11136  1.281   msaitoh 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   11137  1.281   msaitoh 			if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
   11138  1.281   msaitoh 				sc->sc_fcrtl |= FCRTL_XONE;
   11139  1.281   msaitoh 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   11140  1.281   msaitoh 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   11141  1.281   msaitoh 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   11142  1.281   msaitoh 				      sc->sc_fcrtl);
   11143  1.281   msaitoh 			sc->sc_tbi_linkup = 1;
   11144  1.281   msaitoh 		} else {
   11145  1.281   msaitoh 			if (i == WM_LINKUP_TIMEOUT)
   11146  1.281   msaitoh 				wm_check_for_link(sc);
   11147  1.281   msaitoh 			/* Link is down. */
   11148  1.281   msaitoh 			DPRINTF(WM_DEBUG_LINK,
   11149  1.281   msaitoh 			    ("%s: LINK: set media -> link down\n",
   11150  1.281   msaitoh 			    device_xname(sc->sc_dev)));
   11151  1.281   msaitoh 			sc->sc_tbi_linkup = 0;
   11152  1.281   msaitoh 		}
   11153  1.281   msaitoh 	} else {
   11154  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
   11155  1.281   msaitoh 		    device_xname(sc->sc_dev)));
   11156  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   11157  1.281   msaitoh 	}
   11158  1.198   msaitoh 
   11159  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11160  1.192   msaitoh 
   11161  1.281   msaitoh 	return 0;
   11162  1.192   msaitoh }
   11163  1.192   msaitoh 
   11164  1.167   msaitoh /*
   11165  1.324   msaitoh  * wm_tbi_mediastatus:	[ifmedia interface function]
   11166  1.324   msaitoh  *
   11167  1.324   msaitoh  *	Get the current interface media status on a 1000BASE-X device.
   11168  1.324   msaitoh  */
   11169  1.324   msaitoh static void
   11170  1.324   msaitoh wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   11171  1.324   msaitoh {
   11172  1.324   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   11173  1.324   msaitoh 	uint32_t ctrl, status;
   11174  1.324   msaitoh 
   11175  1.324   msaitoh 	ifmr->ifm_status = IFM_AVALID;
   11176  1.324   msaitoh 	ifmr->ifm_active = IFM_ETHER;
   11177  1.324   msaitoh 
   11178  1.324   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   11179  1.324   msaitoh 	if ((status & STATUS_LU) == 0) {
   11180  1.324   msaitoh 		ifmr->ifm_active |= IFM_NONE;
   11181  1.324   msaitoh 		return;
   11182  1.324   msaitoh 	}
   11183  1.324   msaitoh 
   11184  1.324   msaitoh 	ifmr->ifm_status |= IFM_ACTIVE;
   11185  1.324   msaitoh 	/* Only 82545 is LX */
   11186  1.324   msaitoh 	if (sc->sc_type == WM_T_82545)
   11187  1.324   msaitoh 		ifmr->ifm_active |= IFM_1000_LX;
   11188  1.324   msaitoh 	else
   11189  1.324   msaitoh 		ifmr->ifm_active |= IFM_1000_SX;
   11190  1.324   msaitoh 	if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
   11191  1.324   msaitoh 		ifmr->ifm_active |= IFM_FDX;
   11192  1.324   msaitoh 	else
   11193  1.324   msaitoh 		ifmr->ifm_active |= IFM_HDX;
   11194  1.324   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   11195  1.324   msaitoh 	if (ctrl & CTRL_RFCE)
   11196  1.324   msaitoh 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE;
   11197  1.324   msaitoh 	if (ctrl & CTRL_TFCE)
   11198  1.324   msaitoh 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE;
   11199  1.324   msaitoh }
   11200  1.324   msaitoh 
   11201  1.325   msaitoh /* XXX TBI only */
   11202  1.324   msaitoh static int
   11203  1.324   msaitoh wm_check_for_link(struct wm_softc *sc)
   11204  1.324   msaitoh {
   11205  1.324   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   11206  1.324   msaitoh 	uint32_t rxcw;
   11207  1.324   msaitoh 	uint32_t ctrl;
   11208  1.324   msaitoh 	uint32_t status;
   11209  1.324   msaitoh 	uint32_t sig;
   11210  1.324   msaitoh 
   11211  1.324   msaitoh 	if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) {
   11212  1.325   msaitoh 		/* XXX need some work for >= 82571 */
   11213  1.325   msaitoh 		if (sc->sc_type >= WM_T_82571) {
   11214  1.325   msaitoh 			sc->sc_tbi_linkup = 1;
   11215  1.325   msaitoh 			return 0;
   11216  1.325   msaitoh 		}
   11217  1.324   msaitoh 	}
   11218  1.324   msaitoh 
   11219  1.324   msaitoh 	rxcw = CSR_READ(sc, WMREG_RXCW);
   11220  1.324   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   11221  1.324   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   11222  1.324   msaitoh 
   11223  1.324   msaitoh 	sig = (sc->sc_type > WM_T_82544) ? CTRL_SWDPIN(1) : 0;
   11224  1.324   msaitoh 
   11225  1.388   msaitoh 	DPRINTF(WM_DEBUG_LINK,
   11226  1.388   msaitoh 	    ("%s: %s: sig = %d, status_lu = %d, rxcw_c = %d\n",
   11227  1.324   msaitoh 		device_xname(sc->sc_dev), __func__,
   11228  1.324   msaitoh 		((ctrl & CTRL_SWDPIN(1)) == sig),
   11229  1.388   msaitoh 		((status & STATUS_LU) != 0), ((rxcw & RXCW_C) != 0)));
   11230  1.324   msaitoh 
   11231  1.324   msaitoh 	/*
   11232  1.324   msaitoh 	 * SWDPIN   LU RXCW
   11233  1.324   msaitoh 	 *      0    0    0
   11234  1.324   msaitoh 	 *      0    0    1	(should not happen)
   11235  1.324   msaitoh 	 *      0    1    0	(should not happen)
   11236  1.324   msaitoh 	 *      0    1    1	(should not happen)
   11237  1.324   msaitoh 	 *      1    0    0	Disable autonego and force linkup
   11238  1.324   msaitoh 	 *      1    0    1	got /C/ but not linkup yet
   11239  1.324   msaitoh 	 *      1    1    0	(linkup)
   11240  1.324   msaitoh 	 *      1    1    1	If IFM_AUTO, back to autonego
   11241  1.324   msaitoh 	 *
   11242  1.324   msaitoh 	 */
   11243  1.324   msaitoh 	if (((ctrl & CTRL_SWDPIN(1)) == sig)
   11244  1.324   msaitoh 	    && ((status & STATUS_LU) == 0)
   11245  1.324   msaitoh 	    && ((rxcw & RXCW_C) == 0)) {
   11246  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: force linkup and fullduplex\n",
   11247  1.324   msaitoh 			__func__));
   11248  1.324   msaitoh 		sc->sc_tbi_linkup = 0;
   11249  1.324   msaitoh 		/* Disable auto-negotiation in the TXCW register */
   11250  1.324   msaitoh 		CSR_WRITE(sc, WMREG_TXCW, (sc->sc_txcw & ~TXCW_ANE));
   11251  1.324   msaitoh 
   11252  1.324   msaitoh 		/*
   11253  1.324   msaitoh 		 * Force link-up and also force full-duplex.
   11254  1.324   msaitoh 		 *
   11255  1.324   msaitoh 		 * NOTE: CTRL was updated TFCE and RFCE automatically,
   11256  1.324   msaitoh 		 * so we should update sc->sc_ctrl
   11257  1.324   msaitoh 		 */
   11258  1.324   msaitoh 		sc->sc_ctrl = ctrl | CTRL_SLU | CTRL_FD;
   11259  1.324   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11260  1.324   msaitoh 	} else if (((status & STATUS_LU) != 0)
   11261  1.324   msaitoh 	    && ((rxcw & RXCW_C) != 0)
   11262  1.324   msaitoh 	    && (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)) {
   11263  1.324   msaitoh 		sc->sc_tbi_linkup = 1;
   11264  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: go back to autonego\n",
   11265  1.324   msaitoh 			__func__));
   11266  1.324   msaitoh 		CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   11267  1.324   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, (ctrl & ~CTRL_SLU));
   11268  1.324   msaitoh 	} else if (((ctrl & CTRL_SWDPIN(1)) == sig)
   11269  1.324   msaitoh 	    && ((rxcw & RXCW_C) != 0)) {
   11270  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("/C/"));
   11271  1.324   msaitoh 	} else {
   11272  1.324   msaitoh 		DPRINTF(WM_DEBUG_LINK, ("%s: %x,%x,%x\n", __func__, rxcw, ctrl,
   11273  1.324   msaitoh 			status));
   11274  1.324   msaitoh 	}
   11275  1.324   msaitoh 
   11276  1.324   msaitoh 	return 0;
   11277  1.324   msaitoh }
   11278  1.324   msaitoh 
   11279  1.324   msaitoh /*
   11280  1.325   msaitoh  * wm_tbi_tick:
   11281  1.191   msaitoh  *
   11282  1.325   msaitoh  *	Check the link on TBI devices.
   11283  1.325   msaitoh  *	This function acts as mii_tick().
   11284  1.191   msaitoh  */
   11285  1.281   msaitoh static void
   11286  1.325   msaitoh wm_tbi_tick(struct wm_softc *sc)
   11287  1.191   msaitoh {
   11288  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   11289  1.325   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
   11290  1.281   msaitoh 	uint32_t status;
   11291  1.281   msaitoh 
   11292  1.384  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   11293  1.191   msaitoh 
   11294  1.281   msaitoh 	status = CSR_READ(sc, WMREG_STATUS);
   11295  1.192   msaitoh 
   11296  1.281   msaitoh 	/* XXX is this needed? */
   11297  1.281   msaitoh 	(void)CSR_READ(sc, WMREG_RXCW);
   11298  1.281   msaitoh 	(void)CSR_READ(sc, WMREG_CTRL);
   11299  1.192   msaitoh 
   11300  1.281   msaitoh 	/* set link status */
   11301  1.281   msaitoh 	if ((status & STATUS_LU) == 0) {
   11302  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   11303  1.281   msaitoh 		    ("%s: LINK: checklink -> down\n",
   11304  1.281   msaitoh 			device_xname(sc->sc_dev)));
   11305  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   11306  1.281   msaitoh 	} else if (sc->sc_tbi_linkup == 0) {
   11307  1.281   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   11308  1.281   msaitoh 		    ("%s: LINK: checklink -> up %s\n",
   11309  1.281   msaitoh 			device_xname(sc->sc_dev),
   11310  1.281   msaitoh 			(status & STATUS_FD) ? "FDX" : "HDX"));
   11311  1.281   msaitoh 		sc->sc_tbi_linkup = 1;
   11312  1.325   msaitoh 		sc->sc_tbi_serdes_ticks = 0;
   11313  1.325   msaitoh 	}
   11314  1.325   msaitoh 
   11315  1.325   msaitoh 	if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) == 0)
   11316  1.325   msaitoh 		goto setled;
   11317  1.325   msaitoh 
   11318  1.325   msaitoh 	if ((status & STATUS_LU) == 0) {
   11319  1.325   msaitoh 		sc->sc_tbi_linkup = 0;
   11320  1.325   msaitoh 		/* If the timer expired, retry autonegotiation */
   11321  1.325   msaitoh 		if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   11322  1.325   msaitoh 		    && (++sc->sc_tbi_serdes_ticks
   11323  1.325   msaitoh 			>= sc->sc_tbi_serdes_anegticks)) {
   11324  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
   11325  1.325   msaitoh 			sc->sc_tbi_serdes_ticks = 0;
   11326  1.325   msaitoh 			/*
   11327  1.325   msaitoh 			 * Reset the link, and let autonegotiation do
   11328  1.325   msaitoh 			 * its thing
   11329  1.325   msaitoh 			 */
   11330  1.325   msaitoh 			sc->sc_ctrl |= CTRL_LRST;
   11331  1.325   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11332  1.325   msaitoh 			CSR_WRITE_FLUSH(sc);
   11333  1.325   msaitoh 			delay(1000);
   11334  1.325   msaitoh 			sc->sc_ctrl &= ~CTRL_LRST;
   11335  1.325   msaitoh 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11336  1.325   msaitoh 			CSR_WRITE_FLUSH(sc);
   11337  1.325   msaitoh 			delay(1000);
   11338  1.325   msaitoh 			CSR_WRITE(sc, WMREG_TXCW,
   11339  1.325   msaitoh 			    sc->sc_txcw & ~TXCW_ANE);
   11340  1.325   msaitoh 			CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   11341  1.325   msaitoh 		}
   11342  1.192   msaitoh 	}
   11343  1.192   msaitoh 
   11344  1.325   msaitoh setled:
   11345  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11346  1.325   msaitoh }
   11347  1.325   msaitoh 
   11348  1.325   msaitoh /* SERDES related */
   11349  1.325   msaitoh static void
   11350  1.325   msaitoh wm_serdes_power_up_link_82575(struct wm_softc *sc)
   11351  1.325   msaitoh {
   11352  1.325   msaitoh 	uint32_t reg;
   11353  1.325   msaitoh 
   11354  1.325   msaitoh 	if ((sc->sc_mediatype != WM_MEDIATYPE_SERDES)
   11355  1.325   msaitoh 	    && ((sc->sc_flags & WM_F_SGMII) == 0))
   11356  1.325   msaitoh 		return;
   11357  1.325   msaitoh 
   11358  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_CFG);
   11359  1.325   msaitoh 	reg |= PCS_CFG_PCS_EN;
   11360  1.325   msaitoh 	CSR_WRITE(sc, WMREG_PCS_CFG, reg);
   11361  1.325   msaitoh 
   11362  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL_EXT);
   11363  1.325   msaitoh 	reg &= ~CTRL_EXT_SWDPIN(3);
   11364  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   11365  1.325   msaitoh 	CSR_WRITE_FLUSH(sc);
   11366  1.325   msaitoh }
   11367  1.325   msaitoh 
   11368  1.325   msaitoh static int
   11369  1.325   msaitoh wm_serdes_mediachange(struct ifnet *ifp)
   11370  1.325   msaitoh {
   11371  1.325   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   11372  1.325   msaitoh 	bool pcs_autoneg = true; /* XXX */
   11373  1.325   msaitoh 	uint32_t ctrl_ext, pcs_lctl, reg;
   11374  1.325   msaitoh 
   11375  1.325   msaitoh 	/* XXX Currently, this function is not called on 8257[12] */
   11376  1.325   msaitoh 	if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572)
   11377  1.325   msaitoh 	    || (sc->sc_type >= WM_T_82575))
   11378  1.325   msaitoh 		CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK);
   11379  1.325   msaitoh 
   11380  1.325   msaitoh 	wm_serdes_power_up_link_82575(sc);
   11381  1.325   msaitoh 
   11382  1.325   msaitoh 	sc->sc_ctrl |= CTRL_SLU;
   11383  1.325   msaitoh 
   11384  1.325   msaitoh 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576))
   11385  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SWDPIN(0) | CTRL_SWDPIN(1);
   11386  1.325   msaitoh 
   11387  1.325   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   11388  1.325   msaitoh 	pcs_lctl = CSR_READ(sc, WMREG_PCS_LCTL);
   11389  1.325   msaitoh 	switch (ctrl_ext & CTRL_EXT_LINK_MODE_MASK) {
   11390  1.325   msaitoh 	case CTRL_EXT_LINK_MODE_SGMII:
   11391  1.325   msaitoh 		pcs_autoneg = true;
   11392  1.325   msaitoh 		pcs_lctl &= ~PCS_LCTL_AN_TIMEOUT;
   11393  1.325   msaitoh 		break;
   11394  1.325   msaitoh 	case CTRL_EXT_LINK_MODE_1000KX:
   11395  1.325   msaitoh 		pcs_autoneg = false;
   11396  1.325   msaitoh 		/* FALLTHROUGH */
   11397  1.325   msaitoh 	default:
   11398  1.388   msaitoh 		if ((sc->sc_type == WM_T_82575)
   11399  1.388   msaitoh 		    || (sc->sc_type == WM_T_82576)) {
   11400  1.325   msaitoh 			if ((sc->sc_flags & WM_F_PCS_DIS_AUTONEGO) != 0)
   11401  1.325   msaitoh 				pcs_autoneg = false;
   11402  1.325   msaitoh 		}
   11403  1.325   msaitoh 		sc->sc_ctrl |= CTRL_SPEED_1000 | CTRL_FRCSPD | CTRL_FD
   11404  1.325   msaitoh 		    | CTRL_FRCFDX;
   11405  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_FSV_1000 | PCS_LCTL_FDV_FULL;
   11406  1.325   msaitoh 	}
   11407  1.325   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   11408  1.325   msaitoh 
   11409  1.325   msaitoh 	if (pcs_autoneg) {
   11410  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_AN_ENABLE | PCS_LCTL_AN_RESTART;
   11411  1.325   msaitoh 		pcs_lctl &= ~PCS_LCTL_FORCE_FC;
   11412  1.325   msaitoh 
   11413  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_ANADV);
   11414  1.325   msaitoh 		reg &= ~(TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE);
   11415  1.327   msaitoh 		reg |= TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE;
   11416  1.325   msaitoh 		CSR_WRITE(sc, WMREG_PCS_ANADV, reg);
   11417  1.325   msaitoh 	} else
   11418  1.325   msaitoh 		pcs_lctl |= PCS_LCTL_FSD | PCS_LCTL_FORCE_FC;
   11419  1.325   msaitoh 
   11420  1.325   msaitoh 	CSR_WRITE(sc, WMREG_PCS_LCTL, pcs_lctl);
   11421  1.325   msaitoh 
   11422  1.325   msaitoh 
   11423  1.325   msaitoh 	return 0;
   11424  1.325   msaitoh }
   11425  1.325   msaitoh 
   11426  1.325   msaitoh static void
   11427  1.325   msaitoh wm_serdes_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   11428  1.325   msaitoh {
   11429  1.325   msaitoh 	struct wm_softc *sc = ifp->if_softc;
   11430  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   11431  1.325   msaitoh 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   11432  1.325   msaitoh 	uint32_t pcs_adv, pcs_lpab, reg;
   11433  1.325   msaitoh 
   11434  1.325   msaitoh 	ifmr->ifm_status = IFM_AVALID;
   11435  1.325   msaitoh 	ifmr->ifm_active = IFM_ETHER;
   11436  1.325   msaitoh 
   11437  1.325   msaitoh 	/* Check PCS */
   11438  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_LSTS);
   11439  1.325   msaitoh 	if ((reg & PCS_LSTS_LINKOK) == 0) {
   11440  1.325   msaitoh 		ifmr->ifm_active |= IFM_NONE;
   11441  1.325   msaitoh 		sc->sc_tbi_linkup = 0;
   11442  1.325   msaitoh 		goto setled;
   11443  1.325   msaitoh 	}
   11444  1.325   msaitoh 
   11445  1.325   msaitoh 	sc->sc_tbi_linkup = 1;
   11446  1.325   msaitoh 	ifmr->ifm_status |= IFM_ACTIVE;
   11447  1.457   msaitoh 	if (sc->sc_type == WM_T_I354) {
   11448  1.457   msaitoh 		uint32_t status;
   11449  1.457   msaitoh 
   11450  1.457   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   11451  1.457   msaitoh 		if (((status & STATUS_2P5_SKU) != 0)
   11452  1.457   msaitoh 		    && ((status & STATUS_2P5_SKU_OVER) == 0)) {
   11453  1.457   msaitoh 			ifmr->ifm_active |= IFM_2500_SX; /* XXX KX */
   11454  1.457   msaitoh 		} else
   11455  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX KX */
   11456  1.457   msaitoh 	} else {
   11457  1.457   msaitoh 		switch (__SHIFTOUT(reg, PCS_LSTS_SPEED)) {
   11458  1.457   msaitoh 		case PCS_LSTS_SPEED_10:
   11459  1.457   msaitoh 			ifmr->ifm_active |= IFM_10_T; /* XXX */
   11460  1.457   msaitoh 			break;
   11461  1.457   msaitoh 		case PCS_LSTS_SPEED_100:
   11462  1.457   msaitoh 			ifmr->ifm_active |= IFM_100_FX; /* XXX */
   11463  1.457   msaitoh 			break;
   11464  1.457   msaitoh 		case PCS_LSTS_SPEED_1000:
   11465  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX */
   11466  1.457   msaitoh 			break;
   11467  1.457   msaitoh 		default:
   11468  1.457   msaitoh 			device_printf(sc->sc_dev, "Unknown speed\n");
   11469  1.457   msaitoh 			ifmr->ifm_active |= IFM_1000_SX; /* XXX */
   11470  1.457   msaitoh 			break;
   11471  1.457   msaitoh 		}
   11472  1.457   msaitoh 	}
   11473  1.325   msaitoh 	if ((reg & PCS_LSTS_FDX) != 0)
   11474  1.325   msaitoh 		ifmr->ifm_active |= IFM_FDX;
   11475  1.325   msaitoh 	else
   11476  1.325   msaitoh 		ifmr->ifm_active |= IFM_HDX;
   11477  1.325   msaitoh 	mii->mii_media_active &= ~IFM_ETH_FMASK;
   11478  1.325   msaitoh 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
   11479  1.325   msaitoh 		/* Check flow */
   11480  1.325   msaitoh 		reg = CSR_READ(sc, WMREG_PCS_LSTS);
   11481  1.325   msaitoh 		if ((reg & PCS_LSTS_AN_COMP) == 0) {
   11482  1.388   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("XXX LINKOK but not ACOMP\n"));
   11483  1.325   msaitoh 			goto setled;
   11484  1.325   msaitoh 		}
   11485  1.325   msaitoh 		pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
   11486  1.325   msaitoh 		pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
   11487  1.388   msaitoh 		DPRINTF(WM_DEBUG_LINK,
   11488  1.388   msaitoh 		    ("XXX AN result(2) %08x, %08x\n", pcs_adv, pcs_lpab));
   11489  1.325   msaitoh 		if ((pcs_adv & TXCW_SYM_PAUSE)
   11490  1.325   msaitoh 		    && (pcs_lpab & TXCW_SYM_PAUSE)) {
   11491  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11492  1.325   msaitoh 			    | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   11493  1.325   msaitoh 		} else if (((pcs_adv & TXCW_SYM_PAUSE) == 0)
   11494  1.325   msaitoh 		    && (pcs_adv & TXCW_ASYM_PAUSE)
   11495  1.325   msaitoh 		    && (pcs_lpab & TXCW_SYM_PAUSE)
   11496  1.325   msaitoh 		    && (pcs_lpab & TXCW_ASYM_PAUSE)) {
   11497  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11498  1.325   msaitoh 			    | IFM_ETH_TXPAUSE;
   11499  1.325   msaitoh 		} else if ((pcs_adv & TXCW_SYM_PAUSE)
   11500  1.325   msaitoh 		    && (pcs_adv & TXCW_ASYM_PAUSE)
   11501  1.325   msaitoh 		    && ((pcs_lpab & TXCW_SYM_PAUSE) == 0)
   11502  1.325   msaitoh 		    && (pcs_lpab & TXCW_ASYM_PAUSE)) {
   11503  1.325   msaitoh 			mii->mii_media_active |= IFM_FLOW
   11504  1.325   msaitoh 			    | IFM_ETH_RXPAUSE;
   11505  1.325   msaitoh 		}
   11506  1.325   msaitoh 	}
   11507  1.325   msaitoh 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
   11508  1.325   msaitoh 	    | (mii->mii_media_active & IFM_ETH_FMASK);
   11509  1.325   msaitoh setled:
   11510  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11511  1.325   msaitoh }
   11512  1.325   msaitoh 
   11513  1.325   msaitoh /*
   11514  1.325   msaitoh  * wm_serdes_tick:
   11515  1.325   msaitoh  *
   11516  1.325   msaitoh  *	Check the link on serdes devices.
   11517  1.325   msaitoh  */
   11518  1.325   msaitoh static void
   11519  1.325   msaitoh wm_serdes_tick(struct wm_softc *sc)
   11520  1.325   msaitoh {
   11521  1.325   msaitoh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   11522  1.325   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   11523  1.325   msaitoh 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
   11524  1.325   msaitoh 	uint32_t reg;
   11525  1.325   msaitoh 
   11526  1.384  knakahar 	KASSERT(WM_CORE_LOCKED(sc));
   11527  1.325   msaitoh 
   11528  1.325   msaitoh 	mii->mii_media_status = IFM_AVALID;
   11529  1.325   msaitoh 	mii->mii_media_active = IFM_ETHER;
   11530  1.325   msaitoh 
   11531  1.325   msaitoh 	/* Check PCS */
   11532  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_PCS_LSTS);
   11533  1.325   msaitoh 	if ((reg & PCS_LSTS_LINKOK) != 0) {
   11534  1.325   msaitoh 		mii->mii_media_status |= IFM_ACTIVE;
   11535  1.325   msaitoh 		sc->sc_tbi_linkup = 1;
   11536  1.325   msaitoh 		sc->sc_tbi_serdes_ticks = 0;
   11537  1.325   msaitoh 		mii->mii_media_active |= IFM_1000_SX; /* XXX */
   11538  1.325   msaitoh 		if ((reg & PCS_LSTS_FDX) != 0)
   11539  1.325   msaitoh 			mii->mii_media_active |= IFM_FDX;
   11540  1.325   msaitoh 		else
   11541  1.325   msaitoh 			mii->mii_media_active |= IFM_HDX;
   11542  1.325   msaitoh 	} else {
   11543  1.325   msaitoh 		mii->mii_media_status |= IFM_NONE;
   11544  1.281   msaitoh 		sc->sc_tbi_linkup = 0;
   11545  1.457   msaitoh 		/* If the timer expired, retry autonegotiation */
   11546  1.325   msaitoh 		if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
   11547  1.325   msaitoh 		    && (++sc->sc_tbi_serdes_ticks
   11548  1.325   msaitoh 			>= sc->sc_tbi_serdes_anegticks)) {
   11549  1.325   msaitoh 			DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
   11550  1.325   msaitoh 			sc->sc_tbi_serdes_ticks = 0;
   11551  1.325   msaitoh 			/* XXX */
   11552  1.325   msaitoh 			wm_serdes_mediachange(ifp);
   11553  1.281   msaitoh 		}
   11554  1.192   msaitoh 	}
   11555  1.192   msaitoh 
   11556  1.325   msaitoh 	wm_tbi_serdes_set_linkled(sc);
   11557  1.191   msaitoh }
   11558  1.191   msaitoh 
   11559  1.292   msaitoh /* SFP related */
   11560  1.295   msaitoh 
   11561  1.295   msaitoh static int
   11562  1.295   msaitoh wm_sfp_read_data_byte(struct wm_softc *sc, uint16_t offset, uint8_t *data)
   11563  1.295   msaitoh {
   11564  1.295   msaitoh 	uint32_t i2ccmd;
   11565  1.295   msaitoh 	int i;
   11566  1.295   msaitoh 
   11567  1.295   msaitoh 	i2ccmd = (offset << I2CCMD_REG_ADDR_SHIFT) | I2CCMD_OPCODE_READ;
   11568  1.295   msaitoh 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
   11569  1.295   msaitoh 
   11570  1.295   msaitoh 	/* Poll the ready bit */
   11571  1.295   msaitoh 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
   11572  1.295   msaitoh 		delay(50);
   11573  1.295   msaitoh 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
   11574  1.295   msaitoh 		if (i2ccmd & I2CCMD_READY)
   11575  1.295   msaitoh 			break;
   11576  1.295   msaitoh 	}
   11577  1.295   msaitoh 	if ((i2ccmd & I2CCMD_READY) == 0)
   11578  1.295   msaitoh 		return -1;
   11579  1.295   msaitoh 	if ((i2ccmd & I2CCMD_ERROR) != 0)
   11580  1.295   msaitoh 		return -1;
   11581  1.295   msaitoh 
   11582  1.295   msaitoh 	*data = i2ccmd & 0x00ff;
   11583  1.295   msaitoh 
   11584  1.295   msaitoh 	return 0;
   11585  1.295   msaitoh }
   11586  1.295   msaitoh 
   11587  1.292   msaitoh static uint32_t
   11588  1.295   msaitoh wm_sfp_get_media_type(struct wm_softc *sc)
   11589  1.292   msaitoh {
   11590  1.295   msaitoh 	uint32_t ctrl_ext;
   11591  1.295   msaitoh 	uint8_t val = 0;
   11592  1.295   msaitoh 	int timeout = 3;
   11593  1.311   msaitoh 	uint32_t mediatype = WM_MEDIATYPE_UNKNOWN;
   11594  1.295   msaitoh 	int rv = -1;
   11595  1.292   msaitoh 
   11596  1.295   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   11597  1.295   msaitoh 	ctrl_ext &= ~CTRL_EXT_SWDPIN(3);
   11598  1.295   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_I2C_ENA);
   11599  1.295   msaitoh 	CSR_WRITE_FLUSH(sc);
   11600  1.295   msaitoh 
   11601  1.295   msaitoh 	/* Read SFP module data */
   11602  1.295   msaitoh 	while (timeout) {
   11603  1.295   msaitoh 		rv = wm_sfp_read_data_byte(sc, SFF_SFP_ID_OFF, &val);
   11604  1.295   msaitoh 		if (rv == 0)
   11605  1.295   msaitoh 			break;
   11606  1.295   msaitoh 		delay(100*1000); /* XXX too big */
   11607  1.295   msaitoh 		timeout--;
   11608  1.295   msaitoh 	}
   11609  1.295   msaitoh 	if (rv != 0)
   11610  1.295   msaitoh 		goto out;
   11611  1.295   msaitoh 	switch (val) {
   11612  1.295   msaitoh 	case SFF_SFP_ID_SFF:
   11613  1.295   msaitoh 		aprint_normal_dev(sc->sc_dev,
   11614  1.295   msaitoh 		    "Module/Connector soldered to board\n");
   11615  1.295   msaitoh 		break;
   11616  1.295   msaitoh 	case SFF_SFP_ID_SFP:
   11617  1.295   msaitoh 		aprint_normal_dev(sc->sc_dev, "SFP\n");
   11618  1.295   msaitoh 		break;
   11619  1.295   msaitoh 	case SFF_SFP_ID_UNKNOWN:
   11620  1.295   msaitoh 		goto out;
   11621  1.295   msaitoh 	default:
   11622  1.295   msaitoh 		break;
   11623  1.295   msaitoh 	}
   11624  1.295   msaitoh 
   11625  1.295   msaitoh 	rv = wm_sfp_read_data_byte(sc, SFF_SFP_ETH_FLAGS_OFF, &val);
   11626  1.295   msaitoh 	if (rv != 0) {
   11627  1.295   msaitoh 		goto out;
   11628  1.295   msaitoh 	}
   11629  1.295   msaitoh 
   11630  1.295   msaitoh 	if ((val & (SFF_SFP_ETH_FLAGS_1000SX | SFF_SFP_ETH_FLAGS_1000LX)) != 0)
   11631  1.311   msaitoh 		mediatype = WM_MEDIATYPE_SERDES;
   11632  1.295   msaitoh 	else if ((val & SFF_SFP_ETH_FLAGS_1000T) != 0){
   11633  1.295   msaitoh 		sc->sc_flags |= WM_F_SGMII;
   11634  1.311   msaitoh 		mediatype = WM_MEDIATYPE_COPPER;
   11635  1.295   msaitoh 	} else if ((val & SFF_SFP_ETH_FLAGS_100FX) != 0){
   11636  1.295   msaitoh 		sc->sc_flags |= WM_F_SGMII;
   11637  1.311   msaitoh 		mediatype = WM_MEDIATYPE_SERDES;
   11638  1.295   msaitoh 	}
   11639  1.295   msaitoh 
   11640  1.295   msaitoh out:
   11641  1.295   msaitoh 	/* Restore I2C interface setting */
   11642  1.295   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   11643  1.295   msaitoh 
   11644  1.295   msaitoh 	return mediatype;
   11645  1.292   msaitoh }
   11646  1.453   msaitoh 
   11647  1.191   msaitoh /*
   11648  1.281   msaitoh  * NVM related.
   11649  1.281   msaitoh  * Microwire, SPI (w/wo EERD) and Flash.
   11650  1.265   msaitoh  */
   11651  1.265   msaitoh 
   11652  1.281   msaitoh /* Both spi and uwire */
   11653  1.265   msaitoh 
   11654  1.265   msaitoh /*
   11655  1.281   msaitoh  * wm_eeprom_sendbits:
   11656  1.199   msaitoh  *
   11657  1.281   msaitoh  *	Send a series of bits to the EEPROM.
   11658  1.199   msaitoh  */
   11659  1.281   msaitoh static void
   11660  1.281   msaitoh wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
   11661  1.199   msaitoh {
   11662  1.281   msaitoh 	uint32_t reg;
   11663  1.281   msaitoh 	int x;
   11664  1.199   msaitoh 
   11665  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   11666  1.199   msaitoh 
   11667  1.281   msaitoh 	for (x = nbits; x > 0; x--) {
   11668  1.281   msaitoh 		if (bits & (1U << (x - 1)))
   11669  1.281   msaitoh 			reg |= EECD_DI;
   11670  1.281   msaitoh 		else
   11671  1.281   msaitoh 			reg &= ~EECD_DI;
   11672  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11673  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11674  1.281   msaitoh 		delay(2);
   11675  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   11676  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11677  1.281   msaitoh 		delay(2);
   11678  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11679  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11680  1.281   msaitoh 		delay(2);
   11681  1.199   msaitoh 	}
   11682  1.199   msaitoh }
   11683  1.199   msaitoh 
   11684  1.199   msaitoh /*
   11685  1.281   msaitoh  * wm_eeprom_recvbits:
   11686  1.199   msaitoh  *
   11687  1.281   msaitoh  *	Receive a series of bits from the EEPROM.
   11688  1.199   msaitoh  */
   11689  1.199   msaitoh static void
   11690  1.281   msaitoh wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
   11691  1.199   msaitoh {
   11692  1.281   msaitoh 	uint32_t reg, val;
   11693  1.281   msaitoh 	int x;
   11694  1.199   msaitoh 
   11695  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
   11696  1.199   msaitoh 
   11697  1.281   msaitoh 	val = 0;
   11698  1.281   msaitoh 	for (x = nbits; x > 0; x--) {
   11699  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   11700  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11701  1.281   msaitoh 		delay(2);
   11702  1.281   msaitoh 		if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
   11703  1.281   msaitoh 			val |= (1U << (x - 1));
   11704  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11705  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11706  1.281   msaitoh 		delay(2);
   11707  1.199   msaitoh 	}
   11708  1.281   msaitoh 	*valp = val;
   11709  1.281   msaitoh }
   11710  1.199   msaitoh 
   11711  1.281   msaitoh /* Microwire */
   11712  1.199   msaitoh 
   11713  1.199   msaitoh /*
   11714  1.281   msaitoh  * wm_nvm_read_uwire:
   11715  1.243   msaitoh  *
   11716  1.281   msaitoh  *	Read a word from the EEPROM using the MicroWire protocol.
   11717  1.243   msaitoh  */
   11718  1.243   msaitoh static int
   11719  1.281   msaitoh wm_nvm_read_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   11720  1.243   msaitoh {
   11721  1.281   msaitoh 	uint32_t reg, val;
   11722  1.281   msaitoh 	int i;
   11723  1.281   msaitoh 
   11724  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11725  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11726  1.420   msaitoh 
   11727  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   11728  1.530   msaitoh 		return -1;
   11729  1.530   msaitoh 
   11730  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11731  1.281   msaitoh 		/* Clear SK and DI. */
   11732  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
   11733  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11734  1.281   msaitoh 
   11735  1.281   msaitoh 		/*
   11736  1.281   msaitoh 		 * XXX: workaround for a bug in qemu-0.12.x and prior
   11737  1.281   msaitoh 		 * and Xen.
   11738  1.281   msaitoh 		 *
   11739  1.281   msaitoh 		 * We use this workaround only for 82540 because qemu's
   11740  1.281   msaitoh 		 * e1000 act as 82540.
   11741  1.281   msaitoh 		 */
   11742  1.281   msaitoh 		if (sc->sc_type == WM_T_82540) {
   11743  1.281   msaitoh 			reg |= EECD_SK;
   11744  1.281   msaitoh 			CSR_WRITE(sc, WMREG_EECD, reg);
   11745  1.281   msaitoh 			reg &= ~EECD_SK;
   11746  1.281   msaitoh 			CSR_WRITE(sc, WMREG_EECD, reg);
   11747  1.281   msaitoh 			CSR_WRITE_FLUSH(sc);
   11748  1.281   msaitoh 			delay(2);
   11749  1.281   msaitoh 		}
   11750  1.281   msaitoh 		/* XXX: end of workaround */
   11751  1.332   msaitoh 
   11752  1.281   msaitoh 		/* Set CHIP SELECT. */
   11753  1.281   msaitoh 		reg |= EECD_CS;
   11754  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11755  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11756  1.281   msaitoh 		delay(2);
   11757  1.281   msaitoh 
   11758  1.281   msaitoh 		/* Shift in the READ command. */
   11759  1.281   msaitoh 		wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
   11760  1.281   msaitoh 
   11761  1.281   msaitoh 		/* Shift in address. */
   11762  1.294   msaitoh 		wm_eeprom_sendbits(sc, word + i, sc->sc_nvm_addrbits);
   11763  1.281   msaitoh 
   11764  1.281   msaitoh 		/* Shift out the data. */
   11765  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 16);
   11766  1.281   msaitoh 		data[i] = val & 0xffff;
   11767  1.243   msaitoh 
   11768  1.281   msaitoh 		/* Clear CHIP SELECT. */
   11769  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
   11770  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   11771  1.281   msaitoh 		CSR_WRITE_FLUSH(sc);
   11772  1.281   msaitoh 		delay(2);
   11773  1.243   msaitoh 	}
   11774  1.243   msaitoh 
   11775  1.530   msaitoh 	sc->nvm.release(sc);
   11776  1.281   msaitoh 	return 0;
   11777  1.281   msaitoh }
   11778  1.243   msaitoh 
   11779  1.281   msaitoh /* SPI */
   11780  1.243   msaitoh 
   11781  1.294   msaitoh /*
   11782  1.294   msaitoh  * Set SPI and FLASH related information from the EECD register.
   11783  1.294   msaitoh  * For 82541 and 82547, the word size is taken from EEPROM.
   11784  1.294   msaitoh  */
   11785  1.294   msaitoh static int
   11786  1.294   msaitoh wm_nvm_set_addrbits_size_eecd(struct wm_softc *sc)
   11787  1.243   msaitoh {
   11788  1.294   msaitoh 	int size;
   11789  1.281   msaitoh 	uint32_t reg;
   11790  1.294   msaitoh 	uint16_t data;
   11791  1.243   msaitoh 
   11792  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   11793  1.294   msaitoh 	sc->sc_nvm_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
   11794  1.294   msaitoh 
   11795  1.294   msaitoh 	/* Read the size of NVM from EECD by default */
   11796  1.294   msaitoh 	size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);
   11797  1.294   msaitoh 	switch (sc->sc_type) {
   11798  1.294   msaitoh 	case WM_T_82541:
   11799  1.294   msaitoh 	case WM_T_82541_2:
   11800  1.294   msaitoh 	case WM_T_82547:
   11801  1.294   msaitoh 	case WM_T_82547_2:
   11802  1.294   msaitoh 		/* Set dummy value to access EEPROM */
   11803  1.294   msaitoh 		sc->sc_nvm_wordsize = 64;
   11804  1.535   msaitoh 		if (wm_nvm_read(sc, NVM_OFF_EEPROM_SIZE, 1, &data) != 0) {
   11805  1.535   msaitoh 			aprint_error_dev(sc->sc_dev,
   11806  1.535   msaitoh 			    "%s: failed to read EEPROM size\n", __func__);
   11807  1.535   msaitoh 		}
   11808  1.294   msaitoh 		reg = data;
   11809  1.294   msaitoh 		size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);
   11810  1.294   msaitoh 		if (size == 0)
   11811  1.294   msaitoh 			size = 6; /* 64 word size */
   11812  1.294   msaitoh 		else
   11813  1.294   msaitoh 			size += NVM_WORD_SIZE_BASE_SHIFT + 1;
   11814  1.294   msaitoh 		break;
   11815  1.294   msaitoh 	case WM_T_80003:
   11816  1.294   msaitoh 	case WM_T_82571:
   11817  1.294   msaitoh 	case WM_T_82572:
   11818  1.294   msaitoh 	case WM_T_82573: /* SPI case */
   11819  1.294   msaitoh 	case WM_T_82574: /* SPI case */
   11820  1.294   msaitoh 	case WM_T_82583: /* SPI case */
   11821  1.294   msaitoh 		size += NVM_WORD_SIZE_BASE_SHIFT;
   11822  1.294   msaitoh 		if (size > 14)
   11823  1.294   msaitoh 			size = 14;
   11824  1.294   msaitoh 		break;
   11825  1.294   msaitoh 	case WM_T_82575:
   11826  1.294   msaitoh 	case WM_T_82576:
   11827  1.294   msaitoh 	case WM_T_82580:
   11828  1.294   msaitoh 	case WM_T_I350:
   11829  1.294   msaitoh 	case WM_T_I354:
   11830  1.294   msaitoh 	case WM_T_I210:
   11831  1.294   msaitoh 	case WM_T_I211:
   11832  1.294   msaitoh 		size += NVM_WORD_SIZE_BASE_SHIFT;
   11833  1.294   msaitoh 		if (size > 15)
   11834  1.294   msaitoh 			size = 15;
   11835  1.294   msaitoh 		break;
   11836  1.294   msaitoh 	default:
   11837  1.294   msaitoh 		aprint_error_dev(sc->sc_dev,
   11838  1.294   msaitoh 		    "%s: unknown device(%d)?\n", __func__, sc->sc_type);
   11839  1.294   msaitoh 		return -1;
   11840  1.294   msaitoh 		break;
   11841  1.294   msaitoh 	}
   11842  1.294   msaitoh 
   11843  1.294   msaitoh 	sc->sc_nvm_wordsize = 1 << size;
   11844  1.294   msaitoh 
   11845  1.294   msaitoh 	return 0;
   11846  1.243   msaitoh }
   11847  1.243   msaitoh 
   11848  1.243   msaitoh /*
   11849  1.281   msaitoh  * wm_nvm_ready_spi:
   11850    1.1   thorpej  *
   11851  1.281   msaitoh  *	Wait for a SPI EEPROM to be ready for commands.
   11852    1.1   thorpej  */
   11853  1.281   msaitoh static int
   11854  1.281   msaitoh wm_nvm_ready_spi(struct wm_softc *sc)
   11855    1.1   thorpej {
   11856  1.281   msaitoh 	uint32_t val;
   11857  1.281   msaitoh 	int usec;
   11858    1.1   thorpej 
   11859  1.421   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11860  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   11861  1.421   msaitoh 
   11862  1.281   msaitoh 	for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) {
   11863  1.281   msaitoh 		wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8);
   11864  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 8);
   11865  1.281   msaitoh 		if ((val & SPI_SR_RDY) == 0)
   11866  1.281   msaitoh 			break;
   11867   1.71   thorpej 	}
   11868  1.281   msaitoh 	if (usec >= SPI_MAX_RETRIES) {
   11869  1.388   msaitoh 		aprint_error_dev(sc->sc_dev,"EEPROM failed to become ready\n");
   11870  1.530   msaitoh 		return -1;
   11871  1.127    bouyer 	}
   11872  1.281   msaitoh 	return 0;
   11873  1.127    bouyer }
   11874  1.127    bouyer 
   11875  1.127    bouyer /*
   11876  1.281   msaitoh  * wm_nvm_read_spi:
   11877  1.127    bouyer  *
   11878  1.281   msaitoh  *	Read a work from the EEPROM using the SPI protocol.
   11879  1.127    bouyer  */
   11880  1.127    bouyer static int
   11881  1.281   msaitoh wm_nvm_read_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   11882  1.127    bouyer {
   11883  1.281   msaitoh 	uint32_t reg, val;
   11884  1.281   msaitoh 	int i;
   11885  1.281   msaitoh 	uint8_t opc;
   11886  1.530   msaitoh 	int rv = 0;
   11887  1.281   msaitoh 
   11888  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11889  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11890  1.420   msaitoh 
   11891  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   11892  1.530   msaitoh 		return -1;
   11893  1.530   msaitoh 
   11894  1.281   msaitoh 	/* Clear SK and CS. */
   11895  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
   11896  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11897  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11898  1.281   msaitoh 	delay(2);
   11899  1.127    bouyer 
   11900  1.530   msaitoh 	if ((rv = wm_nvm_ready_spi(sc)) != 0)
   11901  1.530   msaitoh 		goto out;
   11902  1.127    bouyer 
   11903  1.281   msaitoh 	/* Toggle CS to flush commands. */
   11904  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
   11905  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11906  1.281   msaitoh 	delay(2);
   11907  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11908  1.266   msaitoh 	CSR_WRITE_FLUSH(sc);
   11909  1.127    bouyer 	delay(2);
   11910  1.127    bouyer 
   11911  1.281   msaitoh 	opc = SPI_OPC_READ;
   11912  1.294   msaitoh 	if (sc->sc_nvm_addrbits == 8 && word >= 128)
   11913  1.281   msaitoh 		opc |= SPI_OPC_A8;
   11914  1.281   msaitoh 
   11915  1.281   msaitoh 	wm_eeprom_sendbits(sc, opc, 8);
   11916  1.294   msaitoh 	wm_eeprom_sendbits(sc, word << 1, sc->sc_nvm_addrbits);
   11917  1.281   msaitoh 
   11918  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11919  1.281   msaitoh 		wm_eeprom_recvbits(sc, &val, 16);
   11920  1.281   msaitoh 		data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
   11921  1.281   msaitoh 	}
   11922  1.178   msaitoh 
   11923  1.281   msaitoh 	/* Raise CS and clear SK. */
   11924  1.281   msaitoh 	reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
   11925  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   11926  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   11927  1.281   msaitoh 	delay(2);
   11928  1.178   msaitoh 
   11929  1.530   msaitoh out:
   11930  1.530   msaitoh 	sc->nvm.release(sc);
   11931  1.530   msaitoh 	return rv;
   11932  1.127    bouyer }
   11933  1.127    bouyer 
   11934  1.281   msaitoh /* Using with EERD */
   11935  1.281   msaitoh 
   11936  1.281   msaitoh static int
   11937  1.281   msaitoh wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
   11938  1.127    bouyer {
   11939  1.281   msaitoh 	uint32_t attempts = 100000;
   11940  1.281   msaitoh 	uint32_t i, reg = 0;
   11941  1.281   msaitoh 	int32_t done = -1;
   11942  1.281   msaitoh 
   11943  1.281   msaitoh 	for (i = 0; i < attempts; i++) {
   11944  1.281   msaitoh 		reg = CSR_READ(sc, rw);
   11945  1.127    bouyer 
   11946  1.281   msaitoh 		if (reg & EERD_DONE) {
   11947  1.281   msaitoh 			done = 0;
   11948  1.281   msaitoh 			break;
   11949  1.178   msaitoh 		}
   11950  1.281   msaitoh 		delay(5);
   11951  1.169   msaitoh 	}
   11952  1.127    bouyer 
   11953  1.281   msaitoh 	return done;
   11954    1.1   thorpej }
   11955  1.117   msaitoh 
   11956  1.117   msaitoh static int
   11957  1.573   msaitoh wm_nvm_read_eerd(struct wm_softc *sc, int offset, int wordcnt, uint16_t *data)
   11958  1.117   msaitoh {
   11959  1.281   msaitoh 	int i, eerd = 0;
   11960  1.530   msaitoh 	int rv = 0;
   11961  1.117   msaitoh 
   11962  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   11963  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   11964  1.420   msaitoh 
   11965  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   11966  1.530   msaitoh 		return -1;
   11967  1.530   msaitoh 
   11968  1.281   msaitoh 	for (i = 0; i < wordcnt; i++) {
   11969  1.281   msaitoh 		eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
   11970  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EERD, eerd);
   11971  1.530   msaitoh 		rv = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
   11972  1.530   msaitoh 		if (rv != 0) {
   11973  1.539   msaitoh 			aprint_error_dev(sc->sc_dev, "EERD polling failed: "
   11974  1.539   msaitoh 			    "offset=%d. wordcnt=%d\n", offset, wordcnt);
   11975  1.281   msaitoh 			break;
   11976  1.530   msaitoh 		}
   11977  1.281   msaitoh 		data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
   11978  1.117   msaitoh 	}
   11979  1.281   msaitoh 
   11980  1.530   msaitoh 	sc->nvm.release(sc);
   11981  1.530   msaitoh 	return rv;
   11982  1.117   msaitoh }
   11983  1.117   msaitoh 
   11984  1.281   msaitoh /* Flash */
   11985  1.281   msaitoh 
   11986  1.117   msaitoh static int
   11987  1.281   msaitoh wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank)
   11988  1.117   msaitoh {
   11989  1.281   msaitoh 	uint32_t eecd;
   11990  1.281   msaitoh 	uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1;
   11991  1.281   msaitoh 	uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t);
   11992  1.570   msaitoh 	uint32_t nvm_dword = 0;
   11993  1.281   msaitoh 	uint8_t sig_byte = 0;
   11994  1.568   msaitoh  	int rv;
   11995  1.117   msaitoh 
   11996  1.281   msaitoh 	switch (sc->sc_type) {
   11997  1.392   msaitoh 	case WM_T_PCH_SPT:
   11998  1.570   msaitoh 	case WM_T_PCH_CNP:
   11999  1.568   msaitoh 		bank1_offset = sc->sc_ich8_flash_bank_size * 2;
   12000  1.568   msaitoh 		act_offset = ICH_NVM_SIG_WORD * 2;
   12001  1.568   msaitoh 
   12002  1.568   msaitoh 		/* set bank to 0 in case flash read fails. */
   12003  1.568   msaitoh 		*bank = 0;
   12004  1.568   msaitoh 
   12005  1.568   msaitoh 		/* Check bank 0 */
   12006  1.568   msaitoh 		rv = wm_read_ich8_dword(sc, act_offset, &nvm_dword);
   12007  1.568   msaitoh 		if (rv != 0)
   12008  1.568   msaitoh 			return rv;
   12009  1.568   msaitoh 		sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
   12010  1.568   msaitoh 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
   12011  1.568   msaitoh 			*bank = 0;
   12012  1.568   msaitoh 			return 0;
   12013  1.568   msaitoh 		}
   12014  1.568   msaitoh 
   12015  1.568   msaitoh 		/* Check bank 1 */
   12016  1.568   msaitoh 		rv = wm_read_ich8_dword(sc, act_offset + bank1_offset,
   12017  1.568   msaitoh 		    &nvm_dword);
   12018  1.568   msaitoh 		sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
   12019  1.568   msaitoh 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
   12020  1.568   msaitoh 			*bank = 1;
   12021  1.392   msaitoh 			return 0;
   12022  1.392   msaitoh 		}
   12023  1.568   msaitoh 		aprint_error_dev(sc->sc_dev,
   12024  1.568   msaitoh 		    "%s: no valid NVM bank present (%u)\n", __func__, *bank);
   12025  1.568   msaitoh 		return -1;
   12026  1.281   msaitoh 	case WM_T_ICH8:
   12027  1.281   msaitoh 	case WM_T_ICH9:
   12028  1.281   msaitoh 		eecd = CSR_READ(sc, WMREG_EECD);
   12029  1.281   msaitoh 		if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) {
   12030  1.281   msaitoh 			*bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0;
   12031  1.281   msaitoh 			return 0;
   12032  1.281   msaitoh 		}
   12033  1.281   msaitoh 		/* FALLTHROUGH */
   12034  1.281   msaitoh 	default:
   12035  1.281   msaitoh 		/* Default to 0 */
   12036  1.281   msaitoh 		*bank = 0;
   12037  1.271     ozaki 
   12038  1.281   msaitoh 		/* Check bank 0 */
   12039  1.281   msaitoh 		wm_read_ich8_byte(sc, act_offset, &sig_byte);
   12040  1.281   msaitoh 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
   12041  1.281   msaitoh 			*bank = 0;
   12042  1.281   msaitoh 			return 0;
   12043  1.281   msaitoh 		}
   12044  1.271     ozaki 
   12045  1.281   msaitoh 		/* Check bank 1 */
   12046  1.281   msaitoh 		wm_read_ich8_byte(sc, act_offset + bank1_offset,
   12047  1.281   msaitoh 		    &sig_byte);
   12048  1.281   msaitoh 		if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) {
   12049  1.281   msaitoh 			*bank = 1;
   12050  1.281   msaitoh 			return 0;
   12051  1.281   msaitoh 		}
   12052  1.271     ozaki 	}
   12053  1.271     ozaki 
   12054  1.281   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: No valid NVM bank present\n",
   12055  1.281   msaitoh 		device_xname(sc->sc_dev)));
   12056  1.281   msaitoh 	return -1;
   12057  1.281   msaitoh }
   12058  1.281   msaitoh 
   12059  1.281   msaitoh /******************************************************************************
   12060  1.281   msaitoh  * This function does initial flash setup so that a new read/write/erase cycle
   12061  1.281   msaitoh  * can be started.
   12062  1.281   msaitoh  *
   12063  1.281   msaitoh  * sc - The pointer to the hw structure
   12064  1.281   msaitoh  ****************************************************************************/
   12065  1.281   msaitoh static int32_t
   12066  1.281   msaitoh wm_ich8_cycle_init(struct wm_softc *sc)
   12067  1.281   msaitoh {
   12068  1.281   msaitoh 	uint16_t hsfsts;
   12069  1.281   msaitoh 	int32_t error = 1;
   12070  1.281   msaitoh 	int32_t i     = 0;
   12071  1.271     ozaki 
   12072  1.567   msaitoh 	if (sc->sc_type >= WM_T_PCH_SPT)
   12073  1.567   msaitoh 		hsfsts = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS) & 0xffffUL;
   12074  1.567   msaitoh 	else
   12075  1.567   msaitoh 		hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   12076  1.117   msaitoh 
   12077  1.281   msaitoh 	/* May be check the Flash Des Valid bit in Hw status */
   12078  1.281   msaitoh 	if ((hsfsts & HSFSTS_FLDVAL) == 0) {
   12079  1.281   msaitoh 		return error;
   12080  1.117   msaitoh 	}
   12081  1.117   msaitoh 
   12082  1.281   msaitoh 	/* Clear FCERR in Hw status by writing 1 */
   12083  1.281   msaitoh 	/* Clear DAEL in Hw status by writing a 1 */
   12084  1.281   msaitoh 	hsfsts |= HSFSTS_ERR | HSFSTS_DAEL;
   12085  1.117   msaitoh 
   12086  1.567   msaitoh 	if (sc->sc_type >= WM_T_PCH_SPT)
   12087  1.567   msaitoh 		ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS, hsfsts & 0xffffUL);
   12088  1.567   msaitoh 	else
   12089  1.567   msaitoh 		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   12090  1.117   msaitoh 
   12091  1.281   msaitoh 	/*
   12092  1.281   msaitoh 	 * Either we should have a hardware SPI cycle in progress bit to check
   12093  1.281   msaitoh 	 * against, in order to start a new cycle or FDONE bit should be
   12094  1.281   msaitoh 	 * changed in the hardware so that it is 1 after harware reset, which
   12095  1.281   msaitoh 	 * can then be used as an indication whether a cycle is in progress or
   12096  1.281   msaitoh 	 * has been completed .. we should also have some software semaphore
   12097  1.281   msaitoh 	 * mechanism to guard FDONE or the cycle in progress bit so that two
   12098  1.281   msaitoh 	 * threads access to those bits can be sequentiallized or a way so that
   12099  1.281   msaitoh 	 * 2 threads dont start the cycle at the same time
   12100  1.281   msaitoh 	 */
   12101  1.127    bouyer 
   12102  1.281   msaitoh 	if ((hsfsts & HSFSTS_FLINPRO) == 0) {
   12103  1.281   msaitoh 		/*
   12104  1.281   msaitoh 		 * There is no cycle running at present, so we can start a
   12105  1.281   msaitoh 		 * cycle
   12106  1.281   msaitoh 		 */
   12107  1.127    bouyer 
   12108  1.281   msaitoh 		/* Begin by setting Flash Cycle Done. */
   12109  1.281   msaitoh 		hsfsts |= HSFSTS_DONE;
   12110  1.567   msaitoh 		if (sc->sc_type >= WM_T_PCH_SPT)
   12111  1.567   msaitoh 			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
   12112  1.567   msaitoh 			    hsfsts & 0xffffUL);
   12113  1.567   msaitoh 		else
   12114  1.567   msaitoh 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts);
   12115  1.281   msaitoh 		error = 0;
   12116  1.281   msaitoh 	} else {
   12117  1.281   msaitoh 		/*
   12118  1.281   msaitoh 		 * otherwise poll for sometime so the current cycle has a
   12119  1.281   msaitoh 		 * chance to end before giving up.
   12120  1.281   msaitoh 		 */
   12121  1.281   msaitoh 		for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
   12122  1.567   msaitoh 			if (sc->sc_type >= WM_T_PCH_SPT)
   12123  1.567   msaitoh 				hsfsts = ICH8_FLASH_READ32(sc,
   12124  1.567   msaitoh 				    ICH_FLASH_HSFSTS) & 0xffffUL;
   12125  1.567   msaitoh 			else
   12126  1.567   msaitoh 				hsfsts = ICH8_FLASH_READ16(sc,
   12127  1.567   msaitoh 				    ICH_FLASH_HSFSTS);
   12128  1.281   msaitoh 			if ((hsfsts & HSFSTS_FLINPRO) == 0) {
   12129  1.281   msaitoh 				error = 0;
   12130  1.281   msaitoh 				break;
   12131  1.169   msaitoh 			}
   12132  1.281   msaitoh 			delay(1);
   12133  1.127    bouyer 		}
   12134  1.281   msaitoh 		if (error == 0) {
   12135  1.281   msaitoh 			/*
   12136  1.281   msaitoh 			 * Successful in waiting for previous cycle to timeout,
   12137  1.281   msaitoh 			 * now set the Flash Cycle Done.
   12138  1.281   msaitoh 			 */
   12139  1.281   msaitoh 			hsfsts |= HSFSTS_DONE;
   12140  1.567   msaitoh 			if (sc->sc_type >= WM_T_PCH_SPT)
   12141  1.567   msaitoh 				ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
   12142  1.567   msaitoh 				    hsfsts & 0xffffUL);
   12143  1.567   msaitoh 			else
   12144  1.567   msaitoh 				ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS,
   12145  1.567   msaitoh 				    hsfsts);
   12146  1.127    bouyer 		}
   12147  1.127    bouyer 	}
   12148  1.281   msaitoh 	return error;
   12149  1.127    bouyer }
   12150  1.127    bouyer 
   12151  1.281   msaitoh /******************************************************************************
   12152  1.281   msaitoh  * This function starts a flash cycle and waits for its completion
   12153  1.281   msaitoh  *
   12154  1.281   msaitoh  * sc - The pointer to the hw structure
   12155  1.281   msaitoh  ****************************************************************************/
   12156  1.281   msaitoh static int32_t
   12157  1.281   msaitoh wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout)
   12158  1.136   msaitoh {
   12159  1.281   msaitoh 	uint16_t hsflctl;
   12160  1.281   msaitoh 	uint16_t hsfsts;
   12161  1.281   msaitoh 	int32_t error = 1;
   12162  1.281   msaitoh 	uint32_t i = 0;
   12163  1.127    bouyer 
   12164  1.281   msaitoh 	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
   12165  1.567   msaitoh 	if (sc->sc_type >= WM_T_PCH_SPT)
   12166  1.567   msaitoh 		hsflctl = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS) >> 16;
   12167  1.567   msaitoh 	else
   12168  1.567   msaitoh 		hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
   12169  1.281   msaitoh 	hsflctl |= HSFCTL_GO;
   12170  1.567   msaitoh 	if (sc->sc_type >= WM_T_PCH_SPT)
   12171  1.567   msaitoh 		ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
   12172  1.567   msaitoh 		    (uint32_t)hsflctl << 16);
   12173  1.567   msaitoh 	else
   12174  1.567   msaitoh 		ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
   12175  1.139    bouyer 
   12176  1.281   msaitoh 	/* Wait till FDONE bit is set to 1 */
   12177  1.281   msaitoh 	do {
   12178  1.567   msaitoh 		if (sc->sc_type >= WM_T_PCH_SPT)
   12179  1.567   msaitoh 			hsfsts = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS)
   12180  1.567   msaitoh 			    & 0xffffUL;
   12181  1.567   msaitoh 		else
   12182  1.567   msaitoh 			hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS);
   12183  1.281   msaitoh 		if (hsfsts & HSFSTS_DONE)
   12184  1.281   msaitoh 			break;
   12185  1.281   msaitoh 		delay(1);
   12186  1.281   msaitoh 		i++;
   12187  1.281   msaitoh 	} while (i < timeout);
   12188  1.281   msaitoh 	if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0)
   12189  1.281   msaitoh 		error = 0;
   12190  1.139    bouyer 
   12191  1.281   msaitoh 	return error;
   12192  1.139    bouyer }
   12193  1.139    bouyer 
   12194  1.281   msaitoh /******************************************************************************
   12195  1.392   msaitoh  * Reads a byte or (d)word from the NVM using the ICH8 flash access registers.
   12196  1.281   msaitoh  *
   12197  1.281   msaitoh  * sc - The pointer to the hw structure
   12198  1.281   msaitoh  * index - The index of the byte or word to read.
   12199  1.392   msaitoh  * size - Size of data to read, 1=byte 2=word, 4=dword
   12200  1.281   msaitoh  * data - Pointer to the word to store the value read.
   12201  1.281   msaitoh  *****************************************************************************/
   12202  1.281   msaitoh static int32_t
   12203  1.281   msaitoh wm_read_ich8_data(struct wm_softc *sc, uint32_t index,
   12204  1.392   msaitoh     uint32_t size, uint32_t *data)
   12205  1.139    bouyer {
   12206  1.281   msaitoh 	uint16_t hsfsts;
   12207  1.281   msaitoh 	uint16_t hsflctl;
   12208  1.281   msaitoh 	uint32_t flash_linear_address;
   12209  1.281   msaitoh 	uint32_t flash_data = 0;
   12210  1.281   msaitoh 	int32_t error = 1;
   12211  1.281   msaitoh 	int32_t count = 0;
   12212  1.281   msaitoh 
   12213  1.392   msaitoh 	if (size < 1  || size > 4 || data == 0x0 ||
   12214  1.281   msaitoh 	    index > ICH_FLASH_LINEAR_ADDR_MASK)
   12215  1.281   msaitoh 		return error;
   12216  1.139    bouyer 
   12217  1.281   msaitoh 	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
   12218  1.281   msaitoh 	    sc->sc_ich8_flash_base;
   12219  1.259   msaitoh 
   12220  1.259   msaitoh 	do {
   12221  1.281   msaitoh 		delay(1);
   12222  1.281   msaitoh 		/* Steps */
   12223  1.281   msaitoh 		error = wm_ich8_cycle_init(sc);
   12224  1.281   msaitoh 		if (error)
   12225  1.259   msaitoh 			break;
   12226  1.259   msaitoh 
   12227  1.567   msaitoh 		if (sc->sc_type >= WM_T_PCH_SPT)
   12228  1.567   msaitoh 			hsflctl = ICH8_FLASH_READ32(sc, ICH_FLASH_HSFSTS)
   12229  1.567   msaitoh 			    >> 16;
   12230  1.567   msaitoh 		else
   12231  1.567   msaitoh 			hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL);
   12232  1.281   msaitoh 		/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
   12233  1.281   msaitoh 		hsflctl |=  ((size - 1) << HSFCTL_BCOUNT_SHIFT)
   12234  1.281   msaitoh 		    & HSFCTL_BCOUNT_MASK;
   12235  1.281   msaitoh 		hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT;
   12236  1.567   msaitoh 		if (sc->sc_type >= WM_T_PCH_SPT) {
   12237  1.392   msaitoh 			/*
   12238  1.392   msaitoh 			 * In SPT, This register is in Lan memory space, not
   12239  1.392   msaitoh 			 * flash. Therefore, only 32 bit access is supported.
   12240  1.392   msaitoh 			 */
   12241  1.567   msaitoh 			ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFSTS,
   12242  1.567   msaitoh 			    (uint32_t)hsflctl << 16);
   12243  1.392   msaitoh 		} else
   12244  1.392   msaitoh 			ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl);
   12245  1.281   msaitoh 
   12246  1.281   msaitoh 		/*
   12247  1.281   msaitoh 		 * Write the last 24 bits of index into Flash Linear address
   12248  1.281   msaitoh 		 * field in Flash Address
   12249  1.281   msaitoh 		 */
   12250  1.281   msaitoh 		/* TODO: TBD maybe check the index against the size of flash */
   12251  1.281   msaitoh 
   12252  1.281   msaitoh 		ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address);
   12253  1.259   msaitoh 
   12254  1.281   msaitoh 		error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT);
   12255  1.259   msaitoh 
   12256  1.281   msaitoh 		/*
   12257  1.281   msaitoh 		 * Check if FCERR is set to 1, if set to 1, clear it and try
   12258  1.281   msaitoh 		 * the whole sequence a few more times, else read in (shift in)
   12259  1.281   msaitoh 		 * the Flash Data0, the order is least significant byte first
   12260  1.281   msaitoh 		 * msb to lsb
   12261  1.281   msaitoh 		 */
   12262  1.281   msaitoh 		if (error == 0) {
   12263  1.281   msaitoh 			flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0);
   12264  1.281   msaitoh 			if (size == 1)
   12265  1.281   msaitoh 				*data = (uint8_t)(flash_data & 0x000000FF);
   12266  1.281   msaitoh 			else if (size == 2)
   12267  1.281   msaitoh 				*data = (uint16_t)(flash_data & 0x0000FFFF);
   12268  1.392   msaitoh 			else if (size == 4)
   12269  1.392   msaitoh 				*data = (uint32_t)flash_data;
   12270  1.281   msaitoh 			break;
   12271  1.281   msaitoh 		} else {
   12272  1.281   msaitoh 			/*
   12273  1.281   msaitoh 			 * If we've gotten here, then things are probably
   12274  1.281   msaitoh 			 * completely hosed, but if the error condition is
   12275  1.281   msaitoh 			 * detected, it won't hurt to give it another try...
   12276  1.281   msaitoh 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
   12277  1.281   msaitoh 			 */
   12278  1.567   msaitoh 			if (sc->sc_type >= WM_T_PCH_SPT)
   12279  1.567   msaitoh 				hsfsts = ICH8_FLASH_READ32(sc,
   12280  1.567   msaitoh 				    ICH_FLASH_HSFSTS) & 0xffffUL;
   12281  1.567   msaitoh 			else
   12282  1.567   msaitoh 				hsfsts = ICH8_FLASH_READ16(sc,
   12283  1.567   msaitoh 				    ICH_FLASH_HSFSTS);
   12284  1.567   msaitoh 
   12285  1.281   msaitoh 			if (hsfsts & HSFSTS_ERR) {
   12286  1.281   msaitoh 				/* Repeat for some time before giving up. */
   12287  1.281   msaitoh 				continue;
   12288  1.281   msaitoh 			} else if ((hsfsts & HSFSTS_DONE) == 0)
   12289  1.281   msaitoh 				break;
   12290  1.281   msaitoh 		}
   12291  1.281   msaitoh 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
   12292  1.259   msaitoh 
   12293  1.281   msaitoh 	return error;
   12294  1.259   msaitoh }
   12295  1.259   msaitoh 
   12296  1.281   msaitoh /******************************************************************************
   12297  1.281   msaitoh  * Reads a single byte from the NVM using the ICH8 flash access registers.
   12298  1.281   msaitoh  *
   12299  1.281   msaitoh  * sc - pointer to wm_hw structure
   12300  1.281   msaitoh  * index - The index of the byte to read.
   12301  1.281   msaitoh  * data - Pointer to a byte to store the value read.
   12302  1.281   msaitoh  *****************************************************************************/
   12303  1.281   msaitoh static int32_t
   12304  1.281   msaitoh wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data)
   12305  1.169   msaitoh {
   12306  1.281   msaitoh 	int32_t status;
   12307  1.392   msaitoh 	uint32_t word = 0;
   12308  1.250   msaitoh 
   12309  1.281   msaitoh 	status = wm_read_ich8_data(sc, index, 1, &word);
   12310  1.281   msaitoh 	if (status == 0)
   12311  1.281   msaitoh 		*data = (uint8_t)word;
   12312  1.281   msaitoh 	else
   12313  1.281   msaitoh 		*data = 0;
   12314  1.169   msaitoh 
   12315  1.281   msaitoh 	return status;
   12316  1.281   msaitoh }
   12317  1.250   msaitoh 
   12318  1.281   msaitoh /******************************************************************************
   12319  1.281   msaitoh  * Reads a word from the NVM using the ICH8 flash access registers.
   12320  1.281   msaitoh  *
   12321  1.281   msaitoh  * sc - pointer to wm_hw structure
   12322  1.281   msaitoh  * index - The starting byte index of the word to read.
   12323  1.281   msaitoh  * data - Pointer to a word to store the value read.
   12324  1.281   msaitoh  *****************************************************************************/
   12325  1.281   msaitoh static int32_t
   12326  1.281   msaitoh wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data)
   12327  1.281   msaitoh {
   12328  1.281   msaitoh 	int32_t status;
   12329  1.392   msaitoh 	uint32_t word = 0;
   12330  1.392   msaitoh 
   12331  1.392   msaitoh 	status = wm_read_ich8_data(sc, index, 2, &word);
   12332  1.392   msaitoh 	if (status == 0)
   12333  1.392   msaitoh 		*data = (uint16_t)word;
   12334  1.392   msaitoh 	else
   12335  1.392   msaitoh 		*data = 0;
   12336  1.392   msaitoh 
   12337  1.392   msaitoh 	return status;
   12338  1.392   msaitoh }
   12339  1.392   msaitoh 
   12340  1.392   msaitoh /******************************************************************************
   12341  1.392   msaitoh  * Reads a dword from the NVM using the ICH8 flash access registers.
   12342  1.392   msaitoh  *
   12343  1.392   msaitoh  * sc - pointer to wm_hw structure
   12344  1.392   msaitoh  * index - The starting byte index of the word to read.
   12345  1.392   msaitoh  * data - Pointer to a word to store the value read.
   12346  1.392   msaitoh  *****************************************************************************/
   12347  1.392   msaitoh static int32_t
   12348  1.392   msaitoh wm_read_ich8_dword(struct wm_softc *sc, uint32_t index, uint32_t *data)
   12349  1.392   msaitoh {
   12350  1.392   msaitoh 	int32_t status;
   12351  1.169   msaitoh 
   12352  1.392   msaitoh 	status = wm_read_ich8_data(sc, index, 4, data);
   12353  1.281   msaitoh 	return status;
   12354  1.169   msaitoh }
   12355  1.169   msaitoh 
   12356  1.139    bouyer /******************************************************************************
   12357  1.139    bouyer  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
   12358  1.139    bouyer  * register.
   12359  1.139    bouyer  *
   12360  1.139    bouyer  * sc - Struct containing variables accessed by shared code
   12361  1.139    bouyer  * offset - offset of word in the EEPROM to read
   12362  1.139    bouyer  * data - word read from the EEPROM
   12363  1.139    bouyer  * words - number of words to read
   12364  1.139    bouyer  *****************************************************************************/
   12365  1.139    bouyer static int
   12366  1.280   msaitoh wm_nvm_read_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data)
   12367  1.139    bouyer {
   12368  1.530   msaitoh 	int32_t  rv = 0;
   12369  1.194   msaitoh 	uint32_t flash_bank = 0;
   12370  1.194   msaitoh 	uint32_t act_offset = 0;
   12371  1.194   msaitoh 	uint32_t bank_offset = 0;
   12372  1.194   msaitoh 	uint16_t word = 0;
   12373  1.194   msaitoh 	uint16_t i = 0;
   12374  1.194   msaitoh 
   12375  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12376  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12377  1.420   msaitoh 
   12378  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   12379  1.530   msaitoh 		return -1;
   12380  1.530   msaitoh 
   12381  1.281   msaitoh 	/*
   12382  1.281   msaitoh 	 * We need to know which is the valid flash bank.  In the event
   12383  1.194   msaitoh 	 * that we didn't allocate eeprom_shadow_ram, we may not be
   12384  1.194   msaitoh 	 * managing flash_bank.  So it cannot be trusted and needs
   12385  1.194   msaitoh 	 * to be updated with each read.
   12386  1.194   msaitoh 	 */
   12387  1.530   msaitoh 	rv = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
   12388  1.530   msaitoh 	if (rv) {
   12389  1.297   msaitoh 		DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
   12390  1.297   msaitoh 			device_xname(sc->sc_dev)));
   12391  1.262   msaitoh 		flash_bank = 0;
   12392  1.194   msaitoh 	}
   12393  1.139    bouyer 
   12394  1.238   msaitoh 	/*
   12395  1.238   msaitoh 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
   12396  1.238   msaitoh 	 * size
   12397  1.238   msaitoh 	 */
   12398  1.194   msaitoh 	bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
   12399  1.139    bouyer 
   12400  1.194   msaitoh 	for (i = 0; i < words; i++) {
   12401  1.194   msaitoh 		/* The NVM part needs a byte offset, hence * 2 */
   12402  1.194   msaitoh 		act_offset = bank_offset + ((offset + i) * 2);
   12403  1.530   msaitoh 		rv = wm_read_ich8_word(sc, act_offset, &word);
   12404  1.530   msaitoh 		if (rv) {
   12405  1.238   msaitoh 			aprint_error_dev(sc->sc_dev,
   12406  1.238   msaitoh 			    "%s: failed to read NVM\n", __func__);
   12407  1.194   msaitoh 			break;
   12408  1.194   msaitoh 		}
   12409  1.194   msaitoh 		data[i] = word;
   12410  1.194   msaitoh 	}
   12411  1.194   msaitoh 
   12412  1.530   msaitoh 	sc->nvm.release(sc);
   12413  1.530   msaitoh 	return rv;
   12414  1.139    bouyer }
   12415  1.139    bouyer 
   12416  1.392   msaitoh /******************************************************************************
   12417  1.392   msaitoh  * Reads a 16 bit word or words from the EEPROM using the SPT's flash access
   12418  1.392   msaitoh  * register.
   12419  1.392   msaitoh  *
   12420  1.392   msaitoh  * sc - Struct containing variables accessed by shared code
   12421  1.392   msaitoh  * offset - offset of word in the EEPROM to read
   12422  1.392   msaitoh  * data - word read from the EEPROM
   12423  1.392   msaitoh  * words - number of words to read
   12424  1.392   msaitoh  *****************************************************************************/
   12425  1.392   msaitoh static int
   12426  1.392   msaitoh wm_nvm_read_spt(struct wm_softc *sc, int offset, int words, uint16_t *data)
   12427  1.392   msaitoh {
   12428  1.530   msaitoh 	int32_t  rv = 0;
   12429  1.392   msaitoh 	uint32_t flash_bank = 0;
   12430  1.392   msaitoh 	uint32_t act_offset = 0;
   12431  1.392   msaitoh 	uint32_t bank_offset = 0;
   12432  1.392   msaitoh 	uint32_t dword = 0;
   12433  1.392   msaitoh 	uint16_t i = 0;
   12434  1.392   msaitoh 
   12435  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12436  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12437  1.420   msaitoh 
   12438  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   12439  1.530   msaitoh 		return -1;
   12440  1.530   msaitoh 
   12441  1.392   msaitoh 	/*
   12442  1.392   msaitoh 	 * We need to know which is the valid flash bank.  In the event
   12443  1.392   msaitoh 	 * that we didn't allocate eeprom_shadow_ram, we may not be
   12444  1.392   msaitoh 	 * managing flash_bank.  So it cannot be trusted and needs
   12445  1.392   msaitoh 	 * to be updated with each read.
   12446  1.392   msaitoh 	 */
   12447  1.530   msaitoh 	rv = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank);
   12448  1.530   msaitoh 	if (rv) {
   12449  1.392   msaitoh 		DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n",
   12450  1.392   msaitoh 			device_xname(sc->sc_dev)));
   12451  1.392   msaitoh 		flash_bank = 0;
   12452  1.392   msaitoh 	}
   12453  1.392   msaitoh 
   12454  1.392   msaitoh 	/*
   12455  1.392   msaitoh 	 * Adjust offset appropriately if we're on bank 1 - adjust for word
   12456  1.392   msaitoh 	 * size
   12457  1.392   msaitoh 	 */
   12458  1.392   msaitoh 	bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2);
   12459  1.392   msaitoh 
   12460  1.392   msaitoh 	for (i = 0; i < words; i++) {
   12461  1.392   msaitoh 		/* The NVM part needs a byte offset, hence * 2 */
   12462  1.392   msaitoh 		act_offset = bank_offset + ((offset + i) * 2);
   12463  1.392   msaitoh 		/* but we must read dword aligned, so mask ... */
   12464  1.530   msaitoh 		rv = wm_read_ich8_dword(sc, act_offset & ~0x3, &dword);
   12465  1.530   msaitoh 		if (rv) {
   12466  1.392   msaitoh 			aprint_error_dev(sc->sc_dev,
   12467  1.392   msaitoh 			    "%s: failed to read NVM\n", __func__);
   12468  1.392   msaitoh 			break;
   12469  1.392   msaitoh 		}
   12470  1.392   msaitoh 		/* ... and pick out low or high word */
   12471  1.392   msaitoh 		if ((act_offset & 0x2) == 0)
   12472  1.392   msaitoh 			data[i] = (uint16_t)(dword & 0xFFFF);
   12473  1.392   msaitoh 		else
   12474  1.392   msaitoh 			data[i] = (uint16_t)((dword >> 16) & 0xFFFF);
   12475  1.392   msaitoh 	}
   12476  1.392   msaitoh 
   12477  1.530   msaitoh 	sc->nvm.release(sc);
   12478  1.530   msaitoh 	return rv;
   12479  1.392   msaitoh }
   12480  1.392   msaitoh 
   12481  1.321   msaitoh /* iNVM */
   12482  1.321   msaitoh 
   12483  1.321   msaitoh static int
   12484  1.321   msaitoh wm_nvm_read_word_invm(struct wm_softc *sc, uint16_t address, uint16_t *data)
   12485  1.321   msaitoh {
   12486  1.321   msaitoh 	int32_t  rv = 0;
   12487  1.321   msaitoh 	uint32_t invm_dword;
   12488  1.321   msaitoh 	uint16_t i;
   12489  1.321   msaitoh 	uint8_t record_type, word_address;
   12490  1.321   msaitoh 
   12491  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12492  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12493  1.420   msaitoh 
   12494  1.321   msaitoh 	for (i = 0; i < INVM_SIZE; i++) {
   12495  1.329   msaitoh 		invm_dword = CSR_READ(sc, WM_INVM_DATA_REG(i));
   12496  1.321   msaitoh 		/* Get record type */
   12497  1.321   msaitoh 		record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
   12498  1.321   msaitoh 		if (record_type == INVM_UNINITIALIZED_STRUCTURE)
   12499  1.321   msaitoh 			break;
   12500  1.321   msaitoh 		if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE)
   12501  1.321   msaitoh 			i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
   12502  1.321   msaitoh 		if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE)
   12503  1.321   msaitoh 			i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
   12504  1.321   msaitoh 		if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) {
   12505  1.321   msaitoh 			word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
   12506  1.321   msaitoh 			if (word_address == address) {
   12507  1.321   msaitoh 				*data = INVM_DWORD_TO_WORD_DATA(invm_dword);
   12508  1.321   msaitoh 				rv = 0;
   12509  1.321   msaitoh 				break;
   12510  1.321   msaitoh 			}
   12511  1.321   msaitoh 		}
   12512  1.321   msaitoh 	}
   12513  1.321   msaitoh 
   12514  1.321   msaitoh 	return rv;
   12515  1.321   msaitoh }
   12516  1.321   msaitoh 
   12517  1.321   msaitoh static int
   12518  1.321   msaitoh wm_nvm_read_invm(struct wm_softc *sc, int offset, int words, uint16_t *data)
   12519  1.321   msaitoh {
   12520  1.321   msaitoh 	int rv = 0;
   12521  1.321   msaitoh 	int i;
   12522  1.421   msaitoh 
   12523  1.421   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12524  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   12525  1.321   msaitoh 
   12526  1.530   msaitoh 	if (sc->nvm.acquire(sc) != 0)
   12527  1.530   msaitoh 		return -1;
   12528  1.530   msaitoh 
   12529  1.321   msaitoh 	for (i = 0; i < words; i++) {
   12530  1.321   msaitoh 		switch (offset + i) {
   12531  1.321   msaitoh 		case NVM_OFF_MACADDR:
   12532  1.321   msaitoh 		case NVM_OFF_MACADDR1:
   12533  1.321   msaitoh 		case NVM_OFF_MACADDR2:
   12534  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset + i, &data[i]);
   12535  1.321   msaitoh 			if (rv != 0) {
   12536  1.321   msaitoh 				data[i] = 0xffff;
   12537  1.321   msaitoh 				rv = -1;
   12538  1.321   msaitoh 			}
   12539  1.321   msaitoh 			break;
   12540  1.321   msaitoh 		case NVM_OFF_CFG2:
   12541  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12542  1.321   msaitoh 			if (rv != 0) {
   12543  1.321   msaitoh 				*data = NVM_INIT_CTRL_2_DEFAULT_I211;
   12544  1.321   msaitoh 				rv = 0;
   12545  1.321   msaitoh 			}
   12546  1.321   msaitoh 			break;
   12547  1.321   msaitoh 		case NVM_OFF_CFG4:
   12548  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12549  1.321   msaitoh 			if (rv != 0) {
   12550  1.321   msaitoh 				*data = NVM_INIT_CTRL_4_DEFAULT_I211;
   12551  1.321   msaitoh 				rv = 0;
   12552  1.321   msaitoh 			}
   12553  1.321   msaitoh 			break;
   12554  1.321   msaitoh 		case NVM_OFF_LED_1_CFG:
   12555  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12556  1.321   msaitoh 			if (rv != 0) {
   12557  1.321   msaitoh 				*data = NVM_LED_1_CFG_DEFAULT_I211;
   12558  1.321   msaitoh 				rv = 0;
   12559  1.321   msaitoh 			}
   12560  1.321   msaitoh 			break;
   12561  1.321   msaitoh 		case NVM_OFF_LED_0_2_CFG:
   12562  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12563  1.321   msaitoh 			if (rv != 0) {
   12564  1.321   msaitoh 				*data = NVM_LED_0_2_CFG_DEFAULT_I211;
   12565  1.321   msaitoh 				rv = 0;
   12566  1.321   msaitoh 			}
   12567  1.321   msaitoh 			break;
   12568  1.321   msaitoh 		case NVM_OFF_ID_LED_SETTINGS:
   12569  1.321   msaitoh 			rv = wm_nvm_read_word_invm(sc, offset, data);
   12570  1.321   msaitoh 			if (rv != 0) {
   12571  1.321   msaitoh 				*data = ID_LED_RESERVED_FFFF;
   12572  1.321   msaitoh 				rv = 0;
   12573  1.321   msaitoh 			}
   12574  1.321   msaitoh 			break;
   12575  1.321   msaitoh 		default:
   12576  1.321   msaitoh 			DPRINTF(WM_DEBUG_NVM,
   12577  1.321   msaitoh 			    ("NVM word 0x%02x is not mapped.\n", offset));
   12578  1.321   msaitoh 			*data = NVM_RESERVED_WORD;
   12579  1.321   msaitoh 			break;
   12580  1.321   msaitoh 		}
   12581  1.321   msaitoh 	}
   12582  1.321   msaitoh 
   12583  1.530   msaitoh 	sc->nvm.release(sc);
   12584  1.321   msaitoh 	return rv;
   12585  1.321   msaitoh }
   12586  1.321   msaitoh 
   12587  1.328   msaitoh /* Lock, detecting NVM type, validate checksum, version and read */
   12588  1.281   msaitoh 
   12589  1.281   msaitoh static int
   12590  1.281   msaitoh wm_nvm_is_onboard_eeprom(struct wm_softc *sc)
   12591  1.139    bouyer {
   12592  1.281   msaitoh 	uint32_t eecd = 0;
   12593  1.281   msaitoh 
   12594  1.281   msaitoh 	if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574
   12595  1.281   msaitoh 	    || sc->sc_type == WM_T_82583) {
   12596  1.281   msaitoh 		eecd = CSR_READ(sc, WMREG_EECD);
   12597  1.281   msaitoh 
   12598  1.281   msaitoh 		/* Isolate bits 15 & 16 */
   12599  1.281   msaitoh 		eecd = ((eecd >> 15) & 0x03);
   12600  1.194   msaitoh 
   12601  1.281   msaitoh 		/* If both bits are set, device is Flash type */
   12602  1.281   msaitoh 		if (eecd == 0x03)
   12603  1.281   msaitoh 			return 0;
   12604  1.281   msaitoh 	}
   12605  1.281   msaitoh 	return 1;
   12606  1.281   msaitoh }
   12607  1.194   msaitoh 
   12608  1.321   msaitoh static int
   12609  1.565   msaitoh wm_nvm_flash_presence_i210(struct wm_softc *sc)
   12610  1.321   msaitoh {
   12611  1.321   msaitoh 	uint32_t eec;
   12612  1.321   msaitoh 
   12613  1.321   msaitoh 	eec = CSR_READ(sc, WMREG_EEC);
   12614  1.321   msaitoh 	if ((eec & EEC_FLASH_DETECTED) != 0)
   12615  1.321   msaitoh 		return 1;
   12616  1.321   msaitoh 
   12617  1.321   msaitoh 	return 0;
   12618  1.321   msaitoh }
   12619  1.321   msaitoh 
   12620  1.281   msaitoh /*
   12621  1.281   msaitoh  * wm_nvm_validate_checksum
   12622  1.281   msaitoh  *
   12623  1.281   msaitoh  * The checksum is defined as the sum of the first 64 (16 bit) words.
   12624  1.281   msaitoh  */
   12625  1.281   msaitoh static int
   12626  1.281   msaitoh wm_nvm_validate_checksum(struct wm_softc *sc)
   12627  1.281   msaitoh {
   12628  1.281   msaitoh 	uint16_t checksum;
   12629  1.281   msaitoh 	uint16_t eeprom_data;
   12630  1.281   msaitoh #ifdef WM_DEBUG
   12631  1.281   msaitoh 	uint16_t csum_wordaddr, valid_checksum;
   12632  1.281   msaitoh #endif
   12633  1.281   msaitoh 	int i;
   12634  1.194   msaitoh 
   12635  1.281   msaitoh 	checksum = 0;
   12636  1.139    bouyer 
   12637  1.281   msaitoh 	/* Don't check for I211 */
   12638  1.281   msaitoh 	if (sc->sc_type == WM_T_I211)
   12639  1.281   msaitoh 		return 0;
   12640  1.194   msaitoh 
   12641  1.281   msaitoh #ifdef WM_DEBUG
   12642  1.570   msaitoh 	if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)
   12643  1.570   msaitoh 	    || (sc->sc_type == WM_T_PCH_CNP)) {
   12644  1.293   msaitoh 		csum_wordaddr = NVM_OFF_COMPAT;
   12645  1.281   msaitoh 		valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
   12646  1.281   msaitoh 	} else {
   12647  1.293   msaitoh 		csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1;
   12648  1.281   msaitoh 		valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;
   12649  1.281   msaitoh 	}
   12650  1.194   msaitoh 
   12651  1.281   msaitoh 	/* Dump EEPROM image for debug */
   12652  1.281   msaitoh 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   12653  1.281   msaitoh 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   12654  1.281   msaitoh 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
   12655  1.392   msaitoh 		/* XXX PCH_SPT? */
   12656  1.281   msaitoh 		wm_nvm_read(sc, csum_wordaddr, 1, &eeprom_data);
   12657  1.281   msaitoh 		if ((eeprom_data & valid_checksum) == 0) {
   12658  1.281   msaitoh 			DPRINTF(WM_DEBUG_NVM,
   12659  1.281   msaitoh 			    ("%s: NVM need to be updated (%04x != %04x)\n",
   12660  1.281   msaitoh 				device_xname(sc->sc_dev), eeprom_data,
   12661  1.281   msaitoh 				    valid_checksum));
   12662  1.281   msaitoh 		}
   12663  1.281   msaitoh 	}
   12664  1.194   msaitoh 
   12665  1.281   msaitoh 	if ((wm_debug & WM_DEBUG_NVM) != 0) {
   12666  1.281   msaitoh 		printf("%s: NVM dump:\n", device_xname(sc->sc_dev));
   12667  1.293   msaitoh 		for (i = 0; i < NVM_SIZE; i++) {
   12668  1.281   msaitoh 			if (wm_nvm_read(sc, i, 1, &eeprom_data))
   12669  1.301   msaitoh 				printf("XXXX ");
   12670  1.281   msaitoh 			else
   12671  1.301   msaitoh 				printf("%04hx ", eeprom_data);
   12672  1.281   msaitoh 			if (i % 8 == 7)
   12673  1.281   msaitoh 				printf("\n");
   12674  1.194   msaitoh 		}
   12675  1.281   msaitoh 	}
   12676  1.194   msaitoh 
   12677  1.281   msaitoh #endif /* WM_DEBUG */
   12678  1.139    bouyer 
   12679  1.293   msaitoh 	for (i = 0; i < NVM_SIZE; i++) {
   12680  1.281   msaitoh 		if (wm_nvm_read(sc, i, 1, &eeprom_data))
   12681  1.281   msaitoh 			return 1;
   12682  1.281   msaitoh 		checksum += eeprom_data;
   12683  1.281   msaitoh 	}
   12684  1.139    bouyer 
   12685  1.281   msaitoh 	if (checksum != (uint16_t) NVM_CHECKSUM) {
   12686  1.281   msaitoh #ifdef WM_DEBUG
   12687  1.281   msaitoh 		printf("%s: NVM checksum mismatch (%04x != %04x)\n",
   12688  1.281   msaitoh 		    device_xname(sc->sc_dev), checksum, NVM_CHECKSUM);
   12689  1.281   msaitoh #endif
   12690  1.281   msaitoh 	}
   12691  1.139    bouyer 
   12692  1.281   msaitoh 	return 0;
   12693  1.139    bouyer }
   12694  1.139    bouyer 
   12695  1.328   msaitoh static void
   12696  1.347   msaitoh wm_nvm_version_invm(struct wm_softc *sc)
   12697  1.347   msaitoh {
   12698  1.347   msaitoh 	uint32_t dword;
   12699  1.347   msaitoh 
   12700  1.347   msaitoh 	/*
   12701  1.347   msaitoh 	 * Linux's code to decode version is very strange, so we don't
   12702  1.347   msaitoh 	 * obey that algorithm and just use word 61 as the document.
   12703  1.347   msaitoh 	 * Perhaps it's not perfect though...
   12704  1.347   msaitoh 	 *
   12705  1.347   msaitoh 	 * Example:
   12706  1.347   msaitoh 	 *
   12707  1.347   msaitoh 	 *   Word61: 00800030 -> Version 0.6 (I211 spec update notes about 0.6)
   12708  1.347   msaitoh 	 */
   12709  1.347   msaitoh 	dword = CSR_READ(sc, WM_INVM_DATA_REG(61));
   12710  1.347   msaitoh 	dword = __SHIFTOUT(dword, INVM_VER_1);
   12711  1.347   msaitoh 	sc->sc_nvm_ver_major = __SHIFTOUT(dword, INVM_MAJOR);
   12712  1.347   msaitoh 	sc->sc_nvm_ver_minor = __SHIFTOUT(dword, INVM_MINOR);
   12713  1.347   msaitoh }
   12714  1.347   msaitoh 
   12715  1.347   msaitoh static void
   12716  1.328   msaitoh wm_nvm_version(struct wm_softc *sc)
   12717  1.328   msaitoh {
   12718  1.331   msaitoh 	uint16_t major, minor, build, patch;
   12719  1.328   msaitoh 	uint16_t uid0, uid1;
   12720  1.328   msaitoh 	uint16_t nvm_data;
   12721  1.328   msaitoh 	uint16_t off;
   12722  1.330   msaitoh 	bool check_version = false;
   12723  1.330   msaitoh 	bool check_optionrom = false;
   12724  1.334   msaitoh 	bool have_build = false;
   12725  1.512   msaitoh 	bool have_uid = true;
   12726  1.328   msaitoh 
   12727  1.334   msaitoh 	/*
   12728  1.334   msaitoh 	 * Version format:
   12729  1.334   msaitoh 	 *
   12730  1.334   msaitoh 	 * XYYZ
   12731  1.334   msaitoh 	 * X0YZ
   12732  1.334   msaitoh 	 * X0YY
   12733  1.334   msaitoh 	 *
   12734  1.334   msaitoh 	 * Example:
   12735  1.334   msaitoh 	 *
   12736  1.334   msaitoh 	 *	82571	0x50a2	5.10.2?	(the spec update notes about 5.6-5.10)
   12737  1.334   msaitoh 	 *	82571	0x50a6	5.10.6?
   12738  1.334   msaitoh 	 *	82572	0x506a	5.6.10?
   12739  1.334   msaitoh 	 *	82572EI	0x5069	5.6.9?
   12740  1.334   msaitoh 	 *	82574L	0x1080	1.8.0?	(the spec update notes about 2.1.4)
   12741  1.334   msaitoh 	 *		0x2013	2.1.3?
   12742  1.334   msaitoh 	 *	82583	0x10a0	1.10.0? (document says it's default vaule)
   12743  1.334   msaitoh 	 */
   12744  1.534   msaitoh 
   12745  1.534   msaitoh 	/*
   12746  1.534   msaitoh 	 * XXX
   12747  1.534   msaitoh 	 * Qemu's e1000e emulation (82574L)'s SPI has only 64 words.
   12748  1.534   msaitoh 	 * I've never seen on real 82574 hardware with such small SPI ROM.
   12749  1.534   msaitoh 	 */
   12750  1.535   msaitoh 	if ((sc->sc_nvm_wordsize < NVM_OFF_IMAGE_UID1)
   12751  1.535   msaitoh 	    || (wm_nvm_read(sc, NVM_OFF_IMAGE_UID1, 1, &uid1) != 0))
   12752  1.534   msaitoh 		have_uid = false;
   12753  1.534   msaitoh 
   12754  1.328   msaitoh 	switch (sc->sc_type) {
   12755  1.334   msaitoh 	case WM_T_82571:
   12756  1.334   msaitoh 	case WM_T_82572:
   12757  1.334   msaitoh 	case WM_T_82574:
   12758  1.350   msaitoh 	case WM_T_82583:
   12759  1.334   msaitoh 		check_version = true;
   12760  1.334   msaitoh 		check_optionrom = true;
   12761  1.334   msaitoh 		have_build = true;
   12762  1.334   msaitoh 		break;
   12763  1.328   msaitoh 	case WM_T_82575:
   12764  1.328   msaitoh 	case WM_T_82576:
   12765  1.328   msaitoh 	case WM_T_82580:
   12766  1.558  christos 		if (have_uid && (uid1 & NVM_MAJOR_MASK) != NVM_UID_VALID)
   12767  1.330   msaitoh 			check_version = true;
   12768  1.328   msaitoh 		break;
   12769  1.328   msaitoh 	case WM_T_I211:
   12770  1.347   msaitoh 		wm_nvm_version_invm(sc);
   12771  1.512   msaitoh 		have_uid = false;
   12772  1.347   msaitoh 		goto printver;
   12773  1.328   msaitoh 	case WM_T_I210:
   12774  1.565   msaitoh 		if (!wm_nvm_flash_presence_i210(sc)) {
   12775  1.347   msaitoh 			wm_nvm_version_invm(sc);
   12776  1.512   msaitoh 			have_uid = false;
   12777  1.347   msaitoh 			goto printver;
   12778  1.328   msaitoh 		}
   12779  1.328   msaitoh 		/* FALLTHROUGH */
   12780  1.328   msaitoh 	case WM_T_I350:
   12781  1.328   msaitoh 	case WM_T_I354:
   12782  1.330   msaitoh 		check_version = true;
   12783  1.330   msaitoh 		check_optionrom = true;
   12784  1.330   msaitoh 		break;
   12785  1.330   msaitoh 	default:
   12786  1.330   msaitoh 		return;
   12787  1.330   msaitoh 	}
   12788  1.535   msaitoh 	if (check_version
   12789  1.535   msaitoh 	    && (wm_nvm_read(sc, NVM_OFF_VERSION, 1, &nvm_data) == 0)) {
   12790  1.330   msaitoh 		major = (nvm_data & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
   12791  1.334   msaitoh 		if (have_build || ((nvm_data & 0x0f00) != 0x0000)) {
   12792  1.330   msaitoh 			minor = (nvm_data & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
   12793  1.330   msaitoh 			build = nvm_data & NVM_BUILD_MASK;
   12794  1.331   msaitoh 			have_build = true;
   12795  1.334   msaitoh 		} else
   12796  1.334   msaitoh 			minor = nvm_data & 0x00ff;
   12797  1.334   msaitoh 
   12798  1.330   msaitoh 		/* Decimal */
   12799  1.330   msaitoh 		minor = (minor / 16) * 10 + (minor % 16);
   12800  1.347   msaitoh 		sc->sc_nvm_ver_major = major;
   12801  1.347   msaitoh 		sc->sc_nvm_ver_minor = minor;
   12802  1.330   msaitoh 
   12803  1.347   msaitoh printver:
   12804  1.347   msaitoh 		aprint_verbose(", version %d.%d", sc->sc_nvm_ver_major,
   12805  1.347   msaitoh 		    sc->sc_nvm_ver_minor);
   12806  1.350   msaitoh 		if (have_build) {
   12807  1.350   msaitoh 			sc->sc_nvm_ver_build = build;
   12808  1.334   msaitoh 			aprint_verbose(".%d", build);
   12809  1.350   msaitoh 		}
   12810  1.330   msaitoh 	}
   12811  1.534   msaitoh 
   12812  1.534   msaitoh 	/* Assume the Option ROM area is at avove NVM_SIZE */
   12813  1.539   msaitoh 	if ((sc->sc_nvm_wordsize > NVM_SIZE) && check_optionrom
   12814  1.535   msaitoh 	    && (wm_nvm_read(sc, NVM_OFF_COMB_VER_PTR, 1, &off) == 0)) {
   12815  1.328   msaitoh 		/* Option ROM Version */
   12816  1.328   msaitoh 		if ((off != 0x0000) && (off != 0xffff)) {
   12817  1.535   msaitoh 			int rv;
   12818  1.535   msaitoh 
   12819  1.328   msaitoh 			off += NVM_COMBO_VER_OFF;
   12820  1.535   msaitoh 			rv = wm_nvm_read(sc, off + 1, 1, &uid1);
   12821  1.535   msaitoh 			rv |= wm_nvm_read(sc, off, 1, &uid0);
   12822  1.535   msaitoh 			if ((rv == 0) && (uid0 != 0) && (uid0 != 0xffff)
   12823  1.328   msaitoh 			    && (uid1 != 0) && (uid1 != 0xffff)) {
   12824  1.331   msaitoh 				/* 16bits */
   12825  1.331   msaitoh 				major = uid0 >> 8;
   12826  1.331   msaitoh 				build = (uid0 << 8) | (uid1 >> 8);
   12827  1.331   msaitoh 				patch = uid1 & 0x00ff;
   12828  1.330   msaitoh 				aprint_verbose(", option ROM Version %d.%d.%d",
   12829  1.331   msaitoh 				    major, build, patch);
   12830  1.328   msaitoh 			}
   12831  1.328   msaitoh 		}
   12832  1.328   msaitoh 	}
   12833  1.328   msaitoh 
   12834  1.535   msaitoh 	if (have_uid && (wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0) == 0))
   12835  1.512   msaitoh 		aprint_verbose(", Image Unique ID %08x", (uid1 << 16) | uid0);
   12836  1.328   msaitoh }
   12837  1.328   msaitoh 
   12838  1.281   msaitoh /*
   12839  1.281   msaitoh  * wm_nvm_read:
   12840  1.139    bouyer  *
   12841  1.281   msaitoh  *	Read data from the serial EEPROM.
   12842  1.281   msaitoh  */
   12843  1.169   msaitoh static int
   12844  1.281   msaitoh wm_nvm_read(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   12845  1.169   msaitoh {
   12846  1.169   msaitoh 	int rv;
   12847  1.169   msaitoh 
   12848  1.420   msaitoh 	DPRINTF(WM_DEBUG_NVM, ("%s: %s called\n",
   12849  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   12850  1.420   msaitoh 
   12851  1.281   msaitoh 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   12852  1.530   msaitoh 		return -1;
   12853  1.281   msaitoh 
   12854  1.530   msaitoh 	rv = sc->nvm.read(sc, word, wordcnt, data);
   12855  1.530   msaitoh 
   12856  1.169   msaitoh 	return rv;
   12857  1.169   msaitoh }
   12858  1.169   msaitoh 
   12859  1.281   msaitoh /*
   12860  1.281   msaitoh  * Hardware semaphores.
   12861  1.281   msaitoh  * Very complexed...
   12862  1.281   msaitoh  */
   12863  1.281   msaitoh 
   12864  1.169   msaitoh static int
   12865  1.424   msaitoh wm_get_null(struct wm_softc *sc)
   12866  1.424   msaitoh {
   12867  1.424   msaitoh 
   12868  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12869  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12870  1.424   msaitoh 	return 0;
   12871  1.424   msaitoh }
   12872  1.424   msaitoh 
   12873  1.424   msaitoh static void
   12874  1.424   msaitoh wm_put_null(struct wm_softc *sc)
   12875  1.424   msaitoh {
   12876  1.424   msaitoh 
   12877  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12878  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   12879  1.424   msaitoh 	return;
   12880  1.424   msaitoh }
   12881  1.424   msaitoh 
   12882  1.530   msaitoh static int
   12883  1.530   msaitoh wm_get_eecd(struct wm_softc *sc)
   12884  1.530   msaitoh {
   12885  1.530   msaitoh 	uint32_t reg;
   12886  1.530   msaitoh 	int x;
   12887  1.530   msaitoh 
   12888  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK | WM_DEBUG_NVM, ("%s: %s called\n",
   12889  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   12890  1.530   msaitoh 
   12891  1.530   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   12892  1.530   msaitoh 
   12893  1.530   msaitoh 	/* Request EEPROM access. */
   12894  1.530   msaitoh 	reg |= EECD_EE_REQ;
   12895  1.530   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   12896  1.530   msaitoh 
   12897  1.530   msaitoh 	/* ..and wait for it to be granted. */
   12898  1.530   msaitoh 	for (x = 0; x < 1000; x++) {
   12899  1.530   msaitoh 		reg = CSR_READ(sc, WMREG_EECD);
   12900  1.530   msaitoh 		if (reg & EECD_EE_GNT)
   12901  1.530   msaitoh 			break;
   12902  1.530   msaitoh 		delay(5);
   12903  1.530   msaitoh 	}
   12904  1.530   msaitoh 	if ((reg & EECD_EE_GNT) == 0) {
   12905  1.530   msaitoh 		aprint_error_dev(sc->sc_dev,
   12906  1.530   msaitoh 		    "could not acquire EEPROM GNT\n");
   12907  1.530   msaitoh 		reg &= ~EECD_EE_REQ;
   12908  1.530   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   12909  1.530   msaitoh 		return -1;
   12910  1.530   msaitoh 	}
   12911  1.530   msaitoh 
   12912  1.530   msaitoh 	return 0;
   12913  1.530   msaitoh }
   12914  1.530   msaitoh 
   12915  1.530   msaitoh static void
   12916  1.530   msaitoh wm_nvm_eec_clock_raise(struct wm_softc *sc, uint32_t *eecd)
   12917  1.530   msaitoh {
   12918  1.530   msaitoh 
   12919  1.530   msaitoh 	*eecd |= EECD_SK;
   12920  1.530   msaitoh 	CSR_WRITE(sc, WMREG_EECD, *eecd);
   12921  1.530   msaitoh 	CSR_WRITE_FLUSH(sc);
   12922  1.530   msaitoh 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0)
   12923  1.530   msaitoh 		delay(1);
   12924  1.530   msaitoh 	else
   12925  1.530   msaitoh 		delay(50);
   12926  1.530   msaitoh }
   12927  1.530   msaitoh 
   12928  1.530   msaitoh static void
   12929  1.530   msaitoh wm_nvm_eec_clock_lower(struct wm_softc *sc, uint32_t *eecd)
   12930  1.530   msaitoh {
   12931  1.530   msaitoh 
   12932  1.530   msaitoh 	*eecd &= ~EECD_SK;
   12933  1.530   msaitoh 	CSR_WRITE(sc, WMREG_EECD, *eecd);
   12934  1.530   msaitoh 	CSR_WRITE_FLUSH(sc);
   12935  1.530   msaitoh 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0)
   12936  1.530   msaitoh 		delay(1);
   12937  1.530   msaitoh 	else
   12938  1.530   msaitoh 		delay(50);
   12939  1.530   msaitoh }
   12940  1.530   msaitoh 
   12941  1.530   msaitoh static void
   12942  1.530   msaitoh wm_put_eecd(struct wm_softc *sc)
   12943  1.530   msaitoh {
   12944  1.530   msaitoh 	uint32_t reg;
   12945  1.530   msaitoh 
   12946  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12947  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   12948  1.530   msaitoh 
   12949  1.530   msaitoh 	/* Stop nvm */
   12950  1.530   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   12951  1.530   msaitoh 	if ((sc->sc_flags & WM_F_EEPROM_SPI) != 0) {
   12952  1.530   msaitoh 		/* Pull CS high */
   12953  1.530   msaitoh 		reg |= EECD_CS;
   12954  1.530   msaitoh 		wm_nvm_eec_clock_lower(sc, &reg);
   12955  1.530   msaitoh 	} else {
   12956  1.530   msaitoh 		/* CS on Microwire is active-high */
   12957  1.530   msaitoh 		reg &= ~(EECD_CS | EECD_DI);
   12958  1.530   msaitoh 		CSR_WRITE(sc, WMREG_EECD, reg);
   12959  1.530   msaitoh 		wm_nvm_eec_clock_raise(sc, &reg);
   12960  1.530   msaitoh 		wm_nvm_eec_clock_lower(sc, &reg);
   12961  1.530   msaitoh 	}
   12962  1.530   msaitoh 
   12963  1.530   msaitoh 	reg = CSR_READ(sc, WMREG_EECD);
   12964  1.530   msaitoh 	reg &= ~EECD_EE_REQ;
   12965  1.530   msaitoh 	CSR_WRITE(sc, WMREG_EECD, reg);
   12966  1.530   msaitoh 
   12967  1.530   msaitoh 	return;
   12968  1.530   msaitoh }
   12969  1.530   msaitoh 
   12970  1.424   msaitoh /*
   12971  1.424   msaitoh  * Get hardware semaphore.
   12972  1.424   msaitoh  * Same as e1000_get_hw_semaphore_generic()
   12973  1.424   msaitoh  */
   12974  1.424   msaitoh static int
   12975  1.281   msaitoh wm_get_swsm_semaphore(struct wm_softc *sc)
   12976  1.169   msaitoh {
   12977  1.281   msaitoh 	int32_t timeout;
   12978  1.281   msaitoh 	uint32_t swsm;
   12979  1.281   msaitoh 
   12980  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   12981  1.421   msaitoh 		device_xname(sc->sc_dev), __func__));
   12982  1.424   msaitoh 	KASSERT(sc->sc_nvm_wordsize > 0);
   12983  1.421   msaitoh 
   12984  1.533   msaitoh retry:
   12985  1.424   msaitoh 	/* Get the SW semaphore. */
   12986  1.424   msaitoh 	timeout = sc->sc_nvm_wordsize + 1;
   12987  1.424   msaitoh 	while (timeout) {
   12988  1.424   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   12989  1.281   msaitoh 
   12990  1.424   msaitoh 		if ((swsm & SWSM_SMBI) == 0)
   12991  1.424   msaitoh 			break;
   12992  1.169   msaitoh 
   12993  1.424   msaitoh 		delay(50);
   12994  1.424   msaitoh 		timeout--;
   12995  1.424   msaitoh 	}
   12996  1.169   msaitoh 
   12997  1.424   msaitoh 	if (timeout == 0) {
   12998  1.533   msaitoh 		if ((sc->sc_flags & WM_F_WA_I210_CLSEM) != 0) {
   12999  1.533   msaitoh 			/*
   13000  1.533   msaitoh 			 * In rare circumstances, the SW semaphore may already
   13001  1.533   msaitoh 			 * be held unintentionally. Clear the semaphore once
   13002  1.533   msaitoh 			 * before giving up.
   13003  1.533   msaitoh 			 */
   13004  1.533   msaitoh 			sc->sc_flags &= ~WM_F_WA_I210_CLSEM;
   13005  1.533   msaitoh 			wm_put_swsm_semaphore(sc);
   13006  1.533   msaitoh 			goto retry;
   13007  1.533   msaitoh 		}
   13008  1.424   msaitoh 		aprint_error_dev(sc->sc_dev,
   13009  1.424   msaitoh 		    "could not acquire SWSM SMBI\n");
   13010  1.424   msaitoh 		return 1;
   13011  1.281   msaitoh 	}
   13012  1.281   msaitoh 
   13013  1.281   msaitoh 	/* Get the FW semaphore. */
   13014  1.294   msaitoh 	timeout = sc->sc_nvm_wordsize + 1;
   13015  1.281   msaitoh 	while (timeout) {
   13016  1.281   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   13017  1.281   msaitoh 		swsm |= SWSM_SWESMBI;
   13018  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, swsm);
   13019  1.281   msaitoh 		/* If we managed to set the bit we got the semaphore. */
   13020  1.281   msaitoh 		swsm = CSR_READ(sc, WMREG_SWSM);
   13021  1.281   msaitoh 		if (swsm & SWSM_SWESMBI)
   13022  1.281   msaitoh 			break;
   13023  1.169   msaitoh 
   13024  1.281   msaitoh 		delay(50);
   13025  1.281   msaitoh 		timeout--;
   13026  1.281   msaitoh 	}
   13027  1.281   msaitoh 
   13028  1.281   msaitoh 	if (timeout == 0) {
   13029  1.388   msaitoh 		aprint_error_dev(sc->sc_dev,
   13030  1.388   msaitoh 		    "could not acquire SWSM SWESMBI\n");
   13031  1.281   msaitoh 		/* Release semaphores */
   13032  1.281   msaitoh 		wm_put_swsm_semaphore(sc);
   13033  1.281   msaitoh 		return 1;
   13034  1.281   msaitoh 	}
   13035  1.169   msaitoh 	return 0;
   13036  1.169   msaitoh }
   13037  1.169   msaitoh 
   13038  1.420   msaitoh /*
   13039  1.420   msaitoh  * Put hardware semaphore.
   13040  1.420   msaitoh  * Same as e1000_put_hw_semaphore_generic()
   13041  1.420   msaitoh  */
   13042  1.281   msaitoh static void
   13043  1.281   msaitoh wm_put_swsm_semaphore(struct wm_softc *sc)
   13044  1.169   msaitoh {
   13045  1.281   msaitoh 	uint32_t swsm;
   13046  1.169   msaitoh 
   13047  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13048  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13049  1.420   msaitoh 
   13050  1.281   msaitoh 	swsm = CSR_READ(sc, WMREG_SWSM);
   13051  1.281   msaitoh 	swsm &= ~(SWSM_SMBI | SWSM_SWESMBI);
   13052  1.281   msaitoh 	CSR_WRITE(sc, WMREG_SWSM, swsm);
   13053  1.169   msaitoh }
   13054  1.169   msaitoh 
   13055  1.420   msaitoh /*
   13056  1.420   msaitoh  * Get SW/FW semaphore.
   13057  1.530   msaitoh  * Same as e1000_acquire_swfw_sync_{80003es2lan,82575}().
   13058  1.420   msaitoh  */
   13059  1.169   msaitoh static int
   13060  1.281   msaitoh wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
   13061  1.169   msaitoh {
   13062  1.281   msaitoh 	uint32_t swfw_sync;
   13063  1.281   msaitoh 	uint32_t swmask = mask << SWFW_SOFT_SHIFT;
   13064  1.281   msaitoh 	uint32_t fwmask = mask << SWFW_FIRM_SHIFT;
   13065  1.530   msaitoh 	int timeout;
   13066  1.169   msaitoh 
   13067  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13068  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13069  1.530   msaitoh 
   13070  1.530   msaitoh 	if (sc->sc_type == WM_T_80003)
   13071  1.530   msaitoh 		timeout = 50;
   13072  1.530   msaitoh 	else
   13073  1.530   msaitoh 		timeout = 200;
   13074  1.420   msaitoh 
   13075  1.575   msaitoh 	while (timeout) {
   13076  1.530   msaitoh 		if (wm_get_swsm_semaphore(sc)) {
   13077  1.530   msaitoh 			aprint_error_dev(sc->sc_dev,
   13078  1.530   msaitoh 			    "%s: failed to get semaphore\n",
   13079  1.530   msaitoh 			    __func__);
   13080  1.530   msaitoh 			return 1;
   13081  1.281   msaitoh 		}
   13082  1.281   msaitoh 		swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
   13083  1.281   msaitoh 		if ((swfw_sync & (swmask | fwmask)) == 0) {
   13084  1.281   msaitoh 			swfw_sync |= swmask;
   13085  1.281   msaitoh 			CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
   13086  1.530   msaitoh 			wm_put_swsm_semaphore(sc);
   13087  1.281   msaitoh 			return 0;
   13088  1.281   msaitoh 		}
   13089  1.530   msaitoh 		wm_put_swsm_semaphore(sc);
   13090  1.281   msaitoh 		delay(5000);
   13091  1.575   msaitoh 		timeout--;
   13092  1.281   msaitoh 	}
   13093  1.281   msaitoh 	printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n",
   13094  1.281   msaitoh 	    device_xname(sc->sc_dev), mask, swfw_sync);
   13095  1.281   msaitoh 	return 1;
   13096  1.281   msaitoh }
   13097  1.169   msaitoh 
   13098  1.281   msaitoh static void
   13099  1.281   msaitoh wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask)
   13100  1.281   msaitoh {
   13101  1.281   msaitoh 	uint32_t swfw_sync;
   13102  1.169   msaitoh 
   13103  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13104  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13105  1.420   msaitoh 
   13106  1.530   msaitoh 	while (wm_get_swsm_semaphore(sc) != 0)
   13107  1.530   msaitoh 		continue;
   13108  1.530   msaitoh 
   13109  1.281   msaitoh 	swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
   13110  1.281   msaitoh 	swfw_sync &= ~(mask << SWFW_SOFT_SHIFT);
   13111  1.281   msaitoh 	CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync);
   13112  1.530   msaitoh 
   13113  1.530   msaitoh 	wm_put_swsm_semaphore(sc);
   13114  1.530   msaitoh }
   13115  1.530   msaitoh 
   13116  1.530   msaitoh static int
   13117  1.530   msaitoh wm_get_nvm_80003(struct wm_softc *sc)
   13118  1.530   msaitoh {
   13119  1.530   msaitoh 	int rv;
   13120  1.530   msaitoh 
   13121  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK | WM_DEBUG_NVM, ("%s: %s called\n",
   13122  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   13123  1.530   msaitoh 
   13124  1.530   msaitoh 	if ((rv = wm_get_swfw_semaphore(sc, SWFW_EEP_SM)) != 0) {
   13125  1.530   msaitoh 		aprint_error_dev(sc->sc_dev,
   13126  1.530   msaitoh 		    "%s: failed to get semaphore(SWFW)\n",
   13127  1.530   msaitoh 		    __func__);
   13128  1.530   msaitoh 		return rv;
   13129  1.530   msaitoh 	}
   13130  1.530   msaitoh 
   13131  1.530   msaitoh 	if (((sc->sc_flags & WM_F_LOCK_EECD) != 0)
   13132  1.530   msaitoh 	    && (rv = wm_get_eecd(sc)) != 0) {
   13133  1.530   msaitoh 		aprint_error_dev(sc->sc_dev,
   13134  1.530   msaitoh 		    "%s: failed to get semaphore(EECD)\n",
   13135  1.530   msaitoh 		    __func__);
   13136  1.530   msaitoh 		wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
   13137  1.530   msaitoh 		return rv;
   13138  1.530   msaitoh 	}
   13139  1.530   msaitoh 
   13140  1.530   msaitoh 	return 0;
   13141  1.530   msaitoh }
   13142  1.530   msaitoh 
   13143  1.530   msaitoh static void
   13144  1.530   msaitoh wm_put_nvm_80003(struct wm_softc *sc)
   13145  1.530   msaitoh {
   13146  1.530   msaitoh 
   13147  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13148  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   13149  1.530   msaitoh 
   13150  1.530   msaitoh 	if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
   13151  1.530   msaitoh 		wm_put_eecd(sc);
   13152  1.530   msaitoh 	wm_put_swfw_semaphore(sc, SWFW_EEP_SM);
   13153  1.530   msaitoh }
   13154  1.530   msaitoh 
   13155  1.530   msaitoh static int
   13156  1.530   msaitoh wm_get_nvm_82571(struct wm_softc *sc)
   13157  1.530   msaitoh {
   13158  1.530   msaitoh 	int rv;
   13159  1.530   msaitoh 
   13160  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13161  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   13162  1.530   msaitoh 
   13163  1.530   msaitoh 	if ((rv = wm_get_swsm_semaphore(sc)) != 0)
   13164  1.530   msaitoh 		return rv;
   13165  1.530   msaitoh 
   13166  1.530   msaitoh 	switch (sc->sc_type) {
   13167  1.530   msaitoh 	case WM_T_82573:
   13168  1.530   msaitoh 		break;
   13169  1.530   msaitoh 	default:
   13170  1.530   msaitoh 		if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
   13171  1.530   msaitoh 			rv = wm_get_eecd(sc);
   13172  1.530   msaitoh 		break;
   13173  1.530   msaitoh 	}
   13174  1.530   msaitoh 
   13175  1.530   msaitoh 	if (rv != 0) {
   13176  1.530   msaitoh 		aprint_error_dev(sc->sc_dev,
   13177  1.530   msaitoh 		    "%s: failed to get semaphore\n",
   13178  1.530   msaitoh 		    __func__);
   13179  1.281   msaitoh 		wm_put_swsm_semaphore(sc);
   13180  1.530   msaitoh 	}
   13181  1.530   msaitoh 
   13182  1.530   msaitoh 	return rv;
   13183  1.530   msaitoh }
   13184  1.530   msaitoh 
   13185  1.530   msaitoh static void
   13186  1.530   msaitoh wm_put_nvm_82571(struct wm_softc *sc)
   13187  1.530   msaitoh {
   13188  1.530   msaitoh 
   13189  1.530   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13190  1.530   msaitoh 		device_xname(sc->sc_dev), __func__));
   13191  1.530   msaitoh 
   13192  1.530   msaitoh 	switch (sc->sc_type) {
   13193  1.530   msaitoh 	case WM_T_82573:
   13194  1.530   msaitoh 		break;
   13195  1.530   msaitoh 	default:
   13196  1.530   msaitoh 		if ((sc->sc_flags & WM_F_LOCK_EECD) != 0)
   13197  1.530   msaitoh 			wm_put_eecd(sc);
   13198  1.530   msaitoh 		break;
   13199  1.530   msaitoh 	}
   13200  1.530   msaitoh 
   13201  1.530   msaitoh 	wm_put_swsm_semaphore(sc);
   13202  1.169   msaitoh }
   13203  1.169   msaitoh 
   13204  1.189   msaitoh static int
   13205  1.424   msaitoh wm_get_phy_82575(struct wm_softc *sc)
   13206  1.424   msaitoh {
   13207  1.424   msaitoh 
   13208  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13209  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   13210  1.424   msaitoh 	return wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
   13211  1.424   msaitoh }
   13212  1.424   msaitoh 
   13213  1.424   msaitoh static void
   13214  1.424   msaitoh wm_put_phy_82575(struct wm_softc *sc)
   13215  1.424   msaitoh {
   13216  1.424   msaitoh 
   13217  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13218  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   13219  1.424   msaitoh 	return wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
   13220  1.424   msaitoh }
   13221  1.424   msaitoh 
   13222  1.424   msaitoh static int
   13223  1.281   msaitoh wm_get_swfwhw_semaphore(struct wm_softc *sc)
   13224  1.203   msaitoh {
   13225  1.281   msaitoh 	uint32_t ext_ctrl;
   13226  1.281   msaitoh 	int timeout = 200;
   13227  1.203   msaitoh 
   13228  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13229  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13230  1.420   msaitoh 
   13231  1.424   msaitoh 	mutex_enter(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   13232  1.281   msaitoh 	for (timeout = 0; timeout < 200; timeout++) {
   13233  1.281   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13234  1.329   msaitoh 		ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13235  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13236  1.203   msaitoh 
   13237  1.281   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13238  1.329   msaitoh 		if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
   13239  1.281   msaitoh 			return 0;
   13240  1.281   msaitoh 		delay(5000);
   13241  1.281   msaitoh 	}
   13242  1.281   msaitoh 	printf("%s: failed to get swfwhw semaphore ext_ctrl 0x%x\n",
   13243  1.281   msaitoh 	    device_xname(sc->sc_dev), ext_ctrl);
   13244  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   13245  1.281   msaitoh 	return 1;
   13246  1.281   msaitoh }
   13247  1.203   msaitoh 
   13248  1.281   msaitoh static void
   13249  1.281   msaitoh wm_put_swfwhw_semaphore(struct wm_softc *sc)
   13250  1.281   msaitoh {
   13251  1.281   msaitoh 	uint32_t ext_ctrl;
   13252  1.388   msaitoh 
   13253  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13254  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13255  1.420   msaitoh 
   13256  1.281   msaitoh 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13257  1.329   msaitoh 	ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13258  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13259  1.424   msaitoh 
   13260  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx); /* Use PHY mtx for both PHY and NVM */
   13261  1.424   msaitoh }
   13262  1.424   msaitoh 
   13263  1.424   msaitoh static int
   13264  1.424   msaitoh wm_get_swflag_ich8lan(struct wm_softc *sc)
   13265  1.424   msaitoh {
   13266  1.424   msaitoh 	uint32_t ext_ctrl;
   13267  1.424   msaitoh 	int timeout;
   13268  1.424   msaitoh 
   13269  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13270  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   13271  1.424   msaitoh 	mutex_enter(sc->sc_ich_phymtx);
   13272  1.424   msaitoh 	for (timeout = 0; timeout < WM_PHY_CFG_TIMEOUT; timeout++) {
   13273  1.424   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13274  1.424   msaitoh 		if ((ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) == 0)
   13275  1.424   msaitoh 			break;
   13276  1.424   msaitoh 		delay(1000);
   13277  1.424   msaitoh 	}
   13278  1.424   msaitoh 	if (timeout >= WM_PHY_CFG_TIMEOUT) {
   13279  1.424   msaitoh 		printf("%s: SW has already locked the resource\n",
   13280  1.424   msaitoh 		    device_xname(sc->sc_dev));
   13281  1.424   msaitoh 		goto out;
   13282  1.424   msaitoh 	}
   13283  1.424   msaitoh 
   13284  1.424   msaitoh 	ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13285  1.424   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13286  1.424   msaitoh 	for (timeout = 0; timeout < 1000; timeout++) {
   13287  1.424   msaitoh 		ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13288  1.424   msaitoh 		if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP)
   13289  1.424   msaitoh 			break;
   13290  1.424   msaitoh 		delay(1000);
   13291  1.424   msaitoh 	}
   13292  1.424   msaitoh 	if (timeout >= 1000) {
   13293  1.424   msaitoh 		printf("%s: failed to acquire semaphore\n",
   13294  1.424   msaitoh 		    device_xname(sc->sc_dev));
   13295  1.424   msaitoh 		ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13296  1.424   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13297  1.424   msaitoh 		goto out;
   13298  1.424   msaitoh 	}
   13299  1.424   msaitoh 	return 0;
   13300  1.424   msaitoh 
   13301  1.424   msaitoh out:
   13302  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx);
   13303  1.424   msaitoh 	return 1;
   13304  1.424   msaitoh }
   13305  1.424   msaitoh 
   13306  1.424   msaitoh static void
   13307  1.424   msaitoh wm_put_swflag_ich8lan(struct wm_softc *sc)
   13308  1.424   msaitoh {
   13309  1.424   msaitoh 	uint32_t ext_ctrl;
   13310  1.424   msaitoh 
   13311  1.424   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13312  1.424   msaitoh 		device_xname(sc->sc_dev), __func__));
   13313  1.424   msaitoh 	ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
   13314  1.424   msaitoh 	if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) {
   13315  1.424   msaitoh 		ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13316  1.424   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl);
   13317  1.424   msaitoh 	} else {
   13318  1.424   msaitoh 		printf("%s: Semaphore unexpectedly released\n",
   13319  1.424   msaitoh 		    device_xname(sc->sc_dev));
   13320  1.424   msaitoh 	}
   13321  1.424   msaitoh 
   13322  1.424   msaitoh 	mutex_exit(sc->sc_ich_phymtx);
   13323  1.203   msaitoh }
   13324  1.203   msaitoh 
   13325  1.203   msaitoh static int
   13326  1.423   msaitoh wm_get_nvm_ich8lan(struct wm_softc *sc)
   13327  1.423   msaitoh {
   13328  1.423   msaitoh 
   13329  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13330  1.423   msaitoh 		device_xname(sc->sc_dev), __func__));
   13331  1.423   msaitoh 	mutex_enter(sc->sc_ich_nvmmtx);
   13332  1.423   msaitoh 
   13333  1.423   msaitoh 	return 0;
   13334  1.423   msaitoh }
   13335  1.423   msaitoh 
   13336  1.423   msaitoh static void
   13337  1.423   msaitoh wm_put_nvm_ich8lan(struct wm_softc *sc)
   13338  1.423   msaitoh {
   13339  1.423   msaitoh 
   13340  1.434   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13341  1.423   msaitoh 		device_xname(sc->sc_dev), __func__));
   13342  1.423   msaitoh 	mutex_exit(sc->sc_ich_nvmmtx);
   13343  1.423   msaitoh }
   13344  1.423   msaitoh 
   13345  1.423   msaitoh static int
   13346  1.281   msaitoh wm_get_hw_semaphore_82573(struct wm_softc *sc)
   13347  1.189   msaitoh {
   13348  1.281   msaitoh 	int i = 0;
   13349  1.189   msaitoh 	uint32_t reg;
   13350  1.189   msaitoh 
   13351  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13352  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13353  1.420   msaitoh 
   13354  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   13355  1.281   msaitoh 	do {
   13356  1.281   msaitoh 		CSR_WRITE(sc, WMREG_EXTCNFCTR,
   13357  1.281   msaitoh 		    reg | EXTCNFCTR_MDIO_SW_OWNERSHIP);
   13358  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   13359  1.281   msaitoh 		if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0)
   13360  1.281   msaitoh 			break;
   13361  1.281   msaitoh 		delay(2*1000);
   13362  1.281   msaitoh 		i++;
   13363  1.281   msaitoh 	} while (i < WM_MDIO_OWNERSHIP_TIMEOUT);
   13364  1.281   msaitoh 
   13365  1.281   msaitoh 	if (i == WM_MDIO_OWNERSHIP_TIMEOUT) {
   13366  1.281   msaitoh 		wm_put_hw_semaphore_82573(sc);
   13367  1.281   msaitoh 		log(LOG_ERR, "%s: Driver can't access the PHY\n",
   13368  1.281   msaitoh 		    device_xname(sc->sc_dev));
   13369  1.281   msaitoh 		return -1;
   13370  1.189   msaitoh 	}
   13371  1.189   msaitoh 
   13372  1.189   msaitoh 	return 0;
   13373  1.189   msaitoh }
   13374  1.189   msaitoh 
   13375  1.169   msaitoh static void
   13376  1.281   msaitoh wm_put_hw_semaphore_82573(struct wm_softc *sc)
   13377  1.169   msaitoh {
   13378  1.169   msaitoh 	uint32_t reg;
   13379  1.169   msaitoh 
   13380  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13381  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13382  1.420   msaitoh 
   13383  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   13384  1.281   msaitoh 	reg &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;
   13385  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
   13386  1.281   msaitoh }
   13387  1.281   msaitoh 
   13388  1.281   msaitoh /*
   13389  1.281   msaitoh  * Management mode and power management related subroutines.
   13390  1.281   msaitoh  * BMC, AMT, suspend/resume and EEE.
   13391  1.281   msaitoh  */
   13392  1.281   msaitoh 
   13393  1.378   msaitoh #ifdef WM_WOL
   13394  1.281   msaitoh static int
   13395  1.281   msaitoh wm_check_mng_mode(struct wm_softc *sc)
   13396  1.281   msaitoh {
   13397  1.281   msaitoh 	int rv;
   13398  1.281   msaitoh 
   13399  1.169   msaitoh 	switch (sc->sc_type) {
   13400  1.169   msaitoh 	case WM_T_ICH8:
   13401  1.169   msaitoh 	case WM_T_ICH9:
   13402  1.169   msaitoh 	case WM_T_ICH10:
   13403  1.190   msaitoh 	case WM_T_PCH:
   13404  1.221   msaitoh 	case WM_T_PCH2:
   13405  1.249   msaitoh 	case WM_T_PCH_LPT:
   13406  1.392   msaitoh 	case WM_T_PCH_SPT:
   13407  1.570   msaitoh 	case WM_T_PCH_CNP:
   13408  1.281   msaitoh 		rv = wm_check_mng_mode_ich8lan(sc);
   13409  1.281   msaitoh 		break;
   13410  1.281   msaitoh 	case WM_T_82574:
   13411  1.281   msaitoh 	case WM_T_82583:
   13412  1.281   msaitoh 		rv = wm_check_mng_mode_82574(sc);
   13413  1.281   msaitoh 		break;
   13414  1.281   msaitoh 	case WM_T_82571:
   13415  1.281   msaitoh 	case WM_T_82572:
   13416  1.281   msaitoh 	case WM_T_82573:
   13417  1.281   msaitoh 	case WM_T_80003:
   13418  1.281   msaitoh 		rv = wm_check_mng_mode_generic(sc);
   13419  1.169   msaitoh 		break;
   13420  1.169   msaitoh 	default:
   13421  1.281   msaitoh 		/* noting to do */
   13422  1.281   msaitoh 		rv = 0;
   13423  1.169   msaitoh 		break;
   13424  1.169   msaitoh 	}
   13425  1.281   msaitoh 
   13426  1.281   msaitoh 	return rv;
   13427  1.169   msaitoh }
   13428  1.173   msaitoh 
   13429  1.281   msaitoh static int
   13430  1.281   msaitoh wm_check_mng_mode_ich8lan(struct wm_softc *sc)
   13431  1.203   msaitoh {
   13432  1.281   msaitoh 	uint32_t fwsm;
   13433  1.281   msaitoh 
   13434  1.281   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   13435  1.203   msaitoh 
   13436  1.386   msaitoh 	if (((fwsm & FWSM_FW_VALID) != 0)
   13437  1.386   msaitoh 	    && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))
   13438  1.281   msaitoh 		return 1;
   13439  1.246  christos 
   13440  1.281   msaitoh 	return 0;
   13441  1.203   msaitoh }
   13442  1.203   msaitoh 
   13443  1.173   msaitoh static int
   13444  1.281   msaitoh wm_check_mng_mode_82574(struct wm_softc *sc)
   13445  1.173   msaitoh {
   13446  1.281   msaitoh 	uint16_t data;
   13447  1.173   msaitoh 
   13448  1.293   msaitoh 	wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
   13449  1.279   msaitoh 
   13450  1.293   msaitoh 	if ((data & NVM_CFG2_MNGM_MASK) != 0)
   13451  1.281   msaitoh 		return 1;
   13452  1.173   msaitoh 
   13453  1.173   msaitoh 	return 0;
   13454  1.173   msaitoh }
   13455  1.192   msaitoh 
   13456  1.281   msaitoh static int
   13457  1.281   msaitoh wm_check_mng_mode_generic(struct wm_softc *sc)
   13458  1.202   msaitoh {
   13459  1.281   msaitoh 	uint32_t fwsm;
   13460  1.202   msaitoh 
   13461  1.281   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   13462  1.202   msaitoh 
   13463  1.386   msaitoh 	if (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_IAMT_MODE)
   13464  1.281   msaitoh 		return 1;
   13465  1.202   msaitoh 
   13466  1.281   msaitoh 	return 0;
   13467  1.202   msaitoh }
   13468  1.378   msaitoh #endif /* WM_WOL */
   13469  1.202   msaitoh 
   13470  1.281   msaitoh static int
   13471  1.281   msaitoh wm_enable_mng_pass_thru(struct wm_softc *sc)
   13472  1.202   msaitoh {
   13473  1.281   msaitoh 	uint32_t manc, fwsm, factps;
   13474  1.202   msaitoh 
   13475  1.281   msaitoh 	if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) == 0)
   13476  1.281   msaitoh 		return 0;
   13477  1.202   msaitoh 
   13478  1.281   msaitoh 	manc = CSR_READ(sc, WMREG_MANC);
   13479  1.203   msaitoh 
   13480  1.281   msaitoh 	DPRINTF(WM_DEBUG_MANAGE, ("%s: MANC (%08x)\n",
   13481  1.281   msaitoh 		device_xname(sc->sc_dev), manc));
   13482  1.281   msaitoh 	if ((manc & MANC_RECV_TCO_EN) == 0)
   13483  1.281   msaitoh 		return 0;
   13484  1.203   msaitoh 
   13485  1.281   msaitoh 	if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) {
   13486  1.281   msaitoh 		fwsm = CSR_READ(sc, WMREG_FWSM);
   13487  1.281   msaitoh 		factps = CSR_READ(sc, WMREG_FACTPS);
   13488  1.281   msaitoh 		if (((factps & FACTPS_MNGCG) == 0)
   13489  1.386   msaitoh 		    && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE))
   13490  1.281   msaitoh 			return 1;
   13491  1.281   msaitoh 	} else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){
   13492  1.281   msaitoh 		uint16_t data;
   13493  1.203   msaitoh 
   13494  1.281   msaitoh 		factps = CSR_READ(sc, WMREG_FACTPS);
   13495  1.293   msaitoh 		wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data);
   13496  1.281   msaitoh 		DPRINTF(WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n",
   13497  1.281   msaitoh 			device_xname(sc->sc_dev), factps, data));
   13498  1.281   msaitoh 		if (((factps & FACTPS_MNGCG) == 0)
   13499  1.293   msaitoh 		    && ((data & NVM_CFG2_MNGM_MASK)
   13500  1.293   msaitoh 			== (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT)))
   13501  1.281   msaitoh 			return 1;
   13502  1.281   msaitoh 	} else if (((manc & MANC_SMBUS_EN) != 0)
   13503  1.281   msaitoh 	    && ((manc & MANC_ASF_EN) == 0))
   13504  1.281   msaitoh 		return 1;
   13505  1.203   msaitoh 
   13506  1.281   msaitoh 	return 0;
   13507  1.203   msaitoh }
   13508  1.203   msaitoh 
   13509  1.386   msaitoh static bool
   13510  1.386   msaitoh wm_phy_resetisblocked(struct wm_softc *sc)
   13511  1.192   msaitoh {
   13512  1.380   msaitoh 	bool blocked = false;
   13513  1.281   msaitoh 	uint32_t reg;
   13514  1.380   msaitoh 	int i = 0;
   13515  1.192   msaitoh 
   13516  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13517  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13518  1.420   msaitoh 
   13519  1.281   msaitoh 	switch (sc->sc_type) {
   13520  1.281   msaitoh 	case WM_T_ICH8:
   13521  1.281   msaitoh 	case WM_T_ICH9:
   13522  1.281   msaitoh 	case WM_T_ICH10:
   13523  1.281   msaitoh 	case WM_T_PCH:
   13524  1.281   msaitoh 	case WM_T_PCH2:
   13525  1.281   msaitoh 	case WM_T_PCH_LPT:
   13526  1.392   msaitoh 	case WM_T_PCH_SPT:
   13527  1.570   msaitoh 	case WM_T_PCH_CNP:
   13528  1.380   msaitoh 		do {
   13529  1.380   msaitoh 			reg = CSR_READ(sc, WMREG_FWSM);
   13530  1.380   msaitoh 			if ((reg & FWSM_RSPCIPHY) == 0) {
   13531  1.380   msaitoh 				blocked = true;
   13532  1.380   msaitoh 				delay(10*1000);
   13533  1.380   msaitoh 				continue;
   13534  1.380   msaitoh 			}
   13535  1.380   msaitoh 			blocked = false;
   13536  1.424   msaitoh 		} while (blocked && (i++ < 30));
   13537  1.386   msaitoh 		return blocked;
   13538  1.281   msaitoh 		break;
   13539  1.281   msaitoh 	case WM_T_82571:
   13540  1.281   msaitoh 	case WM_T_82572:
   13541  1.281   msaitoh 	case WM_T_82573:
   13542  1.281   msaitoh 	case WM_T_82574:
   13543  1.281   msaitoh 	case WM_T_82583:
   13544  1.281   msaitoh 	case WM_T_80003:
   13545  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_MANC);
   13546  1.281   msaitoh 		if ((reg & MANC_BLK_PHY_RST_ON_IDE) != 0)
   13547  1.386   msaitoh 			return true;
   13548  1.281   msaitoh 		else
   13549  1.386   msaitoh 			return false;
   13550  1.281   msaitoh 		break;
   13551  1.281   msaitoh 	default:
   13552  1.281   msaitoh 		/* no problem */
   13553  1.281   msaitoh 		break;
   13554  1.192   msaitoh 	}
   13555  1.192   msaitoh 
   13556  1.386   msaitoh 	return false;
   13557  1.192   msaitoh }
   13558  1.192   msaitoh 
   13559  1.192   msaitoh static void
   13560  1.281   msaitoh wm_get_hw_control(struct wm_softc *sc)
   13561  1.221   msaitoh {
   13562  1.281   msaitoh 	uint32_t reg;
   13563  1.221   msaitoh 
   13564  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13565  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13566  1.420   msaitoh 
   13567  1.446   msaitoh 	if (sc->sc_type == WM_T_82573) {
   13568  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   13569  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD);
   13570  1.446   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   13571  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13572  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);
   13573  1.281   msaitoh 	}
   13574  1.221   msaitoh }
   13575  1.221   msaitoh 
   13576  1.221   msaitoh static void
   13577  1.281   msaitoh wm_release_hw_control(struct wm_softc *sc)
   13578  1.192   msaitoh {
   13579  1.281   msaitoh 	uint32_t reg;
   13580  1.192   msaitoh 
   13581  1.420   msaitoh 	DPRINTF(WM_DEBUG_LOCK, ("%s: %s called\n",
   13582  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13583  1.420   msaitoh 
   13584  1.281   msaitoh 	if (sc->sc_type == WM_T_82573) {
   13585  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_SWSM);
   13586  1.281   msaitoh 		CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_DRV_LOAD);
   13587  1.446   msaitoh 	} else if (sc->sc_type >= WM_T_82571) {
   13588  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13589  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg & ~CTRL_EXT_DRV_LOAD);
   13590  1.192   msaitoh 	}
   13591  1.192   msaitoh }
   13592  1.192   msaitoh 
   13593  1.192   msaitoh static void
   13594  1.392   msaitoh wm_gate_hw_phy_config_ich8lan(struct wm_softc *sc, bool gate)
   13595  1.221   msaitoh {
   13596  1.221   msaitoh 	uint32_t reg;
   13597  1.221   msaitoh 
   13598  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13599  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13600  1.420   msaitoh 
   13601  1.394   msaitoh 	if (sc->sc_type < WM_T_PCH2)
   13602  1.394   msaitoh 		return;
   13603  1.394   msaitoh 
   13604  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_EXTCNFCTR);
   13605  1.221   msaitoh 
   13606  1.392   msaitoh 	if (gate)
   13607  1.281   msaitoh 		reg |= EXTCNFCTR_GATE_PHY_CFG;
   13608  1.192   msaitoh 	else
   13609  1.281   msaitoh 		reg &= ~EXTCNFCTR_GATE_PHY_CFG;
   13610  1.192   msaitoh 
   13611  1.281   msaitoh 	CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);
   13612  1.192   msaitoh }
   13613  1.199   msaitoh 
   13614  1.199   msaitoh static void
   13615  1.221   msaitoh wm_smbustopci(struct wm_softc *sc)
   13616  1.221   msaitoh {
   13617  1.394   msaitoh 	uint32_t fwsm, reg;
   13618  1.447   msaitoh 	int rv = 0;
   13619  1.394   msaitoh 
   13620  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13621  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   13622  1.420   msaitoh 
   13623  1.394   msaitoh 	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
   13624  1.394   msaitoh 	wm_gate_hw_phy_config_ich8lan(sc, true);
   13625  1.394   msaitoh 
   13626  1.447   msaitoh 	/* Disable ULP */
   13627  1.447   msaitoh 	wm_ulp_disable(sc);
   13628  1.447   msaitoh 
   13629  1.424   msaitoh 	/* Acquire PHY semaphore */
   13630  1.424   msaitoh 	sc->phy.acquire(sc);
   13631  1.221   msaitoh 
   13632  1.221   msaitoh 	fwsm = CSR_READ(sc, WMREG_FWSM);
   13633  1.447   msaitoh 	switch (sc->sc_type) {
   13634  1.447   msaitoh 	case WM_T_PCH_LPT:
   13635  1.447   msaitoh 	case WM_T_PCH_SPT:
   13636  1.570   msaitoh 	case WM_T_PCH_CNP:
   13637  1.447   msaitoh 		if (wm_phy_is_accessible_pchlan(sc))
   13638  1.447   msaitoh 			break;
   13639  1.447   msaitoh 
   13640  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13641  1.447   msaitoh 		reg |= CTRL_EXT_FORCE_SMBUS;
   13642  1.447   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13643  1.447   msaitoh #if 0
   13644  1.447   msaitoh 		/* XXX Isn't this required??? */
   13645  1.447   msaitoh 		CSR_WRITE_FLUSH(sc);
   13646  1.447   msaitoh #endif
   13647  1.447   msaitoh 		delay(50 * 1000);
   13648  1.447   msaitoh 		/* FALLTHROUGH */
   13649  1.447   msaitoh 	case WM_T_PCH2:
   13650  1.447   msaitoh 		if (wm_phy_is_accessible_pchlan(sc) == true)
   13651  1.447   msaitoh 			break;
   13652  1.447   msaitoh 		/* FALLTHROUGH */
   13653  1.447   msaitoh 	case WM_T_PCH:
   13654  1.452     joerg 		if (sc->sc_type == WM_T_PCH)
   13655  1.447   msaitoh 			if ((fwsm & FWSM_FW_VALID) != 0)
   13656  1.447   msaitoh 				break;
   13657  1.447   msaitoh 
   13658  1.447   msaitoh 		if (wm_phy_resetisblocked(sc) == true) {
   13659  1.447   msaitoh 			printf("XXX reset is blocked(3)\n");
   13660  1.447   msaitoh 			break;
   13661  1.394   msaitoh 		}
   13662  1.394   msaitoh 
   13663  1.447   msaitoh 		wm_toggle_lanphypc_pch_lpt(sc);
   13664  1.221   msaitoh 
   13665  1.394   msaitoh 		if (sc->sc_type >= WM_T_PCH_LPT) {
   13666  1.447   msaitoh 			if (wm_phy_is_accessible_pchlan(sc) == true)
   13667  1.447   msaitoh 				break;
   13668  1.447   msaitoh 
   13669  1.394   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13670  1.394   msaitoh 			reg &= ~CTRL_EXT_FORCE_SMBUS;
   13671  1.394   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13672  1.447   msaitoh 
   13673  1.447   msaitoh 			if (wm_phy_is_accessible_pchlan(sc) == true)
   13674  1.447   msaitoh 				break;
   13675  1.447   msaitoh 			rv = -1;
   13676  1.394   msaitoh 		}
   13677  1.447   msaitoh 		break;
   13678  1.447   msaitoh 	default:
   13679  1.447   msaitoh 		break;
   13680  1.221   msaitoh 	}
   13681  1.394   msaitoh 
   13682  1.394   msaitoh 	/* Release semaphore */
   13683  1.424   msaitoh 	sc->phy.release(sc);
   13684  1.394   msaitoh 
   13685  1.447   msaitoh 	if (rv == 0) {
   13686  1.447   msaitoh 		if (wm_phy_resetisblocked(sc)) {
   13687  1.447   msaitoh 			printf("XXX reset is blocked(4)\n");
   13688  1.447   msaitoh 			goto out;
   13689  1.447   msaitoh 		}
   13690  1.447   msaitoh 		wm_reset_phy(sc);
   13691  1.447   msaitoh 		if (wm_phy_resetisblocked(sc))
   13692  1.447   msaitoh 			printf("XXX reset is blocked(4)\n");
   13693  1.447   msaitoh 	}
   13694  1.447   msaitoh 
   13695  1.447   msaitoh out:
   13696  1.394   msaitoh 	/*
   13697  1.394   msaitoh 	 * Ungate automatic PHY configuration by hardware on non-managed 82579
   13698  1.394   msaitoh 	 */
   13699  1.447   msaitoh 	if ((sc->sc_type == WM_T_PCH2) && ((fwsm & FWSM_FW_VALID) == 0)) {
   13700  1.447   msaitoh 		delay(10*1000);
   13701  1.394   msaitoh 		wm_gate_hw_phy_config_ich8lan(sc, false);
   13702  1.447   msaitoh 	}
   13703  1.221   msaitoh }
   13704  1.221   msaitoh 
   13705  1.221   msaitoh static void
   13706  1.203   msaitoh wm_init_manageability(struct wm_softc *sc)
   13707  1.203   msaitoh {
   13708  1.203   msaitoh 
   13709  1.392   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13710  1.392   msaitoh 		device_xname(sc->sc_dev), __func__));
   13711  1.203   msaitoh 	if (sc->sc_flags & WM_F_HAS_MANAGE) {
   13712  1.203   msaitoh 		uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H);
   13713  1.203   msaitoh 		uint32_t manc = CSR_READ(sc, WMREG_MANC);
   13714  1.203   msaitoh 
   13715  1.281   msaitoh 		/* Disable hardware interception of ARP */
   13716  1.203   msaitoh 		manc &= ~MANC_ARP_EN;
   13717  1.203   msaitoh 
   13718  1.281   msaitoh 		/* Enable receiving management packets to the host */
   13719  1.203   msaitoh 		if (sc->sc_type >= WM_T_82571) {
   13720  1.203   msaitoh 			manc |= MANC_EN_MNG2HOST;
   13721  1.573   msaitoh 			manc2h |= MANC2H_PORT_623 | MANC2H_PORT_624;
   13722  1.203   msaitoh 			CSR_WRITE(sc, WMREG_MANC2H, manc2h);
   13723  1.203   msaitoh 		}
   13724  1.203   msaitoh 
   13725  1.203   msaitoh 		CSR_WRITE(sc, WMREG_MANC, manc);
   13726  1.203   msaitoh 	}
   13727  1.203   msaitoh }
   13728  1.203   msaitoh 
   13729  1.203   msaitoh static void
   13730  1.203   msaitoh wm_release_manageability(struct wm_softc *sc)
   13731  1.203   msaitoh {
   13732  1.203   msaitoh 
   13733  1.203   msaitoh 	if (sc->sc_flags & WM_F_HAS_MANAGE) {
   13734  1.203   msaitoh 		uint32_t manc = CSR_READ(sc, WMREG_MANC);
   13735  1.203   msaitoh 
   13736  1.260   msaitoh 		manc |= MANC_ARP_EN;
   13737  1.203   msaitoh 		if (sc->sc_type >= WM_T_82571)
   13738  1.203   msaitoh 			manc &= ~MANC_EN_MNG2HOST;
   13739  1.203   msaitoh 
   13740  1.203   msaitoh 		CSR_WRITE(sc, WMREG_MANC, manc);
   13741  1.203   msaitoh 	}
   13742  1.203   msaitoh }
   13743  1.203   msaitoh 
   13744  1.203   msaitoh static void
   13745  1.203   msaitoh wm_get_wakeup(struct wm_softc *sc)
   13746  1.203   msaitoh {
   13747  1.203   msaitoh 
   13748  1.203   msaitoh 	/* 0: HAS_AMT, ARC_SUBSYS_VALID, ASF_FIRMWARE_PRES */
   13749  1.203   msaitoh 	switch (sc->sc_type) {
   13750  1.203   msaitoh 	case WM_T_82573:
   13751  1.203   msaitoh 	case WM_T_82583:
   13752  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_AMT;
   13753  1.203   msaitoh 		/* FALLTHROUGH */
   13754  1.246  christos 	case WM_T_80003:
   13755  1.203   msaitoh 	case WM_T_82575:
   13756  1.203   msaitoh 	case WM_T_82576:
   13757  1.208   msaitoh 	case WM_T_82580:
   13758  1.228   msaitoh 	case WM_T_I350:
   13759  1.265   msaitoh 	case WM_T_I354:
   13760  1.386   msaitoh 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE) != 0)
   13761  1.203   msaitoh 			sc->sc_flags |= WM_F_ARC_SUBSYS_VALID;
   13762  1.449   msaitoh 		/* FALLTHROUGH */
   13763  1.449   msaitoh 	case WM_T_82541:
   13764  1.449   msaitoh 	case WM_T_82541_2:
   13765  1.449   msaitoh 	case WM_T_82547:
   13766  1.449   msaitoh 	case WM_T_82547_2:
   13767  1.450   msaitoh 	case WM_T_82571:
   13768  1.450   msaitoh 	case WM_T_82572:
   13769  1.450   msaitoh 	case WM_T_82574:
   13770  1.203   msaitoh 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
   13771  1.203   msaitoh 		break;
   13772  1.203   msaitoh 	case WM_T_ICH8:
   13773  1.203   msaitoh 	case WM_T_ICH9:
   13774  1.203   msaitoh 	case WM_T_ICH10:
   13775  1.203   msaitoh 	case WM_T_PCH:
   13776  1.221   msaitoh 	case WM_T_PCH2:
   13777  1.249   msaitoh 	case WM_T_PCH_LPT:
   13778  1.449   msaitoh 	case WM_T_PCH_SPT:
   13779  1.570   msaitoh 	case WM_T_PCH_CNP:
   13780  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_AMT;
   13781  1.203   msaitoh 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
   13782  1.203   msaitoh 		break;
   13783  1.203   msaitoh 	default:
   13784  1.203   msaitoh 		break;
   13785  1.203   msaitoh 	}
   13786  1.203   msaitoh 
   13787  1.203   msaitoh 	/* 1: HAS_MANAGE */
   13788  1.203   msaitoh 	if (wm_enable_mng_pass_thru(sc) != 0)
   13789  1.203   msaitoh 		sc->sc_flags |= WM_F_HAS_MANAGE;
   13790  1.203   msaitoh 
   13791  1.203   msaitoh 	/*
   13792  1.203   msaitoh 	 * Note that the WOL flags is set after the resetting of the eeprom
   13793  1.203   msaitoh 	 * stuff
   13794  1.203   msaitoh 	 */
   13795  1.203   msaitoh }
   13796  1.203   msaitoh 
   13797  1.447   msaitoh /*
   13798  1.447   msaitoh  * Unconfigure Ultra Low Power mode.
   13799  1.447   msaitoh  * Only for I217 and newer (see below).
   13800  1.447   msaitoh  */
   13801  1.447   msaitoh static void
   13802  1.447   msaitoh wm_ulp_disable(struct wm_softc *sc)
   13803  1.447   msaitoh {
   13804  1.447   msaitoh 	uint32_t reg;
   13805  1.447   msaitoh 	int i = 0;
   13806  1.447   msaitoh 
   13807  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13808  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   13809  1.447   msaitoh 	/* Exclude old devices */
   13810  1.447   msaitoh 	if ((sc->sc_type < WM_T_PCH_LPT)
   13811  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I217_LM)
   13812  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I217_V)
   13813  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_LM2)
   13814  1.447   msaitoh 	    || (sc->sc_pcidevid == PCI_PRODUCT_INTEL_I218_V2))
   13815  1.447   msaitoh 		return;
   13816  1.447   msaitoh 
   13817  1.447   msaitoh 	if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) != 0) {
   13818  1.447   msaitoh 		/* Request ME un-configure ULP mode in the PHY */
   13819  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_H2ME);
   13820  1.447   msaitoh 		reg &= ~H2ME_ULP;
   13821  1.447   msaitoh 		reg |= H2ME_ENFORCE_SETTINGS;
   13822  1.447   msaitoh 		CSR_WRITE(sc, WMREG_H2ME, reg);
   13823  1.447   msaitoh 
   13824  1.447   msaitoh 		/* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
   13825  1.447   msaitoh 		while ((CSR_READ(sc, WMREG_FWSM) & FWSM_ULP_CFG_DONE) != 0) {
   13826  1.447   msaitoh 			if (i++ == 30) {
   13827  1.447   msaitoh 				printf("%s timed out\n", __func__);
   13828  1.447   msaitoh 				return;
   13829  1.447   msaitoh 			}
   13830  1.447   msaitoh 			delay(10 * 1000);
   13831  1.447   msaitoh 		}
   13832  1.447   msaitoh 		reg = CSR_READ(sc, WMREG_H2ME);
   13833  1.447   msaitoh 		reg &= ~H2ME_ENFORCE_SETTINGS;
   13834  1.447   msaitoh 		CSR_WRITE(sc, WMREG_H2ME, reg);
   13835  1.447   msaitoh 
   13836  1.447   msaitoh 		return;
   13837  1.447   msaitoh 	}
   13838  1.447   msaitoh 
   13839  1.447   msaitoh 	/* Acquire semaphore */
   13840  1.447   msaitoh 	sc->phy.acquire(sc);
   13841  1.447   msaitoh 
   13842  1.447   msaitoh 	/* Toggle LANPHYPC */
   13843  1.447   msaitoh 	wm_toggle_lanphypc_pch_lpt(sc);
   13844  1.447   msaitoh 
   13845  1.447   msaitoh 	/* Unforce SMBus mode in PHY */
   13846  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, CV_SMB_CTRL);
   13847  1.447   msaitoh 	if (reg == 0x0000 || reg == 0xffff) {
   13848  1.447   msaitoh 		uint32_t reg2;
   13849  1.447   msaitoh 
   13850  1.447   msaitoh 		printf("%s: Force SMBus first.\n", __func__);
   13851  1.447   msaitoh 		reg2 = CSR_READ(sc, WMREG_CTRL_EXT);
   13852  1.447   msaitoh 		reg2 |= CTRL_EXT_FORCE_SMBUS;
   13853  1.447   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg2);
   13854  1.447   msaitoh 		delay(50 * 1000);
   13855  1.447   msaitoh 
   13856  1.447   msaitoh 		reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, CV_SMB_CTRL);
   13857  1.447   msaitoh 	}
   13858  1.447   msaitoh 	reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
   13859  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, CV_SMB_CTRL, reg);
   13860  1.447   msaitoh 
   13861  1.447   msaitoh 	/* Unforce SMBus mode in MAC */
   13862  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL_EXT);
   13863  1.447   msaitoh 	reg &= ~CTRL_EXT_FORCE_SMBUS;
   13864  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   13865  1.447   msaitoh 
   13866  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, HV_PM_CTRL);
   13867  1.447   msaitoh 	reg |= HV_PM_CTRL_K1_ENA;
   13868  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, HV_PM_CTRL, reg);
   13869  1.447   msaitoh 
   13870  1.447   msaitoh 	reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1);
   13871  1.447   msaitoh 	reg &= ~(I218_ULP_CONFIG1_IND
   13872  1.447   msaitoh 	    | I218_ULP_CONFIG1_STICKY_ULP
   13873  1.447   msaitoh 	    | I218_ULP_CONFIG1_RESET_TO_SMBUS
   13874  1.447   msaitoh 	    | I218_ULP_CONFIG1_WOL_HOST
   13875  1.447   msaitoh 	    | I218_ULP_CONFIG1_INBAND_EXIT
   13876  1.447   msaitoh 	    | I218_ULP_CONFIG1_EN_ULP_LANPHYPC
   13877  1.447   msaitoh 	    | I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST
   13878  1.447   msaitoh 	    | I218_ULP_CONFIG1_DIS_SMB_PERST);
   13879  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1, reg);
   13880  1.447   msaitoh 	reg |= I218_ULP_CONFIG1_START;
   13881  1.447   msaitoh 	wm_gmii_hv_writereg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1, reg);
   13882  1.447   msaitoh 
   13883  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM7);
   13884  1.447   msaitoh 	reg &= ~FEXTNVM7_DIS_SMB_PERST;
   13885  1.447   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM7, reg);
   13886  1.447   msaitoh 
   13887  1.447   msaitoh 	/* Release semaphore */
   13888  1.447   msaitoh 	sc->phy.release(sc);
   13889  1.447   msaitoh 	wm_gmii_reset(sc);
   13890  1.447   msaitoh 	delay(50 * 1000);
   13891  1.447   msaitoh }
   13892  1.447   msaitoh 
   13893  1.203   msaitoh /* WOL in the newer chipset interfaces (pchlan) */
   13894  1.203   msaitoh static void
   13895  1.203   msaitoh wm_enable_phy_wakeup(struct wm_softc *sc)
   13896  1.203   msaitoh {
   13897  1.203   msaitoh #if 0
   13898  1.203   msaitoh 	uint16_t preg;
   13899  1.203   msaitoh 
   13900  1.203   msaitoh 	/* Copy MAC RARs to PHY RARs */
   13901  1.203   msaitoh 
   13902  1.203   msaitoh 	/* Copy MAC MTA to PHY MTA */
   13903  1.203   msaitoh 
   13904  1.281   msaitoh 	/* Configure PHY Rx Control register */
   13905  1.281   msaitoh 
   13906  1.281   msaitoh 	/* Enable PHY wakeup in MAC register */
   13907  1.281   msaitoh 
   13908  1.281   msaitoh 	/* Configure and enable PHY wakeup in PHY registers */
   13909  1.281   msaitoh 
   13910  1.281   msaitoh 	/* Activate PHY wakeup */
   13911  1.281   msaitoh 
   13912  1.281   msaitoh 	/* XXX */
   13913  1.281   msaitoh #endif
   13914  1.281   msaitoh }
   13915  1.281   msaitoh 
   13916  1.281   msaitoh /* Power down workaround on D3 */
   13917  1.281   msaitoh static void
   13918  1.281   msaitoh wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *sc)
   13919  1.281   msaitoh {
   13920  1.281   msaitoh 	uint32_t reg;
   13921  1.281   msaitoh 	int i;
   13922  1.281   msaitoh 
   13923  1.281   msaitoh 	for (i = 0; i < 2; i++) {
   13924  1.281   msaitoh 		/* Disable link */
   13925  1.281   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13926  1.281   msaitoh 		reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
   13927  1.281   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13928  1.281   msaitoh 
   13929  1.281   msaitoh 		/*
   13930  1.281   msaitoh 		 * Call gig speed drop workaround on Gig disable before
   13931  1.281   msaitoh 		 * accessing any PHY registers
   13932  1.281   msaitoh 		 */
   13933  1.281   msaitoh 		if (sc->sc_type == WM_T_ICH8)
   13934  1.281   msaitoh 			wm_gig_downshift_workaround_ich8lan(sc);
   13935  1.203   msaitoh 
   13936  1.281   msaitoh 		/* Write VR power-down enable */
   13937  1.281   msaitoh 		reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL);
   13938  1.281   msaitoh 		reg &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
   13939  1.281   msaitoh 		reg |= IGP3_VR_CTRL_MODE_SHUTDOWN;
   13940  1.281   msaitoh 		sc->sc_mii.mii_writereg(sc->sc_dev, 1, IGP3_VR_CTRL, reg);
   13941  1.203   msaitoh 
   13942  1.281   msaitoh 		/* Read it back and test */
   13943  1.281   msaitoh 		reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL);
   13944  1.281   msaitoh 		reg &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
   13945  1.281   msaitoh 		if ((reg == IGP3_VR_CTRL_MODE_SHUTDOWN) || (i != 0))
   13946  1.281   msaitoh 			break;
   13947  1.203   msaitoh 
   13948  1.281   msaitoh 		/* Issue PHY reset and repeat at most one more time */
   13949  1.281   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   13950  1.281   msaitoh 	}
   13951  1.203   msaitoh }
   13952  1.203   msaitoh 
   13953  1.203   msaitoh static void
   13954  1.203   msaitoh wm_enable_wakeup(struct wm_softc *sc)
   13955  1.203   msaitoh {
   13956  1.203   msaitoh 	uint32_t reg, pmreg;
   13957  1.203   msaitoh 	pcireg_t pmode;
   13958  1.203   msaitoh 
   13959  1.425   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   13960  1.425   msaitoh 		device_xname(sc->sc_dev), __func__));
   13961  1.425   msaitoh 
   13962  1.203   msaitoh 	if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT,
   13963  1.203   msaitoh 		&pmreg, NULL) == 0)
   13964  1.203   msaitoh 		return;
   13965  1.203   msaitoh 
   13966  1.203   msaitoh 	/* Advertise the wakeup capability */
   13967  1.203   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_SWDPIN(2)
   13968  1.203   msaitoh 	    | CTRL_SWDPIN(3));
   13969  1.203   msaitoh 	CSR_WRITE(sc, WMREG_WUC, WUC_APME);
   13970  1.203   msaitoh 
   13971  1.203   msaitoh 	/* ICH workaround */
   13972  1.203   msaitoh 	switch (sc->sc_type) {
   13973  1.203   msaitoh 	case WM_T_ICH8:
   13974  1.203   msaitoh 	case WM_T_ICH9:
   13975  1.203   msaitoh 	case WM_T_ICH10:
   13976  1.203   msaitoh 	case WM_T_PCH:
   13977  1.221   msaitoh 	case WM_T_PCH2:
   13978  1.249   msaitoh 	case WM_T_PCH_LPT:
   13979  1.392   msaitoh 	case WM_T_PCH_SPT:
   13980  1.570   msaitoh 	case WM_T_PCH_CNP:
   13981  1.203   msaitoh 		/* Disable gig during WOL */
   13982  1.203   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   13983  1.203   msaitoh 		reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS;
   13984  1.203   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   13985  1.203   msaitoh 		if (sc->sc_type == WM_T_PCH)
   13986  1.203   msaitoh 			wm_gmii_reset(sc);
   13987  1.203   msaitoh 
   13988  1.203   msaitoh 		/* Power down workaround */
   13989  1.203   msaitoh 		if (sc->sc_phytype == WMPHY_82577) {
   13990  1.203   msaitoh 			struct mii_softc *child;
   13991  1.203   msaitoh 
   13992  1.203   msaitoh 			/* Assume that the PHY is copper */
   13993  1.203   msaitoh 			child = LIST_FIRST(&sc->sc_mii.mii_phys);
   13994  1.497    kardel 			if ((child != NULL) && (child->mii_mpd_rev <= 2))
   13995  1.203   msaitoh 				sc->sc_mii.mii_writereg(sc->sc_dev, 1,
   13996  1.203   msaitoh 				    (768 << 5) | 25, 0x0444); /* magic num */
   13997  1.203   msaitoh 		}
   13998  1.203   msaitoh 		break;
   13999  1.203   msaitoh 	default:
   14000  1.203   msaitoh 		break;
   14001  1.203   msaitoh 	}
   14002  1.203   msaitoh 
   14003  1.203   msaitoh 	/* Keep the laser running on fiber adapters */
   14004  1.311   msaitoh 	if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER)
   14005  1.311   msaitoh 	    || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) {
   14006  1.203   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   14007  1.203   msaitoh 		reg |= CTRL_EXT_SWDPIN(3);
   14008  1.203   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   14009  1.203   msaitoh 	}
   14010  1.203   msaitoh 
   14011  1.203   msaitoh 	reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG;
   14012  1.203   msaitoh #if 0	/* for the multicast packet */
   14013  1.203   msaitoh 	reg |= WUFC_MC;
   14014  1.203   msaitoh 	CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE);
   14015  1.203   msaitoh #endif
   14016  1.203   msaitoh 
   14017  1.442   msaitoh 	if (sc->sc_type >= WM_T_PCH)
   14018  1.203   msaitoh 		wm_enable_phy_wakeup(sc);
   14019  1.442   msaitoh 	else {
   14020  1.451   msaitoh 		CSR_WRITE(sc, WMREG_WUC, CSR_READ(sc, WMREG_WUC) | WUC_PME_EN);
   14021  1.203   msaitoh 		CSR_WRITE(sc, WMREG_WUFC, reg);
   14022  1.203   msaitoh 	}
   14023  1.203   msaitoh 
   14024  1.203   msaitoh 	if (((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
   14025  1.221   msaitoh 		|| (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
   14026  1.221   msaitoh 		|| (sc->sc_type == WM_T_PCH2))
   14027  1.203   msaitoh 		    && (sc->sc_phytype == WMPHY_IGP_3))
   14028  1.203   msaitoh 			wm_igp3_phy_powerdown_workaround_ich8lan(sc);
   14029  1.203   msaitoh 
   14030  1.203   msaitoh 	/* Request PME */
   14031  1.203   msaitoh 	pmode = pci_conf_read(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR);
   14032  1.203   msaitoh #if 0
   14033  1.203   msaitoh 	/* Disable WOL */
   14034  1.203   msaitoh 	pmode &= ~(PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN);
   14035  1.203   msaitoh #else
   14036  1.203   msaitoh 	/* For WOL */
   14037  1.203   msaitoh 	pmode |= PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN;
   14038  1.203   msaitoh #endif
   14039  1.203   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR, pmode);
   14040  1.203   msaitoh }
   14041  1.203   msaitoh 
   14042  1.552   msaitoh /* Disable ASPM L0s and/or L1 for workaround */
   14043  1.552   msaitoh static void
   14044  1.552   msaitoh wm_disable_aspm(struct wm_softc *sc)
   14045  1.552   msaitoh {
   14046  1.552   msaitoh 	pcireg_t reg, mask = 0;
   14047  1.552   msaitoh 	unsigned const char *str = "";
   14048  1.552   msaitoh 
   14049  1.552   msaitoh 	/*
   14050  1.552   msaitoh 	 *  Only for PCIe device which has PCIe capability in the PCI config
   14051  1.552   msaitoh 	 * space.
   14052  1.552   msaitoh 	 */
   14053  1.552   msaitoh 	if (((sc->sc_flags & WM_F_PCIE) == 0) || (sc->sc_pcixe_capoff == 0))
   14054  1.552   msaitoh 		return;
   14055  1.552   msaitoh 
   14056  1.552   msaitoh 	switch (sc->sc_type) {
   14057  1.552   msaitoh 	case WM_T_82571:
   14058  1.552   msaitoh 	case WM_T_82572:
   14059  1.552   msaitoh 		/*
   14060  1.552   msaitoh 		 * 8257[12] Errata 13: Device Does Not Support PCIe Active
   14061  1.552   msaitoh 		 * State Power management L1 State (ASPM L1).
   14062  1.552   msaitoh 		 */
   14063  1.552   msaitoh 		mask = PCIE_LCSR_ASPM_L1;
   14064  1.552   msaitoh 		str = "L1 is";
   14065  1.552   msaitoh 		break;
   14066  1.552   msaitoh 	case WM_T_82573:
   14067  1.552   msaitoh 	case WM_T_82574:
   14068  1.552   msaitoh 	case WM_T_82583:
   14069  1.552   msaitoh 		/*
   14070  1.552   msaitoh 		 * The 82573 disappears when PCIe ASPM L0s is enabled.
   14071  1.552   msaitoh 		 *
   14072  1.552   msaitoh 		 * The 82574 and 82583 does not support PCIe ASPM L0s with
   14073  1.552   msaitoh 		 * some chipset.  The document of 82574 and 82583 says that
   14074  1.552   msaitoh 		 * disabling L0s with some specific chipset is sufficient,
   14075  1.552   msaitoh 		 * but we follow as of the Intel em driver does.
   14076  1.552   msaitoh 		 *
   14077  1.552   msaitoh 		 * References:
   14078  1.552   msaitoh 		 * Errata 8 of the Specification Update of i82573.
   14079  1.552   msaitoh 		 * Errata 20 of the Specification Update of i82574.
   14080  1.552   msaitoh 		 * Errata 9 of the Specification Update of i82583.
   14081  1.552   msaitoh 		 */
   14082  1.552   msaitoh 		mask = PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S;
   14083  1.552   msaitoh 		str = "L0s and L1 are";
   14084  1.552   msaitoh 		break;
   14085  1.552   msaitoh 	default:
   14086  1.552   msaitoh 		return;
   14087  1.552   msaitoh 	}
   14088  1.552   msaitoh 
   14089  1.552   msaitoh 	reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   14090  1.552   msaitoh 	    sc->sc_pcixe_capoff + PCIE_LCSR);
   14091  1.552   msaitoh 	reg &= ~mask;
   14092  1.552   msaitoh 	pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   14093  1.552   msaitoh 	    sc->sc_pcixe_capoff + PCIE_LCSR, reg);
   14094  1.552   msaitoh 
   14095  1.552   msaitoh 	/* Print only in wm_attach() */
   14096  1.552   msaitoh 	if ((sc->sc_flags & WM_F_ATTACHED) == 0)
   14097  1.552   msaitoh 		aprint_verbose_dev(sc->sc_dev,
   14098  1.552   msaitoh 		    "ASPM %s disabled to workaround the errata.\n",
   14099  1.552   msaitoh 			str);
   14100  1.552   msaitoh }
   14101  1.552   msaitoh 
   14102  1.377   msaitoh /* LPLU */
   14103  1.377   msaitoh 
   14104  1.377   msaitoh static void
   14105  1.377   msaitoh wm_lplu_d0_disable(struct wm_softc *sc)
   14106  1.377   msaitoh {
   14107  1.519   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   14108  1.377   msaitoh 	uint32_t reg;
   14109  1.377   msaitoh 
   14110  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14111  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   14112  1.430   msaitoh 
   14113  1.519   msaitoh 	if (sc->sc_phytype == WMPHY_IFE)
   14114  1.519   msaitoh 		return;
   14115  1.377   msaitoh 
   14116  1.519   msaitoh 	switch (sc->sc_type) {
   14117  1.519   msaitoh 	case WM_T_82571:
   14118  1.519   msaitoh 	case WM_T_82572:
   14119  1.519   msaitoh 	case WM_T_82573:
   14120  1.519   msaitoh 	case WM_T_82575:
   14121  1.519   msaitoh 	case WM_T_82576:
   14122  1.519   msaitoh 		reg = mii->mii_readreg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT);
   14123  1.519   msaitoh 		reg &= ~PMR_D0_LPLU;
   14124  1.519   msaitoh 		mii->mii_writereg(sc->sc_dev, 1, MII_IGPHY_POWER_MGMT, reg);
   14125  1.519   msaitoh 		break;
   14126  1.519   msaitoh 	case WM_T_82580:
   14127  1.519   msaitoh 	case WM_T_I350:
   14128  1.519   msaitoh 	case WM_T_I210:
   14129  1.519   msaitoh 	case WM_T_I211:
   14130  1.519   msaitoh 		reg = CSR_READ(sc, WMREG_PHPM);
   14131  1.519   msaitoh 		reg &= ~PHPM_D0A_LPLU;
   14132  1.519   msaitoh 		CSR_WRITE(sc, WMREG_PHPM, reg);
   14133  1.519   msaitoh 		break;
   14134  1.519   msaitoh 	case WM_T_82574:
   14135  1.519   msaitoh 	case WM_T_82583:
   14136  1.519   msaitoh 	case WM_T_ICH8:
   14137  1.519   msaitoh 	case WM_T_ICH9:
   14138  1.519   msaitoh 	case WM_T_ICH10:
   14139  1.519   msaitoh 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
   14140  1.519   msaitoh 		reg &= ~(PHY_CTRL_GBE_DIS | PHY_CTRL_D0A_LPLU);
   14141  1.519   msaitoh 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   14142  1.519   msaitoh 		CSR_WRITE_FLUSH(sc);
   14143  1.519   msaitoh 		break;
   14144  1.519   msaitoh 	case WM_T_PCH:
   14145  1.519   msaitoh 	case WM_T_PCH2:
   14146  1.519   msaitoh 	case WM_T_PCH_LPT:
   14147  1.519   msaitoh 	case WM_T_PCH_SPT:
   14148  1.570   msaitoh 	case WM_T_PCH_CNP:
   14149  1.519   msaitoh 		reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_OEM_BITS);
   14150  1.519   msaitoh 		reg &= ~(HV_OEM_BITS_A1KDIS | HV_OEM_BITS_LPLU);
   14151  1.519   msaitoh 		if (wm_phy_resetisblocked(sc) == false)
   14152  1.519   msaitoh 			reg |= HV_OEM_BITS_ANEGNOW;
   14153  1.519   msaitoh 		wm_gmii_hv_writereg(sc->sc_dev, 1, HV_OEM_BITS, reg);
   14154  1.519   msaitoh 		break;
   14155  1.519   msaitoh 	default:
   14156  1.519   msaitoh 		break;
   14157  1.519   msaitoh 	}
   14158  1.377   msaitoh }
   14159  1.377   msaitoh 
   14160  1.281   msaitoh /* EEE */
   14161  1.228   msaitoh 
   14162  1.228   msaitoh static void
   14163  1.281   msaitoh wm_set_eee_i350(struct wm_softc *sc)
   14164  1.228   msaitoh {
   14165  1.228   msaitoh 	uint32_t ipcnfg, eeer;
   14166  1.228   msaitoh 
   14167  1.228   msaitoh 	ipcnfg = CSR_READ(sc, WMREG_IPCNFG);
   14168  1.228   msaitoh 	eeer = CSR_READ(sc, WMREG_EEER);
   14169  1.228   msaitoh 
   14170  1.228   msaitoh 	if ((sc->sc_flags & WM_F_EEE) != 0) {
   14171  1.228   msaitoh 		ipcnfg |= (IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN);
   14172  1.228   msaitoh 		eeer |= (EEER_TX_LPI_EN | EEER_RX_LPI_EN
   14173  1.228   msaitoh 		    | EEER_LPI_FC);
   14174  1.228   msaitoh 	} else {
   14175  1.228   msaitoh 		ipcnfg &= ~(IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN);
   14176  1.322   msaitoh 		ipcnfg &= ~IPCNFG_10BASE_TE;
   14177  1.228   msaitoh 		eeer &= ~(EEER_TX_LPI_EN | EEER_RX_LPI_EN
   14178  1.228   msaitoh 		    | EEER_LPI_FC);
   14179  1.228   msaitoh 	}
   14180  1.228   msaitoh 
   14181  1.228   msaitoh 	CSR_WRITE(sc, WMREG_IPCNFG, ipcnfg);
   14182  1.228   msaitoh 	CSR_WRITE(sc, WMREG_EEER, eeer);
   14183  1.228   msaitoh 	CSR_READ(sc, WMREG_IPCNFG); /* XXX flush? */
   14184  1.228   msaitoh 	CSR_READ(sc, WMREG_EEER); /* XXX flush? */
   14185  1.228   msaitoh }
   14186  1.281   msaitoh 
   14187  1.281   msaitoh /*
   14188  1.281   msaitoh  * Workarounds (mainly PHY related).
   14189  1.281   msaitoh  * Basically, PHY's workarounds are in the PHY drivers.
   14190  1.281   msaitoh  */
   14191  1.281   msaitoh 
   14192  1.281   msaitoh /* Work-around for 82566 Kumeran PCS lock loss */
   14193  1.281   msaitoh static void
   14194  1.281   msaitoh wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *sc)
   14195  1.281   msaitoh {
   14196  1.523   msaitoh 	struct mii_data *mii = &sc->sc_mii;
   14197  1.523   msaitoh 	uint32_t status = CSR_READ(sc, WMREG_STATUS);
   14198  1.523   msaitoh 	int i;
   14199  1.281   msaitoh 	int reg;
   14200  1.281   msaitoh 
   14201  1.523   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14202  1.523   msaitoh 		device_xname(sc->sc_dev), __func__));
   14203  1.281   msaitoh 
   14204  1.281   msaitoh 	/* If the link is not up, do nothing */
   14205  1.523   msaitoh 	if ((status & STATUS_LU) == 0)
   14206  1.281   msaitoh 		return;
   14207  1.281   msaitoh 
   14208  1.281   msaitoh 	/* Nothing to do if the link is other than 1Gbps */
   14209  1.523   msaitoh 	if (__SHIFTOUT(status, STATUS_SPEED) != STATUS_SPEED_1000)
   14210  1.281   msaitoh 		return;
   14211  1.281   msaitoh 
   14212  1.523   msaitoh 	reg = CSR_READ(sc, WMREG_PHY_CTRL);
   14213  1.281   msaitoh 	for (i = 0; i < 10; i++) {
   14214  1.281   msaitoh 		/* read twice */
   14215  1.523   msaitoh 		reg = mii->mii_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
   14216  1.523   msaitoh 		reg = mii->mii_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
   14217  1.381   msaitoh 		if ((reg & IGP3_KMRN_DIAG_PCS_LOCK_LOSS) == 0)
   14218  1.281   msaitoh 			goto out;	/* GOOD! */
   14219  1.281   msaitoh 
   14220  1.281   msaitoh 		/* Reset the PHY */
   14221  1.523   msaitoh 		wm_reset_phy(sc);
   14222  1.281   msaitoh 		delay(5*1000);
   14223  1.281   msaitoh 	}
   14224  1.281   msaitoh 
   14225  1.281   msaitoh 	/* Disable GigE link negotiation */
   14226  1.281   msaitoh 	reg = CSR_READ(sc, WMREG_PHY_CTRL);
   14227  1.281   msaitoh 	reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
   14228  1.281   msaitoh 	CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
   14229  1.281   msaitoh 
   14230  1.281   msaitoh 	/*
   14231  1.281   msaitoh 	 * Call gig speed drop workaround on Gig disable before accessing
   14232  1.281   msaitoh 	 * any PHY registers.
   14233  1.281   msaitoh 	 */
   14234  1.281   msaitoh 	wm_gig_downshift_workaround_ich8lan(sc);
   14235  1.281   msaitoh 
   14236  1.281   msaitoh out:
   14237  1.281   msaitoh 	return;
   14238  1.281   msaitoh }
   14239  1.281   msaitoh 
   14240  1.281   msaitoh /* WOL from S5 stops working */
   14241  1.281   msaitoh static void
   14242  1.281   msaitoh wm_gig_downshift_workaround_ich8lan(struct wm_softc *sc)
   14243  1.281   msaitoh {
   14244  1.531   msaitoh 	uint16_t kmreg;
   14245  1.281   msaitoh 
   14246  1.281   msaitoh 	/* Only for igp3 */
   14247  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_IGP_3) {
   14248  1.531   msaitoh 		if (wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_DIAG, &kmreg) != 0)
   14249  1.531   msaitoh 			return;
   14250  1.531   msaitoh 		kmreg |= KUMCTRLSTA_DIAG_NELPBK;
   14251  1.531   msaitoh 		if (wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmreg) != 0)
   14252  1.531   msaitoh 			return;
   14253  1.531   msaitoh 		kmreg &= ~KUMCTRLSTA_DIAG_NELPBK;
   14254  1.531   msaitoh 		wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmreg);
   14255  1.281   msaitoh 	}
   14256  1.281   msaitoh }
   14257  1.281   msaitoh 
   14258  1.281   msaitoh /*
   14259  1.281   msaitoh  * Workaround for pch's PHYs
   14260  1.281   msaitoh  * XXX should be moved to new PHY driver?
   14261  1.281   msaitoh  */
   14262  1.281   msaitoh static void
   14263  1.281   msaitoh wm_hv_phy_workaround_ich8lan(struct wm_softc *sc)
   14264  1.281   msaitoh {
   14265  1.420   msaitoh 
   14266  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14267  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   14268  1.420   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH);
   14269  1.420   msaitoh 
   14270  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_82577)
   14271  1.281   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   14272  1.281   msaitoh 
   14273  1.281   msaitoh 	/* (PCH rev.2) && (82577 && (phy rev 2 or 3)) */
   14274  1.281   msaitoh 
   14275  1.281   msaitoh 	/* (82577 && (phy rev 1 or 2)) || (82578 & phy rev 1)*/
   14276  1.281   msaitoh 
   14277  1.281   msaitoh 	/* 82578 */
   14278  1.281   msaitoh 	if (sc->sc_phytype == WMPHY_82578) {
   14279  1.430   msaitoh 		struct mii_softc *child;
   14280  1.430   msaitoh 
   14281  1.430   msaitoh 		/*
   14282  1.430   msaitoh 		 * Return registers to default by doing a soft reset then
   14283  1.430   msaitoh 		 * writing 0x3140 to the control register
   14284  1.430   msaitoh 		 * 0x3140 == BMCR_SPEED0 | BMCR_AUTOEN | BMCR_FDX | BMCR_SPEED1
   14285  1.430   msaitoh 		 */
   14286  1.430   msaitoh 		child = LIST_FIRST(&sc->sc_mii.mii_phys);
   14287  1.430   msaitoh 		if ((child != NULL) && (child->mii_mpd_rev < 2)) {
   14288  1.430   msaitoh 			PHY_RESET(child);
   14289  1.430   msaitoh 			sc->sc_mii.mii_writereg(sc->sc_dev, 2, MII_BMCR,
   14290  1.430   msaitoh 			    0x3140);
   14291  1.281   msaitoh 		}
   14292  1.281   msaitoh 	}
   14293  1.281   msaitoh 
   14294  1.281   msaitoh 	/* Select page 0 */
   14295  1.424   msaitoh 	sc->phy.acquire(sc);
   14296  1.424   msaitoh 	wm_gmii_mdic_writereg(sc->sc_dev, 1, MII_IGPHY_PAGE_SELECT, 0);
   14297  1.424   msaitoh 	sc->phy.release(sc);
   14298  1.281   msaitoh 
   14299  1.281   msaitoh 	/*
   14300  1.281   msaitoh 	 * Configure the K1 Si workaround during phy reset assuming there is
   14301  1.281   msaitoh 	 * link so that it disables K1 if link is in 1Gbps.
   14302  1.281   msaitoh 	 */
   14303  1.281   msaitoh 	wm_k1_gig_workaround_hv(sc, 1);
   14304  1.281   msaitoh }
   14305  1.281   msaitoh 
   14306  1.281   msaitoh static void
   14307  1.281   msaitoh wm_lv_phy_workaround_ich8lan(struct wm_softc *sc)
   14308  1.281   msaitoh {
   14309  1.281   msaitoh 
   14310  1.430   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14311  1.430   msaitoh 		device_xname(sc->sc_dev), __func__));
   14312  1.420   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH2);
   14313  1.420   msaitoh 
   14314  1.281   msaitoh 	wm_set_mdio_slow_mode_hv(sc);
   14315  1.281   msaitoh }
   14316  1.281   msaitoh 
   14317  1.424   msaitoh static int
   14318  1.281   msaitoh wm_k1_gig_workaround_hv(struct wm_softc *sc, int link)
   14319  1.281   msaitoh {
   14320  1.281   msaitoh 	int k1_enable = sc->sc_nvm_k1_enabled;
   14321  1.281   msaitoh 
   14322  1.420   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14323  1.420   msaitoh 		device_xname(sc->sc_dev), __func__));
   14324  1.420   msaitoh 
   14325  1.424   msaitoh 	if (sc->phy.acquire(sc) != 0)
   14326  1.424   msaitoh 		return -1;
   14327  1.281   msaitoh 
   14328  1.281   msaitoh 	if (link) {
   14329  1.281   msaitoh 		k1_enable = 0;
   14330  1.281   msaitoh 
   14331  1.281   msaitoh 		/* Link stall fix for link up */
   14332  1.573   msaitoh 		wm_gmii_hv_writereg_locked(sc->sc_dev, 1, IGP3_KMRN_DIAG,
   14333  1.573   msaitoh 		    0x0100);
   14334  1.281   msaitoh 	} else {
   14335  1.281   msaitoh 		/* Link stall fix for link down */
   14336  1.573   msaitoh 		wm_gmii_hv_writereg_locked(sc->sc_dev, 1, IGP3_KMRN_DIAG,
   14337  1.573   msaitoh 		    0x4100);
   14338  1.281   msaitoh 	}
   14339  1.281   msaitoh 
   14340  1.281   msaitoh 	wm_configure_k1_ich8lan(sc, k1_enable);
   14341  1.424   msaitoh 	sc->phy.release(sc);
   14342  1.281   msaitoh 
   14343  1.424   msaitoh 	return 0;
   14344  1.281   msaitoh }
   14345  1.281   msaitoh 
   14346  1.281   msaitoh static void
   14347  1.281   msaitoh wm_set_mdio_slow_mode_hv(struct wm_softc *sc)
   14348  1.281   msaitoh {
   14349  1.281   msaitoh 	uint32_t reg;
   14350  1.281   msaitoh 
   14351  1.281   msaitoh 	reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL);
   14352  1.281   msaitoh 	wm_gmii_hv_writereg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL,
   14353  1.281   msaitoh 	    reg | HV_KMRN_MDIO_SLOW);
   14354  1.281   msaitoh }
   14355  1.281   msaitoh 
   14356  1.281   msaitoh static void
   14357  1.281   msaitoh wm_configure_k1_ich8lan(struct wm_softc *sc, int k1_enable)
   14358  1.281   msaitoh {
   14359  1.281   msaitoh 	uint32_t ctrl, ctrl_ext, tmp;
   14360  1.531   msaitoh 	uint16_t kmreg;
   14361  1.531   msaitoh 	int rv;
   14362  1.281   msaitoh 
   14363  1.531   msaitoh 	rv = wm_kmrn_readreg_locked(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, &kmreg);
   14364  1.531   msaitoh 	if (rv != 0)
   14365  1.531   msaitoh 		return;
   14366  1.281   msaitoh 
   14367  1.281   msaitoh 	if (k1_enable)
   14368  1.531   msaitoh 		kmreg |= KUMCTRLSTA_K1_ENABLE;
   14369  1.281   msaitoh 	else
   14370  1.531   msaitoh 		kmreg &= ~KUMCTRLSTA_K1_ENABLE;
   14371  1.281   msaitoh 
   14372  1.531   msaitoh 	rv = wm_kmrn_writereg_locked(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, kmreg);
   14373  1.531   msaitoh 	if (rv != 0)
   14374  1.531   msaitoh 		return;
   14375  1.281   msaitoh 
   14376  1.281   msaitoh 	delay(20);
   14377  1.281   msaitoh 
   14378  1.281   msaitoh 	ctrl = CSR_READ(sc, WMREG_CTRL);
   14379  1.281   msaitoh 	ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
   14380  1.281   msaitoh 
   14381  1.281   msaitoh 	tmp = ctrl & ~(CTRL_SPEED_1000 | CTRL_SPEED_100);
   14382  1.281   msaitoh 	tmp |= CTRL_FRCSPD;
   14383  1.281   msaitoh 
   14384  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, tmp);
   14385  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_SPD_BYPS);
   14386  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   14387  1.281   msaitoh 	delay(20);
   14388  1.281   msaitoh 
   14389  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, ctrl);
   14390  1.281   msaitoh 	CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
   14391  1.281   msaitoh 	CSR_WRITE_FLUSH(sc);
   14392  1.281   msaitoh 	delay(20);
   14393  1.531   msaitoh 
   14394  1.531   msaitoh 	return;
   14395  1.281   msaitoh }
   14396  1.281   msaitoh 
   14397  1.281   msaitoh /* special case - for 82575 - need to do manual init ... */
   14398  1.281   msaitoh static void
   14399  1.281   msaitoh wm_reset_init_script_82575(struct wm_softc *sc)
   14400  1.281   msaitoh {
   14401  1.281   msaitoh 	/*
   14402  1.281   msaitoh 	 * remark: this is untested code - we have no board without EEPROM
   14403  1.312   msaitoh 	 *  same setup as mentioned int the FreeBSD driver for the i82575
   14404  1.281   msaitoh 	 */
   14405  1.281   msaitoh 
   14406  1.281   msaitoh 	/* SerDes configuration via SERDESCTRL */
   14407  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x00, 0x0c);
   14408  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x01, 0x78);
   14409  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x1b, 0x23);
   14410  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x23, 0x15);
   14411  1.281   msaitoh 
   14412  1.281   msaitoh 	/* CCM configuration via CCMCTL register */
   14413  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x14, 0x00);
   14414  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x10, 0x00);
   14415  1.281   msaitoh 
   14416  1.281   msaitoh 	/* PCIe lanes configuration */
   14417  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x00, 0xec);
   14418  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x61, 0xdf);
   14419  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x34, 0x05);
   14420  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x2f, 0x81);
   14421  1.281   msaitoh 
   14422  1.281   msaitoh 	/* PCIe PLL Configuration */
   14423  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x02, 0x47);
   14424  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x14, 0x00);
   14425  1.281   msaitoh 	wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x10, 0x00);
   14426  1.281   msaitoh }
   14427  1.325   msaitoh 
   14428  1.325   msaitoh static void
   14429  1.325   msaitoh wm_reset_mdicnfg_82580(struct wm_softc *sc)
   14430  1.325   msaitoh {
   14431  1.325   msaitoh 	uint32_t reg;
   14432  1.325   msaitoh 	uint16_t nvmword;
   14433  1.325   msaitoh 	int rv;
   14434  1.325   msaitoh 
   14435  1.566   msaitoh 	if (sc->sc_type != WM_T_82580)
   14436  1.566   msaitoh 		return;
   14437  1.325   msaitoh 	if ((sc->sc_flags & WM_F_SGMII) == 0)
   14438  1.325   msaitoh 		return;
   14439  1.325   msaitoh 
   14440  1.325   msaitoh 	rv = wm_nvm_read(sc, NVM_OFF_LAN_FUNC_82580(sc->sc_funcid)
   14441  1.325   msaitoh 	    + NVM_OFF_CFG3_PORTA, 1, &nvmword);
   14442  1.325   msaitoh 	if (rv != 0) {
   14443  1.325   msaitoh 		aprint_error_dev(sc->sc_dev, "%s: failed to read NVM\n",
   14444  1.325   msaitoh 		    __func__);
   14445  1.325   msaitoh 		return;
   14446  1.325   msaitoh 	}
   14447  1.325   msaitoh 
   14448  1.325   msaitoh 	reg = CSR_READ(sc, WMREG_MDICNFG);
   14449  1.325   msaitoh 	if (nvmword & NVM_CFG3_PORTA_EXT_MDIO)
   14450  1.325   msaitoh 		reg |= MDICNFG_DEST;
   14451  1.325   msaitoh 	if (nvmword & NVM_CFG3_PORTA_COM_MDIO)
   14452  1.325   msaitoh 		reg |= MDICNFG_COM_MDIO;
   14453  1.325   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, reg);
   14454  1.325   msaitoh }
   14455  1.329   msaitoh 
   14456  1.447   msaitoh #define MII_INVALIDID(x)	(((x) == 0x0000) || ((x) == 0xffff))
   14457  1.447   msaitoh 
   14458  1.447   msaitoh static bool
   14459  1.447   msaitoh wm_phy_is_accessible_pchlan(struct wm_softc *sc)
   14460  1.447   msaitoh {
   14461  1.447   msaitoh 	int i;
   14462  1.447   msaitoh 	uint32_t reg;
   14463  1.447   msaitoh 	uint16_t id1, id2;
   14464  1.447   msaitoh 
   14465  1.447   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14466  1.447   msaitoh 		device_xname(sc->sc_dev), __func__));
   14467  1.447   msaitoh 	id1 = id2 = 0xffff;
   14468  1.447   msaitoh 	for (i = 0; i < 2; i++) {
   14469  1.447   msaitoh 		id1 = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, MII_PHYIDR1);
   14470  1.447   msaitoh 		if (MII_INVALIDID(id1))
   14471  1.447   msaitoh 			continue;
   14472  1.447   msaitoh 		id2 = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, MII_PHYIDR2);
   14473  1.447   msaitoh 		if (MII_INVALIDID(id2))
   14474  1.447   msaitoh 			continue;
   14475  1.447   msaitoh 		break;
   14476  1.447   msaitoh 	}
   14477  1.447   msaitoh 	if (!MII_INVALIDID(id1) && !MII_INVALIDID(id2)) {
   14478  1.447   msaitoh 		goto out;
   14479  1.447   msaitoh 	}
   14480  1.447   msaitoh 
   14481  1.447   msaitoh 	if (sc->sc_type < WM_T_PCH_LPT) {
   14482  1.447   msaitoh 		sc->phy.release(sc);
   14483  1.447   msaitoh 		wm_set_mdio_slow_mode_hv(sc);
   14484  1.447   msaitoh 		id1 = wm_gmii_hv_readreg(sc->sc_dev, 2, MII_PHYIDR1);
   14485  1.447   msaitoh 		id2 = wm_gmii_hv_readreg(sc->sc_dev, 2, MII_PHYIDR2);
   14486  1.447   msaitoh 		sc->phy.acquire(sc);
   14487  1.447   msaitoh 	}
   14488  1.447   msaitoh 	if (MII_INVALIDID(id1) || MII_INVALIDID(id2)) {
   14489  1.447   msaitoh 		printf("XXX return with false\n");
   14490  1.447   msaitoh 		return false;
   14491  1.447   msaitoh 	}
   14492  1.447   msaitoh out:
   14493  1.570   msaitoh 	if (sc->sc_type >= WM_T_PCH_LPT) {
   14494  1.447   msaitoh 		/* Only unforce SMBus if ME is not active */
   14495  1.447   msaitoh 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) == 0) {
   14496  1.447   msaitoh 			/* Unforce SMBus mode in PHY */
   14497  1.447   msaitoh 			reg = wm_gmii_hv_readreg_locked(sc->sc_dev, 2,
   14498  1.447   msaitoh 			    CV_SMB_CTRL);
   14499  1.447   msaitoh 			reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
   14500  1.447   msaitoh 			wm_gmii_hv_writereg_locked(sc->sc_dev, 2,
   14501  1.447   msaitoh 			    CV_SMB_CTRL, reg);
   14502  1.447   msaitoh 
   14503  1.447   msaitoh 			/* Unforce SMBus mode in MAC */
   14504  1.447   msaitoh 			reg = CSR_READ(sc, WMREG_CTRL_EXT);
   14505  1.447   msaitoh 			reg &= ~CTRL_EXT_FORCE_SMBUS;
   14506  1.447   msaitoh 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   14507  1.447   msaitoh 		}
   14508  1.447   msaitoh 	}
   14509  1.447   msaitoh 	return true;
   14510  1.447   msaitoh }
   14511  1.447   msaitoh 
   14512  1.447   msaitoh static void
   14513  1.447   msaitoh wm_toggle_lanphypc_pch_lpt(struct wm_softc *sc)
   14514  1.447   msaitoh {
   14515  1.447   msaitoh 	uint32_t reg;
   14516  1.447   msaitoh 	int i;
   14517  1.447   msaitoh 
   14518  1.447   msaitoh 	/* Set PHY Config Counter to 50msec */
   14519  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM3);
   14520  1.447   msaitoh 	reg &= ~FEXTNVM3_PHY_CFG_COUNTER_MASK;
   14521  1.447   msaitoh 	reg |= FEXTNVM3_PHY_CFG_COUNTER_50MS;
   14522  1.447   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM3, reg);
   14523  1.447   msaitoh 
   14524  1.447   msaitoh 	/* Toggle LANPHYPC */
   14525  1.447   msaitoh 	reg = CSR_READ(sc, WMREG_CTRL);
   14526  1.447   msaitoh 	reg |= CTRL_LANPHYPC_OVERRIDE;
   14527  1.447   msaitoh 	reg &= ~CTRL_LANPHYPC_VALUE;
   14528  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   14529  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   14530  1.447   msaitoh 	delay(1000);
   14531  1.447   msaitoh 	reg &= ~CTRL_LANPHYPC_OVERRIDE;
   14532  1.447   msaitoh 	CSR_WRITE(sc, WMREG_CTRL, reg);
   14533  1.447   msaitoh 	CSR_WRITE_FLUSH(sc);
   14534  1.447   msaitoh 
   14535  1.447   msaitoh 	if (sc->sc_type < WM_T_PCH_LPT)
   14536  1.447   msaitoh 		delay(50 * 1000);
   14537  1.447   msaitoh 	else {
   14538  1.447   msaitoh 		i = 20;
   14539  1.447   msaitoh 
   14540  1.447   msaitoh 		do {
   14541  1.447   msaitoh 			delay(5 * 1000);
   14542  1.447   msaitoh 		} while (((CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_LPCD) == 0)
   14543  1.447   msaitoh 		    && i--);
   14544  1.447   msaitoh 
   14545  1.447   msaitoh 		delay(30 * 1000);
   14546  1.447   msaitoh 	}
   14547  1.447   msaitoh }
   14548  1.447   msaitoh 
   14549  1.445   msaitoh static int
   14550  1.445   msaitoh wm_platform_pm_pch_lpt(struct wm_softc *sc, bool link)
   14551  1.445   msaitoh {
   14552  1.445   msaitoh 	uint32_t reg = __SHIFTIN(link, LTRV_NONSNOOP_REQ)
   14553  1.445   msaitoh 	    | __SHIFTIN(link, LTRV_SNOOP_REQ) | LTRV_SEND;
   14554  1.445   msaitoh 	uint32_t rxa;
   14555  1.445   msaitoh 	uint16_t scale = 0, lat_enc = 0;
   14556  1.517   msaitoh 	int32_t obff_hwm = 0;
   14557  1.445   msaitoh 	int64_t lat_ns, value;
   14558  1.445   msaitoh 
   14559  1.445   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14560  1.445   msaitoh 		device_xname(sc->sc_dev), __func__));
   14561  1.445   msaitoh 
   14562  1.445   msaitoh 	if (link) {
   14563  1.517   msaitoh 		uint16_t max_snoop, max_nosnoop, max_ltr_enc;
   14564  1.517   msaitoh 		uint32_t status;
   14565  1.517   msaitoh 		uint16_t speed;
   14566  1.445   msaitoh 		pcireg_t preg;
   14567  1.445   msaitoh 
   14568  1.517   msaitoh 		status = CSR_READ(sc, WMREG_STATUS);
   14569  1.517   msaitoh 		switch (__SHIFTOUT(status, STATUS_SPEED)) {
   14570  1.517   msaitoh 		case STATUS_SPEED_10:
   14571  1.517   msaitoh 			speed = 10;
   14572  1.517   msaitoh 			break;
   14573  1.517   msaitoh 		case STATUS_SPEED_100:
   14574  1.517   msaitoh 			speed = 100;
   14575  1.517   msaitoh 			break;
   14576  1.517   msaitoh 		case STATUS_SPEED_1000:
   14577  1.517   msaitoh 			speed = 1000;
   14578  1.517   msaitoh 			break;
   14579  1.517   msaitoh 		default:
   14580  1.517   msaitoh 			device_printf(sc->sc_dev, "Unknown speed "
   14581  1.517   msaitoh 			    "(status = %08x)\n", status);
   14582  1.517   msaitoh 			return -1;
   14583  1.517   msaitoh 		}
   14584  1.517   msaitoh 
   14585  1.517   msaitoh 		/* Rx Packet Buffer Allocation size (KB) */
   14586  1.445   msaitoh 		rxa = CSR_READ(sc, WMREG_PBA) & PBA_RXA_MASK;
   14587  1.445   msaitoh 
   14588  1.445   msaitoh 		/*
   14589  1.445   msaitoh 		 * Determine the maximum latency tolerated by the device.
   14590  1.445   msaitoh 		 *
   14591  1.445   msaitoh 		 * Per the PCIe spec, the tolerated latencies are encoded as
   14592  1.445   msaitoh 		 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
   14593  1.445   msaitoh 		 * a 10-bit value (0-1023) to provide a range from 1 ns to
   14594  1.445   msaitoh 		 * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
   14595  1.445   msaitoh 		 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
   14596  1.445   msaitoh 		 */
   14597  1.445   msaitoh 		lat_ns = ((int64_t)rxa * 1024 -
   14598  1.517   msaitoh 		    (2 * ((int64_t)sc->sc_ethercom.ec_if.if_mtu
   14599  1.517   msaitoh 			+ ETHER_HDR_LEN))) * 8 * 1000;
   14600  1.445   msaitoh 		if (lat_ns < 0)
   14601  1.445   msaitoh 			lat_ns = 0;
   14602  1.517   msaitoh 		else
   14603  1.445   msaitoh 			lat_ns /= speed;
   14604  1.445   msaitoh 		value = lat_ns;
   14605  1.445   msaitoh 
   14606  1.445   msaitoh 		while (value > LTRV_VALUE) {
   14607  1.445   msaitoh 			scale ++;
   14608  1.445   msaitoh 			value = howmany(value, __BIT(5));
   14609  1.445   msaitoh 		}
   14610  1.445   msaitoh 		if (scale > LTRV_SCALE_MAX) {
   14611  1.445   msaitoh 			printf("%s: Invalid LTR latency scale %d\n",
   14612  1.445   msaitoh 			    device_xname(sc->sc_dev), scale);
   14613  1.445   msaitoh 			return -1;
   14614  1.445   msaitoh 		}
   14615  1.445   msaitoh 		lat_enc = (uint16_t)(__SHIFTIN(scale, LTRV_SCALE) | value);
   14616  1.445   msaitoh 
   14617  1.511   msaitoh 		/* Determine the maximum latency tolerated by the platform */
   14618  1.445   msaitoh 		preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   14619  1.445   msaitoh 		    WM_PCI_LTR_CAP_LPT);
   14620  1.445   msaitoh 		max_snoop = preg & 0xffff;
   14621  1.445   msaitoh 		max_nosnoop = preg >> 16;
   14622  1.445   msaitoh 
   14623  1.445   msaitoh 		max_ltr_enc = MAX(max_snoop, max_nosnoop);
   14624  1.445   msaitoh 
   14625  1.445   msaitoh 		if (lat_enc > max_ltr_enc) {
   14626  1.445   msaitoh 			lat_enc = max_ltr_enc;
   14627  1.517   msaitoh 			lat_ns = __SHIFTOUT(lat_enc, PCI_LTR_MAXSNOOPLAT_VAL)
   14628  1.517   msaitoh 			    * PCI_LTR_SCALETONS(
   14629  1.517   msaitoh 				    __SHIFTOUT(lat_enc,
   14630  1.517   msaitoh 					PCI_LTR_MAXSNOOPLAT_SCALE));
   14631  1.517   msaitoh 		}
   14632  1.517   msaitoh 
   14633  1.517   msaitoh 		if (lat_ns) {
   14634  1.517   msaitoh 			lat_ns *= speed * 1000;
   14635  1.517   msaitoh 			lat_ns /= 8;
   14636  1.517   msaitoh 			lat_ns /= 1000000000;
   14637  1.517   msaitoh 			obff_hwm = (int32_t)(rxa - lat_ns);
   14638  1.517   msaitoh 		}
   14639  1.517   msaitoh 		if ((obff_hwm < 0) || (obff_hwm > SVT_OFF_HWM)) {
   14640  1.517   msaitoh 			device_printf(sc->sc_dev, "Invalid high water mark %d"
   14641  1.517   msaitoh 			    "(rxa = %d, lat_ns = %d)\n",
   14642  1.517   msaitoh 			    obff_hwm, (int32_t)rxa, (int32_t)lat_ns);
   14643  1.517   msaitoh 			return -1;
   14644  1.445   msaitoh 		}
   14645  1.445   msaitoh 	}
   14646  1.445   msaitoh 	/* Snoop and No-Snoop latencies the same */
   14647  1.445   msaitoh 	reg |= lat_enc | __SHIFTIN(lat_enc, LTRV_NONSNOOP);
   14648  1.445   msaitoh 	CSR_WRITE(sc, WMREG_LTRV, reg);
   14649  1.445   msaitoh 
   14650  1.517   msaitoh 	/* Set OBFF high water mark */
   14651  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_SVT) & ~SVT_OFF_HWM;
   14652  1.517   msaitoh 	reg |= obff_hwm;
   14653  1.517   msaitoh 	CSR_WRITE(sc, WMREG_SVT, reg);
   14654  1.517   msaitoh 
   14655  1.517   msaitoh 	/* Enable OBFF */
   14656  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_SVCR);
   14657  1.517   msaitoh 	reg |= SVCR_OFF_EN | SVCR_OFF_MASKINT;
   14658  1.517   msaitoh 	CSR_WRITE(sc, WMREG_SVCR, reg);
   14659  1.517   msaitoh 
   14660  1.445   msaitoh 	return 0;
   14661  1.445   msaitoh }
   14662  1.445   msaitoh 
   14663  1.329   msaitoh /*
   14664  1.329   msaitoh  * I210 Errata 25 and I211 Errata 10
   14665  1.329   msaitoh  * Slow System Clock.
   14666  1.329   msaitoh  */
   14667  1.329   msaitoh static void
   14668  1.329   msaitoh wm_pll_workaround_i210(struct wm_softc *sc)
   14669  1.329   msaitoh {
   14670  1.329   msaitoh 	uint32_t mdicnfg, wuc;
   14671  1.329   msaitoh 	uint32_t reg;
   14672  1.329   msaitoh 	pcireg_t pcireg;
   14673  1.329   msaitoh 	uint32_t pmreg;
   14674  1.329   msaitoh 	uint16_t nvmword, tmp_nvmword;
   14675  1.329   msaitoh 	int phyval;
   14676  1.329   msaitoh 	bool wa_done = false;
   14677  1.329   msaitoh 	int i;
   14678  1.329   msaitoh 
   14679  1.329   msaitoh 	/* Save WUC and MDICNFG registers */
   14680  1.329   msaitoh 	wuc = CSR_READ(sc, WMREG_WUC);
   14681  1.329   msaitoh 	mdicnfg = CSR_READ(sc, WMREG_MDICNFG);
   14682  1.329   msaitoh 
   14683  1.329   msaitoh 	reg = mdicnfg & ~MDICNFG_DEST;
   14684  1.329   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, reg);
   14685  1.329   msaitoh 
   14686  1.329   msaitoh 	if (wm_nvm_read(sc, INVM_AUTOLOAD, 1, &nvmword) != 0)
   14687  1.329   msaitoh 		nvmword = INVM_DEFAULT_AL;
   14688  1.329   msaitoh 	tmp_nvmword = nvmword | INVM_PLL_WO_VAL;
   14689  1.329   msaitoh 
   14690  1.329   msaitoh 	/* Get Power Management cap offset */
   14691  1.329   msaitoh 	if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT,
   14692  1.329   msaitoh 		&pmreg, NULL) == 0)
   14693  1.329   msaitoh 		return;
   14694  1.329   msaitoh 	for (i = 0; i < WM_MAX_PLL_TRIES; i++) {
   14695  1.329   msaitoh 		phyval = wm_gmii_gs40g_readreg(sc->sc_dev, 1,
   14696  1.329   msaitoh 		    GS40G_PHY_PLL_FREQ_PAGE | GS40G_PHY_PLL_FREQ_REG);
   14697  1.332   msaitoh 
   14698  1.329   msaitoh 		if ((phyval & GS40G_PHY_PLL_UNCONF) != GS40G_PHY_PLL_UNCONF) {
   14699  1.329   msaitoh 			break; /* OK */
   14700  1.329   msaitoh 		}
   14701  1.329   msaitoh 
   14702  1.329   msaitoh 		wa_done = true;
   14703  1.329   msaitoh 		/* Directly reset the internal PHY */
   14704  1.329   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL);
   14705  1.329   msaitoh 		CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);
   14706  1.329   msaitoh 
   14707  1.329   msaitoh 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   14708  1.329   msaitoh 		reg |= CTRL_EXT_PHYPDEN | CTRL_EXT_SDLPE;
   14709  1.329   msaitoh 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   14710  1.329   msaitoh 
   14711  1.329   msaitoh 		CSR_WRITE(sc, WMREG_WUC, 0);
   14712  1.329   msaitoh 		reg = (INVM_AUTOLOAD << 4) | (tmp_nvmword << 16);
   14713  1.329   msaitoh 		CSR_WRITE(sc, WMREG_EEARBC_I210, reg);
   14714  1.332   msaitoh 
   14715  1.329   msaitoh 		pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
   14716  1.329   msaitoh 		    pmreg + PCI_PMCSR);
   14717  1.329   msaitoh 		pcireg |= PCI_PMCSR_STATE_D3;
   14718  1.329   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   14719  1.329   msaitoh 		    pmreg + PCI_PMCSR, pcireg);
   14720  1.329   msaitoh 		delay(1000);
   14721  1.329   msaitoh 		pcireg &= ~PCI_PMCSR_STATE_D3;
   14722  1.329   msaitoh 		pci_conf_write(sc->sc_pc, sc->sc_pcitag,
   14723  1.329   msaitoh 		    pmreg + PCI_PMCSR, pcireg);
   14724  1.329   msaitoh 
   14725  1.329   msaitoh 		reg = (INVM_AUTOLOAD << 4) | (nvmword << 16);
   14726  1.329   msaitoh 		CSR_WRITE(sc, WMREG_EEARBC_I210, reg);
   14727  1.332   msaitoh 
   14728  1.329   msaitoh 		/* Restore WUC register */
   14729  1.329   msaitoh 		CSR_WRITE(sc, WMREG_WUC, wuc);
   14730  1.329   msaitoh 	}
   14731  1.332   msaitoh 
   14732  1.329   msaitoh 	/* Restore MDICNFG setting */
   14733  1.329   msaitoh 	CSR_WRITE(sc, WMREG_MDICNFG, mdicnfg);
   14734  1.329   msaitoh 	if (wa_done)
   14735  1.329   msaitoh 		aprint_verbose_dev(sc->sc_dev, "I210 workaround done\n");
   14736  1.329   msaitoh }
   14737  1.517   msaitoh 
   14738  1.517   msaitoh static void
   14739  1.517   msaitoh wm_legacy_irq_quirk_spt(struct wm_softc *sc)
   14740  1.517   msaitoh {
   14741  1.517   msaitoh 	uint32_t reg;
   14742  1.517   msaitoh 
   14743  1.517   msaitoh 	DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
   14744  1.517   msaitoh 		device_xname(sc->sc_dev), __func__));
   14745  1.517   msaitoh 	KASSERT(sc->sc_type == WM_T_PCH_SPT);
   14746  1.517   msaitoh 
   14747  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM7);
   14748  1.517   msaitoh 	reg |= FEXTNVM7_SIDE_CLK_UNGATE;
   14749  1.517   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM7, reg);
   14750  1.517   msaitoh 
   14751  1.517   msaitoh 	reg = CSR_READ(sc, WMREG_FEXTNVM9);
   14752  1.517   msaitoh 	reg |= FEXTNVM9_IOSFSB_CLKGATE_DIS | FEXTNVM9_IOSFSB_CLKREQ_DIS;
   14753  1.517   msaitoh 	CSR_WRITE(sc, WMREG_FEXTNVM9, reg);
   14754  1.517   msaitoh }
   14755