if_wm.c revision 1.100
1 /* $NetBSD: if_wm.c,v 1.100 2005/03/11 17:07:51 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.100 2005/03/11 17:07:51 matt Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 280 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 281 282 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 283 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 284 285 struct evcnt sc_ev_tu; /* Tx underrun */ 286 287 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 288 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 289 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 290 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 291 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 292 #endif /* WM_EVENT_COUNTERS */ 293 294 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 295 296 int sc_txfree; /* number of free Tx descriptors */ 297 int sc_txnext; /* next ready Tx descriptor */ 298 299 int sc_txsfree; /* number of free Tx jobs */ 300 int sc_txsnext; /* next free Tx job */ 301 int sc_txsdirty; /* dirty Tx jobs */ 302 303 /* These 5 variables are used only on the 82547. */ 304 int sc_txfifo_size; /* Tx FIFO size */ 305 int sc_txfifo_head; /* current head of FIFO */ 306 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 307 int sc_txfifo_stall; /* Tx FIFO is stalled */ 308 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 309 310 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 311 312 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 313 int sc_rxdiscard; 314 int sc_rxlen; 315 struct mbuf *sc_rxhead; 316 struct mbuf *sc_rxtail; 317 struct mbuf **sc_rxtailp; 318 319 uint32_t sc_ctrl; /* prototype CTRL register */ 320 #if 0 321 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 322 #endif 323 uint32_t sc_icr; /* prototype interrupt bits */ 324 uint32_t sc_itr; /* prototype intr throttling reg */ 325 uint32_t sc_tctl; /* prototype TCTL register */ 326 uint32_t sc_rctl; /* prototype RCTL register */ 327 uint32_t sc_txcw; /* prototype TXCW register */ 328 uint32_t sc_tipg; /* prototype TIPG register */ 329 uint32_t sc_fcrtl; /* prototype FCRTL register */ 330 uint32_t sc_pba; /* prototype PBA register */ 331 332 int sc_tbi_linkup; /* TBI link status */ 333 int sc_tbi_anstate; /* autonegotiation state */ 334 335 int sc_mchash_type; /* multicast filter offset */ 336 337 #if NRND > 0 338 rndsource_element_t rnd_source; /* random source */ 339 #endif 340 }; 341 342 #define WM_RXCHAIN_RESET(sc) \ 343 do { \ 344 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 345 *(sc)->sc_rxtailp = NULL; \ 346 (sc)->sc_rxlen = 0; \ 347 } while (/*CONSTCOND*/0) 348 349 #define WM_RXCHAIN_LINK(sc, m) \ 350 do { \ 351 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 352 (sc)->sc_rxtailp = &(m)->m_next; \ 353 } while (/*CONSTCOND*/0) 354 355 /* sc_flags */ 356 #define WM_F_HAS_MII 0x01 /* has MII */ 357 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 358 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 359 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 360 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 361 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 362 #define WM_F_CSA 0x80 /* bus is CSA */ 363 364 #ifdef WM_EVENT_COUNTERS 365 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 366 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 367 #else 368 #define WM_EVCNT_INCR(ev) /* nothing */ 369 #define WM_EVCNT_ADD(ev, val) /* nothing */ 370 #endif 371 372 #define CSR_READ(sc, reg) \ 373 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 374 #define CSR_WRITE(sc, reg, val) \ 375 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 376 #define CSR_WRITE_FLUSH(sc) \ 377 (void) CSR_READ((sc), WMREG_STATUS) 378 379 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 380 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 381 382 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 383 #define WM_CDTXADDR_HI(sc, x) \ 384 (sizeof(bus_addr_t) == 8 ? \ 385 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 386 387 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 388 #define WM_CDRXADDR_HI(sc, x) \ 389 (sizeof(bus_addr_t) == 8 ? \ 390 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 391 392 #define WM_CDTXSYNC(sc, x, n, ops) \ 393 do { \ 394 int __x, __n; \ 395 \ 396 __x = (x); \ 397 __n = (n); \ 398 \ 399 /* If it will wrap around, sync to the end of the ring. */ \ 400 if ((__x + __n) > WM_NTXDESC(sc)) { \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 403 (WM_NTXDESC(sc) - __x), (ops)); \ 404 __n -= (WM_NTXDESC(sc) - __x); \ 405 __x = 0; \ 406 } \ 407 \ 408 /* Now sync whatever is left. */ \ 409 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 410 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 411 } while (/*CONSTCOND*/0) 412 413 #define WM_CDRXSYNC(sc, x, ops) \ 414 do { \ 415 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 416 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 417 } while (/*CONSTCOND*/0) 418 419 #define WM_INIT_RXDESC(sc, x) \ 420 do { \ 421 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 422 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 423 struct mbuf *__m = __rxs->rxs_mbuf; \ 424 \ 425 /* \ 426 * Note: We scoot the packet forward 2 bytes in the buffer \ 427 * so that the payload after the Ethernet header is aligned \ 428 * to a 4-byte boundary. \ 429 * \ 430 * XXX BRAINDAMAGE ALERT! \ 431 * The stupid chip uses the same size for every buffer, which \ 432 * is set in the Receive Control register. We are using the 2K \ 433 * size option, but what we REALLY want is (2K - 2)! For this \ 434 * reason, we can't "scoot" packets longer than the standard \ 435 * Ethernet MTU. On strict-alignment platforms, if the total \ 436 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 437 * the upper layer copy the headers. \ 438 */ \ 439 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 440 \ 441 wm_set_dma_addr(&__rxd->wrx_addr, \ 442 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 443 __rxd->wrx_len = 0; \ 444 __rxd->wrx_cksum = 0; \ 445 __rxd->wrx_status = 0; \ 446 __rxd->wrx_errors = 0; \ 447 __rxd->wrx_special = 0; \ 448 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 449 \ 450 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 451 } while (/*CONSTCOND*/0) 452 453 static void wm_start(struct ifnet *); 454 static void wm_watchdog(struct ifnet *); 455 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 456 static int wm_init(struct ifnet *); 457 static void wm_stop(struct ifnet *, int); 458 459 static void wm_shutdown(void *); 460 461 static void wm_reset(struct wm_softc *); 462 static void wm_rxdrain(struct wm_softc *); 463 static int wm_add_rxbuf(struct wm_softc *, int); 464 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 465 static void wm_tick(void *); 466 467 static void wm_set_filter(struct wm_softc *); 468 469 static int wm_intr(void *); 470 static void wm_txintr(struct wm_softc *); 471 static void wm_rxintr(struct wm_softc *); 472 static void wm_linkintr(struct wm_softc *, uint32_t); 473 474 static void wm_tbi_mediainit(struct wm_softc *); 475 static int wm_tbi_mediachange(struct ifnet *); 476 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 477 478 static void wm_tbi_set_linkled(struct wm_softc *); 479 static void wm_tbi_check_link(struct wm_softc *); 480 481 static void wm_gmii_reset(struct wm_softc *); 482 483 static int wm_gmii_i82543_readreg(struct device *, int, int); 484 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 485 486 static int wm_gmii_i82544_readreg(struct device *, int, int); 487 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 488 489 static void wm_gmii_statchg(struct device *); 490 491 static void wm_gmii_mediainit(struct wm_softc *); 492 static int wm_gmii_mediachange(struct ifnet *); 493 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 494 495 static int wm_match(struct device *, struct cfdata *, void *); 496 static void wm_attach(struct device *, struct device *, void *); 497 498 CFATTACH_DECL(wm, sizeof(struct wm_softc), 499 wm_match, wm_attach, NULL, NULL); 500 501 static void wm_82547_txfifo_stall(void *); 502 503 /* 504 * Devices supported by this driver. 505 */ 506 static const struct wm_product { 507 pci_vendor_id_t wmp_vendor; 508 pci_product_id_t wmp_product; 509 const char *wmp_name; 510 wm_chip_type wmp_type; 511 int wmp_flags; 512 #define WMP_F_1000X 0x01 513 #define WMP_F_1000T 0x02 514 } wm_products[] = { 515 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 516 "Intel i82542 1000BASE-X Ethernet", 517 WM_T_82542_2_1, WMP_F_1000X }, 518 519 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 520 "Intel i82543GC 1000BASE-X Ethernet", 521 WM_T_82543, WMP_F_1000X }, 522 523 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 524 "Intel i82543GC 1000BASE-T Ethernet", 525 WM_T_82543, WMP_F_1000T }, 526 527 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 528 "Intel i82544EI 1000BASE-T Ethernet", 529 WM_T_82544, WMP_F_1000T }, 530 531 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 532 "Intel i82544EI 1000BASE-X Ethernet", 533 WM_T_82544, WMP_F_1000X }, 534 535 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 536 "Intel i82544GC 1000BASE-T Ethernet", 537 WM_T_82544, WMP_F_1000T }, 538 539 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 540 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 541 WM_T_82544, WMP_F_1000T }, 542 543 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 544 "Intel i82540EM 1000BASE-T Ethernet", 545 WM_T_82540, WMP_F_1000T }, 546 547 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 548 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 549 WM_T_82540, WMP_F_1000T }, 550 551 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 552 "Intel i82540EP 1000BASE-T Ethernet", 553 WM_T_82540, WMP_F_1000T }, 554 555 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 556 "Intel i82540EP 1000BASE-T Ethernet", 557 WM_T_82540, WMP_F_1000T }, 558 559 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 560 "Intel i82540EP 1000BASE-T Ethernet", 561 WM_T_82540, WMP_F_1000T }, 562 563 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 564 "Intel i82545EM 1000BASE-T Ethernet", 565 WM_T_82545, WMP_F_1000T }, 566 567 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 568 "Intel i82545GM 1000BASE-T Ethernet", 569 WM_T_82545_3, WMP_F_1000T }, 570 571 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 572 "Intel i82545GM 1000BASE-X Ethernet", 573 WM_T_82545_3, WMP_F_1000X }, 574 #if 0 575 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 576 "Intel i82545GM Gigabit Ethernet (SERDES)", 577 WM_T_82545_3, WMP_F_SERDES }, 578 #endif 579 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 580 "Intel i82546EB 1000BASE-T Ethernet", 581 WM_T_82546, WMP_F_1000T }, 582 583 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 584 "Intel i82546EB 1000BASE-T Ethernet", 585 WM_T_82546, WMP_F_1000T }, 586 587 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 588 "Intel i82545EM 1000BASE-X Ethernet", 589 WM_T_82545, WMP_F_1000X }, 590 591 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 592 "Intel i82546EB 1000BASE-X Ethernet", 593 WM_T_82546, WMP_F_1000X }, 594 595 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 596 "Intel i82546GB 1000BASE-T Ethernet", 597 WM_T_82546_3, WMP_F_1000T }, 598 599 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 600 "Intel i82546GB 1000BASE-X Ethernet", 601 WM_T_82546_3, WMP_F_1000X }, 602 #if 0 603 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 604 "Intel i82546GB Gigabit Ethernet (SERDES)", 605 WM_T_82546_3, WMP_F_SERDES }, 606 #endif 607 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 608 "Intel i82541EI 1000BASE-T Ethernet", 609 WM_T_82541, WMP_F_1000T }, 610 611 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 612 "Intel i82541EI Mobile 1000BASE-T Ethernet", 613 WM_T_82541, WMP_F_1000T }, 614 615 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 616 "Intel i82541ER 1000BASE-T Ethernet", 617 WM_T_82541_2, WMP_F_1000T }, 618 619 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 620 "Intel i82541GI 1000BASE-T Ethernet", 621 WM_T_82541_2, WMP_F_1000T }, 622 623 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 624 "Intel i82541GI Mobile 1000BASE-T Ethernet", 625 WM_T_82541_2, WMP_F_1000T }, 626 627 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 628 "Intel i82547EI 1000BASE-T Ethernet", 629 WM_T_82547, WMP_F_1000T }, 630 631 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 632 "Intel i82547GI 1000BASE-T Ethernet", 633 WM_T_82547_2, WMP_F_1000T }, 634 { 0, 0, 635 NULL, 636 0, 0 }, 637 }; 638 639 #ifdef WM_EVENT_COUNTERS 640 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 641 #endif /* WM_EVENT_COUNTERS */ 642 643 #if 0 /* Not currently used */ 644 static __inline uint32_t 645 wm_io_read(struct wm_softc *sc, int reg) 646 { 647 648 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 649 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 650 } 651 #endif 652 653 static __inline void 654 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 655 { 656 657 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 658 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 659 } 660 661 static __inline void 662 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 663 { 664 wa->wa_low = htole32(v & 0xffffffffU); 665 if (sizeof(bus_addr_t) == 8) 666 wa->wa_high = htole32((uint64_t) v >> 32); 667 else 668 wa->wa_high = 0; 669 } 670 671 static const struct wm_product * 672 wm_lookup(const struct pci_attach_args *pa) 673 { 674 const struct wm_product *wmp; 675 676 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 677 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 678 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 679 return (wmp); 680 } 681 return (NULL); 682 } 683 684 static int 685 wm_match(struct device *parent, struct cfdata *cf, void *aux) 686 { 687 struct pci_attach_args *pa = aux; 688 689 if (wm_lookup(pa) != NULL) 690 return (1); 691 692 return (0); 693 } 694 695 static void 696 wm_attach(struct device *parent, struct device *self, void *aux) 697 { 698 struct wm_softc *sc = (void *) self; 699 struct pci_attach_args *pa = aux; 700 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 701 pci_chipset_tag_t pc = pa->pa_pc; 702 pci_intr_handle_t ih; 703 size_t cdata_size; 704 const char *intrstr = NULL; 705 const char *eetype; 706 bus_space_tag_t memt; 707 bus_space_handle_t memh; 708 bus_dma_segment_t seg; 709 int memh_valid; 710 int i, rseg, error; 711 const struct wm_product *wmp; 712 uint8_t enaddr[ETHER_ADDR_LEN]; 713 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 714 pcireg_t preg, memtype; 715 uint32_t reg; 716 int pmreg; 717 718 callout_init(&sc->sc_tick_ch); 719 720 wmp = wm_lookup(pa); 721 if (wmp == NULL) { 722 printf("\n"); 723 panic("wm_attach: impossible"); 724 } 725 726 if (pci_dma64_available(pa)) 727 sc->sc_dmat = pa->pa_dmat64; 728 else 729 sc->sc_dmat = pa->pa_dmat; 730 731 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 732 aprint_naive(": Ethernet controller\n"); 733 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 734 735 sc->sc_type = wmp->wmp_type; 736 if (sc->sc_type < WM_T_82543) { 737 if (preg < 2) { 738 aprint_error("%s: i82542 must be at least rev. 2\n", 739 sc->sc_dev.dv_xname); 740 return; 741 } 742 if (preg < 3) 743 sc->sc_type = WM_T_82542_2_0; 744 } 745 746 /* 747 * Map the device. All devices support memory-mapped acccess, 748 * and it is really required for normal operation. 749 */ 750 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 751 switch (memtype) { 752 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 753 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 754 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 755 memtype, 0, &memt, &memh, NULL, NULL) == 0); 756 break; 757 default: 758 memh_valid = 0; 759 } 760 761 if (memh_valid) { 762 sc->sc_st = memt; 763 sc->sc_sh = memh; 764 } else { 765 aprint_error("%s: unable to map device registers\n", 766 sc->sc_dev.dv_xname); 767 return; 768 } 769 770 /* 771 * In addition, i82544 and later support I/O mapped indirect 772 * register access. It is not desirable (nor supported in 773 * this driver) to use it for normal operation, though it is 774 * required to work around bugs in some chip versions. 775 */ 776 if (sc->sc_type >= WM_T_82544) { 777 /* First we have to find the I/O BAR. */ 778 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 779 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 780 PCI_MAPREG_TYPE_IO) 781 break; 782 } 783 if (i == PCI_MAPREG_END) 784 aprint_error("%s: WARNING: unable to find I/O BAR\n", 785 sc->sc_dev.dv_xname); 786 else { 787 /* 788 * The i8254x doesn't apparently respond when the 789 * I/O BAR is 0, which looks somewhat like it's not 790 * been configured. 791 */ 792 preg = pci_conf_read(pc, pa->pa_tag, i); 793 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 794 aprint_error("%s: WARNING: I/O BAR at zero.\n", 795 sc->sc_dev.dv_xname); 796 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 797 0, &sc->sc_iot, &sc->sc_ioh, 798 NULL, NULL) == 0) { 799 sc->sc_flags |= WM_F_IOH_VALID; 800 } else { 801 aprint_error("%s: WARNING: unable to map " 802 "I/O space\n", sc->sc_dev.dv_xname); 803 } 804 } 805 806 } 807 808 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 809 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 810 preg |= PCI_COMMAND_MASTER_ENABLE; 811 if (sc->sc_type < WM_T_82542_2_1) 812 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 813 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 814 815 /* Get it out of power save mode, if needed. */ 816 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 817 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 818 PCI_PMCSR_STATE_MASK; 819 if (preg == PCI_PMCSR_STATE_D3) { 820 /* 821 * The card has lost all configuration data in 822 * this state, so punt. 823 */ 824 aprint_error("%s: unable to wake from power state D3\n", 825 sc->sc_dev.dv_xname); 826 return; 827 } 828 if (preg != PCI_PMCSR_STATE_D0) { 829 aprint_normal("%s: waking up from power state D%d\n", 830 sc->sc_dev.dv_xname, preg); 831 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 832 PCI_PMCSR_STATE_D0); 833 } 834 } 835 836 /* 837 * Map and establish our interrupt. 838 */ 839 if (pci_intr_map(pa, &ih)) { 840 aprint_error("%s: unable to map interrupt\n", 841 sc->sc_dev.dv_xname); 842 return; 843 } 844 intrstr = pci_intr_string(pc, ih); 845 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 846 if (sc->sc_ih == NULL) { 847 aprint_error("%s: unable to establish interrupt", 848 sc->sc_dev.dv_xname); 849 if (intrstr != NULL) 850 aprint_normal(" at %s", intrstr); 851 aprint_normal("\n"); 852 return; 853 } 854 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 855 856 /* 857 * Determine a few things about the bus we're connected to. 858 */ 859 if (sc->sc_type < WM_T_82543) { 860 /* We don't really know the bus characteristics here. */ 861 sc->sc_bus_speed = 33; 862 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 863 /* 864 * CSA (Communication Streaming Architecture) is about as fast 865 * a 32-bit 66MHz PCI Bus. 866 */ 867 sc->sc_flags |= WM_F_CSA; 868 sc->sc_bus_speed = 66; 869 aprint_verbose("%s: Communication Streaming Architecture\n", 870 sc->sc_dev.dv_xname); 871 if (sc->sc_type == WM_T_82547) { 872 callout_init(&sc->sc_txfifo_ch); 873 callout_setfunc(&sc->sc_txfifo_ch, 874 wm_82547_txfifo_stall, sc); 875 aprint_verbose("%s: using 82547 Tx FIFO stall " 876 "work-around\n", sc->sc_dev.dv_xname); 877 } 878 } else { 879 reg = CSR_READ(sc, WMREG_STATUS); 880 if (reg & STATUS_BUS64) 881 sc->sc_flags |= WM_F_BUS64; 882 if (sc->sc_type >= WM_T_82544 && 883 (reg & STATUS_PCIX_MODE) != 0) { 884 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 885 886 sc->sc_flags |= WM_F_PCIX; 887 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 888 PCI_CAP_PCIX, 889 &sc->sc_pcix_offset, NULL) == 0) 890 aprint_error("%s: unable to find PCIX " 891 "capability\n", sc->sc_dev.dv_xname); 892 else if (sc->sc_type != WM_T_82545_3 && 893 sc->sc_type != WM_T_82546_3) { 894 /* 895 * Work around a problem caused by the BIOS 896 * setting the max memory read byte count 897 * incorrectly. 898 */ 899 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 900 sc->sc_pcix_offset + PCI_PCIX_CMD); 901 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 902 sc->sc_pcix_offset + PCI_PCIX_STATUS); 903 904 bytecnt = 905 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 906 PCI_PCIX_CMD_BYTECNT_SHIFT; 907 maxb = 908 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 909 PCI_PCIX_STATUS_MAXB_SHIFT; 910 if (bytecnt > maxb) { 911 aprint_verbose("%s: resetting PCI-X " 912 "MMRBC: %d -> %d\n", 913 sc->sc_dev.dv_xname, 914 512 << bytecnt, 512 << maxb); 915 pcix_cmd = (pcix_cmd & 916 ~PCI_PCIX_CMD_BYTECNT_MASK) | 917 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 918 pci_conf_write(pa->pa_pc, pa->pa_tag, 919 sc->sc_pcix_offset + PCI_PCIX_CMD, 920 pcix_cmd); 921 } 922 } 923 } 924 /* 925 * The quad port adapter is special; it has a PCIX-PCIX 926 * bridge on the board, and can run the secondary bus at 927 * a higher speed. 928 */ 929 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 930 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 931 : 66; 932 } else if (sc->sc_flags & WM_F_PCIX) { 933 switch (reg & STATUS_PCIXSPD_MASK) { 934 case STATUS_PCIXSPD_50_66: 935 sc->sc_bus_speed = 66; 936 break; 937 case STATUS_PCIXSPD_66_100: 938 sc->sc_bus_speed = 100; 939 break; 940 case STATUS_PCIXSPD_100_133: 941 sc->sc_bus_speed = 133; 942 break; 943 default: 944 aprint_error( 945 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 946 sc->sc_dev.dv_xname, 947 reg & STATUS_PCIXSPD_MASK); 948 sc->sc_bus_speed = 66; 949 } 950 } else 951 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 952 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 953 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 954 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 955 } 956 957 /* 958 * Allocate the control data structures, and create and load the 959 * DMA map for it. 960 * 961 * NOTE: All Tx descriptors must be in the same 4G segment of 962 * memory. So must Rx descriptors. We simplify by allocating 963 * both sets within the same 4G segment. 964 */ 965 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 966 WM_NTXDESC_82542 : WM_NTXDESC_82544; 967 cdata_size = sc->sc_type < WM_T_82544 ? 968 sizeof(struct wm_control_data_82542) : 969 sizeof(struct wm_control_data_82544); 970 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 971 (bus_size_t) 0x100000000ULL, 972 &seg, 1, &rseg, 0)) != 0) { 973 aprint_error( 974 "%s: unable to allocate control data, error = %d\n", 975 sc->sc_dev.dv_xname, error); 976 goto fail_0; 977 } 978 979 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 980 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 981 aprint_error("%s: unable to map control data, error = %d\n", 982 sc->sc_dev.dv_xname, error); 983 goto fail_1; 984 } 985 986 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 987 0, 0, &sc->sc_cddmamap)) != 0) { 988 aprint_error("%s: unable to create control data DMA map, " 989 "error = %d\n", sc->sc_dev.dv_xname, error); 990 goto fail_2; 991 } 992 993 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 994 sc->sc_control_data, cdata_size, NULL, 995 0)) != 0) { 996 aprint_error( 997 "%s: unable to load control data DMA map, error = %d\n", 998 sc->sc_dev.dv_xname, error); 999 goto fail_3; 1000 } 1001 1002 1003 /* 1004 * Create the transmit buffer DMA maps. 1005 */ 1006 WM_TXQUEUELEN(sc) = 1007 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1008 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1009 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1010 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1011 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1012 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1013 aprint_error("%s: unable to create Tx DMA map %d, " 1014 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1015 goto fail_4; 1016 } 1017 } 1018 1019 /* 1020 * Create the receive buffer DMA maps. 1021 */ 1022 for (i = 0; i < WM_NRXDESC; i++) { 1023 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1024 MCLBYTES, 0, 0, 1025 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1026 aprint_error("%s: unable to create Rx DMA map %d, " 1027 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1028 goto fail_5; 1029 } 1030 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1031 } 1032 1033 /* 1034 * Reset the chip to a known state. 1035 */ 1036 wm_reset(sc); 1037 1038 /* 1039 * Get some information about the EEPROM. 1040 */ 1041 if (sc->sc_type >= WM_T_82540) 1042 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1043 if (sc->sc_type <= WM_T_82544) 1044 sc->sc_ee_addrbits = 6; 1045 else if (sc->sc_type <= WM_T_82546_3) { 1046 reg = CSR_READ(sc, WMREG_EECD); 1047 if (reg & EECD_EE_SIZE) 1048 sc->sc_ee_addrbits = 8; 1049 else 1050 sc->sc_ee_addrbits = 6; 1051 } else if (sc->sc_type <= WM_T_82547_2) { 1052 reg = CSR_READ(sc, WMREG_EECD); 1053 if (reg & EECD_EE_TYPE) { 1054 sc->sc_flags |= WM_F_EEPROM_SPI; 1055 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1056 } else 1057 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1058 } else { 1059 /* Assume everything else is SPI. */ 1060 reg = CSR_READ(sc, WMREG_EECD); 1061 sc->sc_flags |= WM_F_EEPROM_SPI; 1062 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1063 } 1064 if (sc->sc_flags & WM_F_EEPROM_SPI) 1065 eetype = "SPI"; 1066 else 1067 eetype = "MicroWire"; 1068 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1069 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1070 sc->sc_ee_addrbits, eetype); 1071 1072 /* 1073 * Read the Ethernet address from the EEPROM. 1074 */ 1075 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1076 sizeof(myea) / sizeof(myea[0]), myea)) { 1077 aprint_error("%s: unable to read Ethernet address\n", 1078 sc->sc_dev.dv_xname); 1079 return; 1080 } 1081 enaddr[0] = myea[0] & 0xff; 1082 enaddr[1] = myea[0] >> 8; 1083 enaddr[2] = myea[1] & 0xff; 1084 enaddr[3] = myea[1] >> 8; 1085 enaddr[4] = myea[2] & 0xff; 1086 enaddr[5] = myea[2] >> 8; 1087 1088 /* 1089 * Toggle the LSB of the MAC address on the second port 1090 * of the i82546. 1091 */ 1092 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1093 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1094 enaddr[5] ^= 1; 1095 } 1096 1097 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1098 ether_sprintf(enaddr)); 1099 1100 /* 1101 * Read the config info from the EEPROM, and set up various 1102 * bits in the control registers based on their contents. 1103 */ 1104 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1105 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1106 sc->sc_dev.dv_xname); 1107 return; 1108 } 1109 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1110 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1111 sc->sc_dev.dv_xname); 1112 return; 1113 } 1114 if (sc->sc_type >= WM_T_82544) { 1115 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1116 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1117 sc->sc_dev.dv_xname); 1118 return; 1119 } 1120 } 1121 1122 if (cfg1 & EEPROM_CFG1_ILOS) 1123 sc->sc_ctrl |= CTRL_ILOS; 1124 if (sc->sc_type >= WM_T_82544) { 1125 sc->sc_ctrl |= 1126 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1127 CTRL_SWDPIO_SHIFT; 1128 sc->sc_ctrl |= 1129 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1130 CTRL_SWDPINS_SHIFT; 1131 } else { 1132 sc->sc_ctrl |= 1133 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1134 CTRL_SWDPIO_SHIFT; 1135 } 1136 1137 #if 0 1138 if (sc->sc_type >= WM_T_82544) { 1139 if (cfg1 & EEPROM_CFG1_IPS0) 1140 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1141 if (cfg1 & EEPROM_CFG1_IPS1) 1142 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1143 sc->sc_ctrl_ext |= 1144 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1145 CTRL_EXT_SWDPIO_SHIFT; 1146 sc->sc_ctrl_ext |= 1147 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1148 CTRL_EXT_SWDPINS_SHIFT; 1149 } else { 1150 sc->sc_ctrl_ext |= 1151 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1152 CTRL_EXT_SWDPIO_SHIFT; 1153 } 1154 #endif 1155 1156 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1157 #if 0 1158 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1159 #endif 1160 1161 /* 1162 * Set up some register offsets that are different between 1163 * the i82542 and the i82543 and later chips. 1164 */ 1165 if (sc->sc_type < WM_T_82543) { 1166 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1167 sc->sc_tdt_reg = WMREG_OLD_TDT; 1168 } else { 1169 sc->sc_rdt_reg = WMREG_RDT; 1170 sc->sc_tdt_reg = WMREG_TDT; 1171 } 1172 1173 /* 1174 * Determine if we're TBI or GMII mode, and initialize the 1175 * media structures accordingly. 1176 */ 1177 if (sc->sc_type < WM_T_82543 || 1178 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1179 if (wmp->wmp_flags & WMP_F_1000T) 1180 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1181 "product!\n", sc->sc_dev.dv_xname); 1182 wm_tbi_mediainit(sc); 1183 } else { 1184 if (wmp->wmp_flags & WMP_F_1000X) 1185 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1186 "product!\n", sc->sc_dev.dv_xname); 1187 wm_gmii_mediainit(sc); 1188 } 1189 1190 ifp = &sc->sc_ethercom.ec_if; 1191 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1192 ifp->if_softc = sc; 1193 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1194 ifp->if_ioctl = wm_ioctl; 1195 ifp->if_start = wm_start; 1196 ifp->if_watchdog = wm_watchdog; 1197 ifp->if_init = wm_init; 1198 ifp->if_stop = wm_stop; 1199 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1200 IFQ_SET_READY(&ifp->if_snd); 1201 1202 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1203 1204 /* 1205 * If we're a i82543 or greater, we can support VLANs. 1206 */ 1207 if (sc->sc_type >= WM_T_82543) 1208 sc->sc_ethercom.ec_capabilities |= 1209 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1210 1211 /* 1212 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1213 * on i82543 and later. 1214 */ 1215 if (sc->sc_type >= WM_T_82543) 1216 ifp->if_capabilities |= 1217 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1218 1219 /* 1220 * If we're a i82544 or greater (except i82547), we can do 1221 * TCP segmentation offload. 1222 */ 1223 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1224 ifp->if_capabilities |= IFCAP_TSOv4; 1225 1226 /* 1227 * Attach the interface. 1228 */ 1229 if_attach(ifp); 1230 ether_ifattach(ifp, enaddr); 1231 #if NRND > 0 1232 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1233 RND_TYPE_NET, 0); 1234 #endif 1235 1236 #ifdef WM_EVENT_COUNTERS 1237 /* Attach event counters. */ 1238 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1239 NULL, sc->sc_dev.dv_xname, "txsstall"); 1240 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1241 NULL, sc->sc_dev.dv_xname, "txdstall"); 1242 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1243 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1244 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1245 NULL, sc->sc_dev.dv_xname, "txdw"); 1246 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1247 NULL, sc->sc_dev.dv_xname, "txqe"); 1248 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1249 NULL, sc->sc_dev.dv_xname, "rxintr"); 1250 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1251 NULL, sc->sc_dev.dv_xname, "linkintr"); 1252 1253 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1254 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1255 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1256 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1257 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1258 NULL, sc->sc_dev.dv_xname, "txipsum"); 1259 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "txtusum"); 1261 1262 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "txtso"); 1264 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1265 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1266 1267 for (i = 0; i < WM_NTXSEGS; i++) { 1268 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1269 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1270 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1271 } 1272 1273 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "txdrop"); 1275 1276 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1277 NULL, sc->sc_dev.dv_xname, "tu"); 1278 1279 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1280 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1281 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1282 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1283 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1284 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1285 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1287 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1289 #endif /* WM_EVENT_COUNTERS */ 1290 1291 /* 1292 * Make sure the interface is shutdown during reboot. 1293 */ 1294 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1295 if (sc->sc_sdhook == NULL) 1296 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1297 sc->sc_dev.dv_xname); 1298 return; 1299 1300 /* 1301 * Free any resources we've allocated during the failed attach 1302 * attempt. Do this in reverse order and fall through. 1303 */ 1304 fail_5: 1305 for (i = 0; i < WM_NRXDESC; i++) { 1306 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1307 bus_dmamap_destroy(sc->sc_dmat, 1308 sc->sc_rxsoft[i].rxs_dmamap); 1309 } 1310 fail_4: 1311 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1312 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1313 bus_dmamap_destroy(sc->sc_dmat, 1314 sc->sc_txsoft[i].txs_dmamap); 1315 } 1316 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1317 fail_3: 1318 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1319 fail_2: 1320 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1321 cdata_size); 1322 fail_1: 1323 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1324 fail_0: 1325 return; 1326 } 1327 1328 /* 1329 * wm_shutdown: 1330 * 1331 * Make sure the interface is stopped at reboot time. 1332 */ 1333 static void 1334 wm_shutdown(void *arg) 1335 { 1336 struct wm_softc *sc = arg; 1337 1338 wm_stop(&sc->sc_ethercom.ec_if, 1); 1339 } 1340 1341 /* 1342 * wm_tx_offload: 1343 * 1344 * Set up TCP/IP checksumming parameters for the 1345 * specified packet. 1346 */ 1347 static int 1348 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1349 uint8_t *fieldsp) 1350 { 1351 struct mbuf *m0 = txs->txs_mbuf; 1352 struct livengood_tcpip_ctxdesc *t; 1353 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1354 struct ether_header *eh; 1355 int offset, iphl; 1356 uint8_t fields; 1357 1358 /* 1359 * XXX It would be nice if the mbuf pkthdr had offset 1360 * fields for the protocol headers. 1361 */ 1362 1363 eh = mtod(m0, struct ether_header *); 1364 switch (htons(eh->ether_type)) { 1365 case ETHERTYPE_IP: 1366 offset = ETHER_HDR_LEN; 1367 break; 1368 1369 case ETHERTYPE_VLAN: 1370 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1371 break; 1372 1373 default: 1374 /* 1375 * Don't support this protocol or encapsulation. 1376 */ 1377 *fieldsp = 0; 1378 *cmdp = 0; 1379 return (0); 1380 } 1381 1382 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1383 1384 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1385 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1386 seg = 0; 1387 fields = 0; 1388 1389 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1390 int hlen = offset + iphl; 1391 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1392 if (__predict_false(m0->m_len < 1393 (hlen + sizeof(struct tcphdr)))) { 1394 /* 1395 * TCP/IP headers are not in the first mbuf; we need 1396 * to do this the slow and painful way. Let's just 1397 * hope this doesn't happen very often. 1398 */ 1399 struct ip ip; 1400 struct tcphdr th; 1401 1402 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1403 1404 m_copydata(m0, offset, sizeof(ip), &ip); 1405 m_copydata(m0, hlen, sizeof(th), &th); 1406 1407 ip.ip_len = 0; 1408 1409 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1410 sizeof(ip.ip_len), &ip.ip_len); 1411 1412 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1413 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1414 1415 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1416 sizeof(th.th_sum), &th.th_sum); 1417 1418 hlen += th.th_off << 2; 1419 } else { 1420 /* 1421 * TCP/IP headers are in the first mbuf; we can do 1422 * this the easy way. 1423 */ 1424 struct ip *ip = 1425 (struct ip *) (mtod(m0, caddr_t) + offset); 1426 struct tcphdr *th = 1427 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1428 1429 ip->ip_len = 0; 1430 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1431 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1432 1433 hlen += th->th_off << 2; 1434 } 1435 1436 cmd |= WTX_TCPIP_CMD_TSE; 1437 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1438 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1439 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1440 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1441 } 1442 1443 /* 1444 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1445 * offload feature, if we load the context descriptor, we 1446 * MUST provide valid values for IPCSS and TUCSS fields. 1447 */ 1448 1449 ipcs = WTX_TCPIP_IPCSS(offset) | 1450 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1451 WTX_TCPIP_IPCSE(offset + iphl - 1); 1452 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1453 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1454 fields |= WTX_IXSM; 1455 } 1456 1457 offset += iphl; 1458 1459 if (m0->m_pkthdr.csum_flags & 1460 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1461 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1462 fields |= WTX_TXSM; 1463 tucs = WTX_TCPIP_TUCSS(offset) | 1464 WTX_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1465 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1466 } else { 1467 /* Just initialize it to a valid TCP context. */ 1468 tucs = WTX_TCPIP_TUCSS(offset) | 1469 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1470 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1471 } 1472 1473 /* Fill in the context descriptor. */ 1474 t = (struct livengood_tcpip_ctxdesc *) 1475 &sc->sc_txdescs[sc->sc_txnext]; 1476 t->tcpip_ipcs = htole32(ipcs); 1477 t->tcpip_tucs = htole32(tucs); 1478 t->tcpip_cmdlen = htole32(cmdlen); 1479 t->tcpip_seg = htole32(seg); 1480 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1481 1482 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1483 txs->txs_ndesc++; 1484 1485 *cmdp = cmd; 1486 *fieldsp = fields; 1487 1488 return (0); 1489 } 1490 1491 static void 1492 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1493 { 1494 struct mbuf *m; 1495 int i; 1496 1497 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1498 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1499 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1500 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1501 m->m_data, m->m_len, m->m_flags); 1502 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1503 i, i == 1 ? "" : "s"); 1504 } 1505 1506 /* 1507 * wm_82547_txfifo_stall: 1508 * 1509 * Callout used to wait for the 82547 Tx FIFO to drain, 1510 * reset the FIFO pointers, and restart packet transmission. 1511 */ 1512 static void 1513 wm_82547_txfifo_stall(void *arg) 1514 { 1515 struct wm_softc *sc = arg; 1516 int s; 1517 1518 s = splnet(); 1519 1520 if (sc->sc_txfifo_stall) { 1521 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1522 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1523 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1524 /* 1525 * Packets have drained. Stop transmitter, reset 1526 * FIFO pointers, restart transmitter, and kick 1527 * the packet queue. 1528 */ 1529 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1530 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1531 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1532 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1533 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1534 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1535 CSR_WRITE(sc, WMREG_TCTL, tctl); 1536 CSR_WRITE_FLUSH(sc); 1537 1538 sc->sc_txfifo_head = 0; 1539 sc->sc_txfifo_stall = 0; 1540 wm_start(&sc->sc_ethercom.ec_if); 1541 } else { 1542 /* 1543 * Still waiting for packets to drain; try again in 1544 * another tick. 1545 */ 1546 callout_schedule(&sc->sc_txfifo_ch, 1); 1547 } 1548 } 1549 1550 splx(s); 1551 } 1552 1553 /* 1554 * wm_82547_txfifo_bugchk: 1555 * 1556 * Check for bug condition in the 82547 Tx FIFO. We need to 1557 * prevent enqueueing a packet that would wrap around the end 1558 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1559 * 1560 * We do this by checking the amount of space before the end 1561 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1562 * the Tx FIFO, wait for all remaining packets to drain, reset 1563 * the internal FIFO pointers to the beginning, and restart 1564 * transmission on the interface. 1565 */ 1566 #define WM_FIFO_HDR 0x10 1567 #define WM_82547_PAD_LEN 0x3e0 1568 static int 1569 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1570 { 1571 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1572 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1573 1574 /* Just return if already stalled. */ 1575 if (sc->sc_txfifo_stall) 1576 return (1); 1577 1578 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1579 /* Stall only occurs in half-duplex mode. */ 1580 goto send_packet; 1581 } 1582 1583 if (len >= WM_82547_PAD_LEN + space) { 1584 sc->sc_txfifo_stall = 1; 1585 callout_schedule(&sc->sc_txfifo_ch, 1); 1586 return (1); 1587 } 1588 1589 send_packet: 1590 sc->sc_txfifo_head += len; 1591 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1592 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1593 1594 return (0); 1595 } 1596 1597 /* 1598 * wm_start: [ifnet interface function] 1599 * 1600 * Start packet transmission on the interface. 1601 */ 1602 static void 1603 wm_start(struct ifnet *ifp) 1604 { 1605 struct wm_softc *sc = ifp->if_softc; 1606 struct mbuf *m0; 1607 #if 0 /* XXXJRT */ 1608 struct m_tag *mtag; 1609 #endif 1610 struct wm_txsoft *txs; 1611 bus_dmamap_t dmamap; 1612 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1613 bus_addr_t curaddr; 1614 bus_size_t seglen, curlen; 1615 uint32_t cksumcmd; 1616 uint8_t cksumfields; 1617 1618 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1619 return; 1620 1621 /* 1622 * Remember the previous number of free descriptors. 1623 */ 1624 ofree = sc->sc_txfree; 1625 1626 /* 1627 * Loop through the send queue, setting up transmit descriptors 1628 * until we drain the queue, or use up all available transmit 1629 * descriptors. 1630 */ 1631 for (;;) { 1632 /* Grab a packet off the queue. */ 1633 IFQ_POLL(&ifp->if_snd, m0); 1634 if (m0 == NULL) 1635 break; 1636 1637 DPRINTF(WM_DEBUG_TX, 1638 ("%s: TX: have packet to transmit: %p\n", 1639 sc->sc_dev.dv_xname, m0)); 1640 1641 /* Get a work queue entry. */ 1642 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1643 wm_txintr(sc); 1644 if (sc->sc_txsfree == 0) { 1645 DPRINTF(WM_DEBUG_TX, 1646 ("%s: TX: no free job descriptors\n", 1647 sc->sc_dev.dv_xname)); 1648 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1649 break; 1650 } 1651 } 1652 1653 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1654 dmamap = txs->txs_dmamap; 1655 1656 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1657 1658 /* 1659 * So says the Linux driver: 1660 * The controller does a simple calculation to make sure 1661 * there is enough room in the FIFO before initiating the 1662 * DMA for each buffer. The calc is: 1663 * 4 = ceil(buffer len / MSS) 1664 * To make sure we don't overrun the FIFO, adjust the max 1665 * buffer len if the MSS drops. 1666 */ 1667 dmamap->dm_maxsegsz = 1668 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1669 ? m0->m_pkthdr.segsz << 2 1670 : WTX_MAX_LEN; 1671 1672 /* 1673 * Load the DMA map. If this fails, the packet either 1674 * didn't fit in the allotted number of segments, or we 1675 * were short on resources. For the too-many-segments 1676 * case, we simply report an error and drop the packet, 1677 * since we can't sanely copy a jumbo packet to a single 1678 * buffer. 1679 */ 1680 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1681 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1682 if (error) { 1683 if (error == EFBIG) { 1684 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1685 log(LOG_ERR, "%s: Tx packet consumes too many " 1686 "DMA segments, dropping...\n", 1687 sc->sc_dev.dv_xname); 1688 IFQ_DEQUEUE(&ifp->if_snd, m0); 1689 wm_dump_mbuf_chain(sc, m0); 1690 m_freem(m0); 1691 continue; 1692 } 1693 /* 1694 * Short on resources, just stop for now. 1695 */ 1696 DPRINTF(WM_DEBUG_TX, 1697 ("%s: TX: dmamap load failed: %d\n", 1698 sc->sc_dev.dv_xname, error)); 1699 break; 1700 } 1701 1702 segs_needed = dmamap->dm_nsegs; 1703 if (use_tso) { 1704 /* For sentinel descriptor; see below. */ 1705 segs_needed++; 1706 } 1707 1708 /* 1709 * Ensure we have enough descriptors free to describe 1710 * the packet. Note, we always reserve one descriptor 1711 * at the end of the ring due to the semantics of the 1712 * TDT register, plus one more in the event we need 1713 * to load offload context. 1714 */ 1715 if (segs_needed > sc->sc_txfree - 2) { 1716 /* 1717 * Not enough free descriptors to transmit this 1718 * packet. We haven't committed anything yet, 1719 * so just unload the DMA map, put the packet 1720 * pack on the queue, and punt. Notify the upper 1721 * layer that there are no more slots left. 1722 */ 1723 DPRINTF(WM_DEBUG_TX, 1724 ("%s: TX: need %d (%) descriptors, have %d\n", 1725 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1726 sc->sc_txfree - 1)); 1727 ifp->if_flags |= IFF_OACTIVE; 1728 bus_dmamap_unload(sc->sc_dmat, dmamap); 1729 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1730 break; 1731 } 1732 1733 /* 1734 * Check for 82547 Tx FIFO bug. We need to do this 1735 * once we know we can transmit the packet, since we 1736 * do some internal FIFO space accounting here. 1737 */ 1738 if (sc->sc_type == WM_T_82547 && 1739 wm_82547_txfifo_bugchk(sc, m0)) { 1740 DPRINTF(WM_DEBUG_TX, 1741 ("%s: TX: 82547 Tx FIFO bug detected\n", 1742 sc->sc_dev.dv_xname)); 1743 ifp->if_flags |= IFF_OACTIVE; 1744 bus_dmamap_unload(sc->sc_dmat, dmamap); 1745 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1746 break; 1747 } 1748 1749 IFQ_DEQUEUE(&ifp->if_snd, m0); 1750 1751 /* 1752 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1753 */ 1754 1755 DPRINTF(WM_DEBUG_TX, 1756 ("%s: TX: packet has %d (%d) DMA segments\n", 1757 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1758 1759 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1760 1761 /* 1762 * Store a pointer to the packet so that we can free it 1763 * later. 1764 * 1765 * Initially, we consider the number of descriptors the 1766 * packet uses the number of DMA segments. This may be 1767 * incremented by 1 if we do checksum offload (a descriptor 1768 * is used to set the checksum context). 1769 */ 1770 txs->txs_mbuf = m0; 1771 txs->txs_firstdesc = sc->sc_txnext; 1772 txs->txs_ndesc = segs_needed; 1773 1774 /* Set up offload parameters for this packet. */ 1775 if (m0->m_pkthdr.csum_flags & 1776 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1777 if (wm_tx_offload(sc, txs, &cksumcmd, 1778 &cksumfields) != 0) { 1779 /* Error message already displayed. */ 1780 bus_dmamap_unload(sc->sc_dmat, dmamap); 1781 continue; 1782 } 1783 } else { 1784 cksumcmd = 0; 1785 cksumfields = 0; 1786 } 1787 1788 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1789 1790 /* Sync the DMA map. */ 1791 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1792 BUS_DMASYNC_PREWRITE); 1793 1794 /* 1795 * Initialize the transmit descriptor. 1796 */ 1797 for (nexttx = sc->sc_txnext, seg = 0; 1798 seg < dmamap->dm_nsegs; seg++) { 1799 for (seglen = dmamap->dm_segs[seg].ds_len, 1800 curaddr = dmamap->dm_segs[seg].ds_addr; 1801 seglen != 0; 1802 curaddr += curlen, seglen -= curlen, 1803 nexttx = WM_NEXTTX(sc, nexttx)) { 1804 curlen = seglen; 1805 1806 /* 1807 * So says the Linux driver: 1808 * Work around for premature descriptor 1809 * write-backs in TSO mode. Append a 1810 * 4-byte sentinel descriptor. 1811 */ 1812 if (use_tso && 1813 seg == dmamap->dm_nsegs - 1 && 1814 curlen > 8) 1815 curlen -= 4; 1816 1817 wm_set_dma_addr( 1818 &sc->sc_txdescs[nexttx].wtx_addr, 1819 curaddr); 1820 sc->sc_txdescs[nexttx].wtx_cmdlen = 1821 htole32(cksumcmd | curlen); 1822 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1823 0; 1824 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1825 cksumfields; 1826 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1827 lasttx = nexttx; 1828 1829 DPRINTF(WM_DEBUG_TX, 1830 ("%s: TX: desc %d: low 0x%08x, " 1831 "len 0x%04x\n", 1832 sc->sc_dev.dv_xname, nexttx, 1833 curaddr & 0xffffffffU, curlen, curlen)); 1834 } 1835 } 1836 1837 KASSERT(lasttx != -1); 1838 1839 /* 1840 * Set up the command byte on the last descriptor of 1841 * the packet. If we're in the interrupt delay window, 1842 * delay the interrupt. 1843 */ 1844 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1845 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1846 1847 #if 0 /* XXXJRT */ 1848 /* 1849 * If VLANs are enabled and the packet has a VLAN tag, set 1850 * up the descriptor to encapsulate the packet for us. 1851 * 1852 * This is only valid on the last descriptor of the packet. 1853 */ 1854 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1855 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1856 htole32(WTX_CMD_VLE); 1857 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1858 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1859 } 1860 #endif /* XXXJRT */ 1861 1862 txs->txs_lastdesc = lasttx; 1863 1864 DPRINTF(WM_DEBUG_TX, 1865 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1866 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1867 1868 /* Sync the descriptors we're using. */ 1869 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1870 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1871 1872 /* Give the packet to the chip. */ 1873 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1874 1875 DPRINTF(WM_DEBUG_TX, 1876 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1877 1878 DPRINTF(WM_DEBUG_TX, 1879 ("%s: TX: finished transmitting packet, job %d\n", 1880 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1881 1882 /* Advance the tx pointer. */ 1883 sc->sc_txfree -= txs->txs_ndesc; 1884 sc->sc_txnext = nexttx; 1885 1886 sc->sc_txsfree--; 1887 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1888 1889 #if NBPFILTER > 0 1890 /* Pass the packet to any BPF listeners. */ 1891 if (ifp->if_bpf) 1892 bpf_mtap(ifp->if_bpf, m0); 1893 #endif /* NBPFILTER > 0 */ 1894 } 1895 1896 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1897 /* No more slots; notify upper layer. */ 1898 ifp->if_flags |= IFF_OACTIVE; 1899 } 1900 1901 if (sc->sc_txfree != ofree) { 1902 /* Set a watchdog timer in case the chip flakes out. */ 1903 ifp->if_timer = 5; 1904 } 1905 } 1906 1907 /* 1908 * wm_watchdog: [ifnet interface function] 1909 * 1910 * Watchdog timer handler. 1911 */ 1912 static void 1913 wm_watchdog(struct ifnet *ifp) 1914 { 1915 struct wm_softc *sc = ifp->if_softc; 1916 1917 /* 1918 * Since we're using delayed interrupts, sweep up 1919 * before we report an error. 1920 */ 1921 wm_txintr(sc); 1922 1923 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1924 log(LOG_ERR, 1925 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1926 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1927 sc->sc_txnext); 1928 ifp->if_oerrors++; 1929 1930 /* Reset the interface. */ 1931 (void) wm_init(ifp); 1932 } 1933 1934 /* Try to get more packets going. */ 1935 wm_start(ifp); 1936 } 1937 1938 /* 1939 * wm_ioctl: [ifnet interface function] 1940 * 1941 * Handle control requests from the operator. 1942 */ 1943 static int 1944 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1945 { 1946 struct wm_softc *sc = ifp->if_softc; 1947 struct ifreq *ifr = (struct ifreq *) data; 1948 int s, error; 1949 1950 s = splnet(); 1951 1952 switch (cmd) { 1953 case SIOCSIFMEDIA: 1954 case SIOCGIFMEDIA: 1955 /* Flow control requires full-duplex mode. */ 1956 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1957 (ifr->ifr_media & IFM_FDX) == 0) 1958 ifr->ifr_media &= ~IFM_ETH_FMASK; 1959 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1960 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1961 /* We can do both TXPAUSE and RXPAUSE. */ 1962 ifr->ifr_media |= 1963 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1964 } 1965 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1966 } 1967 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1968 break; 1969 default: 1970 error = ether_ioctl(ifp, cmd, data); 1971 if (error == ENETRESET) { 1972 /* 1973 * Multicast list has changed; set the hardware filter 1974 * accordingly. 1975 */ 1976 if (ifp->if_flags & IFF_RUNNING) 1977 wm_set_filter(sc); 1978 error = 0; 1979 } 1980 break; 1981 } 1982 1983 /* Try to get more packets going. */ 1984 wm_start(ifp); 1985 1986 splx(s); 1987 return (error); 1988 } 1989 1990 /* 1991 * wm_intr: 1992 * 1993 * Interrupt service routine. 1994 */ 1995 static int 1996 wm_intr(void *arg) 1997 { 1998 struct wm_softc *sc = arg; 1999 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2000 uint32_t icr; 2001 int wantinit, handled = 0; 2002 2003 for (wantinit = 0; wantinit == 0;) { 2004 icr = CSR_READ(sc, WMREG_ICR); 2005 if ((icr & sc->sc_icr) == 0) 2006 break; 2007 2008 #if 0 /*NRND > 0*/ 2009 if (RND_ENABLED(&sc->rnd_source)) 2010 rnd_add_uint32(&sc->rnd_source, icr); 2011 #endif 2012 2013 handled = 1; 2014 2015 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2016 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2017 DPRINTF(WM_DEBUG_RX, 2018 ("%s: RX: got Rx intr 0x%08x\n", 2019 sc->sc_dev.dv_xname, 2020 icr & (ICR_RXDMT0|ICR_RXT0))); 2021 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2022 } 2023 #endif 2024 wm_rxintr(sc); 2025 2026 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2027 if (icr & ICR_TXDW) { 2028 DPRINTF(WM_DEBUG_TX, 2029 ("%s: TX: got TXDW interrupt\n", 2030 sc->sc_dev.dv_xname)); 2031 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2032 } 2033 #endif 2034 wm_txintr(sc); 2035 2036 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2037 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2038 wm_linkintr(sc, icr); 2039 } 2040 2041 if (icr & ICR_RXO) { 2042 log(LOG_WARNING, "%s: Receive overrun\n", 2043 sc->sc_dev.dv_xname); 2044 wantinit = 1; 2045 } 2046 } 2047 2048 if (handled) { 2049 if (wantinit) 2050 wm_init(ifp); 2051 2052 /* Try to get more packets going. */ 2053 wm_start(ifp); 2054 } 2055 2056 return (handled); 2057 } 2058 2059 /* 2060 * wm_txintr: 2061 * 2062 * Helper; handle transmit interrupts. 2063 */ 2064 static void 2065 wm_txintr(struct wm_softc *sc) 2066 { 2067 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2068 struct wm_txsoft *txs; 2069 uint8_t status; 2070 int i; 2071 2072 ifp->if_flags &= ~IFF_OACTIVE; 2073 2074 /* 2075 * Go through the Tx list and free mbufs for those 2076 * frames which have been transmitted. 2077 */ 2078 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2079 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2080 txs = &sc->sc_txsoft[i]; 2081 2082 DPRINTF(WM_DEBUG_TX, 2083 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2084 2085 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2086 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2087 2088 status = 2089 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2090 if ((status & WTX_ST_DD) == 0) { 2091 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2092 BUS_DMASYNC_PREREAD); 2093 break; 2094 } 2095 2096 DPRINTF(WM_DEBUG_TX, 2097 ("%s: TX: job %d done: descs %d..%d\n", 2098 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2099 txs->txs_lastdesc)); 2100 2101 /* 2102 * XXX We should probably be using the statistics 2103 * XXX registers, but I don't know if they exist 2104 * XXX on chips before the i82544. 2105 */ 2106 2107 #ifdef WM_EVENT_COUNTERS 2108 if (status & WTX_ST_TU) 2109 WM_EVCNT_INCR(&sc->sc_ev_tu); 2110 #endif /* WM_EVENT_COUNTERS */ 2111 2112 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2113 ifp->if_oerrors++; 2114 if (status & WTX_ST_LC) 2115 log(LOG_WARNING, "%s: late collision\n", 2116 sc->sc_dev.dv_xname); 2117 else if (status & WTX_ST_EC) { 2118 ifp->if_collisions += 16; 2119 log(LOG_WARNING, "%s: excessive collisions\n", 2120 sc->sc_dev.dv_xname); 2121 } 2122 } else 2123 ifp->if_opackets++; 2124 2125 sc->sc_txfree += txs->txs_ndesc; 2126 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2127 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2128 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2129 m_freem(txs->txs_mbuf); 2130 txs->txs_mbuf = NULL; 2131 } 2132 2133 /* Update the dirty transmit buffer pointer. */ 2134 sc->sc_txsdirty = i; 2135 DPRINTF(WM_DEBUG_TX, 2136 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2137 2138 /* 2139 * If there are no more pending transmissions, cancel the watchdog 2140 * timer. 2141 */ 2142 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2143 ifp->if_timer = 0; 2144 } 2145 2146 /* 2147 * wm_rxintr: 2148 * 2149 * Helper; handle receive interrupts. 2150 */ 2151 static void 2152 wm_rxintr(struct wm_softc *sc) 2153 { 2154 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2155 struct wm_rxsoft *rxs; 2156 struct mbuf *m; 2157 int i, len; 2158 uint8_t status, errors; 2159 2160 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2161 rxs = &sc->sc_rxsoft[i]; 2162 2163 DPRINTF(WM_DEBUG_RX, 2164 ("%s: RX: checking descriptor %d\n", 2165 sc->sc_dev.dv_xname, i)); 2166 2167 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2168 2169 status = sc->sc_rxdescs[i].wrx_status; 2170 errors = sc->sc_rxdescs[i].wrx_errors; 2171 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2172 2173 if ((status & WRX_ST_DD) == 0) { 2174 /* 2175 * We have processed all of the receive descriptors. 2176 */ 2177 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2178 break; 2179 } 2180 2181 if (__predict_false(sc->sc_rxdiscard)) { 2182 DPRINTF(WM_DEBUG_RX, 2183 ("%s: RX: discarding contents of descriptor %d\n", 2184 sc->sc_dev.dv_xname, i)); 2185 WM_INIT_RXDESC(sc, i); 2186 if (status & WRX_ST_EOP) { 2187 /* Reset our state. */ 2188 DPRINTF(WM_DEBUG_RX, 2189 ("%s: RX: resetting rxdiscard -> 0\n", 2190 sc->sc_dev.dv_xname)); 2191 sc->sc_rxdiscard = 0; 2192 } 2193 continue; 2194 } 2195 2196 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2197 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2198 2199 m = rxs->rxs_mbuf; 2200 2201 /* 2202 * Add a new receive buffer to the ring. 2203 */ 2204 if (wm_add_rxbuf(sc, i) != 0) { 2205 /* 2206 * Failed, throw away what we've done so 2207 * far, and discard the rest of the packet. 2208 */ 2209 ifp->if_ierrors++; 2210 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2211 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2212 WM_INIT_RXDESC(sc, i); 2213 if ((status & WRX_ST_EOP) == 0) 2214 sc->sc_rxdiscard = 1; 2215 if (sc->sc_rxhead != NULL) 2216 m_freem(sc->sc_rxhead); 2217 WM_RXCHAIN_RESET(sc); 2218 DPRINTF(WM_DEBUG_RX, 2219 ("%s: RX: Rx buffer allocation failed, " 2220 "dropping packet%s\n", sc->sc_dev.dv_xname, 2221 sc->sc_rxdiscard ? " (discard)" : "")); 2222 continue; 2223 } 2224 2225 WM_RXCHAIN_LINK(sc, m); 2226 2227 m->m_len = len; 2228 2229 DPRINTF(WM_DEBUG_RX, 2230 ("%s: RX: buffer at %p len %d\n", 2231 sc->sc_dev.dv_xname, m->m_data, len)); 2232 2233 /* 2234 * If this is not the end of the packet, keep 2235 * looking. 2236 */ 2237 if ((status & WRX_ST_EOP) == 0) { 2238 sc->sc_rxlen += len; 2239 DPRINTF(WM_DEBUG_RX, 2240 ("%s: RX: not yet EOP, rxlen -> %d\n", 2241 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2242 continue; 2243 } 2244 2245 /* 2246 * Okay, we have the entire packet now. The chip is 2247 * configured to include the FCS (not all chips can 2248 * be configured to strip it), so we need to trim it. 2249 */ 2250 m->m_len -= ETHER_CRC_LEN; 2251 2252 *sc->sc_rxtailp = NULL; 2253 m = sc->sc_rxhead; 2254 len = m->m_len + sc->sc_rxlen; 2255 2256 WM_RXCHAIN_RESET(sc); 2257 2258 DPRINTF(WM_DEBUG_RX, 2259 ("%s: RX: have entire packet, len -> %d\n", 2260 sc->sc_dev.dv_xname, len)); 2261 2262 /* 2263 * If an error occurred, update stats and drop the packet. 2264 */ 2265 if (errors & 2266 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2267 ifp->if_ierrors++; 2268 if (errors & WRX_ER_SE) 2269 log(LOG_WARNING, "%s: symbol error\n", 2270 sc->sc_dev.dv_xname); 2271 else if (errors & WRX_ER_SEQ) 2272 log(LOG_WARNING, "%s: receive sequence error\n", 2273 sc->sc_dev.dv_xname); 2274 else if (errors & WRX_ER_CE) 2275 log(LOG_WARNING, "%s: CRC error\n", 2276 sc->sc_dev.dv_xname); 2277 m_freem(m); 2278 continue; 2279 } 2280 2281 /* 2282 * No errors. Receive the packet. 2283 */ 2284 m->m_pkthdr.rcvif = ifp; 2285 m->m_pkthdr.len = len; 2286 2287 #if 0 /* XXXJRT */ 2288 /* 2289 * If VLANs are enabled, VLAN packets have been unwrapped 2290 * for us. Associate the tag with the packet. 2291 */ 2292 if ((status & WRX_ST_VP) != 0) { 2293 VLAN_INPUT_TAG(ifp, m, 2294 le16toh(sc->sc_rxdescs[i].wrx_special, 2295 continue); 2296 } 2297 #endif /* XXXJRT */ 2298 2299 /* 2300 * Set up checksum info for this packet. 2301 */ 2302 if (status & WRX_ST_IPCS) { 2303 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2304 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2305 if (errors & WRX_ER_IPE) 2306 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2307 } 2308 if (status & WRX_ST_TCPCS) { 2309 /* 2310 * Note: we don't know if this was TCP or UDP, 2311 * so we just set both bits, and expect the 2312 * upper layers to deal. 2313 */ 2314 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2315 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2316 if (errors & WRX_ER_TCPE) 2317 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2318 } 2319 2320 ifp->if_ipackets++; 2321 2322 #if NBPFILTER > 0 2323 /* Pass this up to any BPF listeners. */ 2324 if (ifp->if_bpf) 2325 bpf_mtap(ifp->if_bpf, m); 2326 #endif /* NBPFILTER > 0 */ 2327 2328 /* Pass it on. */ 2329 (*ifp->if_input)(ifp, m); 2330 } 2331 2332 /* Update the receive pointer. */ 2333 sc->sc_rxptr = i; 2334 2335 DPRINTF(WM_DEBUG_RX, 2336 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2337 } 2338 2339 /* 2340 * wm_linkintr: 2341 * 2342 * Helper; handle link interrupts. 2343 */ 2344 static void 2345 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2346 { 2347 uint32_t status; 2348 2349 /* 2350 * If we get a link status interrupt on a 1000BASE-T 2351 * device, just fall into the normal MII tick path. 2352 */ 2353 if (sc->sc_flags & WM_F_HAS_MII) { 2354 if (icr & ICR_LSC) { 2355 DPRINTF(WM_DEBUG_LINK, 2356 ("%s: LINK: LSC -> mii_tick\n", 2357 sc->sc_dev.dv_xname)); 2358 mii_tick(&sc->sc_mii); 2359 } else if (icr & ICR_RXSEQ) { 2360 DPRINTF(WM_DEBUG_LINK, 2361 ("%s: LINK Receive sequence error\n", 2362 sc->sc_dev.dv_xname)); 2363 } 2364 return; 2365 } 2366 2367 /* 2368 * If we are now receiving /C/, check for link again in 2369 * a couple of link clock ticks. 2370 */ 2371 if (icr & ICR_RXCFG) { 2372 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2373 sc->sc_dev.dv_xname)); 2374 sc->sc_tbi_anstate = 2; 2375 } 2376 2377 if (icr & ICR_LSC) { 2378 status = CSR_READ(sc, WMREG_STATUS); 2379 if (status & STATUS_LU) { 2380 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2381 sc->sc_dev.dv_xname, 2382 (status & STATUS_FD) ? "FDX" : "HDX")); 2383 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2384 sc->sc_fcrtl &= ~FCRTL_XONE; 2385 if (status & STATUS_FD) 2386 sc->sc_tctl |= 2387 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2388 else 2389 sc->sc_tctl |= 2390 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2391 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2392 sc->sc_fcrtl |= FCRTL_XONE; 2393 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2394 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2395 WMREG_OLD_FCRTL : WMREG_FCRTL, 2396 sc->sc_fcrtl); 2397 sc->sc_tbi_linkup = 1; 2398 } else { 2399 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2400 sc->sc_dev.dv_xname)); 2401 sc->sc_tbi_linkup = 0; 2402 } 2403 sc->sc_tbi_anstate = 2; 2404 wm_tbi_set_linkled(sc); 2405 } else if (icr & ICR_RXSEQ) { 2406 DPRINTF(WM_DEBUG_LINK, 2407 ("%s: LINK: Receive sequence error\n", 2408 sc->sc_dev.dv_xname)); 2409 } 2410 } 2411 2412 /* 2413 * wm_tick: 2414 * 2415 * One second timer, used to check link status, sweep up 2416 * completed transmit jobs, etc. 2417 */ 2418 static void 2419 wm_tick(void *arg) 2420 { 2421 struct wm_softc *sc = arg; 2422 int s; 2423 2424 s = splnet(); 2425 2426 if (sc->sc_type >= WM_T_82542_2_1) { 2427 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2428 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2429 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2430 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2431 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2432 } 2433 2434 if (sc->sc_flags & WM_F_HAS_MII) 2435 mii_tick(&sc->sc_mii); 2436 else 2437 wm_tbi_check_link(sc); 2438 2439 splx(s); 2440 2441 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2442 } 2443 2444 /* 2445 * wm_reset: 2446 * 2447 * Reset the i82542 chip. 2448 */ 2449 static void 2450 wm_reset(struct wm_softc *sc) 2451 { 2452 int i; 2453 2454 /* 2455 * Allocate on-chip memory according to the MTU size. 2456 * The Packet Buffer Allocation register must be written 2457 * before the chip is reset. 2458 */ 2459 if (sc->sc_type < WM_T_82547) { 2460 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2461 PBA_40K : PBA_48K; 2462 } else { 2463 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2464 PBA_22K : PBA_30K; 2465 sc->sc_txfifo_head = 0; 2466 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2467 sc->sc_txfifo_size = 2468 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2469 sc->sc_txfifo_stall = 0; 2470 } 2471 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2472 2473 switch (sc->sc_type) { 2474 case WM_T_82544: 2475 case WM_T_82540: 2476 case WM_T_82545: 2477 case WM_T_82546: 2478 case WM_T_82541: 2479 case WM_T_82541_2: 2480 /* 2481 * On some chipsets, a reset through a memory-mapped write 2482 * cycle can cause the chip to reset before completing the 2483 * write cycle. This causes major headache that can be 2484 * avoided by issuing the reset via indirect register writes 2485 * through I/O space. 2486 * 2487 * So, if we successfully mapped the I/O BAR at attach time, 2488 * use that. Otherwise, try our luck with a memory-mapped 2489 * reset. 2490 */ 2491 if (sc->sc_flags & WM_F_IOH_VALID) 2492 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2493 else 2494 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2495 break; 2496 2497 case WM_T_82545_3: 2498 case WM_T_82546_3: 2499 /* Use the shadow control register on these chips. */ 2500 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2501 break; 2502 2503 default: 2504 /* Everything else can safely use the documented method. */ 2505 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2506 break; 2507 } 2508 delay(10000); 2509 2510 for (i = 0; i < 1000; i++) { 2511 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2512 return; 2513 delay(20); 2514 } 2515 2516 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2517 log(LOG_ERR, "%s: reset failed to complete\n", 2518 sc->sc_dev.dv_xname); 2519 } 2520 2521 /* 2522 * wm_init: [ifnet interface function] 2523 * 2524 * Initialize the interface. Must be called at splnet(). 2525 */ 2526 static int 2527 wm_init(struct ifnet *ifp) 2528 { 2529 struct wm_softc *sc = ifp->if_softc; 2530 struct wm_rxsoft *rxs; 2531 int i, error = 0; 2532 uint32_t reg; 2533 2534 /* 2535 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2536 * There is a small but measurable benefit to avoiding the adjusment 2537 * of the descriptor so that the headers are aligned, for normal mtu, 2538 * on such platforms. One possibility is that the DMA itself is 2539 * slightly more efficient if the front of the entire packet (instead 2540 * of the front of the headers) is aligned. 2541 * 2542 * Note we must always set align_tweak to 0 if we are using 2543 * jumbo frames. 2544 */ 2545 #ifdef __NO_STRICT_ALIGNMENT 2546 sc->sc_align_tweak = 0; 2547 #else 2548 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2549 sc->sc_align_tweak = 0; 2550 else 2551 sc->sc_align_tweak = 2; 2552 #endif /* __NO_STRICT_ALIGNMENT */ 2553 2554 /* Cancel any pending I/O. */ 2555 wm_stop(ifp, 0); 2556 2557 /* Reset the chip to a known state. */ 2558 wm_reset(sc); 2559 2560 /* Initialize the transmit descriptor ring. */ 2561 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2562 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2563 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2564 sc->sc_txfree = WM_NTXDESC(sc); 2565 sc->sc_txnext = 0; 2566 2567 if (sc->sc_type < WM_T_82543) { 2568 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2569 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2570 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2571 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2572 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2573 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2574 } else { 2575 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2576 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2577 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2578 CSR_WRITE(sc, WMREG_TDH, 0); 2579 CSR_WRITE(sc, WMREG_TDT, 0); 2580 CSR_WRITE(sc, WMREG_TIDV, 64); 2581 CSR_WRITE(sc, WMREG_TADV, 128); 2582 2583 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2584 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2585 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2586 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2587 } 2588 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2589 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2590 2591 /* Initialize the transmit job descriptors. */ 2592 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2593 sc->sc_txsoft[i].txs_mbuf = NULL; 2594 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2595 sc->sc_txsnext = 0; 2596 sc->sc_txsdirty = 0; 2597 2598 /* 2599 * Initialize the receive descriptor and receive job 2600 * descriptor rings. 2601 */ 2602 if (sc->sc_type < WM_T_82543) { 2603 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2604 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2605 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2606 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2607 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2608 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2609 2610 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2611 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2612 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2613 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2614 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2615 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2616 } else { 2617 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2618 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2619 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2620 CSR_WRITE(sc, WMREG_RDH, 0); 2621 CSR_WRITE(sc, WMREG_RDT, 0); 2622 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2623 CSR_WRITE(sc, WMREG_RADV, 128); 2624 } 2625 for (i = 0; i < WM_NRXDESC; i++) { 2626 rxs = &sc->sc_rxsoft[i]; 2627 if (rxs->rxs_mbuf == NULL) { 2628 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2629 log(LOG_ERR, "%s: unable to allocate or map rx " 2630 "buffer %d, error = %d\n", 2631 sc->sc_dev.dv_xname, i, error); 2632 /* 2633 * XXX Should attempt to run with fewer receive 2634 * XXX buffers instead of just failing. 2635 */ 2636 wm_rxdrain(sc); 2637 goto out; 2638 } 2639 } else 2640 WM_INIT_RXDESC(sc, i); 2641 } 2642 sc->sc_rxptr = 0; 2643 sc->sc_rxdiscard = 0; 2644 WM_RXCHAIN_RESET(sc); 2645 2646 /* 2647 * Clear out the VLAN table -- we don't use it (yet). 2648 */ 2649 CSR_WRITE(sc, WMREG_VET, 0); 2650 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2651 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2652 2653 /* 2654 * Set up flow-control parameters. 2655 * 2656 * XXX Values could probably stand some tuning. 2657 */ 2658 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2659 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2660 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2661 2662 sc->sc_fcrtl = FCRTL_DFLT; 2663 if (sc->sc_type < WM_T_82543) { 2664 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2665 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2666 } else { 2667 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2668 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2669 } 2670 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2671 2672 #if 0 /* XXXJRT */ 2673 /* Deal with VLAN enables. */ 2674 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2675 sc->sc_ctrl |= CTRL_VME; 2676 else 2677 #endif /* XXXJRT */ 2678 sc->sc_ctrl &= ~CTRL_VME; 2679 2680 /* Write the control registers. */ 2681 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2682 #if 0 2683 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2684 #endif 2685 2686 /* 2687 * Set up checksum offload parameters. 2688 */ 2689 reg = CSR_READ(sc, WMREG_RXCSUM); 2690 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2691 reg |= RXCSUM_IPOFL; 2692 else 2693 reg &= ~RXCSUM_IPOFL; 2694 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2695 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2696 else { 2697 reg &= ~RXCSUM_TUOFL; 2698 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2699 reg &= ~RXCSUM_IPOFL; 2700 } 2701 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2702 2703 /* 2704 * Set up the interrupt registers. 2705 */ 2706 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2707 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2708 ICR_RXO | ICR_RXT0; 2709 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2710 sc->sc_icr |= ICR_RXCFG; 2711 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2712 2713 /* Set up the inter-packet gap. */ 2714 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2715 2716 if (sc->sc_type >= WM_T_82543) { 2717 /* Set up the interrupt throttling register (units of 256ns) */ 2718 sc->sc_itr = 1000000000 / (7000 * 256); 2719 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2720 } 2721 2722 #if 0 /* XXXJRT */ 2723 /* Set the VLAN ethernetype. */ 2724 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2725 #endif 2726 2727 /* 2728 * Set up the transmit control register; we start out with 2729 * a collision distance suitable for FDX, but update it whe 2730 * we resolve the media type. 2731 */ 2732 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2733 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2734 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2735 2736 /* Set the media. */ 2737 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2738 2739 /* 2740 * Set up the receive control register; we actually program 2741 * the register when we set the receive filter. Use multicast 2742 * address offset type 0. 2743 * 2744 * Only the i82544 has the ability to strip the incoming 2745 * CRC, so we don't enable that feature. 2746 */ 2747 sc->sc_mchash_type = 0; 2748 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2749 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2750 2751 if(MCLBYTES == 2048) { 2752 sc->sc_rctl |= RCTL_2k; 2753 } else { 2754 if(sc->sc_type >= WM_T_82543) { 2755 switch(MCLBYTES) { 2756 case 4096: 2757 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2758 break; 2759 case 8192: 2760 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2761 break; 2762 case 16384: 2763 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2764 break; 2765 default: 2766 panic("wm_init: MCLBYTES %d unsupported", 2767 MCLBYTES); 2768 break; 2769 } 2770 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2771 } 2772 2773 /* Set the receive filter. */ 2774 wm_set_filter(sc); 2775 2776 /* Start the one second link check clock. */ 2777 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2778 2779 /* ...all done! */ 2780 ifp->if_flags |= IFF_RUNNING; 2781 ifp->if_flags &= ~IFF_OACTIVE; 2782 2783 out: 2784 if (error) 2785 log(LOG_ERR, "%s: interface not running\n", 2786 sc->sc_dev.dv_xname); 2787 return (error); 2788 } 2789 2790 /* 2791 * wm_rxdrain: 2792 * 2793 * Drain the receive queue. 2794 */ 2795 static void 2796 wm_rxdrain(struct wm_softc *sc) 2797 { 2798 struct wm_rxsoft *rxs; 2799 int i; 2800 2801 for (i = 0; i < WM_NRXDESC; i++) { 2802 rxs = &sc->sc_rxsoft[i]; 2803 if (rxs->rxs_mbuf != NULL) { 2804 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2805 m_freem(rxs->rxs_mbuf); 2806 rxs->rxs_mbuf = NULL; 2807 } 2808 } 2809 } 2810 2811 /* 2812 * wm_stop: [ifnet interface function] 2813 * 2814 * Stop transmission on the interface. 2815 */ 2816 static void 2817 wm_stop(struct ifnet *ifp, int disable) 2818 { 2819 struct wm_softc *sc = ifp->if_softc; 2820 struct wm_txsoft *txs; 2821 int i; 2822 2823 /* Stop the one second clock. */ 2824 callout_stop(&sc->sc_tick_ch); 2825 2826 /* Stop the 82547 Tx FIFO stall check timer. */ 2827 if (sc->sc_type == WM_T_82547) 2828 callout_stop(&sc->sc_txfifo_ch); 2829 2830 if (sc->sc_flags & WM_F_HAS_MII) { 2831 /* Down the MII. */ 2832 mii_down(&sc->sc_mii); 2833 } 2834 2835 /* Stop the transmit and receive processes. */ 2836 CSR_WRITE(sc, WMREG_TCTL, 0); 2837 CSR_WRITE(sc, WMREG_RCTL, 0); 2838 2839 /* Release any queued transmit buffers. */ 2840 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2841 txs = &sc->sc_txsoft[i]; 2842 if (txs->txs_mbuf != NULL) { 2843 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2844 m_freem(txs->txs_mbuf); 2845 txs->txs_mbuf = NULL; 2846 } 2847 } 2848 2849 if (disable) 2850 wm_rxdrain(sc); 2851 2852 /* Mark the interface as down and cancel the watchdog timer. */ 2853 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2854 ifp->if_timer = 0; 2855 } 2856 2857 /* 2858 * wm_acquire_eeprom: 2859 * 2860 * Perform the EEPROM handshake required on some chips. 2861 */ 2862 static int 2863 wm_acquire_eeprom(struct wm_softc *sc) 2864 { 2865 uint32_t reg; 2866 int x; 2867 2868 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2869 reg = CSR_READ(sc, WMREG_EECD); 2870 2871 /* Request EEPROM access. */ 2872 reg |= EECD_EE_REQ; 2873 CSR_WRITE(sc, WMREG_EECD, reg); 2874 2875 /* ..and wait for it to be granted. */ 2876 for (x = 0; x < 100; x++) { 2877 reg = CSR_READ(sc, WMREG_EECD); 2878 if (reg & EECD_EE_GNT) 2879 break; 2880 delay(5); 2881 } 2882 if ((reg & EECD_EE_GNT) == 0) { 2883 aprint_error("%s: could not acquire EEPROM GNT\n", 2884 sc->sc_dev.dv_xname); 2885 reg &= ~EECD_EE_REQ; 2886 CSR_WRITE(sc, WMREG_EECD, reg); 2887 return (1); 2888 } 2889 } 2890 2891 return (0); 2892 } 2893 2894 /* 2895 * wm_release_eeprom: 2896 * 2897 * Release the EEPROM mutex. 2898 */ 2899 static void 2900 wm_release_eeprom(struct wm_softc *sc) 2901 { 2902 uint32_t reg; 2903 2904 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2905 reg = CSR_READ(sc, WMREG_EECD); 2906 reg &= ~EECD_EE_REQ; 2907 CSR_WRITE(sc, WMREG_EECD, reg); 2908 } 2909 } 2910 2911 /* 2912 * wm_eeprom_sendbits: 2913 * 2914 * Send a series of bits to the EEPROM. 2915 */ 2916 static void 2917 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2918 { 2919 uint32_t reg; 2920 int x; 2921 2922 reg = CSR_READ(sc, WMREG_EECD); 2923 2924 for (x = nbits; x > 0; x--) { 2925 if (bits & (1U << (x - 1))) 2926 reg |= EECD_DI; 2927 else 2928 reg &= ~EECD_DI; 2929 CSR_WRITE(sc, WMREG_EECD, reg); 2930 delay(2); 2931 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2932 delay(2); 2933 CSR_WRITE(sc, WMREG_EECD, reg); 2934 delay(2); 2935 } 2936 } 2937 2938 /* 2939 * wm_eeprom_recvbits: 2940 * 2941 * Receive a series of bits from the EEPROM. 2942 */ 2943 static void 2944 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2945 { 2946 uint32_t reg, val; 2947 int x; 2948 2949 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2950 2951 val = 0; 2952 for (x = nbits; x > 0; x--) { 2953 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2954 delay(2); 2955 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2956 val |= (1U << (x - 1)); 2957 CSR_WRITE(sc, WMREG_EECD, reg); 2958 delay(2); 2959 } 2960 *valp = val; 2961 } 2962 2963 /* 2964 * wm_read_eeprom_uwire: 2965 * 2966 * Read a word from the EEPROM using the MicroWire protocol. 2967 */ 2968 static int 2969 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2970 { 2971 uint32_t reg, val; 2972 int i; 2973 2974 for (i = 0; i < wordcnt; i++) { 2975 /* Clear SK and DI. */ 2976 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2977 CSR_WRITE(sc, WMREG_EECD, reg); 2978 2979 /* Set CHIP SELECT. */ 2980 reg |= EECD_CS; 2981 CSR_WRITE(sc, WMREG_EECD, reg); 2982 delay(2); 2983 2984 /* Shift in the READ command. */ 2985 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2986 2987 /* Shift in address. */ 2988 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2989 2990 /* Shift out the data. */ 2991 wm_eeprom_recvbits(sc, &val, 16); 2992 data[i] = val & 0xffff; 2993 2994 /* Clear CHIP SELECT. */ 2995 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2996 CSR_WRITE(sc, WMREG_EECD, reg); 2997 delay(2); 2998 } 2999 3000 return (0); 3001 } 3002 3003 /* 3004 * wm_spi_eeprom_ready: 3005 * 3006 * Wait for a SPI EEPROM to be ready for commands. 3007 */ 3008 static int 3009 wm_spi_eeprom_ready(struct wm_softc *sc) 3010 { 3011 uint32_t val; 3012 int usec; 3013 3014 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3015 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3016 wm_eeprom_recvbits(sc, &val, 8); 3017 if ((val & SPI_SR_RDY) == 0) 3018 break; 3019 } 3020 if (usec >= SPI_MAX_RETRIES) { 3021 aprint_error("%s: EEPROM failed to become ready\n", 3022 sc->sc_dev.dv_xname); 3023 return (1); 3024 } 3025 return (0); 3026 } 3027 3028 /* 3029 * wm_read_eeprom_spi: 3030 * 3031 * Read a work from the EEPROM using the SPI protocol. 3032 */ 3033 static int 3034 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3035 { 3036 uint32_t reg, val; 3037 int i; 3038 uint8_t opc; 3039 3040 /* Clear SK and CS. */ 3041 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3042 CSR_WRITE(sc, WMREG_EECD, reg); 3043 delay(2); 3044 3045 if (wm_spi_eeprom_ready(sc)) 3046 return (1); 3047 3048 /* Toggle CS to flush commands. */ 3049 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3050 delay(2); 3051 CSR_WRITE(sc, WMREG_EECD, reg); 3052 delay(2); 3053 3054 opc = SPI_OPC_READ; 3055 if (sc->sc_ee_addrbits == 8 && word >= 128) 3056 opc |= SPI_OPC_A8; 3057 3058 wm_eeprom_sendbits(sc, opc, 8); 3059 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3060 3061 for (i = 0; i < wordcnt; i++) { 3062 wm_eeprom_recvbits(sc, &val, 16); 3063 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3064 } 3065 3066 /* Raise CS and clear SK. */ 3067 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3068 CSR_WRITE(sc, WMREG_EECD, reg); 3069 delay(2); 3070 3071 return (0); 3072 } 3073 3074 /* 3075 * wm_read_eeprom: 3076 * 3077 * Read data from the serial EEPROM. 3078 */ 3079 static int 3080 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3081 { 3082 int rv; 3083 3084 if (wm_acquire_eeprom(sc)) 3085 return (1); 3086 3087 if (sc->sc_flags & WM_F_EEPROM_SPI) 3088 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3089 else 3090 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3091 3092 wm_release_eeprom(sc); 3093 return (rv); 3094 } 3095 3096 /* 3097 * wm_add_rxbuf: 3098 * 3099 * Add a receive buffer to the indiciated descriptor. 3100 */ 3101 static int 3102 wm_add_rxbuf(struct wm_softc *sc, int idx) 3103 { 3104 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3105 struct mbuf *m; 3106 int error; 3107 3108 MGETHDR(m, M_DONTWAIT, MT_DATA); 3109 if (m == NULL) 3110 return (ENOBUFS); 3111 3112 MCLGET(m, M_DONTWAIT); 3113 if ((m->m_flags & M_EXT) == 0) { 3114 m_freem(m); 3115 return (ENOBUFS); 3116 } 3117 3118 if (rxs->rxs_mbuf != NULL) 3119 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3120 3121 rxs->rxs_mbuf = m; 3122 3123 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3124 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3125 BUS_DMA_READ|BUS_DMA_NOWAIT); 3126 if (error) { 3127 /* XXX XXX XXX */ 3128 printf("%s: unable to load rx DMA map %d, error = %d\n", 3129 sc->sc_dev.dv_xname, idx, error); 3130 panic("wm_add_rxbuf"); 3131 } 3132 3133 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3134 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3135 3136 WM_INIT_RXDESC(sc, idx); 3137 3138 return (0); 3139 } 3140 3141 /* 3142 * wm_set_ral: 3143 * 3144 * Set an entery in the receive address list. 3145 */ 3146 static void 3147 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3148 { 3149 uint32_t ral_lo, ral_hi; 3150 3151 if (enaddr != NULL) { 3152 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3153 (enaddr[3] << 24); 3154 ral_hi = enaddr[4] | (enaddr[5] << 8); 3155 ral_hi |= RAL_AV; 3156 } else { 3157 ral_lo = 0; 3158 ral_hi = 0; 3159 } 3160 3161 if (sc->sc_type >= WM_T_82544) { 3162 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3163 ral_lo); 3164 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3165 ral_hi); 3166 } else { 3167 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3168 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3169 } 3170 } 3171 3172 /* 3173 * wm_mchash: 3174 * 3175 * Compute the hash of the multicast address for the 4096-bit 3176 * multicast filter. 3177 */ 3178 static uint32_t 3179 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3180 { 3181 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3182 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3183 uint32_t hash; 3184 3185 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3186 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3187 3188 return (hash & 0xfff); 3189 } 3190 3191 /* 3192 * wm_set_filter: 3193 * 3194 * Set up the receive filter. 3195 */ 3196 static void 3197 wm_set_filter(struct wm_softc *sc) 3198 { 3199 struct ethercom *ec = &sc->sc_ethercom; 3200 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3201 struct ether_multi *enm; 3202 struct ether_multistep step; 3203 bus_addr_t mta_reg; 3204 uint32_t hash, reg, bit; 3205 int i; 3206 3207 if (sc->sc_type >= WM_T_82544) 3208 mta_reg = WMREG_CORDOVA_MTA; 3209 else 3210 mta_reg = WMREG_MTA; 3211 3212 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3213 3214 if (ifp->if_flags & IFF_BROADCAST) 3215 sc->sc_rctl |= RCTL_BAM; 3216 if (ifp->if_flags & IFF_PROMISC) { 3217 sc->sc_rctl |= RCTL_UPE; 3218 goto allmulti; 3219 } 3220 3221 /* 3222 * Set the station address in the first RAL slot, and 3223 * clear the remaining slots. 3224 */ 3225 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3226 for (i = 1; i < WM_RAL_TABSIZE; i++) 3227 wm_set_ral(sc, NULL, i); 3228 3229 /* Clear out the multicast table. */ 3230 for (i = 0; i < WM_MC_TABSIZE; i++) 3231 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3232 3233 ETHER_FIRST_MULTI(step, ec, enm); 3234 while (enm != NULL) { 3235 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3236 /* 3237 * We must listen to a range of multicast addresses. 3238 * For now, just accept all multicasts, rather than 3239 * trying to set only those filter bits needed to match 3240 * the range. (At this time, the only use of address 3241 * ranges is for IP multicast routing, for which the 3242 * range is big enough to require all bits set.) 3243 */ 3244 goto allmulti; 3245 } 3246 3247 hash = wm_mchash(sc, enm->enm_addrlo); 3248 3249 reg = (hash >> 5) & 0x7f; 3250 bit = hash & 0x1f; 3251 3252 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3253 hash |= 1U << bit; 3254 3255 /* XXX Hardware bug?? */ 3256 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3257 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3258 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3259 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3260 } else 3261 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3262 3263 ETHER_NEXT_MULTI(step, enm); 3264 } 3265 3266 ifp->if_flags &= ~IFF_ALLMULTI; 3267 goto setit; 3268 3269 allmulti: 3270 ifp->if_flags |= IFF_ALLMULTI; 3271 sc->sc_rctl |= RCTL_MPE; 3272 3273 setit: 3274 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3275 } 3276 3277 /* 3278 * wm_tbi_mediainit: 3279 * 3280 * Initialize media for use on 1000BASE-X devices. 3281 */ 3282 static void 3283 wm_tbi_mediainit(struct wm_softc *sc) 3284 { 3285 const char *sep = ""; 3286 3287 if (sc->sc_type < WM_T_82543) 3288 sc->sc_tipg = TIPG_WM_DFLT; 3289 else 3290 sc->sc_tipg = TIPG_LG_DFLT; 3291 3292 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3293 wm_tbi_mediastatus); 3294 3295 /* 3296 * SWD Pins: 3297 * 3298 * 0 = Link LED (output) 3299 * 1 = Loss Of Signal (input) 3300 */ 3301 sc->sc_ctrl |= CTRL_SWDPIO(0); 3302 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3303 3304 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3305 3306 #define ADD(ss, mm, dd) \ 3307 do { \ 3308 aprint_normal("%s%s", sep, ss); \ 3309 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3310 sep = ", "; \ 3311 } while (/*CONSTCOND*/0) 3312 3313 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3314 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3315 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3316 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3317 aprint_normal("\n"); 3318 3319 #undef ADD 3320 3321 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3322 } 3323 3324 /* 3325 * wm_tbi_mediastatus: [ifmedia interface function] 3326 * 3327 * Get the current interface media status on a 1000BASE-X device. 3328 */ 3329 static void 3330 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3331 { 3332 struct wm_softc *sc = ifp->if_softc; 3333 uint32_t ctrl; 3334 3335 ifmr->ifm_status = IFM_AVALID; 3336 ifmr->ifm_active = IFM_ETHER; 3337 3338 if (sc->sc_tbi_linkup == 0) { 3339 ifmr->ifm_active |= IFM_NONE; 3340 return; 3341 } 3342 3343 ifmr->ifm_status |= IFM_ACTIVE; 3344 ifmr->ifm_active |= IFM_1000_SX; 3345 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3346 ifmr->ifm_active |= IFM_FDX; 3347 ctrl = CSR_READ(sc, WMREG_CTRL); 3348 if (ctrl & CTRL_RFCE) 3349 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3350 if (ctrl & CTRL_TFCE) 3351 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3352 } 3353 3354 /* 3355 * wm_tbi_mediachange: [ifmedia interface function] 3356 * 3357 * Set hardware to newly-selected media on a 1000BASE-X device. 3358 */ 3359 static int 3360 wm_tbi_mediachange(struct ifnet *ifp) 3361 { 3362 struct wm_softc *sc = ifp->if_softc; 3363 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3364 uint32_t status; 3365 int i; 3366 3367 sc->sc_txcw = ife->ifm_data; 3368 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3369 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3370 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3371 sc->sc_txcw |= TXCW_ANE; 3372 3373 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3374 delay(10000); 3375 3376 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3377 3378 sc->sc_tbi_anstate = 0; 3379 3380 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3381 /* Have signal; wait for the link to come up. */ 3382 for (i = 0; i < 50; i++) { 3383 delay(10000); 3384 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3385 break; 3386 } 3387 3388 status = CSR_READ(sc, WMREG_STATUS); 3389 if (status & STATUS_LU) { 3390 /* Link is up. */ 3391 DPRINTF(WM_DEBUG_LINK, 3392 ("%s: LINK: set media -> link up %s\n", 3393 sc->sc_dev.dv_xname, 3394 (status & STATUS_FD) ? "FDX" : "HDX")); 3395 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3396 sc->sc_fcrtl &= ~FCRTL_XONE; 3397 if (status & STATUS_FD) 3398 sc->sc_tctl |= 3399 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3400 else 3401 sc->sc_tctl |= 3402 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3403 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3404 sc->sc_fcrtl |= FCRTL_XONE; 3405 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3406 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3407 WMREG_OLD_FCRTL : WMREG_FCRTL, 3408 sc->sc_fcrtl); 3409 sc->sc_tbi_linkup = 1; 3410 } else { 3411 /* Link is down. */ 3412 DPRINTF(WM_DEBUG_LINK, 3413 ("%s: LINK: set media -> link down\n", 3414 sc->sc_dev.dv_xname)); 3415 sc->sc_tbi_linkup = 0; 3416 } 3417 } else { 3418 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3419 sc->sc_dev.dv_xname)); 3420 sc->sc_tbi_linkup = 0; 3421 } 3422 3423 wm_tbi_set_linkled(sc); 3424 3425 return (0); 3426 } 3427 3428 /* 3429 * wm_tbi_set_linkled: 3430 * 3431 * Update the link LED on 1000BASE-X devices. 3432 */ 3433 static void 3434 wm_tbi_set_linkled(struct wm_softc *sc) 3435 { 3436 3437 if (sc->sc_tbi_linkup) 3438 sc->sc_ctrl |= CTRL_SWDPIN(0); 3439 else 3440 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3441 3442 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3443 } 3444 3445 /* 3446 * wm_tbi_check_link: 3447 * 3448 * Check the link on 1000BASE-X devices. 3449 */ 3450 static void 3451 wm_tbi_check_link(struct wm_softc *sc) 3452 { 3453 uint32_t rxcw, ctrl, status; 3454 3455 if (sc->sc_tbi_anstate == 0) 3456 return; 3457 else if (sc->sc_tbi_anstate > 1) { 3458 DPRINTF(WM_DEBUG_LINK, 3459 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3460 sc->sc_tbi_anstate)); 3461 sc->sc_tbi_anstate--; 3462 return; 3463 } 3464 3465 sc->sc_tbi_anstate = 0; 3466 3467 rxcw = CSR_READ(sc, WMREG_RXCW); 3468 ctrl = CSR_READ(sc, WMREG_CTRL); 3469 status = CSR_READ(sc, WMREG_STATUS); 3470 3471 if ((status & STATUS_LU) == 0) { 3472 DPRINTF(WM_DEBUG_LINK, 3473 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3474 sc->sc_tbi_linkup = 0; 3475 } else { 3476 DPRINTF(WM_DEBUG_LINK, 3477 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3478 (status & STATUS_FD) ? "FDX" : "HDX")); 3479 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3480 sc->sc_fcrtl &= ~FCRTL_XONE; 3481 if (status & STATUS_FD) 3482 sc->sc_tctl |= 3483 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3484 else 3485 sc->sc_tctl |= 3486 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3487 if (ctrl & CTRL_TFCE) 3488 sc->sc_fcrtl |= FCRTL_XONE; 3489 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3490 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3491 WMREG_OLD_FCRTL : WMREG_FCRTL, 3492 sc->sc_fcrtl); 3493 sc->sc_tbi_linkup = 1; 3494 } 3495 3496 wm_tbi_set_linkled(sc); 3497 } 3498 3499 /* 3500 * wm_gmii_reset: 3501 * 3502 * Reset the PHY. 3503 */ 3504 static void 3505 wm_gmii_reset(struct wm_softc *sc) 3506 { 3507 uint32_t reg; 3508 3509 if (sc->sc_type >= WM_T_82544) { 3510 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3511 delay(20000); 3512 3513 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3514 delay(20000); 3515 } else { 3516 /* The PHY reset pin is active-low. */ 3517 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3518 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3519 CTRL_EXT_SWDPIN(4)); 3520 reg |= CTRL_EXT_SWDPIO(4); 3521 3522 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3523 delay(10); 3524 3525 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3526 delay(10); 3527 3528 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3529 delay(10); 3530 #if 0 3531 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3532 #endif 3533 } 3534 } 3535 3536 /* 3537 * wm_gmii_mediainit: 3538 * 3539 * Initialize media for use on 1000BASE-T devices. 3540 */ 3541 static void 3542 wm_gmii_mediainit(struct wm_softc *sc) 3543 { 3544 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3545 3546 /* We have MII. */ 3547 sc->sc_flags |= WM_F_HAS_MII; 3548 3549 sc->sc_tipg = TIPG_1000T_DFLT; 3550 3551 /* 3552 * Let the chip set speed/duplex on its own based on 3553 * signals from the PHY. 3554 */ 3555 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3556 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3557 3558 /* Initialize our media structures and probe the GMII. */ 3559 sc->sc_mii.mii_ifp = ifp; 3560 3561 if (sc->sc_type >= WM_T_82544) { 3562 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3563 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3564 } else { 3565 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3566 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3567 } 3568 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3569 3570 wm_gmii_reset(sc); 3571 3572 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3573 wm_gmii_mediastatus); 3574 3575 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3576 MII_OFFSET_ANY, MIIF_DOPAUSE); 3577 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3578 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3579 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3580 } else 3581 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3582 } 3583 3584 /* 3585 * wm_gmii_mediastatus: [ifmedia interface function] 3586 * 3587 * Get the current interface media status on a 1000BASE-T device. 3588 */ 3589 static void 3590 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3591 { 3592 struct wm_softc *sc = ifp->if_softc; 3593 3594 mii_pollstat(&sc->sc_mii); 3595 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3596 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3597 sc->sc_flowflags; 3598 } 3599 3600 /* 3601 * wm_gmii_mediachange: [ifmedia interface function] 3602 * 3603 * Set hardware to newly-selected media on a 1000BASE-T device. 3604 */ 3605 static int 3606 wm_gmii_mediachange(struct ifnet *ifp) 3607 { 3608 struct wm_softc *sc = ifp->if_softc; 3609 3610 if (ifp->if_flags & IFF_UP) 3611 mii_mediachg(&sc->sc_mii); 3612 return (0); 3613 } 3614 3615 #define MDI_IO CTRL_SWDPIN(2) 3616 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3617 #define MDI_CLK CTRL_SWDPIN(3) 3618 3619 static void 3620 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3621 { 3622 uint32_t i, v; 3623 3624 v = CSR_READ(sc, WMREG_CTRL); 3625 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3626 v |= MDI_DIR | CTRL_SWDPIO(3); 3627 3628 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3629 if (data & i) 3630 v |= MDI_IO; 3631 else 3632 v &= ~MDI_IO; 3633 CSR_WRITE(sc, WMREG_CTRL, v); 3634 delay(10); 3635 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3636 delay(10); 3637 CSR_WRITE(sc, WMREG_CTRL, v); 3638 delay(10); 3639 } 3640 } 3641 3642 static uint32_t 3643 i82543_mii_recvbits(struct wm_softc *sc) 3644 { 3645 uint32_t v, i, data = 0; 3646 3647 v = CSR_READ(sc, WMREG_CTRL); 3648 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3649 v |= CTRL_SWDPIO(3); 3650 3651 CSR_WRITE(sc, WMREG_CTRL, v); 3652 delay(10); 3653 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3654 delay(10); 3655 CSR_WRITE(sc, WMREG_CTRL, v); 3656 delay(10); 3657 3658 for (i = 0; i < 16; i++) { 3659 data <<= 1; 3660 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3661 delay(10); 3662 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3663 data |= 1; 3664 CSR_WRITE(sc, WMREG_CTRL, v); 3665 delay(10); 3666 } 3667 3668 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3669 delay(10); 3670 CSR_WRITE(sc, WMREG_CTRL, v); 3671 delay(10); 3672 3673 return (data); 3674 } 3675 3676 #undef MDI_IO 3677 #undef MDI_DIR 3678 #undef MDI_CLK 3679 3680 /* 3681 * wm_gmii_i82543_readreg: [mii interface function] 3682 * 3683 * Read a PHY register on the GMII (i82543 version). 3684 */ 3685 static int 3686 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3687 { 3688 struct wm_softc *sc = (void *) self; 3689 int rv; 3690 3691 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3692 i82543_mii_sendbits(sc, reg | (phy << 5) | 3693 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3694 rv = i82543_mii_recvbits(sc) & 0xffff; 3695 3696 DPRINTF(WM_DEBUG_GMII, 3697 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3698 sc->sc_dev.dv_xname, phy, reg, rv)); 3699 3700 return (rv); 3701 } 3702 3703 /* 3704 * wm_gmii_i82543_writereg: [mii interface function] 3705 * 3706 * Write a PHY register on the GMII (i82543 version). 3707 */ 3708 static void 3709 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3710 { 3711 struct wm_softc *sc = (void *) self; 3712 3713 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3714 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3715 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3716 (MII_COMMAND_START << 30), 32); 3717 } 3718 3719 /* 3720 * wm_gmii_i82544_readreg: [mii interface function] 3721 * 3722 * Read a PHY register on the GMII. 3723 */ 3724 static int 3725 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3726 { 3727 struct wm_softc *sc = (void *) self; 3728 uint32_t mdic = 0; 3729 int i, rv; 3730 3731 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3732 MDIC_REGADD(reg)); 3733 3734 for (i = 0; i < 100; i++) { 3735 mdic = CSR_READ(sc, WMREG_MDIC); 3736 if (mdic & MDIC_READY) 3737 break; 3738 delay(10); 3739 } 3740 3741 if ((mdic & MDIC_READY) == 0) { 3742 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3743 sc->sc_dev.dv_xname, phy, reg); 3744 rv = 0; 3745 } else if (mdic & MDIC_E) { 3746 #if 0 /* This is normal if no PHY is present. */ 3747 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3748 sc->sc_dev.dv_xname, phy, reg); 3749 #endif 3750 rv = 0; 3751 } else { 3752 rv = MDIC_DATA(mdic); 3753 if (rv == 0xffff) 3754 rv = 0; 3755 } 3756 3757 return (rv); 3758 } 3759 3760 /* 3761 * wm_gmii_i82544_writereg: [mii interface function] 3762 * 3763 * Write a PHY register on the GMII. 3764 */ 3765 static void 3766 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3767 { 3768 struct wm_softc *sc = (void *) self; 3769 uint32_t mdic = 0; 3770 int i; 3771 3772 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3773 MDIC_REGADD(reg) | MDIC_DATA(val)); 3774 3775 for (i = 0; i < 100; i++) { 3776 mdic = CSR_READ(sc, WMREG_MDIC); 3777 if (mdic & MDIC_READY) 3778 break; 3779 delay(10); 3780 } 3781 3782 if ((mdic & MDIC_READY) == 0) 3783 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3784 sc->sc_dev.dv_xname, phy, reg); 3785 else if (mdic & MDIC_E) 3786 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3787 sc->sc_dev.dv_xname, phy, reg); 3788 } 3789 3790 /* 3791 * wm_gmii_statchg: [mii interface function] 3792 * 3793 * Callback from MII layer when media changes. 3794 */ 3795 static void 3796 wm_gmii_statchg(struct device *self) 3797 { 3798 struct wm_softc *sc = (void *) self; 3799 struct mii_data *mii = &sc->sc_mii; 3800 3801 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3802 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3803 sc->sc_fcrtl &= ~FCRTL_XONE; 3804 3805 /* 3806 * Get flow control negotiation result. 3807 */ 3808 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3809 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3810 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3811 mii->mii_media_active &= ~IFM_ETH_FMASK; 3812 } 3813 3814 if (sc->sc_flowflags & IFM_FLOW) { 3815 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3816 sc->sc_ctrl |= CTRL_TFCE; 3817 sc->sc_fcrtl |= FCRTL_XONE; 3818 } 3819 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3820 sc->sc_ctrl |= CTRL_RFCE; 3821 } 3822 3823 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3824 DPRINTF(WM_DEBUG_LINK, 3825 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3826 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3827 } else { 3828 DPRINTF(WM_DEBUG_LINK, 3829 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3830 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3831 } 3832 3833 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3834 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3835 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3836 : WMREG_FCRTL, sc->sc_fcrtl); 3837 } 3838
Indexes created Wed Sep 24 02:09:48 GMT 2025