if_wm.c revision 1.101
1 /* $NetBSD: if_wm.c,v 1.101 2005/03/19 11:58:03 tron Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.101 2005/03/19 11:58:03 tron Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 280 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 281 282 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 283 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 284 285 struct evcnt sc_ev_tu; /* Tx underrun */ 286 287 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 288 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 289 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 290 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 291 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 292 #endif /* WM_EVENT_COUNTERS */ 293 294 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 295 296 int sc_txfree; /* number of free Tx descriptors */ 297 int sc_txnext; /* next ready Tx descriptor */ 298 299 int sc_txsfree; /* number of free Tx jobs */ 300 int sc_txsnext; /* next free Tx job */ 301 int sc_txsdirty; /* dirty Tx jobs */ 302 303 /* These 5 variables are used only on the 82547. */ 304 int sc_txfifo_size; /* Tx FIFO size */ 305 int sc_txfifo_head; /* current head of FIFO */ 306 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 307 int sc_txfifo_stall; /* Tx FIFO is stalled */ 308 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 309 310 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 311 312 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 313 int sc_rxdiscard; 314 int sc_rxlen; 315 struct mbuf *sc_rxhead; 316 struct mbuf *sc_rxtail; 317 struct mbuf **sc_rxtailp; 318 319 uint32_t sc_ctrl; /* prototype CTRL register */ 320 #if 0 321 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 322 #endif 323 uint32_t sc_icr; /* prototype interrupt bits */ 324 uint32_t sc_itr; /* prototype intr throttling reg */ 325 uint32_t sc_tctl; /* prototype TCTL register */ 326 uint32_t sc_rctl; /* prototype RCTL register */ 327 uint32_t sc_txcw; /* prototype TXCW register */ 328 uint32_t sc_tipg; /* prototype TIPG register */ 329 uint32_t sc_fcrtl; /* prototype FCRTL register */ 330 uint32_t sc_pba; /* prototype PBA register */ 331 332 int sc_tbi_linkup; /* TBI link status */ 333 int sc_tbi_anstate; /* autonegotiation state */ 334 335 int sc_mchash_type; /* multicast filter offset */ 336 337 #if NRND > 0 338 rndsource_element_t rnd_source; /* random source */ 339 #endif 340 }; 341 342 #define WM_RXCHAIN_RESET(sc) \ 343 do { \ 344 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 345 *(sc)->sc_rxtailp = NULL; \ 346 (sc)->sc_rxlen = 0; \ 347 } while (/*CONSTCOND*/0) 348 349 #define WM_RXCHAIN_LINK(sc, m) \ 350 do { \ 351 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 352 (sc)->sc_rxtailp = &(m)->m_next; \ 353 } while (/*CONSTCOND*/0) 354 355 /* sc_flags */ 356 #define WM_F_HAS_MII 0x01 /* has MII */ 357 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 358 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 359 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 360 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 361 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 362 #define WM_F_CSA 0x80 /* bus is CSA */ 363 364 #ifdef WM_EVENT_COUNTERS 365 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 366 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 367 #else 368 #define WM_EVCNT_INCR(ev) /* nothing */ 369 #define WM_EVCNT_ADD(ev, val) /* nothing */ 370 #endif 371 372 #define CSR_READ(sc, reg) \ 373 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 374 #define CSR_WRITE(sc, reg, val) \ 375 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 376 #define CSR_WRITE_FLUSH(sc) \ 377 (void) CSR_READ((sc), WMREG_STATUS) 378 379 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 380 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 381 382 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 383 #define WM_CDTXADDR_HI(sc, x) \ 384 (sizeof(bus_addr_t) == 8 ? \ 385 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 386 387 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 388 #define WM_CDRXADDR_HI(sc, x) \ 389 (sizeof(bus_addr_t) == 8 ? \ 390 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 391 392 #define WM_CDTXSYNC(sc, x, n, ops) \ 393 do { \ 394 int __x, __n; \ 395 \ 396 __x = (x); \ 397 __n = (n); \ 398 \ 399 /* If it will wrap around, sync to the end of the ring. */ \ 400 if ((__x + __n) > WM_NTXDESC(sc)) { \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 403 (WM_NTXDESC(sc) - __x), (ops)); \ 404 __n -= (WM_NTXDESC(sc) - __x); \ 405 __x = 0; \ 406 } \ 407 \ 408 /* Now sync whatever is left. */ \ 409 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 410 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 411 } while (/*CONSTCOND*/0) 412 413 #define WM_CDRXSYNC(sc, x, ops) \ 414 do { \ 415 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 416 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 417 } while (/*CONSTCOND*/0) 418 419 #define WM_INIT_RXDESC(sc, x) \ 420 do { \ 421 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 422 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 423 struct mbuf *__m = __rxs->rxs_mbuf; \ 424 \ 425 /* \ 426 * Note: We scoot the packet forward 2 bytes in the buffer \ 427 * so that the payload after the Ethernet header is aligned \ 428 * to a 4-byte boundary. \ 429 * \ 430 * XXX BRAINDAMAGE ALERT! \ 431 * The stupid chip uses the same size for every buffer, which \ 432 * is set in the Receive Control register. We are using the 2K \ 433 * size option, but what we REALLY want is (2K - 2)! For this \ 434 * reason, we can't "scoot" packets longer than the standard \ 435 * Ethernet MTU. On strict-alignment platforms, if the total \ 436 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 437 * the upper layer copy the headers. \ 438 */ \ 439 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 440 \ 441 wm_set_dma_addr(&__rxd->wrx_addr, \ 442 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 443 __rxd->wrx_len = 0; \ 444 __rxd->wrx_cksum = 0; \ 445 __rxd->wrx_status = 0; \ 446 __rxd->wrx_errors = 0; \ 447 __rxd->wrx_special = 0; \ 448 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 449 \ 450 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 451 } while (/*CONSTCOND*/0) 452 453 static void wm_start(struct ifnet *); 454 static void wm_watchdog(struct ifnet *); 455 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 456 static int wm_init(struct ifnet *); 457 static void wm_stop(struct ifnet *, int); 458 459 static void wm_shutdown(void *); 460 461 static void wm_reset(struct wm_softc *); 462 static void wm_rxdrain(struct wm_softc *); 463 static int wm_add_rxbuf(struct wm_softc *, int); 464 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 465 static void wm_tick(void *); 466 467 static void wm_set_filter(struct wm_softc *); 468 469 static int wm_intr(void *); 470 static void wm_txintr(struct wm_softc *); 471 static void wm_rxintr(struct wm_softc *); 472 static void wm_linkintr(struct wm_softc *, uint32_t); 473 474 static void wm_tbi_mediainit(struct wm_softc *); 475 static int wm_tbi_mediachange(struct ifnet *); 476 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 477 478 static void wm_tbi_set_linkled(struct wm_softc *); 479 static void wm_tbi_check_link(struct wm_softc *); 480 481 static void wm_gmii_reset(struct wm_softc *); 482 483 static int wm_gmii_i82543_readreg(struct device *, int, int); 484 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 485 486 static int wm_gmii_i82544_readreg(struct device *, int, int); 487 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 488 489 static void wm_gmii_statchg(struct device *); 490 491 static void wm_gmii_mediainit(struct wm_softc *); 492 static int wm_gmii_mediachange(struct ifnet *); 493 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 494 495 static int wm_match(struct device *, struct cfdata *, void *); 496 static void wm_attach(struct device *, struct device *, void *); 497 498 CFATTACH_DECL(wm, sizeof(struct wm_softc), 499 wm_match, wm_attach, NULL, NULL); 500 501 static void wm_82547_txfifo_stall(void *); 502 503 /* 504 * Devices supported by this driver. 505 */ 506 static const struct wm_product { 507 pci_vendor_id_t wmp_vendor; 508 pci_product_id_t wmp_product; 509 const char *wmp_name; 510 wm_chip_type wmp_type; 511 int wmp_flags; 512 #define WMP_F_1000X 0x01 513 #define WMP_F_1000T 0x02 514 } wm_products[] = { 515 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 516 "Intel i82542 1000BASE-X Ethernet", 517 WM_T_82542_2_1, WMP_F_1000X }, 518 519 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 520 "Intel i82543GC 1000BASE-X Ethernet", 521 WM_T_82543, WMP_F_1000X }, 522 523 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 524 "Intel i82543GC 1000BASE-T Ethernet", 525 WM_T_82543, WMP_F_1000T }, 526 527 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 528 "Intel i82544EI 1000BASE-T Ethernet", 529 WM_T_82544, WMP_F_1000T }, 530 531 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 532 "Intel i82544EI 1000BASE-X Ethernet", 533 WM_T_82544, WMP_F_1000X }, 534 535 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 536 "Intel i82544GC 1000BASE-T Ethernet", 537 WM_T_82544, WMP_F_1000T }, 538 539 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 540 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 541 WM_T_82544, WMP_F_1000T }, 542 543 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 544 "Intel i82540EM 1000BASE-T Ethernet", 545 WM_T_82540, WMP_F_1000T }, 546 547 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 548 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 549 WM_T_82540, WMP_F_1000T }, 550 551 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 552 "Intel i82540EP 1000BASE-T Ethernet", 553 WM_T_82540, WMP_F_1000T }, 554 555 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 556 "Intel i82540EP 1000BASE-T Ethernet", 557 WM_T_82540, WMP_F_1000T }, 558 559 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 560 "Intel i82540EP 1000BASE-T Ethernet", 561 WM_T_82540, WMP_F_1000T }, 562 563 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 564 "Intel i82545EM 1000BASE-T Ethernet", 565 WM_T_82545, WMP_F_1000T }, 566 567 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 568 "Intel i82545GM 1000BASE-T Ethernet", 569 WM_T_82545_3, WMP_F_1000T }, 570 571 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 572 "Intel i82545GM 1000BASE-X Ethernet", 573 WM_T_82545_3, WMP_F_1000X }, 574 #if 0 575 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 576 "Intel i82545GM Gigabit Ethernet (SERDES)", 577 WM_T_82545_3, WMP_F_SERDES }, 578 #endif 579 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 580 "Intel i82546EB 1000BASE-T Ethernet", 581 WM_T_82546, WMP_F_1000T }, 582 583 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 584 "Intel i82546EB 1000BASE-T Ethernet", 585 WM_T_82546, WMP_F_1000T }, 586 587 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 588 "Intel i82545EM 1000BASE-X Ethernet", 589 WM_T_82545, WMP_F_1000X }, 590 591 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 592 "Intel i82546EB 1000BASE-X Ethernet", 593 WM_T_82546, WMP_F_1000X }, 594 595 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 596 "Intel i82546GB 1000BASE-T Ethernet", 597 WM_T_82546_3, WMP_F_1000T }, 598 599 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 600 "Intel i82546GB 1000BASE-X Ethernet", 601 WM_T_82546_3, WMP_F_1000X }, 602 #if 0 603 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 604 "Intel i82546GB Gigabit Ethernet (SERDES)", 605 WM_T_82546_3, WMP_F_SERDES }, 606 #endif 607 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 608 "Intel i82541EI 1000BASE-T Ethernet", 609 WM_T_82541, WMP_F_1000T }, 610 611 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 612 "Intel i82541EI Mobile 1000BASE-T Ethernet", 613 WM_T_82541, WMP_F_1000T }, 614 615 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 616 "Intel i82541ER 1000BASE-T Ethernet", 617 WM_T_82541_2, WMP_F_1000T }, 618 619 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 620 "Intel i82541GI 1000BASE-T Ethernet", 621 WM_T_82541_2, WMP_F_1000T }, 622 623 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 624 "Intel i82541GI Mobile 1000BASE-T Ethernet", 625 WM_T_82541_2, WMP_F_1000T }, 626 627 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 628 "Intel i82541PI 1000BASE-T Ethernet", 629 WM_T_82541_2, WMP_F_1000T }, 630 631 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 632 "Intel i82547EI 1000BASE-T Ethernet", 633 WM_T_82547, WMP_F_1000T }, 634 635 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 636 "Intel i82547GI 1000BASE-T Ethernet", 637 WM_T_82547_2, WMP_F_1000T }, 638 { 0, 0, 639 NULL, 640 0, 0 }, 641 }; 642 643 #ifdef WM_EVENT_COUNTERS 644 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 645 #endif /* WM_EVENT_COUNTERS */ 646 647 #if 0 /* Not currently used */ 648 static __inline uint32_t 649 wm_io_read(struct wm_softc *sc, int reg) 650 { 651 652 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 653 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 654 } 655 #endif 656 657 static __inline void 658 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 659 { 660 661 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 662 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 663 } 664 665 static __inline void 666 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 667 { 668 wa->wa_low = htole32(v & 0xffffffffU); 669 if (sizeof(bus_addr_t) == 8) 670 wa->wa_high = htole32((uint64_t) v >> 32); 671 else 672 wa->wa_high = 0; 673 } 674 675 static const struct wm_product * 676 wm_lookup(const struct pci_attach_args *pa) 677 { 678 const struct wm_product *wmp; 679 680 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 681 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 682 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 683 return (wmp); 684 } 685 return (NULL); 686 } 687 688 static int 689 wm_match(struct device *parent, struct cfdata *cf, void *aux) 690 { 691 struct pci_attach_args *pa = aux; 692 693 if (wm_lookup(pa) != NULL) 694 return (1); 695 696 return (0); 697 } 698 699 static void 700 wm_attach(struct device *parent, struct device *self, void *aux) 701 { 702 struct wm_softc *sc = (void *) self; 703 struct pci_attach_args *pa = aux; 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 pci_chipset_tag_t pc = pa->pa_pc; 706 pci_intr_handle_t ih; 707 size_t cdata_size; 708 const char *intrstr = NULL; 709 const char *eetype; 710 bus_space_tag_t memt; 711 bus_space_handle_t memh; 712 bus_dma_segment_t seg; 713 int memh_valid; 714 int i, rseg, error; 715 const struct wm_product *wmp; 716 uint8_t enaddr[ETHER_ADDR_LEN]; 717 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 718 pcireg_t preg, memtype; 719 uint32_t reg; 720 int pmreg; 721 722 callout_init(&sc->sc_tick_ch); 723 724 wmp = wm_lookup(pa); 725 if (wmp == NULL) { 726 printf("\n"); 727 panic("wm_attach: impossible"); 728 } 729 730 if (pci_dma64_available(pa)) 731 sc->sc_dmat = pa->pa_dmat64; 732 else 733 sc->sc_dmat = pa->pa_dmat; 734 735 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 736 aprint_naive(": Ethernet controller\n"); 737 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 738 739 sc->sc_type = wmp->wmp_type; 740 if (sc->sc_type < WM_T_82543) { 741 if (preg < 2) { 742 aprint_error("%s: i82542 must be at least rev. 2\n", 743 sc->sc_dev.dv_xname); 744 return; 745 } 746 if (preg < 3) 747 sc->sc_type = WM_T_82542_2_0; 748 } 749 750 /* 751 * Map the device. All devices support memory-mapped acccess, 752 * and it is really required for normal operation. 753 */ 754 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 755 switch (memtype) { 756 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 757 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 758 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 759 memtype, 0, &memt, &memh, NULL, NULL) == 0); 760 break; 761 default: 762 memh_valid = 0; 763 } 764 765 if (memh_valid) { 766 sc->sc_st = memt; 767 sc->sc_sh = memh; 768 } else { 769 aprint_error("%s: unable to map device registers\n", 770 sc->sc_dev.dv_xname); 771 return; 772 } 773 774 /* 775 * In addition, i82544 and later support I/O mapped indirect 776 * register access. It is not desirable (nor supported in 777 * this driver) to use it for normal operation, though it is 778 * required to work around bugs in some chip versions. 779 */ 780 if (sc->sc_type >= WM_T_82544) { 781 /* First we have to find the I/O BAR. */ 782 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 783 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 784 PCI_MAPREG_TYPE_IO) 785 break; 786 } 787 if (i == PCI_MAPREG_END) 788 aprint_error("%s: WARNING: unable to find I/O BAR\n", 789 sc->sc_dev.dv_xname); 790 else { 791 /* 792 * The i8254x doesn't apparently respond when the 793 * I/O BAR is 0, which looks somewhat like it's not 794 * been configured. 795 */ 796 preg = pci_conf_read(pc, pa->pa_tag, i); 797 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 798 aprint_error("%s: WARNING: I/O BAR at zero.\n", 799 sc->sc_dev.dv_xname); 800 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 801 0, &sc->sc_iot, &sc->sc_ioh, 802 NULL, NULL) == 0) { 803 sc->sc_flags |= WM_F_IOH_VALID; 804 } else { 805 aprint_error("%s: WARNING: unable to map " 806 "I/O space\n", sc->sc_dev.dv_xname); 807 } 808 } 809 810 } 811 812 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 813 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 814 preg |= PCI_COMMAND_MASTER_ENABLE; 815 if (sc->sc_type < WM_T_82542_2_1) 816 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 817 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 818 819 /* Get it out of power save mode, if needed. */ 820 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 821 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 822 PCI_PMCSR_STATE_MASK; 823 if (preg == PCI_PMCSR_STATE_D3) { 824 /* 825 * The card has lost all configuration data in 826 * this state, so punt. 827 */ 828 aprint_error("%s: unable to wake from power state D3\n", 829 sc->sc_dev.dv_xname); 830 return; 831 } 832 if (preg != PCI_PMCSR_STATE_D0) { 833 aprint_normal("%s: waking up from power state D%d\n", 834 sc->sc_dev.dv_xname, preg); 835 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 836 PCI_PMCSR_STATE_D0); 837 } 838 } 839 840 /* 841 * Map and establish our interrupt. 842 */ 843 if (pci_intr_map(pa, &ih)) { 844 aprint_error("%s: unable to map interrupt\n", 845 sc->sc_dev.dv_xname); 846 return; 847 } 848 intrstr = pci_intr_string(pc, ih); 849 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 850 if (sc->sc_ih == NULL) { 851 aprint_error("%s: unable to establish interrupt", 852 sc->sc_dev.dv_xname); 853 if (intrstr != NULL) 854 aprint_normal(" at %s", intrstr); 855 aprint_normal("\n"); 856 return; 857 } 858 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 859 860 /* 861 * Determine a few things about the bus we're connected to. 862 */ 863 if (sc->sc_type < WM_T_82543) { 864 /* We don't really know the bus characteristics here. */ 865 sc->sc_bus_speed = 33; 866 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 867 /* 868 * CSA (Communication Streaming Architecture) is about as fast 869 * a 32-bit 66MHz PCI Bus. 870 */ 871 sc->sc_flags |= WM_F_CSA; 872 sc->sc_bus_speed = 66; 873 aprint_verbose("%s: Communication Streaming Architecture\n", 874 sc->sc_dev.dv_xname); 875 if (sc->sc_type == WM_T_82547) { 876 callout_init(&sc->sc_txfifo_ch); 877 callout_setfunc(&sc->sc_txfifo_ch, 878 wm_82547_txfifo_stall, sc); 879 aprint_verbose("%s: using 82547 Tx FIFO stall " 880 "work-around\n", sc->sc_dev.dv_xname); 881 } 882 } else { 883 reg = CSR_READ(sc, WMREG_STATUS); 884 if (reg & STATUS_BUS64) 885 sc->sc_flags |= WM_F_BUS64; 886 if (sc->sc_type >= WM_T_82544 && 887 (reg & STATUS_PCIX_MODE) != 0) { 888 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 889 890 sc->sc_flags |= WM_F_PCIX; 891 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 892 PCI_CAP_PCIX, 893 &sc->sc_pcix_offset, NULL) == 0) 894 aprint_error("%s: unable to find PCIX " 895 "capability\n", sc->sc_dev.dv_xname); 896 else if (sc->sc_type != WM_T_82545_3 && 897 sc->sc_type != WM_T_82546_3) { 898 /* 899 * Work around a problem caused by the BIOS 900 * setting the max memory read byte count 901 * incorrectly. 902 */ 903 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 904 sc->sc_pcix_offset + PCI_PCIX_CMD); 905 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 906 sc->sc_pcix_offset + PCI_PCIX_STATUS); 907 908 bytecnt = 909 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 910 PCI_PCIX_CMD_BYTECNT_SHIFT; 911 maxb = 912 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 913 PCI_PCIX_STATUS_MAXB_SHIFT; 914 if (bytecnt > maxb) { 915 aprint_verbose("%s: resetting PCI-X " 916 "MMRBC: %d -> %d\n", 917 sc->sc_dev.dv_xname, 918 512 << bytecnt, 512 << maxb); 919 pcix_cmd = (pcix_cmd & 920 ~PCI_PCIX_CMD_BYTECNT_MASK) | 921 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 922 pci_conf_write(pa->pa_pc, pa->pa_tag, 923 sc->sc_pcix_offset + PCI_PCIX_CMD, 924 pcix_cmd); 925 } 926 } 927 } 928 /* 929 * The quad port adapter is special; it has a PCIX-PCIX 930 * bridge on the board, and can run the secondary bus at 931 * a higher speed. 932 */ 933 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 934 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 935 : 66; 936 } else if (sc->sc_flags & WM_F_PCIX) { 937 switch (reg & STATUS_PCIXSPD_MASK) { 938 case STATUS_PCIXSPD_50_66: 939 sc->sc_bus_speed = 66; 940 break; 941 case STATUS_PCIXSPD_66_100: 942 sc->sc_bus_speed = 100; 943 break; 944 case STATUS_PCIXSPD_100_133: 945 sc->sc_bus_speed = 133; 946 break; 947 default: 948 aprint_error( 949 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 950 sc->sc_dev.dv_xname, 951 reg & STATUS_PCIXSPD_MASK); 952 sc->sc_bus_speed = 66; 953 } 954 } else 955 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 956 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 957 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 958 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 959 } 960 961 /* 962 * Allocate the control data structures, and create and load the 963 * DMA map for it. 964 * 965 * NOTE: All Tx descriptors must be in the same 4G segment of 966 * memory. So must Rx descriptors. We simplify by allocating 967 * both sets within the same 4G segment. 968 */ 969 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 970 WM_NTXDESC_82542 : WM_NTXDESC_82544; 971 cdata_size = sc->sc_type < WM_T_82544 ? 972 sizeof(struct wm_control_data_82542) : 973 sizeof(struct wm_control_data_82544); 974 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 975 (bus_size_t) 0x100000000ULL, 976 &seg, 1, &rseg, 0)) != 0) { 977 aprint_error( 978 "%s: unable to allocate control data, error = %d\n", 979 sc->sc_dev.dv_xname, error); 980 goto fail_0; 981 } 982 983 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 984 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 985 aprint_error("%s: unable to map control data, error = %d\n", 986 sc->sc_dev.dv_xname, error); 987 goto fail_1; 988 } 989 990 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 991 0, 0, &sc->sc_cddmamap)) != 0) { 992 aprint_error("%s: unable to create control data DMA map, " 993 "error = %d\n", sc->sc_dev.dv_xname, error); 994 goto fail_2; 995 } 996 997 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 998 sc->sc_control_data, cdata_size, NULL, 999 0)) != 0) { 1000 aprint_error( 1001 "%s: unable to load control data DMA map, error = %d\n", 1002 sc->sc_dev.dv_xname, error); 1003 goto fail_3; 1004 } 1005 1006 1007 /* 1008 * Create the transmit buffer DMA maps. 1009 */ 1010 WM_TXQUEUELEN(sc) = 1011 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1012 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1013 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1014 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1015 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1016 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1017 aprint_error("%s: unable to create Tx DMA map %d, " 1018 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1019 goto fail_4; 1020 } 1021 } 1022 1023 /* 1024 * Create the receive buffer DMA maps. 1025 */ 1026 for (i = 0; i < WM_NRXDESC; i++) { 1027 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1028 MCLBYTES, 0, 0, 1029 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1030 aprint_error("%s: unable to create Rx DMA map %d, " 1031 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1032 goto fail_5; 1033 } 1034 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1035 } 1036 1037 /* 1038 * Reset the chip to a known state. 1039 */ 1040 wm_reset(sc); 1041 1042 /* 1043 * Get some information about the EEPROM. 1044 */ 1045 if (sc->sc_type >= WM_T_82540) 1046 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1047 if (sc->sc_type <= WM_T_82544) 1048 sc->sc_ee_addrbits = 6; 1049 else if (sc->sc_type <= WM_T_82546_3) { 1050 reg = CSR_READ(sc, WMREG_EECD); 1051 if (reg & EECD_EE_SIZE) 1052 sc->sc_ee_addrbits = 8; 1053 else 1054 sc->sc_ee_addrbits = 6; 1055 } else if (sc->sc_type <= WM_T_82547_2) { 1056 reg = CSR_READ(sc, WMREG_EECD); 1057 if (reg & EECD_EE_TYPE) { 1058 sc->sc_flags |= WM_F_EEPROM_SPI; 1059 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1060 } else 1061 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1062 } else { 1063 /* Assume everything else is SPI. */ 1064 reg = CSR_READ(sc, WMREG_EECD); 1065 sc->sc_flags |= WM_F_EEPROM_SPI; 1066 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1067 } 1068 if (sc->sc_flags & WM_F_EEPROM_SPI) 1069 eetype = "SPI"; 1070 else 1071 eetype = "MicroWire"; 1072 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1073 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1074 sc->sc_ee_addrbits, eetype); 1075 1076 /* 1077 * Read the Ethernet address from the EEPROM. 1078 */ 1079 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1080 sizeof(myea) / sizeof(myea[0]), myea)) { 1081 aprint_error("%s: unable to read Ethernet address\n", 1082 sc->sc_dev.dv_xname); 1083 return; 1084 } 1085 enaddr[0] = myea[0] & 0xff; 1086 enaddr[1] = myea[0] >> 8; 1087 enaddr[2] = myea[1] & 0xff; 1088 enaddr[3] = myea[1] >> 8; 1089 enaddr[4] = myea[2] & 0xff; 1090 enaddr[5] = myea[2] >> 8; 1091 1092 /* 1093 * Toggle the LSB of the MAC address on the second port 1094 * of the i82546. 1095 */ 1096 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1097 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1098 enaddr[5] ^= 1; 1099 } 1100 1101 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1102 ether_sprintf(enaddr)); 1103 1104 /* 1105 * Read the config info from the EEPROM, and set up various 1106 * bits in the control registers based on their contents. 1107 */ 1108 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1109 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1110 sc->sc_dev.dv_xname); 1111 return; 1112 } 1113 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1114 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1115 sc->sc_dev.dv_xname); 1116 return; 1117 } 1118 if (sc->sc_type >= WM_T_82544) { 1119 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1120 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1121 sc->sc_dev.dv_xname); 1122 return; 1123 } 1124 } 1125 1126 if (cfg1 & EEPROM_CFG1_ILOS) 1127 sc->sc_ctrl |= CTRL_ILOS; 1128 if (sc->sc_type >= WM_T_82544) { 1129 sc->sc_ctrl |= 1130 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1131 CTRL_SWDPIO_SHIFT; 1132 sc->sc_ctrl |= 1133 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1134 CTRL_SWDPINS_SHIFT; 1135 } else { 1136 sc->sc_ctrl |= 1137 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1138 CTRL_SWDPIO_SHIFT; 1139 } 1140 1141 #if 0 1142 if (sc->sc_type >= WM_T_82544) { 1143 if (cfg1 & EEPROM_CFG1_IPS0) 1144 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1145 if (cfg1 & EEPROM_CFG1_IPS1) 1146 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1147 sc->sc_ctrl_ext |= 1148 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1149 CTRL_EXT_SWDPIO_SHIFT; 1150 sc->sc_ctrl_ext |= 1151 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1152 CTRL_EXT_SWDPINS_SHIFT; 1153 } else { 1154 sc->sc_ctrl_ext |= 1155 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1156 CTRL_EXT_SWDPIO_SHIFT; 1157 } 1158 #endif 1159 1160 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1161 #if 0 1162 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1163 #endif 1164 1165 /* 1166 * Set up some register offsets that are different between 1167 * the i82542 and the i82543 and later chips. 1168 */ 1169 if (sc->sc_type < WM_T_82543) { 1170 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1171 sc->sc_tdt_reg = WMREG_OLD_TDT; 1172 } else { 1173 sc->sc_rdt_reg = WMREG_RDT; 1174 sc->sc_tdt_reg = WMREG_TDT; 1175 } 1176 1177 /* 1178 * Determine if we're TBI or GMII mode, and initialize the 1179 * media structures accordingly. 1180 */ 1181 if (sc->sc_type < WM_T_82543 || 1182 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1183 if (wmp->wmp_flags & WMP_F_1000T) 1184 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1185 "product!\n", sc->sc_dev.dv_xname); 1186 wm_tbi_mediainit(sc); 1187 } else { 1188 if (wmp->wmp_flags & WMP_F_1000X) 1189 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1190 "product!\n", sc->sc_dev.dv_xname); 1191 wm_gmii_mediainit(sc); 1192 } 1193 1194 ifp = &sc->sc_ethercom.ec_if; 1195 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1196 ifp->if_softc = sc; 1197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1198 ifp->if_ioctl = wm_ioctl; 1199 ifp->if_start = wm_start; 1200 ifp->if_watchdog = wm_watchdog; 1201 ifp->if_init = wm_init; 1202 ifp->if_stop = wm_stop; 1203 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1204 IFQ_SET_READY(&ifp->if_snd); 1205 1206 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1207 1208 /* 1209 * If we're a i82543 or greater, we can support VLANs. 1210 */ 1211 if (sc->sc_type >= WM_T_82543) 1212 sc->sc_ethercom.ec_capabilities |= 1213 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1214 1215 /* 1216 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1217 * on i82543 and later. 1218 */ 1219 if (sc->sc_type >= WM_T_82543) 1220 ifp->if_capabilities |= 1221 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1222 1223 /* 1224 * If we're a i82544 or greater (except i82547), we can do 1225 * TCP segmentation offload. 1226 */ 1227 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1228 ifp->if_capabilities |= IFCAP_TSOv4; 1229 1230 /* 1231 * Attach the interface. 1232 */ 1233 if_attach(ifp); 1234 ether_ifattach(ifp, enaddr); 1235 #if NRND > 0 1236 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1237 RND_TYPE_NET, 0); 1238 #endif 1239 1240 #ifdef WM_EVENT_COUNTERS 1241 /* Attach event counters. */ 1242 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1243 NULL, sc->sc_dev.dv_xname, "txsstall"); 1244 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1245 NULL, sc->sc_dev.dv_xname, "txdstall"); 1246 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1247 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1248 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1249 NULL, sc->sc_dev.dv_xname, "txdw"); 1250 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1251 NULL, sc->sc_dev.dv_xname, "txqe"); 1252 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1253 NULL, sc->sc_dev.dv_xname, "rxintr"); 1254 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1255 NULL, sc->sc_dev.dv_xname, "linkintr"); 1256 1257 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1258 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1259 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1261 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1262 NULL, sc->sc_dev.dv_xname, "txipsum"); 1263 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1264 NULL, sc->sc_dev.dv_xname, "txtusum"); 1265 1266 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1267 NULL, sc->sc_dev.dv_xname, "txtso"); 1268 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1269 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1270 1271 for (i = 0; i < WM_NTXSEGS; i++) { 1272 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1273 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1275 } 1276 1277 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1278 NULL, sc->sc_dev.dv_xname, "txdrop"); 1279 1280 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1281 NULL, sc->sc_dev.dv_xname, "tu"); 1282 1283 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1284 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1285 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1287 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1289 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1290 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1291 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1292 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1293 #endif /* WM_EVENT_COUNTERS */ 1294 1295 /* 1296 * Make sure the interface is shutdown during reboot. 1297 */ 1298 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1299 if (sc->sc_sdhook == NULL) 1300 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1301 sc->sc_dev.dv_xname); 1302 return; 1303 1304 /* 1305 * Free any resources we've allocated during the failed attach 1306 * attempt. Do this in reverse order and fall through. 1307 */ 1308 fail_5: 1309 for (i = 0; i < WM_NRXDESC; i++) { 1310 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1311 bus_dmamap_destroy(sc->sc_dmat, 1312 sc->sc_rxsoft[i].rxs_dmamap); 1313 } 1314 fail_4: 1315 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1316 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1317 bus_dmamap_destroy(sc->sc_dmat, 1318 sc->sc_txsoft[i].txs_dmamap); 1319 } 1320 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1321 fail_3: 1322 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1323 fail_2: 1324 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1325 cdata_size); 1326 fail_1: 1327 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1328 fail_0: 1329 return; 1330 } 1331 1332 /* 1333 * wm_shutdown: 1334 * 1335 * Make sure the interface is stopped at reboot time. 1336 */ 1337 static void 1338 wm_shutdown(void *arg) 1339 { 1340 struct wm_softc *sc = arg; 1341 1342 wm_stop(&sc->sc_ethercom.ec_if, 1); 1343 } 1344 1345 /* 1346 * wm_tx_offload: 1347 * 1348 * Set up TCP/IP checksumming parameters for the 1349 * specified packet. 1350 */ 1351 static int 1352 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1353 uint8_t *fieldsp) 1354 { 1355 struct mbuf *m0 = txs->txs_mbuf; 1356 struct livengood_tcpip_ctxdesc *t; 1357 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1358 struct ether_header *eh; 1359 int offset, iphl; 1360 uint8_t fields; 1361 1362 /* 1363 * XXX It would be nice if the mbuf pkthdr had offset 1364 * fields for the protocol headers. 1365 */ 1366 1367 eh = mtod(m0, struct ether_header *); 1368 switch (htons(eh->ether_type)) { 1369 case ETHERTYPE_IP: 1370 offset = ETHER_HDR_LEN; 1371 break; 1372 1373 case ETHERTYPE_VLAN: 1374 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1375 break; 1376 1377 default: 1378 /* 1379 * Don't support this protocol or encapsulation. 1380 */ 1381 *fieldsp = 0; 1382 *cmdp = 0; 1383 return (0); 1384 } 1385 1386 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1387 1388 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1389 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1390 seg = 0; 1391 fields = 0; 1392 1393 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1394 int hlen = offset + iphl; 1395 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1396 if (__predict_false(m0->m_len < 1397 (hlen + sizeof(struct tcphdr)))) { 1398 /* 1399 * TCP/IP headers are not in the first mbuf; we need 1400 * to do this the slow and painful way. Let's just 1401 * hope this doesn't happen very often. 1402 */ 1403 struct ip ip; 1404 struct tcphdr th; 1405 1406 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1407 1408 m_copydata(m0, offset, sizeof(ip), &ip); 1409 m_copydata(m0, hlen, sizeof(th), &th); 1410 1411 ip.ip_len = 0; 1412 1413 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1414 sizeof(ip.ip_len), &ip.ip_len); 1415 1416 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1417 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1418 1419 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1420 sizeof(th.th_sum), &th.th_sum); 1421 1422 hlen += th.th_off << 2; 1423 } else { 1424 /* 1425 * TCP/IP headers are in the first mbuf; we can do 1426 * this the easy way. 1427 */ 1428 struct ip *ip = 1429 (struct ip *) (mtod(m0, caddr_t) + offset); 1430 struct tcphdr *th = 1431 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1432 1433 ip->ip_len = 0; 1434 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1435 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1436 1437 hlen += th->th_off << 2; 1438 } 1439 1440 cmd |= WTX_TCPIP_CMD_TSE; 1441 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1442 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1443 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1444 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1445 } 1446 1447 /* 1448 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1449 * offload feature, if we load the context descriptor, we 1450 * MUST provide valid values for IPCSS and TUCSS fields. 1451 */ 1452 1453 ipcs = WTX_TCPIP_IPCSS(offset) | 1454 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1455 WTX_TCPIP_IPCSE(offset + iphl - 1); 1456 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1457 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1458 fields |= WTX_IXSM; 1459 } 1460 1461 offset += iphl; 1462 1463 if (m0->m_pkthdr.csum_flags & 1464 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1465 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1466 fields |= WTX_TXSM; 1467 tucs = WTX_TCPIP_TUCSS(offset) | 1468 WTX_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1469 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1470 } else { 1471 /* Just initialize it to a valid TCP context. */ 1472 tucs = WTX_TCPIP_TUCSS(offset) | 1473 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1474 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1475 } 1476 1477 /* Fill in the context descriptor. */ 1478 t = (struct livengood_tcpip_ctxdesc *) 1479 &sc->sc_txdescs[sc->sc_txnext]; 1480 t->tcpip_ipcs = htole32(ipcs); 1481 t->tcpip_tucs = htole32(tucs); 1482 t->tcpip_cmdlen = htole32(cmdlen); 1483 t->tcpip_seg = htole32(seg); 1484 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1485 1486 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1487 txs->txs_ndesc++; 1488 1489 *cmdp = cmd; 1490 *fieldsp = fields; 1491 1492 return (0); 1493 } 1494 1495 static void 1496 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1497 { 1498 struct mbuf *m; 1499 int i; 1500 1501 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1502 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1503 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1504 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1505 m->m_data, m->m_len, m->m_flags); 1506 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1507 i, i == 1 ? "" : "s"); 1508 } 1509 1510 /* 1511 * wm_82547_txfifo_stall: 1512 * 1513 * Callout used to wait for the 82547 Tx FIFO to drain, 1514 * reset the FIFO pointers, and restart packet transmission. 1515 */ 1516 static void 1517 wm_82547_txfifo_stall(void *arg) 1518 { 1519 struct wm_softc *sc = arg; 1520 int s; 1521 1522 s = splnet(); 1523 1524 if (sc->sc_txfifo_stall) { 1525 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1526 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1527 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1528 /* 1529 * Packets have drained. Stop transmitter, reset 1530 * FIFO pointers, restart transmitter, and kick 1531 * the packet queue. 1532 */ 1533 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1534 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1535 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1536 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1537 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1538 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1539 CSR_WRITE(sc, WMREG_TCTL, tctl); 1540 CSR_WRITE_FLUSH(sc); 1541 1542 sc->sc_txfifo_head = 0; 1543 sc->sc_txfifo_stall = 0; 1544 wm_start(&sc->sc_ethercom.ec_if); 1545 } else { 1546 /* 1547 * Still waiting for packets to drain; try again in 1548 * another tick. 1549 */ 1550 callout_schedule(&sc->sc_txfifo_ch, 1); 1551 } 1552 } 1553 1554 splx(s); 1555 } 1556 1557 /* 1558 * wm_82547_txfifo_bugchk: 1559 * 1560 * Check for bug condition in the 82547 Tx FIFO. We need to 1561 * prevent enqueueing a packet that would wrap around the end 1562 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1563 * 1564 * We do this by checking the amount of space before the end 1565 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1566 * the Tx FIFO, wait for all remaining packets to drain, reset 1567 * the internal FIFO pointers to the beginning, and restart 1568 * transmission on the interface. 1569 */ 1570 #define WM_FIFO_HDR 0x10 1571 #define WM_82547_PAD_LEN 0x3e0 1572 static int 1573 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1574 { 1575 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1576 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1577 1578 /* Just return if already stalled. */ 1579 if (sc->sc_txfifo_stall) 1580 return (1); 1581 1582 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1583 /* Stall only occurs in half-duplex mode. */ 1584 goto send_packet; 1585 } 1586 1587 if (len >= WM_82547_PAD_LEN + space) { 1588 sc->sc_txfifo_stall = 1; 1589 callout_schedule(&sc->sc_txfifo_ch, 1); 1590 return (1); 1591 } 1592 1593 send_packet: 1594 sc->sc_txfifo_head += len; 1595 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1596 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1597 1598 return (0); 1599 } 1600 1601 /* 1602 * wm_start: [ifnet interface function] 1603 * 1604 * Start packet transmission on the interface. 1605 */ 1606 static void 1607 wm_start(struct ifnet *ifp) 1608 { 1609 struct wm_softc *sc = ifp->if_softc; 1610 struct mbuf *m0; 1611 #if 0 /* XXXJRT */ 1612 struct m_tag *mtag; 1613 #endif 1614 struct wm_txsoft *txs; 1615 bus_dmamap_t dmamap; 1616 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1617 bus_addr_t curaddr; 1618 bus_size_t seglen, curlen; 1619 uint32_t cksumcmd; 1620 uint8_t cksumfields; 1621 1622 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1623 return; 1624 1625 /* 1626 * Remember the previous number of free descriptors. 1627 */ 1628 ofree = sc->sc_txfree; 1629 1630 /* 1631 * Loop through the send queue, setting up transmit descriptors 1632 * until we drain the queue, or use up all available transmit 1633 * descriptors. 1634 */ 1635 for (;;) { 1636 /* Grab a packet off the queue. */ 1637 IFQ_POLL(&ifp->if_snd, m0); 1638 if (m0 == NULL) 1639 break; 1640 1641 DPRINTF(WM_DEBUG_TX, 1642 ("%s: TX: have packet to transmit: %p\n", 1643 sc->sc_dev.dv_xname, m0)); 1644 1645 /* Get a work queue entry. */ 1646 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1647 wm_txintr(sc); 1648 if (sc->sc_txsfree == 0) { 1649 DPRINTF(WM_DEBUG_TX, 1650 ("%s: TX: no free job descriptors\n", 1651 sc->sc_dev.dv_xname)); 1652 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1653 break; 1654 } 1655 } 1656 1657 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1658 dmamap = txs->txs_dmamap; 1659 1660 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1661 1662 /* 1663 * So says the Linux driver: 1664 * The controller does a simple calculation to make sure 1665 * there is enough room in the FIFO before initiating the 1666 * DMA for each buffer. The calc is: 1667 * 4 = ceil(buffer len / MSS) 1668 * To make sure we don't overrun the FIFO, adjust the max 1669 * buffer len if the MSS drops. 1670 */ 1671 dmamap->dm_maxsegsz = 1672 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1673 ? m0->m_pkthdr.segsz << 2 1674 : WTX_MAX_LEN; 1675 1676 /* 1677 * Load the DMA map. If this fails, the packet either 1678 * didn't fit in the allotted number of segments, or we 1679 * were short on resources. For the too-many-segments 1680 * case, we simply report an error and drop the packet, 1681 * since we can't sanely copy a jumbo packet to a single 1682 * buffer. 1683 */ 1684 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1685 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1686 if (error) { 1687 if (error == EFBIG) { 1688 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1689 log(LOG_ERR, "%s: Tx packet consumes too many " 1690 "DMA segments, dropping...\n", 1691 sc->sc_dev.dv_xname); 1692 IFQ_DEQUEUE(&ifp->if_snd, m0); 1693 wm_dump_mbuf_chain(sc, m0); 1694 m_freem(m0); 1695 continue; 1696 } 1697 /* 1698 * Short on resources, just stop for now. 1699 */ 1700 DPRINTF(WM_DEBUG_TX, 1701 ("%s: TX: dmamap load failed: %d\n", 1702 sc->sc_dev.dv_xname, error)); 1703 break; 1704 } 1705 1706 segs_needed = dmamap->dm_nsegs; 1707 if (use_tso) { 1708 /* For sentinel descriptor; see below. */ 1709 segs_needed++; 1710 } 1711 1712 /* 1713 * Ensure we have enough descriptors free to describe 1714 * the packet. Note, we always reserve one descriptor 1715 * at the end of the ring due to the semantics of the 1716 * TDT register, plus one more in the event we need 1717 * to load offload context. 1718 */ 1719 if (segs_needed > sc->sc_txfree - 2) { 1720 /* 1721 * Not enough free descriptors to transmit this 1722 * packet. We haven't committed anything yet, 1723 * so just unload the DMA map, put the packet 1724 * pack on the queue, and punt. Notify the upper 1725 * layer that there are no more slots left. 1726 */ 1727 DPRINTF(WM_DEBUG_TX, 1728 ("%s: TX: need %d (%) descriptors, have %d\n", 1729 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1730 sc->sc_txfree - 1)); 1731 ifp->if_flags |= IFF_OACTIVE; 1732 bus_dmamap_unload(sc->sc_dmat, dmamap); 1733 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1734 break; 1735 } 1736 1737 /* 1738 * Check for 82547 Tx FIFO bug. We need to do this 1739 * once we know we can transmit the packet, since we 1740 * do some internal FIFO space accounting here. 1741 */ 1742 if (sc->sc_type == WM_T_82547 && 1743 wm_82547_txfifo_bugchk(sc, m0)) { 1744 DPRINTF(WM_DEBUG_TX, 1745 ("%s: TX: 82547 Tx FIFO bug detected\n", 1746 sc->sc_dev.dv_xname)); 1747 ifp->if_flags |= IFF_OACTIVE; 1748 bus_dmamap_unload(sc->sc_dmat, dmamap); 1749 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1750 break; 1751 } 1752 1753 IFQ_DEQUEUE(&ifp->if_snd, m0); 1754 1755 /* 1756 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1757 */ 1758 1759 DPRINTF(WM_DEBUG_TX, 1760 ("%s: TX: packet has %d (%d) DMA segments\n", 1761 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1762 1763 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1764 1765 /* 1766 * Store a pointer to the packet so that we can free it 1767 * later. 1768 * 1769 * Initially, we consider the number of descriptors the 1770 * packet uses the number of DMA segments. This may be 1771 * incremented by 1 if we do checksum offload (a descriptor 1772 * is used to set the checksum context). 1773 */ 1774 txs->txs_mbuf = m0; 1775 txs->txs_firstdesc = sc->sc_txnext; 1776 txs->txs_ndesc = segs_needed; 1777 1778 /* Set up offload parameters for this packet. */ 1779 if (m0->m_pkthdr.csum_flags & 1780 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1781 if (wm_tx_offload(sc, txs, &cksumcmd, 1782 &cksumfields) != 0) { 1783 /* Error message already displayed. */ 1784 bus_dmamap_unload(sc->sc_dmat, dmamap); 1785 continue; 1786 } 1787 } else { 1788 cksumcmd = 0; 1789 cksumfields = 0; 1790 } 1791 1792 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1793 1794 /* Sync the DMA map. */ 1795 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1796 BUS_DMASYNC_PREWRITE); 1797 1798 /* 1799 * Initialize the transmit descriptor. 1800 */ 1801 for (nexttx = sc->sc_txnext, seg = 0; 1802 seg < dmamap->dm_nsegs; seg++) { 1803 for (seglen = dmamap->dm_segs[seg].ds_len, 1804 curaddr = dmamap->dm_segs[seg].ds_addr; 1805 seglen != 0; 1806 curaddr += curlen, seglen -= curlen, 1807 nexttx = WM_NEXTTX(sc, nexttx)) { 1808 curlen = seglen; 1809 1810 /* 1811 * So says the Linux driver: 1812 * Work around for premature descriptor 1813 * write-backs in TSO mode. Append a 1814 * 4-byte sentinel descriptor. 1815 */ 1816 if (use_tso && 1817 seg == dmamap->dm_nsegs - 1 && 1818 curlen > 8) 1819 curlen -= 4; 1820 1821 wm_set_dma_addr( 1822 &sc->sc_txdescs[nexttx].wtx_addr, 1823 curaddr); 1824 sc->sc_txdescs[nexttx].wtx_cmdlen = 1825 htole32(cksumcmd | curlen); 1826 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1827 0; 1828 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1829 cksumfields; 1830 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1831 lasttx = nexttx; 1832 1833 DPRINTF(WM_DEBUG_TX, 1834 ("%s: TX: desc %d: low 0x%08x, " 1835 "len 0x%04x\n", 1836 sc->sc_dev.dv_xname, nexttx, 1837 curaddr & 0xffffffffU, curlen, curlen)); 1838 } 1839 } 1840 1841 KASSERT(lasttx != -1); 1842 1843 /* 1844 * Set up the command byte on the last descriptor of 1845 * the packet. If we're in the interrupt delay window, 1846 * delay the interrupt. 1847 */ 1848 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1849 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1850 1851 #if 0 /* XXXJRT */ 1852 /* 1853 * If VLANs are enabled and the packet has a VLAN tag, set 1854 * up the descriptor to encapsulate the packet for us. 1855 * 1856 * This is only valid on the last descriptor of the packet. 1857 */ 1858 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1859 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1860 htole32(WTX_CMD_VLE); 1861 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1862 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1863 } 1864 #endif /* XXXJRT */ 1865 1866 txs->txs_lastdesc = lasttx; 1867 1868 DPRINTF(WM_DEBUG_TX, 1869 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1870 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1871 1872 /* Sync the descriptors we're using. */ 1873 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1874 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1875 1876 /* Give the packet to the chip. */ 1877 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1878 1879 DPRINTF(WM_DEBUG_TX, 1880 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1881 1882 DPRINTF(WM_DEBUG_TX, 1883 ("%s: TX: finished transmitting packet, job %d\n", 1884 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1885 1886 /* Advance the tx pointer. */ 1887 sc->sc_txfree -= txs->txs_ndesc; 1888 sc->sc_txnext = nexttx; 1889 1890 sc->sc_txsfree--; 1891 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1892 1893 #if NBPFILTER > 0 1894 /* Pass the packet to any BPF listeners. */ 1895 if (ifp->if_bpf) 1896 bpf_mtap(ifp->if_bpf, m0); 1897 #endif /* NBPFILTER > 0 */ 1898 } 1899 1900 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1901 /* No more slots; notify upper layer. */ 1902 ifp->if_flags |= IFF_OACTIVE; 1903 } 1904 1905 if (sc->sc_txfree != ofree) { 1906 /* Set a watchdog timer in case the chip flakes out. */ 1907 ifp->if_timer = 5; 1908 } 1909 } 1910 1911 /* 1912 * wm_watchdog: [ifnet interface function] 1913 * 1914 * Watchdog timer handler. 1915 */ 1916 static void 1917 wm_watchdog(struct ifnet *ifp) 1918 { 1919 struct wm_softc *sc = ifp->if_softc; 1920 1921 /* 1922 * Since we're using delayed interrupts, sweep up 1923 * before we report an error. 1924 */ 1925 wm_txintr(sc); 1926 1927 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1928 log(LOG_ERR, 1929 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1930 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1931 sc->sc_txnext); 1932 ifp->if_oerrors++; 1933 1934 /* Reset the interface. */ 1935 (void) wm_init(ifp); 1936 } 1937 1938 /* Try to get more packets going. */ 1939 wm_start(ifp); 1940 } 1941 1942 /* 1943 * wm_ioctl: [ifnet interface function] 1944 * 1945 * Handle control requests from the operator. 1946 */ 1947 static int 1948 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1949 { 1950 struct wm_softc *sc = ifp->if_softc; 1951 struct ifreq *ifr = (struct ifreq *) data; 1952 int s, error; 1953 1954 s = splnet(); 1955 1956 switch (cmd) { 1957 case SIOCSIFMEDIA: 1958 case SIOCGIFMEDIA: 1959 /* Flow control requires full-duplex mode. */ 1960 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1961 (ifr->ifr_media & IFM_FDX) == 0) 1962 ifr->ifr_media &= ~IFM_ETH_FMASK; 1963 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1964 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1965 /* We can do both TXPAUSE and RXPAUSE. */ 1966 ifr->ifr_media |= 1967 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1968 } 1969 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1970 } 1971 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1972 break; 1973 default: 1974 error = ether_ioctl(ifp, cmd, data); 1975 if (error == ENETRESET) { 1976 /* 1977 * Multicast list has changed; set the hardware filter 1978 * accordingly. 1979 */ 1980 if (ifp->if_flags & IFF_RUNNING) 1981 wm_set_filter(sc); 1982 error = 0; 1983 } 1984 break; 1985 } 1986 1987 /* Try to get more packets going. */ 1988 wm_start(ifp); 1989 1990 splx(s); 1991 return (error); 1992 } 1993 1994 /* 1995 * wm_intr: 1996 * 1997 * Interrupt service routine. 1998 */ 1999 static int 2000 wm_intr(void *arg) 2001 { 2002 struct wm_softc *sc = arg; 2003 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2004 uint32_t icr; 2005 int wantinit, handled = 0; 2006 2007 for (wantinit = 0; wantinit == 0;) { 2008 icr = CSR_READ(sc, WMREG_ICR); 2009 if ((icr & sc->sc_icr) == 0) 2010 break; 2011 2012 #if 0 /*NRND > 0*/ 2013 if (RND_ENABLED(&sc->rnd_source)) 2014 rnd_add_uint32(&sc->rnd_source, icr); 2015 #endif 2016 2017 handled = 1; 2018 2019 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2020 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2021 DPRINTF(WM_DEBUG_RX, 2022 ("%s: RX: got Rx intr 0x%08x\n", 2023 sc->sc_dev.dv_xname, 2024 icr & (ICR_RXDMT0|ICR_RXT0))); 2025 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2026 } 2027 #endif 2028 wm_rxintr(sc); 2029 2030 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2031 if (icr & ICR_TXDW) { 2032 DPRINTF(WM_DEBUG_TX, 2033 ("%s: TX: got TXDW interrupt\n", 2034 sc->sc_dev.dv_xname)); 2035 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2036 } 2037 #endif 2038 wm_txintr(sc); 2039 2040 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2041 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2042 wm_linkintr(sc, icr); 2043 } 2044 2045 if (icr & ICR_RXO) { 2046 log(LOG_WARNING, "%s: Receive overrun\n", 2047 sc->sc_dev.dv_xname); 2048 wantinit = 1; 2049 } 2050 } 2051 2052 if (handled) { 2053 if (wantinit) 2054 wm_init(ifp); 2055 2056 /* Try to get more packets going. */ 2057 wm_start(ifp); 2058 } 2059 2060 return (handled); 2061 } 2062 2063 /* 2064 * wm_txintr: 2065 * 2066 * Helper; handle transmit interrupts. 2067 */ 2068 static void 2069 wm_txintr(struct wm_softc *sc) 2070 { 2071 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2072 struct wm_txsoft *txs; 2073 uint8_t status; 2074 int i; 2075 2076 ifp->if_flags &= ~IFF_OACTIVE; 2077 2078 /* 2079 * Go through the Tx list and free mbufs for those 2080 * frames which have been transmitted. 2081 */ 2082 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2083 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2084 txs = &sc->sc_txsoft[i]; 2085 2086 DPRINTF(WM_DEBUG_TX, 2087 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2088 2089 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2090 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2091 2092 status = 2093 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2094 if ((status & WTX_ST_DD) == 0) { 2095 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2096 BUS_DMASYNC_PREREAD); 2097 break; 2098 } 2099 2100 DPRINTF(WM_DEBUG_TX, 2101 ("%s: TX: job %d done: descs %d..%d\n", 2102 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2103 txs->txs_lastdesc)); 2104 2105 /* 2106 * XXX We should probably be using the statistics 2107 * XXX registers, but I don't know if they exist 2108 * XXX on chips before the i82544. 2109 */ 2110 2111 #ifdef WM_EVENT_COUNTERS 2112 if (status & WTX_ST_TU) 2113 WM_EVCNT_INCR(&sc->sc_ev_tu); 2114 #endif /* WM_EVENT_COUNTERS */ 2115 2116 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2117 ifp->if_oerrors++; 2118 if (status & WTX_ST_LC) 2119 log(LOG_WARNING, "%s: late collision\n", 2120 sc->sc_dev.dv_xname); 2121 else if (status & WTX_ST_EC) { 2122 ifp->if_collisions += 16; 2123 log(LOG_WARNING, "%s: excessive collisions\n", 2124 sc->sc_dev.dv_xname); 2125 } 2126 } else 2127 ifp->if_opackets++; 2128 2129 sc->sc_txfree += txs->txs_ndesc; 2130 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2131 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2132 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2133 m_freem(txs->txs_mbuf); 2134 txs->txs_mbuf = NULL; 2135 } 2136 2137 /* Update the dirty transmit buffer pointer. */ 2138 sc->sc_txsdirty = i; 2139 DPRINTF(WM_DEBUG_TX, 2140 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2141 2142 /* 2143 * If there are no more pending transmissions, cancel the watchdog 2144 * timer. 2145 */ 2146 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2147 ifp->if_timer = 0; 2148 } 2149 2150 /* 2151 * wm_rxintr: 2152 * 2153 * Helper; handle receive interrupts. 2154 */ 2155 static void 2156 wm_rxintr(struct wm_softc *sc) 2157 { 2158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2159 struct wm_rxsoft *rxs; 2160 struct mbuf *m; 2161 int i, len; 2162 uint8_t status, errors; 2163 2164 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2165 rxs = &sc->sc_rxsoft[i]; 2166 2167 DPRINTF(WM_DEBUG_RX, 2168 ("%s: RX: checking descriptor %d\n", 2169 sc->sc_dev.dv_xname, i)); 2170 2171 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2172 2173 status = sc->sc_rxdescs[i].wrx_status; 2174 errors = sc->sc_rxdescs[i].wrx_errors; 2175 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2176 2177 if ((status & WRX_ST_DD) == 0) { 2178 /* 2179 * We have processed all of the receive descriptors. 2180 */ 2181 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2182 break; 2183 } 2184 2185 if (__predict_false(sc->sc_rxdiscard)) { 2186 DPRINTF(WM_DEBUG_RX, 2187 ("%s: RX: discarding contents of descriptor %d\n", 2188 sc->sc_dev.dv_xname, i)); 2189 WM_INIT_RXDESC(sc, i); 2190 if (status & WRX_ST_EOP) { 2191 /* Reset our state. */ 2192 DPRINTF(WM_DEBUG_RX, 2193 ("%s: RX: resetting rxdiscard -> 0\n", 2194 sc->sc_dev.dv_xname)); 2195 sc->sc_rxdiscard = 0; 2196 } 2197 continue; 2198 } 2199 2200 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2201 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2202 2203 m = rxs->rxs_mbuf; 2204 2205 /* 2206 * Add a new receive buffer to the ring. 2207 */ 2208 if (wm_add_rxbuf(sc, i) != 0) { 2209 /* 2210 * Failed, throw away what we've done so 2211 * far, and discard the rest of the packet. 2212 */ 2213 ifp->if_ierrors++; 2214 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2215 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2216 WM_INIT_RXDESC(sc, i); 2217 if ((status & WRX_ST_EOP) == 0) 2218 sc->sc_rxdiscard = 1; 2219 if (sc->sc_rxhead != NULL) 2220 m_freem(sc->sc_rxhead); 2221 WM_RXCHAIN_RESET(sc); 2222 DPRINTF(WM_DEBUG_RX, 2223 ("%s: RX: Rx buffer allocation failed, " 2224 "dropping packet%s\n", sc->sc_dev.dv_xname, 2225 sc->sc_rxdiscard ? " (discard)" : "")); 2226 continue; 2227 } 2228 2229 WM_RXCHAIN_LINK(sc, m); 2230 2231 m->m_len = len; 2232 2233 DPRINTF(WM_DEBUG_RX, 2234 ("%s: RX: buffer at %p len %d\n", 2235 sc->sc_dev.dv_xname, m->m_data, len)); 2236 2237 /* 2238 * If this is not the end of the packet, keep 2239 * looking. 2240 */ 2241 if ((status & WRX_ST_EOP) == 0) { 2242 sc->sc_rxlen += len; 2243 DPRINTF(WM_DEBUG_RX, 2244 ("%s: RX: not yet EOP, rxlen -> %d\n", 2245 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2246 continue; 2247 } 2248 2249 /* 2250 * Okay, we have the entire packet now. The chip is 2251 * configured to include the FCS (not all chips can 2252 * be configured to strip it), so we need to trim it. 2253 */ 2254 m->m_len -= ETHER_CRC_LEN; 2255 2256 *sc->sc_rxtailp = NULL; 2257 m = sc->sc_rxhead; 2258 len = m->m_len + sc->sc_rxlen; 2259 2260 WM_RXCHAIN_RESET(sc); 2261 2262 DPRINTF(WM_DEBUG_RX, 2263 ("%s: RX: have entire packet, len -> %d\n", 2264 sc->sc_dev.dv_xname, len)); 2265 2266 /* 2267 * If an error occurred, update stats and drop the packet. 2268 */ 2269 if (errors & 2270 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2271 ifp->if_ierrors++; 2272 if (errors & WRX_ER_SE) 2273 log(LOG_WARNING, "%s: symbol error\n", 2274 sc->sc_dev.dv_xname); 2275 else if (errors & WRX_ER_SEQ) 2276 log(LOG_WARNING, "%s: receive sequence error\n", 2277 sc->sc_dev.dv_xname); 2278 else if (errors & WRX_ER_CE) 2279 log(LOG_WARNING, "%s: CRC error\n", 2280 sc->sc_dev.dv_xname); 2281 m_freem(m); 2282 continue; 2283 } 2284 2285 /* 2286 * No errors. Receive the packet. 2287 */ 2288 m->m_pkthdr.rcvif = ifp; 2289 m->m_pkthdr.len = len; 2290 2291 #if 0 /* XXXJRT */ 2292 /* 2293 * If VLANs are enabled, VLAN packets have been unwrapped 2294 * for us. Associate the tag with the packet. 2295 */ 2296 if ((status & WRX_ST_VP) != 0) { 2297 VLAN_INPUT_TAG(ifp, m, 2298 le16toh(sc->sc_rxdescs[i].wrx_special, 2299 continue); 2300 } 2301 #endif /* XXXJRT */ 2302 2303 /* 2304 * Set up checksum info for this packet. 2305 */ 2306 if (status & WRX_ST_IPCS) { 2307 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2308 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2309 if (errors & WRX_ER_IPE) 2310 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2311 } 2312 if (status & WRX_ST_TCPCS) { 2313 /* 2314 * Note: we don't know if this was TCP or UDP, 2315 * so we just set both bits, and expect the 2316 * upper layers to deal. 2317 */ 2318 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2319 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2320 if (errors & WRX_ER_TCPE) 2321 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2322 } 2323 2324 ifp->if_ipackets++; 2325 2326 #if NBPFILTER > 0 2327 /* Pass this up to any BPF listeners. */ 2328 if (ifp->if_bpf) 2329 bpf_mtap(ifp->if_bpf, m); 2330 #endif /* NBPFILTER > 0 */ 2331 2332 /* Pass it on. */ 2333 (*ifp->if_input)(ifp, m); 2334 } 2335 2336 /* Update the receive pointer. */ 2337 sc->sc_rxptr = i; 2338 2339 DPRINTF(WM_DEBUG_RX, 2340 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2341 } 2342 2343 /* 2344 * wm_linkintr: 2345 * 2346 * Helper; handle link interrupts. 2347 */ 2348 static void 2349 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2350 { 2351 uint32_t status; 2352 2353 /* 2354 * If we get a link status interrupt on a 1000BASE-T 2355 * device, just fall into the normal MII tick path. 2356 */ 2357 if (sc->sc_flags & WM_F_HAS_MII) { 2358 if (icr & ICR_LSC) { 2359 DPRINTF(WM_DEBUG_LINK, 2360 ("%s: LINK: LSC -> mii_tick\n", 2361 sc->sc_dev.dv_xname)); 2362 mii_tick(&sc->sc_mii); 2363 } else if (icr & ICR_RXSEQ) { 2364 DPRINTF(WM_DEBUG_LINK, 2365 ("%s: LINK Receive sequence error\n", 2366 sc->sc_dev.dv_xname)); 2367 } 2368 return; 2369 } 2370 2371 /* 2372 * If we are now receiving /C/, check for link again in 2373 * a couple of link clock ticks. 2374 */ 2375 if (icr & ICR_RXCFG) { 2376 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2377 sc->sc_dev.dv_xname)); 2378 sc->sc_tbi_anstate = 2; 2379 } 2380 2381 if (icr & ICR_LSC) { 2382 status = CSR_READ(sc, WMREG_STATUS); 2383 if (status & STATUS_LU) { 2384 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2385 sc->sc_dev.dv_xname, 2386 (status & STATUS_FD) ? "FDX" : "HDX")); 2387 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2388 sc->sc_fcrtl &= ~FCRTL_XONE; 2389 if (status & STATUS_FD) 2390 sc->sc_tctl |= 2391 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2392 else 2393 sc->sc_tctl |= 2394 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2395 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2396 sc->sc_fcrtl |= FCRTL_XONE; 2397 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2398 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2399 WMREG_OLD_FCRTL : WMREG_FCRTL, 2400 sc->sc_fcrtl); 2401 sc->sc_tbi_linkup = 1; 2402 } else { 2403 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2404 sc->sc_dev.dv_xname)); 2405 sc->sc_tbi_linkup = 0; 2406 } 2407 sc->sc_tbi_anstate = 2; 2408 wm_tbi_set_linkled(sc); 2409 } else if (icr & ICR_RXSEQ) { 2410 DPRINTF(WM_DEBUG_LINK, 2411 ("%s: LINK: Receive sequence error\n", 2412 sc->sc_dev.dv_xname)); 2413 } 2414 } 2415 2416 /* 2417 * wm_tick: 2418 * 2419 * One second timer, used to check link status, sweep up 2420 * completed transmit jobs, etc. 2421 */ 2422 static void 2423 wm_tick(void *arg) 2424 { 2425 struct wm_softc *sc = arg; 2426 int s; 2427 2428 s = splnet(); 2429 2430 if (sc->sc_type >= WM_T_82542_2_1) { 2431 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2432 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2433 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2434 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2435 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2436 } 2437 2438 if (sc->sc_flags & WM_F_HAS_MII) 2439 mii_tick(&sc->sc_mii); 2440 else 2441 wm_tbi_check_link(sc); 2442 2443 splx(s); 2444 2445 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2446 } 2447 2448 /* 2449 * wm_reset: 2450 * 2451 * Reset the i82542 chip. 2452 */ 2453 static void 2454 wm_reset(struct wm_softc *sc) 2455 { 2456 int i; 2457 2458 /* 2459 * Allocate on-chip memory according to the MTU size. 2460 * The Packet Buffer Allocation register must be written 2461 * before the chip is reset. 2462 */ 2463 if (sc->sc_type < WM_T_82547) { 2464 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2465 PBA_40K : PBA_48K; 2466 } else { 2467 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2468 PBA_22K : PBA_30K; 2469 sc->sc_txfifo_head = 0; 2470 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2471 sc->sc_txfifo_size = 2472 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2473 sc->sc_txfifo_stall = 0; 2474 } 2475 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2476 2477 switch (sc->sc_type) { 2478 case WM_T_82544: 2479 case WM_T_82540: 2480 case WM_T_82545: 2481 case WM_T_82546: 2482 case WM_T_82541: 2483 case WM_T_82541_2: 2484 /* 2485 * On some chipsets, a reset through a memory-mapped write 2486 * cycle can cause the chip to reset before completing the 2487 * write cycle. This causes major headache that can be 2488 * avoided by issuing the reset via indirect register writes 2489 * through I/O space. 2490 * 2491 * So, if we successfully mapped the I/O BAR at attach time, 2492 * use that. Otherwise, try our luck with a memory-mapped 2493 * reset. 2494 */ 2495 if (sc->sc_flags & WM_F_IOH_VALID) 2496 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2497 else 2498 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2499 break; 2500 2501 case WM_T_82545_3: 2502 case WM_T_82546_3: 2503 /* Use the shadow control register on these chips. */ 2504 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2505 break; 2506 2507 default: 2508 /* Everything else can safely use the documented method. */ 2509 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2510 break; 2511 } 2512 delay(10000); 2513 2514 for (i = 0; i < 1000; i++) { 2515 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2516 return; 2517 delay(20); 2518 } 2519 2520 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2521 log(LOG_ERR, "%s: reset failed to complete\n", 2522 sc->sc_dev.dv_xname); 2523 } 2524 2525 /* 2526 * wm_init: [ifnet interface function] 2527 * 2528 * Initialize the interface. Must be called at splnet(). 2529 */ 2530 static int 2531 wm_init(struct ifnet *ifp) 2532 { 2533 struct wm_softc *sc = ifp->if_softc; 2534 struct wm_rxsoft *rxs; 2535 int i, error = 0; 2536 uint32_t reg; 2537 2538 /* 2539 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2540 * There is a small but measurable benefit to avoiding the adjusment 2541 * of the descriptor so that the headers are aligned, for normal mtu, 2542 * on such platforms. One possibility is that the DMA itself is 2543 * slightly more efficient if the front of the entire packet (instead 2544 * of the front of the headers) is aligned. 2545 * 2546 * Note we must always set align_tweak to 0 if we are using 2547 * jumbo frames. 2548 */ 2549 #ifdef __NO_STRICT_ALIGNMENT 2550 sc->sc_align_tweak = 0; 2551 #else 2552 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2553 sc->sc_align_tweak = 0; 2554 else 2555 sc->sc_align_tweak = 2; 2556 #endif /* __NO_STRICT_ALIGNMENT */ 2557 2558 /* Cancel any pending I/O. */ 2559 wm_stop(ifp, 0); 2560 2561 /* Reset the chip to a known state. */ 2562 wm_reset(sc); 2563 2564 /* Initialize the transmit descriptor ring. */ 2565 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2566 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2567 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2568 sc->sc_txfree = WM_NTXDESC(sc); 2569 sc->sc_txnext = 0; 2570 2571 if (sc->sc_type < WM_T_82543) { 2572 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2573 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2574 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2575 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2576 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2577 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2578 } else { 2579 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2580 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2581 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2582 CSR_WRITE(sc, WMREG_TDH, 0); 2583 CSR_WRITE(sc, WMREG_TDT, 0); 2584 CSR_WRITE(sc, WMREG_TIDV, 64); 2585 CSR_WRITE(sc, WMREG_TADV, 128); 2586 2587 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2588 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2589 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2590 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2591 } 2592 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2593 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2594 2595 /* Initialize the transmit job descriptors. */ 2596 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2597 sc->sc_txsoft[i].txs_mbuf = NULL; 2598 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2599 sc->sc_txsnext = 0; 2600 sc->sc_txsdirty = 0; 2601 2602 /* 2603 * Initialize the receive descriptor and receive job 2604 * descriptor rings. 2605 */ 2606 if (sc->sc_type < WM_T_82543) { 2607 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2608 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2609 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2610 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2611 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2612 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2613 2614 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2615 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2616 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2617 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2618 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2619 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2620 } else { 2621 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2622 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2623 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2624 CSR_WRITE(sc, WMREG_RDH, 0); 2625 CSR_WRITE(sc, WMREG_RDT, 0); 2626 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2627 CSR_WRITE(sc, WMREG_RADV, 128); 2628 } 2629 for (i = 0; i < WM_NRXDESC; i++) { 2630 rxs = &sc->sc_rxsoft[i]; 2631 if (rxs->rxs_mbuf == NULL) { 2632 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2633 log(LOG_ERR, "%s: unable to allocate or map rx " 2634 "buffer %d, error = %d\n", 2635 sc->sc_dev.dv_xname, i, error); 2636 /* 2637 * XXX Should attempt to run with fewer receive 2638 * XXX buffers instead of just failing. 2639 */ 2640 wm_rxdrain(sc); 2641 goto out; 2642 } 2643 } else 2644 WM_INIT_RXDESC(sc, i); 2645 } 2646 sc->sc_rxptr = 0; 2647 sc->sc_rxdiscard = 0; 2648 WM_RXCHAIN_RESET(sc); 2649 2650 /* 2651 * Clear out the VLAN table -- we don't use it (yet). 2652 */ 2653 CSR_WRITE(sc, WMREG_VET, 0); 2654 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2655 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2656 2657 /* 2658 * Set up flow-control parameters. 2659 * 2660 * XXX Values could probably stand some tuning. 2661 */ 2662 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2663 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2664 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2665 2666 sc->sc_fcrtl = FCRTL_DFLT; 2667 if (sc->sc_type < WM_T_82543) { 2668 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2669 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2670 } else { 2671 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2672 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2673 } 2674 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2675 2676 #if 0 /* XXXJRT */ 2677 /* Deal with VLAN enables. */ 2678 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2679 sc->sc_ctrl |= CTRL_VME; 2680 else 2681 #endif /* XXXJRT */ 2682 sc->sc_ctrl &= ~CTRL_VME; 2683 2684 /* Write the control registers. */ 2685 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2686 #if 0 2687 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2688 #endif 2689 2690 /* 2691 * Set up checksum offload parameters. 2692 */ 2693 reg = CSR_READ(sc, WMREG_RXCSUM); 2694 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2695 reg |= RXCSUM_IPOFL; 2696 else 2697 reg &= ~RXCSUM_IPOFL; 2698 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2699 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2700 else { 2701 reg &= ~RXCSUM_TUOFL; 2702 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2703 reg &= ~RXCSUM_IPOFL; 2704 } 2705 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2706 2707 /* 2708 * Set up the interrupt registers. 2709 */ 2710 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2711 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2712 ICR_RXO | ICR_RXT0; 2713 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2714 sc->sc_icr |= ICR_RXCFG; 2715 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2716 2717 /* Set up the inter-packet gap. */ 2718 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2719 2720 if (sc->sc_type >= WM_T_82543) { 2721 /* Set up the interrupt throttling register (units of 256ns) */ 2722 sc->sc_itr = 1000000000 / (7000 * 256); 2723 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2724 } 2725 2726 #if 0 /* XXXJRT */ 2727 /* Set the VLAN ethernetype. */ 2728 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2729 #endif 2730 2731 /* 2732 * Set up the transmit control register; we start out with 2733 * a collision distance suitable for FDX, but update it whe 2734 * we resolve the media type. 2735 */ 2736 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2737 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2738 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2739 2740 /* Set the media. */ 2741 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2742 2743 /* 2744 * Set up the receive control register; we actually program 2745 * the register when we set the receive filter. Use multicast 2746 * address offset type 0. 2747 * 2748 * Only the i82544 has the ability to strip the incoming 2749 * CRC, so we don't enable that feature. 2750 */ 2751 sc->sc_mchash_type = 0; 2752 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2753 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2754 2755 if(MCLBYTES == 2048) { 2756 sc->sc_rctl |= RCTL_2k; 2757 } else { 2758 if(sc->sc_type >= WM_T_82543) { 2759 switch(MCLBYTES) { 2760 case 4096: 2761 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2762 break; 2763 case 8192: 2764 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2765 break; 2766 case 16384: 2767 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2768 break; 2769 default: 2770 panic("wm_init: MCLBYTES %d unsupported", 2771 MCLBYTES); 2772 break; 2773 } 2774 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2775 } 2776 2777 /* Set the receive filter. */ 2778 wm_set_filter(sc); 2779 2780 /* Start the one second link check clock. */ 2781 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2782 2783 /* ...all done! */ 2784 ifp->if_flags |= IFF_RUNNING; 2785 ifp->if_flags &= ~IFF_OACTIVE; 2786 2787 out: 2788 if (error) 2789 log(LOG_ERR, "%s: interface not running\n", 2790 sc->sc_dev.dv_xname); 2791 return (error); 2792 } 2793 2794 /* 2795 * wm_rxdrain: 2796 * 2797 * Drain the receive queue. 2798 */ 2799 static void 2800 wm_rxdrain(struct wm_softc *sc) 2801 { 2802 struct wm_rxsoft *rxs; 2803 int i; 2804 2805 for (i = 0; i < WM_NRXDESC; i++) { 2806 rxs = &sc->sc_rxsoft[i]; 2807 if (rxs->rxs_mbuf != NULL) { 2808 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2809 m_freem(rxs->rxs_mbuf); 2810 rxs->rxs_mbuf = NULL; 2811 } 2812 } 2813 } 2814 2815 /* 2816 * wm_stop: [ifnet interface function] 2817 * 2818 * Stop transmission on the interface. 2819 */ 2820 static void 2821 wm_stop(struct ifnet *ifp, int disable) 2822 { 2823 struct wm_softc *sc = ifp->if_softc; 2824 struct wm_txsoft *txs; 2825 int i; 2826 2827 /* Stop the one second clock. */ 2828 callout_stop(&sc->sc_tick_ch); 2829 2830 /* Stop the 82547 Tx FIFO stall check timer. */ 2831 if (sc->sc_type == WM_T_82547) 2832 callout_stop(&sc->sc_txfifo_ch); 2833 2834 if (sc->sc_flags & WM_F_HAS_MII) { 2835 /* Down the MII. */ 2836 mii_down(&sc->sc_mii); 2837 } 2838 2839 /* Stop the transmit and receive processes. */ 2840 CSR_WRITE(sc, WMREG_TCTL, 0); 2841 CSR_WRITE(sc, WMREG_RCTL, 0); 2842 2843 /* Release any queued transmit buffers. */ 2844 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2845 txs = &sc->sc_txsoft[i]; 2846 if (txs->txs_mbuf != NULL) { 2847 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2848 m_freem(txs->txs_mbuf); 2849 txs->txs_mbuf = NULL; 2850 } 2851 } 2852 2853 if (disable) 2854 wm_rxdrain(sc); 2855 2856 /* Mark the interface as down and cancel the watchdog timer. */ 2857 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2858 ifp->if_timer = 0; 2859 } 2860 2861 /* 2862 * wm_acquire_eeprom: 2863 * 2864 * Perform the EEPROM handshake required on some chips. 2865 */ 2866 static int 2867 wm_acquire_eeprom(struct wm_softc *sc) 2868 { 2869 uint32_t reg; 2870 int x; 2871 2872 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2873 reg = CSR_READ(sc, WMREG_EECD); 2874 2875 /* Request EEPROM access. */ 2876 reg |= EECD_EE_REQ; 2877 CSR_WRITE(sc, WMREG_EECD, reg); 2878 2879 /* ..and wait for it to be granted. */ 2880 for (x = 0; x < 100; x++) { 2881 reg = CSR_READ(sc, WMREG_EECD); 2882 if (reg & EECD_EE_GNT) 2883 break; 2884 delay(5); 2885 } 2886 if ((reg & EECD_EE_GNT) == 0) { 2887 aprint_error("%s: could not acquire EEPROM GNT\n", 2888 sc->sc_dev.dv_xname); 2889 reg &= ~EECD_EE_REQ; 2890 CSR_WRITE(sc, WMREG_EECD, reg); 2891 return (1); 2892 } 2893 } 2894 2895 return (0); 2896 } 2897 2898 /* 2899 * wm_release_eeprom: 2900 * 2901 * Release the EEPROM mutex. 2902 */ 2903 static void 2904 wm_release_eeprom(struct wm_softc *sc) 2905 { 2906 uint32_t reg; 2907 2908 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2909 reg = CSR_READ(sc, WMREG_EECD); 2910 reg &= ~EECD_EE_REQ; 2911 CSR_WRITE(sc, WMREG_EECD, reg); 2912 } 2913 } 2914 2915 /* 2916 * wm_eeprom_sendbits: 2917 * 2918 * Send a series of bits to the EEPROM. 2919 */ 2920 static void 2921 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2922 { 2923 uint32_t reg; 2924 int x; 2925 2926 reg = CSR_READ(sc, WMREG_EECD); 2927 2928 for (x = nbits; x > 0; x--) { 2929 if (bits & (1U << (x - 1))) 2930 reg |= EECD_DI; 2931 else 2932 reg &= ~EECD_DI; 2933 CSR_WRITE(sc, WMREG_EECD, reg); 2934 delay(2); 2935 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2936 delay(2); 2937 CSR_WRITE(sc, WMREG_EECD, reg); 2938 delay(2); 2939 } 2940 } 2941 2942 /* 2943 * wm_eeprom_recvbits: 2944 * 2945 * Receive a series of bits from the EEPROM. 2946 */ 2947 static void 2948 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2949 { 2950 uint32_t reg, val; 2951 int x; 2952 2953 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2954 2955 val = 0; 2956 for (x = nbits; x > 0; x--) { 2957 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2958 delay(2); 2959 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2960 val |= (1U << (x - 1)); 2961 CSR_WRITE(sc, WMREG_EECD, reg); 2962 delay(2); 2963 } 2964 *valp = val; 2965 } 2966 2967 /* 2968 * wm_read_eeprom_uwire: 2969 * 2970 * Read a word from the EEPROM using the MicroWire protocol. 2971 */ 2972 static int 2973 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2974 { 2975 uint32_t reg, val; 2976 int i; 2977 2978 for (i = 0; i < wordcnt; i++) { 2979 /* Clear SK and DI. */ 2980 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2981 CSR_WRITE(sc, WMREG_EECD, reg); 2982 2983 /* Set CHIP SELECT. */ 2984 reg |= EECD_CS; 2985 CSR_WRITE(sc, WMREG_EECD, reg); 2986 delay(2); 2987 2988 /* Shift in the READ command. */ 2989 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2990 2991 /* Shift in address. */ 2992 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2993 2994 /* Shift out the data. */ 2995 wm_eeprom_recvbits(sc, &val, 16); 2996 data[i] = val & 0xffff; 2997 2998 /* Clear CHIP SELECT. */ 2999 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3000 CSR_WRITE(sc, WMREG_EECD, reg); 3001 delay(2); 3002 } 3003 3004 return (0); 3005 } 3006 3007 /* 3008 * wm_spi_eeprom_ready: 3009 * 3010 * Wait for a SPI EEPROM to be ready for commands. 3011 */ 3012 static int 3013 wm_spi_eeprom_ready(struct wm_softc *sc) 3014 { 3015 uint32_t val; 3016 int usec; 3017 3018 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3019 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3020 wm_eeprom_recvbits(sc, &val, 8); 3021 if ((val & SPI_SR_RDY) == 0) 3022 break; 3023 } 3024 if (usec >= SPI_MAX_RETRIES) { 3025 aprint_error("%s: EEPROM failed to become ready\n", 3026 sc->sc_dev.dv_xname); 3027 return (1); 3028 } 3029 return (0); 3030 } 3031 3032 /* 3033 * wm_read_eeprom_spi: 3034 * 3035 * Read a work from the EEPROM using the SPI protocol. 3036 */ 3037 static int 3038 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3039 { 3040 uint32_t reg, val; 3041 int i; 3042 uint8_t opc; 3043 3044 /* Clear SK and CS. */ 3045 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3046 CSR_WRITE(sc, WMREG_EECD, reg); 3047 delay(2); 3048 3049 if (wm_spi_eeprom_ready(sc)) 3050 return (1); 3051 3052 /* Toggle CS to flush commands. */ 3053 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3054 delay(2); 3055 CSR_WRITE(sc, WMREG_EECD, reg); 3056 delay(2); 3057 3058 opc = SPI_OPC_READ; 3059 if (sc->sc_ee_addrbits == 8 && word >= 128) 3060 opc |= SPI_OPC_A8; 3061 3062 wm_eeprom_sendbits(sc, opc, 8); 3063 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3064 3065 for (i = 0; i < wordcnt; i++) { 3066 wm_eeprom_recvbits(sc, &val, 16); 3067 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3068 } 3069 3070 /* Raise CS and clear SK. */ 3071 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3072 CSR_WRITE(sc, WMREG_EECD, reg); 3073 delay(2); 3074 3075 return (0); 3076 } 3077 3078 /* 3079 * wm_read_eeprom: 3080 * 3081 * Read data from the serial EEPROM. 3082 */ 3083 static int 3084 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3085 { 3086 int rv; 3087 3088 if (wm_acquire_eeprom(sc)) 3089 return (1); 3090 3091 if (sc->sc_flags & WM_F_EEPROM_SPI) 3092 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3093 else 3094 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3095 3096 wm_release_eeprom(sc); 3097 return (rv); 3098 } 3099 3100 /* 3101 * wm_add_rxbuf: 3102 * 3103 * Add a receive buffer to the indiciated descriptor. 3104 */ 3105 static int 3106 wm_add_rxbuf(struct wm_softc *sc, int idx) 3107 { 3108 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3109 struct mbuf *m; 3110 int error; 3111 3112 MGETHDR(m, M_DONTWAIT, MT_DATA); 3113 if (m == NULL) 3114 return (ENOBUFS); 3115 3116 MCLGET(m, M_DONTWAIT); 3117 if ((m->m_flags & M_EXT) == 0) { 3118 m_freem(m); 3119 return (ENOBUFS); 3120 } 3121 3122 if (rxs->rxs_mbuf != NULL) 3123 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3124 3125 rxs->rxs_mbuf = m; 3126 3127 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3128 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3129 BUS_DMA_READ|BUS_DMA_NOWAIT); 3130 if (error) { 3131 /* XXX XXX XXX */ 3132 printf("%s: unable to load rx DMA map %d, error = %d\n", 3133 sc->sc_dev.dv_xname, idx, error); 3134 panic("wm_add_rxbuf"); 3135 } 3136 3137 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3138 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3139 3140 WM_INIT_RXDESC(sc, idx); 3141 3142 return (0); 3143 } 3144 3145 /* 3146 * wm_set_ral: 3147 * 3148 * Set an entery in the receive address list. 3149 */ 3150 static void 3151 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3152 { 3153 uint32_t ral_lo, ral_hi; 3154 3155 if (enaddr != NULL) { 3156 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3157 (enaddr[3] << 24); 3158 ral_hi = enaddr[4] | (enaddr[5] << 8); 3159 ral_hi |= RAL_AV; 3160 } else { 3161 ral_lo = 0; 3162 ral_hi = 0; 3163 } 3164 3165 if (sc->sc_type >= WM_T_82544) { 3166 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3167 ral_lo); 3168 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3169 ral_hi); 3170 } else { 3171 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3172 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3173 } 3174 } 3175 3176 /* 3177 * wm_mchash: 3178 * 3179 * Compute the hash of the multicast address for the 4096-bit 3180 * multicast filter. 3181 */ 3182 static uint32_t 3183 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3184 { 3185 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3186 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3187 uint32_t hash; 3188 3189 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3190 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3191 3192 return (hash & 0xfff); 3193 } 3194 3195 /* 3196 * wm_set_filter: 3197 * 3198 * Set up the receive filter. 3199 */ 3200 static void 3201 wm_set_filter(struct wm_softc *sc) 3202 { 3203 struct ethercom *ec = &sc->sc_ethercom; 3204 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3205 struct ether_multi *enm; 3206 struct ether_multistep step; 3207 bus_addr_t mta_reg; 3208 uint32_t hash, reg, bit; 3209 int i; 3210 3211 if (sc->sc_type >= WM_T_82544) 3212 mta_reg = WMREG_CORDOVA_MTA; 3213 else 3214 mta_reg = WMREG_MTA; 3215 3216 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3217 3218 if (ifp->if_flags & IFF_BROADCAST) 3219 sc->sc_rctl |= RCTL_BAM; 3220 if (ifp->if_flags & IFF_PROMISC) { 3221 sc->sc_rctl |= RCTL_UPE; 3222 goto allmulti; 3223 } 3224 3225 /* 3226 * Set the station address in the first RAL slot, and 3227 * clear the remaining slots. 3228 */ 3229 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3230 for (i = 1; i < WM_RAL_TABSIZE; i++) 3231 wm_set_ral(sc, NULL, i); 3232 3233 /* Clear out the multicast table. */ 3234 for (i = 0; i < WM_MC_TABSIZE; i++) 3235 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3236 3237 ETHER_FIRST_MULTI(step, ec, enm); 3238 while (enm != NULL) { 3239 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3240 /* 3241 * We must listen to a range of multicast addresses. 3242 * For now, just accept all multicasts, rather than 3243 * trying to set only those filter bits needed to match 3244 * the range. (At this time, the only use of address 3245 * ranges is for IP multicast routing, for which the 3246 * range is big enough to require all bits set.) 3247 */ 3248 goto allmulti; 3249 } 3250 3251 hash = wm_mchash(sc, enm->enm_addrlo); 3252 3253 reg = (hash >> 5) & 0x7f; 3254 bit = hash & 0x1f; 3255 3256 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3257 hash |= 1U << bit; 3258 3259 /* XXX Hardware bug?? */ 3260 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3261 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3262 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3263 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3264 } else 3265 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3266 3267 ETHER_NEXT_MULTI(step, enm); 3268 } 3269 3270 ifp->if_flags &= ~IFF_ALLMULTI; 3271 goto setit; 3272 3273 allmulti: 3274 ifp->if_flags |= IFF_ALLMULTI; 3275 sc->sc_rctl |= RCTL_MPE; 3276 3277 setit: 3278 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3279 } 3280 3281 /* 3282 * wm_tbi_mediainit: 3283 * 3284 * Initialize media for use on 1000BASE-X devices. 3285 */ 3286 static void 3287 wm_tbi_mediainit(struct wm_softc *sc) 3288 { 3289 const char *sep = ""; 3290 3291 if (sc->sc_type < WM_T_82543) 3292 sc->sc_tipg = TIPG_WM_DFLT; 3293 else 3294 sc->sc_tipg = TIPG_LG_DFLT; 3295 3296 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3297 wm_tbi_mediastatus); 3298 3299 /* 3300 * SWD Pins: 3301 * 3302 * 0 = Link LED (output) 3303 * 1 = Loss Of Signal (input) 3304 */ 3305 sc->sc_ctrl |= CTRL_SWDPIO(0); 3306 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3307 3308 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3309 3310 #define ADD(ss, mm, dd) \ 3311 do { \ 3312 aprint_normal("%s%s", sep, ss); \ 3313 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3314 sep = ", "; \ 3315 } while (/*CONSTCOND*/0) 3316 3317 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3318 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3319 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3320 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3321 aprint_normal("\n"); 3322 3323 #undef ADD 3324 3325 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3326 } 3327 3328 /* 3329 * wm_tbi_mediastatus: [ifmedia interface function] 3330 * 3331 * Get the current interface media status on a 1000BASE-X device. 3332 */ 3333 static void 3334 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3335 { 3336 struct wm_softc *sc = ifp->if_softc; 3337 uint32_t ctrl; 3338 3339 ifmr->ifm_status = IFM_AVALID; 3340 ifmr->ifm_active = IFM_ETHER; 3341 3342 if (sc->sc_tbi_linkup == 0) { 3343 ifmr->ifm_active |= IFM_NONE; 3344 return; 3345 } 3346 3347 ifmr->ifm_status |= IFM_ACTIVE; 3348 ifmr->ifm_active |= IFM_1000_SX; 3349 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3350 ifmr->ifm_active |= IFM_FDX; 3351 ctrl = CSR_READ(sc, WMREG_CTRL); 3352 if (ctrl & CTRL_RFCE) 3353 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3354 if (ctrl & CTRL_TFCE) 3355 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3356 } 3357 3358 /* 3359 * wm_tbi_mediachange: [ifmedia interface function] 3360 * 3361 * Set hardware to newly-selected media on a 1000BASE-X device. 3362 */ 3363 static int 3364 wm_tbi_mediachange(struct ifnet *ifp) 3365 { 3366 struct wm_softc *sc = ifp->if_softc; 3367 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3368 uint32_t status; 3369 int i; 3370 3371 sc->sc_txcw = ife->ifm_data; 3372 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3373 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3374 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3375 sc->sc_txcw |= TXCW_ANE; 3376 3377 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3378 delay(10000); 3379 3380 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3381 3382 sc->sc_tbi_anstate = 0; 3383 3384 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3385 /* Have signal; wait for the link to come up. */ 3386 for (i = 0; i < 50; i++) { 3387 delay(10000); 3388 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3389 break; 3390 } 3391 3392 status = CSR_READ(sc, WMREG_STATUS); 3393 if (status & STATUS_LU) { 3394 /* Link is up. */ 3395 DPRINTF(WM_DEBUG_LINK, 3396 ("%s: LINK: set media -> link up %s\n", 3397 sc->sc_dev.dv_xname, 3398 (status & STATUS_FD) ? "FDX" : "HDX")); 3399 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3400 sc->sc_fcrtl &= ~FCRTL_XONE; 3401 if (status & STATUS_FD) 3402 sc->sc_tctl |= 3403 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3404 else 3405 sc->sc_tctl |= 3406 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3407 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3408 sc->sc_fcrtl |= FCRTL_XONE; 3409 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3410 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3411 WMREG_OLD_FCRTL : WMREG_FCRTL, 3412 sc->sc_fcrtl); 3413 sc->sc_tbi_linkup = 1; 3414 } else { 3415 /* Link is down. */ 3416 DPRINTF(WM_DEBUG_LINK, 3417 ("%s: LINK: set media -> link down\n", 3418 sc->sc_dev.dv_xname)); 3419 sc->sc_tbi_linkup = 0; 3420 } 3421 } else { 3422 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3423 sc->sc_dev.dv_xname)); 3424 sc->sc_tbi_linkup = 0; 3425 } 3426 3427 wm_tbi_set_linkled(sc); 3428 3429 return (0); 3430 } 3431 3432 /* 3433 * wm_tbi_set_linkled: 3434 * 3435 * Update the link LED on 1000BASE-X devices. 3436 */ 3437 static void 3438 wm_tbi_set_linkled(struct wm_softc *sc) 3439 { 3440 3441 if (sc->sc_tbi_linkup) 3442 sc->sc_ctrl |= CTRL_SWDPIN(0); 3443 else 3444 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3445 3446 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3447 } 3448 3449 /* 3450 * wm_tbi_check_link: 3451 * 3452 * Check the link on 1000BASE-X devices. 3453 */ 3454 static void 3455 wm_tbi_check_link(struct wm_softc *sc) 3456 { 3457 uint32_t rxcw, ctrl, status; 3458 3459 if (sc->sc_tbi_anstate == 0) 3460 return; 3461 else if (sc->sc_tbi_anstate > 1) { 3462 DPRINTF(WM_DEBUG_LINK, 3463 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3464 sc->sc_tbi_anstate)); 3465 sc->sc_tbi_anstate--; 3466 return; 3467 } 3468 3469 sc->sc_tbi_anstate = 0; 3470 3471 rxcw = CSR_READ(sc, WMREG_RXCW); 3472 ctrl = CSR_READ(sc, WMREG_CTRL); 3473 status = CSR_READ(sc, WMREG_STATUS); 3474 3475 if ((status & STATUS_LU) == 0) { 3476 DPRINTF(WM_DEBUG_LINK, 3477 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3478 sc->sc_tbi_linkup = 0; 3479 } else { 3480 DPRINTF(WM_DEBUG_LINK, 3481 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3482 (status & STATUS_FD) ? "FDX" : "HDX")); 3483 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3484 sc->sc_fcrtl &= ~FCRTL_XONE; 3485 if (status & STATUS_FD) 3486 sc->sc_tctl |= 3487 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3488 else 3489 sc->sc_tctl |= 3490 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3491 if (ctrl & CTRL_TFCE) 3492 sc->sc_fcrtl |= FCRTL_XONE; 3493 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3494 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3495 WMREG_OLD_FCRTL : WMREG_FCRTL, 3496 sc->sc_fcrtl); 3497 sc->sc_tbi_linkup = 1; 3498 } 3499 3500 wm_tbi_set_linkled(sc); 3501 } 3502 3503 /* 3504 * wm_gmii_reset: 3505 * 3506 * Reset the PHY. 3507 */ 3508 static void 3509 wm_gmii_reset(struct wm_softc *sc) 3510 { 3511 uint32_t reg; 3512 3513 if (sc->sc_type >= WM_T_82544) { 3514 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3515 delay(20000); 3516 3517 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3518 delay(20000); 3519 } else { 3520 /* The PHY reset pin is active-low. */ 3521 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3522 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3523 CTRL_EXT_SWDPIN(4)); 3524 reg |= CTRL_EXT_SWDPIO(4); 3525 3526 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3527 delay(10); 3528 3529 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3530 delay(10); 3531 3532 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3533 delay(10); 3534 #if 0 3535 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3536 #endif 3537 } 3538 } 3539 3540 /* 3541 * wm_gmii_mediainit: 3542 * 3543 * Initialize media for use on 1000BASE-T devices. 3544 */ 3545 static void 3546 wm_gmii_mediainit(struct wm_softc *sc) 3547 { 3548 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3549 3550 /* We have MII. */ 3551 sc->sc_flags |= WM_F_HAS_MII; 3552 3553 sc->sc_tipg = TIPG_1000T_DFLT; 3554 3555 /* 3556 * Let the chip set speed/duplex on its own based on 3557 * signals from the PHY. 3558 */ 3559 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3560 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3561 3562 /* Initialize our media structures and probe the GMII. */ 3563 sc->sc_mii.mii_ifp = ifp; 3564 3565 if (sc->sc_type >= WM_T_82544) { 3566 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3567 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3568 } else { 3569 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3570 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3571 } 3572 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3573 3574 wm_gmii_reset(sc); 3575 3576 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3577 wm_gmii_mediastatus); 3578 3579 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3580 MII_OFFSET_ANY, MIIF_DOPAUSE); 3581 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3582 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3583 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3584 } else 3585 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3586 } 3587 3588 /* 3589 * wm_gmii_mediastatus: [ifmedia interface function] 3590 * 3591 * Get the current interface media status on a 1000BASE-T device. 3592 */ 3593 static void 3594 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3595 { 3596 struct wm_softc *sc = ifp->if_softc; 3597 3598 mii_pollstat(&sc->sc_mii); 3599 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3600 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3601 sc->sc_flowflags; 3602 } 3603 3604 /* 3605 * wm_gmii_mediachange: [ifmedia interface function] 3606 * 3607 * Set hardware to newly-selected media on a 1000BASE-T device. 3608 */ 3609 static int 3610 wm_gmii_mediachange(struct ifnet *ifp) 3611 { 3612 struct wm_softc *sc = ifp->if_softc; 3613 3614 if (ifp->if_flags & IFF_UP) 3615 mii_mediachg(&sc->sc_mii); 3616 return (0); 3617 } 3618 3619 #define MDI_IO CTRL_SWDPIN(2) 3620 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3621 #define MDI_CLK CTRL_SWDPIN(3) 3622 3623 static void 3624 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3625 { 3626 uint32_t i, v; 3627 3628 v = CSR_READ(sc, WMREG_CTRL); 3629 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3630 v |= MDI_DIR | CTRL_SWDPIO(3); 3631 3632 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3633 if (data & i) 3634 v |= MDI_IO; 3635 else 3636 v &= ~MDI_IO; 3637 CSR_WRITE(sc, WMREG_CTRL, v); 3638 delay(10); 3639 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3640 delay(10); 3641 CSR_WRITE(sc, WMREG_CTRL, v); 3642 delay(10); 3643 } 3644 } 3645 3646 static uint32_t 3647 i82543_mii_recvbits(struct wm_softc *sc) 3648 { 3649 uint32_t v, i, data = 0; 3650 3651 v = CSR_READ(sc, WMREG_CTRL); 3652 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3653 v |= CTRL_SWDPIO(3); 3654 3655 CSR_WRITE(sc, WMREG_CTRL, v); 3656 delay(10); 3657 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3658 delay(10); 3659 CSR_WRITE(sc, WMREG_CTRL, v); 3660 delay(10); 3661 3662 for (i = 0; i < 16; i++) { 3663 data <<= 1; 3664 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3665 delay(10); 3666 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3667 data |= 1; 3668 CSR_WRITE(sc, WMREG_CTRL, v); 3669 delay(10); 3670 } 3671 3672 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3673 delay(10); 3674 CSR_WRITE(sc, WMREG_CTRL, v); 3675 delay(10); 3676 3677 return (data); 3678 } 3679 3680 #undef MDI_IO 3681 #undef MDI_DIR 3682 #undef MDI_CLK 3683 3684 /* 3685 * wm_gmii_i82543_readreg: [mii interface function] 3686 * 3687 * Read a PHY register on the GMII (i82543 version). 3688 */ 3689 static int 3690 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3691 { 3692 struct wm_softc *sc = (void *) self; 3693 int rv; 3694 3695 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3696 i82543_mii_sendbits(sc, reg | (phy << 5) | 3697 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3698 rv = i82543_mii_recvbits(sc) & 0xffff; 3699 3700 DPRINTF(WM_DEBUG_GMII, 3701 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3702 sc->sc_dev.dv_xname, phy, reg, rv)); 3703 3704 return (rv); 3705 } 3706 3707 /* 3708 * wm_gmii_i82543_writereg: [mii interface function] 3709 * 3710 * Write a PHY register on the GMII (i82543 version). 3711 */ 3712 static void 3713 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3714 { 3715 struct wm_softc *sc = (void *) self; 3716 3717 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3718 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3719 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3720 (MII_COMMAND_START << 30), 32); 3721 } 3722 3723 /* 3724 * wm_gmii_i82544_readreg: [mii interface function] 3725 * 3726 * Read a PHY register on the GMII. 3727 */ 3728 static int 3729 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3730 { 3731 struct wm_softc *sc = (void *) self; 3732 uint32_t mdic = 0; 3733 int i, rv; 3734 3735 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3736 MDIC_REGADD(reg)); 3737 3738 for (i = 0; i < 100; i++) { 3739 mdic = CSR_READ(sc, WMREG_MDIC); 3740 if (mdic & MDIC_READY) 3741 break; 3742 delay(10); 3743 } 3744 3745 if ((mdic & MDIC_READY) == 0) { 3746 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3747 sc->sc_dev.dv_xname, phy, reg); 3748 rv = 0; 3749 } else if (mdic & MDIC_E) { 3750 #if 0 /* This is normal if no PHY is present. */ 3751 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3752 sc->sc_dev.dv_xname, phy, reg); 3753 #endif 3754 rv = 0; 3755 } else { 3756 rv = MDIC_DATA(mdic); 3757 if (rv == 0xffff) 3758 rv = 0; 3759 } 3760 3761 return (rv); 3762 } 3763 3764 /* 3765 * wm_gmii_i82544_writereg: [mii interface function] 3766 * 3767 * Write a PHY register on the GMII. 3768 */ 3769 static void 3770 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3771 { 3772 struct wm_softc *sc = (void *) self; 3773 uint32_t mdic = 0; 3774 int i; 3775 3776 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3777 MDIC_REGADD(reg) | MDIC_DATA(val)); 3778 3779 for (i = 0; i < 100; i++) { 3780 mdic = CSR_READ(sc, WMREG_MDIC); 3781 if (mdic & MDIC_READY) 3782 break; 3783 delay(10); 3784 } 3785 3786 if ((mdic & MDIC_READY) == 0) 3787 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3788 sc->sc_dev.dv_xname, phy, reg); 3789 else if (mdic & MDIC_E) 3790 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3791 sc->sc_dev.dv_xname, phy, reg); 3792 } 3793 3794 /* 3795 * wm_gmii_statchg: [mii interface function] 3796 * 3797 * Callback from MII layer when media changes. 3798 */ 3799 static void 3800 wm_gmii_statchg(struct device *self) 3801 { 3802 struct wm_softc *sc = (void *) self; 3803 struct mii_data *mii = &sc->sc_mii; 3804 3805 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3806 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3807 sc->sc_fcrtl &= ~FCRTL_XONE; 3808 3809 /* 3810 * Get flow control negotiation result. 3811 */ 3812 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3813 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3814 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3815 mii->mii_media_active &= ~IFM_ETH_FMASK; 3816 } 3817 3818 if (sc->sc_flowflags & IFM_FLOW) { 3819 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3820 sc->sc_ctrl |= CTRL_TFCE; 3821 sc->sc_fcrtl |= FCRTL_XONE; 3822 } 3823 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3824 sc->sc_ctrl |= CTRL_RFCE; 3825 } 3826 3827 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3828 DPRINTF(WM_DEBUG_LINK, 3829 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3830 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3831 } else { 3832 DPRINTF(WM_DEBUG_LINK, 3833 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3834 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3835 } 3836 3837 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3838 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3839 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3840 : WMREG_FCRTL, sc->sc_fcrtl); 3841 } 3842
Indexes created Wed Sep 24 22:09:59 GMT 2025