if_wm.c revision 1.104
1 /* $NetBSD: if_wm.c,v 1.104 2005/07/25 18:26:24 ross Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.104 2005/07/25 18:26:24 ross Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make serveral things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 280 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 281 282 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 283 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 284 285 struct evcnt sc_ev_tu; /* Tx underrun */ 286 287 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 288 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 289 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 290 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 291 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 292 #endif /* WM_EVENT_COUNTERS */ 293 294 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 295 296 int sc_txfree; /* number of free Tx descriptors */ 297 int sc_txnext; /* next ready Tx descriptor */ 298 299 int sc_txsfree; /* number of free Tx jobs */ 300 int sc_txsnext; /* next free Tx job */ 301 int sc_txsdirty; /* dirty Tx jobs */ 302 303 /* These 5 variables are used only on the 82547. */ 304 int sc_txfifo_size; /* Tx FIFO size */ 305 int sc_txfifo_head; /* current head of FIFO */ 306 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 307 int sc_txfifo_stall; /* Tx FIFO is stalled */ 308 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 309 310 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 311 312 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 313 int sc_rxdiscard; 314 int sc_rxlen; 315 struct mbuf *sc_rxhead; 316 struct mbuf *sc_rxtail; 317 struct mbuf **sc_rxtailp; 318 319 uint32_t sc_ctrl; /* prototype CTRL register */ 320 #if 0 321 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 322 #endif 323 uint32_t sc_icr; /* prototype interrupt bits */ 324 uint32_t sc_itr; /* prototype intr throttling reg */ 325 uint32_t sc_tctl; /* prototype TCTL register */ 326 uint32_t sc_rctl; /* prototype RCTL register */ 327 uint32_t sc_txcw; /* prototype TXCW register */ 328 uint32_t sc_tipg; /* prototype TIPG register */ 329 uint32_t sc_fcrtl; /* prototype FCRTL register */ 330 uint32_t sc_pba; /* prototype PBA register */ 331 332 int sc_tbi_linkup; /* TBI link status */ 333 int sc_tbi_anstate; /* autonegotiation state */ 334 335 int sc_mchash_type; /* multicast filter offset */ 336 337 #if NRND > 0 338 rndsource_element_t rnd_source; /* random source */ 339 #endif 340 }; 341 342 #define WM_RXCHAIN_RESET(sc) \ 343 do { \ 344 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 345 *(sc)->sc_rxtailp = NULL; \ 346 (sc)->sc_rxlen = 0; \ 347 } while (/*CONSTCOND*/0) 348 349 #define WM_RXCHAIN_LINK(sc, m) \ 350 do { \ 351 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 352 (sc)->sc_rxtailp = &(m)->m_next; \ 353 } while (/*CONSTCOND*/0) 354 355 /* sc_flags */ 356 #define WM_F_HAS_MII 0x01 /* has MII */ 357 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 358 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 359 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 360 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 361 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 362 #define WM_F_CSA 0x80 /* bus is CSA */ 363 364 #ifdef WM_EVENT_COUNTERS 365 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 366 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 367 #else 368 #define WM_EVCNT_INCR(ev) /* nothing */ 369 #define WM_EVCNT_ADD(ev, val) /* nothing */ 370 #endif 371 372 #define CSR_READ(sc, reg) \ 373 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 374 #define CSR_WRITE(sc, reg, val) \ 375 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 376 #define CSR_WRITE_FLUSH(sc) \ 377 (void) CSR_READ((sc), WMREG_STATUS) 378 379 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 380 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 381 382 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 383 #define WM_CDTXADDR_HI(sc, x) \ 384 (sizeof(bus_addr_t) == 8 ? \ 385 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 386 387 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 388 #define WM_CDRXADDR_HI(sc, x) \ 389 (sizeof(bus_addr_t) == 8 ? \ 390 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 391 392 #define WM_CDTXSYNC(sc, x, n, ops) \ 393 do { \ 394 int __x, __n; \ 395 \ 396 __x = (x); \ 397 __n = (n); \ 398 \ 399 /* If it will wrap around, sync to the end of the ring. */ \ 400 if ((__x + __n) > WM_NTXDESC(sc)) { \ 401 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 402 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 403 (WM_NTXDESC(sc) - __x), (ops)); \ 404 __n -= (WM_NTXDESC(sc) - __x); \ 405 __x = 0; \ 406 } \ 407 \ 408 /* Now sync whatever is left. */ \ 409 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 410 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 411 } while (/*CONSTCOND*/0) 412 413 #define WM_CDRXSYNC(sc, x, ops) \ 414 do { \ 415 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 416 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 417 } while (/*CONSTCOND*/0) 418 419 #define WM_INIT_RXDESC(sc, x) \ 420 do { \ 421 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 422 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 423 struct mbuf *__m = __rxs->rxs_mbuf; \ 424 \ 425 /* \ 426 * Note: We scoot the packet forward 2 bytes in the buffer \ 427 * so that the payload after the Ethernet header is aligned \ 428 * to a 4-byte boundary. \ 429 * \ 430 * XXX BRAINDAMAGE ALERT! \ 431 * The stupid chip uses the same size for every buffer, which \ 432 * is set in the Receive Control register. We are using the 2K \ 433 * size option, but what we REALLY want is (2K - 2)! For this \ 434 * reason, we can't "scoot" packets longer than the standard \ 435 * Ethernet MTU. On strict-alignment platforms, if the total \ 436 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 437 * the upper layer copy the headers. \ 438 */ \ 439 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 440 \ 441 wm_set_dma_addr(&__rxd->wrx_addr, \ 442 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 443 __rxd->wrx_len = 0; \ 444 __rxd->wrx_cksum = 0; \ 445 __rxd->wrx_status = 0; \ 446 __rxd->wrx_errors = 0; \ 447 __rxd->wrx_special = 0; \ 448 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 449 \ 450 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 451 } while (/*CONSTCOND*/0) 452 453 static void wm_start(struct ifnet *); 454 static void wm_watchdog(struct ifnet *); 455 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 456 static int wm_init(struct ifnet *); 457 static void wm_stop(struct ifnet *, int); 458 459 static void wm_shutdown(void *); 460 461 static void wm_reset(struct wm_softc *); 462 static void wm_rxdrain(struct wm_softc *); 463 static int wm_add_rxbuf(struct wm_softc *, int); 464 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 465 static void wm_tick(void *); 466 467 static void wm_set_filter(struct wm_softc *); 468 469 static int wm_intr(void *); 470 static void wm_txintr(struct wm_softc *); 471 static void wm_rxintr(struct wm_softc *); 472 static void wm_linkintr(struct wm_softc *, uint32_t); 473 474 static void wm_tbi_mediainit(struct wm_softc *); 475 static int wm_tbi_mediachange(struct ifnet *); 476 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 477 478 static void wm_tbi_set_linkled(struct wm_softc *); 479 static void wm_tbi_check_link(struct wm_softc *); 480 481 static void wm_gmii_reset(struct wm_softc *); 482 483 static int wm_gmii_i82543_readreg(struct device *, int, int); 484 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 485 486 static int wm_gmii_i82544_readreg(struct device *, int, int); 487 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 488 489 static void wm_gmii_statchg(struct device *); 490 491 static void wm_gmii_mediainit(struct wm_softc *); 492 static int wm_gmii_mediachange(struct ifnet *); 493 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 494 495 static int wm_match(struct device *, struct cfdata *, void *); 496 static void wm_attach(struct device *, struct device *, void *); 497 498 CFATTACH_DECL(wm, sizeof(struct wm_softc), 499 wm_match, wm_attach, NULL, NULL); 500 501 static void wm_82547_txfifo_stall(void *); 502 503 /* 504 * Devices supported by this driver. 505 */ 506 static const struct wm_product { 507 pci_vendor_id_t wmp_vendor; 508 pci_product_id_t wmp_product; 509 const char *wmp_name; 510 wm_chip_type wmp_type; 511 int wmp_flags; 512 #define WMP_F_1000X 0x01 513 #define WMP_F_1000T 0x02 514 } wm_products[] = { 515 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 516 "Intel i82542 1000BASE-X Ethernet", 517 WM_T_82542_2_1, WMP_F_1000X }, 518 519 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 520 "Intel i82543GC 1000BASE-X Ethernet", 521 WM_T_82543, WMP_F_1000X }, 522 523 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 524 "Intel i82543GC 1000BASE-T Ethernet", 525 WM_T_82543, WMP_F_1000T }, 526 527 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 528 "Intel i82544EI 1000BASE-T Ethernet", 529 WM_T_82544, WMP_F_1000T }, 530 531 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 532 "Intel i82544EI 1000BASE-X Ethernet", 533 WM_T_82544, WMP_F_1000X }, 534 535 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 536 "Intel i82544GC 1000BASE-T Ethernet", 537 WM_T_82544, WMP_F_1000T }, 538 539 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 540 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 541 WM_T_82544, WMP_F_1000T }, 542 543 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 544 "Intel i82540EM 1000BASE-T Ethernet", 545 WM_T_82540, WMP_F_1000T }, 546 547 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 548 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 549 WM_T_82540, WMP_F_1000T }, 550 551 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 552 "Intel i82540EP 1000BASE-T Ethernet", 553 WM_T_82540, WMP_F_1000T }, 554 555 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 556 "Intel i82540EP 1000BASE-T Ethernet", 557 WM_T_82540, WMP_F_1000T }, 558 559 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 560 "Intel i82540EP 1000BASE-T Ethernet", 561 WM_T_82540, WMP_F_1000T }, 562 563 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 564 "Intel i82545EM 1000BASE-T Ethernet", 565 WM_T_82545, WMP_F_1000T }, 566 567 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 568 "Intel i82545GM 1000BASE-T Ethernet", 569 WM_T_82545_3, WMP_F_1000T }, 570 571 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 572 "Intel i82545GM 1000BASE-X Ethernet", 573 WM_T_82545_3, WMP_F_1000X }, 574 #if 0 575 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 576 "Intel i82545GM Gigabit Ethernet (SERDES)", 577 WM_T_82545_3, WMP_F_SERDES }, 578 #endif 579 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 580 "Intel i82546EB 1000BASE-T Ethernet", 581 WM_T_82546, WMP_F_1000T }, 582 583 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 584 "Intel i82546EB 1000BASE-T Ethernet", 585 WM_T_82546, WMP_F_1000T }, 586 587 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 588 "Intel i82545EM 1000BASE-X Ethernet", 589 WM_T_82545, WMP_F_1000X }, 590 591 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 592 "Intel i82546EB 1000BASE-X Ethernet", 593 WM_T_82546, WMP_F_1000X }, 594 595 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 596 "Intel i82546GB 1000BASE-T Ethernet", 597 WM_T_82546_3, WMP_F_1000T }, 598 599 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 600 "Intel i82546GB 1000BASE-X Ethernet", 601 WM_T_82546_3, WMP_F_1000X }, 602 #if 0 603 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 604 "Intel i82546GB Gigabit Ethernet (SERDES)", 605 WM_T_82546_3, WMP_F_SERDES }, 606 #endif 607 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 608 "Intel i82541EI 1000BASE-T Ethernet", 609 WM_T_82541, WMP_F_1000T }, 610 611 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 612 "Intel i82541EI Mobile 1000BASE-T Ethernet", 613 WM_T_82541, WMP_F_1000T }, 614 615 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 616 "Intel i82541ER 1000BASE-T Ethernet", 617 WM_T_82541_2, WMP_F_1000T }, 618 619 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 620 "Intel i82541GI 1000BASE-T Ethernet", 621 WM_T_82541_2, WMP_F_1000T }, 622 623 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 624 "Intel i82541GI Mobile 1000BASE-T Ethernet", 625 WM_T_82541_2, WMP_F_1000T }, 626 627 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 628 "Intel i82541PI 1000BASE-T Ethernet", 629 WM_T_82541_2, WMP_F_1000T }, 630 631 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 632 "Intel i82547EI 1000BASE-T Ethernet", 633 WM_T_82547, WMP_F_1000T }, 634 635 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 636 "Intel i82547GI 1000BASE-T Ethernet", 637 WM_T_82547_2, WMP_F_1000T }, 638 { 0, 0, 639 NULL, 640 0, 0 }, 641 }; 642 643 #ifdef WM_EVENT_COUNTERS 644 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 645 #endif /* WM_EVENT_COUNTERS */ 646 647 #if 0 /* Not currently used */ 648 static __inline uint32_t 649 wm_io_read(struct wm_softc *sc, int reg) 650 { 651 652 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 653 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 654 } 655 #endif 656 657 static __inline void 658 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 659 { 660 661 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 662 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 663 } 664 665 static __inline void 666 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 667 { 668 wa->wa_low = htole32(v & 0xffffffffU); 669 if (sizeof(bus_addr_t) == 8) 670 wa->wa_high = htole32((uint64_t) v >> 32); 671 else 672 wa->wa_high = 0; 673 } 674 675 static const struct wm_product * 676 wm_lookup(const struct pci_attach_args *pa) 677 { 678 const struct wm_product *wmp; 679 680 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 681 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 682 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 683 return (wmp); 684 } 685 return (NULL); 686 } 687 688 static int 689 wm_match(struct device *parent, struct cfdata *cf, void *aux) 690 { 691 struct pci_attach_args *pa = aux; 692 693 if (wm_lookup(pa) != NULL) 694 return (1); 695 696 return (0); 697 } 698 699 static void 700 wm_attach(struct device *parent, struct device *self, void *aux) 701 { 702 struct wm_softc *sc = (void *) self; 703 struct pci_attach_args *pa = aux; 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 pci_chipset_tag_t pc = pa->pa_pc; 706 pci_intr_handle_t ih; 707 size_t cdata_size; 708 const char *intrstr = NULL; 709 const char *eetype; 710 bus_space_tag_t memt; 711 bus_space_handle_t memh; 712 bus_dma_segment_t seg; 713 int memh_valid; 714 int i, rseg, error; 715 const struct wm_product *wmp; 716 uint8_t enaddr[ETHER_ADDR_LEN]; 717 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 718 pcireg_t preg, memtype; 719 uint32_t reg; 720 int pmreg; 721 722 callout_init(&sc->sc_tick_ch); 723 724 wmp = wm_lookup(pa); 725 if (wmp == NULL) { 726 printf("\n"); 727 panic("wm_attach: impossible"); 728 } 729 730 if (pci_dma64_available(pa)) 731 sc->sc_dmat = pa->pa_dmat64; 732 else 733 sc->sc_dmat = pa->pa_dmat; 734 735 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 736 aprint_naive(": Ethernet controller\n"); 737 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 738 739 sc->sc_type = wmp->wmp_type; 740 if (sc->sc_type < WM_T_82543) { 741 if (preg < 2) { 742 aprint_error("%s: i82542 must be at least rev. 2\n", 743 sc->sc_dev.dv_xname); 744 return; 745 } 746 if (preg < 3) 747 sc->sc_type = WM_T_82542_2_0; 748 } 749 750 /* 751 * Map the device. All devices support memory-mapped acccess, 752 * and it is really required for normal operation. 753 */ 754 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 755 switch (memtype) { 756 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 757 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 758 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 759 memtype, 0, &memt, &memh, NULL, NULL) == 0); 760 break; 761 default: 762 memh_valid = 0; 763 } 764 765 if (memh_valid) { 766 sc->sc_st = memt; 767 sc->sc_sh = memh; 768 } else { 769 aprint_error("%s: unable to map device registers\n", 770 sc->sc_dev.dv_xname); 771 return; 772 } 773 774 /* 775 * In addition, i82544 and later support I/O mapped indirect 776 * register access. It is not desirable (nor supported in 777 * this driver) to use it for normal operation, though it is 778 * required to work around bugs in some chip versions. 779 */ 780 if (sc->sc_type >= WM_T_82544) { 781 /* First we have to find the I/O BAR. */ 782 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 783 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 784 PCI_MAPREG_TYPE_IO) 785 break; 786 } 787 if (i == PCI_MAPREG_END) 788 aprint_error("%s: WARNING: unable to find I/O BAR\n", 789 sc->sc_dev.dv_xname); 790 else { 791 /* 792 * The i8254x doesn't apparently respond when the 793 * I/O BAR is 0, which looks somewhat like it's not 794 * been configured. 795 */ 796 preg = pci_conf_read(pc, pa->pa_tag, i); 797 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 798 aprint_error("%s: WARNING: I/O BAR at zero.\n", 799 sc->sc_dev.dv_xname); 800 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 801 0, &sc->sc_iot, &sc->sc_ioh, 802 NULL, NULL) == 0) { 803 sc->sc_flags |= WM_F_IOH_VALID; 804 } else { 805 aprint_error("%s: WARNING: unable to map " 806 "I/O space\n", sc->sc_dev.dv_xname); 807 } 808 } 809 810 } 811 812 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 813 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 814 preg |= PCI_COMMAND_MASTER_ENABLE; 815 if (sc->sc_type < WM_T_82542_2_1) 816 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 817 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 818 819 /* Get it out of power save mode, if needed. */ 820 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 821 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 822 PCI_PMCSR_STATE_MASK; 823 if (preg == PCI_PMCSR_STATE_D3) { 824 /* 825 * The card has lost all configuration data in 826 * this state, so punt. 827 */ 828 aprint_error("%s: unable to wake from power state D3\n", 829 sc->sc_dev.dv_xname); 830 return; 831 } 832 if (preg != PCI_PMCSR_STATE_D0) { 833 aprint_normal("%s: waking up from power state D%d\n", 834 sc->sc_dev.dv_xname, preg); 835 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 836 PCI_PMCSR_STATE_D0); 837 } 838 } 839 840 /* 841 * Map and establish our interrupt. 842 */ 843 if (pci_intr_map(pa, &ih)) { 844 aprint_error("%s: unable to map interrupt\n", 845 sc->sc_dev.dv_xname); 846 return; 847 } 848 intrstr = pci_intr_string(pc, ih); 849 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 850 if (sc->sc_ih == NULL) { 851 aprint_error("%s: unable to establish interrupt", 852 sc->sc_dev.dv_xname); 853 if (intrstr != NULL) 854 aprint_normal(" at %s", intrstr); 855 aprint_normal("\n"); 856 return; 857 } 858 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 859 860 /* 861 * Determine a few things about the bus we're connected to. 862 */ 863 if (sc->sc_type < WM_T_82543) { 864 /* We don't really know the bus characteristics here. */ 865 sc->sc_bus_speed = 33; 866 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 867 /* 868 * CSA (Communication Streaming Architecture) is about as fast 869 * a 32-bit 66MHz PCI Bus. 870 */ 871 sc->sc_flags |= WM_F_CSA; 872 sc->sc_bus_speed = 66; 873 aprint_verbose("%s: Communication Streaming Architecture\n", 874 sc->sc_dev.dv_xname); 875 if (sc->sc_type == WM_T_82547) { 876 callout_init(&sc->sc_txfifo_ch); 877 callout_setfunc(&sc->sc_txfifo_ch, 878 wm_82547_txfifo_stall, sc); 879 aprint_verbose("%s: using 82547 Tx FIFO stall " 880 "work-around\n", sc->sc_dev.dv_xname); 881 } 882 } else { 883 reg = CSR_READ(sc, WMREG_STATUS); 884 if (reg & STATUS_BUS64) 885 sc->sc_flags |= WM_F_BUS64; 886 if (sc->sc_type >= WM_T_82544 && 887 (reg & STATUS_PCIX_MODE) != 0) { 888 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 889 890 sc->sc_flags |= WM_F_PCIX; 891 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 892 PCI_CAP_PCIX, 893 &sc->sc_pcix_offset, NULL) == 0) 894 aprint_error("%s: unable to find PCIX " 895 "capability\n", sc->sc_dev.dv_xname); 896 else if (sc->sc_type != WM_T_82545_3 && 897 sc->sc_type != WM_T_82546_3) { 898 /* 899 * Work around a problem caused by the BIOS 900 * setting the max memory read byte count 901 * incorrectly. 902 */ 903 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 904 sc->sc_pcix_offset + PCI_PCIX_CMD); 905 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 906 sc->sc_pcix_offset + PCI_PCIX_STATUS); 907 908 bytecnt = 909 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 910 PCI_PCIX_CMD_BYTECNT_SHIFT; 911 maxb = 912 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 913 PCI_PCIX_STATUS_MAXB_SHIFT; 914 if (bytecnt > maxb) { 915 aprint_verbose("%s: resetting PCI-X " 916 "MMRBC: %d -> %d\n", 917 sc->sc_dev.dv_xname, 918 512 << bytecnt, 512 << maxb); 919 pcix_cmd = (pcix_cmd & 920 ~PCI_PCIX_CMD_BYTECNT_MASK) | 921 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 922 pci_conf_write(pa->pa_pc, pa->pa_tag, 923 sc->sc_pcix_offset + PCI_PCIX_CMD, 924 pcix_cmd); 925 } 926 } 927 } 928 /* 929 * The quad port adapter is special; it has a PCIX-PCIX 930 * bridge on the board, and can run the secondary bus at 931 * a higher speed. 932 */ 933 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 934 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 935 : 66; 936 } else if (sc->sc_flags & WM_F_PCIX) { 937 switch (reg & STATUS_PCIXSPD_MASK) { 938 case STATUS_PCIXSPD_50_66: 939 sc->sc_bus_speed = 66; 940 break; 941 case STATUS_PCIXSPD_66_100: 942 sc->sc_bus_speed = 100; 943 break; 944 case STATUS_PCIXSPD_100_133: 945 sc->sc_bus_speed = 133; 946 break; 947 default: 948 aprint_error( 949 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 950 sc->sc_dev.dv_xname, 951 reg & STATUS_PCIXSPD_MASK); 952 sc->sc_bus_speed = 66; 953 } 954 } else 955 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 956 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 957 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 958 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 959 } 960 961 /* 962 * Allocate the control data structures, and create and load the 963 * DMA map for it. 964 * 965 * NOTE: All Tx descriptors must be in the same 4G segment of 966 * memory. So must Rx descriptors. We simplify by allocating 967 * both sets within the same 4G segment. 968 */ 969 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 970 WM_NTXDESC_82542 : WM_NTXDESC_82544; 971 cdata_size = sc->sc_type < WM_T_82544 ? 972 sizeof(struct wm_control_data_82542) : 973 sizeof(struct wm_control_data_82544); 974 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 975 (bus_size_t) 0x100000000ULL, 976 &seg, 1, &rseg, 0)) != 0) { 977 aprint_error( 978 "%s: unable to allocate control data, error = %d\n", 979 sc->sc_dev.dv_xname, error); 980 goto fail_0; 981 } 982 983 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 984 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 985 aprint_error("%s: unable to map control data, error = %d\n", 986 sc->sc_dev.dv_xname, error); 987 goto fail_1; 988 } 989 990 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 991 0, 0, &sc->sc_cddmamap)) != 0) { 992 aprint_error("%s: unable to create control data DMA map, " 993 "error = %d\n", sc->sc_dev.dv_xname, error); 994 goto fail_2; 995 } 996 997 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 998 sc->sc_control_data, cdata_size, NULL, 999 0)) != 0) { 1000 aprint_error( 1001 "%s: unable to load control data DMA map, error = %d\n", 1002 sc->sc_dev.dv_xname, error); 1003 goto fail_3; 1004 } 1005 1006 1007 /* 1008 * Create the transmit buffer DMA maps. 1009 */ 1010 WM_TXQUEUELEN(sc) = 1011 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1012 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1013 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1014 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1015 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1016 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1017 aprint_error("%s: unable to create Tx DMA map %d, " 1018 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1019 goto fail_4; 1020 } 1021 } 1022 1023 /* 1024 * Create the receive buffer DMA maps. 1025 */ 1026 for (i = 0; i < WM_NRXDESC; i++) { 1027 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1028 MCLBYTES, 0, 0, 1029 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1030 aprint_error("%s: unable to create Rx DMA map %d, " 1031 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1032 goto fail_5; 1033 } 1034 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1035 } 1036 1037 /* 1038 * Reset the chip to a known state. 1039 */ 1040 wm_reset(sc); 1041 1042 /* 1043 * Get some information about the EEPROM. 1044 */ 1045 if (sc->sc_type >= WM_T_82540) 1046 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1047 if (sc->sc_type <= WM_T_82544) 1048 sc->sc_ee_addrbits = 6; 1049 else if (sc->sc_type <= WM_T_82546_3) { 1050 reg = CSR_READ(sc, WMREG_EECD); 1051 if (reg & EECD_EE_SIZE) 1052 sc->sc_ee_addrbits = 8; 1053 else 1054 sc->sc_ee_addrbits = 6; 1055 } else if (sc->sc_type <= WM_T_82547_2) { 1056 reg = CSR_READ(sc, WMREG_EECD); 1057 if (reg & EECD_EE_TYPE) { 1058 sc->sc_flags |= WM_F_EEPROM_SPI; 1059 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1060 } else 1061 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1062 } else { 1063 /* Assume everything else is SPI. */ 1064 reg = CSR_READ(sc, WMREG_EECD); 1065 sc->sc_flags |= WM_F_EEPROM_SPI; 1066 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1067 } 1068 if (sc->sc_flags & WM_F_EEPROM_SPI) 1069 eetype = "SPI"; 1070 else 1071 eetype = "MicroWire"; 1072 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1073 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1074 sc->sc_ee_addrbits, eetype); 1075 1076 /* 1077 * Read the Ethernet address from the EEPROM. 1078 */ 1079 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1080 sizeof(myea) / sizeof(myea[0]), myea)) { 1081 aprint_error("%s: unable to read Ethernet address\n", 1082 sc->sc_dev.dv_xname); 1083 return; 1084 } 1085 enaddr[0] = myea[0] & 0xff; 1086 enaddr[1] = myea[0] >> 8; 1087 enaddr[2] = myea[1] & 0xff; 1088 enaddr[3] = myea[1] >> 8; 1089 enaddr[4] = myea[2] & 0xff; 1090 enaddr[5] = myea[2] >> 8; 1091 1092 /* 1093 * Toggle the LSB of the MAC address on the second port 1094 * of the i82546. 1095 */ 1096 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1097 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1098 enaddr[5] ^= 1; 1099 } 1100 1101 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1102 ether_sprintf(enaddr)); 1103 1104 /* 1105 * Read the config info from the EEPROM, and set up various 1106 * bits in the control registers based on their contents. 1107 */ 1108 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1109 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1110 sc->sc_dev.dv_xname); 1111 return; 1112 } 1113 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1114 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1115 sc->sc_dev.dv_xname); 1116 return; 1117 } 1118 if (sc->sc_type >= WM_T_82544) { 1119 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1120 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1121 sc->sc_dev.dv_xname); 1122 return; 1123 } 1124 } 1125 1126 if (cfg1 & EEPROM_CFG1_ILOS) 1127 sc->sc_ctrl |= CTRL_ILOS; 1128 if (sc->sc_type >= WM_T_82544) { 1129 sc->sc_ctrl |= 1130 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1131 CTRL_SWDPIO_SHIFT; 1132 sc->sc_ctrl |= 1133 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1134 CTRL_SWDPINS_SHIFT; 1135 } else { 1136 sc->sc_ctrl |= 1137 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1138 CTRL_SWDPIO_SHIFT; 1139 } 1140 1141 #if 0 1142 if (sc->sc_type >= WM_T_82544) { 1143 if (cfg1 & EEPROM_CFG1_IPS0) 1144 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1145 if (cfg1 & EEPROM_CFG1_IPS1) 1146 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1147 sc->sc_ctrl_ext |= 1148 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1149 CTRL_EXT_SWDPIO_SHIFT; 1150 sc->sc_ctrl_ext |= 1151 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1152 CTRL_EXT_SWDPINS_SHIFT; 1153 } else { 1154 sc->sc_ctrl_ext |= 1155 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1156 CTRL_EXT_SWDPIO_SHIFT; 1157 } 1158 #endif 1159 1160 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1161 #if 0 1162 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1163 #endif 1164 1165 /* 1166 * Set up some register offsets that are different between 1167 * the i82542 and the i82543 and later chips. 1168 */ 1169 if (sc->sc_type < WM_T_82543) { 1170 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1171 sc->sc_tdt_reg = WMREG_OLD_TDT; 1172 } else { 1173 sc->sc_rdt_reg = WMREG_RDT; 1174 sc->sc_tdt_reg = WMREG_TDT; 1175 } 1176 1177 /* 1178 * Determine if we're TBI or GMII mode, and initialize the 1179 * media structures accordingly. 1180 */ 1181 if (sc->sc_type < WM_T_82543 || 1182 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1183 if (wmp->wmp_flags & WMP_F_1000T) 1184 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1185 "product!\n", sc->sc_dev.dv_xname); 1186 wm_tbi_mediainit(sc); 1187 } else { 1188 if (wmp->wmp_flags & WMP_F_1000X) 1189 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1190 "product!\n", sc->sc_dev.dv_xname); 1191 wm_gmii_mediainit(sc); 1192 } 1193 1194 ifp = &sc->sc_ethercom.ec_if; 1195 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1196 ifp->if_softc = sc; 1197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1198 ifp->if_ioctl = wm_ioctl; 1199 ifp->if_start = wm_start; 1200 ifp->if_watchdog = wm_watchdog; 1201 ifp->if_init = wm_init; 1202 ifp->if_stop = wm_stop; 1203 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1204 IFQ_SET_READY(&ifp->if_snd); 1205 1206 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1207 1208 /* 1209 * If we're a i82543 or greater, we can support VLANs. 1210 */ 1211 if (sc->sc_type >= WM_T_82543) 1212 sc->sc_ethercom.ec_capabilities |= 1213 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1214 1215 /* 1216 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1217 * on i82543 and later. 1218 */ 1219 if (sc->sc_type >= WM_T_82543) 1220 ifp->if_capabilities |= 1221 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1222 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1223 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1224 1225 /* 1226 * If we're a i82544 or greater (except i82547), we can do 1227 * TCP segmentation offload. 1228 */ 1229 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1230 ifp->if_capabilities |= IFCAP_TSOv4; 1231 1232 /* 1233 * Attach the interface. 1234 */ 1235 if_attach(ifp); 1236 ether_ifattach(ifp, enaddr); 1237 #if NRND > 0 1238 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1239 RND_TYPE_NET, 0); 1240 #endif 1241 1242 #ifdef WM_EVENT_COUNTERS 1243 /* Attach event counters. */ 1244 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1245 NULL, sc->sc_dev.dv_xname, "txsstall"); 1246 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1247 NULL, sc->sc_dev.dv_xname, "txdstall"); 1248 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1249 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1250 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1251 NULL, sc->sc_dev.dv_xname, "txdw"); 1252 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1253 NULL, sc->sc_dev.dv_xname, "txqe"); 1254 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1255 NULL, sc->sc_dev.dv_xname, "rxintr"); 1256 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1257 NULL, sc->sc_dev.dv_xname, "linkintr"); 1258 1259 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1261 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1262 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1263 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1264 NULL, sc->sc_dev.dv_xname, "txipsum"); 1265 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1266 NULL, sc->sc_dev.dv_xname, "txtusum"); 1267 1268 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1269 NULL, sc->sc_dev.dv_xname, "txtso"); 1270 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1271 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1272 1273 for (i = 0; i < WM_NTXSEGS; i++) { 1274 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1275 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1276 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1277 } 1278 1279 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1280 NULL, sc->sc_dev.dv_xname, "txdrop"); 1281 1282 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1283 NULL, sc->sc_dev.dv_xname, "tu"); 1284 1285 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1287 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1289 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1290 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1291 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1292 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1293 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1294 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1295 #endif /* WM_EVENT_COUNTERS */ 1296 1297 /* 1298 * Make sure the interface is shutdown during reboot. 1299 */ 1300 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1301 if (sc->sc_sdhook == NULL) 1302 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1303 sc->sc_dev.dv_xname); 1304 return; 1305 1306 /* 1307 * Free any resources we've allocated during the failed attach 1308 * attempt. Do this in reverse order and fall through. 1309 */ 1310 fail_5: 1311 for (i = 0; i < WM_NRXDESC; i++) { 1312 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1313 bus_dmamap_destroy(sc->sc_dmat, 1314 sc->sc_rxsoft[i].rxs_dmamap); 1315 } 1316 fail_4: 1317 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1318 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1319 bus_dmamap_destroy(sc->sc_dmat, 1320 sc->sc_txsoft[i].txs_dmamap); 1321 } 1322 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1323 fail_3: 1324 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1325 fail_2: 1326 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1327 cdata_size); 1328 fail_1: 1329 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1330 fail_0: 1331 return; 1332 } 1333 1334 /* 1335 * wm_shutdown: 1336 * 1337 * Make sure the interface is stopped at reboot time. 1338 */ 1339 static void 1340 wm_shutdown(void *arg) 1341 { 1342 struct wm_softc *sc = arg; 1343 1344 wm_stop(&sc->sc_ethercom.ec_if, 1); 1345 } 1346 1347 /* 1348 * wm_tx_offload: 1349 * 1350 * Set up TCP/IP checksumming parameters for the 1351 * specified packet. 1352 */ 1353 static int 1354 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1355 uint8_t *fieldsp) 1356 { 1357 struct mbuf *m0 = txs->txs_mbuf; 1358 struct livengood_tcpip_ctxdesc *t; 1359 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1360 struct ether_header *eh; 1361 int offset, iphl; 1362 uint8_t fields; 1363 1364 /* 1365 * XXX It would be nice if the mbuf pkthdr had offset 1366 * fields for the protocol headers. 1367 */ 1368 1369 eh = mtod(m0, struct ether_header *); 1370 switch (htons(eh->ether_type)) { 1371 case ETHERTYPE_IP: 1372 offset = ETHER_HDR_LEN; 1373 break; 1374 1375 case ETHERTYPE_VLAN: 1376 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1377 break; 1378 1379 default: 1380 /* 1381 * Don't support this protocol or encapsulation. 1382 */ 1383 *fieldsp = 0; 1384 *cmdp = 0; 1385 return (0); 1386 } 1387 1388 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1389 1390 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1391 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1392 seg = 0; 1393 fields = 0; 1394 1395 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1396 int hlen = offset + iphl; 1397 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1398 if (__predict_false(m0->m_len < 1399 (hlen + sizeof(struct tcphdr)))) { 1400 /* 1401 * TCP/IP headers are not in the first mbuf; we need 1402 * to do this the slow and painful way. Let's just 1403 * hope this doesn't happen very often. 1404 */ 1405 struct ip ip; 1406 struct tcphdr th; 1407 1408 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1409 1410 m_copydata(m0, offset, sizeof(ip), &ip); 1411 m_copydata(m0, hlen, sizeof(th), &th); 1412 1413 ip.ip_len = 0; 1414 1415 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1416 sizeof(ip.ip_len), &ip.ip_len); 1417 1418 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1419 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1420 1421 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1422 sizeof(th.th_sum), &th.th_sum); 1423 1424 hlen += th.th_off << 2; 1425 } else { 1426 /* 1427 * TCP/IP headers are in the first mbuf; we can do 1428 * this the easy way. 1429 */ 1430 struct ip *ip = 1431 (struct ip *) (mtod(m0, caddr_t) + offset); 1432 struct tcphdr *th = 1433 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1434 1435 ip->ip_len = 0; 1436 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1437 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1438 1439 hlen += th->th_off << 2; 1440 } 1441 1442 cmd |= WTX_TCPIP_CMD_TSE; 1443 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1444 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1445 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1446 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1447 } 1448 1449 /* 1450 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1451 * offload feature, if we load the context descriptor, we 1452 * MUST provide valid values for IPCSS and TUCSS fields. 1453 */ 1454 1455 ipcs = WTX_TCPIP_IPCSS(offset) | 1456 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1457 WTX_TCPIP_IPCSE(offset + iphl - 1); 1458 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1459 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1460 fields |= WTX_IXSM; 1461 } 1462 1463 offset += iphl; 1464 1465 if (m0->m_pkthdr.csum_flags & 1466 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1467 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1468 fields |= WTX_TXSM; 1469 tucs = WTX_TCPIP_TUCSS(offset) | 1470 WTX_TCPIP_TUCSO(offset + M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1471 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1472 } else { 1473 /* Just initialize it to a valid TCP context. */ 1474 tucs = WTX_TCPIP_TUCSS(offset) | 1475 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1476 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1477 } 1478 1479 /* Fill in the context descriptor. */ 1480 t = (struct livengood_tcpip_ctxdesc *) 1481 &sc->sc_txdescs[sc->sc_txnext]; 1482 t->tcpip_ipcs = htole32(ipcs); 1483 t->tcpip_tucs = htole32(tucs); 1484 t->tcpip_cmdlen = htole32(cmdlen); 1485 t->tcpip_seg = htole32(seg); 1486 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1487 1488 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1489 txs->txs_ndesc++; 1490 1491 *cmdp = cmd; 1492 *fieldsp = fields; 1493 1494 return (0); 1495 } 1496 1497 static void 1498 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1499 { 1500 struct mbuf *m; 1501 int i; 1502 1503 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1504 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1505 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1506 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1507 m->m_data, m->m_len, m->m_flags); 1508 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1509 i, i == 1 ? "" : "s"); 1510 } 1511 1512 /* 1513 * wm_82547_txfifo_stall: 1514 * 1515 * Callout used to wait for the 82547 Tx FIFO to drain, 1516 * reset the FIFO pointers, and restart packet transmission. 1517 */ 1518 static void 1519 wm_82547_txfifo_stall(void *arg) 1520 { 1521 struct wm_softc *sc = arg; 1522 int s; 1523 1524 s = splnet(); 1525 1526 if (sc->sc_txfifo_stall) { 1527 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1528 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1529 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1530 /* 1531 * Packets have drained. Stop transmitter, reset 1532 * FIFO pointers, restart transmitter, and kick 1533 * the packet queue. 1534 */ 1535 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1536 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1537 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1538 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1539 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1540 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1541 CSR_WRITE(sc, WMREG_TCTL, tctl); 1542 CSR_WRITE_FLUSH(sc); 1543 1544 sc->sc_txfifo_head = 0; 1545 sc->sc_txfifo_stall = 0; 1546 wm_start(&sc->sc_ethercom.ec_if); 1547 } else { 1548 /* 1549 * Still waiting for packets to drain; try again in 1550 * another tick. 1551 */ 1552 callout_schedule(&sc->sc_txfifo_ch, 1); 1553 } 1554 } 1555 1556 splx(s); 1557 } 1558 1559 /* 1560 * wm_82547_txfifo_bugchk: 1561 * 1562 * Check for bug condition in the 82547 Tx FIFO. We need to 1563 * prevent enqueueing a packet that would wrap around the end 1564 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1565 * 1566 * We do this by checking the amount of space before the end 1567 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1568 * the Tx FIFO, wait for all remaining packets to drain, reset 1569 * the internal FIFO pointers to the beginning, and restart 1570 * transmission on the interface. 1571 */ 1572 #define WM_FIFO_HDR 0x10 1573 #define WM_82547_PAD_LEN 0x3e0 1574 static int 1575 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1576 { 1577 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1578 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1579 1580 /* Just return if already stalled. */ 1581 if (sc->sc_txfifo_stall) 1582 return (1); 1583 1584 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1585 /* Stall only occurs in half-duplex mode. */ 1586 goto send_packet; 1587 } 1588 1589 if (len >= WM_82547_PAD_LEN + space) { 1590 sc->sc_txfifo_stall = 1; 1591 callout_schedule(&sc->sc_txfifo_ch, 1); 1592 return (1); 1593 } 1594 1595 send_packet: 1596 sc->sc_txfifo_head += len; 1597 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1598 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1599 1600 return (0); 1601 } 1602 1603 /* 1604 * wm_start: [ifnet interface function] 1605 * 1606 * Start packet transmission on the interface. 1607 */ 1608 static void 1609 wm_start(struct ifnet *ifp) 1610 { 1611 struct wm_softc *sc = ifp->if_softc; 1612 struct mbuf *m0; 1613 #if 0 /* XXXJRT */ 1614 struct m_tag *mtag; 1615 #endif 1616 struct wm_txsoft *txs; 1617 bus_dmamap_t dmamap; 1618 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1619 bus_addr_t curaddr; 1620 bus_size_t seglen, curlen; 1621 uint32_t cksumcmd; 1622 uint8_t cksumfields; 1623 1624 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1625 return; 1626 1627 /* 1628 * Remember the previous number of free descriptors. 1629 */ 1630 ofree = sc->sc_txfree; 1631 1632 /* 1633 * Loop through the send queue, setting up transmit descriptors 1634 * until we drain the queue, or use up all available transmit 1635 * descriptors. 1636 */ 1637 for (;;) { 1638 /* Grab a packet off the queue. */ 1639 IFQ_POLL(&ifp->if_snd, m0); 1640 if (m0 == NULL) 1641 break; 1642 1643 DPRINTF(WM_DEBUG_TX, 1644 ("%s: TX: have packet to transmit: %p\n", 1645 sc->sc_dev.dv_xname, m0)); 1646 1647 /* Get a work queue entry. */ 1648 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1649 wm_txintr(sc); 1650 if (sc->sc_txsfree == 0) { 1651 DPRINTF(WM_DEBUG_TX, 1652 ("%s: TX: no free job descriptors\n", 1653 sc->sc_dev.dv_xname)); 1654 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1655 break; 1656 } 1657 } 1658 1659 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1660 dmamap = txs->txs_dmamap; 1661 1662 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1663 1664 /* 1665 * So says the Linux driver: 1666 * The controller does a simple calculation to make sure 1667 * there is enough room in the FIFO before initiating the 1668 * DMA for each buffer. The calc is: 1669 * 4 = ceil(buffer len / MSS) 1670 * To make sure we don't overrun the FIFO, adjust the max 1671 * buffer len if the MSS drops. 1672 */ 1673 dmamap->dm_maxsegsz = 1674 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1675 ? m0->m_pkthdr.segsz << 2 1676 : WTX_MAX_LEN; 1677 1678 /* 1679 * Load the DMA map. If this fails, the packet either 1680 * didn't fit in the allotted number of segments, or we 1681 * were short on resources. For the too-many-segments 1682 * case, we simply report an error and drop the packet, 1683 * since we can't sanely copy a jumbo packet to a single 1684 * buffer. 1685 */ 1686 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1687 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1688 if (error) { 1689 if (error == EFBIG) { 1690 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1691 log(LOG_ERR, "%s: Tx packet consumes too many " 1692 "DMA segments, dropping...\n", 1693 sc->sc_dev.dv_xname); 1694 IFQ_DEQUEUE(&ifp->if_snd, m0); 1695 wm_dump_mbuf_chain(sc, m0); 1696 m_freem(m0); 1697 continue; 1698 } 1699 /* 1700 * Short on resources, just stop for now. 1701 */ 1702 DPRINTF(WM_DEBUG_TX, 1703 ("%s: TX: dmamap load failed: %d\n", 1704 sc->sc_dev.dv_xname, error)); 1705 break; 1706 } 1707 1708 segs_needed = dmamap->dm_nsegs; 1709 if (use_tso) { 1710 /* For sentinel descriptor; see below. */ 1711 segs_needed++; 1712 } 1713 1714 /* 1715 * Ensure we have enough descriptors free to describe 1716 * the packet. Note, we always reserve one descriptor 1717 * at the end of the ring due to the semantics of the 1718 * TDT register, plus one more in the event we need 1719 * to load offload context. 1720 */ 1721 if (segs_needed > sc->sc_txfree - 2) { 1722 /* 1723 * Not enough free descriptors to transmit this 1724 * packet. We haven't committed anything yet, 1725 * so just unload the DMA map, put the packet 1726 * pack on the queue, and punt. Notify the upper 1727 * layer that there are no more slots left. 1728 */ 1729 DPRINTF(WM_DEBUG_TX, 1730 ("%s: TX: need %d (%d) descriptors, have %d\n", 1731 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1732 sc->sc_txfree - 1)); 1733 ifp->if_flags |= IFF_OACTIVE; 1734 bus_dmamap_unload(sc->sc_dmat, dmamap); 1735 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1736 break; 1737 } 1738 1739 /* 1740 * Check for 82547 Tx FIFO bug. We need to do this 1741 * once we know we can transmit the packet, since we 1742 * do some internal FIFO space accounting here. 1743 */ 1744 if (sc->sc_type == WM_T_82547 && 1745 wm_82547_txfifo_bugchk(sc, m0)) { 1746 DPRINTF(WM_DEBUG_TX, 1747 ("%s: TX: 82547 Tx FIFO bug detected\n", 1748 sc->sc_dev.dv_xname)); 1749 ifp->if_flags |= IFF_OACTIVE; 1750 bus_dmamap_unload(sc->sc_dmat, dmamap); 1751 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1752 break; 1753 } 1754 1755 IFQ_DEQUEUE(&ifp->if_snd, m0); 1756 1757 /* 1758 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1759 */ 1760 1761 DPRINTF(WM_DEBUG_TX, 1762 ("%s: TX: packet has %d (%d) DMA segments\n", 1763 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1764 1765 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1766 1767 /* 1768 * Store a pointer to the packet so that we can free it 1769 * later. 1770 * 1771 * Initially, we consider the number of descriptors the 1772 * packet uses the number of DMA segments. This may be 1773 * incremented by 1 if we do checksum offload (a descriptor 1774 * is used to set the checksum context). 1775 */ 1776 txs->txs_mbuf = m0; 1777 txs->txs_firstdesc = sc->sc_txnext; 1778 txs->txs_ndesc = segs_needed; 1779 1780 /* Set up offload parameters for this packet. */ 1781 if (m0->m_pkthdr.csum_flags & 1782 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1783 if (wm_tx_offload(sc, txs, &cksumcmd, 1784 &cksumfields) != 0) { 1785 /* Error message already displayed. */ 1786 bus_dmamap_unload(sc->sc_dmat, dmamap); 1787 continue; 1788 } 1789 } else { 1790 cksumcmd = 0; 1791 cksumfields = 0; 1792 } 1793 1794 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1795 1796 /* Sync the DMA map. */ 1797 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1798 BUS_DMASYNC_PREWRITE); 1799 1800 /* 1801 * Initialize the transmit descriptor. 1802 */ 1803 for (nexttx = sc->sc_txnext, seg = 0; 1804 seg < dmamap->dm_nsegs; seg++) { 1805 for (seglen = dmamap->dm_segs[seg].ds_len, 1806 curaddr = dmamap->dm_segs[seg].ds_addr; 1807 seglen != 0; 1808 curaddr += curlen, seglen -= curlen, 1809 nexttx = WM_NEXTTX(sc, nexttx)) { 1810 curlen = seglen; 1811 1812 /* 1813 * So says the Linux driver: 1814 * Work around for premature descriptor 1815 * write-backs in TSO mode. Append a 1816 * 4-byte sentinel descriptor. 1817 */ 1818 if (use_tso && 1819 seg == dmamap->dm_nsegs - 1 && 1820 curlen > 8) 1821 curlen -= 4; 1822 1823 wm_set_dma_addr( 1824 &sc->sc_txdescs[nexttx].wtx_addr, 1825 curaddr); 1826 sc->sc_txdescs[nexttx].wtx_cmdlen = 1827 htole32(cksumcmd | curlen); 1828 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1829 0; 1830 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1831 cksumfields; 1832 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1833 lasttx = nexttx; 1834 1835 DPRINTF(WM_DEBUG_TX, 1836 ("%s: TX: desc %d: low 0x%08lx, " 1837 "len 0x%04x\n", 1838 sc->sc_dev.dv_xname, nexttx, 1839 curaddr & 0xffffffffUL, (unsigned)curlen)); 1840 } 1841 } 1842 1843 KASSERT(lasttx != -1); 1844 1845 /* 1846 * Set up the command byte on the last descriptor of 1847 * the packet. If we're in the interrupt delay window, 1848 * delay the interrupt. 1849 */ 1850 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1851 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1852 1853 #if 0 /* XXXJRT */ 1854 /* 1855 * If VLANs are enabled and the packet has a VLAN tag, set 1856 * up the descriptor to encapsulate the packet for us. 1857 * 1858 * This is only valid on the last descriptor of the packet. 1859 */ 1860 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1861 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1862 htole32(WTX_CMD_VLE); 1863 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1864 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1865 } 1866 #endif /* XXXJRT */ 1867 1868 txs->txs_lastdesc = lasttx; 1869 1870 DPRINTF(WM_DEBUG_TX, 1871 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1872 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1873 1874 /* Sync the descriptors we're using. */ 1875 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1876 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1877 1878 /* Give the packet to the chip. */ 1879 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1880 1881 DPRINTF(WM_DEBUG_TX, 1882 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1883 1884 DPRINTF(WM_DEBUG_TX, 1885 ("%s: TX: finished transmitting packet, job %d\n", 1886 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1887 1888 /* Advance the tx pointer. */ 1889 sc->sc_txfree -= txs->txs_ndesc; 1890 sc->sc_txnext = nexttx; 1891 1892 sc->sc_txsfree--; 1893 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1894 1895 #if NBPFILTER > 0 1896 /* Pass the packet to any BPF listeners. */ 1897 if (ifp->if_bpf) 1898 bpf_mtap(ifp->if_bpf, m0); 1899 #endif /* NBPFILTER > 0 */ 1900 } 1901 1902 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1903 /* No more slots; notify upper layer. */ 1904 ifp->if_flags |= IFF_OACTIVE; 1905 } 1906 1907 if (sc->sc_txfree != ofree) { 1908 /* Set a watchdog timer in case the chip flakes out. */ 1909 ifp->if_timer = 5; 1910 } 1911 } 1912 1913 /* 1914 * wm_watchdog: [ifnet interface function] 1915 * 1916 * Watchdog timer handler. 1917 */ 1918 static void 1919 wm_watchdog(struct ifnet *ifp) 1920 { 1921 struct wm_softc *sc = ifp->if_softc; 1922 1923 /* 1924 * Since we're using delayed interrupts, sweep up 1925 * before we report an error. 1926 */ 1927 wm_txintr(sc); 1928 1929 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1930 log(LOG_ERR, 1931 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1932 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1933 sc->sc_txnext); 1934 ifp->if_oerrors++; 1935 1936 /* Reset the interface. */ 1937 (void) wm_init(ifp); 1938 } 1939 1940 /* Try to get more packets going. */ 1941 wm_start(ifp); 1942 } 1943 1944 /* 1945 * wm_ioctl: [ifnet interface function] 1946 * 1947 * Handle control requests from the operator. 1948 */ 1949 static int 1950 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1951 { 1952 struct wm_softc *sc = ifp->if_softc; 1953 struct ifreq *ifr = (struct ifreq *) data; 1954 int s, error; 1955 1956 s = splnet(); 1957 1958 switch (cmd) { 1959 case SIOCSIFMEDIA: 1960 case SIOCGIFMEDIA: 1961 /* Flow control requires full-duplex mode. */ 1962 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1963 (ifr->ifr_media & IFM_FDX) == 0) 1964 ifr->ifr_media &= ~IFM_ETH_FMASK; 1965 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1966 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1967 /* We can do both TXPAUSE and RXPAUSE. */ 1968 ifr->ifr_media |= 1969 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1970 } 1971 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1972 } 1973 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1974 break; 1975 default: 1976 error = ether_ioctl(ifp, cmd, data); 1977 if (error == ENETRESET) { 1978 /* 1979 * Multicast list has changed; set the hardware filter 1980 * accordingly. 1981 */ 1982 if (ifp->if_flags & IFF_RUNNING) 1983 wm_set_filter(sc); 1984 error = 0; 1985 } 1986 break; 1987 } 1988 1989 /* Try to get more packets going. */ 1990 wm_start(ifp); 1991 1992 splx(s); 1993 return (error); 1994 } 1995 1996 /* 1997 * wm_intr: 1998 * 1999 * Interrupt service routine. 2000 */ 2001 static int 2002 wm_intr(void *arg) 2003 { 2004 struct wm_softc *sc = arg; 2005 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2006 uint32_t icr; 2007 int wantinit, handled = 0; 2008 2009 for (wantinit = 0; wantinit == 0;) { 2010 icr = CSR_READ(sc, WMREG_ICR); 2011 if ((icr & sc->sc_icr) == 0) 2012 break; 2013 2014 #if 0 /*NRND > 0*/ 2015 if (RND_ENABLED(&sc->rnd_source)) 2016 rnd_add_uint32(&sc->rnd_source, icr); 2017 #endif 2018 2019 handled = 1; 2020 2021 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2022 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2023 DPRINTF(WM_DEBUG_RX, 2024 ("%s: RX: got Rx intr 0x%08x\n", 2025 sc->sc_dev.dv_xname, 2026 icr & (ICR_RXDMT0|ICR_RXT0))); 2027 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2028 } 2029 #endif 2030 wm_rxintr(sc); 2031 2032 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2033 if (icr & ICR_TXDW) { 2034 DPRINTF(WM_DEBUG_TX, 2035 ("%s: TX: got TXDW interrupt\n", 2036 sc->sc_dev.dv_xname)); 2037 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2038 } 2039 #endif 2040 wm_txintr(sc); 2041 2042 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2043 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2044 wm_linkintr(sc, icr); 2045 } 2046 2047 if (icr & ICR_RXO) { 2048 log(LOG_WARNING, "%s: Receive overrun\n", 2049 sc->sc_dev.dv_xname); 2050 wantinit = 1; 2051 } 2052 } 2053 2054 if (handled) { 2055 if (wantinit) 2056 wm_init(ifp); 2057 2058 /* Try to get more packets going. */ 2059 wm_start(ifp); 2060 } 2061 2062 return (handled); 2063 } 2064 2065 /* 2066 * wm_txintr: 2067 * 2068 * Helper; handle transmit interrupts. 2069 */ 2070 static void 2071 wm_txintr(struct wm_softc *sc) 2072 { 2073 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2074 struct wm_txsoft *txs; 2075 uint8_t status; 2076 int i; 2077 2078 ifp->if_flags &= ~IFF_OACTIVE; 2079 2080 /* 2081 * Go through the Tx list and free mbufs for those 2082 * frames which have been transmitted. 2083 */ 2084 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2085 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2086 txs = &sc->sc_txsoft[i]; 2087 2088 DPRINTF(WM_DEBUG_TX, 2089 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2090 2091 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2092 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2093 2094 status = 2095 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2096 if ((status & WTX_ST_DD) == 0) { 2097 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2098 BUS_DMASYNC_PREREAD); 2099 break; 2100 } 2101 2102 DPRINTF(WM_DEBUG_TX, 2103 ("%s: TX: job %d done: descs %d..%d\n", 2104 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2105 txs->txs_lastdesc)); 2106 2107 /* 2108 * XXX We should probably be using the statistics 2109 * XXX registers, but I don't know if they exist 2110 * XXX on chips before the i82544. 2111 */ 2112 2113 #ifdef WM_EVENT_COUNTERS 2114 if (status & WTX_ST_TU) 2115 WM_EVCNT_INCR(&sc->sc_ev_tu); 2116 #endif /* WM_EVENT_COUNTERS */ 2117 2118 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2119 ifp->if_oerrors++; 2120 if (status & WTX_ST_LC) 2121 log(LOG_WARNING, "%s: late collision\n", 2122 sc->sc_dev.dv_xname); 2123 else if (status & WTX_ST_EC) { 2124 ifp->if_collisions += 16; 2125 log(LOG_WARNING, "%s: excessive collisions\n", 2126 sc->sc_dev.dv_xname); 2127 } 2128 } else 2129 ifp->if_opackets++; 2130 2131 sc->sc_txfree += txs->txs_ndesc; 2132 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2133 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2134 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2135 m_freem(txs->txs_mbuf); 2136 txs->txs_mbuf = NULL; 2137 } 2138 2139 /* Update the dirty transmit buffer pointer. */ 2140 sc->sc_txsdirty = i; 2141 DPRINTF(WM_DEBUG_TX, 2142 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2143 2144 /* 2145 * If there are no more pending transmissions, cancel the watchdog 2146 * timer. 2147 */ 2148 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2149 ifp->if_timer = 0; 2150 } 2151 2152 /* 2153 * wm_rxintr: 2154 * 2155 * Helper; handle receive interrupts. 2156 */ 2157 static void 2158 wm_rxintr(struct wm_softc *sc) 2159 { 2160 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2161 struct wm_rxsoft *rxs; 2162 struct mbuf *m; 2163 int i, len; 2164 uint8_t status, errors; 2165 2166 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2167 rxs = &sc->sc_rxsoft[i]; 2168 2169 DPRINTF(WM_DEBUG_RX, 2170 ("%s: RX: checking descriptor %d\n", 2171 sc->sc_dev.dv_xname, i)); 2172 2173 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2174 2175 status = sc->sc_rxdescs[i].wrx_status; 2176 errors = sc->sc_rxdescs[i].wrx_errors; 2177 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2178 2179 if ((status & WRX_ST_DD) == 0) { 2180 /* 2181 * We have processed all of the receive descriptors. 2182 */ 2183 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2184 break; 2185 } 2186 2187 if (__predict_false(sc->sc_rxdiscard)) { 2188 DPRINTF(WM_DEBUG_RX, 2189 ("%s: RX: discarding contents of descriptor %d\n", 2190 sc->sc_dev.dv_xname, i)); 2191 WM_INIT_RXDESC(sc, i); 2192 if (status & WRX_ST_EOP) { 2193 /* Reset our state. */ 2194 DPRINTF(WM_DEBUG_RX, 2195 ("%s: RX: resetting rxdiscard -> 0\n", 2196 sc->sc_dev.dv_xname)); 2197 sc->sc_rxdiscard = 0; 2198 } 2199 continue; 2200 } 2201 2202 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2203 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2204 2205 m = rxs->rxs_mbuf; 2206 2207 /* 2208 * Add a new receive buffer to the ring. 2209 */ 2210 if (wm_add_rxbuf(sc, i) != 0) { 2211 /* 2212 * Failed, throw away what we've done so 2213 * far, and discard the rest of the packet. 2214 */ 2215 ifp->if_ierrors++; 2216 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2217 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2218 WM_INIT_RXDESC(sc, i); 2219 if ((status & WRX_ST_EOP) == 0) 2220 sc->sc_rxdiscard = 1; 2221 if (sc->sc_rxhead != NULL) 2222 m_freem(sc->sc_rxhead); 2223 WM_RXCHAIN_RESET(sc); 2224 DPRINTF(WM_DEBUG_RX, 2225 ("%s: RX: Rx buffer allocation failed, " 2226 "dropping packet%s\n", sc->sc_dev.dv_xname, 2227 sc->sc_rxdiscard ? " (discard)" : "")); 2228 continue; 2229 } 2230 2231 WM_RXCHAIN_LINK(sc, m); 2232 2233 m->m_len = len; 2234 2235 DPRINTF(WM_DEBUG_RX, 2236 ("%s: RX: buffer at %p len %d\n", 2237 sc->sc_dev.dv_xname, m->m_data, len)); 2238 2239 /* 2240 * If this is not the end of the packet, keep 2241 * looking. 2242 */ 2243 if ((status & WRX_ST_EOP) == 0) { 2244 sc->sc_rxlen += len; 2245 DPRINTF(WM_DEBUG_RX, 2246 ("%s: RX: not yet EOP, rxlen -> %d\n", 2247 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2248 continue; 2249 } 2250 2251 /* 2252 * Okay, we have the entire packet now. The chip is 2253 * configured to include the FCS (not all chips can 2254 * be configured to strip it), so we need to trim it. 2255 */ 2256 m->m_len -= ETHER_CRC_LEN; 2257 2258 *sc->sc_rxtailp = NULL; 2259 m = sc->sc_rxhead; 2260 len = m->m_len + sc->sc_rxlen; 2261 2262 WM_RXCHAIN_RESET(sc); 2263 2264 DPRINTF(WM_DEBUG_RX, 2265 ("%s: RX: have entire packet, len -> %d\n", 2266 sc->sc_dev.dv_xname, len)); 2267 2268 /* 2269 * If an error occurred, update stats and drop the packet. 2270 */ 2271 if (errors & 2272 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2273 ifp->if_ierrors++; 2274 if (errors & WRX_ER_SE) 2275 log(LOG_WARNING, "%s: symbol error\n", 2276 sc->sc_dev.dv_xname); 2277 else if (errors & WRX_ER_SEQ) 2278 log(LOG_WARNING, "%s: receive sequence error\n", 2279 sc->sc_dev.dv_xname); 2280 else if (errors & WRX_ER_CE) 2281 log(LOG_WARNING, "%s: CRC error\n", 2282 sc->sc_dev.dv_xname); 2283 m_freem(m); 2284 continue; 2285 } 2286 2287 /* 2288 * No errors. Receive the packet. 2289 */ 2290 m->m_pkthdr.rcvif = ifp; 2291 m->m_pkthdr.len = len; 2292 2293 #if 0 /* XXXJRT */ 2294 /* 2295 * If VLANs are enabled, VLAN packets have been unwrapped 2296 * for us. Associate the tag with the packet. 2297 */ 2298 if ((status & WRX_ST_VP) != 0) { 2299 VLAN_INPUT_TAG(ifp, m, 2300 le16toh(sc->sc_rxdescs[i].wrx_special, 2301 continue); 2302 } 2303 #endif /* XXXJRT */ 2304 2305 /* 2306 * Set up checksum info for this packet. 2307 */ 2308 if (status & WRX_ST_IPCS) { 2309 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2310 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2311 if (errors & WRX_ER_IPE) 2312 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2313 } 2314 if (status & WRX_ST_TCPCS) { 2315 /* 2316 * Note: we don't know if this was TCP or UDP, 2317 * so we just set both bits, and expect the 2318 * upper layers to deal. 2319 */ 2320 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2321 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2322 if (errors & WRX_ER_TCPE) 2323 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2324 } 2325 2326 ifp->if_ipackets++; 2327 2328 #if NBPFILTER > 0 2329 /* Pass this up to any BPF listeners. */ 2330 if (ifp->if_bpf) 2331 bpf_mtap(ifp->if_bpf, m); 2332 #endif /* NBPFILTER > 0 */ 2333 2334 /* Pass it on. */ 2335 (*ifp->if_input)(ifp, m); 2336 } 2337 2338 /* Update the receive pointer. */ 2339 sc->sc_rxptr = i; 2340 2341 DPRINTF(WM_DEBUG_RX, 2342 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2343 } 2344 2345 /* 2346 * wm_linkintr: 2347 * 2348 * Helper; handle link interrupts. 2349 */ 2350 static void 2351 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2352 { 2353 uint32_t status; 2354 2355 /* 2356 * If we get a link status interrupt on a 1000BASE-T 2357 * device, just fall into the normal MII tick path. 2358 */ 2359 if (sc->sc_flags & WM_F_HAS_MII) { 2360 if (icr & ICR_LSC) { 2361 DPRINTF(WM_DEBUG_LINK, 2362 ("%s: LINK: LSC -> mii_tick\n", 2363 sc->sc_dev.dv_xname)); 2364 mii_tick(&sc->sc_mii); 2365 } else if (icr & ICR_RXSEQ) { 2366 DPRINTF(WM_DEBUG_LINK, 2367 ("%s: LINK Receive sequence error\n", 2368 sc->sc_dev.dv_xname)); 2369 } 2370 return; 2371 } 2372 2373 /* 2374 * If we are now receiving /C/, check for link again in 2375 * a couple of link clock ticks. 2376 */ 2377 if (icr & ICR_RXCFG) { 2378 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2379 sc->sc_dev.dv_xname)); 2380 sc->sc_tbi_anstate = 2; 2381 } 2382 2383 if (icr & ICR_LSC) { 2384 status = CSR_READ(sc, WMREG_STATUS); 2385 if (status & STATUS_LU) { 2386 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2387 sc->sc_dev.dv_xname, 2388 (status & STATUS_FD) ? "FDX" : "HDX")); 2389 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2390 sc->sc_fcrtl &= ~FCRTL_XONE; 2391 if (status & STATUS_FD) 2392 sc->sc_tctl |= 2393 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2394 else 2395 sc->sc_tctl |= 2396 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2397 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2398 sc->sc_fcrtl |= FCRTL_XONE; 2399 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2400 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2401 WMREG_OLD_FCRTL : WMREG_FCRTL, 2402 sc->sc_fcrtl); 2403 sc->sc_tbi_linkup = 1; 2404 } else { 2405 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2406 sc->sc_dev.dv_xname)); 2407 sc->sc_tbi_linkup = 0; 2408 } 2409 sc->sc_tbi_anstate = 2; 2410 wm_tbi_set_linkled(sc); 2411 } else if (icr & ICR_RXSEQ) { 2412 DPRINTF(WM_DEBUG_LINK, 2413 ("%s: LINK: Receive sequence error\n", 2414 sc->sc_dev.dv_xname)); 2415 } 2416 } 2417 2418 /* 2419 * wm_tick: 2420 * 2421 * One second timer, used to check link status, sweep up 2422 * completed transmit jobs, etc. 2423 */ 2424 static void 2425 wm_tick(void *arg) 2426 { 2427 struct wm_softc *sc = arg; 2428 int s; 2429 2430 s = splnet(); 2431 2432 if (sc->sc_type >= WM_T_82542_2_1) { 2433 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2434 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2435 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2436 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2437 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2438 } 2439 2440 if (sc->sc_flags & WM_F_HAS_MII) 2441 mii_tick(&sc->sc_mii); 2442 else 2443 wm_tbi_check_link(sc); 2444 2445 splx(s); 2446 2447 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2448 } 2449 2450 /* 2451 * wm_reset: 2452 * 2453 * Reset the i82542 chip. 2454 */ 2455 static void 2456 wm_reset(struct wm_softc *sc) 2457 { 2458 int i; 2459 2460 /* 2461 * Allocate on-chip memory according to the MTU size. 2462 * The Packet Buffer Allocation register must be written 2463 * before the chip is reset. 2464 */ 2465 if (sc->sc_type < WM_T_82547) { 2466 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2467 PBA_40K : PBA_48K; 2468 } else { 2469 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2470 PBA_22K : PBA_30K; 2471 sc->sc_txfifo_head = 0; 2472 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2473 sc->sc_txfifo_size = 2474 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2475 sc->sc_txfifo_stall = 0; 2476 } 2477 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2478 2479 switch (sc->sc_type) { 2480 case WM_T_82544: 2481 case WM_T_82540: 2482 case WM_T_82545: 2483 case WM_T_82546: 2484 case WM_T_82541: 2485 case WM_T_82541_2: 2486 /* 2487 * On some chipsets, a reset through a memory-mapped write 2488 * cycle can cause the chip to reset before completing the 2489 * write cycle. This causes major headache that can be 2490 * avoided by issuing the reset via indirect register writes 2491 * through I/O space. 2492 * 2493 * So, if we successfully mapped the I/O BAR at attach time, 2494 * use that. Otherwise, try our luck with a memory-mapped 2495 * reset. 2496 */ 2497 if (sc->sc_flags & WM_F_IOH_VALID) 2498 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2499 else 2500 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2501 break; 2502 2503 case WM_T_82545_3: 2504 case WM_T_82546_3: 2505 /* Use the shadow control register on these chips. */ 2506 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2507 break; 2508 2509 default: 2510 /* Everything else can safely use the documented method. */ 2511 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2512 break; 2513 } 2514 delay(10000); 2515 2516 for (i = 0; i < 1000; i++) { 2517 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2518 return; 2519 delay(20); 2520 } 2521 2522 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2523 log(LOG_ERR, "%s: reset failed to complete\n", 2524 sc->sc_dev.dv_xname); 2525 } 2526 2527 /* 2528 * wm_init: [ifnet interface function] 2529 * 2530 * Initialize the interface. Must be called at splnet(). 2531 */ 2532 static int 2533 wm_init(struct ifnet *ifp) 2534 { 2535 struct wm_softc *sc = ifp->if_softc; 2536 struct wm_rxsoft *rxs; 2537 int i, error = 0; 2538 uint32_t reg; 2539 2540 /* 2541 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2542 * There is a small but measurable benefit to avoiding the adjusment 2543 * of the descriptor so that the headers are aligned, for normal mtu, 2544 * on such platforms. One possibility is that the DMA itself is 2545 * slightly more efficient if the front of the entire packet (instead 2546 * of the front of the headers) is aligned. 2547 * 2548 * Note we must always set align_tweak to 0 if we are using 2549 * jumbo frames. 2550 */ 2551 #ifdef __NO_STRICT_ALIGNMENT 2552 sc->sc_align_tweak = 0; 2553 #else 2554 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2555 sc->sc_align_tweak = 0; 2556 else 2557 sc->sc_align_tweak = 2; 2558 #endif /* __NO_STRICT_ALIGNMENT */ 2559 2560 /* Cancel any pending I/O. */ 2561 wm_stop(ifp, 0); 2562 2563 /* Reset the chip to a known state. */ 2564 wm_reset(sc); 2565 2566 /* Initialize the transmit descriptor ring. */ 2567 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2568 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2569 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2570 sc->sc_txfree = WM_NTXDESC(sc); 2571 sc->sc_txnext = 0; 2572 2573 if (sc->sc_type < WM_T_82543) { 2574 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2575 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2576 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2577 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2578 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2579 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2580 } else { 2581 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2582 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2583 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2584 CSR_WRITE(sc, WMREG_TDH, 0); 2585 CSR_WRITE(sc, WMREG_TDT, 0); 2586 CSR_WRITE(sc, WMREG_TIDV, 64); 2587 CSR_WRITE(sc, WMREG_TADV, 128); 2588 2589 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2590 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2591 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2592 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2593 } 2594 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2595 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2596 2597 /* Initialize the transmit job descriptors. */ 2598 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2599 sc->sc_txsoft[i].txs_mbuf = NULL; 2600 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2601 sc->sc_txsnext = 0; 2602 sc->sc_txsdirty = 0; 2603 2604 /* 2605 * Initialize the receive descriptor and receive job 2606 * descriptor rings. 2607 */ 2608 if (sc->sc_type < WM_T_82543) { 2609 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2610 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2611 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2612 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2613 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2614 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2615 2616 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2617 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2618 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2619 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2620 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2621 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2622 } else { 2623 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2624 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2625 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2626 CSR_WRITE(sc, WMREG_RDH, 0); 2627 CSR_WRITE(sc, WMREG_RDT, 0); 2628 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2629 CSR_WRITE(sc, WMREG_RADV, 128); 2630 } 2631 for (i = 0; i < WM_NRXDESC; i++) { 2632 rxs = &sc->sc_rxsoft[i]; 2633 if (rxs->rxs_mbuf == NULL) { 2634 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2635 log(LOG_ERR, "%s: unable to allocate or map rx " 2636 "buffer %d, error = %d\n", 2637 sc->sc_dev.dv_xname, i, error); 2638 /* 2639 * XXX Should attempt to run with fewer receive 2640 * XXX buffers instead of just failing. 2641 */ 2642 wm_rxdrain(sc); 2643 goto out; 2644 } 2645 } else 2646 WM_INIT_RXDESC(sc, i); 2647 } 2648 sc->sc_rxptr = 0; 2649 sc->sc_rxdiscard = 0; 2650 WM_RXCHAIN_RESET(sc); 2651 2652 /* 2653 * Clear out the VLAN table -- we don't use it (yet). 2654 */ 2655 CSR_WRITE(sc, WMREG_VET, 0); 2656 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2657 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2658 2659 /* 2660 * Set up flow-control parameters. 2661 * 2662 * XXX Values could probably stand some tuning. 2663 */ 2664 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2665 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2666 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2667 2668 sc->sc_fcrtl = FCRTL_DFLT; 2669 if (sc->sc_type < WM_T_82543) { 2670 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2671 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2672 } else { 2673 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2674 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2675 } 2676 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2677 2678 #if 0 /* XXXJRT */ 2679 /* Deal with VLAN enables. */ 2680 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2681 sc->sc_ctrl |= CTRL_VME; 2682 else 2683 #endif /* XXXJRT */ 2684 sc->sc_ctrl &= ~CTRL_VME; 2685 2686 /* Write the control registers. */ 2687 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2688 #if 0 2689 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2690 #endif 2691 2692 /* 2693 * Set up checksum offload parameters. 2694 */ 2695 reg = CSR_READ(sc, WMREG_RXCSUM); 2696 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2697 reg |= RXCSUM_IPOFL; 2698 else 2699 reg &= ~RXCSUM_IPOFL; 2700 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2701 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2702 else { 2703 reg &= ~RXCSUM_TUOFL; 2704 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2705 reg &= ~RXCSUM_IPOFL; 2706 } 2707 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2708 2709 /* 2710 * Set up the interrupt registers. 2711 */ 2712 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2713 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2714 ICR_RXO | ICR_RXT0; 2715 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2716 sc->sc_icr |= ICR_RXCFG; 2717 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2718 2719 /* Set up the inter-packet gap. */ 2720 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2721 2722 if (sc->sc_type >= WM_T_82543) { 2723 /* Set up the interrupt throttling register (units of 256ns) */ 2724 sc->sc_itr = 1000000000 / (7000 * 256); 2725 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2726 } 2727 2728 #if 0 /* XXXJRT */ 2729 /* Set the VLAN ethernetype. */ 2730 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2731 #endif 2732 2733 /* 2734 * Set up the transmit control register; we start out with 2735 * a collision distance suitable for FDX, but update it whe 2736 * we resolve the media type. 2737 */ 2738 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2739 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2740 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2741 2742 /* Set the media. */ 2743 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2744 2745 /* 2746 * Set up the receive control register; we actually program 2747 * the register when we set the receive filter. Use multicast 2748 * address offset type 0. 2749 * 2750 * Only the i82544 has the ability to strip the incoming 2751 * CRC, so we don't enable that feature. 2752 */ 2753 sc->sc_mchash_type = 0; 2754 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2755 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2756 2757 if(MCLBYTES == 2048) { 2758 sc->sc_rctl |= RCTL_2k; 2759 } else { 2760 if(sc->sc_type >= WM_T_82543) { 2761 switch(MCLBYTES) { 2762 case 4096: 2763 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2764 break; 2765 case 8192: 2766 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2767 break; 2768 case 16384: 2769 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2770 break; 2771 default: 2772 panic("wm_init: MCLBYTES %d unsupported", 2773 MCLBYTES); 2774 break; 2775 } 2776 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2777 } 2778 2779 /* Set the receive filter. */ 2780 wm_set_filter(sc); 2781 2782 /* Start the one second link check clock. */ 2783 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2784 2785 /* ...all done! */ 2786 ifp->if_flags |= IFF_RUNNING; 2787 ifp->if_flags &= ~IFF_OACTIVE; 2788 2789 out: 2790 if (error) 2791 log(LOG_ERR, "%s: interface not running\n", 2792 sc->sc_dev.dv_xname); 2793 return (error); 2794 } 2795 2796 /* 2797 * wm_rxdrain: 2798 * 2799 * Drain the receive queue. 2800 */ 2801 static void 2802 wm_rxdrain(struct wm_softc *sc) 2803 { 2804 struct wm_rxsoft *rxs; 2805 int i; 2806 2807 for (i = 0; i < WM_NRXDESC; i++) { 2808 rxs = &sc->sc_rxsoft[i]; 2809 if (rxs->rxs_mbuf != NULL) { 2810 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2811 m_freem(rxs->rxs_mbuf); 2812 rxs->rxs_mbuf = NULL; 2813 } 2814 } 2815 } 2816 2817 /* 2818 * wm_stop: [ifnet interface function] 2819 * 2820 * Stop transmission on the interface. 2821 */ 2822 static void 2823 wm_stop(struct ifnet *ifp, int disable) 2824 { 2825 struct wm_softc *sc = ifp->if_softc; 2826 struct wm_txsoft *txs; 2827 int i; 2828 2829 /* Stop the one second clock. */ 2830 callout_stop(&sc->sc_tick_ch); 2831 2832 /* Stop the 82547 Tx FIFO stall check timer. */ 2833 if (sc->sc_type == WM_T_82547) 2834 callout_stop(&sc->sc_txfifo_ch); 2835 2836 if (sc->sc_flags & WM_F_HAS_MII) { 2837 /* Down the MII. */ 2838 mii_down(&sc->sc_mii); 2839 } 2840 2841 /* Stop the transmit and receive processes. */ 2842 CSR_WRITE(sc, WMREG_TCTL, 0); 2843 CSR_WRITE(sc, WMREG_RCTL, 0); 2844 2845 /* 2846 * Clear the interrupt mask to ensure the device cannot assert its 2847 * interrupt line. 2848 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 2849 * any currently pending or shared interrupt. 2850 */ 2851 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2852 sc->sc_icr = 0; 2853 2854 /* Release any queued transmit buffers. */ 2855 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2856 txs = &sc->sc_txsoft[i]; 2857 if (txs->txs_mbuf != NULL) { 2858 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2859 m_freem(txs->txs_mbuf); 2860 txs->txs_mbuf = NULL; 2861 } 2862 } 2863 2864 if (disable) 2865 wm_rxdrain(sc); 2866 2867 /* Mark the interface as down and cancel the watchdog timer. */ 2868 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2869 ifp->if_timer = 0; 2870 } 2871 2872 /* 2873 * wm_acquire_eeprom: 2874 * 2875 * Perform the EEPROM handshake required on some chips. 2876 */ 2877 static int 2878 wm_acquire_eeprom(struct wm_softc *sc) 2879 { 2880 uint32_t reg; 2881 int x; 2882 2883 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2884 reg = CSR_READ(sc, WMREG_EECD); 2885 2886 /* Request EEPROM access. */ 2887 reg |= EECD_EE_REQ; 2888 CSR_WRITE(sc, WMREG_EECD, reg); 2889 2890 /* ..and wait for it to be granted. */ 2891 for (x = 0; x < 100; x++) { 2892 reg = CSR_READ(sc, WMREG_EECD); 2893 if (reg & EECD_EE_GNT) 2894 break; 2895 delay(5); 2896 } 2897 if ((reg & EECD_EE_GNT) == 0) { 2898 aprint_error("%s: could not acquire EEPROM GNT\n", 2899 sc->sc_dev.dv_xname); 2900 reg &= ~EECD_EE_REQ; 2901 CSR_WRITE(sc, WMREG_EECD, reg); 2902 return (1); 2903 } 2904 } 2905 2906 return (0); 2907 } 2908 2909 /* 2910 * wm_release_eeprom: 2911 * 2912 * Release the EEPROM mutex. 2913 */ 2914 static void 2915 wm_release_eeprom(struct wm_softc *sc) 2916 { 2917 uint32_t reg; 2918 2919 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2920 reg = CSR_READ(sc, WMREG_EECD); 2921 reg &= ~EECD_EE_REQ; 2922 CSR_WRITE(sc, WMREG_EECD, reg); 2923 } 2924 } 2925 2926 /* 2927 * wm_eeprom_sendbits: 2928 * 2929 * Send a series of bits to the EEPROM. 2930 */ 2931 static void 2932 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2933 { 2934 uint32_t reg; 2935 int x; 2936 2937 reg = CSR_READ(sc, WMREG_EECD); 2938 2939 for (x = nbits; x > 0; x--) { 2940 if (bits & (1U << (x - 1))) 2941 reg |= EECD_DI; 2942 else 2943 reg &= ~EECD_DI; 2944 CSR_WRITE(sc, WMREG_EECD, reg); 2945 delay(2); 2946 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2947 delay(2); 2948 CSR_WRITE(sc, WMREG_EECD, reg); 2949 delay(2); 2950 } 2951 } 2952 2953 /* 2954 * wm_eeprom_recvbits: 2955 * 2956 * Receive a series of bits from the EEPROM. 2957 */ 2958 static void 2959 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2960 { 2961 uint32_t reg, val; 2962 int x; 2963 2964 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2965 2966 val = 0; 2967 for (x = nbits; x > 0; x--) { 2968 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2969 delay(2); 2970 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2971 val |= (1U << (x - 1)); 2972 CSR_WRITE(sc, WMREG_EECD, reg); 2973 delay(2); 2974 } 2975 *valp = val; 2976 } 2977 2978 /* 2979 * wm_read_eeprom_uwire: 2980 * 2981 * Read a word from the EEPROM using the MicroWire protocol. 2982 */ 2983 static int 2984 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2985 { 2986 uint32_t reg, val; 2987 int i; 2988 2989 for (i = 0; i < wordcnt; i++) { 2990 /* Clear SK and DI. */ 2991 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2992 CSR_WRITE(sc, WMREG_EECD, reg); 2993 2994 /* Set CHIP SELECT. */ 2995 reg |= EECD_CS; 2996 CSR_WRITE(sc, WMREG_EECD, reg); 2997 delay(2); 2998 2999 /* Shift in the READ command. */ 3000 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3001 3002 /* Shift in address. */ 3003 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3004 3005 /* Shift out the data. */ 3006 wm_eeprom_recvbits(sc, &val, 16); 3007 data[i] = val & 0xffff; 3008 3009 /* Clear CHIP SELECT. */ 3010 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3011 CSR_WRITE(sc, WMREG_EECD, reg); 3012 delay(2); 3013 } 3014 3015 return (0); 3016 } 3017 3018 /* 3019 * wm_spi_eeprom_ready: 3020 * 3021 * Wait for a SPI EEPROM to be ready for commands. 3022 */ 3023 static int 3024 wm_spi_eeprom_ready(struct wm_softc *sc) 3025 { 3026 uint32_t val; 3027 int usec; 3028 3029 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3030 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3031 wm_eeprom_recvbits(sc, &val, 8); 3032 if ((val & SPI_SR_RDY) == 0) 3033 break; 3034 } 3035 if (usec >= SPI_MAX_RETRIES) { 3036 aprint_error("%s: EEPROM failed to become ready\n", 3037 sc->sc_dev.dv_xname); 3038 return (1); 3039 } 3040 return (0); 3041 } 3042 3043 /* 3044 * wm_read_eeprom_spi: 3045 * 3046 * Read a work from the EEPROM using the SPI protocol. 3047 */ 3048 static int 3049 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3050 { 3051 uint32_t reg, val; 3052 int i; 3053 uint8_t opc; 3054 3055 /* Clear SK and CS. */ 3056 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3057 CSR_WRITE(sc, WMREG_EECD, reg); 3058 delay(2); 3059 3060 if (wm_spi_eeprom_ready(sc)) 3061 return (1); 3062 3063 /* Toggle CS to flush commands. */ 3064 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3065 delay(2); 3066 CSR_WRITE(sc, WMREG_EECD, reg); 3067 delay(2); 3068 3069 opc = SPI_OPC_READ; 3070 if (sc->sc_ee_addrbits == 8 && word >= 128) 3071 opc |= SPI_OPC_A8; 3072 3073 wm_eeprom_sendbits(sc, opc, 8); 3074 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3075 3076 for (i = 0; i < wordcnt; i++) { 3077 wm_eeprom_recvbits(sc, &val, 16); 3078 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3079 } 3080 3081 /* Raise CS and clear SK. */ 3082 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3083 CSR_WRITE(sc, WMREG_EECD, reg); 3084 delay(2); 3085 3086 return (0); 3087 } 3088 3089 /* 3090 * wm_read_eeprom: 3091 * 3092 * Read data from the serial EEPROM. 3093 */ 3094 static int 3095 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3096 { 3097 int rv; 3098 3099 if (wm_acquire_eeprom(sc)) 3100 return (1); 3101 3102 if (sc->sc_flags & WM_F_EEPROM_SPI) 3103 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3104 else 3105 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3106 3107 wm_release_eeprom(sc); 3108 return (rv); 3109 } 3110 3111 /* 3112 * wm_add_rxbuf: 3113 * 3114 * Add a receive buffer to the indiciated descriptor. 3115 */ 3116 static int 3117 wm_add_rxbuf(struct wm_softc *sc, int idx) 3118 { 3119 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3120 struct mbuf *m; 3121 int error; 3122 3123 MGETHDR(m, M_DONTWAIT, MT_DATA); 3124 if (m == NULL) 3125 return (ENOBUFS); 3126 3127 MCLGET(m, M_DONTWAIT); 3128 if ((m->m_flags & M_EXT) == 0) { 3129 m_freem(m); 3130 return (ENOBUFS); 3131 } 3132 3133 if (rxs->rxs_mbuf != NULL) 3134 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3135 3136 rxs->rxs_mbuf = m; 3137 3138 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3139 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3140 BUS_DMA_READ|BUS_DMA_NOWAIT); 3141 if (error) { 3142 /* XXX XXX XXX */ 3143 printf("%s: unable to load rx DMA map %d, error = %d\n", 3144 sc->sc_dev.dv_xname, idx, error); 3145 panic("wm_add_rxbuf"); 3146 } 3147 3148 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3149 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3150 3151 WM_INIT_RXDESC(sc, idx); 3152 3153 return (0); 3154 } 3155 3156 /* 3157 * wm_set_ral: 3158 * 3159 * Set an entery in the receive address list. 3160 */ 3161 static void 3162 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3163 { 3164 uint32_t ral_lo, ral_hi; 3165 3166 if (enaddr != NULL) { 3167 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3168 (enaddr[3] << 24); 3169 ral_hi = enaddr[4] | (enaddr[5] << 8); 3170 ral_hi |= RAL_AV; 3171 } else { 3172 ral_lo = 0; 3173 ral_hi = 0; 3174 } 3175 3176 if (sc->sc_type >= WM_T_82544) { 3177 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3178 ral_lo); 3179 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3180 ral_hi); 3181 } else { 3182 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3183 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3184 } 3185 } 3186 3187 /* 3188 * wm_mchash: 3189 * 3190 * Compute the hash of the multicast address for the 4096-bit 3191 * multicast filter. 3192 */ 3193 static uint32_t 3194 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3195 { 3196 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3197 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3198 uint32_t hash; 3199 3200 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3201 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3202 3203 return (hash & 0xfff); 3204 } 3205 3206 /* 3207 * wm_set_filter: 3208 * 3209 * Set up the receive filter. 3210 */ 3211 static void 3212 wm_set_filter(struct wm_softc *sc) 3213 { 3214 struct ethercom *ec = &sc->sc_ethercom; 3215 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3216 struct ether_multi *enm; 3217 struct ether_multistep step; 3218 bus_addr_t mta_reg; 3219 uint32_t hash, reg, bit; 3220 int i; 3221 3222 if (sc->sc_type >= WM_T_82544) 3223 mta_reg = WMREG_CORDOVA_MTA; 3224 else 3225 mta_reg = WMREG_MTA; 3226 3227 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3228 3229 if (ifp->if_flags & IFF_BROADCAST) 3230 sc->sc_rctl |= RCTL_BAM; 3231 if (ifp->if_flags & IFF_PROMISC) { 3232 sc->sc_rctl |= RCTL_UPE; 3233 goto allmulti; 3234 } 3235 3236 /* 3237 * Set the station address in the first RAL slot, and 3238 * clear the remaining slots. 3239 */ 3240 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3241 for (i = 1; i < WM_RAL_TABSIZE; i++) 3242 wm_set_ral(sc, NULL, i); 3243 3244 /* Clear out the multicast table. */ 3245 for (i = 0; i < WM_MC_TABSIZE; i++) 3246 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3247 3248 ETHER_FIRST_MULTI(step, ec, enm); 3249 while (enm != NULL) { 3250 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3251 /* 3252 * We must listen to a range of multicast addresses. 3253 * For now, just accept all multicasts, rather than 3254 * trying to set only those filter bits needed to match 3255 * the range. (At this time, the only use of address 3256 * ranges is for IP multicast routing, for which the 3257 * range is big enough to require all bits set.) 3258 */ 3259 goto allmulti; 3260 } 3261 3262 hash = wm_mchash(sc, enm->enm_addrlo); 3263 3264 reg = (hash >> 5) & 0x7f; 3265 bit = hash & 0x1f; 3266 3267 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3268 hash |= 1U << bit; 3269 3270 /* XXX Hardware bug?? */ 3271 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3272 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3273 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3274 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3275 } else 3276 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3277 3278 ETHER_NEXT_MULTI(step, enm); 3279 } 3280 3281 ifp->if_flags &= ~IFF_ALLMULTI; 3282 goto setit; 3283 3284 allmulti: 3285 ifp->if_flags |= IFF_ALLMULTI; 3286 sc->sc_rctl |= RCTL_MPE; 3287 3288 setit: 3289 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3290 } 3291 3292 /* 3293 * wm_tbi_mediainit: 3294 * 3295 * Initialize media for use on 1000BASE-X devices. 3296 */ 3297 static void 3298 wm_tbi_mediainit(struct wm_softc *sc) 3299 { 3300 const char *sep = ""; 3301 3302 if (sc->sc_type < WM_T_82543) 3303 sc->sc_tipg = TIPG_WM_DFLT; 3304 else 3305 sc->sc_tipg = TIPG_LG_DFLT; 3306 3307 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3308 wm_tbi_mediastatus); 3309 3310 /* 3311 * SWD Pins: 3312 * 3313 * 0 = Link LED (output) 3314 * 1 = Loss Of Signal (input) 3315 */ 3316 sc->sc_ctrl |= CTRL_SWDPIO(0); 3317 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3318 3319 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3320 3321 #define ADD(ss, mm, dd) \ 3322 do { \ 3323 aprint_normal("%s%s", sep, ss); \ 3324 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3325 sep = ", "; \ 3326 } while (/*CONSTCOND*/0) 3327 3328 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3329 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3330 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3331 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3332 aprint_normal("\n"); 3333 3334 #undef ADD 3335 3336 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3337 } 3338 3339 /* 3340 * wm_tbi_mediastatus: [ifmedia interface function] 3341 * 3342 * Get the current interface media status on a 1000BASE-X device. 3343 */ 3344 static void 3345 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3346 { 3347 struct wm_softc *sc = ifp->if_softc; 3348 uint32_t ctrl; 3349 3350 ifmr->ifm_status = IFM_AVALID; 3351 ifmr->ifm_active = IFM_ETHER; 3352 3353 if (sc->sc_tbi_linkup == 0) { 3354 ifmr->ifm_active |= IFM_NONE; 3355 return; 3356 } 3357 3358 ifmr->ifm_status |= IFM_ACTIVE; 3359 ifmr->ifm_active |= IFM_1000_SX; 3360 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3361 ifmr->ifm_active |= IFM_FDX; 3362 ctrl = CSR_READ(sc, WMREG_CTRL); 3363 if (ctrl & CTRL_RFCE) 3364 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3365 if (ctrl & CTRL_TFCE) 3366 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3367 } 3368 3369 /* 3370 * wm_tbi_mediachange: [ifmedia interface function] 3371 * 3372 * Set hardware to newly-selected media on a 1000BASE-X device. 3373 */ 3374 static int 3375 wm_tbi_mediachange(struct ifnet *ifp) 3376 { 3377 struct wm_softc *sc = ifp->if_softc; 3378 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3379 uint32_t status; 3380 int i; 3381 3382 sc->sc_txcw = ife->ifm_data; 3383 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3384 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3385 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3386 sc->sc_txcw |= TXCW_ANE; 3387 3388 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3389 delay(10000); 3390 3391 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3392 3393 sc->sc_tbi_anstate = 0; 3394 3395 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3396 /* Have signal; wait for the link to come up. */ 3397 for (i = 0; i < 50; i++) { 3398 delay(10000); 3399 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3400 break; 3401 } 3402 3403 status = CSR_READ(sc, WMREG_STATUS); 3404 if (status & STATUS_LU) { 3405 /* Link is up. */ 3406 DPRINTF(WM_DEBUG_LINK, 3407 ("%s: LINK: set media -> link up %s\n", 3408 sc->sc_dev.dv_xname, 3409 (status & STATUS_FD) ? "FDX" : "HDX")); 3410 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3411 sc->sc_fcrtl &= ~FCRTL_XONE; 3412 if (status & STATUS_FD) 3413 sc->sc_tctl |= 3414 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3415 else 3416 sc->sc_tctl |= 3417 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3418 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3419 sc->sc_fcrtl |= FCRTL_XONE; 3420 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3421 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3422 WMREG_OLD_FCRTL : WMREG_FCRTL, 3423 sc->sc_fcrtl); 3424 sc->sc_tbi_linkup = 1; 3425 } else { 3426 /* Link is down. */ 3427 DPRINTF(WM_DEBUG_LINK, 3428 ("%s: LINK: set media -> link down\n", 3429 sc->sc_dev.dv_xname)); 3430 sc->sc_tbi_linkup = 0; 3431 } 3432 } else { 3433 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3434 sc->sc_dev.dv_xname)); 3435 sc->sc_tbi_linkup = 0; 3436 } 3437 3438 wm_tbi_set_linkled(sc); 3439 3440 return (0); 3441 } 3442 3443 /* 3444 * wm_tbi_set_linkled: 3445 * 3446 * Update the link LED on 1000BASE-X devices. 3447 */ 3448 static void 3449 wm_tbi_set_linkled(struct wm_softc *sc) 3450 { 3451 3452 if (sc->sc_tbi_linkup) 3453 sc->sc_ctrl |= CTRL_SWDPIN(0); 3454 else 3455 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3456 3457 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3458 } 3459 3460 /* 3461 * wm_tbi_check_link: 3462 * 3463 * Check the link on 1000BASE-X devices. 3464 */ 3465 static void 3466 wm_tbi_check_link(struct wm_softc *sc) 3467 { 3468 uint32_t rxcw, ctrl, status; 3469 3470 if (sc->sc_tbi_anstate == 0) 3471 return; 3472 else if (sc->sc_tbi_anstate > 1) { 3473 DPRINTF(WM_DEBUG_LINK, 3474 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3475 sc->sc_tbi_anstate)); 3476 sc->sc_tbi_anstate--; 3477 return; 3478 } 3479 3480 sc->sc_tbi_anstate = 0; 3481 3482 rxcw = CSR_READ(sc, WMREG_RXCW); 3483 ctrl = CSR_READ(sc, WMREG_CTRL); 3484 status = CSR_READ(sc, WMREG_STATUS); 3485 3486 if ((status & STATUS_LU) == 0) { 3487 DPRINTF(WM_DEBUG_LINK, 3488 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3489 sc->sc_tbi_linkup = 0; 3490 } else { 3491 DPRINTF(WM_DEBUG_LINK, 3492 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3493 (status & STATUS_FD) ? "FDX" : "HDX")); 3494 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3495 sc->sc_fcrtl &= ~FCRTL_XONE; 3496 if (status & STATUS_FD) 3497 sc->sc_tctl |= 3498 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3499 else 3500 sc->sc_tctl |= 3501 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3502 if (ctrl & CTRL_TFCE) 3503 sc->sc_fcrtl |= FCRTL_XONE; 3504 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3505 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3506 WMREG_OLD_FCRTL : WMREG_FCRTL, 3507 sc->sc_fcrtl); 3508 sc->sc_tbi_linkup = 1; 3509 } 3510 3511 wm_tbi_set_linkled(sc); 3512 } 3513 3514 /* 3515 * wm_gmii_reset: 3516 * 3517 * Reset the PHY. 3518 */ 3519 static void 3520 wm_gmii_reset(struct wm_softc *sc) 3521 { 3522 uint32_t reg; 3523 3524 if (sc->sc_type >= WM_T_82544) { 3525 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3526 delay(20000); 3527 3528 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3529 delay(20000); 3530 } else { 3531 /* The PHY reset pin is active-low. */ 3532 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3533 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3534 CTRL_EXT_SWDPIN(4)); 3535 reg |= CTRL_EXT_SWDPIO(4); 3536 3537 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3538 delay(10); 3539 3540 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3541 delay(10); 3542 3543 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3544 delay(10); 3545 #if 0 3546 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3547 #endif 3548 } 3549 } 3550 3551 /* 3552 * wm_gmii_mediainit: 3553 * 3554 * Initialize media for use on 1000BASE-T devices. 3555 */ 3556 static void 3557 wm_gmii_mediainit(struct wm_softc *sc) 3558 { 3559 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3560 3561 /* We have MII. */ 3562 sc->sc_flags |= WM_F_HAS_MII; 3563 3564 sc->sc_tipg = TIPG_1000T_DFLT; 3565 3566 /* 3567 * Let the chip set speed/duplex on its own based on 3568 * signals from the PHY. 3569 */ 3570 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3571 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3572 3573 /* Initialize our media structures and probe the GMII. */ 3574 sc->sc_mii.mii_ifp = ifp; 3575 3576 if (sc->sc_type >= WM_T_82544) { 3577 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3578 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3579 } else { 3580 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3581 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3582 } 3583 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3584 3585 wm_gmii_reset(sc); 3586 3587 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3588 wm_gmii_mediastatus); 3589 3590 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3591 MII_OFFSET_ANY, MIIF_DOPAUSE); 3592 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3593 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3594 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3595 } else 3596 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3597 } 3598 3599 /* 3600 * wm_gmii_mediastatus: [ifmedia interface function] 3601 * 3602 * Get the current interface media status on a 1000BASE-T device. 3603 */ 3604 static void 3605 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3606 { 3607 struct wm_softc *sc = ifp->if_softc; 3608 3609 mii_pollstat(&sc->sc_mii); 3610 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3611 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3612 sc->sc_flowflags; 3613 } 3614 3615 /* 3616 * wm_gmii_mediachange: [ifmedia interface function] 3617 * 3618 * Set hardware to newly-selected media on a 1000BASE-T device. 3619 */ 3620 static int 3621 wm_gmii_mediachange(struct ifnet *ifp) 3622 { 3623 struct wm_softc *sc = ifp->if_softc; 3624 3625 if (ifp->if_flags & IFF_UP) 3626 mii_mediachg(&sc->sc_mii); 3627 return (0); 3628 } 3629 3630 #define MDI_IO CTRL_SWDPIN(2) 3631 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3632 #define MDI_CLK CTRL_SWDPIN(3) 3633 3634 static void 3635 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3636 { 3637 uint32_t i, v; 3638 3639 v = CSR_READ(sc, WMREG_CTRL); 3640 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3641 v |= MDI_DIR | CTRL_SWDPIO(3); 3642 3643 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3644 if (data & i) 3645 v |= MDI_IO; 3646 else 3647 v &= ~MDI_IO; 3648 CSR_WRITE(sc, WMREG_CTRL, v); 3649 delay(10); 3650 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3651 delay(10); 3652 CSR_WRITE(sc, WMREG_CTRL, v); 3653 delay(10); 3654 } 3655 } 3656 3657 static uint32_t 3658 i82543_mii_recvbits(struct wm_softc *sc) 3659 { 3660 uint32_t v, i, data = 0; 3661 3662 v = CSR_READ(sc, WMREG_CTRL); 3663 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3664 v |= CTRL_SWDPIO(3); 3665 3666 CSR_WRITE(sc, WMREG_CTRL, v); 3667 delay(10); 3668 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3669 delay(10); 3670 CSR_WRITE(sc, WMREG_CTRL, v); 3671 delay(10); 3672 3673 for (i = 0; i < 16; i++) { 3674 data <<= 1; 3675 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3676 delay(10); 3677 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3678 data |= 1; 3679 CSR_WRITE(sc, WMREG_CTRL, v); 3680 delay(10); 3681 } 3682 3683 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3684 delay(10); 3685 CSR_WRITE(sc, WMREG_CTRL, v); 3686 delay(10); 3687 3688 return (data); 3689 } 3690 3691 #undef MDI_IO 3692 #undef MDI_DIR 3693 #undef MDI_CLK 3694 3695 /* 3696 * wm_gmii_i82543_readreg: [mii interface function] 3697 * 3698 * Read a PHY register on the GMII (i82543 version). 3699 */ 3700 static int 3701 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3702 { 3703 struct wm_softc *sc = (void *) self; 3704 int rv; 3705 3706 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3707 i82543_mii_sendbits(sc, reg | (phy << 5) | 3708 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3709 rv = i82543_mii_recvbits(sc) & 0xffff; 3710 3711 DPRINTF(WM_DEBUG_GMII, 3712 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3713 sc->sc_dev.dv_xname, phy, reg, rv)); 3714 3715 return (rv); 3716 } 3717 3718 /* 3719 * wm_gmii_i82543_writereg: [mii interface function] 3720 * 3721 * Write a PHY register on the GMII (i82543 version). 3722 */ 3723 static void 3724 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3725 { 3726 struct wm_softc *sc = (void *) self; 3727 3728 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3729 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3730 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3731 (MII_COMMAND_START << 30), 32); 3732 } 3733 3734 /* 3735 * wm_gmii_i82544_readreg: [mii interface function] 3736 * 3737 * Read a PHY register on the GMII. 3738 */ 3739 static int 3740 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3741 { 3742 struct wm_softc *sc = (void *) self; 3743 uint32_t mdic = 0; 3744 int i, rv; 3745 3746 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3747 MDIC_REGADD(reg)); 3748 3749 for (i = 0; i < 100; i++) { 3750 mdic = CSR_READ(sc, WMREG_MDIC); 3751 if (mdic & MDIC_READY) 3752 break; 3753 delay(10); 3754 } 3755 3756 if ((mdic & MDIC_READY) == 0) { 3757 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3758 sc->sc_dev.dv_xname, phy, reg); 3759 rv = 0; 3760 } else if (mdic & MDIC_E) { 3761 #if 0 /* This is normal if no PHY is present. */ 3762 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3763 sc->sc_dev.dv_xname, phy, reg); 3764 #endif 3765 rv = 0; 3766 } else { 3767 rv = MDIC_DATA(mdic); 3768 if (rv == 0xffff) 3769 rv = 0; 3770 } 3771 3772 return (rv); 3773 } 3774 3775 /* 3776 * wm_gmii_i82544_writereg: [mii interface function] 3777 * 3778 * Write a PHY register on the GMII. 3779 */ 3780 static void 3781 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3782 { 3783 struct wm_softc *sc = (void *) self; 3784 uint32_t mdic = 0; 3785 int i; 3786 3787 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3788 MDIC_REGADD(reg) | MDIC_DATA(val)); 3789 3790 for (i = 0; i < 100; i++) { 3791 mdic = CSR_READ(sc, WMREG_MDIC); 3792 if (mdic & MDIC_READY) 3793 break; 3794 delay(10); 3795 } 3796 3797 if ((mdic & MDIC_READY) == 0) 3798 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3799 sc->sc_dev.dv_xname, phy, reg); 3800 else if (mdic & MDIC_E) 3801 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3802 sc->sc_dev.dv_xname, phy, reg); 3803 } 3804 3805 /* 3806 * wm_gmii_statchg: [mii interface function] 3807 * 3808 * Callback from MII layer when media changes. 3809 */ 3810 static void 3811 wm_gmii_statchg(struct device *self) 3812 { 3813 struct wm_softc *sc = (void *) self; 3814 struct mii_data *mii = &sc->sc_mii; 3815 3816 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3817 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3818 sc->sc_fcrtl &= ~FCRTL_XONE; 3819 3820 /* 3821 * Get flow control negotiation result. 3822 */ 3823 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3824 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3825 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3826 mii->mii_media_active &= ~IFM_ETH_FMASK; 3827 } 3828 3829 if (sc->sc_flowflags & IFM_FLOW) { 3830 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3831 sc->sc_ctrl |= CTRL_TFCE; 3832 sc->sc_fcrtl |= FCRTL_XONE; 3833 } 3834 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3835 sc->sc_ctrl |= CTRL_RFCE; 3836 } 3837 3838 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3839 DPRINTF(WM_DEBUG_LINK, 3840 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3841 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3842 } else { 3843 DPRINTF(WM_DEBUG_LINK, 3844 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3845 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3846 } 3847 3848 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3849 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3850 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3851 : WMREG_FCRTL, sc->sc_fcrtl); 3852 } 3853
Indexes created Tue Sep 23 13:09:54 GMT 2025