if_wm.c revision 1.111
1 /* $NetBSD: if_wm.c,v 1.111 2006/02/07 06:20:04 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.111 2006/02/07 06:20:04 thorpej Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make several things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 280 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 281 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 282 283 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 284 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 285 286 struct evcnt sc_ev_tu; /* Tx underrun */ 287 288 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 289 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 290 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 291 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 292 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 293 #endif /* WM_EVENT_COUNTERS */ 294 295 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 296 297 int sc_txfree; /* number of free Tx descriptors */ 298 int sc_txnext; /* next ready Tx descriptor */ 299 300 int sc_txsfree; /* number of free Tx jobs */ 301 int sc_txsnext; /* next free Tx job */ 302 int sc_txsdirty; /* dirty Tx jobs */ 303 304 /* These 5 variables are used only on the 82547. */ 305 int sc_txfifo_size; /* Tx FIFO size */ 306 int sc_txfifo_head; /* current head of FIFO */ 307 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 308 int sc_txfifo_stall; /* Tx FIFO is stalled */ 309 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 310 311 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 312 313 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 314 int sc_rxdiscard; 315 int sc_rxlen; 316 struct mbuf *sc_rxhead; 317 struct mbuf *sc_rxtail; 318 struct mbuf **sc_rxtailp; 319 320 uint32_t sc_ctrl; /* prototype CTRL register */ 321 #if 0 322 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 323 #endif 324 uint32_t sc_icr; /* prototype interrupt bits */ 325 uint32_t sc_itr; /* prototype intr throttling reg */ 326 uint32_t sc_tctl; /* prototype TCTL register */ 327 uint32_t sc_rctl; /* prototype RCTL register */ 328 uint32_t sc_txcw; /* prototype TXCW register */ 329 uint32_t sc_tipg; /* prototype TIPG register */ 330 uint32_t sc_fcrtl; /* prototype FCRTL register */ 331 uint32_t sc_pba; /* prototype PBA register */ 332 333 int sc_tbi_linkup; /* TBI link status */ 334 int sc_tbi_anstate; /* autonegotiation state */ 335 336 int sc_mchash_type; /* multicast filter offset */ 337 338 #if NRND > 0 339 rndsource_element_t rnd_source; /* random source */ 340 #endif 341 }; 342 343 #define WM_RXCHAIN_RESET(sc) \ 344 do { \ 345 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 346 *(sc)->sc_rxtailp = NULL; \ 347 (sc)->sc_rxlen = 0; \ 348 } while (/*CONSTCOND*/0) 349 350 #define WM_RXCHAIN_LINK(sc, m) \ 351 do { \ 352 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 353 (sc)->sc_rxtailp = &(m)->m_next; \ 354 } while (/*CONSTCOND*/0) 355 356 /* sc_flags */ 357 #define WM_F_HAS_MII 0x01 /* has MII */ 358 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 359 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 360 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 361 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 362 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 363 #define WM_F_CSA 0x80 /* bus is CSA */ 364 365 #ifdef WM_EVENT_COUNTERS 366 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 367 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 368 #else 369 #define WM_EVCNT_INCR(ev) /* nothing */ 370 #define WM_EVCNT_ADD(ev, val) /* nothing */ 371 #endif 372 373 #define CSR_READ(sc, reg) \ 374 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 375 #define CSR_WRITE(sc, reg, val) \ 376 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 377 #define CSR_WRITE_FLUSH(sc) \ 378 (void) CSR_READ((sc), WMREG_STATUS) 379 380 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 381 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 382 383 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 384 #define WM_CDTXADDR_HI(sc, x) \ 385 (sizeof(bus_addr_t) == 8 ? \ 386 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 387 388 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 389 #define WM_CDRXADDR_HI(sc, x) \ 390 (sizeof(bus_addr_t) == 8 ? \ 391 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 392 393 #define WM_CDTXSYNC(sc, x, n, ops) \ 394 do { \ 395 int __x, __n; \ 396 \ 397 __x = (x); \ 398 __n = (n); \ 399 \ 400 /* If it will wrap around, sync to the end of the ring. */ \ 401 if ((__x + __n) > WM_NTXDESC(sc)) { \ 402 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 403 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 404 (WM_NTXDESC(sc) - __x), (ops)); \ 405 __n -= (WM_NTXDESC(sc) - __x); \ 406 __x = 0; \ 407 } \ 408 \ 409 /* Now sync whatever is left. */ \ 410 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 411 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 412 } while (/*CONSTCOND*/0) 413 414 #define WM_CDRXSYNC(sc, x, ops) \ 415 do { \ 416 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 417 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 418 } while (/*CONSTCOND*/0) 419 420 #define WM_INIT_RXDESC(sc, x) \ 421 do { \ 422 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 423 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 424 struct mbuf *__m = __rxs->rxs_mbuf; \ 425 \ 426 /* \ 427 * Note: We scoot the packet forward 2 bytes in the buffer \ 428 * so that the payload after the Ethernet header is aligned \ 429 * to a 4-byte boundary. \ 430 * \ 431 * XXX BRAINDAMAGE ALERT! \ 432 * The stupid chip uses the same size for every buffer, which \ 433 * is set in the Receive Control register. We are using the 2K \ 434 * size option, but what we REALLY want is (2K - 2)! For this \ 435 * reason, we can't "scoot" packets longer than the standard \ 436 * Ethernet MTU. On strict-alignment platforms, if the total \ 437 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 438 * the upper layer copy the headers. \ 439 */ \ 440 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 441 \ 442 wm_set_dma_addr(&__rxd->wrx_addr, \ 443 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 444 __rxd->wrx_len = 0; \ 445 __rxd->wrx_cksum = 0; \ 446 __rxd->wrx_status = 0; \ 447 __rxd->wrx_errors = 0; \ 448 __rxd->wrx_special = 0; \ 449 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 450 \ 451 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 452 } while (/*CONSTCOND*/0) 453 454 static void wm_start(struct ifnet *); 455 static void wm_watchdog(struct ifnet *); 456 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 457 static int wm_init(struct ifnet *); 458 static void wm_stop(struct ifnet *, int); 459 460 static void wm_shutdown(void *); 461 462 static void wm_reset(struct wm_softc *); 463 static void wm_rxdrain(struct wm_softc *); 464 static int wm_add_rxbuf(struct wm_softc *, int); 465 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 466 static void wm_tick(void *); 467 468 static void wm_set_filter(struct wm_softc *); 469 470 static int wm_intr(void *); 471 static void wm_txintr(struct wm_softc *); 472 static void wm_rxintr(struct wm_softc *); 473 static void wm_linkintr(struct wm_softc *, uint32_t); 474 475 static void wm_tbi_mediainit(struct wm_softc *); 476 static int wm_tbi_mediachange(struct ifnet *); 477 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 478 479 static void wm_tbi_set_linkled(struct wm_softc *); 480 static void wm_tbi_check_link(struct wm_softc *); 481 482 static void wm_gmii_reset(struct wm_softc *); 483 484 static int wm_gmii_i82543_readreg(struct device *, int, int); 485 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 486 487 static int wm_gmii_i82544_readreg(struct device *, int, int); 488 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 489 490 static void wm_gmii_statchg(struct device *); 491 492 static void wm_gmii_mediainit(struct wm_softc *); 493 static int wm_gmii_mediachange(struct ifnet *); 494 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 495 496 static int wm_match(struct device *, struct cfdata *, void *); 497 static void wm_attach(struct device *, struct device *, void *); 498 499 CFATTACH_DECL(wm, sizeof(struct wm_softc), 500 wm_match, wm_attach, NULL, NULL); 501 502 static void wm_82547_txfifo_stall(void *); 503 504 /* 505 * Devices supported by this driver. 506 */ 507 static const struct wm_product { 508 pci_vendor_id_t wmp_vendor; 509 pci_product_id_t wmp_product; 510 const char *wmp_name; 511 wm_chip_type wmp_type; 512 int wmp_flags; 513 #define WMP_F_1000X 0x01 514 #define WMP_F_1000T 0x02 515 } wm_products[] = { 516 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 517 "Intel i82542 1000BASE-X Ethernet", 518 WM_T_82542_2_1, WMP_F_1000X }, 519 520 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 521 "Intel i82543GC 1000BASE-X Ethernet", 522 WM_T_82543, WMP_F_1000X }, 523 524 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 525 "Intel i82543GC 1000BASE-T Ethernet", 526 WM_T_82543, WMP_F_1000T }, 527 528 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 529 "Intel i82544EI 1000BASE-T Ethernet", 530 WM_T_82544, WMP_F_1000T }, 531 532 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 533 "Intel i82544EI 1000BASE-X Ethernet", 534 WM_T_82544, WMP_F_1000X }, 535 536 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 537 "Intel i82544GC 1000BASE-T Ethernet", 538 WM_T_82544, WMP_F_1000T }, 539 540 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 541 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 542 WM_T_82544, WMP_F_1000T }, 543 544 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 545 "Intel i82540EM 1000BASE-T Ethernet", 546 WM_T_82540, WMP_F_1000T }, 547 548 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 549 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 550 WM_T_82540, WMP_F_1000T }, 551 552 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 553 "Intel i82540EP 1000BASE-T Ethernet", 554 WM_T_82540, WMP_F_1000T }, 555 556 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 557 "Intel i82540EP 1000BASE-T Ethernet", 558 WM_T_82540, WMP_F_1000T }, 559 560 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 561 "Intel i82540EP 1000BASE-T Ethernet", 562 WM_T_82540, WMP_F_1000T }, 563 564 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 565 "Intel i82545EM 1000BASE-T Ethernet", 566 WM_T_82545, WMP_F_1000T }, 567 568 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 569 "Intel i82545GM 1000BASE-T Ethernet", 570 WM_T_82545_3, WMP_F_1000T }, 571 572 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 573 "Intel i82545GM 1000BASE-X Ethernet", 574 WM_T_82545_3, WMP_F_1000X }, 575 #if 0 576 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 577 "Intel i82545GM Gigabit Ethernet (SERDES)", 578 WM_T_82545_3, WMP_F_SERDES }, 579 #endif 580 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 581 "Intel i82546EB 1000BASE-T Ethernet", 582 WM_T_82546, WMP_F_1000T }, 583 584 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 585 "Intel i82546EB 1000BASE-T Ethernet", 586 WM_T_82546, WMP_F_1000T }, 587 588 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 589 "Intel i82545EM 1000BASE-X Ethernet", 590 WM_T_82545, WMP_F_1000X }, 591 592 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 593 "Intel i82546EB 1000BASE-X Ethernet", 594 WM_T_82546, WMP_F_1000X }, 595 596 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 597 "Intel i82546GB 1000BASE-T Ethernet", 598 WM_T_82546_3, WMP_F_1000T }, 599 600 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 601 "Intel i82546GB 1000BASE-X Ethernet", 602 WM_T_82546_3, WMP_F_1000X }, 603 #if 0 604 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 605 "Intel i82546GB Gigabit Ethernet (SERDES)", 606 WM_T_82546_3, WMP_F_SERDES }, 607 #endif 608 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 609 "Intel i82541EI 1000BASE-T Ethernet", 610 WM_T_82541, WMP_F_1000T }, 611 612 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 613 "Intel i82541EI Mobile 1000BASE-T Ethernet", 614 WM_T_82541, WMP_F_1000T }, 615 616 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 617 "Intel i82541ER 1000BASE-T Ethernet", 618 WM_T_82541_2, WMP_F_1000T }, 619 620 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 621 "Intel i82541GI 1000BASE-T Ethernet", 622 WM_T_82541_2, WMP_F_1000T }, 623 624 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 625 "Intel i82541GI Mobile 1000BASE-T Ethernet", 626 WM_T_82541_2, WMP_F_1000T }, 627 628 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 629 "Intel i82541PI 1000BASE-T Ethernet", 630 WM_T_82541_2, WMP_F_1000T }, 631 632 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 633 "Intel i82547EI 1000BASE-T Ethernet", 634 WM_T_82547, WMP_F_1000T }, 635 636 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 637 "Intel i82547GI 1000BASE-T Ethernet", 638 WM_T_82547_2, WMP_F_1000T }, 639 { 0, 0, 640 NULL, 641 0, 0 }, 642 }; 643 644 #ifdef WM_EVENT_COUNTERS 645 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 646 #endif /* WM_EVENT_COUNTERS */ 647 648 #if 0 /* Not currently used */ 649 static inline uint32_t 650 wm_io_read(struct wm_softc *sc, int reg) 651 { 652 653 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 654 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 655 } 656 #endif 657 658 static inline void 659 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 660 { 661 662 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 663 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 664 } 665 666 static inline void 667 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 668 { 669 wa->wa_low = htole32(v & 0xffffffffU); 670 if (sizeof(bus_addr_t) == 8) 671 wa->wa_high = htole32((uint64_t) v >> 32); 672 else 673 wa->wa_high = 0; 674 } 675 676 static const struct wm_product * 677 wm_lookup(const struct pci_attach_args *pa) 678 { 679 const struct wm_product *wmp; 680 681 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 682 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 683 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 684 return (wmp); 685 } 686 return (NULL); 687 } 688 689 static int 690 wm_match(struct device *parent, struct cfdata *cf, void *aux) 691 { 692 struct pci_attach_args *pa = aux; 693 694 if (wm_lookup(pa) != NULL) 695 return (1); 696 697 return (0); 698 } 699 700 static void 701 wm_attach(struct device *parent, struct device *self, void *aux) 702 { 703 struct wm_softc *sc = (void *) self; 704 struct pci_attach_args *pa = aux; 705 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 706 pci_chipset_tag_t pc = pa->pa_pc; 707 pci_intr_handle_t ih; 708 size_t cdata_size; 709 const char *intrstr = NULL; 710 const char *eetype; 711 bus_space_tag_t memt; 712 bus_space_handle_t memh; 713 bus_dma_segment_t seg; 714 int memh_valid; 715 int i, rseg, error; 716 const struct wm_product *wmp; 717 uint8_t enaddr[ETHER_ADDR_LEN]; 718 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 719 pcireg_t preg, memtype; 720 uint32_t reg; 721 int pmreg; 722 723 callout_init(&sc->sc_tick_ch); 724 725 wmp = wm_lookup(pa); 726 if (wmp == NULL) { 727 printf("\n"); 728 panic("wm_attach: impossible"); 729 } 730 731 if (pci_dma64_available(pa)) 732 sc->sc_dmat = pa->pa_dmat64; 733 else 734 sc->sc_dmat = pa->pa_dmat; 735 736 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 737 aprint_naive(": Ethernet controller\n"); 738 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 739 740 sc->sc_type = wmp->wmp_type; 741 if (sc->sc_type < WM_T_82543) { 742 if (preg < 2) { 743 aprint_error("%s: i82542 must be at least rev. 2\n", 744 sc->sc_dev.dv_xname); 745 return; 746 } 747 if (preg < 3) 748 sc->sc_type = WM_T_82542_2_0; 749 } 750 751 /* 752 * Map the device. All devices support memory-mapped acccess, 753 * and it is really required for normal operation. 754 */ 755 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 756 switch (memtype) { 757 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 758 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 759 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 760 memtype, 0, &memt, &memh, NULL, NULL) == 0); 761 break; 762 default: 763 memh_valid = 0; 764 } 765 766 if (memh_valid) { 767 sc->sc_st = memt; 768 sc->sc_sh = memh; 769 } else { 770 aprint_error("%s: unable to map device registers\n", 771 sc->sc_dev.dv_xname); 772 return; 773 } 774 775 /* 776 * In addition, i82544 and later support I/O mapped indirect 777 * register access. It is not desirable (nor supported in 778 * this driver) to use it for normal operation, though it is 779 * required to work around bugs in some chip versions. 780 */ 781 if (sc->sc_type >= WM_T_82544) { 782 /* First we have to find the I/O BAR. */ 783 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 784 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 785 PCI_MAPREG_TYPE_IO) 786 break; 787 } 788 if (i == PCI_MAPREG_END) 789 aprint_error("%s: WARNING: unable to find I/O BAR\n", 790 sc->sc_dev.dv_xname); 791 else { 792 /* 793 * The i8254x doesn't apparently respond when the 794 * I/O BAR is 0, which looks somewhat like it's not 795 * been configured. 796 */ 797 preg = pci_conf_read(pc, pa->pa_tag, i); 798 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 799 aprint_error("%s: WARNING: I/O BAR at zero.\n", 800 sc->sc_dev.dv_xname); 801 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 802 0, &sc->sc_iot, &sc->sc_ioh, 803 NULL, NULL) == 0) { 804 sc->sc_flags |= WM_F_IOH_VALID; 805 } else { 806 aprint_error("%s: WARNING: unable to map " 807 "I/O space\n", sc->sc_dev.dv_xname); 808 } 809 } 810 811 } 812 813 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 814 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 815 preg |= PCI_COMMAND_MASTER_ENABLE; 816 if (sc->sc_type < WM_T_82542_2_1) 817 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 818 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 819 820 /* Get it out of power save mode, if needed. */ 821 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 822 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 823 PCI_PMCSR_STATE_MASK; 824 if (preg == PCI_PMCSR_STATE_D3) { 825 /* 826 * The card has lost all configuration data in 827 * this state, so punt. 828 */ 829 aprint_error("%s: unable to wake from power state D3\n", 830 sc->sc_dev.dv_xname); 831 return; 832 } 833 if (preg != PCI_PMCSR_STATE_D0) { 834 aprint_normal("%s: waking up from power state D%d\n", 835 sc->sc_dev.dv_xname, preg); 836 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 837 PCI_PMCSR_STATE_D0); 838 } 839 } 840 841 /* 842 * Map and establish our interrupt. 843 */ 844 if (pci_intr_map(pa, &ih)) { 845 aprint_error("%s: unable to map interrupt\n", 846 sc->sc_dev.dv_xname); 847 return; 848 } 849 intrstr = pci_intr_string(pc, ih); 850 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 851 if (sc->sc_ih == NULL) { 852 aprint_error("%s: unable to establish interrupt", 853 sc->sc_dev.dv_xname); 854 if (intrstr != NULL) 855 aprint_normal(" at %s", intrstr); 856 aprint_normal("\n"); 857 return; 858 } 859 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 860 861 /* 862 * Determine a few things about the bus we're connected to. 863 */ 864 if (sc->sc_type < WM_T_82543) { 865 /* We don't really know the bus characteristics here. */ 866 sc->sc_bus_speed = 33; 867 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 868 /* 869 * CSA (Communication Streaming Architecture) is about as fast 870 * a 32-bit 66MHz PCI Bus. 871 */ 872 sc->sc_flags |= WM_F_CSA; 873 sc->sc_bus_speed = 66; 874 aprint_verbose("%s: Communication Streaming Architecture\n", 875 sc->sc_dev.dv_xname); 876 if (sc->sc_type == WM_T_82547) { 877 callout_init(&sc->sc_txfifo_ch); 878 callout_setfunc(&sc->sc_txfifo_ch, 879 wm_82547_txfifo_stall, sc); 880 aprint_verbose("%s: using 82547 Tx FIFO stall " 881 "work-around\n", sc->sc_dev.dv_xname); 882 } 883 } else { 884 reg = CSR_READ(sc, WMREG_STATUS); 885 if (reg & STATUS_BUS64) 886 sc->sc_flags |= WM_F_BUS64; 887 if (sc->sc_type >= WM_T_82544 && 888 (reg & STATUS_PCIX_MODE) != 0) { 889 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 890 891 sc->sc_flags |= WM_F_PCIX; 892 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 893 PCI_CAP_PCIX, 894 &sc->sc_pcix_offset, NULL) == 0) 895 aprint_error("%s: unable to find PCIX " 896 "capability\n", sc->sc_dev.dv_xname); 897 else if (sc->sc_type != WM_T_82545_3 && 898 sc->sc_type != WM_T_82546_3) { 899 /* 900 * Work around a problem caused by the BIOS 901 * setting the max memory read byte count 902 * incorrectly. 903 */ 904 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 905 sc->sc_pcix_offset + PCI_PCIX_CMD); 906 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 907 sc->sc_pcix_offset + PCI_PCIX_STATUS); 908 909 bytecnt = 910 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 911 PCI_PCIX_CMD_BYTECNT_SHIFT; 912 maxb = 913 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 914 PCI_PCIX_STATUS_MAXB_SHIFT; 915 if (bytecnt > maxb) { 916 aprint_verbose("%s: resetting PCI-X " 917 "MMRBC: %d -> %d\n", 918 sc->sc_dev.dv_xname, 919 512 << bytecnt, 512 << maxb); 920 pcix_cmd = (pcix_cmd & 921 ~PCI_PCIX_CMD_BYTECNT_MASK) | 922 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 923 pci_conf_write(pa->pa_pc, pa->pa_tag, 924 sc->sc_pcix_offset + PCI_PCIX_CMD, 925 pcix_cmd); 926 } 927 } 928 } 929 /* 930 * The quad port adapter is special; it has a PCIX-PCIX 931 * bridge on the board, and can run the secondary bus at 932 * a higher speed. 933 */ 934 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 935 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 936 : 66; 937 } else if (sc->sc_flags & WM_F_PCIX) { 938 switch (reg & STATUS_PCIXSPD_MASK) { 939 case STATUS_PCIXSPD_50_66: 940 sc->sc_bus_speed = 66; 941 break; 942 case STATUS_PCIXSPD_66_100: 943 sc->sc_bus_speed = 100; 944 break; 945 case STATUS_PCIXSPD_100_133: 946 sc->sc_bus_speed = 133; 947 break; 948 default: 949 aprint_error( 950 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 951 sc->sc_dev.dv_xname, 952 reg & STATUS_PCIXSPD_MASK); 953 sc->sc_bus_speed = 66; 954 } 955 } else 956 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 957 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 958 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 959 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 960 } 961 962 /* 963 * Allocate the control data structures, and create and load the 964 * DMA map for it. 965 * 966 * NOTE: All Tx descriptors must be in the same 4G segment of 967 * memory. So must Rx descriptors. We simplify by allocating 968 * both sets within the same 4G segment. 969 */ 970 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 971 WM_NTXDESC_82542 : WM_NTXDESC_82544; 972 cdata_size = sc->sc_type < WM_T_82544 ? 973 sizeof(struct wm_control_data_82542) : 974 sizeof(struct wm_control_data_82544); 975 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 976 (bus_size_t) 0x100000000ULL, 977 &seg, 1, &rseg, 0)) != 0) { 978 aprint_error( 979 "%s: unable to allocate control data, error = %d\n", 980 sc->sc_dev.dv_xname, error); 981 goto fail_0; 982 } 983 984 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 985 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 986 aprint_error("%s: unable to map control data, error = %d\n", 987 sc->sc_dev.dv_xname, error); 988 goto fail_1; 989 } 990 991 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 992 0, 0, &sc->sc_cddmamap)) != 0) { 993 aprint_error("%s: unable to create control data DMA map, " 994 "error = %d\n", sc->sc_dev.dv_xname, error); 995 goto fail_2; 996 } 997 998 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 999 sc->sc_control_data, cdata_size, NULL, 1000 0)) != 0) { 1001 aprint_error( 1002 "%s: unable to load control data DMA map, error = %d\n", 1003 sc->sc_dev.dv_xname, error); 1004 goto fail_3; 1005 } 1006 1007 1008 /* 1009 * Create the transmit buffer DMA maps. 1010 */ 1011 WM_TXQUEUELEN(sc) = 1012 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1013 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1014 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1015 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1016 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1017 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1018 aprint_error("%s: unable to create Tx DMA map %d, " 1019 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1020 goto fail_4; 1021 } 1022 } 1023 1024 /* 1025 * Create the receive buffer DMA maps. 1026 */ 1027 for (i = 0; i < WM_NRXDESC; i++) { 1028 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1029 MCLBYTES, 0, 0, 1030 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1031 aprint_error("%s: unable to create Rx DMA map %d, " 1032 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1033 goto fail_5; 1034 } 1035 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1036 } 1037 1038 /* 1039 * Reset the chip to a known state. 1040 */ 1041 wm_reset(sc); 1042 1043 /* 1044 * Get some information about the EEPROM. 1045 */ 1046 if (sc->sc_type >= WM_T_82540) 1047 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1048 if (sc->sc_type <= WM_T_82544) 1049 sc->sc_ee_addrbits = 6; 1050 else if (sc->sc_type <= WM_T_82546_3) { 1051 reg = CSR_READ(sc, WMREG_EECD); 1052 if (reg & EECD_EE_SIZE) 1053 sc->sc_ee_addrbits = 8; 1054 else 1055 sc->sc_ee_addrbits = 6; 1056 } else if (sc->sc_type <= WM_T_82547_2) { 1057 reg = CSR_READ(sc, WMREG_EECD); 1058 if (reg & EECD_EE_TYPE) { 1059 sc->sc_flags |= WM_F_EEPROM_SPI; 1060 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1061 } else 1062 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1063 } else { 1064 /* Assume everything else is SPI. */ 1065 reg = CSR_READ(sc, WMREG_EECD); 1066 sc->sc_flags |= WM_F_EEPROM_SPI; 1067 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1068 } 1069 if (sc->sc_flags & WM_F_EEPROM_SPI) 1070 eetype = "SPI"; 1071 else 1072 eetype = "MicroWire"; 1073 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1074 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1075 sc->sc_ee_addrbits, eetype); 1076 1077 /* 1078 * Read the Ethernet address from the EEPROM. 1079 */ 1080 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1081 sizeof(myea) / sizeof(myea[0]), myea)) { 1082 aprint_error("%s: unable to read Ethernet address\n", 1083 sc->sc_dev.dv_xname); 1084 return; 1085 } 1086 enaddr[0] = myea[0] & 0xff; 1087 enaddr[1] = myea[0] >> 8; 1088 enaddr[2] = myea[1] & 0xff; 1089 enaddr[3] = myea[1] >> 8; 1090 enaddr[4] = myea[2] & 0xff; 1091 enaddr[5] = myea[2] >> 8; 1092 1093 /* 1094 * Toggle the LSB of the MAC address on the second port 1095 * of the i82546. 1096 */ 1097 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1098 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1099 enaddr[5] ^= 1; 1100 } 1101 1102 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1103 ether_sprintf(enaddr)); 1104 1105 /* 1106 * Read the config info from the EEPROM, and set up various 1107 * bits in the control registers based on their contents. 1108 */ 1109 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1110 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1111 sc->sc_dev.dv_xname); 1112 return; 1113 } 1114 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1115 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1116 sc->sc_dev.dv_xname); 1117 return; 1118 } 1119 if (sc->sc_type >= WM_T_82544) { 1120 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1121 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1122 sc->sc_dev.dv_xname); 1123 return; 1124 } 1125 } 1126 1127 if (cfg1 & EEPROM_CFG1_ILOS) 1128 sc->sc_ctrl |= CTRL_ILOS; 1129 if (sc->sc_type >= WM_T_82544) { 1130 sc->sc_ctrl |= 1131 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1132 CTRL_SWDPIO_SHIFT; 1133 sc->sc_ctrl |= 1134 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1135 CTRL_SWDPINS_SHIFT; 1136 } else { 1137 sc->sc_ctrl |= 1138 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1139 CTRL_SWDPIO_SHIFT; 1140 } 1141 1142 #if 0 1143 if (sc->sc_type >= WM_T_82544) { 1144 if (cfg1 & EEPROM_CFG1_IPS0) 1145 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1146 if (cfg1 & EEPROM_CFG1_IPS1) 1147 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1148 sc->sc_ctrl_ext |= 1149 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1150 CTRL_EXT_SWDPIO_SHIFT; 1151 sc->sc_ctrl_ext |= 1152 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1153 CTRL_EXT_SWDPINS_SHIFT; 1154 } else { 1155 sc->sc_ctrl_ext |= 1156 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1157 CTRL_EXT_SWDPIO_SHIFT; 1158 } 1159 #endif 1160 1161 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1162 #if 0 1163 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1164 #endif 1165 1166 /* 1167 * Set up some register offsets that are different between 1168 * the i82542 and the i82543 and later chips. 1169 */ 1170 if (sc->sc_type < WM_T_82543) { 1171 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1172 sc->sc_tdt_reg = WMREG_OLD_TDT; 1173 } else { 1174 sc->sc_rdt_reg = WMREG_RDT; 1175 sc->sc_tdt_reg = WMREG_TDT; 1176 } 1177 1178 /* 1179 * Determine if we're TBI or GMII mode, and initialize the 1180 * media structures accordingly. 1181 */ 1182 if (sc->sc_type < WM_T_82543 || 1183 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1184 if (wmp->wmp_flags & WMP_F_1000T) 1185 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1186 "product!\n", sc->sc_dev.dv_xname); 1187 wm_tbi_mediainit(sc); 1188 } else { 1189 if (wmp->wmp_flags & WMP_F_1000X) 1190 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1191 "product!\n", sc->sc_dev.dv_xname); 1192 wm_gmii_mediainit(sc); 1193 } 1194 1195 ifp = &sc->sc_ethercom.ec_if; 1196 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1197 ifp->if_softc = sc; 1198 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1199 ifp->if_ioctl = wm_ioctl; 1200 ifp->if_start = wm_start; 1201 ifp->if_watchdog = wm_watchdog; 1202 ifp->if_init = wm_init; 1203 ifp->if_stop = wm_stop; 1204 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1205 IFQ_SET_READY(&ifp->if_snd); 1206 1207 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1208 1209 /* 1210 * If we're a i82543 or greater, we can support VLANs. 1211 */ 1212 if (sc->sc_type >= WM_T_82543) 1213 sc->sc_ethercom.ec_capabilities |= 1214 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1215 1216 /* 1217 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1218 * on i82543 and later. 1219 */ 1220 if (sc->sc_type >= WM_T_82543) 1221 ifp->if_capabilities |= 1222 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1223 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1224 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1225 IFCAP_CSUM_TCPv6_Tx | 1226 IFCAP_CSUM_UDPv6_Tx; 1227 1228 /* 1229 * If we're a i82544 or greater (except i82547), we can do 1230 * TCP segmentation offload. 1231 */ 1232 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1233 ifp->if_capabilities |= IFCAP_TSOv4; 1234 1235 /* 1236 * Attach the interface. 1237 */ 1238 if_attach(ifp); 1239 ether_ifattach(ifp, enaddr); 1240 #if NRND > 0 1241 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1242 RND_TYPE_NET, 0); 1243 #endif 1244 1245 #ifdef WM_EVENT_COUNTERS 1246 /* Attach event counters. */ 1247 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1248 NULL, sc->sc_dev.dv_xname, "txsstall"); 1249 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1250 NULL, sc->sc_dev.dv_xname, "txdstall"); 1251 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1252 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1253 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1254 NULL, sc->sc_dev.dv_xname, "txdw"); 1255 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1256 NULL, sc->sc_dev.dv_xname, "txqe"); 1257 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1258 NULL, sc->sc_dev.dv_xname, "rxintr"); 1259 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1260 NULL, sc->sc_dev.dv_xname, "linkintr"); 1261 1262 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1264 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1265 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1266 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1267 NULL, sc->sc_dev.dv_xname, "txipsum"); 1268 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1269 NULL, sc->sc_dev.dv_xname, "txtusum"); 1270 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1271 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1272 1273 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "txtso"); 1275 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1276 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1277 1278 for (i = 0; i < WM_NTXSEGS; i++) { 1279 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1280 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1281 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1282 } 1283 1284 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1285 NULL, sc->sc_dev.dv_xname, "txdrop"); 1286 1287 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "tu"); 1289 1290 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1291 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1292 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1293 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1294 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1295 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1296 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1297 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1298 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1299 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1300 #endif /* WM_EVENT_COUNTERS */ 1301 1302 /* 1303 * Make sure the interface is shutdown during reboot. 1304 */ 1305 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1306 if (sc->sc_sdhook == NULL) 1307 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1308 sc->sc_dev.dv_xname); 1309 return; 1310 1311 /* 1312 * Free any resources we've allocated during the failed attach 1313 * attempt. Do this in reverse order and fall through. 1314 */ 1315 fail_5: 1316 for (i = 0; i < WM_NRXDESC; i++) { 1317 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1318 bus_dmamap_destroy(sc->sc_dmat, 1319 sc->sc_rxsoft[i].rxs_dmamap); 1320 } 1321 fail_4: 1322 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1323 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1324 bus_dmamap_destroy(sc->sc_dmat, 1325 sc->sc_txsoft[i].txs_dmamap); 1326 } 1327 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1328 fail_3: 1329 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1330 fail_2: 1331 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1332 cdata_size); 1333 fail_1: 1334 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1335 fail_0: 1336 return; 1337 } 1338 1339 /* 1340 * wm_shutdown: 1341 * 1342 * Make sure the interface is stopped at reboot time. 1343 */ 1344 static void 1345 wm_shutdown(void *arg) 1346 { 1347 struct wm_softc *sc = arg; 1348 1349 wm_stop(&sc->sc_ethercom.ec_if, 1); 1350 } 1351 1352 /* 1353 * wm_tx_offload: 1354 * 1355 * Set up TCP/IP checksumming parameters for the 1356 * specified packet. 1357 */ 1358 static int 1359 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1360 uint8_t *fieldsp) 1361 { 1362 struct mbuf *m0 = txs->txs_mbuf; 1363 struct livengood_tcpip_ctxdesc *t; 1364 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1365 struct ether_header *eh; 1366 int offset, iphl; 1367 uint8_t fields; 1368 1369 /* 1370 * XXX It would be nice if the mbuf pkthdr had offset 1371 * fields for the protocol headers. 1372 */ 1373 1374 eh = mtod(m0, struct ether_header *); 1375 switch (htons(eh->ether_type)) { 1376 case ETHERTYPE_IP: 1377 case ETHERTYPE_IPV6: 1378 offset = ETHER_HDR_LEN; 1379 break; 1380 1381 case ETHERTYPE_VLAN: 1382 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1383 break; 1384 1385 default: 1386 /* 1387 * Don't support this protocol or encapsulation. 1388 */ 1389 *fieldsp = 0; 1390 *cmdp = 0; 1391 return (0); 1392 } 1393 1394 if ((m0->m_pkthdr.csum_flags & 1395 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1396 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1397 } else { 1398 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1399 } 1400 1401 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1402 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1403 seg = 0; 1404 fields = 0; 1405 1406 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1407 int hlen = offset + iphl; 1408 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1409 if (__predict_false(m0->m_len < 1410 (hlen + sizeof(struct tcphdr)))) { 1411 /* 1412 * TCP/IP headers are not in the first mbuf; we need 1413 * to do this the slow and painful way. Let's just 1414 * hope this doesn't happen very often. 1415 */ 1416 struct ip ip; 1417 struct tcphdr th; 1418 1419 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1420 1421 m_copydata(m0, offset, sizeof(ip), &ip); 1422 m_copydata(m0, hlen, sizeof(th), &th); 1423 1424 ip.ip_len = 0; 1425 1426 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1427 sizeof(ip.ip_len), &ip.ip_len); 1428 1429 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1430 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1431 1432 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1433 sizeof(th.th_sum), &th.th_sum); 1434 1435 hlen += th.th_off << 2; 1436 } else { 1437 /* 1438 * TCP/IP headers are in the first mbuf; we can do 1439 * this the easy way. 1440 */ 1441 struct ip *ip = 1442 (struct ip *) (mtod(m0, caddr_t) + offset); 1443 struct tcphdr *th = 1444 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1445 1446 ip->ip_len = 0; 1447 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1448 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1449 1450 hlen += th->th_off << 2; 1451 } 1452 1453 cmd |= WTX_TCPIP_CMD_TSE; 1454 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1455 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1456 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1457 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1458 } 1459 1460 /* 1461 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1462 * offload feature, if we load the context descriptor, we 1463 * MUST provide valid values for IPCSS and TUCSS fields. 1464 */ 1465 1466 ipcs = WTX_TCPIP_IPCSS(offset) | 1467 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1468 WTX_TCPIP_IPCSE(offset + iphl - 1); 1469 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1470 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1471 fields |= WTX_IXSM; 1472 } 1473 1474 offset += iphl; 1475 1476 if (m0->m_pkthdr.csum_flags & 1477 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1478 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1479 fields |= WTX_TXSM; 1480 tucs = WTX_TCPIP_TUCSS(offset) | 1481 WTX_TCPIP_TUCSO(offset + 1482 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1483 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1484 } else if ((m0->m_pkthdr.csum_flags & 1485 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) { 1486 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1487 fields |= WTX_TXSM; 1488 tucs = WTX_TCPIP_TUCSS(offset) | 1489 WTX_TCPIP_TUCSO(offset + 1490 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1491 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1492 } else { 1493 /* Just initialize it to a valid TCP context. */ 1494 tucs = WTX_TCPIP_TUCSS(offset) | 1495 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1496 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1497 } 1498 1499 /* Fill in the context descriptor. */ 1500 t = (struct livengood_tcpip_ctxdesc *) 1501 &sc->sc_txdescs[sc->sc_txnext]; 1502 t->tcpip_ipcs = htole32(ipcs); 1503 t->tcpip_tucs = htole32(tucs); 1504 t->tcpip_cmdlen = htole32(cmdlen); 1505 t->tcpip_seg = htole32(seg); 1506 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1507 1508 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1509 txs->txs_ndesc++; 1510 1511 *cmdp = cmd; 1512 *fieldsp = fields; 1513 1514 return (0); 1515 } 1516 1517 static void 1518 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1519 { 1520 struct mbuf *m; 1521 int i; 1522 1523 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1524 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1525 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1526 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1527 m->m_data, m->m_len, m->m_flags); 1528 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1529 i, i == 1 ? "" : "s"); 1530 } 1531 1532 /* 1533 * wm_82547_txfifo_stall: 1534 * 1535 * Callout used to wait for the 82547 Tx FIFO to drain, 1536 * reset the FIFO pointers, and restart packet transmission. 1537 */ 1538 static void 1539 wm_82547_txfifo_stall(void *arg) 1540 { 1541 struct wm_softc *sc = arg; 1542 int s; 1543 1544 s = splnet(); 1545 1546 if (sc->sc_txfifo_stall) { 1547 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1548 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1549 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1550 /* 1551 * Packets have drained. Stop transmitter, reset 1552 * FIFO pointers, restart transmitter, and kick 1553 * the packet queue. 1554 */ 1555 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1556 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1557 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1558 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1559 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1560 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1561 CSR_WRITE(sc, WMREG_TCTL, tctl); 1562 CSR_WRITE_FLUSH(sc); 1563 1564 sc->sc_txfifo_head = 0; 1565 sc->sc_txfifo_stall = 0; 1566 wm_start(&sc->sc_ethercom.ec_if); 1567 } else { 1568 /* 1569 * Still waiting for packets to drain; try again in 1570 * another tick. 1571 */ 1572 callout_schedule(&sc->sc_txfifo_ch, 1); 1573 } 1574 } 1575 1576 splx(s); 1577 } 1578 1579 /* 1580 * wm_82547_txfifo_bugchk: 1581 * 1582 * Check for bug condition in the 82547 Tx FIFO. We need to 1583 * prevent enqueueing a packet that would wrap around the end 1584 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1585 * 1586 * We do this by checking the amount of space before the end 1587 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1588 * the Tx FIFO, wait for all remaining packets to drain, reset 1589 * the internal FIFO pointers to the beginning, and restart 1590 * transmission on the interface. 1591 */ 1592 #define WM_FIFO_HDR 0x10 1593 #define WM_82547_PAD_LEN 0x3e0 1594 static int 1595 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1596 { 1597 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1598 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1599 1600 /* Just return if already stalled. */ 1601 if (sc->sc_txfifo_stall) 1602 return (1); 1603 1604 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1605 /* Stall only occurs in half-duplex mode. */ 1606 goto send_packet; 1607 } 1608 1609 if (len >= WM_82547_PAD_LEN + space) { 1610 sc->sc_txfifo_stall = 1; 1611 callout_schedule(&sc->sc_txfifo_ch, 1); 1612 return (1); 1613 } 1614 1615 send_packet: 1616 sc->sc_txfifo_head += len; 1617 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1618 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1619 1620 return (0); 1621 } 1622 1623 /* 1624 * wm_start: [ifnet interface function] 1625 * 1626 * Start packet transmission on the interface. 1627 */ 1628 static void 1629 wm_start(struct ifnet *ifp) 1630 { 1631 struct wm_softc *sc = ifp->if_softc; 1632 struct mbuf *m0; 1633 #if 0 /* XXXJRT */ 1634 struct m_tag *mtag; 1635 #endif 1636 struct wm_txsoft *txs; 1637 bus_dmamap_t dmamap; 1638 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1639 bus_addr_t curaddr; 1640 bus_size_t seglen, curlen; 1641 uint32_t cksumcmd; 1642 uint8_t cksumfields; 1643 1644 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1645 return; 1646 1647 /* 1648 * Remember the previous number of free descriptors. 1649 */ 1650 ofree = sc->sc_txfree; 1651 1652 /* 1653 * Loop through the send queue, setting up transmit descriptors 1654 * until we drain the queue, or use up all available transmit 1655 * descriptors. 1656 */ 1657 for (;;) { 1658 /* Grab a packet off the queue. */ 1659 IFQ_POLL(&ifp->if_snd, m0); 1660 if (m0 == NULL) 1661 break; 1662 1663 DPRINTF(WM_DEBUG_TX, 1664 ("%s: TX: have packet to transmit: %p\n", 1665 sc->sc_dev.dv_xname, m0)); 1666 1667 /* Get a work queue entry. */ 1668 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1669 wm_txintr(sc); 1670 if (sc->sc_txsfree == 0) { 1671 DPRINTF(WM_DEBUG_TX, 1672 ("%s: TX: no free job descriptors\n", 1673 sc->sc_dev.dv_xname)); 1674 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1675 break; 1676 } 1677 } 1678 1679 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1680 dmamap = txs->txs_dmamap; 1681 1682 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1683 1684 /* 1685 * So says the Linux driver: 1686 * The controller does a simple calculation to make sure 1687 * there is enough room in the FIFO before initiating the 1688 * DMA for each buffer. The calc is: 1689 * 4 = ceil(buffer len / MSS) 1690 * To make sure we don't overrun the FIFO, adjust the max 1691 * buffer len if the MSS drops. 1692 */ 1693 dmamap->dm_maxsegsz = 1694 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1695 ? m0->m_pkthdr.segsz << 2 1696 : WTX_MAX_LEN; 1697 1698 /* 1699 * Load the DMA map. If this fails, the packet either 1700 * didn't fit in the allotted number of segments, or we 1701 * were short on resources. For the too-many-segments 1702 * case, we simply report an error and drop the packet, 1703 * since we can't sanely copy a jumbo packet to a single 1704 * buffer. 1705 */ 1706 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1707 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1708 if (error) { 1709 if (error == EFBIG) { 1710 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1711 log(LOG_ERR, "%s: Tx packet consumes too many " 1712 "DMA segments, dropping...\n", 1713 sc->sc_dev.dv_xname); 1714 IFQ_DEQUEUE(&ifp->if_snd, m0); 1715 wm_dump_mbuf_chain(sc, m0); 1716 m_freem(m0); 1717 continue; 1718 } 1719 /* 1720 * Short on resources, just stop for now. 1721 */ 1722 DPRINTF(WM_DEBUG_TX, 1723 ("%s: TX: dmamap load failed: %d\n", 1724 sc->sc_dev.dv_xname, error)); 1725 break; 1726 } 1727 1728 segs_needed = dmamap->dm_nsegs; 1729 if (use_tso) { 1730 /* For sentinel descriptor; see below. */ 1731 segs_needed++; 1732 } 1733 1734 /* 1735 * Ensure we have enough descriptors free to describe 1736 * the packet. Note, we always reserve one descriptor 1737 * at the end of the ring due to the semantics of the 1738 * TDT register, plus one more in the event we need 1739 * to load offload context. 1740 */ 1741 if (segs_needed > sc->sc_txfree - 2) { 1742 /* 1743 * Not enough free descriptors to transmit this 1744 * packet. We haven't committed anything yet, 1745 * so just unload the DMA map, put the packet 1746 * pack on the queue, and punt. Notify the upper 1747 * layer that there are no more slots left. 1748 */ 1749 DPRINTF(WM_DEBUG_TX, 1750 ("%s: TX: need %d (%d) descriptors, have %d\n", 1751 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1752 sc->sc_txfree - 1)); 1753 ifp->if_flags |= IFF_OACTIVE; 1754 bus_dmamap_unload(sc->sc_dmat, dmamap); 1755 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1756 break; 1757 } 1758 1759 /* 1760 * Check for 82547 Tx FIFO bug. We need to do this 1761 * once we know we can transmit the packet, since we 1762 * do some internal FIFO space accounting here. 1763 */ 1764 if (sc->sc_type == WM_T_82547 && 1765 wm_82547_txfifo_bugchk(sc, m0)) { 1766 DPRINTF(WM_DEBUG_TX, 1767 ("%s: TX: 82547 Tx FIFO bug detected\n", 1768 sc->sc_dev.dv_xname)); 1769 ifp->if_flags |= IFF_OACTIVE; 1770 bus_dmamap_unload(sc->sc_dmat, dmamap); 1771 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1772 break; 1773 } 1774 1775 IFQ_DEQUEUE(&ifp->if_snd, m0); 1776 1777 /* 1778 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1779 */ 1780 1781 DPRINTF(WM_DEBUG_TX, 1782 ("%s: TX: packet has %d (%d) DMA segments\n", 1783 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1784 1785 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1786 1787 /* 1788 * Store a pointer to the packet so that we can free it 1789 * later. 1790 * 1791 * Initially, we consider the number of descriptors the 1792 * packet uses the number of DMA segments. This may be 1793 * incremented by 1 if we do checksum offload (a descriptor 1794 * is used to set the checksum context). 1795 */ 1796 txs->txs_mbuf = m0; 1797 txs->txs_firstdesc = sc->sc_txnext; 1798 txs->txs_ndesc = segs_needed; 1799 1800 /* Set up offload parameters for this packet. */ 1801 if (m0->m_pkthdr.csum_flags & 1802 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 1803 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 1804 if (wm_tx_offload(sc, txs, &cksumcmd, 1805 &cksumfields) != 0) { 1806 /* Error message already displayed. */ 1807 bus_dmamap_unload(sc->sc_dmat, dmamap); 1808 continue; 1809 } 1810 } else { 1811 cksumcmd = 0; 1812 cksumfields = 0; 1813 } 1814 1815 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1816 1817 /* Sync the DMA map. */ 1818 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1819 BUS_DMASYNC_PREWRITE); 1820 1821 /* 1822 * Initialize the transmit descriptor. 1823 */ 1824 for (nexttx = sc->sc_txnext, seg = 0; 1825 seg < dmamap->dm_nsegs; seg++) { 1826 for (seglen = dmamap->dm_segs[seg].ds_len, 1827 curaddr = dmamap->dm_segs[seg].ds_addr; 1828 seglen != 0; 1829 curaddr += curlen, seglen -= curlen, 1830 nexttx = WM_NEXTTX(sc, nexttx)) { 1831 curlen = seglen; 1832 1833 /* 1834 * So says the Linux driver: 1835 * Work around for premature descriptor 1836 * write-backs in TSO mode. Append a 1837 * 4-byte sentinel descriptor. 1838 */ 1839 if (use_tso && 1840 seg == dmamap->dm_nsegs - 1 && 1841 curlen > 8) 1842 curlen -= 4; 1843 1844 wm_set_dma_addr( 1845 &sc->sc_txdescs[nexttx].wtx_addr, 1846 curaddr); 1847 sc->sc_txdescs[nexttx].wtx_cmdlen = 1848 htole32(cksumcmd | curlen); 1849 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1850 0; 1851 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1852 cksumfields; 1853 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1854 lasttx = nexttx; 1855 1856 DPRINTF(WM_DEBUG_TX, 1857 ("%s: TX: desc %d: low 0x%08lx, " 1858 "len 0x%04x\n", 1859 sc->sc_dev.dv_xname, nexttx, 1860 curaddr & 0xffffffffUL, (unsigned)curlen)); 1861 } 1862 } 1863 1864 KASSERT(lasttx != -1); 1865 1866 /* 1867 * Set up the command byte on the last descriptor of 1868 * the packet. If we're in the interrupt delay window, 1869 * delay the interrupt. 1870 */ 1871 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1872 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1873 1874 #if 0 /* XXXJRT */ 1875 /* 1876 * If VLANs are enabled and the packet has a VLAN tag, set 1877 * up the descriptor to encapsulate the packet for us. 1878 * 1879 * This is only valid on the last descriptor of the packet. 1880 */ 1881 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1882 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1883 htole32(WTX_CMD_VLE); 1884 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1885 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1886 } 1887 #endif /* XXXJRT */ 1888 1889 txs->txs_lastdesc = lasttx; 1890 1891 DPRINTF(WM_DEBUG_TX, 1892 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1893 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1894 1895 /* Sync the descriptors we're using. */ 1896 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1897 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1898 1899 /* Give the packet to the chip. */ 1900 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1901 1902 DPRINTF(WM_DEBUG_TX, 1903 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1904 1905 DPRINTF(WM_DEBUG_TX, 1906 ("%s: TX: finished transmitting packet, job %d\n", 1907 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1908 1909 /* Advance the tx pointer. */ 1910 sc->sc_txfree -= txs->txs_ndesc; 1911 sc->sc_txnext = nexttx; 1912 1913 sc->sc_txsfree--; 1914 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1915 1916 #if NBPFILTER > 0 1917 /* Pass the packet to any BPF listeners. */ 1918 if (ifp->if_bpf) 1919 bpf_mtap(ifp->if_bpf, m0); 1920 #endif /* NBPFILTER > 0 */ 1921 } 1922 1923 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1924 /* No more slots; notify upper layer. */ 1925 ifp->if_flags |= IFF_OACTIVE; 1926 } 1927 1928 if (sc->sc_txfree != ofree) { 1929 /* Set a watchdog timer in case the chip flakes out. */ 1930 ifp->if_timer = 5; 1931 } 1932 } 1933 1934 /* 1935 * wm_watchdog: [ifnet interface function] 1936 * 1937 * Watchdog timer handler. 1938 */ 1939 static void 1940 wm_watchdog(struct ifnet *ifp) 1941 { 1942 struct wm_softc *sc = ifp->if_softc; 1943 1944 /* 1945 * Since we're using delayed interrupts, sweep up 1946 * before we report an error. 1947 */ 1948 wm_txintr(sc); 1949 1950 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1951 log(LOG_ERR, 1952 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1953 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1954 sc->sc_txnext); 1955 ifp->if_oerrors++; 1956 1957 /* Reset the interface. */ 1958 (void) wm_init(ifp); 1959 } 1960 1961 /* Try to get more packets going. */ 1962 wm_start(ifp); 1963 } 1964 1965 /* 1966 * wm_ioctl: [ifnet interface function] 1967 * 1968 * Handle control requests from the operator. 1969 */ 1970 static int 1971 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1972 { 1973 struct wm_softc *sc = ifp->if_softc; 1974 struct ifreq *ifr = (struct ifreq *) data; 1975 int s, error; 1976 1977 s = splnet(); 1978 1979 switch (cmd) { 1980 case SIOCSIFMEDIA: 1981 case SIOCGIFMEDIA: 1982 /* Flow control requires full-duplex mode. */ 1983 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1984 (ifr->ifr_media & IFM_FDX) == 0) 1985 ifr->ifr_media &= ~IFM_ETH_FMASK; 1986 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1987 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1988 /* We can do both TXPAUSE and RXPAUSE. */ 1989 ifr->ifr_media |= 1990 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1991 } 1992 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1993 } 1994 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1995 break; 1996 default: 1997 error = ether_ioctl(ifp, cmd, data); 1998 if (error == ENETRESET) { 1999 /* 2000 * Multicast list has changed; set the hardware filter 2001 * accordingly. 2002 */ 2003 if (ifp->if_flags & IFF_RUNNING) 2004 wm_set_filter(sc); 2005 error = 0; 2006 } 2007 break; 2008 } 2009 2010 /* Try to get more packets going. */ 2011 wm_start(ifp); 2012 2013 splx(s); 2014 return (error); 2015 } 2016 2017 /* 2018 * wm_intr: 2019 * 2020 * Interrupt service routine. 2021 */ 2022 static int 2023 wm_intr(void *arg) 2024 { 2025 struct wm_softc *sc = arg; 2026 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2027 uint32_t icr; 2028 int handled = 0; 2029 2030 while (1 /* CONSTCOND */) { 2031 icr = CSR_READ(sc, WMREG_ICR); 2032 if ((icr & sc->sc_icr) == 0) 2033 break; 2034 2035 #if 0 /*NRND > 0*/ 2036 if (RND_ENABLED(&sc->rnd_source)) 2037 rnd_add_uint32(&sc->rnd_source, icr); 2038 #endif 2039 2040 handled = 1; 2041 2042 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2043 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2044 DPRINTF(WM_DEBUG_RX, 2045 ("%s: RX: got Rx intr 0x%08x\n", 2046 sc->sc_dev.dv_xname, 2047 icr & (ICR_RXDMT0|ICR_RXT0))); 2048 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2049 } 2050 #endif 2051 wm_rxintr(sc); 2052 2053 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2054 if (icr & ICR_TXDW) { 2055 DPRINTF(WM_DEBUG_TX, 2056 ("%s: TX: got TXDW interrupt\n", 2057 sc->sc_dev.dv_xname)); 2058 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2059 } 2060 #endif 2061 wm_txintr(sc); 2062 2063 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2064 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2065 wm_linkintr(sc, icr); 2066 } 2067 2068 if (icr & ICR_RXO) { 2069 ifp->if_ierrors++; 2070 #if defined(WM_DEBUG) 2071 log(LOG_WARNING, "%s: Receive overrun\n", 2072 sc->sc_dev.dv_xname); 2073 #endif /* defined(WM_DEBUG) */ 2074 } 2075 } 2076 2077 if (handled) { 2078 /* Try to get more packets going. */ 2079 wm_start(ifp); 2080 } 2081 2082 return (handled); 2083 } 2084 2085 /* 2086 * wm_txintr: 2087 * 2088 * Helper; handle transmit interrupts. 2089 */ 2090 static void 2091 wm_txintr(struct wm_softc *sc) 2092 { 2093 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2094 struct wm_txsoft *txs; 2095 uint8_t status; 2096 int i; 2097 2098 ifp->if_flags &= ~IFF_OACTIVE; 2099 2100 /* 2101 * Go through the Tx list and free mbufs for those 2102 * frames which have been transmitted. 2103 */ 2104 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2105 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2106 txs = &sc->sc_txsoft[i]; 2107 2108 DPRINTF(WM_DEBUG_TX, 2109 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2110 2111 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2112 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2113 2114 status = 2115 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2116 if ((status & WTX_ST_DD) == 0) { 2117 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2118 BUS_DMASYNC_PREREAD); 2119 break; 2120 } 2121 2122 DPRINTF(WM_DEBUG_TX, 2123 ("%s: TX: job %d done: descs %d..%d\n", 2124 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2125 txs->txs_lastdesc)); 2126 2127 /* 2128 * XXX We should probably be using the statistics 2129 * XXX registers, but I don't know if they exist 2130 * XXX on chips before the i82544. 2131 */ 2132 2133 #ifdef WM_EVENT_COUNTERS 2134 if (status & WTX_ST_TU) 2135 WM_EVCNT_INCR(&sc->sc_ev_tu); 2136 #endif /* WM_EVENT_COUNTERS */ 2137 2138 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2139 ifp->if_oerrors++; 2140 if (status & WTX_ST_LC) 2141 log(LOG_WARNING, "%s: late collision\n", 2142 sc->sc_dev.dv_xname); 2143 else if (status & WTX_ST_EC) { 2144 ifp->if_collisions += 16; 2145 log(LOG_WARNING, "%s: excessive collisions\n", 2146 sc->sc_dev.dv_xname); 2147 } 2148 } else 2149 ifp->if_opackets++; 2150 2151 sc->sc_txfree += txs->txs_ndesc; 2152 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2153 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2154 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2155 m_freem(txs->txs_mbuf); 2156 txs->txs_mbuf = NULL; 2157 } 2158 2159 /* Update the dirty transmit buffer pointer. */ 2160 sc->sc_txsdirty = i; 2161 DPRINTF(WM_DEBUG_TX, 2162 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2163 2164 /* 2165 * If there are no more pending transmissions, cancel the watchdog 2166 * timer. 2167 */ 2168 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2169 ifp->if_timer = 0; 2170 } 2171 2172 /* 2173 * wm_rxintr: 2174 * 2175 * Helper; handle receive interrupts. 2176 */ 2177 static void 2178 wm_rxintr(struct wm_softc *sc) 2179 { 2180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2181 struct wm_rxsoft *rxs; 2182 struct mbuf *m; 2183 int i, len; 2184 uint8_t status, errors; 2185 2186 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2187 rxs = &sc->sc_rxsoft[i]; 2188 2189 DPRINTF(WM_DEBUG_RX, 2190 ("%s: RX: checking descriptor %d\n", 2191 sc->sc_dev.dv_xname, i)); 2192 2193 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2194 2195 status = sc->sc_rxdescs[i].wrx_status; 2196 errors = sc->sc_rxdescs[i].wrx_errors; 2197 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2198 2199 if ((status & WRX_ST_DD) == 0) { 2200 /* 2201 * We have processed all of the receive descriptors. 2202 */ 2203 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2204 break; 2205 } 2206 2207 if (__predict_false(sc->sc_rxdiscard)) { 2208 DPRINTF(WM_DEBUG_RX, 2209 ("%s: RX: discarding contents of descriptor %d\n", 2210 sc->sc_dev.dv_xname, i)); 2211 WM_INIT_RXDESC(sc, i); 2212 if (status & WRX_ST_EOP) { 2213 /* Reset our state. */ 2214 DPRINTF(WM_DEBUG_RX, 2215 ("%s: RX: resetting rxdiscard -> 0\n", 2216 sc->sc_dev.dv_xname)); 2217 sc->sc_rxdiscard = 0; 2218 } 2219 continue; 2220 } 2221 2222 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2223 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2224 2225 m = rxs->rxs_mbuf; 2226 2227 /* 2228 * Add a new receive buffer to the ring. 2229 */ 2230 if (wm_add_rxbuf(sc, i) != 0) { 2231 /* 2232 * Failed, throw away what we've done so 2233 * far, and discard the rest of the packet. 2234 */ 2235 ifp->if_ierrors++; 2236 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2237 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2238 WM_INIT_RXDESC(sc, i); 2239 if ((status & WRX_ST_EOP) == 0) 2240 sc->sc_rxdiscard = 1; 2241 if (sc->sc_rxhead != NULL) 2242 m_freem(sc->sc_rxhead); 2243 WM_RXCHAIN_RESET(sc); 2244 DPRINTF(WM_DEBUG_RX, 2245 ("%s: RX: Rx buffer allocation failed, " 2246 "dropping packet%s\n", sc->sc_dev.dv_xname, 2247 sc->sc_rxdiscard ? " (discard)" : "")); 2248 continue; 2249 } 2250 2251 WM_RXCHAIN_LINK(sc, m); 2252 2253 m->m_len = len; 2254 2255 DPRINTF(WM_DEBUG_RX, 2256 ("%s: RX: buffer at %p len %d\n", 2257 sc->sc_dev.dv_xname, m->m_data, len)); 2258 2259 /* 2260 * If this is not the end of the packet, keep 2261 * looking. 2262 */ 2263 if ((status & WRX_ST_EOP) == 0) { 2264 sc->sc_rxlen += len; 2265 DPRINTF(WM_DEBUG_RX, 2266 ("%s: RX: not yet EOP, rxlen -> %d\n", 2267 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2268 continue; 2269 } 2270 2271 /* 2272 * Okay, we have the entire packet now. The chip is 2273 * configured to include the FCS (not all chips can 2274 * be configured to strip it), so we need to trim it. 2275 */ 2276 m->m_len -= ETHER_CRC_LEN; 2277 2278 *sc->sc_rxtailp = NULL; 2279 len = m->m_len + sc->sc_rxlen; 2280 m = sc->sc_rxhead; 2281 2282 WM_RXCHAIN_RESET(sc); 2283 2284 DPRINTF(WM_DEBUG_RX, 2285 ("%s: RX: have entire packet, len -> %d\n", 2286 sc->sc_dev.dv_xname, len)); 2287 2288 /* 2289 * If an error occurred, update stats and drop the packet. 2290 */ 2291 if (errors & 2292 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2293 ifp->if_ierrors++; 2294 if (errors & WRX_ER_SE) 2295 log(LOG_WARNING, "%s: symbol error\n", 2296 sc->sc_dev.dv_xname); 2297 else if (errors & WRX_ER_SEQ) 2298 log(LOG_WARNING, "%s: receive sequence error\n", 2299 sc->sc_dev.dv_xname); 2300 else if (errors & WRX_ER_CE) 2301 log(LOG_WARNING, "%s: CRC error\n", 2302 sc->sc_dev.dv_xname); 2303 m_freem(m); 2304 continue; 2305 } 2306 2307 /* 2308 * No errors. Receive the packet. 2309 */ 2310 m->m_pkthdr.rcvif = ifp; 2311 m->m_pkthdr.len = len; 2312 2313 #if 0 /* XXXJRT */ 2314 /* 2315 * If VLANs are enabled, VLAN packets have been unwrapped 2316 * for us. Associate the tag with the packet. 2317 */ 2318 if ((status & WRX_ST_VP) != 0) { 2319 VLAN_INPUT_TAG(ifp, m, 2320 le16toh(sc->sc_rxdescs[i].wrx_special, 2321 continue); 2322 } 2323 #endif /* XXXJRT */ 2324 2325 /* 2326 * Set up checksum info for this packet. 2327 */ 2328 if ((status & WRX_ST_IXSM) == 0) { 2329 if (status & WRX_ST_IPCS) { 2330 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2331 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2332 if (errors & WRX_ER_IPE) 2333 m->m_pkthdr.csum_flags |= 2334 M_CSUM_IPv4_BAD; 2335 } 2336 if (status & WRX_ST_TCPCS) { 2337 /* 2338 * Note: we don't know if this was TCP or UDP, 2339 * so we just set both bits, and expect the 2340 * upper layers to deal. 2341 */ 2342 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2343 m->m_pkthdr.csum_flags |= 2344 M_CSUM_TCPv4|M_CSUM_UDPv4; 2345 if (errors & WRX_ER_TCPE) 2346 m->m_pkthdr.csum_flags |= 2347 M_CSUM_TCP_UDP_BAD; 2348 } 2349 } 2350 2351 ifp->if_ipackets++; 2352 2353 #if NBPFILTER > 0 2354 /* Pass this up to any BPF listeners. */ 2355 if (ifp->if_bpf) 2356 bpf_mtap(ifp->if_bpf, m); 2357 #endif /* NBPFILTER > 0 */ 2358 2359 /* Pass it on. */ 2360 (*ifp->if_input)(ifp, m); 2361 } 2362 2363 /* Update the receive pointer. */ 2364 sc->sc_rxptr = i; 2365 2366 DPRINTF(WM_DEBUG_RX, 2367 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2368 } 2369 2370 /* 2371 * wm_linkintr: 2372 * 2373 * Helper; handle link interrupts. 2374 */ 2375 static void 2376 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2377 { 2378 uint32_t status; 2379 2380 /* 2381 * If we get a link status interrupt on a 1000BASE-T 2382 * device, just fall into the normal MII tick path. 2383 */ 2384 if (sc->sc_flags & WM_F_HAS_MII) { 2385 if (icr & ICR_LSC) { 2386 DPRINTF(WM_DEBUG_LINK, 2387 ("%s: LINK: LSC -> mii_tick\n", 2388 sc->sc_dev.dv_xname)); 2389 mii_tick(&sc->sc_mii); 2390 } else if (icr & ICR_RXSEQ) { 2391 DPRINTF(WM_DEBUG_LINK, 2392 ("%s: LINK Receive sequence error\n", 2393 sc->sc_dev.dv_xname)); 2394 } 2395 return; 2396 } 2397 2398 /* 2399 * If we are now receiving /C/, check for link again in 2400 * a couple of link clock ticks. 2401 */ 2402 if (icr & ICR_RXCFG) { 2403 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2404 sc->sc_dev.dv_xname)); 2405 sc->sc_tbi_anstate = 2; 2406 } 2407 2408 if (icr & ICR_LSC) { 2409 status = CSR_READ(sc, WMREG_STATUS); 2410 if (status & STATUS_LU) { 2411 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2412 sc->sc_dev.dv_xname, 2413 (status & STATUS_FD) ? "FDX" : "HDX")); 2414 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2415 sc->sc_fcrtl &= ~FCRTL_XONE; 2416 if (status & STATUS_FD) 2417 sc->sc_tctl |= 2418 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2419 else 2420 sc->sc_tctl |= 2421 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2422 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2423 sc->sc_fcrtl |= FCRTL_XONE; 2424 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2425 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2426 WMREG_OLD_FCRTL : WMREG_FCRTL, 2427 sc->sc_fcrtl); 2428 sc->sc_tbi_linkup = 1; 2429 } else { 2430 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2431 sc->sc_dev.dv_xname)); 2432 sc->sc_tbi_linkup = 0; 2433 } 2434 sc->sc_tbi_anstate = 2; 2435 wm_tbi_set_linkled(sc); 2436 } else if (icr & ICR_RXSEQ) { 2437 DPRINTF(WM_DEBUG_LINK, 2438 ("%s: LINK: Receive sequence error\n", 2439 sc->sc_dev.dv_xname)); 2440 } 2441 } 2442 2443 /* 2444 * wm_tick: 2445 * 2446 * One second timer, used to check link status, sweep up 2447 * completed transmit jobs, etc. 2448 */ 2449 static void 2450 wm_tick(void *arg) 2451 { 2452 struct wm_softc *sc = arg; 2453 int s; 2454 2455 s = splnet(); 2456 2457 if (sc->sc_type >= WM_T_82542_2_1) { 2458 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2459 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2460 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2461 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2462 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2463 } 2464 2465 if (sc->sc_flags & WM_F_HAS_MII) 2466 mii_tick(&sc->sc_mii); 2467 else 2468 wm_tbi_check_link(sc); 2469 2470 splx(s); 2471 2472 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2473 } 2474 2475 /* 2476 * wm_reset: 2477 * 2478 * Reset the i82542 chip. 2479 */ 2480 static void 2481 wm_reset(struct wm_softc *sc) 2482 { 2483 int i; 2484 2485 /* 2486 * Allocate on-chip memory according to the MTU size. 2487 * The Packet Buffer Allocation register must be written 2488 * before the chip is reset. 2489 */ 2490 if (sc->sc_type < WM_T_82547) { 2491 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2492 PBA_40K : PBA_48K; 2493 } else { 2494 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2495 PBA_22K : PBA_30K; 2496 sc->sc_txfifo_head = 0; 2497 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2498 sc->sc_txfifo_size = 2499 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2500 sc->sc_txfifo_stall = 0; 2501 } 2502 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2503 2504 switch (sc->sc_type) { 2505 case WM_T_82544: 2506 case WM_T_82540: 2507 case WM_T_82545: 2508 case WM_T_82546: 2509 case WM_T_82541: 2510 case WM_T_82541_2: 2511 /* 2512 * On some chipsets, a reset through a memory-mapped write 2513 * cycle can cause the chip to reset before completing the 2514 * write cycle. This causes major headache that can be 2515 * avoided by issuing the reset via indirect register writes 2516 * through I/O space. 2517 * 2518 * So, if we successfully mapped the I/O BAR at attach time, 2519 * use that. Otherwise, try our luck with a memory-mapped 2520 * reset. 2521 */ 2522 if (sc->sc_flags & WM_F_IOH_VALID) 2523 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2524 else 2525 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2526 break; 2527 2528 case WM_T_82545_3: 2529 case WM_T_82546_3: 2530 /* Use the shadow control register on these chips. */ 2531 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2532 break; 2533 2534 default: 2535 /* Everything else can safely use the documented method. */ 2536 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2537 break; 2538 } 2539 delay(10000); 2540 2541 for (i = 0; i < 1000; i++) { 2542 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2543 return; 2544 delay(20); 2545 } 2546 2547 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2548 log(LOG_ERR, "%s: reset failed to complete\n", 2549 sc->sc_dev.dv_xname); 2550 } 2551 2552 /* 2553 * wm_init: [ifnet interface function] 2554 * 2555 * Initialize the interface. Must be called at splnet(). 2556 */ 2557 static int 2558 wm_init(struct ifnet *ifp) 2559 { 2560 struct wm_softc *sc = ifp->if_softc; 2561 struct wm_rxsoft *rxs; 2562 int i, error = 0; 2563 uint32_t reg; 2564 2565 /* 2566 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2567 * There is a small but measurable benefit to avoiding the adjusment 2568 * of the descriptor so that the headers are aligned, for normal mtu, 2569 * on such platforms. One possibility is that the DMA itself is 2570 * slightly more efficient if the front of the entire packet (instead 2571 * of the front of the headers) is aligned. 2572 * 2573 * Note we must always set align_tweak to 0 if we are using 2574 * jumbo frames. 2575 */ 2576 #ifdef __NO_STRICT_ALIGNMENT 2577 sc->sc_align_tweak = 0; 2578 #else 2579 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2580 sc->sc_align_tweak = 0; 2581 else 2582 sc->sc_align_tweak = 2; 2583 #endif /* __NO_STRICT_ALIGNMENT */ 2584 2585 /* Cancel any pending I/O. */ 2586 wm_stop(ifp, 0); 2587 2588 /* Reset the chip to a known state. */ 2589 wm_reset(sc); 2590 2591 /* Initialize the transmit descriptor ring. */ 2592 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2593 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2594 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2595 sc->sc_txfree = WM_NTXDESC(sc); 2596 sc->sc_txnext = 0; 2597 2598 if (sc->sc_type < WM_T_82543) { 2599 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2600 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2601 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2602 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2603 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2604 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2605 } else { 2606 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2607 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2608 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2609 CSR_WRITE(sc, WMREG_TDH, 0); 2610 CSR_WRITE(sc, WMREG_TDT, 0); 2611 CSR_WRITE(sc, WMREG_TIDV, 64); 2612 CSR_WRITE(sc, WMREG_TADV, 128); 2613 2614 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2615 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2616 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2617 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2618 } 2619 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2620 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2621 2622 /* Initialize the transmit job descriptors. */ 2623 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2624 sc->sc_txsoft[i].txs_mbuf = NULL; 2625 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2626 sc->sc_txsnext = 0; 2627 sc->sc_txsdirty = 0; 2628 2629 /* 2630 * Initialize the receive descriptor and receive job 2631 * descriptor rings. 2632 */ 2633 if (sc->sc_type < WM_T_82543) { 2634 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2635 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2636 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2637 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2638 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2639 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2640 2641 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2642 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2643 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2644 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2645 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2646 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2647 } else { 2648 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2649 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2650 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2651 CSR_WRITE(sc, WMREG_RDH, 0); 2652 CSR_WRITE(sc, WMREG_RDT, 0); 2653 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2654 CSR_WRITE(sc, WMREG_RADV, 128); 2655 } 2656 for (i = 0; i < WM_NRXDESC; i++) { 2657 rxs = &sc->sc_rxsoft[i]; 2658 if (rxs->rxs_mbuf == NULL) { 2659 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2660 log(LOG_ERR, "%s: unable to allocate or map rx " 2661 "buffer %d, error = %d\n", 2662 sc->sc_dev.dv_xname, i, error); 2663 /* 2664 * XXX Should attempt to run with fewer receive 2665 * XXX buffers instead of just failing. 2666 */ 2667 wm_rxdrain(sc); 2668 goto out; 2669 } 2670 } else 2671 WM_INIT_RXDESC(sc, i); 2672 } 2673 sc->sc_rxptr = 0; 2674 sc->sc_rxdiscard = 0; 2675 WM_RXCHAIN_RESET(sc); 2676 2677 /* 2678 * Clear out the VLAN table -- we don't use it (yet). 2679 */ 2680 CSR_WRITE(sc, WMREG_VET, 0); 2681 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2682 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2683 2684 /* 2685 * Set up flow-control parameters. 2686 * 2687 * XXX Values could probably stand some tuning. 2688 */ 2689 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2690 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2691 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2692 2693 sc->sc_fcrtl = FCRTL_DFLT; 2694 if (sc->sc_type < WM_T_82543) { 2695 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2696 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2697 } else { 2698 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2699 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2700 } 2701 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2702 2703 #if 0 /* XXXJRT */ 2704 /* Deal with VLAN enables. */ 2705 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2706 sc->sc_ctrl |= CTRL_VME; 2707 else 2708 #endif /* XXXJRT */ 2709 sc->sc_ctrl &= ~CTRL_VME; 2710 2711 /* Write the control registers. */ 2712 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2713 #if 0 2714 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2715 #endif 2716 2717 /* 2718 * Set up checksum offload parameters. 2719 */ 2720 reg = CSR_READ(sc, WMREG_RXCSUM); 2721 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2722 reg |= RXCSUM_IPOFL; 2723 else 2724 reg &= ~RXCSUM_IPOFL; 2725 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2726 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2727 else { 2728 reg &= ~RXCSUM_TUOFL; 2729 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2730 reg &= ~RXCSUM_IPOFL; 2731 } 2732 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2733 2734 /* 2735 * Set up the interrupt registers. 2736 */ 2737 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2738 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2739 ICR_RXO | ICR_RXT0; 2740 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2741 sc->sc_icr |= ICR_RXCFG; 2742 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2743 2744 /* Set up the inter-packet gap. */ 2745 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2746 2747 if (sc->sc_type >= WM_T_82543) { 2748 /* Set up the interrupt throttling register (units of 256ns) */ 2749 sc->sc_itr = 1000000000 / (7000 * 256); 2750 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2751 } 2752 2753 #if 0 /* XXXJRT */ 2754 /* Set the VLAN ethernetype. */ 2755 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2756 #endif 2757 2758 /* 2759 * Set up the transmit control register; we start out with 2760 * a collision distance suitable for FDX, but update it whe 2761 * we resolve the media type. 2762 */ 2763 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2764 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2765 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2766 2767 /* Set the media. */ 2768 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2769 2770 /* 2771 * Set up the receive control register; we actually program 2772 * the register when we set the receive filter. Use multicast 2773 * address offset type 0. 2774 * 2775 * Only the i82544 has the ability to strip the incoming 2776 * CRC, so we don't enable that feature. 2777 */ 2778 sc->sc_mchash_type = 0; 2779 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2780 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2781 2782 if(MCLBYTES == 2048) { 2783 sc->sc_rctl |= RCTL_2k; 2784 } else { 2785 if(sc->sc_type >= WM_T_82543) { 2786 switch(MCLBYTES) { 2787 case 4096: 2788 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2789 break; 2790 case 8192: 2791 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2792 break; 2793 case 16384: 2794 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2795 break; 2796 default: 2797 panic("wm_init: MCLBYTES %d unsupported", 2798 MCLBYTES); 2799 break; 2800 } 2801 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2802 } 2803 2804 /* Set the receive filter. */ 2805 wm_set_filter(sc); 2806 2807 /* Start the one second link check clock. */ 2808 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2809 2810 /* ...all done! */ 2811 ifp->if_flags |= IFF_RUNNING; 2812 ifp->if_flags &= ~IFF_OACTIVE; 2813 2814 out: 2815 if (error) 2816 log(LOG_ERR, "%s: interface not running\n", 2817 sc->sc_dev.dv_xname); 2818 return (error); 2819 } 2820 2821 /* 2822 * wm_rxdrain: 2823 * 2824 * Drain the receive queue. 2825 */ 2826 static void 2827 wm_rxdrain(struct wm_softc *sc) 2828 { 2829 struct wm_rxsoft *rxs; 2830 int i; 2831 2832 for (i = 0; i < WM_NRXDESC; i++) { 2833 rxs = &sc->sc_rxsoft[i]; 2834 if (rxs->rxs_mbuf != NULL) { 2835 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2836 m_freem(rxs->rxs_mbuf); 2837 rxs->rxs_mbuf = NULL; 2838 } 2839 } 2840 } 2841 2842 /* 2843 * wm_stop: [ifnet interface function] 2844 * 2845 * Stop transmission on the interface. 2846 */ 2847 static void 2848 wm_stop(struct ifnet *ifp, int disable) 2849 { 2850 struct wm_softc *sc = ifp->if_softc; 2851 struct wm_txsoft *txs; 2852 int i; 2853 2854 /* Stop the one second clock. */ 2855 callout_stop(&sc->sc_tick_ch); 2856 2857 /* Stop the 82547 Tx FIFO stall check timer. */ 2858 if (sc->sc_type == WM_T_82547) 2859 callout_stop(&sc->sc_txfifo_ch); 2860 2861 if (sc->sc_flags & WM_F_HAS_MII) { 2862 /* Down the MII. */ 2863 mii_down(&sc->sc_mii); 2864 } 2865 2866 /* Stop the transmit and receive processes. */ 2867 CSR_WRITE(sc, WMREG_TCTL, 0); 2868 CSR_WRITE(sc, WMREG_RCTL, 0); 2869 2870 /* 2871 * Clear the interrupt mask to ensure the device cannot assert its 2872 * interrupt line. 2873 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 2874 * any currently pending or shared interrupt. 2875 */ 2876 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2877 sc->sc_icr = 0; 2878 2879 /* Release any queued transmit buffers. */ 2880 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2881 txs = &sc->sc_txsoft[i]; 2882 if (txs->txs_mbuf != NULL) { 2883 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2884 m_freem(txs->txs_mbuf); 2885 txs->txs_mbuf = NULL; 2886 } 2887 } 2888 2889 if (disable) 2890 wm_rxdrain(sc); 2891 2892 /* Mark the interface as down and cancel the watchdog timer. */ 2893 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2894 ifp->if_timer = 0; 2895 } 2896 2897 /* 2898 * wm_acquire_eeprom: 2899 * 2900 * Perform the EEPROM handshake required on some chips. 2901 */ 2902 static int 2903 wm_acquire_eeprom(struct wm_softc *sc) 2904 { 2905 uint32_t reg; 2906 int x; 2907 2908 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2909 reg = CSR_READ(sc, WMREG_EECD); 2910 2911 /* Request EEPROM access. */ 2912 reg |= EECD_EE_REQ; 2913 CSR_WRITE(sc, WMREG_EECD, reg); 2914 2915 /* ..and wait for it to be granted. */ 2916 for (x = 0; x < 100; x++) { 2917 reg = CSR_READ(sc, WMREG_EECD); 2918 if (reg & EECD_EE_GNT) 2919 break; 2920 delay(5); 2921 } 2922 if ((reg & EECD_EE_GNT) == 0) { 2923 aprint_error("%s: could not acquire EEPROM GNT\n", 2924 sc->sc_dev.dv_xname); 2925 reg &= ~EECD_EE_REQ; 2926 CSR_WRITE(sc, WMREG_EECD, reg); 2927 return (1); 2928 } 2929 } 2930 2931 return (0); 2932 } 2933 2934 /* 2935 * wm_release_eeprom: 2936 * 2937 * Release the EEPROM mutex. 2938 */ 2939 static void 2940 wm_release_eeprom(struct wm_softc *sc) 2941 { 2942 uint32_t reg; 2943 2944 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2945 reg = CSR_READ(sc, WMREG_EECD); 2946 reg &= ~EECD_EE_REQ; 2947 CSR_WRITE(sc, WMREG_EECD, reg); 2948 } 2949 } 2950 2951 /* 2952 * wm_eeprom_sendbits: 2953 * 2954 * Send a series of bits to the EEPROM. 2955 */ 2956 static void 2957 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2958 { 2959 uint32_t reg; 2960 int x; 2961 2962 reg = CSR_READ(sc, WMREG_EECD); 2963 2964 for (x = nbits; x > 0; x--) { 2965 if (bits & (1U << (x - 1))) 2966 reg |= EECD_DI; 2967 else 2968 reg &= ~EECD_DI; 2969 CSR_WRITE(sc, WMREG_EECD, reg); 2970 delay(2); 2971 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2972 delay(2); 2973 CSR_WRITE(sc, WMREG_EECD, reg); 2974 delay(2); 2975 } 2976 } 2977 2978 /* 2979 * wm_eeprom_recvbits: 2980 * 2981 * Receive a series of bits from the EEPROM. 2982 */ 2983 static void 2984 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2985 { 2986 uint32_t reg, val; 2987 int x; 2988 2989 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2990 2991 val = 0; 2992 for (x = nbits; x > 0; x--) { 2993 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2994 delay(2); 2995 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2996 val |= (1U << (x - 1)); 2997 CSR_WRITE(sc, WMREG_EECD, reg); 2998 delay(2); 2999 } 3000 *valp = val; 3001 } 3002 3003 /* 3004 * wm_read_eeprom_uwire: 3005 * 3006 * Read a word from the EEPROM using the MicroWire protocol. 3007 */ 3008 static int 3009 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3010 { 3011 uint32_t reg, val; 3012 int i; 3013 3014 for (i = 0; i < wordcnt; i++) { 3015 /* Clear SK and DI. */ 3016 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3017 CSR_WRITE(sc, WMREG_EECD, reg); 3018 3019 /* Set CHIP SELECT. */ 3020 reg |= EECD_CS; 3021 CSR_WRITE(sc, WMREG_EECD, reg); 3022 delay(2); 3023 3024 /* Shift in the READ command. */ 3025 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3026 3027 /* Shift in address. */ 3028 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3029 3030 /* Shift out the data. */ 3031 wm_eeprom_recvbits(sc, &val, 16); 3032 data[i] = val & 0xffff; 3033 3034 /* Clear CHIP SELECT. */ 3035 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3036 CSR_WRITE(sc, WMREG_EECD, reg); 3037 delay(2); 3038 } 3039 3040 return (0); 3041 } 3042 3043 /* 3044 * wm_spi_eeprom_ready: 3045 * 3046 * Wait for a SPI EEPROM to be ready for commands. 3047 */ 3048 static int 3049 wm_spi_eeprom_ready(struct wm_softc *sc) 3050 { 3051 uint32_t val; 3052 int usec; 3053 3054 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3055 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3056 wm_eeprom_recvbits(sc, &val, 8); 3057 if ((val & SPI_SR_RDY) == 0) 3058 break; 3059 } 3060 if (usec >= SPI_MAX_RETRIES) { 3061 aprint_error("%s: EEPROM failed to become ready\n", 3062 sc->sc_dev.dv_xname); 3063 return (1); 3064 } 3065 return (0); 3066 } 3067 3068 /* 3069 * wm_read_eeprom_spi: 3070 * 3071 * Read a work from the EEPROM using the SPI protocol. 3072 */ 3073 static int 3074 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3075 { 3076 uint32_t reg, val; 3077 int i; 3078 uint8_t opc; 3079 3080 /* Clear SK and CS. */ 3081 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3082 CSR_WRITE(sc, WMREG_EECD, reg); 3083 delay(2); 3084 3085 if (wm_spi_eeprom_ready(sc)) 3086 return (1); 3087 3088 /* Toggle CS to flush commands. */ 3089 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3090 delay(2); 3091 CSR_WRITE(sc, WMREG_EECD, reg); 3092 delay(2); 3093 3094 opc = SPI_OPC_READ; 3095 if (sc->sc_ee_addrbits == 8 && word >= 128) 3096 opc |= SPI_OPC_A8; 3097 3098 wm_eeprom_sendbits(sc, opc, 8); 3099 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3100 3101 for (i = 0; i < wordcnt; i++) { 3102 wm_eeprom_recvbits(sc, &val, 16); 3103 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3104 } 3105 3106 /* Raise CS and clear SK. */ 3107 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3108 CSR_WRITE(sc, WMREG_EECD, reg); 3109 delay(2); 3110 3111 return (0); 3112 } 3113 3114 /* 3115 * wm_read_eeprom: 3116 * 3117 * Read data from the serial EEPROM. 3118 */ 3119 static int 3120 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3121 { 3122 int rv; 3123 3124 if (wm_acquire_eeprom(sc)) 3125 return (1); 3126 3127 if (sc->sc_flags & WM_F_EEPROM_SPI) 3128 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3129 else 3130 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3131 3132 wm_release_eeprom(sc); 3133 return (rv); 3134 } 3135 3136 /* 3137 * wm_add_rxbuf: 3138 * 3139 * Add a receive buffer to the indiciated descriptor. 3140 */ 3141 static int 3142 wm_add_rxbuf(struct wm_softc *sc, int idx) 3143 { 3144 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3145 struct mbuf *m; 3146 int error; 3147 3148 MGETHDR(m, M_DONTWAIT, MT_DATA); 3149 if (m == NULL) 3150 return (ENOBUFS); 3151 3152 MCLGET(m, M_DONTWAIT); 3153 if ((m->m_flags & M_EXT) == 0) { 3154 m_freem(m); 3155 return (ENOBUFS); 3156 } 3157 3158 if (rxs->rxs_mbuf != NULL) 3159 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3160 3161 rxs->rxs_mbuf = m; 3162 3163 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3164 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3165 BUS_DMA_READ|BUS_DMA_NOWAIT); 3166 if (error) { 3167 /* XXX XXX XXX */ 3168 printf("%s: unable to load rx DMA map %d, error = %d\n", 3169 sc->sc_dev.dv_xname, idx, error); 3170 panic("wm_add_rxbuf"); 3171 } 3172 3173 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3174 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3175 3176 WM_INIT_RXDESC(sc, idx); 3177 3178 return (0); 3179 } 3180 3181 /* 3182 * wm_set_ral: 3183 * 3184 * Set an entery in the receive address list. 3185 */ 3186 static void 3187 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3188 { 3189 uint32_t ral_lo, ral_hi; 3190 3191 if (enaddr != NULL) { 3192 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3193 (enaddr[3] << 24); 3194 ral_hi = enaddr[4] | (enaddr[5] << 8); 3195 ral_hi |= RAL_AV; 3196 } else { 3197 ral_lo = 0; 3198 ral_hi = 0; 3199 } 3200 3201 if (sc->sc_type >= WM_T_82544) { 3202 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3203 ral_lo); 3204 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3205 ral_hi); 3206 } else { 3207 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3208 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3209 } 3210 } 3211 3212 /* 3213 * wm_mchash: 3214 * 3215 * Compute the hash of the multicast address for the 4096-bit 3216 * multicast filter. 3217 */ 3218 static uint32_t 3219 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3220 { 3221 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3222 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3223 uint32_t hash; 3224 3225 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3226 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3227 3228 return (hash & 0xfff); 3229 } 3230 3231 /* 3232 * wm_set_filter: 3233 * 3234 * Set up the receive filter. 3235 */ 3236 static void 3237 wm_set_filter(struct wm_softc *sc) 3238 { 3239 struct ethercom *ec = &sc->sc_ethercom; 3240 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3241 struct ether_multi *enm; 3242 struct ether_multistep step; 3243 bus_addr_t mta_reg; 3244 uint32_t hash, reg, bit; 3245 int i; 3246 3247 if (sc->sc_type >= WM_T_82544) 3248 mta_reg = WMREG_CORDOVA_MTA; 3249 else 3250 mta_reg = WMREG_MTA; 3251 3252 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3253 3254 if (ifp->if_flags & IFF_BROADCAST) 3255 sc->sc_rctl |= RCTL_BAM; 3256 if (ifp->if_flags & IFF_PROMISC) { 3257 sc->sc_rctl |= RCTL_UPE; 3258 goto allmulti; 3259 } 3260 3261 /* 3262 * Set the station address in the first RAL slot, and 3263 * clear the remaining slots. 3264 */ 3265 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3266 for (i = 1; i < WM_RAL_TABSIZE; i++) 3267 wm_set_ral(sc, NULL, i); 3268 3269 /* Clear out the multicast table. */ 3270 for (i = 0; i < WM_MC_TABSIZE; i++) 3271 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3272 3273 ETHER_FIRST_MULTI(step, ec, enm); 3274 while (enm != NULL) { 3275 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3276 /* 3277 * We must listen to a range of multicast addresses. 3278 * For now, just accept all multicasts, rather than 3279 * trying to set only those filter bits needed to match 3280 * the range. (At this time, the only use of address 3281 * ranges is for IP multicast routing, for which the 3282 * range is big enough to require all bits set.) 3283 */ 3284 goto allmulti; 3285 } 3286 3287 hash = wm_mchash(sc, enm->enm_addrlo); 3288 3289 reg = (hash >> 5) & 0x7f; 3290 bit = hash & 0x1f; 3291 3292 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3293 hash |= 1U << bit; 3294 3295 /* XXX Hardware bug?? */ 3296 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3297 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3298 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3299 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3300 } else 3301 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3302 3303 ETHER_NEXT_MULTI(step, enm); 3304 } 3305 3306 ifp->if_flags &= ~IFF_ALLMULTI; 3307 goto setit; 3308 3309 allmulti: 3310 ifp->if_flags |= IFF_ALLMULTI; 3311 sc->sc_rctl |= RCTL_MPE; 3312 3313 setit: 3314 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3315 } 3316 3317 /* 3318 * wm_tbi_mediainit: 3319 * 3320 * Initialize media for use on 1000BASE-X devices. 3321 */ 3322 static void 3323 wm_tbi_mediainit(struct wm_softc *sc) 3324 { 3325 const char *sep = ""; 3326 3327 if (sc->sc_type < WM_T_82543) 3328 sc->sc_tipg = TIPG_WM_DFLT; 3329 else 3330 sc->sc_tipg = TIPG_LG_DFLT; 3331 3332 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3333 wm_tbi_mediastatus); 3334 3335 /* 3336 * SWD Pins: 3337 * 3338 * 0 = Link LED (output) 3339 * 1 = Loss Of Signal (input) 3340 */ 3341 sc->sc_ctrl |= CTRL_SWDPIO(0); 3342 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3343 3344 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3345 3346 #define ADD(ss, mm, dd) \ 3347 do { \ 3348 aprint_normal("%s%s", sep, ss); \ 3349 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3350 sep = ", "; \ 3351 } while (/*CONSTCOND*/0) 3352 3353 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3354 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3355 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3356 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3357 aprint_normal("\n"); 3358 3359 #undef ADD 3360 3361 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3362 } 3363 3364 /* 3365 * wm_tbi_mediastatus: [ifmedia interface function] 3366 * 3367 * Get the current interface media status on a 1000BASE-X device. 3368 */ 3369 static void 3370 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3371 { 3372 struct wm_softc *sc = ifp->if_softc; 3373 uint32_t ctrl; 3374 3375 ifmr->ifm_status = IFM_AVALID; 3376 ifmr->ifm_active = IFM_ETHER; 3377 3378 if (sc->sc_tbi_linkup == 0) { 3379 ifmr->ifm_active |= IFM_NONE; 3380 return; 3381 } 3382 3383 ifmr->ifm_status |= IFM_ACTIVE; 3384 ifmr->ifm_active |= IFM_1000_SX; 3385 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3386 ifmr->ifm_active |= IFM_FDX; 3387 ctrl = CSR_READ(sc, WMREG_CTRL); 3388 if (ctrl & CTRL_RFCE) 3389 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3390 if (ctrl & CTRL_TFCE) 3391 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3392 } 3393 3394 /* 3395 * wm_tbi_mediachange: [ifmedia interface function] 3396 * 3397 * Set hardware to newly-selected media on a 1000BASE-X device. 3398 */ 3399 static int 3400 wm_tbi_mediachange(struct ifnet *ifp) 3401 { 3402 struct wm_softc *sc = ifp->if_softc; 3403 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3404 uint32_t status; 3405 int i; 3406 3407 sc->sc_txcw = ife->ifm_data; 3408 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3409 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3410 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3411 sc->sc_txcw |= TXCW_ANE; 3412 3413 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3414 delay(10000); 3415 3416 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3417 3418 sc->sc_tbi_anstate = 0; 3419 3420 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3421 /* Have signal; wait for the link to come up. */ 3422 for (i = 0; i < 50; i++) { 3423 delay(10000); 3424 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3425 break; 3426 } 3427 3428 status = CSR_READ(sc, WMREG_STATUS); 3429 if (status & STATUS_LU) { 3430 /* Link is up. */ 3431 DPRINTF(WM_DEBUG_LINK, 3432 ("%s: LINK: set media -> link up %s\n", 3433 sc->sc_dev.dv_xname, 3434 (status & STATUS_FD) ? "FDX" : "HDX")); 3435 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3436 sc->sc_fcrtl &= ~FCRTL_XONE; 3437 if (status & STATUS_FD) 3438 sc->sc_tctl |= 3439 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3440 else 3441 sc->sc_tctl |= 3442 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3443 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3444 sc->sc_fcrtl |= FCRTL_XONE; 3445 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3446 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3447 WMREG_OLD_FCRTL : WMREG_FCRTL, 3448 sc->sc_fcrtl); 3449 sc->sc_tbi_linkup = 1; 3450 } else { 3451 /* Link is down. */ 3452 DPRINTF(WM_DEBUG_LINK, 3453 ("%s: LINK: set media -> link down\n", 3454 sc->sc_dev.dv_xname)); 3455 sc->sc_tbi_linkup = 0; 3456 } 3457 } else { 3458 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3459 sc->sc_dev.dv_xname)); 3460 sc->sc_tbi_linkup = 0; 3461 } 3462 3463 wm_tbi_set_linkled(sc); 3464 3465 return (0); 3466 } 3467 3468 /* 3469 * wm_tbi_set_linkled: 3470 * 3471 * Update the link LED on 1000BASE-X devices. 3472 */ 3473 static void 3474 wm_tbi_set_linkled(struct wm_softc *sc) 3475 { 3476 3477 if (sc->sc_tbi_linkup) 3478 sc->sc_ctrl |= CTRL_SWDPIN(0); 3479 else 3480 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3481 3482 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3483 } 3484 3485 /* 3486 * wm_tbi_check_link: 3487 * 3488 * Check the link on 1000BASE-X devices. 3489 */ 3490 static void 3491 wm_tbi_check_link(struct wm_softc *sc) 3492 { 3493 uint32_t rxcw, ctrl, status; 3494 3495 if (sc->sc_tbi_anstate == 0) 3496 return; 3497 else if (sc->sc_tbi_anstate > 1) { 3498 DPRINTF(WM_DEBUG_LINK, 3499 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3500 sc->sc_tbi_anstate)); 3501 sc->sc_tbi_anstate--; 3502 return; 3503 } 3504 3505 sc->sc_tbi_anstate = 0; 3506 3507 rxcw = CSR_READ(sc, WMREG_RXCW); 3508 ctrl = CSR_READ(sc, WMREG_CTRL); 3509 status = CSR_READ(sc, WMREG_STATUS); 3510 3511 if ((status & STATUS_LU) == 0) { 3512 DPRINTF(WM_DEBUG_LINK, 3513 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3514 sc->sc_tbi_linkup = 0; 3515 } else { 3516 DPRINTF(WM_DEBUG_LINK, 3517 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3518 (status & STATUS_FD) ? "FDX" : "HDX")); 3519 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3520 sc->sc_fcrtl &= ~FCRTL_XONE; 3521 if (status & STATUS_FD) 3522 sc->sc_tctl |= 3523 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3524 else 3525 sc->sc_tctl |= 3526 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3527 if (ctrl & CTRL_TFCE) 3528 sc->sc_fcrtl |= FCRTL_XONE; 3529 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3530 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3531 WMREG_OLD_FCRTL : WMREG_FCRTL, 3532 sc->sc_fcrtl); 3533 sc->sc_tbi_linkup = 1; 3534 } 3535 3536 wm_tbi_set_linkled(sc); 3537 } 3538 3539 /* 3540 * wm_gmii_reset: 3541 * 3542 * Reset the PHY. 3543 */ 3544 static void 3545 wm_gmii_reset(struct wm_softc *sc) 3546 { 3547 uint32_t reg; 3548 3549 if (sc->sc_type >= WM_T_82544) { 3550 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3551 delay(20000); 3552 3553 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3554 delay(20000); 3555 } else { 3556 /* The PHY reset pin is active-low. */ 3557 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3558 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3559 CTRL_EXT_SWDPIN(4)); 3560 reg |= CTRL_EXT_SWDPIO(4); 3561 3562 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3563 delay(10); 3564 3565 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3566 delay(10); 3567 3568 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3569 delay(10); 3570 #if 0 3571 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3572 #endif 3573 } 3574 } 3575 3576 /* 3577 * wm_gmii_mediainit: 3578 * 3579 * Initialize media for use on 1000BASE-T devices. 3580 */ 3581 static void 3582 wm_gmii_mediainit(struct wm_softc *sc) 3583 { 3584 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3585 3586 /* We have MII. */ 3587 sc->sc_flags |= WM_F_HAS_MII; 3588 3589 sc->sc_tipg = TIPG_1000T_DFLT; 3590 3591 /* 3592 * Let the chip set speed/duplex on its own based on 3593 * signals from the PHY. 3594 */ 3595 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3596 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3597 3598 /* Initialize our media structures and probe the GMII. */ 3599 sc->sc_mii.mii_ifp = ifp; 3600 3601 if (sc->sc_type >= WM_T_82544) { 3602 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3603 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3604 } else { 3605 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3606 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3607 } 3608 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3609 3610 wm_gmii_reset(sc); 3611 3612 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3613 wm_gmii_mediastatus); 3614 3615 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3616 MII_OFFSET_ANY, MIIF_DOPAUSE); 3617 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3618 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3619 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3620 } else 3621 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3622 } 3623 3624 /* 3625 * wm_gmii_mediastatus: [ifmedia interface function] 3626 * 3627 * Get the current interface media status on a 1000BASE-T device. 3628 */ 3629 static void 3630 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3631 { 3632 struct wm_softc *sc = ifp->if_softc; 3633 3634 mii_pollstat(&sc->sc_mii); 3635 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3636 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3637 sc->sc_flowflags; 3638 } 3639 3640 /* 3641 * wm_gmii_mediachange: [ifmedia interface function] 3642 * 3643 * Set hardware to newly-selected media on a 1000BASE-T device. 3644 */ 3645 static int 3646 wm_gmii_mediachange(struct ifnet *ifp) 3647 { 3648 struct wm_softc *sc = ifp->if_softc; 3649 3650 if (ifp->if_flags & IFF_UP) 3651 mii_mediachg(&sc->sc_mii); 3652 return (0); 3653 } 3654 3655 #define MDI_IO CTRL_SWDPIN(2) 3656 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3657 #define MDI_CLK CTRL_SWDPIN(3) 3658 3659 static void 3660 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3661 { 3662 uint32_t i, v; 3663 3664 v = CSR_READ(sc, WMREG_CTRL); 3665 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3666 v |= MDI_DIR | CTRL_SWDPIO(3); 3667 3668 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3669 if (data & i) 3670 v |= MDI_IO; 3671 else 3672 v &= ~MDI_IO; 3673 CSR_WRITE(sc, WMREG_CTRL, v); 3674 delay(10); 3675 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3676 delay(10); 3677 CSR_WRITE(sc, WMREG_CTRL, v); 3678 delay(10); 3679 } 3680 } 3681 3682 static uint32_t 3683 i82543_mii_recvbits(struct wm_softc *sc) 3684 { 3685 uint32_t v, i, data = 0; 3686 3687 v = CSR_READ(sc, WMREG_CTRL); 3688 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3689 v |= CTRL_SWDPIO(3); 3690 3691 CSR_WRITE(sc, WMREG_CTRL, v); 3692 delay(10); 3693 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3694 delay(10); 3695 CSR_WRITE(sc, WMREG_CTRL, v); 3696 delay(10); 3697 3698 for (i = 0; i < 16; i++) { 3699 data <<= 1; 3700 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3701 delay(10); 3702 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3703 data |= 1; 3704 CSR_WRITE(sc, WMREG_CTRL, v); 3705 delay(10); 3706 } 3707 3708 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3709 delay(10); 3710 CSR_WRITE(sc, WMREG_CTRL, v); 3711 delay(10); 3712 3713 return (data); 3714 } 3715 3716 #undef MDI_IO 3717 #undef MDI_DIR 3718 #undef MDI_CLK 3719 3720 /* 3721 * wm_gmii_i82543_readreg: [mii interface function] 3722 * 3723 * Read a PHY register on the GMII (i82543 version). 3724 */ 3725 static int 3726 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3727 { 3728 struct wm_softc *sc = (void *) self; 3729 int rv; 3730 3731 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3732 i82543_mii_sendbits(sc, reg | (phy << 5) | 3733 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3734 rv = i82543_mii_recvbits(sc) & 0xffff; 3735 3736 DPRINTF(WM_DEBUG_GMII, 3737 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3738 sc->sc_dev.dv_xname, phy, reg, rv)); 3739 3740 return (rv); 3741 } 3742 3743 /* 3744 * wm_gmii_i82543_writereg: [mii interface function] 3745 * 3746 * Write a PHY register on the GMII (i82543 version). 3747 */ 3748 static void 3749 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3750 { 3751 struct wm_softc *sc = (void *) self; 3752 3753 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3754 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3755 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3756 (MII_COMMAND_START << 30), 32); 3757 } 3758 3759 /* 3760 * wm_gmii_i82544_readreg: [mii interface function] 3761 * 3762 * Read a PHY register on the GMII. 3763 */ 3764 static int 3765 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3766 { 3767 struct wm_softc *sc = (void *) self; 3768 uint32_t mdic = 0; 3769 int i, rv; 3770 3771 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3772 MDIC_REGADD(reg)); 3773 3774 for (i = 0; i < 100; i++) { 3775 mdic = CSR_READ(sc, WMREG_MDIC); 3776 if (mdic & MDIC_READY) 3777 break; 3778 delay(10); 3779 } 3780 3781 if ((mdic & MDIC_READY) == 0) { 3782 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3783 sc->sc_dev.dv_xname, phy, reg); 3784 rv = 0; 3785 } else if (mdic & MDIC_E) { 3786 #if 0 /* This is normal if no PHY is present. */ 3787 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3788 sc->sc_dev.dv_xname, phy, reg); 3789 #endif 3790 rv = 0; 3791 } else { 3792 rv = MDIC_DATA(mdic); 3793 if (rv == 0xffff) 3794 rv = 0; 3795 } 3796 3797 return (rv); 3798 } 3799 3800 /* 3801 * wm_gmii_i82544_writereg: [mii interface function] 3802 * 3803 * Write a PHY register on the GMII. 3804 */ 3805 static void 3806 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3807 { 3808 struct wm_softc *sc = (void *) self; 3809 uint32_t mdic = 0; 3810 int i; 3811 3812 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3813 MDIC_REGADD(reg) | MDIC_DATA(val)); 3814 3815 for (i = 0; i < 100; i++) { 3816 mdic = CSR_READ(sc, WMREG_MDIC); 3817 if (mdic & MDIC_READY) 3818 break; 3819 delay(10); 3820 } 3821 3822 if ((mdic & MDIC_READY) == 0) 3823 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3824 sc->sc_dev.dv_xname, phy, reg); 3825 else if (mdic & MDIC_E) 3826 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3827 sc->sc_dev.dv_xname, phy, reg); 3828 } 3829 3830 /* 3831 * wm_gmii_statchg: [mii interface function] 3832 * 3833 * Callback from MII layer when media changes. 3834 */ 3835 static void 3836 wm_gmii_statchg(struct device *self) 3837 { 3838 struct wm_softc *sc = (void *) self; 3839 struct mii_data *mii = &sc->sc_mii; 3840 3841 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3842 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3843 sc->sc_fcrtl &= ~FCRTL_XONE; 3844 3845 /* 3846 * Get flow control negotiation result. 3847 */ 3848 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3849 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3850 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3851 mii->mii_media_active &= ~IFM_ETH_FMASK; 3852 } 3853 3854 if (sc->sc_flowflags & IFM_FLOW) { 3855 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3856 sc->sc_ctrl |= CTRL_TFCE; 3857 sc->sc_fcrtl |= FCRTL_XONE; 3858 } 3859 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3860 sc->sc_ctrl |= CTRL_RFCE; 3861 } 3862 3863 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3864 DPRINTF(WM_DEBUG_LINK, 3865 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3866 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3867 } else { 3868 DPRINTF(WM_DEBUG_LINK, 3869 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3870 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3871 } 3872 3873 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3874 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3875 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3876 : WMREG_FCRTL, sc->sc_fcrtl); 3877 } 3878
Indexes created Tue Sep 23 20:09:58 GMT 2025