if_wm.c revision 1.112
1 /* $NetBSD: if_wm.c,v 1.112 2006/02/16 00:02:00 gavan Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.112 2006/02/16 00:02:00 gavan Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 #include <dev/pci/if_wmvar.h> 102 103 #ifdef WM_DEBUG 104 #define WM_DEBUG_LINK 0x01 105 #define WM_DEBUG_TX 0x02 106 #define WM_DEBUG_RX 0x04 107 #define WM_DEBUG_GMII 0x08 108 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 109 110 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 111 #else 112 #define DPRINTF(x, y) /* nothing */ 113 #endif /* WM_DEBUG */ 114 115 /* 116 * Transmit descriptor list size. Due to errata, we can only have 117 * 256 hardware descriptors in the ring on < 82544, but we use 4096 118 * on >= 82544. We tell the upper layers that they can queue a lot 119 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 120 * of them at a time. 121 * 122 * We allow up to 256 (!) DMA segments per packet. Pathological packet 123 * chains containing many small mbufs have been observed in zero-copy 124 * situations with jumbo frames. 125 */ 126 #define WM_NTXSEGS 256 127 #define WM_IFQUEUELEN 256 128 #define WM_TXQUEUELEN_MAX 64 129 #define WM_TXQUEUELEN_MAX_82547 16 130 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 131 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 132 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 133 #define WM_NTXDESC_82542 256 134 #define WM_NTXDESC_82544 4096 135 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 136 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 137 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 138 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 139 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 140 141 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 142 143 /* 144 * Receive descriptor list size. We have one Rx buffer for normal 145 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 146 * packet. We allocate 256 receive descriptors, each with a 2k 147 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 148 */ 149 #define WM_NRXDESC 256 150 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 151 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 152 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 153 154 /* 155 * Control structures are DMA'd to the i82542 chip. We allocate them in 156 * a single clump that maps to a single DMA segment to make several things 157 * easier. 158 */ 159 struct wm_control_data_82544 { 160 /* 161 * The receive descriptors. 162 */ 163 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 164 165 /* 166 * The transmit descriptors. Put these at the end, because 167 * we might use a smaller number of them. 168 */ 169 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 170 }; 171 172 struct wm_control_data_82542 { 173 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 174 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 175 }; 176 177 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 178 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 179 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 180 181 /* 182 * Software state for transmit jobs. 183 */ 184 struct wm_txsoft { 185 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 186 bus_dmamap_t txs_dmamap; /* our DMA map */ 187 int txs_firstdesc; /* first descriptor in packet */ 188 int txs_lastdesc; /* last descriptor in packet */ 189 int txs_ndesc; /* # of descriptors used */ 190 }; 191 192 /* 193 * Software state for receive buffers. Each descriptor gets a 194 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 195 * more than one buffer, we chain them together. 196 */ 197 struct wm_rxsoft { 198 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t rxs_dmamap; /* our DMA map */ 200 }; 201 202 typedef enum { 203 WM_T_unknown = 0, 204 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 205 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 206 WM_T_82543, /* i82543 */ 207 WM_T_82544, /* i82544 */ 208 WM_T_82540, /* i82540 */ 209 WM_T_82545, /* i82545 */ 210 WM_T_82545_3, /* i82545 3.0+ */ 211 WM_T_82546, /* i82546 */ 212 WM_T_82546_3, /* i82546 3.0+ */ 213 WM_T_82541, /* i82541 */ 214 WM_T_82541_2, /* i82541 2.0+ */ 215 WM_T_82547, /* i82547 */ 216 WM_T_82547_2, /* i82547 2.0+ */ 217 } wm_chip_type; 218 219 /* 220 * Software state per device. 221 */ 222 struct wm_softc { 223 struct device sc_dev; /* generic device information */ 224 bus_space_tag_t sc_st; /* bus space tag */ 225 bus_space_handle_t sc_sh; /* bus space handle */ 226 bus_space_tag_t sc_iot; /* I/O space tag */ 227 bus_space_handle_t sc_ioh; /* I/O space handle */ 228 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 229 struct ethercom sc_ethercom; /* ethernet common data */ 230 void *sc_sdhook; /* shutdown hook */ 231 232 wm_chip_type sc_type; /* chip type */ 233 int sc_flags; /* flags; see below */ 234 int sc_bus_speed; /* PCI/PCIX bus speed */ 235 int sc_pcix_offset; /* PCIX capability register offset */ 236 int sc_flowflags; /* 802.3x flow control flags */ 237 238 void *sc_ih; /* interrupt cookie */ 239 240 int sc_ee_addrbits; /* EEPROM address bits */ 241 242 struct mii_data sc_mii; /* MII/media information */ 243 244 struct callout sc_tick_ch; /* tick callout */ 245 246 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 247 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 248 249 int sc_align_tweak; 250 251 /* 252 * Software state for the transmit and receive descriptors. 253 */ 254 int sc_txnum; /* must be a power of two */ 255 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 256 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 257 258 /* 259 * Control data structures. 260 */ 261 int sc_ntxdesc; /* must be a power of two */ 262 struct wm_control_data_82544 *sc_control_data; 263 #define sc_txdescs sc_control_data->wcd_txdescs 264 #define sc_rxdescs sc_control_data->wcd_rxdescs 265 266 #ifdef WM_EVENT_COUNTERS 267 /* Event counters. */ 268 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 269 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 270 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 271 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 272 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 273 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 274 struct evcnt sc_ev_linkintr; /* Link interrupts */ 275 276 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 277 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 278 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 279 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 280 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 281 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 282 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 283 284 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 285 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 286 287 struct evcnt sc_ev_tu; /* Tx underrun */ 288 289 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 290 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 291 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 292 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 293 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 294 #endif /* WM_EVENT_COUNTERS */ 295 296 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 297 298 int sc_txfree; /* number of free Tx descriptors */ 299 int sc_txnext; /* next ready Tx descriptor */ 300 301 int sc_txsfree; /* number of free Tx jobs */ 302 int sc_txsnext; /* next free Tx job */ 303 int sc_txsdirty; /* dirty Tx jobs */ 304 305 /* These 5 variables are used only on the 82547. */ 306 int sc_txfifo_size; /* Tx FIFO size */ 307 int sc_txfifo_head; /* current head of FIFO */ 308 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 309 int sc_txfifo_stall; /* Tx FIFO is stalled */ 310 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 311 312 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 313 314 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 315 int sc_rxdiscard; 316 int sc_rxlen; 317 struct mbuf *sc_rxhead; 318 struct mbuf *sc_rxtail; 319 struct mbuf **sc_rxtailp; 320 321 uint32_t sc_ctrl; /* prototype CTRL register */ 322 #if 0 323 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 324 #endif 325 uint32_t sc_icr; /* prototype interrupt bits */ 326 uint32_t sc_itr; /* prototype intr throttling reg */ 327 uint32_t sc_tctl; /* prototype TCTL register */ 328 uint32_t sc_rctl; /* prototype RCTL register */ 329 uint32_t sc_txcw; /* prototype TXCW register */ 330 uint32_t sc_tipg; /* prototype TIPG register */ 331 uint32_t sc_fcrtl; /* prototype FCRTL register */ 332 uint32_t sc_pba; /* prototype PBA register */ 333 334 int sc_tbi_linkup; /* TBI link status */ 335 int sc_tbi_anstate; /* autonegotiation state */ 336 337 int sc_mchash_type; /* multicast filter offset */ 338 339 #if NRND > 0 340 rndsource_element_t rnd_source; /* random source */ 341 #endif 342 }; 343 344 #define WM_RXCHAIN_RESET(sc) \ 345 do { \ 346 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 347 *(sc)->sc_rxtailp = NULL; \ 348 (sc)->sc_rxlen = 0; \ 349 } while (/*CONSTCOND*/0) 350 351 #define WM_RXCHAIN_LINK(sc, m) \ 352 do { \ 353 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 354 (sc)->sc_rxtailp = &(m)->m_next; \ 355 } while (/*CONSTCOND*/0) 356 357 /* sc_flags */ 358 #define WM_F_HAS_MII 0x01 /* has MII */ 359 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 360 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 361 #define WM_F_EEPROM_MD 0x08 /* EEPROM not present, use MD hook */ 362 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 363 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 364 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 365 #define WM_F_CSA 0x80 /* bus is CSA */ 366 367 #ifdef WM_EVENT_COUNTERS 368 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 369 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 370 #else 371 #define WM_EVCNT_INCR(ev) /* nothing */ 372 #define WM_EVCNT_ADD(ev, val) /* nothing */ 373 #endif 374 375 #define CSR_READ(sc, reg) \ 376 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 377 #define CSR_WRITE(sc, reg, val) \ 378 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 379 #define CSR_WRITE_FLUSH(sc) \ 380 (void) CSR_READ((sc), WMREG_STATUS) 381 382 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 383 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 384 385 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 386 #define WM_CDTXADDR_HI(sc, x) \ 387 (sizeof(bus_addr_t) == 8 ? \ 388 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 389 390 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 391 #define WM_CDRXADDR_HI(sc, x) \ 392 (sizeof(bus_addr_t) == 8 ? \ 393 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 394 395 #define WM_CDTXSYNC(sc, x, n, ops) \ 396 do { \ 397 int __x, __n; \ 398 \ 399 __x = (x); \ 400 __n = (n); \ 401 \ 402 /* If it will wrap around, sync to the end of the ring. */ \ 403 if ((__x + __n) > WM_NTXDESC(sc)) { \ 404 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 405 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 406 (WM_NTXDESC(sc) - __x), (ops)); \ 407 __n -= (WM_NTXDESC(sc) - __x); \ 408 __x = 0; \ 409 } \ 410 \ 411 /* Now sync whatever is left. */ \ 412 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 413 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 414 } while (/*CONSTCOND*/0) 415 416 #define WM_CDRXSYNC(sc, x, ops) \ 417 do { \ 418 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 419 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 420 } while (/*CONSTCOND*/0) 421 422 #define WM_INIT_RXDESC(sc, x) \ 423 do { \ 424 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 425 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 426 struct mbuf *__m = __rxs->rxs_mbuf; \ 427 \ 428 /* \ 429 * Note: We scoot the packet forward 2 bytes in the buffer \ 430 * so that the payload after the Ethernet header is aligned \ 431 * to a 4-byte boundary. \ 432 * \ 433 * XXX BRAINDAMAGE ALERT! \ 434 * The stupid chip uses the same size for every buffer, which \ 435 * is set in the Receive Control register. We are using the 2K \ 436 * size option, but what we REALLY want is (2K - 2)! For this \ 437 * reason, we can't "scoot" packets longer than the standard \ 438 * Ethernet MTU. On strict-alignment platforms, if the total \ 439 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 440 * the upper layer copy the headers. \ 441 */ \ 442 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 443 \ 444 wm_set_dma_addr(&__rxd->wrx_addr, \ 445 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 446 __rxd->wrx_len = 0; \ 447 __rxd->wrx_cksum = 0; \ 448 __rxd->wrx_status = 0; \ 449 __rxd->wrx_errors = 0; \ 450 __rxd->wrx_special = 0; \ 451 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 452 \ 453 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 454 } while (/*CONSTCOND*/0) 455 456 static void wm_start(struct ifnet *); 457 static void wm_watchdog(struct ifnet *); 458 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 459 static int wm_init(struct ifnet *); 460 static void wm_stop(struct ifnet *, int); 461 462 static void wm_shutdown(void *); 463 464 static void wm_reset(struct wm_softc *); 465 static void wm_rxdrain(struct wm_softc *); 466 static int wm_add_rxbuf(struct wm_softc *, int); 467 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 468 static int wm_validate_eeprom_checksum(struct wm_softc *); 469 static void wm_tick(void *); 470 #ifdef __HAVE_WM_READ_EEPROM_HOOK 471 extern int wm_read_eeprom_hook(int, int, u_int16_t *); 472 #endif 473 474 static void wm_set_filter(struct wm_softc *); 475 476 static int wm_intr(void *); 477 static void wm_txintr(struct wm_softc *); 478 static void wm_rxintr(struct wm_softc *); 479 static void wm_linkintr(struct wm_softc *, uint32_t); 480 481 static void wm_tbi_mediainit(struct wm_softc *); 482 static int wm_tbi_mediachange(struct ifnet *); 483 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 484 485 static void wm_tbi_set_linkled(struct wm_softc *); 486 static void wm_tbi_check_link(struct wm_softc *); 487 488 static void wm_gmii_reset(struct wm_softc *); 489 490 static int wm_gmii_i82543_readreg(struct device *, int, int); 491 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 492 493 static int wm_gmii_i82544_readreg(struct device *, int, int); 494 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 495 496 static void wm_gmii_statchg(struct device *); 497 498 static void wm_gmii_mediainit(struct wm_softc *); 499 static int wm_gmii_mediachange(struct ifnet *); 500 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 501 502 static int wm_match(struct device *, struct cfdata *, void *); 503 static void wm_attach(struct device *, struct device *, void *); 504 505 CFATTACH_DECL(wm, sizeof(struct wm_softc), 506 wm_match, wm_attach, NULL, NULL); 507 508 static void wm_82547_txfifo_stall(void *); 509 510 /* 511 * Devices supported by this driver. 512 */ 513 static const struct wm_product { 514 pci_vendor_id_t wmp_vendor; 515 pci_product_id_t wmp_product; 516 const char *wmp_name; 517 wm_chip_type wmp_type; 518 int wmp_flags; 519 #define WMP_F_1000X 0x01 520 #define WMP_F_1000T 0x02 521 } wm_products[] = { 522 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 523 "Intel i82542 1000BASE-X Ethernet", 524 WM_T_82542_2_1, WMP_F_1000X }, 525 526 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 527 "Intel i82543GC 1000BASE-X Ethernet", 528 WM_T_82543, WMP_F_1000X }, 529 530 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 531 "Intel i82543GC 1000BASE-T Ethernet", 532 WM_T_82543, WMP_F_1000T }, 533 534 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 535 "Intel i82544EI 1000BASE-T Ethernet", 536 WM_T_82544, WMP_F_1000T }, 537 538 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 539 "Intel i82544EI 1000BASE-X Ethernet", 540 WM_T_82544, WMP_F_1000X }, 541 542 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 543 "Intel i82544GC 1000BASE-T Ethernet", 544 WM_T_82544, WMP_F_1000T }, 545 546 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 547 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 548 WM_T_82544, WMP_F_1000T }, 549 550 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 551 "Intel i82540EM 1000BASE-T Ethernet", 552 WM_T_82540, WMP_F_1000T }, 553 554 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 555 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 556 WM_T_82540, WMP_F_1000T }, 557 558 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 559 "Intel i82540EP 1000BASE-T Ethernet", 560 WM_T_82540, WMP_F_1000T }, 561 562 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 563 "Intel i82540EP 1000BASE-T Ethernet", 564 WM_T_82540, WMP_F_1000T }, 565 566 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 567 "Intel i82540EP 1000BASE-T Ethernet", 568 WM_T_82540, WMP_F_1000T }, 569 570 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 571 "Intel i82545EM 1000BASE-T Ethernet", 572 WM_T_82545, WMP_F_1000T }, 573 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 575 "Intel i82545GM 1000BASE-T Ethernet", 576 WM_T_82545_3, WMP_F_1000T }, 577 578 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 579 "Intel i82545GM 1000BASE-X Ethernet", 580 WM_T_82545_3, WMP_F_1000X }, 581 #if 0 582 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 583 "Intel i82545GM Gigabit Ethernet (SERDES)", 584 WM_T_82545_3, WMP_F_SERDES }, 585 #endif 586 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 587 "Intel i82546EB 1000BASE-T Ethernet", 588 WM_T_82546, WMP_F_1000T }, 589 590 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 591 "Intel i82546EB 1000BASE-T Ethernet", 592 WM_T_82546, WMP_F_1000T }, 593 594 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 595 "Intel i82545EM 1000BASE-X Ethernet", 596 WM_T_82545, WMP_F_1000X }, 597 598 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 599 "Intel i82546EB 1000BASE-X Ethernet", 600 WM_T_82546, WMP_F_1000X }, 601 602 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 603 "Intel i82546GB 1000BASE-T Ethernet", 604 WM_T_82546_3, WMP_F_1000T }, 605 606 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 607 "Intel i82546GB 1000BASE-X Ethernet", 608 WM_T_82546_3, WMP_F_1000X }, 609 #if 0 610 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 611 "Intel i82546GB Gigabit Ethernet (SERDES)", 612 WM_T_82546_3, WMP_F_SERDES }, 613 #endif 614 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 615 "Intel i82541EI 1000BASE-T Ethernet", 616 WM_T_82541, WMP_F_1000T }, 617 618 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 619 "Intel i82541EI Mobile 1000BASE-T Ethernet", 620 WM_T_82541, WMP_F_1000T }, 621 622 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 623 "Intel i82541ER 1000BASE-T Ethernet", 624 WM_T_82541_2, WMP_F_1000T }, 625 626 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 627 "Intel i82541GI 1000BASE-T Ethernet", 628 WM_T_82541_2, WMP_F_1000T }, 629 630 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 631 "Intel i82541GI Mobile 1000BASE-T Ethernet", 632 WM_T_82541_2, WMP_F_1000T }, 633 634 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 635 "Intel i82541PI 1000BASE-T Ethernet", 636 WM_T_82541_2, WMP_F_1000T }, 637 638 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 639 "Intel i82547EI 1000BASE-T Ethernet", 640 WM_T_82547, WMP_F_1000T }, 641 642 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 643 "Intel i82547GI 1000BASE-T Ethernet", 644 WM_T_82547_2, WMP_F_1000T }, 645 { 0, 0, 646 NULL, 647 0, 0 }, 648 }; 649 650 #ifdef WM_EVENT_COUNTERS 651 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 652 #endif /* WM_EVENT_COUNTERS */ 653 654 #if 0 /* Not currently used */ 655 static inline uint32_t 656 wm_io_read(struct wm_softc *sc, int reg) 657 { 658 659 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 660 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 661 } 662 #endif 663 664 static inline void 665 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 666 { 667 668 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 669 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 670 } 671 672 static inline void 673 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 674 { 675 wa->wa_low = htole32(v & 0xffffffffU); 676 if (sizeof(bus_addr_t) == 8) 677 wa->wa_high = htole32((uint64_t) v >> 32); 678 else 679 wa->wa_high = 0; 680 } 681 682 static const struct wm_product * 683 wm_lookup(const struct pci_attach_args *pa) 684 { 685 const struct wm_product *wmp; 686 687 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 688 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 689 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 690 return (wmp); 691 } 692 return (NULL); 693 } 694 695 static int 696 wm_match(struct device *parent, struct cfdata *cf, void *aux) 697 { 698 struct pci_attach_args *pa = aux; 699 700 if (wm_lookup(pa) != NULL) 701 return (1); 702 703 return (0); 704 } 705 706 static void 707 wm_attach(struct device *parent, struct device *self, void *aux) 708 { 709 struct wm_softc *sc = (void *) self; 710 struct pci_attach_args *pa = aux; 711 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 712 pci_chipset_tag_t pc = pa->pa_pc; 713 pci_intr_handle_t ih; 714 size_t cdata_size; 715 const char *intrstr = NULL; 716 const char *eetype; 717 bus_space_tag_t memt; 718 bus_space_handle_t memh; 719 bus_dma_segment_t seg; 720 int memh_valid; 721 int i, rseg, error; 722 const struct wm_product *wmp; 723 uint8_t enaddr[ETHER_ADDR_LEN]; 724 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 725 pcireg_t preg, memtype; 726 uint32_t reg; 727 int pmreg; 728 729 callout_init(&sc->sc_tick_ch); 730 731 wmp = wm_lookup(pa); 732 if (wmp == NULL) { 733 printf("\n"); 734 panic("wm_attach: impossible"); 735 } 736 737 if (pci_dma64_available(pa)) 738 sc->sc_dmat = pa->pa_dmat64; 739 else 740 sc->sc_dmat = pa->pa_dmat; 741 742 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 743 aprint_naive(": Ethernet controller\n"); 744 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 745 746 sc->sc_type = wmp->wmp_type; 747 if (sc->sc_type < WM_T_82543) { 748 if (preg < 2) { 749 aprint_error("%s: i82542 must be at least rev. 2\n", 750 sc->sc_dev.dv_xname); 751 return; 752 } 753 if (preg < 3) 754 sc->sc_type = WM_T_82542_2_0; 755 } 756 757 /* 758 * Map the device. All devices support memory-mapped acccess, 759 * and it is really required for normal operation. 760 */ 761 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 762 switch (memtype) { 763 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 764 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 765 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 766 memtype, 0, &memt, &memh, NULL, NULL) == 0); 767 break; 768 default: 769 memh_valid = 0; 770 } 771 772 if (memh_valid) { 773 sc->sc_st = memt; 774 sc->sc_sh = memh; 775 } else { 776 aprint_error("%s: unable to map device registers\n", 777 sc->sc_dev.dv_xname); 778 return; 779 } 780 781 /* 782 * In addition, i82544 and later support I/O mapped indirect 783 * register access. It is not desirable (nor supported in 784 * this driver) to use it for normal operation, though it is 785 * required to work around bugs in some chip versions. 786 */ 787 if (sc->sc_type >= WM_T_82544) { 788 /* First we have to find the I/O BAR. */ 789 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 790 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 791 PCI_MAPREG_TYPE_IO) 792 break; 793 } 794 if (i == PCI_MAPREG_END) 795 aprint_error("%s: WARNING: unable to find I/O BAR\n", 796 sc->sc_dev.dv_xname); 797 else { 798 /* 799 * The i8254x doesn't apparently respond when the 800 * I/O BAR is 0, which looks somewhat like it's not 801 * been configured. 802 */ 803 preg = pci_conf_read(pc, pa->pa_tag, i); 804 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 805 aprint_error("%s: WARNING: I/O BAR at zero.\n", 806 sc->sc_dev.dv_xname); 807 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 808 0, &sc->sc_iot, &sc->sc_ioh, 809 NULL, NULL) == 0) { 810 sc->sc_flags |= WM_F_IOH_VALID; 811 } else { 812 aprint_error("%s: WARNING: unable to map " 813 "I/O space\n", sc->sc_dev.dv_xname); 814 } 815 } 816 817 } 818 819 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 820 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 821 preg |= PCI_COMMAND_MASTER_ENABLE; 822 if (sc->sc_type < WM_T_82542_2_1) 823 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 824 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 825 826 /* Get it out of power save mode, if needed. */ 827 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 828 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 829 PCI_PMCSR_STATE_MASK; 830 if (preg == PCI_PMCSR_STATE_D3) { 831 /* 832 * The card has lost all configuration data in 833 * this state, so punt. 834 */ 835 aprint_error("%s: unable to wake from power state D3\n", 836 sc->sc_dev.dv_xname); 837 return; 838 } 839 if (preg != PCI_PMCSR_STATE_D0) { 840 aprint_normal("%s: waking up from power state D%d\n", 841 sc->sc_dev.dv_xname, preg); 842 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 843 PCI_PMCSR_STATE_D0); 844 } 845 } 846 847 /* 848 * Map and establish our interrupt. 849 */ 850 if (pci_intr_map(pa, &ih)) { 851 aprint_error("%s: unable to map interrupt\n", 852 sc->sc_dev.dv_xname); 853 return; 854 } 855 intrstr = pci_intr_string(pc, ih); 856 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 857 if (sc->sc_ih == NULL) { 858 aprint_error("%s: unable to establish interrupt", 859 sc->sc_dev.dv_xname); 860 if (intrstr != NULL) 861 aprint_normal(" at %s", intrstr); 862 aprint_normal("\n"); 863 return; 864 } 865 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 866 867 /* 868 * Determine a few things about the bus we're connected to. 869 */ 870 if (sc->sc_type < WM_T_82543) { 871 /* We don't really know the bus characteristics here. */ 872 sc->sc_bus_speed = 33; 873 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 874 /* 875 * CSA (Communication Streaming Architecture) is about as fast 876 * a 32-bit 66MHz PCI Bus. 877 */ 878 sc->sc_flags |= WM_F_CSA; 879 sc->sc_bus_speed = 66; 880 aprint_verbose("%s: Communication Streaming Architecture\n", 881 sc->sc_dev.dv_xname); 882 if (sc->sc_type == WM_T_82547) { 883 callout_init(&sc->sc_txfifo_ch); 884 callout_setfunc(&sc->sc_txfifo_ch, 885 wm_82547_txfifo_stall, sc); 886 aprint_verbose("%s: using 82547 Tx FIFO stall " 887 "work-around\n", sc->sc_dev.dv_xname); 888 } 889 } else { 890 reg = CSR_READ(sc, WMREG_STATUS); 891 if (reg & STATUS_BUS64) 892 sc->sc_flags |= WM_F_BUS64; 893 if (sc->sc_type >= WM_T_82544 && 894 (reg & STATUS_PCIX_MODE) != 0) { 895 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 896 897 sc->sc_flags |= WM_F_PCIX; 898 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 899 PCI_CAP_PCIX, 900 &sc->sc_pcix_offset, NULL) == 0) 901 aprint_error("%s: unable to find PCIX " 902 "capability\n", sc->sc_dev.dv_xname); 903 else if (sc->sc_type != WM_T_82545_3 && 904 sc->sc_type != WM_T_82546_3) { 905 /* 906 * Work around a problem caused by the BIOS 907 * setting the max memory read byte count 908 * incorrectly. 909 */ 910 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 911 sc->sc_pcix_offset + PCI_PCIX_CMD); 912 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 913 sc->sc_pcix_offset + PCI_PCIX_STATUS); 914 915 bytecnt = 916 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 917 PCI_PCIX_CMD_BYTECNT_SHIFT; 918 maxb = 919 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 920 PCI_PCIX_STATUS_MAXB_SHIFT; 921 if (bytecnt > maxb) { 922 aprint_verbose("%s: resetting PCI-X " 923 "MMRBC: %d -> %d\n", 924 sc->sc_dev.dv_xname, 925 512 << bytecnt, 512 << maxb); 926 pcix_cmd = (pcix_cmd & 927 ~PCI_PCIX_CMD_BYTECNT_MASK) | 928 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 929 pci_conf_write(pa->pa_pc, pa->pa_tag, 930 sc->sc_pcix_offset + PCI_PCIX_CMD, 931 pcix_cmd); 932 } 933 } 934 } 935 /* 936 * The quad port adapter is special; it has a PCIX-PCIX 937 * bridge on the board, and can run the secondary bus at 938 * a higher speed. 939 */ 940 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 941 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 942 : 66; 943 } else if (sc->sc_flags & WM_F_PCIX) { 944 switch (reg & STATUS_PCIXSPD_MASK) { 945 case STATUS_PCIXSPD_50_66: 946 sc->sc_bus_speed = 66; 947 break; 948 case STATUS_PCIXSPD_66_100: 949 sc->sc_bus_speed = 100; 950 break; 951 case STATUS_PCIXSPD_100_133: 952 sc->sc_bus_speed = 133; 953 break; 954 default: 955 aprint_error( 956 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 957 sc->sc_dev.dv_xname, 958 reg & STATUS_PCIXSPD_MASK); 959 sc->sc_bus_speed = 66; 960 } 961 } else 962 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 963 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 964 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 965 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 966 } 967 968 /* 969 * Allocate the control data structures, and create and load the 970 * DMA map for it. 971 * 972 * NOTE: All Tx descriptors must be in the same 4G segment of 973 * memory. So must Rx descriptors. We simplify by allocating 974 * both sets within the same 4G segment. 975 */ 976 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 977 WM_NTXDESC_82542 : WM_NTXDESC_82544; 978 cdata_size = sc->sc_type < WM_T_82544 ? 979 sizeof(struct wm_control_data_82542) : 980 sizeof(struct wm_control_data_82544); 981 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 982 (bus_size_t) 0x100000000ULL, 983 &seg, 1, &rseg, 0)) != 0) { 984 aprint_error( 985 "%s: unable to allocate control data, error = %d\n", 986 sc->sc_dev.dv_xname, error); 987 goto fail_0; 988 } 989 990 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 991 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 992 aprint_error("%s: unable to map control data, error = %d\n", 993 sc->sc_dev.dv_xname, error); 994 goto fail_1; 995 } 996 997 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 998 0, 0, &sc->sc_cddmamap)) != 0) { 999 aprint_error("%s: unable to create control data DMA map, " 1000 "error = %d\n", sc->sc_dev.dv_xname, error); 1001 goto fail_2; 1002 } 1003 1004 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1005 sc->sc_control_data, cdata_size, NULL, 1006 0)) != 0) { 1007 aprint_error( 1008 "%s: unable to load control data DMA map, error = %d\n", 1009 sc->sc_dev.dv_xname, error); 1010 goto fail_3; 1011 } 1012 1013 1014 /* 1015 * Create the transmit buffer DMA maps. 1016 */ 1017 WM_TXQUEUELEN(sc) = 1018 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1019 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1020 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1021 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1022 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1023 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1024 aprint_error("%s: unable to create Tx DMA map %d, " 1025 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1026 goto fail_4; 1027 } 1028 } 1029 1030 /* 1031 * Create the receive buffer DMA maps. 1032 */ 1033 for (i = 0; i < WM_NRXDESC; i++) { 1034 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1035 MCLBYTES, 0, 0, 1036 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1037 aprint_error("%s: unable to create Rx DMA map %d, " 1038 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1039 goto fail_5; 1040 } 1041 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1042 } 1043 1044 /* 1045 * Reset the chip to a known state. 1046 */ 1047 wm_reset(sc); 1048 1049 /* 1050 * Get some information about the EEPROM. 1051 */ 1052 if (sc->sc_type >= WM_T_82540) 1053 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1054 if (sc->sc_type <= WM_T_82544) 1055 sc->sc_ee_addrbits = 6; 1056 else if (sc->sc_type <= WM_T_82546_3) { 1057 reg = CSR_READ(sc, WMREG_EECD); 1058 if (reg & EECD_EE_SIZE) 1059 sc->sc_ee_addrbits = 8; 1060 else 1061 sc->sc_ee_addrbits = 6; 1062 } else if (sc->sc_type <= WM_T_82547_2) { 1063 reg = CSR_READ(sc, WMREG_EECD); 1064 if (reg & EECD_EE_TYPE) { 1065 sc->sc_flags |= WM_F_EEPROM_SPI; 1066 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1067 } else 1068 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1069 } else { 1070 /* Assume everything else is SPI. */ 1071 reg = CSR_READ(sc, WMREG_EECD); 1072 sc->sc_flags |= WM_F_EEPROM_SPI; 1073 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1074 } 1075 1076 /* 1077 * Defer printing the EEPROM type until after verifying the checksum 1078 * This allows the EEPROM type to be printed correctly in the case 1079 * that no EEPROM is attached. 1080 */ 1081 1082 1083 /* 1084 * Validate the EEPROM checksum. If the checksum fails: 1085 * 1086 * If __HAVE_WM_READ_EEPROM_HOOK, we defer to the device-specific 1087 * hook for EEPROM reads. Otherwise we have run out of options, 1088 * so bail. 1089 */ 1090 if (wm_validate_eeprom_checksum(sc)) { 1091 #ifdef __HAVE_WM_READ_EEPROM_HOOK 1092 sc->sc_flags |= WM_F_EEPROM_MD; 1093 #else 1094 aprint_error("%s: EEPROM failed checksum\n", 1095 sc->sc_dev.dv_xname); 1096 return; 1097 #endif 1098 } 1099 1100 /* 1101 * Read the Ethernet address from the EEPROM. 1102 */ 1103 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1104 sizeof(myea) / sizeof(myea[0]), myea)) { 1105 aprint_error("%s: unable to read Ethernet address\n", 1106 sc->sc_dev.dv_xname); 1107 return; 1108 } 1109 1110 if (sc->sc_flags & WM_F_EEPROM_MD) 1111 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname); 1112 else { 1113 if (sc->sc_flags & WM_F_EEPROM_SPI) 1114 eetype = "SPI"; 1115 else 1116 eetype = "MicroWire"; 1117 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1118 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1119 sc->sc_ee_addrbits, eetype); 1120 } 1121 1122 enaddr[0] = myea[0] & 0xff; 1123 enaddr[1] = myea[0] >> 8; 1124 enaddr[2] = myea[1] & 0xff; 1125 enaddr[3] = myea[1] >> 8; 1126 enaddr[4] = myea[2] & 0xff; 1127 enaddr[5] = myea[2] >> 8; 1128 1129 /* 1130 * Toggle the LSB of the MAC address on the second port 1131 * of the i82546. 1132 */ 1133 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1134 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1135 enaddr[5] ^= 1; 1136 } 1137 1138 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1139 ether_sprintf(enaddr)); 1140 1141 /* 1142 * Read the config info from the EEPROM, and set up various 1143 * bits in the control registers based on their contents. 1144 */ 1145 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1146 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1147 sc->sc_dev.dv_xname); 1148 return; 1149 } 1150 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1151 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1152 sc->sc_dev.dv_xname); 1153 return; 1154 } 1155 if (sc->sc_type >= WM_T_82544) { 1156 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1157 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1158 sc->sc_dev.dv_xname); 1159 return; 1160 } 1161 } 1162 1163 if (cfg1 & EEPROM_CFG1_ILOS) 1164 sc->sc_ctrl |= CTRL_ILOS; 1165 if (sc->sc_type >= WM_T_82544) { 1166 sc->sc_ctrl |= 1167 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1168 CTRL_SWDPIO_SHIFT; 1169 sc->sc_ctrl |= 1170 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1171 CTRL_SWDPINS_SHIFT; 1172 } else { 1173 sc->sc_ctrl |= 1174 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1175 CTRL_SWDPIO_SHIFT; 1176 } 1177 1178 #if 0 1179 if (sc->sc_type >= WM_T_82544) { 1180 if (cfg1 & EEPROM_CFG1_IPS0) 1181 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1182 if (cfg1 & EEPROM_CFG1_IPS1) 1183 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1184 sc->sc_ctrl_ext |= 1185 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1186 CTRL_EXT_SWDPIO_SHIFT; 1187 sc->sc_ctrl_ext |= 1188 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1189 CTRL_EXT_SWDPINS_SHIFT; 1190 } else { 1191 sc->sc_ctrl_ext |= 1192 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1193 CTRL_EXT_SWDPIO_SHIFT; 1194 } 1195 #endif 1196 1197 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1198 #if 0 1199 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1200 #endif 1201 1202 /* 1203 * Set up some register offsets that are different between 1204 * the i82542 and the i82543 and later chips. 1205 */ 1206 if (sc->sc_type < WM_T_82543) { 1207 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1208 sc->sc_tdt_reg = WMREG_OLD_TDT; 1209 } else { 1210 sc->sc_rdt_reg = WMREG_RDT; 1211 sc->sc_tdt_reg = WMREG_TDT; 1212 } 1213 1214 /* 1215 * Determine if we're TBI or GMII mode, and initialize the 1216 * media structures accordingly. 1217 */ 1218 if (sc->sc_type < WM_T_82543 || 1219 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1220 if (wmp->wmp_flags & WMP_F_1000T) 1221 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1222 "product!\n", sc->sc_dev.dv_xname); 1223 wm_tbi_mediainit(sc); 1224 } else { 1225 if (wmp->wmp_flags & WMP_F_1000X) 1226 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1227 "product!\n", sc->sc_dev.dv_xname); 1228 wm_gmii_mediainit(sc); 1229 } 1230 1231 ifp = &sc->sc_ethercom.ec_if; 1232 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1233 ifp->if_softc = sc; 1234 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1235 ifp->if_ioctl = wm_ioctl; 1236 ifp->if_start = wm_start; 1237 ifp->if_watchdog = wm_watchdog; 1238 ifp->if_init = wm_init; 1239 ifp->if_stop = wm_stop; 1240 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1241 IFQ_SET_READY(&ifp->if_snd); 1242 1243 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1244 1245 /* 1246 * If we're a i82543 or greater, we can support VLANs. 1247 */ 1248 if (sc->sc_type >= WM_T_82543) 1249 sc->sc_ethercom.ec_capabilities |= 1250 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1251 1252 /* 1253 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1254 * on i82543 and later. 1255 */ 1256 if (sc->sc_type >= WM_T_82543) 1257 ifp->if_capabilities |= 1258 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1259 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1260 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1261 IFCAP_CSUM_TCPv6_Tx | 1262 IFCAP_CSUM_UDPv6_Tx; 1263 1264 /* 1265 * If we're a i82544 or greater (except i82547), we can do 1266 * TCP segmentation offload. 1267 */ 1268 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1269 ifp->if_capabilities |= IFCAP_TSOv4; 1270 1271 /* 1272 * Attach the interface. 1273 */ 1274 if_attach(ifp); 1275 ether_ifattach(ifp, enaddr); 1276 #if NRND > 0 1277 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1278 RND_TYPE_NET, 0); 1279 #endif 1280 1281 #ifdef WM_EVENT_COUNTERS 1282 /* Attach event counters. */ 1283 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1284 NULL, sc->sc_dev.dv_xname, "txsstall"); 1285 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "txdstall"); 1287 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1289 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1290 NULL, sc->sc_dev.dv_xname, "txdw"); 1291 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1292 NULL, sc->sc_dev.dv_xname, "txqe"); 1293 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1294 NULL, sc->sc_dev.dv_xname, "rxintr"); 1295 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1296 NULL, sc->sc_dev.dv_xname, "linkintr"); 1297 1298 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1299 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1300 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1301 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1302 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1303 NULL, sc->sc_dev.dv_xname, "txipsum"); 1304 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1305 NULL, sc->sc_dev.dv_xname, "txtusum"); 1306 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1307 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1308 1309 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1310 NULL, sc->sc_dev.dv_xname, "txtso"); 1311 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1312 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1313 1314 for (i = 0; i < WM_NTXSEGS; i++) { 1315 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1316 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1317 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1318 } 1319 1320 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1321 NULL, sc->sc_dev.dv_xname, "txdrop"); 1322 1323 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1324 NULL, sc->sc_dev.dv_xname, "tu"); 1325 1326 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1327 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1328 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1329 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1330 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1331 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1332 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1333 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1334 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1335 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1336 #endif /* WM_EVENT_COUNTERS */ 1337 1338 /* 1339 * Make sure the interface is shutdown during reboot. 1340 */ 1341 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1342 if (sc->sc_sdhook == NULL) 1343 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1344 sc->sc_dev.dv_xname); 1345 return; 1346 1347 /* 1348 * Free any resources we've allocated during the failed attach 1349 * attempt. Do this in reverse order and fall through. 1350 */ 1351 fail_5: 1352 for (i = 0; i < WM_NRXDESC; i++) { 1353 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1354 bus_dmamap_destroy(sc->sc_dmat, 1355 sc->sc_rxsoft[i].rxs_dmamap); 1356 } 1357 fail_4: 1358 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1359 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1360 bus_dmamap_destroy(sc->sc_dmat, 1361 sc->sc_txsoft[i].txs_dmamap); 1362 } 1363 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1364 fail_3: 1365 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1366 fail_2: 1367 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1368 cdata_size); 1369 fail_1: 1370 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1371 fail_0: 1372 return; 1373 } 1374 1375 /* 1376 * wm_shutdown: 1377 * 1378 * Make sure the interface is stopped at reboot time. 1379 */ 1380 static void 1381 wm_shutdown(void *arg) 1382 { 1383 struct wm_softc *sc = arg; 1384 1385 wm_stop(&sc->sc_ethercom.ec_if, 1); 1386 } 1387 1388 /* 1389 * wm_tx_offload: 1390 * 1391 * Set up TCP/IP checksumming parameters for the 1392 * specified packet. 1393 */ 1394 static int 1395 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1396 uint8_t *fieldsp) 1397 { 1398 struct mbuf *m0 = txs->txs_mbuf; 1399 struct livengood_tcpip_ctxdesc *t; 1400 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1401 struct ether_header *eh; 1402 int offset, iphl; 1403 uint8_t fields; 1404 1405 /* 1406 * XXX It would be nice if the mbuf pkthdr had offset 1407 * fields for the protocol headers. 1408 */ 1409 1410 eh = mtod(m0, struct ether_header *); 1411 switch (htons(eh->ether_type)) { 1412 case ETHERTYPE_IP: 1413 case ETHERTYPE_IPV6: 1414 offset = ETHER_HDR_LEN; 1415 break; 1416 1417 case ETHERTYPE_VLAN: 1418 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1419 break; 1420 1421 default: 1422 /* 1423 * Don't support this protocol or encapsulation. 1424 */ 1425 *fieldsp = 0; 1426 *cmdp = 0; 1427 return (0); 1428 } 1429 1430 if ((m0->m_pkthdr.csum_flags & 1431 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1432 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1433 } else { 1434 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1435 } 1436 1437 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1438 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1439 seg = 0; 1440 fields = 0; 1441 1442 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1443 int hlen = offset + iphl; 1444 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1445 if (__predict_false(m0->m_len < 1446 (hlen + sizeof(struct tcphdr)))) { 1447 /* 1448 * TCP/IP headers are not in the first mbuf; we need 1449 * to do this the slow and painful way. Let's just 1450 * hope this doesn't happen very often. 1451 */ 1452 struct ip ip; 1453 struct tcphdr th; 1454 1455 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1456 1457 m_copydata(m0, offset, sizeof(ip), &ip); 1458 m_copydata(m0, hlen, sizeof(th), &th); 1459 1460 ip.ip_len = 0; 1461 1462 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1463 sizeof(ip.ip_len), &ip.ip_len); 1464 1465 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1466 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1467 1468 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1469 sizeof(th.th_sum), &th.th_sum); 1470 1471 hlen += th.th_off << 2; 1472 } else { 1473 /* 1474 * TCP/IP headers are in the first mbuf; we can do 1475 * this the easy way. 1476 */ 1477 struct ip *ip = 1478 (struct ip *) (mtod(m0, caddr_t) + offset); 1479 struct tcphdr *th = 1480 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1481 1482 ip->ip_len = 0; 1483 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1484 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1485 1486 hlen += th->th_off << 2; 1487 } 1488 1489 cmd |= WTX_TCPIP_CMD_TSE; 1490 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1491 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1492 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1493 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1494 } 1495 1496 /* 1497 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1498 * offload feature, if we load the context descriptor, we 1499 * MUST provide valid values for IPCSS and TUCSS fields. 1500 */ 1501 1502 ipcs = WTX_TCPIP_IPCSS(offset) | 1503 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1504 WTX_TCPIP_IPCSE(offset + iphl - 1); 1505 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1506 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1507 fields |= WTX_IXSM; 1508 } 1509 1510 offset += iphl; 1511 1512 if (m0->m_pkthdr.csum_flags & 1513 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1514 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1515 fields |= WTX_TXSM; 1516 tucs = WTX_TCPIP_TUCSS(offset) | 1517 WTX_TCPIP_TUCSO(offset + 1518 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1519 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1520 } else if ((m0->m_pkthdr.csum_flags & 1521 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) { 1522 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1523 fields |= WTX_TXSM; 1524 tucs = WTX_TCPIP_TUCSS(offset) | 1525 WTX_TCPIP_TUCSO(offset + 1526 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1527 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1528 } else { 1529 /* Just initialize it to a valid TCP context. */ 1530 tucs = WTX_TCPIP_TUCSS(offset) | 1531 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1532 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1533 } 1534 1535 /* Fill in the context descriptor. */ 1536 t = (struct livengood_tcpip_ctxdesc *) 1537 &sc->sc_txdescs[sc->sc_txnext]; 1538 t->tcpip_ipcs = htole32(ipcs); 1539 t->tcpip_tucs = htole32(tucs); 1540 t->tcpip_cmdlen = htole32(cmdlen); 1541 t->tcpip_seg = htole32(seg); 1542 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1543 1544 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1545 txs->txs_ndesc++; 1546 1547 *cmdp = cmd; 1548 *fieldsp = fields; 1549 1550 return (0); 1551 } 1552 1553 static void 1554 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1555 { 1556 struct mbuf *m; 1557 int i; 1558 1559 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1560 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1561 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1562 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1563 m->m_data, m->m_len, m->m_flags); 1564 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1565 i, i == 1 ? "" : "s"); 1566 } 1567 1568 /* 1569 * wm_82547_txfifo_stall: 1570 * 1571 * Callout used to wait for the 82547 Tx FIFO to drain, 1572 * reset the FIFO pointers, and restart packet transmission. 1573 */ 1574 static void 1575 wm_82547_txfifo_stall(void *arg) 1576 { 1577 struct wm_softc *sc = arg; 1578 int s; 1579 1580 s = splnet(); 1581 1582 if (sc->sc_txfifo_stall) { 1583 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1584 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1585 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1586 /* 1587 * Packets have drained. Stop transmitter, reset 1588 * FIFO pointers, restart transmitter, and kick 1589 * the packet queue. 1590 */ 1591 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1592 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1593 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1594 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1595 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1596 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1597 CSR_WRITE(sc, WMREG_TCTL, tctl); 1598 CSR_WRITE_FLUSH(sc); 1599 1600 sc->sc_txfifo_head = 0; 1601 sc->sc_txfifo_stall = 0; 1602 wm_start(&sc->sc_ethercom.ec_if); 1603 } else { 1604 /* 1605 * Still waiting for packets to drain; try again in 1606 * another tick. 1607 */ 1608 callout_schedule(&sc->sc_txfifo_ch, 1); 1609 } 1610 } 1611 1612 splx(s); 1613 } 1614 1615 /* 1616 * wm_82547_txfifo_bugchk: 1617 * 1618 * Check for bug condition in the 82547 Tx FIFO. We need to 1619 * prevent enqueueing a packet that would wrap around the end 1620 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1621 * 1622 * We do this by checking the amount of space before the end 1623 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1624 * the Tx FIFO, wait for all remaining packets to drain, reset 1625 * the internal FIFO pointers to the beginning, and restart 1626 * transmission on the interface. 1627 */ 1628 #define WM_FIFO_HDR 0x10 1629 #define WM_82547_PAD_LEN 0x3e0 1630 static int 1631 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1632 { 1633 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1634 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1635 1636 /* Just return if already stalled. */ 1637 if (sc->sc_txfifo_stall) 1638 return (1); 1639 1640 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1641 /* Stall only occurs in half-duplex mode. */ 1642 goto send_packet; 1643 } 1644 1645 if (len >= WM_82547_PAD_LEN + space) { 1646 sc->sc_txfifo_stall = 1; 1647 callout_schedule(&sc->sc_txfifo_ch, 1); 1648 return (1); 1649 } 1650 1651 send_packet: 1652 sc->sc_txfifo_head += len; 1653 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1654 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1655 1656 return (0); 1657 } 1658 1659 /* 1660 * wm_start: [ifnet interface function] 1661 * 1662 * Start packet transmission on the interface. 1663 */ 1664 static void 1665 wm_start(struct ifnet *ifp) 1666 { 1667 struct wm_softc *sc = ifp->if_softc; 1668 struct mbuf *m0; 1669 #if 0 /* XXXJRT */ 1670 struct m_tag *mtag; 1671 #endif 1672 struct wm_txsoft *txs; 1673 bus_dmamap_t dmamap; 1674 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1675 bus_addr_t curaddr; 1676 bus_size_t seglen, curlen; 1677 uint32_t cksumcmd; 1678 uint8_t cksumfields; 1679 1680 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1681 return; 1682 1683 /* 1684 * Remember the previous number of free descriptors. 1685 */ 1686 ofree = sc->sc_txfree; 1687 1688 /* 1689 * Loop through the send queue, setting up transmit descriptors 1690 * until we drain the queue, or use up all available transmit 1691 * descriptors. 1692 */ 1693 for (;;) { 1694 /* Grab a packet off the queue. */ 1695 IFQ_POLL(&ifp->if_snd, m0); 1696 if (m0 == NULL) 1697 break; 1698 1699 DPRINTF(WM_DEBUG_TX, 1700 ("%s: TX: have packet to transmit: %p\n", 1701 sc->sc_dev.dv_xname, m0)); 1702 1703 /* Get a work queue entry. */ 1704 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1705 wm_txintr(sc); 1706 if (sc->sc_txsfree == 0) { 1707 DPRINTF(WM_DEBUG_TX, 1708 ("%s: TX: no free job descriptors\n", 1709 sc->sc_dev.dv_xname)); 1710 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1711 break; 1712 } 1713 } 1714 1715 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1716 dmamap = txs->txs_dmamap; 1717 1718 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1719 1720 /* 1721 * So says the Linux driver: 1722 * The controller does a simple calculation to make sure 1723 * there is enough room in the FIFO before initiating the 1724 * DMA for each buffer. The calc is: 1725 * 4 = ceil(buffer len / MSS) 1726 * To make sure we don't overrun the FIFO, adjust the max 1727 * buffer len if the MSS drops. 1728 */ 1729 dmamap->dm_maxsegsz = 1730 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1731 ? m0->m_pkthdr.segsz << 2 1732 : WTX_MAX_LEN; 1733 1734 /* 1735 * Load the DMA map. If this fails, the packet either 1736 * didn't fit in the allotted number of segments, or we 1737 * were short on resources. For the too-many-segments 1738 * case, we simply report an error and drop the packet, 1739 * since we can't sanely copy a jumbo packet to a single 1740 * buffer. 1741 */ 1742 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1743 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1744 if (error) { 1745 if (error == EFBIG) { 1746 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1747 log(LOG_ERR, "%s: Tx packet consumes too many " 1748 "DMA segments, dropping...\n", 1749 sc->sc_dev.dv_xname); 1750 IFQ_DEQUEUE(&ifp->if_snd, m0); 1751 wm_dump_mbuf_chain(sc, m0); 1752 m_freem(m0); 1753 continue; 1754 } 1755 /* 1756 * Short on resources, just stop for now. 1757 */ 1758 DPRINTF(WM_DEBUG_TX, 1759 ("%s: TX: dmamap load failed: %d\n", 1760 sc->sc_dev.dv_xname, error)); 1761 break; 1762 } 1763 1764 segs_needed = dmamap->dm_nsegs; 1765 if (use_tso) { 1766 /* For sentinel descriptor; see below. */ 1767 segs_needed++; 1768 } 1769 1770 /* 1771 * Ensure we have enough descriptors free to describe 1772 * the packet. Note, we always reserve one descriptor 1773 * at the end of the ring due to the semantics of the 1774 * TDT register, plus one more in the event we need 1775 * to load offload context. 1776 */ 1777 if (segs_needed > sc->sc_txfree - 2) { 1778 /* 1779 * Not enough free descriptors to transmit this 1780 * packet. We haven't committed anything yet, 1781 * so just unload the DMA map, put the packet 1782 * pack on the queue, and punt. Notify the upper 1783 * layer that there are no more slots left. 1784 */ 1785 DPRINTF(WM_DEBUG_TX, 1786 ("%s: TX: need %d (%d) descriptors, have %d\n", 1787 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1788 sc->sc_txfree - 1)); 1789 ifp->if_flags |= IFF_OACTIVE; 1790 bus_dmamap_unload(sc->sc_dmat, dmamap); 1791 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1792 break; 1793 } 1794 1795 /* 1796 * Check for 82547 Tx FIFO bug. We need to do this 1797 * once we know we can transmit the packet, since we 1798 * do some internal FIFO space accounting here. 1799 */ 1800 if (sc->sc_type == WM_T_82547 && 1801 wm_82547_txfifo_bugchk(sc, m0)) { 1802 DPRINTF(WM_DEBUG_TX, 1803 ("%s: TX: 82547 Tx FIFO bug detected\n", 1804 sc->sc_dev.dv_xname)); 1805 ifp->if_flags |= IFF_OACTIVE; 1806 bus_dmamap_unload(sc->sc_dmat, dmamap); 1807 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1808 break; 1809 } 1810 1811 IFQ_DEQUEUE(&ifp->if_snd, m0); 1812 1813 /* 1814 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1815 */ 1816 1817 DPRINTF(WM_DEBUG_TX, 1818 ("%s: TX: packet has %d (%d) DMA segments\n", 1819 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1820 1821 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1822 1823 /* 1824 * Store a pointer to the packet so that we can free it 1825 * later. 1826 * 1827 * Initially, we consider the number of descriptors the 1828 * packet uses the number of DMA segments. This may be 1829 * incremented by 1 if we do checksum offload (a descriptor 1830 * is used to set the checksum context). 1831 */ 1832 txs->txs_mbuf = m0; 1833 txs->txs_firstdesc = sc->sc_txnext; 1834 txs->txs_ndesc = segs_needed; 1835 1836 /* Set up offload parameters for this packet. */ 1837 if (m0->m_pkthdr.csum_flags & 1838 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 1839 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 1840 if (wm_tx_offload(sc, txs, &cksumcmd, 1841 &cksumfields) != 0) { 1842 /* Error message already displayed. */ 1843 bus_dmamap_unload(sc->sc_dmat, dmamap); 1844 continue; 1845 } 1846 } else { 1847 cksumcmd = 0; 1848 cksumfields = 0; 1849 } 1850 1851 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1852 1853 /* Sync the DMA map. */ 1854 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1855 BUS_DMASYNC_PREWRITE); 1856 1857 /* 1858 * Initialize the transmit descriptor. 1859 */ 1860 for (nexttx = sc->sc_txnext, seg = 0; 1861 seg < dmamap->dm_nsegs; seg++) { 1862 for (seglen = dmamap->dm_segs[seg].ds_len, 1863 curaddr = dmamap->dm_segs[seg].ds_addr; 1864 seglen != 0; 1865 curaddr += curlen, seglen -= curlen, 1866 nexttx = WM_NEXTTX(sc, nexttx)) { 1867 curlen = seglen; 1868 1869 /* 1870 * So says the Linux driver: 1871 * Work around for premature descriptor 1872 * write-backs in TSO mode. Append a 1873 * 4-byte sentinel descriptor. 1874 */ 1875 if (use_tso && 1876 seg == dmamap->dm_nsegs - 1 && 1877 curlen > 8) 1878 curlen -= 4; 1879 1880 wm_set_dma_addr( 1881 &sc->sc_txdescs[nexttx].wtx_addr, 1882 curaddr); 1883 sc->sc_txdescs[nexttx].wtx_cmdlen = 1884 htole32(cksumcmd | curlen); 1885 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1886 0; 1887 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1888 cksumfields; 1889 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1890 lasttx = nexttx; 1891 1892 DPRINTF(WM_DEBUG_TX, 1893 ("%s: TX: desc %d: low 0x%08lx, " 1894 "len 0x%04x\n", 1895 sc->sc_dev.dv_xname, nexttx, 1896 curaddr & 0xffffffffUL, (unsigned)curlen)); 1897 } 1898 } 1899 1900 KASSERT(lasttx != -1); 1901 1902 /* 1903 * Set up the command byte on the last descriptor of 1904 * the packet. If we're in the interrupt delay window, 1905 * delay the interrupt. 1906 */ 1907 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1908 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1909 1910 #if 0 /* XXXJRT */ 1911 /* 1912 * If VLANs are enabled and the packet has a VLAN tag, set 1913 * up the descriptor to encapsulate the packet for us. 1914 * 1915 * This is only valid on the last descriptor of the packet. 1916 */ 1917 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1918 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1919 htole32(WTX_CMD_VLE); 1920 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1921 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1922 } 1923 #endif /* XXXJRT */ 1924 1925 txs->txs_lastdesc = lasttx; 1926 1927 DPRINTF(WM_DEBUG_TX, 1928 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1929 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1930 1931 /* Sync the descriptors we're using. */ 1932 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1933 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1934 1935 /* Give the packet to the chip. */ 1936 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1937 1938 DPRINTF(WM_DEBUG_TX, 1939 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1940 1941 DPRINTF(WM_DEBUG_TX, 1942 ("%s: TX: finished transmitting packet, job %d\n", 1943 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1944 1945 /* Advance the tx pointer. */ 1946 sc->sc_txfree -= txs->txs_ndesc; 1947 sc->sc_txnext = nexttx; 1948 1949 sc->sc_txsfree--; 1950 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1951 1952 #if NBPFILTER > 0 1953 /* Pass the packet to any BPF listeners. */ 1954 if (ifp->if_bpf) 1955 bpf_mtap(ifp->if_bpf, m0); 1956 #endif /* NBPFILTER > 0 */ 1957 } 1958 1959 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1960 /* No more slots; notify upper layer. */ 1961 ifp->if_flags |= IFF_OACTIVE; 1962 } 1963 1964 if (sc->sc_txfree != ofree) { 1965 /* Set a watchdog timer in case the chip flakes out. */ 1966 ifp->if_timer = 5; 1967 } 1968 } 1969 1970 /* 1971 * wm_watchdog: [ifnet interface function] 1972 * 1973 * Watchdog timer handler. 1974 */ 1975 static void 1976 wm_watchdog(struct ifnet *ifp) 1977 { 1978 struct wm_softc *sc = ifp->if_softc; 1979 1980 /* 1981 * Since we're using delayed interrupts, sweep up 1982 * before we report an error. 1983 */ 1984 wm_txintr(sc); 1985 1986 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1987 log(LOG_ERR, 1988 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1989 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1990 sc->sc_txnext); 1991 ifp->if_oerrors++; 1992 1993 /* Reset the interface. */ 1994 (void) wm_init(ifp); 1995 } 1996 1997 /* Try to get more packets going. */ 1998 wm_start(ifp); 1999 } 2000 2001 /* 2002 * wm_ioctl: [ifnet interface function] 2003 * 2004 * Handle control requests from the operator. 2005 */ 2006 static int 2007 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2008 { 2009 struct wm_softc *sc = ifp->if_softc; 2010 struct ifreq *ifr = (struct ifreq *) data; 2011 int s, error; 2012 2013 s = splnet(); 2014 2015 switch (cmd) { 2016 case SIOCSIFMEDIA: 2017 case SIOCGIFMEDIA: 2018 /* Flow control requires full-duplex mode. */ 2019 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2020 (ifr->ifr_media & IFM_FDX) == 0) 2021 ifr->ifr_media &= ~IFM_ETH_FMASK; 2022 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2023 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2024 /* We can do both TXPAUSE and RXPAUSE. */ 2025 ifr->ifr_media |= 2026 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2027 } 2028 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2029 } 2030 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2031 break; 2032 default: 2033 error = ether_ioctl(ifp, cmd, data); 2034 if (error == ENETRESET) { 2035 /* 2036 * Multicast list has changed; set the hardware filter 2037 * accordingly. 2038 */ 2039 if (ifp->if_flags & IFF_RUNNING) 2040 wm_set_filter(sc); 2041 error = 0; 2042 } 2043 break; 2044 } 2045 2046 /* Try to get more packets going. */ 2047 wm_start(ifp); 2048 2049 splx(s); 2050 return (error); 2051 } 2052 2053 /* 2054 * wm_intr: 2055 * 2056 * Interrupt service routine. 2057 */ 2058 static int 2059 wm_intr(void *arg) 2060 { 2061 struct wm_softc *sc = arg; 2062 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2063 uint32_t icr; 2064 int handled = 0; 2065 2066 while (1 /* CONSTCOND */) { 2067 icr = CSR_READ(sc, WMREG_ICR); 2068 if ((icr & sc->sc_icr) == 0) 2069 break; 2070 2071 #if 0 /*NRND > 0*/ 2072 if (RND_ENABLED(&sc->rnd_source)) 2073 rnd_add_uint32(&sc->rnd_source, icr); 2074 #endif 2075 2076 handled = 1; 2077 2078 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2079 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2080 DPRINTF(WM_DEBUG_RX, 2081 ("%s: RX: got Rx intr 0x%08x\n", 2082 sc->sc_dev.dv_xname, 2083 icr & (ICR_RXDMT0|ICR_RXT0))); 2084 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2085 } 2086 #endif 2087 wm_rxintr(sc); 2088 2089 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2090 if (icr & ICR_TXDW) { 2091 DPRINTF(WM_DEBUG_TX, 2092 ("%s: TX: got TXDW interrupt\n", 2093 sc->sc_dev.dv_xname)); 2094 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2095 } 2096 #endif 2097 wm_txintr(sc); 2098 2099 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2100 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2101 wm_linkintr(sc, icr); 2102 } 2103 2104 if (icr & ICR_RXO) { 2105 ifp->if_ierrors++; 2106 #if defined(WM_DEBUG) 2107 log(LOG_WARNING, "%s: Receive overrun\n", 2108 sc->sc_dev.dv_xname); 2109 #endif /* defined(WM_DEBUG) */ 2110 } 2111 } 2112 2113 if (handled) { 2114 /* Try to get more packets going. */ 2115 wm_start(ifp); 2116 } 2117 2118 return (handled); 2119 } 2120 2121 /* 2122 * wm_txintr: 2123 * 2124 * Helper; handle transmit interrupts. 2125 */ 2126 static void 2127 wm_txintr(struct wm_softc *sc) 2128 { 2129 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2130 struct wm_txsoft *txs; 2131 uint8_t status; 2132 int i; 2133 2134 ifp->if_flags &= ~IFF_OACTIVE; 2135 2136 /* 2137 * Go through the Tx list and free mbufs for those 2138 * frames which have been transmitted. 2139 */ 2140 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2141 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2142 txs = &sc->sc_txsoft[i]; 2143 2144 DPRINTF(WM_DEBUG_TX, 2145 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2146 2147 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2148 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2149 2150 status = 2151 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2152 if ((status & WTX_ST_DD) == 0) { 2153 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2154 BUS_DMASYNC_PREREAD); 2155 break; 2156 } 2157 2158 DPRINTF(WM_DEBUG_TX, 2159 ("%s: TX: job %d done: descs %d..%d\n", 2160 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2161 txs->txs_lastdesc)); 2162 2163 /* 2164 * XXX We should probably be using the statistics 2165 * XXX registers, but I don't know if they exist 2166 * XXX on chips before the i82544. 2167 */ 2168 2169 #ifdef WM_EVENT_COUNTERS 2170 if (status & WTX_ST_TU) 2171 WM_EVCNT_INCR(&sc->sc_ev_tu); 2172 #endif /* WM_EVENT_COUNTERS */ 2173 2174 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2175 ifp->if_oerrors++; 2176 if (status & WTX_ST_LC) 2177 log(LOG_WARNING, "%s: late collision\n", 2178 sc->sc_dev.dv_xname); 2179 else if (status & WTX_ST_EC) { 2180 ifp->if_collisions += 16; 2181 log(LOG_WARNING, "%s: excessive collisions\n", 2182 sc->sc_dev.dv_xname); 2183 } 2184 } else 2185 ifp->if_opackets++; 2186 2187 sc->sc_txfree += txs->txs_ndesc; 2188 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2189 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2190 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2191 m_freem(txs->txs_mbuf); 2192 txs->txs_mbuf = NULL; 2193 } 2194 2195 /* Update the dirty transmit buffer pointer. */ 2196 sc->sc_txsdirty = i; 2197 DPRINTF(WM_DEBUG_TX, 2198 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2199 2200 /* 2201 * If there are no more pending transmissions, cancel the watchdog 2202 * timer. 2203 */ 2204 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2205 ifp->if_timer = 0; 2206 } 2207 2208 /* 2209 * wm_rxintr: 2210 * 2211 * Helper; handle receive interrupts. 2212 */ 2213 static void 2214 wm_rxintr(struct wm_softc *sc) 2215 { 2216 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2217 struct wm_rxsoft *rxs; 2218 struct mbuf *m; 2219 int i, len; 2220 uint8_t status, errors; 2221 2222 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2223 rxs = &sc->sc_rxsoft[i]; 2224 2225 DPRINTF(WM_DEBUG_RX, 2226 ("%s: RX: checking descriptor %d\n", 2227 sc->sc_dev.dv_xname, i)); 2228 2229 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2230 2231 status = sc->sc_rxdescs[i].wrx_status; 2232 errors = sc->sc_rxdescs[i].wrx_errors; 2233 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2234 2235 if ((status & WRX_ST_DD) == 0) { 2236 /* 2237 * We have processed all of the receive descriptors. 2238 */ 2239 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2240 break; 2241 } 2242 2243 if (__predict_false(sc->sc_rxdiscard)) { 2244 DPRINTF(WM_DEBUG_RX, 2245 ("%s: RX: discarding contents of descriptor %d\n", 2246 sc->sc_dev.dv_xname, i)); 2247 WM_INIT_RXDESC(sc, i); 2248 if (status & WRX_ST_EOP) { 2249 /* Reset our state. */ 2250 DPRINTF(WM_DEBUG_RX, 2251 ("%s: RX: resetting rxdiscard -> 0\n", 2252 sc->sc_dev.dv_xname)); 2253 sc->sc_rxdiscard = 0; 2254 } 2255 continue; 2256 } 2257 2258 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2259 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2260 2261 m = rxs->rxs_mbuf; 2262 2263 /* 2264 * Add a new receive buffer to the ring. 2265 */ 2266 if (wm_add_rxbuf(sc, i) != 0) { 2267 /* 2268 * Failed, throw away what we've done so 2269 * far, and discard the rest of the packet. 2270 */ 2271 ifp->if_ierrors++; 2272 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2273 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2274 WM_INIT_RXDESC(sc, i); 2275 if ((status & WRX_ST_EOP) == 0) 2276 sc->sc_rxdiscard = 1; 2277 if (sc->sc_rxhead != NULL) 2278 m_freem(sc->sc_rxhead); 2279 WM_RXCHAIN_RESET(sc); 2280 DPRINTF(WM_DEBUG_RX, 2281 ("%s: RX: Rx buffer allocation failed, " 2282 "dropping packet%s\n", sc->sc_dev.dv_xname, 2283 sc->sc_rxdiscard ? " (discard)" : "")); 2284 continue; 2285 } 2286 2287 WM_RXCHAIN_LINK(sc, m); 2288 2289 m->m_len = len; 2290 2291 DPRINTF(WM_DEBUG_RX, 2292 ("%s: RX: buffer at %p len %d\n", 2293 sc->sc_dev.dv_xname, m->m_data, len)); 2294 2295 /* 2296 * If this is not the end of the packet, keep 2297 * looking. 2298 */ 2299 if ((status & WRX_ST_EOP) == 0) { 2300 sc->sc_rxlen += len; 2301 DPRINTF(WM_DEBUG_RX, 2302 ("%s: RX: not yet EOP, rxlen -> %d\n", 2303 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2304 continue; 2305 } 2306 2307 /* 2308 * Okay, we have the entire packet now. The chip is 2309 * configured to include the FCS (not all chips can 2310 * be configured to strip it), so we need to trim it. 2311 */ 2312 m->m_len -= ETHER_CRC_LEN; 2313 2314 *sc->sc_rxtailp = NULL; 2315 len = m->m_len + sc->sc_rxlen; 2316 m = sc->sc_rxhead; 2317 2318 WM_RXCHAIN_RESET(sc); 2319 2320 DPRINTF(WM_DEBUG_RX, 2321 ("%s: RX: have entire packet, len -> %d\n", 2322 sc->sc_dev.dv_xname, len)); 2323 2324 /* 2325 * If an error occurred, update stats and drop the packet. 2326 */ 2327 if (errors & 2328 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2329 ifp->if_ierrors++; 2330 if (errors & WRX_ER_SE) 2331 log(LOG_WARNING, "%s: symbol error\n", 2332 sc->sc_dev.dv_xname); 2333 else if (errors & WRX_ER_SEQ) 2334 log(LOG_WARNING, "%s: receive sequence error\n", 2335 sc->sc_dev.dv_xname); 2336 else if (errors & WRX_ER_CE) 2337 log(LOG_WARNING, "%s: CRC error\n", 2338 sc->sc_dev.dv_xname); 2339 m_freem(m); 2340 continue; 2341 } 2342 2343 /* 2344 * No errors. Receive the packet. 2345 */ 2346 m->m_pkthdr.rcvif = ifp; 2347 m->m_pkthdr.len = len; 2348 2349 #if 0 /* XXXJRT */ 2350 /* 2351 * If VLANs are enabled, VLAN packets have been unwrapped 2352 * for us. Associate the tag with the packet. 2353 */ 2354 if ((status & WRX_ST_VP) != 0) { 2355 VLAN_INPUT_TAG(ifp, m, 2356 le16toh(sc->sc_rxdescs[i].wrx_special, 2357 continue); 2358 } 2359 #endif /* XXXJRT */ 2360 2361 /* 2362 * Set up checksum info for this packet. 2363 */ 2364 if ((status & WRX_ST_IXSM) == 0) { 2365 if (status & WRX_ST_IPCS) { 2366 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2367 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2368 if (errors & WRX_ER_IPE) 2369 m->m_pkthdr.csum_flags |= 2370 M_CSUM_IPv4_BAD; 2371 } 2372 if (status & WRX_ST_TCPCS) { 2373 /* 2374 * Note: we don't know if this was TCP or UDP, 2375 * so we just set both bits, and expect the 2376 * upper layers to deal. 2377 */ 2378 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2379 m->m_pkthdr.csum_flags |= 2380 M_CSUM_TCPv4|M_CSUM_UDPv4; 2381 if (errors & WRX_ER_TCPE) 2382 m->m_pkthdr.csum_flags |= 2383 M_CSUM_TCP_UDP_BAD; 2384 } 2385 } 2386 2387 ifp->if_ipackets++; 2388 2389 #if NBPFILTER > 0 2390 /* Pass this up to any BPF listeners. */ 2391 if (ifp->if_bpf) 2392 bpf_mtap(ifp->if_bpf, m); 2393 #endif /* NBPFILTER > 0 */ 2394 2395 /* Pass it on. */ 2396 (*ifp->if_input)(ifp, m); 2397 } 2398 2399 /* Update the receive pointer. */ 2400 sc->sc_rxptr = i; 2401 2402 DPRINTF(WM_DEBUG_RX, 2403 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2404 } 2405 2406 /* 2407 * wm_linkintr: 2408 * 2409 * Helper; handle link interrupts. 2410 */ 2411 static void 2412 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2413 { 2414 uint32_t status; 2415 2416 /* 2417 * If we get a link status interrupt on a 1000BASE-T 2418 * device, just fall into the normal MII tick path. 2419 */ 2420 if (sc->sc_flags & WM_F_HAS_MII) { 2421 if (icr & ICR_LSC) { 2422 DPRINTF(WM_DEBUG_LINK, 2423 ("%s: LINK: LSC -> mii_tick\n", 2424 sc->sc_dev.dv_xname)); 2425 mii_tick(&sc->sc_mii); 2426 } else if (icr & ICR_RXSEQ) { 2427 DPRINTF(WM_DEBUG_LINK, 2428 ("%s: LINK Receive sequence error\n", 2429 sc->sc_dev.dv_xname)); 2430 } 2431 return; 2432 } 2433 2434 /* 2435 * If we are now receiving /C/, check for link again in 2436 * a couple of link clock ticks. 2437 */ 2438 if (icr & ICR_RXCFG) { 2439 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2440 sc->sc_dev.dv_xname)); 2441 sc->sc_tbi_anstate = 2; 2442 } 2443 2444 if (icr & ICR_LSC) { 2445 status = CSR_READ(sc, WMREG_STATUS); 2446 if (status & STATUS_LU) { 2447 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2448 sc->sc_dev.dv_xname, 2449 (status & STATUS_FD) ? "FDX" : "HDX")); 2450 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2451 sc->sc_fcrtl &= ~FCRTL_XONE; 2452 if (status & STATUS_FD) 2453 sc->sc_tctl |= 2454 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2455 else 2456 sc->sc_tctl |= 2457 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2458 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2459 sc->sc_fcrtl |= FCRTL_XONE; 2460 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2461 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2462 WMREG_OLD_FCRTL : WMREG_FCRTL, 2463 sc->sc_fcrtl); 2464 sc->sc_tbi_linkup = 1; 2465 } else { 2466 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2467 sc->sc_dev.dv_xname)); 2468 sc->sc_tbi_linkup = 0; 2469 } 2470 sc->sc_tbi_anstate = 2; 2471 wm_tbi_set_linkled(sc); 2472 } else if (icr & ICR_RXSEQ) { 2473 DPRINTF(WM_DEBUG_LINK, 2474 ("%s: LINK: Receive sequence error\n", 2475 sc->sc_dev.dv_xname)); 2476 } 2477 } 2478 2479 /* 2480 * wm_tick: 2481 * 2482 * One second timer, used to check link status, sweep up 2483 * completed transmit jobs, etc. 2484 */ 2485 static void 2486 wm_tick(void *arg) 2487 { 2488 struct wm_softc *sc = arg; 2489 int s; 2490 2491 s = splnet(); 2492 2493 if (sc->sc_type >= WM_T_82542_2_1) { 2494 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2495 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2496 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2497 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2498 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2499 } 2500 2501 if (sc->sc_flags & WM_F_HAS_MII) 2502 mii_tick(&sc->sc_mii); 2503 else 2504 wm_tbi_check_link(sc); 2505 2506 splx(s); 2507 2508 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2509 } 2510 2511 /* 2512 * wm_reset: 2513 * 2514 * Reset the i82542 chip. 2515 */ 2516 static void 2517 wm_reset(struct wm_softc *sc) 2518 { 2519 int i; 2520 2521 /* 2522 * Allocate on-chip memory according to the MTU size. 2523 * The Packet Buffer Allocation register must be written 2524 * before the chip is reset. 2525 */ 2526 if (sc->sc_type < WM_T_82547) { 2527 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2528 PBA_40K : PBA_48K; 2529 } else { 2530 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2531 PBA_22K : PBA_30K; 2532 sc->sc_txfifo_head = 0; 2533 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2534 sc->sc_txfifo_size = 2535 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2536 sc->sc_txfifo_stall = 0; 2537 } 2538 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2539 2540 switch (sc->sc_type) { 2541 case WM_T_82544: 2542 case WM_T_82540: 2543 case WM_T_82545: 2544 case WM_T_82546: 2545 case WM_T_82541: 2546 case WM_T_82541_2: 2547 /* 2548 * On some chipsets, a reset through a memory-mapped write 2549 * cycle can cause the chip to reset before completing the 2550 * write cycle. This causes major headache that can be 2551 * avoided by issuing the reset via indirect register writes 2552 * through I/O space. 2553 * 2554 * So, if we successfully mapped the I/O BAR at attach time, 2555 * use that. Otherwise, try our luck with a memory-mapped 2556 * reset. 2557 */ 2558 if (sc->sc_flags & WM_F_IOH_VALID) 2559 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2560 else 2561 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2562 break; 2563 2564 case WM_T_82545_3: 2565 case WM_T_82546_3: 2566 /* Use the shadow control register on these chips. */ 2567 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2568 break; 2569 2570 default: 2571 /* Everything else can safely use the documented method. */ 2572 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2573 break; 2574 } 2575 delay(10000); 2576 2577 for (i = 0; i < 1000; i++) { 2578 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2579 return; 2580 delay(20); 2581 } 2582 2583 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2584 log(LOG_ERR, "%s: reset failed to complete\n", 2585 sc->sc_dev.dv_xname); 2586 } 2587 2588 /* 2589 * wm_init: [ifnet interface function] 2590 * 2591 * Initialize the interface. Must be called at splnet(). 2592 */ 2593 static int 2594 wm_init(struct ifnet *ifp) 2595 { 2596 struct wm_softc *sc = ifp->if_softc; 2597 struct wm_rxsoft *rxs; 2598 int i, error = 0; 2599 uint32_t reg; 2600 2601 /* 2602 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2603 * There is a small but measurable benefit to avoiding the adjusment 2604 * of the descriptor so that the headers are aligned, for normal mtu, 2605 * on such platforms. One possibility is that the DMA itself is 2606 * slightly more efficient if the front of the entire packet (instead 2607 * of the front of the headers) is aligned. 2608 * 2609 * Note we must always set align_tweak to 0 if we are using 2610 * jumbo frames. 2611 */ 2612 #ifdef __NO_STRICT_ALIGNMENT 2613 sc->sc_align_tweak = 0; 2614 #else 2615 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2616 sc->sc_align_tweak = 0; 2617 else 2618 sc->sc_align_tweak = 2; 2619 #endif /* __NO_STRICT_ALIGNMENT */ 2620 2621 /* Cancel any pending I/O. */ 2622 wm_stop(ifp, 0); 2623 2624 /* Reset the chip to a known state. */ 2625 wm_reset(sc); 2626 2627 /* Initialize the transmit descriptor ring. */ 2628 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2629 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2630 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2631 sc->sc_txfree = WM_NTXDESC(sc); 2632 sc->sc_txnext = 0; 2633 2634 if (sc->sc_type < WM_T_82543) { 2635 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2636 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2637 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2638 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2639 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2640 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2641 } else { 2642 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2643 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2644 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2645 CSR_WRITE(sc, WMREG_TDH, 0); 2646 CSR_WRITE(sc, WMREG_TDT, 0); 2647 CSR_WRITE(sc, WMREG_TIDV, 64); 2648 CSR_WRITE(sc, WMREG_TADV, 128); 2649 2650 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2651 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2652 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2653 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2654 } 2655 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2656 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2657 2658 /* Initialize the transmit job descriptors. */ 2659 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2660 sc->sc_txsoft[i].txs_mbuf = NULL; 2661 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2662 sc->sc_txsnext = 0; 2663 sc->sc_txsdirty = 0; 2664 2665 /* 2666 * Initialize the receive descriptor and receive job 2667 * descriptor rings. 2668 */ 2669 if (sc->sc_type < WM_T_82543) { 2670 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2671 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2672 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2673 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2674 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2675 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2676 2677 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2678 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2679 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2680 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2681 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2682 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2683 } else { 2684 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2685 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2686 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2687 CSR_WRITE(sc, WMREG_RDH, 0); 2688 CSR_WRITE(sc, WMREG_RDT, 0); 2689 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2690 CSR_WRITE(sc, WMREG_RADV, 128); 2691 } 2692 for (i = 0; i < WM_NRXDESC; i++) { 2693 rxs = &sc->sc_rxsoft[i]; 2694 if (rxs->rxs_mbuf == NULL) { 2695 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2696 log(LOG_ERR, "%s: unable to allocate or map rx " 2697 "buffer %d, error = %d\n", 2698 sc->sc_dev.dv_xname, i, error); 2699 /* 2700 * XXX Should attempt to run with fewer receive 2701 * XXX buffers instead of just failing. 2702 */ 2703 wm_rxdrain(sc); 2704 goto out; 2705 } 2706 } else 2707 WM_INIT_RXDESC(sc, i); 2708 } 2709 sc->sc_rxptr = 0; 2710 sc->sc_rxdiscard = 0; 2711 WM_RXCHAIN_RESET(sc); 2712 2713 /* 2714 * Clear out the VLAN table -- we don't use it (yet). 2715 */ 2716 CSR_WRITE(sc, WMREG_VET, 0); 2717 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2718 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2719 2720 /* 2721 * Set up flow-control parameters. 2722 * 2723 * XXX Values could probably stand some tuning. 2724 */ 2725 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2726 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2727 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2728 2729 sc->sc_fcrtl = FCRTL_DFLT; 2730 if (sc->sc_type < WM_T_82543) { 2731 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2732 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2733 } else { 2734 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2735 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2736 } 2737 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2738 2739 #if 0 /* XXXJRT */ 2740 /* Deal with VLAN enables. */ 2741 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2742 sc->sc_ctrl |= CTRL_VME; 2743 else 2744 #endif /* XXXJRT */ 2745 sc->sc_ctrl &= ~CTRL_VME; 2746 2747 /* Write the control registers. */ 2748 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2749 #if 0 2750 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2751 #endif 2752 2753 /* 2754 * Set up checksum offload parameters. 2755 */ 2756 reg = CSR_READ(sc, WMREG_RXCSUM); 2757 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2758 reg |= RXCSUM_IPOFL; 2759 else 2760 reg &= ~RXCSUM_IPOFL; 2761 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2762 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2763 else { 2764 reg &= ~RXCSUM_TUOFL; 2765 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2766 reg &= ~RXCSUM_IPOFL; 2767 } 2768 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2769 2770 /* 2771 * Set up the interrupt registers. 2772 */ 2773 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2774 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2775 ICR_RXO | ICR_RXT0; 2776 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2777 sc->sc_icr |= ICR_RXCFG; 2778 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2779 2780 /* Set up the inter-packet gap. */ 2781 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2782 2783 if (sc->sc_type >= WM_T_82543) { 2784 /* Set up the interrupt throttling register (units of 256ns) */ 2785 sc->sc_itr = 1000000000 / (7000 * 256); 2786 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2787 } 2788 2789 #if 0 /* XXXJRT */ 2790 /* Set the VLAN ethernetype. */ 2791 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2792 #endif 2793 2794 /* 2795 * Set up the transmit control register; we start out with 2796 * a collision distance suitable for FDX, but update it whe 2797 * we resolve the media type. 2798 */ 2799 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2800 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2801 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2802 2803 /* Set the media. */ 2804 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2805 2806 /* 2807 * Set up the receive control register; we actually program 2808 * the register when we set the receive filter. Use multicast 2809 * address offset type 0. 2810 * 2811 * Only the i82544 has the ability to strip the incoming 2812 * CRC, so we don't enable that feature. 2813 */ 2814 sc->sc_mchash_type = 0; 2815 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2816 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2817 2818 if(MCLBYTES == 2048) { 2819 sc->sc_rctl |= RCTL_2k; 2820 } else { 2821 if(sc->sc_type >= WM_T_82543) { 2822 switch(MCLBYTES) { 2823 case 4096: 2824 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2825 break; 2826 case 8192: 2827 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2828 break; 2829 case 16384: 2830 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2831 break; 2832 default: 2833 panic("wm_init: MCLBYTES %d unsupported", 2834 MCLBYTES); 2835 break; 2836 } 2837 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2838 } 2839 2840 /* Set the receive filter. */ 2841 wm_set_filter(sc); 2842 2843 /* Start the one second link check clock. */ 2844 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2845 2846 /* ...all done! */ 2847 ifp->if_flags |= IFF_RUNNING; 2848 ifp->if_flags &= ~IFF_OACTIVE; 2849 2850 out: 2851 if (error) 2852 log(LOG_ERR, "%s: interface not running\n", 2853 sc->sc_dev.dv_xname); 2854 return (error); 2855 } 2856 2857 /* 2858 * wm_rxdrain: 2859 * 2860 * Drain the receive queue. 2861 */ 2862 static void 2863 wm_rxdrain(struct wm_softc *sc) 2864 { 2865 struct wm_rxsoft *rxs; 2866 int i; 2867 2868 for (i = 0; i < WM_NRXDESC; i++) { 2869 rxs = &sc->sc_rxsoft[i]; 2870 if (rxs->rxs_mbuf != NULL) { 2871 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2872 m_freem(rxs->rxs_mbuf); 2873 rxs->rxs_mbuf = NULL; 2874 } 2875 } 2876 } 2877 2878 /* 2879 * wm_stop: [ifnet interface function] 2880 * 2881 * Stop transmission on the interface. 2882 */ 2883 static void 2884 wm_stop(struct ifnet *ifp, int disable) 2885 { 2886 struct wm_softc *sc = ifp->if_softc; 2887 struct wm_txsoft *txs; 2888 int i; 2889 2890 /* Stop the one second clock. */ 2891 callout_stop(&sc->sc_tick_ch); 2892 2893 /* Stop the 82547 Tx FIFO stall check timer. */ 2894 if (sc->sc_type == WM_T_82547) 2895 callout_stop(&sc->sc_txfifo_ch); 2896 2897 if (sc->sc_flags & WM_F_HAS_MII) { 2898 /* Down the MII. */ 2899 mii_down(&sc->sc_mii); 2900 } 2901 2902 /* Stop the transmit and receive processes. */ 2903 CSR_WRITE(sc, WMREG_TCTL, 0); 2904 CSR_WRITE(sc, WMREG_RCTL, 0); 2905 2906 /* 2907 * Clear the interrupt mask to ensure the device cannot assert its 2908 * interrupt line. 2909 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 2910 * any currently pending or shared interrupt. 2911 */ 2912 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2913 sc->sc_icr = 0; 2914 2915 /* Release any queued transmit buffers. */ 2916 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2917 txs = &sc->sc_txsoft[i]; 2918 if (txs->txs_mbuf != NULL) { 2919 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2920 m_freem(txs->txs_mbuf); 2921 txs->txs_mbuf = NULL; 2922 } 2923 } 2924 2925 if (disable) 2926 wm_rxdrain(sc); 2927 2928 /* Mark the interface as down and cancel the watchdog timer. */ 2929 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2930 ifp->if_timer = 0; 2931 } 2932 2933 /* 2934 * wm_acquire_eeprom: 2935 * 2936 * Perform the EEPROM handshake required on some chips. 2937 */ 2938 static int 2939 wm_acquire_eeprom(struct wm_softc *sc) 2940 { 2941 uint32_t reg; 2942 int x; 2943 2944 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2945 reg = CSR_READ(sc, WMREG_EECD); 2946 2947 /* Request EEPROM access. */ 2948 reg |= EECD_EE_REQ; 2949 CSR_WRITE(sc, WMREG_EECD, reg); 2950 2951 /* ..and wait for it to be granted. */ 2952 for (x = 0; x < 100; x++) { 2953 reg = CSR_READ(sc, WMREG_EECD); 2954 if (reg & EECD_EE_GNT) 2955 break; 2956 delay(5); 2957 } 2958 if ((reg & EECD_EE_GNT) == 0) { 2959 aprint_error("%s: could not acquire EEPROM GNT\n", 2960 sc->sc_dev.dv_xname); 2961 reg &= ~EECD_EE_REQ; 2962 CSR_WRITE(sc, WMREG_EECD, reg); 2963 return (1); 2964 } 2965 } 2966 2967 return (0); 2968 } 2969 2970 /* 2971 * wm_release_eeprom: 2972 * 2973 * Release the EEPROM mutex. 2974 */ 2975 static void 2976 wm_release_eeprom(struct wm_softc *sc) 2977 { 2978 uint32_t reg; 2979 2980 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2981 reg = CSR_READ(sc, WMREG_EECD); 2982 reg &= ~EECD_EE_REQ; 2983 CSR_WRITE(sc, WMREG_EECD, reg); 2984 } 2985 } 2986 2987 /* 2988 * wm_eeprom_sendbits: 2989 * 2990 * Send a series of bits to the EEPROM. 2991 */ 2992 static void 2993 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2994 { 2995 uint32_t reg; 2996 int x; 2997 2998 reg = CSR_READ(sc, WMREG_EECD); 2999 3000 for (x = nbits; x > 0; x--) { 3001 if (bits & (1U << (x - 1))) 3002 reg |= EECD_DI; 3003 else 3004 reg &= ~EECD_DI; 3005 CSR_WRITE(sc, WMREG_EECD, reg); 3006 delay(2); 3007 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3008 delay(2); 3009 CSR_WRITE(sc, WMREG_EECD, reg); 3010 delay(2); 3011 } 3012 } 3013 3014 /* 3015 * wm_eeprom_recvbits: 3016 * 3017 * Receive a series of bits from the EEPROM. 3018 */ 3019 static void 3020 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 3021 { 3022 uint32_t reg, val; 3023 int x; 3024 3025 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 3026 3027 val = 0; 3028 for (x = nbits; x > 0; x--) { 3029 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3030 delay(2); 3031 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 3032 val |= (1U << (x - 1)); 3033 CSR_WRITE(sc, WMREG_EECD, reg); 3034 delay(2); 3035 } 3036 *valp = val; 3037 } 3038 3039 /* 3040 * wm_read_eeprom_uwire: 3041 * 3042 * Read a word from the EEPROM using the MicroWire protocol. 3043 */ 3044 static int 3045 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3046 { 3047 uint32_t reg, val; 3048 int i; 3049 3050 for (i = 0; i < wordcnt; i++) { 3051 /* Clear SK and DI. */ 3052 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3053 CSR_WRITE(sc, WMREG_EECD, reg); 3054 3055 /* Set CHIP SELECT. */ 3056 reg |= EECD_CS; 3057 CSR_WRITE(sc, WMREG_EECD, reg); 3058 delay(2); 3059 3060 /* Shift in the READ command. */ 3061 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3062 3063 /* Shift in address. */ 3064 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3065 3066 /* Shift out the data. */ 3067 wm_eeprom_recvbits(sc, &val, 16); 3068 data[i] = val & 0xffff; 3069 3070 /* Clear CHIP SELECT. */ 3071 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3072 CSR_WRITE(sc, WMREG_EECD, reg); 3073 delay(2); 3074 } 3075 3076 return (0); 3077 } 3078 3079 /* 3080 * wm_spi_eeprom_ready: 3081 * 3082 * Wait for a SPI EEPROM to be ready for commands. 3083 */ 3084 static int 3085 wm_spi_eeprom_ready(struct wm_softc *sc) 3086 { 3087 uint32_t val; 3088 int usec; 3089 3090 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3091 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3092 wm_eeprom_recvbits(sc, &val, 8); 3093 if ((val & SPI_SR_RDY) == 0) 3094 break; 3095 } 3096 if (usec >= SPI_MAX_RETRIES) { 3097 aprint_error("%s: EEPROM failed to become ready\n", 3098 sc->sc_dev.dv_xname); 3099 return (1); 3100 } 3101 return (0); 3102 } 3103 3104 /* 3105 * wm_read_eeprom_spi: 3106 * 3107 * Read a work from the EEPROM using the SPI protocol. 3108 */ 3109 static int 3110 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3111 { 3112 uint32_t reg, val; 3113 int i; 3114 uint8_t opc; 3115 3116 /* Clear SK and CS. */ 3117 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3118 CSR_WRITE(sc, WMREG_EECD, reg); 3119 delay(2); 3120 3121 if (wm_spi_eeprom_ready(sc)) 3122 return (1); 3123 3124 /* Toggle CS to flush commands. */ 3125 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3126 delay(2); 3127 CSR_WRITE(sc, WMREG_EECD, reg); 3128 delay(2); 3129 3130 opc = SPI_OPC_READ; 3131 if (sc->sc_ee_addrbits == 8 && word >= 128) 3132 opc |= SPI_OPC_A8; 3133 3134 wm_eeprom_sendbits(sc, opc, 8); 3135 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3136 3137 for (i = 0; i < wordcnt; i++) { 3138 wm_eeprom_recvbits(sc, &val, 16); 3139 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3140 } 3141 3142 /* Raise CS and clear SK. */ 3143 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3144 CSR_WRITE(sc, WMREG_EECD, reg); 3145 delay(2); 3146 3147 return (0); 3148 } 3149 3150 #define EEPROM_CHECKSUM 0xBABA 3151 #define EEPROM_SIZE 0x0040 3152 3153 /* 3154 * wm_validate_eeprom_checksum 3155 * 3156 * The checksum is defined as the sum of the first 64 (16 bit) words. 3157 */ 3158 static int 3159 wm_validate_eeprom_checksum(struct wm_softc *sc) 3160 { 3161 uint16_t checksum; 3162 uint16_t eeprom_data; 3163 int i; 3164 3165 checksum = 0; 3166 3167 for (i = 0; i < EEPROM_SIZE; i++) { 3168 if(wm_read_eeprom(sc, i, 1, &eeprom_data)) 3169 return 1; 3170 checksum += eeprom_data; 3171 } 3172 3173 if (checksum != (uint16_t) EEPROM_CHECKSUM) 3174 return 1; 3175 3176 return 0; 3177 } 3178 3179 /* 3180 * wm_read_eeprom: 3181 * 3182 * Read data from the serial EEPROM. 3183 */ 3184 static int 3185 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3186 { 3187 int rv; 3188 3189 #ifdef __HAVE_WM_READ_EEPROM_HOOK 3190 if (sc->sc_flags & WM_F_EEPROM_MD) { 3191 rv = wm_read_eeprom_hook(word, wordcnt, data); 3192 return (rv); 3193 } 3194 #endif 3195 3196 if (wm_acquire_eeprom(sc)) 3197 return (1); 3198 3199 if (sc->sc_flags & WM_F_EEPROM_SPI) 3200 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3201 else 3202 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3203 3204 wm_release_eeprom(sc); 3205 return (rv); 3206 } 3207 3208 /* 3209 * wm_add_rxbuf: 3210 * 3211 * Add a receive buffer to the indiciated descriptor. 3212 */ 3213 static int 3214 wm_add_rxbuf(struct wm_softc *sc, int idx) 3215 { 3216 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3217 struct mbuf *m; 3218 int error; 3219 3220 MGETHDR(m, M_DONTWAIT, MT_DATA); 3221 if (m == NULL) 3222 return (ENOBUFS); 3223 3224 MCLGET(m, M_DONTWAIT); 3225 if ((m->m_flags & M_EXT) == 0) { 3226 m_freem(m); 3227 return (ENOBUFS); 3228 } 3229 3230 if (rxs->rxs_mbuf != NULL) 3231 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3232 3233 rxs->rxs_mbuf = m; 3234 3235 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3236 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3237 BUS_DMA_READ|BUS_DMA_NOWAIT); 3238 if (error) { 3239 /* XXX XXX XXX */ 3240 printf("%s: unable to load rx DMA map %d, error = %d\n", 3241 sc->sc_dev.dv_xname, idx, error); 3242 panic("wm_add_rxbuf"); 3243 } 3244 3245 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3246 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3247 3248 WM_INIT_RXDESC(sc, idx); 3249 3250 return (0); 3251 } 3252 3253 /* 3254 * wm_set_ral: 3255 * 3256 * Set an entery in the receive address list. 3257 */ 3258 static void 3259 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3260 { 3261 uint32_t ral_lo, ral_hi; 3262 3263 if (enaddr != NULL) { 3264 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3265 (enaddr[3] << 24); 3266 ral_hi = enaddr[4] | (enaddr[5] << 8); 3267 ral_hi |= RAL_AV; 3268 } else { 3269 ral_lo = 0; 3270 ral_hi = 0; 3271 } 3272 3273 if (sc->sc_type >= WM_T_82544) { 3274 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3275 ral_lo); 3276 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3277 ral_hi); 3278 } else { 3279 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3280 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3281 } 3282 } 3283 3284 /* 3285 * wm_mchash: 3286 * 3287 * Compute the hash of the multicast address for the 4096-bit 3288 * multicast filter. 3289 */ 3290 static uint32_t 3291 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3292 { 3293 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3294 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3295 uint32_t hash; 3296 3297 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3298 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3299 3300 return (hash & 0xfff); 3301 } 3302 3303 /* 3304 * wm_set_filter: 3305 * 3306 * Set up the receive filter. 3307 */ 3308 static void 3309 wm_set_filter(struct wm_softc *sc) 3310 { 3311 struct ethercom *ec = &sc->sc_ethercom; 3312 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3313 struct ether_multi *enm; 3314 struct ether_multistep step; 3315 bus_addr_t mta_reg; 3316 uint32_t hash, reg, bit; 3317 int i; 3318 3319 if (sc->sc_type >= WM_T_82544) 3320 mta_reg = WMREG_CORDOVA_MTA; 3321 else 3322 mta_reg = WMREG_MTA; 3323 3324 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3325 3326 if (ifp->if_flags & IFF_BROADCAST) 3327 sc->sc_rctl |= RCTL_BAM; 3328 if (ifp->if_flags & IFF_PROMISC) { 3329 sc->sc_rctl |= RCTL_UPE; 3330 goto allmulti; 3331 } 3332 3333 /* 3334 * Set the station address in the first RAL slot, and 3335 * clear the remaining slots. 3336 */ 3337 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3338 for (i = 1; i < WM_RAL_TABSIZE; i++) 3339 wm_set_ral(sc, NULL, i); 3340 3341 /* Clear out the multicast table. */ 3342 for (i = 0; i < WM_MC_TABSIZE; i++) 3343 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3344 3345 ETHER_FIRST_MULTI(step, ec, enm); 3346 while (enm != NULL) { 3347 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3348 /* 3349 * We must listen to a range of multicast addresses. 3350 * For now, just accept all multicasts, rather than 3351 * trying to set only those filter bits needed to match 3352 * the range. (At this time, the only use of address 3353 * ranges is for IP multicast routing, for which the 3354 * range is big enough to require all bits set.) 3355 */ 3356 goto allmulti; 3357 } 3358 3359 hash = wm_mchash(sc, enm->enm_addrlo); 3360 3361 reg = (hash >> 5) & 0x7f; 3362 bit = hash & 0x1f; 3363 3364 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3365 hash |= 1U << bit; 3366 3367 /* XXX Hardware bug?? */ 3368 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3369 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3370 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3371 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3372 } else 3373 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3374 3375 ETHER_NEXT_MULTI(step, enm); 3376 } 3377 3378 ifp->if_flags &= ~IFF_ALLMULTI; 3379 goto setit; 3380 3381 allmulti: 3382 ifp->if_flags |= IFF_ALLMULTI; 3383 sc->sc_rctl |= RCTL_MPE; 3384 3385 setit: 3386 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3387 } 3388 3389 /* 3390 * wm_tbi_mediainit: 3391 * 3392 * Initialize media for use on 1000BASE-X devices. 3393 */ 3394 static void 3395 wm_tbi_mediainit(struct wm_softc *sc) 3396 { 3397 const char *sep = ""; 3398 3399 if (sc->sc_type < WM_T_82543) 3400 sc->sc_tipg = TIPG_WM_DFLT; 3401 else 3402 sc->sc_tipg = TIPG_LG_DFLT; 3403 3404 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3405 wm_tbi_mediastatus); 3406 3407 /* 3408 * SWD Pins: 3409 * 3410 * 0 = Link LED (output) 3411 * 1 = Loss Of Signal (input) 3412 */ 3413 sc->sc_ctrl |= CTRL_SWDPIO(0); 3414 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3415 3416 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3417 3418 #define ADD(ss, mm, dd) \ 3419 do { \ 3420 aprint_normal("%s%s", sep, ss); \ 3421 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3422 sep = ", "; \ 3423 } while (/*CONSTCOND*/0) 3424 3425 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3426 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3427 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3428 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3429 aprint_normal("\n"); 3430 3431 #undef ADD 3432 3433 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3434 } 3435 3436 /* 3437 * wm_tbi_mediastatus: [ifmedia interface function] 3438 * 3439 * Get the current interface media status on a 1000BASE-X device. 3440 */ 3441 static void 3442 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3443 { 3444 struct wm_softc *sc = ifp->if_softc; 3445 uint32_t ctrl; 3446 3447 ifmr->ifm_status = IFM_AVALID; 3448 ifmr->ifm_active = IFM_ETHER; 3449 3450 if (sc->sc_tbi_linkup == 0) { 3451 ifmr->ifm_active |= IFM_NONE; 3452 return; 3453 } 3454 3455 ifmr->ifm_status |= IFM_ACTIVE; 3456 ifmr->ifm_active |= IFM_1000_SX; 3457 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3458 ifmr->ifm_active |= IFM_FDX; 3459 ctrl = CSR_READ(sc, WMREG_CTRL); 3460 if (ctrl & CTRL_RFCE) 3461 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3462 if (ctrl & CTRL_TFCE) 3463 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3464 } 3465 3466 /* 3467 * wm_tbi_mediachange: [ifmedia interface function] 3468 * 3469 * Set hardware to newly-selected media on a 1000BASE-X device. 3470 */ 3471 static int 3472 wm_tbi_mediachange(struct ifnet *ifp) 3473 { 3474 struct wm_softc *sc = ifp->if_softc; 3475 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3476 uint32_t status; 3477 int i; 3478 3479 sc->sc_txcw = ife->ifm_data; 3480 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3481 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3482 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3483 sc->sc_txcw |= TXCW_ANE; 3484 3485 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3486 delay(10000); 3487 3488 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3489 3490 sc->sc_tbi_anstate = 0; 3491 3492 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3493 /* Have signal; wait for the link to come up. */ 3494 for (i = 0; i < 50; i++) { 3495 delay(10000); 3496 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3497 break; 3498 } 3499 3500 status = CSR_READ(sc, WMREG_STATUS); 3501 if (status & STATUS_LU) { 3502 /* Link is up. */ 3503 DPRINTF(WM_DEBUG_LINK, 3504 ("%s: LINK: set media -> link up %s\n", 3505 sc->sc_dev.dv_xname, 3506 (status & STATUS_FD) ? "FDX" : "HDX")); 3507 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3508 sc->sc_fcrtl &= ~FCRTL_XONE; 3509 if (status & STATUS_FD) 3510 sc->sc_tctl |= 3511 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3512 else 3513 sc->sc_tctl |= 3514 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3515 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3516 sc->sc_fcrtl |= FCRTL_XONE; 3517 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3518 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3519 WMREG_OLD_FCRTL : WMREG_FCRTL, 3520 sc->sc_fcrtl); 3521 sc->sc_tbi_linkup = 1; 3522 } else { 3523 /* Link is down. */ 3524 DPRINTF(WM_DEBUG_LINK, 3525 ("%s: LINK: set media -> link down\n", 3526 sc->sc_dev.dv_xname)); 3527 sc->sc_tbi_linkup = 0; 3528 } 3529 } else { 3530 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3531 sc->sc_dev.dv_xname)); 3532 sc->sc_tbi_linkup = 0; 3533 } 3534 3535 wm_tbi_set_linkled(sc); 3536 3537 return (0); 3538 } 3539 3540 /* 3541 * wm_tbi_set_linkled: 3542 * 3543 * Update the link LED on 1000BASE-X devices. 3544 */ 3545 static void 3546 wm_tbi_set_linkled(struct wm_softc *sc) 3547 { 3548 3549 if (sc->sc_tbi_linkup) 3550 sc->sc_ctrl |= CTRL_SWDPIN(0); 3551 else 3552 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3553 3554 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3555 } 3556 3557 /* 3558 * wm_tbi_check_link: 3559 * 3560 * Check the link on 1000BASE-X devices. 3561 */ 3562 static void 3563 wm_tbi_check_link(struct wm_softc *sc) 3564 { 3565 uint32_t rxcw, ctrl, status; 3566 3567 if (sc->sc_tbi_anstate == 0) 3568 return; 3569 else if (sc->sc_tbi_anstate > 1) { 3570 DPRINTF(WM_DEBUG_LINK, 3571 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3572 sc->sc_tbi_anstate)); 3573 sc->sc_tbi_anstate--; 3574 return; 3575 } 3576 3577 sc->sc_tbi_anstate = 0; 3578 3579 rxcw = CSR_READ(sc, WMREG_RXCW); 3580 ctrl = CSR_READ(sc, WMREG_CTRL); 3581 status = CSR_READ(sc, WMREG_STATUS); 3582 3583 if ((status & STATUS_LU) == 0) { 3584 DPRINTF(WM_DEBUG_LINK, 3585 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3586 sc->sc_tbi_linkup = 0; 3587 } else { 3588 DPRINTF(WM_DEBUG_LINK, 3589 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3590 (status & STATUS_FD) ? "FDX" : "HDX")); 3591 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3592 sc->sc_fcrtl &= ~FCRTL_XONE; 3593 if (status & STATUS_FD) 3594 sc->sc_tctl |= 3595 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3596 else 3597 sc->sc_tctl |= 3598 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3599 if (ctrl & CTRL_TFCE) 3600 sc->sc_fcrtl |= FCRTL_XONE; 3601 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3602 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3603 WMREG_OLD_FCRTL : WMREG_FCRTL, 3604 sc->sc_fcrtl); 3605 sc->sc_tbi_linkup = 1; 3606 } 3607 3608 wm_tbi_set_linkled(sc); 3609 } 3610 3611 /* 3612 * wm_gmii_reset: 3613 * 3614 * Reset the PHY. 3615 */ 3616 static void 3617 wm_gmii_reset(struct wm_softc *sc) 3618 { 3619 uint32_t reg; 3620 3621 if (sc->sc_type >= WM_T_82544) { 3622 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3623 delay(20000); 3624 3625 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3626 delay(20000); 3627 } else { 3628 /* The PHY reset pin is active-low. */ 3629 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3630 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3631 CTRL_EXT_SWDPIN(4)); 3632 reg |= CTRL_EXT_SWDPIO(4); 3633 3634 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3635 delay(10); 3636 3637 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3638 delay(10); 3639 3640 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3641 delay(10); 3642 #if 0 3643 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3644 #endif 3645 } 3646 } 3647 3648 /* 3649 * wm_gmii_mediainit: 3650 * 3651 * Initialize media for use on 1000BASE-T devices. 3652 */ 3653 static void 3654 wm_gmii_mediainit(struct wm_softc *sc) 3655 { 3656 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3657 3658 /* We have MII. */ 3659 sc->sc_flags |= WM_F_HAS_MII; 3660 3661 sc->sc_tipg = TIPG_1000T_DFLT; 3662 3663 /* 3664 * Let the chip set speed/duplex on its own based on 3665 * signals from the PHY. 3666 */ 3667 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3668 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3669 3670 /* Initialize our media structures and probe the GMII. */ 3671 sc->sc_mii.mii_ifp = ifp; 3672 3673 if (sc->sc_type >= WM_T_82544) { 3674 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3675 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3676 } else { 3677 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3678 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3679 } 3680 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3681 3682 wm_gmii_reset(sc); 3683 3684 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3685 wm_gmii_mediastatus); 3686 3687 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3688 MII_OFFSET_ANY, MIIF_DOPAUSE); 3689 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3690 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3691 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3692 } else 3693 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3694 } 3695 3696 /* 3697 * wm_gmii_mediastatus: [ifmedia interface function] 3698 * 3699 * Get the current interface media status on a 1000BASE-T device. 3700 */ 3701 static void 3702 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3703 { 3704 struct wm_softc *sc = ifp->if_softc; 3705 3706 mii_pollstat(&sc->sc_mii); 3707 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3708 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3709 sc->sc_flowflags; 3710 } 3711 3712 /* 3713 * wm_gmii_mediachange: [ifmedia interface function] 3714 * 3715 * Set hardware to newly-selected media on a 1000BASE-T device. 3716 */ 3717 static int 3718 wm_gmii_mediachange(struct ifnet *ifp) 3719 { 3720 struct wm_softc *sc = ifp->if_softc; 3721 3722 if (ifp->if_flags & IFF_UP) 3723 mii_mediachg(&sc->sc_mii); 3724 return (0); 3725 } 3726 3727 #define MDI_IO CTRL_SWDPIN(2) 3728 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3729 #define MDI_CLK CTRL_SWDPIN(3) 3730 3731 static void 3732 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3733 { 3734 uint32_t i, v; 3735 3736 v = CSR_READ(sc, WMREG_CTRL); 3737 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3738 v |= MDI_DIR | CTRL_SWDPIO(3); 3739 3740 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3741 if (data & i) 3742 v |= MDI_IO; 3743 else 3744 v &= ~MDI_IO; 3745 CSR_WRITE(sc, WMREG_CTRL, v); 3746 delay(10); 3747 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3748 delay(10); 3749 CSR_WRITE(sc, WMREG_CTRL, v); 3750 delay(10); 3751 } 3752 } 3753 3754 static uint32_t 3755 i82543_mii_recvbits(struct wm_softc *sc) 3756 { 3757 uint32_t v, i, data = 0; 3758 3759 v = CSR_READ(sc, WMREG_CTRL); 3760 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3761 v |= CTRL_SWDPIO(3); 3762 3763 CSR_WRITE(sc, WMREG_CTRL, v); 3764 delay(10); 3765 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3766 delay(10); 3767 CSR_WRITE(sc, WMREG_CTRL, v); 3768 delay(10); 3769 3770 for (i = 0; i < 16; i++) { 3771 data <<= 1; 3772 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3773 delay(10); 3774 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3775 data |= 1; 3776 CSR_WRITE(sc, WMREG_CTRL, v); 3777 delay(10); 3778 } 3779 3780 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3781 delay(10); 3782 CSR_WRITE(sc, WMREG_CTRL, v); 3783 delay(10); 3784 3785 return (data); 3786 } 3787 3788 #undef MDI_IO 3789 #undef MDI_DIR 3790 #undef MDI_CLK 3791 3792 /* 3793 * wm_gmii_i82543_readreg: [mii interface function] 3794 * 3795 * Read a PHY register on the GMII (i82543 version). 3796 */ 3797 static int 3798 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3799 { 3800 struct wm_softc *sc = (void *) self; 3801 int rv; 3802 3803 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3804 i82543_mii_sendbits(sc, reg | (phy << 5) | 3805 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3806 rv = i82543_mii_recvbits(sc) & 0xffff; 3807 3808 DPRINTF(WM_DEBUG_GMII, 3809 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3810 sc->sc_dev.dv_xname, phy, reg, rv)); 3811 3812 return (rv); 3813 } 3814 3815 /* 3816 * wm_gmii_i82543_writereg: [mii interface function] 3817 * 3818 * Write a PHY register on the GMII (i82543 version). 3819 */ 3820 static void 3821 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3822 { 3823 struct wm_softc *sc = (void *) self; 3824 3825 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3826 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3827 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3828 (MII_COMMAND_START << 30), 32); 3829 } 3830 3831 /* 3832 * wm_gmii_i82544_readreg: [mii interface function] 3833 * 3834 * Read a PHY register on the GMII. 3835 */ 3836 static int 3837 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3838 { 3839 struct wm_softc *sc = (void *) self; 3840 uint32_t mdic = 0; 3841 int i, rv; 3842 3843 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3844 MDIC_REGADD(reg)); 3845 3846 for (i = 0; i < 100; i++) { 3847 mdic = CSR_READ(sc, WMREG_MDIC); 3848 if (mdic & MDIC_READY) 3849 break; 3850 delay(10); 3851 } 3852 3853 if ((mdic & MDIC_READY) == 0) { 3854 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3855 sc->sc_dev.dv_xname, phy, reg); 3856 rv = 0; 3857 } else if (mdic & MDIC_E) { 3858 #if 0 /* This is normal if no PHY is present. */ 3859 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3860 sc->sc_dev.dv_xname, phy, reg); 3861 #endif 3862 rv = 0; 3863 } else { 3864 rv = MDIC_DATA(mdic); 3865 if (rv == 0xffff) 3866 rv = 0; 3867 } 3868 3869 return (rv); 3870 } 3871 3872 /* 3873 * wm_gmii_i82544_writereg: [mii interface function] 3874 * 3875 * Write a PHY register on the GMII. 3876 */ 3877 static void 3878 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3879 { 3880 struct wm_softc *sc = (void *) self; 3881 uint32_t mdic = 0; 3882 int i; 3883 3884 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3885 MDIC_REGADD(reg) | MDIC_DATA(val)); 3886 3887 for (i = 0; i < 100; i++) { 3888 mdic = CSR_READ(sc, WMREG_MDIC); 3889 if (mdic & MDIC_READY) 3890 break; 3891 delay(10); 3892 } 3893 3894 if ((mdic & MDIC_READY) == 0) 3895 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3896 sc->sc_dev.dv_xname, phy, reg); 3897 else if (mdic & MDIC_E) 3898 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3899 sc->sc_dev.dv_xname, phy, reg); 3900 } 3901 3902 /* 3903 * wm_gmii_statchg: [mii interface function] 3904 * 3905 * Callback from MII layer when media changes. 3906 */ 3907 static void 3908 wm_gmii_statchg(struct device *self) 3909 { 3910 struct wm_softc *sc = (void *) self; 3911 struct mii_data *mii = &sc->sc_mii; 3912 3913 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3914 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3915 sc->sc_fcrtl &= ~FCRTL_XONE; 3916 3917 /* 3918 * Get flow control negotiation result. 3919 */ 3920 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3921 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3922 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3923 mii->mii_media_active &= ~IFM_ETH_FMASK; 3924 } 3925 3926 if (sc->sc_flowflags & IFM_FLOW) { 3927 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3928 sc->sc_ctrl |= CTRL_TFCE; 3929 sc->sc_fcrtl |= FCRTL_XONE; 3930 } 3931 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3932 sc->sc_ctrl |= CTRL_RFCE; 3933 } 3934 3935 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3936 DPRINTF(WM_DEBUG_LINK, 3937 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3938 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3939 } else { 3940 DPRINTF(WM_DEBUG_LINK, 3941 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3942 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3943 } 3944 3945 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3946 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3947 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3948 : WMREG_FCRTL, sc->sc_fcrtl); 3949 } 3950
Indexes created Tue Sep 23 14:10:03 GMT 2025