if_wm.c revision 1.113
1 /* $NetBSD: if_wm.c,v 1.113 2006/02/22 00:17:43 gavan Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.113 2006/02/22 00:17:43 gavan Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make several things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 280 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 281 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 282 283 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 284 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 285 286 struct evcnt sc_ev_tu; /* Tx underrun */ 287 288 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 289 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 290 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 291 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 292 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 293 #endif /* WM_EVENT_COUNTERS */ 294 295 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 296 297 int sc_txfree; /* number of free Tx descriptors */ 298 int sc_txnext; /* next ready Tx descriptor */ 299 300 int sc_txsfree; /* number of free Tx jobs */ 301 int sc_txsnext; /* next free Tx job */ 302 int sc_txsdirty; /* dirty Tx jobs */ 303 304 /* These 5 variables are used only on the 82547. */ 305 int sc_txfifo_size; /* Tx FIFO size */ 306 int sc_txfifo_head; /* current head of FIFO */ 307 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 308 int sc_txfifo_stall; /* Tx FIFO is stalled */ 309 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 310 311 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 312 313 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 314 int sc_rxdiscard; 315 int sc_rxlen; 316 struct mbuf *sc_rxhead; 317 struct mbuf *sc_rxtail; 318 struct mbuf **sc_rxtailp; 319 320 uint32_t sc_ctrl; /* prototype CTRL register */ 321 #if 0 322 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 323 #endif 324 uint32_t sc_icr; /* prototype interrupt bits */ 325 uint32_t sc_itr; /* prototype intr throttling reg */ 326 uint32_t sc_tctl; /* prototype TCTL register */ 327 uint32_t sc_rctl; /* prototype RCTL register */ 328 uint32_t sc_txcw; /* prototype TXCW register */ 329 uint32_t sc_tipg; /* prototype TIPG register */ 330 uint32_t sc_fcrtl; /* prototype FCRTL register */ 331 uint32_t sc_pba; /* prototype PBA register */ 332 333 int sc_tbi_linkup; /* TBI link status */ 334 int sc_tbi_anstate; /* autonegotiation state */ 335 336 int sc_mchash_type; /* multicast filter offset */ 337 338 #if NRND > 0 339 rndsource_element_t rnd_source; /* random source */ 340 #endif 341 }; 342 343 #define WM_RXCHAIN_RESET(sc) \ 344 do { \ 345 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 346 *(sc)->sc_rxtailp = NULL; \ 347 (sc)->sc_rxlen = 0; \ 348 } while (/*CONSTCOND*/0) 349 350 #define WM_RXCHAIN_LINK(sc, m) \ 351 do { \ 352 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 353 (sc)->sc_rxtailp = &(m)->m_next; \ 354 } while (/*CONSTCOND*/0) 355 356 /* sc_flags */ 357 #define WM_F_HAS_MII 0x01 /* has MII */ 358 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 359 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 360 #define WM_F_EEPROM_INVALID 0x08 /* EEPROM not present (bad checksum) */ 361 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 362 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 363 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 364 #define WM_F_CSA 0x80 /* bus is CSA */ 365 366 #ifdef WM_EVENT_COUNTERS 367 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 368 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 369 #else 370 #define WM_EVCNT_INCR(ev) /* nothing */ 371 #define WM_EVCNT_ADD(ev, val) /* nothing */ 372 #endif 373 374 #define CSR_READ(sc, reg) \ 375 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 376 #define CSR_WRITE(sc, reg, val) \ 377 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 378 #define CSR_WRITE_FLUSH(sc) \ 379 (void) CSR_READ((sc), WMREG_STATUS) 380 381 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 382 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 383 384 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 385 #define WM_CDTXADDR_HI(sc, x) \ 386 (sizeof(bus_addr_t) == 8 ? \ 387 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 388 389 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 390 #define WM_CDRXADDR_HI(sc, x) \ 391 (sizeof(bus_addr_t) == 8 ? \ 392 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 393 394 #define WM_CDTXSYNC(sc, x, n, ops) \ 395 do { \ 396 int __x, __n; \ 397 \ 398 __x = (x); \ 399 __n = (n); \ 400 \ 401 /* If it will wrap around, sync to the end of the ring. */ \ 402 if ((__x + __n) > WM_NTXDESC(sc)) { \ 403 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 404 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 405 (WM_NTXDESC(sc) - __x), (ops)); \ 406 __n -= (WM_NTXDESC(sc) - __x); \ 407 __x = 0; \ 408 } \ 409 \ 410 /* Now sync whatever is left. */ \ 411 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 412 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 413 } while (/*CONSTCOND*/0) 414 415 #define WM_CDRXSYNC(sc, x, ops) \ 416 do { \ 417 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 418 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 419 } while (/*CONSTCOND*/0) 420 421 #define WM_INIT_RXDESC(sc, x) \ 422 do { \ 423 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 424 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 425 struct mbuf *__m = __rxs->rxs_mbuf; \ 426 \ 427 /* \ 428 * Note: We scoot the packet forward 2 bytes in the buffer \ 429 * so that the payload after the Ethernet header is aligned \ 430 * to a 4-byte boundary. \ 431 * \ 432 * XXX BRAINDAMAGE ALERT! \ 433 * The stupid chip uses the same size for every buffer, which \ 434 * is set in the Receive Control register. We are using the 2K \ 435 * size option, but what we REALLY want is (2K - 2)! For this \ 436 * reason, we can't "scoot" packets longer than the standard \ 437 * Ethernet MTU. On strict-alignment platforms, if the total \ 438 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 439 * the upper layer copy the headers. \ 440 */ \ 441 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 442 \ 443 wm_set_dma_addr(&__rxd->wrx_addr, \ 444 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 445 __rxd->wrx_len = 0; \ 446 __rxd->wrx_cksum = 0; \ 447 __rxd->wrx_status = 0; \ 448 __rxd->wrx_errors = 0; \ 449 __rxd->wrx_special = 0; \ 450 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 451 \ 452 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 453 } while (/*CONSTCOND*/0) 454 455 static void wm_start(struct ifnet *); 456 static void wm_watchdog(struct ifnet *); 457 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 458 static int wm_init(struct ifnet *); 459 static void wm_stop(struct ifnet *, int); 460 461 static void wm_shutdown(void *); 462 463 static void wm_reset(struct wm_softc *); 464 static void wm_rxdrain(struct wm_softc *); 465 static int wm_add_rxbuf(struct wm_softc *, int); 466 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 467 static int wm_validate_eeprom_checksum(struct wm_softc *); 468 static void wm_tick(void *); 469 470 static void wm_set_filter(struct wm_softc *); 471 472 static int wm_intr(void *); 473 static void wm_txintr(struct wm_softc *); 474 static void wm_rxintr(struct wm_softc *); 475 static void wm_linkintr(struct wm_softc *, uint32_t); 476 477 static void wm_tbi_mediainit(struct wm_softc *); 478 static int wm_tbi_mediachange(struct ifnet *); 479 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 480 481 static void wm_tbi_set_linkled(struct wm_softc *); 482 static void wm_tbi_check_link(struct wm_softc *); 483 484 static void wm_gmii_reset(struct wm_softc *); 485 486 static int wm_gmii_i82543_readreg(struct device *, int, int); 487 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 488 489 static int wm_gmii_i82544_readreg(struct device *, int, int); 490 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 491 492 static void wm_gmii_statchg(struct device *); 493 494 static void wm_gmii_mediainit(struct wm_softc *); 495 static int wm_gmii_mediachange(struct ifnet *); 496 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 497 498 static int wm_match(struct device *, struct cfdata *, void *); 499 static void wm_attach(struct device *, struct device *, void *); 500 501 CFATTACH_DECL(wm, sizeof(struct wm_softc), 502 wm_match, wm_attach, NULL, NULL); 503 504 static void wm_82547_txfifo_stall(void *); 505 506 /* 507 * Devices supported by this driver. 508 */ 509 static const struct wm_product { 510 pci_vendor_id_t wmp_vendor; 511 pci_product_id_t wmp_product; 512 const char *wmp_name; 513 wm_chip_type wmp_type; 514 int wmp_flags; 515 #define WMP_F_1000X 0x01 516 #define WMP_F_1000T 0x02 517 } wm_products[] = { 518 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 519 "Intel i82542 1000BASE-X Ethernet", 520 WM_T_82542_2_1, WMP_F_1000X }, 521 522 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 523 "Intel i82543GC 1000BASE-X Ethernet", 524 WM_T_82543, WMP_F_1000X }, 525 526 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 527 "Intel i82543GC 1000BASE-T Ethernet", 528 WM_T_82543, WMP_F_1000T }, 529 530 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 531 "Intel i82544EI 1000BASE-T Ethernet", 532 WM_T_82544, WMP_F_1000T }, 533 534 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 535 "Intel i82544EI 1000BASE-X Ethernet", 536 WM_T_82544, WMP_F_1000X }, 537 538 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 539 "Intel i82544GC 1000BASE-T Ethernet", 540 WM_T_82544, WMP_F_1000T }, 541 542 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 543 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 544 WM_T_82544, WMP_F_1000T }, 545 546 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 547 "Intel i82540EM 1000BASE-T Ethernet", 548 WM_T_82540, WMP_F_1000T }, 549 550 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 551 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 552 WM_T_82540, WMP_F_1000T }, 553 554 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 555 "Intel i82540EP 1000BASE-T Ethernet", 556 WM_T_82540, WMP_F_1000T }, 557 558 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 559 "Intel i82540EP 1000BASE-T Ethernet", 560 WM_T_82540, WMP_F_1000T }, 561 562 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 563 "Intel i82540EP 1000BASE-T Ethernet", 564 WM_T_82540, WMP_F_1000T }, 565 566 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 567 "Intel i82545EM 1000BASE-T Ethernet", 568 WM_T_82545, WMP_F_1000T }, 569 570 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 571 "Intel i82545GM 1000BASE-T Ethernet", 572 WM_T_82545_3, WMP_F_1000T }, 573 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 575 "Intel i82545GM 1000BASE-X Ethernet", 576 WM_T_82545_3, WMP_F_1000X }, 577 #if 0 578 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 579 "Intel i82545GM Gigabit Ethernet (SERDES)", 580 WM_T_82545_3, WMP_F_SERDES }, 581 #endif 582 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 583 "Intel i82546EB 1000BASE-T Ethernet", 584 WM_T_82546, WMP_F_1000T }, 585 586 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 587 "Intel i82546EB 1000BASE-T Ethernet", 588 WM_T_82546, WMP_F_1000T }, 589 590 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 591 "Intel i82545EM 1000BASE-X Ethernet", 592 WM_T_82545, WMP_F_1000X }, 593 594 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 595 "Intel i82546EB 1000BASE-X Ethernet", 596 WM_T_82546, WMP_F_1000X }, 597 598 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 599 "Intel i82546GB 1000BASE-T Ethernet", 600 WM_T_82546_3, WMP_F_1000T }, 601 602 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 603 "Intel i82546GB 1000BASE-X Ethernet", 604 WM_T_82546_3, WMP_F_1000X }, 605 #if 0 606 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 607 "Intel i82546GB Gigabit Ethernet (SERDES)", 608 WM_T_82546_3, WMP_F_SERDES }, 609 #endif 610 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 611 "Intel i82541EI 1000BASE-T Ethernet", 612 WM_T_82541, WMP_F_1000T }, 613 614 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 615 "Intel i82541EI Mobile 1000BASE-T Ethernet", 616 WM_T_82541, WMP_F_1000T }, 617 618 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 619 "Intel i82541ER 1000BASE-T Ethernet", 620 WM_T_82541_2, WMP_F_1000T }, 621 622 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 623 "Intel i82541GI 1000BASE-T Ethernet", 624 WM_T_82541_2, WMP_F_1000T }, 625 626 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 627 "Intel i82541GI Mobile 1000BASE-T Ethernet", 628 WM_T_82541_2, WMP_F_1000T }, 629 630 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 631 "Intel i82541PI 1000BASE-T Ethernet", 632 WM_T_82541_2, WMP_F_1000T }, 633 634 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 635 "Intel i82547EI 1000BASE-T Ethernet", 636 WM_T_82547, WMP_F_1000T }, 637 638 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 639 "Intel i82547GI 1000BASE-T Ethernet", 640 WM_T_82547_2, WMP_F_1000T }, 641 { 0, 0, 642 NULL, 643 0, 0 }, 644 }; 645 646 #ifdef WM_EVENT_COUNTERS 647 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 648 #endif /* WM_EVENT_COUNTERS */ 649 650 #if 0 /* Not currently used */ 651 static inline uint32_t 652 wm_io_read(struct wm_softc *sc, int reg) 653 { 654 655 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 656 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 657 } 658 #endif 659 660 static inline void 661 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 662 { 663 664 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 665 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 666 } 667 668 static inline void 669 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 670 { 671 wa->wa_low = htole32(v & 0xffffffffU); 672 if (sizeof(bus_addr_t) == 8) 673 wa->wa_high = htole32((uint64_t) v >> 32); 674 else 675 wa->wa_high = 0; 676 } 677 678 static const struct wm_product * 679 wm_lookup(const struct pci_attach_args *pa) 680 { 681 const struct wm_product *wmp; 682 683 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 684 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 685 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 686 return (wmp); 687 } 688 return (NULL); 689 } 690 691 static int 692 wm_match(struct device *parent, struct cfdata *cf, void *aux) 693 { 694 struct pci_attach_args *pa = aux; 695 696 if (wm_lookup(pa) != NULL) 697 return (1); 698 699 return (0); 700 } 701 702 static void 703 wm_attach(struct device *parent, struct device *self, void *aux) 704 { 705 struct wm_softc *sc = (void *) self; 706 struct pci_attach_args *pa = aux; 707 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 708 pci_chipset_tag_t pc = pa->pa_pc; 709 pci_intr_handle_t ih; 710 size_t cdata_size; 711 const char *intrstr = NULL; 712 const char *eetype; 713 bus_space_tag_t memt; 714 bus_space_handle_t memh; 715 bus_dma_segment_t seg; 716 int memh_valid; 717 int i, rseg, error; 718 const struct wm_product *wmp; 719 uint8_t enaddr[ETHER_ADDR_LEN]; 720 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 721 pcireg_t preg, memtype; 722 uint32_t reg; 723 int pmreg; 724 725 callout_init(&sc->sc_tick_ch); 726 727 wmp = wm_lookup(pa); 728 if (wmp == NULL) { 729 printf("\n"); 730 panic("wm_attach: impossible"); 731 } 732 733 if (pci_dma64_available(pa)) 734 sc->sc_dmat = pa->pa_dmat64; 735 else 736 sc->sc_dmat = pa->pa_dmat; 737 738 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 739 aprint_naive(": Ethernet controller\n"); 740 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 741 742 sc->sc_type = wmp->wmp_type; 743 if (sc->sc_type < WM_T_82543) { 744 if (preg < 2) { 745 aprint_error("%s: i82542 must be at least rev. 2\n", 746 sc->sc_dev.dv_xname); 747 return; 748 } 749 if (preg < 3) 750 sc->sc_type = WM_T_82542_2_0; 751 } 752 753 /* 754 * Map the device. All devices support memory-mapped acccess, 755 * and it is really required for normal operation. 756 */ 757 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 758 switch (memtype) { 759 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 760 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 761 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 762 memtype, 0, &memt, &memh, NULL, NULL) == 0); 763 break; 764 default: 765 memh_valid = 0; 766 } 767 768 if (memh_valid) { 769 sc->sc_st = memt; 770 sc->sc_sh = memh; 771 } else { 772 aprint_error("%s: unable to map device registers\n", 773 sc->sc_dev.dv_xname); 774 return; 775 } 776 777 /* 778 * In addition, i82544 and later support I/O mapped indirect 779 * register access. It is not desirable (nor supported in 780 * this driver) to use it for normal operation, though it is 781 * required to work around bugs in some chip versions. 782 */ 783 if (sc->sc_type >= WM_T_82544) { 784 /* First we have to find the I/O BAR. */ 785 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 786 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 787 PCI_MAPREG_TYPE_IO) 788 break; 789 } 790 if (i == PCI_MAPREG_END) 791 aprint_error("%s: WARNING: unable to find I/O BAR\n", 792 sc->sc_dev.dv_xname); 793 else { 794 /* 795 * The i8254x doesn't apparently respond when the 796 * I/O BAR is 0, which looks somewhat like it's not 797 * been configured. 798 */ 799 preg = pci_conf_read(pc, pa->pa_tag, i); 800 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 801 aprint_error("%s: WARNING: I/O BAR at zero.\n", 802 sc->sc_dev.dv_xname); 803 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 804 0, &sc->sc_iot, &sc->sc_ioh, 805 NULL, NULL) == 0) { 806 sc->sc_flags |= WM_F_IOH_VALID; 807 } else { 808 aprint_error("%s: WARNING: unable to map " 809 "I/O space\n", sc->sc_dev.dv_xname); 810 } 811 } 812 813 } 814 815 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 816 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 817 preg |= PCI_COMMAND_MASTER_ENABLE; 818 if (sc->sc_type < WM_T_82542_2_1) 819 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 820 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 821 822 /* Get it out of power save mode, if needed. */ 823 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 824 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 825 PCI_PMCSR_STATE_MASK; 826 if (preg == PCI_PMCSR_STATE_D3) { 827 /* 828 * The card has lost all configuration data in 829 * this state, so punt. 830 */ 831 aprint_error("%s: unable to wake from power state D3\n", 832 sc->sc_dev.dv_xname); 833 return; 834 } 835 if (preg != PCI_PMCSR_STATE_D0) { 836 aprint_normal("%s: waking up from power state D%d\n", 837 sc->sc_dev.dv_xname, preg); 838 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 839 PCI_PMCSR_STATE_D0); 840 } 841 } 842 843 /* 844 * Map and establish our interrupt. 845 */ 846 if (pci_intr_map(pa, &ih)) { 847 aprint_error("%s: unable to map interrupt\n", 848 sc->sc_dev.dv_xname); 849 return; 850 } 851 intrstr = pci_intr_string(pc, ih); 852 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 853 if (sc->sc_ih == NULL) { 854 aprint_error("%s: unable to establish interrupt", 855 sc->sc_dev.dv_xname); 856 if (intrstr != NULL) 857 aprint_normal(" at %s", intrstr); 858 aprint_normal("\n"); 859 return; 860 } 861 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 862 863 /* 864 * Determine a few things about the bus we're connected to. 865 */ 866 if (sc->sc_type < WM_T_82543) { 867 /* We don't really know the bus characteristics here. */ 868 sc->sc_bus_speed = 33; 869 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 870 /* 871 * CSA (Communication Streaming Architecture) is about as fast 872 * a 32-bit 66MHz PCI Bus. 873 */ 874 sc->sc_flags |= WM_F_CSA; 875 sc->sc_bus_speed = 66; 876 aprint_verbose("%s: Communication Streaming Architecture\n", 877 sc->sc_dev.dv_xname); 878 if (sc->sc_type == WM_T_82547) { 879 callout_init(&sc->sc_txfifo_ch); 880 callout_setfunc(&sc->sc_txfifo_ch, 881 wm_82547_txfifo_stall, sc); 882 aprint_verbose("%s: using 82547 Tx FIFO stall " 883 "work-around\n", sc->sc_dev.dv_xname); 884 } 885 } else { 886 reg = CSR_READ(sc, WMREG_STATUS); 887 if (reg & STATUS_BUS64) 888 sc->sc_flags |= WM_F_BUS64; 889 if (sc->sc_type >= WM_T_82544 && 890 (reg & STATUS_PCIX_MODE) != 0) { 891 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 892 893 sc->sc_flags |= WM_F_PCIX; 894 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 895 PCI_CAP_PCIX, 896 &sc->sc_pcix_offset, NULL) == 0) 897 aprint_error("%s: unable to find PCIX " 898 "capability\n", sc->sc_dev.dv_xname); 899 else if (sc->sc_type != WM_T_82545_3 && 900 sc->sc_type != WM_T_82546_3) { 901 /* 902 * Work around a problem caused by the BIOS 903 * setting the max memory read byte count 904 * incorrectly. 905 */ 906 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 907 sc->sc_pcix_offset + PCI_PCIX_CMD); 908 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 909 sc->sc_pcix_offset + PCI_PCIX_STATUS); 910 911 bytecnt = 912 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 913 PCI_PCIX_CMD_BYTECNT_SHIFT; 914 maxb = 915 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 916 PCI_PCIX_STATUS_MAXB_SHIFT; 917 if (bytecnt > maxb) { 918 aprint_verbose("%s: resetting PCI-X " 919 "MMRBC: %d -> %d\n", 920 sc->sc_dev.dv_xname, 921 512 << bytecnt, 512 << maxb); 922 pcix_cmd = (pcix_cmd & 923 ~PCI_PCIX_CMD_BYTECNT_MASK) | 924 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 925 pci_conf_write(pa->pa_pc, pa->pa_tag, 926 sc->sc_pcix_offset + PCI_PCIX_CMD, 927 pcix_cmd); 928 } 929 } 930 } 931 /* 932 * The quad port adapter is special; it has a PCIX-PCIX 933 * bridge on the board, and can run the secondary bus at 934 * a higher speed. 935 */ 936 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 937 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 938 : 66; 939 } else if (sc->sc_flags & WM_F_PCIX) { 940 switch (reg & STATUS_PCIXSPD_MASK) { 941 case STATUS_PCIXSPD_50_66: 942 sc->sc_bus_speed = 66; 943 break; 944 case STATUS_PCIXSPD_66_100: 945 sc->sc_bus_speed = 100; 946 break; 947 case STATUS_PCIXSPD_100_133: 948 sc->sc_bus_speed = 133; 949 break; 950 default: 951 aprint_error( 952 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 953 sc->sc_dev.dv_xname, 954 reg & STATUS_PCIXSPD_MASK); 955 sc->sc_bus_speed = 66; 956 } 957 } else 958 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 959 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 960 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 961 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 962 } 963 964 /* 965 * Allocate the control data structures, and create and load the 966 * DMA map for it. 967 * 968 * NOTE: All Tx descriptors must be in the same 4G segment of 969 * memory. So must Rx descriptors. We simplify by allocating 970 * both sets within the same 4G segment. 971 */ 972 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 973 WM_NTXDESC_82542 : WM_NTXDESC_82544; 974 cdata_size = sc->sc_type < WM_T_82544 ? 975 sizeof(struct wm_control_data_82542) : 976 sizeof(struct wm_control_data_82544); 977 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 978 (bus_size_t) 0x100000000ULL, 979 &seg, 1, &rseg, 0)) != 0) { 980 aprint_error( 981 "%s: unable to allocate control data, error = %d\n", 982 sc->sc_dev.dv_xname, error); 983 goto fail_0; 984 } 985 986 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 987 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 988 aprint_error("%s: unable to map control data, error = %d\n", 989 sc->sc_dev.dv_xname, error); 990 goto fail_1; 991 } 992 993 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 994 0, 0, &sc->sc_cddmamap)) != 0) { 995 aprint_error("%s: unable to create control data DMA map, " 996 "error = %d\n", sc->sc_dev.dv_xname, error); 997 goto fail_2; 998 } 999 1000 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1001 sc->sc_control_data, cdata_size, NULL, 1002 0)) != 0) { 1003 aprint_error( 1004 "%s: unable to load control data DMA map, error = %d\n", 1005 sc->sc_dev.dv_xname, error); 1006 goto fail_3; 1007 } 1008 1009 1010 /* 1011 * Create the transmit buffer DMA maps. 1012 */ 1013 WM_TXQUEUELEN(sc) = 1014 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1015 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1016 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1017 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1018 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1019 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1020 aprint_error("%s: unable to create Tx DMA map %d, " 1021 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1022 goto fail_4; 1023 } 1024 } 1025 1026 /* 1027 * Create the receive buffer DMA maps. 1028 */ 1029 for (i = 0; i < WM_NRXDESC; i++) { 1030 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1031 MCLBYTES, 0, 0, 1032 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1033 aprint_error("%s: unable to create Rx DMA map %d, " 1034 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1035 goto fail_5; 1036 } 1037 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1038 } 1039 1040 /* 1041 * Reset the chip to a known state. 1042 */ 1043 wm_reset(sc); 1044 1045 /* 1046 * Get some information about the EEPROM. 1047 */ 1048 if (sc->sc_type >= WM_T_82540) 1049 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1050 if (sc->sc_type <= WM_T_82544) 1051 sc->sc_ee_addrbits = 6; 1052 else if (sc->sc_type <= WM_T_82546_3) { 1053 reg = CSR_READ(sc, WMREG_EECD); 1054 if (reg & EECD_EE_SIZE) 1055 sc->sc_ee_addrbits = 8; 1056 else 1057 sc->sc_ee_addrbits = 6; 1058 } else if (sc->sc_type <= WM_T_82547_2) { 1059 reg = CSR_READ(sc, WMREG_EECD); 1060 if (reg & EECD_EE_TYPE) { 1061 sc->sc_flags |= WM_F_EEPROM_SPI; 1062 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1063 } else 1064 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1065 } else { 1066 /* Assume everything else is SPI. */ 1067 reg = CSR_READ(sc, WMREG_EECD); 1068 sc->sc_flags |= WM_F_EEPROM_SPI; 1069 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1070 } 1071 1072 /* 1073 * Defer printing the EEPROM type until after verifying the checksum 1074 * This allows the EEPROM type to be printed correctly in the case 1075 * that no EEPROM is attached. 1076 */ 1077 1078 1079 /* 1080 * Validate the EEPROM checksum. If the checksum fails, flag this for 1081 * later, so we can fail future reads from the EEPROM. 1082 */ 1083 if (wm_validate_eeprom_checksum(sc)) 1084 sc->sc_flags |= WM_F_EEPROM_INVALID; 1085 1086 if (sc->sc_flags & WM_F_EEPROM_INVALID) 1087 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname); 1088 else { 1089 if (sc->sc_flags & WM_F_EEPROM_SPI) 1090 eetype = "SPI"; 1091 else 1092 eetype = "MicroWire"; 1093 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1094 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1095 sc->sc_ee_addrbits, eetype); 1096 } 1097 1098 /* 1099 * Read the Ethernet address from the EEPROM, if not first found 1100 * in device properties. 1101 */ 1102 if (devprop_get(&sc->sc_dev, "mac-addr", 1103 enaddr, sizeof(enaddr), NULL) != sizeof(enaddr)) { 1104 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1105 sizeof(myea) / sizeof(myea[0]), myea)) { 1106 aprint_error("%s: unable to read Ethernet address\n", 1107 sc->sc_dev.dv_xname); 1108 return; 1109 } 1110 enaddr[0] = myea[0] & 0xff; 1111 enaddr[1] = myea[0] >> 8; 1112 enaddr[2] = myea[1] & 0xff; 1113 enaddr[3] = myea[1] >> 8; 1114 enaddr[4] = myea[2] & 0xff; 1115 enaddr[5] = myea[2] >> 8; 1116 } 1117 1118 /* 1119 * Toggle the LSB of the MAC address on the second port 1120 * of the i82546. 1121 */ 1122 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1123 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1124 enaddr[5] ^= 1; 1125 } 1126 1127 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1128 ether_sprintf(enaddr)); 1129 1130 /* 1131 * Read the config info from the EEPROM, and set up various 1132 * bits in the control registers based on their contents. 1133 */ 1134 if (devprop_get(&sc->sc_dev, "cfg1", 1135 &cfg1, sizeof(cfg1), NULL) != sizeof(cfg1)) { 1136 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1137 aprint_error("%s: unable to read CFG1\n", 1138 sc->sc_dev.dv_xname); 1139 return; 1140 } 1141 } 1142 if (devprop_get(&sc->sc_dev, "cfg2", 1143 &cfg2, sizeof(cfg2), NULL) != sizeof(cfg2)) { 1144 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1145 aprint_error("%s: unable to read CFG2\n", 1146 sc->sc_dev.dv_xname); 1147 return; 1148 } 1149 } 1150 if (sc->sc_type >= WM_T_82544) { 1151 if (devprop_get(&sc->sc_dev, "swdpin", 1152 &swdpin, sizeof(swdpin), NULL) != sizeof(swdpin)) { 1153 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1154 aprint_error("%s: unable to read SWDPIN\n", 1155 sc->sc_dev.dv_xname); 1156 return; 1157 } 1158 } 1159 } 1160 1161 if (cfg1 & EEPROM_CFG1_ILOS) 1162 sc->sc_ctrl |= CTRL_ILOS; 1163 if (sc->sc_type >= WM_T_82544) { 1164 sc->sc_ctrl |= 1165 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1166 CTRL_SWDPIO_SHIFT; 1167 sc->sc_ctrl |= 1168 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1169 CTRL_SWDPINS_SHIFT; 1170 } else { 1171 sc->sc_ctrl |= 1172 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1173 CTRL_SWDPIO_SHIFT; 1174 } 1175 1176 #if 0 1177 if (sc->sc_type >= WM_T_82544) { 1178 if (cfg1 & EEPROM_CFG1_IPS0) 1179 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1180 if (cfg1 & EEPROM_CFG1_IPS1) 1181 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1182 sc->sc_ctrl_ext |= 1183 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1184 CTRL_EXT_SWDPIO_SHIFT; 1185 sc->sc_ctrl_ext |= 1186 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1187 CTRL_EXT_SWDPINS_SHIFT; 1188 } else { 1189 sc->sc_ctrl_ext |= 1190 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1191 CTRL_EXT_SWDPIO_SHIFT; 1192 } 1193 #endif 1194 1195 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1196 #if 0 1197 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1198 #endif 1199 1200 /* 1201 * Set up some register offsets that are different between 1202 * the i82542 and the i82543 and later chips. 1203 */ 1204 if (sc->sc_type < WM_T_82543) { 1205 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1206 sc->sc_tdt_reg = WMREG_OLD_TDT; 1207 } else { 1208 sc->sc_rdt_reg = WMREG_RDT; 1209 sc->sc_tdt_reg = WMREG_TDT; 1210 } 1211 1212 /* 1213 * Determine if we're TBI or GMII mode, and initialize the 1214 * media structures accordingly. 1215 */ 1216 if (sc->sc_type < WM_T_82543 || 1217 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1218 if (wmp->wmp_flags & WMP_F_1000T) 1219 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1220 "product!\n", sc->sc_dev.dv_xname); 1221 wm_tbi_mediainit(sc); 1222 } else { 1223 if (wmp->wmp_flags & WMP_F_1000X) 1224 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1225 "product!\n", sc->sc_dev.dv_xname); 1226 wm_gmii_mediainit(sc); 1227 } 1228 1229 ifp = &sc->sc_ethercom.ec_if; 1230 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1231 ifp->if_softc = sc; 1232 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1233 ifp->if_ioctl = wm_ioctl; 1234 ifp->if_start = wm_start; 1235 ifp->if_watchdog = wm_watchdog; 1236 ifp->if_init = wm_init; 1237 ifp->if_stop = wm_stop; 1238 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1239 IFQ_SET_READY(&ifp->if_snd); 1240 1241 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1242 1243 /* 1244 * If we're a i82543 or greater, we can support VLANs. 1245 */ 1246 if (sc->sc_type >= WM_T_82543) 1247 sc->sc_ethercom.ec_capabilities |= 1248 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1249 1250 /* 1251 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1252 * on i82543 and later. 1253 */ 1254 if (sc->sc_type >= WM_T_82543) 1255 ifp->if_capabilities |= 1256 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1257 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1258 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1259 IFCAP_CSUM_TCPv6_Tx | 1260 IFCAP_CSUM_UDPv6_Tx; 1261 1262 /* 1263 * If we're a i82544 or greater (except i82547), we can do 1264 * TCP segmentation offload. 1265 */ 1266 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1267 ifp->if_capabilities |= IFCAP_TSOv4; 1268 1269 /* 1270 * Attach the interface. 1271 */ 1272 if_attach(ifp); 1273 ether_ifattach(ifp, enaddr); 1274 #if NRND > 0 1275 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1276 RND_TYPE_NET, 0); 1277 #endif 1278 1279 #ifdef WM_EVENT_COUNTERS 1280 /* Attach event counters. */ 1281 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1282 NULL, sc->sc_dev.dv_xname, "txsstall"); 1283 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1284 NULL, sc->sc_dev.dv_xname, "txdstall"); 1285 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1287 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1288 NULL, sc->sc_dev.dv_xname, "txdw"); 1289 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1290 NULL, sc->sc_dev.dv_xname, "txqe"); 1291 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1292 NULL, sc->sc_dev.dv_xname, "rxintr"); 1293 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1294 NULL, sc->sc_dev.dv_xname, "linkintr"); 1295 1296 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1297 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1298 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1299 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1300 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1301 NULL, sc->sc_dev.dv_xname, "txipsum"); 1302 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1303 NULL, sc->sc_dev.dv_xname, "txtusum"); 1304 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1305 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1306 1307 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1308 NULL, sc->sc_dev.dv_xname, "txtso"); 1309 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1310 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1311 1312 for (i = 0; i < WM_NTXSEGS; i++) { 1313 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1314 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1315 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1316 } 1317 1318 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1319 NULL, sc->sc_dev.dv_xname, "txdrop"); 1320 1321 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1322 NULL, sc->sc_dev.dv_xname, "tu"); 1323 1324 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1325 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1326 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1327 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1328 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1329 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1330 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1331 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1332 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1333 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1334 #endif /* WM_EVENT_COUNTERS */ 1335 1336 /* 1337 * Make sure the interface is shutdown during reboot. 1338 */ 1339 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1340 if (sc->sc_sdhook == NULL) 1341 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1342 sc->sc_dev.dv_xname); 1343 return; 1344 1345 /* 1346 * Free any resources we've allocated during the failed attach 1347 * attempt. Do this in reverse order and fall through. 1348 */ 1349 fail_5: 1350 for (i = 0; i < WM_NRXDESC; i++) { 1351 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1352 bus_dmamap_destroy(sc->sc_dmat, 1353 sc->sc_rxsoft[i].rxs_dmamap); 1354 } 1355 fail_4: 1356 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1357 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1358 bus_dmamap_destroy(sc->sc_dmat, 1359 sc->sc_txsoft[i].txs_dmamap); 1360 } 1361 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1362 fail_3: 1363 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1364 fail_2: 1365 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1366 cdata_size); 1367 fail_1: 1368 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1369 fail_0: 1370 return; 1371 } 1372 1373 /* 1374 * wm_shutdown: 1375 * 1376 * Make sure the interface is stopped at reboot time. 1377 */ 1378 static void 1379 wm_shutdown(void *arg) 1380 { 1381 struct wm_softc *sc = arg; 1382 1383 wm_stop(&sc->sc_ethercom.ec_if, 1); 1384 } 1385 1386 /* 1387 * wm_tx_offload: 1388 * 1389 * Set up TCP/IP checksumming parameters for the 1390 * specified packet. 1391 */ 1392 static int 1393 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1394 uint8_t *fieldsp) 1395 { 1396 struct mbuf *m0 = txs->txs_mbuf; 1397 struct livengood_tcpip_ctxdesc *t; 1398 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1399 struct ether_header *eh; 1400 int offset, iphl; 1401 uint8_t fields; 1402 1403 /* 1404 * XXX It would be nice if the mbuf pkthdr had offset 1405 * fields for the protocol headers. 1406 */ 1407 1408 eh = mtod(m0, struct ether_header *); 1409 switch (htons(eh->ether_type)) { 1410 case ETHERTYPE_IP: 1411 case ETHERTYPE_IPV6: 1412 offset = ETHER_HDR_LEN; 1413 break; 1414 1415 case ETHERTYPE_VLAN: 1416 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1417 break; 1418 1419 default: 1420 /* 1421 * Don't support this protocol or encapsulation. 1422 */ 1423 *fieldsp = 0; 1424 *cmdp = 0; 1425 return (0); 1426 } 1427 1428 if ((m0->m_pkthdr.csum_flags & 1429 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1430 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1431 } else { 1432 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1433 } 1434 1435 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1436 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1437 seg = 0; 1438 fields = 0; 1439 1440 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1441 int hlen = offset + iphl; 1442 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1443 if (__predict_false(m0->m_len < 1444 (hlen + sizeof(struct tcphdr)))) { 1445 /* 1446 * TCP/IP headers are not in the first mbuf; we need 1447 * to do this the slow and painful way. Let's just 1448 * hope this doesn't happen very often. 1449 */ 1450 struct ip ip; 1451 struct tcphdr th; 1452 1453 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1454 1455 m_copydata(m0, offset, sizeof(ip), &ip); 1456 m_copydata(m0, hlen, sizeof(th), &th); 1457 1458 ip.ip_len = 0; 1459 1460 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1461 sizeof(ip.ip_len), &ip.ip_len); 1462 1463 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1464 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1465 1466 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1467 sizeof(th.th_sum), &th.th_sum); 1468 1469 hlen += th.th_off << 2; 1470 } else { 1471 /* 1472 * TCP/IP headers are in the first mbuf; we can do 1473 * this the easy way. 1474 */ 1475 struct ip *ip = 1476 (struct ip *) (mtod(m0, caddr_t) + offset); 1477 struct tcphdr *th = 1478 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1479 1480 ip->ip_len = 0; 1481 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1482 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1483 1484 hlen += th->th_off << 2; 1485 } 1486 1487 cmd |= WTX_TCPIP_CMD_TSE; 1488 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1489 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1490 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1491 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1492 } 1493 1494 /* 1495 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1496 * offload feature, if we load the context descriptor, we 1497 * MUST provide valid values for IPCSS and TUCSS fields. 1498 */ 1499 1500 ipcs = WTX_TCPIP_IPCSS(offset) | 1501 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1502 WTX_TCPIP_IPCSE(offset + iphl - 1); 1503 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1504 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1505 fields |= WTX_IXSM; 1506 } 1507 1508 offset += iphl; 1509 1510 if (m0->m_pkthdr.csum_flags & 1511 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1512 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1513 fields |= WTX_TXSM; 1514 tucs = WTX_TCPIP_TUCSS(offset) | 1515 WTX_TCPIP_TUCSO(offset + 1516 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1517 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1518 } else if ((m0->m_pkthdr.csum_flags & 1519 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) { 1520 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1521 fields |= WTX_TXSM; 1522 tucs = WTX_TCPIP_TUCSS(offset) | 1523 WTX_TCPIP_TUCSO(offset + 1524 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1525 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1526 } else { 1527 /* Just initialize it to a valid TCP context. */ 1528 tucs = WTX_TCPIP_TUCSS(offset) | 1529 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1530 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1531 } 1532 1533 /* Fill in the context descriptor. */ 1534 t = (struct livengood_tcpip_ctxdesc *) 1535 &sc->sc_txdescs[sc->sc_txnext]; 1536 t->tcpip_ipcs = htole32(ipcs); 1537 t->tcpip_tucs = htole32(tucs); 1538 t->tcpip_cmdlen = htole32(cmdlen); 1539 t->tcpip_seg = htole32(seg); 1540 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1541 1542 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1543 txs->txs_ndesc++; 1544 1545 *cmdp = cmd; 1546 *fieldsp = fields; 1547 1548 return (0); 1549 } 1550 1551 static void 1552 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1553 { 1554 struct mbuf *m; 1555 int i; 1556 1557 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1558 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1559 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1560 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1561 m->m_data, m->m_len, m->m_flags); 1562 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1563 i, i == 1 ? "" : "s"); 1564 } 1565 1566 /* 1567 * wm_82547_txfifo_stall: 1568 * 1569 * Callout used to wait for the 82547 Tx FIFO to drain, 1570 * reset the FIFO pointers, and restart packet transmission. 1571 */ 1572 static void 1573 wm_82547_txfifo_stall(void *arg) 1574 { 1575 struct wm_softc *sc = arg; 1576 int s; 1577 1578 s = splnet(); 1579 1580 if (sc->sc_txfifo_stall) { 1581 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1582 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1583 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1584 /* 1585 * Packets have drained. Stop transmitter, reset 1586 * FIFO pointers, restart transmitter, and kick 1587 * the packet queue. 1588 */ 1589 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1590 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1591 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1592 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1593 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1594 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1595 CSR_WRITE(sc, WMREG_TCTL, tctl); 1596 CSR_WRITE_FLUSH(sc); 1597 1598 sc->sc_txfifo_head = 0; 1599 sc->sc_txfifo_stall = 0; 1600 wm_start(&sc->sc_ethercom.ec_if); 1601 } else { 1602 /* 1603 * Still waiting for packets to drain; try again in 1604 * another tick. 1605 */ 1606 callout_schedule(&sc->sc_txfifo_ch, 1); 1607 } 1608 } 1609 1610 splx(s); 1611 } 1612 1613 /* 1614 * wm_82547_txfifo_bugchk: 1615 * 1616 * Check for bug condition in the 82547 Tx FIFO. We need to 1617 * prevent enqueueing a packet that would wrap around the end 1618 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1619 * 1620 * We do this by checking the amount of space before the end 1621 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1622 * the Tx FIFO, wait for all remaining packets to drain, reset 1623 * the internal FIFO pointers to the beginning, and restart 1624 * transmission on the interface. 1625 */ 1626 #define WM_FIFO_HDR 0x10 1627 #define WM_82547_PAD_LEN 0x3e0 1628 static int 1629 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1630 { 1631 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1632 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1633 1634 /* Just return if already stalled. */ 1635 if (sc->sc_txfifo_stall) 1636 return (1); 1637 1638 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1639 /* Stall only occurs in half-duplex mode. */ 1640 goto send_packet; 1641 } 1642 1643 if (len >= WM_82547_PAD_LEN + space) { 1644 sc->sc_txfifo_stall = 1; 1645 callout_schedule(&sc->sc_txfifo_ch, 1); 1646 return (1); 1647 } 1648 1649 send_packet: 1650 sc->sc_txfifo_head += len; 1651 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1652 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1653 1654 return (0); 1655 } 1656 1657 /* 1658 * wm_start: [ifnet interface function] 1659 * 1660 * Start packet transmission on the interface. 1661 */ 1662 static void 1663 wm_start(struct ifnet *ifp) 1664 { 1665 struct wm_softc *sc = ifp->if_softc; 1666 struct mbuf *m0; 1667 #if 0 /* XXXJRT */ 1668 struct m_tag *mtag; 1669 #endif 1670 struct wm_txsoft *txs; 1671 bus_dmamap_t dmamap; 1672 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1673 bus_addr_t curaddr; 1674 bus_size_t seglen, curlen; 1675 uint32_t cksumcmd; 1676 uint8_t cksumfields; 1677 1678 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1679 return; 1680 1681 /* 1682 * Remember the previous number of free descriptors. 1683 */ 1684 ofree = sc->sc_txfree; 1685 1686 /* 1687 * Loop through the send queue, setting up transmit descriptors 1688 * until we drain the queue, or use up all available transmit 1689 * descriptors. 1690 */ 1691 for (;;) { 1692 /* Grab a packet off the queue. */ 1693 IFQ_POLL(&ifp->if_snd, m0); 1694 if (m0 == NULL) 1695 break; 1696 1697 DPRINTF(WM_DEBUG_TX, 1698 ("%s: TX: have packet to transmit: %p\n", 1699 sc->sc_dev.dv_xname, m0)); 1700 1701 /* Get a work queue entry. */ 1702 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1703 wm_txintr(sc); 1704 if (sc->sc_txsfree == 0) { 1705 DPRINTF(WM_DEBUG_TX, 1706 ("%s: TX: no free job descriptors\n", 1707 sc->sc_dev.dv_xname)); 1708 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1709 break; 1710 } 1711 } 1712 1713 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1714 dmamap = txs->txs_dmamap; 1715 1716 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1717 1718 /* 1719 * So says the Linux driver: 1720 * The controller does a simple calculation to make sure 1721 * there is enough room in the FIFO before initiating the 1722 * DMA for each buffer. The calc is: 1723 * 4 = ceil(buffer len / MSS) 1724 * To make sure we don't overrun the FIFO, adjust the max 1725 * buffer len if the MSS drops. 1726 */ 1727 dmamap->dm_maxsegsz = 1728 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1729 ? m0->m_pkthdr.segsz << 2 1730 : WTX_MAX_LEN; 1731 1732 /* 1733 * Load the DMA map. If this fails, the packet either 1734 * didn't fit in the allotted number of segments, or we 1735 * were short on resources. For the too-many-segments 1736 * case, we simply report an error and drop the packet, 1737 * since we can't sanely copy a jumbo packet to a single 1738 * buffer. 1739 */ 1740 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1741 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1742 if (error) { 1743 if (error == EFBIG) { 1744 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1745 log(LOG_ERR, "%s: Tx packet consumes too many " 1746 "DMA segments, dropping...\n", 1747 sc->sc_dev.dv_xname); 1748 IFQ_DEQUEUE(&ifp->if_snd, m0); 1749 wm_dump_mbuf_chain(sc, m0); 1750 m_freem(m0); 1751 continue; 1752 } 1753 /* 1754 * Short on resources, just stop for now. 1755 */ 1756 DPRINTF(WM_DEBUG_TX, 1757 ("%s: TX: dmamap load failed: %d\n", 1758 sc->sc_dev.dv_xname, error)); 1759 break; 1760 } 1761 1762 segs_needed = dmamap->dm_nsegs; 1763 if (use_tso) { 1764 /* For sentinel descriptor; see below. */ 1765 segs_needed++; 1766 } 1767 1768 /* 1769 * Ensure we have enough descriptors free to describe 1770 * the packet. Note, we always reserve one descriptor 1771 * at the end of the ring due to the semantics of the 1772 * TDT register, plus one more in the event we need 1773 * to load offload context. 1774 */ 1775 if (segs_needed > sc->sc_txfree - 2) { 1776 /* 1777 * Not enough free descriptors to transmit this 1778 * packet. We haven't committed anything yet, 1779 * so just unload the DMA map, put the packet 1780 * pack on the queue, and punt. Notify the upper 1781 * layer that there are no more slots left. 1782 */ 1783 DPRINTF(WM_DEBUG_TX, 1784 ("%s: TX: need %d (%d) descriptors, have %d\n", 1785 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1786 sc->sc_txfree - 1)); 1787 ifp->if_flags |= IFF_OACTIVE; 1788 bus_dmamap_unload(sc->sc_dmat, dmamap); 1789 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1790 break; 1791 } 1792 1793 /* 1794 * Check for 82547 Tx FIFO bug. We need to do this 1795 * once we know we can transmit the packet, since we 1796 * do some internal FIFO space accounting here. 1797 */ 1798 if (sc->sc_type == WM_T_82547 && 1799 wm_82547_txfifo_bugchk(sc, m0)) { 1800 DPRINTF(WM_DEBUG_TX, 1801 ("%s: TX: 82547 Tx FIFO bug detected\n", 1802 sc->sc_dev.dv_xname)); 1803 ifp->if_flags |= IFF_OACTIVE; 1804 bus_dmamap_unload(sc->sc_dmat, dmamap); 1805 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1806 break; 1807 } 1808 1809 IFQ_DEQUEUE(&ifp->if_snd, m0); 1810 1811 /* 1812 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1813 */ 1814 1815 DPRINTF(WM_DEBUG_TX, 1816 ("%s: TX: packet has %d (%d) DMA segments\n", 1817 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1818 1819 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1820 1821 /* 1822 * Store a pointer to the packet so that we can free it 1823 * later. 1824 * 1825 * Initially, we consider the number of descriptors the 1826 * packet uses the number of DMA segments. This may be 1827 * incremented by 1 if we do checksum offload (a descriptor 1828 * is used to set the checksum context). 1829 */ 1830 txs->txs_mbuf = m0; 1831 txs->txs_firstdesc = sc->sc_txnext; 1832 txs->txs_ndesc = segs_needed; 1833 1834 /* Set up offload parameters for this packet. */ 1835 if (m0->m_pkthdr.csum_flags & 1836 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 1837 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 1838 if (wm_tx_offload(sc, txs, &cksumcmd, 1839 &cksumfields) != 0) { 1840 /* Error message already displayed. */ 1841 bus_dmamap_unload(sc->sc_dmat, dmamap); 1842 continue; 1843 } 1844 } else { 1845 cksumcmd = 0; 1846 cksumfields = 0; 1847 } 1848 1849 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1850 1851 /* Sync the DMA map. */ 1852 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1853 BUS_DMASYNC_PREWRITE); 1854 1855 /* 1856 * Initialize the transmit descriptor. 1857 */ 1858 for (nexttx = sc->sc_txnext, seg = 0; 1859 seg < dmamap->dm_nsegs; seg++) { 1860 for (seglen = dmamap->dm_segs[seg].ds_len, 1861 curaddr = dmamap->dm_segs[seg].ds_addr; 1862 seglen != 0; 1863 curaddr += curlen, seglen -= curlen, 1864 nexttx = WM_NEXTTX(sc, nexttx)) { 1865 curlen = seglen; 1866 1867 /* 1868 * So says the Linux driver: 1869 * Work around for premature descriptor 1870 * write-backs in TSO mode. Append a 1871 * 4-byte sentinel descriptor. 1872 */ 1873 if (use_tso && 1874 seg == dmamap->dm_nsegs - 1 && 1875 curlen > 8) 1876 curlen -= 4; 1877 1878 wm_set_dma_addr( 1879 &sc->sc_txdescs[nexttx].wtx_addr, 1880 curaddr); 1881 sc->sc_txdescs[nexttx].wtx_cmdlen = 1882 htole32(cksumcmd | curlen); 1883 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1884 0; 1885 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1886 cksumfields; 1887 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1888 lasttx = nexttx; 1889 1890 DPRINTF(WM_DEBUG_TX, 1891 ("%s: TX: desc %d: low 0x%08lx, " 1892 "len 0x%04x\n", 1893 sc->sc_dev.dv_xname, nexttx, 1894 curaddr & 0xffffffffUL, (unsigned)curlen)); 1895 } 1896 } 1897 1898 KASSERT(lasttx != -1); 1899 1900 /* 1901 * Set up the command byte on the last descriptor of 1902 * the packet. If we're in the interrupt delay window, 1903 * delay the interrupt. 1904 */ 1905 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1906 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1907 1908 #if 0 /* XXXJRT */ 1909 /* 1910 * If VLANs are enabled and the packet has a VLAN tag, set 1911 * up the descriptor to encapsulate the packet for us. 1912 * 1913 * This is only valid on the last descriptor of the packet. 1914 */ 1915 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1916 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1917 htole32(WTX_CMD_VLE); 1918 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1919 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1920 } 1921 #endif /* XXXJRT */ 1922 1923 txs->txs_lastdesc = lasttx; 1924 1925 DPRINTF(WM_DEBUG_TX, 1926 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1927 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1928 1929 /* Sync the descriptors we're using. */ 1930 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1931 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1932 1933 /* Give the packet to the chip. */ 1934 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1935 1936 DPRINTF(WM_DEBUG_TX, 1937 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1938 1939 DPRINTF(WM_DEBUG_TX, 1940 ("%s: TX: finished transmitting packet, job %d\n", 1941 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1942 1943 /* Advance the tx pointer. */ 1944 sc->sc_txfree -= txs->txs_ndesc; 1945 sc->sc_txnext = nexttx; 1946 1947 sc->sc_txsfree--; 1948 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1949 1950 #if NBPFILTER > 0 1951 /* Pass the packet to any BPF listeners. */ 1952 if (ifp->if_bpf) 1953 bpf_mtap(ifp->if_bpf, m0); 1954 #endif /* NBPFILTER > 0 */ 1955 } 1956 1957 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1958 /* No more slots; notify upper layer. */ 1959 ifp->if_flags |= IFF_OACTIVE; 1960 } 1961 1962 if (sc->sc_txfree != ofree) { 1963 /* Set a watchdog timer in case the chip flakes out. */ 1964 ifp->if_timer = 5; 1965 } 1966 } 1967 1968 /* 1969 * wm_watchdog: [ifnet interface function] 1970 * 1971 * Watchdog timer handler. 1972 */ 1973 static void 1974 wm_watchdog(struct ifnet *ifp) 1975 { 1976 struct wm_softc *sc = ifp->if_softc; 1977 1978 /* 1979 * Since we're using delayed interrupts, sweep up 1980 * before we report an error. 1981 */ 1982 wm_txintr(sc); 1983 1984 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1985 log(LOG_ERR, 1986 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1987 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1988 sc->sc_txnext); 1989 ifp->if_oerrors++; 1990 1991 /* Reset the interface. */ 1992 (void) wm_init(ifp); 1993 } 1994 1995 /* Try to get more packets going. */ 1996 wm_start(ifp); 1997 } 1998 1999 /* 2000 * wm_ioctl: [ifnet interface function] 2001 * 2002 * Handle control requests from the operator. 2003 */ 2004 static int 2005 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2006 { 2007 struct wm_softc *sc = ifp->if_softc; 2008 struct ifreq *ifr = (struct ifreq *) data; 2009 int s, error; 2010 2011 s = splnet(); 2012 2013 switch (cmd) { 2014 case SIOCSIFMEDIA: 2015 case SIOCGIFMEDIA: 2016 /* Flow control requires full-duplex mode. */ 2017 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2018 (ifr->ifr_media & IFM_FDX) == 0) 2019 ifr->ifr_media &= ~IFM_ETH_FMASK; 2020 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2021 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2022 /* We can do both TXPAUSE and RXPAUSE. */ 2023 ifr->ifr_media |= 2024 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2025 } 2026 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2027 } 2028 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2029 break; 2030 default: 2031 error = ether_ioctl(ifp, cmd, data); 2032 if (error == ENETRESET) { 2033 /* 2034 * Multicast list has changed; set the hardware filter 2035 * accordingly. 2036 */ 2037 if (ifp->if_flags & IFF_RUNNING) 2038 wm_set_filter(sc); 2039 error = 0; 2040 } 2041 break; 2042 } 2043 2044 /* Try to get more packets going. */ 2045 wm_start(ifp); 2046 2047 splx(s); 2048 return (error); 2049 } 2050 2051 /* 2052 * wm_intr: 2053 * 2054 * Interrupt service routine. 2055 */ 2056 static int 2057 wm_intr(void *arg) 2058 { 2059 struct wm_softc *sc = arg; 2060 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2061 uint32_t icr; 2062 int handled = 0; 2063 2064 while (1 /* CONSTCOND */) { 2065 icr = CSR_READ(sc, WMREG_ICR); 2066 if ((icr & sc->sc_icr) == 0) 2067 break; 2068 2069 #if 0 /*NRND > 0*/ 2070 if (RND_ENABLED(&sc->rnd_source)) 2071 rnd_add_uint32(&sc->rnd_source, icr); 2072 #endif 2073 2074 handled = 1; 2075 2076 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2077 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2078 DPRINTF(WM_DEBUG_RX, 2079 ("%s: RX: got Rx intr 0x%08x\n", 2080 sc->sc_dev.dv_xname, 2081 icr & (ICR_RXDMT0|ICR_RXT0))); 2082 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2083 } 2084 #endif 2085 wm_rxintr(sc); 2086 2087 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2088 if (icr & ICR_TXDW) { 2089 DPRINTF(WM_DEBUG_TX, 2090 ("%s: TX: got TXDW interrupt\n", 2091 sc->sc_dev.dv_xname)); 2092 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2093 } 2094 #endif 2095 wm_txintr(sc); 2096 2097 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2098 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2099 wm_linkintr(sc, icr); 2100 } 2101 2102 if (icr & ICR_RXO) { 2103 ifp->if_ierrors++; 2104 #if defined(WM_DEBUG) 2105 log(LOG_WARNING, "%s: Receive overrun\n", 2106 sc->sc_dev.dv_xname); 2107 #endif /* defined(WM_DEBUG) */ 2108 } 2109 } 2110 2111 if (handled) { 2112 /* Try to get more packets going. */ 2113 wm_start(ifp); 2114 } 2115 2116 return (handled); 2117 } 2118 2119 /* 2120 * wm_txintr: 2121 * 2122 * Helper; handle transmit interrupts. 2123 */ 2124 static void 2125 wm_txintr(struct wm_softc *sc) 2126 { 2127 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2128 struct wm_txsoft *txs; 2129 uint8_t status; 2130 int i; 2131 2132 ifp->if_flags &= ~IFF_OACTIVE; 2133 2134 /* 2135 * Go through the Tx list and free mbufs for those 2136 * frames which have been transmitted. 2137 */ 2138 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2139 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2140 txs = &sc->sc_txsoft[i]; 2141 2142 DPRINTF(WM_DEBUG_TX, 2143 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2144 2145 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2146 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2147 2148 status = 2149 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2150 if ((status & WTX_ST_DD) == 0) { 2151 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2152 BUS_DMASYNC_PREREAD); 2153 break; 2154 } 2155 2156 DPRINTF(WM_DEBUG_TX, 2157 ("%s: TX: job %d done: descs %d..%d\n", 2158 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2159 txs->txs_lastdesc)); 2160 2161 /* 2162 * XXX We should probably be using the statistics 2163 * XXX registers, but I don't know if they exist 2164 * XXX on chips before the i82544. 2165 */ 2166 2167 #ifdef WM_EVENT_COUNTERS 2168 if (status & WTX_ST_TU) 2169 WM_EVCNT_INCR(&sc->sc_ev_tu); 2170 #endif /* WM_EVENT_COUNTERS */ 2171 2172 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2173 ifp->if_oerrors++; 2174 if (status & WTX_ST_LC) 2175 log(LOG_WARNING, "%s: late collision\n", 2176 sc->sc_dev.dv_xname); 2177 else if (status & WTX_ST_EC) { 2178 ifp->if_collisions += 16; 2179 log(LOG_WARNING, "%s: excessive collisions\n", 2180 sc->sc_dev.dv_xname); 2181 } 2182 } else 2183 ifp->if_opackets++; 2184 2185 sc->sc_txfree += txs->txs_ndesc; 2186 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2187 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2188 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2189 m_freem(txs->txs_mbuf); 2190 txs->txs_mbuf = NULL; 2191 } 2192 2193 /* Update the dirty transmit buffer pointer. */ 2194 sc->sc_txsdirty = i; 2195 DPRINTF(WM_DEBUG_TX, 2196 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2197 2198 /* 2199 * If there are no more pending transmissions, cancel the watchdog 2200 * timer. 2201 */ 2202 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2203 ifp->if_timer = 0; 2204 } 2205 2206 /* 2207 * wm_rxintr: 2208 * 2209 * Helper; handle receive interrupts. 2210 */ 2211 static void 2212 wm_rxintr(struct wm_softc *sc) 2213 { 2214 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2215 struct wm_rxsoft *rxs; 2216 struct mbuf *m; 2217 int i, len; 2218 uint8_t status, errors; 2219 2220 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2221 rxs = &sc->sc_rxsoft[i]; 2222 2223 DPRINTF(WM_DEBUG_RX, 2224 ("%s: RX: checking descriptor %d\n", 2225 sc->sc_dev.dv_xname, i)); 2226 2227 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2228 2229 status = sc->sc_rxdescs[i].wrx_status; 2230 errors = sc->sc_rxdescs[i].wrx_errors; 2231 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2232 2233 if ((status & WRX_ST_DD) == 0) { 2234 /* 2235 * We have processed all of the receive descriptors. 2236 */ 2237 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2238 break; 2239 } 2240 2241 if (__predict_false(sc->sc_rxdiscard)) { 2242 DPRINTF(WM_DEBUG_RX, 2243 ("%s: RX: discarding contents of descriptor %d\n", 2244 sc->sc_dev.dv_xname, i)); 2245 WM_INIT_RXDESC(sc, i); 2246 if (status & WRX_ST_EOP) { 2247 /* Reset our state. */ 2248 DPRINTF(WM_DEBUG_RX, 2249 ("%s: RX: resetting rxdiscard -> 0\n", 2250 sc->sc_dev.dv_xname)); 2251 sc->sc_rxdiscard = 0; 2252 } 2253 continue; 2254 } 2255 2256 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2257 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2258 2259 m = rxs->rxs_mbuf; 2260 2261 /* 2262 * Add a new receive buffer to the ring. 2263 */ 2264 if (wm_add_rxbuf(sc, i) != 0) { 2265 /* 2266 * Failed, throw away what we've done so 2267 * far, and discard the rest of the packet. 2268 */ 2269 ifp->if_ierrors++; 2270 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2271 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2272 WM_INIT_RXDESC(sc, i); 2273 if ((status & WRX_ST_EOP) == 0) 2274 sc->sc_rxdiscard = 1; 2275 if (sc->sc_rxhead != NULL) 2276 m_freem(sc->sc_rxhead); 2277 WM_RXCHAIN_RESET(sc); 2278 DPRINTF(WM_DEBUG_RX, 2279 ("%s: RX: Rx buffer allocation failed, " 2280 "dropping packet%s\n", sc->sc_dev.dv_xname, 2281 sc->sc_rxdiscard ? " (discard)" : "")); 2282 continue; 2283 } 2284 2285 WM_RXCHAIN_LINK(sc, m); 2286 2287 m->m_len = len; 2288 2289 DPRINTF(WM_DEBUG_RX, 2290 ("%s: RX: buffer at %p len %d\n", 2291 sc->sc_dev.dv_xname, m->m_data, len)); 2292 2293 /* 2294 * If this is not the end of the packet, keep 2295 * looking. 2296 */ 2297 if ((status & WRX_ST_EOP) == 0) { 2298 sc->sc_rxlen += len; 2299 DPRINTF(WM_DEBUG_RX, 2300 ("%s: RX: not yet EOP, rxlen -> %d\n", 2301 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2302 continue; 2303 } 2304 2305 /* 2306 * Okay, we have the entire packet now. The chip is 2307 * configured to include the FCS (not all chips can 2308 * be configured to strip it), so we need to trim it. 2309 */ 2310 m->m_len -= ETHER_CRC_LEN; 2311 2312 *sc->sc_rxtailp = NULL; 2313 len = m->m_len + sc->sc_rxlen; 2314 m = sc->sc_rxhead; 2315 2316 WM_RXCHAIN_RESET(sc); 2317 2318 DPRINTF(WM_DEBUG_RX, 2319 ("%s: RX: have entire packet, len -> %d\n", 2320 sc->sc_dev.dv_xname, len)); 2321 2322 /* 2323 * If an error occurred, update stats and drop the packet. 2324 */ 2325 if (errors & 2326 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2327 ifp->if_ierrors++; 2328 if (errors & WRX_ER_SE) 2329 log(LOG_WARNING, "%s: symbol error\n", 2330 sc->sc_dev.dv_xname); 2331 else if (errors & WRX_ER_SEQ) 2332 log(LOG_WARNING, "%s: receive sequence error\n", 2333 sc->sc_dev.dv_xname); 2334 else if (errors & WRX_ER_CE) 2335 log(LOG_WARNING, "%s: CRC error\n", 2336 sc->sc_dev.dv_xname); 2337 m_freem(m); 2338 continue; 2339 } 2340 2341 /* 2342 * No errors. Receive the packet. 2343 */ 2344 m->m_pkthdr.rcvif = ifp; 2345 m->m_pkthdr.len = len; 2346 2347 #if 0 /* XXXJRT */ 2348 /* 2349 * If VLANs are enabled, VLAN packets have been unwrapped 2350 * for us. Associate the tag with the packet. 2351 */ 2352 if ((status & WRX_ST_VP) != 0) { 2353 VLAN_INPUT_TAG(ifp, m, 2354 le16toh(sc->sc_rxdescs[i].wrx_special, 2355 continue); 2356 } 2357 #endif /* XXXJRT */ 2358 2359 /* 2360 * Set up checksum info for this packet. 2361 */ 2362 if ((status & WRX_ST_IXSM) == 0) { 2363 if (status & WRX_ST_IPCS) { 2364 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2365 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2366 if (errors & WRX_ER_IPE) 2367 m->m_pkthdr.csum_flags |= 2368 M_CSUM_IPv4_BAD; 2369 } 2370 if (status & WRX_ST_TCPCS) { 2371 /* 2372 * Note: we don't know if this was TCP or UDP, 2373 * so we just set both bits, and expect the 2374 * upper layers to deal. 2375 */ 2376 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2377 m->m_pkthdr.csum_flags |= 2378 M_CSUM_TCPv4|M_CSUM_UDPv4; 2379 if (errors & WRX_ER_TCPE) 2380 m->m_pkthdr.csum_flags |= 2381 M_CSUM_TCP_UDP_BAD; 2382 } 2383 } 2384 2385 ifp->if_ipackets++; 2386 2387 #if NBPFILTER > 0 2388 /* Pass this up to any BPF listeners. */ 2389 if (ifp->if_bpf) 2390 bpf_mtap(ifp->if_bpf, m); 2391 #endif /* NBPFILTER > 0 */ 2392 2393 /* Pass it on. */ 2394 (*ifp->if_input)(ifp, m); 2395 } 2396 2397 /* Update the receive pointer. */ 2398 sc->sc_rxptr = i; 2399 2400 DPRINTF(WM_DEBUG_RX, 2401 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2402 } 2403 2404 /* 2405 * wm_linkintr: 2406 * 2407 * Helper; handle link interrupts. 2408 */ 2409 static void 2410 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2411 { 2412 uint32_t status; 2413 2414 /* 2415 * If we get a link status interrupt on a 1000BASE-T 2416 * device, just fall into the normal MII tick path. 2417 */ 2418 if (sc->sc_flags & WM_F_HAS_MII) { 2419 if (icr & ICR_LSC) { 2420 DPRINTF(WM_DEBUG_LINK, 2421 ("%s: LINK: LSC -> mii_tick\n", 2422 sc->sc_dev.dv_xname)); 2423 mii_tick(&sc->sc_mii); 2424 } else if (icr & ICR_RXSEQ) { 2425 DPRINTF(WM_DEBUG_LINK, 2426 ("%s: LINK Receive sequence error\n", 2427 sc->sc_dev.dv_xname)); 2428 } 2429 return; 2430 } 2431 2432 /* 2433 * If we are now receiving /C/, check for link again in 2434 * a couple of link clock ticks. 2435 */ 2436 if (icr & ICR_RXCFG) { 2437 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2438 sc->sc_dev.dv_xname)); 2439 sc->sc_tbi_anstate = 2; 2440 } 2441 2442 if (icr & ICR_LSC) { 2443 status = CSR_READ(sc, WMREG_STATUS); 2444 if (status & STATUS_LU) { 2445 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2446 sc->sc_dev.dv_xname, 2447 (status & STATUS_FD) ? "FDX" : "HDX")); 2448 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2449 sc->sc_fcrtl &= ~FCRTL_XONE; 2450 if (status & STATUS_FD) 2451 sc->sc_tctl |= 2452 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2453 else 2454 sc->sc_tctl |= 2455 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2456 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2457 sc->sc_fcrtl |= FCRTL_XONE; 2458 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2459 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2460 WMREG_OLD_FCRTL : WMREG_FCRTL, 2461 sc->sc_fcrtl); 2462 sc->sc_tbi_linkup = 1; 2463 } else { 2464 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2465 sc->sc_dev.dv_xname)); 2466 sc->sc_tbi_linkup = 0; 2467 } 2468 sc->sc_tbi_anstate = 2; 2469 wm_tbi_set_linkled(sc); 2470 } else if (icr & ICR_RXSEQ) { 2471 DPRINTF(WM_DEBUG_LINK, 2472 ("%s: LINK: Receive sequence error\n", 2473 sc->sc_dev.dv_xname)); 2474 } 2475 } 2476 2477 /* 2478 * wm_tick: 2479 * 2480 * One second timer, used to check link status, sweep up 2481 * completed transmit jobs, etc. 2482 */ 2483 static void 2484 wm_tick(void *arg) 2485 { 2486 struct wm_softc *sc = arg; 2487 int s; 2488 2489 s = splnet(); 2490 2491 if (sc->sc_type >= WM_T_82542_2_1) { 2492 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2493 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2494 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2495 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2496 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2497 } 2498 2499 if (sc->sc_flags & WM_F_HAS_MII) 2500 mii_tick(&sc->sc_mii); 2501 else 2502 wm_tbi_check_link(sc); 2503 2504 splx(s); 2505 2506 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2507 } 2508 2509 /* 2510 * wm_reset: 2511 * 2512 * Reset the i82542 chip. 2513 */ 2514 static void 2515 wm_reset(struct wm_softc *sc) 2516 { 2517 int i; 2518 2519 /* 2520 * Allocate on-chip memory according to the MTU size. 2521 * The Packet Buffer Allocation register must be written 2522 * before the chip is reset. 2523 */ 2524 if (sc->sc_type < WM_T_82547) { 2525 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2526 PBA_40K : PBA_48K; 2527 } else { 2528 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2529 PBA_22K : PBA_30K; 2530 sc->sc_txfifo_head = 0; 2531 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2532 sc->sc_txfifo_size = 2533 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2534 sc->sc_txfifo_stall = 0; 2535 } 2536 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2537 2538 switch (sc->sc_type) { 2539 case WM_T_82544: 2540 case WM_T_82540: 2541 case WM_T_82545: 2542 case WM_T_82546: 2543 case WM_T_82541: 2544 case WM_T_82541_2: 2545 /* 2546 * On some chipsets, a reset through a memory-mapped write 2547 * cycle can cause the chip to reset before completing the 2548 * write cycle. This causes major headache that can be 2549 * avoided by issuing the reset via indirect register writes 2550 * through I/O space. 2551 * 2552 * So, if we successfully mapped the I/O BAR at attach time, 2553 * use that. Otherwise, try our luck with a memory-mapped 2554 * reset. 2555 */ 2556 if (sc->sc_flags & WM_F_IOH_VALID) 2557 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2558 else 2559 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2560 break; 2561 2562 case WM_T_82545_3: 2563 case WM_T_82546_3: 2564 /* Use the shadow control register on these chips. */ 2565 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2566 break; 2567 2568 default: 2569 /* Everything else can safely use the documented method. */ 2570 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2571 break; 2572 } 2573 delay(10000); 2574 2575 for (i = 0; i < 1000; i++) { 2576 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2577 return; 2578 delay(20); 2579 } 2580 2581 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2582 log(LOG_ERR, "%s: reset failed to complete\n", 2583 sc->sc_dev.dv_xname); 2584 } 2585 2586 /* 2587 * wm_init: [ifnet interface function] 2588 * 2589 * Initialize the interface. Must be called at splnet(). 2590 */ 2591 static int 2592 wm_init(struct ifnet *ifp) 2593 { 2594 struct wm_softc *sc = ifp->if_softc; 2595 struct wm_rxsoft *rxs; 2596 int i, error = 0; 2597 uint32_t reg; 2598 2599 /* 2600 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2601 * There is a small but measurable benefit to avoiding the adjusment 2602 * of the descriptor so that the headers are aligned, for normal mtu, 2603 * on such platforms. One possibility is that the DMA itself is 2604 * slightly more efficient if the front of the entire packet (instead 2605 * of the front of the headers) is aligned. 2606 * 2607 * Note we must always set align_tweak to 0 if we are using 2608 * jumbo frames. 2609 */ 2610 #ifdef __NO_STRICT_ALIGNMENT 2611 sc->sc_align_tweak = 0; 2612 #else 2613 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2614 sc->sc_align_tweak = 0; 2615 else 2616 sc->sc_align_tweak = 2; 2617 #endif /* __NO_STRICT_ALIGNMENT */ 2618 2619 /* Cancel any pending I/O. */ 2620 wm_stop(ifp, 0); 2621 2622 /* Reset the chip to a known state. */ 2623 wm_reset(sc); 2624 2625 /* Initialize the transmit descriptor ring. */ 2626 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2627 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2628 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2629 sc->sc_txfree = WM_NTXDESC(sc); 2630 sc->sc_txnext = 0; 2631 2632 if (sc->sc_type < WM_T_82543) { 2633 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2634 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2635 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2636 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2637 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2638 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2639 } else { 2640 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2641 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2642 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2643 CSR_WRITE(sc, WMREG_TDH, 0); 2644 CSR_WRITE(sc, WMREG_TDT, 0); 2645 CSR_WRITE(sc, WMREG_TIDV, 64); 2646 CSR_WRITE(sc, WMREG_TADV, 128); 2647 2648 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2649 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2650 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2651 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2652 } 2653 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2654 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2655 2656 /* Initialize the transmit job descriptors. */ 2657 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2658 sc->sc_txsoft[i].txs_mbuf = NULL; 2659 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2660 sc->sc_txsnext = 0; 2661 sc->sc_txsdirty = 0; 2662 2663 /* 2664 * Initialize the receive descriptor and receive job 2665 * descriptor rings. 2666 */ 2667 if (sc->sc_type < WM_T_82543) { 2668 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2669 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2670 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2671 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2672 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2673 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2674 2675 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2676 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2677 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2678 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2679 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2680 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2681 } else { 2682 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2683 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2684 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2685 CSR_WRITE(sc, WMREG_RDH, 0); 2686 CSR_WRITE(sc, WMREG_RDT, 0); 2687 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2688 CSR_WRITE(sc, WMREG_RADV, 128); 2689 } 2690 for (i = 0; i < WM_NRXDESC; i++) { 2691 rxs = &sc->sc_rxsoft[i]; 2692 if (rxs->rxs_mbuf == NULL) { 2693 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2694 log(LOG_ERR, "%s: unable to allocate or map rx " 2695 "buffer %d, error = %d\n", 2696 sc->sc_dev.dv_xname, i, error); 2697 /* 2698 * XXX Should attempt to run with fewer receive 2699 * XXX buffers instead of just failing. 2700 */ 2701 wm_rxdrain(sc); 2702 goto out; 2703 } 2704 } else 2705 WM_INIT_RXDESC(sc, i); 2706 } 2707 sc->sc_rxptr = 0; 2708 sc->sc_rxdiscard = 0; 2709 WM_RXCHAIN_RESET(sc); 2710 2711 /* 2712 * Clear out the VLAN table -- we don't use it (yet). 2713 */ 2714 CSR_WRITE(sc, WMREG_VET, 0); 2715 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2716 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2717 2718 /* 2719 * Set up flow-control parameters. 2720 * 2721 * XXX Values could probably stand some tuning. 2722 */ 2723 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2724 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2725 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2726 2727 sc->sc_fcrtl = FCRTL_DFLT; 2728 if (sc->sc_type < WM_T_82543) { 2729 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2730 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2731 } else { 2732 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2733 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2734 } 2735 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2736 2737 #if 0 /* XXXJRT */ 2738 /* Deal with VLAN enables. */ 2739 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2740 sc->sc_ctrl |= CTRL_VME; 2741 else 2742 #endif /* XXXJRT */ 2743 sc->sc_ctrl &= ~CTRL_VME; 2744 2745 /* Write the control registers. */ 2746 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2747 #if 0 2748 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2749 #endif 2750 2751 /* 2752 * Set up checksum offload parameters. 2753 */ 2754 reg = CSR_READ(sc, WMREG_RXCSUM); 2755 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2756 reg |= RXCSUM_IPOFL; 2757 else 2758 reg &= ~RXCSUM_IPOFL; 2759 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2760 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2761 else { 2762 reg &= ~RXCSUM_TUOFL; 2763 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2764 reg &= ~RXCSUM_IPOFL; 2765 } 2766 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2767 2768 /* 2769 * Set up the interrupt registers. 2770 */ 2771 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2772 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2773 ICR_RXO | ICR_RXT0; 2774 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2775 sc->sc_icr |= ICR_RXCFG; 2776 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2777 2778 /* Set up the inter-packet gap. */ 2779 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2780 2781 if (sc->sc_type >= WM_T_82543) { 2782 /* Set up the interrupt throttling register (units of 256ns) */ 2783 sc->sc_itr = 1000000000 / (7000 * 256); 2784 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2785 } 2786 2787 #if 0 /* XXXJRT */ 2788 /* Set the VLAN ethernetype. */ 2789 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2790 #endif 2791 2792 /* 2793 * Set up the transmit control register; we start out with 2794 * a collision distance suitable for FDX, but update it whe 2795 * we resolve the media type. 2796 */ 2797 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2798 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2799 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2800 2801 /* Set the media. */ 2802 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2803 2804 /* 2805 * Set up the receive control register; we actually program 2806 * the register when we set the receive filter. Use multicast 2807 * address offset type 0. 2808 * 2809 * Only the i82544 has the ability to strip the incoming 2810 * CRC, so we don't enable that feature. 2811 */ 2812 sc->sc_mchash_type = 0; 2813 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2814 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2815 2816 if(MCLBYTES == 2048) { 2817 sc->sc_rctl |= RCTL_2k; 2818 } else { 2819 if(sc->sc_type >= WM_T_82543) { 2820 switch(MCLBYTES) { 2821 case 4096: 2822 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2823 break; 2824 case 8192: 2825 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2826 break; 2827 case 16384: 2828 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2829 break; 2830 default: 2831 panic("wm_init: MCLBYTES %d unsupported", 2832 MCLBYTES); 2833 break; 2834 } 2835 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2836 } 2837 2838 /* Set the receive filter. */ 2839 wm_set_filter(sc); 2840 2841 /* Start the one second link check clock. */ 2842 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2843 2844 /* ...all done! */ 2845 ifp->if_flags |= IFF_RUNNING; 2846 ifp->if_flags &= ~IFF_OACTIVE; 2847 2848 out: 2849 if (error) 2850 log(LOG_ERR, "%s: interface not running\n", 2851 sc->sc_dev.dv_xname); 2852 return (error); 2853 } 2854 2855 /* 2856 * wm_rxdrain: 2857 * 2858 * Drain the receive queue. 2859 */ 2860 static void 2861 wm_rxdrain(struct wm_softc *sc) 2862 { 2863 struct wm_rxsoft *rxs; 2864 int i; 2865 2866 for (i = 0; i < WM_NRXDESC; i++) { 2867 rxs = &sc->sc_rxsoft[i]; 2868 if (rxs->rxs_mbuf != NULL) { 2869 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2870 m_freem(rxs->rxs_mbuf); 2871 rxs->rxs_mbuf = NULL; 2872 } 2873 } 2874 } 2875 2876 /* 2877 * wm_stop: [ifnet interface function] 2878 * 2879 * Stop transmission on the interface. 2880 */ 2881 static void 2882 wm_stop(struct ifnet *ifp, int disable) 2883 { 2884 struct wm_softc *sc = ifp->if_softc; 2885 struct wm_txsoft *txs; 2886 int i; 2887 2888 /* Stop the one second clock. */ 2889 callout_stop(&sc->sc_tick_ch); 2890 2891 /* Stop the 82547 Tx FIFO stall check timer. */ 2892 if (sc->sc_type == WM_T_82547) 2893 callout_stop(&sc->sc_txfifo_ch); 2894 2895 if (sc->sc_flags & WM_F_HAS_MII) { 2896 /* Down the MII. */ 2897 mii_down(&sc->sc_mii); 2898 } 2899 2900 /* Stop the transmit and receive processes. */ 2901 CSR_WRITE(sc, WMREG_TCTL, 0); 2902 CSR_WRITE(sc, WMREG_RCTL, 0); 2903 2904 /* 2905 * Clear the interrupt mask to ensure the device cannot assert its 2906 * interrupt line. 2907 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 2908 * any currently pending or shared interrupt. 2909 */ 2910 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2911 sc->sc_icr = 0; 2912 2913 /* Release any queued transmit buffers. */ 2914 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2915 txs = &sc->sc_txsoft[i]; 2916 if (txs->txs_mbuf != NULL) { 2917 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2918 m_freem(txs->txs_mbuf); 2919 txs->txs_mbuf = NULL; 2920 } 2921 } 2922 2923 if (disable) 2924 wm_rxdrain(sc); 2925 2926 /* Mark the interface as down and cancel the watchdog timer. */ 2927 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2928 ifp->if_timer = 0; 2929 } 2930 2931 /* 2932 * wm_acquire_eeprom: 2933 * 2934 * Perform the EEPROM handshake required on some chips. 2935 */ 2936 static int 2937 wm_acquire_eeprom(struct wm_softc *sc) 2938 { 2939 uint32_t reg; 2940 int x; 2941 2942 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2943 reg = CSR_READ(sc, WMREG_EECD); 2944 2945 /* Request EEPROM access. */ 2946 reg |= EECD_EE_REQ; 2947 CSR_WRITE(sc, WMREG_EECD, reg); 2948 2949 /* ..and wait for it to be granted. */ 2950 for (x = 0; x < 100; x++) { 2951 reg = CSR_READ(sc, WMREG_EECD); 2952 if (reg & EECD_EE_GNT) 2953 break; 2954 delay(5); 2955 } 2956 if ((reg & EECD_EE_GNT) == 0) { 2957 aprint_error("%s: could not acquire EEPROM GNT\n", 2958 sc->sc_dev.dv_xname); 2959 reg &= ~EECD_EE_REQ; 2960 CSR_WRITE(sc, WMREG_EECD, reg); 2961 return (1); 2962 } 2963 } 2964 2965 return (0); 2966 } 2967 2968 /* 2969 * wm_release_eeprom: 2970 * 2971 * Release the EEPROM mutex. 2972 */ 2973 static void 2974 wm_release_eeprom(struct wm_softc *sc) 2975 { 2976 uint32_t reg; 2977 2978 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2979 reg = CSR_READ(sc, WMREG_EECD); 2980 reg &= ~EECD_EE_REQ; 2981 CSR_WRITE(sc, WMREG_EECD, reg); 2982 } 2983 } 2984 2985 /* 2986 * wm_eeprom_sendbits: 2987 * 2988 * Send a series of bits to the EEPROM. 2989 */ 2990 static void 2991 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2992 { 2993 uint32_t reg; 2994 int x; 2995 2996 reg = CSR_READ(sc, WMREG_EECD); 2997 2998 for (x = nbits; x > 0; x--) { 2999 if (bits & (1U << (x - 1))) 3000 reg |= EECD_DI; 3001 else 3002 reg &= ~EECD_DI; 3003 CSR_WRITE(sc, WMREG_EECD, reg); 3004 delay(2); 3005 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3006 delay(2); 3007 CSR_WRITE(sc, WMREG_EECD, reg); 3008 delay(2); 3009 } 3010 } 3011 3012 /* 3013 * wm_eeprom_recvbits: 3014 * 3015 * Receive a series of bits from the EEPROM. 3016 */ 3017 static void 3018 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 3019 { 3020 uint32_t reg, val; 3021 int x; 3022 3023 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 3024 3025 val = 0; 3026 for (x = nbits; x > 0; x--) { 3027 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3028 delay(2); 3029 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 3030 val |= (1U << (x - 1)); 3031 CSR_WRITE(sc, WMREG_EECD, reg); 3032 delay(2); 3033 } 3034 *valp = val; 3035 } 3036 3037 /* 3038 * wm_read_eeprom_uwire: 3039 * 3040 * Read a word from the EEPROM using the MicroWire protocol. 3041 */ 3042 static int 3043 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3044 { 3045 uint32_t reg, val; 3046 int i; 3047 3048 for (i = 0; i < wordcnt; i++) { 3049 /* Clear SK and DI. */ 3050 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3051 CSR_WRITE(sc, WMREG_EECD, reg); 3052 3053 /* Set CHIP SELECT. */ 3054 reg |= EECD_CS; 3055 CSR_WRITE(sc, WMREG_EECD, reg); 3056 delay(2); 3057 3058 /* Shift in the READ command. */ 3059 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3060 3061 /* Shift in address. */ 3062 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3063 3064 /* Shift out the data. */ 3065 wm_eeprom_recvbits(sc, &val, 16); 3066 data[i] = val & 0xffff; 3067 3068 /* Clear CHIP SELECT. */ 3069 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3070 CSR_WRITE(sc, WMREG_EECD, reg); 3071 delay(2); 3072 } 3073 3074 return (0); 3075 } 3076 3077 /* 3078 * wm_spi_eeprom_ready: 3079 * 3080 * Wait for a SPI EEPROM to be ready for commands. 3081 */ 3082 static int 3083 wm_spi_eeprom_ready(struct wm_softc *sc) 3084 { 3085 uint32_t val; 3086 int usec; 3087 3088 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3089 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3090 wm_eeprom_recvbits(sc, &val, 8); 3091 if ((val & SPI_SR_RDY) == 0) 3092 break; 3093 } 3094 if (usec >= SPI_MAX_RETRIES) { 3095 aprint_error("%s: EEPROM failed to become ready\n", 3096 sc->sc_dev.dv_xname); 3097 return (1); 3098 } 3099 return (0); 3100 } 3101 3102 /* 3103 * wm_read_eeprom_spi: 3104 * 3105 * Read a work from the EEPROM using the SPI protocol. 3106 */ 3107 static int 3108 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3109 { 3110 uint32_t reg, val; 3111 int i; 3112 uint8_t opc; 3113 3114 /* Clear SK and CS. */ 3115 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3116 CSR_WRITE(sc, WMREG_EECD, reg); 3117 delay(2); 3118 3119 if (wm_spi_eeprom_ready(sc)) 3120 return (1); 3121 3122 /* Toggle CS to flush commands. */ 3123 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3124 delay(2); 3125 CSR_WRITE(sc, WMREG_EECD, reg); 3126 delay(2); 3127 3128 opc = SPI_OPC_READ; 3129 if (sc->sc_ee_addrbits == 8 && word >= 128) 3130 opc |= SPI_OPC_A8; 3131 3132 wm_eeprom_sendbits(sc, opc, 8); 3133 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3134 3135 for (i = 0; i < wordcnt; i++) { 3136 wm_eeprom_recvbits(sc, &val, 16); 3137 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3138 } 3139 3140 /* Raise CS and clear SK. */ 3141 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3142 CSR_WRITE(sc, WMREG_EECD, reg); 3143 delay(2); 3144 3145 return (0); 3146 } 3147 3148 #define EEPROM_CHECKSUM 0xBABA 3149 #define EEPROM_SIZE 0x0040 3150 3151 /* 3152 * wm_validate_eeprom_checksum 3153 * 3154 * The checksum is defined as the sum of the first 64 (16 bit) words. 3155 */ 3156 static int 3157 wm_validate_eeprom_checksum(struct wm_softc *sc) 3158 { 3159 uint16_t checksum; 3160 uint16_t eeprom_data; 3161 int i; 3162 3163 checksum = 0; 3164 3165 for (i = 0; i < EEPROM_SIZE; i++) { 3166 if(wm_read_eeprom(sc, i, 1, &eeprom_data)) 3167 return 1; 3168 checksum += eeprom_data; 3169 } 3170 3171 if (checksum != (uint16_t) EEPROM_CHECKSUM) 3172 return 1; 3173 3174 return 0; 3175 } 3176 3177 /* 3178 * wm_read_eeprom: 3179 * 3180 * Read data from the serial EEPROM. 3181 */ 3182 static int 3183 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3184 { 3185 int rv; 3186 3187 if (sc->sc_flags & WM_F_EEPROM_INVALID) 3188 return 1; 3189 3190 if (wm_acquire_eeprom(sc)) 3191 return 1; 3192 3193 if (sc->sc_flags & WM_F_EEPROM_SPI) 3194 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3195 else 3196 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3197 3198 wm_release_eeprom(sc); 3199 return rv; 3200 } 3201 3202 /* 3203 * wm_add_rxbuf: 3204 * 3205 * Add a receive buffer to the indiciated descriptor. 3206 */ 3207 static int 3208 wm_add_rxbuf(struct wm_softc *sc, int idx) 3209 { 3210 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3211 struct mbuf *m; 3212 int error; 3213 3214 MGETHDR(m, M_DONTWAIT, MT_DATA); 3215 if (m == NULL) 3216 return (ENOBUFS); 3217 3218 MCLGET(m, M_DONTWAIT); 3219 if ((m->m_flags & M_EXT) == 0) { 3220 m_freem(m); 3221 return (ENOBUFS); 3222 } 3223 3224 if (rxs->rxs_mbuf != NULL) 3225 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3226 3227 rxs->rxs_mbuf = m; 3228 3229 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3230 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3231 BUS_DMA_READ|BUS_DMA_NOWAIT); 3232 if (error) { 3233 /* XXX XXX XXX */ 3234 printf("%s: unable to load rx DMA map %d, error = %d\n", 3235 sc->sc_dev.dv_xname, idx, error); 3236 panic("wm_add_rxbuf"); 3237 } 3238 3239 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3240 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3241 3242 WM_INIT_RXDESC(sc, idx); 3243 3244 return (0); 3245 } 3246 3247 /* 3248 * wm_set_ral: 3249 * 3250 * Set an entery in the receive address list. 3251 */ 3252 static void 3253 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3254 { 3255 uint32_t ral_lo, ral_hi; 3256 3257 if (enaddr != NULL) { 3258 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3259 (enaddr[3] << 24); 3260 ral_hi = enaddr[4] | (enaddr[5] << 8); 3261 ral_hi |= RAL_AV; 3262 } else { 3263 ral_lo = 0; 3264 ral_hi = 0; 3265 } 3266 3267 if (sc->sc_type >= WM_T_82544) { 3268 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3269 ral_lo); 3270 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3271 ral_hi); 3272 } else { 3273 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3274 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3275 } 3276 } 3277 3278 /* 3279 * wm_mchash: 3280 * 3281 * Compute the hash of the multicast address for the 4096-bit 3282 * multicast filter. 3283 */ 3284 static uint32_t 3285 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3286 { 3287 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3288 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3289 uint32_t hash; 3290 3291 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3292 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3293 3294 return (hash & 0xfff); 3295 } 3296 3297 /* 3298 * wm_set_filter: 3299 * 3300 * Set up the receive filter. 3301 */ 3302 static void 3303 wm_set_filter(struct wm_softc *sc) 3304 { 3305 struct ethercom *ec = &sc->sc_ethercom; 3306 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3307 struct ether_multi *enm; 3308 struct ether_multistep step; 3309 bus_addr_t mta_reg; 3310 uint32_t hash, reg, bit; 3311 int i; 3312 3313 if (sc->sc_type >= WM_T_82544) 3314 mta_reg = WMREG_CORDOVA_MTA; 3315 else 3316 mta_reg = WMREG_MTA; 3317 3318 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3319 3320 if (ifp->if_flags & IFF_BROADCAST) 3321 sc->sc_rctl |= RCTL_BAM; 3322 if (ifp->if_flags & IFF_PROMISC) { 3323 sc->sc_rctl |= RCTL_UPE; 3324 goto allmulti; 3325 } 3326 3327 /* 3328 * Set the station address in the first RAL slot, and 3329 * clear the remaining slots. 3330 */ 3331 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3332 for (i = 1; i < WM_RAL_TABSIZE; i++) 3333 wm_set_ral(sc, NULL, i); 3334 3335 /* Clear out the multicast table. */ 3336 for (i = 0; i < WM_MC_TABSIZE; i++) 3337 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3338 3339 ETHER_FIRST_MULTI(step, ec, enm); 3340 while (enm != NULL) { 3341 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3342 /* 3343 * We must listen to a range of multicast addresses. 3344 * For now, just accept all multicasts, rather than 3345 * trying to set only those filter bits needed to match 3346 * the range. (At this time, the only use of address 3347 * ranges is for IP multicast routing, for which the 3348 * range is big enough to require all bits set.) 3349 */ 3350 goto allmulti; 3351 } 3352 3353 hash = wm_mchash(sc, enm->enm_addrlo); 3354 3355 reg = (hash >> 5) & 0x7f; 3356 bit = hash & 0x1f; 3357 3358 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3359 hash |= 1U << bit; 3360 3361 /* XXX Hardware bug?? */ 3362 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3363 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3364 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3365 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3366 } else 3367 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3368 3369 ETHER_NEXT_MULTI(step, enm); 3370 } 3371 3372 ifp->if_flags &= ~IFF_ALLMULTI; 3373 goto setit; 3374 3375 allmulti: 3376 ifp->if_flags |= IFF_ALLMULTI; 3377 sc->sc_rctl |= RCTL_MPE; 3378 3379 setit: 3380 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3381 } 3382 3383 /* 3384 * wm_tbi_mediainit: 3385 * 3386 * Initialize media for use on 1000BASE-X devices. 3387 */ 3388 static void 3389 wm_tbi_mediainit(struct wm_softc *sc) 3390 { 3391 const char *sep = ""; 3392 3393 if (sc->sc_type < WM_T_82543) 3394 sc->sc_tipg = TIPG_WM_DFLT; 3395 else 3396 sc->sc_tipg = TIPG_LG_DFLT; 3397 3398 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3399 wm_tbi_mediastatus); 3400 3401 /* 3402 * SWD Pins: 3403 * 3404 * 0 = Link LED (output) 3405 * 1 = Loss Of Signal (input) 3406 */ 3407 sc->sc_ctrl |= CTRL_SWDPIO(0); 3408 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3409 3410 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3411 3412 #define ADD(ss, mm, dd) \ 3413 do { \ 3414 aprint_normal("%s%s", sep, ss); \ 3415 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3416 sep = ", "; \ 3417 } while (/*CONSTCOND*/0) 3418 3419 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3420 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3421 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3422 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3423 aprint_normal("\n"); 3424 3425 #undef ADD 3426 3427 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3428 } 3429 3430 /* 3431 * wm_tbi_mediastatus: [ifmedia interface function] 3432 * 3433 * Get the current interface media status on a 1000BASE-X device. 3434 */ 3435 static void 3436 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3437 { 3438 struct wm_softc *sc = ifp->if_softc; 3439 uint32_t ctrl; 3440 3441 ifmr->ifm_status = IFM_AVALID; 3442 ifmr->ifm_active = IFM_ETHER; 3443 3444 if (sc->sc_tbi_linkup == 0) { 3445 ifmr->ifm_active |= IFM_NONE; 3446 return; 3447 } 3448 3449 ifmr->ifm_status |= IFM_ACTIVE; 3450 ifmr->ifm_active |= IFM_1000_SX; 3451 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3452 ifmr->ifm_active |= IFM_FDX; 3453 ctrl = CSR_READ(sc, WMREG_CTRL); 3454 if (ctrl & CTRL_RFCE) 3455 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3456 if (ctrl & CTRL_TFCE) 3457 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3458 } 3459 3460 /* 3461 * wm_tbi_mediachange: [ifmedia interface function] 3462 * 3463 * Set hardware to newly-selected media on a 1000BASE-X device. 3464 */ 3465 static int 3466 wm_tbi_mediachange(struct ifnet *ifp) 3467 { 3468 struct wm_softc *sc = ifp->if_softc; 3469 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3470 uint32_t status; 3471 int i; 3472 3473 sc->sc_txcw = ife->ifm_data; 3474 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3475 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3476 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3477 sc->sc_txcw |= TXCW_ANE; 3478 3479 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3480 delay(10000); 3481 3482 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3483 3484 sc->sc_tbi_anstate = 0; 3485 3486 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3487 /* Have signal; wait for the link to come up. */ 3488 for (i = 0; i < 50; i++) { 3489 delay(10000); 3490 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3491 break; 3492 } 3493 3494 status = CSR_READ(sc, WMREG_STATUS); 3495 if (status & STATUS_LU) { 3496 /* Link is up. */ 3497 DPRINTF(WM_DEBUG_LINK, 3498 ("%s: LINK: set media -> link up %s\n", 3499 sc->sc_dev.dv_xname, 3500 (status & STATUS_FD) ? "FDX" : "HDX")); 3501 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3502 sc->sc_fcrtl &= ~FCRTL_XONE; 3503 if (status & STATUS_FD) 3504 sc->sc_tctl |= 3505 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3506 else 3507 sc->sc_tctl |= 3508 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3509 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3510 sc->sc_fcrtl |= FCRTL_XONE; 3511 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3512 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3513 WMREG_OLD_FCRTL : WMREG_FCRTL, 3514 sc->sc_fcrtl); 3515 sc->sc_tbi_linkup = 1; 3516 } else { 3517 /* Link is down. */ 3518 DPRINTF(WM_DEBUG_LINK, 3519 ("%s: LINK: set media -> link down\n", 3520 sc->sc_dev.dv_xname)); 3521 sc->sc_tbi_linkup = 0; 3522 } 3523 } else { 3524 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3525 sc->sc_dev.dv_xname)); 3526 sc->sc_tbi_linkup = 0; 3527 } 3528 3529 wm_tbi_set_linkled(sc); 3530 3531 return (0); 3532 } 3533 3534 /* 3535 * wm_tbi_set_linkled: 3536 * 3537 * Update the link LED on 1000BASE-X devices. 3538 */ 3539 static void 3540 wm_tbi_set_linkled(struct wm_softc *sc) 3541 { 3542 3543 if (sc->sc_tbi_linkup) 3544 sc->sc_ctrl |= CTRL_SWDPIN(0); 3545 else 3546 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3547 3548 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3549 } 3550 3551 /* 3552 * wm_tbi_check_link: 3553 * 3554 * Check the link on 1000BASE-X devices. 3555 */ 3556 static void 3557 wm_tbi_check_link(struct wm_softc *sc) 3558 { 3559 uint32_t rxcw, ctrl, status; 3560 3561 if (sc->sc_tbi_anstate == 0) 3562 return; 3563 else if (sc->sc_tbi_anstate > 1) { 3564 DPRINTF(WM_DEBUG_LINK, 3565 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3566 sc->sc_tbi_anstate)); 3567 sc->sc_tbi_anstate--; 3568 return; 3569 } 3570 3571 sc->sc_tbi_anstate = 0; 3572 3573 rxcw = CSR_READ(sc, WMREG_RXCW); 3574 ctrl = CSR_READ(sc, WMREG_CTRL); 3575 status = CSR_READ(sc, WMREG_STATUS); 3576 3577 if ((status & STATUS_LU) == 0) { 3578 DPRINTF(WM_DEBUG_LINK, 3579 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3580 sc->sc_tbi_linkup = 0; 3581 } else { 3582 DPRINTF(WM_DEBUG_LINK, 3583 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3584 (status & STATUS_FD) ? "FDX" : "HDX")); 3585 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3586 sc->sc_fcrtl &= ~FCRTL_XONE; 3587 if (status & STATUS_FD) 3588 sc->sc_tctl |= 3589 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3590 else 3591 sc->sc_tctl |= 3592 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3593 if (ctrl & CTRL_TFCE) 3594 sc->sc_fcrtl |= FCRTL_XONE; 3595 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3596 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3597 WMREG_OLD_FCRTL : WMREG_FCRTL, 3598 sc->sc_fcrtl); 3599 sc->sc_tbi_linkup = 1; 3600 } 3601 3602 wm_tbi_set_linkled(sc); 3603 } 3604 3605 /* 3606 * wm_gmii_reset: 3607 * 3608 * Reset the PHY. 3609 */ 3610 static void 3611 wm_gmii_reset(struct wm_softc *sc) 3612 { 3613 uint32_t reg; 3614 3615 if (sc->sc_type >= WM_T_82544) { 3616 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3617 delay(20000); 3618 3619 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3620 delay(20000); 3621 } else { 3622 /* The PHY reset pin is active-low. */ 3623 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3624 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3625 CTRL_EXT_SWDPIN(4)); 3626 reg |= CTRL_EXT_SWDPIO(4); 3627 3628 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3629 delay(10); 3630 3631 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3632 delay(10); 3633 3634 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3635 delay(10); 3636 #if 0 3637 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3638 #endif 3639 } 3640 } 3641 3642 /* 3643 * wm_gmii_mediainit: 3644 * 3645 * Initialize media for use on 1000BASE-T devices. 3646 */ 3647 static void 3648 wm_gmii_mediainit(struct wm_softc *sc) 3649 { 3650 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3651 3652 /* We have MII. */ 3653 sc->sc_flags |= WM_F_HAS_MII; 3654 3655 sc->sc_tipg = TIPG_1000T_DFLT; 3656 3657 /* 3658 * Let the chip set speed/duplex on its own based on 3659 * signals from the PHY. 3660 */ 3661 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3662 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3663 3664 /* Initialize our media structures and probe the GMII. */ 3665 sc->sc_mii.mii_ifp = ifp; 3666 3667 if (sc->sc_type >= WM_T_82544) { 3668 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3669 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3670 } else { 3671 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3672 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3673 } 3674 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3675 3676 wm_gmii_reset(sc); 3677 3678 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3679 wm_gmii_mediastatus); 3680 3681 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3682 MII_OFFSET_ANY, MIIF_DOPAUSE); 3683 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3684 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3685 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3686 } else 3687 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3688 } 3689 3690 /* 3691 * wm_gmii_mediastatus: [ifmedia interface function] 3692 * 3693 * Get the current interface media status on a 1000BASE-T device. 3694 */ 3695 static void 3696 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3697 { 3698 struct wm_softc *sc = ifp->if_softc; 3699 3700 mii_pollstat(&sc->sc_mii); 3701 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3702 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3703 sc->sc_flowflags; 3704 } 3705 3706 /* 3707 * wm_gmii_mediachange: [ifmedia interface function] 3708 * 3709 * Set hardware to newly-selected media on a 1000BASE-T device. 3710 */ 3711 static int 3712 wm_gmii_mediachange(struct ifnet *ifp) 3713 { 3714 struct wm_softc *sc = ifp->if_softc; 3715 3716 if (ifp->if_flags & IFF_UP) 3717 mii_mediachg(&sc->sc_mii); 3718 return (0); 3719 } 3720 3721 #define MDI_IO CTRL_SWDPIN(2) 3722 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3723 #define MDI_CLK CTRL_SWDPIN(3) 3724 3725 static void 3726 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3727 { 3728 uint32_t i, v; 3729 3730 v = CSR_READ(sc, WMREG_CTRL); 3731 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3732 v |= MDI_DIR | CTRL_SWDPIO(3); 3733 3734 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3735 if (data & i) 3736 v |= MDI_IO; 3737 else 3738 v &= ~MDI_IO; 3739 CSR_WRITE(sc, WMREG_CTRL, v); 3740 delay(10); 3741 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3742 delay(10); 3743 CSR_WRITE(sc, WMREG_CTRL, v); 3744 delay(10); 3745 } 3746 } 3747 3748 static uint32_t 3749 i82543_mii_recvbits(struct wm_softc *sc) 3750 { 3751 uint32_t v, i, data = 0; 3752 3753 v = CSR_READ(sc, WMREG_CTRL); 3754 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3755 v |= CTRL_SWDPIO(3); 3756 3757 CSR_WRITE(sc, WMREG_CTRL, v); 3758 delay(10); 3759 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3760 delay(10); 3761 CSR_WRITE(sc, WMREG_CTRL, v); 3762 delay(10); 3763 3764 for (i = 0; i < 16; i++) { 3765 data <<= 1; 3766 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3767 delay(10); 3768 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3769 data |= 1; 3770 CSR_WRITE(sc, WMREG_CTRL, v); 3771 delay(10); 3772 } 3773 3774 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3775 delay(10); 3776 CSR_WRITE(sc, WMREG_CTRL, v); 3777 delay(10); 3778 3779 return (data); 3780 } 3781 3782 #undef MDI_IO 3783 #undef MDI_DIR 3784 #undef MDI_CLK 3785 3786 /* 3787 * wm_gmii_i82543_readreg: [mii interface function] 3788 * 3789 * Read a PHY register on the GMII (i82543 version). 3790 */ 3791 static int 3792 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3793 { 3794 struct wm_softc *sc = (void *) self; 3795 int rv; 3796 3797 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3798 i82543_mii_sendbits(sc, reg | (phy << 5) | 3799 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3800 rv = i82543_mii_recvbits(sc) & 0xffff; 3801 3802 DPRINTF(WM_DEBUG_GMII, 3803 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3804 sc->sc_dev.dv_xname, phy, reg, rv)); 3805 3806 return (rv); 3807 } 3808 3809 /* 3810 * wm_gmii_i82543_writereg: [mii interface function] 3811 * 3812 * Write a PHY register on the GMII (i82543 version). 3813 */ 3814 static void 3815 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3816 { 3817 struct wm_softc *sc = (void *) self; 3818 3819 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3820 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3821 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3822 (MII_COMMAND_START << 30), 32); 3823 } 3824 3825 /* 3826 * wm_gmii_i82544_readreg: [mii interface function] 3827 * 3828 * Read a PHY register on the GMII. 3829 */ 3830 static int 3831 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3832 { 3833 struct wm_softc *sc = (void *) self; 3834 uint32_t mdic = 0; 3835 int i, rv; 3836 3837 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3838 MDIC_REGADD(reg)); 3839 3840 for (i = 0; i < 100; i++) { 3841 mdic = CSR_READ(sc, WMREG_MDIC); 3842 if (mdic & MDIC_READY) 3843 break; 3844 delay(10); 3845 } 3846 3847 if ((mdic & MDIC_READY) == 0) { 3848 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3849 sc->sc_dev.dv_xname, phy, reg); 3850 rv = 0; 3851 } else if (mdic & MDIC_E) { 3852 #if 0 /* This is normal if no PHY is present. */ 3853 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3854 sc->sc_dev.dv_xname, phy, reg); 3855 #endif 3856 rv = 0; 3857 } else { 3858 rv = MDIC_DATA(mdic); 3859 if (rv == 0xffff) 3860 rv = 0; 3861 } 3862 3863 return (rv); 3864 } 3865 3866 /* 3867 * wm_gmii_i82544_writereg: [mii interface function] 3868 * 3869 * Write a PHY register on the GMII. 3870 */ 3871 static void 3872 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3873 { 3874 struct wm_softc *sc = (void *) self; 3875 uint32_t mdic = 0; 3876 int i; 3877 3878 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3879 MDIC_REGADD(reg) | MDIC_DATA(val)); 3880 3881 for (i = 0; i < 100; i++) { 3882 mdic = CSR_READ(sc, WMREG_MDIC); 3883 if (mdic & MDIC_READY) 3884 break; 3885 delay(10); 3886 } 3887 3888 if ((mdic & MDIC_READY) == 0) 3889 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3890 sc->sc_dev.dv_xname, phy, reg); 3891 else if (mdic & MDIC_E) 3892 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3893 sc->sc_dev.dv_xname, phy, reg); 3894 } 3895 3896 /* 3897 * wm_gmii_statchg: [mii interface function] 3898 * 3899 * Callback from MII layer when media changes. 3900 */ 3901 static void 3902 wm_gmii_statchg(struct device *self) 3903 { 3904 struct wm_softc *sc = (void *) self; 3905 struct mii_data *mii = &sc->sc_mii; 3906 3907 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3908 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3909 sc->sc_fcrtl &= ~FCRTL_XONE; 3910 3911 /* 3912 * Get flow control negotiation result. 3913 */ 3914 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3915 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3916 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3917 mii->mii_media_active &= ~IFM_ETH_FMASK; 3918 } 3919 3920 if (sc->sc_flowflags & IFM_FLOW) { 3921 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3922 sc->sc_ctrl |= CTRL_TFCE; 3923 sc->sc_fcrtl |= FCRTL_XONE; 3924 } 3925 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3926 sc->sc_ctrl |= CTRL_RFCE; 3927 } 3928 3929 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3930 DPRINTF(WM_DEBUG_LINK, 3931 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3932 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3933 } else { 3934 DPRINTF(WM_DEBUG_LINK, 3935 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3936 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3937 } 3938 3939 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3940 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3941 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3942 : WMREG_FCRTL, sc->sc_fcrtl); 3943 } 3944
Indexes created Tue Sep 23 07:09:52 GMT 2025