if_wm.c revision 1.115
1 /* $NetBSD: if_wm.c,v 1.115 2006/05/05 18:04:42 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.115 2006/05/05 18:04:42 thorpej Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make several things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 } wm_chip_type; 217 218 /* 219 * Software state per device. 220 */ 221 struct wm_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_space_tag_t sc_iot; /* I/O space tag */ 226 bus_space_handle_t sc_ioh; /* I/O space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct ethercom sc_ethercom; /* ethernet common data */ 229 void *sc_sdhook; /* shutdown hook */ 230 231 wm_chip_type sc_type; /* chip type */ 232 int sc_flags; /* flags; see below */ 233 int sc_bus_speed; /* PCI/PCIX bus speed */ 234 int sc_pcix_offset; /* PCIX capability register offset */ 235 int sc_flowflags; /* 802.3x flow control flags */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 int sc_ee_addrbits; /* EEPROM address bits */ 240 241 struct mii_data sc_mii; /* MII/media information */ 242 243 struct callout sc_tick_ch; /* tick callout */ 244 245 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 246 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 247 248 int sc_align_tweak; 249 250 /* 251 * Software state for the transmit and receive descriptors. 252 */ 253 int sc_txnum; /* must be a power of two */ 254 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 255 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 256 257 /* 258 * Control data structures. 259 */ 260 int sc_ntxdesc; /* must be a power of two */ 261 struct wm_control_data_82544 *sc_control_data; 262 #define sc_txdescs sc_control_data->wcd_txdescs 263 #define sc_rxdescs sc_control_data->wcd_rxdescs 264 265 #ifdef WM_EVENT_COUNTERS 266 /* Event counters. */ 267 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 268 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 269 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 270 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 271 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 272 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 273 struct evcnt sc_ev_linkintr; /* Link interrupts */ 274 275 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 276 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 277 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 278 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 279 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 280 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 281 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 282 283 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 284 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 285 286 struct evcnt sc_ev_tu; /* Tx underrun */ 287 288 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 289 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 290 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 291 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 292 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 293 #endif /* WM_EVENT_COUNTERS */ 294 295 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 296 297 int sc_txfree; /* number of free Tx descriptors */ 298 int sc_txnext; /* next ready Tx descriptor */ 299 300 int sc_txsfree; /* number of free Tx jobs */ 301 int sc_txsnext; /* next free Tx job */ 302 int sc_txsdirty; /* dirty Tx jobs */ 303 304 /* These 5 variables are used only on the 82547. */ 305 int sc_txfifo_size; /* Tx FIFO size */ 306 int sc_txfifo_head; /* current head of FIFO */ 307 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 308 int sc_txfifo_stall; /* Tx FIFO is stalled */ 309 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 310 311 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 312 313 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 314 int sc_rxdiscard; 315 int sc_rxlen; 316 struct mbuf *sc_rxhead; 317 struct mbuf *sc_rxtail; 318 struct mbuf **sc_rxtailp; 319 320 uint32_t sc_ctrl; /* prototype CTRL register */ 321 #if 0 322 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 323 #endif 324 uint32_t sc_icr; /* prototype interrupt bits */ 325 uint32_t sc_itr; /* prototype intr throttling reg */ 326 uint32_t sc_tctl; /* prototype TCTL register */ 327 uint32_t sc_rctl; /* prototype RCTL register */ 328 uint32_t sc_txcw; /* prototype TXCW register */ 329 uint32_t sc_tipg; /* prototype TIPG register */ 330 uint32_t sc_fcrtl; /* prototype FCRTL register */ 331 uint32_t sc_pba; /* prototype PBA register */ 332 333 int sc_tbi_linkup; /* TBI link status */ 334 int sc_tbi_anstate; /* autonegotiation state */ 335 336 int sc_mchash_type; /* multicast filter offset */ 337 338 #if NRND > 0 339 rndsource_element_t rnd_source; /* random source */ 340 #endif 341 }; 342 343 #define WM_RXCHAIN_RESET(sc) \ 344 do { \ 345 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 346 *(sc)->sc_rxtailp = NULL; \ 347 (sc)->sc_rxlen = 0; \ 348 } while (/*CONSTCOND*/0) 349 350 #define WM_RXCHAIN_LINK(sc, m) \ 351 do { \ 352 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 353 (sc)->sc_rxtailp = &(m)->m_next; \ 354 } while (/*CONSTCOND*/0) 355 356 /* sc_flags */ 357 #define WM_F_HAS_MII 0x01 /* has MII */ 358 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 359 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 360 #define WM_F_EEPROM_INVALID 0x08 /* EEPROM not present (bad checksum) */ 361 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 362 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 363 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 364 #define WM_F_CSA 0x80 /* bus is CSA */ 365 366 #ifdef WM_EVENT_COUNTERS 367 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 368 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 369 #else 370 #define WM_EVCNT_INCR(ev) /* nothing */ 371 #define WM_EVCNT_ADD(ev, val) /* nothing */ 372 #endif 373 374 #define CSR_READ(sc, reg) \ 375 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 376 #define CSR_WRITE(sc, reg, val) \ 377 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 378 #define CSR_WRITE_FLUSH(sc) \ 379 (void) CSR_READ((sc), WMREG_STATUS) 380 381 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 382 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 383 384 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 385 #define WM_CDTXADDR_HI(sc, x) \ 386 (sizeof(bus_addr_t) == 8 ? \ 387 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 388 389 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 390 #define WM_CDRXADDR_HI(sc, x) \ 391 (sizeof(bus_addr_t) == 8 ? \ 392 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 393 394 #define WM_CDTXSYNC(sc, x, n, ops) \ 395 do { \ 396 int __x, __n; \ 397 \ 398 __x = (x); \ 399 __n = (n); \ 400 \ 401 /* If it will wrap around, sync to the end of the ring. */ \ 402 if ((__x + __n) > WM_NTXDESC(sc)) { \ 403 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 404 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 405 (WM_NTXDESC(sc) - __x), (ops)); \ 406 __n -= (WM_NTXDESC(sc) - __x); \ 407 __x = 0; \ 408 } \ 409 \ 410 /* Now sync whatever is left. */ \ 411 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 412 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 413 } while (/*CONSTCOND*/0) 414 415 #define WM_CDRXSYNC(sc, x, ops) \ 416 do { \ 417 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 418 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 419 } while (/*CONSTCOND*/0) 420 421 #define WM_INIT_RXDESC(sc, x) \ 422 do { \ 423 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 424 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 425 struct mbuf *__m = __rxs->rxs_mbuf; \ 426 \ 427 /* \ 428 * Note: We scoot the packet forward 2 bytes in the buffer \ 429 * so that the payload after the Ethernet header is aligned \ 430 * to a 4-byte boundary. \ 431 * \ 432 * XXX BRAINDAMAGE ALERT! \ 433 * The stupid chip uses the same size for every buffer, which \ 434 * is set in the Receive Control register. We are using the 2K \ 435 * size option, but what we REALLY want is (2K - 2)! For this \ 436 * reason, we can't "scoot" packets longer than the standard \ 437 * Ethernet MTU. On strict-alignment platforms, if the total \ 438 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 439 * the upper layer copy the headers. \ 440 */ \ 441 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 442 \ 443 wm_set_dma_addr(&__rxd->wrx_addr, \ 444 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 445 __rxd->wrx_len = 0; \ 446 __rxd->wrx_cksum = 0; \ 447 __rxd->wrx_status = 0; \ 448 __rxd->wrx_errors = 0; \ 449 __rxd->wrx_special = 0; \ 450 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 451 \ 452 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 453 } while (/*CONSTCOND*/0) 454 455 static void wm_start(struct ifnet *); 456 static void wm_watchdog(struct ifnet *); 457 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 458 static int wm_init(struct ifnet *); 459 static void wm_stop(struct ifnet *, int); 460 461 static void wm_shutdown(void *); 462 463 static void wm_reset(struct wm_softc *); 464 static void wm_rxdrain(struct wm_softc *); 465 static int wm_add_rxbuf(struct wm_softc *, int); 466 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 467 static int wm_validate_eeprom_checksum(struct wm_softc *); 468 static void wm_tick(void *); 469 470 static void wm_set_filter(struct wm_softc *); 471 472 static int wm_intr(void *); 473 static void wm_txintr(struct wm_softc *); 474 static void wm_rxintr(struct wm_softc *); 475 static void wm_linkintr(struct wm_softc *, uint32_t); 476 477 static void wm_tbi_mediainit(struct wm_softc *); 478 static int wm_tbi_mediachange(struct ifnet *); 479 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 480 481 static void wm_tbi_set_linkled(struct wm_softc *); 482 static void wm_tbi_check_link(struct wm_softc *); 483 484 static void wm_gmii_reset(struct wm_softc *); 485 486 static int wm_gmii_i82543_readreg(struct device *, int, int); 487 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 488 489 static int wm_gmii_i82544_readreg(struct device *, int, int); 490 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 491 492 static void wm_gmii_statchg(struct device *); 493 494 static void wm_gmii_mediainit(struct wm_softc *); 495 static int wm_gmii_mediachange(struct ifnet *); 496 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 497 498 static int wm_match(struct device *, struct cfdata *, void *); 499 static void wm_attach(struct device *, struct device *, void *); 500 501 CFATTACH_DECL(wm, sizeof(struct wm_softc), 502 wm_match, wm_attach, NULL, NULL); 503 504 static void wm_82547_txfifo_stall(void *); 505 506 /* 507 * Devices supported by this driver. 508 */ 509 static const struct wm_product { 510 pci_vendor_id_t wmp_vendor; 511 pci_product_id_t wmp_product; 512 const char *wmp_name; 513 wm_chip_type wmp_type; 514 int wmp_flags; 515 #define WMP_F_1000X 0x01 516 #define WMP_F_1000T 0x02 517 } wm_products[] = { 518 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 519 "Intel i82542 1000BASE-X Ethernet", 520 WM_T_82542_2_1, WMP_F_1000X }, 521 522 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 523 "Intel i82543GC 1000BASE-X Ethernet", 524 WM_T_82543, WMP_F_1000X }, 525 526 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 527 "Intel i82543GC 1000BASE-T Ethernet", 528 WM_T_82543, WMP_F_1000T }, 529 530 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 531 "Intel i82544EI 1000BASE-T Ethernet", 532 WM_T_82544, WMP_F_1000T }, 533 534 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 535 "Intel i82544EI 1000BASE-X Ethernet", 536 WM_T_82544, WMP_F_1000X }, 537 538 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 539 "Intel i82544GC 1000BASE-T Ethernet", 540 WM_T_82544, WMP_F_1000T }, 541 542 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 543 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 544 WM_T_82544, WMP_F_1000T }, 545 546 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 547 "Intel i82540EM 1000BASE-T Ethernet", 548 WM_T_82540, WMP_F_1000T }, 549 550 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 551 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 552 WM_T_82540, WMP_F_1000T }, 553 554 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 555 "Intel i82540EP 1000BASE-T Ethernet", 556 WM_T_82540, WMP_F_1000T }, 557 558 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 559 "Intel i82540EP 1000BASE-T Ethernet", 560 WM_T_82540, WMP_F_1000T }, 561 562 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 563 "Intel i82540EP 1000BASE-T Ethernet", 564 WM_T_82540, WMP_F_1000T }, 565 566 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 567 "Intel i82545EM 1000BASE-T Ethernet", 568 WM_T_82545, WMP_F_1000T }, 569 570 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 571 "Intel i82545GM 1000BASE-T Ethernet", 572 WM_T_82545_3, WMP_F_1000T }, 573 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 575 "Intel i82545GM 1000BASE-X Ethernet", 576 WM_T_82545_3, WMP_F_1000X }, 577 #if 0 578 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 579 "Intel i82545GM Gigabit Ethernet (SERDES)", 580 WM_T_82545_3, WMP_F_SERDES }, 581 #endif 582 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 583 "Intel i82546EB 1000BASE-T Ethernet", 584 WM_T_82546, WMP_F_1000T }, 585 586 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 587 "Intel i82546EB 1000BASE-T Ethernet", 588 WM_T_82546, WMP_F_1000T }, 589 590 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 591 "Intel i82545EM 1000BASE-X Ethernet", 592 WM_T_82545, WMP_F_1000X }, 593 594 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 595 "Intel i82546EB 1000BASE-X Ethernet", 596 WM_T_82546, WMP_F_1000X }, 597 598 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 599 "Intel i82546GB 1000BASE-T Ethernet", 600 WM_T_82546_3, WMP_F_1000T }, 601 602 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 603 "Intel i82546GB 1000BASE-X Ethernet", 604 WM_T_82546_3, WMP_F_1000X }, 605 #if 0 606 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 607 "Intel i82546GB Gigabit Ethernet (SERDES)", 608 WM_T_82546_3, WMP_F_SERDES }, 609 #endif 610 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 611 "Intel i82541EI 1000BASE-T Ethernet", 612 WM_T_82541, WMP_F_1000T }, 613 614 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 615 "Intel i82541EI Mobile 1000BASE-T Ethernet", 616 WM_T_82541, WMP_F_1000T }, 617 618 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 619 "Intel i82541ER 1000BASE-T Ethernet", 620 WM_T_82541_2, WMP_F_1000T }, 621 622 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 623 "Intel i82541GI 1000BASE-T Ethernet", 624 WM_T_82541_2, WMP_F_1000T }, 625 626 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 627 "Intel i82541GI Mobile 1000BASE-T Ethernet", 628 WM_T_82541_2, WMP_F_1000T }, 629 630 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 631 "Intel i82541PI 1000BASE-T Ethernet", 632 WM_T_82541_2, WMP_F_1000T }, 633 634 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 635 "Intel i82547EI 1000BASE-T Ethernet", 636 WM_T_82547, WMP_F_1000T }, 637 638 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 639 "Intel i82547GI 1000BASE-T Ethernet", 640 WM_T_82547_2, WMP_F_1000T }, 641 { 0, 0, 642 NULL, 643 0, 0 }, 644 }; 645 646 #ifdef WM_EVENT_COUNTERS 647 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 648 #endif /* WM_EVENT_COUNTERS */ 649 650 #if 0 /* Not currently used */ 651 static inline uint32_t 652 wm_io_read(struct wm_softc *sc, int reg) 653 { 654 655 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 656 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 657 } 658 #endif 659 660 static inline void 661 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 662 { 663 664 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 665 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 666 } 667 668 static inline void 669 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 670 { 671 wa->wa_low = htole32(v & 0xffffffffU); 672 if (sizeof(bus_addr_t) == 8) 673 wa->wa_high = htole32((uint64_t) v >> 32); 674 else 675 wa->wa_high = 0; 676 } 677 678 static const struct wm_product * 679 wm_lookup(const struct pci_attach_args *pa) 680 { 681 const struct wm_product *wmp; 682 683 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 684 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 685 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 686 return (wmp); 687 } 688 return (NULL); 689 } 690 691 static int 692 wm_match(struct device *parent, struct cfdata *cf, void *aux) 693 { 694 struct pci_attach_args *pa = aux; 695 696 if (wm_lookup(pa) != NULL) 697 return (1); 698 699 return (0); 700 } 701 702 static void 703 wm_attach(struct device *parent, struct device *self, void *aux) 704 { 705 struct wm_softc *sc = (void *) self; 706 struct pci_attach_args *pa = aux; 707 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 708 pci_chipset_tag_t pc = pa->pa_pc; 709 pci_intr_handle_t ih; 710 size_t cdata_size; 711 const char *intrstr = NULL; 712 const char *eetype; 713 bus_space_tag_t memt; 714 bus_space_handle_t memh; 715 bus_dma_segment_t seg; 716 int memh_valid; 717 int i, rseg, error; 718 const struct wm_product *wmp; 719 prop_data_t ea; 720 prop_number_t pn; 721 uint8_t enaddr[ETHER_ADDR_LEN]; 722 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 723 pcireg_t preg, memtype; 724 uint32_t reg; 725 int pmreg; 726 727 callout_init(&sc->sc_tick_ch); 728 729 wmp = wm_lookup(pa); 730 if (wmp == NULL) { 731 printf("\n"); 732 panic("wm_attach: impossible"); 733 } 734 735 if (pci_dma64_available(pa)) 736 sc->sc_dmat = pa->pa_dmat64; 737 else 738 sc->sc_dmat = pa->pa_dmat; 739 740 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 741 aprint_naive(": Ethernet controller\n"); 742 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 743 744 sc->sc_type = wmp->wmp_type; 745 if (sc->sc_type < WM_T_82543) { 746 if (preg < 2) { 747 aprint_error("%s: i82542 must be at least rev. 2\n", 748 sc->sc_dev.dv_xname); 749 return; 750 } 751 if (preg < 3) 752 sc->sc_type = WM_T_82542_2_0; 753 } 754 755 /* 756 * Map the device. All devices support memory-mapped acccess, 757 * and it is really required for normal operation. 758 */ 759 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 760 switch (memtype) { 761 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 762 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 763 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 764 memtype, 0, &memt, &memh, NULL, NULL) == 0); 765 break; 766 default: 767 memh_valid = 0; 768 } 769 770 if (memh_valid) { 771 sc->sc_st = memt; 772 sc->sc_sh = memh; 773 } else { 774 aprint_error("%s: unable to map device registers\n", 775 sc->sc_dev.dv_xname); 776 return; 777 } 778 779 /* 780 * In addition, i82544 and later support I/O mapped indirect 781 * register access. It is not desirable (nor supported in 782 * this driver) to use it for normal operation, though it is 783 * required to work around bugs in some chip versions. 784 */ 785 if (sc->sc_type >= WM_T_82544) { 786 /* First we have to find the I/O BAR. */ 787 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 788 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 789 PCI_MAPREG_TYPE_IO) 790 break; 791 } 792 if (i == PCI_MAPREG_END) 793 aprint_error("%s: WARNING: unable to find I/O BAR\n", 794 sc->sc_dev.dv_xname); 795 else { 796 /* 797 * The i8254x doesn't apparently respond when the 798 * I/O BAR is 0, which looks somewhat like it's not 799 * been configured. 800 */ 801 preg = pci_conf_read(pc, pa->pa_tag, i); 802 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 803 aprint_error("%s: WARNING: I/O BAR at zero.\n", 804 sc->sc_dev.dv_xname); 805 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 806 0, &sc->sc_iot, &sc->sc_ioh, 807 NULL, NULL) == 0) { 808 sc->sc_flags |= WM_F_IOH_VALID; 809 } else { 810 aprint_error("%s: WARNING: unable to map " 811 "I/O space\n", sc->sc_dev.dv_xname); 812 } 813 } 814 815 } 816 817 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 818 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 819 preg |= PCI_COMMAND_MASTER_ENABLE; 820 if (sc->sc_type < WM_T_82542_2_1) 821 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 822 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 823 824 /* Get it out of power save mode, if needed. */ 825 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 826 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 827 PCI_PMCSR_STATE_MASK; 828 if (preg == PCI_PMCSR_STATE_D3) { 829 /* 830 * The card has lost all configuration data in 831 * this state, so punt. 832 */ 833 aprint_error("%s: unable to wake from power state D3\n", 834 sc->sc_dev.dv_xname); 835 return; 836 } 837 if (preg != PCI_PMCSR_STATE_D0) { 838 aprint_normal("%s: waking up from power state D%d\n", 839 sc->sc_dev.dv_xname, preg); 840 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 841 PCI_PMCSR_STATE_D0); 842 } 843 } 844 845 /* 846 * Map and establish our interrupt. 847 */ 848 if (pci_intr_map(pa, &ih)) { 849 aprint_error("%s: unable to map interrupt\n", 850 sc->sc_dev.dv_xname); 851 return; 852 } 853 intrstr = pci_intr_string(pc, ih); 854 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 855 if (sc->sc_ih == NULL) { 856 aprint_error("%s: unable to establish interrupt", 857 sc->sc_dev.dv_xname); 858 if (intrstr != NULL) 859 aprint_normal(" at %s", intrstr); 860 aprint_normal("\n"); 861 return; 862 } 863 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 864 865 /* 866 * Determine a few things about the bus we're connected to. 867 */ 868 if (sc->sc_type < WM_T_82543) { 869 /* We don't really know the bus characteristics here. */ 870 sc->sc_bus_speed = 33; 871 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 872 /* 873 * CSA (Communication Streaming Architecture) is about as fast 874 * a 32-bit 66MHz PCI Bus. 875 */ 876 sc->sc_flags |= WM_F_CSA; 877 sc->sc_bus_speed = 66; 878 aprint_verbose("%s: Communication Streaming Architecture\n", 879 sc->sc_dev.dv_xname); 880 if (sc->sc_type == WM_T_82547) { 881 callout_init(&sc->sc_txfifo_ch); 882 callout_setfunc(&sc->sc_txfifo_ch, 883 wm_82547_txfifo_stall, sc); 884 aprint_verbose("%s: using 82547 Tx FIFO stall " 885 "work-around\n", sc->sc_dev.dv_xname); 886 } 887 } else { 888 reg = CSR_READ(sc, WMREG_STATUS); 889 if (reg & STATUS_BUS64) 890 sc->sc_flags |= WM_F_BUS64; 891 if (sc->sc_type >= WM_T_82544 && 892 (reg & STATUS_PCIX_MODE) != 0) { 893 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 894 895 sc->sc_flags |= WM_F_PCIX; 896 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 897 PCI_CAP_PCIX, 898 &sc->sc_pcix_offset, NULL) == 0) 899 aprint_error("%s: unable to find PCIX " 900 "capability\n", sc->sc_dev.dv_xname); 901 else if (sc->sc_type != WM_T_82545_3 && 902 sc->sc_type != WM_T_82546_3) { 903 /* 904 * Work around a problem caused by the BIOS 905 * setting the max memory read byte count 906 * incorrectly. 907 */ 908 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 909 sc->sc_pcix_offset + PCI_PCIX_CMD); 910 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 911 sc->sc_pcix_offset + PCI_PCIX_STATUS); 912 913 bytecnt = 914 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 915 PCI_PCIX_CMD_BYTECNT_SHIFT; 916 maxb = 917 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 918 PCI_PCIX_STATUS_MAXB_SHIFT; 919 if (bytecnt > maxb) { 920 aprint_verbose("%s: resetting PCI-X " 921 "MMRBC: %d -> %d\n", 922 sc->sc_dev.dv_xname, 923 512 << bytecnt, 512 << maxb); 924 pcix_cmd = (pcix_cmd & 925 ~PCI_PCIX_CMD_BYTECNT_MASK) | 926 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 927 pci_conf_write(pa->pa_pc, pa->pa_tag, 928 sc->sc_pcix_offset + PCI_PCIX_CMD, 929 pcix_cmd); 930 } 931 } 932 } 933 /* 934 * The quad port adapter is special; it has a PCIX-PCIX 935 * bridge on the board, and can run the secondary bus at 936 * a higher speed. 937 */ 938 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 939 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 940 : 66; 941 } else if (sc->sc_flags & WM_F_PCIX) { 942 switch (reg & STATUS_PCIXSPD_MASK) { 943 case STATUS_PCIXSPD_50_66: 944 sc->sc_bus_speed = 66; 945 break; 946 case STATUS_PCIXSPD_66_100: 947 sc->sc_bus_speed = 100; 948 break; 949 case STATUS_PCIXSPD_100_133: 950 sc->sc_bus_speed = 133; 951 break; 952 default: 953 aprint_error( 954 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 955 sc->sc_dev.dv_xname, 956 reg & STATUS_PCIXSPD_MASK); 957 sc->sc_bus_speed = 66; 958 } 959 } else 960 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 961 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 962 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 963 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 964 } 965 966 /* 967 * Allocate the control data structures, and create and load the 968 * DMA map for it. 969 * 970 * NOTE: All Tx descriptors must be in the same 4G segment of 971 * memory. So must Rx descriptors. We simplify by allocating 972 * both sets within the same 4G segment. 973 */ 974 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 975 WM_NTXDESC_82542 : WM_NTXDESC_82544; 976 cdata_size = sc->sc_type < WM_T_82544 ? 977 sizeof(struct wm_control_data_82542) : 978 sizeof(struct wm_control_data_82544); 979 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 980 (bus_size_t) 0x100000000ULL, 981 &seg, 1, &rseg, 0)) != 0) { 982 aprint_error( 983 "%s: unable to allocate control data, error = %d\n", 984 sc->sc_dev.dv_xname, error); 985 goto fail_0; 986 } 987 988 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 989 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 990 aprint_error("%s: unable to map control data, error = %d\n", 991 sc->sc_dev.dv_xname, error); 992 goto fail_1; 993 } 994 995 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 996 0, 0, &sc->sc_cddmamap)) != 0) { 997 aprint_error("%s: unable to create control data DMA map, " 998 "error = %d\n", sc->sc_dev.dv_xname, error); 999 goto fail_2; 1000 } 1001 1002 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1003 sc->sc_control_data, cdata_size, NULL, 1004 0)) != 0) { 1005 aprint_error( 1006 "%s: unable to load control data DMA map, error = %d\n", 1007 sc->sc_dev.dv_xname, error); 1008 goto fail_3; 1009 } 1010 1011 1012 /* 1013 * Create the transmit buffer DMA maps. 1014 */ 1015 WM_TXQUEUELEN(sc) = 1016 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1017 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1018 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1019 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1020 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1021 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1022 aprint_error("%s: unable to create Tx DMA map %d, " 1023 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1024 goto fail_4; 1025 } 1026 } 1027 1028 /* 1029 * Create the receive buffer DMA maps. 1030 */ 1031 for (i = 0; i < WM_NRXDESC; i++) { 1032 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1033 MCLBYTES, 0, 0, 1034 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1035 aprint_error("%s: unable to create Rx DMA map %d, " 1036 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1037 goto fail_5; 1038 } 1039 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1040 } 1041 1042 /* 1043 * Reset the chip to a known state. 1044 */ 1045 wm_reset(sc); 1046 1047 /* 1048 * Get some information about the EEPROM. 1049 */ 1050 if (sc->sc_type >= WM_T_82540) 1051 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1052 if (sc->sc_type <= WM_T_82544) 1053 sc->sc_ee_addrbits = 6; 1054 else if (sc->sc_type <= WM_T_82546_3) { 1055 reg = CSR_READ(sc, WMREG_EECD); 1056 if (reg & EECD_EE_SIZE) 1057 sc->sc_ee_addrbits = 8; 1058 else 1059 sc->sc_ee_addrbits = 6; 1060 } else if (sc->sc_type <= WM_T_82547_2) { 1061 reg = CSR_READ(sc, WMREG_EECD); 1062 if (reg & EECD_EE_TYPE) { 1063 sc->sc_flags |= WM_F_EEPROM_SPI; 1064 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1065 } else 1066 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1067 } else { 1068 /* Assume everything else is SPI. */ 1069 reg = CSR_READ(sc, WMREG_EECD); 1070 sc->sc_flags |= WM_F_EEPROM_SPI; 1071 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1072 } 1073 1074 /* 1075 * Defer printing the EEPROM type until after verifying the checksum 1076 * This allows the EEPROM type to be printed correctly in the case 1077 * that no EEPROM is attached. 1078 */ 1079 1080 1081 /* 1082 * Validate the EEPROM checksum. If the checksum fails, flag this for 1083 * later, so we can fail future reads from the EEPROM. 1084 */ 1085 if (wm_validate_eeprom_checksum(sc)) 1086 sc->sc_flags |= WM_F_EEPROM_INVALID; 1087 1088 if (sc->sc_flags & WM_F_EEPROM_INVALID) 1089 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname); 1090 else { 1091 if (sc->sc_flags & WM_F_EEPROM_SPI) 1092 eetype = "SPI"; 1093 else 1094 eetype = "MicroWire"; 1095 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1096 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1097 sc->sc_ee_addrbits, eetype); 1098 } 1099 1100 /* 1101 * Read the Ethernet address from the EEPROM, if not first found 1102 * in device properties. 1103 */ 1104 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 1105 if (ea != NULL) { 1106 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 1107 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 1108 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 1109 } else { 1110 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1111 sizeof(myea) / sizeof(myea[0]), myea)) { 1112 aprint_error("%s: unable to read Ethernet address\n", 1113 sc->sc_dev.dv_xname); 1114 return; 1115 } 1116 enaddr[0] = myea[0] & 0xff; 1117 enaddr[1] = myea[0] >> 8; 1118 enaddr[2] = myea[1] & 0xff; 1119 enaddr[3] = myea[1] >> 8; 1120 enaddr[4] = myea[2] & 0xff; 1121 enaddr[5] = myea[2] >> 8; 1122 } 1123 1124 /* 1125 * Toggle the LSB of the MAC address on the second port 1126 * of the i82546. 1127 */ 1128 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1129 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1130 enaddr[5] ^= 1; 1131 } 1132 1133 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1134 ether_sprintf(enaddr)); 1135 1136 /* 1137 * Read the config info from the EEPROM, and set up various 1138 * bits in the control registers based on their contents. 1139 */ 1140 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1141 "i82543-cfg1"); 1142 if (pn != NULL) { 1143 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1144 cfg1 = (uint16_t) prop_number_integer_value(pn); 1145 } else { 1146 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1147 aprint_error("%s: unable to read CFG1\n", 1148 sc->sc_dev.dv_xname); 1149 return; 1150 } 1151 } 1152 1153 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1154 "i82543-cfg2"); 1155 if (pn != NULL) { 1156 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1157 cfg2 = (uint16_t) prop_number_integer_value(pn); 1158 } else { 1159 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1160 aprint_error("%s: unable to read CFG2\n", 1161 sc->sc_dev.dv_xname); 1162 return; 1163 } 1164 } 1165 1166 if (sc->sc_type >= WM_T_82544) { 1167 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1168 "i82543-swdpin"); 1169 if (pn != NULL) { 1170 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1171 swdpin = (uint16_t) prop_number_integer_value(pn); 1172 } else { 1173 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1174 aprint_error("%s: unable to read SWDPIN\n", 1175 sc->sc_dev.dv_xname); 1176 return; 1177 } 1178 } 1179 } 1180 1181 if (cfg1 & EEPROM_CFG1_ILOS) 1182 sc->sc_ctrl |= CTRL_ILOS; 1183 if (sc->sc_type >= WM_T_82544) { 1184 sc->sc_ctrl |= 1185 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1186 CTRL_SWDPIO_SHIFT; 1187 sc->sc_ctrl |= 1188 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1189 CTRL_SWDPINS_SHIFT; 1190 } else { 1191 sc->sc_ctrl |= 1192 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1193 CTRL_SWDPIO_SHIFT; 1194 } 1195 1196 #if 0 1197 if (sc->sc_type >= WM_T_82544) { 1198 if (cfg1 & EEPROM_CFG1_IPS0) 1199 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1200 if (cfg1 & EEPROM_CFG1_IPS1) 1201 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1202 sc->sc_ctrl_ext |= 1203 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1204 CTRL_EXT_SWDPIO_SHIFT; 1205 sc->sc_ctrl_ext |= 1206 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1207 CTRL_EXT_SWDPINS_SHIFT; 1208 } else { 1209 sc->sc_ctrl_ext |= 1210 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1211 CTRL_EXT_SWDPIO_SHIFT; 1212 } 1213 #endif 1214 1215 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1216 #if 0 1217 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1218 #endif 1219 1220 /* 1221 * Set up some register offsets that are different between 1222 * the i82542 and the i82543 and later chips. 1223 */ 1224 if (sc->sc_type < WM_T_82543) { 1225 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1226 sc->sc_tdt_reg = WMREG_OLD_TDT; 1227 } else { 1228 sc->sc_rdt_reg = WMREG_RDT; 1229 sc->sc_tdt_reg = WMREG_TDT; 1230 } 1231 1232 /* 1233 * Determine if we're TBI or GMII mode, and initialize the 1234 * media structures accordingly. 1235 */ 1236 if (sc->sc_type < WM_T_82543 || 1237 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1238 if (wmp->wmp_flags & WMP_F_1000T) 1239 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1240 "product!\n", sc->sc_dev.dv_xname); 1241 wm_tbi_mediainit(sc); 1242 } else { 1243 if (wmp->wmp_flags & WMP_F_1000X) 1244 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1245 "product!\n", sc->sc_dev.dv_xname); 1246 wm_gmii_mediainit(sc); 1247 } 1248 1249 ifp = &sc->sc_ethercom.ec_if; 1250 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1251 ifp->if_softc = sc; 1252 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1253 ifp->if_ioctl = wm_ioctl; 1254 ifp->if_start = wm_start; 1255 ifp->if_watchdog = wm_watchdog; 1256 ifp->if_init = wm_init; 1257 ifp->if_stop = wm_stop; 1258 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1259 IFQ_SET_READY(&ifp->if_snd); 1260 1261 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1262 1263 /* 1264 * If we're a i82543 or greater, we can support VLANs. 1265 */ 1266 if (sc->sc_type >= WM_T_82543) 1267 sc->sc_ethercom.ec_capabilities |= 1268 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1269 1270 /* 1271 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1272 * on i82543 and later. 1273 */ 1274 if (sc->sc_type >= WM_T_82543) 1275 ifp->if_capabilities |= 1276 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1277 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1278 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1279 IFCAP_CSUM_TCPv6_Tx | 1280 IFCAP_CSUM_UDPv6_Tx; 1281 1282 /* 1283 * If we're a i82544 or greater (except i82547), we can do 1284 * TCP segmentation offload. 1285 */ 1286 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1287 ifp->if_capabilities |= IFCAP_TSOv4; 1288 1289 /* 1290 * Attach the interface. 1291 */ 1292 if_attach(ifp); 1293 ether_ifattach(ifp, enaddr); 1294 #if NRND > 0 1295 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1296 RND_TYPE_NET, 0); 1297 #endif 1298 1299 #ifdef WM_EVENT_COUNTERS 1300 /* Attach event counters. */ 1301 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1302 NULL, sc->sc_dev.dv_xname, "txsstall"); 1303 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1304 NULL, sc->sc_dev.dv_xname, "txdstall"); 1305 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1306 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1307 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1308 NULL, sc->sc_dev.dv_xname, "txdw"); 1309 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1310 NULL, sc->sc_dev.dv_xname, "txqe"); 1311 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1312 NULL, sc->sc_dev.dv_xname, "rxintr"); 1313 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1314 NULL, sc->sc_dev.dv_xname, "linkintr"); 1315 1316 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1317 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1318 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1319 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1320 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1321 NULL, sc->sc_dev.dv_xname, "txipsum"); 1322 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1323 NULL, sc->sc_dev.dv_xname, "txtusum"); 1324 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1325 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1326 1327 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1328 NULL, sc->sc_dev.dv_xname, "txtso"); 1329 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1330 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1331 1332 for (i = 0; i < WM_NTXSEGS; i++) { 1333 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1334 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1335 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1336 } 1337 1338 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1339 NULL, sc->sc_dev.dv_xname, "txdrop"); 1340 1341 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1342 NULL, sc->sc_dev.dv_xname, "tu"); 1343 1344 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1345 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1346 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1347 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1348 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1349 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1350 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1351 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1352 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1353 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1354 #endif /* WM_EVENT_COUNTERS */ 1355 1356 /* 1357 * Make sure the interface is shutdown during reboot. 1358 */ 1359 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1360 if (sc->sc_sdhook == NULL) 1361 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1362 sc->sc_dev.dv_xname); 1363 return; 1364 1365 /* 1366 * Free any resources we've allocated during the failed attach 1367 * attempt. Do this in reverse order and fall through. 1368 */ 1369 fail_5: 1370 for (i = 0; i < WM_NRXDESC; i++) { 1371 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1372 bus_dmamap_destroy(sc->sc_dmat, 1373 sc->sc_rxsoft[i].rxs_dmamap); 1374 } 1375 fail_4: 1376 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1377 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1378 bus_dmamap_destroy(sc->sc_dmat, 1379 sc->sc_txsoft[i].txs_dmamap); 1380 } 1381 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1382 fail_3: 1383 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1384 fail_2: 1385 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1386 cdata_size); 1387 fail_1: 1388 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1389 fail_0: 1390 return; 1391 } 1392 1393 /* 1394 * wm_shutdown: 1395 * 1396 * Make sure the interface is stopped at reboot time. 1397 */ 1398 static void 1399 wm_shutdown(void *arg) 1400 { 1401 struct wm_softc *sc = arg; 1402 1403 wm_stop(&sc->sc_ethercom.ec_if, 1); 1404 } 1405 1406 /* 1407 * wm_tx_offload: 1408 * 1409 * Set up TCP/IP checksumming parameters for the 1410 * specified packet. 1411 */ 1412 static int 1413 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1414 uint8_t *fieldsp) 1415 { 1416 struct mbuf *m0 = txs->txs_mbuf; 1417 struct livengood_tcpip_ctxdesc *t; 1418 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1419 struct ether_header *eh; 1420 int offset, iphl; 1421 uint8_t fields; 1422 1423 /* 1424 * XXX It would be nice if the mbuf pkthdr had offset 1425 * fields for the protocol headers. 1426 */ 1427 1428 eh = mtod(m0, struct ether_header *); 1429 switch (htons(eh->ether_type)) { 1430 case ETHERTYPE_IP: 1431 case ETHERTYPE_IPV6: 1432 offset = ETHER_HDR_LEN; 1433 break; 1434 1435 case ETHERTYPE_VLAN: 1436 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1437 break; 1438 1439 default: 1440 /* 1441 * Don't support this protocol or encapsulation. 1442 */ 1443 *fieldsp = 0; 1444 *cmdp = 0; 1445 return (0); 1446 } 1447 1448 if ((m0->m_pkthdr.csum_flags & 1449 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1450 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1451 } else { 1452 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1453 } 1454 1455 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1456 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1457 seg = 0; 1458 fields = 0; 1459 1460 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1461 int hlen = offset + iphl; 1462 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1463 if (__predict_false(m0->m_len < 1464 (hlen + sizeof(struct tcphdr)))) { 1465 /* 1466 * TCP/IP headers are not in the first mbuf; we need 1467 * to do this the slow and painful way. Let's just 1468 * hope this doesn't happen very often. 1469 */ 1470 struct ip ip; 1471 struct tcphdr th; 1472 1473 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1474 1475 m_copydata(m0, offset, sizeof(ip), &ip); 1476 m_copydata(m0, hlen, sizeof(th), &th); 1477 1478 ip.ip_len = 0; 1479 1480 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1481 sizeof(ip.ip_len), &ip.ip_len); 1482 1483 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1484 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1485 1486 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1487 sizeof(th.th_sum), &th.th_sum); 1488 1489 hlen += th.th_off << 2; 1490 } else { 1491 /* 1492 * TCP/IP headers are in the first mbuf; we can do 1493 * this the easy way. 1494 */ 1495 struct ip *ip = 1496 (struct ip *) (mtod(m0, caddr_t) + offset); 1497 struct tcphdr *th = 1498 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1499 1500 ip->ip_len = 0; 1501 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1502 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1503 1504 hlen += th->th_off << 2; 1505 } 1506 1507 cmd |= WTX_TCPIP_CMD_TSE; 1508 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1509 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1510 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1511 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1512 } 1513 1514 /* 1515 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1516 * offload feature, if we load the context descriptor, we 1517 * MUST provide valid values for IPCSS and TUCSS fields. 1518 */ 1519 1520 ipcs = WTX_TCPIP_IPCSS(offset) | 1521 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1522 WTX_TCPIP_IPCSE(offset + iphl - 1); 1523 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1524 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1525 fields |= WTX_IXSM; 1526 } 1527 1528 offset += iphl; 1529 1530 if (m0->m_pkthdr.csum_flags & 1531 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1532 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1533 fields |= WTX_TXSM; 1534 tucs = WTX_TCPIP_TUCSS(offset) | 1535 WTX_TCPIP_TUCSO(offset + 1536 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1537 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1538 } else if ((m0->m_pkthdr.csum_flags & 1539 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) { 1540 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1541 fields |= WTX_TXSM; 1542 tucs = WTX_TCPIP_TUCSS(offset) | 1543 WTX_TCPIP_TUCSO(offset + 1544 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1545 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1546 } else { 1547 /* Just initialize it to a valid TCP context. */ 1548 tucs = WTX_TCPIP_TUCSS(offset) | 1549 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1550 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1551 } 1552 1553 /* Fill in the context descriptor. */ 1554 t = (struct livengood_tcpip_ctxdesc *) 1555 &sc->sc_txdescs[sc->sc_txnext]; 1556 t->tcpip_ipcs = htole32(ipcs); 1557 t->tcpip_tucs = htole32(tucs); 1558 t->tcpip_cmdlen = htole32(cmdlen); 1559 t->tcpip_seg = htole32(seg); 1560 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1561 1562 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1563 txs->txs_ndesc++; 1564 1565 *cmdp = cmd; 1566 *fieldsp = fields; 1567 1568 return (0); 1569 } 1570 1571 static void 1572 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1573 { 1574 struct mbuf *m; 1575 int i; 1576 1577 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1578 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1579 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1580 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1581 m->m_data, m->m_len, m->m_flags); 1582 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1583 i, i == 1 ? "" : "s"); 1584 } 1585 1586 /* 1587 * wm_82547_txfifo_stall: 1588 * 1589 * Callout used to wait for the 82547 Tx FIFO to drain, 1590 * reset the FIFO pointers, and restart packet transmission. 1591 */ 1592 static void 1593 wm_82547_txfifo_stall(void *arg) 1594 { 1595 struct wm_softc *sc = arg; 1596 int s; 1597 1598 s = splnet(); 1599 1600 if (sc->sc_txfifo_stall) { 1601 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1602 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1603 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1604 /* 1605 * Packets have drained. Stop transmitter, reset 1606 * FIFO pointers, restart transmitter, and kick 1607 * the packet queue. 1608 */ 1609 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1610 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1611 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1612 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1613 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1614 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1615 CSR_WRITE(sc, WMREG_TCTL, tctl); 1616 CSR_WRITE_FLUSH(sc); 1617 1618 sc->sc_txfifo_head = 0; 1619 sc->sc_txfifo_stall = 0; 1620 wm_start(&sc->sc_ethercom.ec_if); 1621 } else { 1622 /* 1623 * Still waiting for packets to drain; try again in 1624 * another tick. 1625 */ 1626 callout_schedule(&sc->sc_txfifo_ch, 1); 1627 } 1628 } 1629 1630 splx(s); 1631 } 1632 1633 /* 1634 * wm_82547_txfifo_bugchk: 1635 * 1636 * Check for bug condition in the 82547 Tx FIFO. We need to 1637 * prevent enqueueing a packet that would wrap around the end 1638 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1639 * 1640 * We do this by checking the amount of space before the end 1641 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1642 * the Tx FIFO, wait for all remaining packets to drain, reset 1643 * the internal FIFO pointers to the beginning, and restart 1644 * transmission on the interface. 1645 */ 1646 #define WM_FIFO_HDR 0x10 1647 #define WM_82547_PAD_LEN 0x3e0 1648 static int 1649 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1650 { 1651 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1652 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1653 1654 /* Just return if already stalled. */ 1655 if (sc->sc_txfifo_stall) 1656 return (1); 1657 1658 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1659 /* Stall only occurs in half-duplex mode. */ 1660 goto send_packet; 1661 } 1662 1663 if (len >= WM_82547_PAD_LEN + space) { 1664 sc->sc_txfifo_stall = 1; 1665 callout_schedule(&sc->sc_txfifo_ch, 1); 1666 return (1); 1667 } 1668 1669 send_packet: 1670 sc->sc_txfifo_head += len; 1671 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1672 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1673 1674 return (0); 1675 } 1676 1677 /* 1678 * wm_start: [ifnet interface function] 1679 * 1680 * Start packet transmission on the interface. 1681 */ 1682 static void 1683 wm_start(struct ifnet *ifp) 1684 { 1685 struct wm_softc *sc = ifp->if_softc; 1686 struct mbuf *m0; 1687 #if 0 /* XXXJRT */ 1688 struct m_tag *mtag; 1689 #endif 1690 struct wm_txsoft *txs; 1691 bus_dmamap_t dmamap; 1692 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1693 bus_addr_t curaddr; 1694 bus_size_t seglen, curlen; 1695 uint32_t cksumcmd; 1696 uint8_t cksumfields; 1697 1698 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1699 return; 1700 1701 /* 1702 * Remember the previous number of free descriptors. 1703 */ 1704 ofree = sc->sc_txfree; 1705 1706 /* 1707 * Loop through the send queue, setting up transmit descriptors 1708 * until we drain the queue, or use up all available transmit 1709 * descriptors. 1710 */ 1711 for (;;) { 1712 /* Grab a packet off the queue. */ 1713 IFQ_POLL(&ifp->if_snd, m0); 1714 if (m0 == NULL) 1715 break; 1716 1717 DPRINTF(WM_DEBUG_TX, 1718 ("%s: TX: have packet to transmit: %p\n", 1719 sc->sc_dev.dv_xname, m0)); 1720 1721 /* Get a work queue entry. */ 1722 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1723 wm_txintr(sc); 1724 if (sc->sc_txsfree == 0) { 1725 DPRINTF(WM_DEBUG_TX, 1726 ("%s: TX: no free job descriptors\n", 1727 sc->sc_dev.dv_xname)); 1728 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1729 break; 1730 } 1731 } 1732 1733 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1734 dmamap = txs->txs_dmamap; 1735 1736 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1737 1738 /* 1739 * So says the Linux driver: 1740 * The controller does a simple calculation to make sure 1741 * there is enough room in the FIFO before initiating the 1742 * DMA for each buffer. The calc is: 1743 * 4 = ceil(buffer len / MSS) 1744 * To make sure we don't overrun the FIFO, adjust the max 1745 * buffer len if the MSS drops. 1746 */ 1747 dmamap->dm_maxsegsz = 1748 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1749 ? m0->m_pkthdr.segsz << 2 1750 : WTX_MAX_LEN; 1751 1752 /* 1753 * Load the DMA map. If this fails, the packet either 1754 * didn't fit in the allotted number of segments, or we 1755 * were short on resources. For the too-many-segments 1756 * case, we simply report an error and drop the packet, 1757 * since we can't sanely copy a jumbo packet to a single 1758 * buffer. 1759 */ 1760 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1761 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1762 if (error) { 1763 if (error == EFBIG) { 1764 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1765 log(LOG_ERR, "%s: Tx packet consumes too many " 1766 "DMA segments, dropping...\n", 1767 sc->sc_dev.dv_xname); 1768 IFQ_DEQUEUE(&ifp->if_snd, m0); 1769 wm_dump_mbuf_chain(sc, m0); 1770 m_freem(m0); 1771 continue; 1772 } 1773 /* 1774 * Short on resources, just stop for now. 1775 */ 1776 DPRINTF(WM_DEBUG_TX, 1777 ("%s: TX: dmamap load failed: %d\n", 1778 sc->sc_dev.dv_xname, error)); 1779 break; 1780 } 1781 1782 segs_needed = dmamap->dm_nsegs; 1783 if (use_tso) { 1784 /* For sentinel descriptor; see below. */ 1785 segs_needed++; 1786 } 1787 1788 /* 1789 * Ensure we have enough descriptors free to describe 1790 * the packet. Note, we always reserve one descriptor 1791 * at the end of the ring due to the semantics of the 1792 * TDT register, plus one more in the event we need 1793 * to load offload context. 1794 */ 1795 if (segs_needed > sc->sc_txfree - 2) { 1796 /* 1797 * Not enough free descriptors to transmit this 1798 * packet. We haven't committed anything yet, 1799 * so just unload the DMA map, put the packet 1800 * pack on the queue, and punt. Notify the upper 1801 * layer that there are no more slots left. 1802 */ 1803 DPRINTF(WM_DEBUG_TX, 1804 ("%s: TX: need %d (%d) descriptors, have %d\n", 1805 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1806 sc->sc_txfree - 1)); 1807 ifp->if_flags |= IFF_OACTIVE; 1808 bus_dmamap_unload(sc->sc_dmat, dmamap); 1809 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1810 break; 1811 } 1812 1813 /* 1814 * Check for 82547 Tx FIFO bug. We need to do this 1815 * once we know we can transmit the packet, since we 1816 * do some internal FIFO space accounting here. 1817 */ 1818 if (sc->sc_type == WM_T_82547 && 1819 wm_82547_txfifo_bugchk(sc, m0)) { 1820 DPRINTF(WM_DEBUG_TX, 1821 ("%s: TX: 82547 Tx FIFO bug detected\n", 1822 sc->sc_dev.dv_xname)); 1823 ifp->if_flags |= IFF_OACTIVE; 1824 bus_dmamap_unload(sc->sc_dmat, dmamap); 1825 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1826 break; 1827 } 1828 1829 IFQ_DEQUEUE(&ifp->if_snd, m0); 1830 1831 /* 1832 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1833 */ 1834 1835 DPRINTF(WM_DEBUG_TX, 1836 ("%s: TX: packet has %d (%d) DMA segments\n", 1837 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1838 1839 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1840 1841 /* 1842 * Store a pointer to the packet so that we can free it 1843 * later. 1844 * 1845 * Initially, we consider the number of descriptors the 1846 * packet uses the number of DMA segments. This may be 1847 * incremented by 1 if we do checksum offload (a descriptor 1848 * is used to set the checksum context). 1849 */ 1850 txs->txs_mbuf = m0; 1851 txs->txs_firstdesc = sc->sc_txnext; 1852 txs->txs_ndesc = segs_needed; 1853 1854 /* Set up offload parameters for this packet. */ 1855 if (m0->m_pkthdr.csum_flags & 1856 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 1857 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 1858 if (wm_tx_offload(sc, txs, &cksumcmd, 1859 &cksumfields) != 0) { 1860 /* Error message already displayed. */ 1861 bus_dmamap_unload(sc->sc_dmat, dmamap); 1862 continue; 1863 } 1864 } else { 1865 cksumcmd = 0; 1866 cksumfields = 0; 1867 } 1868 1869 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1870 1871 /* Sync the DMA map. */ 1872 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1873 BUS_DMASYNC_PREWRITE); 1874 1875 /* 1876 * Initialize the transmit descriptor. 1877 */ 1878 for (nexttx = sc->sc_txnext, seg = 0; 1879 seg < dmamap->dm_nsegs; seg++) { 1880 for (seglen = dmamap->dm_segs[seg].ds_len, 1881 curaddr = dmamap->dm_segs[seg].ds_addr; 1882 seglen != 0; 1883 curaddr += curlen, seglen -= curlen, 1884 nexttx = WM_NEXTTX(sc, nexttx)) { 1885 curlen = seglen; 1886 1887 /* 1888 * So says the Linux driver: 1889 * Work around for premature descriptor 1890 * write-backs in TSO mode. Append a 1891 * 4-byte sentinel descriptor. 1892 */ 1893 if (use_tso && 1894 seg == dmamap->dm_nsegs - 1 && 1895 curlen > 8) 1896 curlen -= 4; 1897 1898 wm_set_dma_addr( 1899 &sc->sc_txdescs[nexttx].wtx_addr, 1900 curaddr); 1901 sc->sc_txdescs[nexttx].wtx_cmdlen = 1902 htole32(cksumcmd | curlen); 1903 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1904 0; 1905 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1906 cksumfields; 1907 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1908 lasttx = nexttx; 1909 1910 DPRINTF(WM_DEBUG_TX, 1911 ("%s: TX: desc %d: low 0x%08lx, " 1912 "len 0x%04x\n", 1913 sc->sc_dev.dv_xname, nexttx, 1914 curaddr & 0xffffffffUL, (unsigned)curlen)); 1915 } 1916 } 1917 1918 KASSERT(lasttx != -1); 1919 1920 /* 1921 * Set up the command byte on the last descriptor of 1922 * the packet. If we're in the interrupt delay window, 1923 * delay the interrupt. 1924 */ 1925 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1926 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1927 1928 #if 0 /* XXXJRT */ 1929 /* 1930 * If VLANs are enabled and the packet has a VLAN tag, set 1931 * up the descriptor to encapsulate the packet for us. 1932 * 1933 * This is only valid on the last descriptor of the packet. 1934 */ 1935 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1936 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1937 htole32(WTX_CMD_VLE); 1938 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1939 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 1940 } 1941 #endif /* XXXJRT */ 1942 1943 txs->txs_lastdesc = lasttx; 1944 1945 DPRINTF(WM_DEBUG_TX, 1946 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1947 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1948 1949 /* Sync the descriptors we're using. */ 1950 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1951 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1952 1953 /* Give the packet to the chip. */ 1954 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1955 1956 DPRINTF(WM_DEBUG_TX, 1957 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1958 1959 DPRINTF(WM_DEBUG_TX, 1960 ("%s: TX: finished transmitting packet, job %d\n", 1961 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1962 1963 /* Advance the tx pointer. */ 1964 sc->sc_txfree -= txs->txs_ndesc; 1965 sc->sc_txnext = nexttx; 1966 1967 sc->sc_txsfree--; 1968 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1969 1970 #if NBPFILTER > 0 1971 /* Pass the packet to any BPF listeners. */ 1972 if (ifp->if_bpf) 1973 bpf_mtap(ifp->if_bpf, m0); 1974 #endif /* NBPFILTER > 0 */ 1975 } 1976 1977 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1978 /* No more slots; notify upper layer. */ 1979 ifp->if_flags |= IFF_OACTIVE; 1980 } 1981 1982 if (sc->sc_txfree != ofree) { 1983 /* Set a watchdog timer in case the chip flakes out. */ 1984 ifp->if_timer = 5; 1985 } 1986 } 1987 1988 /* 1989 * wm_watchdog: [ifnet interface function] 1990 * 1991 * Watchdog timer handler. 1992 */ 1993 static void 1994 wm_watchdog(struct ifnet *ifp) 1995 { 1996 struct wm_softc *sc = ifp->if_softc; 1997 1998 /* 1999 * Since we're using delayed interrupts, sweep up 2000 * before we report an error. 2001 */ 2002 wm_txintr(sc); 2003 2004 if (sc->sc_txfree != WM_NTXDESC(sc)) { 2005 log(LOG_ERR, 2006 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 2007 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 2008 sc->sc_txnext); 2009 ifp->if_oerrors++; 2010 2011 /* Reset the interface. */ 2012 (void) wm_init(ifp); 2013 } 2014 2015 /* Try to get more packets going. */ 2016 wm_start(ifp); 2017 } 2018 2019 /* 2020 * wm_ioctl: [ifnet interface function] 2021 * 2022 * Handle control requests from the operator. 2023 */ 2024 static int 2025 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2026 { 2027 struct wm_softc *sc = ifp->if_softc; 2028 struct ifreq *ifr = (struct ifreq *) data; 2029 int s, error; 2030 2031 s = splnet(); 2032 2033 switch (cmd) { 2034 case SIOCSIFMEDIA: 2035 case SIOCGIFMEDIA: 2036 /* Flow control requires full-duplex mode. */ 2037 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2038 (ifr->ifr_media & IFM_FDX) == 0) 2039 ifr->ifr_media &= ~IFM_ETH_FMASK; 2040 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2041 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2042 /* We can do both TXPAUSE and RXPAUSE. */ 2043 ifr->ifr_media |= 2044 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2045 } 2046 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2047 } 2048 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2049 break; 2050 default: 2051 error = ether_ioctl(ifp, cmd, data); 2052 if (error == ENETRESET) { 2053 /* 2054 * Multicast list has changed; set the hardware filter 2055 * accordingly. 2056 */ 2057 if (ifp->if_flags & IFF_RUNNING) 2058 wm_set_filter(sc); 2059 error = 0; 2060 } 2061 break; 2062 } 2063 2064 /* Try to get more packets going. */ 2065 wm_start(ifp); 2066 2067 splx(s); 2068 return (error); 2069 } 2070 2071 /* 2072 * wm_intr: 2073 * 2074 * Interrupt service routine. 2075 */ 2076 static int 2077 wm_intr(void *arg) 2078 { 2079 struct wm_softc *sc = arg; 2080 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2081 uint32_t icr; 2082 int handled = 0; 2083 2084 while (1 /* CONSTCOND */) { 2085 icr = CSR_READ(sc, WMREG_ICR); 2086 if ((icr & sc->sc_icr) == 0) 2087 break; 2088 2089 #if 0 /*NRND > 0*/ 2090 if (RND_ENABLED(&sc->rnd_source)) 2091 rnd_add_uint32(&sc->rnd_source, icr); 2092 #endif 2093 2094 handled = 1; 2095 2096 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2097 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2098 DPRINTF(WM_DEBUG_RX, 2099 ("%s: RX: got Rx intr 0x%08x\n", 2100 sc->sc_dev.dv_xname, 2101 icr & (ICR_RXDMT0|ICR_RXT0))); 2102 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2103 } 2104 #endif 2105 wm_rxintr(sc); 2106 2107 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2108 if (icr & ICR_TXDW) { 2109 DPRINTF(WM_DEBUG_TX, 2110 ("%s: TX: got TXDW interrupt\n", 2111 sc->sc_dev.dv_xname)); 2112 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2113 } 2114 #endif 2115 wm_txintr(sc); 2116 2117 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2118 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2119 wm_linkintr(sc, icr); 2120 } 2121 2122 if (icr & ICR_RXO) { 2123 ifp->if_ierrors++; 2124 #if defined(WM_DEBUG) 2125 log(LOG_WARNING, "%s: Receive overrun\n", 2126 sc->sc_dev.dv_xname); 2127 #endif /* defined(WM_DEBUG) */ 2128 } 2129 } 2130 2131 if (handled) { 2132 /* Try to get more packets going. */ 2133 wm_start(ifp); 2134 } 2135 2136 return (handled); 2137 } 2138 2139 /* 2140 * wm_txintr: 2141 * 2142 * Helper; handle transmit interrupts. 2143 */ 2144 static void 2145 wm_txintr(struct wm_softc *sc) 2146 { 2147 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2148 struct wm_txsoft *txs; 2149 uint8_t status; 2150 int i; 2151 2152 ifp->if_flags &= ~IFF_OACTIVE; 2153 2154 /* 2155 * Go through the Tx list and free mbufs for those 2156 * frames which have been transmitted. 2157 */ 2158 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2159 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2160 txs = &sc->sc_txsoft[i]; 2161 2162 DPRINTF(WM_DEBUG_TX, 2163 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2164 2165 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2166 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2167 2168 status = 2169 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2170 if ((status & WTX_ST_DD) == 0) { 2171 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2172 BUS_DMASYNC_PREREAD); 2173 break; 2174 } 2175 2176 DPRINTF(WM_DEBUG_TX, 2177 ("%s: TX: job %d done: descs %d..%d\n", 2178 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2179 txs->txs_lastdesc)); 2180 2181 /* 2182 * XXX We should probably be using the statistics 2183 * XXX registers, but I don't know if they exist 2184 * XXX on chips before the i82544. 2185 */ 2186 2187 #ifdef WM_EVENT_COUNTERS 2188 if (status & WTX_ST_TU) 2189 WM_EVCNT_INCR(&sc->sc_ev_tu); 2190 #endif /* WM_EVENT_COUNTERS */ 2191 2192 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2193 ifp->if_oerrors++; 2194 if (status & WTX_ST_LC) 2195 log(LOG_WARNING, "%s: late collision\n", 2196 sc->sc_dev.dv_xname); 2197 else if (status & WTX_ST_EC) { 2198 ifp->if_collisions += 16; 2199 log(LOG_WARNING, "%s: excessive collisions\n", 2200 sc->sc_dev.dv_xname); 2201 } 2202 } else 2203 ifp->if_opackets++; 2204 2205 sc->sc_txfree += txs->txs_ndesc; 2206 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2207 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2208 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2209 m_freem(txs->txs_mbuf); 2210 txs->txs_mbuf = NULL; 2211 } 2212 2213 /* Update the dirty transmit buffer pointer. */ 2214 sc->sc_txsdirty = i; 2215 DPRINTF(WM_DEBUG_TX, 2216 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2217 2218 /* 2219 * If there are no more pending transmissions, cancel the watchdog 2220 * timer. 2221 */ 2222 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2223 ifp->if_timer = 0; 2224 } 2225 2226 /* 2227 * wm_rxintr: 2228 * 2229 * Helper; handle receive interrupts. 2230 */ 2231 static void 2232 wm_rxintr(struct wm_softc *sc) 2233 { 2234 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2235 struct wm_rxsoft *rxs; 2236 struct mbuf *m; 2237 int i, len; 2238 uint8_t status, errors; 2239 2240 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2241 rxs = &sc->sc_rxsoft[i]; 2242 2243 DPRINTF(WM_DEBUG_RX, 2244 ("%s: RX: checking descriptor %d\n", 2245 sc->sc_dev.dv_xname, i)); 2246 2247 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2248 2249 status = sc->sc_rxdescs[i].wrx_status; 2250 errors = sc->sc_rxdescs[i].wrx_errors; 2251 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2252 2253 if ((status & WRX_ST_DD) == 0) { 2254 /* 2255 * We have processed all of the receive descriptors. 2256 */ 2257 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2258 break; 2259 } 2260 2261 if (__predict_false(sc->sc_rxdiscard)) { 2262 DPRINTF(WM_DEBUG_RX, 2263 ("%s: RX: discarding contents of descriptor %d\n", 2264 sc->sc_dev.dv_xname, i)); 2265 WM_INIT_RXDESC(sc, i); 2266 if (status & WRX_ST_EOP) { 2267 /* Reset our state. */ 2268 DPRINTF(WM_DEBUG_RX, 2269 ("%s: RX: resetting rxdiscard -> 0\n", 2270 sc->sc_dev.dv_xname)); 2271 sc->sc_rxdiscard = 0; 2272 } 2273 continue; 2274 } 2275 2276 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2277 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2278 2279 m = rxs->rxs_mbuf; 2280 2281 /* 2282 * Add a new receive buffer to the ring. 2283 */ 2284 if (wm_add_rxbuf(sc, i) != 0) { 2285 /* 2286 * Failed, throw away what we've done so 2287 * far, and discard the rest of the packet. 2288 */ 2289 ifp->if_ierrors++; 2290 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2291 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2292 WM_INIT_RXDESC(sc, i); 2293 if ((status & WRX_ST_EOP) == 0) 2294 sc->sc_rxdiscard = 1; 2295 if (sc->sc_rxhead != NULL) 2296 m_freem(sc->sc_rxhead); 2297 WM_RXCHAIN_RESET(sc); 2298 DPRINTF(WM_DEBUG_RX, 2299 ("%s: RX: Rx buffer allocation failed, " 2300 "dropping packet%s\n", sc->sc_dev.dv_xname, 2301 sc->sc_rxdiscard ? " (discard)" : "")); 2302 continue; 2303 } 2304 2305 WM_RXCHAIN_LINK(sc, m); 2306 2307 m->m_len = len; 2308 2309 DPRINTF(WM_DEBUG_RX, 2310 ("%s: RX: buffer at %p len %d\n", 2311 sc->sc_dev.dv_xname, m->m_data, len)); 2312 2313 /* 2314 * If this is not the end of the packet, keep 2315 * looking. 2316 */ 2317 if ((status & WRX_ST_EOP) == 0) { 2318 sc->sc_rxlen += len; 2319 DPRINTF(WM_DEBUG_RX, 2320 ("%s: RX: not yet EOP, rxlen -> %d\n", 2321 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2322 continue; 2323 } 2324 2325 /* 2326 * Okay, we have the entire packet now. The chip is 2327 * configured to include the FCS (not all chips can 2328 * be configured to strip it), so we need to trim it. 2329 */ 2330 m->m_len -= ETHER_CRC_LEN; 2331 2332 *sc->sc_rxtailp = NULL; 2333 len = m->m_len + sc->sc_rxlen; 2334 m = sc->sc_rxhead; 2335 2336 WM_RXCHAIN_RESET(sc); 2337 2338 DPRINTF(WM_DEBUG_RX, 2339 ("%s: RX: have entire packet, len -> %d\n", 2340 sc->sc_dev.dv_xname, len)); 2341 2342 /* 2343 * If an error occurred, update stats and drop the packet. 2344 */ 2345 if (errors & 2346 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2347 ifp->if_ierrors++; 2348 if (errors & WRX_ER_SE) 2349 log(LOG_WARNING, "%s: symbol error\n", 2350 sc->sc_dev.dv_xname); 2351 else if (errors & WRX_ER_SEQ) 2352 log(LOG_WARNING, "%s: receive sequence error\n", 2353 sc->sc_dev.dv_xname); 2354 else if (errors & WRX_ER_CE) 2355 log(LOG_WARNING, "%s: CRC error\n", 2356 sc->sc_dev.dv_xname); 2357 m_freem(m); 2358 continue; 2359 } 2360 2361 /* 2362 * No errors. Receive the packet. 2363 */ 2364 m->m_pkthdr.rcvif = ifp; 2365 m->m_pkthdr.len = len; 2366 2367 #if 0 /* XXXJRT */ 2368 /* 2369 * If VLANs are enabled, VLAN packets have been unwrapped 2370 * for us. Associate the tag with the packet. 2371 */ 2372 if ((status & WRX_ST_VP) != 0) { 2373 VLAN_INPUT_TAG(ifp, m, 2374 le16toh(sc->sc_rxdescs[i].wrx_special, 2375 continue); 2376 } 2377 #endif /* XXXJRT */ 2378 2379 /* 2380 * Set up checksum info for this packet. 2381 */ 2382 if ((status & WRX_ST_IXSM) == 0) { 2383 if (status & WRX_ST_IPCS) { 2384 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2385 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2386 if (errors & WRX_ER_IPE) 2387 m->m_pkthdr.csum_flags |= 2388 M_CSUM_IPv4_BAD; 2389 } 2390 if (status & WRX_ST_TCPCS) { 2391 /* 2392 * Note: we don't know if this was TCP or UDP, 2393 * so we just set both bits, and expect the 2394 * upper layers to deal. 2395 */ 2396 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2397 m->m_pkthdr.csum_flags |= 2398 M_CSUM_TCPv4|M_CSUM_UDPv4; 2399 if (errors & WRX_ER_TCPE) 2400 m->m_pkthdr.csum_flags |= 2401 M_CSUM_TCP_UDP_BAD; 2402 } 2403 } 2404 2405 ifp->if_ipackets++; 2406 2407 #if NBPFILTER > 0 2408 /* Pass this up to any BPF listeners. */ 2409 if (ifp->if_bpf) 2410 bpf_mtap(ifp->if_bpf, m); 2411 #endif /* NBPFILTER > 0 */ 2412 2413 /* Pass it on. */ 2414 (*ifp->if_input)(ifp, m); 2415 } 2416 2417 /* Update the receive pointer. */ 2418 sc->sc_rxptr = i; 2419 2420 DPRINTF(WM_DEBUG_RX, 2421 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2422 } 2423 2424 /* 2425 * wm_linkintr: 2426 * 2427 * Helper; handle link interrupts. 2428 */ 2429 static void 2430 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2431 { 2432 uint32_t status; 2433 2434 /* 2435 * If we get a link status interrupt on a 1000BASE-T 2436 * device, just fall into the normal MII tick path. 2437 */ 2438 if (sc->sc_flags & WM_F_HAS_MII) { 2439 if (icr & ICR_LSC) { 2440 DPRINTF(WM_DEBUG_LINK, 2441 ("%s: LINK: LSC -> mii_tick\n", 2442 sc->sc_dev.dv_xname)); 2443 mii_tick(&sc->sc_mii); 2444 } else if (icr & ICR_RXSEQ) { 2445 DPRINTF(WM_DEBUG_LINK, 2446 ("%s: LINK Receive sequence error\n", 2447 sc->sc_dev.dv_xname)); 2448 } 2449 return; 2450 } 2451 2452 /* 2453 * If we are now receiving /C/, check for link again in 2454 * a couple of link clock ticks. 2455 */ 2456 if (icr & ICR_RXCFG) { 2457 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2458 sc->sc_dev.dv_xname)); 2459 sc->sc_tbi_anstate = 2; 2460 } 2461 2462 if (icr & ICR_LSC) { 2463 status = CSR_READ(sc, WMREG_STATUS); 2464 if (status & STATUS_LU) { 2465 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2466 sc->sc_dev.dv_xname, 2467 (status & STATUS_FD) ? "FDX" : "HDX")); 2468 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2469 sc->sc_fcrtl &= ~FCRTL_XONE; 2470 if (status & STATUS_FD) 2471 sc->sc_tctl |= 2472 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2473 else 2474 sc->sc_tctl |= 2475 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2476 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2477 sc->sc_fcrtl |= FCRTL_XONE; 2478 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2479 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2480 WMREG_OLD_FCRTL : WMREG_FCRTL, 2481 sc->sc_fcrtl); 2482 sc->sc_tbi_linkup = 1; 2483 } else { 2484 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2485 sc->sc_dev.dv_xname)); 2486 sc->sc_tbi_linkup = 0; 2487 } 2488 sc->sc_tbi_anstate = 2; 2489 wm_tbi_set_linkled(sc); 2490 } else if (icr & ICR_RXSEQ) { 2491 DPRINTF(WM_DEBUG_LINK, 2492 ("%s: LINK: Receive sequence error\n", 2493 sc->sc_dev.dv_xname)); 2494 } 2495 } 2496 2497 /* 2498 * wm_tick: 2499 * 2500 * One second timer, used to check link status, sweep up 2501 * completed transmit jobs, etc. 2502 */ 2503 static void 2504 wm_tick(void *arg) 2505 { 2506 struct wm_softc *sc = arg; 2507 int s; 2508 2509 s = splnet(); 2510 2511 if (sc->sc_type >= WM_T_82542_2_1) { 2512 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2513 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2514 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2515 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2516 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2517 } 2518 2519 if (sc->sc_flags & WM_F_HAS_MII) 2520 mii_tick(&sc->sc_mii); 2521 else 2522 wm_tbi_check_link(sc); 2523 2524 splx(s); 2525 2526 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2527 } 2528 2529 /* 2530 * wm_reset: 2531 * 2532 * Reset the i82542 chip. 2533 */ 2534 static void 2535 wm_reset(struct wm_softc *sc) 2536 { 2537 int i; 2538 2539 /* 2540 * Allocate on-chip memory according to the MTU size. 2541 * The Packet Buffer Allocation register must be written 2542 * before the chip is reset. 2543 */ 2544 if (sc->sc_type < WM_T_82547) { 2545 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2546 PBA_40K : PBA_48K; 2547 } else { 2548 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2549 PBA_22K : PBA_30K; 2550 sc->sc_txfifo_head = 0; 2551 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2552 sc->sc_txfifo_size = 2553 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2554 sc->sc_txfifo_stall = 0; 2555 } 2556 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2557 2558 switch (sc->sc_type) { 2559 case WM_T_82544: 2560 case WM_T_82540: 2561 case WM_T_82545: 2562 case WM_T_82546: 2563 case WM_T_82541: 2564 case WM_T_82541_2: 2565 /* 2566 * On some chipsets, a reset through a memory-mapped write 2567 * cycle can cause the chip to reset before completing the 2568 * write cycle. This causes major headache that can be 2569 * avoided by issuing the reset via indirect register writes 2570 * through I/O space. 2571 * 2572 * So, if we successfully mapped the I/O BAR at attach time, 2573 * use that. Otherwise, try our luck with a memory-mapped 2574 * reset. 2575 */ 2576 if (sc->sc_flags & WM_F_IOH_VALID) 2577 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2578 else 2579 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2580 break; 2581 2582 case WM_T_82545_3: 2583 case WM_T_82546_3: 2584 /* Use the shadow control register on these chips. */ 2585 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2586 break; 2587 2588 default: 2589 /* Everything else can safely use the documented method. */ 2590 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2591 break; 2592 } 2593 delay(10000); 2594 2595 for (i = 0; i < 1000; i++) { 2596 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2597 return; 2598 delay(20); 2599 } 2600 2601 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2602 log(LOG_ERR, "%s: reset failed to complete\n", 2603 sc->sc_dev.dv_xname); 2604 } 2605 2606 /* 2607 * wm_init: [ifnet interface function] 2608 * 2609 * Initialize the interface. Must be called at splnet(). 2610 */ 2611 static int 2612 wm_init(struct ifnet *ifp) 2613 { 2614 struct wm_softc *sc = ifp->if_softc; 2615 struct wm_rxsoft *rxs; 2616 int i, error = 0; 2617 uint32_t reg; 2618 2619 /* 2620 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2621 * There is a small but measurable benefit to avoiding the adjusment 2622 * of the descriptor so that the headers are aligned, for normal mtu, 2623 * on such platforms. One possibility is that the DMA itself is 2624 * slightly more efficient if the front of the entire packet (instead 2625 * of the front of the headers) is aligned. 2626 * 2627 * Note we must always set align_tweak to 0 if we are using 2628 * jumbo frames. 2629 */ 2630 #ifdef __NO_STRICT_ALIGNMENT 2631 sc->sc_align_tweak = 0; 2632 #else 2633 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2634 sc->sc_align_tweak = 0; 2635 else 2636 sc->sc_align_tweak = 2; 2637 #endif /* __NO_STRICT_ALIGNMENT */ 2638 2639 /* Cancel any pending I/O. */ 2640 wm_stop(ifp, 0); 2641 2642 /* Reset the chip to a known state. */ 2643 wm_reset(sc); 2644 2645 /* Initialize the transmit descriptor ring. */ 2646 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2647 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2648 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2649 sc->sc_txfree = WM_NTXDESC(sc); 2650 sc->sc_txnext = 0; 2651 2652 if (sc->sc_type < WM_T_82543) { 2653 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2654 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2655 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2656 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2657 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2658 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2659 } else { 2660 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2661 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2662 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2663 CSR_WRITE(sc, WMREG_TDH, 0); 2664 CSR_WRITE(sc, WMREG_TDT, 0); 2665 CSR_WRITE(sc, WMREG_TIDV, 64); 2666 CSR_WRITE(sc, WMREG_TADV, 128); 2667 2668 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2669 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2670 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2671 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2672 } 2673 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2674 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2675 2676 /* Initialize the transmit job descriptors. */ 2677 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2678 sc->sc_txsoft[i].txs_mbuf = NULL; 2679 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2680 sc->sc_txsnext = 0; 2681 sc->sc_txsdirty = 0; 2682 2683 /* 2684 * Initialize the receive descriptor and receive job 2685 * descriptor rings. 2686 */ 2687 if (sc->sc_type < WM_T_82543) { 2688 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2689 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2690 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2691 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2692 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2693 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2694 2695 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2696 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2697 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2698 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2699 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2700 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2701 } else { 2702 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2703 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2704 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2705 CSR_WRITE(sc, WMREG_RDH, 0); 2706 CSR_WRITE(sc, WMREG_RDT, 0); 2707 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2708 CSR_WRITE(sc, WMREG_RADV, 128); 2709 } 2710 for (i = 0; i < WM_NRXDESC; i++) { 2711 rxs = &sc->sc_rxsoft[i]; 2712 if (rxs->rxs_mbuf == NULL) { 2713 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2714 log(LOG_ERR, "%s: unable to allocate or map rx " 2715 "buffer %d, error = %d\n", 2716 sc->sc_dev.dv_xname, i, error); 2717 /* 2718 * XXX Should attempt to run with fewer receive 2719 * XXX buffers instead of just failing. 2720 */ 2721 wm_rxdrain(sc); 2722 goto out; 2723 } 2724 } else 2725 WM_INIT_RXDESC(sc, i); 2726 } 2727 sc->sc_rxptr = 0; 2728 sc->sc_rxdiscard = 0; 2729 WM_RXCHAIN_RESET(sc); 2730 2731 /* 2732 * Clear out the VLAN table -- we don't use it (yet). 2733 */ 2734 CSR_WRITE(sc, WMREG_VET, 0); 2735 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2736 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2737 2738 /* 2739 * Set up flow-control parameters. 2740 * 2741 * XXX Values could probably stand some tuning. 2742 */ 2743 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2744 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2745 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2746 2747 sc->sc_fcrtl = FCRTL_DFLT; 2748 if (sc->sc_type < WM_T_82543) { 2749 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2750 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2751 } else { 2752 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2753 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2754 } 2755 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2756 2757 #if 0 /* XXXJRT */ 2758 /* Deal with VLAN enables. */ 2759 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2760 sc->sc_ctrl |= CTRL_VME; 2761 else 2762 #endif /* XXXJRT */ 2763 sc->sc_ctrl &= ~CTRL_VME; 2764 2765 /* Write the control registers. */ 2766 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2767 #if 0 2768 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2769 #endif 2770 2771 /* 2772 * Set up checksum offload parameters. 2773 */ 2774 reg = CSR_READ(sc, WMREG_RXCSUM); 2775 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2776 reg |= RXCSUM_IPOFL; 2777 else 2778 reg &= ~RXCSUM_IPOFL; 2779 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2780 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2781 else { 2782 reg &= ~RXCSUM_TUOFL; 2783 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2784 reg &= ~RXCSUM_IPOFL; 2785 } 2786 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2787 2788 /* 2789 * Set up the interrupt registers. 2790 */ 2791 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2792 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2793 ICR_RXO | ICR_RXT0; 2794 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2795 sc->sc_icr |= ICR_RXCFG; 2796 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2797 2798 /* Set up the inter-packet gap. */ 2799 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2800 2801 if (sc->sc_type >= WM_T_82543) { 2802 /* Set up the interrupt throttling register (units of 256ns) */ 2803 sc->sc_itr = 1000000000 / (7000 * 256); 2804 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2805 } 2806 2807 #if 0 /* XXXJRT */ 2808 /* Set the VLAN ethernetype. */ 2809 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2810 #endif 2811 2812 /* 2813 * Set up the transmit control register; we start out with 2814 * a collision distance suitable for FDX, but update it whe 2815 * we resolve the media type. 2816 */ 2817 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2818 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2819 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2820 2821 /* Set the media. */ 2822 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2823 2824 /* 2825 * Set up the receive control register; we actually program 2826 * the register when we set the receive filter. Use multicast 2827 * address offset type 0. 2828 * 2829 * Only the i82544 has the ability to strip the incoming 2830 * CRC, so we don't enable that feature. 2831 */ 2832 sc->sc_mchash_type = 0; 2833 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2834 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2835 2836 if(MCLBYTES == 2048) { 2837 sc->sc_rctl |= RCTL_2k; 2838 } else { 2839 if(sc->sc_type >= WM_T_82543) { 2840 switch(MCLBYTES) { 2841 case 4096: 2842 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2843 break; 2844 case 8192: 2845 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2846 break; 2847 case 16384: 2848 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2849 break; 2850 default: 2851 panic("wm_init: MCLBYTES %d unsupported", 2852 MCLBYTES); 2853 break; 2854 } 2855 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2856 } 2857 2858 /* Set the receive filter. */ 2859 wm_set_filter(sc); 2860 2861 /* Start the one second link check clock. */ 2862 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2863 2864 /* ...all done! */ 2865 ifp->if_flags |= IFF_RUNNING; 2866 ifp->if_flags &= ~IFF_OACTIVE; 2867 2868 out: 2869 if (error) 2870 log(LOG_ERR, "%s: interface not running\n", 2871 sc->sc_dev.dv_xname); 2872 return (error); 2873 } 2874 2875 /* 2876 * wm_rxdrain: 2877 * 2878 * Drain the receive queue. 2879 */ 2880 static void 2881 wm_rxdrain(struct wm_softc *sc) 2882 { 2883 struct wm_rxsoft *rxs; 2884 int i; 2885 2886 for (i = 0; i < WM_NRXDESC; i++) { 2887 rxs = &sc->sc_rxsoft[i]; 2888 if (rxs->rxs_mbuf != NULL) { 2889 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2890 m_freem(rxs->rxs_mbuf); 2891 rxs->rxs_mbuf = NULL; 2892 } 2893 } 2894 } 2895 2896 /* 2897 * wm_stop: [ifnet interface function] 2898 * 2899 * Stop transmission on the interface. 2900 */ 2901 static void 2902 wm_stop(struct ifnet *ifp, int disable) 2903 { 2904 struct wm_softc *sc = ifp->if_softc; 2905 struct wm_txsoft *txs; 2906 int i; 2907 2908 /* Stop the one second clock. */ 2909 callout_stop(&sc->sc_tick_ch); 2910 2911 /* Stop the 82547 Tx FIFO stall check timer. */ 2912 if (sc->sc_type == WM_T_82547) 2913 callout_stop(&sc->sc_txfifo_ch); 2914 2915 if (sc->sc_flags & WM_F_HAS_MII) { 2916 /* Down the MII. */ 2917 mii_down(&sc->sc_mii); 2918 } 2919 2920 /* Stop the transmit and receive processes. */ 2921 CSR_WRITE(sc, WMREG_TCTL, 0); 2922 CSR_WRITE(sc, WMREG_RCTL, 0); 2923 2924 /* 2925 * Clear the interrupt mask to ensure the device cannot assert its 2926 * interrupt line. 2927 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 2928 * any currently pending or shared interrupt. 2929 */ 2930 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2931 sc->sc_icr = 0; 2932 2933 /* Release any queued transmit buffers. */ 2934 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2935 txs = &sc->sc_txsoft[i]; 2936 if (txs->txs_mbuf != NULL) { 2937 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2938 m_freem(txs->txs_mbuf); 2939 txs->txs_mbuf = NULL; 2940 } 2941 } 2942 2943 if (disable) 2944 wm_rxdrain(sc); 2945 2946 /* Mark the interface as down and cancel the watchdog timer. */ 2947 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2948 ifp->if_timer = 0; 2949 } 2950 2951 /* 2952 * wm_acquire_eeprom: 2953 * 2954 * Perform the EEPROM handshake required on some chips. 2955 */ 2956 static int 2957 wm_acquire_eeprom(struct wm_softc *sc) 2958 { 2959 uint32_t reg; 2960 int x; 2961 2962 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2963 reg = CSR_READ(sc, WMREG_EECD); 2964 2965 /* Request EEPROM access. */ 2966 reg |= EECD_EE_REQ; 2967 CSR_WRITE(sc, WMREG_EECD, reg); 2968 2969 /* ..and wait for it to be granted. */ 2970 for (x = 0; x < 100; x++) { 2971 reg = CSR_READ(sc, WMREG_EECD); 2972 if (reg & EECD_EE_GNT) 2973 break; 2974 delay(5); 2975 } 2976 if ((reg & EECD_EE_GNT) == 0) { 2977 aprint_error("%s: could not acquire EEPROM GNT\n", 2978 sc->sc_dev.dv_xname); 2979 reg &= ~EECD_EE_REQ; 2980 CSR_WRITE(sc, WMREG_EECD, reg); 2981 return (1); 2982 } 2983 } 2984 2985 return (0); 2986 } 2987 2988 /* 2989 * wm_release_eeprom: 2990 * 2991 * Release the EEPROM mutex. 2992 */ 2993 static void 2994 wm_release_eeprom(struct wm_softc *sc) 2995 { 2996 uint32_t reg; 2997 2998 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2999 reg = CSR_READ(sc, WMREG_EECD); 3000 reg &= ~EECD_EE_REQ; 3001 CSR_WRITE(sc, WMREG_EECD, reg); 3002 } 3003 } 3004 3005 /* 3006 * wm_eeprom_sendbits: 3007 * 3008 * Send a series of bits to the EEPROM. 3009 */ 3010 static void 3011 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 3012 { 3013 uint32_t reg; 3014 int x; 3015 3016 reg = CSR_READ(sc, WMREG_EECD); 3017 3018 for (x = nbits; x > 0; x--) { 3019 if (bits & (1U << (x - 1))) 3020 reg |= EECD_DI; 3021 else 3022 reg &= ~EECD_DI; 3023 CSR_WRITE(sc, WMREG_EECD, reg); 3024 delay(2); 3025 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3026 delay(2); 3027 CSR_WRITE(sc, WMREG_EECD, reg); 3028 delay(2); 3029 } 3030 } 3031 3032 /* 3033 * wm_eeprom_recvbits: 3034 * 3035 * Receive a series of bits from the EEPROM. 3036 */ 3037 static void 3038 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 3039 { 3040 uint32_t reg, val; 3041 int x; 3042 3043 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 3044 3045 val = 0; 3046 for (x = nbits; x > 0; x--) { 3047 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3048 delay(2); 3049 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 3050 val |= (1U << (x - 1)); 3051 CSR_WRITE(sc, WMREG_EECD, reg); 3052 delay(2); 3053 } 3054 *valp = val; 3055 } 3056 3057 /* 3058 * wm_read_eeprom_uwire: 3059 * 3060 * Read a word from the EEPROM using the MicroWire protocol. 3061 */ 3062 static int 3063 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3064 { 3065 uint32_t reg, val; 3066 int i; 3067 3068 for (i = 0; i < wordcnt; i++) { 3069 /* Clear SK and DI. */ 3070 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3071 CSR_WRITE(sc, WMREG_EECD, reg); 3072 3073 /* Set CHIP SELECT. */ 3074 reg |= EECD_CS; 3075 CSR_WRITE(sc, WMREG_EECD, reg); 3076 delay(2); 3077 3078 /* Shift in the READ command. */ 3079 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3080 3081 /* Shift in address. */ 3082 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3083 3084 /* Shift out the data. */ 3085 wm_eeprom_recvbits(sc, &val, 16); 3086 data[i] = val & 0xffff; 3087 3088 /* Clear CHIP SELECT. */ 3089 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3090 CSR_WRITE(sc, WMREG_EECD, reg); 3091 delay(2); 3092 } 3093 3094 return (0); 3095 } 3096 3097 /* 3098 * wm_spi_eeprom_ready: 3099 * 3100 * Wait for a SPI EEPROM to be ready for commands. 3101 */ 3102 static int 3103 wm_spi_eeprom_ready(struct wm_softc *sc) 3104 { 3105 uint32_t val; 3106 int usec; 3107 3108 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3109 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3110 wm_eeprom_recvbits(sc, &val, 8); 3111 if ((val & SPI_SR_RDY) == 0) 3112 break; 3113 } 3114 if (usec >= SPI_MAX_RETRIES) { 3115 aprint_error("%s: EEPROM failed to become ready\n", 3116 sc->sc_dev.dv_xname); 3117 return (1); 3118 } 3119 return (0); 3120 } 3121 3122 /* 3123 * wm_read_eeprom_spi: 3124 * 3125 * Read a work from the EEPROM using the SPI protocol. 3126 */ 3127 static int 3128 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3129 { 3130 uint32_t reg, val; 3131 int i; 3132 uint8_t opc; 3133 3134 /* Clear SK and CS. */ 3135 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3136 CSR_WRITE(sc, WMREG_EECD, reg); 3137 delay(2); 3138 3139 if (wm_spi_eeprom_ready(sc)) 3140 return (1); 3141 3142 /* Toggle CS to flush commands. */ 3143 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3144 delay(2); 3145 CSR_WRITE(sc, WMREG_EECD, reg); 3146 delay(2); 3147 3148 opc = SPI_OPC_READ; 3149 if (sc->sc_ee_addrbits == 8 && word >= 128) 3150 opc |= SPI_OPC_A8; 3151 3152 wm_eeprom_sendbits(sc, opc, 8); 3153 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3154 3155 for (i = 0; i < wordcnt; i++) { 3156 wm_eeprom_recvbits(sc, &val, 16); 3157 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3158 } 3159 3160 /* Raise CS and clear SK. */ 3161 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3162 CSR_WRITE(sc, WMREG_EECD, reg); 3163 delay(2); 3164 3165 return (0); 3166 } 3167 3168 #define EEPROM_CHECKSUM 0xBABA 3169 #define EEPROM_SIZE 0x0040 3170 3171 /* 3172 * wm_validate_eeprom_checksum 3173 * 3174 * The checksum is defined as the sum of the first 64 (16 bit) words. 3175 */ 3176 static int 3177 wm_validate_eeprom_checksum(struct wm_softc *sc) 3178 { 3179 uint16_t checksum; 3180 uint16_t eeprom_data; 3181 int i; 3182 3183 checksum = 0; 3184 3185 for (i = 0; i < EEPROM_SIZE; i++) { 3186 if(wm_read_eeprom(sc, i, 1, &eeprom_data)) 3187 return 1; 3188 checksum += eeprom_data; 3189 } 3190 3191 if (checksum != (uint16_t) EEPROM_CHECKSUM) 3192 return 1; 3193 3194 return 0; 3195 } 3196 3197 /* 3198 * wm_read_eeprom: 3199 * 3200 * Read data from the serial EEPROM. 3201 */ 3202 static int 3203 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3204 { 3205 int rv; 3206 3207 if (sc->sc_flags & WM_F_EEPROM_INVALID) 3208 return 1; 3209 3210 if (wm_acquire_eeprom(sc)) 3211 return 1; 3212 3213 if (sc->sc_flags & WM_F_EEPROM_SPI) 3214 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3215 else 3216 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3217 3218 wm_release_eeprom(sc); 3219 return rv; 3220 } 3221 3222 /* 3223 * wm_add_rxbuf: 3224 * 3225 * Add a receive buffer to the indiciated descriptor. 3226 */ 3227 static int 3228 wm_add_rxbuf(struct wm_softc *sc, int idx) 3229 { 3230 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3231 struct mbuf *m; 3232 int error; 3233 3234 MGETHDR(m, M_DONTWAIT, MT_DATA); 3235 if (m == NULL) 3236 return (ENOBUFS); 3237 3238 MCLGET(m, M_DONTWAIT); 3239 if ((m->m_flags & M_EXT) == 0) { 3240 m_freem(m); 3241 return (ENOBUFS); 3242 } 3243 3244 if (rxs->rxs_mbuf != NULL) 3245 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3246 3247 rxs->rxs_mbuf = m; 3248 3249 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3250 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3251 BUS_DMA_READ|BUS_DMA_NOWAIT); 3252 if (error) { 3253 /* XXX XXX XXX */ 3254 printf("%s: unable to load rx DMA map %d, error = %d\n", 3255 sc->sc_dev.dv_xname, idx, error); 3256 panic("wm_add_rxbuf"); 3257 } 3258 3259 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3260 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3261 3262 WM_INIT_RXDESC(sc, idx); 3263 3264 return (0); 3265 } 3266 3267 /* 3268 * wm_set_ral: 3269 * 3270 * Set an entery in the receive address list. 3271 */ 3272 static void 3273 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3274 { 3275 uint32_t ral_lo, ral_hi; 3276 3277 if (enaddr != NULL) { 3278 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3279 (enaddr[3] << 24); 3280 ral_hi = enaddr[4] | (enaddr[5] << 8); 3281 ral_hi |= RAL_AV; 3282 } else { 3283 ral_lo = 0; 3284 ral_hi = 0; 3285 } 3286 3287 if (sc->sc_type >= WM_T_82544) { 3288 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3289 ral_lo); 3290 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3291 ral_hi); 3292 } else { 3293 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3294 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3295 } 3296 } 3297 3298 /* 3299 * wm_mchash: 3300 * 3301 * Compute the hash of the multicast address for the 4096-bit 3302 * multicast filter. 3303 */ 3304 static uint32_t 3305 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3306 { 3307 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3308 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3309 uint32_t hash; 3310 3311 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3312 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3313 3314 return (hash & 0xfff); 3315 } 3316 3317 /* 3318 * wm_set_filter: 3319 * 3320 * Set up the receive filter. 3321 */ 3322 static void 3323 wm_set_filter(struct wm_softc *sc) 3324 { 3325 struct ethercom *ec = &sc->sc_ethercom; 3326 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3327 struct ether_multi *enm; 3328 struct ether_multistep step; 3329 bus_addr_t mta_reg; 3330 uint32_t hash, reg, bit; 3331 int i; 3332 3333 if (sc->sc_type >= WM_T_82544) 3334 mta_reg = WMREG_CORDOVA_MTA; 3335 else 3336 mta_reg = WMREG_MTA; 3337 3338 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3339 3340 if (ifp->if_flags & IFF_BROADCAST) 3341 sc->sc_rctl |= RCTL_BAM; 3342 if (ifp->if_flags & IFF_PROMISC) { 3343 sc->sc_rctl |= RCTL_UPE; 3344 goto allmulti; 3345 } 3346 3347 /* 3348 * Set the station address in the first RAL slot, and 3349 * clear the remaining slots. 3350 */ 3351 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3352 for (i = 1; i < WM_RAL_TABSIZE; i++) 3353 wm_set_ral(sc, NULL, i); 3354 3355 /* Clear out the multicast table. */ 3356 for (i = 0; i < WM_MC_TABSIZE; i++) 3357 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3358 3359 ETHER_FIRST_MULTI(step, ec, enm); 3360 while (enm != NULL) { 3361 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3362 /* 3363 * We must listen to a range of multicast addresses. 3364 * For now, just accept all multicasts, rather than 3365 * trying to set only those filter bits needed to match 3366 * the range. (At this time, the only use of address 3367 * ranges is for IP multicast routing, for which the 3368 * range is big enough to require all bits set.) 3369 */ 3370 goto allmulti; 3371 } 3372 3373 hash = wm_mchash(sc, enm->enm_addrlo); 3374 3375 reg = (hash >> 5) & 0x7f; 3376 bit = hash & 0x1f; 3377 3378 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3379 hash |= 1U << bit; 3380 3381 /* XXX Hardware bug?? */ 3382 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3383 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3384 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3385 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3386 } else 3387 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3388 3389 ETHER_NEXT_MULTI(step, enm); 3390 } 3391 3392 ifp->if_flags &= ~IFF_ALLMULTI; 3393 goto setit; 3394 3395 allmulti: 3396 ifp->if_flags |= IFF_ALLMULTI; 3397 sc->sc_rctl |= RCTL_MPE; 3398 3399 setit: 3400 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3401 } 3402 3403 /* 3404 * wm_tbi_mediainit: 3405 * 3406 * Initialize media for use on 1000BASE-X devices. 3407 */ 3408 static void 3409 wm_tbi_mediainit(struct wm_softc *sc) 3410 { 3411 const char *sep = ""; 3412 3413 if (sc->sc_type < WM_T_82543) 3414 sc->sc_tipg = TIPG_WM_DFLT; 3415 else 3416 sc->sc_tipg = TIPG_LG_DFLT; 3417 3418 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3419 wm_tbi_mediastatus); 3420 3421 /* 3422 * SWD Pins: 3423 * 3424 * 0 = Link LED (output) 3425 * 1 = Loss Of Signal (input) 3426 */ 3427 sc->sc_ctrl |= CTRL_SWDPIO(0); 3428 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3429 3430 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3431 3432 #define ADD(ss, mm, dd) \ 3433 do { \ 3434 aprint_normal("%s%s", sep, ss); \ 3435 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3436 sep = ", "; \ 3437 } while (/*CONSTCOND*/0) 3438 3439 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3440 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3441 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3442 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3443 aprint_normal("\n"); 3444 3445 #undef ADD 3446 3447 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3448 } 3449 3450 /* 3451 * wm_tbi_mediastatus: [ifmedia interface function] 3452 * 3453 * Get the current interface media status on a 1000BASE-X device. 3454 */ 3455 static void 3456 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3457 { 3458 struct wm_softc *sc = ifp->if_softc; 3459 uint32_t ctrl; 3460 3461 ifmr->ifm_status = IFM_AVALID; 3462 ifmr->ifm_active = IFM_ETHER; 3463 3464 if (sc->sc_tbi_linkup == 0) { 3465 ifmr->ifm_active |= IFM_NONE; 3466 return; 3467 } 3468 3469 ifmr->ifm_status |= IFM_ACTIVE; 3470 ifmr->ifm_active |= IFM_1000_SX; 3471 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3472 ifmr->ifm_active |= IFM_FDX; 3473 ctrl = CSR_READ(sc, WMREG_CTRL); 3474 if (ctrl & CTRL_RFCE) 3475 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3476 if (ctrl & CTRL_TFCE) 3477 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3478 } 3479 3480 /* 3481 * wm_tbi_mediachange: [ifmedia interface function] 3482 * 3483 * Set hardware to newly-selected media on a 1000BASE-X device. 3484 */ 3485 static int 3486 wm_tbi_mediachange(struct ifnet *ifp) 3487 { 3488 struct wm_softc *sc = ifp->if_softc; 3489 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3490 uint32_t status; 3491 int i; 3492 3493 sc->sc_txcw = ife->ifm_data; 3494 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3495 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3496 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3497 sc->sc_txcw |= TXCW_ANE; 3498 3499 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3500 delay(10000); 3501 3502 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3503 3504 sc->sc_tbi_anstate = 0; 3505 3506 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3507 /* Have signal; wait for the link to come up. */ 3508 for (i = 0; i < 50; i++) { 3509 delay(10000); 3510 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3511 break; 3512 } 3513 3514 status = CSR_READ(sc, WMREG_STATUS); 3515 if (status & STATUS_LU) { 3516 /* Link is up. */ 3517 DPRINTF(WM_DEBUG_LINK, 3518 ("%s: LINK: set media -> link up %s\n", 3519 sc->sc_dev.dv_xname, 3520 (status & STATUS_FD) ? "FDX" : "HDX")); 3521 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3522 sc->sc_fcrtl &= ~FCRTL_XONE; 3523 if (status & STATUS_FD) 3524 sc->sc_tctl |= 3525 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3526 else 3527 sc->sc_tctl |= 3528 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3529 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3530 sc->sc_fcrtl |= FCRTL_XONE; 3531 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3532 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3533 WMREG_OLD_FCRTL : WMREG_FCRTL, 3534 sc->sc_fcrtl); 3535 sc->sc_tbi_linkup = 1; 3536 } else { 3537 /* Link is down. */ 3538 DPRINTF(WM_DEBUG_LINK, 3539 ("%s: LINK: set media -> link down\n", 3540 sc->sc_dev.dv_xname)); 3541 sc->sc_tbi_linkup = 0; 3542 } 3543 } else { 3544 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3545 sc->sc_dev.dv_xname)); 3546 sc->sc_tbi_linkup = 0; 3547 } 3548 3549 wm_tbi_set_linkled(sc); 3550 3551 return (0); 3552 } 3553 3554 /* 3555 * wm_tbi_set_linkled: 3556 * 3557 * Update the link LED on 1000BASE-X devices. 3558 */ 3559 static void 3560 wm_tbi_set_linkled(struct wm_softc *sc) 3561 { 3562 3563 if (sc->sc_tbi_linkup) 3564 sc->sc_ctrl |= CTRL_SWDPIN(0); 3565 else 3566 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3567 3568 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3569 } 3570 3571 /* 3572 * wm_tbi_check_link: 3573 * 3574 * Check the link on 1000BASE-X devices. 3575 */ 3576 static void 3577 wm_tbi_check_link(struct wm_softc *sc) 3578 { 3579 uint32_t rxcw, ctrl, status; 3580 3581 if (sc->sc_tbi_anstate == 0) 3582 return; 3583 else if (sc->sc_tbi_anstate > 1) { 3584 DPRINTF(WM_DEBUG_LINK, 3585 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3586 sc->sc_tbi_anstate)); 3587 sc->sc_tbi_anstate--; 3588 return; 3589 } 3590 3591 sc->sc_tbi_anstate = 0; 3592 3593 rxcw = CSR_READ(sc, WMREG_RXCW); 3594 ctrl = CSR_READ(sc, WMREG_CTRL); 3595 status = CSR_READ(sc, WMREG_STATUS); 3596 3597 if ((status & STATUS_LU) == 0) { 3598 DPRINTF(WM_DEBUG_LINK, 3599 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3600 sc->sc_tbi_linkup = 0; 3601 } else { 3602 DPRINTF(WM_DEBUG_LINK, 3603 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3604 (status & STATUS_FD) ? "FDX" : "HDX")); 3605 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3606 sc->sc_fcrtl &= ~FCRTL_XONE; 3607 if (status & STATUS_FD) 3608 sc->sc_tctl |= 3609 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3610 else 3611 sc->sc_tctl |= 3612 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3613 if (ctrl & CTRL_TFCE) 3614 sc->sc_fcrtl |= FCRTL_XONE; 3615 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3616 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3617 WMREG_OLD_FCRTL : WMREG_FCRTL, 3618 sc->sc_fcrtl); 3619 sc->sc_tbi_linkup = 1; 3620 } 3621 3622 wm_tbi_set_linkled(sc); 3623 } 3624 3625 /* 3626 * wm_gmii_reset: 3627 * 3628 * Reset the PHY. 3629 */ 3630 static void 3631 wm_gmii_reset(struct wm_softc *sc) 3632 { 3633 uint32_t reg; 3634 3635 if (sc->sc_type >= WM_T_82544) { 3636 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3637 delay(20000); 3638 3639 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3640 delay(20000); 3641 } else { 3642 /* The PHY reset pin is active-low. */ 3643 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3644 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3645 CTRL_EXT_SWDPIN(4)); 3646 reg |= CTRL_EXT_SWDPIO(4); 3647 3648 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3649 delay(10); 3650 3651 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3652 delay(10); 3653 3654 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3655 delay(10); 3656 #if 0 3657 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3658 #endif 3659 } 3660 } 3661 3662 /* 3663 * wm_gmii_mediainit: 3664 * 3665 * Initialize media for use on 1000BASE-T devices. 3666 */ 3667 static void 3668 wm_gmii_mediainit(struct wm_softc *sc) 3669 { 3670 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3671 3672 /* We have MII. */ 3673 sc->sc_flags |= WM_F_HAS_MII; 3674 3675 sc->sc_tipg = TIPG_1000T_DFLT; 3676 3677 /* 3678 * Let the chip set speed/duplex on its own based on 3679 * signals from the PHY. 3680 */ 3681 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3682 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3683 3684 /* Initialize our media structures and probe the GMII. */ 3685 sc->sc_mii.mii_ifp = ifp; 3686 3687 if (sc->sc_type >= WM_T_82544) { 3688 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3689 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3690 } else { 3691 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3692 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3693 } 3694 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3695 3696 wm_gmii_reset(sc); 3697 3698 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3699 wm_gmii_mediastatus); 3700 3701 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3702 MII_OFFSET_ANY, MIIF_DOPAUSE); 3703 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3704 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3705 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3706 } else 3707 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3708 } 3709 3710 /* 3711 * wm_gmii_mediastatus: [ifmedia interface function] 3712 * 3713 * Get the current interface media status on a 1000BASE-T device. 3714 */ 3715 static void 3716 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3717 { 3718 struct wm_softc *sc = ifp->if_softc; 3719 3720 mii_pollstat(&sc->sc_mii); 3721 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3722 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3723 sc->sc_flowflags; 3724 } 3725 3726 /* 3727 * wm_gmii_mediachange: [ifmedia interface function] 3728 * 3729 * Set hardware to newly-selected media on a 1000BASE-T device. 3730 */ 3731 static int 3732 wm_gmii_mediachange(struct ifnet *ifp) 3733 { 3734 struct wm_softc *sc = ifp->if_softc; 3735 3736 if (ifp->if_flags & IFF_UP) 3737 mii_mediachg(&sc->sc_mii); 3738 return (0); 3739 } 3740 3741 #define MDI_IO CTRL_SWDPIN(2) 3742 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3743 #define MDI_CLK CTRL_SWDPIN(3) 3744 3745 static void 3746 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3747 { 3748 uint32_t i, v; 3749 3750 v = CSR_READ(sc, WMREG_CTRL); 3751 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3752 v |= MDI_DIR | CTRL_SWDPIO(3); 3753 3754 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3755 if (data & i) 3756 v |= MDI_IO; 3757 else 3758 v &= ~MDI_IO; 3759 CSR_WRITE(sc, WMREG_CTRL, v); 3760 delay(10); 3761 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3762 delay(10); 3763 CSR_WRITE(sc, WMREG_CTRL, v); 3764 delay(10); 3765 } 3766 } 3767 3768 static uint32_t 3769 i82543_mii_recvbits(struct wm_softc *sc) 3770 { 3771 uint32_t v, i, data = 0; 3772 3773 v = CSR_READ(sc, WMREG_CTRL); 3774 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3775 v |= CTRL_SWDPIO(3); 3776 3777 CSR_WRITE(sc, WMREG_CTRL, v); 3778 delay(10); 3779 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3780 delay(10); 3781 CSR_WRITE(sc, WMREG_CTRL, v); 3782 delay(10); 3783 3784 for (i = 0; i < 16; i++) { 3785 data <<= 1; 3786 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3787 delay(10); 3788 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3789 data |= 1; 3790 CSR_WRITE(sc, WMREG_CTRL, v); 3791 delay(10); 3792 } 3793 3794 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3795 delay(10); 3796 CSR_WRITE(sc, WMREG_CTRL, v); 3797 delay(10); 3798 3799 return (data); 3800 } 3801 3802 #undef MDI_IO 3803 #undef MDI_DIR 3804 #undef MDI_CLK 3805 3806 /* 3807 * wm_gmii_i82543_readreg: [mii interface function] 3808 * 3809 * Read a PHY register on the GMII (i82543 version). 3810 */ 3811 static int 3812 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3813 { 3814 struct wm_softc *sc = (void *) self; 3815 int rv; 3816 3817 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3818 i82543_mii_sendbits(sc, reg | (phy << 5) | 3819 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3820 rv = i82543_mii_recvbits(sc) & 0xffff; 3821 3822 DPRINTF(WM_DEBUG_GMII, 3823 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3824 sc->sc_dev.dv_xname, phy, reg, rv)); 3825 3826 return (rv); 3827 } 3828 3829 /* 3830 * wm_gmii_i82543_writereg: [mii interface function] 3831 * 3832 * Write a PHY register on the GMII (i82543 version). 3833 */ 3834 static void 3835 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3836 { 3837 struct wm_softc *sc = (void *) self; 3838 3839 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3840 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3841 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3842 (MII_COMMAND_START << 30), 32); 3843 } 3844 3845 /* 3846 * wm_gmii_i82544_readreg: [mii interface function] 3847 * 3848 * Read a PHY register on the GMII. 3849 */ 3850 static int 3851 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3852 { 3853 struct wm_softc *sc = (void *) self; 3854 uint32_t mdic = 0; 3855 int i, rv; 3856 3857 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3858 MDIC_REGADD(reg)); 3859 3860 for (i = 0; i < 100; i++) { 3861 mdic = CSR_READ(sc, WMREG_MDIC); 3862 if (mdic & MDIC_READY) 3863 break; 3864 delay(10); 3865 } 3866 3867 if ((mdic & MDIC_READY) == 0) { 3868 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3869 sc->sc_dev.dv_xname, phy, reg); 3870 rv = 0; 3871 } else if (mdic & MDIC_E) { 3872 #if 0 /* This is normal if no PHY is present. */ 3873 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3874 sc->sc_dev.dv_xname, phy, reg); 3875 #endif 3876 rv = 0; 3877 } else { 3878 rv = MDIC_DATA(mdic); 3879 if (rv == 0xffff) 3880 rv = 0; 3881 } 3882 3883 return (rv); 3884 } 3885 3886 /* 3887 * wm_gmii_i82544_writereg: [mii interface function] 3888 * 3889 * Write a PHY register on the GMII. 3890 */ 3891 static void 3892 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3893 { 3894 struct wm_softc *sc = (void *) self; 3895 uint32_t mdic = 0; 3896 int i; 3897 3898 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3899 MDIC_REGADD(reg) | MDIC_DATA(val)); 3900 3901 for (i = 0; i < 100; i++) { 3902 mdic = CSR_READ(sc, WMREG_MDIC); 3903 if (mdic & MDIC_READY) 3904 break; 3905 delay(10); 3906 } 3907 3908 if ((mdic & MDIC_READY) == 0) 3909 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3910 sc->sc_dev.dv_xname, phy, reg); 3911 else if (mdic & MDIC_E) 3912 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3913 sc->sc_dev.dv_xname, phy, reg); 3914 } 3915 3916 /* 3917 * wm_gmii_statchg: [mii interface function] 3918 * 3919 * Callback from MII layer when media changes. 3920 */ 3921 static void 3922 wm_gmii_statchg(struct device *self) 3923 { 3924 struct wm_softc *sc = (void *) self; 3925 struct mii_data *mii = &sc->sc_mii; 3926 3927 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3928 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3929 sc->sc_fcrtl &= ~FCRTL_XONE; 3930 3931 /* 3932 * Get flow control negotiation result. 3933 */ 3934 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3935 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3936 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3937 mii->mii_media_active &= ~IFM_ETH_FMASK; 3938 } 3939 3940 if (sc->sc_flowflags & IFM_FLOW) { 3941 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3942 sc->sc_ctrl |= CTRL_TFCE; 3943 sc->sc_fcrtl |= FCRTL_XONE; 3944 } 3945 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3946 sc->sc_ctrl |= CTRL_RFCE; 3947 } 3948 3949 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3950 DPRINTF(WM_DEBUG_LINK, 3951 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3952 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3953 } else { 3954 DPRINTF(WM_DEBUG_LINK, 3955 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3956 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3957 } 3958 3959 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3960 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3961 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3962 : WMREG_FCRTL, sc->sc_fcrtl); 3963 } 3964
Indexes created Wed Sep 24 22:09:59 GMT 2025