if_wm.c revision 1.116
1 /* $NetBSD: if_wm.c,v 1.116 2006/06/05 16:06:10 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.116 2006/06/05 16:06:10 msaitoh Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make several things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 WM_T_82571, 217 WM_T_82572, 218 WM_T_82573, 219 } wm_chip_type; 220 221 /* 222 * Software state per device. 223 */ 224 struct wm_softc { 225 struct device sc_dev; /* generic device information */ 226 bus_space_tag_t sc_st; /* bus space tag */ 227 bus_space_handle_t sc_sh; /* bus space handle */ 228 bus_space_tag_t sc_iot; /* I/O space tag */ 229 bus_space_handle_t sc_ioh; /* I/O space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 wm_chip_type sc_type; /* chip type */ 235 int sc_flags; /* flags; see below */ 236 int sc_bus_speed; /* PCI/PCIX bus speed */ 237 int sc_pcix_offset; /* PCIX capability register offset */ 238 int sc_flowflags; /* 802.3x flow control flags */ 239 240 void *sc_ih; /* interrupt cookie */ 241 242 int sc_ee_addrbits; /* EEPROM address bits */ 243 244 struct mii_data sc_mii; /* MII/media information */ 245 246 struct callout sc_tick_ch; /* tick callout */ 247 248 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 249 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 250 251 int sc_align_tweak; 252 253 /* 254 * Software state for the transmit and receive descriptors. 255 */ 256 int sc_txnum; /* must be a power of two */ 257 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 258 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 259 260 /* 261 * Control data structures. 262 */ 263 int sc_ntxdesc; /* must be a power of two */ 264 struct wm_control_data_82544 *sc_control_data; 265 #define sc_txdescs sc_control_data->wcd_txdescs 266 #define sc_rxdescs sc_control_data->wcd_rxdescs 267 268 #ifdef WM_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 272 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 273 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 274 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 275 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 276 struct evcnt sc_ev_linkintr; /* Link interrupts */ 277 278 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 279 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 280 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 281 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 282 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 283 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 284 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 285 286 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 287 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 288 289 struct evcnt sc_ev_tu; /* Tx underrun */ 290 291 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 292 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 293 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 294 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 295 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 296 #endif /* WM_EVENT_COUNTERS */ 297 298 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 299 300 int sc_txfree; /* number of free Tx descriptors */ 301 int sc_txnext; /* next ready Tx descriptor */ 302 303 int sc_txsfree; /* number of free Tx jobs */ 304 int sc_txsnext; /* next free Tx job */ 305 int sc_txsdirty; /* dirty Tx jobs */ 306 307 /* These 5 variables are used only on the 82547. */ 308 int sc_txfifo_size; /* Tx FIFO size */ 309 int sc_txfifo_head; /* current head of FIFO */ 310 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 311 int sc_txfifo_stall; /* Tx FIFO is stalled */ 312 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 313 314 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 315 316 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 317 int sc_rxdiscard; 318 int sc_rxlen; 319 struct mbuf *sc_rxhead; 320 struct mbuf *sc_rxtail; 321 struct mbuf **sc_rxtailp; 322 323 uint32_t sc_ctrl; /* prototype CTRL register */ 324 #if 0 325 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 326 #endif 327 uint32_t sc_icr; /* prototype interrupt bits */ 328 uint32_t sc_itr; /* prototype intr throttling reg */ 329 uint32_t sc_tctl; /* prototype TCTL register */ 330 uint32_t sc_rctl; /* prototype RCTL register */ 331 uint32_t sc_txcw; /* prototype TXCW register */ 332 uint32_t sc_tipg; /* prototype TIPG register */ 333 uint32_t sc_fcrtl; /* prototype FCRTL register */ 334 uint32_t sc_pba; /* prototype PBA register */ 335 336 int sc_tbi_linkup; /* TBI link status */ 337 int sc_tbi_anstate; /* autonegotiation state */ 338 339 int sc_mchash_type; /* multicast filter offset */ 340 341 #if NRND > 0 342 rndsource_element_t rnd_source; /* random source */ 343 #endif 344 }; 345 346 #define WM_RXCHAIN_RESET(sc) \ 347 do { \ 348 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 349 *(sc)->sc_rxtailp = NULL; \ 350 (sc)->sc_rxlen = 0; \ 351 } while (/*CONSTCOND*/0) 352 353 #define WM_RXCHAIN_LINK(sc, m) \ 354 do { \ 355 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 356 (sc)->sc_rxtailp = &(m)->m_next; \ 357 } while (/*CONSTCOND*/0) 358 359 /* sc_flags */ 360 #define WM_F_HAS_MII 0x01 /* has MII */ 361 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 362 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 363 #define WM_F_EEPROM_INVALID 0x08 /* EEPROM not present (bad checksum) */ 364 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 365 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 366 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 367 #define WM_F_CSA 0x80 /* bus is CSA */ 368 #define WM_F_PCIE 0x100 /* bus is PCI-Express */ 369 370 #ifdef WM_EVENT_COUNTERS 371 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 372 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 373 #else 374 #define WM_EVCNT_INCR(ev) /* nothing */ 375 #define WM_EVCNT_ADD(ev, val) /* nothing */ 376 #endif 377 378 #define CSR_READ(sc, reg) \ 379 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 380 #define CSR_WRITE(sc, reg, val) \ 381 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 382 #define CSR_WRITE_FLUSH(sc) \ 383 (void) CSR_READ((sc), WMREG_STATUS) 384 385 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 386 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 387 388 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 389 #define WM_CDTXADDR_HI(sc, x) \ 390 (sizeof(bus_addr_t) == 8 ? \ 391 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 392 393 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 394 #define WM_CDRXADDR_HI(sc, x) \ 395 (sizeof(bus_addr_t) == 8 ? \ 396 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 397 398 #define WM_CDTXSYNC(sc, x, n, ops) \ 399 do { \ 400 int __x, __n; \ 401 \ 402 __x = (x); \ 403 __n = (n); \ 404 \ 405 /* If it will wrap around, sync to the end of the ring. */ \ 406 if ((__x + __n) > WM_NTXDESC(sc)) { \ 407 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 408 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 409 (WM_NTXDESC(sc) - __x), (ops)); \ 410 __n -= (WM_NTXDESC(sc) - __x); \ 411 __x = 0; \ 412 } \ 413 \ 414 /* Now sync whatever is left. */ \ 415 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 416 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 417 } while (/*CONSTCOND*/0) 418 419 #define WM_CDRXSYNC(sc, x, ops) \ 420 do { \ 421 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 422 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 423 } while (/*CONSTCOND*/0) 424 425 #define WM_INIT_RXDESC(sc, x) \ 426 do { \ 427 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 428 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 429 struct mbuf *__m = __rxs->rxs_mbuf; \ 430 \ 431 /* \ 432 * Note: We scoot the packet forward 2 bytes in the buffer \ 433 * so that the payload after the Ethernet header is aligned \ 434 * to a 4-byte boundary. \ 435 * \ 436 * XXX BRAINDAMAGE ALERT! \ 437 * The stupid chip uses the same size for every buffer, which \ 438 * is set in the Receive Control register. We are using the 2K \ 439 * size option, but what we REALLY want is (2K - 2)! For this \ 440 * reason, we can't "scoot" packets longer than the standard \ 441 * Ethernet MTU. On strict-alignment platforms, if the total \ 442 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 443 * the upper layer copy the headers. \ 444 */ \ 445 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 446 \ 447 wm_set_dma_addr(&__rxd->wrx_addr, \ 448 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 449 __rxd->wrx_len = 0; \ 450 __rxd->wrx_cksum = 0; \ 451 __rxd->wrx_status = 0; \ 452 __rxd->wrx_errors = 0; \ 453 __rxd->wrx_special = 0; \ 454 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 455 \ 456 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 457 } while (/*CONSTCOND*/0) 458 459 static void wm_start(struct ifnet *); 460 static void wm_watchdog(struct ifnet *); 461 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 462 static int wm_init(struct ifnet *); 463 static void wm_stop(struct ifnet *, int); 464 465 static void wm_shutdown(void *); 466 467 static void wm_reset(struct wm_softc *); 468 static void wm_rxdrain(struct wm_softc *); 469 static int wm_add_rxbuf(struct wm_softc *, int); 470 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 471 static int wm_validate_eeprom_checksum(struct wm_softc *); 472 static void wm_tick(void *); 473 474 static void wm_set_filter(struct wm_softc *); 475 476 static int wm_intr(void *); 477 static void wm_txintr(struct wm_softc *); 478 static void wm_rxintr(struct wm_softc *); 479 static void wm_linkintr(struct wm_softc *, uint32_t); 480 481 static void wm_tbi_mediainit(struct wm_softc *); 482 static int wm_tbi_mediachange(struct ifnet *); 483 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 484 485 static void wm_tbi_set_linkled(struct wm_softc *); 486 static void wm_tbi_check_link(struct wm_softc *); 487 488 static void wm_gmii_reset(struct wm_softc *); 489 490 static int wm_gmii_i82543_readreg(struct device *, int, int); 491 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 492 493 static int wm_gmii_i82544_readreg(struct device *, int, int); 494 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 495 496 static void wm_gmii_statchg(struct device *); 497 498 static void wm_gmii_mediainit(struct wm_softc *); 499 static int wm_gmii_mediachange(struct ifnet *); 500 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 501 502 static int wm_match(struct device *, struct cfdata *, void *); 503 static void wm_attach(struct device *, struct device *, void *); 504 505 CFATTACH_DECL(wm, sizeof(struct wm_softc), 506 wm_match, wm_attach, NULL, NULL); 507 508 static void wm_82547_txfifo_stall(void *); 509 510 /* 511 * Devices supported by this driver. 512 */ 513 static const struct wm_product { 514 pci_vendor_id_t wmp_vendor; 515 pci_product_id_t wmp_product; 516 const char *wmp_name; 517 wm_chip_type wmp_type; 518 int wmp_flags; 519 #define WMP_F_1000X 0x01 520 #define WMP_F_1000T 0x02 521 } wm_products[] = { 522 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 523 "Intel i82542 1000BASE-X Ethernet", 524 WM_T_82542_2_1, WMP_F_1000X }, 525 526 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 527 "Intel i82543GC 1000BASE-X Ethernet", 528 WM_T_82543, WMP_F_1000X }, 529 530 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 531 "Intel i82543GC 1000BASE-T Ethernet", 532 WM_T_82543, WMP_F_1000T }, 533 534 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 535 "Intel i82544EI 1000BASE-T Ethernet", 536 WM_T_82544, WMP_F_1000T }, 537 538 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 539 "Intel i82544EI 1000BASE-X Ethernet", 540 WM_T_82544, WMP_F_1000X }, 541 542 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 543 "Intel i82544GC 1000BASE-T Ethernet", 544 WM_T_82544, WMP_F_1000T }, 545 546 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 547 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 548 WM_T_82544, WMP_F_1000T }, 549 550 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 551 "Intel i82540EM 1000BASE-T Ethernet", 552 WM_T_82540, WMP_F_1000T }, 553 554 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 555 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 556 WM_T_82540, WMP_F_1000T }, 557 558 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 559 "Intel i82540EP 1000BASE-T Ethernet", 560 WM_T_82540, WMP_F_1000T }, 561 562 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 563 "Intel i82540EP 1000BASE-T Ethernet", 564 WM_T_82540, WMP_F_1000T }, 565 566 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 567 "Intel i82540EP 1000BASE-T Ethernet", 568 WM_T_82540, WMP_F_1000T }, 569 570 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 571 "Intel i82545EM 1000BASE-T Ethernet", 572 WM_T_82545, WMP_F_1000T }, 573 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 575 "Intel i82545GM 1000BASE-T Ethernet", 576 WM_T_82545_3, WMP_F_1000T }, 577 578 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 579 "Intel i82545GM 1000BASE-X Ethernet", 580 WM_T_82545_3, WMP_F_1000X }, 581 #if 0 582 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 583 "Intel i82545GM Gigabit Ethernet (SERDES)", 584 WM_T_82545_3, WMP_F_SERDES }, 585 #endif 586 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 587 "Intel i82546EB 1000BASE-T Ethernet", 588 WM_T_82546, WMP_F_1000T }, 589 590 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 591 "Intel i82546EB 1000BASE-T Ethernet", 592 WM_T_82546, WMP_F_1000T }, 593 594 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 595 "Intel i82545EM 1000BASE-X Ethernet", 596 WM_T_82545, WMP_F_1000X }, 597 598 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 599 "Intel i82546EB 1000BASE-X Ethernet", 600 WM_T_82546, WMP_F_1000X }, 601 602 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 603 "Intel i82546GB 1000BASE-T Ethernet", 604 WM_T_82546_3, WMP_F_1000T }, 605 606 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 607 "Intel i82546GB 1000BASE-X Ethernet", 608 WM_T_82546_3, WMP_F_1000X }, 609 #if 0 610 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 611 "Intel i82546GB Gigabit Ethernet (SERDES)", 612 WM_T_82546_3, WMP_F_SERDES }, 613 #endif 614 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, 615 "Intel PRO/1000MT (82546GB)", 616 WM_T_82546_3, WMP_F_1000T }, 617 618 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 619 "Intel i82541EI 1000BASE-T Ethernet", 620 WM_T_82541, WMP_F_1000T }, 621 622 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, 623 "Intel i82541ER (LOM) 1000BASE-T Ethernet", 624 WM_T_82541, WMP_F_1000T }, 625 626 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 627 "Intel i82541EI Mobile 1000BASE-T Ethernet", 628 WM_T_82541, WMP_F_1000T }, 629 630 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 631 "Intel i82541ER 1000BASE-T Ethernet", 632 WM_T_82541_2, WMP_F_1000T }, 633 634 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 635 "Intel i82541GI 1000BASE-T Ethernet", 636 WM_T_82541_2, WMP_F_1000T }, 637 638 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 639 "Intel i82541GI Mobile 1000BASE-T Ethernet", 640 WM_T_82541_2, WMP_F_1000T }, 641 642 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 643 "Intel i82541PI 1000BASE-T Ethernet", 644 WM_T_82541_2, WMP_F_1000T }, 645 646 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 647 "Intel i82547EI 1000BASE-T Ethernet", 648 WM_T_82547, WMP_F_1000T }, 649 650 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, 651 "Intel i82547EI Moblie 1000BASE-T Ethernet", 652 WM_T_82547, WMP_F_1000T }, 653 654 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 655 "Intel i82547GI 1000BASE-T Ethernet", 656 WM_T_82547_2, WMP_F_1000T }, 657 658 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, 659 "Intel PRO/1000 PT (82571EB)", 660 WM_T_82571, WMP_F_1000T }, 661 662 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, 663 "Intel PRO/1000 PF (82571EB)", 664 WM_T_82571, WMP_F_1000X }, 665 #if 0 666 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, 667 "Intel PRO/1000 PB (82571EB)", 668 WM_T_82571, WMP_F_SERDES }, 669 #endif 670 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, 671 "Intel i82572EI 1000baseT Ethernet", 672 WM_T_82572, WMP_F_1000T }, 673 674 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, 675 "Intel i82572EI 1000baseX Ethernet", 676 WM_T_82572, WMP_F_1000X }, 677 #if 0 678 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, 679 "Intel i82572EI Gigabit Ethernet (SERDES)", 680 WM_T_82572, WMP_F_SERDES }, 681 #endif 682 683 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, 684 "Intel i82572EI 1000baseT Ethernet", 685 WM_T_82572, WMP_F_1000T }, 686 687 #if 0 688 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, 689 "Intel i82573E", 690 WM_T_82573, WMP_F_1000T }, 691 692 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, 693 "Intel i82573E", 694 WM_T_82573, WMP_F_1000T }, 695 696 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, 697 "Intel i82573L Gigabit Ethernet", 698 WM_T_82573, WMP_F_1000T }, 699 #endif 700 701 { 0, 0, 702 NULL, 703 0, 0 }, 704 }; 705 706 #ifdef WM_EVENT_COUNTERS 707 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 708 #endif /* WM_EVENT_COUNTERS */ 709 710 #if 0 /* Not currently used */ 711 static inline uint32_t 712 wm_io_read(struct wm_softc *sc, int reg) 713 { 714 715 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 716 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 717 } 718 #endif 719 720 static inline void 721 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 722 { 723 724 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 725 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 726 } 727 728 static inline void 729 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 730 { 731 wa->wa_low = htole32(v & 0xffffffffU); 732 if (sizeof(bus_addr_t) == 8) 733 wa->wa_high = htole32((uint64_t) v >> 32); 734 else 735 wa->wa_high = 0; 736 } 737 738 static const struct wm_product * 739 wm_lookup(const struct pci_attach_args *pa) 740 { 741 const struct wm_product *wmp; 742 743 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 744 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 745 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 746 return (wmp); 747 } 748 return (NULL); 749 } 750 751 static int 752 wm_match(struct device *parent, struct cfdata *cf, void *aux) 753 { 754 struct pci_attach_args *pa = aux; 755 756 if (wm_lookup(pa) != NULL) 757 return (1); 758 759 return (0); 760 } 761 762 static void 763 wm_attach(struct device *parent, struct device *self, void *aux) 764 { 765 struct wm_softc *sc = (void *) self; 766 struct pci_attach_args *pa = aux; 767 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 768 pci_chipset_tag_t pc = pa->pa_pc; 769 pci_intr_handle_t ih; 770 size_t cdata_size; 771 const char *intrstr = NULL; 772 const char *eetype; 773 bus_space_tag_t memt; 774 bus_space_handle_t memh; 775 bus_dma_segment_t seg; 776 int memh_valid; 777 int i, rseg, error; 778 const struct wm_product *wmp; 779 prop_data_t ea; 780 prop_number_t pn; 781 uint8_t enaddr[ETHER_ADDR_LEN]; 782 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 783 pcireg_t preg, memtype; 784 uint32_t reg; 785 int pmreg; 786 787 callout_init(&sc->sc_tick_ch); 788 789 wmp = wm_lookup(pa); 790 if (wmp == NULL) { 791 printf("\n"); 792 panic("wm_attach: impossible"); 793 } 794 795 if (pci_dma64_available(pa)) 796 sc->sc_dmat = pa->pa_dmat64; 797 else 798 sc->sc_dmat = pa->pa_dmat; 799 800 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 801 aprint_naive(": Ethernet controller\n"); 802 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 803 804 sc->sc_type = wmp->wmp_type; 805 if (sc->sc_type < WM_T_82543) { 806 if (preg < 2) { 807 aprint_error("%s: i82542 must be at least rev. 2\n", 808 sc->sc_dev.dv_xname); 809 return; 810 } 811 if (preg < 3) 812 sc->sc_type = WM_T_82542_2_0; 813 } 814 815 /* 816 * Map the device. All devices support memory-mapped acccess, 817 * and it is really required for normal operation. 818 */ 819 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 820 switch (memtype) { 821 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 822 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 823 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 824 memtype, 0, &memt, &memh, NULL, NULL) == 0); 825 break; 826 default: 827 memh_valid = 0; 828 } 829 830 if (memh_valid) { 831 sc->sc_st = memt; 832 sc->sc_sh = memh; 833 } else { 834 aprint_error("%s: unable to map device registers\n", 835 sc->sc_dev.dv_xname); 836 return; 837 } 838 839 /* 840 * In addition, i82544 and later support I/O mapped indirect 841 * register access. It is not desirable (nor supported in 842 * this driver) to use it for normal operation, though it is 843 * required to work around bugs in some chip versions. 844 */ 845 if (sc->sc_type >= WM_T_82544) { 846 /* First we have to find the I/O BAR. */ 847 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 848 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 849 PCI_MAPREG_TYPE_IO) 850 break; 851 } 852 if (i == PCI_MAPREG_END) 853 aprint_error("%s: WARNING: unable to find I/O BAR\n", 854 sc->sc_dev.dv_xname); 855 else { 856 /* 857 * The i8254x doesn't apparently respond when the 858 * I/O BAR is 0, which looks somewhat like it's not 859 * been configured. 860 */ 861 preg = pci_conf_read(pc, pa->pa_tag, i); 862 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 863 aprint_error("%s: WARNING: I/O BAR at zero.\n", 864 sc->sc_dev.dv_xname); 865 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 866 0, &sc->sc_iot, &sc->sc_ioh, 867 NULL, NULL) == 0) { 868 sc->sc_flags |= WM_F_IOH_VALID; 869 } else { 870 aprint_error("%s: WARNING: unable to map " 871 "I/O space\n", sc->sc_dev.dv_xname); 872 } 873 } 874 875 } 876 877 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 878 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 879 preg |= PCI_COMMAND_MASTER_ENABLE; 880 if (sc->sc_type < WM_T_82542_2_1) 881 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 882 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 883 884 /* Get it out of power save mode, if needed. */ 885 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 886 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 887 PCI_PMCSR_STATE_MASK; 888 if (preg == PCI_PMCSR_STATE_D3) { 889 /* 890 * The card has lost all configuration data in 891 * this state, so punt. 892 */ 893 aprint_error("%s: unable to wake from power state D3\n", 894 sc->sc_dev.dv_xname); 895 return; 896 } 897 if (preg != PCI_PMCSR_STATE_D0) { 898 aprint_normal("%s: waking up from power state D%d\n", 899 sc->sc_dev.dv_xname, preg); 900 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 901 PCI_PMCSR_STATE_D0); 902 } 903 } 904 905 /* 906 * Map and establish our interrupt. 907 */ 908 if (pci_intr_map(pa, &ih)) { 909 aprint_error("%s: unable to map interrupt\n", 910 sc->sc_dev.dv_xname); 911 return; 912 } 913 intrstr = pci_intr_string(pc, ih); 914 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 915 if (sc->sc_ih == NULL) { 916 aprint_error("%s: unable to establish interrupt", 917 sc->sc_dev.dv_xname); 918 if (intrstr != NULL) 919 aprint_normal(" at %s", intrstr); 920 aprint_normal("\n"); 921 return; 922 } 923 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 924 925 /* 926 * Determine a few things about the bus we're connected to. 927 */ 928 if (sc->sc_type < WM_T_82543) { 929 /* We don't really know the bus characteristics here. */ 930 sc->sc_bus_speed = 33; 931 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 932 /* 933 * CSA (Communication Streaming Architecture) is about as fast 934 * a 32-bit 66MHz PCI Bus. 935 */ 936 sc->sc_flags |= WM_F_CSA; 937 sc->sc_bus_speed = 66; 938 aprint_verbose("%s: Communication Streaming Architecture\n", 939 sc->sc_dev.dv_xname); 940 if (sc->sc_type == WM_T_82547) { 941 callout_init(&sc->sc_txfifo_ch); 942 callout_setfunc(&sc->sc_txfifo_ch, 943 wm_82547_txfifo_stall, sc); 944 aprint_verbose("%s: using 82547 Tx FIFO stall " 945 "work-around\n", sc->sc_dev.dv_xname); 946 } 947 } else if (sc->sc_type >= WM_T_82571) { 948 sc->sc_flags |= WM_F_PCIE; 949 aprint_verbose("%s: PCI-Express bus\n", sc->sc_dev.dv_xname); 950 } else { 951 reg = CSR_READ(sc, WMREG_STATUS); 952 if (reg & STATUS_BUS64) 953 sc->sc_flags |= WM_F_BUS64; 954 if (sc->sc_type >= WM_T_82544 && 955 (reg & STATUS_PCIX_MODE) != 0) { 956 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 957 958 sc->sc_flags |= WM_F_PCIX; 959 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 960 PCI_CAP_PCIX, 961 &sc->sc_pcix_offset, NULL) == 0) 962 aprint_error("%s: unable to find PCIX " 963 "capability\n", sc->sc_dev.dv_xname); 964 else if (sc->sc_type != WM_T_82545_3 && 965 sc->sc_type != WM_T_82546_3) { 966 /* 967 * Work around a problem caused by the BIOS 968 * setting the max memory read byte count 969 * incorrectly. 970 */ 971 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 972 sc->sc_pcix_offset + PCI_PCIX_CMD); 973 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 974 sc->sc_pcix_offset + PCI_PCIX_STATUS); 975 976 bytecnt = 977 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 978 PCI_PCIX_CMD_BYTECNT_SHIFT; 979 maxb = 980 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 981 PCI_PCIX_STATUS_MAXB_SHIFT; 982 if (bytecnt > maxb) { 983 aprint_verbose("%s: resetting PCI-X " 984 "MMRBC: %d -> %d\n", 985 sc->sc_dev.dv_xname, 986 512 << bytecnt, 512 << maxb); 987 pcix_cmd = (pcix_cmd & 988 ~PCI_PCIX_CMD_BYTECNT_MASK) | 989 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 990 pci_conf_write(pa->pa_pc, pa->pa_tag, 991 sc->sc_pcix_offset + PCI_PCIX_CMD, 992 pcix_cmd); 993 } 994 } 995 } 996 /* 997 * The quad port adapter is special; it has a PCIX-PCIX 998 * bridge on the board, and can run the secondary bus at 999 * a higher speed. 1000 */ 1001 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 1002 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 1003 : 66; 1004 } else if (sc->sc_flags & WM_F_PCIX) { 1005 switch (reg & STATUS_PCIXSPD_MASK) { 1006 case STATUS_PCIXSPD_50_66: 1007 sc->sc_bus_speed = 66; 1008 break; 1009 case STATUS_PCIXSPD_66_100: 1010 sc->sc_bus_speed = 100; 1011 break; 1012 case STATUS_PCIXSPD_100_133: 1013 sc->sc_bus_speed = 133; 1014 break; 1015 default: 1016 aprint_error( 1017 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 1018 sc->sc_dev.dv_xname, 1019 reg & STATUS_PCIXSPD_MASK); 1020 sc->sc_bus_speed = 66; 1021 } 1022 } else 1023 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 1024 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 1025 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 1026 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 1027 } 1028 1029 /* 1030 * Allocate the control data structures, and create and load the 1031 * DMA map for it. 1032 * 1033 * NOTE: All Tx descriptors must be in the same 4G segment of 1034 * memory. So must Rx descriptors. We simplify by allocating 1035 * both sets within the same 4G segment. 1036 */ 1037 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 1038 WM_NTXDESC_82542 : WM_NTXDESC_82544; 1039 cdata_size = sc->sc_type < WM_T_82544 ? 1040 sizeof(struct wm_control_data_82542) : 1041 sizeof(struct wm_control_data_82544); 1042 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 1043 (bus_size_t) 0x100000000ULL, 1044 &seg, 1, &rseg, 0)) != 0) { 1045 aprint_error( 1046 "%s: unable to allocate control data, error = %d\n", 1047 sc->sc_dev.dv_xname, error); 1048 goto fail_0; 1049 } 1050 1051 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 1052 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 1053 aprint_error("%s: unable to map control data, error = %d\n", 1054 sc->sc_dev.dv_xname, error); 1055 goto fail_1; 1056 } 1057 1058 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 1059 0, 0, &sc->sc_cddmamap)) != 0) { 1060 aprint_error("%s: unable to create control data DMA map, " 1061 "error = %d\n", sc->sc_dev.dv_xname, error); 1062 goto fail_2; 1063 } 1064 1065 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1066 sc->sc_control_data, cdata_size, NULL, 1067 0)) != 0) { 1068 aprint_error( 1069 "%s: unable to load control data DMA map, error = %d\n", 1070 sc->sc_dev.dv_xname, error); 1071 goto fail_3; 1072 } 1073 1074 1075 /* 1076 * Create the transmit buffer DMA maps. 1077 */ 1078 WM_TXQUEUELEN(sc) = 1079 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1080 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1081 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1082 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1083 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1084 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1085 aprint_error("%s: unable to create Tx DMA map %d, " 1086 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1087 goto fail_4; 1088 } 1089 } 1090 1091 /* 1092 * Create the receive buffer DMA maps. 1093 */ 1094 for (i = 0; i < WM_NRXDESC; i++) { 1095 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1096 MCLBYTES, 0, 0, 1097 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1098 aprint_error("%s: unable to create Rx DMA map %d, " 1099 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1100 goto fail_5; 1101 } 1102 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1103 } 1104 1105 /* 1106 * Reset the chip to a known state. 1107 */ 1108 wm_reset(sc); 1109 1110 /* 1111 * Get some information about the EEPROM. 1112 */ 1113 if (sc->sc_type >= WM_T_82540) 1114 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1115 if (sc->sc_type <= WM_T_82544) 1116 sc->sc_ee_addrbits = 6; 1117 else if (sc->sc_type <= WM_T_82546_3) { 1118 reg = CSR_READ(sc, WMREG_EECD); 1119 if (reg & EECD_EE_SIZE) 1120 sc->sc_ee_addrbits = 8; 1121 else 1122 sc->sc_ee_addrbits = 6; 1123 } else if (sc->sc_type <= WM_T_82547_2) { 1124 reg = CSR_READ(sc, WMREG_EECD); 1125 if (reg & EECD_EE_TYPE) { 1126 sc->sc_flags |= WM_F_EEPROM_SPI; 1127 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1128 } else 1129 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1130 } else { 1131 /* Assume everything else is SPI. */ 1132 reg = CSR_READ(sc, WMREG_EECD); 1133 sc->sc_flags |= WM_F_EEPROM_SPI; 1134 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1135 } 1136 1137 /* 1138 * Defer printing the EEPROM type until after verifying the checksum 1139 * This allows the EEPROM type to be printed correctly in the case 1140 * that no EEPROM is attached. 1141 */ 1142 1143 1144 /* 1145 * Validate the EEPROM checksum. If the checksum fails, flag this for 1146 * later, so we can fail future reads from the EEPROM. 1147 */ 1148 if (wm_validate_eeprom_checksum(sc)) 1149 sc->sc_flags |= WM_F_EEPROM_INVALID; 1150 1151 if (sc->sc_flags & WM_F_EEPROM_INVALID) 1152 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname); 1153 else { 1154 if (sc->sc_flags & WM_F_EEPROM_SPI) 1155 eetype = "SPI"; 1156 else 1157 eetype = "MicroWire"; 1158 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1159 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1160 sc->sc_ee_addrbits, eetype); 1161 } 1162 1163 /* 1164 * Read the Ethernet address from the EEPROM, if not first found 1165 * in device properties. 1166 */ 1167 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 1168 if (ea != NULL) { 1169 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 1170 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 1171 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 1172 } else { 1173 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1174 sizeof(myea) / sizeof(myea[0]), myea)) { 1175 aprint_error("%s: unable to read Ethernet address\n", 1176 sc->sc_dev.dv_xname); 1177 return; 1178 } 1179 enaddr[0] = myea[0] & 0xff; 1180 enaddr[1] = myea[0] >> 8; 1181 enaddr[2] = myea[1] & 0xff; 1182 enaddr[3] = myea[1] >> 8; 1183 enaddr[4] = myea[2] & 0xff; 1184 enaddr[5] = myea[2] >> 8; 1185 } 1186 1187 /* 1188 * Toggle the LSB of the MAC address on the second port 1189 * of the i82546. 1190 */ 1191 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1192 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1193 enaddr[5] ^= 1; 1194 } 1195 1196 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1197 ether_sprintf(enaddr)); 1198 1199 /* 1200 * Read the config info from the EEPROM, and set up various 1201 * bits in the control registers based on their contents. 1202 */ 1203 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1204 "i82543-cfg1"); 1205 if (pn != NULL) { 1206 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1207 cfg1 = (uint16_t) prop_number_integer_value(pn); 1208 } else { 1209 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1210 aprint_error("%s: unable to read CFG1\n", 1211 sc->sc_dev.dv_xname); 1212 return; 1213 } 1214 } 1215 1216 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1217 "i82543-cfg2"); 1218 if (pn != NULL) { 1219 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1220 cfg2 = (uint16_t) prop_number_integer_value(pn); 1221 } else { 1222 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1223 aprint_error("%s: unable to read CFG2\n", 1224 sc->sc_dev.dv_xname); 1225 return; 1226 } 1227 } 1228 1229 if (sc->sc_type >= WM_T_82544) { 1230 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1231 "i82543-swdpin"); 1232 if (pn != NULL) { 1233 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1234 swdpin = (uint16_t) prop_number_integer_value(pn); 1235 } else { 1236 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1237 aprint_error("%s: unable to read SWDPIN\n", 1238 sc->sc_dev.dv_xname); 1239 return; 1240 } 1241 } 1242 } 1243 1244 if (cfg1 & EEPROM_CFG1_ILOS) 1245 sc->sc_ctrl |= CTRL_ILOS; 1246 if (sc->sc_type >= WM_T_82544) { 1247 sc->sc_ctrl |= 1248 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1249 CTRL_SWDPIO_SHIFT; 1250 sc->sc_ctrl |= 1251 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1252 CTRL_SWDPINS_SHIFT; 1253 } else { 1254 sc->sc_ctrl |= 1255 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1256 CTRL_SWDPIO_SHIFT; 1257 } 1258 1259 #if 0 1260 if (sc->sc_type >= WM_T_82544) { 1261 if (cfg1 & EEPROM_CFG1_IPS0) 1262 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1263 if (cfg1 & EEPROM_CFG1_IPS1) 1264 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1265 sc->sc_ctrl_ext |= 1266 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1267 CTRL_EXT_SWDPIO_SHIFT; 1268 sc->sc_ctrl_ext |= 1269 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1270 CTRL_EXT_SWDPINS_SHIFT; 1271 } else { 1272 sc->sc_ctrl_ext |= 1273 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1274 CTRL_EXT_SWDPIO_SHIFT; 1275 } 1276 #endif 1277 1278 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1279 #if 0 1280 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1281 #endif 1282 1283 /* 1284 * Set up some register offsets that are different between 1285 * the i82542 and the i82543 and later chips. 1286 */ 1287 if (sc->sc_type < WM_T_82543) { 1288 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1289 sc->sc_tdt_reg = WMREG_OLD_TDT; 1290 } else { 1291 sc->sc_rdt_reg = WMREG_RDT; 1292 sc->sc_tdt_reg = WMREG_TDT; 1293 } 1294 1295 /* 1296 * Determine if we're TBI or GMII mode, and initialize the 1297 * media structures accordingly. 1298 */ 1299 if (sc->sc_type < WM_T_82543 || 1300 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1301 if (wmp->wmp_flags & WMP_F_1000T) 1302 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1303 "product!\n", sc->sc_dev.dv_xname); 1304 wm_tbi_mediainit(sc); 1305 } else { 1306 if (wmp->wmp_flags & WMP_F_1000X) 1307 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1308 "product!\n", sc->sc_dev.dv_xname); 1309 wm_gmii_mediainit(sc); 1310 } 1311 1312 ifp = &sc->sc_ethercom.ec_if; 1313 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1314 ifp->if_softc = sc; 1315 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1316 ifp->if_ioctl = wm_ioctl; 1317 ifp->if_start = wm_start; 1318 ifp->if_watchdog = wm_watchdog; 1319 ifp->if_init = wm_init; 1320 ifp->if_stop = wm_stop; 1321 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1322 IFQ_SET_READY(&ifp->if_snd); 1323 1324 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1325 1326 /* 1327 * If we're a i82543 or greater, we can support VLANs. 1328 */ 1329 if (sc->sc_type >= WM_T_82543) 1330 sc->sc_ethercom.ec_capabilities |= 1331 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1332 1333 /* 1334 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1335 * on i82543 and later. 1336 */ 1337 if (sc->sc_type >= WM_T_82543) 1338 ifp->if_capabilities |= 1339 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1340 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1341 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1342 IFCAP_CSUM_TCPv6_Tx | 1343 IFCAP_CSUM_UDPv6_Tx; 1344 1345 /* 1346 * If we're a i82544 or greater (except i82547), we can do 1347 * TCP segmentation offload. 1348 */ 1349 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1350 ifp->if_capabilities |= IFCAP_TSOv4; 1351 1352 /* 1353 * Attach the interface. 1354 */ 1355 if_attach(ifp); 1356 ether_ifattach(ifp, enaddr); 1357 #if NRND > 0 1358 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1359 RND_TYPE_NET, 0); 1360 #endif 1361 1362 #ifdef WM_EVENT_COUNTERS 1363 /* Attach event counters. */ 1364 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1365 NULL, sc->sc_dev.dv_xname, "txsstall"); 1366 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1367 NULL, sc->sc_dev.dv_xname, "txdstall"); 1368 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1369 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1370 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1371 NULL, sc->sc_dev.dv_xname, "txdw"); 1372 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1373 NULL, sc->sc_dev.dv_xname, "txqe"); 1374 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1375 NULL, sc->sc_dev.dv_xname, "rxintr"); 1376 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1377 NULL, sc->sc_dev.dv_xname, "linkintr"); 1378 1379 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1380 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1381 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1382 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1383 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1384 NULL, sc->sc_dev.dv_xname, "txipsum"); 1385 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1386 NULL, sc->sc_dev.dv_xname, "txtusum"); 1387 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1388 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1389 1390 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1391 NULL, sc->sc_dev.dv_xname, "txtso"); 1392 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1393 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1394 1395 for (i = 0; i < WM_NTXSEGS; i++) { 1396 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1397 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1398 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1399 } 1400 1401 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1402 NULL, sc->sc_dev.dv_xname, "txdrop"); 1403 1404 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1405 NULL, sc->sc_dev.dv_xname, "tu"); 1406 1407 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1408 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1409 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1410 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1411 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1412 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1413 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1414 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1415 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1416 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1417 #endif /* WM_EVENT_COUNTERS */ 1418 1419 /* 1420 * Make sure the interface is shutdown during reboot. 1421 */ 1422 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1423 if (sc->sc_sdhook == NULL) 1424 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1425 sc->sc_dev.dv_xname); 1426 return; 1427 1428 /* 1429 * Free any resources we've allocated during the failed attach 1430 * attempt. Do this in reverse order and fall through. 1431 */ 1432 fail_5: 1433 for (i = 0; i < WM_NRXDESC; i++) { 1434 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1435 bus_dmamap_destroy(sc->sc_dmat, 1436 sc->sc_rxsoft[i].rxs_dmamap); 1437 } 1438 fail_4: 1439 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1440 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1441 bus_dmamap_destroy(sc->sc_dmat, 1442 sc->sc_txsoft[i].txs_dmamap); 1443 } 1444 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1445 fail_3: 1446 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1447 fail_2: 1448 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1449 cdata_size); 1450 fail_1: 1451 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1452 fail_0: 1453 return; 1454 } 1455 1456 /* 1457 * wm_shutdown: 1458 * 1459 * Make sure the interface is stopped at reboot time. 1460 */ 1461 static void 1462 wm_shutdown(void *arg) 1463 { 1464 struct wm_softc *sc = arg; 1465 1466 wm_stop(&sc->sc_ethercom.ec_if, 1); 1467 } 1468 1469 /* 1470 * wm_tx_offload: 1471 * 1472 * Set up TCP/IP checksumming parameters for the 1473 * specified packet. 1474 */ 1475 static int 1476 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1477 uint8_t *fieldsp) 1478 { 1479 struct mbuf *m0 = txs->txs_mbuf; 1480 struct livengood_tcpip_ctxdesc *t; 1481 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1482 struct ether_header *eh; 1483 int offset, iphl; 1484 uint8_t fields; 1485 1486 /* 1487 * XXX It would be nice if the mbuf pkthdr had offset 1488 * fields for the protocol headers. 1489 */ 1490 1491 eh = mtod(m0, struct ether_header *); 1492 switch (htons(eh->ether_type)) { 1493 case ETHERTYPE_IP: 1494 case ETHERTYPE_IPV6: 1495 offset = ETHER_HDR_LEN; 1496 break; 1497 1498 case ETHERTYPE_VLAN: 1499 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1500 break; 1501 1502 default: 1503 /* 1504 * Don't support this protocol or encapsulation. 1505 */ 1506 *fieldsp = 0; 1507 *cmdp = 0; 1508 return (0); 1509 } 1510 1511 if ((m0->m_pkthdr.csum_flags & 1512 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1513 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1514 } else { 1515 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1516 } 1517 1518 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1519 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1520 seg = 0; 1521 fields = 0; 1522 1523 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1524 int hlen = offset + iphl; 1525 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1526 if (__predict_false(m0->m_len < 1527 (hlen + sizeof(struct tcphdr)))) { 1528 /* 1529 * TCP/IP headers are not in the first mbuf; we need 1530 * to do this the slow and painful way. Let's just 1531 * hope this doesn't happen very often. 1532 */ 1533 struct ip ip; 1534 struct tcphdr th; 1535 1536 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1537 1538 m_copydata(m0, offset, sizeof(ip), &ip); 1539 m_copydata(m0, hlen, sizeof(th), &th); 1540 1541 ip.ip_len = 0; 1542 1543 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1544 sizeof(ip.ip_len), &ip.ip_len); 1545 1546 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1547 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1548 1549 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1550 sizeof(th.th_sum), &th.th_sum); 1551 1552 hlen += th.th_off << 2; 1553 } else { 1554 /* 1555 * TCP/IP headers are in the first mbuf; we can do 1556 * this the easy way. 1557 */ 1558 struct ip *ip = 1559 (struct ip *) (mtod(m0, caddr_t) + offset); 1560 struct tcphdr *th = 1561 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1562 1563 ip->ip_len = 0; 1564 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1565 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1566 1567 hlen += th->th_off << 2; 1568 } 1569 1570 cmd |= WTX_TCPIP_CMD_TSE; 1571 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1572 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1573 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1574 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1575 } 1576 1577 /* 1578 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1579 * offload feature, if we load the context descriptor, we 1580 * MUST provide valid values for IPCSS and TUCSS fields. 1581 */ 1582 1583 ipcs = WTX_TCPIP_IPCSS(offset) | 1584 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1585 WTX_TCPIP_IPCSE(offset + iphl - 1); 1586 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1587 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1588 fields |= WTX_IXSM; 1589 } 1590 1591 offset += iphl; 1592 1593 if (m0->m_pkthdr.csum_flags & 1594 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1595 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1596 fields |= WTX_TXSM; 1597 tucs = WTX_TCPIP_TUCSS(offset) | 1598 WTX_TCPIP_TUCSO(offset + 1599 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1600 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1601 } else if ((m0->m_pkthdr.csum_flags & 1602 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) { 1603 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1604 fields |= WTX_TXSM; 1605 tucs = WTX_TCPIP_TUCSS(offset) | 1606 WTX_TCPIP_TUCSO(offset + 1607 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1608 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1609 } else { 1610 /* Just initialize it to a valid TCP context. */ 1611 tucs = WTX_TCPIP_TUCSS(offset) | 1612 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1613 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1614 } 1615 1616 /* Fill in the context descriptor. */ 1617 t = (struct livengood_tcpip_ctxdesc *) 1618 &sc->sc_txdescs[sc->sc_txnext]; 1619 t->tcpip_ipcs = htole32(ipcs); 1620 t->tcpip_tucs = htole32(tucs); 1621 t->tcpip_cmdlen = htole32(cmdlen); 1622 t->tcpip_seg = htole32(seg); 1623 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1624 1625 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1626 txs->txs_ndesc++; 1627 1628 *cmdp = cmd; 1629 *fieldsp = fields; 1630 1631 return (0); 1632 } 1633 1634 static void 1635 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1636 { 1637 struct mbuf *m; 1638 int i; 1639 1640 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1641 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1642 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1643 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1644 m->m_data, m->m_len, m->m_flags); 1645 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1646 i, i == 1 ? "" : "s"); 1647 } 1648 1649 /* 1650 * wm_82547_txfifo_stall: 1651 * 1652 * Callout used to wait for the 82547 Tx FIFO to drain, 1653 * reset the FIFO pointers, and restart packet transmission. 1654 */ 1655 static void 1656 wm_82547_txfifo_stall(void *arg) 1657 { 1658 struct wm_softc *sc = arg; 1659 int s; 1660 1661 s = splnet(); 1662 1663 if (sc->sc_txfifo_stall) { 1664 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1665 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1666 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1667 /* 1668 * Packets have drained. Stop transmitter, reset 1669 * FIFO pointers, restart transmitter, and kick 1670 * the packet queue. 1671 */ 1672 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1673 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1674 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1675 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1676 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1677 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1678 CSR_WRITE(sc, WMREG_TCTL, tctl); 1679 CSR_WRITE_FLUSH(sc); 1680 1681 sc->sc_txfifo_head = 0; 1682 sc->sc_txfifo_stall = 0; 1683 wm_start(&sc->sc_ethercom.ec_if); 1684 } else { 1685 /* 1686 * Still waiting for packets to drain; try again in 1687 * another tick. 1688 */ 1689 callout_schedule(&sc->sc_txfifo_ch, 1); 1690 } 1691 } 1692 1693 splx(s); 1694 } 1695 1696 /* 1697 * wm_82547_txfifo_bugchk: 1698 * 1699 * Check for bug condition in the 82547 Tx FIFO. We need to 1700 * prevent enqueueing a packet that would wrap around the end 1701 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1702 * 1703 * We do this by checking the amount of space before the end 1704 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1705 * the Tx FIFO, wait for all remaining packets to drain, reset 1706 * the internal FIFO pointers to the beginning, and restart 1707 * transmission on the interface. 1708 */ 1709 #define WM_FIFO_HDR 0x10 1710 #define WM_82547_PAD_LEN 0x3e0 1711 static int 1712 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1713 { 1714 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1715 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1716 1717 /* Just return if already stalled. */ 1718 if (sc->sc_txfifo_stall) 1719 return (1); 1720 1721 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1722 /* Stall only occurs in half-duplex mode. */ 1723 goto send_packet; 1724 } 1725 1726 if (len >= WM_82547_PAD_LEN + space) { 1727 sc->sc_txfifo_stall = 1; 1728 callout_schedule(&sc->sc_txfifo_ch, 1); 1729 return (1); 1730 } 1731 1732 send_packet: 1733 sc->sc_txfifo_head += len; 1734 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1735 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1736 1737 return (0); 1738 } 1739 1740 /* 1741 * wm_start: [ifnet interface function] 1742 * 1743 * Start packet transmission on the interface. 1744 */ 1745 static void 1746 wm_start(struct ifnet *ifp) 1747 { 1748 struct wm_softc *sc = ifp->if_softc; 1749 struct mbuf *m0; 1750 #if 0 /* XXXJRT */ 1751 struct m_tag *mtag; 1752 #endif 1753 struct wm_txsoft *txs; 1754 bus_dmamap_t dmamap; 1755 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1756 bus_addr_t curaddr; 1757 bus_size_t seglen, curlen; 1758 uint32_t cksumcmd; 1759 uint8_t cksumfields; 1760 1761 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1762 return; 1763 1764 /* 1765 * Remember the previous number of free descriptors. 1766 */ 1767 ofree = sc->sc_txfree; 1768 1769 /* 1770 * Loop through the send queue, setting up transmit descriptors 1771 * until we drain the queue, or use up all available transmit 1772 * descriptors. 1773 */ 1774 for (;;) { 1775 /* Grab a packet off the queue. */ 1776 IFQ_POLL(&ifp->if_snd, m0); 1777 if (m0 == NULL) 1778 break; 1779 1780 DPRINTF(WM_DEBUG_TX, 1781 ("%s: TX: have packet to transmit: %p\n", 1782 sc->sc_dev.dv_xname, m0)); 1783 1784 /* Get a work queue entry. */ 1785 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1786 wm_txintr(sc); 1787 if (sc->sc_txsfree == 0) { 1788 DPRINTF(WM_DEBUG_TX, 1789 ("%s: TX: no free job descriptors\n", 1790 sc->sc_dev.dv_xname)); 1791 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1792 break; 1793 } 1794 } 1795 1796 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1797 dmamap = txs->txs_dmamap; 1798 1799 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1800 1801 /* 1802 * So says the Linux driver: 1803 * The controller does a simple calculation to make sure 1804 * there is enough room in the FIFO before initiating the 1805 * DMA for each buffer. The calc is: 1806 * 4 = ceil(buffer len / MSS) 1807 * To make sure we don't overrun the FIFO, adjust the max 1808 * buffer len if the MSS drops. 1809 */ 1810 dmamap->dm_maxsegsz = 1811 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1812 ? m0->m_pkthdr.segsz << 2 1813 : WTX_MAX_LEN; 1814 1815 /* 1816 * Load the DMA map. If this fails, the packet either 1817 * didn't fit in the allotted number of segments, or we 1818 * were short on resources. For the too-many-segments 1819 * case, we simply report an error and drop the packet, 1820 * since we can't sanely copy a jumbo packet to a single 1821 * buffer. 1822 */ 1823 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1824 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1825 if (error) { 1826 if (error == EFBIG) { 1827 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1828 log(LOG_ERR, "%s: Tx packet consumes too many " 1829 "DMA segments, dropping...\n", 1830 sc->sc_dev.dv_xname); 1831 IFQ_DEQUEUE(&ifp->if_snd, m0); 1832 wm_dump_mbuf_chain(sc, m0); 1833 m_freem(m0); 1834 continue; 1835 } 1836 /* 1837 * Short on resources, just stop for now. 1838 */ 1839 DPRINTF(WM_DEBUG_TX, 1840 ("%s: TX: dmamap load failed: %d\n", 1841 sc->sc_dev.dv_xname, error)); 1842 break; 1843 } 1844 1845 segs_needed = dmamap->dm_nsegs; 1846 if (use_tso) { 1847 /* For sentinel descriptor; see below. */ 1848 segs_needed++; 1849 } 1850 1851 /* 1852 * Ensure we have enough descriptors free to describe 1853 * the packet. Note, we always reserve one descriptor 1854 * at the end of the ring due to the semantics of the 1855 * TDT register, plus one more in the event we need 1856 * to load offload context. 1857 */ 1858 if (segs_needed > sc->sc_txfree - 2) { 1859 /* 1860 * Not enough free descriptors to transmit this 1861 * packet. We haven't committed anything yet, 1862 * so just unload the DMA map, put the packet 1863 * pack on the queue, and punt. Notify the upper 1864 * layer that there are no more slots left. 1865 */ 1866 DPRINTF(WM_DEBUG_TX, 1867 ("%s: TX: need %d (%d) descriptors, have %d\n", 1868 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1869 sc->sc_txfree - 1)); 1870 ifp->if_flags |= IFF_OACTIVE; 1871 bus_dmamap_unload(sc->sc_dmat, dmamap); 1872 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1873 break; 1874 } 1875 1876 /* 1877 * Check for 82547 Tx FIFO bug. We need to do this 1878 * once we know we can transmit the packet, since we 1879 * do some internal FIFO space accounting here. 1880 */ 1881 if (sc->sc_type == WM_T_82547 && 1882 wm_82547_txfifo_bugchk(sc, m0)) { 1883 DPRINTF(WM_DEBUG_TX, 1884 ("%s: TX: 82547 Tx FIFO bug detected\n", 1885 sc->sc_dev.dv_xname)); 1886 ifp->if_flags |= IFF_OACTIVE; 1887 bus_dmamap_unload(sc->sc_dmat, dmamap); 1888 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1889 break; 1890 } 1891 1892 IFQ_DEQUEUE(&ifp->if_snd, m0); 1893 1894 /* 1895 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1896 */ 1897 1898 DPRINTF(WM_DEBUG_TX, 1899 ("%s: TX: packet has %d (%d) DMA segments\n", 1900 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1901 1902 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1903 1904 /* 1905 * Store a pointer to the packet so that we can free it 1906 * later. 1907 * 1908 * Initially, we consider the number of descriptors the 1909 * packet uses the number of DMA segments. This may be 1910 * incremented by 1 if we do checksum offload (a descriptor 1911 * is used to set the checksum context). 1912 */ 1913 txs->txs_mbuf = m0; 1914 txs->txs_firstdesc = sc->sc_txnext; 1915 txs->txs_ndesc = segs_needed; 1916 1917 /* Set up offload parameters for this packet. */ 1918 if (m0->m_pkthdr.csum_flags & 1919 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 1920 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 1921 if (wm_tx_offload(sc, txs, &cksumcmd, 1922 &cksumfields) != 0) { 1923 /* Error message already displayed. */ 1924 bus_dmamap_unload(sc->sc_dmat, dmamap); 1925 continue; 1926 } 1927 } else { 1928 cksumcmd = 0; 1929 cksumfields = 0; 1930 } 1931 1932 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1933 1934 /* Sync the DMA map. */ 1935 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1936 BUS_DMASYNC_PREWRITE); 1937 1938 /* 1939 * Initialize the transmit descriptor. 1940 */ 1941 for (nexttx = sc->sc_txnext, seg = 0; 1942 seg < dmamap->dm_nsegs; seg++) { 1943 for (seglen = dmamap->dm_segs[seg].ds_len, 1944 curaddr = dmamap->dm_segs[seg].ds_addr; 1945 seglen != 0; 1946 curaddr += curlen, seglen -= curlen, 1947 nexttx = WM_NEXTTX(sc, nexttx)) { 1948 curlen = seglen; 1949 1950 /* 1951 * So says the Linux driver: 1952 * Work around for premature descriptor 1953 * write-backs in TSO mode. Append a 1954 * 4-byte sentinel descriptor. 1955 */ 1956 if (use_tso && 1957 seg == dmamap->dm_nsegs - 1 && 1958 curlen > 8) 1959 curlen -= 4; 1960 1961 wm_set_dma_addr( 1962 &sc->sc_txdescs[nexttx].wtx_addr, 1963 curaddr); 1964 sc->sc_txdescs[nexttx].wtx_cmdlen = 1965 htole32(cksumcmd | curlen); 1966 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1967 0; 1968 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1969 cksumfields; 1970 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1971 lasttx = nexttx; 1972 1973 DPRINTF(WM_DEBUG_TX, 1974 ("%s: TX: desc %d: low 0x%08lx, " 1975 "len 0x%04x\n", 1976 sc->sc_dev.dv_xname, nexttx, 1977 curaddr & 0xffffffffUL, (unsigned)curlen)); 1978 } 1979 } 1980 1981 KASSERT(lasttx != -1); 1982 1983 /* 1984 * Set up the command byte on the last descriptor of 1985 * the packet. If we're in the interrupt delay window, 1986 * delay the interrupt. 1987 */ 1988 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1989 htole32(WTX_CMD_EOP | WTX_CMD_RS); 1990 1991 #if 0 /* XXXJRT */ 1992 /* 1993 * If VLANs are enabled and the packet has a VLAN tag, set 1994 * up the descriptor to encapsulate the packet for us. 1995 * 1996 * This is only valid on the last descriptor of the packet. 1997 */ 1998 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1999 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2000 htole32(WTX_CMD_VLE); 2001 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 2002 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 2003 } 2004 #endif /* XXXJRT */ 2005 2006 txs->txs_lastdesc = lasttx; 2007 2008 DPRINTF(WM_DEBUG_TX, 2009 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 2010 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 2011 2012 /* Sync the descriptors we're using. */ 2013 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 2014 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2015 2016 /* Give the packet to the chip. */ 2017 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 2018 2019 DPRINTF(WM_DEBUG_TX, 2020 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 2021 2022 DPRINTF(WM_DEBUG_TX, 2023 ("%s: TX: finished transmitting packet, job %d\n", 2024 sc->sc_dev.dv_xname, sc->sc_txsnext)); 2025 2026 /* Advance the tx pointer. */ 2027 sc->sc_txfree -= txs->txs_ndesc; 2028 sc->sc_txnext = nexttx; 2029 2030 sc->sc_txsfree--; 2031 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 2032 2033 #if NBPFILTER > 0 2034 /* Pass the packet to any BPF listeners. */ 2035 if (ifp->if_bpf) 2036 bpf_mtap(ifp->if_bpf, m0); 2037 #endif /* NBPFILTER > 0 */ 2038 } 2039 2040 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 2041 /* No more slots; notify upper layer. */ 2042 ifp->if_flags |= IFF_OACTIVE; 2043 } 2044 2045 if (sc->sc_txfree != ofree) { 2046 /* Set a watchdog timer in case the chip flakes out. */ 2047 ifp->if_timer = 5; 2048 } 2049 } 2050 2051 /* 2052 * wm_watchdog: [ifnet interface function] 2053 * 2054 * Watchdog timer handler. 2055 */ 2056 static void 2057 wm_watchdog(struct ifnet *ifp) 2058 { 2059 struct wm_softc *sc = ifp->if_softc; 2060 2061 /* 2062 * Since we're using delayed interrupts, sweep up 2063 * before we report an error. 2064 */ 2065 wm_txintr(sc); 2066 2067 if (sc->sc_txfree != WM_NTXDESC(sc)) { 2068 log(LOG_ERR, 2069 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 2070 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 2071 sc->sc_txnext); 2072 ifp->if_oerrors++; 2073 2074 /* Reset the interface. */ 2075 (void) wm_init(ifp); 2076 } 2077 2078 /* Try to get more packets going. */ 2079 wm_start(ifp); 2080 } 2081 2082 /* 2083 * wm_ioctl: [ifnet interface function] 2084 * 2085 * Handle control requests from the operator. 2086 */ 2087 static int 2088 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2089 { 2090 struct wm_softc *sc = ifp->if_softc; 2091 struct ifreq *ifr = (struct ifreq *) data; 2092 int s, error; 2093 2094 s = splnet(); 2095 2096 switch (cmd) { 2097 case SIOCSIFMEDIA: 2098 case SIOCGIFMEDIA: 2099 /* Flow control requires full-duplex mode. */ 2100 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2101 (ifr->ifr_media & IFM_FDX) == 0) 2102 ifr->ifr_media &= ~IFM_ETH_FMASK; 2103 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2104 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2105 /* We can do both TXPAUSE and RXPAUSE. */ 2106 ifr->ifr_media |= 2107 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2108 } 2109 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2110 } 2111 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2112 break; 2113 default: 2114 error = ether_ioctl(ifp, cmd, data); 2115 if (error == ENETRESET) { 2116 /* 2117 * Multicast list has changed; set the hardware filter 2118 * accordingly. 2119 */ 2120 if (ifp->if_flags & IFF_RUNNING) 2121 wm_set_filter(sc); 2122 error = 0; 2123 } 2124 break; 2125 } 2126 2127 /* Try to get more packets going. */ 2128 wm_start(ifp); 2129 2130 splx(s); 2131 return (error); 2132 } 2133 2134 /* 2135 * wm_intr: 2136 * 2137 * Interrupt service routine. 2138 */ 2139 static int 2140 wm_intr(void *arg) 2141 { 2142 struct wm_softc *sc = arg; 2143 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2144 uint32_t icr; 2145 int handled = 0; 2146 2147 while (1 /* CONSTCOND */) { 2148 icr = CSR_READ(sc, WMREG_ICR); 2149 if ((icr & sc->sc_icr) == 0) 2150 break; 2151 2152 #if 0 /*NRND > 0*/ 2153 if (RND_ENABLED(&sc->rnd_source)) 2154 rnd_add_uint32(&sc->rnd_source, icr); 2155 #endif 2156 2157 handled = 1; 2158 2159 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2160 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2161 DPRINTF(WM_DEBUG_RX, 2162 ("%s: RX: got Rx intr 0x%08x\n", 2163 sc->sc_dev.dv_xname, 2164 icr & (ICR_RXDMT0|ICR_RXT0))); 2165 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2166 } 2167 #endif 2168 wm_rxintr(sc); 2169 2170 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2171 if (icr & ICR_TXDW) { 2172 DPRINTF(WM_DEBUG_TX, 2173 ("%s: TX: got TXDW interrupt\n", 2174 sc->sc_dev.dv_xname)); 2175 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2176 } 2177 #endif 2178 wm_txintr(sc); 2179 2180 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2181 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2182 wm_linkintr(sc, icr); 2183 } 2184 2185 if (icr & ICR_RXO) { 2186 ifp->if_ierrors++; 2187 #if defined(WM_DEBUG) 2188 log(LOG_WARNING, "%s: Receive overrun\n", 2189 sc->sc_dev.dv_xname); 2190 #endif /* defined(WM_DEBUG) */ 2191 } 2192 } 2193 2194 if (handled) { 2195 /* Try to get more packets going. */ 2196 wm_start(ifp); 2197 } 2198 2199 return (handled); 2200 } 2201 2202 /* 2203 * wm_txintr: 2204 * 2205 * Helper; handle transmit interrupts. 2206 */ 2207 static void 2208 wm_txintr(struct wm_softc *sc) 2209 { 2210 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2211 struct wm_txsoft *txs; 2212 uint8_t status; 2213 int i; 2214 2215 ifp->if_flags &= ~IFF_OACTIVE; 2216 2217 /* 2218 * Go through the Tx list and free mbufs for those 2219 * frames which have been transmitted. 2220 */ 2221 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2222 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2223 txs = &sc->sc_txsoft[i]; 2224 2225 DPRINTF(WM_DEBUG_TX, 2226 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2227 2228 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2229 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2230 2231 status = 2232 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2233 if ((status & WTX_ST_DD) == 0) { 2234 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2235 BUS_DMASYNC_PREREAD); 2236 break; 2237 } 2238 2239 DPRINTF(WM_DEBUG_TX, 2240 ("%s: TX: job %d done: descs %d..%d\n", 2241 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2242 txs->txs_lastdesc)); 2243 2244 /* 2245 * XXX We should probably be using the statistics 2246 * XXX registers, but I don't know if they exist 2247 * XXX on chips before the i82544. 2248 */ 2249 2250 #ifdef WM_EVENT_COUNTERS 2251 if (status & WTX_ST_TU) 2252 WM_EVCNT_INCR(&sc->sc_ev_tu); 2253 #endif /* WM_EVENT_COUNTERS */ 2254 2255 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2256 ifp->if_oerrors++; 2257 if (status & WTX_ST_LC) 2258 log(LOG_WARNING, "%s: late collision\n", 2259 sc->sc_dev.dv_xname); 2260 else if (status & WTX_ST_EC) { 2261 ifp->if_collisions += 16; 2262 log(LOG_WARNING, "%s: excessive collisions\n", 2263 sc->sc_dev.dv_xname); 2264 } 2265 } else 2266 ifp->if_opackets++; 2267 2268 sc->sc_txfree += txs->txs_ndesc; 2269 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2270 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2271 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2272 m_freem(txs->txs_mbuf); 2273 txs->txs_mbuf = NULL; 2274 } 2275 2276 /* Update the dirty transmit buffer pointer. */ 2277 sc->sc_txsdirty = i; 2278 DPRINTF(WM_DEBUG_TX, 2279 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2280 2281 /* 2282 * If there are no more pending transmissions, cancel the watchdog 2283 * timer. 2284 */ 2285 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2286 ifp->if_timer = 0; 2287 } 2288 2289 /* 2290 * wm_rxintr: 2291 * 2292 * Helper; handle receive interrupts. 2293 */ 2294 static void 2295 wm_rxintr(struct wm_softc *sc) 2296 { 2297 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2298 struct wm_rxsoft *rxs; 2299 struct mbuf *m; 2300 int i, len; 2301 uint8_t status, errors; 2302 2303 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2304 rxs = &sc->sc_rxsoft[i]; 2305 2306 DPRINTF(WM_DEBUG_RX, 2307 ("%s: RX: checking descriptor %d\n", 2308 sc->sc_dev.dv_xname, i)); 2309 2310 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2311 2312 status = sc->sc_rxdescs[i].wrx_status; 2313 errors = sc->sc_rxdescs[i].wrx_errors; 2314 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2315 2316 if ((status & WRX_ST_DD) == 0) { 2317 /* 2318 * We have processed all of the receive descriptors. 2319 */ 2320 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2321 break; 2322 } 2323 2324 if (__predict_false(sc->sc_rxdiscard)) { 2325 DPRINTF(WM_DEBUG_RX, 2326 ("%s: RX: discarding contents of descriptor %d\n", 2327 sc->sc_dev.dv_xname, i)); 2328 WM_INIT_RXDESC(sc, i); 2329 if (status & WRX_ST_EOP) { 2330 /* Reset our state. */ 2331 DPRINTF(WM_DEBUG_RX, 2332 ("%s: RX: resetting rxdiscard -> 0\n", 2333 sc->sc_dev.dv_xname)); 2334 sc->sc_rxdiscard = 0; 2335 } 2336 continue; 2337 } 2338 2339 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2340 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2341 2342 m = rxs->rxs_mbuf; 2343 2344 /* 2345 * Add a new receive buffer to the ring. 2346 */ 2347 if (wm_add_rxbuf(sc, i) != 0) { 2348 /* 2349 * Failed, throw away what we've done so 2350 * far, and discard the rest of the packet. 2351 */ 2352 ifp->if_ierrors++; 2353 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2354 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2355 WM_INIT_RXDESC(sc, i); 2356 if ((status & WRX_ST_EOP) == 0) 2357 sc->sc_rxdiscard = 1; 2358 if (sc->sc_rxhead != NULL) 2359 m_freem(sc->sc_rxhead); 2360 WM_RXCHAIN_RESET(sc); 2361 DPRINTF(WM_DEBUG_RX, 2362 ("%s: RX: Rx buffer allocation failed, " 2363 "dropping packet%s\n", sc->sc_dev.dv_xname, 2364 sc->sc_rxdiscard ? " (discard)" : "")); 2365 continue; 2366 } 2367 2368 WM_RXCHAIN_LINK(sc, m); 2369 2370 m->m_len = len; 2371 2372 DPRINTF(WM_DEBUG_RX, 2373 ("%s: RX: buffer at %p len %d\n", 2374 sc->sc_dev.dv_xname, m->m_data, len)); 2375 2376 /* 2377 * If this is not the end of the packet, keep 2378 * looking. 2379 */ 2380 if ((status & WRX_ST_EOP) == 0) { 2381 sc->sc_rxlen += len; 2382 DPRINTF(WM_DEBUG_RX, 2383 ("%s: RX: not yet EOP, rxlen -> %d\n", 2384 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2385 continue; 2386 } 2387 2388 /* 2389 * Okay, we have the entire packet now. The chip is 2390 * configured to include the FCS (not all chips can 2391 * be configured to strip it), so we need to trim it. 2392 */ 2393 m->m_len -= ETHER_CRC_LEN; 2394 2395 *sc->sc_rxtailp = NULL; 2396 len = m->m_len + sc->sc_rxlen; 2397 m = sc->sc_rxhead; 2398 2399 WM_RXCHAIN_RESET(sc); 2400 2401 DPRINTF(WM_DEBUG_RX, 2402 ("%s: RX: have entire packet, len -> %d\n", 2403 sc->sc_dev.dv_xname, len)); 2404 2405 /* 2406 * If an error occurred, update stats and drop the packet. 2407 */ 2408 if (errors & 2409 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2410 ifp->if_ierrors++; 2411 if (errors & WRX_ER_SE) 2412 log(LOG_WARNING, "%s: symbol error\n", 2413 sc->sc_dev.dv_xname); 2414 else if (errors & WRX_ER_SEQ) 2415 log(LOG_WARNING, "%s: receive sequence error\n", 2416 sc->sc_dev.dv_xname); 2417 else if (errors & WRX_ER_CE) 2418 log(LOG_WARNING, "%s: CRC error\n", 2419 sc->sc_dev.dv_xname); 2420 m_freem(m); 2421 continue; 2422 } 2423 2424 /* 2425 * No errors. Receive the packet. 2426 */ 2427 m->m_pkthdr.rcvif = ifp; 2428 m->m_pkthdr.len = len; 2429 2430 #if 0 /* XXXJRT */ 2431 /* 2432 * If VLANs are enabled, VLAN packets have been unwrapped 2433 * for us. Associate the tag with the packet. 2434 */ 2435 if ((status & WRX_ST_VP) != 0) { 2436 VLAN_INPUT_TAG(ifp, m, 2437 le16toh(sc->sc_rxdescs[i].wrx_special, 2438 continue); 2439 } 2440 #endif /* XXXJRT */ 2441 2442 /* 2443 * Set up checksum info for this packet. 2444 */ 2445 if ((status & WRX_ST_IXSM) == 0) { 2446 if (status & WRX_ST_IPCS) { 2447 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2448 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2449 if (errors & WRX_ER_IPE) 2450 m->m_pkthdr.csum_flags |= 2451 M_CSUM_IPv4_BAD; 2452 } 2453 if (status & WRX_ST_TCPCS) { 2454 /* 2455 * Note: we don't know if this was TCP or UDP, 2456 * so we just set both bits, and expect the 2457 * upper layers to deal. 2458 */ 2459 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2460 m->m_pkthdr.csum_flags |= 2461 M_CSUM_TCPv4|M_CSUM_UDPv4; 2462 if (errors & WRX_ER_TCPE) 2463 m->m_pkthdr.csum_flags |= 2464 M_CSUM_TCP_UDP_BAD; 2465 } 2466 } 2467 2468 ifp->if_ipackets++; 2469 2470 #if NBPFILTER > 0 2471 /* Pass this up to any BPF listeners. */ 2472 if (ifp->if_bpf) 2473 bpf_mtap(ifp->if_bpf, m); 2474 #endif /* NBPFILTER > 0 */ 2475 2476 /* Pass it on. */ 2477 (*ifp->if_input)(ifp, m); 2478 } 2479 2480 /* Update the receive pointer. */ 2481 sc->sc_rxptr = i; 2482 2483 DPRINTF(WM_DEBUG_RX, 2484 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2485 } 2486 2487 /* 2488 * wm_linkintr: 2489 * 2490 * Helper; handle link interrupts. 2491 */ 2492 static void 2493 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2494 { 2495 uint32_t status; 2496 2497 /* 2498 * If we get a link status interrupt on a 1000BASE-T 2499 * device, just fall into the normal MII tick path. 2500 */ 2501 if (sc->sc_flags & WM_F_HAS_MII) { 2502 if (icr & ICR_LSC) { 2503 DPRINTF(WM_DEBUG_LINK, 2504 ("%s: LINK: LSC -> mii_tick\n", 2505 sc->sc_dev.dv_xname)); 2506 mii_tick(&sc->sc_mii); 2507 } else if (icr & ICR_RXSEQ) { 2508 DPRINTF(WM_DEBUG_LINK, 2509 ("%s: LINK Receive sequence error\n", 2510 sc->sc_dev.dv_xname)); 2511 } 2512 return; 2513 } 2514 2515 /* 2516 * If we are now receiving /C/, check for link again in 2517 * a couple of link clock ticks. 2518 */ 2519 if (icr & ICR_RXCFG) { 2520 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2521 sc->sc_dev.dv_xname)); 2522 sc->sc_tbi_anstate = 2; 2523 } 2524 2525 if (icr & ICR_LSC) { 2526 status = CSR_READ(sc, WMREG_STATUS); 2527 if (status & STATUS_LU) { 2528 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2529 sc->sc_dev.dv_xname, 2530 (status & STATUS_FD) ? "FDX" : "HDX")); 2531 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2532 sc->sc_fcrtl &= ~FCRTL_XONE; 2533 if (status & STATUS_FD) 2534 sc->sc_tctl |= 2535 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2536 else 2537 sc->sc_tctl |= 2538 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2539 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2540 sc->sc_fcrtl |= FCRTL_XONE; 2541 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2542 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2543 WMREG_OLD_FCRTL : WMREG_FCRTL, 2544 sc->sc_fcrtl); 2545 sc->sc_tbi_linkup = 1; 2546 } else { 2547 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2548 sc->sc_dev.dv_xname)); 2549 sc->sc_tbi_linkup = 0; 2550 } 2551 sc->sc_tbi_anstate = 2; 2552 wm_tbi_set_linkled(sc); 2553 } else if (icr & ICR_RXSEQ) { 2554 DPRINTF(WM_DEBUG_LINK, 2555 ("%s: LINK: Receive sequence error\n", 2556 sc->sc_dev.dv_xname)); 2557 } 2558 } 2559 2560 /* 2561 * wm_tick: 2562 * 2563 * One second timer, used to check link status, sweep up 2564 * completed transmit jobs, etc. 2565 */ 2566 static void 2567 wm_tick(void *arg) 2568 { 2569 struct wm_softc *sc = arg; 2570 int s; 2571 2572 s = splnet(); 2573 2574 if (sc->sc_type >= WM_T_82542_2_1) { 2575 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2576 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2577 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2578 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2579 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2580 } 2581 2582 if (sc->sc_flags & WM_F_HAS_MII) 2583 mii_tick(&sc->sc_mii); 2584 else 2585 wm_tbi_check_link(sc); 2586 2587 splx(s); 2588 2589 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2590 } 2591 2592 /* 2593 * wm_reset: 2594 * 2595 * Reset the i82542 chip. 2596 */ 2597 static void 2598 wm_reset(struct wm_softc *sc) 2599 { 2600 int i; 2601 2602 /* 2603 * Allocate on-chip memory according to the MTU size. 2604 * The Packet Buffer Allocation register must be written 2605 * before the chip is reset. 2606 */ 2607 if (sc->sc_type < WM_T_82547) { 2608 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2609 PBA_40K : PBA_48K; 2610 } else { 2611 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2612 PBA_22K : PBA_30K; 2613 sc->sc_txfifo_head = 0; 2614 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2615 sc->sc_txfifo_size = 2616 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2617 sc->sc_txfifo_stall = 0; 2618 } 2619 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2620 2621 switch (sc->sc_type) { 2622 case WM_T_82544: 2623 case WM_T_82540: 2624 case WM_T_82545: 2625 case WM_T_82546: 2626 case WM_T_82541: 2627 case WM_T_82541_2: 2628 /* 2629 * On some chipsets, a reset through a memory-mapped write 2630 * cycle can cause the chip to reset before completing the 2631 * write cycle. This causes major headache that can be 2632 * avoided by issuing the reset via indirect register writes 2633 * through I/O space. 2634 * 2635 * So, if we successfully mapped the I/O BAR at attach time, 2636 * use that. Otherwise, try our luck with a memory-mapped 2637 * reset. 2638 */ 2639 if (sc->sc_flags & WM_F_IOH_VALID) 2640 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2641 else 2642 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2643 break; 2644 2645 case WM_T_82545_3: 2646 case WM_T_82546_3: 2647 /* Use the shadow control register on these chips. */ 2648 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2649 break; 2650 2651 default: 2652 /* Everything else can safely use the documented method. */ 2653 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2654 break; 2655 } 2656 delay(10000); 2657 2658 for (i = 0; i < 1000; i++) { 2659 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2660 return; 2661 delay(20); 2662 } 2663 2664 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2665 log(LOG_ERR, "%s: reset failed to complete\n", 2666 sc->sc_dev.dv_xname); 2667 } 2668 2669 /* 2670 * wm_init: [ifnet interface function] 2671 * 2672 * Initialize the interface. Must be called at splnet(). 2673 */ 2674 static int 2675 wm_init(struct ifnet *ifp) 2676 { 2677 struct wm_softc *sc = ifp->if_softc; 2678 struct wm_rxsoft *rxs; 2679 int i, error = 0; 2680 uint32_t reg; 2681 2682 /* 2683 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2684 * There is a small but measurable benefit to avoiding the adjusment 2685 * of the descriptor so that the headers are aligned, for normal mtu, 2686 * on such platforms. One possibility is that the DMA itself is 2687 * slightly more efficient if the front of the entire packet (instead 2688 * of the front of the headers) is aligned. 2689 * 2690 * Note we must always set align_tweak to 0 if we are using 2691 * jumbo frames. 2692 */ 2693 #ifdef __NO_STRICT_ALIGNMENT 2694 sc->sc_align_tweak = 0; 2695 #else 2696 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2697 sc->sc_align_tweak = 0; 2698 else 2699 sc->sc_align_tweak = 2; 2700 #endif /* __NO_STRICT_ALIGNMENT */ 2701 2702 /* Cancel any pending I/O. */ 2703 wm_stop(ifp, 0); 2704 2705 /* Reset the chip to a known state. */ 2706 wm_reset(sc); 2707 2708 /* Initialize the transmit descriptor ring. */ 2709 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2710 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2711 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2712 sc->sc_txfree = WM_NTXDESC(sc); 2713 sc->sc_txnext = 0; 2714 2715 if (sc->sc_type < WM_T_82543) { 2716 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2717 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2718 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2719 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2720 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2721 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2722 } else { 2723 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2724 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2725 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2726 CSR_WRITE(sc, WMREG_TDH, 0); 2727 CSR_WRITE(sc, WMREG_TDT, 0); 2728 CSR_WRITE(sc, WMREG_TIDV, 64); 2729 CSR_WRITE(sc, WMREG_TADV, 128); 2730 2731 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2732 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2733 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2734 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2735 } 2736 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2737 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2738 2739 /* Initialize the transmit job descriptors. */ 2740 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2741 sc->sc_txsoft[i].txs_mbuf = NULL; 2742 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2743 sc->sc_txsnext = 0; 2744 sc->sc_txsdirty = 0; 2745 2746 /* 2747 * Initialize the receive descriptor and receive job 2748 * descriptor rings. 2749 */ 2750 if (sc->sc_type < WM_T_82543) { 2751 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2752 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2753 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2754 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2755 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2756 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2757 2758 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2759 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2760 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2761 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2762 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2763 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2764 } else { 2765 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2766 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2767 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2768 CSR_WRITE(sc, WMREG_RDH, 0); 2769 CSR_WRITE(sc, WMREG_RDT, 0); 2770 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2771 CSR_WRITE(sc, WMREG_RADV, 128); 2772 } 2773 for (i = 0; i < WM_NRXDESC; i++) { 2774 rxs = &sc->sc_rxsoft[i]; 2775 if (rxs->rxs_mbuf == NULL) { 2776 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2777 log(LOG_ERR, "%s: unable to allocate or map rx " 2778 "buffer %d, error = %d\n", 2779 sc->sc_dev.dv_xname, i, error); 2780 /* 2781 * XXX Should attempt to run with fewer receive 2782 * XXX buffers instead of just failing. 2783 */ 2784 wm_rxdrain(sc); 2785 goto out; 2786 } 2787 } else 2788 WM_INIT_RXDESC(sc, i); 2789 } 2790 sc->sc_rxptr = 0; 2791 sc->sc_rxdiscard = 0; 2792 WM_RXCHAIN_RESET(sc); 2793 2794 /* 2795 * Clear out the VLAN table -- we don't use it (yet). 2796 */ 2797 CSR_WRITE(sc, WMREG_VET, 0); 2798 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2799 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2800 2801 /* 2802 * Set up flow-control parameters. 2803 * 2804 * XXX Values could probably stand some tuning. 2805 */ 2806 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2807 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2808 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2809 2810 sc->sc_fcrtl = FCRTL_DFLT; 2811 if (sc->sc_type < WM_T_82543) { 2812 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2813 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2814 } else { 2815 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2816 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2817 } 2818 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2819 2820 #if 0 /* XXXJRT */ 2821 /* Deal with VLAN enables. */ 2822 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2823 sc->sc_ctrl |= CTRL_VME; 2824 else 2825 #endif /* XXXJRT */ 2826 sc->sc_ctrl &= ~CTRL_VME; 2827 2828 /* Write the control registers. */ 2829 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2830 #if 0 2831 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2832 #endif 2833 2834 /* 2835 * Set up checksum offload parameters. 2836 */ 2837 reg = CSR_READ(sc, WMREG_RXCSUM); 2838 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2839 reg |= RXCSUM_IPOFL; 2840 else 2841 reg &= ~RXCSUM_IPOFL; 2842 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2843 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2844 else { 2845 reg &= ~RXCSUM_TUOFL; 2846 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2847 reg &= ~RXCSUM_IPOFL; 2848 } 2849 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2850 2851 /* 2852 * Set up the interrupt registers. 2853 */ 2854 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2855 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2856 ICR_RXO | ICR_RXT0; 2857 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2858 sc->sc_icr |= ICR_RXCFG; 2859 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2860 2861 /* Set up the inter-packet gap. */ 2862 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2863 2864 if (sc->sc_type >= WM_T_82543) { 2865 /* Set up the interrupt throttling register (units of 256ns) */ 2866 sc->sc_itr = 1000000000 / (7000 * 256); 2867 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2868 } 2869 2870 #if 0 /* XXXJRT */ 2871 /* Set the VLAN ethernetype. */ 2872 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2873 #endif 2874 2875 /* 2876 * Set up the transmit control register; we start out with 2877 * a collision distance suitable for FDX, but update it whe 2878 * we resolve the media type. 2879 */ 2880 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2881 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2882 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2883 2884 /* Set the media. */ 2885 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2886 2887 /* 2888 * Set up the receive control register; we actually program 2889 * the register when we set the receive filter. Use multicast 2890 * address offset type 0. 2891 * 2892 * Only the i82544 has the ability to strip the incoming 2893 * CRC, so we don't enable that feature. 2894 */ 2895 sc->sc_mchash_type = 0; 2896 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2897 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2898 2899 if(MCLBYTES == 2048) { 2900 sc->sc_rctl |= RCTL_2k; 2901 } else { 2902 if(sc->sc_type >= WM_T_82543) { 2903 switch(MCLBYTES) { 2904 case 4096: 2905 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2906 break; 2907 case 8192: 2908 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2909 break; 2910 case 16384: 2911 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2912 break; 2913 default: 2914 panic("wm_init: MCLBYTES %d unsupported", 2915 MCLBYTES); 2916 break; 2917 } 2918 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2919 } 2920 2921 /* Set the receive filter. */ 2922 wm_set_filter(sc); 2923 2924 /* Start the one second link check clock. */ 2925 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2926 2927 /* ...all done! */ 2928 ifp->if_flags |= IFF_RUNNING; 2929 ifp->if_flags &= ~IFF_OACTIVE; 2930 2931 out: 2932 if (error) 2933 log(LOG_ERR, "%s: interface not running\n", 2934 sc->sc_dev.dv_xname); 2935 return (error); 2936 } 2937 2938 /* 2939 * wm_rxdrain: 2940 * 2941 * Drain the receive queue. 2942 */ 2943 static void 2944 wm_rxdrain(struct wm_softc *sc) 2945 { 2946 struct wm_rxsoft *rxs; 2947 int i; 2948 2949 for (i = 0; i < WM_NRXDESC; i++) { 2950 rxs = &sc->sc_rxsoft[i]; 2951 if (rxs->rxs_mbuf != NULL) { 2952 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2953 m_freem(rxs->rxs_mbuf); 2954 rxs->rxs_mbuf = NULL; 2955 } 2956 } 2957 } 2958 2959 /* 2960 * wm_stop: [ifnet interface function] 2961 * 2962 * Stop transmission on the interface. 2963 */ 2964 static void 2965 wm_stop(struct ifnet *ifp, int disable) 2966 { 2967 struct wm_softc *sc = ifp->if_softc; 2968 struct wm_txsoft *txs; 2969 int i; 2970 2971 /* Stop the one second clock. */ 2972 callout_stop(&sc->sc_tick_ch); 2973 2974 /* Stop the 82547 Tx FIFO stall check timer. */ 2975 if (sc->sc_type == WM_T_82547) 2976 callout_stop(&sc->sc_txfifo_ch); 2977 2978 if (sc->sc_flags & WM_F_HAS_MII) { 2979 /* Down the MII. */ 2980 mii_down(&sc->sc_mii); 2981 } 2982 2983 /* Stop the transmit and receive processes. */ 2984 CSR_WRITE(sc, WMREG_TCTL, 0); 2985 CSR_WRITE(sc, WMREG_RCTL, 0); 2986 2987 /* 2988 * Clear the interrupt mask to ensure the device cannot assert its 2989 * interrupt line. 2990 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 2991 * any currently pending or shared interrupt. 2992 */ 2993 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2994 sc->sc_icr = 0; 2995 2996 /* Release any queued transmit buffers. */ 2997 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2998 txs = &sc->sc_txsoft[i]; 2999 if (txs->txs_mbuf != NULL) { 3000 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3001 m_freem(txs->txs_mbuf); 3002 txs->txs_mbuf = NULL; 3003 } 3004 } 3005 3006 if (disable) 3007 wm_rxdrain(sc); 3008 3009 /* Mark the interface as down and cancel the watchdog timer. */ 3010 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3011 ifp->if_timer = 0; 3012 } 3013 3014 /* 3015 * wm_acquire_eeprom: 3016 * 3017 * Perform the EEPROM handshake required on some chips. 3018 */ 3019 static int 3020 wm_acquire_eeprom(struct wm_softc *sc) 3021 { 3022 uint32_t reg; 3023 int x; 3024 3025 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3026 reg = CSR_READ(sc, WMREG_EECD); 3027 3028 /* Request EEPROM access. */ 3029 reg |= EECD_EE_REQ; 3030 CSR_WRITE(sc, WMREG_EECD, reg); 3031 3032 /* ..and wait for it to be granted. */ 3033 for (x = 0; x < 100; x++) { 3034 reg = CSR_READ(sc, WMREG_EECD); 3035 if (reg & EECD_EE_GNT) 3036 break; 3037 delay(5); 3038 } 3039 if ((reg & EECD_EE_GNT) == 0) { 3040 aprint_error("%s: could not acquire EEPROM GNT\n", 3041 sc->sc_dev.dv_xname); 3042 reg &= ~EECD_EE_REQ; 3043 CSR_WRITE(sc, WMREG_EECD, reg); 3044 return (1); 3045 } 3046 } 3047 3048 return (0); 3049 } 3050 3051 /* 3052 * wm_release_eeprom: 3053 * 3054 * Release the EEPROM mutex. 3055 */ 3056 static void 3057 wm_release_eeprom(struct wm_softc *sc) 3058 { 3059 uint32_t reg; 3060 3061 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3062 reg = CSR_READ(sc, WMREG_EECD); 3063 reg &= ~EECD_EE_REQ; 3064 CSR_WRITE(sc, WMREG_EECD, reg); 3065 } 3066 } 3067 3068 /* 3069 * wm_eeprom_sendbits: 3070 * 3071 * Send a series of bits to the EEPROM. 3072 */ 3073 static void 3074 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 3075 { 3076 uint32_t reg; 3077 int x; 3078 3079 reg = CSR_READ(sc, WMREG_EECD); 3080 3081 for (x = nbits; x > 0; x--) { 3082 if (bits & (1U << (x - 1))) 3083 reg |= EECD_DI; 3084 else 3085 reg &= ~EECD_DI; 3086 CSR_WRITE(sc, WMREG_EECD, reg); 3087 delay(2); 3088 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3089 delay(2); 3090 CSR_WRITE(sc, WMREG_EECD, reg); 3091 delay(2); 3092 } 3093 } 3094 3095 /* 3096 * wm_eeprom_recvbits: 3097 * 3098 * Receive a series of bits from the EEPROM. 3099 */ 3100 static void 3101 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 3102 { 3103 uint32_t reg, val; 3104 int x; 3105 3106 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 3107 3108 val = 0; 3109 for (x = nbits; x > 0; x--) { 3110 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3111 delay(2); 3112 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 3113 val |= (1U << (x - 1)); 3114 CSR_WRITE(sc, WMREG_EECD, reg); 3115 delay(2); 3116 } 3117 *valp = val; 3118 } 3119 3120 /* 3121 * wm_read_eeprom_uwire: 3122 * 3123 * Read a word from the EEPROM using the MicroWire protocol. 3124 */ 3125 static int 3126 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3127 { 3128 uint32_t reg, val; 3129 int i; 3130 3131 for (i = 0; i < wordcnt; i++) { 3132 /* Clear SK and DI. */ 3133 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3134 CSR_WRITE(sc, WMREG_EECD, reg); 3135 3136 /* Set CHIP SELECT. */ 3137 reg |= EECD_CS; 3138 CSR_WRITE(sc, WMREG_EECD, reg); 3139 delay(2); 3140 3141 /* Shift in the READ command. */ 3142 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3143 3144 /* Shift in address. */ 3145 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3146 3147 /* Shift out the data. */ 3148 wm_eeprom_recvbits(sc, &val, 16); 3149 data[i] = val & 0xffff; 3150 3151 /* Clear CHIP SELECT. */ 3152 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3153 CSR_WRITE(sc, WMREG_EECD, reg); 3154 delay(2); 3155 } 3156 3157 return (0); 3158 } 3159 3160 /* 3161 * wm_spi_eeprom_ready: 3162 * 3163 * Wait for a SPI EEPROM to be ready for commands. 3164 */ 3165 static int 3166 wm_spi_eeprom_ready(struct wm_softc *sc) 3167 { 3168 uint32_t val; 3169 int usec; 3170 3171 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3172 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3173 wm_eeprom_recvbits(sc, &val, 8); 3174 if ((val & SPI_SR_RDY) == 0) 3175 break; 3176 } 3177 if (usec >= SPI_MAX_RETRIES) { 3178 aprint_error("%s: EEPROM failed to become ready\n", 3179 sc->sc_dev.dv_xname); 3180 return (1); 3181 } 3182 return (0); 3183 } 3184 3185 /* 3186 * wm_read_eeprom_spi: 3187 * 3188 * Read a work from the EEPROM using the SPI protocol. 3189 */ 3190 static int 3191 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3192 { 3193 uint32_t reg, val; 3194 int i; 3195 uint8_t opc; 3196 3197 /* Clear SK and CS. */ 3198 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3199 CSR_WRITE(sc, WMREG_EECD, reg); 3200 delay(2); 3201 3202 if (wm_spi_eeprom_ready(sc)) 3203 return (1); 3204 3205 /* Toggle CS to flush commands. */ 3206 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3207 delay(2); 3208 CSR_WRITE(sc, WMREG_EECD, reg); 3209 delay(2); 3210 3211 opc = SPI_OPC_READ; 3212 if (sc->sc_ee_addrbits == 8 && word >= 128) 3213 opc |= SPI_OPC_A8; 3214 3215 wm_eeprom_sendbits(sc, opc, 8); 3216 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3217 3218 for (i = 0; i < wordcnt; i++) { 3219 wm_eeprom_recvbits(sc, &val, 16); 3220 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3221 } 3222 3223 /* Raise CS and clear SK. */ 3224 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3225 CSR_WRITE(sc, WMREG_EECD, reg); 3226 delay(2); 3227 3228 return (0); 3229 } 3230 3231 #define EEPROM_CHECKSUM 0xBABA 3232 #define EEPROM_SIZE 0x0040 3233 3234 /* 3235 * wm_validate_eeprom_checksum 3236 * 3237 * The checksum is defined as the sum of the first 64 (16 bit) words. 3238 */ 3239 static int 3240 wm_validate_eeprom_checksum(struct wm_softc *sc) 3241 { 3242 uint16_t checksum; 3243 uint16_t eeprom_data; 3244 int i; 3245 3246 checksum = 0; 3247 3248 for (i = 0; i < EEPROM_SIZE; i++) { 3249 if(wm_read_eeprom(sc, i, 1, &eeprom_data)) 3250 return 1; 3251 checksum += eeprom_data; 3252 } 3253 3254 if (checksum != (uint16_t) EEPROM_CHECKSUM) 3255 return 1; 3256 3257 return 0; 3258 } 3259 3260 /* 3261 * wm_read_eeprom: 3262 * 3263 * Read data from the serial EEPROM. 3264 */ 3265 static int 3266 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3267 { 3268 int rv; 3269 3270 if (sc->sc_flags & WM_F_EEPROM_INVALID) 3271 return 1; 3272 3273 if (wm_acquire_eeprom(sc)) 3274 return 1; 3275 3276 if (sc->sc_flags & WM_F_EEPROM_SPI) 3277 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3278 else 3279 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3280 3281 wm_release_eeprom(sc); 3282 return rv; 3283 } 3284 3285 /* 3286 * wm_add_rxbuf: 3287 * 3288 * Add a receive buffer to the indiciated descriptor. 3289 */ 3290 static int 3291 wm_add_rxbuf(struct wm_softc *sc, int idx) 3292 { 3293 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3294 struct mbuf *m; 3295 int error; 3296 3297 MGETHDR(m, M_DONTWAIT, MT_DATA); 3298 if (m == NULL) 3299 return (ENOBUFS); 3300 3301 MCLGET(m, M_DONTWAIT); 3302 if ((m->m_flags & M_EXT) == 0) { 3303 m_freem(m); 3304 return (ENOBUFS); 3305 } 3306 3307 if (rxs->rxs_mbuf != NULL) 3308 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3309 3310 rxs->rxs_mbuf = m; 3311 3312 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3313 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3314 BUS_DMA_READ|BUS_DMA_NOWAIT); 3315 if (error) { 3316 /* XXX XXX XXX */ 3317 printf("%s: unable to load rx DMA map %d, error = %d\n", 3318 sc->sc_dev.dv_xname, idx, error); 3319 panic("wm_add_rxbuf"); 3320 } 3321 3322 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3323 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3324 3325 WM_INIT_RXDESC(sc, idx); 3326 3327 return (0); 3328 } 3329 3330 /* 3331 * wm_set_ral: 3332 * 3333 * Set an entery in the receive address list. 3334 */ 3335 static void 3336 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3337 { 3338 uint32_t ral_lo, ral_hi; 3339 3340 if (enaddr != NULL) { 3341 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3342 (enaddr[3] << 24); 3343 ral_hi = enaddr[4] | (enaddr[5] << 8); 3344 ral_hi |= RAL_AV; 3345 } else { 3346 ral_lo = 0; 3347 ral_hi = 0; 3348 } 3349 3350 if (sc->sc_type >= WM_T_82544) { 3351 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3352 ral_lo); 3353 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3354 ral_hi); 3355 } else { 3356 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3357 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3358 } 3359 } 3360 3361 /* 3362 * wm_mchash: 3363 * 3364 * Compute the hash of the multicast address for the 4096-bit 3365 * multicast filter. 3366 */ 3367 static uint32_t 3368 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3369 { 3370 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3371 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3372 uint32_t hash; 3373 3374 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3375 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3376 3377 return (hash & 0xfff); 3378 } 3379 3380 /* 3381 * wm_set_filter: 3382 * 3383 * Set up the receive filter. 3384 */ 3385 static void 3386 wm_set_filter(struct wm_softc *sc) 3387 { 3388 struct ethercom *ec = &sc->sc_ethercom; 3389 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3390 struct ether_multi *enm; 3391 struct ether_multistep step; 3392 bus_addr_t mta_reg; 3393 uint32_t hash, reg, bit; 3394 int i; 3395 3396 if (sc->sc_type >= WM_T_82544) 3397 mta_reg = WMREG_CORDOVA_MTA; 3398 else 3399 mta_reg = WMREG_MTA; 3400 3401 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3402 3403 if (ifp->if_flags & IFF_BROADCAST) 3404 sc->sc_rctl |= RCTL_BAM; 3405 if (ifp->if_flags & IFF_PROMISC) { 3406 sc->sc_rctl |= RCTL_UPE; 3407 goto allmulti; 3408 } 3409 3410 /* 3411 * Set the station address in the first RAL slot, and 3412 * clear the remaining slots. 3413 */ 3414 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3415 for (i = 1; i < WM_RAL_TABSIZE; i++) 3416 wm_set_ral(sc, NULL, i); 3417 3418 /* Clear out the multicast table. */ 3419 for (i = 0; i < WM_MC_TABSIZE; i++) 3420 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3421 3422 ETHER_FIRST_MULTI(step, ec, enm); 3423 while (enm != NULL) { 3424 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3425 /* 3426 * We must listen to a range of multicast addresses. 3427 * For now, just accept all multicasts, rather than 3428 * trying to set only those filter bits needed to match 3429 * the range. (At this time, the only use of address 3430 * ranges is for IP multicast routing, for which the 3431 * range is big enough to require all bits set.) 3432 */ 3433 goto allmulti; 3434 } 3435 3436 hash = wm_mchash(sc, enm->enm_addrlo); 3437 3438 reg = (hash >> 5) & 0x7f; 3439 bit = hash & 0x1f; 3440 3441 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3442 hash |= 1U << bit; 3443 3444 /* XXX Hardware bug?? */ 3445 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3446 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3447 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3448 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3449 } else 3450 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3451 3452 ETHER_NEXT_MULTI(step, enm); 3453 } 3454 3455 ifp->if_flags &= ~IFF_ALLMULTI; 3456 goto setit; 3457 3458 allmulti: 3459 ifp->if_flags |= IFF_ALLMULTI; 3460 sc->sc_rctl |= RCTL_MPE; 3461 3462 setit: 3463 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3464 } 3465 3466 /* 3467 * wm_tbi_mediainit: 3468 * 3469 * Initialize media for use on 1000BASE-X devices. 3470 */ 3471 static void 3472 wm_tbi_mediainit(struct wm_softc *sc) 3473 { 3474 const char *sep = ""; 3475 3476 if (sc->sc_type < WM_T_82543) 3477 sc->sc_tipg = TIPG_WM_DFLT; 3478 else 3479 sc->sc_tipg = TIPG_LG_DFLT; 3480 3481 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3482 wm_tbi_mediastatus); 3483 3484 /* 3485 * SWD Pins: 3486 * 3487 * 0 = Link LED (output) 3488 * 1 = Loss Of Signal (input) 3489 */ 3490 sc->sc_ctrl |= CTRL_SWDPIO(0); 3491 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3492 3493 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3494 3495 #define ADD(ss, mm, dd) \ 3496 do { \ 3497 aprint_normal("%s%s", sep, ss); \ 3498 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3499 sep = ", "; \ 3500 } while (/*CONSTCOND*/0) 3501 3502 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3503 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3504 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3505 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3506 aprint_normal("\n"); 3507 3508 #undef ADD 3509 3510 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3511 } 3512 3513 /* 3514 * wm_tbi_mediastatus: [ifmedia interface function] 3515 * 3516 * Get the current interface media status on a 1000BASE-X device. 3517 */ 3518 static void 3519 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3520 { 3521 struct wm_softc *sc = ifp->if_softc; 3522 uint32_t ctrl; 3523 3524 ifmr->ifm_status = IFM_AVALID; 3525 ifmr->ifm_active = IFM_ETHER; 3526 3527 if (sc->sc_tbi_linkup == 0) { 3528 ifmr->ifm_active |= IFM_NONE; 3529 return; 3530 } 3531 3532 ifmr->ifm_status |= IFM_ACTIVE; 3533 ifmr->ifm_active |= IFM_1000_SX; 3534 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3535 ifmr->ifm_active |= IFM_FDX; 3536 ctrl = CSR_READ(sc, WMREG_CTRL); 3537 if (ctrl & CTRL_RFCE) 3538 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3539 if (ctrl & CTRL_TFCE) 3540 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3541 } 3542 3543 /* 3544 * wm_tbi_mediachange: [ifmedia interface function] 3545 * 3546 * Set hardware to newly-selected media on a 1000BASE-X device. 3547 */ 3548 static int 3549 wm_tbi_mediachange(struct ifnet *ifp) 3550 { 3551 struct wm_softc *sc = ifp->if_softc; 3552 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3553 uint32_t status; 3554 int i; 3555 3556 sc->sc_txcw = ife->ifm_data; 3557 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3558 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3559 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3560 sc->sc_txcw |= TXCW_ANE; 3561 3562 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3563 delay(10000); 3564 3565 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3566 3567 sc->sc_tbi_anstate = 0; 3568 3569 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3570 /* Have signal; wait for the link to come up. */ 3571 for (i = 0; i < 50; i++) { 3572 delay(10000); 3573 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3574 break; 3575 } 3576 3577 status = CSR_READ(sc, WMREG_STATUS); 3578 if (status & STATUS_LU) { 3579 /* Link is up. */ 3580 DPRINTF(WM_DEBUG_LINK, 3581 ("%s: LINK: set media -> link up %s\n", 3582 sc->sc_dev.dv_xname, 3583 (status & STATUS_FD) ? "FDX" : "HDX")); 3584 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3585 sc->sc_fcrtl &= ~FCRTL_XONE; 3586 if (status & STATUS_FD) 3587 sc->sc_tctl |= 3588 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3589 else 3590 sc->sc_tctl |= 3591 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3592 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3593 sc->sc_fcrtl |= FCRTL_XONE; 3594 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3595 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3596 WMREG_OLD_FCRTL : WMREG_FCRTL, 3597 sc->sc_fcrtl); 3598 sc->sc_tbi_linkup = 1; 3599 } else { 3600 /* Link is down. */ 3601 DPRINTF(WM_DEBUG_LINK, 3602 ("%s: LINK: set media -> link down\n", 3603 sc->sc_dev.dv_xname)); 3604 sc->sc_tbi_linkup = 0; 3605 } 3606 } else { 3607 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3608 sc->sc_dev.dv_xname)); 3609 sc->sc_tbi_linkup = 0; 3610 } 3611 3612 wm_tbi_set_linkled(sc); 3613 3614 return (0); 3615 } 3616 3617 /* 3618 * wm_tbi_set_linkled: 3619 * 3620 * Update the link LED on 1000BASE-X devices. 3621 */ 3622 static void 3623 wm_tbi_set_linkled(struct wm_softc *sc) 3624 { 3625 3626 if (sc->sc_tbi_linkup) 3627 sc->sc_ctrl |= CTRL_SWDPIN(0); 3628 else 3629 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3630 3631 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3632 } 3633 3634 /* 3635 * wm_tbi_check_link: 3636 * 3637 * Check the link on 1000BASE-X devices. 3638 */ 3639 static void 3640 wm_tbi_check_link(struct wm_softc *sc) 3641 { 3642 uint32_t rxcw, ctrl, status; 3643 3644 if (sc->sc_tbi_anstate == 0) 3645 return; 3646 else if (sc->sc_tbi_anstate > 1) { 3647 DPRINTF(WM_DEBUG_LINK, 3648 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3649 sc->sc_tbi_anstate)); 3650 sc->sc_tbi_anstate--; 3651 return; 3652 } 3653 3654 sc->sc_tbi_anstate = 0; 3655 3656 rxcw = CSR_READ(sc, WMREG_RXCW); 3657 ctrl = CSR_READ(sc, WMREG_CTRL); 3658 status = CSR_READ(sc, WMREG_STATUS); 3659 3660 if ((status & STATUS_LU) == 0) { 3661 DPRINTF(WM_DEBUG_LINK, 3662 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3663 sc->sc_tbi_linkup = 0; 3664 } else { 3665 DPRINTF(WM_DEBUG_LINK, 3666 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3667 (status & STATUS_FD) ? "FDX" : "HDX")); 3668 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3669 sc->sc_fcrtl &= ~FCRTL_XONE; 3670 if (status & STATUS_FD) 3671 sc->sc_tctl |= 3672 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3673 else 3674 sc->sc_tctl |= 3675 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3676 if (ctrl & CTRL_TFCE) 3677 sc->sc_fcrtl |= FCRTL_XONE; 3678 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3679 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3680 WMREG_OLD_FCRTL : WMREG_FCRTL, 3681 sc->sc_fcrtl); 3682 sc->sc_tbi_linkup = 1; 3683 } 3684 3685 wm_tbi_set_linkled(sc); 3686 } 3687 3688 /* 3689 * wm_gmii_reset: 3690 * 3691 * Reset the PHY. 3692 */ 3693 static void 3694 wm_gmii_reset(struct wm_softc *sc) 3695 { 3696 uint32_t reg; 3697 3698 if (sc->sc_type >= WM_T_82544) { 3699 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3700 delay(20000); 3701 3702 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3703 delay(20000); 3704 } else { 3705 /* The PHY reset pin is active-low. */ 3706 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3707 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3708 CTRL_EXT_SWDPIN(4)); 3709 reg |= CTRL_EXT_SWDPIO(4); 3710 3711 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3712 delay(10); 3713 3714 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3715 delay(10); 3716 3717 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3718 delay(10); 3719 #if 0 3720 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3721 #endif 3722 } 3723 } 3724 3725 /* 3726 * wm_gmii_mediainit: 3727 * 3728 * Initialize media for use on 1000BASE-T devices. 3729 */ 3730 static void 3731 wm_gmii_mediainit(struct wm_softc *sc) 3732 { 3733 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3734 3735 /* We have MII. */ 3736 sc->sc_flags |= WM_F_HAS_MII; 3737 3738 sc->sc_tipg = TIPG_1000T_DFLT; 3739 3740 /* 3741 * Let the chip set speed/duplex on its own based on 3742 * signals from the PHY. 3743 */ 3744 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3745 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3746 3747 /* Initialize our media structures and probe the GMII. */ 3748 sc->sc_mii.mii_ifp = ifp; 3749 3750 if (sc->sc_type >= WM_T_82544) { 3751 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3752 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3753 } else { 3754 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3755 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3756 } 3757 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3758 3759 wm_gmii_reset(sc); 3760 3761 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3762 wm_gmii_mediastatus); 3763 3764 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3765 MII_OFFSET_ANY, MIIF_DOPAUSE); 3766 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3767 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3768 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3769 } else 3770 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3771 } 3772 3773 /* 3774 * wm_gmii_mediastatus: [ifmedia interface function] 3775 * 3776 * Get the current interface media status on a 1000BASE-T device. 3777 */ 3778 static void 3779 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3780 { 3781 struct wm_softc *sc = ifp->if_softc; 3782 3783 mii_pollstat(&sc->sc_mii); 3784 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3785 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3786 sc->sc_flowflags; 3787 } 3788 3789 /* 3790 * wm_gmii_mediachange: [ifmedia interface function] 3791 * 3792 * Set hardware to newly-selected media on a 1000BASE-T device. 3793 */ 3794 static int 3795 wm_gmii_mediachange(struct ifnet *ifp) 3796 { 3797 struct wm_softc *sc = ifp->if_softc; 3798 3799 if (ifp->if_flags & IFF_UP) 3800 mii_mediachg(&sc->sc_mii); 3801 return (0); 3802 } 3803 3804 #define MDI_IO CTRL_SWDPIN(2) 3805 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3806 #define MDI_CLK CTRL_SWDPIN(3) 3807 3808 static void 3809 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3810 { 3811 uint32_t i, v; 3812 3813 v = CSR_READ(sc, WMREG_CTRL); 3814 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3815 v |= MDI_DIR | CTRL_SWDPIO(3); 3816 3817 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3818 if (data & i) 3819 v |= MDI_IO; 3820 else 3821 v &= ~MDI_IO; 3822 CSR_WRITE(sc, WMREG_CTRL, v); 3823 delay(10); 3824 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3825 delay(10); 3826 CSR_WRITE(sc, WMREG_CTRL, v); 3827 delay(10); 3828 } 3829 } 3830 3831 static uint32_t 3832 i82543_mii_recvbits(struct wm_softc *sc) 3833 { 3834 uint32_t v, i, data = 0; 3835 3836 v = CSR_READ(sc, WMREG_CTRL); 3837 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3838 v |= CTRL_SWDPIO(3); 3839 3840 CSR_WRITE(sc, WMREG_CTRL, v); 3841 delay(10); 3842 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3843 delay(10); 3844 CSR_WRITE(sc, WMREG_CTRL, v); 3845 delay(10); 3846 3847 for (i = 0; i < 16; i++) { 3848 data <<= 1; 3849 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3850 delay(10); 3851 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3852 data |= 1; 3853 CSR_WRITE(sc, WMREG_CTRL, v); 3854 delay(10); 3855 } 3856 3857 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3858 delay(10); 3859 CSR_WRITE(sc, WMREG_CTRL, v); 3860 delay(10); 3861 3862 return (data); 3863 } 3864 3865 #undef MDI_IO 3866 #undef MDI_DIR 3867 #undef MDI_CLK 3868 3869 /* 3870 * wm_gmii_i82543_readreg: [mii interface function] 3871 * 3872 * Read a PHY register on the GMII (i82543 version). 3873 */ 3874 static int 3875 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3876 { 3877 struct wm_softc *sc = (void *) self; 3878 int rv; 3879 3880 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3881 i82543_mii_sendbits(sc, reg | (phy << 5) | 3882 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3883 rv = i82543_mii_recvbits(sc) & 0xffff; 3884 3885 DPRINTF(WM_DEBUG_GMII, 3886 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3887 sc->sc_dev.dv_xname, phy, reg, rv)); 3888 3889 return (rv); 3890 } 3891 3892 /* 3893 * wm_gmii_i82543_writereg: [mii interface function] 3894 * 3895 * Write a PHY register on the GMII (i82543 version). 3896 */ 3897 static void 3898 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3899 { 3900 struct wm_softc *sc = (void *) self; 3901 3902 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3903 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3904 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3905 (MII_COMMAND_START << 30), 32); 3906 } 3907 3908 /* 3909 * wm_gmii_i82544_readreg: [mii interface function] 3910 * 3911 * Read a PHY register on the GMII. 3912 */ 3913 static int 3914 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3915 { 3916 struct wm_softc *sc = (void *) self; 3917 uint32_t mdic = 0; 3918 int i, rv; 3919 3920 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3921 MDIC_REGADD(reg)); 3922 3923 for (i = 0; i < 100; i++) { 3924 mdic = CSR_READ(sc, WMREG_MDIC); 3925 if (mdic & MDIC_READY) 3926 break; 3927 delay(10); 3928 } 3929 3930 if ((mdic & MDIC_READY) == 0) { 3931 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 3932 sc->sc_dev.dv_xname, phy, reg); 3933 rv = 0; 3934 } else if (mdic & MDIC_E) { 3935 #if 0 /* This is normal if no PHY is present. */ 3936 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 3937 sc->sc_dev.dv_xname, phy, reg); 3938 #endif 3939 rv = 0; 3940 } else { 3941 rv = MDIC_DATA(mdic); 3942 if (rv == 0xffff) 3943 rv = 0; 3944 } 3945 3946 return (rv); 3947 } 3948 3949 /* 3950 * wm_gmii_i82544_writereg: [mii interface function] 3951 * 3952 * Write a PHY register on the GMII. 3953 */ 3954 static void 3955 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3956 { 3957 struct wm_softc *sc = (void *) self; 3958 uint32_t mdic = 0; 3959 int i; 3960 3961 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3962 MDIC_REGADD(reg) | MDIC_DATA(val)); 3963 3964 for (i = 0; i < 100; i++) { 3965 mdic = CSR_READ(sc, WMREG_MDIC); 3966 if (mdic & MDIC_READY) 3967 break; 3968 delay(10); 3969 } 3970 3971 if ((mdic & MDIC_READY) == 0) 3972 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 3973 sc->sc_dev.dv_xname, phy, reg); 3974 else if (mdic & MDIC_E) 3975 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 3976 sc->sc_dev.dv_xname, phy, reg); 3977 } 3978 3979 /* 3980 * wm_gmii_statchg: [mii interface function] 3981 * 3982 * Callback from MII layer when media changes. 3983 */ 3984 static void 3985 wm_gmii_statchg(struct device *self) 3986 { 3987 struct wm_softc *sc = (void *) self; 3988 struct mii_data *mii = &sc->sc_mii; 3989 3990 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3991 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3992 sc->sc_fcrtl &= ~FCRTL_XONE; 3993 3994 /* 3995 * Get flow control negotiation result. 3996 */ 3997 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3998 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3999 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 4000 mii->mii_media_active &= ~IFM_ETH_FMASK; 4001 } 4002 4003 if (sc->sc_flowflags & IFM_FLOW) { 4004 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 4005 sc->sc_ctrl |= CTRL_TFCE; 4006 sc->sc_fcrtl |= FCRTL_XONE; 4007 } 4008 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 4009 sc->sc_ctrl |= CTRL_RFCE; 4010 } 4011 4012 if (sc->sc_mii.mii_media_active & IFM_FDX) { 4013 DPRINTF(WM_DEBUG_LINK, 4014 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 4015 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4016 } else { 4017 DPRINTF(WM_DEBUG_LINK, 4018 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 4019 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 4020 } 4021 4022 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4023 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4024 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 4025 : WMREG_FCRTL, sc->sc_fcrtl); 4026 } 4027
Indexes created Wed Sep 24 15:09:51 GMT 2025