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if_wm.c revision 1.118
      1 /*	$NetBSD: if_wm.c,v 1.118 2006/06/10 08:08:33 msaitoh Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
      5  * All rights reserved.
      6  *
      7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
      8  *
      9  * Redistribution and use in source and binary forms, with or without
     10  * modification, are permitted provided that the following conditions
     11  * are met:
     12  * 1. Redistributions of source code must retain the above copyright
     13  *    notice, this list of conditions and the following disclaimer.
     14  * 2. Redistributions in binary form must reproduce the above copyright
     15  *    notice, this list of conditions and the following disclaimer in the
     16  *    documentation and/or other materials provided with the distribution.
     17  * 3. All advertising materials mentioning features or use of this software
     18  *    must display the following acknowledgement:
     19  *	This product includes software developed for the NetBSD Project by
     20  *	Wasabi Systems, Inc.
     21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  *    or promote products derived from this software without specific prior
     23  *    written permission.
     24  *
     25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  * POSSIBILITY OF SUCH DAMAGE.
     36  */
     37 
     38 /*
     39  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
     40  *
     41  * TODO (in order of importance):
     42  *
     43  *	- Rework how parameters are loaded from the EEPROM.
     44  *	- Figure out what to do with the i82545GM and i82546GB
     45  *	  SERDES controllers.
     46  *	- Fix hw VLAN assist.
     47  */
     48 
     49 #include <sys/cdefs.h>
     50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.118 2006/06/10 08:08:33 msaitoh Exp $");
     51 
     52 #include "bpfilter.h"
     53 #include "rnd.h"
     54 
     55 #include <sys/param.h>
     56 #include <sys/systm.h>
     57 #include <sys/callout.h>
     58 #include <sys/mbuf.h>
     59 #include <sys/malloc.h>
     60 #include <sys/kernel.h>
     61 #include <sys/socket.h>
     62 #include <sys/ioctl.h>
     63 #include <sys/errno.h>
     64 #include <sys/device.h>
     65 #include <sys/queue.h>
     66 #include <sys/syslog.h>
     67 
     68 #include <uvm/uvm_extern.h>		/* for PAGE_SIZE */
     69 
     70 #if NRND > 0
     71 #include <sys/rnd.h>
     72 #endif
     73 
     74 #include <net/if.h>
     75 #include <net/if_dl.h>
     76 #include <net/if_media.h>
     77 #include <net/if_ether.h>
     78 
     79 #if NBPFILTER > 0
     80 #include <net/bpf.h>
     81 #endif
     82 
     83 #include <netinet/in.h>			/* XXX for struct ip */
     84 #include <netinet/in_systm.h>		/* XXX for struct ip */
     85 #include <netinet/ip.h>			/* XXX for struct ip */
     86 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
     87 
     88 #include <machine/bus.h>
     89 #include <machine/intr.h>
     90 #include <machine/endian.h>
     91 
     92 #include <dev/mii/mii.h>
     93 #include <dev/mii/miivar.h>
     94 #include <dev/mii/mii_bitbang.h>
     95 
     96 #include <dev/pci/pcireg.h>
     97 #include <dev/pci/pcivar.h>
     98 #include <dev/pci/pcidevs.h>
     99 
    100 #include <dev/pci/if_wmreg.h>
    101 
    102 #ifdef WM_DEBUG
    103 #define	WM_DEBUG_LINK		0x01
    104 #define	WM_DEBUG_TX		0x02
    105 #define	WM_DEBUG_RX		0x04
    106 #define	WM_DEBUG_GMII		0x08
    107 int	wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;
    108 
    109 #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
    110 #else
    111 #define	DPRINTF(x, y)	/* nothing */
    112 #endif /* WM_DEBUG */
    113 
    114 /*
    115  * Transmit descriptor list size.  Due to errata, we can only have
    116  * 256 hardware descriptors in the ring on < 82544, but we use 4096
    117  * on >= 82544.  We tell the upper layers that they can queue a lot
    118  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
    119  * of them at a time.
    120  *
    121  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
    122  * chains containing many small mbufs have been observed in zero-copy
    123  * situations with jumbo frames.
    124  */
    125 #define	WM_NTXSEGS		256
    126 #define	WM_IFQUEUELEN		256
    127 #define	WM_TXQUEUELEN_MAX	64
    128 #define	WM_TXQUEUELEN_MAX_82547	16
    129 #define	WM_TXQUEUELEN(sc)	((sc)->sc_txnum)
    130 #define	WM_TXQUEUELEN_MASK(sc)	(WM_TXQUEUELEN(sc) - 1)
    131 #define	WM_TXQUEUE_GC(sc)	(WM_TXQUEUELEN(sc) / 8)
    132 #define	WM_NTXDESC_82542	256
    133 #define	WM_NTXDESC_82544	4096
    134 #define	WM_NTXDESC(sc)		((sc)->sc_ntxdesc)
    135 #define	WM_NTXDESC_MASK(sc)	(WM_NTXDESC(sc) - 1)
    136 #define	WM_TXDESCSIZE(sc)	(WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t))
    137 #define	WM_NEXTTX(sc, x)	(((x) + 1) & WM_NTXDESC_MASK(sc))
    138 #define	WM_NEXTTXS(sc, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(sc))
    139 
    140 #define	WM_MAXTXDMA		round_page(IP_MAXPACKET) /* for TSO */
    141 
    142 /*
    143  * Receive descriptor list size.  We have one Rx buffer for normal
    144  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
    145  * packet.  We allocate 256 receive descriptors, each with a 2k
    146  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
    147  */
    148 #define	WM_NRXDESC		256
    149 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
    150 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
    151 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
    152 
    153 /*
    154  * Control structures are DMA'd to the i82542 chip.  We allocate them in
    155  * a single clump that maps to a single DMA segment to make several things
    156  * easier.
    157  */
    158 struct wm_control_data_82544 {
    159 	/*
    160 	 * The receive descriptors.
    161 	 */
    162 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
    163 
    164 	/*
    165 	 * The transmit descriptors.  Put these at the end, because
    166 	 * we might use a smaller number of them.
    167 	 */
    168 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544];
    169 };
    170 
    171 struct wm_control_data_82542 {
    172 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
    173 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542];
    174 };
    175 
    176 #define	WM_CDOFF(x)	offsetof(struct wm_control_data_82544, x)
    177 #define	WM_CDTXOFF(x)	WM_CDOFF(wcd_txdescs[(x)])
    178 #define	WM_CDRXOFF(x)	WM_CDOFF(wcd_rxdescs[(x)])
    179 
    180 /*
    181  * Software state for transmit jobs.
    182  */
    183 struct wm_txsoft {
    184 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
    185 	bus_dmamap_t txs_dmamap;	/* our DMA map */
    186 	int txs_firstdesc;		/* first descriptor in packet */
    187 	int txs_lastdesc;		/* last descriptor in packet */
    188 	int txs_ndesc;			/* # of descriptors used */
    189 };
    190 
    191 /*
    192  * Software state for receive buffers.  Each descriptor gets a
    193  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
    194  * more than one buffer, we chain them together.
    195  */
    196 struct wm_rxsoft {
    197 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
    198 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
    199 };
    200 
    201 typedef enum {
    202 	WM_T_unknown		= 0,
    203 	WM_T_82542_2_0,			/* i82542 2.0 (really old) */
    204 	WM_T_82542_2_1,			/* i82542 2.1+ (old) */
    205 	WM_T_82543,			/* i82543 */
    206 	WM_T_82544,			/* i82544 */
    207 	WM_T_82540,			/* i82540 */
    208 	WM_T_82545,			/* i82545 */
    209 	WM_T_82545_3,			/* i82545 3.0+ */
    210 	WM_T_82546,			/* i82546 */
    211 	WM_T_82546_3,			/* i82546 3.0+ */
    212 	WM_T_82541,			/* i82541 */
    213 	WM_T_82541_2,			/* i82541 2.0+ */
    214 	WM_T_82547,			/* i82547 */
    215 	WM_T_82547_2,			/* i82547 2.0+ */
    216 	WM_T_82571,			/* i82571 */
    217 	WM_T_82572,			/* i82572 */
    218 	WM_T_82573,			/* i82573 */
    219 } wm_chip_type;
    220 
    221 /*
    222  * Software state per device.
    223  */
    224 struct wm_softc {
    225 	struct device sc_dev;		/* generic device information */
    226 	bus_space_tag_t sc_st;		/* bus space tag */
    227 	bus_space_handle_t sc_sh;	/* bus space handle */
    228 	bus_space_tag_t sc_iot;		/* I/O space tag */
    229 	bus_space_handle_t sc_ioh;	/* I/O space handle */
    230 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
    231 	struct ethercom sc_ethercom;	/* ethernet common data */
    232 	void *sc_sdhook;		/* shutdown hook */
    233 
    234 	wm_chip_type sc_type;		/* chip type */
    235 	int sc_flags;			/* flags; see below */
    236 	int sc_bus_speed;		/* PCI/PCIX bus speed */
    237 	int sc_pcix_offset;		/* PCIX capability register offset */
    238 	int sc_flowflags;		/* 802.3x flow control flags */
    239 
    240 	void *sc_ih;			/* interrupt cookie */
    241 
    242 	int sc_ee_addrbits;		/* EEPROM address bits */
    243 
    244 	struct mii_data sc_mii;		/* MII/media information */
    245 
    246 	struct callout sc_tick_ch;	/* tick callout */
    247 
    248 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
    249 #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
    250 
    251 	int		sc_align_tweak;
    252 
    253 	/*
    254 	 * Software state for the transmit and receive descriptors.
    255 	 */
    256 	int			sc_txnum;	/* must be a power of two */
    257 	struct wm_txsoft	sc_txsoft[WM_TXQUEUELEN_MAX];
    258 	struct wm_rxsoft	sc_rxsoft[WM_NRXDESC];
    259 
    260 	/*
    261 	 * Control data structures.
    262 	 */
    263 	int			sc_ntxdesc;	/* must be a power of two */
    264 	struct wm_control_data_82544 *sc_control_data;
    265 #define	sc_txdescs	sc_control_data->wcd_txdescs
    266 #define	sc_rxdescs	sc_control_data->wcd_rxdescs
    267 
    268 #ifdef WM_EVENT_COUNTERS
    269 	/* Event counters. */
    270 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
    271 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
    272 	struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
    273 	struct evcnt sc_ev_txdw;	/* Tx descriptor interrupts */
    274 	struct evcnt sc_ev_txqe;	/* Tx queue empty interrupts */
    275 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
    276 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
    277 
    278 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
    279 	struct evcnt sc_ev_rxtusum;	/* TCP/UDP cksums checked in-bound */
    280 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
    281 	struct evcnt sc_ev_txtusum;	/* TCP/UDP cksums comp. out-bound */
    282 	struct evcnt sc_ev_txtusum6;	/* TCP/UDP v6 cksums comp. out-bound */
    283 	struct evcnt sc_ev_txtso;	/* TCP seg offload out-bound */
    284 	struct evcnt sc_ev_txtsopain;	/* painful header manip. for TSO */
    285 
    286 	struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
    287 	struct evcnt sc_ev_txdrop;	/* Tx packets dropped (too many segs) */
    288 
    289 	struct evcnt sc_ev_tu;		/* Tx underrun */
    290 
    291 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
    292 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
    293 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
    294 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
    295 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
    296 #endif /* WM_EVENT_COUNTERS */
    297 
    298 	bus_addr_t sc_tdt_reg;		/* offset of TDT register */
    299 
    300 	int	sc_txfree;		/* number of free Tx descriptors */
    301 	int	sc_txnext;		/* next ready Tx descriptor */
    302 
    303 	int	sc_txsfree;		/* number of free Tx jobs */
    304 	int	sc_txsnext;		/* next free Tx job */
    305 	int	sc_txsdirty;		/* dirty Tx jobs */
    306 
    307 	/* These 5 variables are used only on the 82547. */
    308 	int	sc_txfifo_size;		/* Tx FIFO size */
    309 	int	sc_txfifo_head;		/* current head of FIFO */
    310 	uint32_t sc_txfifo_addr;	/* internal address of start of FIFO */
    311 	int	sc_txfifo_stall;	/* Tx FIFO is stalled */
    312 	struct callout sc_txfifo_ch;	/* Tx FIFO stall work-around timer */
    313 
    314 	bus_addr_t sc_rdt_reg;		/* offset of RDT register */
    315 
    316 	int	sc_rxptr;		/* next ready Rx descriptor/queue ent */
    317 	int	sc_rxdiscard;
    318 	int	sc_rxlen;
    319 	struct mbuf *sc_rxhead;
    320 	struct mbuf *sc_rxtail;
    321 	struct mbuf **sc_rxtailp;
    322 
    323 	uint32_t sc_ctrl;		/* prototype CTRL register */
    324 #if 0
    325 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
    326 #endif
    327 	uint32_t sc_icr;		/* prototype interrupt bits */
    328 	uint32_t sc_itr;		/* prototype intr throttling reg */
    329 	uint32_t sc_tctl;		/* prototype TCTL register */
    330 	uint32_t sc_rctl;		/* prototype RCTL register */
    331 	uint32_t sc_txcw;		/* prototype TXCW register */
    332 	uint32_t sc_tipg;		/* prototype TIPG register */
    333 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
    334 	uint32_t sc_pba;		/* prototype PBA register */
    335 
    336 	int sc_tbi_linkup;		/* TBI link status */
    337 	int sc_tbi_anstate;		/* autonegotiation state */
    338 
    339 	int sc_mchash_type;		/* multicast filter offset */
    340 
    341 #if NRND > 0
    342 	rndsource_element_t rnd_source;	/* random source */
    343 #endif
    344 };
    345 
    346 #define	WM_RXCHAIN_RESET(sc)						\
    347 do {									\
    348 	(sc)->sc_rxtailp = &(sc)->sc_rxhead;				\
    349 	*(sc)->sc_rxtailp = NULL;					\
    350 	(sc)->sc_rxlen = 0;						\
    351 } while (/*CONSTCOND*/0)
    352 
    353 #define	WM_RXCHAIN_LINK(sc, m)						\
    354 do {									\
    355 	*(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);			\
    356 	(sc)->sc_rxtailp = &(m)->m_next;				\
    357 } while (/*CONSTCOND*/0)
    358 
    359 /* sc_flags */
    360 #define	WM_F_HAS_MII		0x001	/* has MII */
    361 #define	WM_F_EEPROM_HANDSHAKE	0x002	/* requires EEPROM handshake */
    362 #define	WM_F_EEPROM_SEMAPHORE	0x004	/* EEPROM with semaphore */
    363 #define	WM_F_EEPROM_EERDEEWR	0x008	/* EEPROM access via EERD/EEWR */
    364 #define	WM_F_EEPROM_SPI		0x010	/* EEPROM is SPI */
    365 #define	WM_F_EEPROM_FLASH	0x020	/* EEPROM is FLASH */
    366 #define	WM_F_EEPROM_INVALID	0x040	/* EEPROM not present (bad checksum) */
    367 #define	WM_F_IOH_VALID		0x080	/* I/O handle is valid */
    368 #define	WM_F_BUS64		0x100	/* bus is 64-bit */
    369 #define	WM_F_PCIX		0x200	/* bus is PCI-X */
    370 #define	WM_F_CSA		0x400	/* bus is CSA */
    371 #define	WM_F_PCIE		0x800	/* bus is PCI-Express */
    372 
    373 #ifdef WM_EVENT_COUNTERS
    374 #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
    375 #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
    376 #else
    377 #define	WM_EVCNT_INCR(ev)	/* nothing */
    378 #define	WM_EVCNT_ADD(ev, val)	/* nothing */
    379 #endif
    380 
    381 #define	CSR_READ(sc, reg)						\
    382 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
    383 #define	CSR_WRITE(sc, reg, val)						\
    384 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
    385 #define	CSR_WRITE_FLUSH(sc)						\
    386 	(void) CSR_READ((sc), WMREG_STATUS)
    387 
    388 #define	WM_CDTXADDR(sc, x)	((sc)->sc_cddma + WM_CDTXOFF((x)))
    389 #define	WM_CDRXADDR(sc, x)	((sc)->sc_cddma + WM_CDRXOFF((x)))
    390 
    391 #define	WM_CDTXADDR_LO(sc, x)	(WM_CDTXADDR((sc), (x)) & 0xffffffffU)
    392 #define	WM_CDTXADDR_HI(sc, x)						\
    393 	(sizeof(bus_addr_t) == 8 ?					\
    394 	 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
    395 
    396 #define	WM_CDRXADDR_LO(sc, x)	(WM_CDRXADDR((sc), (x)) & 0xffffffffU)
    397 #define	WM_CDRXADDR_HI(sc, x)						\
    398 	(sizeof(bus_addr_t) == 8 ?					\
    399 	 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
    400 
    401 #define	WM_CDTXSYNC(sc, x, n, ops)					\
    402 do {									\
    403 	int __x, __n;							\
    404 									\
    405 	__x = (x);							\
    406 	__n = (n);							\
    407 									\
    408 	/* If it will wrap around, sync to the end of the ring. */	\
    409 	if ((__x + __n) > WM_NTXDESC(sc)) {				\
    410 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
    411 		    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) *		\
    412 		    (WM_NTXDESC(sc) - __x), (ops));			\
    413 		__n -= (WM_NTXDESC(sc) - __x);				\
    414 		__x = 0;						\
    415 	}								\
    416 									\
    417 	/* Now sync whatever is left. */				\
    418 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    419 	    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops));	\
    420 } while (/*CONSTCOND*/0)
    421 
    422 #define	WM_CDRXSYNC(sc, x, ops)						\
    423 do {									\
    424 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
    425 	   WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops));		\
    426 } while (/*CONSTCOND*/0)
    427 
    428 #define	WM_INIT_RXDESC(sc, x)						\
    429 do {									\
    430 	struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
    431 	wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];		\
    432 	struct mbuf *__m = __rxs->rxs_mbuf;				\
    433 									\
    434 	/*								\
    435 	 * Note: We scoot the packet forward 2 bytes in the buffer	\
    436 	 * so that the payload after the Ethernet header is aligned	\
    437 	 * to a 4-byte boundary.					\
    438 	 *								\
    439 	 * XXX BRAINDAMAGE ALERT!					\
    440 	 * The stupid chip uses the same size for every buffer, which	\
    441 	 * is set in the Receive Control register.  We are using the 2K	\
    442 	 * size option, but what we REALLY want is (2K - 2)!  For this	\
    443 	 * reason, we can't "scoot" packets longer than the standard	\
    444 	 * Ethernet MTU.  On strict-alignment platforms, if the total	\
    445 	 * size exceeds (2K - 2) we set align_tweak to 0 and let	\
    446 	 * the upper layer copy the headers.				\
    447 	 */								\
    448 	__m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak;	\
    449 									\
    450 	wm_set_dma_addr(&__rxd->wrx_addr,				\
    451 	    __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \
    452 	__rxd->wrx_len = 0;						\
    453 	__rxd->wrx_cksum = 0;						\
    454 	__rxd->wrx_status = 0;						\
    455 	__rxd->wrx_errors = 0;						\
    456 	__rxd->wrx_special = 0;						\
    457 	WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
    458 									\
    459 	CSR_WRITE((sc), (sc)->sc_rdt_reg, (x));				\
    460 } while (/*CONSTCOND*/0)
    461 
    462 static void	wm_start(struct ifnet *);
    463 static void	wm_watchdog(struct ifnet *);
    464 static int	wm_ioctl(struct ifnet *, u_long, caddr_t);
    465 static int	wm_init(struct ifnet *);
    466 static void	wm_stop(struct ifnet *, int);
    467 
    468 static void	wm_shutdown(void *);
    469 
    470 static void	wm_reset(struct wm_softc *);
    471 static void	wm_rxdrain(struct wm_softc *);
    472 static int	wm_add_rxbuf(struct wm_softc *, int);
    473 static int	wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *);
    474 static int	wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *);
    475 static int	wm_validate_eeprom_checksum(struct wm_softc *);
    476 static void	wm_tick(void *);
    477 
    478 static void	wm_set_filter(struct wm_softc *);
    479 
    480 static int	wm_intr(void *);
    481 static void	wm_txintr(struct wm_softc *);
    482 static void	wm_rxintr(struct wm_softc *);
    483 static void	wm_linkintr(struct wm_softc *, uint32_t);
    484 
    485 static void	wm_tbi_mediainit(struct wm_softc *);
    486 static int	wm_tbi_mediachange(struct ifnet *);
    487 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
    488 
    489 static void	wm_tbi_set_linkled(struct wm_softc *);
    490 static void	wm_tbi_check_link(struct wm_softc *);
    491 
    492 static void	wm_gmii_reset(struct wm_softc *);
    493 
    494 static int	wm_gmii_i82543_readreg(struct device *, int, int);
    495 static void	wm_gmii_i82543_writereg(struct device *, int, int, int);
    496 
    497 static int	wm_gmii_i82544_readreg(struct device *, int, int);
    498 static void	wm_gmii_i82544_writereg(struct device *, int, int, int);
    499 
    500 static void	wm_gmii_statchg(struct device *);
    501 
    502 static void	wm_gmii_mediainit(struct wm_softc *);
    503 static int	wm_gmii_mediachange(struct ifnet *);
    504 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
    505 
    506 static int	wm_match(struct device *, struct cfdata *, void *);
    507 static void	wm_attach(struct device *, struct device *, void *);
    508 static int	wm_is_onboard_nvm_eeprom(struct wm_softc *);
    509 static int	wm_get_eeprom_semaphore(struct wm_softc *);
    510 static void	wm_put_eeprom_semaphore(struct wm_softc *);
    511 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
    512 
    513 CFATTACH_DECL(wm, sizeof(struct wm_softc),
    514     wm_match, wm_attach, NULL, NULL);
    515 
    516 static void	wm_82547_txfifo_stall(void *);
    517 
    518 /*
    519  * Devices supported by this driver.
    520  */
    521 static const struct wm_product {
    522 	pci_vendor_id_t		wmp_vendor;
    523 	pci_product_id_t	wmp_product;
    524 	const char		*wmp_name;
    525 	wm_chip_type		wmp_type;
    526 	int			wmp_flags;
    527 #define	WMP_F_1000X		0x01
    528 #define	WMP_F_1000T		0x02
    529 } wm_products[] = {
    530 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
    531 	  "Intel i82542 1000BASE-X Ethernet",
    532 	  WM_T_82542_2_1,	WMP_F_1000X },
    533 
    534 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
    535 	  "Intel i82543GC 1000BASE-X Ethernet",
    536 	  WM_T_82543,		WMP_F_1000X },
    537 
    538 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
    539 	  "Intel i82543GC 1000BASE-T Ethernet",
    540 	  WM_T_82543,		WMP_F_1000T },
    541 
    542 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
    543 	  "Intel i82544EI 1000BASE-T Ethernet",
    544 	  WM_T_82544,		WMP_F_1000T },
    545 
    546 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
    547 	  "Intel i82544EI 1000BASE-X Ethernet",
    548 	  WM_T_82544,		WMP_F_1000X },
    549 
    550 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
    551 	  "Intel i82544GC 1000BASE-T Ethernet",
    552 	  WM_T_82544,		WMP_F_1000T },
    553 
    554 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
    555 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
    556 	  WM_T_82544,		WMP_F_1000T },
    557 
    558 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
    559 	  "Intel i82540EM 1000BASE-T Ethernet",
    560 	  WM_T_82540,		WMP_F_1000T },
    561 
    562 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
    563 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
    564 	  WM_T_82540,		WMP_F_1000T },
    565 
    566 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
    567 	  "Intel i82540EP 1000BASE-T Ethernet",
    568 	  WM_T_82540,		WMP_F_1000T },
    569 
    570 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
    571 	  "Intel i82540EP 1000BASE-T Ethernet",
    572 	  WM_T_82540,		WMP_F_1000T },
    573 
    574 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
    575 	  "Intel i82540EP 1000BASE-T Ethernet",
    576 	  WM_T_82540,		WMP_F_1000T },
    577 
    578 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
    579 	  "Intel i82545EM 1000BASE-T Ethernet",
    580 	  WM_T_82545,		WMP_F_1000T },
    581 
    582 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
    583 	  "Intel i82545GM 1000BASE-T Ethernet",
    584 	  WM_T_82545_3,		WMP_F_1000T },
    585 
    586 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
    587 	  "Intel i82545GM 1000BASE-X Ethernet",
    588 	  WM_T_82545_3,		WMP_F_1000X },
    589 #if 0
    590 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
    591 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
    592 	  WM_T_82545_3,		WMP_F_SERDES },
    593 #endif
    594 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
    595 	  "Intel i82546EB 1000BASE-T Ethernet",
    596 	  WM_T_82546,		WMP_F_1000T },
    597 
    598 	{ PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82546EB_QUAD,
    599 	  "Intel i82546EB 1000BASE-T Ethernet",
    600 	  WM_T_82546,		WMP_F_1000T },
    601 
    602 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
    603 	  "Intel i82545EM 1000BASE-X Ethernet",
    604 	  WM_T_82545,		WMP_F_1000X },
    605 
    606 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
    607 	  "Intel i82546EB 1000BASE-X Ethernet",
    608 	  WM_T_82546,		WMP_F_1000X },
    609 
    610 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
    611 	  "Intel i82546GB 1000BASE-T Ethernet",
    612 	  WM_T_82546_3,		WMP_F_1000T },
    613 
    614 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
    615 	  "Intel i82546GB 1000BASE-X Ethernet",
    616 	  WM_T_82546_3,		WMP_F_1000X },
    617 #if 0
    618 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
    619 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
    620 	  WM_T_82546_3,		WMP_F_SERDES },
    621 #endif
    622 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
    623 	  "Intel PRO/1000MT (82546GB)",
    624 	  WM_T_82546_3,		WMP_F_1000T },
    625 
    626 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
    627 	  "Intel i82541EI 1000BASE-T Ethernet",
    628 	  WM_T_82541,		WMP_F_1000T },
    629 
    630 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
    631 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
    632 	  WM_T_82541,		WMP_F_1000T },
    633 
    634 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
    635 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
    636 	  WM_T_82541,		WMP_F_1000T },
    637 
    638 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
    639 	  "Intel i82541ER 1000BASE-T Ethernet",
    640 	  WM_T_82541_2,		WMP_F_1000T },
    641 
    642 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
    643 	  "Intel i82541GI 1000BASE-T Ethernet",
    644 	  WM_T_82541_2,		WMP_F_1000T },
    645 
    646 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
    647 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
    648 	  WM_T_82541_2,		WMP_F_1000T },
    649 
    650 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
    651 	  "Intel i82541PI 1000BASE-T Ethernet",
    652 	  WM_T_82541_2,		WMP_F_1000T },
    653 
    654 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
    655 	  "Intel i82547EI 1000BASE-T Ethernet",
    656 	  WM_T_82547,		WMP_F_1000T },
    657 
    658 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
    659 	  "Intel i82547EI Moblie 1000BASE-T Ethernet",
    660 	  WM_T_82547,		WMP_F_1000T },
    661 
    662 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
    663 	  "Intel i82547GI 1000BASE-T Ethernet",
    664 	  WM_T_82547_2,		WMP_F_1000T },
    665 
    666 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
    667 	  "Intel PRO/1000 PT (82571EB)",
    668 	  WM_T_82571,		WMP_F_1000T },
    669 
    670 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
    671 	  "Intel PRO/1000 PF (82571EB)",
    672 	  WM_T_82571,		WMP_F_1000X },
    673 #if 0
    674 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
    675 	  "Intel PRO/1000 PB (82571EB)",
    676 	  WM_T_82571,		WMP_F_SERDES },
    677 #endif
    678 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
    679 	  "Intel i82572EI 1000baseT Ethernet",
    680 	  WM_T_82572,		WMP_F_1000T },
    681 
    682 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
    683 	  "Intel i82572EI 1000baseX Ethernet",
    684 	  WM_T_82572,		WMP_F_1000X },
    685 #if 0
    686 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
    687 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
    688 	  WM_T_82572,		WMP_F_SERDES },
    689 #endif
    690 
    691 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
    692 	  "Intel i82572EI 1000baseT Ethernet",
    693 	  WM_T_82572,		WMP_F_1000T },
    694 
    695 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
    696 	  "Intel i82573E",
    697 	  WM_T_82573,		WMP_F_1000T },
    698 
    699 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
    700 	  "Intel i82573E IAMT",
    701 	  WM_T_82573,		WMP_F_1000T },
    702 
    703 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
    704 	  "Intel i82573L Gigabit Ethernet",
    705 	  WM_T_82573,		WMP_F_1000T },
    706 
    707 	{ 0,			0,
    708 	  NULL,
    709 	  0,			0 },
    710 };
    711 
    712 #ifdef WM_EVENT_COUNTERS
    713 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")];
    714 #endif /* WM_EVENT_COUNTERS */
    715 
    716 #if 0 /* Not currently used */
    717 static inline uint32_t
    718 wm_io_read(struct wm_softc *sc, int reg)
    719 {
    720 
    721 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
    722 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
    723 }
    724 #endif
    725 
    726 static inline void
    727 wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
    728 {
    729 
    730 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
    731 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
    732 }
    733 
    734 static inline void
    735 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
    736 {
    737 	wa->wa_low = htole32(v & 0xffffffffU);
    738 	if (sizeof(bus_addr_t) == 8)
    739 		wa->wa_high = htole32((uint64_t) v >> 32);
    740 	else
    741 		wa->wa_high = 0;
    742 }
    743 
    744 static const struct wm_product *
    745 wm_lookup(const struct pci_attach_args *pa)
    746 {
    747 	const struct wm_product *wmp;
    748 
    749 	for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
    750 		if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
    751 		    PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
    752 			return (wmp);
    753 	}
    754 	return (NULL);
    755 }
    756 
    757 static int
    758 wm_match(struct device *parent, struct cfdata *cf, void *aux)
    759 {
    760 	struct pci_attach_args *pa = aux;
    761 
    762 	if (wm_lookup(pa) != NULL)
    763 		return (1);
    764 
    765 	return (0);
    766 }
    767 
    768 static void
    769 wm_attach(struct device *parent, struct device *self, void *aux)
    770 {
    771 	struct wm_softc *sc = (void *) self;
    772 	struct pci_attach_args *pa = aux;
    773 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    774 	pci_chipset_tag_t pc = pa->pa_pc;
    775 	pci_intr_handle_t ih;
    776 	size_t cdata_size;
    777 	const char *intrstr = NULL;
    778 	const char *eetype;
    779 	bus_space_tag_t memt;
    780 	bus_space_handle_t memh;
    781 	bus_dma_segment_t seg;
    782 	int memh_valid;
    783 	int i, rseg, error;
    784 	const struct wm_product *wmp;
    785 	prop_data_t ea;
    786 	prop_number_t pn;
    787 	uint8_t enaddr[ETHER_ADDR_LEN];
    788 	uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
    789 	pcireg_t preg, memtype;
    790 	uint32_t reg;
    791 	int pmreg;
    792 
    793 	callout_init(&sc->sc_tick_ch);
    794 
    795 	wmp = wm_lookup(pa);
    796 	if (wmp == NULL) {
    797 		printf("\n");
    798 		panic("wm_attach: impossible");
    799 	}
    800 
    801 	if (pci_dma64_available(pa))
    802 		sc->sc_dmat = pa->pa_dmat64;
    803 	else
    804 		sc->sc_dmat = pa->pa_dmat;
    805 
    806 	preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG));
    807 	aprint_naive(": Ethernet controller\n");
    808 	aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg);
    809 
    810 	sc->sc_type = wmp->wmp_type;
    811 	if (sc->sc_type < WM_T_82543) {
    812 		if (preg < 2) {
    813 			aprint_error("%s: i82542 must be at least rev. 2\n",
    814 			    sc->sc_dev.dv_xname);
    815 			return;
    816 		}
    817 		if (preg < 3)
    818 			sc->sc_type = WM_T_82542_2_0;
    819 	}
    820 
    821 	/*
    822 	 * Map the device.  All devices support memory-mapped acccess,
    823 	 * and it is really required for normal operation.
    824 	 */
    825 	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
    826 	switch (memtype) {
    827 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
    828 	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
    829 		memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
    830 		    memtype, 0, &memt, &memh, NULL, NULL) == 0);
    831 		break;
    832 	default:
    833 		memh_valid = 0;
    834 	}
    835 
    836 	if (memh_valid) {
    837 		sc->sc_st = memt;
    838 		sc->sc_sh = memh;
    839 	} else {
    840 		aprint_error("%s: unable to map device registers\n",
    841 		    sc->sc_dev.dv_xname);
    842 		return;
    843 	}
    844 
    845 	/*
    846 	 * In addition, i82544 and later support I/O mapped indirect
    847 	 * register access.  It is not desirable (nor supported in
    848 	 * this driver) to use it for normal operation, though it is
    849 	 * required to work around bugs in some chip versions.
    850 	 */
    851 	if (sc->sc_type >= WM_T_82544) {
    852 		/* First we have to find the I/O BAR. */
    853 		for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
    854 			if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) ==
    855 			    PCI_MAPREG_TYPE_IO)
    856 				break;
    857 		}
    858 		if (i == PCI_MAPREG_END)
    859 			aprint_error("%s: WARNING: unable to find I/O BAR\n",
    860 			    sc->sc_dev.dv_xname);
    861 		else {
    862 			/*
    863 			 * The i8254x doesn't apparently respond when the
    864 			 * I/O BAR is 0, which looks somewhat like it's not
    865 			 * been configured.
    866 			 */
    867 			preg = pci_conf_read(pc, pa->pa_tag, i);
    868 			if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
    869 				aprint_error("%s: WARNING: I/O BAR at zero.\n",
    870 				    sc->sc_dev.dv_xname);
    871 			} else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
    872 					0, &sc->sc_iot, &sc->sc_ioh,
    873 					NULL, NULL) == 0) {
    874 				sc->sc_flags |= WM_F_IOH_VALID;
    875 			} else {
    876 				aprint_error("%s: WARNING: unable to map "
    877 				    "I/O space\n", sc->sc_dev.dv_xname);
    878 			}
    879 		}
    880 
    881 	}
    882 
    883 	/* Enable bus mastering.  Disable MWI on the i82542 2.0. */
    884 	preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
    885 	preg |= PCI_COMMAND_MASTER_ENABLE;
    886 	if (sc->sc_type < WM_T_82542_2_1)
    887 		preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
    888 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
    889 
    890 	/* Get it out of power save mode, if needed. */
    891 	if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
    892 		preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) &
    893 		    PCI_PMCSR_STATE_MASK;
    894 		if (preg == PCI_PMCSR_STATE_D3) {
    895 			/*
    896 			 * The card has lost all configuration data in
    897 			 * this state, so punt.
    898 			 */
    899 			aprint_error("%s: unable to wake from power state D3\n",
    900 			    sc->sc_dev.dv_xname);
    901 			return;
    902 		}
    903 		if (preg != PCI_PMCSR_STATE_D0) {
    904 			aprint_normal("%s: waking up from power state D%d\n",
    905 			    sc->sc_dev.dv_xname, preg);
    906 			pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR,
    907 			    PCI_PMCSR_STATE_D0);
    908 		}
    909 	}
    910 
    911 	/*
    912 	 * Map and establish our interrupt.
    913 	 */
    914 	if (pci_intr_map(pa, &ih)) {
    915 		aprint_error("%s: unable to map interrupt\n",
    916 		    sc->sc_dev.dv_xname);
    917 		return;
    918 	}
    919 	intrstr = pci_intr_string(pc, ih);
    920 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc);
    921 	if (sc->sc_ih == NULL) {
    922 		aprint_error("%s: unable to establish interrupt",
    923 		    sc->sc_dev.dv_xname);
    924 		if (intrstr != NULL)
    925 			aprint_normal(" at %s", intrstr);
    926 		aprint_normal("\n");
    927 		return;
    928 	}
    929 	aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
    930 
    931 	/*
    932 	 * Determine a few things about the bus we're connected to.
    933 	 */
    934 	if (sc->sc_type < WM_T_82543) {
    935 		/* We don't really know the bus characteristics here. */
    936 		sc->sc_bus_speed = 33;
    937 	} else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
    938 		/*
    939 		 * CSA (Communication Streaming Architecture) is about as fast
    940 		 * a 32-bit 66MHz PCI Bus.
    941 		 */
    942 		sc->sc_flags |= WM_F_CSA;
    943 		sc->sc_bus_speed = 66;
    944 		aprint_verbose("%s: Communication Streaming Architecture\n",
    945 		    sc->sc_dev.dv_xname);
    946 		if (sc->sc_type == WM_T_82547) {
    947 			callout_init(&sc->sc_txfifo_ch);
    948 			callout_setfunc(&sc->sc_txfifo_ch,
    949 					wm_82547_txfifo_stall, sc);
    950 			aprint_verbose("%s: using 82547 Tx FIFO stall "
    951 				       "work-around\n", sc->sc_dev.dv_xname);
    952 		}
    953 	} else if (sc->sc_type >= WM_T_82571) {
    954 		sc->sc_flags |= WM_F_PCIE | WM_F_EEPROM_SEMAPHORE;
    955 		aprint_verbose("%s: PCI-Express bus\n", sc->sc_dev.dv_xname);
    956 	} else {
    957 		reg = CSR_READ(sc, WMREG_STATUS);
    958 		if (reg & STATUS_BUS64)
    959 			sc->sc_flags |= WM_F_BUS64;
    960 		if (sc->sc_type >= WM_T_82544 &&
    961 		    (reg & STATUS_PCIX_MODE) != 0) {
    962 			pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
    963 
    964 			sc->sc_flags |= WM_F_PCIX;
    965 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
    966 					       PCI_CAP_PCIX,
    967 					       &sc->sc_pcix_offset, NULL) == 0)
    968 				aprint_error("%s: unable to find PCIX "
    969 				    "capability\n", sc->sc_dev.dv_xname);
    970 			else if (sc->sc_type != WM_T_82545_3 &&
    971 				 sc->sc_type != WM_T_82546_3) {
    972 				/*
    973 				 * Work around a problem caused by the BIOS
    974 				 * setting the max memory read byte count
    975 				 * incorrectly.
    976 				 */
    977 				pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
    978 				    sc->sc_pcix_offset + PCI_PCIX_CMD);
    979 				pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
    980 				    sc->sc_pcix_offset + PCI_PCIX_STATUS);
    981 
    982 				bytecnt =
    983 				    (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >>
    984 				    PCI_PCIX_CMD_BYTECNT_SHIFT;
    985 				maxb =
    986 				    (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >>
    987 				    PCI_PCIX_STATUS_MAXB_SHIFT;
    988 				if (bytecnt > maxb) {
    989 					aprint_verbose("%s: resetting PCI-X "
    990 					    "MMRBC: %d -> %d\n",
    991 					    sc->sc_dev.dv_xname,
    992 					    512 << bytecnt, 512 << maxb);
    993 					pcix_cmd = (pcix_cmd &
    994 					    ~PCI_PCIX_CMD_BYTECNT_MASK) |
    995 					   (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT);
    996 					pci_conf_write(pa->pa_pc, pa->pa_tag,
    997 					    sc->sc_pcix_offset + PCI_PCIX_CMD,
    998 					    pcix_cmd);
    999 				}
   1000 			}
   1001 		}
   1002 		/*
   1003 		 * The quad port adapter is special; it has a PCIX-PCIX
   1004 		 * bridge on the board, and can run the secondary bus at
   1005 		 * a higher speed.
   1006 		 */
   1007 		if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
   1008 			sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
   1009 								      : 66;
   1010 		} else if (sc->sc_flags & WM_F_PCIX) {
   1011 			switch (reg & STATUS_PCIXSPD_MASK) {
   1012 			case STATUS_PCIXSPD_50_66:
   1013 				sc->sc_bus_speed = 66;
   1014 				break;
   1015 			case STATUS_PCIXSPD_66_100:
   1016 				sc->sc_bus_speed = 100;
   1017 				break;
   1018 			case STATUS_PCIXSPD_100_133:
   1019 				sc->sc_bus_speed = 133;
   1020 				break;
   1021 			default:
   1022 				aprint_error(
   1023 				    "%s: unknown PCIXSPD %d; assuming 66MHz\n",
   1024 				    sc->sc_dev.dv_xname,
   1025 				    reg & STATUS_PCIXSPD_MASK);
   1026 				sc->sc_bus_speed = 66;
   1027 			}
   1028 		} else
   1029 			sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
   1030 		aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname,
   1031 		    (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
   1032 		    (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
   1033 	}
   1034 
   1035 	/*
   1036 	 * Allocate the control data structures, and create and load the
   1037 	 * DMA map for it.
   1038 	 *
   1039 	 * NOTE: All Tx descriptors must be in the same 4G segment of
   1040 	 * memory.  So must Rx descriptors.  We simplify by allocating
   1041 	 * both sets within the same 4G segment.
   1042 	 */
   1043 	WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ?
   1044 	    WM_NTXDESC_82542 : WM_NTXDESC_82544;
   1045 	cdata_size = sc->sc_type < WM_T_82544 ?
   1046 	    sizeof(struct wm_control_data_82542) :
   1047 	    sizeof(struct wm_control_data_82544);
   1048 	if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE,
   1049 				      (bus_size_t) 0x100000000ULL,
   1050 				      &seg, 1, &rseg, 0)) != 0) {
   1051 		aprint_error(
   1052 		    "%s: unable to allocate control data, error = %d\n",
   1053 		    sc->sc_dev.dv_xname, error);
   1054 		goto fail_0;
   1055 	}
   1056 
   1057 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size,
   1058 				    (caddr_t *)&sc->sc_control_data, 0)) != 0) {
   1059 		aprint_error("%s: unable to map control data, error = %d\n",
   1060 		    sc->sc_dev.dv_xname, error);
   1061 		goto fail_1;
   1062 	}
   1063 
   1064 	if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size,
   1065 				       0, 0, &sc->sc_cddmamap)) != 0) {
   1066 		aprint_error("%s: unable to create control data DMA map, "
   1067 		    "error = %d\n", sc->sc_dev.dv_xname, error);
   1068 		goto fail_2;
   1069 	}
   1070 
   1071 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
   1072 				     sc->sc_control_data, cdata_size, NULL,
   1073 				     0)) != 0) {
   1074 		aprint_error(
   1075 		    "%s: unable to load control data DMA map, error = %d\n",
   1076 		    sc->sc_dev.dv_xname, error);
   1077 		goto fail_3;
   1078 	}
   1079 
   1080 
   1081 	/*
   1082 	 * Create the transmit buffer DMA maps.
   1083 	 */
   1084 	WM_TXQUEUELEN(sc) =
   1085 	    (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
   1086 	    WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
   1087 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
   1088 		if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
   1089 					       WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
   1090 					  &sc->sc_txsoft[i].txs_dmamap)) != 0) {
   1091 			aprint_error("%s: unable to create Tx DMA map %d, "
   1092 			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
   1093 			goto fail_4;
   1094 		}
   1095 	}
   1096 
   1097 	/*
   1098 	 * Create the receive buffer DMA maps.
   1099 	 */
   1100 	for (i = 0; i < WM_NRXDESC; i++) {
   1101 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
   1102 					       MCLBYTES, 0, 0,
   1103 					  &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
   1104 			aprint_error("%s: unable to create Rx DMA map %d, "
   1105 			    "error = %d\n", sc->sc_dev.dv_xname, i, error);
   1106 			goto fail_5;
   1107 		}
   1108 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
   1109 	}
   1110 
   1111 	/*
   1112 	 * Reset the chip to a known state.
   1113 	 */
   1114 	wm_reset(sc);
   1115 
   1116 	/*
   1117 	 * Get some information about the EEPROM.
   1118 	 */
   1119 	if (sc->sc_type == WM_T_82573)
   1120  		sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
   1121 	else if (sc->sc_type > WM_T_82544)
   1122 		sc->sc_flags |= WM_F_EEPROM_HANDSHAKE;
   1123 
   1124 	if (sc->sc_type <= WM_T_82544)
   1125 		sc->sc_ee_addrbits = 6;
   1126 	else if (sc->sc_type <= WM_T_82546_3) {
   1127 		reg = CSR_READ(sc, WMREG_EECD);
   1128 		if (reg & EECD_EE_SIZE)
   1129 			sc->sc_ee_addrbits = 8;
   1130 		else
   1131 			sc->sc_ee_addrbits = 6;
   1132 	} else if (sc->sc_type <= WM_T_82547_2) {
   1133 		reg = CSR_READ(sc, WMREG_EECD);
   1134 		if (reg & EECD_EE_TYPE) {
   1135 			sc->sc_flags |= WM_F_EEPROM_SPI;
   1136 			sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
   1137 		} else
   1138 			sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6;
   1139 	} else if ((sc->sc_type == WM_T_82573) &&
   1140 	    (wm_is_onboard_nvm_eeprom(sc) == 0)) {
   1141 		sc->sc_flags |= WM_F_EEPROM_FLASH;
   1142 	} else {
   1143 		/* Assume everything else is SPI. */
   1144 		reg = CSR_READ(sc, WMREG_EECD);
   1145 		sc->sc_flags |= WM_F_EEPROM_SPI;
   1146 		sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
   1147 	}
   1148 
   1149 	/*
   1150 	 * Defer printing the EEPROM type until after verifying the checksum
   1151 	 * This allows the EEPROM type to be printed correctly in the case
   1152 	 * that no EEPROM is attached.
   1153 	 */
   1154 
   1155 
   1156 	/*
   1157 	 * Validate the EEPROM checksum. If the checksum fails, flag this for
   1158 	 * later, so we can fail future reads from the EEPROM.
   1159 	 */
   1160 	if (wm_validate_eeprom_checksum(sc))
   1161 		sc->sc_flags |= WM_F_EEPROM_INVALID;
   1162 
   1163 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   1164 		aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname);
   1165 	else if (sc->sc_flags & WM_F_EEPROM_FLASH) {
   1166 		aprint_verbose("%s: FLASH\n", sc->sc_dev.dv_xname);
   1167 	} else {
   1168 		if (sc->sc_flags & WM_F_EEPROM_SPI)
   1169 			eetype = "SPI";
   1170 		else
   1171 			eetype = "MicroWire";
   1172 		aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n",
   1173 		    sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits,
   1174 		    sc->sc_ee_addrbits, eetype);
   1175 	}
   1176 
   1177 	/*
   1178 	 * Read the Ethernet address from the EEPROM, if not first found
   1179 	 * in device properties.
   1180 	 */
   1181 	ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr");
   1182 	if (ea != NULL) {
   1183 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
   1184 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
   1185 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
   1186 	} else {
   1187 		if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
   1188 		    sizeof(myea) / sizeof(myea[0]), myea)) {
   1189 			aprint_error("%s: unable to read Ethernet address\n",
   1190 			    sc->sc_dev.dv_xname);
   1191 			return;
   1192 		}
   1193 		enaddr[0] = myea[0] & 0xff;
   1194 		enaddr[1] = myea[0] >> 8;
   1195 		enaddr[2] = myea[1] & 0xff;
   1196 		enaddr[3] = myea[1] >> 8;
   1197 		enaddr[4] = myea[2] & 0xff;
   1198 		enaddr[5] = myea[2] >> 8;
   1199 	}
   1200 
   1201 	/*
   1202 	 * Toggle the LSB of the MAC address on the second port
   1203 	 * of the i82546.
   1204 	 */
   1205 	if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) {
   1206 		if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1)
   1207 			enaddr[5] ^= 1;
   1208 	}
   1209 
   1210 	aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
   1211 	    ether_sprintf(enaddr));
   1212 
   1213 	/*
   1214 	 * Read the config info from the EEPROM, and set up various
   1215 	 * bits in the control registers based on their contents.
   1216 	 */
   1217 	pn = prop_dictionary_get(device_properties(&sc->sc_dev),
   1218 				 "i82543-cfg1");
   1219 	if (pn != NULL) {
   1220 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   1221 		cfg1 = (uint16_t) prop_number_integer_value(pn);
   1222 	} else {
   1223 		if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
   1224 			aprint_error("%s: unable to read CFG1\n",
   1225 			    sc->sc_dev.dv_xname);
   1226 			return;
   1227 		}
   1228 	}
   1229 
   1230 	pn = prop_dictionary_get(device_properties(&sc->sc_dev),
   1231 				 "i82543-cfg2");
   1232 	if (pn != NULL) {
   1233 		KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   1234 		cfg2 = (uint16_t) prop_number_integer_value(pn);
   1235 	} else {
   1236 		if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
   1237 			aprint_error("%s: unable to read CFG2\n",
   1238 			    sc->sc_dev.dv_xname);
   1239 			return;
   1240 		}
   1241 	}
   1242 
   1243 	if (sc->sc_type >= WM_T_82544) {
   1244 		pn = prop_dictionary_get(device_properties(&sc->sc_dev),
   1245 					 "i82543-swdpin");
   1246 		if (pn != NULL) {
   1247 			KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   1248 			swdpin = (uint16_t) prop_number_integer_value(pn);
   1249 		} else {
   1250 			if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
   1251 				aprint_error("%s: unable to read SWDPIN\n",
   1252 				    sc->sc_dev.dv_xname);
   1253 				return;
   1254 			}
   1255 		}
   1256 	}
   1257 
   1258 	if (cfg1 & EEPROM_CFG1_ILOS)
   1259 		sc->sc_ctrl |= CTRL_ILOS;
   1260 	if (sc->sc_type >= WM_T_82544) {
   1261 		sc->sc_ctrl |=
   1262 		    ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
   1263 		    CTRL_SWDPIO_SHIFT;
   1264 		sc->sc_ctrl |=
   1265 		    ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
   1266 		    CTRL_SWDPINS_SHIFT;
   1267 	} else {
   1268 		sc->sc_ctrl |=
   1269 		    ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) <<
   1270 		    CTRL_SWDPIO_SHIFT;
   1271 	}
   1272 
   1273 #if 0
   1274 	if (sc->sc_type >= WM_T_82544) {
   1275 		if (cfg1 & EEPROM_CFG1_IPS0)
   1276 			sc->sc_ctrl_ext |= CTRL_EXT_IPS;
   1277 		if (cfg1 & EEPROM_CFG1_IPS1)
   1278 			sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
   1279 		sc->sc_ctrl_ext |=
   1280 		    ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
   1281 		    CTRL_EXT_SWDPIO_SHIFT;
   1282 		sc->sc_ctrl_ext |=
   1283 		    ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
   1284 		    CTRL_EXT_SWDPINS_SHIFT;
   1285 	} else {
   1286 		sc->sc_ctrl_ext |=
   1287 		    ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) <<
   1288 		    CTRL_EXT_SWDPIO_SHIFT;
   1289 	}
   1290 #endif
   1291 
   1292 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   1293 #if 0
   1294 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   1295 #endif
   1296 
   1297 	/*
   1298 	 * Set up some register offsets that are different between
   1299 	 * the i82542 and the i82543 and later chips.
   1300 	 */
   1301 	if (sc->sc_type < WM_T_82543) {
   1302 		sc->sc_rdt_reg = WMREG_OLD_RDT0;
   1303 		sc->sc_tdt_reg = WMREG_OLD_TDT;
   1304 	} else {
   1305 		sc->sc_rdt_reg = WMREG_RDT;
   1306 		sc->sc_tdt_reg = WMREG_TDT;
   1307 	}
   1308 
   1309 	/*
   1310 	 * Determine if we're TBI or GMII mode, and initialize the
   1311 	 * media structures accordingly.
   1312 	 */
   1313 	if (sc->sc_type < WM_T_82543 ||
   1314 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
   1315 		if (wmp->wmp_flags & WMP_F_1000T)
   1316 			aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T "
   1317 			    "product!\n", sc->sc_dev.dv_xname);
   1318 		wm_tbi_mediainit(sc);
   1319 	} else {
   1320 		if (wmp->wmp_flags & WMP_F_1000X)
   1321 			aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X "
   1322 			    "product!\n", sc->sc_dev.dv_xname);
   1323 		wm_gmii_mediainit(sc);
   1324 	}
   1325 
   1326 	ifp = &sc->sc_ethercom.ec_if;
   1327 	strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
   1328 	ifp->if_softc = sc;
   1329 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
   1330 	ifp->if_ioctl = wm_ioctl;
   1331 	ifp->if_start = wm_start;
   1332 	ifp->if_watchdog = wm_watchdog;
   1333 	ifp->if_init = wm_init;
   1334 	ifp->if_stop = wm_stop;
   1335 	IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
   1336 	IFQ_SET_READY(&ifp->if_snd);
   1337 
   1338 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
   1339 
   1340 	/*
   1341 	 * If we're a i82543 or greater, we can support VLANs.
   1342 	 */
   1343 	if (sc->sc_type >= WM_T_82543)
   1344 		sc->sc_ethercom.ec_capabilities |=
   1345 		    ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */;
   1346 
   1347 	/*
   1348 	 * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
   1349 	 * on i82543 and later.
   1350 	 */
   1351 	if (sc->sc_type >= WM_T_82543)
   1352 		ifp->if_capabilities |=
   1353 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
   1354 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
   1355 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
   1356 		    IFCAP_CSUM_TCPv6_Tx |
   1357 		    IFCAP_CSUM_UDPv6_Tx;
   1358 
   1359 	/*
   1360 	 * If we're a i82544 or greater (except i82547), we can do
   1361 	 * TCP segmentation offload.
   1362 	 */
   1363 	if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547)
   1364 		ifp->if_capabilities |= IFCAP_TSOv4;
   1365 
   1366 	/*
   1367 	 * Attach the interface.
   1368 	 */
   1369 	if_attach(ifp);
   1370 	ether_ifattach(ifp, enaddr);
   1371 #if NRND > 0
   1372 	rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
   1373 	    RND_TYPE_NET, 0);
   1374 #endif
   1375 
   1376 #ifdef WM_EVENT_COUNTERS
   1377 	/* Attach event counters. */
   1378 	evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
   1379 	    NULL, sc->sc_dev.dv_xname, "txsstall");
   1380 	evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
   1381 	    NULL, sc->sc_dev.dv_xname, "txdstall");
   1382 	evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC,
   1383 	    NULL, sc->sc_dev.dv_xname, "txfifo_stall");
   1384 	evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR,
   1385 	    NULL, sc->sc_dev.dv_xname, "txdw");
   1386 	evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR,
   1387 	    NULL, sc->sc_dev.dv_xname, "txqe");
   1388 	evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
   1389 	    NULL, sc->sc_dev.dv_xname, "rxintr");
   1390 	evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
   1391 	    NULL, sc->sc_dev.dv_xname, "linkintr");
   1392 
   1393 	evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
   1394 	    NULL, sc->sc_dev.dv_xname, "rxipsum");
   1395 	evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC,
   1396 	    NULL, sc->sc_dev.dv_xname, "rxtusum");
   1397 	evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
   1398 	    NULL, sc->sc_dev.dv_xname, "txipsum");
   1399 	evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC,
   1400 	    NULL, sc->sc_dev.dv_xname, "txtusum");
   1401 	evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC,
   1402 	    NULL, sc->sc_dev.dv_xname, "txtusum6");
   1403 
   1404 	evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC,
   1405 	    NULL, sc->sc_dev.dv_xname, "txtso");
   1406 	evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC,
   1407 	    NULL, sc->sc_dev.dv_xname, "txtsopain");
   1408 
   1409 	for (i = 0; i < WM_NTXSEGS; i++) {
   1410 		sprintf(wm_txseg_evcnt_names[i], "txseg%d", i);
   1411 		evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC,
   1412 		    NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]);
   1413 	}
   1414 
   1415 	evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC,
   1416 	    NULL, sc->sc_dev.dv_xname, "txdrop");
   1417 
   1418 	evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC,
   1419 	    NULL, sc->sc_dev.dv_xname, "tu");
   1420 
   1421 	evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
   1422 	    NULL, sc->sc_dev.dv_xname, "tx_xoff");
   1423 	evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
   1424 	    NULL, sc->sc_dev.dv_xname, "tx_xon");
   1425 	evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
   1426 	    NULL, sc->sc_dev.dv_xname, "rx_xoff");
   1427 	evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
   1428 	    NULL, sc->sc_dev.dv_xname, "rx_xon");
   1429 	evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
   1430 	    NULL, sc->sc_dev.dv_xname, "rx_macctl");
   1431 #endif /* WM_EVENT_COUNTERS */
   1432 
   1433 	/*
   1434 	 * Make sure the interface is shutdown during reboot.
   1435 	 */
   1436 	sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc);
   1437 	if (sc->sc_sdhook == NULL)
   1438 		aprint_error("%s: WARNING: unable to establish shutdown hook\n",
   1439 		    sc->sc_dev.dv_xname);
   1440 	return;
   1441 
   1442 	/*
   1443 	 * Free any resources we've allocated during the failed attach
   1444 	 * attempt.  Do this in reverse order and fall through.
   1445 	 */
   1446  fail_5:
   1447 	for (i = 0; i < WM_NRXDESC; i++) {
   1448 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
   1449 			bus_dmamap_destroy(sc->sc_dmat,
   1450 			    sc->sc_rxsoft[i].rxs_dmamap);
   1451 	}
   1452  fail_4:
   1453 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
   1454 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
   1455 			bus_dmamap_destroy(sc->sc_dmat,
   1456 			    sc->sc_txsoft[i].txs_dmamap);
   1457 	}
   1458 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
   1459  fail_3:
   1460 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
   1461  fail_2:
   1462 	bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
   1463 	    cdata_size);
   1464  fail_1:
   1465 	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
   1466  fail_0:
   1467 	return;
   1468 }
   1469 
   1470 /*
   1471  * wm_shutdown:
   1472  *
   1473  *	Make sure the interface is stopped at reboot time.
   1474  */
   1475 static void
   1476 wm_shutdown(void *arg)
   1477 {
   1478 	struct wm_softc *sc = arg;
   1479 
   1480 	wm_stop(&sc->sc_ethercom.ec_if, 1);
   1481 }
   1482 
   1483 /*
   1484  * wm_tx_offload:
   1485  *
   1486  *	Set up TCP/IP checksumming parameters for the
   1487  *	specified packet.
   1488  */
   1489 static int
   1490 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp,
   1491     uint8_t *fieldsp)
   1492 {
   1493 	struct mbuf *m0 = txs->txs_mbuf;
   1494 	struct livengood_tcpip_ctxdesc *t;
   1495 	uint32_t ipcs, tucs, cmd, cmdlen, seg;
   1496 	struct ether_header *eh;
   1497 	int offset, iphl;
   1498 	uint8_t fields;
   1499 
   1500 	/*
   1501 	 * XXX It would be nice if the mbuf pkthdr had offset
   1502 	 * fields for the protocol headers.
   1503 	 */
   1504 
   1505 	eh = mtod(m0, struct ether_header *);
   1506 	switch (htons(eh->ether_type)) {
   1507 	case ETHERTYPE_IP:
   1508 	case ETHERTYPE_IPV6:
   1509 		offset = ETHER_HDR_LEN;
   1510 		break;
   1511 
   1512 	case ETHERTYPE_VLAN:
   1513 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
   1514 		break;
   1515 
   1516 	default:
   1517 		/*
   1518 		 * Don't support this protocol or encapsulation.
   1519 		 */
   1520 		*fieldsp = 0;
   1521 		*cmdp = 0;
   1522 		return (0);
   1523 	}
   1524 
   1525 	if ((m0->m_pkthdr.csum_flags &
   1526 	    (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) {
   1527 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   1528 	} else {
   1529 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
   1530 	}
   1531 
   1532 	cmd = WTX_CMD_DEXT | WTX_DTYP_D;
   1533 	cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
   1534 	seg = 0;
   1535 	fields = 0;
   1536 
   1537 	if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
   1538 		int hlen = offset + iphl;
   1539 		WM_EVCNT_INCR(&sc->sc_ev_txtso);
   1540 		if (__predict_false(m0->m_len <
   1541 				    (hlen + sizeof(struct tcphdr)))) {
   1542 			/*
   1543 			 * TCP/IP headers are not in the first mbuf; we need
   1544 			 * to do this the slow and painful way.  Let's just
   1545 			 * hope this doesn't happen very often.
   1546 			 */
   1547 			struct ip ip;
   1548 			struct tcphdr th;
   1549 
   1550 			WM_EVCNT_INCR(&sc->sc_ev_txtsopain);
   1551 
   1552 			m_copydata(m0, offset, sizeof(ip), &ip);
   1553 			m_copydata(m0, hlen, sizeof(th), &th);
   1554 
   1555 			ip.ip_len = 0;
   1556 
   1557 			m_copyback(m0, hlen + offsetof(struct ip, ip_len),
   1558 			    sizeof(ip.ip_len), &ip.ip_len);
   1559 
   1560 			th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
   1561 			    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
   1562 
   1563 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
   1564 			    sizeof(th.th_sum), &th.th_sum);
   1565 
   1566 			hlen += th.th_off << 2;
   1567 		} else {
   1568 			/*
   1569 			 * TCP/IP headers are in the first mbuf; we can do
   1570 			 * this the easy way.
   1571 			 */
   1572 			struct ip *ip =
   1573 			    (struct ip *) (mtod(m0, caddr_t) + offset);
   1574 			struct tcphdr *th =
   1575 			    (struct tcphdr *) (mtod(m0, caddr_t) + hlen);
   1576 
   1577 			ip->ip_len = 0;
   1578 			th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
   1579 			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
   1580 
   1581 			hlen += th->th_off << 2;
   1582 		}
   1583 
   1584 		cmd |= WTX_TCPIP_CMD_TSE;
   1585 		cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP |
   1586 		    WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
   1587 		seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
   1588 		    WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
   1589 	}
   1590 
   1591 	/*
   1592 	 * NOTE: Even if we're not using the IP or TCP/UDP checksum
   1593 	 * offload feature, if we load the context descriptor, we
   1594 	 * MUST provide valid values for IPCSS and TUCSS fields.
   1595 	 */
   1596 
   1597 	ipcs = WTX_TCPIP_IPCSS(offset) |
   1598 	    WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
   1599 	    WTX_TCPIP_IPCSE(offset + iphl - 1);
   1600 	if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) {
   1601 		WM_EVCNT_INCR(&sc->sc_ev_txipsum);
   1602 		fields |= WTX_IXSM;
   1603 	}
   1604 
   1605 	offset += iphl;
   1606 
   1607 	if (m0->m_pkthdr.csum_flags &
   1608 	    (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) {
   1609 		WM_EVCNT_INCR(&sc->sc_ev_txtusum);
   1610 		fields |= WTX_TXSM;
   1611 		tucs = WTX_TCPIP_TUCSS(offset) |
   1612 		    WTX_TCPIP_TUCSO(offset +
   1613 		    M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
   1614 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   1615 	} else if ((m0->m_pkthdr.csum_flags &
   1616 	    (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) {
   1617 		WM_EVCNT_INCR(&sc->sc_ev_txtusum6);
   1618 		fields |= WTX_TXSM;
   1619 		tucs = WTX_TCPIP_TUCSS(offset) |
   1620 		    WTX_TCPIP_TUCSO(offset +
   1621 		    M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
   1622 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   1623 	} else {
   1624 		/* Just initialize it to a valid TCP context. */
   1625 		tucs = WTX_TCPIP_TUCSS(offset) |
   1626 		    WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
   1627 		    WTX_TCPIP_TUCSE(0) /* rest of packet */;
   1628 	}
   1629 
   1630 	/* Fill in the context descriptor. */
   1631 	t = (struct livengood_tcpip_ctxdesc *)
   1632 	    &sc->sc_txdescs[sc->sc_txnext];
   1633 	t->tcpip_ipcs = htole32(ipcs);
   1634 	t->tcpip_tucs = htole32(tucs);
   1635 	t->tcpip_cmdlen = htole32(cmdlen);
   1636 	t->tcpip_seg = htole32(seg);
   1637 	WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE);
   1638 
   1639 	sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext);
   1640 	txs->txs_ndesc++;
   1641 
   1642 	*cmdp = cmd;
   1643 	*fieldsp = fields;
   1644 
   1645 	return (0);
   1646 }
   1647 
   1648 static void
   1649 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
   1650 {
   1651 	struct mbuf *m;
   1652 	int i;
   1653 
   1654 	log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname);
   1655 	for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
   1656 		log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
   1657 		    "m_flags = 0x%08x\n", sc->sc_dev.dv_xname,
   1658 		    m->m_data, m->m_len, m->m_flags);
   1659 	log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname,
   1660 	    i, i == 1 ? "" : "s");
   1661 }
   1662 
   1663 /*
   1664  * wm_82547_txfifo_stall:
   1665  *
   1666  *	Callout used to wait for the 82547 Tx FIFO to drain,
   1667  *	reset the FIFO pointers, and restart packet transmission.
   1668  */
   1669 static void
   1670 wm_82547_txfifo_stall(void *arg)
   1671 {
   1672 	struct wm_softc *sc = arg;
   1673 	int s;
   1674 
   1675 	s = splnet();
   1676 
   1677 	if (sc->sc_txfifo_stall) {
   1678 		if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) &&
   1679 		    CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
   1680 		    CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
   1681 			/*
   1682 			 * Packets have drained.  Stop transmitter, reset
   1683 			 * FIFO pointers, restart transmitter, and kick
   1684 			 * the packet queue.
   1685 			 */
   1686 			uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
   1687 			CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
   1688 			CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr);
   1689 			CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr);
   1690 			CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr);
   1691 			CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr);
   1692 			CSR_WRITE(sc, WMREG_TCTL, tctl);
   1693 			CSR_WRITE_FLUSH(sc);
   1694 
   1695 			sc->sc_txfifo_head = 0;
   1696 			sc->sc_txfifo_stall = 0;
   1697 			wm_start(&sc->sc_ethercom.ec_if);
   1698 		} else {
   1699 			/*
   1700 			 * Still waiting for packets to drain; try again in
   1701 			 * another tick.
   1702 			 */
   1703 			callout_schedule(&sc->sc_txfifo_ch, 1);
   1704 		}
   1705 	}
   1706 
   1707 	splx(s);
   1708 }
   1709 
   1710 /*
   1711  * wm_82547_txfifo_bugchk:
   1712  *
   1713  *	Check for bug condition in the 82547 Tx FIFO.  We need to
   1714  *	prevent enqueueing a packet that would wrap around the end
   1715  *	if the Tx FIFO ring buffer, otherwise the chip will croak.
   1716  *
   1717  *	We do this by checking the amount of space before the end
   1718  *	of the Tx FIFO buffer.  If the packet will not fit, we "stall"
   1719  *	the Tx FIFO, wait for all remaining packets to drain, reset
   1720  *	the internal FIFO pointers to the beginning, and restart
   1721  *	transmission on the interface.
   1722  */
   1723 #define	WM_FIFO_HDR		0x10
   1724 #define	WM_82547_PAD_LEN	0x3e0
   1725 static int
   1726 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
   1727 {
   1728 	int space = sc->sc_txfifo_size - sc->sc_txfifo_head;
   1729 	int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
   1730 
   1731 	/* Just return if already stalled. */
   1732 	if (sc->sc_txfifo_stall)
   1733 		return (1);
   1734 
   1735 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   1736 		/* Stall only occurs in half-duplex mode. */
   1737 		goto send_packet;
   1738 	}
   1739 
   1740 	if (len >= WM_82547_PAD_LEN + space) {
   1741 		sc->sc_txfifo_stall = 1;
   1742 		callout_schedule(&sc->sc_txfifo_ch, 1);
   1743 		return (1);
   1744 	}
   1745 
   1746  send_packet:
   1747 	sc->sc_txfifo_head += len;
   1748 	if (sc->sc_txfifo_head >= sc->sc_txfifo_size)
   1749 		sc->sc_txfifo_head -= sc->sc_txfifo_size;
   1750 
   1751 	return (0);
   1752 }
   1753 
   1754 /*
   1755  * wm_start:		[ifnet interface function]
   1756  *
   1757  *	Start packet transmission on the interface.
   1758  */
   1759 static void
   1760 wm_start(struct ifnet *ifp)
   1761 {
   1762 	struct wm_softc *sc = ifp->if_softc;
   1763 	struct mbuf *m0;
   1764 #if 0 /* XXXJRT */
   1765 	struct m_tag *mtag;
   1766 #endif
   1767 	struct wm_txsoft *txs;
   1768 	bus_dmamap_t dmamap;
   1769 	int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
   1770 	bus_addr_t curaddr;
   1771 	bus_size_t seglen, curlen;
   1772 	uint32_t cksumcmd;
   1773 	uint8_t cksumfields;
   1774 
   1775 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
   1776 		return;
   1777 
   1778 	/*
   1779 	 * Remember the previous number of free descriptors.
   1780 	 */
   1781 	ofree = sc->sc_txfree;
   1782 
   1783 	/*
   1784 	 * Loop through the send queue, setting up transmit descriptors
   1785 	 * until we drain the queue, or use up all available transmit
   1786 	 * descriptors.
   1787 	 */
   1788 	for (;;) {
   1789 		/* Grab a packet off the queue. */
   1790 		IFQ_POLL(&ifp->if_snd, m0);
   1791 		if (m0 == NULL)
   1792 			break;
   1793 
   1794 		DPRINTF(WM_DEBUG_TX,
   1795 		    ("%s: TX: have packet to transmit: %p\n",
   1796 		    sc->sc_dev.dv_xname, m0));
   1797 
   1798 		/* Get a work queue entry. */
   1799 		if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) {
   1800 			wm_txintr(sc);
   1801 			if (sc->sc_txsfree == 0) {
   1802 				DPRINTF(WM_DEBUG_TX,
   1803 				    ("%s: TX: no free job descriptors\n",
   1804 					sc->sc_dev.dv_xname));
   1805 				WM_EVCNT_INCR(&sc->sc_ev_txsstall);
   1806 				break;
   1807 			}
   1808 		}
   1809 
   1810 		txs = &sc->sc_txsoft[sc->sc_txsnext];
   1811 		dmamap = txs->txs_dmamap;
   1812 
   1813 		use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
   1814 
   1815 		/*
   1816 		 * So says the Linux driver:
   1817 		 * The controller does a simple calculation to make sure
   1818 		 * there is enough room in the FIFO before initiating the
   1819 		 * DMA for each buffer.  The calc is:
   1820 		 *	4 = ceil(buffer len / MSS)
   1821 		 * To make sure we don't overrun the FIFO, adjust the max
   1822 		 * buffer len if the MSS drops.
   1823 		 */
   1824 		dmamap->dm_maxsegsz =
   1825 		    (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
   1826 		    ? m0->m_pkthdr.segsz << 2
   1827 		    : WTX_MAX_LEN;
   1828 
   1829 		/*
   1830 		 * Load the DMA map.  If this fails, the packet either
   1831 		 * didn't fit in the allotted number of segments, or we
   1832 		 * were short on resources.  For the too-many-segments
   1833 		 * case, we simply report an error and drop the packet,
   1834 		 * since we can't sanely copy a jumbo packet to a single
   1835 		 * buffer.
   1836 		 */
   1837 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
   1838 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT);
   1839 		if (error) {
   1840 			if (error == EFBIG) {
   1841 				WM_EVCNT_INCR(&sc->sc_ev_txdrop);
   1842 				log(LOG_ERR, "%s: Tx packet consumes too many "
   1843 				    "DMA segments, dropping...\n",
   1844 				    sc->sc_dev.dv_xname);
   1845 				IFQ_DEQUEUE(&ifp->if_snd, m0);
   1846 				wm_dump_mbuf_chain(sc, m0);
   1847 				m_freem(m0);
   1848 				continue;
   1849 			}
   1850 			/*
   1851 			 * Short on resources, just stop for now.
   1852 			 */
   1853 			DPRINTF(WM_DEBUG_TX,
   1854 			    ("%s: TX: dmamap load failed: %d\n",
   1855 			    sc->sc_dev.dv_xname, error));
   1856 			break;
   1857 		}
   1858 
   1859 		segs_needed = dmamap->dm_nsegs;
   1860 		if (use_tso) {
   1861 			/* For sentinel descriptor; see below. */
   1862 			segs_needed++;
   1863 		}
   1864 
   1865 		/*
   1866 		 * Ensure we have enough descriptors free to describe
   1867 		 * the packet.  Note, we always reserve one descriptor
   1868 		 * at the end of the ring due to the semantics of the
   1869 		 * TDT register, plus one more in the event we need
   1870 		 * to load offload context.
   1871 		 */
   1872 		if (segs_needed > sc->sc_txfree - 2) {
   1873 			/*
   1874 			 * Not enough free descriptors to transmit this
   1875 			 * packet.  We haven't committed anything yet,
   1876 			 * so just unload the DMA map, put the packet
   1877 			 * pack on the queue, and punt.  Notify the upper
   1878 			 * layer that there are no more slots left.
   1879 			 */
   1880 			DPRINTF(WM_DEBUG_TX,
   1881 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
   1882 			    sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed,
   1883 			    sc->sc_txfree - 1));
   1884 			ifp->if_flags |= IFF_OACTIVE;
   1885 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   1886 			WM_EVCNT_INCR(&sc->sc_ev_txdstall);
   1887 			break;
   1888 		}
   1889 
   1890 		/*
   1891 		 * Check for 82547 Tx FIFO bug.  We need to do this
   1892 		 * once we know we can transmit the packet, since we
   1893 		 * do some internal FIFO space accounting here.
   1894 		 */
   1895 		if (sc->sc_type == WM_T_82547 &&
   1896 		    wm_82547_txfifo_bugchk(sc, m0)) {
   1897 			DPRINTF(WM_DEBUG_TX,
   1898 			    ("%s: TX: 82547 Tx FIFO bug detected\n",
   1899 			    sc->sc_dev.dv_xname));
   1900 			ifp->if_flags |= IFF_OACTIVE;
   1901 			bus_dmamap_unload(sc->sc_dmat, dmamap);
   1902 			WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall);
   1903 			break;
   1904 		}
   1905 
   1906 		IFQ_DEQUEUE(&ifp->if_snd, m0);
   1907 
   1908 		/*
   1909 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
   1910 		 */
   1911 
   1912 		DPRINTF(WM_DEBUG_TX,
   1913 		    ("%s: TX: packet has %d (%d) DMA segments\n",
   1914 		    sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed));
   1915 
   1916 		WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]);
   1917 
   1918 		/*
   1919 		 * Store a pointer to the packet so that we can free it
   1920 		 * later.
   1921 		 *
   1922 		 * Initially, we consider the number of descriptors the
   1923 		 * packet uses the number of DMA segments.  This may be
   1924 		 * incremented by 1 if we do checksum offload (a descriptor
   1925 		 * is used to set the checksum context).
   1926 		 */
   1927 		txs->txs_mbuf = m0;
   1928 		txs->txs_firstdesc = sc->sc_txnext;
   1929 		txs->txs_ndesc = segs_needed;
   1930 
   1931 		/* Set up offload parameters for this packet. */
   1932 		if (m0->m_pkthdr.csum_flags &
   1933 		    (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
   1934 		    M_CSUM_TCPv6|M_CSUM_UDPv6)) {
   1935 			if (wm_tx_offload(sc, txs, &cksumcmd,
   1936 					  &cksumfields) != 0) {
   1937 				/* Error message already displayed. */
   1938 				bus_dmamap_unload(sc->sc_dmat, dmamap);
   1939 				continue;
   1940 			}
   1941 		} else {
   1942 			cksumcmd = 0;
   1943 			cksumfields = 0;
   1944 		}
   1945 
   1946 		cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
   1947 
   1948 		/* Sync the DMA map. */
   1949 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
   1950 		    BUS_DMASYNC_PREWRITE);
   1951 
   1952 		/*
   1953 		 * Initialize the transmit descriptor.
   1954 		 */
   1955 		for (nexttx = sc->sc_txnext, seg = 0;
   1956 		     seg < dmamap->dm_nsegs; seg++) {
   1957 			for (seglen = dmamap->dm_segs[seg].ds_len,
   1958 			     curaddr = dmamap->dm_segs[seg].ds_addr;
   1959 			     seglen != 0;
   1960 			     curaddr += curlen, seglen -= curlen,
   1961 			     nexttx = WM_NEXTTX(sc, nexttx)) {
   1962 				curlen = seglen;
   1963 
   1964 				/*
   1965 				 * So says the Linux driver:
   1966 				 * Work around for premature descriptor
   1967 				 * write-backs in TSO mode.  Append a
   1968 				 * 4-byte sentinel descriptor.
   1969 				 */
   1970 				if (use_tso &&
   1971 				    seg == dmamap->dm_nsegs - 1 &&
   1972 				    curlen > 8)
   1973 					curlen -= 4;
   1974 
   1975 				wm_set_dma_addr(
   1976 				    &sc->sc_txdescs[nexttx].wtx_addr,
   1977 				    curaddr);
   1978 				sc->sc_txdescs[nexttx].wtx_cmdlen =
   1979 				    htole32(cksumcmd | curlen);
   1980 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_status =
   1981 				    0;
   1982 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_options =
   1983 				    cksumfields;
   1984 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0;
   1985 				lasttx = nexttx;
   1986 
   1987 				DPRINTF(WM_DEBUG_TX,
   1988 				    ("%s: TX: desc %d: low 0x%08lx, "
   1989 				     "len 0x%04x\n",
   1990 				    sc->sc_dev.dv_xname, nexttx,
   1991 				    curaddr & 0xffffffffUL, (unsigned)curlen));
   1992 			}
   1993 		}
   1994 
   1995 		KASSERT(lasttx != -1);
   1996 
   1997 		/*
   1998 		 * Set up the command byte on the last descriptor of
   1999 		 * the packet.  If we're in the interrupt delay window,
   2000 		 * delay the interrupt.
   2001 		 */
   2002 		sc->sc_txdescs[lasttx].wtx_cmdlen |=
   2003 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
   2004 
   2005 #if 0 /* XXXJRT */
   2006 		/*
   2007 		 * If VLANs are enabled and the packet has a VLAN tag, set
   2008 		 * up the descriptor to encapsulate the packet for us.
   2009 		 *
   2010 		 * This is only valid on the last descriptor of the packet.
   2011 		 */
   2012 		if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
   2013 			sc->sc_txdescs[lasttx].wtx_cmdlen |=
   2014 			    htole32(WTX_CMD_VLE);
   2015 			sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan
   2016 			    = htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
   2017 		}
   2018 #endif /* XXXJRT */
   2019 
   2020 		txs->txs_lastdesc = lasttx;
   2021 
   2022 		DPRINTF(WM_DEBUG_TX,
   2023 		    ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname,
   2024 		    lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen)));
   2025 
   2026 		/* Sync the descriptors we're using. */
   2027 		WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc,
   2028 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   2029 
   2030 		/* Give the packet to the chip. */
   2031 		CSR_WRITE(sc, sc->sc_tdt_reg, nexttx);
   2032 
   2033 		DPRINTF(WM_DEBUG_TX,
   2034 		    ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx));
   2035 
   2036 		DPRINTF(WM_DEBUG_TX,
   2037 		    ("%s: TX: finished transmitting packet, job %d\n",
   2038 		    sc->sc_dev.dv_xname, sc->sc_txsnext));
   2039 
   2040 		/* Advance the tx pointer. */
   2041 		sc->sc_txfree -= txs->txs_ndesc;
   2042 		sc->sc_txnext = nexttx;
   2043 
   2044 		sc->sc_txsfree--;
   2045 		sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext);
   2046 
   2047 #if NBPFILTER > 0
   2048 		/* Pass the packet to any BPF listeners. */
   2049 		if (ifp->if_bpf)
   2050 			bpf_mtap(ifp->if_bpf, m0);
   2051 #endif /* NBPFILTER > 0 */
   2052 	}
   2053 
   2054 	if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) {
   2055 		/* No more slots; notify upper layer. */
   2056 		ifp->if_flags |= IFF_OACTIVE;
   2057 	}
   2058 
   2059 	if (sc->sc_txfree != ofree) {
   2060 		/* Set a watchdog timer in case the chip flakes out. */
   2061 		ifp->if_timer = 5;
   2062 	}
   2063 }
   2064 
   2065 /*
   2066  * wm_watchdog:		[ifnet interface function]
   2067  *
   2068  *	Watchdog timer handler.
   2069  */
   2070 static void
   2071 wm_watchdog(struct ifnet *ifp)
   2072 {
   2073 	struct wm_softc *sc = ifp->if_softc;
   2074 
   2075 	/*
   2076 	 * Since we're using delayed interrupts, sweep up
   2077 	 * before we report an error.
   2078 	 */
   2079 	wm_txintr(sc);
   2080 
   2081 	if (sc->sc_txfree != WM_NTXDESC(sc)) {
   2082 		log(LOG_ERR,
   2083 		    "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
   2084 		    sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree,
   2085 		    sc->sc_txnext);
   2086 		ifp->if_oerrors++;
   2087 
   2088 		/* Reset the interface. */
   2089 		(void) wm_init(ifp);
   2090 	}
   2091 
   2092 	/* Try to get more packets going. */
   2093 	wm_start(ifp);
   2094 }
   2095 
   2096 /*
   2097  * wm_ioctl:		[ifnet interface function]
   2098  *
   2099  *	Handle control requests from the operator.
   2100  */
   2101 static int
   2102 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
   2103 {
   2104 	struct wm_softc *sc = ifp->if_softc;
   2105 	struct ifreq *ifr = (struct ifreq *) data;
   2106 	int s, error;
   2107 
   2108 	s = splnet();
   2109 
   2110 	switch (cmd) {
   2111 	case SIOCSIFMEDIA:
   2112 	case SIOCGIFMEDIA:
   2113 		/* Flow control requires full-duplex mode. */
   2114 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
   2115 		    (ifr->ifr_media & IFM_FDX) == 0)
   2116 			ifr->ifr_media &= ~IFM_ETH_FMASK;
   2117 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
   2118 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
   2119 				/* We can do both TXPAUSE and RXPAUSE. */
   2120 				ifr->ifr_media |=
   2121 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
   2122 			}
   2123 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
   2124 		}
   2125 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
   2126 		break;
   2127 	default:
   2128 		error = ether_ioctl(ifp, cmd, data);
   2129 		if (error == ENETRESET) {
   2130 			/*
   2131 			 * Multicast list has changed; set the hardware filter
   2132 			 * accordingly.
   2133 			 */
   2134 			if (ifp->if_flags & IFF_RUNNING)
   2135 				wm_set_filter(sc);
   2136 			error = 0;
   2137 		}
   2138 		break;
   2139 	}
   2140 
   2141 	/* Try to get more packets going. */
   2142 	wm_start(ifp);
   2143 
   2144 	splx(s);
   2145 	return (error);
   2146 }
   2147 
   2148 /*
   2149  * wm_intr:
   2150  *
   2151  *	Interrupt service routine.
   2152  */
   2153 static int
   2154 wm_intr(void *arg)
   2155 {
   2156 	struct wm_softc *sc = arg;
   2157 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2158 	uint32_t icr;
   2159 	int handled = 0;
   2160 
   2161 	while (1 /* CONSTCOND */) {
   2162 		icr = CSR_READ(sc, WMREG_ICR);
   2163 		if ((icr & sc->sc_icr) == 0)
   2164 			break;
   2165 
   2166 #if 0 /*NRND > 0*/
   2167 		if (RND_ENABLED(&sc->rnd_source))
   2168 			rnd_add_uint32(&sc->rnd_source, icr);
   2169 #endif
   2170 
   2171 		handled = 1;
   2172 
   2173 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   2174 		if (icr & (ICR_RXDMT0|ICR_RXT0)) {
   2175 			DPRINTF(WM_DEBUG_RX,
   2176 			    ("%s: RX: got Rx intr 0x%08x\n",
   2177 			    sc->sc_dev.dv_xname,
   2178 			    icr & (ICR_RXDMT0|ICR_RXT0)));
   2179 			WM_EVCNT_INCR(&sc->sc_ev_rxintr);
   2180 		}
   2181 #endif
   2182 		wm_rxintr(sc);
   2183 
   2184 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
   2185 		if (icr & ICR_TXDW) {
   2186 			DPRINTF(WM_DEBUG_TX,
   2187 			    ("%s: TX: got TXDW interrupt\n",
   2188 			    sc->sc_dev.dv_xname));
   2189 			WM_EVCNT_INCR(&sc->sc_ev_txdw);
   2190 		}
   2191 #endif
   2192 		wm_txintr(sc);
   2193 
   2194 		if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) {
   2195 			WM_EVCNT_INCR(&sc->sc_ev_linkintr);
   2196 			wm_linkintr(sc, icr);
   2197 		}
   2198 
   2199 		if (icr & ICR_RXO) {
   2200 			ifp->if_ierrors++;
   2201 #if defined(WM_DEBUG)
   2202 			log(LOG_WARNING, "%s: Receive overrun\n",
   2203 			    sc->sc_dev.dv_xname);
   2204 #endif /* defined(WM_DEBUG) */
   2205 		}
   2206 	}
   2207 
   2208 	if (handled) {
   2209 		/* Try to get more packets going. */
   2210 		wm_start(ifp);
   2211 	}
   2212 
   2213 	return (handled);
   2214 }
   2215 
   2216 /*
   2217  * wm_txintr:
   2218  *
   2219  *	Helper; handle transmit interrupts.
   2220  */
   2221 static void
   2222 wm_txintr(struct wm_softc *sc)
   2223 {
   2224 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2225 	struct wm_txsoft *txs;
   2226 	uint8_t status;
   2227 	int i;
   2228 
   2229 	ifp->if_flags &= ~IFF_OACTIVE;
   2230 
   2231 	/*
   2232 	 * Go through the Tx list and free mbufs for those
   2233 	 * frames which have been transmitted.
   2234 	 */
   2235 	for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc);
   2236 	     i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) {
   2237 		txs = &sc->sc_txsoft[i];
   2238 
   2239 		DPRINTF(WM_DEBUG_TX,
   2240 		    ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i));
   2241 
   2242 		WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc,
   2243 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   2244 
   2245 		status =
   2246 		    sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status;
   2247 		if ((status & WTX_ST_DD) == 0) {
   2248 			WM_CDTXSYNC(sc, txs->txs_lastdesc, 1,
   2249 			    BUS_DMASYNC_PREREAD);
   2250 			break;
   2251 		}
   2252 
   2253 		DPRINTF(WM_DEBUG_TX,
   2254 		    ("%s: TX: job %d done: descs %d..%d\n",
   2255 		    sc->sc_dev.dv_xname, i, txs->txs_firstdesc,
   2256 		    txs->txs_lastdesc));
   2257 
   2258 		/*
   2259 		 * XXX We should probably be using the statistics
   2260 		 * XXX registers, but I don't know if they exist
   2261 		 * XXX on chips before the i82544.
   2262 		 */
   2263 
   2264 #ifdef WM_EVENT_COUNTERS
   2265 		if (status & WTX_ST_TU)
   2266 			WM_EVCNT_INCR(&sc->sc_ev_tu);
   2267 #endif /* WM_EVENT_COUNTERS */
   2268 
   2269 		if (status & (WTX_ST_EC|WTX_ST_LC)) {
   2270 			ifp->if_oerrors++;
   2271 			if (status & WTX_ST_LC)
   2272 				log(LOG_WARNING, "%s: late collision\n",
   2273 				    sc->sc_dev.dv_xname);
   2274 			else if (status & WTX_ST_EC) {
   2275 				ifp->if_collisions += 16;
   2276 				log(LOG_WARNING, "%s: excessive collisions\n",
   2277 				    sc->sc_dev.dv_xname);
   2278 			}
   2279 		} else
   2280 			ifp->if_opackets++;
   2281 
   2282 		sc->sc_txfree += txs->txs_ndesc;
   2283 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
   2284 		    0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
   2285 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   2286 		m_freem(txs->txs_mbuf);
   2287 		txs->txs_mbuf = NULL;
   2288 	}
   2289 
   2290 	/* Update the dirty transmit buffer pointer. */
   2291 	sc->sc_txsdirty = i;
   2292 	DPRINTF(WM_DEBUG_TX,
   2293 	    ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i));
   2294 
   2295 	/*
   2296 	 * If there are no more pending transmissions, cancel the watchdog
   2297 	 * timer.
   2298 	 */
   2299 	if (sc->sc_txsfree == WM_TXQUEUELEN(sc))
   2300 		ifp->if_timer = 0;
   2301 }
   2302 
   2303 /*
   2304  * wm_rxintr:
   2305  *
   2306  *	Helper; handle receive interrupts.
   2307  */
   2308 static void
   2309 wm_rxintr(struct wm_softc *sc)
   2310 {
   2311 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2312 	struct wm_rxsoft *rxs;
   2313 	struct mbuf *m;
   2314 	int i, len;
   2315 	uint8_t status, errors;
   2316 
   2317 	for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
   2318 		rxs = &sc->sc_rxsoft[i];
   2319 
   2320 		DPRINTF(WM_DEBUG_RX,
   2321 		    ("%s: RX: checking descriptor %d\n",
   2322 		    sc->sc_dev.dv_xname, i));
   2323 
   2324 		WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   2325 
   2326 		status = sc->sc_rxdescs[i].wrx_status;
   2327 		errors = sc->sc_rxdescs[i].wrx_errors;
   2328 		len = le16toh(sc->sc_rxdescs[i].wrx_len);
   2329 
   2330 		if ((status & WRX_ST_DD) == 0) {
   2331 			/*
   2332 			 * We have processed all of the receive descriptors.
   2333 			 */
   2334 			WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
   2335 			break;
   2336 		}
   2337 
   2338 		if (__predict_false(sc->sc_rxdiscard)) {
   2339 			DPRINTF(WM_DEBUG_RX,
   2340 			    ("%s: RX: discarding contents of descriptor %d\n",
   2341 			    sc->sc_dev.dv_xname, i));
   2342 			WM_INIT_RXDESC(sc, i);
   2343 			if (status & WRX_ST_EOP) {
   2344 				/* Reset our state. */
   2345 				DPRINTF(WM_DEBUG_RX,
   2346 				    ("%s: RX: resetting rxdiscard -> 0\n",
   2347 				    sc->sc_dev.dv_xname));
   2348 				sc->sc_rxdiscard = 0;
   2349 			}
   2350 			continue;
   2351 		}
   2352 
   2353 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   2354 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   2355 
   2356 		m = rxs->rxs_mbuf;
   2357 
   2358 		/*
   2359 		 * Add a new receive buffer to the ring.
   2360 		 */
   2361 		if (wm_add_rxbuf(sc, i) != 0) {
   2362 			/*
   2363 			 * Failed, throw away what we've done so
   2364 			 * far, and discard the rest of the packet.
   2365 			 */
   2366 			ifp->if_ierrors++;
   2367 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   2368 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   2369 			WM_INIT_RXDESC(sc, i);
   2370 			if ((status & WRX_ST_EOP) == 0)
   2371 				sc->sc_rxdiscard = 1;
   2372 			if (sc->sc_rxhead != NULL)
   2373 				m_freem(sc->sc_rxhead);
   2374 			WM_RXCHAIN_RESET(sc);
   2375 			DPRINTF(WM_DEBUG_RX,
   2376 			    ("%s: RX: Rx buffer allocation failed, "
   2377 			    "dropping packet%s\n", sc->sc_dev.dv_xname,
   2378 			    sc->sc_rxdiscard ? " (discard)" : ""));
   2379 			continue;
   2380 		}
   2381 
   2382 		WM_RXCHAIN_LINK(sc, m);
   2383 
   2384 		m->m_len = len;
   2385 
   2386 		DPRINTF(WM_DEBUG_RX,
   2387 		    ("%s: RX: buffer at %p len %d\n",
   2388 		    sc->sc_dev.dv_xname, m->m_data, len));
   2389 
   2390 		/*
   2391 		 * If this is not the end of the packet, keep
   2392 		 * looking.
   2393 		 */
   2394 		if ((status & WRX_ST_EOP) == 0) {
   2395 			sc->sc_rxlen += len;
   2396 			DPRINTF(WM_DEBUG_RX,
   2397 			    ("%s: RX: not yet EOP, rxlen -> %d\n",
   2398 			    sc->sc_dev.dv_xname, sc->sc_rxlen));
   2399 			continue;
   2400 		}
   2401 
   2402 		/*
   2403 		 * Okay, we have the entire packet now.  The chip is
   2404 		 * configured to include the FCS (not all chips can
   2405 		 * be configured to strip it), so we need to trim it.
   2406 		 */
   2407 		m->m_len -= ETHER_CRC_LEN;
   2408 
   2409 		*sc->sc_rxtailp = NULL;
   2410 		len = m->m_len + sc->sc_rxlen;
   2411 		m = sc->sc_rxhead;
   2412 
   2413 		WM_RXCHAIN_RESET(sc);
   2414 
   2415 		DPRINTF(WM_DEBUG_RX,
   2416 		    ("%s: RX: have entire packet, len -> %d\n",
   2417 		    sc->sc_dev.dv_xname, len));
   2418 
   2419 		/*
   2420 		 * If an error occurred, update stats and drop the packet.
   2421 		 */
   2422 		if (errors &
   2423 		     (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
   2424 			ifp->if_ierrors++;
   2425 			if (errors & WRX_ER_SE)
   2426 				log(LOG_WARNING, "%s: symbol error\n",
   2427 				    sc->sc_dev.dv_xname);
   2428 			else if (errors & WRX_ER_SEQ)
   2429 				log(LOG_WARNING, "%s: receive sequence error\n",
   2430 				    sc->sc_dev.dv_xname);
   2431 			else if (errors & WRX_ER_CE)
   2432 				log(LOG_WARNING, "%s: CRC error\n",
   2433 				    sc->sc_dev.dv_xname);
   2434 			m_freem(m);
   2435 			continue;
   2436 		}
   2437 
   2438 		/*
   2439 		 * No errors.  Receive the packet.
   2440 		 */
   2441 		m->m_pkthdr.rcvif = ifp;
   2442 		m->m_pkthdr.len = len;
   2443 
   2444 #if 0 /* XXXJRT */
   2445 		/*
   2446 		 * If VLANs are enabled, VLAN packets have been unwrapped
   2447 		 * for us.  Associate the tag with the packet.
   2448 		 */
   2449 		if ((status & WRX_ST_VP) != 0) {
   2450 			VLAN_INPUT_TAG(ifp, m,
   2451 			    le16toh(sc->sc_rxdescs[i].wrx_special,
   2452 			    continue);
   2453 		}
   2454 #endif /* XXXJRT */
   2455 
   2456 		/*
   2457 		 * Set up checksum info for this packet.
   2458 		 */
   2459 		if ((status & WRX_ST_IXSM) == 0) {
   2460 			if (status & WRX_ST_IPCS) {
   2461 				WM_EVCNT_INCR(&sc->sc_ev_rxipsum);
   2462 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
   2463 				if (errors & WRX_ER_IPE)
   2464 					m->m_pkthdr.csum_flags |=
   2465 					    M_CSUM_IPv4_BAD;
   2466 			}
   2467 			if (status & WRX_ST_TCPCS) {
   2468 				/*
   2469 				 * Note: we don't know if this was TCP or UDP,
   2470 				 * so we just set both bits, and expect the
   2471 				 * upper layers to deal.
   2472 				 */
   2473 				WM_EVCNT_INCR(&sc->sc_ev_rxtusum);
   2474 				m->m_pkthdr.csum_flags |=
   2475 				    M_CSUM_TCPv4|M_CSUM_UDPv4;
   2476 				if (errors & WRX_ER_TCPE)
   2477 					m->m_pkthdr.csum_flags |=
   2478 					    M_CSUM_TCP_UDP_BAD;
   2479 			}
   2480 		}
   2481 
   2482 		ifp->if_ipackets++;
   2483 
   2484 #if NBPFILTER > 0
   2485 		/* Pass this up to any BPF listeners. */
   2486 		if (ifp->if_bpf)
   2487 			bpf_mtap(ifp->if_bpf, m);
   2488 #endif /* NBPFILTER > 0 */
   2489 
   2490 		/* Pass it on. */
   2491 		(*ifp->if_input)(ifp, m);
   2492 	}
   2493 
   2494 	/* Update the receive pointer. */
   2495 	sc->sc_rxptr = i;
   2496 
   2497 	DPRINTF(WM_DEBUG_RX,
   2498 	    ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i));
   2499 }
   2500 
   2501 /*
   2502  * wm_linkintr:
   2503  *
   2504  *	Helper; handle link interrupts.
   2505  */
   2506 static void
   2507 wm_linkintr(struct wm_softc *sc, uint32_t icr)
   2508 {
   2509 	uint32_t status;
   2510 
   2511 	/*
   2512 	 * If we get a link status interrupt on a 1000BASE-T
   2513 	 * device, just fall into the normal MII tick path.
   2514 	 */
   2515 	if (sc->sc_flags & WM_F_HAS_MII) {
   2516 		if (icr & ICR_LSC) {
   2517 			DPRINTF(WM_DEBUG_LINK,
   2518 			    ("%s: LINK: LSC -> mii_tick\n",
   2519 			    sc->sc_dev.dv_xname));
   2520 			mii_tick(&sc->sc_mii);
   2521 		} else if (icr & ICR_RXSEQ) {
   2522 			DPRINTF(WM_DEBUG_LINK,
   2523 			    ("%s: LINK Receive sequence error\n",
   2524 			    sc->sc_dev.dv_xname));
   2525 		}
   2526 		return;
   2527 	}
   2528 
   2529 	/*
   2530 	 * If we are now receiving /C/, check for link again in
   2531 	 * a couple of link clock ticks.
   2532 	 */
   2533 	if (icr & ICR_RXCFG) {
   2534 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n",
   2535 		    sc->sc_dev.dv_xname));
   2536 		sc->sc_tbi_anstate = 2;
   2537 	}
   2538 
   2539 	if (icr & ICR_LSC) {
   2540 		status = CSR_READ(sc, WMREG_STATUS);
   2541 		if (status & STATUS_LU) {
   2542 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
   2543 			    sc->sc_dev.dv_xname,
   2544 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   2545 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   2546 			sc->sc_fcrtl &= ~FCRTL_XONE;
   2547 			if (status & STATUS_FD)
   2548 				sc->sc_tctl |=
   2549 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   2550 			else
   2551 				sc->sc_tctl |=
   2552 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   2553 			if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
   2554 				sc->sc_fcrtl |= FCRTL_XONE;
   2555 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   2556 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   2557 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   2558 				      sc->sc_fcrtl);
   2559 			sc->sc_tbi_linkup = 1;
   2560 		} else {
   2561 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
   2562 			    sc->sc_dev.dv_xname));
   2563 			sc->sc_tbi_linkup = 0;
   2564 		}
   2565 		sc->sc_tbi_anstate = 2;
   2566 		wm_tbi_set_linkled(sc);
   2567 	} else if (icr & ICR_RXSEQ) {
   2568 		DPRINTF(WM_DEBUG_LINK,
   2569 		    ("%s: LINK: Receive sequence error\n",
   2570 		    sc->sc_dev.dv_xname));
   2571 	}
   2572 }
   2573 
   2574 /*
   2575  * wm_tick:
   2576  *
   2577  *	One second timer, used to check link status, sweep up
   2578  *	completed transmit jobs, etc.
   2579  */
   2580 static void
   2581 wm_tick(void *arg)
   2582 {
   2583 	struct wm_softc *sc = arg;
   2584 	int s;
   2585 
   2586 	s = splnet();
   2587 
   2588 	if (sc->sc_type >= WM_T_82542_2_1) {
   2589 		WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
   2590 		WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
   2591 		WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
   2592 		WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
   2593 		WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
   2594 	}
   2595 
   2596 	if (sc->sc_flags & WM_F_HAS_MII)
   2597 		mii_tick(&sc->sc_mii);
   2598 	else
   2599 		wm_tbi_check_link(sc);
   2600 
   2601 	splx(s);
   2602 
   2603 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   2604 }
   2605 
   2606 /*
   2607  * wm_reset:
   2608  *
   2609  *	Reset the i82542 chip.
   2610  */
   2611 static void
   2612 wm_reset(struct wm_softc *sc)
   2613 {
   2614 	int i;
   2615 
   2616 	/*
   2617 	 * Allocate on-chip memory according to the MTU size.
   2618 	 * The Packet Buffer Allocation register must be written
   2619 	 * before the chip is reset.
   2620 	 */
   2621 	if (sc->sc_type < WM_T_82547) {
   2622 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   2623 		    PBA_40K : PBA_48K;
   2624 	} else {
   2625 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
   2626 		    PBA_22K : PBA_30K;
   2627 		sc->sc_txfifo_head = 0;
   2628 		sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
   2629 		sc->sc_txfifo_size =
   2630 		    (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
   2631 		sc->sc_txfifo_stall = 0;
   2632 	}
   2633 	CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
   2634 
   2635 	switch (sc->sc_type) {
   2636 	case WM_T_82544:
   2637 	case WM_T_82540:
   2638 	case WM_T_82545:
   2639 	case WM_T_82546:
   2640 	case WM_T_82541:
   2641 	case WM_T_82541_2:
   2642 		/*
   2643 		 * On some chipsets, a reset through a memory-mapped write
   2644 		 * cycle can cause the chip to reset before completing the
   2645 		 * write cycle.  This causes major headache that can be
   2646 		 * avoided by issuing the reset via indirect register writes
   2647 		 * through I/O space.
   2648 		 *
   2649 		 * So, if we successfully mapped the I/O BAR at attach time,
   2650 		 * use that.  Otherwise, try our luck with a memory-mapped
   2651 		 * reset.
   2652 		 */
   2653 		if (sc->sc_flags & WM_F_IOH_VALID)
   2654 			wm_io_write(sc, WMREG_CTRL, CTRL_RST);
   2655 		else
   2656 			CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
   2657 		break;
   2658 
   2659 	case WM_T_82545_3:
   2660 	case WM_T_82546_3:
   2661 		/* Use the shadow control register on these chips. */
   2662 		CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
   2663 		break;
   2664 
   2665 	default:
   2666 		/* Everything else can safely use the documented method. */
   2667 		CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
   2668 		break;
   2669 	}
   2670 	delay(10000);
   2671 
   2672 	for (i = 0; i < 1000; i++) {
   2673 		if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0)
   2674 			return;
   2675 		delay(20);
   2676 	}
   2677 
   2678 	if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
   2679 		log(LOG_ERR, "%s: reset failed to complete\n",
   2680 		    sc->sc_dev.dv_xname);
   2681 }
   2682 
   2683 /*
   2684  * wm_init:		[ifnet interface function]
   2685  *
   2686  *	Initialize the interface.  Must be called at splnet().
   2687  */
   2688 static int
   2689 wm_init(struct ifnet *ifp)
   2690 {
   2691 	struct wm_softc *sc = ifp->if_softc;
   2692 	struct wm_rxsoft *rxs;
   2693 	int i, error = 0;
   2694 	uint32_t reg;
   2695 
   2696 	/*
   2697 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
   2698 	 * There is a small but measurable benefit to avoiding the adjusment
   2699 	 * of the descriptor so that the headers are aligned, for normal mtu,
   2700 	 * on such platforms.  One possibility is that the DMA itself is
   2701 	 * slightly more efficient if the front of the entire packet (instead
   2702 	 * of the front of the headers) is aligned.
   2703 	 *
   2704 	 * Note we must always set align_tweak to 0 if we are using
   2705 	 * jumbo frames.
   2706 	 */
   2707 #ifdef __NO_STRICT_ALIGNMENT
   2708 	sc->sc_align_tweak = 0;
   2709 #else
   2710 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
   2711 		sc->sc_align_tweak = 0;
   2712 	else
   2713 		sc->sc_align_tweak = 2;
   2714 #endif /* __NO_STRICT_ALIGNMENT */
   2715 
   2716 	/* Cancel any pending I/O. */
   2717 	wm_stop(ifp, 0);
   2718 
   2719 	/* Reset the chip to a known state. */
   2720 	wm_reset(sc);
   2721 
   2722 	/* Initialize the transmit descriptor ring. */
   2723 	memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc));
   2724 	WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc),
   2725 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   2726 	sc->sc_txfree = WM_NTXDESC(sc);
   2727 	sc->sc_txnext = 0;
   2728 
   2729 	if (sc->sc_type < WM_T_82543) {
   2730 		CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0));
   2731 		CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0));
   2732 		CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc));
   2733 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
   2734 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
   2735 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
   2736 	} else {
   2737 		CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0));
   2738 		CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0));
   2739 		CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc));
   2740 		CSR_WRITE(sc, WMREG_TDH, 0);
   2741 		CSR_WRITE(sc, WMREG_TDT, 0);
   2742 		CSR_WRITE(sc, WMREG_TIDV, 64);
   2743 		CSR_WRITE(sc, WMREG_TADV, 128);
   2744 
   2745 		CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
   2746 		    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
   2747 		CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
   2748 		    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
   2749 	}
   2750 	CSR_WRITE(sc, WMREG_TQSA_LO, 0);
   2751 	CSR_WRITE(sc, WMREG_TQSA_HI, 0);
   2752 
   2753 	/* Initialize the transmit job descriptors. */
   2754 	for (i = 0; i < WM_TXQUEUELEN(sc); i++)
   2755 		sc->sc_txsoft[i].txs_mbuf = NULL;
   2756 	sc->sc_txsfree = WM_TXQUEUELEN(sc);
   2757 	sc->sc_txsnext = 0;
   2758 	sc->sc_txsdirty = 0;
   2759 
   2760 	/*
   2761 	 * Initialize the receive descriptor and receive job
   2762 	 * descriptor rings.
   2763 	 */
   2764 	if (sc->sc_type < WM_T_82543) {
   2765 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0));
   2766 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0));
   2767 		CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs));
   2768 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
   2769 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
   2770 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
   2771 
   2772 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
   2773 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
   2774 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
   2775 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
   2776 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
   2777 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
   2778 	} else {
   2779 		CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0));
   2780 		CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0));
   2781 		CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs));
   2782 		CSR_WRITE(sc, WMREG_RDH, 0);
   2783 		CSR_WRITE(sc, WMREG_RDT, 0);
   2784 		CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD);
   2785 		CSR_WRITE(sc, WMREG_RADV, 128);
   2786 	}
   2787 	for (i = 0; i < WM_NRXDESC; i++) {
   2788 		rxs = &sc->sc_rxsoft[i];
   2789 		if (rxs->rxs_mbuf == NULL) {
   2790 			if ((error = wm_add_rxbuf(sc, i)) != 0) {
   2791 				log(LOG_ERR, "%s: unable to allocate or map rx "
   2792 				    "buffer %d, error = %d\n",
   2793 				    sc->sc_dev.dv_xname, i, error);
   2794 				/*
   2795 				 * XXX Should attempt to run with fewer receive
   2796 				 * XXX buffers instead of just failing.
   2797 				 */
   2798 				wm_rxdrain(sc);
   2799 				goto out;
   2800 			}
   2801 		} else
   2802 			WM_INIT_RXDESC(sc, i);
   2803 	}
   2804 	sc->sc_rxptr = 0;
   2805 	sc->sc_rxdiscard = 0;
   2806 	WM_RXCHAIN_RESET(sc);
   2807 
   2808 	/*
   2809 	 * Clear out the VLAN table -- we don't use it (yet).
   2810 	 */
   2811 	CSR_WRITE(sc, WMREG_VET, 0);
   2812 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
   2813 		CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
   2814 
   2815 	/*
   2816 	 * Set up flow-control parameters.
   2817 	 *
   2818 	 * XXX Values could probably stand some tuning.
   2819 	 */
   2820 	CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
   2821 	CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
   2822 	CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
   2823 
   2824 	sc->sc_fcrtl = FCRTL_DFLT;
   2825 	if (sc->sc_type < WM_T_82543) {
   2826 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
   2827 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
   2828 	} else {
   2829 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
   2830 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
   2831 	}
   2832 	CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
   2833 
   2834 #if 0 /* XXXJRT */
   2835 	/* Deal with VLAN enables. */
   2836 	if (VLAN_ATTACHED(&sc->sc_ethercom))
   2837 		sc->sc_ctrl |= CTRL_VME;
   2838 	else
   2839 #endif /* XXXJRT */
   2840 		sc->sc_ctrl &= ~CTRL_VME;
   2841 
   2842 	/* Write the control registers. */
   2843 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   2844 #if 0
   2845 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
   2846 #endif
   2847 
   2848 	/*
   2849 	 * Set up checksum offload parameters.
   2850 	 */
   2851 	reg = CSR_READ(sc, WMREG_RXCSUM);
   2852 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
   2853 		reg |= RXCSUM_IPOFL;
   2854 	else
   2855 		reg &= ~RXCSUM_IPOFL;
   2856 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
   2857 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
   2858 	else {
   2859 		reg &= ~RXCSUM_TUOFL;
   2860 		if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0)
   2861 			reg &= ~RXCSUM_IPOFL;
   2862 	}
   2863 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
   2864 
   2865 	/*
   2866 	 * Set up the interrupt registers.
   2867 	 */
   2868 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   2869 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
   2870 	    ICR_RXO | ICR_RXT0;
   2871 	if ((sc->sc_flags & WM_F_HAS_MII) == 0)
   2872 		sc->sc_icr |= ICR_RXCFG;
   2873 	CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
   2874 
   2875 	/* Set up the inter-packet gap. */
   2876 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
   2877 
   2878 	if (sc->sc_type >= WM_T_82543) {
   2879 		/* Set up the interrupt throttling register (units of 256ns) */
   2880 		sc->sc_itr = 1000000000 / (7000 * 256);
   2881 		CSR_WRITE(sc, WMREG_ITR, sc->sc_itr);
   2882 	}
   2883 
   2884 #if 0 /* XXXJRT */
   2885 	/* Set the VLAN ethernetype. */
   2886 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
   2887 #endif
   2888 
   2889 	/*
   2890 	 * Set up the transmit control register; we start out with
   2891 	 * a collision distance suitable for FDX, but update it whe
   2892 	 * we resolve the media type.
   2893 	 */
   2894 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
   2895 	    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   2896 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   2897 
   2898 	/* Set the media. */
   2899 	(void) (*sc->sc_mii.mii_media.ifm_change)(ifp);
   2900 
   2901 	/*
   2902 	 * Set up the receive control register; we actually program
   2903 	 * the register when we set the receive filter.  Use multicast
   2904 	 * address offset type 0.
   2905 	 *
   2906 	 * Only the i82544 has the ability to strip the incoming
   2907 	 * CRC, so we don't enable that feature.
   2908 	 */
   2909 	sc->sc_mchash_type = 0;
   2910 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE |
   2911 	    RCTL_DPF | RCTL_MO(sc->sc_mchash_type);
   2912 
   2913 	if(MCLBYTES == 2048) {
   2914 		sc->sc_rctl |= RCTL_2k;
   2915 	} else {
   2916 		if(sc->sc_type >= WM_T_82543) {
   2917 			switch(MCLBYTES) {
   2918 			case 4096:
   2919 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
   2920 				break;
   2921 			case 8192:
   2922 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
   2923 				break;
   2924 			case 16384:
   2925 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
   2926 				break;
   2927 			default:
   2928 				panic("wm_init: MCLBYTES %d unsupported",
   2929 				    MCLBYTES);
   2930 				break;
   2931 			}
   2932 		} else panic("wm_init: i82542 requires MCLBYTES = 2048");
   2933 	}
   2934 
   2935 	/* Set the receive filter. */
   2936 	wm_set_filter(sc);
   2937 
   2938 	/* Start the one second link check clock. */
   2939 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
   2940 
   2941 	/* ...all done! */
   2942 	ifp->if_flags |= IFF_RUNNING;
   2943 	ifp->if_flags &= ~IFF_OACTIVE;
   2944 
   2945  out:
   2946 	if (error)
   2947 		log(LOG_ERR, "%s: interface not running\n",
   2948 		    sc->sc_dev.dv_xname);
   2949 	return (error);
   2950 }
   2951 
   2952 /*
   2953  * wm_rxdrain:
   2954  *
   2955  *	Drain the receive queue.
   2956  */
   2957 static void
   2958 wm_rxdrain(struct wm_softc *sc)
   2959 {
   2960 	struct wm_rxsoft *rxs;
   2961 	int i;
   2962 
   2963 	for (i = 0; i < WM_NRXDESC; i++) {
   2964 		rxs = &sc->sc_rxsoft[i];
   2965 		if (rxs->rxs_mbuf != NULL) {
   2966 			bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   2967 			m_freem(rxs->rxs_mbuf);
   2968 			rxs->rxs_mbuf = NULL;
   2969 		}
   2970 	}
   2971 }
   2972 
   2973 /*
   2974  * wm_stop:		[ifnet interface function]
   2975  *
   2976  *	Stop transmission on the interface.
   2977  */
   2978 static void
   2979 wm_stop(struct ifnet *ifp, int disable)
   2980 {
   2981 	struct wm_softc *sc = ifp->if_softc;
   2982 	struct wm_txsoft *txs;
   2983 	int i;
   2984 
   2985 	/* Stop the one second clock. */
   2986 	callout_stop(&sc->sc_tick_ch);
   2987 
   2988 	/* Stop the 82547 Tx FIFO stall check timer. */
   2989 	if (sc->sc_type == WM_T_82547)
   2990 		callout_stop(&sc->sc_txfifo_ch);
   2991 
   2992 	if (sc->sc_flags & WM_F_HAS_MII) {
   2993 		/* Down the MII. */
   2994 		mii_down(&sc->sc_mii);
   2995 	}
   2996 
   2997 	/* Stop the transmit and receive processes. */
   2998 	CSR_WRITE(sc, WMREG_TCTL, 0);
   2999 	CSR_WRITE(sc, WMREG_RCTL, 0);
   3000 
   3001 	/*
   3002 	 * Clear the interrupt mask to ensure the device cannot assert its
   3003 	 * interrupt line.
   3004 	 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service
   3005 	 * any currently pending or shared interrupt.
   3006 	 */
   3007 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
   3008 	sc->sc_icr = 0;
   3009 
   3010 	/* Release any queued transmit buffers. */
   3011 	for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
   3012 		txs = &sc->sc_txsoft[i];
   3013 		if (txs->txs_mbuf != NULL) {
   3014 			bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
   3015 			m_freem(txs->txs_mbuf);
   3016 			txs->txs_mbuf = NULL;
   3017 		}
   3018 	}
   3019 
   3020 	if (disable)
   3021 		wm_rxdrain(sc);
   3022 
   3023 	/* Mark the interface as down and cancel the watchdog timer. */
   3024 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
   3025 	ifp->if_timer = 0;
   3026 }
   3027 
   3028 /*
   3029  * wm_acquire_eeprom:
   3030  *
   3031  *	Perform the EEPROM handshake required on some chips.
   3032  */
   3033 static int
   3034 wm_acquire_eeprom(struct wm_softc *sc)
   3035 {
   3036 	uint32_t reg;
   3037 	int x;
   3038 
   3039 	/* always success */
   3040 	if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0)
   3041 		return 0;
   3042 
   3043 	if (wm_get_eeprom_semaphore(sc))
   3044 		return 1;
   3045 
   3046 	if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE)  {
   3047 		reg = CSR_READ(sc, WMREG_EECD);
   3048 
   3049 		/* Request EEPROM access. */
   3050 		reg |= EECD_EE_REQ;
   3051 		CSR_WRITE(sc, WMREG_EECD, reg);
   3052 
   3053 		/* ..and wait for it to be granted. */
   3054 		for (x = 0; x < 1000; x++) {
   3055 			reg = CSR_READ(sc, WMREG_EECD);
   3056 			if (reg & EECD_EE_GNT)
   3057 				break;
   3058 			delay(5);
   3059 		}
   3060 		if ((reg & EECD_EE_GNT) == 0) {
   3061 			aprint_error("%s: could not acquire EEPROM GNT\n",
   3062 			    sc->sc_dev.dv_xname);
   3063 			reg &= ~EECD_EE_REQ;
   3064 			CSR_WRITE(sc, WMREG_EECD, reg);
   3065 			wm_put_eeprom_semaphore(sc);
   3066 			return (1);
   3067 		}
   3068 	}
   3069 
   3070 	return (0);
   3071 }
   3072 
   3073 /*
   3074  * wm_release_eeprom:
   3075  *
   3076  *	Release the EEPROM mutex.
   3077  */
   3078 static void
   3079 wm_release_eeprom(struct wm_softc *sc)
   3080 {
   3081 	uint32_t reg;
   3082 
   3083 	/* always success */
   3084 	if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0)
   3085 		return;
   3086 
   3087 	if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) {
   3088 		reg = CSR_READ(sc, WMREG_EECD);
   3089 		reg &= ~EECD_EE_REQ;
   3090 		CSR_WRITE(sc, WMREG_EECD, reg);
   3091 	}
   3092 
   3093 	wm_put_eeprom_semaphore(sc);
   3094 }
   3095 
   3096 /*
   3097  * wm_eeprom_sendbits:
   3098  *
   3099  *	Send a series of bits to the EEPROM.
   3100  */
   3101 static void
   3102 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
   3103 {
   3104 	uint32_t reg;
   3105 	int x;
   3106 
   3107 	reg = CSR_READ(sc, WMREG_EECD);
   3108 
   3109 	for (x = nbits; x > 0; x--) {
   3110 		if (bits & (1U << (x - 1)))
   3111 			reg |= EECD_DI;
   3112 		else
   3113 			reg &= ~EECD_DI;
   3114 		CSR_WRITE(sc, WMREG_EECD, reg);
   3115 		delay(2);
   3116 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   3117 		delay(2);
   3118 		CSR_WRITE(sc, WMREG_EECD, reg);
   3119 		delay(2);
   3120 	}
   3121 }
   3122 
   3123 /*
   3124  * wm_eeprom_recvbits:
   3125  *
   3126  *	Receive a series of bits from the EEPROM.
   3127  */
   3128 static void
   3129 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
   3130 {
   3131 	uint32_t reg, val;
   3132 	int x;
   3133 
   3134 	reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
   3135 
   3136 	val = 0;
   3137 	for (x = nbits; x > 0; x--) {
   3138 		CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
   3139 		delay(2);
   3140 		if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
   3141 			val |= (1U << (x - 1));
   3142 		CSR_WRITE(sc, WMREG_EECD, reg);
   3143 		delay(2);
   3144 	}
   3145 	*valp = val;
   3146 }
   3147 
   3148 /*
   3149  * wm_read_eeprom_uwire:
   3150  *
   3151  *	Read a word from the EEPROM using the MicroWire protocol.
   3152  */
   3153 static int
   3154 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   3155 {
   3156 	uint32_t reg, val;
   3157 	int i;
   3158 
   3159 	for (i = 0; i < wordcnt; i++) {
   3160 		/* Clear SK and DI. */
   3161 		reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
   3162 		CSR_WRITE(sc, WMREG_EECD, reg);
   3163 
   3164 		/* Set CHIP SELECT. */
   3165 		reg |= EECD_CS;
   3166 		CSR_WRITE(sc, WMREG_EECD, reg);
   3167 		delay(2);
   3168 
   3169 		/* Shift in the READ command. */
   3170 		wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
   3171 
   3172 		/* Shift in address. */
   3173 		wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);
   3174 
   3175 		/* Shift out the data. */
   3176 		wm_eeprom_recvbits(sc, &val, 16);
   3177 		data[i] = val & 0xffff;
   3178 
   3179 		/* Clear CHIP SELECT. */
   3180 		reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
   3181 		CSR_WRITE(sc, WMREG_EECD, reg);
   3182 		delay(2);
   3183 	}
   3184 
   3185 	return (0);
   3186 }
   3187 
   3188 /*
   3189  * wm_spi_eeprom_ready:
   3190  *
   3191  *	Wait for a SPI EEPROM to be ready for commands.
   3192  */
   3193 static int
   3194 wm_spi_eeprom_ready(struct wm_softc *sc)
   3195 {
   3196 	uint32_t val;
   3197 	int usec;
   3198 
   3199 	for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) {
   3200 		wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8);
   3201 		wm_eeprom_recvbits(sc, &val, 8);
   3202 		if ((val & SPI_SR_RDY) == 0)
   3203 			break;
   3204 	}
   3205 	if (usec >= SPI_MAX_RETRIES) {
   3206 		aprint_error("%s: EEPROM failed to become ready\n",
   3207 		    sc->sc_dev.dv_xname);
   3208 		return (1);
   3209 	}
   3210 	return (0);
   3211 }
   3212 
   3213 /*
   3214  * wm_read_eeprom_spi:
   3215  *
   3216  *	Read a work from the EEPROM using the SPI protocol.
   3217  */
   3218 static int
   3219 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   3220 {
   3221 	uint32_t reg, val;
   3222 	int i;
   3223 	uint8_t opc;
   3224 
   3225 	/* Clear SK and CS. */
   3226 	reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
   3227 	CSR_WRITE(sc, WMREG_EECD, reg);
   3228 	delay(2);
   3229 
   3230 	if (wm_spi_eeprom_ready(sc))
   3231 		return (1);
   3232 
   3233 	/* Toggle CS to flush commands. */
   3234 	CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
   3235 	delay(2);
   3236 	CSR_WRITE(sc, WMREG_EECD, reg);
   3237 	delay(2);
   3238 
   3239 	opc = SPI_OPC_READ;
   3240 	if (sc->sc_ee_addrbits == 8 && word >= 128)
   3241 		opc |= SPI_OPC_A8;
   3242 
   3243 	wm_eeprom_sendbits(sc, opc, 8);
   3244 	wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits);
   3245 
   3246 	for (i = 0; i < wordcnt; i++) {
   3247 		wm_eeprom_recvbits(sc, &val, 16);
   3248 		data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
   3249 	}
   3250 
   3251 	/* Raise CS and clear SK. */
   3252 	reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
   3253 	CSR_WRITE(sc, WMREG_EECD, reg);
   3254 	delay(2);
   3255 
   3256 	return (0);
   3257 }
   3258 
   3259 #define EEPROM_CHECKSUM		0xBABA
   3260 #define EEPROM_SIZE		0x0040
   3261 
   3262 /*
   3263  * wm_validate_eeprom_checksum
   3264  *
   3265  * The checksum is defined as the sum of the first 64 (16 bit) words.
   3266  */
   3267 static int
   3268 wm_validate_eeprom_checksum(struct wm_softc *sc)
   3269 {
   3270 	uint16_t checksum;
   3271 	uint16_t eeprom_data;
   3272 	int i;
   3273 
   3274 	checksum = 0;
   3275 
   3276 	for (i = 0; i < EEPROM_SIZE; i++) {
   3277 		if(wm_read_eeprom(sc, i, 1, &eeprom_data))
   3278 			return 1;
   3279 		checksum += eeprom_data;
   3280 	}
   3281 
   3282 	if (checksum != (uint16_t) EEPROM_CHECKSUM)
   3283 		return 1;
   3284 
   3285 	return 0;
   3286 }
   3287 
   3288 /*
   3289  * wm_read_eeprom:
   3290  *
   3291  *	Read data from the serial EEPROM.
   3292  */
   3293 static int
   3294 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
   3295 {
   3296 	int rv;
   3297 
   3298 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
   3299 		return 1;
   3300 
   3301 	if (wm_acquire_eeprom(sc))
   3302 		return 1;
   3303 
   3304 	if (sc->sc_flags & WM_F_EEPROM_EERDEEWR)
   3305 		rv = wm_read_eeprom_eerd(sc, word, wordcnt, data);
   3306 	else if (sc->sc_flags & WM_F_EEPROM_SPI)
   3307 		rv = wm_read_eeprom_spi(sc, word, wordcnt, data);
   3308 	else
   3309 		rv = wm_read_eeprom_uwire(sc, word, wordcnt, data);
   3310 
   3311 	wm_release_eeprom(sc);
   3312 	return rv;
   3313 }
   3314 
   3315 static int
   3316 wm_read_eeprom_eerd(struct wm_softc *sc, int offset, int wordcnt,
   3317     uint16_t *data)
   3318 {
   3319 	int i, eerd = 0;
   3320 	int error = 0;
   3321 
   3322 	for (i = 0; i < wordcnt; i++) {
   3323 		eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
   3324 
   3325 		CSR_WRITE(sc, WMREG_EERD, eerd);
   3326 		error = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
   3327 		if (error != 0)
   3328 			break;
   3329 
   3330 		data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
   3331 	}
   3332 
   3333 	return error;
   3334 }
   3335 
   3336 static int
   3337 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
   3338 {
   3339 	uint32_t attempts = 100000;
   3340 	uint32_t i, reg = 0;
   3341 	int32_t done = -1;
   3342 
   3343 	for(i = 0; i < attempts; i++) {
   3344 		reg = CSR_READ(sc, rw);
   3345 
   3346 		if(reg & EERD_DONE) {
   3347 			done = 0;
   3348 			break;
   3349 		}
   3350 		delay(5);
   3351 	}
   3352 
   3353 	return done;
   3354 }
   3355 
   3356 /*
   3357  * wm_add_rxbuf:
   3358  *
   3359  *	Add a receive buffer to the indiciated descriptor.
   3360  */
   3361 static int
   3362 wm_add_rxbuf(struct wm_softc *sc, int idx)
   3363 {
   3364 	struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx];
   3365 	struct mbuf *m;
   3366 	int error;
   3367 
   3368 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   3369 	if (m == NULL)
   3370 		return (ENOBUFS);
   3371 
   3372 	MCLGET(m, M_DONTWAIT);
   3373 	if ((m->m_flags & M_EXT) == 0) {
   3374 		m_freem(m);
   3375 		return (ENOBUFS);
   3376 	}
   3377 
   3378 	if (rxs->rxs_mbuf != NULL)
   3379 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
   3380 
   3381 	rxs->rxs_mbuf = m;
   3382 
   3383 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
   3384 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
   3385 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
   3386 	if (error) {
   3387 		/* XXX XXX XXX */
   3388 		printf("%s: unable to load rx DMA map %d, error = %d\n",
   3389 		    sc->sc_dev.dv_xname, idx, error);
   3390 		panic("wm_add_rxbuf");
   3391 	}
   3392 
   3393 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
   3394 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   3395 
   3396 	WM_INIT_RXDESC(sc, idx);
   3397 
   3398 	return (0);
   3399 }
   3400 
   3401 /*
   3402  * wm_set_ral:
   3403  *
   3404  *	Set an entery in the receive address list.
   3405  */
   3406 static void
   3407 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
   3408 {
   3409 	uint32_t ral_lo, ral_hi;
   3410 
   3411 	if (enaddr != NULL) {
   3412 		ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
   3413 		    (enaddr[3] << 24);
   3414 		ral_hi = enaddr[4] | (enaddr[5] << 8);
   3415 		ral_hi |= RAL_AV;
   3416 	} else {
   3417 		ral_lo = 0;
   3418 		ral_hi = 0;
   3419 	}
   3420 
   3421 	if (sc->sc_type >= WM_T_82544) {
   3422 		CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),
   3423 		    ral_lo);
   3424 		CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),
   3425 		    ral_hi);
   3426 	} else {
   3427 		CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo);
   3428 		CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi);
   3429 	}
   3430 }
   3431 
   3432 /*
   3433  * wm_mchash:
   3434  *
   3435  *	Compute the hash of the multicast address for the 4096-bit
   3436  *	multicast filter.
   3437  */
   3438 static uint32_t
   3439 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
   3440 {
   3441 	static const int lo_shift[4] = { 4, 3, 2, 0 };
   3442 	static const int hi_shift[4] = { 4, 5, 6, 8 };
   3443 	uint32_t hash;
   3444 
   3445 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
   3446 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
   3447 
   3448 	return (hash & 0xfff);
   3449 }
   3450 
   3451 /*
   3452  * wm_set_filter:
   3453  *
   3454  *	Set up the receive filter.
   3455  */
   3456 static void
   3457 wm_set_filter(struct wm_softc *sc)
   3458 {
   3459 	struct ethercom *ec = &sc->sc_ethercom;
   3460 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   3461 	struct ether_multi *enm;
   3462 	struct ether_multistep step;
   3463 	bus_addr_t mta_reg;
   3464 	uint32_t hash, reg, bit;
   3465 	int i;
   3466 
   3467 	if (sc->sc_type >= WM_T_82544)
   3468 		mta_reg = WMREG_CORDOVA_MTA;
   3469 	else
   3470 		mta_reg = WMREG_MTA;
   3471 
   3472 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
   3473 
   3474 	if (ifp->if_flags & IFF_BROADCAST)
   3475 		sc->sc_rctl |= RCTL_BAM;
   3476 	if (ifp->if_flags & IFF_PROMISC) {
   3477 		sc->sc_rctl |= RCTL_UPE;
   3478 		goto allmulti;
   3479 	}
   3480 
   3481 	/*
   3482 	 * Set the station address in the first RAL slot, and
   3483 	 * clear the remaining slots.
   3484 	 */
   3485 	wm_set_ral(sc, LLADDR(ifp->if_sadl), 0);
   3486 	for (i = 1; i < WM_RAL_TABSIZE; i++)
   3487 		wm_set_ral(sc, NULL, i);
   3488 
   3489 	/* Clear out the multicast table. */
   3490 	for (i = 0; i < WM_MC_TABSIZE; i++)
   3491 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
   3492 
   3493 	ETHER_FIRST_MULTI(step, ec, enm);
   3494 	while (enm != NULL) {
   3495 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   3496 			/*
   3497 			 * We must listen to a range of multicast addresses.
   3498 			 * For now, just accept all multicasts, rather than
   3499 			 * trying to set only those filter bits needed to match
   3500 			 * the range.  (At this time, the only use of address
   3501 			 * ranges is for IP multicast routing, for which the
   3502 			 * range is big enough to require all bits set.)
   3503 			 */
   3504 			goto allmulti;
   3505 		}
   3506 
   3507 		hash = wm_mchash(sc, enm->enm_addrlo);
   3508 
   3509 		reg = (hash >> 5) & 0x7f;
   3510 		bit = hash & 0x1f;
   3511 
   3512 		hash = CSR_READ(sc, mta_reg + (reg << 2));
   3513 		hash |= 1U << bit;
   3514 
   3515 		/* XXX Hardware bug?? */
   3516 		if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
   3517 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
   3518 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   3519 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
   3520 		} else
   3521 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
   3522 
   3523 		ETHER_NEXT_MULTI(step, enm);
   3524 	}
   3525 
   3526 	ifp->if_flags &= ~IFF_ALLMULTI;
   3527 	goto setit;
   3528 
   3529  allmulti:
   3530 	ifp->if_flags |= IFF_ALLMULTI;
   3531 	sc->sc_rctl |= RCTL_MPE;
   3532 
   3533  setit:
   3534 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
   3535 }
   3536 
   3537 /*
   3538  * wm_tbi_mediainit:
   3539  *
   3540  *	Initialize media for use on 1000BASE-X devices.
   3541  */
   3542 static void
   3543 wm_tbi_mediainit(struct wm_softc *sc)
   3544 {
   3545 	const char *sep = "";
   3546 
   3547 	if (sc->sc_type < WM_T_82543)
   3548 		sc->sc_tipg = TIPG_WM_DFLT;
   3549 	else
   3550 		sc->sc_tipg = TIPG_LG_DFLT;
   3551 
   3552 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange,
   3553 	    wm_tbi_mediastatus);
   3554 
   3555 	/*
   3556 	 * SWD Pins:
   3557 	 *
   3558 	 *	0 = Link LED (output)
   3559 	 *	1 = Loss Of Signal (input)
   3560 	 */
   3561 	sc->sc_ctrl |= CTRL_SWDPIO(0);
   3562 	sc->sc_ctrl &= ~CTRL_SWDPIO(1);
   3563 
   3564 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3565 
   3566 #define	ADD(ss, mm, dd)							\
   3567 do {									\
   3568 	aprint_normal("%s%s", sep, ss);					\
   3569 	ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL);	\
   3570 	sep = ", ";							\
   3571 } while (/*CONSTCOND*/0)
   3572 
   3573 	aprint_normal("%s: ", sc->sc_dev.dv_xname);
   3574 	ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
   3575 	ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD);
   3576 	ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD);
   3577 	aprint_normal("\n");
   3578 
   3579 #undef ADD
   3580 
   3581 	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
   3582 }
   3583 
   3584 /*
   3585  * wm_tbi_mediastatus:	[ifmedia interface function]
   3586  *
   3587  *	Get the current interface media status on a 1000BASE-X device.
   3588  */
   3589 static void
   3590 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   3591 {
   3592 	struct wm_softc *sc = ifp->if_softc;
   3593 	uint32_t ctrl;
   3594 
   3595 	ifmr->ifm_status = IFM_AVALID;
   3596 	ifmr->ifm_active = IFM_ETHER;
   3597 
   3598 	if (sc->sc_tbi_linkup == 0) {
   3599 		ifmr->ifm_active |= IFM_NONE;
   3600 		return;
   3601 	}
   3602 
   3603 	ifmr->ifm_status |= IFM_ACTIVE;
   3604 	ifmr->ifm_active |= IFM_1000_SX;
   3605 	if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
   3606 		ifmr->ifm_active |= IFM_FDX;
   3607 	ctrl = CSR_READ(sc, WMREG_CTRL);
   3608 	if (ctrl & CTRL_RFCE)
   3609 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE;
   3610 	if (ctrl & CTRL_TFCE)
   3611 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE;
   3612 }
   3613 
   3614 /*
   3615  * wm_tbi_mediachange:	[ifmedia interface function]
   3616  *
   3617  *	Set hardware to newly-selected media on a 1000BASE-X device.
   3618  */
   3619 static int
   3620 wm_tbi_mediachange(struct ifnet *ifp)
   3621 {
   3622 	struct wm_softc *sc = ifp->if_softc;
   3623 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
   3624 	uint32_t status;
   3625 	int i;
   3626 
   3627 	sc->sc_txcw = ife->ifm_data;
   3628 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
   3629 	    (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
   3630 		sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM;
   3631 	sc->sc_txcw |= TXCW_ANE;
   3632 
   3633 	CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
   3634 	delay(10000);
   3635 
   3636 	/* NOTE: CTRL will update TFCE and RFCE automatically. */
   3637 
   3638 	sc->sc_tbi_anstate = 0;
   3639 
   3640 	if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) {
   3641 		/* Have signal; wait for the link to come up. */
   3642 		for (i = 0; i < 50; i++) {
   3643 			delay(10000);
   3644 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
   3645 				break;
   3646 		}
   3647 
   3648 		status = CSR_READ(sc, WMREG_STATUS);
   3649 		if (status & STATUS_LU) {
   3650 			/* Link is up. */
   3651 			DPRINTF(WM_DEBUG_LINK,
   3652 			    ("%s: LINK: set media -> link up %s\n",
   3653 			    sc->sc_dev.dv_xname,
   3654 			    (status & STATUS_FD) ? "FDX" : "HDX"));
   3655 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   3656 			sc->sc_fcrtl &= ~FCRTL_XONE;
   3657 			if (status & STATUS_FD)
   3658 				sc->sc_tctl |=
   3659 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   3660 			else
   3661 				sc->sc_tctl |=
   3662 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   3663 			if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
   3664 				sc->sc_fcrtl |= FCRTL_XONE;
   3665 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   3666 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   3667 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
   3668 				      sc->sc_fcrtl);
   3669 			sc->sc_tbi_linkup = 1;
   3670 		} else {
   3671 			/* Link is down. */
   3672 			DPRINTF(WM_DEBUG_LINK,
   3673 			    ("%s: LINK: set media -> link down\n",
   3674 			    sc->sc_dev.dv_xname));
   3675 			sc->sc_tbi_linkup = 0;
   3676 		}
   3677 	} else {
   3678 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
   3679 		    sc->sc_dev.dv_xname));
   3680 		sc->sc_tbi_linkup = 0;
   3681 	}
   3682 
   3683 	wm_tbi_set_linkled(sc);
   3684 
   3685 	return (0);
   3686 }
   3687 
   3688 /*
   3689  * wm_tbi_set_linkled:
   3690  *
   3691  *	Update the link LED on 1000BASE-X devices.
   3692  */
   3693 static void
   3694 wm_tbi_set_linkled(struct wm_softc *sc)
   3695 {
   3696 
   3697 	if (sc->sc_tbi_linkup)
   3698 		sc->sc_ctrl |= CTRL_SWDPIN(0);
   3699 	else
   3700 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
   3701 
   3702 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3703 }
   3704 
   3705 /*
   3706  * wm_tbi_check_link:
   3707  *
   3708  *	Check the link on 1000BASE-X devices.
   3709  */
   3710 static void
   3711 wm_tbi_check_link(struct wm_softc *sc)
   3712 {
   3713 	uint32_t rxcw, ctrl, status;
   3714 
   3715 	if (sc->sc_tbi_anstate == 0)
   3716 		return;
   3717 	else if (sc->sc_tbi_anstate > 1) {
   3718 		DPRINTF(WM_DEBUG_LINK,
   3719 		    ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname,
   3720 		    sc->sc_tbi_anstate));
   3721 		sc->sc_tbi_anstate--;
   3722 		return;
   3723 	}
   3724 
   3725 	sc->sc_tbi_anstate = 0;
   3726 
   3727 	rxcw = CSR_READ(sc, WMREG_RXCW);
   3728 	ctrl = CSR_READ(sc, WMREG_CTRL);
   3729 	status = CSR_READ(sc, WMREG_STATUS);
   3730 
   3731 	if ((status & STATUS_LU) == 0) {
   3732 		DPRINTF(WM_DEBUG_LINK,
   3733 		    ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname));
   3734 		sc->sc_tbi_linkup = 0;
   3735 	} else {
   3736 		DPRINTF(WM_DEBUG_LINK,
   3737 		    ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname,
   3738 		    (status & STATUS_FD) ? "FDX" : "HDX"));
   3739 		sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   3740 		sc->sc_fcrtl &= ~FCRTL_XONE;
   3741 		if (status & STATUS_FD)
   3742 			sc->sc_tctl |=
   3743 			    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   3744 		else
   3745 			sc->sc_tctl |=
   3746 			    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   3747 		if (ctrl & CTRL_TFCE)
   3748 			sc->sc_fcrtl |= FCRTL_XONE;
   3749 		CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   3750 		CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
   3751 			      WMREG_OLD_FCRTL : WMREG_FCRTL,
   3752 			      sc->sc_fcrtl);
   3753 		sc->sc_tbi_linkup = 1;
   3754 	}
   3755 
   3756 	wm_tbi_set_linkled(sc);
   3757 }
   3758 
   3759 /*
   3760  * wm_gmii_reset:
   3761  *
   3762  *	Reset the PHY.
   3763  */
   3764 static void
   3765 wm_gmii_reset(struct wm_softc *sc)
   3766 {
   3767 	uint32_t reg;
   3768 
   3769 	if (sc->sc_type >= WM_T_82544) {
   3770 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
   3771 		delay(20000);
   3772 
   3773 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3774 		delay(20000);
   3775 	} else {
   3776 		/* The PHY reset pin is active-low. */
   3777 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
   3778 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
   3779 		    CTRL_EXT_SWDPIN(4));
   3780 		reg |= CTRL_EXT_SWDPIO(4);
   3781 
   3782 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   3783 		delay(10);
   3784 
   3785 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
   3786 		delay(10);
   3787 
   3788 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
   3789 		delay(10);
   3790 #if 0
   3791 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
   3792 #endif
   3793 	}
   3794 }
   3795 
   3796 /*
   3797  * wm_gmii_mediainit:
   3798  *
   3799  *	Initialize media for use on 1000BASE-T devices.
   3800  */
   3801 static void
   3802 wm_gmii_mediainit(struct wm_softc *sc)
   3803 {
   3804 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   3805 
   3806 	/* We have MII. */
   3807 	sc->sc_flags |= WM_F_HAS_MII;
   3808 
   3809 	sc->sc_tipg = TIPG_1000T_DFLT;
   3810 
   3811 	/*
   3812 	 * Let the chip set speed/duplex on its own based on
   3813 	 * signals from the PHY.
   3814 	 */
   3815 	sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE;
   3816 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   3817 
   3818 	/* Initialize our media structures and probe the GMII. */
   3819 	sc->sc_mii.mii_ifp = ifp;
   3820 
   3821 	if (sc->sc_type >= WM_T_82544) {
   3822 		sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
   3823 		sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
   3824 	} else {
   3825 		sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg;
   3826 		sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg;
   3827 	}
   3828 	sc->sc_mii.mii_statchg = wm_gmii_statchg;
   3829 
   3830 	wm_gmii_reset(sc);
   3831 
   3832 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
   3833 	    wm_gmii_mediastatus);
   3834 
   3835 	mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
   3836 	    MII_OFFSET_ANY, MIIF_DOPAUSE);
   3837 	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
   3838 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
   3839 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
   3840 	} else
   3841 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
   3842 }
   3843 
   3844 /*
   3845  * wm_gmii_mediastatus:	[ifmedia interface function]
   3846  *
   3847  *	Get the current interface media status on a 1000BASE-T device.
   3848  */
   3849 static void
   3850 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   3851 {
   3852 	struct wm_softc *sc = ifp->if_softc;
   3853 
   3854 	mii_pollstat(&sc->sc_mii);
   3855 	ifmr->ifm_status = sc->sc_mii.mii_media_status;
   3856 	ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) |
   3857 			   sc->sc_flowflags;
   3858 }
   3859 
   3860 /*
   3861  * wm_gmii_mediachange:	[ifmedia interface function]
   3862  *
   3863  *	Set hardware to newly-selected media on a 1000BASE-T device.
   3864  */
   3865 static int
   3866 wm_gmii_mediachange(struct ifnet *ifp)
   3867 {
   3868 	struct wm_softc *sc = ifp->if_softc;
   3869 
   3870 	if (ifp->if_flags & IFF_UP)
   3871 		mii_mediachg(&sc->sc_mii);
   3872 	return (0);
   3873 }
   3874 
   3875 #define	MDI_IO		CTRL_SWDPIN(2)
   3876 #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
   3877 #define	MDI_CLK		CTRL_SWDPIN(3)
   3878 
   3879 static void
   3880 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
   3881 {
   3882 	uint32_t i, v;
   3883 
   3884 	v = CSR_READ(sc, WMREG_CTRL);
   3885 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   3886 	v |= MDI_DIR | CTRL_SWDPIO(3);
   3887 
   3888 	for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
   3889 		if (data & i)
   3890 			v |= MDI_IO;
   3891 		else
   3892 			v &= ~MDI_IO;
   3893 		CSR_WRITE(sc, WMREG_CTRL, v);
   3894 		delay(10);
   3895 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   3896 		delay(10);
   3897 		CSR_WRITE(sc, WMREG_CTRL, v);
   3898 		delay(10);
   3899 	}
   3900 }
   3901 
   3902 static uint32_t
   3903 i82543_mii_recvbits(struct wm_softc *sc)
   3904 {
   3905 	uint32_t v, i, data = 0;
   3906 
   3907 	v = CSR_READ(sc, WMREG_CTRL);
   3908 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
   3909 	v |= CTRL_SWDPIO(3);
   3910 
   3911 	CSR_WRITE(sc, WMREG_CTRL, v);
   3912 	delay(10);
   3913 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   3914 	delay(10);
   3915 	CSR_WRITE(sc, WMREG_CTRL, v);
   3916 	delay(10);
   3917 
   3918 	for (i = 0; i < 16; i++) {
   3919 		data <<= 1;
   3920 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   3921 		delay(10);
   3922 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
   3923 			data |= 1;
   3924 		CSR_WRITE(sc, WMREG_CTRL, v);
   3925 		delay(10);
   3926 	}
   3927 
   3928 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
   3929 	delay(10);
   3930 	CSR_WRITE(sc, WMREG_CTRL, v);
   3931 	delay(10);
   3932 
   3933 	return (data);
   3934 }
   3935 
   3936 #undef MDI_IO
   3937 #undef MDI_DIR
   3938 #undef MDI_CLK
   3939 
   3940 /*
   3941  * wm_gmii_i82543_readreg:	[mii interface function]
   3942  *
   3943  *	Read a PHY register on the GMII (i82543 version).
   3944  */
   3945 static int
   3946 wm_gmii_i82543_readreg(struct device *self, int phy, int reg)
   3947 {
   3948 	struct wm_softc *sc = (void *) self;
   3949 	int rv;
   3950 
   3951 	i82543_mii_sendbits(sc, 0xffffffffU, 32);
   3952 	i82543_mii_sendbits(sc, reg | (phy << 5) |
   3953 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
   3954 	rv = i82543_mii_recvbits(sc) & 0xffff;
   3955 
   3956 	DPRINTF(WM_DEBUG_GMII,
   3957 	    ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
   3958 	    sc->sc_dev.dv_xname, phy, reg, rv));
   3959 
   3960 	return (rv);
   3961 }
   3962 
   3963 /*
   3964  * wm_gmii_i82543_writereg:	[mii interface function]
   3965  *
   3966  *	Write a PHY register on the GMII (i82543 version).
   3967  */
   3968 static void
   3969 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val)
   3970 {
   3971 	struct wm_softc *sc = (void *) self;
   3972 
   3973 	i82543_mii_sendbits(sc, 0xffffffffU, 32);
   3974 	i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
   3975 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
   3976 	    (MII_COMMAND_START << 30), 32);
   3977 }
   3978 
   3979 /*
   3980  * wm_gmii_i82544_readreg:	[mii interface function]
   3981  *
   3982  *	Read a PHY register on the GMII.
   3983  */
   3984 static int
   3985 wm_gmii_i82544_readreg(struct device *self, int phy, int reg)
   3986 {
   3987 	struct wm_softc *sc = (void *) self;
   3988 	uint32_t mdic = 0;
   3989 	int i, rv;
   3990 
   3991 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
   3992 	    MDIC_REGADD(reg));
   3993 
   3994 	for (i = 0; i < 100; i++) {
   3995 		mdic = CSR_READ(sc, WMREG_MDIC);
   3996 		if (mdic & MDIC_READY)
   3997 			break;
   3998 		delay(10);
   3999 	}
   4000 
   4001 	if ((mdic & MDIC_READY) == 0) {
   4002 		log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
   4003 		    sc->sc_dev.dv_xname, phy, reg);
   4004 		rv = 0;
   4005 	} else if (mdic & MDIC_E) {
   4006 #if 0 /* This is normal if no PHY is present. */
   4007 		log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
   4008 		    sc->sc_dev.dv_xname, phy, reg);
   4009 #endif
   4010 		rv = 0;
   4011 	} else {
   4012 		rv = MDIC_DATA(mdic);
   4013 		if (rv == 0xffff)
   4014 			rv = 0;
   4015 	}
   4016 
   4017 	return (rv);
   4018 }
   4019 
   4020 /*
   4021  * wm_gmii_i82544_writereg:	[mii interface function]
   4022  *
   4023  *	Write a PHY register on the GMII.
   4024  */
   4025 static void
   4026 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val)
   4027 {
   4028 	struct wm_softc *sc = (void *) self;
   4029 	uint32_t mdic = 0;
   4030 	int i;
   4031 
   4032 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
   4033 	    MDIC_REGADD(reg) | MDIC_DATA(val));
   4034 
   4035 	for (i = 0; i < 100; i++) {
   4036 		mdic = CSR_READ(sc, WMREG_MDIC);
   4037 		if (mdic & MDIC_READY)
   4038 			break;
   4039 		delay(10);
   4040 	}
   4041 
   4042 	if ((mdic & MDIC_READY) == 0)
   4043 		log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n",
   4044 		    sc->sc_dev.dv_xname, phy, reg);
   4045 	else if (mdic & MDIC_E)
   4046 		log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n",
   4047 		    sc->sc_dev.dv_xname, phy, reg);
   4048 }
   4049 
   4050 /*
   4051  * wm_gmii_statchg:	[mii interface function]
   4052  *
   4053  *	Callback from MII layer when media changes.
   4054  */
   4055 static void
   4056 wm_gmii_statchg(struct device *self)
   4057 {
   4058 	struct wm_softc *sc = (void *) self;
   4059 	struct mii_data *mii = &sc->sc_mii;
   4060 
   4061 	sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
   4062 	sc->sc_tctl &= ~TCTL_COLD(0x3ff);
   4063 	sc->sc_fcrtl &= ~FCRTL_XONE;
   4064 
   4065 	/*
   4066 	 * Get flow control negotiation result.
   4067 	 */
   4068 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
   4069 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
   4070 		sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
   4071 		mii->mii_media_active &= ~IFM_ETH_FMASK;
   4072 	}
   4073 
   4074 	if (sc->sc_flowflags & IFM_FLOW) {
   4075 		if (sc->sc_flowflags & IFM_ETH_TXPAUSE) {
   4076 			sc->sc_ctrl |= CTRL_TFCE;
   4077 			sc->sc_fcrtl |= FCRTL_XONE;
   4078 		}
   4079 		if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
   4080 			sc->sc_ctrl |= CTRL_RFCE;
   4081 	}
   4082 
   4083 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
   4084 		DPRINTF(WM_DEBUG_LINK,
   4085 		    ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname));
   4086 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
   4087 	} else  {
   4088 		DPRINTF(WM_DEBUG_LINK,
   4089 		    ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname));
   4090 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
   4091 	}
   4092 
   4093 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
   4094 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
   4095 	CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
   4096 						 : WMREG_FCRTL, sc->sc_fcrtl);
   4097 }
   4098 
   4099 static int
   4100 wm_is_onboard_nvm_eeprom(struct wm_softc *sc)
   4101 {
   4102 	uint32_t eecd = 0;
   4103 
   4104 	if(sc->sc_type == WM_T_82573) {
   4105 		eecd = CSR_READ(sc, WMREG_EECD);
   4106 
   4107 		/* Isolate bits 15 & 16 */
   4108 		eecd = ((eecd >> 15) & 0x03);
   4109 
   4110 		/* If both bits are set, device is Flash type */
   4111 		if(eecd == 0x03) {
   4112 			return 0;
   4113 		}
   4114 	}
   4115 	return 1;
   4116 }
   4117 
   4118 static int
   4119 wm_get_eeprom_semaphore(struct wm_softc *sc)
   4120 {
   4121 	int32_t timeout;
   4122 	uint32_t swsm;
   4123 
   4124 	if((sc->sc_flags & WM_F_EEPROM_SEMAPHORE) == 0)
   4125 		return 0;
   4126 
   4127 	/* Get the FW semaphore. */
   4128 	timeout = 1000 + 1; /* XXX */
   4129 	while (timeout) {
   4130 		swsm = CSR_READ(sc, WMREG_SWSM);
   4131 		swsm |= SWSM_SWESMBI;
   4132 		CSR_WRITE(sc, WMREG_SWSM, swsm);
   4133 		/* if we managed to set the bit we got the semaphore. */
   4134 		swsm = CSR_READ(sc, WMREG_SWSM);
   4135 		if(swsm & SWSM_SWESMBI)
   4136 			break;
   4137 
   4138 		delay(50);
   4139 		timeout--;
   4140 	}
   4141 
   4142 	if (timeout == 0) {
   4143 		/* Release semaphores */
   4144 		wm_put_eeprom_semaphore(sc);
   4145 		return 1;
   4146 	}
   4147 
   4148 	return 0;
   4149 }
   4150 
   4151 static void
   4152 wm_put_eeprom_semaphore(struct wm_softc *sc)
   4153 {
   4154 	uint32_t swsm;
   4155 
   4156 	if((sc->sc_flags & WM_F_EEPROM_SEMAPHORE) == 0)
   4157 		return;
   4158 
   4159 	swsm = CSR_READ(sc, WMREG_SWSM);
   4160         swsm &= ~(SWSM_SWESMBI);
   4161 	CSR_WRITE(sc, WMREG_SWSM, swsm);
   4162 }
   4163