if_wm.c revision 1.120
1 /* $NetBSD: if_wm.c,v 1.120 2006/06/10 14:26:52 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.120 2006/06/10 14:26:52 msaitoh Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make several things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 WM_T_82571, /* i82571 */ 217 WM_T_82572, /* i82572 */ 218 WM_T_82573, /* i82573 */ 219 } wm_chip_type; 220 221 /* 222 * Software state per device. 223 */ 224 struct wm_softc { 225 struct device sc_dev; /* generic device information */ 226 bus_space_tag_t sc_st; /* bus space tag */ 227 bus_space_handle_t sc_sh; /* bus space handle */ 228 bus_space_tag_t sc_iot; /* I/O space tag */ 229 bus_space_handle_t sc_ioh; /* I/O space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 wm_chip_type sc_type; /* chip type */ 235 int sc_flags; /* flags; see below */ 236 int sc_bus_speed; /* PCI/PCIX bus speed */ 237 int sc_pcix_offset; /* PCIX capability register offset */ 238 int sc_flowflags; /* 802.3x flow control flags */ 239 240 void *sc_ih; /* interrupt cookie */ 241 242 int sc_ee_addrbits; /* EEPROM address bits */ 243 244 struct mii_data sc_mii; /* MII/media information */ 245 246 struct callout sc_tick_ch; /* tick callout */ 247 248 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 249 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 250 251 int sc_align_tweak; 252 253 /* 254 * Software state for the transmit and receive descriptors. 255 */ 256 int sc_txnum; /* must be a power of two */ 257 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 258 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 259 260 /* 261 * Control data structures. 262 */ 263 int sc_ntxdesc; /* must be a power of two */ 264 struct wm_control_data_82544 *sc_control_data; 265 #define sc_txdescs sc_control_data->wcd_txdescs 266 #define sc_rxdescs sc_control_data->wcd_rxdescs 267 268 #ifdef WM_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 272 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 273 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 274 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 275 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 276 struct evcnt sc_ev_linkintr; /* Link interrupts */ 277 278 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 279 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 280 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 281 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 282 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 283 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 284 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 285 286 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 287 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 288 289 struct evcnt sc_ev_tu; /* Tx underrun */ 290 291 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 292 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 293 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 294 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 295 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 296 #endif /* WM_EVENT_COUNTERS */ 297 298 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 299 300 int sc_txfree; /* number of free Tx descriptors */ 301 int sc_txnext; /* next ready Tx descriptor */ 302 303 int sc_txsfree; /* number of free Tx jobs */ 304 int sc_txsnext; /* next free Tx job */ 305 int sc_txsdirty; /* dirty Tx jobs */ 306 307 /* These 5 variables are used only on the 82547. */ 308 int sc_txfifo_size; /* Tx FIFO size */ 309 int sc_txfifo_head; /* current head of FIFO */ 310 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 311 int sc_txfifo_stall; /* Tx FIFO is stalled */ 312 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 313 314 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 315 316 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 317 int sc_rxdiscard; 318 int sc_rxlen; 319 struct mbuf *sc_rxhead; 320 struct mbuf *sc_rxtail; 321 struct mbuf **sc_rxtailp; 322 323 uint32_t sc_ctrl; /* prototype CTRL register */ 324 #if 0 325 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 326 #endif 327 uint32_t sc_icr; /* prototype interrupt bits */ 328 uint32_t sc_itr; /* prototype intr throttling reg */ 329 uint32_t sc_tctl; /* prototype TCTL register */ 330 uint32_t sc_rctl; /* prototype RCTL register */ 331 uint32_t sc_txcw; /* prototype TXCW register */ 332 uint32_t sc_tipg; /* prototype TIPG register */ 333 uint32_t sc_fcrtl; /* prototype FCRTL register */ 334 uint32_t sc_pba; /* prototype PBA register */ 335 336 int sc_tbi_linkup; /* TBI link status */ 337 int sc_tbi_anstate; /* autonegotiation state */ 338 339 int sc_mchash_type; /* multicast filter offset */ 340 341 #if NRND > 0 342 rndsource_element_t rnd_source; /* random source */ 343 #endif 344 }; 345 346 #define WM_RXCHAIN_RESET(sc) \ 347 do { \ 348 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 349 *(sc)->sc_rxtailp = NULL; \ 350 (sc)->sc_rxlen = 0; \ 351 } while (/*CONSTCOND*/0) 352 353 #define WM_RXCHAIN_LINK(sc, m) \ 354 do { \ 355 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 356 (sc)->sc_rxtailp = &(m)->m_next; \ 357 } while (/*CONSTCOND*/0) 358 359 /* sc_flags */ 360 #define WM_F_HAS_MII 0x001 /* has MII */ 361 #define WM_F_EEPROM_HANDSHAKE 0x002 /* requires EEPROM handshake */ 362 #define WM_F_EEPROM_SEMAPHORE 0x004 /* EEPROM with semaphore */ 363 #define WM_F_EEPROM_EERDEEWR 0x008 /* EEPROM access via EERD/EEWR */ 364 #define WM_F_EEPROM_SPI 0x010 /* EEPROM is SPI */ 365 #define WM_F_EEPROM_FLASH 0x020 /* EEPROM is FLASH */ 366 #define WM_F_EEPROM_INVALID 0x040 /* EEPROM not present (bad checksum) */ 367 #define WM_F_IOH_VALID 0x080 /* I/O handle is valid */ 368 #define WM_F_BUS64 0x100 /* bus is 64-bit */ 369 #define WM_F_PCIX 0x200 /* bus is PCI-X */ 370 #define WM_F_CSA 0x400 /* bus is CSA */ 371 #define WM_F_PCIE 0x800 /* bus is PCI-Express */ 372 373 #ifdef WM_EVENT_COUNTERS 374 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 375 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 376 #else 377 #define WM_EVCNT_INCR(ev) /* nothing */ 378 #define WM_EVCNT_ADD(ev, val) /* nothing */ 379 #endif 380 381 #define CSR_READ(sc, reg) \ 382 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 383 #define CSR_WRITE(sc, reg, val) \ 384 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 385 #define CSR_WRITE_FLUSH(sc) \ 386 (void) CSR_READ((sc), WMREG_STATUS) 387 388 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 389 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 390 391 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 392 #define WM_CDTXADDR_HI(sc, x) \ 393 (sizeof(bus_addr_t) == 8 ? \ 394 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 395 396 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 397 #define WM_CDRXADDR_HI(sc, x) \ 398 (sizeof(bus_addr_t) == 8 ? \ 399 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 400 401 #define WM_CDTXSYNC(sc, x, n, ops) \ 402 do { \ 403 int __x, __n; \ 404 \ 405 __x = (x); \ 406 __n = (n); \ 407 \ 408 /* If it will wrap around, sync to the end of the ring. */ \ 409 if ((__x + __n) > WM_NTXDESC(sc)) { \ 410 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 411 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 412 (WM_NTXDESC(sc) - __x), (ops)); \ 413 __n -= (WM_NTXDESC(sc) - __x); \ 414 __x = 0; \ 415 } \ 416 \ 417 /* Now sync whatever is left. */ \ 418 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 419 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 420 } while (/*CONSTCOND*/0) 421 422 #define WM_CDRXSYNC(sc, x, ops) \ 423 do { \ 424 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 425 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 426 } while (/*CONSTCOND*/0) 427 428 #define WM_INIT_RXDESC(sc, x) \ 429 do { \ 430 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 431 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 432 struct mbuf *__m = __rxs->rxs_mbuf; \ 433 \ 434 /* \ 435 * Note: We scoot the packet forward 2 bytes in the buffer \ 436 * so that the payload after the Ethernet header is aligned \ 437 * to a 4-byte boundary. \ 438 * \ 439 * XXX BRAINDAMAGE ALERT! \ 440 * The stupid chip uses the same size for every buffer, which \ 441 * is set in the Receive Control register. We are using the 2K \ 442 * size option, but what we REALLY want is (2K - 2)! For this \ 443 * reason, we can't "scoot" packets longer than the standard \ 444 * Ethernet MTU. On strict-alignment platforms, if the total \ 445 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 446 * the upper layer copy the headers. \ 447 */ \ 448 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 449 \ 450 wm_set_dma_addr(&__rxd->wrx_addr, \ 451 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 452 __rxd->wrx_len = 0; \ 453 __rxd->wrx_cksum = 0; \ 454 __rxd->wrx_status = 0; \ 455 __rxd->wrx_errors = 0; \ 456 __rxd->wrx_special = 0; \ 457 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 458 \ 459 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 460 } while (/*CONSTCOND*/0) 461 462 static void wm_start(struct ifnet *); 463 static void wm_watchdog(struct ifnet *); 464 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 465 static int wm_init(struct ifnet *); 466 static void wm_stop(struct ifnet *, int); 467 468 static void wm_shutdown(void *); 469 470 static void wm_reset(struct wm_softc *); 471 static void wm_rxdrain(struct wm_softc *); 472 static int wm_add_rxbuf(struct wm_softc *, int); 473 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 474 static int wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *); 475 static int wm_validate_eeprom_checksum(struct wm_softc *); 476 static void wm_tick(void *); 477 478 static void wm_set_filter(struct wm_softc *); 479 480 static int wm_intr(void *); 481 static void wm_txintr(struct wm_softc *); 482 static void wm_rxintr(struct wm_softc *); 483 static void wm_linkintr(struct wm_softc *, uint32_t); 484 485 static void wm_tbi_mediainit(struct wm_softc *); 486 static int wm_tbi_mediachange(struct ifnet *); 487 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 488 489 static void wm_tbi_set_linkled(struct wm_softc *); 490 static void wm_tbi_check_link(struct wm_softc *); 491 492 static void wm_gmii_reset(struct wm_softc *); 493 494 static int wm_gmii_i82543_readreg(struct device *, int, int); 495 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 496 497 static int wm_gmii_i82544_readreg(struct device *, int, int); 498 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 499 500 static void wm_gmii_statchg(struct device *); 501 502 static void wm_gmii_mediainit(struct wm_softc *); 503 static int wm_gmii_mediachange(struct ifnet *); 504 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 505 506 static int wm_match(struct device *, struct cfdata *, void *); 507 static void wm_attach(struct device *, struct device *, void *); 508 static int wm_is_onboard_nvm_eeprom(struct wm_softc *); 509 static int wm_get_eeprom_semaphore(struct wm_softc *); 510 static void wm_put_eeprom_semaphore(struct wm_softc *); 511 static int wm_poll_eerd_eewr_done(struct wm_softc *, int); 512 513 CFATTACH_DECL(wm, sizeof(struct wm_softc), 514 wm_match, wm_attach, NULL, NULL); 515 516 static void wm_82547_txfifo_stall(void *); 517 518 /* 519 * Devices supported by this driver. 520 */ 521 static const struct wm_product { 522 pci_vendor_id_t wmp_vendor; 523 pci_product_id_t wmp_product; 524 const char *wmp_name; 525 wm_chip_type wmp_type; 526 int wmp_flags; 527 #define WMP_F_1000X 0x01 528 #define WMP_F_1000T 0x02 529 } wm_products[] = { 530 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 531 "Intel i82542 1000BASE-X Ethernet", 532 WM_T_82542_2_1, WMP_F_1000X }, 533 534 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 535 "Intel i82543GC 1000BASE-X Ethernet", 536 WM_T_82543, WMP_F_1000X }, 537 538 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 539 "Intel i82543GC 1000BASE-T Ethernet", 540 WM_T_82543, WMP_F_1000T }, 541 542 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 543 "Intel i82544EI 1000BASE-T Ethernet", 544 WM_T_82544, WMP_F_1000T }, 545 546 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 547 "Intel i82544EI 1000BASE-X Ethernet", 548 WM_T_82544, WMP_F_1000X }, 549 550 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 551 "Intel i82544GC 1000BASE-T Ethernet", 552 WM_T_82544, WMP_F_1000T }, 553 554 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 555 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 556 WM_T_82544, WMP_F_1000T }, 557 558 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 559 "Intel i82540EM 1000BASE-T Ethernet", 560 WM_T_82540, WMP_F_1000T }, 561 562 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 563 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 564 WM_T_82540, WMP_F_1000T }, 565 566 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 567 "Intel i82540EP 1000BASE-T Ethernet", 568 WM_T_82540, WMP_F_1000T }, 569 570 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 571 "Intel i82540EP 1000BASE-T Ethernet", 572 WM_T_82540, WMP_F_1000T }, 573 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 575 "Intel i82540EP 1000BASE-T Ethernet", 576 WM_T_82540, WMP_F_1000T }, 577 578 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 579 "Intel i82545EM 1000BASE-T Ethernet", 580 WM_T_82545, WMP_F_1000T }, 581 582 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 583 "Intel i82545GM 1000BASE-T Ethernet", 584 WM_T_82545_3, WMP_F_1000T }, 585 586 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 587 "Intel i82545GM 1000BASE-X Ethernet", 588 WM_T_82545_3, WMP_F_1000X }, 589 #if 0 590 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 591 "Intel i82545GM Gigabit Ethernet (SERDES)", 592 WM_T_82545_3, WMP_F_SERDES }, 593 #endif 594 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 595 "Intel i82546EB 1000BASE-T Ethernet", 596 WM_T_82546, WMP_F_1000T }, 597 598 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 599 "Intel i82546EB 1000BASE-T Ethernet", 600 WM_T_82546, WMP_F_1000T }, 601 602 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 603 "Intel i82545EM 1000BASE-X Ethernet", 604 WM_T_82545, WMP_F_1000X }, 605 606 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 607 "Intel i82546EB 1000BASE-X Ethernet", 608 WM_T_82546, WMP_F_1000X }, 609 610 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 611 "Intel i82546GB 1000BASE-T Ethernet", 612 WM_T_82546_3, WMP_F_1000T }, 613 614 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 615 "Intel i82546GB 1000BASE-X Ethernet", 616 WM_T_82546_3, WMP_F_1000X }, 617 #if 0 618 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 619 "Intel i82546GB Gigabit Ethernet (SERDES)", 620 WM_T_82546_3, WMP_F_SERDES }, 621 #endif 622 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, 623 "Intel PRO/1000MT (82546GB)", 624 WM_T_82546_3, WMP_F_1000T }, 625 626 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 627 "Intel i82541EI 1000BASE-T Ethernet", 628 WM_T_82541, WMP_F_1000T }, 629 630 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, 631 "Intel i82541ER (LOM) 1000BASE-T Ethernet", 632 WM_T_82541, WMP_F_1000T }, 633 634 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 635 "Intel i82541EI Mobile 1000BASE-T Ethernet", 636 WM_T_82541, WMP_F_1000T }, 637 638 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 639 "Intel i82541ER 1000BASE-T Ethernet", 640 WM_T_82541_2, WMP_F_1000T }, 641 642 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 643 "Intel i82541GI 1000BASE-T Ethernet", 644 WM_T_82541_2, WMP_F_1000T }, 645 646 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 647 "Intel i82541GI Mobile 1000BASE-T Ethernet", 648 WM_T_82541_2, WMP_F_1000T }, 649 650 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 651 "Intel i82541PI 1000BASE-T Ethernet", 652 WM_T_82541_2, WMP_F_1000T }, 653 654 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 655 "Intel i82547EI 1000BASE-T Ethernet", 656 WM_T_82547, WMP_F_1000T }, 657 658 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, 659 "Intel i82547EI Moblie 1000BASE-T Ethernet", 660 WM_T_82547, WMP_F_1000T }, 661 662 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 663 "Intel i82547GI 1000BASE-T Ethernet", 664 WM_T_82547_2, WMP_F_1000T }, 665 666 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, 667 "Intel PRO/1000 PT (82571EB)", 668 WM_T_82571, WMP_F_1000T }, 669 670 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, 671 "Intel PRO/1000 PF (82571EB)", 672 WM_T_82571, WMP_F_1000X }, 673 #if 0 674 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, 675 "Intel PRO/1000 PB (82571EB)", 676 WM_T_82571, WMP_F_SERDES }, 677 #endif 678 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, 679 "Intel i82572EI 1000baseT Ethernet", 680 WM_T_82572, WMP_F_1000T }, 681 682 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, 683 "Intel i82572EI 1000baseX Ethernet", 684 WM_T_82572, WMP_F_1000X }, 685 #if 0 686 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, 687 "Intel i82572EI Gigabit Ethernet (SERDES)", 688 WM_T_82572, WMP_F_SERDES }, 689 #endif 690 691 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, 692 "Intel i82572EI 1000baseT Ethernet", 693 WM_T_82572, WMP_F_1000T }, 694 695 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, 696 "Intel i82573E", 697 WM_T_82573, WMP_F_1000T }, 698 699 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, 700 "Intel i82573E IAMT", 701 WM_T_82573, WMP_F_1000T }, 702 703 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, 704 "Intel i82573L Gigabit Ethernet", 705 WM_T_82573, WMP_F_1000T }, 706 707 { 0, 0, 708 NULL, 709 0, 0 }, 710 }; 711 712 #ifdef WM_EVENT_COUNTERS 713 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 714 #endif /* WM_EVENT_COUNTERS */ 715 716 #if 0 /* Not currently used */ 717 static inline uint32_t 718 wm_io_read(struct wm_softc *sc, int reg) 719 { 720 721 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 722 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 723 } 724 #endif 725 726 static inline void 727 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 728 { 729 730 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 731 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 732 } 733 734 static inline void 735 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 736 { 737 wa->wa_low = htole32(v & 0xffffffffU); 738 if (sizeof(bus_addr_t) == 8) 739 wa->wa_high = htole32((uint64_t) v >> 32); 740 else 741 wa->wa_high = 0; 742 } 743 744 static const struct wm_product * 745 wm_lookup(const struct pci_attach_args *pa) 746 { 747 const struct wm_product *wmp; 748 749 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 750 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 751 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 752 return (wmp); 753 } 754 return (NULL); 755 } 756 757 static int 758 wm_match(struct device *parent, struct cfdata *cf, void *aux) 759 { 760 struct pci_attach_args *pa = aux; 761 762 if (wm_lookup(pa) != NULL) 763 return (1); 764 765 return (0); 766 } 767 768 static void 769 wm_attach(struct device *parent, struct device *self, void *aux) 770 { 771 struct wm_softc *sc = (void *) self; 772 struct pci_attach_args *pa = aux; 773 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 774 pci_chipset_tag_t pc = pa->pa_pc; 775 pci_intr_handle_t ih; 776 size_t cdata_size; 777 const char *intrstr = NULL; 778 const char *eetype; 779 bus_space_tag_t memt; 780 bus_space_handle_t memh; 781 bus_dma_segment_t seg; 782 int memh_valid; 783 int i, rseg, error; 784 const struct wm_product *wmp; 785 prop_data_t ea; 786 prop_number_t pn; 787 uint8_t enaddr[ETHER_ADDR_LEN]; 788 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 789 pcireg_t preg, memtype; 790 uint32_t reg; 791 int pmreg; 792 793 callout_init(&sc->sc_tick_ch); 794 795 wmp = wm_lookup(pa); 796 if (wmp == NULL) { 797 printf("\n"); 798 panic("wm_attach: impossible"); 799 } 800 801 if (pci_dma64_available(pa)) 802 sc->sc_dmat = pa->pa_dmat64; 803 else 804 sc->sc_dmat = pa->pa_dmat; 805 806 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 807 aprint_naive(": Ethernet controller\n"); 808 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 809 810 sc->sc_type = wmp->wmp_type; 811 if (sc->sc_type < WM_T_82543) { 812 if (preg < 2) { 813 aprint_error("%s: i82542 must be at least rev. 2\n", 814 sc->sc_dev.dv_xname); 815 return; 816 } 817 if (preg < 3) 818 sc->sc_type = WM_T_82542_2_0; 819 } 820 821 /* 822 * Map the device. All devices support memory-mapped acccess, 823 * and it is really required for normal operation. 824 */ 825 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 826 switch (memtype) { 827 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 828 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 829 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 830 memtype, 0, &memt, &memh, NULL, NULL) == 0); 831 break; 832 default: 833 memh_valid = 0; 834 } 835 836 if (memh_valid) { 837 sc->sc_st = memt; 838 sc->sc_sh = memh; 839 } else { 840 aprint_error("%s: unable to map device registers\n", 841 sc->sc_dev.dv_xname); 842 return; 843 } 844 845 /* 846 * In addition, i82544 and later support I/O mapped indirect 847 * register access. It is not desirable (nor supported in 848 * this driver) to use it for normal operation, though it is 849 * required to work around bugs in some chip versions. 850 */ 851 if (sc->sc_type >= WM_T_82544) { 852 /* First we have to find the I/O BAR. */ 853 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 854 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 855 PCI_MAPREG_TYPE_IO) 856 break; 857 } 858 if (i == PCI_MAPREG_END) 859 aprint_error("%s: WARNING: unable to find I/O BAR\n", 860 sc->sc_dev.dv_xname); 861 else { 862 /* 863 * The i8254x doesn't apparently respond when the 864 * I/O BAR is 0, which looks somewhat like it's not 865 * been configured. 866 */ 867 preg = pci_conf_read(pc, pa->pa_tag, i); 868 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 869 aprint_error("%s: WARNING: I/O BAR at zero.\n", 870 sc->sc_dev.dv_xname); 871 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 872 0, &sc->sc_iot, &sc->sc_ioh, 873 NULL, NULL) == 0) { 874 sc->sc_flags |= WM_F_IOH_VALID; 875 } else { 876 aprint_error("%s: WARNING: unable to map " 877 "I/O space\n", sc->sc_dev.dv_xname); 878 } 879 } 880 881 } 882 883 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 884 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 885 preg |= PCI_COMMAND_MASTER_ENABLE; 886 if (sc->sc_type < WM_T_82542_2_1) 887 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 888 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 889 890 /* Get it out of power save mode, if needed. */ 891 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 892 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 893 PCI_PMCSR_STATE_MASK; 894 if (preg == PCI_PMCSR_STATE_D3) { 895 /* 896 * The card has lost all configuration data in 897 * this state, so punt. 898 */ 899 aprint_error("%s: unable to wake from power state D3\n", 900 sc->sc_dev.dv_xname); 901 return; 902 } 903 if (preg != PCI_PMCSR_STATE_D0) { 904 aprint_normal("%s: waking up from power state D%d\n", 905 sc->sc_dev.dv_xname, preg); 906 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 907 PCI_PMCSR_STATE_D0); 908 } 909 } 910 911 /* 912 * Map and establish our interrupt. 913 */ 914 if (pci_intr_map(pa, &ih)) { 915 aprint_error("%s: unable to map interrupt\n", 916 sc->sc_dev.dv_xname); 917 return; 918 } 919 intrstr = pci_intr_string(pc, ih); 920 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 921 if (sc->sc_ih == NULL) { 922 aprint_error("%s: unable to establish interrupt", 923 sc->sc_dev.dv_xname); 924 if (intrstr != NULL) 925 aprint_normal(" at %s", intrstr); 926 aprint_normal("\n"); 927 return; 928 } 929 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 930 931 /* 932 * Determine a few things about the bus we're connected to. 933 */ 934 if (sc->sc_type < WM_T_82543) { 935 /* We don't really know the bus characteristics here. */ 936 sc->sc_bus_speed = 33; 937 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 938 /* 939 * CSA (Communication Streaming Architecture) is about as fast 940 * a 32-bit 66MHz PCI Bus. 941 */ 942 sc->sc_flags |= WM_F_CSA; 943 sc->sc_bus_speed = 66; 944 aprint_verbose("%s: Communication Streaming Architecture\n", 945 sc->sc_dev.dv_xname); 946 if (sc->sc_type == WM_T_82547) { 947 callout_init(&sc->sc_txfifo_ch); 948 callout_setfunc(&sc->sc_txfifo_ch, 949 wm_82547_txfifo_stall, sc); 950 aprint_verbose("%s: using 82547 Tx FIFO stall " 951 "work-around\n", sc->sc_dev.dv_xname); 952 } 953 } else if (sc->sc_type >= WM_T_82571) { 954 sc->sc_flags |= WM_F_PCIE | WM_F_EEPROM_SEMAPHORE; 955 aprint_verbose("%s: PCI-Express bus\n", sc->sc_dev.dv_xname); 956 } else { 957 reg = CSR_READ(sc, WMREG_STATUS); 958 if (reg & STATUS_BUS64) 959 sc->sc_flags |= WM_F_BUS64; 960 if (sc->sc_type >= WM_T_82544 && 961 (reg & STATUS_PCIX_MODE) != 0) { 962 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 963 964 sc->sc_flags |= WM_F_PCIX; 965 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 966 PCI_CAP_PCIX, 967 &sc->sc_pcix_offset, NULL) == 0) 968 aprint_error("%s: unable to find PCIX " 969 "capability\n", sc->sc_dev.dv_xname); 970 else if (sc->sc_type != WM_T_82545_3 && 971 sc->sc_type != WM_T_82546_3) { 972 /* 973 * Work around a problem caused by the BIOS 974 * setting the max memory read byte count 975 * incorrectly. 976 */ 977 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 978 sc->sc_pcix_offset + PCI_PCIX_CMD); 979 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 980 sc->sc_pcix_offset + PCI_PCIX_STATUS); 981 982 bytecnt = 983 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 984 PCI_PCIX_CMD_BYTECNT_SHIFT; 985 maxb = 986 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 987 PCI_PCIX_STATUS_MAXB_SHIFT; 988 if (bytecnt > maxb) { 989 aprint_verbose("%s: resetting PCI-X " 990 "MMRBC: %d -> %d\n", 991 sc->sc_dev.dv_xname, 992 512 << bytecnt, 512 << maxb); 993 pcix_cmd = (pcix_cmd & 994 ~PCI_PCIX_CMD_BYTECNT_MASK) | 995 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 996 pci_conf_write(pa->pa_pc, pa->pa_tag, 997 sc->sc_pcix_offset + PCI_PCIX_CMD, 998 pcix_cmd); 999 } 1000 } 1001 } 1002 /* 1003 * The quad port adapter is special; it has a PCIX-PCIX 1004 * bridge on the board, and can run the secondary bus at 1005 * a higher speed. 1006 */ 1007 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 1008 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 1009 : 66; 1010 } else if (sc->sc_flags & WM_F_PCIX) { 1011 switch (reg & STATUS_PCIXSPD_MASK) { 1012 case STATUS_PCIXSPD_50_66: 1013 sc->sc_bus_speed = 66; 1014 break; 1015 case STATUS_PCIXSPD_66_100: 1016 sc->sc_bus_speed = 100; 1017 break; 1018 case STATUS_PCIXSPD_100_133: 1019 sc->sc_bus_speed = 133; 1020 break; 1021 default: 1022 aprint_error( 1023 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 1024 sc->sc_dev.dv_xname, 1025 reg & STATUS_PCIXSPD_MASK); 1026 sc->sc_bus_speed = 66; 1027 } 1028 } else 1029 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 1030 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 1031 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 1032 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 1033 } 1034 1035 /* 1036 * Allocate the control data structures, and create and load the 1037 * DMA map for it. 1038 * 1039 * NOTE: All Tx descriptors must be in the same 4G segment of 1040 * memory. So must Rx descriptors. We simplify by allocating 1041 * both sets within the same 4G segment. 1042 */ 1043 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 1044 WM_NTXDESC_82542 : WM_NTXDESC_82544; 1045 cdata_size = sc->sc_type < WM_T_82544 ? 1046 sizeof(struct wm_control_data_82542) : 1047 sizeof(struct wm_control_data_82544); 1048 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 1049 (bus_size_t) 0x100000000ULL, 1050 &seg, 1, &rseg, 0)) != 0) { 1051 aprint_error( 1052 "%s: unable to allocate control data, error = %d\n", 1053 sc->sc_dev.dv_xname, error); 1054 goto fail_0; 1055 } 1056 1057 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 1058 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 1059 aprint_error("%s: unable to map control data, error = %d\n", 1060 sc->sc_dev.dv_xname, error); 1061 goto fail_1; 1062 } 1063 1064 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 1065 0, 0, &sc->sc_cddmamap)) != 0) { 1066 aprint_error("%s: unable to create control data DMA map, " 1067 "error = %d\n", sc->sc_dev.dv_xname, error); 1068 goto fail_2; 1069 } 1070 1071 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1072 sc->sc_control_data, cdata_size, NULL, 1073 0)) != 0) { 1074 aprint_error( 1075 "%s: unable to load control data DMA map, error = %d\n", 1076 sc->sc_dev.dv_xname, error); 1077 goto fail_3; 1078 } 1079 1080 1081 /* 1082 * Create the transmit buffer DMA maps. 1083 */ 1084 WM_TXQUEUELEN(sc) = 1085 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1086 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1087 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1088 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1089 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1090 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1091 aprint_error("%s: unable to create Tx DMA map %d, " 1092 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1093 goto fail_4; 1094 } 1095 } 1096 1097 /* 1098 * Create the receive buffer DMA maps. 1099 */ 1100 for (i = 0; i < WM_NRXDESC; i++) { 1101 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1102 MCLBYTES, 0, 0, 1103 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1104 aprint_error("%s: unable to create Rx DMA map %d, " 1105 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1106 goto fail_5; 1107 } 1108 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1109 } 1110 1111 /* 1112 * Reset the chip to a known state. 1113 */ 1114 wm_reset(sc); 1115 1116 /* 1117 * Get some information about the EEPROM. 1118 */ 1119 if (sc->sc_type == WM_T_82573) 1120 sc->sc_flags |= WM_F_EEPROM_EERDEEWR; 1121 else if (sc->sc_type > WM_T_82544) 1122 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1123 1124 if (sc->sc_type <= WM_T_82544) 1125 sc->sc_ee_addrbits = 6; 1126 else if (sc->sc_type <= WM_T_82546_3) { 1127 reg = CSR_READ(sc, WMREG_EECD); 1128 if (reg & EECD_EE_SIZE) 1129 sc->sc_ee_addrbits = 8; 1130 else 1131 sc->sc_ee_addrbits = 6; 1132 } else if (sc->sc_type <= WM_T_82547_2) { 1133 reg = CSR_READ(sc, WMREG_EECD); 1134 if (reg & EECD_EE_TYPE) { 1135 sc->sc_flags |= WM_F_EEPROM_SPI; 1136 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1137 } else 1138 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1139 } else if ((sc->sc_type == WM_T_82573) && 1140 (wm_is_onboard_nvm_eeprom(sc) == 0)) { 1141 sc->sc_flags |= WM_F_EEPROM_FLASH; 1142 } else { 1143 /* Assume everything else is SPI. */ 1144 reg = CSR_READ(sc, WMREG_EECD); 1145 sc->sc_flags |= WM_F_EEPROM_SPI; 1146 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1147 } 1148 1149 /* 1150 * Defer printing the EEPROM type until after verifying the checksum 1151 * This allows the EEPROM type to be printed correctly in the case 1152 * that no EEPROM is attached. 1153 */ 1154 1155 1156 /* 1157 * Validate the EEPROM checksum. If the checksum fails, flag this for 1158 * later, so we can fail future reads from the EEPROM. 1159 */ 1160 if (wm_validate_eeprom_checksum(sc)) 1161 sc->sc_flags |= WM_F_EEPROM_INVALID; 1162 1163 if (sc->sc_flags & WM_F_EEPROM_INVALID) 1164 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname); 1165 else if (sc->sc_flags & WM_F_EEPROM_FLASH) { 1166 aprint_verbose("%s: FLASH\n", sc->sc_dev.dv_xname); 1167 } else { 1168 if (sc->sc_flags & WM_F_EEPROM_SPI) 1169 eetype = "SPI"; 1170 else 1171 eetype = "MicroWire"; 1172 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1173 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1174 sc->sc_ee_addrbits, eetype); 1175 } 1176 1177 /* 1178 * Read the Ethernet address from the EEPROM, if not first found 1179 * in device properties. 1180 */ 1181 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 1182 if (ea != NULL) { 1183 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 1184 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 1185 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 1186 } else { 1187 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1188 sizeof(myea) / sizeof(myea[0]), myea)) { 1189 aprint_error("%s: unable to read Ethernet address\n", 1190 sc->sc_dev.dv_xname); 1191 return; 1192 } 1193 enaddr[0] = myea[0] & 0xff; 1194 enaddr[1] = myea[0] >> 8; 1195 enaddr[2] = myea[1] & 0xff; 1196 enaddr[3] = myea[1] >> 8; 1197 enaddr[4] = myea[2] & 0xff; 1198 enaddr[5] = myea[2] >> 8; 1199 } 1200 1201 /* 1202 * Toggle the LSB of the MAC address on the second port 1203 * of the i82546. 1204 */ 1205 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3) { 1206 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1207 enaddr[5] ^= 1; 1208 } 1209 1210 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1211 ether_sprintf(enaddr)); 1212 1213 /* 1214 * Read the config info from the EEPROM, and set up various 1215 * bits in the control registers based on their contents. 1216 */ 1217 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1218 "i82543-cfg1"); 1219 if (pn != NULL) { 1220 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1221 cfg1 = (uint16_t) prop_number_integer_value(pn); 1222 } else { 1223 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1224 aprint_error("%s: unable to read CFG1\n", 1225 sc->sc_dev.dv_xname); 1226 return; 1227 } 1228 } 1229 1230 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1231 "i82543-cfg2"); 1232 if (pn != NULL) { 1233 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1234 cfg2 = (uint16_t) prop_number_integer_value(pn); 1235 } else { 1236 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1237 aprint_error("%s: unable to read CFG2\n", 1238 sc->sc_dev.dv_xname); 1239 return; 1240 } 1241 } 1242 1243 if (sc->sc_type >= WM_T_82544) { 1244 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1245 "i82543-swdpin"); 1246 if (pn != NULL) { 1247 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1248 swdpin = (uint16_t) prop_number_integer_value(pn); 1249 } else { 1250 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1251 aprint_error("%s: unable to read SWDPIN\n", 1252 sc->sc_dev.dv_xname); 1253 return; 1254 } 1255 } 1256 } 1257 1258 if (cfg1 & EEPROM_CFG1_ILOS) 1259 sc->sc_ctrl |= CTRL_ILOS; 1260 if (sc->sc_type >= WM_T_82544) { 1261 sc->sc_ctrl |= 1262 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1263 CTRL_SWDPIO_SHIFT; 1264 sc->sc_ctrl |= 1265 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1266 CTRL_SWDPINS_SHIFT; 1267 } else { 1268 sc->sc_ctrl |= 1269 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1270 CTRL_SWDPIO_SHIFT; 1271 } 1272 1273 #if 0 1274 if (sc->sc_type >= WM_T_82544) { 1275 if (cfg1 & EEPROM_CFG1_IPS0) 1276 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1277 if (cfg1 & EEPROM_CFG1_IPS1) 1278 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1279 sc->sc_ctrl_ext |= 1280 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1281 CTRL_EXT_SWDPIO_SHIFT; 1282 sc->sc_ctrl_ext |= 1283 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1284 CTRL_EXT_SWDPINS_SHIFT; 1285 } else { 1286 sc->sc_ctrl_ext |= 1287 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1288 CTRL_EXT_SWDPIO_SHIFT; 1289 } 1290 #endif 1291 1292 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1293 #if 0 1294 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1295 #endif 1296 1297 /* 1298 * Set up some register offsets that are different between 1299 * the i82542 and the i82543 and later chips. 1300 */ 1301 if (sc->sc_type < WM_T_82543) { 1302 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1303 sc->sc_tdt_reg = WMREG_OLD_TDT; 1304 } else { 1305 sc->sc_rdt_reg = WMREG_RDT; 1306 sc->sc_tdt_reg = WMREG_TDT; 1307 } 1308 1309 /* 1310 * Determine if we're TBI or GMII mode, and initialize the 1311 * media structures accordingly. 1312 */ 1313 if (sc->sc_type < WM_T_82543 || 1314 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1315 if (wmp->wmp_flags & WMP_F_1000T) 1316 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1317 "product!\n", sc->sc_dev.dv_xname); 1318 wm_tbi_mediainit(sc); 1319 } else { 1320 if (wmp->wmp_flags & WMP_F_1000X) 1321 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1322 "product!\n", sc->sc_dev.dv_xname); 1323 wm_gmii_mediainit(sc); 1324 } 1325 1326 ifp = &sc->sc_ethercom.ec_if; 1327 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1328 ifp->if_softc = sc; 1329 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1330 ifp->if_ioctl = wm_ioctl; 1331 ifp->if_start = wm_start; 1332 ifp->if_watchdog = wm_watchdog; 1333 ifp->if_init = wm_init; 1334 ifp->if_stop = wm_stop; 1335 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1336 IFQ_SET_READY(&ifp->if_snd); 1337 1338 if (sc->sc_type != WM_T_82573) 1339 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1340 1341 /* 1342 * If we're a i82543 or greater, we can support VLANs. 1343 */ 1344 if (sc->sc_type >= WM_T_82543) 1345 sc->sc_ethercom.ec_capabilities |= 1346 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1347 1348 /* 1349 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1350 * on i82543 and later. 1351 */ 1352 if (sc->sc_type >= WM_T_82543) 1353 ifp->if_capabilities |= 1354 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1355 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1356 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1357 IFCAP_CSUM_TCPv6_Tx | 1358 IFCAP_CSUM_UDPv6_Tx; 1359 1360 /* 1361 * If we're a i82544 or greater (except i82547), we can do 1362 * TCP segmentation offload. 1363 */ 1364 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1365 ifp->if_capabilities |= IFCAP_TSOv4; 1366 1367 /* 1368 * Attach the interface. 1369 */ 1370 if_attach(ifp); 1371 ether_ifattach(ifp, enaddr); 1372 #if NRND > 0 1373 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1374 RND_TYPE_NET, 0); 1375 #endif 1376 1377 #ifdef WM_EVENT_COUNTERS 1378 /* Attach event counters. */ 1379 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1380 NULL, sc->sc_dev.dv_xname, "txsstall"); 1381 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1382 NULL, sc->sc_dev.dv_xname, "txdstall"); 1383 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1384 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1385 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1386 NULL, sc->sc_dev.dv_xname, "txdw"); 1387 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1388 NULL, sc->sc_dev.dv_xname, "txqe"); 1389 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1390 NULL, sc->sc_dev.dv_xname, "rxintr"); 1391 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1392 NULL, sc->sc_dev.dv_xname, "linkintr"); 1393 1394 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1395 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1396 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1397 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1398 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1399 NULL, sc->sc_dev.dv_xname, "txipsum"); 1400 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1401 NULL, sc->sc_dev.dv_xname, "txtusum"); 1402 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1403 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1404 1405 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1406 NULL, sc->sc_dev.dv_xname, "txtso"); 1407 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1408 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1409 1410 for (i = 0; i < WM_NTXSEGS; i++) { 1411 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1412 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1413 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1414 } 1415 1416 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1417 NULL, sc->sc_dev.dv_xname, "txdrop"); 1418 1419 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1420 NULL, sc->sc_dev.dv_xname, "tu"); 1421 1422 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1423 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1424 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1425 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1426 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1427 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1428 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1429 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1430 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1431 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1432 #endif /* WM_EVENT_COUNTERS */ 1433 1434 /* 1435 * Make sure the interface is shutdown during reboot. 1436 */ 1437 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1438 if (sc->sc_sdhook == NULL) 1439 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1440 sc->sc_dev.dv_xname); 1441 return; 1442 1443 /* 1444 * Free any resources we've allocated during the failed attach 1445 * attempt. Do this in reverse order and fall through. 1446 */ 1447 fail_5: 1448 for (i = 0; i < WM_NRXDESC; i++) { 1449 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1450 bus_dmamap_destroy(sc->sc_dmat, 1451 sc->sc_rxsoft[i].rxs_dmamap); 1452 } 1453 fail_4: 1454 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1455 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1456 bus_dmamap_destroy(sc->sc_dmat, 1457 sc->sc_txsoft[i].txs_dmamap); 1458 } 1459 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1460 fail_3: 1461 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1462 fail_2: 1463 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1464 cdata_size); 1465 fail_1: 1466 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1467 fail_0: 1468 return; 1469 } 1470 1471 /* 1472 * wm_shutdown: 1473 * 1474 * Make sure the interface is stopped at reboot time. 1475 */ 1476 static void 1477 wm_shutdown(void *arg) 1478 { 1479 struct wm_softc *sc = arg; 1480 1481 wm_stop(&sc->sc_ethercom.ec_if, 1); 1482 } 1483 1484 /* 1485 * wm_tx_offload: 1486 * 1487 * Set up TCP/IP checksumming parameters for the 1488 * specified packet. 1489 */ 1490 static int 1491 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1492 uint8_t *fieldsp) 1493 { 1494 struct mbuf *m0 = txs->txs_mbuf; 1495 struct livengood_tcpip_ctxdesc *t; 1496 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1497 struct ether_header *eh; 1498 int offset, iphl; 1499 uint8_t fields; 1500 1501 /* 1502 * XXX It would be nice if the mbuf pkthdr had offset 1503 * fields for the protocol headers. 1504 */ 1505 1506 eh = mtod(m0, struct ether_header *); 1507 switch (htons(eh->ether_type)) { 1508 case ETHERTYPE_IP: 1509 case ETHERTYPE_IPV6: 1510 offset = ETHER_HDR_LEN; 1511 break; 1512 1513 case ETHERTYPE_VLAN: 1514 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1515 break; 1516 1517 default: 1518 /* 1519 * Don't support this protocol or encapsulation. 1520 */ 1521 *fieldsp = 0; 1522 *cmdp = 0; 1523 return (0); 1524 } 1525 1526 if ((m0->m_pkthdr.csum_flags & 1527 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1528 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1529 } else { 1530 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1531 } 1532 1533 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1534 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1535 seg = 0; 1536 fields = 0; 1537 1538 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1539 int hlen = offset + iphl; 1540 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1541 if (__predict_false(m0->m_len < 1542 (hlen + sizeof(struct tcphdr)))) { 1543 /* 1544 * TCP/IP headers are not in the first mbuf; we need 1545 * to do this the slow and painful way. Let's just 1546 * hope this doesn't happen very often. 1547 */ 1548 struct ip ip; 1549 struct tcphdr th; 1550 1551 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1552 1553 m_copydata(m0, offset, sizeof(ip), &ip); 1554 m_copydata(m0, hlen, sizeof(th), &th); 1555 1556 ip.ip_len = 0; 1557 1558 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1559 sizeof(ip.ip_len), &ip.ip_len); 1560 1561 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1562 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1563 1564 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1565 sizeof(th.th_sum), &th.th_sum); 1566 1567 hlen += th.th_off << 2; 1568 } else { 1569 /* 1570 * TCP/IP headers are in the first mbuf; we can do 1571 * this the easy way. 1572 */ 1573 struct ip *ip = 1574 (struct ip *) (mtod(m0, caddr_t) + offset); 1575 struct tcphdr *th = 1576 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1577 1578 ip->ip_len = 0; 1579 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1580 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1581 1582 hlen += th->th_off << 2; 1583 } 1584 1585 cmd |= WTX_TCPIP_CMD_TSE; 1586 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1587 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1588 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1589 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1590 } 1591 1592 /* 1593 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1594 * offload feature, if we load the context descriptor, we 1595 * MUST provide valid values for IPCSS and TUCSS fields. 1596 */ 1597 1598 ipcs = WTX_TCPIP_IPCSS(offset) | 1599 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1600 WTX_TCPIP_IPCSE(offset + iphl - 1); 1601 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1602 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1603 fields |= WTX_IXSM; 1604 } 1605 1606 offset += iphl; 1607 1608 if (m0->m_pkthdr.csum_flags & 1609 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1610 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1611 fields |= WTX_TXSM; 1612 tucs = WTX_TCPIP_TUCSS(offset) | 1613 WTX_TCPIP_TUCSO(offset + 1614 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1615 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1616 } else if ((m0->m_pkthdr.csum_flags & 1617 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) { 1618 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1619 fields |= WTX_TXSM; 1620 tucs = WTX_TCPIP_TUCSS(offset) | 1621 WTX_TCPIP_TUCSO(offset + 1622 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1623 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1624 } else { 1625 /* Just initialize it to a valid TCP context. */ 1626 tucs = WTX_TCPIP_TUCSS(offset) | 1627 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1628 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1629 } 1630 1631 /* Fill in the context descriptor. */ 1632 t = (struct livengood_tcpip_ctxdesc *) 1633 &sc->sc_txdescs[sc->sc_txnext]; 1634 t->tcpip_ipcs = htole32(ipcs); 1635 t->tcpip_tucs = htole32(tucs); 1636 t->tcpip_cmdlen = htole32(cmdlen); 1637 t->tcpip_seg = htole32(seg); 1638 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1639 1640 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1641 txs->txs_ndesc++; 1642 1643 *cmdp = cmd; 1644 *fieldsp = fields; 1645 1646 return (0); 1647 } 1648 1649 static void 1650 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1651 { 1652 struct mbuf *m; 1653 int i; 1654 1655 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1656 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1657 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1658 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1659 m->m_data, m->m_len, m->m_flags); 1660 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1661 i, i == 1 ? "" : "s"); 1662 } 1663 1664 /* 1665 * wm_82547_txfifo_stall: 1666 * 1667 * Callout used to wait for the 82547 Tx FIFO to drain, 1668 * reset the FIFO pointers, and restart packet transmission. 1669 */ 1670 static void 1671 wm_82547_txfifo_stall(void *arg) 1672 { 1673 struct wm_softc *sc = arg; 1674 int s; 1675 1676 s = splnet(); 1677 1678 if (sc->sc_txfifo_stall) { 1679 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1680 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1681 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1682 /* 1683 * Packets have drained. Stop transmitter, reset 1684 * FIFO pointers, restart transmitter, and kick 1685 * the packet queue. 1686 */ 1687 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1688 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1689 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1690 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1691 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1692 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1693 CSR_WRITE(sc, WMREG_TCTL, tctl); 1694 CSR_WRITE_FLUSH(sc); 1695 1696 sc->sc_txfifo_head = 0; 1697 sc->sc_txfifo_stall = 0; 1698 wm_start(&sc->sc_ethercom.ec_if); 1699 } else { 1700 /* 1701 * Still waiting for packets to drain; try again in 1702 * another tick. 1703 */ 1704 callout_schedule(&sc->sc_txfifo_ch, 1); 1705 } 1706 } 1707 1708 splx(s); 1709 } 1710 1711 /* 1712 * wm_82547_txfifo_bugchk: 1713 * 1714 * Check for bug condition in the 82547 Tx FIFO. We need to 1715 * prevent enqueueing a packet that would wrap around the end 1716 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1717 * 1718 * We do this by checking the amount of space before the end 1719 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1720 * the Tx FIFO, wait for all remaining packets to drain, reset 1721 * the internal FIFO pointers to the beginning, and restart 1722 * transmission on the interface. 1723 */ 1724 #define WM_FIFO_HDR 0x10 1725 #define WM_82547_PAD_LEN 0x3e0 1726 static int 1727 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1728 { 1729 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1730 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1731 1732 /* Just return if already stalled. */ 1733 if (sc->sc_txfifo_stall) 1734 return (1); 1735 1736 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1737 /* Stall only occurs in half-duplex mode. */ 1738 goto send_packet; 1739 } 1740 1741 if (len >= WM_82547_PAD_LEN + space) { 1742 sc->sc_txfifo_stall = 1; 1743 callout_schedule(&sc->sc_txfifo_ch, 1); 1744 return (1); 1745 } 1746 1747 send_packet: 1748 sc->sc_txfifo_head += len; 1749 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1750 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1751 1752 return (0); 1753 } 1754 1755 /* 1756 * wm_start: [ifnet interface function] 1757 * 1758 * Start packet transmission on the interface. 1759 */ 1760 static void 1761 wm_start(struct ifnet *ifp) 1762 { 1763 struct wm_softc *sc = ifp->if_softc; 1764 struct mbuf *m0; 1765 #if 0 /* XXXJRT */ 1766 struct m_tag *mtag; 1767 #endif 1768 struct wm_txsoft *txs; 1769 bus_dmamap_t dmamap; 1770 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1771 bus_addr_t curaddr; 1772 bus_size_t seglen, curlen; 1773 uint32_t cksumcmd; 1774 uint8_t cksumfields; 1775 1776 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1777 return; 1778 1779 /* 1780 * Remember the previous number of free descriptors. 1781 */ 1782 ofree = sc->sc_txfree; 1783 1784 /* 1785 * Loop through the send queue, setting up transmit descriptors 1786 * until we drain the queue, or use up all available transmit 1787 * descriptors. 1788 */ 1789 for (;;) { 1790 /* Grab a packet off the queue. */ 1791 IFQ_POLL(&ifp->if_snd, m0); 1792 if (m0 == NULL) 1793 break; 1794 1795 DPRINTF(WM_DEBUG_TX, 1796 ("%s: TX: have packet to transmit: %p\n", 1797 sc->sc_dev.dv_xname, m0)); 1798 1799 /* Get a work queue entry. */ 1800 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1801 wm_txintr(sc); 1802 if (sc->sc_txsfree == 0) { 1803 DPRINTF(WM_DEBUG_TX, 1804 ("%s: TX: no free job descriptors\n", 1805 sc->sc_dev.dv_xname)); 1806 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1807 break; 1808 } 1809 } 1810 1811 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1812 dmamap = txs->txs_dmamap; 1813 1814 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1815 1816 /* 1817 * So says the Linux driver: 1818 * The controller does a simple calculation to make sure 1819 * there is enough room in the FIFO before initiating the 1820 * DMA for each buffer. The calc is: 1821 * 4 = ceil(buffer len / MSS) 1822 * To make sure we don't overrun the FIFO, adjust the max 1823 * buffer len if the MSS drops. 1824 */ 1825 dmamap->dm_maxsegsz = 1826 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1827 ? m0->m_pkthdr.segsz << 2 1828 : WTX_MAX_LEN; 1829 1830 /* 1831 * Load the DMA map. If this fails, the packet either 1832 * didn't fit in the allotted number of segments, or we 1833 * were short on resources. For the too-many-segments 1834 * case, we simply report an error and drop the packet, 1835 * since we can't sanely copy a jumbo packet to a single 1836 * buffer. 1837 */ 1838 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1839 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1840 if (error) { 1841 if (error == EFBIG) { 1842 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1843 log(LOG_ERR, "%s: Tx packet consumes too many " 1844 "DMA segments, dropping...\n", 1845 sc->sc_dev.dv_xname); 1846 IFQ_DEQUEUE(&ifp->if_snd, m0); 1847 wm_dump_mbuf_chain(sc, m0); 1848 m_freem(m0); 1849 continue; 1850 } 1851 /* 1852 * Short on resources, just stop for now. 1853 */ 1854 DPRINTF(WM_DEBUG_TX, 1855 ("%s: TX: dmamap load failed: %d\n", 1856 sc->sc_dev.dv_xname, error)); 1857 break; 1858 } 1859 1860 segs_needed = dmamap->dm_nsegs; 1861 if (use_tso) { 1862 /* For sentinel descriptor; see below. */ 1863 segs_needed++; 1864 } 1865 1866 /* 1867 * Ensure we have enough descriptors free to describe 1868 * the packet. Note, we always reserve one descriptor 1869 * at the end of the ring due to the semantics of the 1870 * TDT register, plus one more in the event we need 1871 * to load offload context. 1872 */ 1873 if (segs_needed > sc->sc_txfree - 2) { 1874 /* 1875 * Not enough free descriptors to transmit this 1876 * packet. We haven't committed anything yet, 1877 * so just unload the DMA map, put the packet 1878 * pack on the queue, and punt. Notify the upper 1879 * layer that there are no more slots left. 1880 */ 1881 DPRINTF(WM_DEBUG_TX, 1882 ("%s: TX: need %d (%d) descriptors, have %d\n", 1883 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1884 sc->sc_txfree - 1)); 1885 ifp->if_flags |= IFF_OACTIVE; 1886 bus_dmamap_unload(sc->sc_dmat, dmamap); 1887 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1888 break; 1889 } 1890 1891 /* 1892 * Check for 82547 Tx FIFO bug. We need to do this 1893 * once we know we can transmit the packet, since we 1894 * do some internal FIFO space accounting here. 1895 */ 1896 if (sc->sc_type == WM_T_82547 && 1897 wm_82547_txfifo_bugchk(sc, m0)) { 1898 DPRINTF(WM_DEBUG_TX, 1899 ("%s: TX: 82547 Tx FIFO bug detected\n", 1900 sc->sc_dev.dv_xname)); 1901 ifp->if_flags |= IFF_OACTIVE; 1902 bus_dmamap_unload(sc->sc_dmat, dmamap); 1903 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1904 break; 1905 } 1906 1907 IFQ_DEQUEUE(&ifp->if_snd, m0); 1908 1909 /* 1910 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1911 */ 1912 1913 DPRINTF(WM_DEBUG_TX, 1914 ("%s: TX: packet has %d (%d) DMA segments\n", 1915 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1916 1917 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1918 1919 /* 1920 * Store a pointer to the packet so that we can free it 1921 * later. 1922 * 1923 * Initially, we consider the number of descriptors the 1924 * packet uses the number of DMA segments. This may be 1925 * incremented by 1 if we do checksum offload (a descriptor 1926 * is used to set the checksum context). 1927 */ 1928 txs->txs_mbuf = m0; 1929 txs->txs_firstdesc = sc->sc_txnext; 1930 txs->txs_ndesc = segs_needed; 1931 1932 /* Set up offload parameters for this packet. */ 1933 if (m0->m_pkthdr.csum_flags & 1934 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 1935 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 1936 if (wm_tx_offload(sc, txs, &cksumcmd, 1937 &cksumfields) != 0) { 1938 /* Error message already displayed. */ 1939 bus_dmamap_unload(sc->sc_dmat, dmamap); 1940 continue; 1941 } 1942 } else { 1943 cksumcmd = 0; 1944 cksumfields = 0; 1945 } 1946 1947 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1948 1949 /* Sync the DMA map. */ 1950 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1951 BUS_DMASYNC_PREWRITE); 1952 1953 /* 1954 * Initialize the transmit descriptor. 1955 */ 1956 for (nexttx = sc->sc_txnext, seg = 0; 1957 seg < dmamap->dm_nsegs; seg++) { 1958 for (seglen = dmamap->dm_segs[seg].ds_len, 1959 curaddr = dmamap->dm_segs[seg].ds_addr; 1960 seglen != 0; 1961 curaddr += curlen, seglen -= curlen, 1962 nexttx = WM_NEXTTX(sc, nexttx)) { 1963 curlen = seglen; 1964 1965 /* 1966 * So says the Linux driver: 1967 * Work around for premature descriptor 1968 * write-backs in TSO mode. Append a 1969 * 4-byte sentinel descriptor. 1970 */ 1971 if (use_tso && 1972 seg == dmamap->dm_nsegs - 1 && 1973 curlen > 8) 1974 curlen -= 4; 1975 1976 wm_set_dma_addr( 1977 &sc->sc_txdescs[nexttx].wtx_addr, 1978 curaddr); 1979 sc->sc_txdescs[nexttx].wtx_cmdlen = 1980 htole32(cksumcmd | curlen); 1981 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1982 0; 1983 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1984 cksumfields; 1985 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1986 lasttx = nexttx; 1987 1988 DPRINTF(WM_DEBUG_TX, 1989 ("%s: TX: desc %d: low 0x%08lx, " 1990 "len 0x%04x\n", 1991 sc->sc_dev.dv_xname, nexttx, 1992 curaddr & 0xffffffffUL, (unsigned)curlen)); 1993 } 1994 } 1995 1996 KASSERT(lasttx != -1); 1997 1998 /* 1999 * Set up the command byte on the last descriptor of 2000 * the packet. If we're in the interrupt delay window, 2001 * delay the interrupt. 2002 */ 2003 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2004 htole32(WTX_CMD_EOP | WTX_CMD_RS); 2005 2006 #if 0 /* XXXJRT */ 2007 /* 2008 * If VLANs are enabled and the packet has a VLAN tag, set 2009 * up the descriptor to encapsulate the packet for us. 2010 * 2011 * This is only valid on the last descriptor of the packet. 2012 */ 2013 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 2014 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2015 htole32(WTX_CMD_VLE); 2016 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 2017 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 2018 } 2019 #endif /* XXXJRT */ 2020 2021 txs->txs_lastdesc = lasttx; 2022 2023 DPRINTF(WM_DEBUG_TX, 2024 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 2025 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 2026 2027 /* Sync the descriptors we're using. */ 2028 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 2029 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2030 2031 /* Give the packet to the chip. */ 2032 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 2033 2034 DPRINTF(WM_DEBUG_TX, 2035 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 2036 2037 DPRINTF(WM_DEBUG_TX, 2038 ("%s: TX: finished transmitting packet, job %d\n", 2039 sc->sc_dev.dv_xname, sc->sc_txsnext)); 2040 2041 /* Advance the tx pointer. */ 2042 sc->sc_txfree -= txs->txs_ndesc; 2043 sc->sc_txnext = nexttx; 2044 2045 sc->sc_txsfree--; 2046 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 2047 2048 #if NBPFILTER > 0 2049 /* Pass the packet to any BPF listeners. */ 2050 if (ifp->if_bpf) 2051 bpf_mtap(ifp->if_bpf, m0); 2052 #endif /* NBPFILTER > 0 */ 2053 } 2054 2055 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 2056 /* No more slots; notify upper layer. */ 2057 ifp->if_flags |= IFF_OACTIVE; 2058 } 2059 2060 if (sc->sc_txfree != ofree) { 2061 /* Set a watchdog timer in case the chip flakes out. */ 2062 ifp->if_timer = 5; 2063 } 2064 } 2065 2066 /* 2067 * wm_watchdog: [ifnet interface function] 2068 * 2069 * Watchdog timer handler. 2070 */ 2071 static void 2072 wm_watchdog(struct ifnet *ifp) 2073 { 2074 struct wm_softc *sc = ifp->if_softc; 2075 2076 /* 2077 * Since we're using delayed interrupts, sweep up 2078 * before we report an error. 2079 */ 2080 wm_txintr(sc); 2081 2082 if (sc->sc_txfree != WM_NTXDESC(sc)) { 2083 log(LOG_ERR, 2084 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 2085 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 2086 sc->sc_txnext); 2087 ifp->if_oerrors++; 2088 2089 /* Reset the interface. */ 2090 (void) wm_init(ifp); 2091 } 2092 2093 /* Try to get more packets going. */ 2094 wm_start(ifp); 2095 } 2096 2097 /* 2098 * wm_ioctl: [ifnet interface function] 2099 * 2100 * Handle control requests from the operator. 2101 */ 2102 static int 2103 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2104 { 2105 struct wm_softc *sc = ifp->if_softc; 2106 struct ifreq *ifr = (struct ifreq *) data; 2107 int s, error; 2108 2109 s = splnet(); 2110 2111 switch (cmd) { 2112 case SIOCSIFMEDIA: 2113 case SIOCGIFMEDIA: 2114 /* Flow control requires full-duplex mode. */ 2115 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2116 (ifr->ifr_media & IFM_FDX) == 0) 2117 ifr->ifr_media &= ~IFM_ETH_FMASK; 2118 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2119 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2120 /* We can do both TXPAUSE and RXPAUSE. */ 2121 ifr->ifr_media |= 2122 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2123 } 2124 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2125 } 2126 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2127 break; 2128 default: 2129 error = ether_ioctl(ifp, cmd, data); 2130 if (error == ENETRESET) { 2131 /* 2132 * Multicast list has changed; set the hardware filter 2133 * accordingly. 2134 */ 2135 if (ifp->if_flags & IFF_RUNNING) 2136 wm_set_filter(sc); 2137 error = 0; 2138 } 2139 break; 2140 } 2141 2142 /* Try to get more packets going. */ 2143 wm_start(ifp); 2144 2145 splx(s); 2146 return (error); 2147 } 2148 2149 /* 2150 * wm_intr: 2151 * 2152 * Interrupt service routine. 2153 */ 2154 static int 2155 wm_intr(void *arg) 2156 { 2157 struct wm_softc *sc = arg; 2158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2159 uint32_t icr; 2160 int handled = 0; 2161 2162 while (1 /* CONSTCOND */) { 2163 icr = CSR_READ(sc, WMREG_ICR); 2164 if ((icr & sc->sc_icr) == 0) 2165 break; 2166 2167 #if 0 /*NRND > 0*/ 2168 if (RND_ENABLED(&sc->rnd_source)) 2169 rnd_add_uint32(&sc->rnd_source, icr); 2170 #endif 2171 2172 handled = 1; 2173 2174 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2175 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2176 DPRINTF(WM_DEBUG_RX, 2177 ("%s: RX: got Rx intr 0x%08x\n", 2178 sc->sc_dev.dv_xname, 2179 icr & (ICR_RXDMT0|ICR_RXT0))); 2180 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2181 } 2182 #endif 2183 wm_rxintr(sc); 2184 2185 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2186 if (icr & ICR_TXDW) { 2187 DPRINTF(WM_DEBUG_TX, 2188 ("%s: TX: got TXDW interrupt\n", 2189 sc->sc_dev.dv_xname)); 2190 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2191 } 2192 #endif 2193 wm_txintr(sc); 2194 2195 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2196 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2197 wm_linkintr(sc, icr); 2198 } 2199 2200 if (icr & ICR_RXO) { 2201 ifp->if_ierrors++; 2202 #if defined(WM_DEBUG) 2203 log(LOG_WARNING, "%s: Receive overrun\n", 2204 sc->sc_dev.dv_xname); 2205 #endif /* defined(WM_DEBUG) */ 2206 } 2207 } 2208 2209 if (handled) { 2210 /* Try to get more packets going. */ 2211 wm_start(ifp); 2212 } 2213 2214 return (handled); 2215 } 2216 2217 /* 2218 * wm_txintr: 2219 * 2220 * Helper; handle transmit interrupts. 2221 */ 2222 static void 2223 wm_txintr(struct wm_softc *sc) 2224 { 2225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2226 struct wm_txsoft *txs; 2227 uint8_t status; 2228 int i; 2229 2230 ifp->if_flags &= ~IFF_OACTIVE; 2231 2232 /* 2233 * Go through the Tx list and free mbufs for those 2234 * frames which have been transmitted. 2235 */ 2236 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2237 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2238 txs = &sc->sc_txsoft[i]; 2239 2240 DPRINTF(WM_DEBUG_TX, 2241 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2242 2243 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2244 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2245 2246 status = 2247 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2248 if ((status & WTX_ST_DD) == 0) { 2249 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2250 BUS_DMASYNC_PREREAD); 2251 break; 2252 } 2253 2254 DPRINTF(WM_DEBUG_TX, 2255 ("%s: TX: job %d done: descs %d..%d\n", 2256 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2257 txs->txs_lastdesc)); 2258 2259 /* 2260 * XXX We should probably be using the statistics 2261 * XXX registers, but I don't know if they exist 2262 * XXX on chips before the i82544. 2263 */ 2264 2265 #ifdef WM_EVENT_COUNTERS 2266 if (status & WTX_ST_TU) 2267 WM_EVCNT_INCR(&sc->sc_ev_tu); 2268 #endif /* WM_EVENT_COUNTERS */ 2269 2270 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2271 ifp->if_oerrors++; 2272 if (status & WTX_ST_LC) 2273 log(LOG_WARNING, "%s: late collision\n", 2274 sc->sc_dev.dv_xname); 2275 else if (status & WTX_ST_EC) { 2276 ifp->if_collisions += 16; 2277 log(LOG_WARNING, "%s: excessive collisions\n", 2278 sc->sc_dev.dv_xname); 2279 } 2280 } else 2281 ifp->if_opackets++; 2282 2283 sc->sc_txfree += txs->txs_ndesc; 2284 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2285 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2286 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2287 m_freem(txs->txs_mbuf); 2288 txs->txs_mbuf = NULL; 2289 } 2290 2291 /* Update the dirty transmit buffer pointer. */ 2292 sc->sc_txsdirty = i; 2293 DPRINTF(WM_DEBUG_TX, 2294 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2295 2296 /* 2297 * If there are no more pending transmissions, cancel the watchdog 2298 * timer. 2299 */ 2300 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2301 ifp->if_timer = 0; 2302 } 2303 2304 /* 2305 * wm_rxintr: 2306 * 2307 * Helper; handle receive interrupts. 2308 */ 2309 static void 2310 wm_rxintr(struct wm_softc *sc) 2311 { 2312 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2313 struct wm_rxsoft *rxs; 2314 struct mbuf *m; 2315 int i, len; 2316 uint8_t status, errors; 2317 2318 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2319 rxs = &sc->sc_rxsoft[i]; 2320 2321 DPRINTF(WM_DEBUG_RX, 2322 ("%s: RX: checking descriptor %d\n", 2323 sc->sc_dev.dv_xname, i)); 2324 2325 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2326 2327 status = sc->sc_rxdescs[i].wrx_status; 2328 errors = sc->sc_rxdescs[i].wrx_errors; 2329 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2330 2331 if ((status & WRX_ST_DD) == 0) { 2332 /* 2333 * We have processed all of the receive descriptors. 2334 */ 2335 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2336 break; 2337 } 2338 2339 if (__predict_false(sc->sc_rxdiscard)) { 2340 DPRINTF(WM_DEBUG_RX, 2341 ("%s: RX: discarding contents of descriptor %d\n", 2342 sc->sc_dev.dv_xname, i)); 2343 WM_INIT_RXDESC(sc, i); 2344 if (status & WRX_ST_EOP) { 2345 /* Reset our state. */ 2346 DPRINTF(WM_DEBUG_RX, 2347 ("%s: RX: resetting rxdiscard -> 0\n", 2348 sc->sc_dev.dv_xname)); 2349 sc->sc_rxdiscard = 0; 2350 } 2351 continue; 2352 } 2353 2354 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2355 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2356 2357 m = rxs->rxs_mbuf; 2358 2359 /* 2360 * Add a new receive buffer to the ring. 2361 */ 2362 if (wm_add_rxbuf(sc, i) != 0) { 2363 /* 2364 * Failed, throw away what we've done so 2365 * far, and discard the rest of the packet. 2366 */ 2367 ifp->if_ierrors++; 2368 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2369 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2370 WM_INIT_RXDESC(sc, i); 2371 if ((status & WRX_ST_EOP) == 0) 2372 sc->sc_rxdiscard = 1; 2373 if (sc->sc_rxhead != NULL) 2374 m_freem(sc->sc_rxhead); 2375 WM_RXCHAIN_RESET(sc); 2376 DPRINTF(WM_DEBUG_RX, 2377 ("%s: RX: Rx buffer allocation failed, " 2378 "dropping packet%s\n", sc->sc_dev.dv_xname, 2379 sc->sc_rxdiscard ? " (discard)" : "")); 2380 continue; 2381 } 2382 2383 WM_RXCHAIN_LINK(sc, m); 2384 2385 m->m_len = len; 2386 2387 DPRINTF(WM_DEBUG_RX, 2388 ("%s: RX: buffer at %p len %d\n", 2389 sc->sc_dev.dv_xname, m->m_data, len)); 2390 2391 /* 2392 * If this is not the end of the packet, keep 2393 * looking. 2394 */ 2395 if ((status & WRX_ST_EOP) == 0) { 2396 sc->sc_rxlen += len; 2397 DPRINTF(WM_DEBUG_RX, 2398 ("%s: RX: not yet EOP, rxlen -> %d\n", 2399 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2400 continue; 2401 } 2402 2403 /* 2404 * Okay, we have the entire packet now. The chip is 2405 * configured to include the FCS (not all chips can 2406 * be configured to strip it), so we need to trim it. 2407 */ 2408 m->m_len -= ETHER_CRC_LEN; 2409 2410 *sc->sc_rxtailp = NULL; 2411 len = m->m_len + sc->sc_rxlen; 2412 m = sc->sc_rxhead; 2413 2414 WM_RXCHAIN_RESET(sc); 2415 2416 DPRINTF(WM_DEBUG_RX, 2417 ("%s: RX: have entire packet, len -> %d\n", 2418 sc->sc_dev.dv_xname, len)); 2419 2420 /* 2421 * If an error occurred, update stats and drop the packet. 2422 */ 2423 if (errors & 2424 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2425 ifp->if_ierrors++; 2426 if (errors & WRX_ER_SE) 2427 log(LOG_WARNING, "%s: symbol error\n", 2428 sc->sc_dev.dv_xname); 2429 else if (errors & WRX_ER_SEQ) 2430 log(LOG_WARNING, "%s: receive sequence error\n", 2431 sc->sc_dev.dv_xname); 2432 else if (errors & WRX_ER_CE) 2433 log(LOG_WARNING, "%s: CRC error\n", 2434 sc->sc_dev.dv_xname); 2435 m_freem(m); 2436 continue; 2437 } 2438 2439 /* 2440 * No errors. Receive the packet. 2441 */ 2442 m->m_pkthdr.rcvif = ifp; 2443 m->m_pkthdr.len = len; 2444 2445 #if 0 /* XXXJRT */ 2446 /* 2447 * If VLANs are enabled, VLAN packets have been unwrapped 2448 * for us. Associate the tag with the packet. 2449 */ 2450 if ((status & WRX_ST_VP) != 0) { 2451 VLAN_INPUT_TAG(ifp, m, 2452 le16toh(sc->sc_rxdescs[i].wrx_special, 2453 continue); 2454 } 2455 #endif /* XXXJRT */ 2456 2457 /* 2458 * Set up checksum info for this packet. 2459 */ 2460 if ((status & WRX_ST_IXSM) == 0) { 2461 if (status & WRX_ST_IPCS) { 2462 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2463 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2464 if (errors & WRX_ER_IPE) 2465 m->m_pkthdr.csum_flags |= 2466 M_CSUM_IPv4_BAD; 2467 } 2468 if (status & WRX_ST_TCPCS) { 2469 /* 2470 * Note: we don't know if this was TCP or UDP, 2471 * so we just set both bits, and expect the 2472 * upper layers to deal. 2473 */ 2474 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2475 m->m_pkthdr.csum_flags |= 2476 M_CSUM_TCPv4|M_CSUM_UDPv4; 2477 if (errors & WRX_ER_TCPE) 2478 m->m_pkthdr.csum_flags |= 2479 M_CSUM_TCP_UDP_BAD; 2480 } 2481 } 2482 2483 ifp->if_ipackets++; 2484 2485 #if NBPFILTER > 0 2486 /* Pass this up to any BPF listeners. */ 2487 if (ifp->if_bpf) 2488 bpf_mtap(ifp->if_bpf, m); 2489 #endif /* NBPFILTER > 0 */ 2490 2491 /* Pass it on. */ 2492 (*ifp->if_input)(ifp, m); 2493 } 2494 2495 /* Update the receive pointer. */ 2496 sc->sc_rxptr = i; 2497 2498 DPRINTF(WM_DEBUG_RX, 2499 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2500 } 2501 2502 /* 2503 * wm_linkintr: 2504 * 2505 * Helper; handle link interrupts. 2506 */ 2507 static void 2508 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2509 { 2510 uint32_t status; 2511 2512 /* 2513 * If we get a link status interrupt on a 1000BASE-T 2514 * device, just fall into the normal MII tick path. 2515 */ 2516 if (sc->sc_flags & WM_F_HAS_MII) { 2517 if (icr & ICR_LSC) { 2518 DPRINTF(WM_DEBUG_LINK, 2519 ("%s: LINK: LSC -> mii_tick\n", 2520 sc->sc_dev.dv_xname)); 2521 mii_tick(&sc->sc_mii); 2522 } else if (icr & ICR_RXSEQ) { 2523 DPRINTF(WM_DEBUG_LINK, 2524 ("%s: LINK Receive sequence error\n", 2525 sc->sc_dev.dv_xname)); 2526 } 2527 return; 2528 } 2529 2530 /* 2531 * If we are now receiving /C/, check for link again in 2532 * a couple of link clock ticks. 2533 */ 2534 if (icr & ICR_RXCFG) { 2535 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2536 sc->sc_dev.dv_xname)); 2537 sc->sc_tbi_anstate = 2; 2538 } 2539 2540 if (icr & ICR_LSC) { 2541 status = CSR_READ(sc, WMREG_STATUS); 2542 if (status & STATUS_LU) { 2543 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2544 sc->sc_dev.dv_xname, 2545 (status & STATUS_FD) ? "FDX" : "HDX")); 2546 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2547 sc->sc_fcrtl &= ~FCRTL_XONE; 2548 if (status & STATUS_FD) 2549 sc->sc_tctl |= 2550 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2551 else 2552 sc->sc_tctl |= 2553 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2554 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2555 sc->sc_fcrtl |= FCRTL_XONE; 2556 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2557 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2558 WMREG_OLD_FCRTL : WMREG_FCRTL, 2559 sc->sc_fcrtl); 2560 sc->sc_tbi_linkup = 1; 2561 } else { 2562 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2563 sc->sc_dev.dv_xname)); 2564 sc->sc_tbi_linkup = 0; 2565 } 2566 sc->sc_tbi_anstate = 2; 2567 wm_tbi_set_linkled(sc); 2568 } else if (icr & ICR_RXSEQ) { 2569 DPRINTF(WM_DEBUG_LINK, 2570 ("%s: LINK: Receive sequence error\n", 2571 sc->sc_dev.dv_xname)); 2572 } 2573 } 2574 2575 /* 2576 * wm_tick: 2577 * 2578 * One second timer, used to check link status, sweep up 2579 * completed transmit jobs, etc. 2580 */ 2581 static void 2582 wm_tick(void *arg) 2583 { 2584 struct wm_softc *sc = arg; 2585 int s; 2586 2587 s = splnet(); 2588 2589 if (sc->sc_type >= WM_T_82542_2_1) { 2590 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2591 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2592 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2593 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2594 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2595 } 2596 2597 if (sc->sc_flags & WM_F_HAS_MII) 2598 mii_tick(&sc->sc_mii); 2599 else 2600 wm_tbi_check_link(sc); 2601 2602 splx(s); 2603 2604 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2605 } 2606 2607 /* 2608 * wm_reset: 2609 * 2610 * Reset the i82542 chip. 2611 */ 2612 static void 2613 wm_reset(struct wm_softc *sc) 2614 { 2615 int i; 2616 2617 /* 2618 * Allocate on-chip memory according to the MTU size. 2619 * The Packet Buffer Allocation register must be written 2620 * before the chip is reset. 2621 */ 2622 switch (sc->sc_type) { 2623 case WM_T_82547: 2624 case WM_T_82547_2: 2625 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2626 PBA_22K : PBA_30K; 2627 sc->sc_txfifo_head = 0; 2628 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2629 sc->sc_txfifo_size = 2630 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2631 sc->sc_txfifo_stall = 0; 2632 break; 2633 case WM_T_82571: 2634 case WM_T_82572: 2635 sc->sc_pba = PBA_32K; 2636 break; 2637 case WM_T_82573: 2638 sc->sc_pba = PBA_12K; 2639 break; 2640 default: 2641 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2642 PBA_40K : PBA_48K; 2643 break; 2644 } 2645 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2646 2647 switch (sc->sc_type) { 2648 case WM_T_82544: 2649 case WM_T_82540: 2650 case WM_T_82545: 2651 case WM_T_82546: 2652 case WM_T_82541: 2653 case WM_T_82541_2: 2654 /* 2655 * On some chipsets, a reset through a memory-mapped write 2656 * cycle can cause the chip to reset before completing the 2657 * write cycle. This causes major headache that can be 2658 * avoided by issuing the reset via indirect register writes 2659 * through I/O space. 2660 * 2661 * So, if we successfully mapped the I/O BAR at attach time, 2662 * use that. Otherwise, try our luck with a memory-mapped 2663 * reset. 2664 */ 2665 if (sc->sc_flags & WM_F_IOH_VALID) 2666 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2667 else 2668 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2669 break; 2670 2671 case WM_T_82545_3: 2672 case WM_T_82546_3: 2673 /* Use the shadow control register on these chips. */ 2674 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2675 break; 2676 2677 default: 2678 /* Everything else can safely use the documented method. */ 2679 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2680 break; 2681 } 2682 delay(10000); 2683 2684 for (i = 0; i < 1000; i++) { 2685 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2686 return; 2687 delay(20); 2688 } 2689 2690 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2691 log(LOG_ERR, "%s: reset failed to complete\n", 2692 sc->sc_dev.dv_xname); 2693 } 2694 2695 /* 2696 * wm_init: [ifnet interface function] 2697 * 2698 * Initialize the interface. Must be called at splnet(). 2699 */ 2700 static int 2701 wm_init(struct ifnet *ifp) 2702 { 2703 struct wm_softc *sc = ifp->if_softc; 2704 struct wm_rxsoft *rxs; 2705 int i, error = 0; 2706 uint32_t reg; 2707 2708 /* 2709 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2710 * There is a small but measurable benefit to avoiding the adjusment 2711 * of the descriptor so that the headers are aligned, for normal mtu, 2712 * on such platforms. One possibility is that the DMA itself is 2713 * slightly more efficient if the front of the entire packet (instead 2714 * of the front of the headers) is aligned. 2715 * 2716 * Note we must always set align_tweak to 0 if we are using 2717 * jumbo frames. 2718 */ 2719 #ifdef __NO_STRICT_ALIGNMENT 2720 sc->sc_align_tweak = 0; 2721 #else 2722 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2723 sc->sc_align_tweak = 0; 2724 else 2725 sc->sc_align_tweak = 2; 2726 #endif /* __NO_STRICT_ALIGNMENT */ 2727 2728 /* Cancel any pending I/O. */ 2729 wm_stop(ifp, 0); 2730 2731 /* Reset the chip to a known state. */ 2732 wm_reset(sc); 2733 2734 /* Initialize the transmit descriptor ring. */ 2735 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2736 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2737 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2738 sc->sc_txfree = WM_NTXDESC(sc); 2739 sc->sc_txnext = 0; 2740 2741 if (sc->sc_type < WM_T_82543) { 2742 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2743 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2744 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2745 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2746 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2747 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2748 } else { 2749 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2750 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2751 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2752 CSR_WRITE(sc, WMREG_TDH, 0); 2753 CSR_WRITE(sc, WMREG_TDT, 0); 2754 CSR_WRITE(sc, WMREG_TIDV, 64); 2755 CSR_WRITE(sc, WMREG_TADV, 128); 2756 2757 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2758 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2759 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2760 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2761 } 2762 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2763 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2764 2765 /* Initialize the transmit job descriptors. */ 2766 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2767 sc->sc_txsoft[i].txs_mbuf = NULL; 2768 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2769 sc->sc_txsnext = 0; 2770 sc->sc_txsdirty = 0; 2771 2772 /* 2773 * Initialize the receive descriptor and receive job 2774 * descriptor rings. 2775 */ 2776 if (sc->sc_type < WM_T_82543) { 2777 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2778 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2779 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2780 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2781 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2782 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2783 2784 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2785 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2786 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2787 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2788 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2789 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2790 } else { 2791 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2792 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2793 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2794 CSR_WRITE(sc, WMREG_RDH, 0); 2795 CSR_WRITE(sc, WMREG_RDT, 0); 2796 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2797 CSR_WRITE(sc, WMREG_RADV, 128); 2798 } 2799 for (i = 0; i < WM_NRXDESC; i++) { 2800 rxs = &sc->sc_rxsoft[i]; 2801 if (rxs->rxs_mbuf == NULL) { 2802 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2803 log(LOG_ERR, "%s: unable to allocate or map rx " 2804 "buffer %d, error = %d\n", 2805 sc->sc_dev.dv_xname, i, error); 2806 /* 2807 * XXX Should attempt to run with fewer receive 2808 * XXX buffers instead of just failing. 2809 */ 2810 wm_rxdrain(sc); 2811 goto out; 2812 } 2813 } else 2814 WM_INIT_RXDESC(sc, i); 2815 } 2816 sc->sc_rxptr = 0; 2817 sc->sc_rxdiscard = 0; 2818 WM_RXCHAIN_RESET(sc); 2819 2820 /* 2821 * Clear out the VLAN table -- we don't use it (yet). 2822 */ 2823 CSR_WRITE(sc, WMREG_VET, 0); 2824 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2825 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2826 2827 /* 2828 * Set up flow-control parameters. 2829 * 2830 * XXX Values could probably stand some tuning. 2831 */ 2832 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2833 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2834 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2835 2836 sc->sc_fcrtl = FCRTL_DFLT; 2837 if (sc->sc_type < WM_T_82543) { 2838 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2839 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2840 } else { 2841 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2842 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2843 } 2844 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2845 2846 #if 0 /* XXXJRT */ 2847 /* Deal with VLAN enables. */ 2848 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2849 sc->sc_ctrl |= CTRL_VME; 2850 else 2851 #endif /* XXXJRT */ 2852 sc->sc_ctrl &= ~CTRL_VME; 2853 2854 /* Write the control registers. */ 2855 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2856 #if 0 2857 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2858 #endif 2859 2860 /* 2861 * Set up checksum offload parameters. 2862 */ 2863 reg = CSR_READ(sc, WMREG_RXCSUM); 2864 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2865 reg |= RXCSUM_IPOFL; 2866 else 2867 reg &= ~RXCSUM_IPOFL; 2868 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2869 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2870 else { 2871 reg &= ~RXCSUM_TUOFL; 2872 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2873 reg &= ~RXCSUM_IPOFL; 2874 } 2875 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2876 2877 /* 2878 * Set up the interrupt registers. 2879 */ 2880 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2881 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2882 ICR_RXO | ICR_RXT0; 2883 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2884 sc->sc_icr |= ICR_RXCFG; 2885 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2886 2887 /* Set up the inter-packet gap. */ 2888 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2889 2890 if (sc->sc_type >= WM_T_82543) { 2891 /* Set up the interrupt throttling register (units of 256ns) */ 2892 sc->sc_itr = 1000000000 / (7000 * 256); 2893 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2894 } 2895 2896 #if 0 /* XXXJRT */ 2897 /* Set the VLAN ethernetype. */ 2898 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2899 #endif 2900 2901 /* 2902 * Set up the transmit control register; we start out with 2903 * a collision distance suitable for FDX, but update it whe 2904 * we resolve the media type. 2905 */ 2906 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2907 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2908 if (sc->sc_type >= WM_T_82571) 2909 sc->sc_tctl |= TCTL_MULR; 2910 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2911 2912 /* Set the media. */ 2913 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2914 2915 /* 2916 * Set up the receive control register; we actually program 2917 * the register when we set the receive filter. Use multicast 2918 * address offset type 0. 2919 * 2920 * Only the i82544 has the ability to strip the incoming 2921 * CRC, so we don't enable that feature. 2922 */ 2923 sc->sc_mchash_type = 0; 2924 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF 2925 | RCTL_MO(sc->sc_mchash_type); 2926 2927 /* 82573 doesn't support jumbo frame */ 2928 if (sc->sc_type != WM_T_82573) 2929 sc->sc_rctl |= RCTL_LPE; 2930 2931 if (MCLBYTES == 2048) { 2932 sc->sc_rctl |= RCTL_2k; 2933 } else { 2934 if (sc->sc_type >= WM_T_82543) { 2935 switch(MCLBYTES) { 2936 case 4096: 2937 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2938 break; 2939 case 8192: 2940 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2941 break; 2942 case 16384: 2943 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2944 break; 2945 default: 2946 panic("wm_init: MCLBYTES %d unsupported", 2947 MCLBYTES); 2948 break; 2949 } 2950 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2951 } 2952 2953 /* Set the receive filter. */ 2954 wm_set_filter(sc); 2955 2956 /* Start the one second link check clock. */ 2957 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2958 2959 /* ...all done! */ 2960 ifp->if_flags |= IFF_RUNNING; 2961 ifp->if_flags &= ~IFF_OACTIVE; 2962 2963 out: 2964 if (error) 2965 log(LOG_ERR, "%s: interface not running\n", 2966 sc->sc_dev.dv_xname); 2967 return (error); 2968 } 2969 2970 /* 2971 * wm_rxdrain: 2972 * 2973 * Drain the receive queue. 2974 */ 2975 static void 2976 wm_rxdrain(struct wm_softc *sc) 2977 { 2978 struct wm_rxsoft *rxs; 2979 int i; 2980 2981 for (i = 0; i < WM_NRXDESC; i++) { 2982 rxs = &sc->sc_rxsoft[i]; 2983 if (rxs->rxs_mbuf != NULL) { 2984 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2985 m_freem(rxs->rxs_mbuf); 2986 rxs->rxs_mbuf = NULL; 2987 } 2988 } 2989 } 2990 2991 /* 2992 * wm_stop: [ifnet interface function] 2993 * 2994 * Stop transmission on the interface. 2995 */ 2996 static void 2997 wm_stop(struct ifnet *ifp, int disable) 2998 { 2999 struct wm_softc *sc = ifp->if_softc; 3000 struct wm_txsoft *txs; 3001 int i; 3002 3003 /* Stop the one second clock. */ 3004 callout_stop(&sc->sc_tick_ch); 3005 3006 /* Stop the 82547 Tx FIFO stall check timer. */ 3007 if (sc->sc_type == WM_T_82547) 3008 callout_stop(&sc->sc_txfifo_ch); 3009 3010 if (sc->sc_flags & WM_F_HAS_MII) { 3011 /* Down the MII. */ 3012 mii_down(&sc->sc_mii); 3013 } 3014 3015 /* Stop the transmit and receive processes. */ 3016 CSR_WRITE(sc, WMREG_TCTL, 0); 3017 CSR_WRITE(sc, WMREG_RCTL, 0); 3018 3019 /* 3020 * Clear the interrupt mask to ensure the device cannot assert its 3021 * interrupt line. 3022 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 3023 * any currently pending or shared interrupt. 3024 */ 3025 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3026 sc->sc_icr = 0; 3027 3028 /* Release any queued transmit buffers. */ 3029 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 3030 txs = &sc->sc_txsoft[i]; 3031 if (txs->txs_mbuf != NULL) { 3032 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3033 m_freem(txs->txs_mbuf); 3034 txs->txs_mbuf = NULL; 3035 } 3036 } 3037 3038 if (disable) 3039 wm_rxdrain(sc); 3040 3041 /* Mark the interface as down and cancel the watchdog timer. */ 3042 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3043 ifp->if_timer = 0; 3044 } 3045 3046 /* 3047 * wm_acquire_eeprom: 3048 * 3049 * Perform the EEPROM handshake required on some chips. 3050 */ 3051 static int 3052 wm_acquire_eeprom(struct wm_softc *sc) 3053 { 3054 uint32_t reg; 3055 int x; 3056 3057 /* always success */ 3058 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 3059 return 0; 3060 3061 if (wm_get_eeprom_semaphore(sc)) 3062 return 1; 3063 3064 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3065 reg = CSR_READ(sc, WMREG_EECD); 3066 3067 /* Request EEPROM access. */ 3068 reg |= EECD_EE_REQ; 3069 CSR_WRITE(sc, WMREG_EECD, reg); 3070 3071 /* ..and wait for it to be granted. */ 3072 for (x = 0; x < 1000; x++) { 3073 reg = CSR_READ(sc, WMREG_EECD); 3074 if (reg & EECD_EE_GNT) 3075 break; 3076 delay(5); 3077 } 3078 if ((reg & EECD_EE_GNT) == 0) { 3079 aprint_error("%s: could not acquire EEPROM GNT\n", 3080 sc->sc_dev.dv_xname); 3081 reg &= ~EECD_EE_REQ; 3082 CSR_WRITE(sc, WMREG_EECD, reg); 3083 wm_put_eeprom_semaphore(sc); 3084 return (1); 3085 } 3086 } 3087 3088 return (0); 3089 } 3090 3091 /* 3092 * wm_release_eeprom: 3093 * 3094 * Release the EEPROM mutex. 3095 */ 3096 static void 3097 wm_release_eeprom(struct wm_softc *sc) 3098 { 3099 uint32_t reg; 3100 3101 /* always success */ 3102 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 3103 return; 3104 3105 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3106 reg = CSR_READ(sc, WMREG_EECD); 3107 reg &= ~EECD_EE_REQ; 3108 CSR_WRITE(sc, WMREG_EECD, reg); 3109 } 3110 3111 wm_put_eeprom_semaphore(sc); 3112 } 3113 3114 /* 3115 * wm_eeprom_sendbits: 3116 * 3117 * Send a series of bits to the EEPROM. 3118 */ 3119 static void 3120 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 3121 { 3122 uint32_t reg; 3123 int x; 3124 3125 reg = CSR_READ(sc, WMREG_EECD); 3126 3127 for (x = nbits; x > 0; x--) { 3128 if (bits & (1U << (x - 1))) 3129 reg |= EECD_DI; 3130 else 3131 reg &= ~EECD_DI; 3132 CSR_WRITE(sc, WMREG_EECD, reg); 3133 delay(2); 3134 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3135 delay(2); 3136 CSR_WRITE(sc, WMREG_EECD, reg); 3137 delay(2); 3138 } 3139 } 3140 3141 /* 3142 * wm_eeprom_recvbits: 3143 * 3144 * Receive a series of bits from the EEPROM. 3145 */ 3146 static void 3147 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 3148 { 3149 uint32_t reg, val; 3150 int x; 3151 3152 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 3153 3154 val = 0; 3155 for (x = nbits; x > 0; x--) { 3156 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3157 delay(2); 3158 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 3159 val |= (1U << (x - 1)); 3160 CSR_WRITE(sc, WMREG_EECD, reg); 3161 delay(2); 3162 } 3163 *valp = val; 3164 } 3165 3166 /* 3167 * wm_read_eeprom_uwire: 3168 * 3169 * Read a word from the EEPROM using the MicroWire protocol. 3170 */ 3171 static int 3172 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3173 { 3174 uint32_t reg, val; 3175 int i; 3176 3177 for (i = 0; i < wordcnt; i++) { 3178 /* Clear SK and DI. */ 3179 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3180 CSR_WRITE(sc, WMREG_EECD, reg); 3181 3182 /* Set CHIP SELECT. */ 3183 reg |= EECD_CS; 3184 CSR_WRITE(sc, WMREG_EECD, reg); 3185 delay(2); 3186 3187 /* Shift in the READ command. */ 3188 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3189 3190 /* Shift in address. */ 3191 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3192 3193 /* Shift out the data. */ 3194 wm_eeprom_recvbits(sc, &val, 16); 3195 data[i] = val & 0xffff; 3196 3197 /* Clear CHIP SELECT. */ 3198 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3199 CSR_WRITE(sc, WMREG_EECD, reg); 3200 delay(2); 3201 } 3202 3203 return (0); 3204 } 3205 3206 /* 3207 * wm_spi_eeprom_ready: 3208 * 3209 * Wait for a SPI EEPROM to be ready for commands. 3210 */ 3211 static int 3212 wm_spi_eeprom_ready(struct wm_softc *sc) 3213 { 3214 uint32_t val; 3215 int usec; 3216 3217 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3218 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3219 wm_eeprom_recvbits(sc, &val, 8); 3220 if ((val & SPI_SR_RDY) == 0) 3221 break; 3222 } 3223 if (usec >= SPI_MAX_RETRIES) { 3224 aprint_error("%s: EEPROM failed to become ready\n", 3225 sc->sc_dev.dv_xname); 3226 return (1); 3227 } 3228 return (0); 3229 } 3230 3231 /* 3232 * wm_read_eeprom_spi: 3233 * 3234 * Read a work from the EEPROM using the SPI protocol. 3235 */ 3236 static int 3237 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3238 { 3239 uint32_t reg, val; 3240 int i; 3241 uint8_t opc; 3242 3243 /* Clear SK and CS. */ 3244 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3245 CSR_WRITE(sc, WMREG_EECD, reg); 3246 delay(2); 3247 3248 if (wm_spi_eeprom_ready(sc)) 3249 return (1); 3250 3251 /* Toggle CS to flush commands. */ 3252 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3253 delay(2); 3254 CSR_WRITE(sc, WMREG_EECD, reg); 3255 delay(2); 3256 3257 opc = SPI_OPC_READ; 3258 if (sc->sc_ee_addrbits == 8 && word >= 128) 3259 opc |= SPI_OPC_A8; 3260 3261 wm_eeprom_sendbits(sc, opc, 8); 3262 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3263 3264 for (i = 0; i < wordcnt; i++) { 3265 wm_eeprom_recvbits(sc, &val, 16); 3266 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3267 } 3268 3269 /* Raise CS and clear SK. */ 3270 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3271 CSR_WRITE(sc, WMREG_EECD, reg); 3272 delay(2); 3273 3274 return (0); 3275 } 3276 3277 #define EEPROM_CHECKSUM 0xBABA 3278 #define EEPROM_SIZE 0x0040 3279 3280 /* 3281 * wm_validate_eeprom_checksum 3282 * 3283 * The checksum is defined as the sum of the first 64 (16 bit) words. 3284 */ 3285 static int 3286 wm_validate_eeprom_checksum(struct wm_softc *sc) 3287 { 3288 uint16_t checksum; 3289 uint16_t eeprom_data; 3290 int i; 3291 3292 checksum = 0; 3293 3294 for (i = 0; i < EEPROM_SIZE; i++) { 3295 if (wm_read_eeprom(sc, i, 1, &eeprom_data)) 3296 return 1; 3297 checksum += eeprom_data; 3298 } 3299 3300 if (checksum != (uint16_t) EEPROM_CHECKSUM) 3301 return 1; 3302 3303 return 0; 3304 } 3305 3306 /* 3307 * wm_read_eeprom: 3308 * 3309 * Read data from the serial EEPROM. 3310 */ 3311 static int 3312 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3313 { 3314 int rv; 3315 3316 if (sc->sc_flags & WM_F_EEPROM_INVALID) 3317 return 1; 3318 3319 if (wm_acquire_eeprom(sc)) 3320 return 1; 3321 3322 if (sc->sc_flags & WM_F_EEPROM_EERDEEWR) 3323 rv = wm_read_eeprom_eerd(sc, word, wordcnt, data); 3324 else if (sc->sc_flags & WM_F_EEPROM_SPI) 3325 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3326 else 3327 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3328 3329 wm_release_eeprom(sc); 3330 return rv; 3331 } 3332 3333 static int 3334 wm_read_eeprom_eerd(struct wm_softc *sc, int offset, int wordcnt, 3335 uint16_t *data) 3336 { 3337 int i, eerd = 0; 3338 int error = 0; 3339 3340 for (i = 0; i < wordcnt; i++) { 3341 eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START; 3342 3343 CSR_WRITE(sc, WMREG_EERD, eerd); 3344 error = wm_poll_eerd_eewr_done(sc, WMREG_EERD); 3345 if (error != 0) 3346 break; 3347 3348 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT); 3349 } 3350 3351 return error; 3352 } 3353 3354 static int 3355 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw) 3356 { 3357 uint32_t attempts = 100000; 3358 uint32_t i, reg = 0; 3359 int32_t done = -1; 3360 3361 for (i = 0; i < attempts; i++) { 3362 reg = CSR_READ(sc, rw); 3363 3364 if (reg & EERD_DONE) { 3365 done = 0; 3366 break; 3367 } 3368 delay(5); 3369 } 3370 3371 return done; 3372 } 3373 3374 /* 3375 * wm_add_rxbuf: 3376 * 3377 * Add a receive buffer to the indiciated descriptor. 3378 */ 3379 static int 3380 wm_add_rxbuf(struct wm_softc *sc, int idx) 3381 { 3382 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3383 struct mbuf *m; 3384 int error; 3385 3386 MGETHDR(m, M_DONTWAIT, MT_DATA); 3387 if (m == NULL) 3388 return (ENOBUFS); 3389 3390 MCLGET(m, M_DONTWAIT); 3391 if ((m->m_flags & M_EXT) == 0) { 3392 m_freem(m); 3393 return (ENOBUFS); 3394 } 3395 3396 if (rxs->rxs_mbuf != NULL) 3397 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3398 3399 rxs->rxs_mbuf = m; 3400 3401 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3402 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3403 BUS_DMA_READ|BUS_DMA_NOWAIT); 3404 if (error) { 3405 /* XXX XXX XXX */ 3406 printf("%s: unable to load rx DMA map %d, error = %d\n", 3407 sc->sc_dev.dv_xname, idx, error); 3408 panic("wm_add_rxbuf"); 3409 } 3410 3411 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3412 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3413 3414 WM_INIT_RXDESC(sc, idx); 3415 3416 return (0); 3417 } 3418 3419 /* 3420 * wm_set_ral: 3421 * 3422 * Set an entery in the receive address list. 3423 */ 3424 static void 3425 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3426 { 3427 uint32_t ral_lo, ral_hi; 3428 3429 if (enaddr != NULL) { 3430 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3431 (enaddr[3] << 24); 3432 ral_hi = enaddr[4] | (enaddr[5] << 8); 3433 ral_hi |= RAL_AV; 3434 } else { 3435 ral_lo = 0; 3436 ral_hi = 0; 3437 } 3438 3439 if (sc->sc_type >= WM_T_82544) { 3440 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3441 ral_lo); 3442 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3443 ral_hi); 3444 } else { 3445 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3446 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3447 } 3448 } 3449 3450 /* 3451 * wm_mchash: 3452 * 3453 * Compute the hash of the multicast address for the 4096-bit 3454 * multicast filter. 3455 */ 3456 static uint32_t 3457 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3458 { 3459 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3460 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3461 uint32_t hash; 3462 3463 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3464 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3465 3466 return (hash & 0xfff); 3467 } 3468 3469 /* 3470 * wm_set_filter: 3471 * 3472 * Set up the receive filter. 3473 */ 3474 static void 3475 wm_set_filter(struct wm_softc *sc) 3476 { 3477 struct ethercom *ec = &sc->sc_ethercom; 3478 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3479 struct ether_multi *enm; 3480 struct ether_multistep step; 3481 bus_addr_t mta_reg; 3482 uint32_t hash, reg, bit; 3483 int i; 3484 3485 if (sc->sc_type >= WM_T_82544) 3486 mta_reg = WMREG_CORDOVA_MTA; 3487 else 3488 mta_reg = WMREG_MTA; 3489 3490 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3491 3492 if (ifp->if_flags & IFF_BROADCAST) 3493 sc->sc_rctl |= RCTL_BAM; 3494 if (ifp->if_flags & IFF_PROMISC) { 3495 sc->sc_rctl |= RCTL_UPE; 3496 goto allmulti; 3497 } 3498 3499 /* 3500 * Set the station address in the first RAL slot, and 3501 * clear the remaining slots. 3502 */ 3503 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3504 for (i = 1; i < WM_RAL_TABSIZE; i++) 3505 wm_set_ral(sc, NULL, i); 3506 3507 /* Clear out the multicast table. */ 3508 for (i = 0; i < WM_MC_TABSIZE; i++) 3509 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3510 3511 ETHER_FIRST_MULTI(step, ec, enm); 3512 while (enm != NULL) { 3513 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3514 /* 3515 * We must listen to a range of multicast addresses. 3516 * For now, just accept all multicasts, rather than 3517 * trying to set only those filter bits needed to match 3518 * the range. (At this time, the only use of address 3519 * ranges is for IP multicast routing, for which the 3520 * range is big enough to require all bits set.) 3521 */ 3522 goto allmulti; 3523 } 3524 3525 hash = wm_mchash(sc, enm->enm_addrlo); 3526 3527 reg = (hash >> 5) & 0x7f; 3528 bit = hash & 0x1f; 3529 3530 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3531 hash |= 1U << bit; 3532 3533 /* XXX Hardware bug?? */ 3534 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3535 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3536 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3537 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3538 } else 3539 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3540 3541 ETHER_NEXT_MULTI(step, enm); 3542 } 3543 3544 ifp->if_flags &= ~IFF_ALLMULTI; 3545 goto setit; 3546 3547 allmulti: 3548 ifp->if_flags |= IFF_ALLMULTI; 3549 sc->sc_rctl |= RCTL_MPE; 3550 3551 setit: 3552 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3553 } 3554 3555 /* 3556 * wm_tbi_mediainit: 3557 * 3558 * Initialize media for use on 1000BASE-X devices. 3559 */ 3560 static void 3561 wm_tbi_mediainit(struct wm_softc *sc) 3562 { 3563 const char *sep = ""; 3564 3565 if (sc->sc_type < WM_T_82543) 3566 sc->sc_tipg = TIPG_WM_DFLT; 3567 else 3568 sc->sc_tipg = TIPG_LG_DFLT; 3569 3570 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3571 wm_tbi_mediastatus); 3572 3573 /* 3574 * SWD Pins: 3575 * 3576 * 0 = Link LED (output) 3577 * 1 = Loss Of Signal (input) 3578 */ 3579 sc->sc_ctrl |= CTRL_SWDPIO(0); 3580 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3581 3582 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3583 3584 #define ADD(ss, mm, dd) \ 3585 do { \ 3586 aprint_normal("%s%s", sep, ss); \ 3587 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3588 sep = ", "; \ 3589 } while (/*CONSTCOND*/0) 3590 3591 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3592 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3593 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3594 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3595 aprint_normal("\n"); 3596 3597 #undef ADD 3598 3599 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3600 } 3601 3602 /* 3603 * wm_tbi_mediastatus: [ifmedia interface function] 3604 * 3605 * Get the current interface media status on a 1000BASE-X device. 3606 */ 3607 static void 3608 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3609 { 3610 struct wm_softc *sc = ifp->if_softc; 3611 uint32_t ctrl; 3612 3613 ifmr->ifm_status = IFM_AVALID; 3614 ifmr->ifm_active = IFM_ETHER; 3615 3616 if (sc->sc_tbi_linkup == 0) { 3617 ifmr->ifm_active |= IFM_NONE; 3618 return; 3619 } 3620 3621 ifmr->ifm_status |= IFM_ACTIVE; 3622 ifmr->ifm_active |= IFM_1000_SX; 3623 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3624 ifmr->ifm_active |= IFM_FDX; 3625 ctrl = CSR_READ(sc, WMREG_CTRL); 3626 if (ctrl & CTRL_RFCE) 3627 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3628 if (ctrl & CTRL_TFCE) 3629 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3630 } 3631 3632 /* 3633 * wm_tbi_mediachange: [ifmedia interface function] 3634 * 3635 * Set hardware to newly-selected media on a 1000BASE-X device. 3636 */ 3637 static int 3638 wm_tbi_mediachange(struct ifnet *ifp) 3639 { 3640 struct wm_softc *sc = ifp->if_softc; 3641 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3642 uint32_t status; 3643 int i; 3644 3645 sc->sc_txcw = ife->ifm_data; 3646 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3647 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3648 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3649 sc->sc_txcw |= TXCW_ANE; 3650 3651 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3652 delay(10000); 3653 3654 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3655 3656 sc->sc_tbi_anstate = 0; 3657 3658 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3659 /* Have signal; wait for the link to come up. */ 3660 for (i = 0; i < 50; i++) { 3661 delay(10000); 3662 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3663 break; 3664 } 3665 3666 status = CSR_READ(sc, WMREG_STATUS); 3667 if (status & STATUS_LU) { 3668 /* Link is up. */ 3669 DPRINTF(WM_DEBUG_LINK, 3670 ("%s: LINK: set media -> link up %s\n", 3671 sc->sc_dev.dv_xname, 3672 (status & STATUS_FD) ? "FDX" : "HDX")); 3673 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3674 sc->sc_fcrtl &= ~FCRTL_XONE; 3675 if (status & STATUS_FD) 3676 sc->sc_tctl |= 3677 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3678 else 3679 sc->sc_tctl |= 3680 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3681 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3682 sc->sc_fcrtl |= FCRTL_XONE; 3683 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3684 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3685 WMREG_OLD_FCRTL : WMREG_FCRTL, 3686 sc->sc_fcrtl); 3687 sc->sc_tbi_linkup = 1; 3688 } else { 3689 /* Link is down. */ 3690 DPRINTF(WM_DEBUG_LINK, 3691 ("%s: LINK: set media -> link down\n", 3692 sc->sc_dev.dv_xname)); 3693 sc->sc_tbi_linkup = 0; 3694 } 3695 } else { 3696 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3697 sc->sc_dev.dv_xname)); 3698 sc->sc_tbi_linkup = 0; 3699 } 3700 3701 wm_tbi_set_linkled(sc); 3702 3703 return (0); 3704 } 3705 3706 /* 3707 * wm_tbi_set_linkled: 3708 * 3709 * Update the link LED on 1000BASE-X devices. 3710 */ 3711 static void 3712 wm_tbi_set_linkled(struct wm_softc *sc) 3713 { 3714 3715 if (sc->sc_tbi_linkup) 3716 sc->sc_ctrl |= CTRL_SWDPIN(0); 3717 else 3718 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3719 3720 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3721 } 3722 3723 /* 3724 * wm_tbi_check_link: 3725 * 3726 * Check the link on 1000BASE-X devices. 3727 */ 3728 static void 3729 wm_tbi_check_link(struct wm_softc *sc) 3730 { 3731 uint32_t rxcw, ctrl, status; 3732 3733 if (sc->sc_tbi_anstate == 0) 3734 return; 3735 else if (sc->sc_tbi_anstate > 1) { 3736 DPRINTF(WM_DEBUG_LINK, 3737 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3738 sc->sc_tbi_anstate)); 3739 sc->sc_tbi_anstate--; 3740 return; 3741 } 3742 3743 sc->sc_tbi_anstate = 0; 3744 3745 rxcw = CSR_READ(sc, WMREG_RXCW); 3746 ctrl = CSR_READ(sc, WMREG_CTRL); 3747 status = CSR_READ(sc, WMREG_STATUS); 3748 3749 if ((status & STATUS_LU) == 0) { 3750 DPRINTF(WM_DEBUG_LINK, 3751 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3752 sc->sc_tbi_linkup = 0; 3753 } else { 3754 DPRINTF(WM_DEBUG_LINK, 3755 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3756 (status & STATUS_FD) ? "FDX" : "HDX")); 3757 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3758 sc->sc_fcrtl &= ~FCRTL_XONE; 3759 if (status & STATUS_FD) 3760 sc->sc_tctl |= 3761 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3762 else 3763 sc->sc_tctl |= 3764 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3765 if (ctrl & CTRL_TFCE) 3766 sc->sc_fcrtl |= FCRTL_XONE; 3767 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3768 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3769 WMREG_OLD_FCRTL : WMREG_FCRTL, 3770 sc->sc_fcrtl); 3771 sc->sc_tbi_linkup = 1; 3772 } 3773 3774 wm_tbi_set_linkled(sc); 3775 } 3776 3777 /* 3778 * wm_gmii_reset: 3779 * 3780 * Reset the PHY. 3781 */ 3782 static void 3783 wm_gmii_reset(struct wm_softc *sc) 3784 { 3785 uint32_t reg; 3786 3787 if (sc->sc_type >= WM_T_82544) { 3788 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3789 delay(20000); 3790 3791 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3792 delay(20000); 3793 } else { 3794 /* The PHY reset pin is active-low. */ 3795 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3796 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3797 CTRL_EXT_SWDPIN(4)); 3798 reg |= CTRL_EXT_SWDPIO(4); 3799 3800 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3801 delay(10); 3802 3803 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3804 delay(10); 3805 3806 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3807 delay(10); 3808 #if 0 3809 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3810 #endif 3811 } 3812 } 3813 3814 /* 3815 * wm_gmii_mediainit: 3816 * 3817 * Initialize media for use on 1000BASE-T devices. 3818 */ 3819 static void 3820 wm_gmii_mediainit(struct wm_softc *sc) 3821 { 3822 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3823 3824 /* We have MII. */ 3825 sc->sc_flags |= WM_F_HAS_MII; 3826 3827 sc->sc_tipg = TIPG_1000T_DFLT; 3828 3829 /* 3830 * Let the chip set speed/duplex on its own based on 3831 * signals from the PHY. 3832 */ 3833 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3834 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3835 3836 /* Initialize our media structures and probe the GMII. */ 3837 sc->sc_mii.mii_ifp = ifp; 3838 3839 if (sc->sc_type >= WM_T_82544) { 3840 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3841 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3842 } else { 3843 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3844 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3845 } 3846 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3847 3848 wm_gmii_reset(sc); 3849 3850 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3851 wm_gmii_mediastatus); 3852 3853 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3854 MII_OFFSET_ANY, MIIF_DOPAUSE); 3855 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3856 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3857 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3858 } else 3859 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3860 } 3861 3862 /* 3863 * wm_gmii_mediastatus: [ifmedia interface function] 3864 * 3865 * Get the current interface media status on a 1000BASE-T device. 3866 */ 3867 static void 3868 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3869 { 3870 struct wm_softc *sc = ifp->if_softc; 3871 3872 mii_pollstat(&sc->sc_mii); 3873 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3874 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3875 sc->sc_flowflags; 3876 } 3877 3878 /* 3879 * wm_gmii_mediachange: [ifmedia interface function] 3880 * 3881 * Set hardware to newly-selected media on a 1000BASE-T device. 3882 */ 3883 static int 3884 wm_gmii_mediachange(struct ifnet *ifp) 3885 { 3886 struct wm_softc *sc = ifp->if_softc; 3887 3888 if (ifp->if_flags & IFF_UP) 3889 mii_mediachg(&sc->sc_mii); 3890 return (0); 3891 } 3892 3893 #define MDI_IO CTRL_SWDPIN(2) 3894 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3895 #define MDI_CLK CTRL_SWDPIN(3) 3896 3897 static void 3898 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3899 { 3900 uint32_t i, v; 3901 3902 v = CSR_READ(sc, WMREG_CTRL); 3903 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3904 v |= MDI_DIR | CTRL_SWDPIO(3); 3905 3906 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3907 if (data & i) 3908 v |= MDI_IO; 3909 else 3910 v &= ~MDI_IO; 3911 CSR_WRITE(sc, WMREG_CTRL, v); 3912 delay(10); 3913 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3914 delay(10); 3915 CSR_WRITE(sc, WMREG_CTRL, v); 3916 delay(10); 3917 } 3918 } 3919 3920 static uint32_t 3921 i82543_mii_recvbits(struct wm_softc *sc) 3922 { 3923 uint32_t v, i, data = 0; 3924 3925 v = CSR_READ(sc, WMREG_CTRL); 3926 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3927 v |= CTRL_SWDPIO(3); 3928 3929 CSR_WRITE(sc, WMREG_CTRL, v); 3930 delay(10); 3931 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3932 delay(10); 3933 CSR_WRITE(sc, WMREG_CTRL, v); 3934 delay(10); 3935 3936 for (i = 0; i < 16; i++) { 3937 data <<= 1; 3938 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3939 delay(10); 3940 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3941 data |= 1; 3942 CSR_WRITE(sc, WMREG_CTRL, v); 3943 delay(10); 3944 } 3945 3946 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3947 delay(10); 3948 CSR_WRITE(sc, WMREG_CTRL, v); 3949 delay(10); 3950 3951 return (data); 3952 } 3953 3954 #undef MDI_IO 3955 #undef MDI_DIR 3956 #undef MDI_CLK 3957 3958 /* 3959 * wm_gmii_i82543_readreg: [mii interface function] 3960 * 3961 * Read a PHY register on the GMII (i82543 version). 3962 */ 3963 static int 3964 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3965 { 3966 struct wm_softc *sc = (void *) self; 3967 int rv; 3968 3969 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3970 i82543_mii_sendbits(sc, reg | (phy << 5) | 3971 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3972 rv = i82543_mii_recvbits(sc) & 0xffff; 3973 3974 DPRINTF(WM_DEBUG_GMII, 3975 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3976 sc->sc_dev.dv_xname, phy, reg, rv)); 3977 3978 return (rv); 3979 } 3980 3981 /* 3982 * wm_gmii_i82543_writereg: [mii interface function] 3983 * 3984 * Write a PHY register on the GMII (i82543 version). 3985 */ 3986 static void 3987 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3988 { 3989 struct wm_softc *sc = (void *) self; 3990 3991 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3992 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3993 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3994 (MII_COMMAND_START << 30), 32); 3995 } 3996 3997 /* 3998 * wm_gmii_i82544_readreg: [mii interface function] 3999 * 4000 * Read a PHY register on the GMII. 4001 */ 4002 static int 4003 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 4004 { 4005 struct wm_softc *sc = (void *) self; 4006 uint32_t mdic = 0; 4007 int i, rv; 4008 4009 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 4010 MDIC_REGADD(reg)); 4011 4012 for (i = 0; i < 100; i++) { 4013 mdic = CSR_READ(sc, WMREG_MDIC); 4014 if (mdic & MDIC_READY) 4015 break; 4016 delay(10); 4017 } 4018 4019 if ((mdic & MDIC_READY) == 0) { 4020 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 4021 sc->sc_dev.dv_xname, phy, reg); 4022 rv = 0; 4023 } else if (mdic & MDIC_E) { 4024 #if 0 /* This is normal if no PHY is present. */ 4025 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 4026 sc->sc_dev.dv_xname, phy, reg); 4027 #endif 4028 rv = 0; 4029 } else { 4030 rv = MDIC_DATA(mdic); 4031 if (rv == 0xffff) 4032 rv = 0; 4033 } 4034 4035 return (rv); 4036 } 4037 4038 /* 4039 * wm_gmii_i82544_writereg: [mii interface function] 4040 * 4041 * Write a PHY register on the GMII. 4042 */ 4043 static void 4044 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 4045 { 4046 struct wm_softc *sc = (void *) self; 4047 uint32_t mdic = 0; 4048 int i; 4049 4050 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 4051 MDIC_REGADD(reg) | MDIC_DATA(val)); 4052 4053 for (i = 0; i < 100; i++) { 4054 mdic = CSR_READ(sc, WMREG_MDIC); 4055 if (mdic & MDIC_READY) 4056 break; 4057 delay(10); 4058 } 4059 4060 if ((mdic & MDIC_READY) == 0) 4061 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 4062 sc->sc_dev.dv_xname, phy, reg); 4063 else if (mdic & MDIC_E) 4064 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 4065 sc->sc_dev.dv_xname, phy, reg); 4066 } 4067 4068 /* 4069 * wm_gmii_statchg: [mii interface function] 4070 * 4071 * Callback from MII layer when media changes. 4072 */ 4073 static void 4074 wm_gmii_statchg(struct device *self) 4075 { 4076 struct wm_softc *sc = (void *) self; 4077 struct mii_data *mii = &sc->sc_mii; 4078 4079 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 4080 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 4081 sc->sc_fcrtl &= ~FCRTL_XONE; 4082 4083 /* 4084 * Get flow control negotiation result. 4085 */ 4086 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 4087 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 4088 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 4089 mii->mii_media_active &= ~IFM_ETH_FMASK; 4090 } 4091 4092 if (sc->sc_flowflags & IFM_FLOW) { 4093 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 4094 sc->sc_ctrl |= CTRL_TFCE; 4095 sc->sc_fcrtl |= FCRTL_XONE; 4096 } 4097 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 4098 sc->sc_ctrl |= CTRL_RFCE; 4099 } 4100 4101 if (sc->sc_mii.mii_media_active & IFM_FDX) { 4102 DPRINTF(WM_DEBUG_LINK, 4103 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 4104 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4105 } else { 4106 DPRINTF(WM_DEBUG_LINK, 4107 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 4108 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 4109 } 4110 4111 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4112 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4113 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 4114 : WMREG_FCRTL, sc->sc_fcrtl); 4115 } 4116 4117 static int 4118 wm_is_onboard_nvm_eeprom(struct wm_softc *sc) 4119 { 4120 uint32_t eecd = 0; 4121 4122 if (sc->sc_type == WM_T_82573) { 4123 eecd = CSR_READ(sc, WMREG_EECD); 4124 4125 /* Isolate bits 15 & 16 */ 4126 eecd = ((eecd >> 15) & 0x03); 4127 4128 /* If both bits are set, device is Flash type */ 4129 if (eecd == 0x03) { 4130 return 0; 4131 } 4132 } 4133 return 1; 4134 } 4135 4136 static int 4137 wm_get_eeprom_semaphore(struct wm_softc *sc) 4138 { 4139 int32_t timeout; 4140 uint32_t swsm; 4141 4142 if ((sc->sc_flags & WM_F_EEPROM_SEMAPHORE) == 0) 4143 return 0; 4144 4145 /* Get the FW semaphore. */ 4146 timeout = 1000 + 1; /* XXX */ 4147 while (timeout) { 4148 swsm = CSR_READ(sc, WMREG_SWSM); 4149 swsm |= SWSM_SWESMBI; 4150 CSR_WRITE(sc, WMREG_SWSM, swsm); 4151 /* if we managed to set the bit we got the semaphore. */ 4152 swsm = CSR_READ(sc, WMREG_SWSM); 4153 if (swsm & SWSM_SWESMBI) 4154 break; 4155 4156 delay(50); 4157 timeout--; 4158 } 4159 4160 if (timeout == 0) { 4161 /* Release semaphores */ 4162 wm_put_eeprom_semaphore(sc); 4163 return 1; 4164 } 4165 4166 return 0; 4167 } 4168 4169 static void 4170 wm_put_eeprom_semaphore(struct wm_softc *sc) 4171 { 4172 uint32_t swsm; 4173 4174 if ((sc->sc_flags & WM_F_EEPROM_SEMAPHORE) == 0) 4175 return; 4176 4177 swsm = CSR_READ(sc, WMREG_SWSM); 4178 swsm &= ~(SWSM_SWESMBI); 4179 CSR_WRITE(sc, WMREG_SWSM, swsm); 4180 } 4181
Indexes created Tue Sep 23 13:09:54 GMT 2025