if_wm.c revision 1.121
1 /* $NetBSD: if_wm.c,v 1.121 2006/06/16 15:51:04 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.121 2006/06/16 15:51:04 msaitoh Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 100 #include <dev/pci/if_wmreg.h> 101 102 #ifdef WM_DEBUG 103 #define WM_DEBUG_LINK 0x01 104 #define WM_DEBUG_TX 0x02 105 #define WM_DEBUG_RX 0x04 106 #define WM_DEBUG_GMII 0x08 107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 108 109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 110 #else 111 #define DPRINTF(x, y) /* nothing */ 112 #endif /* WM_DEBUG */ 113 114 /* 115 * Transmit descriptor list size. Due to errata, we can only have 116 * 256 hardware descriptors in the ring on < 82544, but we use 4096 117 * on >= 82544. We tell the upper layers that they can queue a lot 118 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 119 * of them at a time. 120 * 121 * We allow up to 256 (!) DMA segments per packet. Pathological packet 122 * chains containing many small mbufs have been observed in zero-copy 123 * situations with jumbo frames. 124 */ 125 #define WM_NTXSEGS 256 126 #define WM_IFQUEUELEN 256 127 #define WM_TXQUEUELEN_MAX 64 128 #define WM_TXQUEUELEN_MAX_82547 16 129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 132 #define WM_NTXDESC_82542 256 133 #define WM_NTXDESC_82544 4096 134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 139 140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 141 142 /* 143 * Receive descriptor list size. We have one Rx buffer for normal 144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 145 * packet. We allocate 256 receive descriptors, each with a 2k 146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 147 */ 148 #define WM_NRXDESC 256 149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 152 153 /* 154 * Control structures are DMA'd to the i82542 chip. We allocate them in 155 * a single clump that maps to a single DMA segment to make several things 156 * easier. 157 */ 158 struct wm_control_data_82544 { 159 /* 160 * The receive descriptors. 161 */ 162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 163 164 /* 165 * The transmit descriptors. Put these at the end, because 166 * we might use a smaller number of them. 167 */ 168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 169 }; 170 171 struct wm_control_data_82542 { 172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 174 }; 175 176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 179 180 /* 181 * Software state for transmit jobs. 182 */ 183 struct wm_txsoft { 184 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t txs_dmamap; /* our DMA map */ 186 int txs_firstdesc; /* first descriptor in packet */ 187 int txs_lastdesc; /* last descriptor in packet */ 188 int txs_ndesc; /* # of descriptors used */ 189 }; 190 191 /* 192 * Software state for receive buffers. Each descriptor gets a 193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 194 * more than one buffer, we chain them together. 195 */ 196 struct wm_rxsoft { 197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t rxs_dmamap; /* our DMA map */ 199 }; 200 201 typedef enum { 202 WM_T_unknown = 0, 203 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 204 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 205 WM_T_82543, /* i82543 */ 206 WM_T_82544, /* i82544 */ 207 WM_T_82540, /* i82540 */ 208 WM_T_82545, /* i82545 */ 209 WM_T_82545_3, /* i82545 3.0+ */ 210 WM_T_82546, /* i82546 */ 211 WM_T_82546_3, /* i82546 3.0+ */ 212 WM_T_82541, /* i82541 */ 213 WM_T_82541_2, /* i82541 2.0+ */ 214 WM_T_82547, /* i82547 */ 215 WM_T_82547_2, /* i82547 2.0+ */ 216 WM_T_82571, /* i82571 */ 217 WM_T_82572, /* i82572 */ 218 WM_T_82573, /* i82573 */ 219 } wm_chip_type; 220 221 /* 222 * Software state per device. 223 */ 224 struct wm_softc { 225 struct device sc_dev; /* generic device information */ 226 bus_space_tag_t sc_st; /* bus space tag */ 227 bus_space_handle_t sc_sh; /* bus space handle */ 228 bus_space_tag_t sc_iot; /* I/O space tag */ 229 bus_space_handle_t sc_ioh; /* I/O space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 wm_chip_type sc_type; /* chip type */ 235 int sc_flags; /* flags; see below */ 236 int sc_bus_speed; /* PCI/PCIX bus speed */ 237 int sc_pcix_offset; /* PCIX capability register offset */ 238 int sc_flowflags; /* 802.3x flow control flags */ 239 240 void *sc_ih; /* interrupt cookie */ 241 242 int sc_ee_addrbits; /* EEPROM address bits */ 243 244 struct mii_data sc_mii; /* MII/media information */ 245 246 struct callout sc_tick_ch; /* tick callout */ 247 248 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 249 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 250 251 int sc_align_tweak; 252 253 /* 254 * Software state for the transmit and receive descriptors. 255 */ 256 int sc_txnum; /* must be a power of two */ 257 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 258 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 259 260 /* 261 * Control data structures. 262 */ 263 int sc_ntxdesc; /* must be a power of two */ 264 struct wm_control_data_82544 *sc_control_data; 265 #define sc_txdescs sc_control_data->wcd_txdescs 266 #define sc_rxdescs sc_control_data->wcd_rxdescs 267 268 #ifdef WM_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 272 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 273 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 274 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 275 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 276 struct evcnt sc_ev_linkintr; /* Link interrupts */ 277 278 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 279 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 280 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 281 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 282 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 283 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 284 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 285 286 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 287 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 288 289 struct evcnt sc_ev_tu; /* Tx underrun */ 290 291 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 292 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 293 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 294 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 295 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 296 #endif /* WM_EVENT_COUNTERS */ 297 298 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 299 300 int sc_txfree; /* number of free Tx descriptors */ 301 int sc_txnext; /* next ready Tx descriptor */ 302 303 int sc_txsfree; /* number of free Tx jobs */ 304 int sc_txsnext; /* next free Tx job */ 305 int sc_txsdirty; /* dirty Tx jobs */ 306 307 /* These 5 variables are used only on the 82547. */ 308 int sc_txfifo_size; /* Tx FIFO size */ 309 int sc_txfifo_head; /* current head of FIFO */ 310 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 311 int sc_txfifo_stall; /* Tx FIFO is stalled */ 312 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 313 314 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 315 316 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 317 int sc_rxdiscard; 318 int sc_rxlen; 319 struct mbuf *sc_rxhead; 320 struct mbuf *sc_rxtail; 321 struct mbuf **sc_rxtailp; 322 323 uint32_t sc_ctrl; /* prototype CTRL register */ 324 #if 0 325 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 326 #endif 327 uint32_t sc_icr; /* prototype interrupt bits */ 328 uint32_t sc_itr; /* prototype intr throttling reg */ 329 uint32_t sc_tctl; /* prototype TCTL register */ 330 uint32_t sc_rctl; /* prototype RCTL register */ 331 uint32_t sc_txcw; /* prototype TXCW register */ 332 uint32_t sc_tipg; /* prototype TIPG register */ 333 uint32_t sc_fcrtl; /* prototype FCRTL register */ 334 uint32_t sc_pba; /* prototype PBA register */ 335 336 int sc_tbi_linkup; /* TBI link status */ 337 int sc_tbi_anstate; /* autonegotiation state */ 338 339 int sc_mchash_type; /* multicast filter offset */ 340 341 #if NRND > 0 342 rndsource_element_t rnd_source; /* random source */ 343 #endif 344 }; 345 346 #define WM_RXCHAIN_RESET(sc) \ 347 do { \ 348 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 349 *(sc)->sc_rxtailp = NULL; \ 350 (sc)->sc_rxlen = 0; \ 351 } while (/*CONSTCOND*/0) 352 353 #define WM_RXCHAIN_LINK(sc, m) \ 354 do { \ 355 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 356 (sc)->sc_rxtailp = &(m)->m_next; \ 357 } while (/*CONSTCOND*/0) 358 359 /* sc_flags */ 360 #define WM_F_HAS_MII 0x001 /* has MII */ 361 #define WM_F_EEPROM_HANDSHAKE 0x002 /* requires EEPROM handshake */ 362 #define WM_F_EEPROM_SEMAPHORE 0x004 /* EEPROM with semaphore */ 363 #define WM_F_EEPROM_EERDEEWR 0x008 /* EEPROM access via EERD/EEWR */ 364 #define WM_F_EEPROM_SPI 0x010 /* EEPROM is SPI */ 365 #define WM_F_EEPROM_FLASH 0x020 /* EEPROM is FLASH */ 366 #define WM_F_EEPROM_INVALID 0x040 /* EEPROM not present (bad checksum) */ 367 #define WM_F_IOH_VALID 0x080 /* I/O handle is valid */ 368 #define WM_F_BUS64 0x100 /* bus is 64-bit */ 369 #define WM_F_PCIX 0x200 /* bus is PCI-X */ 370 #define WM_F_CSA 0x400 /* bus is CSA */ 371 #define WM_F_PCIE 0x800 /* bus is PCI-Express */ 372 373 #ifdef WM_EVENT_COUNTERS 374 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 375 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 376 #else 377 #define WM_EVCNT_INCR(ev) /* nothing */ 378 #define WM_EVCNT_ADD(ev, val) /* nothing */ 379 #endif 380 381 #define CSR_READ(sc, reg) \ 382 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 383 #define CSR_WRITE(sc, reg, val) \ 384 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 385 #define CSR_WRITE_FLUSH(sc) \ 386 (void) CSR_READ((sc), WMREG_STATUS) 387 388 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 389 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 390 391 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 392 #define WM_CDTXADDR_HI(sc, x) \ 393 (sizeof(bus_addr_t) == 8 ? \ 394 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 395 396 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 397 #define WM_CDRXADDR_HI(sc, x) \ 398 (sizeof(bus_addr_t) == 8 ? \ 399 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 400 401 #define WM_CDTXSYNC(sc, x, n, ops) \ 402 do { \ 403 int __x, __n; \ 404 \ 405 __x = (x); \ 406 __n = (n); \ 407 \ 408 /* If it will wrap around, sync to the end of the ring. */ \ 409 if ((__x + __n) > WM_NTXDESC(sc)) { \ 410 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 411 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 412 (WM_NTXDESC(sc) - __x), (ops)); \ 413 __n -= (WM_NTXDESC(sc) - __x); \ 414 __x = 0; \ 415 } \ 416 \ 417 /* Now sync whatever is left. */ \ 418 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 419 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 420 } while (/*CONSTCOND*/0) 421 422 #define WM_CDRXSYNC(sc, x, ops) \ 423 do { \ 424 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 425 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 426 } while (/*CONSTCOND*/0) 427 428 #define WM_INIT_RXDESC(sc, x) \ 429 do { \ 430 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 431 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 432 struct mbuf *__m = __rxs->rxs_mbuf; \ 433 \ 434 /* \ 435 * Note: We scoot the packet forward 2 bytes in the buffer \ 436 * so that the payload after the Ethernet header is aligned \ 437 * to a 4-byte boundary. \ 438 * \ 439 * XXX BRAINDAMAGE ALERT! \ 440 * The stupid chip uses the same size for every buffer, which \ 441 * is set in the Receive Control register. We are using the 2K \ 442 * size option, but what we REALLY want is (2K - 2)! For this \ 443 * reason, we can't "scoot" packets longer than the standard \ 444 * Ethernet MTU. On strict-alignment platforms, if the total \ 445 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 446 * the upper layer copy the headers. \ 447 */ \ 448 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 449 \ 450 wm_set_dma_addr(&__rxd->wrx_addr, \ 451 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 452 __rxd->wrx_len = 0; \ 453 __rxd->wrx_cksum = 0; \ 454 __rxd->wrx_status = 0; \ 455 __rxd->wrx_errors = 0; \ 456 __rxd->wrx_special = 0; \ 457 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 458 \ 459 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 460 } while (/*CONSTCOND*/0) 461 462 static void wm_start(struct ifnet *); 463 static void wm_watchdog(struct ifnet *); 464 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 465 static int wm_init(struct ifnet *); 466 static void wm_stop(struct ifnet *, int); 467 468 static void wm_shutdown(void *); 469 470 static void wm_reset(struct wm_softc *); 471 static void wm_rxdrain(struct wm_softc *); 472 static int wm_add_rxbuf(struct wm_softc *, int); 473 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 474 static int wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *); 475 static int wm_validate_eeprom_checksum(struct wm_softc *); 476 static void wm_tick(void *); 477 478 static void wm_set_filter(struct wm_softc *); 479 480 static int wm_intr(void *); 481 static void wm_txintr(struct wm_softc *); 482 static void wm_rxintr(struct wm_softc *); 483 static void wm_linkintr(struct wm_softc *, uint32_t); 484 485 static void wm_tbi_mediainit(struct wm_softc *); 486 static int wm_tbi_mediachange(struct ifnet *); 487 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 488 489 static void wm_tbi_set_linkled(struct wm_softc *); 490 static void wm_tbi_check_link(struct wm_softc *); 491 492 static void wm_gmii_reset(struct wm_softc *); 493 494 static int wm_gmii_i82543_readreg(struct device *, int, int); 495 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 496 497 static int wm_gmii_i82544_readreg(struct device *, int, int); 498 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 499 500 static void wm_gmii_statchg(struct device *); 501 502 static void wm_gmii_mediainit(struct wm_softc *); 503 static int wm_gmii_mediachange(struct ifnet *); 504 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 505 506 static int wm_match(struct device *, struct cfdata *, void *); 507 static void wm_attach(struct device *, struct device *, void *); 508 static int wm_is_onboard_nvm_eeprom(struct wm_softc *); 509 static int wm_get_eeprom_semaphore(struct wm_softc *); 510 static void wm_put_eeprom_semaphore(struct wm_softc *); 511 static int wm_poll_eerd_eewr_done(struct wm_softc *, int); 512 513 CFATTACH_DECL(wm, sizeof(struct wm_softc), 514 wm_match, wm_attach, NULL, NULL); 515 516 static void wm_82547_txfifo_stall(void *); 517 518 /* 519 * Devices supported by this driver. 520 */ 521 static const struct wm_product { 522 pci_vendor_id_t wmp_vendor; 523 pci_product_id_t wmp_product; 524 const char *wmp_name; 525 wm_chip_type wmp_type; 526 int wmp_flags; 527 #define WMP_F_1000X 0x01 528 #define WMP_F_1000T 0x02 529 } wm_products[] = { 530 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 531 "Intel i82542 1000BASE-X Ethernet", 532 WM_T_82542_2_1, WMP_F_1000X }, 533 534 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 535 "Intel i82543GC 1000BASE-X Ethernet", 536 WM_T_82543, WMP_F_1000X }, 537 538 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 539 "Intel i82543GC 1000BASE-T Ethernet", 540 WM_T_82543, WMP_F_1000T }, 541 542 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 543 "Intel i82544EI 1000BASE-T Ethernet", 544 WM_T_82544, WMP_F_1000T }, 545 546 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 547 "Intel i82544EI 1000BASE-X Ethernet", 548 WM_T_82544, WMP_F_1000X }, 549 550 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 551 "Intel i82544GC 1000BASE-T Ethernet", 552 WM_T_82544, WMP_F_1000T }, 553 554 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 555 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 556 WM_T_82544, WMP_F_1000T }, 557 558 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 559 "Intel i82540EM 1000BASE-T Ethernet", 560 WM_T_82540, WMP_F_1000T }, 561 562 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 563 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 564 WM_T_82540, WMP_F_1000T }, 565 566 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 567 "Intel i82540EP 1000BASE-T Ethernet", 568 WM_T_82540, WMP_F_1000T }, 569 570 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 571 "Intel i82540EP 1000BASE-T Ethernet", 572 WM_T_82540, WMP_F_1000T }, 573 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 575 "Intel i82540EP 1000BASE-T Ethernet", 576 WM_T_82540, WMP_F_1000T }, 577 578 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 579 "Intel i82545EM 1000BASE-T Ethernet", 580 WM_T_82545, WMP_F_1000T }, 581 582 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 583 "Intel i82545GM 1000BASE-T Ethernet", 584 WM_T_82545_3, WMP_F_1000T }, 585 586 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 587 "Intel i82545GM 1000BASE-X Ethernet", 588 WM_T_82545_3, WMP_F_1000X }, 589 #if 0 590 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 591 "Intel i82545GM Gigabit Ethernet (SERDES)", 592 WM_T_82545_3, WMP_F_SERDES }, 593 #endif 594 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 595 "Intel i82546EB 1000BASE-T Ethernet", 596 WM_T_82546, WMP_F_1000T }, 597 598 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 599 "Intel i82546EB 1000BASE-T Ethernet", 600 WM_T_82546, WMP_F_1000T }, 601 602 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 603 "Intel i82545EM 1000BASE-X Ethernet", 604 WM_T_82545, WMP_F_1000X }, 605 606 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 607 "Intel i82546EB 1000BASE-X Ethernet", 608 WM_T_82546, WMP_F_1000X }, 609 610 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 611 "Intel i82546GB 1000BASE-T Ethernet", 612 WM_T_82546_3, WMP_F_1000T }, 613 614 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 615 "Intel i82546GB 1000BASE-X Ethernet", 616 WM_T_82546_3, WMP_F_1000X }, 617 #if 0 618 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 619 "Intel i82546GB Gigabit Ethernet (SERDES)", 620 WM_T_82546_3, WMP_F_SERDES }, 621 #endif 622 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, 623 "Intel PRO/1000MT (82546GB)", 624 WM_T_82546_3, WMP_F_1000T }, 625 626 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 627 "Intel i82541EI 1000BASE-T Ethernet", 628 WM_T_82541, WMP_F_1000T }, 629 630 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, 631 "Intel i82541ER (LOM) 1000BASE-T Ethernet", 632 WM_T_82541, WMP_F_1000T }, 633 634 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 635 "Intel i82541EI Mobile 1000BASE-T Ethernet", 636 WM_T_82541, WMP_F_1000T }, 637 638 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 639 "Intel i82541ER 1000BASE-T Ethernet", 640 WM_T_82541_2, WMP_F_1000T }, 641 642 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 643 "Intel i82541GI 1000BASE-T Ethernet", 644 WM_T_82541_2, WMP_F_1000T }, 645 646 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 647 "Intel i82541GI Mobile 1000BASE-T Ethernet", 648 WM_T_82541_2, WMP_F_1000T }, 649 650 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 651 "Intel i82541PI 1000BASE-T Ethernet", 652 WM_T_82541_2, WMP_F_1000T }, 653 654 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 655 "Intel i82547EI 1000BASE-T Ethernet", 656 WM_T_82547, WMP_F_1000T }, 657 658 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, 659 "Intel i82547EI Moblie 1000BASE-T Ethernet", 660 WM_T_82547, WMP_F_1000T }, 661 662 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 663 "Intel i82547GI 1000BASE-T Ethernet", 664 WM_T_82547_2, WMP_F_1000T }, 665 666 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, 667 "Intel PRO/1000 PT (82571EB)", 668 WM_T_82571, WMP_F_1000T }, 669 670 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, 671 "Intel PRO/1000 PF (82571EB)", 672 WM_T_82571, WMP_F_1000X }, 673 #if 0 674 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, 675 "Intel PRO/1000 PB (82571EB)", 676 WM_T_82571, WMP_F_SERDES }, 677 #endif 678 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, 679 "Intel i82572EI 1000baseT Ethernet", 680 WM_T_82572, WMP_F_1000T }, 681 682 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, 683 "Intel i82572EI 1000baseX Ethernet", 684 WM_T_82572, WMP_F_1000X }, 685 #if 0 686 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, 687 "Intel i82572EI Gigabit Ethernet (SERDES)", 688 WM_T_82572, WMP_F_SERDES }, 689 #endif 690 691 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, 692 "Intel i82572EI 1000baseT Ethernet", 693 WM_T_82572, WMP_F_1000T }, 694 695 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, 696 "Intel i82573E", 697 WM_T_82573, WMP_F_1000T }, 698 699 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, 700 "Intel i82573E IAMT", 701 WM_T_82573, WMP_F_1000T }, 702 703 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, 704 "Intel i82573L Gigabit Ethernet", 705 WM_T_82573, WMP_F_1000T }, 706 707 { 0, 0, 708 NULL, 709 0, 0 }, 710 }; 711 712 #ifdef WM_EVENT_COUNTERS 713 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 714 #endif /* WM_EVENT_COUNTERS */ 715 716 #if 0 /* Not currently used */ 717 static inline uint32_t 718 wm_io_read(struct wm_softc *sc, int reg) 719 { 720 721 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 722 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 723 } 724 #endif 725 726 static inline void 727 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 728 { 729 730 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 731 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 732 } 733 734 static inline void 735 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 736 { 737 wa->wa_low = htole32(v & 0xffffffffU); 738 if (sizeof(bus_addr_t) == 8) 739 wa->wa_high = htole32((uint64_t) v >> 32); 740 else 741 wa->wa_high = 0; 742 } 743 744 static const struct wm_product * 745 wm_lookup(const struct pci_attach_args *pa) 746 { 747 const struct wm_product *wmp; 748 749 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 750 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 751 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 752 return (wmp); 753 } 754 return (NULL); 755 } 756 757 static int 758 wm_match(struct device *parent, struct cfdata *cf, void *aux) 759 { 760 struct pci_attach_args *pa = aux; 761 762 if (wm_lookup(pa) != NULL) 763 return (1); 764 765 return (0); 766 } 767 768 static void 769 wm_attach(struct device *parent, struct device *self, void *aux) 770 { 771 struct wm_softc *sc = (void *) self; 772 struct pci_attach_args *pa = aux; 773 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 774 pci_chipset_tag_t pc = pa->pa_pc; 775 pci_intr_handle_t ih; 776 size_t cdata_size; 777 const char *intrstr = NULL; 778 const char *eetype; 779 bus_space_tag_t memt; 780 bus_space_handle_t memh; 781 bus_dma_segment_t seg; 782 int memh_valid; 783 int i, rseg, error; 784 const struct wm_product *wmp; 785 prop_data_t ea; 786 prop_number_t pn; 787 uint8_t enaddr[ETHER_ADDR_LEN]; 788 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 789 pcireg_t preg, memtype; 790 uint32_t reg; 791 int pmreg; 792 793 callout_init(&sc->sc_tick_ch); 794 795 wmp = wm_lookup(pa); 796 if (wmp == NULL) { 797 printf("\n"); 798 panic("wm_attach: impossible"); 799 } 800 801 if (pci_dma64_available(pa)) 802 sc->sc_dmat = pa->pa_dmat64; 803 else 804 sc->sc_dmat = pa->pa_dmat; 805 806 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 807 aprint_naive(": Ethernet controller\n"); 808 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 809 810 sc->sc_type = wmp->wmp_type; 811 if (sc->sc_type < WM_T_82543) { 812 if (preg < 2) { 813 aprint_error("%s: i82542 must be at least rev. 2\n", 814 sc->sc_dev.dv_xname); 815 return; 816 } 817 if (preg < 3) 818 sc->sc_type = WM_T_82542_2_0; 819 } 820 821 /* 822 * Map the device. All devices support memory-mapped acccess, 823 * and it is really required for normal operation. 824 */ 825 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 826 switch (memtype) { 827 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 828 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 829 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 830 memtype, 0, &memt, &memh, NULL, NULL) == 0); 831 break; 832 default: 833 memh_valid = 0; 834 } 835 836 if (memh_valid) { 837 sc->sc_st = memt; 838 sc->sc_sh = memh; 839 } else { 840 aprint_error("%s: unable to map device registers\n", 841 sc->sc_dev.dv_xname); 842 return; 843 } 844 845 /* 846 * In addition, i82544 and later support I/O mapped indirect 847 * register access. It is not desirable (nor supported in 848 * this driver) to use it for normal operation, though it is 849 * required to work around bugs in some chip versions. 850 */ 851 if (sc->sc_type >= WM_T_82544) { 852 /* First we have to find the I/O BAR. */ 853 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 854 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 855 PCI_MAPREG_TYPE_IO) 856 break; 857 } 858 if (i == PCI_MAPREG_END) 859 aprint_error("%s: WARNING: unable to find I/O BAR\n", 860 sc->sc_dev.dv_xname); 861 else { 862 /* 863 * The i8254x doesn't apparently respond when the 864 * I/O BAR is 0, which looks somewhat like it's not 865 * been configured. 866 */ 867 preg = pci_conf_read(pc, pa->pa_tag, i); 868 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 869 aprint_error("%s: WARNING: I/O BAR at zero.\n", 870 sc->sc_dev.dv_xname); 871 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 872 0, &sc->sc_iot, &sc->sc_ioh, 873 NULL, NULL) == 0) { 874 sc->sc_flags |= WM_F_IOH_VALID; 875 } else { 876 aprint_error("%s: WARNING: unable to map " 877 "I/O space\n", sc->sc_dev.dv_xname); 878 } 879 } 880 881 } 882 883 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 884 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 885 preg |= PCI_COMMAND_MASTER_ENABLE; 886 if (sc->sc_type < WM_T_82542_2_1) 887 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 888 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 889 890 /* Get it out of power save mode, if needed. */ 891 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 892 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 893 PCI_PMCSR_STATE_MASK; 894 if (preg == PCI_PMCSR_STATE_D3) { 895 /* 896 * The card has lost all configuration data in 897 * this state, so punt. 898 */ 899 aprint_error("%s: unable to wake from power state D3\n", 900 sc->sc_dev.dv_xname); 901 return; 902 } 903 if (preg != PCI_PMCSR_STATE_D0) { 904 aprint_normal("%s: waking up from power state D%d\n", 905 sc->sc_dev.dv_xname, preg); 906 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 907 PCI_PMCSR_STATE_D0); 908 } 909 } 910 911 /* 912 * Map and establish our interrupt. 913 */ 914 if (pci_intr_map(pa, &ih)) { 915 aprint_error("%s: unable to map interrupt\n", 916 sc->sc_dev.dv_xname); 917 return; 918 } 919 intrstr = pci_intr_string(pc, ih); 920 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 921 if (sc->sc_ih == NULL) { 922 aprint_error("%s: unable to establish interrupt", 923 sc->sc_dev.dv_xname); 924 if (intrstr != NULL) 925 aprint_normal(" at %s", intrstr); 926 aprint_normal("\n"); 927 return; 928 } 929 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 930 931 /* 932 * Determine a few things about the bus we're connected to. 933 */ 934 if (sc->sc_type < WM_T_82543) { 935 /* We don't really know the bus characteristics here. */ 936 sc->sc_bus_speed = 33; 937 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 938 /* 939 * CSA (Communication Streaming Architecture) is about as fast 940 * a 32-bit 66MHz PCI Bus. 941 */ 942 sc->sc_flags |= WM_F_CSA; 943 sc->sc_bus_speed = 66; 944 aprint_verbose("%s: Communication Streaming Architecture\n", 945 sc->sc_dev.dv_xname); 946 if (sc->sc_type == WM_T_82547) { 947 callout_init(&sc->sc_txfifo_ch); 948 callout_setfunc(&sc->sc_txfifo_ch, 949 wm_82547_txfifo_stall, sc); 950 aprint_verbose("%s: using 82547 Tx FIFO stall " 951 "work-around\n", sc->sc_dev.dv_xname); 952 } 953 } else if (sc->sc_type >= WM_T_82571) { 954 sc->sc_flags |= WM_F_PCIE | WM_F_EEPROM_SEMAPHORE; 955 aprint_verbose("%s: PCI-Express bus\n", sc->sc_dev.dv_xname); 956 } else { 957 reg = CSR_READ(sc, WMREG_STATUS); 958 if (reg & STATUS_BUS64) 959 sc->sc_flags |= WM_F_BUS64; 960 if (sc->sc_type >= WM_T_82544 && 961 (reg & STATUS_PCIX_MODE) != 0) { 962 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 963 964 sc->sc_flags |= WM_F_PCIX; 965 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 966 PCI_CAP_PCIX, 967 &sc->sc_pcix_offset, NULL) == 0) 968 aprint_error("%s: unable to find PCIX " 969 "capability\n", sc->sc_dev.dv_xname); 970 else if (sc->sc_type != WM_T_82545_3 && 971 sc->sc_type != WM_T_82546_3) { 972 /* 973 * Work around a problem caused by the BIOS 974 * setting the max memory read byte count 975 * incorrectly. 976 */ 977 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 978 sc->sc_pcix_offset + PCI_PCIX_CMD); 979 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 980 sc->sc_pcix_offset + PCI_PCIX_STATUS); 981 982 bytecnt = 983 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 984 PCI_PCIX_CMD_BYTECNT_SHIFT; 985 maxb = 986 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 987 PCI_PCIX_STATUS_MAXB_SHIFT; 988 if (bytecnt > maxb) { 989 aprint_verbose("%s: resetting PCI-X " 990 "MMRBC: %d -> %d\n", 991 sc->sc_dev.dv_xname, 992 512 << bytecnt, 512 << maxb); 993 pcix_cmd = (pcix_cmd & 994 ~PCI_PCIX_CMD_BYTECNT_MASK) | 995 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 996 pci_conf_write(pa->pa_pc, pa->pa_tag, 997 sc->sc_pcix_offset + PCI_PCIX_CMD, 998 pcix_cmd); 999 } 1000 } 1001 } 1002 /* 1003 * The quad port adapter is special; it has a PCIX-PCIX 1004 * bridge on the board, and can run the secondary bus at 1005 * a higher speed. 1006 */ 1007 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 1008 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 1009 : 66; 1010 } else if (sc->sc_flags & WM_F_PCIX) { 1011 switch (reg & STATUS_PCIXSPD_MASK) { 1012 case STATUS_PCIXSPD_50_66: 1013 sc->sc_bus_speed = 66; 1014 break; 1015 case STATUS_PCIXSPD_66_100: 1016 sc->sc_bus_speed = 100; 1017 break; 1018 case STATUS_PCIXSPD_100_133: 1019 sc->sc_bus_speed = 133; 1020 break; 1021 default: 1022 aprint_error( 1023 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 1024 sc->sc_dev.dv_xname, 1025 reg & STATUS_PCIXSPD_MASK); 1026 sc->sc_bus_speed = 66; 1027 } 1028 } else 1029 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 1030 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 1031 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 1032 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 1033 } 1034 1035 /* 1036 * Allocate the control data structures, and create and load the 1037 * DMA map for it. 1038 * 1039 * NOTE: All Tx descriptors must be in the same 4G segment of 1040 * memory. So must Rx descriptors. We simplify by allocating 1041 * both sets within the same 4G segment. 1042 */ 1043 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 1044 WM_NTXDESC_82542 : WM_NTXDESC_82544; 1045 cdata_size = sc->sc_type < WM_T_82544 ? 1046 sizeof(struct wm_control_data_82542) : 1047 sizeof(struct wm_control_data_82544); 1048 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 1049 (bus_size_t) 0x100000000ULL, 1050 &seg, 1, &rseg, 0)) != 0) { 1051 aprint_error( 1052 "%s: unable to allocate control data, error = %d\n", 1053 sc->sc_dev.dv_xname, error); 1054 goto fail_0; 1055 } 1056 1057 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 1058 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 1059 aprint_error("%s: unable to map control data, error = %d\n", 1060 sc->sc_dev.dv_xname, error); 1061 goto fail_1; 1062 } 1063 1064 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 1065 0, 0, &sc->sc_cddmamap)) != 0) { 1066 aprint_error("%s: unable to create control data DMA map, " 1067 "error = %d\n", sc->sc_dev.dv_xname, error); 1068 goto fail_2; 1069 } 1070 1071 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1072 sc->sc_control_data, cdata_size, NULL, 1073 0)) != 0) { 1074 aprint_error( 1075 "%s: unable to load control data DMA map, error = %d\n", 1076 sc->sc_dev.dv_xname, error); 1077 goto fail_3; 1078 } 1079 1080 1081 /* 1082 * Create the transmit buffer DMA maps. 1083 */ 1084 WM_TXQUEUELEN(sc) = 1085 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1086 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1087 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1088 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1089 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1090 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1091 aprint_error("%s: unable to create Tx DMA map %d, " 1092 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1093 goto fail_4; 1094 } 1095 } 1096 1097 /* 1098 * Create the receive buffer DMA maps. 1099 */ 1100 for (i = 0; i < WM_NRXDESC; i++) { 1101 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1102 MCLBYTES, 0, 0, 1103 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1104 aprint_error("%s: unable to create Rx DMA map %d, " 1105 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1106 goto fail_5; 1107 } 1108 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1109 } 1110 1111 /* 1112 * Reset the chip to a known state. 1113 */ 1114 wm_reset(sc); 1115 1116 /* 1117 * Get some information about the EEPROM. 1118 */ 1119 if (sc->sc_type == WM_T_82573) 1120 sc->sc_flags |= WM_F_EEPROM_EERDEEWR; 1121 else if (sc->sc_type > WM_T_82544) 1122 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1123 1124 if (sc->sc_type <= WM_T_82544) 1125 sc->sc_ee_addrbits = 6; 1126 else if (sc->sc_type <= WM_T_82546_3) { 1127 reg = CSR_READ(sc, WMREG_EECD); 1128 if (reg & EECD_EE_SIZE) 1129 sc->sc_ee_addrbits = 8; 1130 else 1131 sc->sc_ee_addrbits = 6; 1132 } else if (sc->sc_type <= WM_T_82547_2) { 1133 reg = CSR_READ(sc, WMREG_EECD); 1134 if (reg & EECD_EE_TYPE) { 1135 sc->sc_flags |= WM_F_EEPROM_SPI; 1136 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1137 } else 1138 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1139 } else if ((sc->sc_type == WM_T_82573) && 1140 (wm_is_onboard_nvm_eeprom(sc) == 0)) { 1141 sc->sc_flags |= WM_F_EEPROM_FLASH; 1142 } else { 1143 /* Assume everything else is SPI. */ 1144 reg = CSR_READ(sc, WMREG_EECD); 1145 sc->sc_flags |= WM_F_EEPROM_SPI; 1146 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1147 } 1148 1149 /* 1150 * Defer printing the EEPROM type until after verifying the checksum 1151 * This allows the EEPROM type to be printed correctly in the case 1152 * that no EEPROM is attached. 1153 */ 1154 1155 1156 /* 1157 * Validate the EEPROM checksum. If the checksum fails, flag this for 1158 * later, so we can fail future reads from the EEPROM. 1159 */ 1160 if (wm_validate_eeprom_checksum(sc)) 1161 sc->sc_flags |= WM_F_EEPROM_INVALID; 1162 1163 if (sc->sc_flags & WM_F_EEPROM_INVALID) 1164 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname); 1165 else if (sc->sc_flags & WM_F_EEPROM_FLASH) { 1166 aprint_verbose("%s: FLASH\n", sc->sc_dev.dv_xname); 1167 } else { 1168 if (sc->sc_flags & WM_F_EEPROM_SPI) 1169 eetype = "SPI"; 1170 else 1171 eetype = "MicroWire"; 1172 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1173 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1174 sc->sc_ee_addrbits, eetype); 1175 } 1176 1177 /* 1178 * Read the Ethernet address from the EEPROM, if not first found 1179 * in device properties. 1180 */ 1181 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 1182 if (ea != NULL) { 1183 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 1184 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 1185 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 1186 } else { 1187 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1188 sizeof(myea) / sizeof(myea[0]), myea)) { 1189 aprint_error("%s: unable to read Ethernet address\n", 1190 sc->sc_dev.dv_xname); 1191 return; 1192 } 1193 enaddr[0] = myea[0] & 0xff; 1194 enaddr[1] = myea[0] >> 8; 1195 enaddr[2] = myea[1] & 0xff; 1196 enaddr[3] = myea[1] >> 8; 1197 enaddr[4] = myea[2] & 0xff; 1198 enaddr[5] = myea[2] >> 8; 1199 } 1200 1201 /* 1202 * Toggle the LSB of the MAC address on the second port 1203 * of the dual port controller. 1204 */ 1205 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3 1206 || sc->sc_type == WM_T_82571) { 1207 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1208 enaddr[5] ^= 1; 1209 } 1210 1211 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1212 ether_sprintf(enaddr)); 1213 1214 /* 1215 * Read the config info from the EEPROM, and set up various 1216 * bits in the control registers based on their contents. 1217 */ 1218 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1219 "i82543-cfg1"); 1220 if (pn != NULL) { 1221 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1222 cfg1 = (uint16_t) prop_number_integer_value(pn); 1223 } else { 1224 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1225 aprint_error("%s: unable to read CFG1\n", 1226 sc->sc_dev.dv_xname); 1227 return; 1228 } 1229 } 1230 1231 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1232 "i82543-cfg2"); 1233 if (pn != NULL) { 1234 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1235 cfg2 = (uint16_t) prop_number_integer_value(pn); 1236 } else { 1237 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1238 aprint_error("%s: unable to read CFG2\n", 1239 sc->sc_dev.dv_xname); 1240 return; 1241 } 1242 } 1243 1244 if (sc->sc_type >= WM_T_82544) { 1245 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1246 "i82543-swdpin"); 1247 if (pn != NULL) { 1248 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1249 swdpin = (uint16_t) prop_number_integer_value(pn); 1250 } else { 1251 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1252 aprint_error("%s: unable to read SWDPIN\n", 1253 sc->sc_dev.dv_xname); 1254 return; 1255 } 1256 } 1257 } 1258 1259 if (cfg1 & EEPROM_CFG1_ILOS) 1260 sc->sc_ctrl |= CTRL_ILOS; 1261 if (sc->sc_type >= WM_T_82544) { 1262 sc->sc_ctrl |= 1263 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1264 CTRL_SWDPIO_SHIFT; 1265 sc->sc_ctrl |= 1266 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1267 CTRL_SWDPINS_SHIFT; 1268 } else { 1269 sc->sc_ctrl |= 1270 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1271 CTRL_SWDPIO_SHIFT; 1272 } 1273 1274 #if 0 1275 if (sc->sc_type >= WM_T_82544) { 1276 if (cfg1 & EEPROM_CFG1_IPS0) 1277 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1278 if (cfg1 & EEPROM_CFG1_IPS1) 1279 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1280 sc->sc_ctrl_ext |= 1281 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1282 CTRL_EXT_SWDPIO_SHIFT; 1283 sc->sc_ctrl_ext |= 1284 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1285 CTRL_EXT_SWDPINS_SHIFT; 1286 } else { 1287 sc->sc_ctrl_ext |= 1288 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1289 CTRL_EXT_SWDPIO_SHIFT; 1290 } 1291 #endif 1292 1293 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1294 #if 0 1295 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1296 #endif 1297 1298 /* 1299 * Set up some register offsets that are different between 1300 * the i82542 and the i82543 and later chips. 1301 */ 1302 if (sc->sc_type < WM_T_82543) { 1303 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1304 sc->sc_tdt_reg = WMREG_OLD_TDT; 1305 } else { 1306 sc->sc_rdt_reg = WMREG_RDT; 1307 sc->sc_tdt_reg = WMREG_TDT; 1308 } 1309 1310 /* 1311 * Determine if we're TBI or GMII mode, and initialize the 1312 * media structures accordingly. 1313 */ 1314 if (sc->sc_type < WM_T_82543 || 1315 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1316 if (wmp->wmp_flags & WMP_F_1000T) 1317 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1318 "product!\n", sc->sc_dev.dv_xname); 1319 wm_tbi_mediainit(sc); 1320 } else { 1321 if (wmp->wmp_flags & WMP_F_1000X) 1322 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1323 "product!\n", sc->sc_dev.dv_xname); 1324 wm_gmii_mediainit(sc); 1325 } 1326 1327 ifp = &sc->sc_ethercom.ec_if; 1328 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1329 ifp->if_softc = sc; 1330 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1331 ifp->if_ioctl = wm_ioctl; 1332 ifp->if_start = wm_start; 1333 ifp->if_watchdog = wm_watchdog; 1334 ifp->if_init = wm_init; 1335 ifp->if_stop = wm_stop; 1336 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1337 IFQ_SET_READY(&ifp->if_snd); 1338 1339 if (sc->sc_type != WM_T_82573) 1340 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1341 1342 /* 1343 * If we're a i82543 or greater, we can support VLANs. 1344 */ 1345 if (sc->sc_type >= WM_T_82543) 1346 sc->sc_ethercom.ec_capabilities |= 1347 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1348 1349 /* 1350 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1351 * on i82543 and later. 1352 */ 1353 if (sc->sc_type >= WM_T_82543) 1354 ifp->if_capabilities |= 1355 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1356 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1357 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1358 IFCAP_CSUM_TCPv6_Tx | 1359 IFCAP_CSUM_UDPv6_Tx; 1360 1361 /* 1362 * If we're a i82544 or greater (except i82547), we can do 1363 * TCP segmentation offload. 1364 */ 1365 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1366 ifp->if_capabilities |= IFCAP_TSOv4; 1367 1368 /* 1369 * Attach the interface. 1370 */ 1371 if_attach(ifp); 1372 ether_ifattach(ifp, enaddr); 1373 #if NRND > 0 1374 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1375 RND_TYPE_NET, 0); 1376 #endif 1377 1378 #ifdef WM_EVENT_COUNTERS 1379 /* Attach event counters. */ 1380 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1381 NULL, sc->sc_dev.dv_xname, "txsstall"); 1382 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1383 NULL, sc->sc_dev.dv_xname, "txdstall"); 1384 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1385 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1386 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1387 NULL, sc->sc_dev.dv_xname, "txdw"); 1388 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1389 NULL, sc->sc_dev.dv_xname, "txqe"); 1390 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1391 NULL, sc->sc_dev.dv_xname, "rxintr"); 1392 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1393 NULL, sc->sc_dev.dv_xname, "linkintr"); 1394 1395 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1396 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1397 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1398 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1399 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1400 NULL, sc->sc_dev.dv_xname, "txipsum"); 1401 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1402 NULL, sc->sc_dev.dv_xname, "txtusum"); 1403 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1404 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1405 1406 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1407 NULL, sc->sc_dev.dv_xname, "txtso"); 1408 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1409 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1410 1411 for (i = 0; i < WM_NTXSEGS; i++) { 1412 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1413 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1414 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1415 } 1416 1417 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1418 NULL, sc->sc_dev.dv_xname, "txdrop"); 1419 1420 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1421 NULL, sc->sc_dev.dv_xname, "tu"); 1422 1423 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1424 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1425 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1426 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1427 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1428 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1429 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1430 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1431 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1432 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1433 #endif /* WM_EVENT_COUNTERS */ 1434 1435 /* 1436 * Make sure the interface is shutdown during reboot. 1437 */ 1438 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1439 if (sc->sc_sdhook == NULL) 1440 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1441 sc->sc_dev.dv_xname); 1442 return; 1443 1444 /* 1445 * Free any resources we've allocated during the failed attach 1446 * attempt. Do this in reverse order and fall through. 1447 */ 1448 fail_5: 1449 for (i = 0; i < WM_NRXDESC; i++) { 1450 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1451 bus_dmamap_destroy(sc->sc_dmat, 1452 sc->sc_rxsoft[i].rxs_dmamap); 1453 } 1454 fail_4: 1455 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1456 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1457 bus_dmamap_destroy(sc->sc_dmat, 1458 sc->sc_txsoft[i].txs_dmamap); 1459 } 1460 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1461 fail_3: 1462 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1463 fail_2: 1464 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1465 cdata_size); 1466 fail_1: 1467 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1468 fail_0: 1469 return; 1470 } 1471 1472 /* 1473 * wm_shutdown: 1474 * 1475 * Make sure the interface is stopped at reboot time. 1476 */ 1477 static void 1478 wm_shutdown(void *arg) 1479 { 1480 struct wm_softc *sc = arg; 1481 1482 wm_stop(&sc->sc_ethercom.ec_if, 1); 1483 } 1484 1485 /* 1486 * wm_tx_offload: 1487 * 1488 * Set up TCP/IP checksumming parameters for the 1489 * specified packet. 1490 */ 1491 static int 1492 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1493 uint8_t *fieldsp) 1494 { 1495 struct mbuf *m0 = txs->txs_mbuf; 1496 struct livengood_tcpip_ctxdesc *t; 1497 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1498 struct ether_header *eh; 1499 int offset, iphl; 1500 uint8_t fields; 1501 1502 /* 1503 * XXX It would be nice if the mbuf pkthdr had offset 1504 * fields for the protocol headers. 1505 */ 1506 1507 eh = mtod(m0, struct ether_header *); 1508 switch (htons(eh->ether_type)) { 1509 case ETHERTYPE_IP: 1510 case ETHERTYPE_IPV6: 1511 offset = ETHER_HDR_LEN; 1512 break; 1513 1514 case ETHERTYPE_VLAN: 1515 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1516 break; 1517 1518 default: 1519 /* 1520 * Don't support this protocol or encapsulation. 1521 */ 1522 *fieldsp = 0; 1523 *cmdp = 0; 1524 return (0); 1525 } 1526 1527 if ((m0->m_pkthdr.csum_flags & 1528 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1529 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1530 } else { 1531 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1532 } 1533 1534 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1535 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1536 seg = 0; 1537 fields = 0; 1538 1539 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1540 int hlen = offset + iphl; 1541 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1542 if (__predict_false(m0->m_len < 1543 (hlen + sizeof(struct tcphdr)))) { 1544 /* 1545 * TCP/IP headers are not in the first mbuf; we need 1546 * to do this the slow and painful way. Let's just 1547 * hope this doesn't happen very often. 1548 */ 1549 struct ip ip; 1550 struct tcphdr th; 1551 1552 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1553 1554 m_copydata(m0, offset, sizeof(ip), &ip); 1555 m_copydata(m0, hlen, sizeof(th), &th); 1556 1557 ip.ip_len = 0; 1558 1559 m_copyback(m0, hlen + offsetof(struct ip, ip_len), 1560 sizeof(ip.ip_len), &ip.ip_len); 1561 1562 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1563 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1564 1565 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1566 sizeof(th.th_sum), &th.th_sum); 1567 1568 hlen += th.th_off << 2; 1569 } else { 1570 /* 1571 * TCP/IP headers are in the first mbuf; we can do 1572 * this the easy way. 1573 */ 1574 struct ip *ip = 1575 (struct ip *) (mtod(m0, caddr_t) + offset); 1576 struct tcphdr *th = 1577 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1578 1579 ip->ip_len = 0; 1580 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1581 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1582 1583 hlen += th->th_off << 2; 1584 } 1585 1586 cmd |= WTX_TCPIP_CMD_TSE; 1587 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1588 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1589 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1590 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1591 } 1592 1593 /* 1594 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1595 * offload feature, if we load the context descriptor, we 1596 * MUST provide valid values for IPCSS and TUCSS fields. 1597 */ 1598 1599 ipcs = WTX_TCPIP_IPCSS(offset) | 1600 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1601 WTX_TCPIP_IPCSE(offset + iphl - 1); 1602 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1603 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1604 fields |= WTX_IXSM; 1605 } 1606 1607 offset += iphl; 1608 1609 if (m0->m_pkthdr.csum_flags & 1610 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1611 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1612 fields |= WTX_TXSM; 1613 tucs = WTX_TCPIP_TUCSS(offset) | 1614 WTX_TCPIP_TUCSO(offset + 1615 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1616 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1617 } else if ((m0->m_pkthdr.csum_flags & 1618 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) { 1619 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1620 fields |= WTX_TXSM; 1621 tucs = WTX_TCPIP_TUCSS(offset) | 1622 WTX_TCPIP_TUCSO(offset + 1623 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1624 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1625 } else { 1626 /* Just initialize it to a valid TCP context. */ 1627 tucs = WTX_TCPIP_TUCSS(offset) | 1628 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1629 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1630 } 1631 1632 /* Fill in the context descriptor. */ 1633 t = (struct livengood_tcpip_ctxdesc *) 1634 &sc->sc_txdescs[sc->sc_txnext]; 1635 t->tcpip_ipcs = htole32(ipcs); 1636 t->tcpip_tucs = htole32(tucs); 1637 t->tcpip_cmdlen = htole32(cmdlen); 1638 t->tcpip_seg = htole32(seg); 1639 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1640 1641 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1642 txs->txs_ndesc++; 1643 1644 *cmdp = cmd; 1645 *fieldsp = fields; 1646 1647 return (0); 1648 } 1649 1650 static void 1651 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1652 { 1653 struct mbuf *m; 1654 int i; 1655 1656 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1657 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1658 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1659 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1660 m->m_data, m->m_len, m->m_flags); 1661 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1662 i, i == 1 ? "" : "s"); 1663 } 1664 1665 /* 1666 * wm_82547_txfifo_stall: 1667 * 1668 * Callout used to wait for the 82547 Tx FIFO to drain, 1669 * reset the FIFO pointers, and restart packet transmission. 1670 */ 1671 static void 1672 wm_82547_txfifo_stall(void *arg) 1673 { 1674 struct wm_softc *sc = arg; 1675 int s; 1676 1677 s = splnet(); 1678 1679 if (sc->sc_txfifo_stall) { 1680 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1681 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1682 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1683 /* 1684 * Packets have drained. Stop transmitter, reset 1685 * FIFO pointers, restart transmitter, and kick 1686 * the packet queue. 1687 */ 1688 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1689 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1690 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1691 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1692 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1693 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1694 CSR_WRITE(sc, WMREG_TCTL, tctl); 1695 CSR_WRITE_FLUSH(sc); 1696 1697 sc->sc_txfifo_head = 0; 1698 sc->sc_txfifo_stall = 0; 1699 wm_start(&sc->sc_ethercom.ec_if); 1700 } else { 1701 /* 1702 * Still waiting for packets to drain; try again in 1703 * another tick. 1704 */ 1705 callout_schedule(&sc->sc_txfifo_ch, 1); 1706 } 1707 } 1708 1709 splx(s); 1710 } 1711 1712 /* 1713 * wm_82547_txfifo_bugchk: 1714 * 1715 * Check for bug condition in the 82547 Tx FIFO. We need to 1716 * prevent enqueueing a packet that would wrap around the end 1717 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1718 * 1719 * We do this by checking the amount of space before the end 1720 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1721 * the Tx FIFO, wait for all remaining packets to drain, reset 1722 * the internal FIFO pointers to the beginning, and restart 1723 * transmission on the interface. 1724 */ 1725 #define WM_FIFO_HDR 0x10 1726 #define WM_82547_PAD_LEN 0x3e0 1727 static int 1728 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1729 { 1730 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1731 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1732 1733 /* Just return if already stalled. */ 1734 if (sc->sc_txfifo_stall) 1735 return (1); 1736 1737 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1738 /* Stall only occurs in half-duplex mode. */ 1739 goto send_packet; 1740 } 1741 1742 if (len >= WM_82547_PAD_LEN + space) { 1743 sc->sc_txfifo_stall = 1; 1744 callout_schedule(&sc->sc_txfifo_ch, 1); 1745 return (1); 1746 } 1747 1748 send_packet: 1749 sc->sc_txfifo_head += len; 1750 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1751 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1752 1753 return (0); 1754 } 1755 1756 /* 1757 * wm_start: [ifnet interface function] 1758 * 1759 * Start packet transmission on the interface. 1760 */ 1761 static void 1762 wm_start(struct ifnet *ifp) 1763 { 1764 struct wm_softc *sc = ifp->if_softc; 1765 struct mbuf *m0; 1766 #if 0 /* XXXJRT */ 1767 struct m_tag *mtag; 1768 #endif 1769 struct wm_txsoft *txs; 1770 bus_dmamap_t dmamap; 1771 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1772 bus_addr_t curaddr; 1773 bus_size_t seglen, curlen; 1774 uint32_t cksumcmd; 1775 uint8_t cksumfields; 1776 1777 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1778 return; 1779 1780 /* 1781 * Remember the previous number of free descriptors. 1782 */ 1783 ofree = sc->sc_txfree; 1784 1785 /* 1786 * Loop through the send queue, setting up transmit descriptors 1787 * until we drain the queue, or use up all available transmit 1788 * descriptors. 1789 */ 1790 for (;;) { 1791 /* Grab a packet off the queue. */ 1792 IFQ_POLL(&ifp->if_snd, m0); 1793 if (m0 == NULL) 1794 break; 1795 1796 DPRINTF(WM_DEBUG_TX, 1797 ("%s: TX: have packet to transmit: %p\n", 1798 sc->sc_dev.dv_xname, m0)); 1799 1800 /* Get a work queue entry. */ 1801 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1802 wm_txintr(sc); 1803 if (sc->sc_txsfree == 0) { 1804 DPRINTF(WM_DEBUG_TX, 1805 ("%s: TX: no free job descriptors\n", 1806 sc->sc_dev.dv_xname)); 1807 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1808 break; 1809 } 1810 } 1811 1812 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1813 dmamap = txs->txs_dmamap; 1814 1815 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1816 1817 /* 1818 * So says the Linux driver: 1819 * The controller does a simple calculation to make sure 1820 * there is enough room in the FIFO before initiating the 1821 * DMA for each buffer. The calc is: 1822 * 4 = ceil(buffer len / MSS) 1823 * To make sure we don't overrun the FIFO, adjust the max 1824 * buffer len if the MSS drops. 1825 */ 1826 dmamap->dm_maxsegsz = 1827 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1828 ? m0->m_pkthdr.segsz << 2 1829 : WTX_MAX_LEN; 1830 1831 /* 1832 * Load the DMA map. If this fails, the packet either 1833 * didn't fit in the allotted number of segments, or we 1834 * were short on resources. For the too-many-segments 1835 * case, we simply report an error and drop the packet, 1836 * since we can't sanely copy a jumbo packet to a single 1837 * buffer. 1838 */ 1839 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1840 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1841 if (error) { 1842 if (error == EFBIG) { 1843 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1844 log(LOG_ERR, "%s: Tx packet consumes too many " 1845 "DMA segments, dropping...\n", 1846 sc->sc_dev.dv_xname); 1847 IFQ_DEQUEUE(&ifp->if_snd, m0); 1848 wm_dump_mbuf_chain(sc, m0); 1849 m_freem(m0); 1850 continue; 1851 } 1852 /* 1853 * Short on resources, just stop for now. 1854 */ 1855 DPRINTF(WM_DEBUG_TX, 1856 ("%s: TX: dmamap load failed: %d\n", 1857 sc->sc_dev.dv_xname, error)); 1858 break; 1859 } 1860 1861 segs_needed = dmamap->dm_nsegs; 1862 if (use_tso) { 1863 /* For sentinel descriptor; see below. */ 1864 segs_needed++; 1865 } 1866 1867 /* 1868 * Ensure we have enough descriptors free to describe 1869 * the packet. Note, we always reserve one descriptor 1870 * at the end of the ring due to the semantics of the 1871 * TDT register, plus one more in the event we need 1872 * to load offload context. 1873 */ 1874 if (segs_needed > sc->sc_txfree - 2) { 1875 /* 1876 * Not enough free descriptors to transmit this 1877 * packet. We haven't committed anything yet, 1878 * so just unload the DMA map, put the packet 1879 * pack on the queue, and punt. Notify the upper 1880 * layer that there are no more slots left. 1881 */ 1882 DPRINTF(WM_DEBUG_TX, 1883 ("%s: TX: need %d (%d) descriptors, have %d\n", 1884 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1885 sc->sc_txfree - 1)); 1886 ifp->if_flags |= IFF_OACTIVE; 1887 bus_dmamap_unload(sc->sc_dmat, dmamap); 1888 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1889 break; 1890 } 1891 1892 /* 1893 * Check for 82547 Tx FIFO bug. We need to do this 1894 * once we know we can transmit the packet, since we 1895 * do some internal FIFO space accounting here. 1896 */ 1897 if (sc->sc_type == WM_T_82547 && 1898 wm_82547_txfifo_bugchk(sc, m0)) { 1899 DPRINTF(WM_DEBUG_TX, 1900 ("%s: TX: 82547 Tx FIFO bug detected\n", 1901 sc->sc_dev.dv_xname)); 1902 ifp->if_flags |= IFF_OACTIVE; 1903 bus_dmamap_unload(sc->sc_dmat, dmamap); 1904 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1905 break; 1906 } 1907 1908 IFQ_DEQUEUE(&ifp->if_snd, m0); 1909 1910 /* 1911 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1912 */ 1913 1914 DPRINTF(WM_DEBUG_TX, 1915 ("%s: TX: packet has %d (%d) DMA segments\n", 1916 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1917 1918 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1919 1920 /* 1921 * Store a pointer to the packet so that we can free it 1922 * later. 1923 * 1924 * Initially, we consider the number of descriptors the 1925 * packet uses the number of DMA segments. This may be 1926 * incremented by 1 if we do checksum offload (a descriptor 1927 * is used to set the checksum context). 1928 */ 1929 txs->txs_mbuf = m0; 1930 txs->txs_firstdesc = sc->sc_txnext; 1931 txs->txs_ndesc = segs_needed; 1932 1933 /* Set up offload parameters for this packet. */ 1934 if (m0->m_pkthdr.csum_flags & 1935 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 1936 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 1937 if (wm_tx_offload(sc, txs, &cksumcmd, 1938 &cksumfields) != 0) { 1939 /* Error message already displayed. */ 1940 bus_dmamap_unload(sc->sc_dmat, dmamap); 1941 continue; 1942 } 1943 } else { 1944 cksumcmd = 0; 1945 cksumfields = 0; 1946 } 1947 1948 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 1949 1950 /* Sync the DMA map. */ 1951 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1952 BUS_DMASYNC_PREWRITE); 1953 1954 /* 1955 * Initialize the transmit descriptor. 1956 */ 1957 for (nexttx = sc->sc_txnext, seg = 0; 1958 seg < dmamap->dm_nsegs; seg++) { 1959 for (seglen = dmamap->dm_segs[seg].ds_len, 1960 curaddr = dmamap->dm_segs[seg].ds_addr; 1961 seglen != 0; 1962 curaddr += curlen, seglen -= curlen, 1963 nexttx = WM_NEXTTX(sc, nexttx)) { 1964 curlen = seglen; 1965 1966 /* 1967 * So says the Linux driver: 1968 * Work around for premature descriptor 1969 * write-backs in TSO mode. Append a 1970 * 4-byte sentinel descriptor. 1971 */ 1972 if (use_tso && 1973 seg == dmamap->dm_nsegs - 1 && 1974 curlen > 8) 1975 curlen -= 4; 1976 1977 wm_set_dma_addr( 1978 &sc->sc_txdescs[nexttx].wtx_addr, 1979 curaddr); 1980 sc->sc_txdescs[nexttx].wtx_cmdlen = 1981 htole32(cksumcmd | curlen); 1982 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1983 0; 1984 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1985 cksumfields; 1986 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1987 lasttx = nexttx; 1988 1989 DPRINTF(WM_DEBUG_TX, 1990 ("%s: TX: desc %d: low 0x%08lx, " 1991 "len 0x%04x\n", 1992 sc->sc_dev.dv_xname, nexttx, 1993 curaddr & 0xffffffffUL, (unsigned)curlen)); 1994 } 1995 } 1996 1997 KASSERT(lasttx != -1); 1998 1999 /* 2000 * Set up the command byte on the last descriptor of 2001 * the packet. If we're in the interrupt delay window, 2002 * delay the interrupt. 2003 */ 2004 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2005 htole32(WTX_CMD_EOP | WTX_CMD_RS); 2006 2007 #if 0 /* XXXJRT */ 2008 /* 2009 * If VLANs are enabled and the packet has a VLAN tag, set 2010 * up the descriptor to encapsulate the packet for us. 2011 * 2012 * This is only valid on the last descriptor of the packet. 2013 */ 2014 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 2015 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2016 htole32(WTX_CMD_VLE); 2017 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 2018 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 2019 } 2020 #endif /* XXXJRT */ 2021 2022 txs->txs_lastdesc = lasttx; 2023 2024 DPRINTF(WM_DEBUG_TX, 2025 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 2026 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 2027 2028 /* Sync the descriptors we're using. */ 2029 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 2030 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2031 2032 /* Give the packet to the chip. */ 2033 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 2034 2035 DPRINTF(WM_DEBUG_TX, 2036 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 2037 2038 DPRINTF(WM_DEBUG_TX, 2039 ("%s: TX: finished transmitting packet, job %d\n", 2040 sc->sc_dev.dv_xname, sc->sc_txsnext)); 2041 2042 /* Advance the tx pointer. */ 2043 sc->sc_txfree -= txs->txs_ndesc; 2044 sc->sc_txnext = nexttx; 2045 2046 sc->sc_txsfree--; 2047 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 2048 2049 #if NBPFILTER > 0 2050 /* Pass the packet to any BPF listeners. */ 2051 if (ifp->if_bpf) 2052 bpf_mtap(ifp->if_bpf, m0); 2053 #endif /* NBPFILTER > 0 */ 2054 } 2055 2056 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 2057 /* No more slots; notify upper layer. */ 2058 ifp->if_flags |= IFF_OACTIVE; 2059 } 2060 2061 if (sc->sc_txfree != ofree) { 2062 /* Set a watchdog timer in case the chip flakes out. */ 2063 ifp->if_timer = 5; 2064 } 2065 } 2066 2067 /* 2068 * wm_watchdog: [ifnet interface function] 2069 * 2070 * Watchdog timer handler. 2071 */ 2072 static void 2073 wm_watchdog(struct ifnet *ifp) 2074 { 2075 struct wm_softc *sc = ifp->if_softc; 2076 2077 /* 2078 * Since we're using delayed interrupts, sweep up 2079 * before we report an error. 2080 */ 2081 wm_txintr(sc); 2082 2083 if (sc->sc_txfree != WM_NTXDESC(sc)) { 2084 log(LOG_ERR, 2085 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 2086 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 2087 sc->sc_txnext); 2088 ifp->if_oerrors++; 2089 2090 /* Reset the interface. */ 2091 (void) wm_init(ifp); 2092 } 2093 2094 /* Try to get more packets going. */ 2095 wm_start(ifp); 2096 } 2097 2098 /* 2099 * wm_ioctl: [ifnet interface function] 2100 * 2101 * Handle control requests from the operator. 2102 */ 2103 static int 2104 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2105 { 2106 struct wm_softc *sc = ifp->if_softc; 2107 struct ifreq *ifr = (struct ifreq *) data; 2108 int s, error; 2109 2110 s = splnet(); 2111 2112 switch (cmd) { 2113 case SIOCSIFMEDIA: 2114 case SIOCGIFMEDIA: 2115 /* Flow control requires full-duplex mode. */ 2116 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2117 (ifr->ifr_media & IFM_FDX) == 0) 2118 ifr->ifr_media &= ~IFM_ETH_FMASK; 2119 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2120 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2121 /* We can do both TXPAUSE and RXPAUSE. */ 2122 ifr->ifr_media |= 2123 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2124 } 2125 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2126 } 2127 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2128 break; 2129 default: 2130 error = ether_ioctl(ifp, cmd, data); 2131 if (error == ENETRESET) { 2132 /* 2133 * Multicast list has changed; set the hardware filter 2134 * accordingly. 2135 */ 2136 if (ifp->if_flags & IFF_RUNNING) 2137 wm_set_filter(sc); 2138 error = 0; 2139 } 2140 break; 2141 } 2142 2143 /* Try to get more packets going. */ 2144 wm_start(ifp); 2145 2146 splx(s); 2147 return (error); 2148 } 2149 2150 /* 2151 * wm_intr: 2152 * 2153 * Interrupt service routine. 2154 */ 2155 static int 2156 wm_intr(void *arg) 2157 { 2158 struct wm_softc *sc = arg; 2159 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2160 uint32_t icr; 2161 int handled = 0; 2162 2163 while (1 /* CONSTCOND */) { 2164 icr = CSR_READ(sc, WMREG_ICR); 2165 if ((icr & sc->sc_icr) == 0) 2166 break; 2167 2168 #if 0 /*NRND > 0*/ 2169 if (RND_ENABLED(&sc->rnd_source)) 2170 rnd_add_uint32(&sc->rnd_source, icr); 2171 #endif 2172 2173 handled = 1; 2174 2175 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2176 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2177 DPRINTF(WM_DEBUG_RX, 2178 ("%s: RX: got Rx intr 0x%08x\n", 2179 sc->sc_dev.dv_xname, 2180 icr & (ICR_RXDMT0|ICR_RXT0))); 2181 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2182 } 2183 #endif 2184 wm_rxintr(sc); 2185 2186 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2187 if (icr & ICR_TXDW) { 2188 DPRINTF(WM_DEBUG_TX, 2189 ("%s: TX: got TXDW interrupt\n", 2190 sc->sc_dev.dv_xname)); 2191 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2192 } 2193 #endif 2194 wm_txintr(sc); 2195 2196 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2197 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2198 wm_linkintr(sc, icr); 2199 } 2200 2201 if (icr & ICR_RXO) { 2202 ifp->if_ierrors++; 2203 #if defined(WM_DEBUG) 2204 log(LOG_WARNING, "%s: Receive overrun\n", 2205 sc->sc_dev.dv_xname); 2206 #endif /* defined(WM_DEBUG) */ 2207 } 2208 } 2209 2210 if (handled) { 2211 /* Try to get more packets going. */ 2212 wm_start(ifp); 2213 } 2214 2215 return (handled); 2216 } 2217 2218 /* 2219 * wm_txintr: 2220 * 2221 * Helper; handle transmit interrupts. 2222 */ 2223 static void 2224 wm_txintr(struct wm_softc *sc) 2225 { 2226 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2227 struct wm_txsoft *txs; 2228 uint8_t status; 2229 int i; 2230 2231 ifp->if_flags &= ~IFF_OACTIVE; 2232 2233 /* 2234 * Go through the Tx list and free mbufs for those 2235 * frames which have been transmitted. 2236 */ 2237 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2238 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2239 txs = &sc->sc_txsoft[i]; 2240 2241 DPRINTF(WM_DEBUG_TX, 2242 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2243 2244 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2245 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2246 2247 status = 2248 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2249 if ((status & WTX_ST_DD) == 0) { 2250 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2251 BUS_DMASYNC_PREREAD); 2252 break; 2253 } 2254 2255 DPRINTF(WM_DEBUG_TX, 2256 ("%s: TX: job %d done: descs %d..%d\n", 2257 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2258 txs->txs_lastdesc)); 2259 2260 /* 2261 * XXX We should probably be using the statistics 2262 * XXX registers, but I don't know if they exist 2263 * XXX on chips before the i82544. 2264 */ 2265 2266 #ifdef WM_EVENT_COUNTERS 2267 if (status & WTX_ST_TU) 2268 WM_EVCNT_INCR(&sc->sc_ev_tu); 2269 #endif /* WM_EVENT_COUNTERS */ 2270 2271 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2272 ifp->if_oerrors++; 2273 if (status & WTX_ST_LC) 2274 log(LOG_WARNING, "%s: late collision\n", 2275 sc->sc_dev.dv_xname); 2276 else if (status & WTX_ST_EC) { 2277 ifp->if_collisions += 16; 2278 log(LOG_WARNING, "%s: excessive collisions\n", 2279 sc->sc_dev.dv_xname); 2280 } 2281 } else 2282 ifp->if_opackets++; 2283 2284 sc->sc_txfree += txs->txs_ndesc; 2285 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2286 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2287 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2288 m_freem(txs->txs_mbuf); 2289 txs->txs_mbuf = NULL; 2290 } 2291 2292 /* Update the dirty transmit buffer pointer. */ 2293 sc->sc_txsdirty = i; 2294 DPRINTF(WM_DEBUG_TX, 2295 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2296 2297 /* 2298 * If there are no more pending transmissions, cancel the watchdog 2299 * timer. 2300 */ 2301 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2302 ifp->if_timer = 0; 2303 } 2304 2305 /* 2306 * wm_rxintr: 2307 * 2308 * Helper; handle receive interrupts. 2309 */ 2310 static void 2311 wm_rxintr(struct wm_softc *sc) 2312 { 2313 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2314 struct wm_rxsoft *rxs; 2315 struct mbuf *m; 2316 int i, len; 2317 uint8_t status, errors; 2318 2319 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2320 rxs = &sc->sc_rxsoft[i]; 2321 2322 DPRINTF(WM_DEBUG_RX, 2323 ("%s: RX: checking descriptor %d\n", 2324 sc->sc_dev.dv_xname, i)); 2325 2326 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2327 2328 status = sc->sc_rxdescs[i].wrx_status; 2329 errors = sc->sc_rxdescs[i].wrx_errors; 2330 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2331 2332 if ((status & WRX_ST_DD) == 0) { 2333 /* 2334 * We have processed all of the receive descriptors. 2335 */ 2336 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2337 break; 2338 } 2339 2340 if (__predict_false(sc->sc_rxdiscard)) { 2341 DPRINTF(WM_DEBUG_RX, 2342 ("%s: RX: discarding contents of descriptor %d\n", 2343 sc->sc_dev.dv_xname, i)); 2344 WM_INIT_RXDESC(sc, i); 2345 if (status & WRX_ST_EOP) { 2346 /* Reset our state. */ 2347 DPRINTF(WM_DEBUG_RX, 2348 ("%s: RX: resetting rxdiscard -> 0\n", 2349 sc->sc_dev.dv_xname)); 2350 sc->sc_rxdiscard = 0; 2351 } 2352 continue; 2353 } 2354 2355 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2356 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2357 2358 m = rxs->rxs_mbuf; 2359 2360 /* 2361 * Add a new receive buffer to the ring. 2362 */ 2363 if (wm_add_rxbuf(sc, i) != 0) { 2364 /* 2365 * Failed, throw away what we've done so 2366 * far, and discard the rest of the packet. 2367 */ 2368 ifp->if_ierrors++; 2369 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2370 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2371 WM_INIT_RXDESC(sc, i); 2372 if ((status & WRX_ST_EOP) == 0) 2373 sc->sc_rxdiscard = 1; 2374 if (sc->sc_rxhead != NULL) 2375 m_freem(sc->sc_rxhead); 2376 WM_RXCHAIN_RESET(sc); 2377 DPRINTF(WM_DEBUG_RX, 2378 ("%s: RX: Rx buffer allocation failed, " 2379 "dropping packet%s\n", sc->sc_dev.dv_xname, 2380 sc->sc_rxdiscard ? " (discard)" : "")); 2381 continue; 2382 } 2383 2384 WM_RXCHAIN_LINK(sc, m); 2385 2386 m->m_len = len; 2387 2388 DPRINTF(WM_DEBUG_RX, 2389 ("%s: RX: buffer at %p len %d\n", 2390 sc->sc_dev.dv_xname, m->m_data, len)); 2391 2392 /* 2393 * If this is not the end of the packet, keep 2394 * looking. 2395 */ 2396 if ((status & WRX_ST_EOP) == 0) { 2397 sc->sc_rxlen += len; 2398 DPRINTF(WM_DEBUG_RX, 2399 ("%s: RX: not yet EOP, rxlen -> %d\n", 2400 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2401 continue; 2402 } 2403 2404 /* 2405 * Okay, we have the entire packet now. The chip is 2406 * configured to include the FCS (not all chips can 2407 * be configured to strip it), so we need to trim it. 2408 */ 2409 m->m_len -= ETHER_CRC_LEN; 2410 2411 *sc->sc_rxtailp = NULL; 2412 len = m->m_len + sc->sc_rxlen; 2413 m = sc->sc_rxhead; 2414 2415 WM_RXCHAIN_RESET(sc); 2416 2417 DPRINTF(WM_DEBUG_RX, 2418 ("%s: RX: have entire packet, len -> %d\n", 2419 sc->sc_dev.dv_xname, len)); 2420 2421 /* 2422 * If an error occurred, update stats and drop the packet. 2423 */ 2424 if (errors & 2425 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2426 ifp->if_ierrors++; 2427 if (errors & WRX_ER_SE) 2428 log(LOG_WARNING, "%s: symbol error\n", 2429 sc->sc_dev.dv_xname); 2430 else if (errors & WRX_ER_SEQ) 2431 log(LOG_WARNING, "%s: receive sequence error\n", 2432 sc->sc_dev.dv_xname); 2433 else if (errors & WRX_ER_CE) 2434 log(LOG_WARNING, "%s: CRC error\n", 2435 sc->sc_dev.dv_xname); 2436 m_freem(m); 2437 continue; 2438 } 2439 2440 /* 2441 * No errors. Receive the packet. 2442 */ 2443 m->m_pkthdr.rcvif = ifp; 2444 m->m_pkthdr.len = len; 2445 2446 #if 0 /* XXXJRT */ 2447 /* 2448 * If VLANs are enabled, VLAN packets have been unwrapped 2449 * for us. Associate the tag with the packet. 2450 */ 2451 if ((status & WRX_ST_VP) != 0) { 2452 VLAN_INPUT_TAG(ifp, m, 2453 le16toh(sc->sc_rxdescs[i].wrx_special, 2454 continue); 2455 } 2456 #endif /* XXXJRT */ 2457 2458 /* 2459 * Set up checksum info for this packet. 2460 */ 2461 if ((status & WRX_ST_IXSM) == 0) { 2462 if (status & WRX_ST_IPCS) { 2463 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2464 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2465 if (errors & WRX_ER_IPE) 2466 m->m_pkthdr.csum_flags |= 2467 M_CSUM_IPv4_BAD; 2468 } 2469 if (status & WRX_ST_TCPCS) { 2470 /* 2471 * Note: we don't know if this was TCP or UDP, 2472 * so we just set both bits, and expect the 2473 * upper layers to deal. 2474 */ 2475 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2476 m->m_pkthdr.csum_flags |= 2477 M_CSUM_TCPv4|M_CSUM_UDPv4; 2478 if (errors & WRX_ER_TCPE) 2479 m->m_pkthdr.csum_flags |= 2480 M_CSUM_TCP_UDP_BAD; 2481 } 2482 } 2483 2484 ifp->if_ipackets++; 2485 2486 #if NBPFILTER > 0 2487 /* Pass this up to any BPF listeners. */ 2488 if (ifp->if_bpf) 2489 bpf_mtap(ifp->if_bpf, m); 2490 #endif /* NBPFILTER > 0 */ 2491 2492 /* Pass it on. */ 2493 (*ifp->if_input)(ifp, m); 2494 } 2495 2496 /* Update the receive pointer. */ 2497 sc->sc_rxptr = i; 2498 2499 DPRINTF(WM_DEBUG_RX, 2500 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2501 } 2502 2503 /* 2504 * wm_linkintr: 2505 * 2506 * Helper; handle link interrupts. 2507 */ 2508 static void 2509 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2510 { 2511 uint32_t status; 2512 2513 /* 2514 * If we get a link status interrupt on a 1000BASE-T 2515 * device, just fall into the normal MII tick path. 2516 */ 2517 if (sc->sc_flags & WM_F_HAS_MII) { 2518 if (icr & ICR_LSC) { 2519 DPRINTF(WM_DEBUG_LINK, 2520 ("%s: LINK: LSC -> mii_tick\n", 2521 sc->sc_dev.dv_xname)); 2522 mii_tick(&sc->sc_mii); 2523 } else if (icr & ICR_RXSEQ) { 2524 DPRINTF(WM_DEBUG_LINK, 2525 ("%s: LINK Receive sequence error\n", 2526 sc->sc_dev.dv_xname)); 2527 } 2528 return; 2529 } 2530 2531 /* 2532 * If we are now receiving /C/, check for link again in 2533 * a couple of link clock ticks. 2534 */ 2535 if (icr & ICR_RXCFG) { 2536 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2537 sc->sc_dev.dv_xname)); 2538 sc->sc_tbi_anstate = 2; 2539 } 2540 2541 if (icr & ICR_LSC) { 2542 status = CSR_READ(sc, WMREG_STATUS); 2543 if (status & STATUS_LU) { 2544 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2545 sc->sc_dev.dv_xname, 2546 (status & STATUS_FD) ? "FDX" : "HDX")); 2547 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2548 sc->sc_fcrtl &= ~FCRTL_XONE; 2549 if (status & STATUS_FD) 2550 sc->sc_tctl |= 2551 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2552 else 2553 sc->sc_tctl |= 2554 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2555 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2556 sc->sc_fcrtl |= FCRTL_XONE; 2557 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2558 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2559 WMREG_OLD_FCRTL : WMREG_FCRTL, 2560 sc->sc_fcrtl); 2561 sc->sc_tbi_linkup = 1; 2562 } else { 2563 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2564 sc->sc_dev.dv_xname)); 2565 sc->sc_tbi_linkup = 0; 2566 } 2567 sc->sc_tbi_anstate = 2; 2568 wm_tbi_set_linkled(sc); 2569 } else if (icr & ICR_RXSEQ) { 2570 DPRINTF(WM_DEBUG_LINK, 2571 ("%s: LINK: Receive sequence error\n", 2572 sc->sc_dev.dv_xname)); 2573 } 2574 } 2575 2576 /* 2577 * wm_tick: 2578 * 2579 * One second timer, used to check link status, sweep up 2580 * completed transmit jobs, etc. 2581 */ 2582 static void 2583 wm_tick(void *arg) 2584 { 2585 struct wm_softc *sc = arg; 2586 int s; 2587 2588 s = splnet(); 2589 2590 if (sc->sc_type >= WM_T_82542_2_1) { 2591 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2592 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2593 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2594 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2595 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2596 } 2597 2598 if (sc->sc_flags & WM_F_HAS_MII) 2599 mii_tick(&sc->sc_mii); 2600 else 2601 wm_tbi_check_link(sc); 2602 2603 splx(s); 2604 2605 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2606 } 2607 2608 /* 2609 * wm_reset: 2610 * 2611 * Reset the i82542 chip. 2612 */ 2613 static void 2614 wm_reset(struct wm_softc *sc) 2615 { 2616 int i; 2617 2618 /* 2619 * Allocate on-chip memory according to the MTU size. 2620 * The Packet Buffer Allocation register must be written 2621 * before the chip is reset. 2622 */ 2623 switch (sc->sc_type) { 2624 case WM_T_82547: 2625 case WM_T_82547_2: 2626 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2627 PBA_22K : PBA_30K; 2628 sc->sc_txfifo_head = 0; 2629 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2630 sc->sc_txfifo_size = 2631 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2632 sc->sc_txfifo_stall = 0; 2633 break; 2634 case WM_T_82571: 2635 case WM_T_82572: 2636 sc->sc_pba = PBA_32K; 2637 break; 2638 case WM_T_82573: 2639 sc->sc_pba = PBA_12K; 2640 break; 2641 default: 2642 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2643 PBA_40K : PBA_48K; 2644 break; 2645 } 2646 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2647 2648 switch (sc->sc_type) { 2649 case WM_T_82544: 2650 case WM_T_82540: 2651 case WM_T_82545: 2652 case WM_T_82546: 2653 case WM_T_82541: 2654 case WM_T_82541_2: 2655 /* 2656 * On some chipsets, a reset through a memory-mapped write 2657 * cycle can cause the chip to reset before completing the 2658 * write cycle. This causes major headache that can be 2659 * avoided by issuing the reset via indirect register writes 2660 * through I/O space. 2661 * 2662 * So, if we successfully mapped the I/O BAR at attach time, 2663 * use that. Otherwise, try our luck with a memory-mapped 2664 * reset. 2665 */ 2666 if (sc->sc_flags & WM_F_IOH_VALID) 2667 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2668 else 2669 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2670 break; 2671 2672 case WM_T_82545_3: 2673 case WM_T_82546_3: 2674 /* Use the shadow control register on these chips. */ 2675 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2676 break; 2677 2678 default: 2679 /* Everything else can safely use the documented method. */ 2680 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2681 break; 2682 } 2683 delay(10000); 2684 2685 for (i = 0; i < 1000; i++) { 2686 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2687 return; 2688 delay(20); 2689 } 2690 2691 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2692 log(LOG_ERR, "%s: reset failed to complete\n", 2693 sc->sc_dev.dv_xname); 2694 } 2695 2696 /* 2697 * wm_init: [ifnet interface function] 2698 * 2699 * Initialize the interface. Must be called at splnet(). 2700 */ 2701 static int 2702 wm_init(struct ifnet *ifp) 2703 { 2704 struct wm_softc *sc = ifp->if_softc; 2705 struct wm_rxsoft *rxs; 2706 int i, error = 0; 2707 uint32_t reg; 2708 2709 /* 2710 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2711 * There is a small but measurable benefit to avoiding the adjusment 2712 * of the descriptor so that the headers are aligned, for normal mtu, 2713 * on such platforms. One possibility is that the DMA itself is 2714 * slightly more efficient if the front of the entire packet (instead 2715 * of the front of the headers) is aligned. 2716 * 2717 * Note we must always set align_tweak to 0 if we are using 2718 * jumbo frames. 2719 */ 2720 #ifdef __NO_STRICT_ALIGNMENT 2721 sc->sc_align_tweak = 0; 2722 #else 2723 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2724 sc->sc_align_tweak = 0; 2725 else 2726 sc->sc_align_tweak = 2; 2727 #endif /* __NO_STRICT_ALIGNMENT */ 2728 2729 /* Cancel any pending I/O. */ 2730 wm_stop(ifp, 0); 2731 2732 /* Reset the chip to a known state. */ 2733 wm_reset(sc); 2734 2735 /* Initialize the transmit descriptor ring. */ 2736 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2737 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2738 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2739 sc->sc_txfree = WM_NTXDESC(sc); 2740 sc->sc_txnext = 0; 2741 2742 if (sc->sc_type < WM_T_82543) { 2743 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2744 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2745 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2746 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2747 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2748 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2749 } else { 2750 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2751 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2752 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2753 CSR_WRITE(sc, WMREG_TDH, 0); 2754 CSR_WRITE(sc, WMREG_TDT, 0); 2755 CSR_WRITE(sc, WMREG_TIDV, 64); 2756 CSR_WRITE(sc, WMREG_TADV, 128); 2757 2758 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2759 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2760 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2761 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2762 } 2763 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2764 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2765 2766 /* Initialize the transmit job descriptors. */ 2767 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2768 sc->sc_txsoft[i].txs_mbuf = NULL; 2769 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2770 sc->sc_txsnext = 0; 2771 sc->sc_txsdirty = 0; 2772 2773 /* 2774 * Initialize the receive descriptor and receive job 2775 * descriptor rings. 2776 */ 2777 if (sc->sc_type < WM_T_82543) { 2778 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2779 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2780 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2781 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2782 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2783 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2784 2785 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2786 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2787 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2788 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2789 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2790 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2791 } else { 2792 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2793 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2794 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2795 CSR_WRITE(sc, WMREG_RDH, 0); 2796 CSR_WRITE(sc, WMREG_RDT, 0); 2797 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2798 CSR_WRITE(sc, WMREG_RADV, 128); 2799 } 2800 for (i = 0; i < WM_NRXDESC; i++) { 2801 rxs = &sc->sc_rxsoft[i]; 2802 if (rxs->rxs_mbuf == NULL) { 2803 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2804 log(LOG_ERR, "%s: unable to allocate or map rx " 2805 "buffer %d, error = %d\n", 2806 sc->sc_dev.dv_xname, i, error); 2807 /* 2808 * XXX Should attempt to run with fewer receive 2809 * XXX buffers instead of just failing. 2810 */ 2811 wm_rxdrain(sc); 2812 goto out; 2813 } 2814 } else 2815 WM_INIT_RXDESC(sc, i); 2816 } 2817 sc->sc_rxptr = 0; 2818 sc->sc_rxdiscard = 0; 2819 WM_RXCHAIN_RESET(sc); 2820 2821 /* 2822 * Clear out the VLAN table -- we don't use it (yet). 2823 */ 2824 CSR_WRITE(sc, WMREG_VET, 0); 2825 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2826 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2827 2828 /* 2829 * Set up flow-control parameters. 2830 * 2831 * XXX Values could probably stand some tuning. 2832 */ 2833 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2834 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2835 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2836 2837 sc->sc_fcrtl = FCRTL_DFLT; 2838 if (sc->sc_type < WM_T_82543) { 2839 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2840 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2841 } else { 2842 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2843 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2844 } 2845 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2846 2847 #if 0 /* XXXJRT */ 2848 /* Deal with VLAN enables. */ 2849 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2850 sc->sc_ctrl |= CTRL_VME; 2851 else 2852 #endif /* XXXJRT */ 2853 sc->sc_ctrl &= ~CTRL_VME; 2854 2855 /* Write the control registers. */ 2856 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2857 #if 0 2858 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2859 #endif 2860 2861 /* 2862 * Set up checksum offload parameters. 2863 */ 2864 reg = CSR_READ(sc, WMREG_RXCSUM); 2865 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2866 reg |= RXCSUM_IPOFL; 2867 else 2868 reg &= ~RXCSUM_IPOFL; 2869 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2870 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2871 else { 2872 reg &= ~RXCSUM_TUOFL; 2873 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 2874 reg &= ~RXCSUM_IPOFL; 2875 } 2876 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2877 2878 /* 2879 * Set up the interrupt registers. 2880 */ 2881 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2882 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2883 ICR_RXO | ICR_RXT0; 2884 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2885 sc->sc_icr |= ICR_RXCFG; 2886 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2887 2888 /* Set up the inter-packet gap. */ 2889 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2890 2891 if (sc->sc_type >= WM_T_82543) { 2892 /* Set up the interrupt throttling register (units of 256ns) */ 2893 sc->sc_itr = 1000000000 / (7000 * 256); 2894 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 2895 } 2896 2897 #if 0 /* XXXJRT */ 2898 /* Set the VLAN ethernetype. */ 2899 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2900 #endif 2901 2902 /* 2903 * Set up the transmit control register; we start out with 2904 * a collision distance suitable for FDX, but update it whe 2905 * we resolve the media type. 2906 */ 2907 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2908 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2909 if (sc->sc_type >= WM_T_82571) 2910 sc->sc_tctl |= TCTL_MULR; 2911 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2912 2913 /* Set the media. */ 2914 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2915 2916 /* 2917 * Set up the receive control register; we actually program 2918 * the register when we set the receive filter. Use multicast 2919 * address offset type 0. 2920 * 2921 * Only the i82544 has the ability to strip the incoming 2922 * CRC, so we don't enable that feature. 2923 */ 2924 sc->sc_mchash_type = 0; 2925 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF 2926 | RCTL_MO(sc->sc_mchash_type); 2927 2928 /* 82573 doesn't support jumbo frame */ 2929 if (sc->sc_type != WM_T_82573) 2930 sc->sc_rctl |= RCTL_LPE; 2931 2932 if (MCLBYTES == 2048) { 2933 sc->sc_rctl |= RCTL_2k; 2934 } else { 2935 if (sc->sc_type >= WM_T_82543) { 2936 switch(MCLBYTES) { 2937 case 4096: 2938 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2939 break; 2940 case 8192: 2941 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2942 break; 2943 case 16384: 2944 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2945 break; 2946 default: 2947 panic("wm_init: MCLBYTES %d unsupported", 2948 MCLBYTES); 2949 break; 2950 } 2951 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2952 } 2953 2954 /* Set the receive filter. */ 2955 wm_set_filter(sc); 2956 2957 /* Start the one second link check clock. */ 2958 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2959 2960 /* ...all done! */ 2961 ifp->if_flags |= IFF_RUNNING; 2962 ifp->if_flags &= ~IFF_OACTIVE; 2963 2964 out: 2965 if (error) 2966 log(LOG_ERR, "%s: interface not running\n", 2967 sc->sc_dev.dv_xname); 2968 return (error); 2969 } 2970 2971 /* 2972 * wm_rxdrain: 2973 * 2974 * Drain the receive queue. 2975 */ 2976 static void 2977 wm_rxdrain(struct wm_softc *sc) 2978 { 2979 struct wm_rxsoft *rxs; 2980 int i; 2981 2982 for (i = 0; i < WM_NRXDESC; i++) { 2983 rxs = &sc->sc_rxsoft[i]; 2984 if (rxs->rxs_mbuf != NULL) { 2985 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2986 m_freem(rxs->rxs_mbuf); 2987 rxs->rxs_mbuf = NULL; 2988 } 2989 } 2990 } 2991 2992 /* 2993 * wm_stop: [ifnet interface function] 2994 * 2995 * Stop transmission on the interface. 2996 */ 2997 static void 2998 wm_stop(struct ifnet *ifp, int disable) 2999 { 3000 struct wm_softc *sc = ifp->if_softc; 3001 struct wm_txsoft *txs; 3002 int i; 3003 3004 /* Stop the one second clock. */ 3005 callout_stop(&sc->sc_tick_ch); 3006 3007 /* Stop the 82547 Tx FIFO stall check timer. */ 3008 if (sc->sc_type == WM_T_82547) 3009 callout_stop(&sc->sc_txfifo_ch); 3010 3011 if (sc->sc_flags & WM_F_HAS_MII) { 3012 /* Down the MII. */ 3013 mii_down(&sc->sc_mii); 3014 } 3015 3016 /* Stop the transmit and receive processes. */ 3017 CSR_WRITE(sc, WMREG_TCTL, 0); 3018 CSR_WRITE(sc, WMREG_RCTL, 0); 3019 3020 /* 3021 * Clear the interrupt mask to ensure the device cannot assert its 3022 * interrupt line. 3023 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 3024 * any currently pending or shared interrupt. 3025 */ 3026 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3027 sc->sc_icr = 0; 3028 3029 /* Release any queued transmit buffers. */ 3030 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 3031 txs = &sc->sc_txsoft[i]; 3032 if (txs->txs_mbuf != NULL) { 3033 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3034 m_freem(txs->txs_mbuf); 3035 txs->txs_mbuf = NULL; 3036 } 3037 } 3038 3039 if (disable) 3040 wm_rxdrain(sc); 3041 3042 /* Mark the interface as down and cancel the watchdog timer. */ 3043 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3044 ifp->if_timer = 0; 3045 } 3046 3047 /* 3048 * wm_acquire_eeprom: 3049 * 3050 * Perform the EEPROM handshake required on some chips. 3051 */ 3052 static int 3053 wm_acquire_eeprom(struct wm_softc *sc) 3054 { 3055 uint32_t reg; 3056 int x; 3057 3058 /* always success */ 3059 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 3060 return 0; 3061 3062 if (wm_get_eeprom_semaphore(sc)) 3063 return 1; 3064 3065 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3066 reg = CSR_READ(sc, WMREG_EECD); 3067 3068 /* Request EEPROM access. */ 3069 reg |= EECD_EE_REQ; 3070 CSR_WRITE(sc, WMREG_EECD, reg); 3071 3072 /* ..and wait for it to be granted. */ 3073 for (x = 0; x < 1000; x++) { 3074 reg = CSR_READ(sc, WMREG_EECD); 3075 if (reg & EECD_EE_GNT) 3076 break; 3077 delay(5); 3078 } 3079 if ((reg & EECD_EE_GNT) == 0) { 3080 aprint_error("%s: could not acquire EEPROM GNT\n", 3081 sc->sc_dev.dv_xname); 3082 reg &= ~EECD_EE_REQ; 3083 CSR_WRITE(sc, WMREG_EECD, reg); 3084 wm_put_eeprom_semaphore(sc); 3085 return (1); 3086 } 3087 } 3088 3089 return (0); 3090 } 3091 3092 /* 3093 * wm_release_eeprom: 3094 * 3095 * Release the EEPROM mutex. 3096 */ 3097 static void 3098 wm_release_eeprom(struct wm_softc *sc) 3099 { 3100 uint32_t reg; 3101 3102 /* always success */ 3103 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 3104 return; 3105 3106 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3107 reg = CSR_READ(sc, WMREG_EECD); 3108 reg &= ~EECD_EE_REQ; 3109 CSR_WRITE(sc, WMREG_EECD, reg); 3110 } 3111 3112 wm_put_eeprom_semaphore(sc); 3113 } 3114 3115 /* 3116 * wm_eeprom_sendbits: 3117 * 3118 * Send a series of bits to the EEPROM. 3119 */ 3120 static void 3121 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 3122 { 3123 uint32_t reg; 3124 int x; 3125 3126 reg = CSR_READ(sc, WMREG_EECD); 3127 3128 for (x = nbits; x > 0; x--) { 3129 if (bits & (1U << (x - 1))) 3130 reg |= EECD_DI; 3131 else 3132 reg &= ~EECD_DI; 3133 CSR_WRITE(sc, WMREG_EECD, reg); 3134 delay(2); 3135 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3136 delay(2); 3137 CSR_WRITE(sc, WMREG_EECD, reg); 3138 delay(2); 3139 } 3140 } 3141 3142 /* 3143 * wm_eeprom_recvbits: 3144 * 3145 * Receive a series of bits from the EEPROM. 3146 */ 3147 static void 3148 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 3149 { 3150 uint32_t reg, val; 3151 int x; 3152 3153 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 3154 3155 val = 0; 3156 for (x = nbits; x > 0; x--) { 3157 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3158 delay(2); 3159 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 3160 val |= (1U << (x - 1)); 3161 CSR_WRITE(sc, WMREG_EECD, reg); 3162 delay(2); 3163 } 3164 *valp = val; 3165 } 3166 3167 /* 3168 * wm_read_eeprom_uwire: 3169 * 3170 * Read a word from the EEPROM using the MicroWire protocol. 3171 */ 3172 static int 3173 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3174 { 3175 uint32_t reg, val; 3176 int i; 3177 3178 for (i = 0; i < wordcnt; i++) { 3179 /* Clear SK and DI. */ 3180 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3181 CSR_WRITE(sc, WMREG_EECD, reg); 3182 3183 /* Set CHIP SELECT. */ 3184 reg |= EECD_CS; 3185 CSR_WRITE(sc, WMREG_EECD, reg); 3186 delay(2); 3187 3188 /* Shift in the READ command. */ 3189 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3190 3191 /* Shift in address. */ 3192 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3193 3194 /* Shift out the data. */ 3195 wm_eeprom_recvbits(sc, &val, 16); 3196 data[i] = val & 0xffff; 3197 3198 /* Clear CHIP SELECT. */ 3199 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3200 CSR_WRITE(sc, WMREG_EECD, reg); 3201 delay(2); 3202 } 3203 3204 return (0); 3205 } 3206 3207 /* 3208 * wm_spi_eeprom_ready: 3209 * 3210 * Wait for a SPI EEPROM to be ready for commands. 3211 */ 3212 static int 3213 wm_spi_eeprom_ready(struct wm_softc *sc) 3214 { 3215 uint32_t val; 3216 int usec; 3217 3218 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3219 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3220 wm_eeprom_recvbits(sc, &val, 8); 3221 if ((val & SPI_SR_RDY) == 0) 3222 break; 3223 } 3224 if (usec >= SPI_MAX_RETRIES) { 3225 aprint_error("%s: EEPROM failed to become ready\n", 3226 sc->sc_dev.dv_xname); 3227 return (1); 3228 } 3229 return (0); 3230 } 3231 3232 /* 3233 * wm_read_eeprom_spi: 3234 * 3235 * Read a work from the EEPROM using the SPI protocol. 3236 */ 3237 static int 3238 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3239 { 3240 uint32_t reg, val; 3241 int i; 3242 uint8_t opc; 3243 3244 /* Clear SK and CS. */ 3245 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3246 CSR_WRITE(sc, WMREG_EECD, reg); 3247 delay(2); 3248 3249 if (wm_spi_eeprom_ready(sc)) 3250 return (1); 3251 3252 /* Toggle CS to flush commands. */ 3253 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3254 delay(2); 3255 CSR_WRITE(sc, WMREG_EECD, reg); 3256 delay(2); 3257 3258 opc = SPI_OPC_READ; 3259 if (sc->sc_ee_addrbits == 8 && word >= 128) 3260 opc |= SPI_OPC_A8; 3261 3262 wm_eeprom_sendbits(sc, opc, 8); 3263 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3264 3265 for (i = 0; i < wordcnt; i++) { 3266 wm_eeprom_recvbits(sc, &val, 16); 3267 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3268 } 3269 3270 /* Raise CS and clear SK. */ 3271 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3272 CSR_WRITE(sc, WMREG_EECD, reg); 3273 delay(2); 3274 3275 return (0); 3276 } 3277 3278 #define EEPROM_CHECKSUM 0xBABA 3279 #define EEPROM_SIZE 0x0040 3280 3281 /* 3282 * wm_validate_eeprom_checksum 3283 * 3284 * The checksum is defined as the sum of the first 64 (16 bit) words. 3285 */ 3286 static int 3287 wm_validate_eeprom_checksum(struct wm_softc *sc) 3288 { 3289 uint16_t checksum; 3290 uint16_t eeprom_data; 3291 int i; 3292 3293 checksum = 0; 3294 3295 for (i = 0; i < EEPROM_SIZE; i++) { 3296 if (wm_read_eeprom(sc, i, 1, &eeprom_data)) 3297 return 1; 3298 checksum += eeprom_data; 3299 } 3300 3301 if (checksum != (uint16_t) EEPROM_CHECKSUM) 3302 return 1; 3303 3304 return 0; 3305 } 3306 3307 /* 3308 * wm_read_eeprom: 3309 * 3310 * Read data from the serial EEPROM. 3311 */ 3312 static int 3313 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3314 { 3315 int rv; 3316 3317 if (sc->sc_flags & WM_F_EEPROM_INVALID) 3318 return 1; 3319 3320 if (wm_acquire_eeprom(sc)) 3321 return 1; 3322 3323 if (sc->sc_flags & WM_F_EEPROM_EERDEEWR) 3324 rv = wm_read_eeprom_eerd(sc, word, wordcnt, data); 3325 else if (sc->sc_flags & WM_F_EEPROM_SPI) 3326 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3327 else 3328 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3329 3330 wm_release_eeprom(sc); 3331 return rv; 3332 } 3333 3334 static int 3335 wm_read_eeprom_eerd(struct wm_softc *sc, int offset, int wordcnt, 3336 uint16_t *data) 3337 { 3338 int i, eerd = 0; 3339 int error = 0; 3340 3341 for (i = 0; i < wordcnt; i++) { 3342 eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START; 3343 3344 CSR_WRITE(sc, WMREG_EERD, eerd); 3345 error = wm_poll_eerd_eewr_done(sc, WMREG_EERD); 3346 if (error != 0) 3347 break; 3348 3349 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT); 3350 } 3351 3352 return error; 3353 } 3354 3355 static int 3356 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw) 3357 { 3358 uint32_t attempts = 100000; 3359 uint32_t i, reg = 0; 3360 int32_t done = -1; 3361 3362 for (i = 0; i < attempts; i++) { 3363 reg = CSR_READ(sc, rw); 3364 3365 if (reg & EERD_DONE) { 3366 done = 0; 3367 break; 3368 } 3369 delay(5); 3370 } 3371 3372 return done; 3373 } 3374 3375 /* 3376 * wm_add_rxbuf: 3377 * 3378 * Add a receive buffer to the indiciated descriptor. 3379 */ 3380 static int 3381 wm_add_rxbuf(struct wm_softc *sc, int idx) 3382 { 3383 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3384 struct mbuf *m; 3385 int error; 3386 3387 MGETHDR(m, M_DONTWAIT, MT_DATA); 3388 if (m == NULL) 3389 return (ENOBUFS); 3390 3391 MCLGET(m, M_DONTWAIT); 3392 if ((m->m_flags & M_EXT) == 0) { 3393 m_freem(m); 3394 return (ENOBUFS); 3395 } 3396 3397 if (rxs->rxs_mbuf != NULL) 3398 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3399 3400 rxs->rxs_mbuf = m; 3401 3402 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3403 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3404 BUS_DMA_READ|BUS_DMA_NOWAIT); 3405 if (error) { 3406 /* XXX XXX XXX */ 3407 printf("%s: unable to load rx DMA map %d, error = %d\n", 3408 sc->sc_dev.dv_xname, idx, error); 3409 panic("wm_add_rxbuf"); 3410 } 3411 3412 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3413 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3414 3415 WM_INIT_RXDESC(sc, idx); 3416 3417 return (0); 3418 } 3419 3420 /* 3421 * wm_set_ral: 3422 * 3423 * Set an entery in the receive address list. 3424 */ 3425 static void 3426 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3427 { 3428 uint32_t ral_lo, ral_hi; 3429 3430 if (enaddr != NULL) { 3431 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3432 (enaddr[3] << 24); 3433 ral_hi = enaddr[4] | (enaddr[5] << 8); 3434 ral_hi |= RAL_AV; 3435 } else { 3436 ral_lo = 0; 3437 ral_hi = 0; 3438 } 3439 3440 if (sc->sc_type >= WM_T_82544) { 3441 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3442 ral_lo); 3443 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3444 ral_hi); 3445 } else { 3446 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3447 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3448 } 3449 } 3450 3451 /* 3452 * wm_mchash: 3453 * 3454 * Compute the hash of the multicast address for the 4096-bit 3455 * multicast filter. 3456 */ 3457 static uint32_t 3458 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3459 { 3460 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3461 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3462 uint32_t hash; 3463 3464 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3465 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3466 3467 return (hash & 0xfff); 3468 } 3469 3470 /* 3471 * wm_set_filter: 3472 * 3473 * Set up the receive filter. 3474 */ 3475 static void 3476 wm_set_filter(struct wm_softc *sc) 3477 { 3478 struct ethercom *ec = &sc->sc_ethercom; 3479 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3480 struct ether_multi *enm; 3481 struct ether_multistep step; 3482 bus_addr_t mta_reg; 3483 uint32_t hash, reg, bit; 3484 int i; 3485 3486 if (sc->sc_type >= WM_T_82544) 3487 mta_reg = WMREG_CORDOVA_MTA; 3488 else 3489 mta_reg = WMREG_MTA; 3490 3491 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3492 3493 if (ifp->if_flags & IFF_BROADCAST) 3494 sc->sc_rctl |= RCTL_BAM; 3495 if (ifp->if_flags & IFF_PROMISC) { 3496 sc->sc_rctl |= RCTL_UPE; 3497 goto allmulti; 3498 } 3499 3500 /* 3501 * Set the station address in the first RAL slot, and 3502 * clear the remaining slots. 3503 */ 3504 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3505 for (i = 1; i < WM_RAL_TABSIZE; i++) 3506 wm_set_ral(sc, NULL, i); 3507 3508 /* Clear out the multicast table. */ 3509 for (i = 0; i < WM_MC_TABSIZE; i++) 3510 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3511 3512 ETHER_FIRST_MULTI(step, ec, enm); 3513 while (enm != NULL) { 3514 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3515 /* 3516 * We must listen to a range of multicast addresses. 3517 * For now, just accept all multicasts, rather than 3518 * trying to set only those filter bits needed to match 3519 * the range. (At this time, the only use of address 3520 * ranges is for IP multicast routing, for which the 3521 * range is big enough to require all bits set.) 3522 */ 3523 goto allmulti; 3524 } 3525 3526 hash = wm_mchash(sc, enm->enm_addrlo); 3527 3528 reg = (hash >> 5) & 0x7f; 3529 bit = hash & 0x1f; 3530 3531 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3532 hash |= 1U << bit; 3533 3534 /* XXX Hardware bug?? */ 3535 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3536 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3537 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3538 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3539 } else 3540 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3541 3542 ETHER_NEXT_MULTI(step, enm); 3543 } 3544 3545 ifp->if_flags &= ~IFF_ALLMULTI; 3546 goto setit; 3547 3548 allmulti: 3549 ifp->if_flags |= IFF_ALLMULTI; 3550 sc->sc_rctl |= RCTL_MPE; 3551 3552 setit: 3553 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3554 } 3555 3556 /* 3557 * wm_tbi_mediainit: 3558 * 3559 * Initialize media for use on 1000BASE-X devices. 3560 */ 3561 static void 3562 wm_tbi_mediainit(struct wm_softc *sc) 3563 { 3564 const char *sep = ""; 3565 3566 if (sc->sc_type < WM_T_82543) 3567 sc->sc_tipg = TIPG_WM_DFLT; 3568 else 3569 sc->sc_tipg = TIPG_LG_DFLT; 3570 3571 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3572 wm_tbi_mediastatus); 3573 3574 /* 3575 * SWD Pins: 3576 * 3577 * 0 = Link LED (output) 3578 * 1 = Loss Of Signal (input) 3579 */ 3580 sc->sc_ctrl |= CTRL_SWDPIO(0); 3581 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3582 3583 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3584 3585 #define ADD(ss, mm, dd) \ 3586 do { \ 3587 aprint_normal("%s%s", sep, ss); \ 3588 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3589 sep = ", "; \ 3590 } while (/*CONSTCOND*/0) 3591 3592 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3593 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3594 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3595 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3596 aprint_normal("\n"); 3597 3598 #undef ADD 3599 3600 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3601 } 3602 3603 /* 3604 * wm_tbi_mediastatus: [ifmedia interface function] 3605 * 3606 * Get the current interface media status on a 1000BASE-X device. 3607 */ 3608 static void 3609 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3610 { 3611 struct wm_softc *sc = ifp->if_softc; 3612 uint32_t ctrl; 3613 3614 ifmr->ifm_status = IFM_AVALID; 3615 ifmr->ifm_active = IFM_ETHER; 3616 3617 if (sc->sc_tbi_linkup == 0) { 3618 ifmr->ifm_active |= IFM_NONE; 3619 return; 3620 } 3621 3622 ifmr->ifm_status |= IFM_ACTIVE; 3623 ifmr->ifm_active |= IFM_1000_SX; 3624 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3625 ifmr->ifm_active |= IFM_FDX; 3626 ctrl = CSR_READ(sc, WMREG_CTRL); 3627 if (ctrl & CTRL_RFCE) 3628 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3629 if (ctrl & CTRL_TFCE) 3630 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3631 } 3632 3633 /* 3634 * wm_tbi_mediachange: [ifmedia interface function] 3635 * 3636 * Set hardware to newly-selected media on a 1000BASE-X device. 3637 */ 3638 static int 3639 wm_tbi_mediachange(struct ifnet *ifp) 3640 { 3641 struct wm_softc *sc = ifp->if_softc; 3642 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3643 uint32_t status; 3644 int i; 3645 3646 sc->sc_txcw = ife->ifm_data; 3647 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3648 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3649 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3650 sc->sc_txcw |= TXCW_ANE; 3651 3652 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3653 delay(10000); 3654 3655 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3656 3657 sc->sc_tbi_anstate = 0; 3658 3659 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3660 /* Have signal; wait for the link to come up. */ 3661 for (i = 0; i < 50; i++) { 3662 delay(10000); 3663 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3664 break; 3665 } 3666 3667 status = CSR_READ(sc, WMREG_STATUS); 3668 if (status & STATUS_LU) { 3669 /* Link is up. */ 3670 DPRINTF(WM_DEBUG_LINK, 3671 ("%s: LINK: set media -> link up %s\n", 3672 sc->sc_dev.dv_xname, 3673 (status & STATUS_FD) ? "FDX" : "HDX")); 3674 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3675 sc->sc_fcrtl &= ~FCRTL_XONE; 3676 if (status & STATUS_FD) 3677 sc->sc_tctl |= 3678 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3679 else 3680 sc->sc_tctl |= 3681 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3682 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3683 sc->sc_fcrtl |= FCRTL_XONE; 3684 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3685 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3686 WMREG_OLD_FCRTL : WMREG_FCRTL, 3687 sc->sc_fcrtl); 3688 sc->sc_tbi_linkup = 1; 3689 } else { 3690 /* Link is down. */ 3691 DPRINTF(WM_DEBUG_LINK, 3692 ("%s: LINK: set media -> link down\n", 3693 sc->sc_dev.dv_xname)); 3694 sc->sc_tbi_linkup = 0; 3695 } 3696 } else { 3697 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3698 sc->sc_dev.dv_xname)); 3699 sc->sc_tbi_linkup = 0; 3700 } 3701 3702 wm_tbi_set_linkled(sc); 3703 3704 return (0); 3705 } 3706 3707 /* 3708 * wm_tbi_set_linkled: 3709 * 3710 * Update the link LED on 1000BASE-X devices. 3711 */ 3712 static void 3713 wm_tbi_set_linkled(struct wm_softc *sc) 3714 { 3715 3716 if (sc->sc_tbi_linkup) 3717 sc->sc_ctrl |= CTRL_SWDPIN(0); 3718 else 3719 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3720 3721 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3722 } 3723 3724 /* 3725 * wm_tbi_check_link: 3726 * 3727 * Check the link on 1000BASE-X devices. 3728 */ 3729 static void 3730 wm_tbi_check_link(struct wm_softc *sc) 3731 { 3732 uint32_t rxcw, ctrl, status; 3733 3734 if (sc->sc_tbi_anstate == 0) 3735 return; 3736 else if (sc->sc_tbi_anstate > 1) { 3737 DPRINTF(WM_DEBUG_LINK, 3738 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3739 sc->sc_tbi_anstate)); 3740 sc->sc_tbi_anstate--; 3741 return; 3742 } 3743 3744 sc->sc_tbi_anstate = 0; 3745 3746 rxcw = CSR_READ(sc, WMREG_RXCW); 3747 ctrl = CSR_READ(sc, WMREG_CTRL); 3748 status = CSR_READ(sc, WMREG_STATUS); 3749 3750 if ((status & STATUS_LU) == 0) { 3751 DPRINTF(WM_DEBUG_LINK, 3752 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3753 sc->sc_tbi_linkup = 0; 3754 } else { 3755 DPRINTF(WM_DEBUG_LINK, 3756 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3757 (status & STATUS_FD) ? "FDX" : "HDX")); 3758 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3759 sc->sc_fcrtl &= ~FCRTL_XONE; 3760 if (status & STATUS_FD) 3761 sc->sc_tctl |= 3762 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3763 else 3764 sc->sc_tctl |= 3765 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3766 if (ctrl & CTRL_TFCE) 3767 sc->sc_fcrtl |= FCRTL_XONE; 3768 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3769 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3770 WMREG_OLD_FCRTL : WMREG_FCRTL, 3771 sc->sc_fcrtl); 3772 sc->sc_tbi_linkup = 1; 3773 } 3774 3775 wm_tbi_set_linkled(sc); 3776 } 3777 3778 /* 3779 * wm_gmii_reset: 3780 * 3781 * Reset the PHY. 3782 */ 3783 static void 3784 wm_gmii_reset(struct wm_softc *sc) 3785 { 3786 uint32_t reg; 3787 3788 if (sc->sc_type >= WM_T_82544) { 3789 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3790 delay(20000); 3791 3792 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3793 delay(20000); 3794 } else { 3795 /* The PHY reset pin is active-low. */ 3796 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3797 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3798 CTRL_EXT_SWDPIN(4)); 3799 reg |= CTRL_EXT_SWDPIO(4); 3800 3801 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3802 delay(10); 3803 3804 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3805 delay(10); 3806 3807 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3808 delay(10); 3809 #if 0 3810 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3811 #endif 3812 } 3813 } 3814 3815 /* 3816 * wm_gmii_mediainit: 3817 * 3818 * Initialize media for use on 1000BASE-T devices. 3819 */ 3820 static void 3821 wm_gmii_mediainit(struct wm_softc *sc) 3822 { 3823 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3824 3825 /* We have MII. */ 3826 sc->sc_flags |= WM_F_HAS_MII; 3827 3828 sc->sc_tipg = TIPG_1000T_DFLT; 3829 3830 /* 3831 * Let the chip set speed/duplex on its own based on 3832 * signals from the PHY. 3833 */ 3834 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3835 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3836 3837 /* Initialize our media structures and probe the GMII. */ 3838 sc->sc_mii.mii_ifp = ifp; 3839 3840 if (sc->sc_type >= WM_T_82544) { 3841 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3842 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3843 } else { 3844 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3845 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3846 } 3847 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3848 3849 wm_gmii_reset(sc); 3850 3851 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3852 wm_gmii_mediastatus); 3853 3854 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3855 MII_OFFSET_ANY, MIIF_DOPAUSE); 3856 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3857 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3858 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3859 } else 3860 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3861 } 3862 3863 /* 3864 * wm_gmii_mediastatus: [ifmedia interface function] 3865 * 3866 * Get the current interface media status on a 1000BASE-T device. 3867 */ 3868 static void 3869 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3870 { 3871 struct wm_softc *sc = ifp->if_softc; 3872 3873 mii_pollstat(&sc->sc_mii); 3874 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3875 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3876 sc->sc_flowflags; 3877 } 3878 3879 /* 3880 * wm_gmii_mediachange: [ifmedia interface function] 3881 * 3882 * Set hardware to newly-selected media on a 1000BASE-T device. 3883 */ 3884 static int 3885 wm_gmii_mediachange(struct ifnet *ifp) 3886 { 3887 struct wm_softc *sc = ifp->if_softc; 3888 3889 if (ifp->if_flags & IFF_UP) 3890 mii_mediachg(&sc->sc_mii); 3891 return (0); 3892 } 3893 3894 #define MDI_IO CTRL_SWDPIN(2) 3895 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3896 #define MDI_CLK CTRL_SWDPIN(3) 3897 3898 static void 3899 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3900 { 3901 uint32_t i, v; 3902 3903 v = CSR_READ(sc, WMREG_CTRL); 3904 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3905 v |= MDI_DIR | CTRL_SWDPIO(3); 3906 3907 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3908 if (data & i) 3909 v |= MDI_IO; 3910 else 3911 v &= ~MDI_IO; 3912 CSR_WRITE(sc, WMREG_CTRL, v); 3913 delay(10); 3914 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3915 delay(10); 3916 CSR_WRITE(sc, WMREG_CTRL, v); 3917 delay(10); 3918 } 3919 } 3920 3921 static uint32_t 3922 i82543_mii_recvbits(struct wm_softc *sc) 3923 { 3924 uint32_t v, i, data = 0; 3925 3926 v = CSR_READ(sc, WMREG_CTRL); 3927 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3928 v |= CTRL_SWDPIO(3); 3929 3930 CSR_WRITE(sc, WMREG_CTRL, v); 3931 delay(10); 3932 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3933 delay(10); 3934 CSR_WRITE(sc, WMREG_CTRL, v); 3935 delay(10); 3936 3937 for (i = 0; i < 16; i++) { 3938 data <<= 1; 3939 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3940 delay(10); 3941 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3942 data |= 1; 3943 CSR_WRITE(sc, WMREG_CTRL, v); 3944 delay(10); 3945 } 3946 3947 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3948 delay(10); 3949 CSR_WRITE(sc, WMREG_CTRL, v); 3950 delay(10); 3951 3952 return (data); 3953 } 3954 3955 #undef MDI_IO 3956 #undef MDI_DIR 3957 #undef MDI_CLK 3958 3959 /* 3960 * wm_gmii_i82543_readreg: [mii interface function] 3961 * 3962 * Read a PHY register on the GMII (i82543 version). 3963 */ 3964 static int 3965 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3966 { 3967 struct wm_softc *sc = (void *) self; 3968 int rv; 3969 3970 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3971 i82543_mii_sendbits(sc, reg | (phy << 5) | 3972 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3973 rv = i82543_mii_recvbits(sc) & 0xffff; 3974 3975 DPRINTF(WM_DEBUG_GMII, 3976 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3977 sc->sc_dev.dv_xname, phy, reg, rv)); 3978 3979 return (rv); 3980 } 3981 3982 /* 3983 * wm_gmii_i82543_writereg: [mii interface function] 3984 * 3985 * Write a PHY register on the GMII (i82543 version). 3986 */ 3987 static void 3988 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3989 { 3990 struct wm_softc *sc = (void *) self; 3991 3992 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3993 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3994 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3995 (MII_COMMAND_START << 30), 32); 3996 } 3997 3998 /* 3999 * wm_gmii_i82544_readreg: [mii interface function] 4000 * 4001 * Read a PHY register on the GMII. 4002 */ 4003 static int 4004 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 4005 { 4006 struct wm_softc *sc = (void *) self; 4007 uint32_t mdic = 0; 4008 int i, rv; 4009 4010 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 4011 MDIC_REGADD(reg)); 4012 4013 for (i = 0; i < 100; i++) { 4014 mdic = CSR_READ(sc, WMREG_MDIC); 4015 if (mdic & MDIC_READY) 4016 break; 4017 delay(10); 4018 } 4019 4020 if ((mdic & MDIC_READY) == 0) { 4021 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 4022 sc->sc_dev.dv_xname, phy, reg); 4023 rv = 0; 4024 } else if (mdic & MDIC_E) { 4025 #if 0 /* This is normal if no PHY is present. */ 4026 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 4027 sc->sc_dev.dv_xname, phy, reg); 4028 #endif 4029 rv = 0; 4030 } else { 4031 rv = MDIC_DATA(mdic); 4032 if (rv == 0xffff) 4033 rv = 0; 4034 } 4035 4036 return (rv); 4037 } 4038 4039 /* 4040 * wm_gmii_i82544_writereg: [mii interface function] 4041 * 4042 * Write a PHY register on the GMII. 4043 */ 4044 static void 4045 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 4046 { 4047 struct wm_softc *sc = (void *) self; 4048 uint32_t mdic = 0; 4049 int i; 4050 4051 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 4052 MDIC_REGADD(reg) | MDIC_DATA(val)); 4053 4054 for (i = 0; i < 100; i++) { 4055 mdic = CSR_READ(sc, WMREG_MDIC); 4056 if (mdic & MDIC_READY) 4057 break; 4058 delay(10); 4059 } 4060 4061 if ((mdic & MDIC_READY) == 0) 4062 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 4063 sc->sc_dev.dv_xname, phy, reg); 4064 else if (mdic & MDIC_E) 4065 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 4066 sc->sc_dev.dv_xname, phy, reg); 4067 } 4068 4069 /* 4070 * wm_gmii_statchg: [mii interface function] 4071 * 4072 * Callback from MII layer when media changes. 4073 */ 4074 static void 4075 wm_gmii_statchg(struct device *self) 4076 { 4077 struct wm_softc *sc = (void *) self; 4078 struct mii_data *mii = &sc->sc_mii; 4079 4080 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 4081 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 4082 sc->sc_fcrtl &= ~FCRTL_XONE; 4083 4084 /* 4085 * Get flow control negotiation result. 4086 */ 4087 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 4088 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 4089 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 4090 mii->mii_media_active &= ~IFM_ETH_FMASK; 4091 } 4092 4093 if (sc->sc_flowflags & IFM_FLOW) { 4094 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 4095 sc->sc_ctrl |= CTRL_TFCE; 4096 sc->sc_fcrtl |= FCRTL_XONE; 4097 } 4098 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 4099 sc->sc_ctrl |= CTRL_RFCE; 4100 } 4101 4102 if (sc->sc_mii.mii_media_active & IFM_FDX) { 4103 DPRINTF(WM_DEBUG_LINK, 4104 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 4105 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4106 } else { 4107 DPRINTF(WM_DEBUG_LINK, 4108 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 4109 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 4110 } 4111 4112 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4113 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4114 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 4115 : WMREG_FCRTL, sc->sc_fcrtl); 4116 } 4117 4118 static int 4119 wm_is_onboard_nvm_eeprom(struct wm_softc *sc) 4120 { 4121 uint32_t eecd = 0; 4122 4123 if (sc->sc_type == WM_T_82573) { 4124 eecd = CSR_READ(sc, WMREG_EECD); 4125 4126 /* Isolate bits 15 & 16 */ 4127 eecd = ((eecd >> 15) & 0x03); 4128 4129 /* If both bits are set, device is Flash type */ 4130 if (eecd == 0x03) { 4131 return 0; 4132 } 4133 } 4134 return 1; 4135 } 4136 4137 static int 4138 wm_get_eeprom_semaphore(struct wm_softc *sc) 4139 { 4140 int32_t timeout; 4141 uint32_t swsm; 4142 4143 if ((sc->sc_flags & WM_F_EEPROM_SEMAPHORE) == 0) 4144 return 0; 4145 4146 /* Get the FW semaphore. */ 4147 timeout = 1000 + 1; /* XXX */ 4148 while (timeout) { 4149 swsm = CSR_READ(sc, WMREG_SWSM); 4150 swsm |= SWSM_SWESMBI; 4151 CSR_WRITE(sc, WMREG_SWSM, swsm); 4152 /* if we managed to set the bit we got the semaphore. */ 4153 swsm = CSR_READ(sc, WMREG_SWSM); 4154 if (swsm & SWSM_SWESMBI) 4155 break; 4156 4157 delay(50); 4158 timeout--; 4159 } 4160 4161 if (timeout == 0) { 4162 /* Release semaphores */ 4163 wm_put_eeprom_semaphore(sc); 4164 return 1; 4165 } 4166 4167 return 0; 4168 } 4169 4170 static void 4171 wm_put_eeprom_semaphore(struct wm_softc *sc) 4172 { 4173 uint32_t swsm; 4174 4175 if ((sc->sc_flags & WM_F_EEPROM_SEMAPHORE) == 0) 4176 return; 4177 4178 swsm = CSR_READ(sc, WMREG_SWSM); 4179 swsm &= ~(SWSM_SWESMBI); 4180 CSR_WRITE(sc, WMREG_SWSM, swsm); 4181 } 4182
Indexes created Fri Sep 26 08:10:20 GMT 2025