if_wm.c revision 1.122 1 /* $NetBSD: if_wm.c,v 1.122 2006/06/17 23:34:27 christos Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
40 *
41 * TODO (in order of importance):
42 *
43 * - Rework how parameters are loaded from the EEPROM.
44 * - Figure out what to do with the i82545GM and i82546GB
45 * SERDES controllers.
46 * - Fix hw VLAN assist.
47 */
48
49 #include <sys/cdefs.h>
50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.122 2006/06/17 23:34:27 christos Exp $");
51
52 #include "bpfilter.h"
53 #include "rnd.h"
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/callout.h>
58 #include <sys/mbuf.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/socket.h>
62 #include <sys/ioctl.h>
63 #include <sys/errno.h>
64 #include <sys/device.h>
65 #include <sys/queue.h>
66 #include <sys/syslog.h>
67
68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */
69
70 #if NRND > 0
71 #include <sys/rnd.h>
72 #endif
73
74 #include <net/if.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_ether.h>
78
79 #if NBPFILTER > 0
80 #include <net/bpf.h>
81 #endif
82
83 #include <netinet/in.h> /* XXX for struct ip */
84 #include <netinet/in_systm.h> /* XXX for struct ip */
85 #include <netinet/ip.h> /* XXX for struct ip */
86 #include <netinet/tcp.h> /* XXX for struct tcphdr */
87
88 #include <machine/bus.h>
89 #include <machine/intr.h>
90 #include <machine/endian.h>
91
92 #include <dev/mii/mii.h>
93 #include <dev/mii/miivar.h>
94 #include <dev/mii/mii_bitbang.h>
95
96 #include <dev/pci/pcireg.h>
97 #include <dev/pci/pcivar.h>
98 #include <dev/pci/pcidevs.h>
99
100 #include <dev/pci/if_wmreg.h>
101
102 #ifdef WM_DEBUG
103 #define WM_DEBUG_LINK 0x01
104 #define WM_DEBUG_TX 0x02
105 #define WM_DEBUG_RX 0x04
106 #define WM_DEBUG_GMII 0x08
107 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;
108
109 #define DPRINTF(x, y) if (wm_debug & (x)) printf y
110 #else
111 #define DPRINTF(x, y) /* nothing */
112 #endif /* WM_DEBUG */
113
114 /*
115 * Transmit descriptor list size. Due to errata, we can only have
116 * 256 hardware descriptors in the ring on < 82544, but we use 4096
117 * on >= 82544. We tell the upper layers that they can queue a lot
118 * of packets, and we go ahead and manage up to 64 (16 for the i82547)
119 * of them at a time.
120 *
121 * We allow up to 256 (!) DMA segments per packet. Pathological packet
122 * chains containing many small mbufs have been observed in zero-copy
123 * situations with jumbo frames.
124 */
125 #define WM_NTXSEGS 256
126 #define WM_IFQUEUELEN 256
127 #define WM_TXQUEUELEN_MAX 64
128 #define WM_TXQUEUELEN_MAX_82547 16
129 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum)
130 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1)
131 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8)
132 #define WM_NTXDESC_82542 256
133 #define WM_NTXDESC_82544 4096
134 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc)
135 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1)
136 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t))
137 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc))
138 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc))
139
140 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */
141
142 /*
143 * Receive descriptor list size. We have one Rx buffer for normal
144 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized
145 * packet. We allocate 256 receive descriptors, each with a 2k
146 * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
147 */
148 #define WM_NRXDESC 256
149 #define WM_NRXDESC_MASK (WM_NRXDESC - 1)
150 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK)
151 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK)
152
153 /*
154 * Control structures are DMA'd to the i82542 chip. We allocate them in
155 * a single clump that maps to a single DMA segment to make several things
156 * easier.
157 */
158 struct wm_control_data_82544 {
159 /*
160 * The receive descriptors.
161 */
162 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
163
164 /*
165 * The transmit descriptors. Put these at the end, because
166 * we might use a smaller number of them.
167 */
168 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544];
169 };
170
171 struct wm_control_data_82542 {
172 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
173 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542];
174 };
175
176 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x)
177 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)])
178 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)])
179
180 /*
181 * Software state for transmit jobs.
182 */
183 struct wm_txsoft {
184 struct mbuf *txs_mbuf; /* head of our mbuf chain */
185 bus_dmamap_t txs_dmamap; /* our DMA map */
186 int txs_firstdesc; /* first descriptor in packet */
187 int txs_lastdesc; /* last descriptor in packet */
188 int txs_ndesc; /* # of descriptors used */
189 };
190
191 /*
192 * Software state for receive buffers. Each descriptor gets a
193 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill
194 * more than one buffer, we chain them together.
195 */
196 struct wm_rxsoft {
197 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
198 bus_dmamap_t rxs_dmamap; /* our DMA map */
199 };
200
201 typedef enum {
202 WM_T_unknown = 0,
203 WM_T_82542_2_0, /* i82542 2.0 (really old) */
204 WM_T_82542_2_1, /* i82542 2.1+ (old) */
205 WM_T_82543, /* i82543 */
206 WM_T_82544, /* i82544 */
207 WM_T_82540, /* i82540 */
208 WM_T_82545, /* i82545 */
209 WM_T_82545_3, /* i82545 3.0+ */
210 WM_T_82546, /* i82546 */
211 WM_T_82546_3, /* i82546 3.0+ */
212 WM_T_82541, /* i82541 */
213 WM_T_82541_2, /* i82541 2.0+ */
214 WM_T_82547, /* i82547 */
215 WM_T_82547_2, /* i82547 2.0+ */
216 WM_T_82571, /* i82571 */
217 WM_T_82572, /* i82572 */
218 WM_T_82573, /* i82573 */
219 } wm_chip_type;
220
221 /*
222 * Software state per device.
223 */
224 struct wm_softc {
225 struct device sc_dev; /* generic device information */
226 bus_space_tag_t sc_st; /* bus space tag */
227 bus_space_handle_t sc_sh; /* bus space handle */
228 bus_space_tag_t sc_iot; /* I/O space tag */
229 bus_space_handle_t sc_ioh; /* I/O space handle */
230 bus_dma_tag_t sc_dmat; /* bus DMA tag */
231 struct ethercom sc_ethercom; /* ethernet common data */
232 void *sc_sdhook; /* shutdown hook */
233
234 wm_chip_type sc_type; /* chip type */
235 int sc_flags; /* flags; see below */
236 int sc_bus_speed; /* PCI/PCIX bus speed */
237 int sc_pcix_offset; /* PCIX capability register offset */
238 int sc_flowflags; /* 802.3x flow control flags */
239
240 void *sc_ih; /* interrupt cookie */
241
242 int sc_ee_addrbits; /* EEPROM address bits */
243
244 struct mii_data sc_mii; /* MII/media information */
245
246 struct callout sc_tick_ch; /* tick callout */
247
248 bus_dmamap_t sc_cddmamap; /* control data DMA map */
249 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
250
251 int sc_align_tweak;
252
253 /*
254 * Software state for the transmit and receive descriptors.
255 */
256 int sc_txnum; /* must be a power of two */
257 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX];
258 struct wm_rxsoft sc_rxsoft[WM_NRXDESC];
259
260 /*
261 * Control data structures.
262 */
263 int sc_ntxdesc; /* must be a power of two */
264 struct wm_control_data_82544 *sc_control_data;
265 #define sc_txdescs sc_control_data->wcd_txdescs
266 #define sc_rxdescs sc_control_data->wcd_rxdescs
267
268 #ifdef WM_EVENT_COUNTERS
269 /* Event counters. */
270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */
271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */
272 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
273 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */
274 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */
275 struct evcnt sc_ev_rxintr; /* Rx interrupts */
276 struct evcnt sc_ev_linkintr; /* Link interrupts */
277
278 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */
279 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */
280 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */
281 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */
282 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */
283 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */
284 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */
285
286 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
287 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */
288
289 struct evcnt sc_ev_tu; /* Tx underrun */
290
291 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */
292 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */
293 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */
294 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */
295 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */
296 #endif /* WM_EVENT_COUNTERS */
297
298 bus_addr_t sc_tdt_reg; /* offset of TDT register */
299
300 int sc_txfree; /* number of free Tx descriptors */
301 int sc_txnext; /* next ready Tx descriptor */
302
303 int sc_txsfree; /* number of free Tx jobs */
304 int sc_txsnext; /* next free Tx job */
305 int sc_txsdirty; /* dirty Tx jobs */
306
307 /* These 5 variables are used only on the 82547. */
308 int sc_txfifo_size; /* Tx FIFO size */
309 int sc_txfifo_head; /* current head of FIFO */
310 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */
311 int sc_txfifo_stall; /* Tx FIFO is stalled */
312 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */
313
314 bus_addr_t sc_rdt_reg; /* offset of RDT register */
315
316 int sc_rxptr; /* next ready Rx descriptor/queue ent */
317 int sc_rxdiscard;
318 int sc_rxlen;
319 struct mbuf *sc_rxhead;
320 struct mbuf *sc_rxtail;
321 struct mbuf **sc_rxtailp;
322
323 uint32_t sc_ctrl; /* prototype CTRL register */
324 #if 0
325 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */
326 #endif
327 uint32_t sc_icr; /* prototype interrupt bits */
328 uint32_t sc_itr; /* prototype intr throttling reg */
329 uint32_t sc_tctl; /* prototype TCTL register */
330 uint32_t sc_rctl; /* prototype RCTL register */
331 uint32_t sc_txcw; /* prototype TXCW register */
332 uint32_t sc_tipg; /* prototype TIPG register */
333 uint32_t sc_fcrtl; /* prototype FCRTL register */
334 uint32_t sc_pba; /* prototype PBA register */
335
336 int sc_tbi_linkup; /* TBI link status */
337 int sc_tbi_anstate; /* autonegotiation state */
338
339 int sc_mchash_type; /* multicast filter offset */
340
341 #if NRND > 0
342 rndsource_element_t rnd_source; /* random source */
343 #endif
344 };
345
346 #define WM_RXCHAIN_RESET(sc) \
347 do { \
348 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \
349 *(sc)->sc_rxtailp = NULL; \
350 (sc)->sc_rxlen = 0; \
351 } while (/*CONSTCOND*/0)
352
353 #define WM_RXCHAIN_LINK(sc, m) \
354 do { \
355 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \
356 (sc)->sc_rxtailp = &(m)->m_next; \
357 } while (/*CONSTCOND*/0)
358
359 /* sc_flags */
360 #define WM_F_HAS_MII 0x001 /* has MII */
361 #define WM_F_EEPROM_HANDSHAKE 0x002 /* requires EEPROM handshake */
362 #define WM_F_EEPROM_SEMAPHORE 0x004 /* EEPROM with semaphore */
363 #define WM_F_EEPROM_EERDEEWR 0x008 /* EEPROM access via EERD/EEWR */
364 #define WM_F_EEPROM_SPI 0x010 /* EEPROM is SPI */
365 #define WM_F_EEPROM_FLASH 0x020 /* EEPROM is FLASH */
366 #define WM_F_EEPROM_INVALID 0x040 /* EEPROM not present (bad checksum) */
367 #define WM_F_IOH_VALID 0x080 /* I/O handle is valid */
368 #define WM_F_BUS64 0x100 /* bus is 64-bit */
369 #define WM_F_PCIX 0x200 /* bus is PCI-X */
370 #define WM_F_CSA 0x400 /* bus is CSA */
371 #define WM_F_PCIE 0x800 /* bus is PCI-Express */
372
373 #ifdef WM_EVENT_COUNTERS
374 #define WM_EVCNT_INCR(ev) (ev)->ev_count++
375 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val)
376 #else
377 #define WM_EVCNT_INCR(ev) /* nothing */
378 #define WM_EVCNT_ADD(ev, val) /* nothing */
379 #endif
380
381 #define CSR_READ(sc, reg) \
382 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
383 #define CSR_WRITE(sc, reg, val) \
384 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
385 #define CSR_WRITE_FLUSH(sc) \
386 (void) CSR_READ((sc), WMREG_STATUS)
387
388 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x)))
389 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x)))
390
391 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU)
392 #define WM_CDTXADDR_HI(sc, x) \
393 (sizeof(bus_addr_t) == 8 ? \
394 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
395
396 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU)
397 #define WM_CDRXADDR_HI(sc, x) \
398 (sizeof(bus_addr_t) == 8 ? \
399 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
400
401 #define WM_CDTXSYNC(sc, x, n, ops) \
402 do { \
403 int __x, __n; \
404 \
405 __x = (x); \
406 __n = (n); \
407 \
408 /* If it will wrap around, sync to the end of the ring. */ \
409 if ((__x + __n) > WM_NTXDESC(sc)) { \
410 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
411 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \
412 (WM_NTXDESC(sc) - __x), (ops)); \
413 __n -= (WM_NTXDESC(sc) - __x); \
414 __x = 0; \
415 } \
416 \
417 /* Now sync whatever is left. */ \
418 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
419 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \
420 } while (/*CONSTCOND*/0)
421
422 #define WM_CDRXSYNC(sc, x, ops) \
423 do { \
424 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
425 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \
426 } while (/*CONSTCOND*/0)
427
428 #define WM_INIT_RXDESC(sc, x) \
429 do { \
430 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \
431 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \
432 struct mbuf *__m = __rxs->rxs_mbuf; \
433 \
434 /* \
435 * Note: We scoot the packet forward 2 bytes in the buffer \
436 * so that the payload after the Ethernet header is aligned \
437 * to a 4-byte boundary. \
438 * \
439 * XXX BRAINDAMAGE ALERT! \
440 * The stupid chip uses the same size for every buffer, which \
441 * is set in the Receive Control register. We are using the 2K \
442 * size option, but what we REALLY want is (2K - 2)! For this \
443 * reason, we can't "scoot" packets longer than the standard \
444 * Ethernet MTU. On strict-alignment platforms, if the total \
445 * size exceeds (2K - 2) we set align_tweak to 0 and let \
446 * the upper layer copy the headers. \
447 */ \
448 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \
449 \
450 wm_set_dma_addr(&__rxd->wrx_addr, \
451 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \
452 __rxd->wrx_len = 0; \
453 __rxd->wrx_cksum = 0; \
454 __rxd->wrx_status = 0; \
455 __rxd->wrx_errors = 0; \
456 __rxd->wrx_special = 0; \
457 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
458 \
459 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \
460 } while (/*CONSTCOND*/0)
461
462 static void wm_start(struct ifnet *);
463 static void wm_watchdog(struct ifnet *);
464 static int wm_ioctl(struct ifnet *, u_long, caddr_t);
465 static int wm_init(struct ifnet *);
466 static void wm_stop(struct ifnet *, int);
467
468 static void wm_shutdown(void *);
469
470 static void wm_reset(struct wm_softc *);
471 static void wm_rxdrain(struct wm_softc *);
472 static int wm_add_rxbuf(struct wm_softc *, int);
473 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *);
474 static int wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *);
475 static int wm_validate_eeprom_checksum(struct wm_softc *);
476 static void wm_tick(void *);
477
478 static void wm_set_filter(struct wm_softc *);
479
480 static int wm_intr(void *);
481 static void wm_txintr(struct wm_softc *);
482 static void wm_rxintr(struct wm_softc *);
483 static void wm_linkintr(struct wm_softc *, uint32_t);
484
485 static void wm_tbi_mediainit(struct wm_softc *);
486 static int wm_tbi_mediachange(struct ifnet *);
487 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
488
489 static void wm_tbi_set_linkled(struct wm_softc *);
490 static void wm_tbi_check_link(struct wm_softc *);
491
492 static void wm_gmii_reset(struct wm_softc *);
493
494 static int wm_gmii_i82543_readreg(struct device *, int, int);
495 static void wm_gmii_i82543_writereg(struct device *, int, int, int);
496
497 static int wm_gmii_i82544_readreg(struct device *, int, int);
498 static void wm_gmii_i82544_writereg(struct device *, int, int, int);
499
500 static void wm_gmii_statchg(struct device *);
501
502 static void wm_gmii_mediainit(struct wm_softc *);
503 static int wm_gmii_mediachange(struct ifnet *);
504 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
505
506 static int wm_match(struct device *, struct cfdata *, void *);
507 static void wm_attach(struct device *, struct device *, void *);
508 static int wm_is_onboard_nvm_eeprom(struct wm_softc *);
509 static int wm_get_eeprom_semaphore(struct wm_softc *);
510 static void wm_put_eeprom_semaphore(struct wm_softc *);
511 static int wm_poll_eerd_eewr_done(struct wm_softc *, int);
512
513 CFATTACH_DECL(wm, sizeof(struct wm_softc),
514 wm_match, wm_attach, NULL, NULL);
515
516 static void wm_82547_txfifo_stall(void *);
517
518 /*
519 * Devices supported by this driver.
520 */
521 static const struct wm_product {
522 pci_vendor_id_t wmp_vendor;
523 pci_product_id_t wmp_product;
524 const char *wmp_name;
525 wm_chip_type wmp_type;
526 int wmp_flags;
527 #define WMP_F_1000X 0x01
528 #define WMP_F_1000T 0x02
529 } wm_products[] = {
530 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542,
531 "Intel i82542 1000BASE-X Ethernet",
532 WM_T_82542_2_1, WMP_F_1000X },
533
534 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER,
535 "Intel i82543GC 1000BASE-X Ethernet",
536 WM_T_82543, WMP_F_1000X },
537
538 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER,
539 "Intel i82543GC 1000BASE-T Ethernet",
540 WM_T_82543, WMP_F_1000T },
541
542 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER,
543 "Intel i82544EI 1000BASE-T Ethernet",
544 WM_T_82544, WMP_F_1000T },
545
546 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER,
547 "Intel i82544EI 1000BASE-X Ethernet",
548 WM_T_82544, WMP_F_1000X },
549
550 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER,
551 "Intel i82544GC 1000BASE-T Ethernet",
552 WM_T_82544, WMP_F_1000T },
553
554 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM,
555 "Intel i82544GC (LOM) 1000BASE-T Ethernet",
556 WM_T_82544, WMP_F_1000T },
557
558 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM,
559 "Intel i82540EM 1000BASE-T Ethernet",
560 WM_T_82540, WMP_F_1000T },
561
562 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM,
563 "Intel i82540EM (LOM) 1000BASE-T Ethernet",
564 WM_T_82540, WMP_F_1000T },
565
566 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM,
567 "Intel i82540EP 1000BASE-T Ethernet",
568 WM_T_82540, WMP_F_1000T },
569
570 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP,
571 "Intel i82540EP 1000BASE-T Ethernet",
572 WM_T_82540, WMP_F_1000T },
573
574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP,
575 "Intel i82540EP 1000BASE-T Ethernet",
576 WM_T_82540, WMP_F_1000T },
577
578 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER,
579 "Intel i82545EM 1000BASE-T Ethernet",
580 WM_T_82545, WMP_F_1000T },
581
582 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER,
583 "Intel i82545GM 1000BASE-T Ethernet",
584 WM_T_82545_3, WMP_F_1000T },
585
586 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER,
587 "Intel i82545GM 1000BASE-X Ethernet",
588 WM_T_82545_3, WMP_F_1000X },
589 #if 0
590 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES,
591 "Intel i82545GM Gigabit Ethernet (SERDES)",
592 WM_T_82545_3, WMP_F_SERDES },
593 #endif
594 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER,
595 "Intel i82546EB 1000BASE-T Ethernet",
596 WM_T_82546, WMP_F_1000T },
597
598 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD,
599 "Intel i82546EB 1000BASE-T Ethernet",
600 WM_T_82546, WMP_F_1000T },
601
602 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER,
603 "Intel i82545EM 1000BASE-X Ethernet",
604 WM_T_82545, WMP_F_1000X },
605
606 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER,
607 "Intel i82546EB 1000BASE-X Ethernet",
608 WM_T_82546, WMP_F_1000X },
609
610 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER,
611 "Intel i82546GB 1000BASE-T Ethernet",
612 WM_T_82546_3, WMP_F_1000T },
613
614 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER,
615 "Intel i82546GB 1000BASE-X Ethernet",
616 WM_T_82546_3, WMP_F_1000X },
617 #if 0
618 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES,
619 "Intel i82546GB Gigabit Ethernet (SERDES)",
620 WM_T_82546_3, WMP_F_SERDES },
621 #endif
622 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE,
623 "Intel PRO/1000MT (82546GB)",
624 WM_T_82546_3, WMP_F_1000T },
625
626 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI,
627 "Intel i82541EI 1000BASE-T Ethernet",
628 WM_T_82541, WMP_F_1000T },
629
630 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM,
631 "Intel i82541ER (LOM) 1000BASE-T Ethernet",
632 WM_T_82541, WMP_F_1000T },
633
634 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE,
635 "Intel i82541EI Mobile 1000BASE-T Ethernet",
636 WM_T_82541, WMP_F_1000T },
637
638 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER,
639 "Intel i82541ER 1000BASE-T Ethernet",
640 WM_T_82541_2, WMP_F_1000T },
641
642 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI,
643 "Intel i82541GI 1000BASE-T Ethernet",
644 WM_T_82541_2, WMP_F_1000T },
645
646 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE,
647 "Intel i82541GI Mobile 1000BASE-T Ethernet",
648 WM_T_82541_2, WMP_F_1000T },
649
650 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI,
651 "Intel i82541PI 1000BASE-T Ethernet",
652 WM_T_82541_2, WMP_F_1000T },
653
654 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI,
655 "Intel i82547EI 1000BASE-T Ethernet",
656 WM_T_82547, WMP_F_1000T },
657
658 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE,
659 "Intel i82547EI Moblie 1000BASE-T Ethernet",
660 WM_T_82547, WMP_F_1000T },
661
662 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI,
663 "Intel i82547GI 1000BASE-T Ethernet",
664 WM_T_82547_2, WMP_F_1000T },
665
666 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER,
667 "Intel PRO/1000 PT (82571EB)",
668 WM_T_82571, WMP_F_1000T },
669
670 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER,
671 "Intel PRO/1000 PF (82571EB)",
672 WM_T_82571, WMP_F_1000X },
673 #if 0
674 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES,
675 "Intel PRO/1000 PB (82571EB)",
676 WM_T_82571, WMP_F_SERDES },
677 #endif
678 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER,
679 "Intel i82572EI 1000baseT Ethernet",
680 WM_T_82572, WMP_F_1000T },
681
682 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER,
683 "Intel i82572EI 1000baseX Ethernet",
684 WM_T_82572, WMP_F_1000X },
685 #if 0
686 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES,
687 "Intel i82572EI Gigabit Ethernet (SERDES)",
688 WM_T_82572, WMP_F_SERDES },
689 #endif
690
691 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI,
692 "Intel i82572EI 1000baseT Ethernet",
693 WM_T_82572, WMP_F_1000T },
694
695 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E,
696 "Intel i82573E",
697 WM_T_82573, WMP_F_1000T },
698
699 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT,
700 "Intel i82573E IAMT",
701 WM_T_82573, WMP_F_1000T },
702
703 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L,
704 "Intel i82573L Gigabit Ethernet",
705 WM_T_82573, WMP_F_1000T },
706
707 { 0, 0,
708 NULL,
709 0, 0 },
710 };
711
712 #ifdef WM_EVENT_COUNTERS
713 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")];
714 #endif /* WM_EVENT_COUNTERS */
715
716 #if 0 /* Not currently used */
717 static inline uint32_t
718 wm_io_read(struct wm_softc *sc, int reg)
719 {
720
721 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
722 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
723 }
724 #endif
725
726 static inline void
727 wm_io_write(struct wm_softc *sc, int reg, uint32_t val)
728 {
729
730 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
731 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val);
732 }
733
734 static inline void
735 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v)
736 {
737 wa->wa_low = htole32(v & 0xffffffffU);
738 if (sizeof(bus_addr_t) == 8)
739 wa->wa_high = htole32((uint64_t) v >> 32);
740 else
741 wa->wa_high = 0;
742 }
743
744 static const struct wm_product *
745 wm_lookup(const struct pci_attach_args *pa)
746 {
747 const struct wm_product *wmp;
748
749 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) {
750 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor &&
751 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product)
752 return (wmp);
753 }
754 return (NULL);
755 }
756
757 static int
758 wm_match(struct device *parent, struct cfdata *cf, void *aux)
759 {
760 struct pci_attach_args *pa = aux;
761
762 if (wm_lookup(pa) != NULL)
763 return (1);
764
765 return (0);
766 }
767
768 static void
769 wm_attach(struct device *parent, struct device *self, void *aux)
770 {
771 struct wm_softc *sc = (void *) self;
772 struct pci_attach_args *pa = aux;
773 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
774 pci_chipset_tag_t pc = pa->pa_pc;
775 pci_intr_handle_t ih;
776 size_t cdata_size;
777 const char *intrstr = NULL;
778 const char *eetype;
779 bus_space_tag_t memt;
780 bus_space_handle_t memh;
781 bus_dma_segment_t seg;
782 int memh_valid;
783 int i, rseg, error;
784 const struct wm_product *wmp;
785 prop_data_t ea;
786 prop_number_t pn;
787 uint8_t enaddr[ETHER_ADDR_LEN];
788 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
789 pcireg_t preg, memtype;
790 uint32_t reg;
791
792 callout_init(&sc->sc_tick_ch);
793
794 wmp = wm_lookup(pa);
795 if (wmp == NULL) {
796 printf("\n");
797 panic("wm_attach: impossible");
798 }
799
800 if (pci_dma64_available(pa))
801 sc->sc_dmat = pa->pa_dmat64;
802 else
803 sc->sc_dmat = pa->pa_dmat;
804
805 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG));
806 aprint_naive(": Ethernet controller\n");
807 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg);
808
809 sc->sc_type = wmp->wmp_type;
810 if (sc->sc_type < WM_T_82543) {
811 if (preg < 2) {
812 aprint_error("%s: i82542 must be at least rev. 2\n",
813 sc->sc_dev.dv_xname);
814 return;
815 }
816 if (preg < 3)
817 sc->sc_type = WM_T_82542_2_0;
818 }
819
820 /*
821 * Map the device. All devices support memory-mapped acccess,
822 * and it is really required for normal operation.
823 */
824 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA);
825 switch (memtype) {
826 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
827 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
828 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA,
829 memtype, 0, &memt, &memh, NULL, NULL) == 0);
830 break;
831 default:
832 memh_valid = 0;
833 }
834
835 if (memh_valid) {
836 sc->sc_st = memt;
837 sc->sc_sh = memh;
838 } else {
839 aprint_error("%s: unable to map device registers\n",
840 sc->sc_dev.dv_xname);
841 return;
842 }
843
844 /*
845 * In addition, i82544 and later support I/O mapped indirect
846 * register access. It is not desirable (nor supported in
847 * this driver) to use it for normal operation, though it is
848 * required to work around bugs in some chip versions.
849 */
850 if (sc->sc_type >= WM_T_82544) {
851 /* First we have to find the I/O BAR. */
852 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) {
853 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) ==
854 PCI_MAPREG_TYPE_IO)
855 break;
856 }
857 if (i == PCI_MAPREG_END)
858 aprint_error("%s: WARNING: unable to find I/O BAR\n",
859 sc->sc_dev.dv_xname);
860 else {
861 /*
862 * The i8254x doesn't apparently respond when the
863 * I/O BAR is 0, which looks somewhat like it's not
864 * been configured.
865 */
866 preg = pci_conf_read(pc, pa->pa_tag, i);
867 if (PCI_MAPREG_MEM_ADDR(preg) == 0) {
868 aprint_error("%s: WARNING: I/O BAR at zero.\n",
869 sc->sc_dev.dv_xname);
870 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO,
871 0, &sc->sc_iot, &sc->sc_ioh,
872 NULL, NULL) == 0) {
873 sc->sc_flags |= WM_F_IOH_VALID;
874 } else {
875 aprint_error("%s: WARNING: unable to map "
876 "I/O space\n", sc->sc_dev.dv_xname);
877 }
878 }
879
880 }
881
882 /* Enable bus mastering. Disable MWI on the i82542 2.0. */
883 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
884 preg |= PCI_COMMAND_MASTER_ENABLE;
885 if (sc->sc_type < WM_T_82542_2_1)
886 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
887 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
888
889 /* power up chip */
890 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc,
891 NULL)) && error != EOPNOTSUPP) {
892 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname,
893 error);
894 return;
895 }
896
897 /*
898 * Map and establish our interrupt.
899 */
900 if (pci_intr_map(pa, &ih)) {
901 aprint_error("%s: unable to map interrupt\n",
902 sc->sc_dev.dv_xname);
903 return;
904 }
905 intrstr = pci_intr_string(pc, ih);
906 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc);
907 if (sc->sc_ih == NULL) {
908 aprint_error("%s: unable to establish interrupt",
909 sc->sc_dev.dv_xname);
910 if (intrstr != NULL)
911 aprint_normal(" at %s", intrstr);
912 aprint_normal("\n");
913 return;
914 }
915 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
916
917 /*
918 * Determine a few things about the bus we're connected to.
919 */
920 if (sc->sc_type < WM_T_82543) {
921 /* We don't really know the bus characteristics here. */
922 sc->sc_bus_speed = 33;
923 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) {
924 /*
925 * CSA (Communication Streaming Architecture) is about as fast
926 * a 32-bit 66MHz PCI Bus.
927 */
928 sc->sc_flags |= WM_F_CSA;
929 sc->sc_bus_speed = 66;
930 aprint_verbose("%s: Communication Streaming Architecture\n",
931 sc->sc_dev.dv_xname);
932 if (sc->sc_type == WM_T_82547) {
933 callout_init(&sc->sc_txfifo_ch);
934 callout_setfunc(&sc->sc_txfifo_ch,
935 wm_82547_txfifo_stall, sc);
936 aprint_verbose("%s: using 82547 Tx FIFO stall "
937 "work-around\n", sc->sc_dev.dv_xname);
938 }
939 } else if (sc->sc_type >= WM_T_82571) {
940 sc->sc_flags |= WM_F_PCIE | WM_F_EEPROM_SEMAPHORE;
941 aprint_verbose("%s: PCI-Express bus\n", sc->sc_dev.dv_xname);
942 } else {
943 reg = CSR_READ(sc, WMREG_STATUS);
944 if (reg & STATUS_BUS64)
945 sc->sc_flags |= WM_F_BUS64;
946 if (sc->sc_type >= WM_T_82544 &&
947 (reg & STATUS_PCIX_MODE) != 0) {
948 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb;
949
950 sc->sc_flags |= WM_F_PCIX;
951 if (pci_get_capability(pa->pa_pc, pa->pa_tag,
952 PCI_CAP_PCIX,
953 &sc->sc_pcix_offset, NULL) == 0)
954 aprint_error("%s: unable to find PCIX "
955 "capability\n", sc->sc_dev.dv_xname);
956 else if (sc->sc_type != WM_T_82545_3 &&
957 sc->sc_type != WM_T_82546_3) {
958 /*
959 * Work around a problem caused by the BIOS
960 * setting the max memory read byte count
961 * incorrectly.
962 */
963 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag,
964 sc->sc_pcix_offset + PCI_PCIX_CMD);
965 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
966 sc->sc_pcix_offset + PCI_PCIX_STATUS);
967
968 bytecnt =
969 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >>
970 PCI_PCIX_CMD_BYTECNT_SHIFT;
971 maxb =
972 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >>
973 PCI_PCIX_STATUS_MAXB_SHIFT;
974 if (bytecnt > maxb) {
975 aprint_verbose("%s: resetting PCI-X "
976 "MMRBC: %d -> %d\n",
977 sc->sc_dev.dv_xname,
978 512 << bytecnt, 512 << maxb);
979 pcix_cmd = (pcix_cmd &
980 ~PCI_PCIX_CMD_BYTECNT_MASK) |
981 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT);
982 pci_conf_write(pa->pa_pc, pa->pa_tag,
983 sc->sc_pcix_offset + PCI_PCIX_CMD,
984 pcix_cmd);
985 }
986 }
987 }
988 /*
989 * The quad port adapter is special; it has a PCIX-PCIX
990 * bridge on the board, and can run the secondary bus at
991 * a higher speed.
992 */
993 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) {
994 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120
995 : 66;
996 } else if (sc->sc_flags & WM_F_PCIX) {
997 switch (reg & STATUS_PCIXSPD_MASK) {
998 case STATUS_PCIXSPD_50_66:
999 sc->sc_bus_speed = 66;
1000 break;
1001 case STATUS_PCIXSPD_66_100:
1002 sc->sc_bus_speed = 100;
1003 break;
1004 case STATUS_PCIXSPD_100_133:
1005 sc->sc_bus_speed = 133;
1006 break;
1007 default:
1008 aprint_error(
1009 "%s: unknown PCIXSPD %d; assuming 66MHz\n",
1010 sc->sc_dev.dv_xname,
1011 reg & STATUS_PCIXSPD_MASK);
1012 sc->sc_bus_speed = 66;
1013 }
1014 } else
1015 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;
1016 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname,
1017 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed,
1018 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI");
1019 }
1020
1021 /*
1022 * Allocate the control data structures, and create and load the
1023 * DMA map for it.
1024 *
1025 * NOTE: All Tx descriptors must be in the same 4G segment of
1026 * memory. So must Rx descriptors. We simplify by allocating
1027 * both sets within the same 4G segment.
1028 */
1029 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ?
1030 WM_NTXDESC_82542 : WM_NTXDESC_82544;
1031 cdata_size = sc->sc_type < WM_T_82544 ?
1032 sizeof(struct wm_control_data_82542) :
1033 sizeof(struct wm_control_data_82544);
1034 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE,
1035 (bus_size_t) 0x100000000ULL,
1036 &seg, 1, &rseg, 0)) != 0) {
1037 aprint_error(
1038 "%s: unable to allocate control data, error = %d\n",
1039 sc->sc_dev.dv_xname, error);
1040 goto fail_0;
1041 }
1042
1043 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size,
1044 (caddr_t *)&sc->sc_control_data, 0)) != 0) {
1045 aprint_error("%s: unable to map control data, error = %d\n",
1046 sc->sc_dev.dv_xname, error);
1047 goto fail_1;
1048 }
1049
1050 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size,
1051 0, 0, &sc->sc_cddmamap)) != 0) {
1052 aprint_error("%s: unable to create control data DMA map, "
1053 "error = %d\n", sc->sc_dev.dv_xname, error);
1054 goto fail_2;
1055 }
1056
1057 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
1058 sc->sc_control_data, cdata_size, NULL,
1059 0)) != 0) {
1060 aprint_error(
1061 "%s: unable to load control data DMA map, error = %d\n",
1062 sc->sc_dev.dv_xname, error);
1063 goto fail_3;
1064 }
1065
1066
1067 /*
1068 * Create the transmit buffer DMA maps.
1069 */
1070 WM_TXQUEUELEN(sc) =
1071 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
1072 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
1073 for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
1074 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA,
1075 WM_NTXSEGS, WTX_MAX_LEN, 0, 0,
1076 &sc->sc_txsoft[i].txs_dmamap)) != 0) {
1077 aprint_error("%s: unable to create Tx DMA map %d, "
1078 "error = %d\n", sc->sc_dev.dv_xname, i, error);
1079 goto fail_4;
1080 }
1081 }
1082
1083 /*
1084 * Create the receive buffer DMA maps.
1085 */
1086 for (i = 0; i < WM_NRXDESC; i++) {
1087 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
1088 MCLBYTES, 0, 0,
1089 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
1090 aprint_error("%s: unable to create Rx DMA map %d, "
1091 "error = %d\n", sc->sc_dev.dv_xname, i, error);
1092 goto fail_5;
1093 }
1094 sc->sc_rxsoft[i].rxs_mbuf = NULL;
1095 }
1096
1097 /*
1098 * Reset the chip to a known state.
1099 */
1100 wm_reset(sc);
1101
1102 /*
1103 * Get some information about the EEPROM.
1104 */
1105 if (sc->sc_type == WM_T_82573)
1106 sc->sc_flags |= WM_F_EEPROM_EERDEEWR;
1107 else if (sc->sc_type > WM_T_82544)
1108 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE;
1109
1110 if (sc->sc_type <= WM_T_82544)
1111 sc->sc_ee_addrbits = 6;
1112 else if (sc->sc_type <= WM_T_82546_3) {
1113 reg = CSR_READ(sc, WMREG_EECD);
1114 if (reg & EECD_EE_SIZE)
1115 sc->sc_ee_addrbits = 8;
1116 else
1117 sc->sc_ee_addrbits = 6;
1118 } else if (sc->sc_type <= WM_T_82547_2) {
1119 reg = CSR_READ(sc, WMREG_EECD);
1120 if (reg & EECD_EE_TYPE) {
1121 sc->sc_flags |= WM_F_EEPROM_SPI;
1122 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
1123 } else
1124 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6;
1125 } else if ((sc->sc_type == WM_T_82573) &&
1126 (wm_is_onboard_nvm_eeprom(sc) == 0)) {
1127 sc->sc_flags |= WM_F_EEPROM_FLASH;
1128 } else {
1129 /* Assume everything else is SPI. */
1130 reg = CSR_READ(sc, WMREG_EECD);
1131 sc->sc_flags |= WM_F_EEPROM_SPI;
1132 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;
1133 }
1134
1135 /*
1136 * Defer printing the EEPROM type until after verifying the checksum
1137 * This allows the EEPROM type to be printed correctly in the case
1138 * that no EEPROM is attached.
1139 */
1140
1141
1142 /*
1143 * Validate the EEPROM checksum. If the checksum fails, flag this for
1144 * later, so we can fail future reads from the EEPROM.
1145 */
1146 if (wm_validate_eeprom_checksum(sc))
1147 sc->sc_flags |= WM_F_EEPROM_INVALID;
1148
1149 if (sc->sc_flags & WM_F_EEPROM_INVALID)
1150 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname);
1151 else if (sc->sc_flags & WM_F_EEPROM_FLASH) {
1152 aprint_verbose("%s: FLASH\n", sc->sc_dev.dv_xname);
1153 } else {
1154 if (sc->sc_flags & WM_F_EEPROM_SPI)
1155 eetype = "SPI";
1156 else
1157 eetype = "MicroWire";
1158 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n",
1159 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits,
1160 sc->sc_ee_addrbits, eetype);
1161 }
1162
1163 /*
1164 * Read the Ethernet address from the EEPROM, if not first found
1165 * in device properties.
1166 */
1167 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr");
1168 if (ea != NULL) {
1169 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
1170 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
1171 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
1172 } else {
1173 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR,
1174 sizeof(myea) / sizeof(myea[0]), myea)) {
1175 aprint_error("%s: unable to read Ethernet address\n",
1176 sc->sc_dev.dv_xname);
1177 return;
1178 }
1179 enaddr[0] = myea[0] & 0xff;
1180 enaddr[1] = myea[0] >> 8;
1181 enaddr[2] = myea[1] & 0xff;
1182 enaddr[3] = myea[1] >> 8;
1183 enaddr[4] = myea[2] & 0xff;
1184 enaddr[5] = myea[2] >> 8;
1185 }
1186
1187 /*
1188 * Toggle the LSB of the MAC address on the second port
1189 * of the dual port controller.
1190 */
1191 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3
1192 || sc->sc_type == WM_T_82571) {
1193 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1)
1194 enaddr[5] ^= 1;
1195 }
1196
1197 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname,
1198 ether_sprintf(enaddr));
1199
1200 /*
1201 * Read the config info from the EEPROM, and set up various
1202 * bits in the control registers based on their contents.
1203 */
1204 pn = prop_dictionary_get(device_properties(&sc->sc_dev),
1205 "i82543-cfg1");
1206 if (pn != NULL) {
1207 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
1208 cfg1 = (uint16_t) prop_number_integer_value(pn);
1209 } else {
1210 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) {
1211 aprint_error("%s: unable to read CFG1\n",
1212 sc->sc_dev.dv_xname);
1213 return;
1214 }
1215 }
1216
1217 pn = prop_dictionary_get(device_properties(&sc->sc_dev),
1218 "i82543-cfg2");
1219 if (pn != NULL) {
1220 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
1221 cfg2 = (uint16_t) prop_number_integer_value(pn);
1222 } else {
1223 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) {
1224 aprint_error("%s: unable to read CFG2\n",
1225 sc->sc_dev.dv_xname);
1226 return;
1227 }
1228 }
1229
1230 if (sc->sc_type >= WM_T_82544) {
1231 pn = prop_dictionary_get(device_properties(&sc->sc_dev),
1232 "i82543-swdpin");
1233 if (pn != NULL) {
1234 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
1235 swdpin = (uint16_t) prop_number_integer_value(pn);
1236 } else {
1237 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) {
1238 aprint_error("%s: unable to read SWDPIN\n",
1239 sc->sc_dev.dv_xname);
1240 return;
1241 }
1242 }
1243 }
1244
1245 if (cfg1 & EEPROM_CFG1_ILOS)
1246 sc->sc_ctrl |= CTRL_ILOS;
1247 if (sc->sc_type >= WM_T_82544) {
1248 sc->sc_ctrl |=
1249 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
1250 CTRL_SWDPIO_SHIFT;
1251 sc->sc_ctrl |=
1252 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) <<
1253 CTRL_SWDPINS_SHIFT;
1254 } else {
1255 sc->sc_ctrl |=
1256 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) <<
1257 CTRL_SWDPIO_SHIFT;
1258 }
1259
1260 #if 0
1261 if (sc->sc_type >= WM_T_82544) {
1262 if (cfg1 & EEPROM_CFG1_IPS0)
1263 sc->sc_ctrl_ext |= CTRL_EXT_IPS;
1264 if (cfg1 & EEPROM_CFG1_IPS1)
1265 sc->sc_ctrl_ext |= CTRL_EXT_IPS1;
1266 sc->sc_ctrl_ext |=
1267 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) <<
1268 CTRL_EXT_SWDPIO_SHIFT;
1269 sc->sc_ctrl_ext |=
1270 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) <<
1271 CTRL_EXT_SWDPINS_SHIFT;
1272 } else {
1273 sc->sc_ctrl_ext |=
1274 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) <<
1275 CTRL_EXT_SWDPIO_SHIFT;
1276 }
1277 #endif
1278
1279 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
1280 #if 0
1281 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
1282 #endif
1283
1284 /*
1285 * Set up some register offsets that are different between
1286 * the i82542 and the i82543 and later chips.
1287 */
1288 if (sc->sc_type < WM_T_82543) {
1289 sc->sc_rdt_reg = WMREG_OLD_RDT0;
1290 sc->sc_tdt_reg = WMREG_OLD_TDT;
1291 } else {
1292 sc->sc_rdt_reg = WMREG_RDT;
1293 sc->sc_tdt_reg = WMREG_TDT;
1294 }
1295
1296 /*
1297 * Determine if we're TBI or GMII mode, and initialize the
1298 * media structures accordingly.
1299 */
1300 if (sc->sc_type < WM_T_82543 ||
1301 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
1302 if (wmp->wmp_flags & WMP_F_1000T)
1303 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T "
1304 "product!\n", sc->sc_dev.dv_xname);
1305 wm_tbi_mediainit(sc);
1306 } else {
1307 if (wmp->wmp_flags & WMP_F_1000X)
1308 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X "
1309 "product!\n", sc->sc_dev.dv_xname);
1310 wm_gmii_mediainit(sc);
1311 }
1312
1313 ifp = &sc->sc_ethercom.ec_if;
1314 strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
1315 ifp->if_softc = sc;
1316 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1317 ifp->if_ioctl = wm_ioctl;
1318 ifp->if_start = wm_start;
1319 ifp->if_watchdog = wm_watchdog;
1320 ifp->if_init = wm_init;
1321 ifp->if_stop = wm_stop;
1322 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
1323 IFQ_SET_READY(&ifp->if_snd);
1324
1325 if (sc->sc_type != WM_T_82573)
1326 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
1327
1328 /*
1329 * If we're a i82543 or greater, we can support VLANs.
1330 */
1331 if (sc->sc_type >= WM_T_82543)
1332 sc->sc_ethercom.ec_capabilities |=
1333 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */;
1334
1335 /*
1336 * We can perform TCPv4 and UDPv4 checkums in-bound. Only
1337 * on i82543 and later.
1338 */
1339 if (sc->sc_type >= WM_T_82543)
1340 ifp->if_capabilities |=
1341 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1342 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1343 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1344 IFCAP_CSUM_TCPv6_Tx |
1345 IFCAP_CSUM_UDPv6_Tx;
1346
1347 /*
1348 * If we're a i82544 or greater (except i82547), we can do
1349 * TCP segmentation offload.
1350 */
1351 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547)
1352 ifp->if_capabilities |= IFCAP_TSOv4;
1353
1354 /*
1355 * Attach the interface.
1356 */
1357 if_attach(ifp);
1358 ether_ifattach(ifp, enaddr);
1359 #if NRND > 0
1360 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
1361 RND_TYPE_NET, 0);
1362 #endif
1363
1364 #ifdef WM_EVENT_COUNTERS
1365 /* Attach event counters. */
1366 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
1367 NULL, sc->sc_dev.dv_xname, "txsstall");
1368 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
1369 NULL, sc->sc_dev.dv_xname, "txdstall");
1370 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC,
1371 NULL, sc->sc_dev.dv_xname, "txfifo_stall");
1372 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR,
1373 NULL, sc->sc_dev.dv_xname, "txdw");
1374 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR,
1375 NULL, sc->sc_dev.dv_xname, "txqe");
1376 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
1377 NULL, sc->sc_dev.dv_xname, "rxintr");
1378 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR,
1379 NULL, sc->sc_dev.dv_xname, "linkintr");
1380
1381 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
1382 NULL, sc->sc_dev.dv_xname, "rxipsum");
1383 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC,
1384 NULL, sc->sc_dev.dv_xname, "rxtusum");
1385 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
1386 NULL, sc->sc_dev.dv_xname, "txipsum");
1387 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC,
1388 NULL, sc->sc_dev.dv_xname, "txtusum");
1389 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC,
1390 NULL, sc->sc_dev.dv_xname, "txtusum6");
1391
1392 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC,
1393 NULL, sc->sc_dev.dv_xname, "txtso");
1394 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC,
1395 NULL, sc->sc_dev.dv_xname, "txtsopain");
1396
1397 for (i = 0; i < WM_NTXSEGS; i++) {
1398 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i);
1399 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC,
1400 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]);
1401 }
1402
1403 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC,
1404 NULL, sc->sc_dev.dv_xname, "txdrop");
1405
1406 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC,
1407 NULL, sc->sc_dev.dv_xname, "tu");
1408
1409 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC,
1410 NULL, sc->sc_dev.dv_xname, "tx_xoff");
1411 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC,
1412 NULL, sc->sc_dev.dv_xname, "tx_xon");
1413 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC,
1414 NULL, sc->sc_dev.dv_xname, "rx_xoff");
1415 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC,
1416 NULL, sc->sc_dev.dv_xname, "rx_xon");
1417 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC,
1418 NULL, sc->sc_dev.dv_xname, "rx_macctl");
1419 #endif /* WM_EVENT_COUNTERS */
1420
1421 /*
1422 * Make sure the interface is shutdown during reboot.
1423 */
1424 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc);
1425 if (sc->sc_sdhook == NULL)
1426 aprint_error("%s: WARNING: unable to establish shutdown hook\n",
1427 sc->sc_dev.dv_xname);
1428 return;
1429
1430 /*
1431 * Free any resources we've allocated during the failed attach
1432 * attempt. Do this in reverse order and fall through.
1433 */
1434 fail_5:
1435 for (i = 0; i < WM_NRXDESC; i++) {
1436 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
1437 bus_dmamap_destroy(sc->sc_dmat,
1438 sc->sc_rxsoft[i].rxs_dmamap);
1439 }
1440 fail_4:
1441 for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
1442 if (sc->sc_txsoft[i].txs_dmamap != NULL)
1443 bus_dmamap_destroy(sc->sc_dmat,
1444 sc->sc_txsoft[i].txs_dmamap);
1445 }
1446 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
1447 fail_3:
1448 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
1449 fail_2:
1450 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
1451 cdata_size);
1452 fail_1:
1453 bus_dmamem_free(sc->sc_dmat, &seg, rseg);
1454 fail_0:
1455 return;
1456 }
1457
1458 /*
1459 * wm_shutdown:
1460 *
1461 * Make sure the interface is stopped at reboot time.
1462 */
1463 static void
1464 wm_shutdown(void *arg)
1465 {
1466 struct wm_softc *sc = arg;
1467
1468 wm_stop(&sc->sc_ethercom.ec_if, 1);
1469 }
1470
1471 /*
1472 * wm_tx_offload:
1473 *
1474 * Set up TCP/IP checksumming parameters for the
1475 * specified packet.
1476 */
1477 static int
1478 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp,
1479 uint8_t *fieldsp)
1480 {
1481 struct mbuf *m0 = txs->txs_mbuf;
1482 struct livengood_tcpip_ctxdesc *t;
1483 uint32_t ipcs, tucs, cmd, cmdlen, seg;
1484 struct ether_header *eh;
1485 int offset, iphl;
1486 uint8_t fields;
1487
1488 /*
1489 * XXX It would be nice if the mbuf pkthdr had offset
1490 * fields for the protocol headers.
1491 */
1492
1493 eh = mtod(m0, struct ether_header *);
1494 switch (htons(eh->ether_type)) {
1495 case ETHERTYPE_IP:
1496 case ETHERTYPE_IPV6:
1497 offset = ETHER_HDR_LEN;
1498 break;
1499
1500 case ETHERTYPE_VLAN:
1501 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1502 break;
1503
1504 default:
1505 /*
1506 * Don't support this protocol or encapsulation.
1507 */
1508 *fieldsp = 0;
1509 *cmdp = 0;
1510 return (0);
1511 }
1512
1513 if ((m0->m_pkthdr.csum_flags &
1514 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) {
1515 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
1516 } else {
1517 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
1518 }
1519
1520 cmd = WTX_CMD_DEXT | WTX_DTYP_D;
1521 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE;
1522 seg = 0;
1523 fields = 0;
1524
1525 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1526 int hlen = offset + iphl;
1527 WM_EVCNT_INCR(&sc->sc_ev_txtso);
1528 if (__predict_false(m0->m_len <
1529 (hlen + sizeof(struct tcphdr)))) {
1530 /*
1531 * TCP/IP headers are not in the first mbuf; we need
1532 * to do this the slow and painful way. Let's just
1533 * hope this doesn't happen very often.
1534 */
1535 struct ip ip;
1536 struct tcphdr th;
1537
1538 WM_EVCNT_INCR(&sc->sc_ev_txtsopain);
1539
1540 m_copydata(m0, offset, sizeof(ip), &ip);
1541 m_copydata(m0, hlen, sizeof(th), &th);
1542
1543 ip.ip_len = 0;
1544
1545 m_copyback(m0, hlen + offsetof(struct ip, ip_len),
1546 sizeof(ip.ip_len), &ip.ip_len);
1547
1548 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
1549 ip.ip_dst.s_addr, htons(IPPROTO_TCP));
1550
1551 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
1552 sizeof(th.th_sum), &th.th_sum);
1553
1554 hlen += th.th_off << 2;
1555 } else {
1556 /*
1557 * TCP/IP headers are in the first mbuf; we can do
1558 * this the easy way.
1559 */
1560 struct ip *ip =
1561 (struct ip *) (mtod(m0, caddr_t) + offset);
1562 struct tcphdr *th =
1563 (struct tcphdr *) (mtod(m0, caddr_t) + hlen);
1564
1565 ip->ip_len = 0;
1566 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
1567 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1568
1569 hlen += th->th_off << 2;
1570 }
1571
1572 cmd |= WTX_TCPIP_CMD_TSE;
1573 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP |
1574 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen);
1575 seg = WTX_TCPIP_SEG_HDRLEN(hlen) |
1576 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz);
1577 }
1578
1579 /*
1580 * NOTE: Even if we're not using the IP or TCP/UDP checksum
1581 * offload feature, if we load the context descriptor, we
1582 * MUST provide valid values for IPCSS and TUCSS fields.
1583 */
1584
1585 ipcs = WTX_TCPIP_IPCSS(offset) |
1586 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) |
1587 WTX_TCPIP_IPCSE(offset + iphl - 1);
1588 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) {
1589 WM_EVCNT_INCR(&sc->sc_ev_txipsum);
1590 fields |= WTX_IXSM;
1591 }
1592
1593 offset += iphl;
1594
1595 if (m0->m_pkthdr.csum_flags &
1596 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) {
1597 WM_EVCNT_INCR(&sc->sc_ev_txtusum);
1598 fields |= WTX_TXSM;
1599 tucs = WTX_TCPIP_TUCSS(offset) |
1600 WTX_TCPIP_TUCSO(offset +
1601 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) |
1602 WTX_TCPIP_TUCSE(0) /* rest of packet */;
1603 } else if ((m0->m_pkthdr.csum_flags &
1604 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) {
1605 WM_EVCNT_INCR(&sc->sc_ev_txtusum6);
1606 fields |= WTX_TXSM;
1607 tucs = WTX_TCPIP_TUCSS(offset) |
1608 WTX_TCPIP_TUCSO(offset +
1609 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) |
1610 WTX_TCPIP_TUCSE(0) /* rest of packet */;
1611 } else {
1612 /* Just initialize it to a valid TCP context. */
1613 tucs = WTX_TCPIP_TUCSS(offset) |
1614 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) |
1615 WTX_TCPIP_TUCSE(0) /* rest of packet */;
1616 }
1617
1618 /* Fill in the context descriptor. */
1619 t = (struct livengood_tcpip_ctxdesc *)
1620 &sc->sc_txdescs[sc->sc_txnext];
1621 t->tcpip_ipcs = htole32(ipcs);
1622 t->tcpip_tucs = htole32(tucs);
1623 t->tcpip_cmdlen = htole32(cmdlen);
1624 t->tcpip_seg = htole32(seg);
1625 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE);
1626
1627 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext);
1628 txs->txs_ndesc++;
1629
1630 *cmdp = cmd;
1631 *fieldsp = fields;
1632
1633 return (0);
1634 }
1635
1636 static void
1637 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0)
1638 {
1639 struct mbuf *m;
1640 int i;
1641
1642 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname);
1643 for (m = m0, i = 0; m != NULL; m = m->m_next, i++)
1644 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, "
1645 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname,
1646 m->m_data, m->m_len, m->m_flags);
1647 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname,
1648 i, i == 1 ? "" : "s");
1649 }
1650
1651 /*
1652 * wm_82547_txfifo_stall:
1653 *
1654 * Callout used to wait for the 82547 Tx FIFO to drain,
1655 * reset the FIFO pointers, and restart packet transmission.
1656 */
1657 static void
1658 wm_82547_txfifo_stall(void *arg)
1659 {
1660 struct wm_softc *sc = arg;
1661 int s;
1662
1663 s = splnet();
1664
1665 if (sc->sc_txfifo_stall) {
1666 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) &&
1667 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
1668 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
1669 /*
1670 * Packets have drained. Stop transmitter, reset
1671 * FIFO pointers, restart transmitter, and kick
1672 * the packet queue.
1673 */
1674 uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
1675 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN);
1676 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr);
1677 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr);
1678 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr);
1679 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr);
1680 CSR_WRITE(sc, WMREG_TCTL, tctl);
1681 CSR_WRITE_FLUSH(sc);
1682
1683 sc->sc_txfifo_head = 0;
1684 sc->sc_txfifo_stall = 0;
1685 wm_start(&sc->sc_ethercom.ec_if);
1686 } else {
1687 /*
1688 * Still waiting for packets to drain; try again in
1689 * another tick.
1690 */
1691 callout_schedule(&sc->sc_txfifo_ch, 1);
1692 }
1693 }
1694
1695 splx(s);
1696 }
1697
1698 /*
1699 * wm_82547_txfifo_bugchk:
1700 *
1701 * Check for bug condition in the 82547 Tx FIFO. We need to
1702 * prevent enqueueing a packet that would wrap around the end
1703 * if the Tx FIFO ring buffer, otherwise the chip will croak.
1704 *
1705 * We do this by checking the amount of space before the end
1706 * of the Tx FIFO buffer. If the packet will not fit, we "stall"
1707 * the Tx FIFO, wait for all remaining packets to drain, reset
1708 * the internal FIFO pointers to the beginning, and restart
1709 * transmission on the interface.
1710 */
1711 #define WM_FIFO_HDR 0x10
1712 #define WM_82547_PAD_LEN 0x3e0
1713 static int
1714 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0)
1715 {
1716 int space = sc->sc_txfifo_size - sc->sc_txfifo_head;
1717 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR);
1718
1719 /* Just return if already stalled. */
1720 if (sc->sc_txfifo_stall)
1721 return (1);
1722
1723 if (sc->sc_mii.mii_media_active & IFM_FDX) {
1724 /* Stall only occurs in half-duplex mode. */
1725 goto send_packet;
1726 }
1727
1728 if (len >= WM_82547_PAD_LEN + space) {
1729 sc->sc_txfifo_stall = 1;
1730 callout_schedule(&sc->sc_txfifo_ch, 1);
1731 return (1);
1732 }
1733
1734 send_packet:
1735 sc->sc_txfifo_head += len;
1736 if (sc->sc_txfifo_head >= sc->sc_txfifo_size)
1737 sc->sc_txfifo_head -= sc->sc_txfifo_size;
1738
1739 return (0);
1740 }
1741
1742 /*
1743 * wm_start: [ifnet interface function]
1744 *
1745 * Start packet transmission on the interface.
1746 */
1747 static void
1748 wm_start(struct ifnet *ifp)
1749 {
1750 struct wm_softc *sc = ifp->if_softc;
1751 struct mbuf *m0;
1752 #if 0 /* XXXJRT */
1753 struct m_tag *mtag;
1754 #endif
1755 struct wm_txsoft *txs;
1756 bus_dmamap_t dmamap;
1757 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso;
1758 bus_addr_t curaddr;
1759 bus_size_t seglen, curlen;
1760 uint32_t cksumcmd;
1761 uint8_t cksumfields;
1762
1763 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
1764 return;
1765
1766 /*
1767 * Remember the previous number of free descriptors.
1768 */
1769 ofree = sc->sc_txfree;
1770
1771 /*
1772 * Loop through the send queue, setting up transmit descriptors
1773 * until we drain the queue, or use up all available transmit
1774 * descriptors.
1775 */
1776 for (;;) {
1777 /* Grab a packet off the queue. */
1778 IFQ_POLL(&ifp->if_snd, m0);
1779 if (m0 == NULL)
1780 break;
1781
1782 DPRINTF(WM_DEBUG_TX,
1783 ("%s: TX: have packet to transmit: %p\n",
1784 sc->sc_dev.dv_xname, m0));
1785
1786 /* Get a work queue entry. */
1787 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) {
1788 wm_txintr(sc);
1789 if (sc->sc_txsfree == 0) {
1790 DPRINTF(WM_DEBUG_TX,
1791 ("%s: TX: no free job descriptors\n",
1792 sc->sc_dev.dv_xname));
1793 WM_EVCNT_INCR(&sc->sc_ev_txsstall);
1794 break;
1795 }
1796 }
1797
1798 txs = &sc->sc_txsoft[sc->sc_txsnext];
1799 dmamap = txs->txs_dmamap;
1800
1801 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
1802
1803 /*
1804 * So says the Linux driver:
1805 * The controller does a simple calculation to make sure
1806 * there is enough room in the FIFO before initiating the
1807 * DMA for each buffer. The calc is:
1808 * 4 = ceil(buffer len / MSS)
1809 * To make sure we don't overrun the FIFO, adjust the max
1810 * buffer len if the MSS drops.
1811 */
1812 dmamap->dm_maxsegsz =
1813 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN)
1814 ? m0->m_pkthdr.segsz << 2
1815 : WTX_MAX_LEN;
1816
1817 /*
1818 * Load the DMA map. If this fails, the packet either
1819 * didn't fit in the allotted number of segments, or we
1820 * were short on resources. For the too-many-segments
1821 * case, we simply report an error and drop the packet,
1822 * since we can't sanely copy a jumbo packet to a single
1823 * buffer.
1824 */
1825 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
1826 BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1827 if (error) {
1828 if (error == EFBIG) {
1829 WM_EVCNT_INCR(&sc->sc_ev_txdrop);
1830 log(LOG_ERR, "%s: Tx packet consumes too many "
1831 "DMA segments, dropping...\n",
1832 sc->sc_dev.dv_xname);
1833 IFQ_DEQUEUE(&ifp->if_snd, m0);
1834 wm_dump_mbuf_chain(sc, m0);
1835 m_freem(m0);
1836 continue;
1837 }
1838 /*
1839 * Short on resources, just stop for now.
1840 */
1841 DPRINTF(WM_DEBUG_TX,
1842 ("%s: TX: dmamap load failed: %d\n",
1843 sc->sc_dev.dv_xname, error));
1844 break;
1845 }
1846
1847 segs_needed = dmamap->dm_nsegs;
1848 if (use_tso) {
1849 /* For sentinel descriptor; see below. */
1850 segs_needed++;
1851 }
1852
1853 /*
1854 * Ensure we have enough descriptors free to describe
1855 * the packet. Note, we always reserve one descriptor
1856 * at the end of the ring due to the semantics of the
1857 * TDT register, plus one more in the event we need
1858 * to load offload context.
1859 */
1860 if (segs_needed > sc->sc_txfree - 2) {
1861 /*
1862 * Not enough free descriptors to transmit this
1863 * packet. We haven't committed anything yet,
1864 * so just unload the DMA map, put the packet
1865 * pack on the queue, and punt. Notify the upper
1866 * layer that there are no more slots left.
1867 */
1868 DPRINTF(WM_DEBUG_TX,
1869 ("%s: TX: need %d (%d) descriptors, have %d\n",
1870 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed,
1871 sc->sc_txfree - 1));
1872 ifp->if_flags |= IFF_OACTIVE;
1873 bus_dmamap_unload(sc->sc_dmat, dmamap);
1874 WM_EVCNT_INCR(&sc->sc_ev_txdstall);
1875 break;
1876 }
1877
1878 /*
1879 * Check for 82547 Tx FIFO bug. We need to do this
1880 * once we know we can transmit the packet, since we
1881 * do some internal FIFO space accounting here.
1882 */
1883 if (sc->sc_type == WM_T_82547 &&
1884 wm_82547_txfifo_bugchk(sc, m0)) {
1885 DPRINTF(WM_DEBUG_TX,
1886 ("%s: TX: 82547 Tx FIFO bug detected\n",
1887 sc->sc_dev.dv_xname));
1888 ifp->if_flags |= IFF_OACTIVE;
1889 bus_dmamap_unload(sc->sc_dmat, dmamap);
1890 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall);
1891 break;
1892 }
1893
1894 IFQ_DEQUEUE(&ifp->if_snd, m0);
1895
1896 /*
1897 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
1898 */
1899
1900 DPRINTF(WM_DEBUG_TX,
1901 ("%s: TX: packet has %d (%d) DMA segments\n",
1902 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed));
1903
1904 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]);
1905
1906 /*
1907 * Store a pointer to the packet so that we can free it
1908 * later.
1909 *
1910 * Initially, we consider the number of descriptors the
1911 * packet uses the number of DMA segments. This may be
1912 * incremented by 1 if we do checksum offload (a descriptor
1913 * is used to set the checksum context).
1914 */
1915 txs->txs_mbuf = m0;
1916 txs->txs_firstdesc = sc->sc_txnext;
1917 txs->txs_ndesc = segs_needed;
1918
1919 /* Set up offload parameters for this packet. */
1920 if (m0->m_pkthdr.csum_flags &
1921 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
1922 M_CSUM_TCPv6|M_CSUM_UDPv6)) {
1923 if (wm_tx_offload(sc, txs, &cksumcmd,
1924 &cksumfields) != 0) {
1925 /* Error message already displayed. */
1926 bus_dmamap_unload(sc->sc_dmat, dmamap);
1927 continue;
1928 }
1929 } else {
1930 cksumcmd = 0;
1931 cksumfields = 0;
1932 }
1933
1934 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS;
1935
1936 /* Sync the DMA map. */
1937 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
1938 BUS_DMASYNC_PREWRITE);
1939
1940 /*
1941 * Initialize the transmit descriptor.
1942 */
1943 for (nexttx = sc->sc_txnext, seg = 0;
1944 seg < dmamap->dm_nsegs; seg++) {
1945 for (seglen = dmamap->dm_segs[seg].ds_len,
1946 curaddr = dmamap->dm_segs[seg].ds_addr;
1947 seglen != 0;
1948 curaddr += curlen, seglen -= curlen,
1949 nexttx = WM_NEXTTX(sc, nexttx)) {
1950 curlen = seglen;
1951
1952 /*
1953 * So says the Linux driver:
1954 * Work around for premature descriptor
1955 * write-backs in TSO mode. Append a
1956 * 4-byte sentinel descriptor.
1957 */
1958 if (use_tso &&
1959 seg == dmamap->dm_nsegs - 1 &&
1960 curlen > 8)
1961 curlen -= 4;
1962
1963 wm_set_dma_addr(
1964 &sc->sc_txdescs[nexttx].wtx_addr,
1965 curaddr);
1966 sc->sc_txdescs[nexttx].wtx_cmdlen =
1967 htole32(cksumcmd | curlen);
1968 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status =
1969 0;
1970 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options =
1971 cksumfields;
1972 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0;
1973 lasttx = nexttx;
1974
1975 DPRINTF(WM_DEBUG_TX,
1976 ("%s: TX: desc %d: low 0x%08lx, "
1977 "len 0x%04x\n",
1978 sc->sc_dev.dv_xname, nexttx,
1979 curaddr & 0xffffffffUL, (unsigned)curlen));
1980 }
1981 }
1982
1983 KASSERT(lasttx != -1);
1984
1985 /*
1986 * Set up the command byte on the last descriptor of
1987 * the packet. If we're in the interrupt delay window,
1988 * delay the interrupt.
1989 */
1990 sc->sc_txdescs[lasttx].wtx_cmdlen |=
1991 htole32(WTX_CMD_EOP | WTX_CMD_RS);
1992
1993 #if 0 /* XXXJRT */
1994 /*
1995 * If VLANs are enabled and the packet has a VLAN tag, set
1996 * up the descriptor to encapsulate the packet for us.
1997 *
1998 * This is only valid on the last descriptor of the packet.
1999 */
2000 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
2001 sc->sc_txdescs[lasttx].wtx_cmdlen |=
2002 htole32(WTX_CMD_VLE);
2003 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan
2004 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
2005 }
2006 #endif /* XXXJRT */
2007
2008 txs->txs_lastdesc = lasttx;
2009
2010 DPRINTF(WM_DEBUG_TX,
2011 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname,
2012 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen)));
2013
2014 /* Sync the descriptors we're using. */
2015 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc,
2016 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2017
2018 /* Give the packet to the chip. */
2019 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx);
2020
2021 DPRINTF(WM_DEBUG_TX,
2022 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx));
2023
2024 DPRINTF(WM_DEBUG_TX,
2025 ("%s: TX: finished transmitting packet, job %d\n",
2026 sc->sc_dev.dv_xname, sc->sc_txsnext));
2027
2028 /* Advance the tx pointer. */
2029 sc->sc_txfree -= txs->txs_ndesc;
2030 sc->sc_txnext = nexttx;
2031
2032 sc->sc_txsfree--;
2033 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext);
2034
2035 #if NBPFILTER > 0
2036 /* Pass the packet to any BPF listeners. */
2037 if (ifp->if_bpf)
2038 bpf_mtap(ifp->if_bpf, m0);
2039 #endif /* NBPFILTER > 0 */
2040 }
2041
2042 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) {
2043 /* No more slots; notify upper layer. */
2044 ifp->if_flags |= IFF_OACTIVE;
2045 }
2046
2047 if (sc->sc_txfree != ofree) {
2048 /* Set a watchdog timer in case the chip flakes out. */
2049 ifp->if_timer = 5;
2050 }
2051 }
2052
2053 /*
2054 * wm_watchdog: [ifnet interface function]
2055 *
2056 * Watchdog timer handler.
2057 */
2058 static void
2059 wm_watchdog(struct ifnet *ifp)
2060 {
2061 struct wm_softc *sc = ifp->if_softc;
2062
2063 /*
2064 * Since we're using delayed interrupts, sweep up
2065 * before we report an error.
2066 */
2067 wm_txintr(sc);
2068
2069 if (sc->sc_txfree != WM_NTXDESC(sc)) {
2070 log(LOG_ERR,
2071 "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
2072 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree,
2073 sc->sc_txnext);
2074 ifp->if_oerrors++;
2075
2076 /* Reset the interface. */
2077 (void) wm_init(ifp);
2078 }
2079
2080 /* Try to get more packets going. */
2081 wm_start(ifp);
2082 }
2083
2084 /*
2085 * wm_ioctl: [ifnet interface function]
2086 *
2087 * Handle control requests from the operator.
2088 */
2089 static int
2090 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2091 {
2092 struct wm_softc *sc = ifp->if_softc;
2093 struct ifreq *ifr = (struct ifreq *) data;
2094 int s, error;
2095
2096 s = splnet();
2097
2098 switch (cmd) {
2099 case SIOCSIFMEDIA:
2100 case SIOCGIFMEDIA:
2101 /* Flow control requires full-duplex mode. */
2102 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
2103 (ifr->ifr_media & IFM_FDX) == 0)
2104 ifr->ifr_media &= ~IFM_ETH_FMASK;
2105 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
2106 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
2107 /* We can do both TXPAUSE and RXPAUSE. */
2108 ifr->ifr_media |=
2109 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
2110 }
2111 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
2112 }
2113 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
2114 break;
2115 default:
2116 error = ether_ioctl(ifp, cmd, data);
2117 if (error == ENETRESET) {
2118 /*
2119 * Multicast list has changed; set the hardware filter
2120 * accordingly.
2121 */
2122 if (ifp->if_flags & IFF_RUNNING)
2123 wm_set_filter(sc);
2124 error = 0;
2125 }
2126 break;
2127 }
2128
2129 /* Try to get more packets going. */
2130 wm_start(ifp);
2131
2132 splx(s);
2133 return (error);
2134 }
2135
2136 /*
2137 * wm_intr:
2138 *
2139 * Interrupt service routine.
2140 */
2141 static int
2142 wm_intr(void *arg)
2143 {
2144 struct wm_softc *sc = arg;
2145 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2146 uint32_t icr;
2147 int handled = 0;
2148
2149 while (1 /* CONSTCOND */) {
2150 icr = CSR_READ(sc, WMREG_ICR);
2151 if ((icr & sc->sc_icr) == 0)
2152 break;
2153
2154 #if 0 /*NRND > 0*/
2155 if (RND_ENABLED(&sc->rnd_source))
2156 rnd_add_uint32(&sc->rnd_source, icr);
2157 #endif
2158
2159 handled = 1;
2160
2161 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
2162 if (icr & (ICR_RXDMT0|ICR_RXT0)) {
2163 DPRINTF(WM_DEBUG_RX,
2164 ("%s: RX: got Rx intr 0x%08x\n",
2165 sc->sc_dev.dv_xname,
2166 icr & (ICR_RXDMT0|ICR_RXT0)));
2167 WM_EVCNT_INCR(&sc->sc_ev_rxintr);
2168 }
2169 #endif
2170 wm_rxintr(sc);
2171
2172 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
2173 if (icr & ICR_TXDW) {
2174 DPRINTF(WM_DEBUG_TX,
2175 ("%s: TX: got TXDW interrupt\n",
2176 sc->sc_dev.dv_xname));
2177 WM_EVCNT_INCR(&sc->sc_ev_txdw);
2178 }
2179 #endif
2180 wm_txintr(sc);
2181
2182 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) {
2183 WM_EVCNT_INCR(&sc->sc_ev_linkintr);
2184 wm_linkintr(sc, icr);
2185 }
2186
2187 if (icr & ICR_RXO) {
2188 ifp->if_ierrors++;
2189 #if defined(WM_DEBUG)
2190 log(LOG_WARNING, "%s: Receive overrun\n",
2191 sc->sc_dev.dv_xname);
2192 #endif /* defined(WM_DEBUG) */
2193 }
2194 }
2195
2196 if (handled) {
2197 /* Try to get more packets going. */
2198 wm_start(ifp);
2199 }
2200
2201 return (handled);
2202 }
2203
2204 /*
2205 * wm_txintr:
2206 *
2207 * Helper; handle transmit interrupts.
2208 */
2209 static void
2210 wm_txintr(struct wm_softc *sc)
2211 {
2212 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2213 struct wm_txsoft *txs;
2214 uint8_t status;
2215 int i;
2216
2217 ifp->if_flags &= ~IFF_OACTIVE;
2218
2219 /*
2220 * Go through the Tx list and free mbufs for those
2221 * frames which have been transmitted.
2222 */
2223 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc);
2224 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) {
2225 txs = &sc->sc_txsoft[i];
2226
2227 DPRINTF(WM_DEBUG_TX,
2228 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i));
2229
2230 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc,
2231 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2232
2233 status =
2234 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status;
2235 if ((status & WTX_ST_DD) == 0) {
2236 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1,
2237 BUS_DMASYNC_PREREAD);
2238 break;
2239 }
2240
2241 DPRINTF(WM_DEBUG_TX,
2242 ("%s: TX: job %d done: descs %d..%d\n",
2243 sc->sc_dev.dv_xname, i, txs->txs_firstdesc,
2244 txs->txs_lastdesc));
2245
2246 /*
2247 * XXX We should probably be using the statistics
2248 * XXX registers, but I don't know if they exist
2249 * XXX on chips before the i82544.
2250 */
2251
2252 #ifdef WM_EVENT_COUNTERS
2253 if (status & WTX_ST_TU)
2254 WM_EVCNT_INCR(&sc->sc_ev_tu);
2255 #endif /* WM_EVENT_COUNTERS */
2256
2257 if (status & (WTX_ST_EC|WTX_ST_LC)) {
2258 ifp->if_oerrors++;
2259 if (status & WTX_ST_LC)
2260 log(LOG_WARNING, "%s: late collision\n",
2261 sc->sc_dev.dv_xname);
2262 else if (status & WTX_ST_EC) {
2263 ifp->if_collisions += 16;
2264 log(LOG_WARNING, "%s: excessive collisions\n",
2265 sc->sc_dev.dv_xname);
2266 }
2267 } else
2268 ifp->if_opackets++;
2269
2270 sc->sc_txfree += txs->txs_ndesc;
2271 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
2272 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2273 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2274 m_freem(txs->txs_mbuf);
2275 txs->txs_mbuf = NULL;
2276 }
2277
2278 /* Update the dirty transmit buffer pointer. */
2279 sc->sc_txsdirty = i;
2280 DPRINTF(WM_DEBUG_TX,
2281 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i));
2282
2283 /*
2284 * If there are no more pending transmissions, cancel the watchdog
2285 * timer.
2286 */
2287 if (sc->sc_txsfree == WM_TXQUEUELEN(sc))
2288 ifp->if_timer = 0;
2289 }
2290
2291 /*
2292 * wm_rxintr:
2293 *
2294 * Helper; handle receive interrupts.
2295 */
2296 static void
2297 wm_rxintr(struct wm_softc *sc)
2298 {
2299 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2300 struct wm_rxsoft *rxs;
2301 struct mbuf *m;
2302 int i, len;
2303 uint8_t status, errors;
2304
2305 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
2306 rxs = &sc->sc_rxsoft[i];
2307
2308 DPRINTF(WM_DEBUG_RX,
2309 ("%s: RX: checking descriptor %d\n",
2310 sc->sc_dev.dv_xname, i));
2311
2312 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2313
2314 status = sc->sc_rxdescs[i].wrx_status;
2315 errors = sc->sc_rxdescs[i].wrx_errors;
2316 len = le16toh(sc->sc_rxdescs[i].wrx_len);
2317
2318 if ((status & WRX_ST_DD) == 0) {
2319 /*
2320 * We have processed all of the receive descriptors.
2321 */
2322 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
2323 break;
2324 }
2325
2326 if (__predict_false(sc->sc_rxdiscard)) {
2327 DPRINTF(WM_DEBUG_RX,
2328 ("%s: RX: discarding contents of descriptor %d\n",
2329 sc->sc_dev.dv_xname, i));
2330 WM_INIT_RXDESC(sc, i);
2331 if (status & WRX_ST_EOP) {
2332 /* Reset our state. */
2333 DPRINTF(WM_DEBUG_RX,
2334 ("%s: RX: resetting rxdiscard -> 0\n",
2335 sc->sc_dev.dv_xname));
2336 sc->sc_rxdiscard = 0;
2337 }
2338 continue;
2339 }
2340
2341 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2342 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
2343
2344 m = rxs->rxs_mbuf;
2345
2346 /*
2347 * Add a new receive buffer to the ring.
2348 */
2349 if (wm_add_rxbuf(sc, i) != 0) {
2350 /*
2351 * Failed, throw away what we've done so
2352 * far, and discard the rest of the packet.
2353 */
2354 ifp->if_ierrors++;
2355 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2356 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2357 WM_INIT_RXDESC(sc, i);
2358 if ((status & WRX_ST_EOP) == 0)
2359 sc->sc_rxdiscard = 1;
2360 if (sc->sc_rxhead != NULL)
2361 m_freem(sc->sc_rxhead);
2362 WM_RXCHAIN_RESET(sc);
2363 DPRINTF(WM_DEBUG_RX,
2364 ("%s: RX: Rx buffer allocation failed, "
2365 "dropping packet%s\n", sc->sc_dev.dv_xname,
2366 sc->sc_rxdiscard ? " (discard)" : ""));
2367 continue;
2368 }
2369
2370 WM_RXCHAIN_LINK(sc, m);
2371
2372 m->m_len = len;
2373
2374 DPRINTF(WM_DEBUG_RX,
2375 ("%s: RX: buffer at %p len %d\n",
2376 sc->sc_dev.dv_xname, m->m_data, len));
2377
2378 /*
2379 * If this is not the end of the packet, keep
2380 * looking.
2381 */
2382 if ((status & WRX_ST_EOP) == 0) {
2383 sc->sc_rxlen += len;
2384 DPRINTF(WM_DEBUG_RX,
2385 ("%s: RX: not yet EOP, rxlen -> %d\n",
2386 sc->sc_dev.dv_xname, sc->sc_rxlen));
2387 continue;
2388 }
2389
2390 /*
2391 * Okay, we have the entire packet now. The chip is
2392 * configured to include the FCS (not all chips can
2393 * be configured to strip it), so we need to trim it.
2394 */
2395 m->m_len -= ETHER_CRC_LEN;
2396
2397 *sc->sc_rxtailp = NULL;
2398 len = m->m_len + sc->sc_rxlen;
2399 m = sc->sc_rxhead;
2400
2401 WM_RXCHAIN_RESET(sc);
2402
2403 DPRINTF(WM_DEBUG_RX,
2404 ("%s: RX: have entire packet, len -> %d\n",
2405 sc->sc_dev.dv_xname, len));
2406
2407 /*
2408 * If an error occurred, update stats and drop the packet.
2409 */
2410 if (errors &
2411 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
2412 ifp->if_ierrors++;
2413 if (errors & WRX_ER_SE)
2414 log(LOG_WARNING, "%s: symbol error\n",
2415 sc->sc_dev.dv_xname);
2416 else if (errors & WRX_ER_SEQ)
2417 log(LOG_WARNING, "%s: receive sequence error\n",
2418 sc->sc_dev.dv_xname);
2419 else if (errors & WRX_ER_CE)
2420 log(LOG_WARNING, "%s: CRC error\n",
2421 sc->sc_dev.dv_xname);
2422 m_freem(m);
2423 continue;
2424 }
2425
2426 /*
2427 * No errors. Receive the packet.
2428 */
2429 m->m_pkthdr.rcvif = ifp;
2430 m->m_pkthdr.len = len;
2431
2432 #if 0 /* XXXJRT */
2433 /*
2434 * If VLANs are enabled, VLAN packets have been unwrapped
2435 * for us. Associate the tag with the packet.
2436 */
2437 if ((status & WRX_ST_VP) != 0) {
2438 VLAN_INPUT_TAG(ifp, m,
2439 le16toh(sc->sc_rxdescs[i].wrx_special,
2440 continue);
2441 }
2442 #endif /* XXXJRT */
2443
2444 /*
2445 * Set up checksum info for this packet.
2446 */
2447 if ((status & WRX_ST_IXSM) == 0) {
2448 if (status & WRX_ST_IPCS) {
2449 WM_EVCNT_INCR(&sc->sc_ev_rxipsum);
2450 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
2451 if (errors & WRX_ER_IPE)
2452 m->m_pkthdr.csum_flags |=
2453 M_CSUM_IPv4_BAD;
2454 }
2455 if (status & WRX_ST_TCPCS) {
2456 /*
2457 * Note: we don't know if this was TCP or UDP,
2458 * so we just set both bits, and expect the
2459 * upper layers to deal.
2460 */
2461 WM_EVCNT_INCR(&sc->sc_ev_rxtusum);
2462 m->m_pkthdr.csum_flags |=
2463 M_CSUM_TCPv4|M_CSUM_UDPv4;
2464 if (errors & WRX_ER_TCPE)
2465 m->m_pkthdr.csum_flags |=
2466 M_CSUM_TCP_UDP_BAD;
2467 }
2468 }
2469
2470 ifp->if_ipackets++;
2471
2472 #if NBPFILTER > 0
2473 /* Pass this up to any BPF listeners. */
2474 if (ifp->if_bpf)
2475 bpf_mtap(ifp->if_bpf, m);
2476 #endif /* NBPFILTER > 0 */
2477
2478 /* Pass it on. */
2479 (*ifp->if_input)(ifp, m);
2480 }
2481
2482 /* Update the receive pointer. */
2483 sc->sc_rxptr = i;
2484
2485 DPRINTF(WM_DEBUG_RX,
2486 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i));
2487 }
2488
2489 /*
2490 * wm_linkintr:
2491 *
2492 * Helper; handle link interrupts.
2493 */
2494 static void
2495 wm_linkintr(struct wm_softc *sc, uint32_t icr)
2496 {
2497 uint32_t status;
2498
2499 /*
2500 * If we get a link status interrupt on a 1000BASE-T
2501 * device, just fall into the normal MII tick path.
2502 */
2503 if (sc->sc_flags & WM_F_HAS_MII) {
2504 if (icr & ICR_LSC) {
2505 DPRINTF(WM_DEBUG_LINK,
2506 ("%s: LINK: LSC -> mii_tick\n",
2507 sc->sc_dev.dv_xname));
2508 mii_tick(&sc->sc_mii);
2509 } else if (icr & ICR_RXSEQ) {
2510 DPRINTF(WM_DEBUG_LINK,
2511 ("%s: LINK Receive sequence error\n",
2512 sc->sc_dev.dv_xname));
2513 }
2514 return;
2515 }
2516
2517 /*
2518 * If we are now receiving /C/, check for link again in
2519 * a couple of link clock ticks.
2520 */
2521 if (icr & ICR_RXCFG) {
2522 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n",
2523 sc->sc_dev.dv_xname));
2524 sc->sc_tbi_anstate = 2;
2525 }
2526
2527 if (icr & ICR_LSC) {
2528 status = CSR_READ(sc, WMREG_STATUS);
2529 if (status & STATUS_LU) {
2530 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
2531 sc->sc_dev.dv_xname,
2532 (status & STATUS_FD) ? "FDX" : "HDX"));
2533 sc->sc_tctl &= ~TCTL_COLD(0x3ff);
2534 sc->sc_fcrtl &= ~FCRTL_XONE;
2535 if (status & STATUS_FD)
2536 sc->sc_tctl |=
2537 TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
2538 else
2539 sc->sc_tctl |=
2540 TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
2541 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
2542 sc->sc_fcrtl |= FCRTL_XONE;
2543 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
2544 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
2545 WMREG_OLD_FCRTL : WMREG_FCRTL,
2546 sc->sc_fcrtl);
2547 sc->sc_tbi_linkup = 1;
2548 } else {
2549 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
2550 sc->sc_dev.dv_xname));
2551 sc->sc_tbi_linkup = 0;
2552 }
2553 sc->sc_tbi_anstate = 2;
2554 wm_tbi_set_linkled(sc);
2555 } else if (icr & ICR_RXSEQ) {
2556 DPRINTF(WM_DEBUG_LINK,
2557 ("%s: LINK: Receive sequence error\n",
2558 sc->sc_dev.dv_xname));
2559 }
2560 }
2561
2562 /*
2563 * wm_tick:
2564 *
2565 * One second timer, used to check link status, sweep up
2566 * completed transmit jobs, etc.
2567 */
2568 static void
2569 wm_tick(void *arg)
2570 {
2571 struct wm_softc *sc = arg;
2572 int s;
2573
2574 s = splnet();
2575
2576 if (sc->sc_type >= WM_T_82542_2_1) {
2577 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
2578 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
2579 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
2580 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
2581 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
2582 }
2583
2584 if (sc->sc_flags & WM_F_HAS_MII)
2585 mii_tick(&sc->sc_mii);
2586 else
2587 wm_tbi_check_link(sc);
2588
2589 splx(s);
2590
2591 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
2592 }
2593
2594 /*
2595 * wm_reset:
2596 *
2597 * Reset the i82542 chip.
2598 */
2599 static void
2600 wm_reset(struct wm_softc *sc)
2601 {
2602 int i;
2603
2604 /*
2605 * Allocate on-chip memory according to the MTU size.
2606 * The Packet Buffer Allocation register must be written
2607 * before the chip is reset.
2608 */
2609 switch (sc->sc_type) {
2610 case WM_T_82547:
2611 case WM_T_82547_2:
2612 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
2613 PBA_22K : PBA_30K;
2614 sc->sc_txfifo_head = 0;
2615 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
2616 sc->sc_txfifo_size =
2617 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
2618 sc->sc_txfifo_stall = 0;
2619 break;
2620 case WM_T_82571:
2621 case WM_T_82572:
2622 sc->sc_pba = PBA_32K;
2623 break;
2624 case WM_T_82573:
2625 sc->sc_pba = PBA_12K;
2626 break;
2627 default:
2628 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
2629 PBA_40K : PBA_48K;
2630 break;
2631 }
2632 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
2633
2634 switch (sc->sc_type) {
2635 case WM_T_82544:
2636 case WM_T_82540:
2637 case WM_T_82545:
2638 case WM_T_82546:
2639 case WM_T_82541:
2640 case WM_T_82541_2:
2641 /*
2642 * On some chipsets, a reset through a memory-mapped write
2643 * cycle can cause the chip to reset before completing the
2644 * write cycle. This causes major headache that can be
2645 * avoided by issuing the reset via indirect register writes
2646 * through I/O space.
2647 *
2648 * So, if we successfully mapped the I/O BAR at attach time,
2649 * use that. Otherwise, try our luck with a memory-mapped
2650 * reset.
2651 */
2652 if (sc->sc_flags & WM_F_IOH_VALID)
2653 wm_io_write(sc, WMREG_CTRL, CTRL_RST);
2654 else
2655 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
2656 break;
2657
2658 case WM_T_82545_3:
2659 case WM_T_82546_3:
2660 /* Use the shadow control register on these chips. */
2661 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
2662 break;
2663
2664 default:
2665 /* Everything else can safely use the documented method. */
2666 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
2667 break;
2668 }
2669 delay(10000);
2670
2671 for (i = 0; i < 1000; i++) {
2672 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0)
2673 return;
2674 delay(20);
2675 }
2676
2677 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
2678 log(LOG_ERR, "%s: reset failed to complete\n",
2679 sc->sc_dev.dv_xname);
2680 }
2681
2682 /*
2683 * wm_init: [ifnet interface function]
2684 *
2685 * Initialize the interface. Must be called at splnet().
2686 */
2687 static int
2688 wm_init(struct ifnet *ifp)
2689 {
2690 struct wm_softc *sc = ifp->if_softc;
2691 struct wm_rxsoft *rxs;
2692 int i, error = 0;
2693 uint32_t reg;
2694
2695 /*
2696 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
2697 * There is a small but measurable benefit to avoiding the adjusment
2698 * of the descriptor so that the headers are aligned, for normal mtu,
2699 * on such platforms. One possibility is that the DMA itself is
2700 * slightly more efficient if the front of the entire packet (instead
2701 * of the front of the headers) is aligned.
2702 *
2703 * Note we must always set align_tweak to 0 if we are using
2704 * jumbo frames.
2705 */
2706 #ifdef __NO_STRICT_ALIGNMENT
2707 sc->sc_align_tweak = 0;
2708 #else
2709 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
2710 sc->sc_align_tweak = 0;
2711 else
2712 sc->sc_align_tweak = 2;
2713 #endif /* __NO_STRICT_ALIGNMENT */
2714
2715 /* Cancel any pending I/O. */
2716 wm_stop(ifp, 0);
2717
2718 /* Reset the chip to a known state. */
2719 wm_reset(sc);
2720
2721 /* Initialize the transmit descriptor ring. */
2722 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc));
2723 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc),
2724 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2725 sc->sc_txfree = WM_NTXDESC(sc);
2726 sc->sc_txnext = 0;
2727
2728 if (sc->sc_type < WM_T_82543) {
2729 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0));
2730 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0));
2731 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc));
2732 CSR_WRITE(sc, WMREG_OLD_TDH, 0);
2733 CSR_WRITE(sc, WMREG_OLD_TDT, 0);
2734 CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
2735 } else {
2736 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0));
2737 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0));
2738 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc));
2739 CSR_WRITE(sc, WMREG_TDH, 0);
2740 CSR_WRITE(sc, WMREG_TDT, 0);
2741 CSR_WRITE(sc, WMREG_TIDV, 64);
2742 CSR_WRITE(sc, WMREG_TADV, 128);
2743
2744 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
2745 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
2746 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
2747 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
2748 }
2749 CSR_WRITE(sc, WMREG_TQSA_LO, 0);
2750 CSR_WRITE(sc, WMREG_TQSA_HI, 0);
2751
2752 /* Initialize the transmit job descriptors. */
2753 for (i = 0; i < WM_TXQUEUELEN(sc); i++)
2754 sc->sc_txsoft[i].txs_mbuf = NULL;
2755 sc->sc_txsfree = WM_TXQUEUELEN(sc);
2756 sc->sc_txsnext = 0;
2757 sc->sc_txsdirty = 0;
2758
2759 /*
2760 * Initialize the receive descriptor and receive job
2761 * descriptor rings.
2762 */
2763 if (sc->sc_type < WM_T_82543) {
2764 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0));
2765 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0));
2766 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs));
2767 CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
2768 CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
2769 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
2770
2771 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
2772 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
2773 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
2774 CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
2775 CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
2776 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
2777 } else {
2778 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0));
2779 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0));
2780 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs));
2781 CSR_WRITE(sc, WMREG_RDH, 0);
2782 CSR_WRITE(sc, WMREG_RDT, 0);
2783 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD);
2784 CSR_WRITE(sc, WMREG_RADV, 128);
2785 }
2786 for (i = 0; i < WM_NRXDESC; i++) {
2787 rxs = &sc->sc_rxsoft[i];
2788 if (rxs->rxs_mbuf == NULL) {
2789 if ((error = wm_add_rxbuf(sc, i)) != 0) {
2790 log(LOG_ERR, "%s: unable to allocate or map rx "
2791 "buffer %d, error = %d\n",
2792 sc->sc_dev.dv_xname, i, error);
2793 /*
2794 * XXX Should attempt to run with fewer receive
2795 * XXX buffers instead of just failing.
2796 */
2797 wm_rxdrain(sc);
2798 goto out;
2799 }
2800 } else
2801 WM_INIT_RXDESC(sc, i);
2802 }
2803 sc->sc_rxptr = 0;
2804 sc->sc_rxdiscard = 0;
2805 WM_RXCHAIN_RESET(sc);
2806
2807 /*
2808 * Clear out the VLAN table -- we don't use it (yet).
2809 */
2810 CSR_WRITE(sc, WMREG_VET, 0);
2811 for (i = 0; i < WM_VLAN_TABSIZE; i++)
2812 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
2813
2814 /*
2815 * Set up flow-control parameters.
2816 *
2817 * XXX Values could probably stand some tuning.
2818 */
2819 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
2820 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
2821 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
2822
2823 sc->sc_fcrtl = FCRTL_DFLT;
2824 if (sc->sc_type < WM_T_82543) {
2825 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
2826 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
2827 } else {
2828 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
2829 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
2830 }
2831 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
2832
2833 #if 0 /* XXXJRT */
2834 /* Deal with VLAN enables. */
2835 if (VLAN_ATTACHED(&sc->sc_ethercom))
2836 sc->sc_ctrl |= CTRL_VME;
2837 else
2838 #endif /* XXXJRT */
2839 sc->sc_ctrl &= ~CTRL_VME;
2840
2841 /* Write the control registers. */
2842 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
2843 #if 0
2844 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
2845 #endif
2846
2847 /*
2848 * Set up checksum offload parameters.
2849 */
2850 reg = CSR_READ(sc, WMREG_RXCSUM);
2851 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
2852 reg |= RXCSUM_IPOFL;
2853 else
2854 reg &= ~RXCSUM_IPOFL;
2855 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
2856 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
2857 else {
2858 reg &= ~RXCSUM_TUOFL;
2859 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0)
2860 reg &= ~RXCSUM_IPOFL;
2861 }
2862 CSR_WRITE(sc, WMREG_RXCSUM, reg);
2863
2864 /*
2865 * Set up the interrupt registers.
2866 */
2867 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
2868 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
2869 ICR_RXO | ICR_RXT0;
2870 if ((sc->sc_flags & WM_F_HAS_MII) == 0)
2871 sc->sc_icr |= ICR_RXCFG;
2872 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
2873
2874 /* Set up the inter-packet gap. */
2875 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
2876
2877 if (sc->sc_type >= WM_T_82543) {
2878 /* Set up the interrupt throttling register (units of 256ns) */
2879 sc->sc_itr = 1000000000 / (7000 * 256);
2880 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr);
2881 }
2882
2883 #if 0 /* XXXJRT */
2884 /* Set the VLAN ethernetype. */
2885 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
2886 #endif
2887
2888 /*
2889 * Set up the transmit control register; we start out with
2890 * a collision distance suitable for FDX, but update it whe
2891 * we resolve the media type.
2892 */
2893 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
2894 TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
2895 if (sc->sc_type >= WM_T_82571)
2896 sc->sc_tctl |= TCTL_MULR;
2897 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
2898
2899 /* Set the media. */
2900 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp);
2901
2902 /*
2903 * Set up the receive control register; we actually program
2904 * the register when we set the receive filter. Use multicast
2905 * address offset type 0.
2906 *
2907 * Only the i82544 has the ability to strip the incoming
2908 * CRC, so we don't enable that feature.
2909 */
2910 sc->sc_mchash_type = 0;
2911 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
2912 | RCTL_MO(sc->sc_mchash_type);
2913
2914 /* 82573 doesn't support jumbo frame */
2915 if (sc->sc_type != WM_T_82573)
2916 sc->sc_rctl |= RCTL_LPE;
2917
2918 if (MCLBYTES == 2048) {
2919 sc->sc_rctl |= RCTL_2k;
2920 } else {
2921 if (sc->sc_type >= WM_T_82543) {
2922 switch(MCLBYTES) {
2923 case 4096:
2924 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
2925 break;
2926 case 8192:
2927 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
2928 break;
2929 case 16384:
2930 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
2931 break;
2932 default:
2933 panic("wm_init: MCLBYTES %d unsupported",
2934 MCLBYTES);
2935 break;
2936 }
2937 } else panic("wm_init: i82542 requires MCLBYTES = 2048");
2938 }
2939
2940 /* Set the receive filter. */
2941 wm_set_filter(sc);
2942
2943 /* Start the one second link check clock. */
2944 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
2945
2946 /* ...all done! */
2947 ifp->if_flags |= IFF_RUNNING;
2948 ifp->if_flags &= ~IFF_OACTIVE;
2949
2950 out:
2951 if (error)
2952 log(LOG_ERR, "%s: interface not running\n",
2953 sc->sc_dev.dv_xname);
2954 return (error);
2955 }
2956
2957 /*
2958 * wm_rxdrain:
2959 *
2960 * Drain the receive queue.
2961 */
2962 static void
2963 wm_rxdrain(struct wm_softc *sc)
2964 {
2965 struct wm_rxsoft *rxs;
2966 int i;
2967
2968 for (i = 0; i < WM_NRXDESC; i++) {
2969 rxs = &sc->sc_rxsoft[i];
2970 if (rxs->rxs_mbuf != NULL) {
2971 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2972 m_freem(rxs->rxs_mbuf);
2973 rxs->rxs_mbuf = NULL;
2974 }
2975 }
2976 }
2977
2978 /*
2979 * wm_stop: [ifnet interface function]
2980 *
2981 * Stop transmission on the interface.
2982 */
2983 static void
2984 wm_stop(struct ifnet *ifp, int disable)
2985 {
2986 struct wm_softc *sc = ifp->if_softc;
2987 struct wm_txsoft *txs;
2988 int i;
2989
2990 /* Stop the one second clock. */
2991 callout_stop(&sc->sc_tick_ch);
2992
2993 /* Stop the 82547 Tx FIFO stall check timer. */
2994 if (sc->sc_type == WM_T_82547)
2995 callout_stop(&sc->sc_txfifo_ch);
2996
2997 if (sc->sc_flags & WM_F_HAS_MII) {
2998 /* Down the MII. */
2999 mii_down(&sc->sc_mii);
3000 }
3001
3002 /* Stop the transmit and receive processes. */
3003 CSR_WRITE(sc, WMREG_TCTL, 0);
3004 CSR_WRITE(sc, WMREG_RCTL, 0);
3005
3006 /*
3007 * Clear the interrupt mask to ensure the device cannot assert its
3008 * interrupt line.
3009 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service
3010 * any currently pending or shared interrupt.
3011 */
3012 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
3013 sc->sc_icr = 0;
3014
3015 /* Release any queued transmit buffers. */
3016 for (i = 0; i < WM_TXQUEUELEN(sc); i++) {
3017 txs = &sc->sc_txsoft[i];
3018 if (txs->txs_mbuf != NULL) {
3019 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
3020 m_freem(txs->txs_mbuf);
3021 txs->txs_mbuf = NULL;
3022 }
3023 }
3024
3025 if (disable)
3026 wm_rxdrain(sc);
3027
3028 /* Mark the interface as down and cancel the watchdog timer. */
3029 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3030 ifp->if_timer = 0;
3031 }
3032
3033 /*
3034 * wm_acquire_eeprom:
3035 *
3036 * Perform the EEPROM handshake required on some chips.
3037 */
3038 static int
3039 wm_acquire_eeprom(struct wm_softc *sc)
3040 {
3041 uint32_t reg;
3042 int x;
3043
3044 /* always success */
3045 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0)
3046 return 0;
3047
3048 if (wm_get_eeprom_semaphore(sc))
3049 return 1;
3050
3051 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) {
3052 reg = CSR_READ(sc, WMREG_EECD);
3053
3054 /* Request EEPROM access. */
3055 reg |= EECD_EE_REQ;
3056 CSR_WRITE(sc, WMREG_EECD, reg);
3057
3058 /* ..and wait for it to be granted. */
3059 for (x = 0; x < 1000; x++) {
3060 reg = CSR_READ(sc, WMREG_EECD);
3061 if (reg & EECD_EE_GNT)
3062 break;
3063 delay(5);
3064 }
3065 if ((reg & EECD_EE_GNT) == 0) {
3066 aprint_error("%s: could not acquire EEPROM GNT\n",
3067 sc->sc_dev.dv_xname);
3068 reg &= ~EECD_EE_REQ;
3069 CSR_WRITE(sc, WMREG_EECD, reg);
3070 wm_put_eeprom_semaphore(sc);
3071 return (1);
3072 }
3073 }
3074
3075 return (0);
3076 }
3077
3078 /*
3079 * wm_release_eeprom:
3080 *
3081 * Release the EEPROM mutex.
3082 */
3083 static void
3084 wm_release_eeprom(struct wm_softc *sc)
3085 {
3086 uint32_t reg;
3087
3088 /* always success */
3089 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0)
3090 return;
3091
3092 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) {
3093 reg = CSR_READ(sc, WMREG_EECD);
3094 reg &= ~EECD_EE_REQ;
3095 CSR_WRITE(sc, WMREG_EECD, reg);
3096 }
3097
3098 wm_put_eeprom_semaphore(sc);
3099 }
3100
3101 /*
3102 * wm_eeprom_sendbits:
3103 *
3104 * Send a series of bits to the EEPROM.
3105 */
3106 static void
3107 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits)
3108 {
3109 uint32_t reg;
3110 int x;
3111
3112 reg = CSR_READ(sc, WMREG_EECD);
3113
3114 for (x = nbits; x > 0; x--) {
3115 if (bits & (1U << (x - 1)))
3116 reg |= EECD_DI;
3117 else
3118 reg &= ~EECD_DI;
3119 CSR_WRITE(sc, WMREG_EECD, reg);
3120 delay(2);
3121 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
3122 delay(2);
3123 CSR_WRITE(sc, WMREG_EECD, reg);
3124 delay(2);
3125 }
3126 }
3127
3128 /*
3129 * wm_eeprom_recvbits:
3130 *
3131 * Receive a series of bits from the EEPROM.
3132 */
3133 static void
3134 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits)
3135 {
3136 uint32_t reg, val;
3137 int x;
3138
3139 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
3140
3141 val = 0;
3142 for (x = nbits; x > 0; x--) {
3143 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);
3144 delay(2);
3145 if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
3146 val |= (1U << (x - 1));
3147 CSR_WRITE(sc, WMREG_EECD, reg);
3148 delay(2);
3149 }
3150 *valp = val;
3151 }
3152
3153 /*
3154 * wm_read_eeprom_uwire:
3155 *
3156 * Read a word from the EEPROM using the MicroWire protocol.
3157 */
3158 static int
3159 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
3160 {
3161 uint32_t reg, val;
3162 int i;
3163
3164 for (i = 0; i < wordcnt; i++) {
3165 /* Clear SK and DI. */
3166 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
3167 CSR_WRITE(sc, WMREG_EECD, reg);
3168
3169 /* Set CHIP SELECT. */
3170 reg |= EECD_CS;
3171 CSR_WRITE(sc, WMREG_EECD, reg);
3172 delay(2);
3173
3174 /* Shift in the READ command. */
3175 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3);
3176
3177 /* Shift in address. */
3178 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits);
3179
3180 /* Shift out the data. */
3181 wm_eeprom_recvbits(sc, &val, 16);
3182 data[i] = val & 0xffff;
3183
3184 /* Clear CHIP SELECT. */
3185 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
3186 CSR_WRITE(sc, WMREG_EECD, reg);
3187 delay(2);
3188 }
3189
3190 return (0);
3191 }
3192
3193 /*
3194 * wm_spi_eeprom_ready:
3195 *
3196 * Wait for a SPI EEPROM to be ready for commands.
3197 */
3198 static int
3199 wm_spi_eeprom_ready(struct wm_softc *sc)
3200 {
3201 uint32_t val;
3202 int usec;
3203
3204 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) {
3205 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8);
3206 wm_eeprom_recvbits(sc, &val, 8);
3207 if ((val & SPI_SR_RDY) == 0)
3208 break;
3209 }
3210 if (usec >= SPI_MAX_RETRIES) {
3211 aprint_error("%s: EEPROM failed to become ready\n",
3212 sc->sc_dev.dv_xname);
3213 return (1);
3214 }
3215 return (0);
3216 }
3217
3218 /*
3219 * wm_read_eeprom_spi:
3220 *
3221 * Read a work from the EEPROM using the SPI protocol.
3222 */
3223 static int
3224 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
3225 {
3226 uint32_t reg, val;
3227 int i;
3228 uint8_t opc;
3229
3230 /* Clear SK and CS. */
3231 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
3232 CSR_WRITE(sc, WMREG_EECD, reg);
3233 delay(2);
3234
3235 if (wm_spi_eeprom_ready(sc))
3236 return (1);
3237
3238 /* Toggle CS to flush commands. */
3239 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);
3240 delay(2);
3241 CSR_WRITE(sc, WMREG_EECD, reg);
3242 delay(2);
3243
3244 opc = SPI_OPC_READ;
3245 if (sc->sc_ee_addrbits == 8 && word >= 128)
3246 opc |= SPI_OPC_A8;
3247
3248 wm_eeprom_sendbits(sc, opc, 8);
3249 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits);
3250
3251 for (i = 0; i < wordcnt; i++) {
3252 wm_eeprom_recvbits(sc, &val, 16);
3253 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
3254 }
3255
3256 /* Raise CS and clear SK. */
3257 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
3258 CSR_WRITE(sc, WMREG_EECD, reg);
3259 delay(2);
3260
3261 return (0);
3262 }
3263
3264 #define EEPROM_CHECKSUM 0xBABA
3265 #define EEPROM_SIZE 0x0040
3266
3267 /*
3268 * wm_validate_eeprom_checksum
3269 *
3270 * The checksum is defined as the sum of the first 64 (16 bit) words.
3271 */
3272 static int
3273 wm_validate_eeprom_checksum(struct wm_softc *sc)
3274 {
3275 uint16_t checksum;
3276 uint16_t eeprom_data;
3277 int i;
3278
3279 checksum = 0;
3280
3281 for (i = 0; i < EEPROM_SIZE; i++) {
3282 if (wm_read_eeprom(sc, i, 1, &eeprom_data))
3283 return 1;
3284 checksum += eeprom_data;
3285 }
3286
3287 if (checksum != (uint16_t) EEPROM_CHECKSUM)
3288 return 1;
3289
3290 return 0;
3291 }
3292
3293 /*
3294 * wm_read_eeprom:
3295 *
3296 * Read data from the serial EEPROM.
3297 */
3298 static int
3299 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
3300 {
3301 int rv;
3302
3303 if (sc->sc_flags & WM_F_EEPROM_INVALID)
3304 return 1;
3305
3306 if (wm_acquire_eeprom(sc))
3307 return 1;
3308
3309 if (sc->sc_flags & WM_F_EEPROM_EERDEEWR)
3310 rv = wm_read_eeprom_eerd(sc, word, wordcnt, data);
3311 else if (sc->sc_flags & WM_F_EEPROM_SPI)
3312 rv = wm_read_eeprom_spi(sc, word, wordcnt, data);
3313 else
3314 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data);
3315
3316 wm_release_eeprom(sc);
3317 return rv;
3318 }
3319
3320 static int
3321 wm_read_eeprom_eerd(struct wm_softc *sc, int offset, int wordcnt,
3322 uint16_t *data)
3323 {
3324 int i, eerd = 0;
3325 int error = 0;
3326
3327 for (i = 0; i < wordcnt; i++) {
3328 eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
3329
3330 CSR_WRITE(sc, WMREG_EERD, eerd);
3331 error = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
3332 if (error != 0)
3333 break;
3334
3335 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
3336 }
3337
3338 return error;
3339 }
3340
3341 static int
3342 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
3343 {
3344 uint32_t attempts = 100000;
3345 uint32_t i, reg = 0;
3346 int32_t done = -1;
3347
3348 for (i = 0; i < attempts; i++) {
3349 reg = CSR_READ(sc, rw);
3350
3351 if (reg & EERD_DONE) {
3352 done = 0;
3353 break;
3354 }
3355 delay(5);
3356 }
3357
3358 return done;
3359 }
3360
3361 /*
3362 * wm_add_rxbuf:
3363 *
3364 * Add a receive buffer to the indiciated descriptor.
3365 */
3366 static int
3367 wm_add_rxbuf(struct wm_softc *sc, int idx)
3368 {
3369 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx];
3370 struct mbuf *m;
3371 int error;
3372
3373 MGETHDR(m, M_DONTWAIT, MT_DATA);
3374 if (m == NULL)
3375 return (ENOBUFS);
3376
3377 MCLGET(m, M_DONTWAIT);
3378 if ((m->m_flags & M_EXT) == 0) {
3379 m_freem(m);
3380 return (ENOBUFS);
3381 }
3382
3383 if (rxs->rxs_mbuf != NULL)
3384 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
3385
3386 rxs->rxs_mbuf = m;
3387
3388 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
3389 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
3390 BUS_DMA_READ|BUS_DMA_NOWAIT);
3391 if (error) {
3392 /* XXX XXX XXX */
3393 printf("%s: unable to load rx DMA map %d, error = %d\n",
3394 sc->sc_dev.dv_xname, idx, error);
3395 panic("wm_add_rxbuf");
3396 }
3397
3398 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
3399 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
3400
3401 WM_INIT_RXDESC(sc, idx);
3402
3403 return (0);
3404 }
3405
3406 /*
3407 * wm_set_ral:
3408 *
3409 * Set an entery in the receive address list.
3410 */
3411 static void
3412 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
3413 {
3414 uint32_t ral_lo, ral_hi;
3415
3416 if (enaddr != NULL) {
3417 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
3418 (enaddr[3] << 24);
3419 ral_hi = enaddr[4] | (enaddr[5] << 8);
3420 ral_hi |= RAL_AV;
3421 } else {
3422 ral_lo = 0;
3423 ral_hi = 0;
3424 }
3425
3426 if (sc->sc_type >= WM_T_82544) {
3427 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),
3428 ral_lo);
3429 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),
3430 ral_hi);
3431 } else {
3432 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo);
3433 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi);
3434 }
3435 }
3436
3437 /*
3438 * wm_mchash:
3439 *
3440 * Compute the hash of the multicast address for the 4096-bit
3441 * multicast filter.
3442 */
3443 static uint32_t
3444 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
3445 {
3446 static const int lo_shift[4] = { 4, 3, 2, 0 };
3447 static const int hi_shift[4] = { 4, 5, 6, 8 };
3448 uint32_t hash;
3449
3450 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
3451 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
3452
3453 return (hash & 0xfff);
3454 }
3455
3456 /*
3457 * wm_set_filter:
3458 *
3459 * Set up the receive filter.
3460 */
3461 static void
3462 wm_set_filter(struct wm_softc *sc)
3463 {
3464 struct ethercom *ec = &sc->sc_ethercom;
3465 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3466 struct ether_multi *enm;
3467 struct ether_multistep step;
3468 bus_addr_t mta_reg;
3469 uint32_t hash, reg, bit;
3470 int i;
3471
3472 if (sc->sc_type >= WM_T_82544)
3473 mta_reg = WMREG_CORDOVA_MTA;
3474 else
3475 mta_reg = WMREG_MTA;
3476
3477 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
3478
3479 if (ifp->if_flags & IFF_BROADCAST)
3480 sc->sc_rctl |= RCTL_BAM;
3481 if (ifp->if_flags & IFF_PROMISC) {
3482 sc->sc_rctl |= RCTL_UPE;
3483 goto allmulti;
3484 }
3485
3486 /*
3487 * Set the station address in the first RAL slot, and
3488 * clear the remaining slots.
3489 */
3490 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0);
3491 for (i = 1; i < WM_RAL_TABSIZE; i++)
3492 wm_set_ral(sc, NULL, i);
3493
3494 /* Clear out the multicast table. */
3495 for (i = 0; i < WM_MC_TABSIZE; i++)
3496 CSR_WRITE(sc, mta_reg + (i << 2), 0);
3497
3498 ETHER_FIRST_MULTI(step, ec, enm);
3499 while (enm != NULL) {
3500 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
3501 /*
3502 * We must listen to a range of multicast addresses.
3503 * For now, just accept all multicasts, rather than
3504 * trying to set only those filter bits needed to match
3505 * the range. (At this time, the only use of address
3506 * ranges is for IP multicast routing, for which the
3507 * range is big enough to require all bits set.)
3508 */
3509 goto allmulti;
3510 }
3511
3512 hash = wm_mchash(sc, enm->enm_addrlo);
3513
3514 reg = (hash >> 5) & 0x7f;
3515 bit = hash & 0x1f;
3516
3517 hash = CSR_READ(sc, mta_reg + (reg << 2));
3518 hash |= 1U << bit;
3519
3520 /* XXX Hardware bug?? */
3521 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
3522 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
3523 CSR_WRITE(sc, mta_reg + (reg << 2), hash);
3524 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
3525 } else
3526 CSR_WRITE(sc, mta_reg + (reg << 2), hash);
3527
3528 ETHER_NEXT_MULTI(step, enm);
3529 }
3530
3531 ifp->if_flags &= ~IFF_ALLMULTI;
3532 goto setit;
3533
3534 allmulti:
3535 ifp->if_flags |= IFF_ALLMULTI;
3536 sc->sc_rctl |= RCTL_MPE;
3537
3538 setit:
3539 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
3540 }
3541
3542 /*
3543 * wm_tbi_mediainit:
3544 *
3545 * Initialize media for use on 1000BASE-X devices.
3546 */
3547 static void
3548 wm_tbi_mediainit(struct wm_softc *sc)
3549 {
3550 const char *sep = "";
3551
3552 if (sc->sc_type < WM_T_82543)
3553 sc->sc_tipg = TIPG_WM_DFLT;
3554 else
3555 sc->sc_tipg = TIPG_LG_DFLT;
3556
3557 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange,
3558 wm_tbi_mediastatus);
3559
3560 /*
3561 * SWD Pins:
3562 *
3563 * 0 = Link LED (output)
3564 * 1 = Loss Of Signal (input)
3565 */
3566 sc->sc_ctrl |= CTRL_SWDPIO(0);
3567 sc->sc_ctrl &= ~CTRL_SWDPIO(1);
3568
3569 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
3570
3571 #define ADD(ss, mm, dd) \
3572 do { \
3573 aprint_normal("%s%s", sep, ss); \
3574 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \
3575 sep = ", "; \
3576 } while (/*CONSTCOND*/0)
3577
3578 aprint_normal("%s: ", sc->sc_dev.dv_xname);
3579 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
3580 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD);
3581 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD);
3582 aprint_normal("\n");
3583
3584 #undef ADD
3585
3586 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
3587 }
3588
3589 /*
3590 * wm_tbi_mediastatus: [ifmedia interface function]
3591 *
3592 * Get the current interface media status on a 1000BASE-X device.
3593 */
3594 static void
3595 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
3596 {
3597 struct wm_softc *sc = ifp->if_softc;
3598 uint32_t ctrl;
3599
3600 ifmr->ifm_status = IFM_AVALID;
3601 ifmr->ifm_active = IFM_ETHER;
3602
3603 if (sc->sc_tbi_linkup == 0) {
3604 ifmr->ifm_active |= IFM_NONE;
3605 return;
3606 }
3607
3608 ifmr->ifm_status |= IFM_ACTIVE;
3609 ifmr->ifm_active |= IFM_1000_SX;
3610 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
3611 ifmr->ifm_active |= IFM_FDX;
3612 ctrl = CSR_READ(sc, WMREG_CTRL);
3613 if (ctrl & CTRL_RFCE)
3614 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE;
3615 if (ctrl & CTRL_TFCE)
3616 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE;
3617 }
3618
3619 /*
3620 * wm_tbi_mediachange: [ifmedia interface function]
3621 *
3622 * Set hardware to newly-selected media on a 1000BASE-X device.
3623 */
3624 static int
3625 wm_tbi_mediachange(struct ifnet *ifp)
3626 {
3627 struct wm_softc *sc = ifp->if_softc;
3628 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
3629 uint32_t status;
3630 int i;
3631
3632 sc->sc_txcw = ife->ifm_data;
3633 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
3634 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
3635 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM;
3636 sc->sc_txcw |= TXCW_ANE;
3637
3638 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
3639 delay(10000);
3640
3641 /* NOTE: CTRL will update TFCE and RFCE automatically. */
3642
3643 sc->sc_tbi_anstate = 0;
3644
3645 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) {
3646 /* Have signal; wait for the link to come up. */
3647 for (i = 0; i < 50; i++) {
3648 delay(10000);
3649 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
3650 break;
3651 }
3652
3653 status = CSR_READ(sc, WMREG_STATUS);
3654 if (status & STATUS_LU) {
3655 /* Link is up. */
3656 DPRINTF(WM_DEBUG_LINK,
3657 ("%s: LINK: set media -> link up %s\n",
3658 sc->sc_dev.dv_xname,
3659 (status & STATUS_FD) ? "FDX" : "HDX"));
3660 sc->sc_tctl &= ~TCTL_COLD(0x3ff);
3661 sc->sc_fcrtl &= ~FCRTL_XONE;
3662 if (status & STATUS_FD)
3663 sc->sc_tctl |=
3664 TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
3665 else
3666 sc->sc_tctl |=
3667 TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
3668 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
3669 sc->sc_fcrtl |= FCRTL_XONE;
3670 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
3671 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
3672 WMREG_OLD_FCRTL : WMREG_FCRTL,
3673 sc->sc_fcrtl);
3674 sc->sc_tbi_linkup = 1;
3675 } else {
3676 /* Link is down. */
3677 DPRINTF(WM_DEBUG_LINK,
3678 ("%s: LINK: set media -> link down\n",
3679 sc->sc_dev.dv_xname));
3680 sc->sc_tbi_linkup = 0;
3681 }
3682 } else {
3683 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
3684 sc->sc_dev.dv_xname));
3685 sc->sc_tbi_linkup = 0;
3686 }
3687
3688 wm_tbi_set_linkled(sc);
3689
3690 return (0);
3691 }
3692
3693 /*
3694 * wm_tbi_set_linkled:
3695 *
3696 * Update the link LED on 1000BASE-X devices.
3697 */
3698 static void
3699 wm_tbi_set_linkled(struct wm_softc *sc)
3700 {
3701
3702 if (sc->sc_tbi_linkup)
3703 sc->sc_ctrl |= CTRL_SWDPIN(0);
3704 else
3705 sc->sc_ctrl &= ~CTRL_SWDPIN(0);
3706
3707 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
3708 }
3709
3710 /*
3711 * wm_tbi_check_link:
3712 *
3713 * Check the link on 1000BASE-X devices.
3714 */
3715 static void
3716 wm_tbi_check_link(struct wm_softc *sc)
3717 {
3718 uint32_t rxcw, ctrl, status;
3719
3720 if (sc->sc_tbi_anstate == 0)
3721 return;
3722 else if (sc->sc_tbi_anstate > 1) {
3723 DPRINTF(WM_DEBUG_LINK,
3724 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname,
3725 sc->sc_tbi_anstate));
3726 sc->sc_tbi_anstate--;
3727 return;
3728 }
3729
3730 sc->sc_tbi_anstate = 0;
3731
3732 rxcw = CSR_READ(sc, WMREG_RXCW);
3733 ctrl = CSR_READ(sc, WMREG_CTRL);
3734 status = CSR_READ(sc, WMREG_STATUS);
3735
3736 if ((status & STATUS_LU) == 0) {
3737 DPRINTF(WM_DEBUG_LINK,
3738 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname));
3739 sc->sc_tbi_linkup = 0;
3740 } else {
3741 DPRINTF(WM_DEBUG_LINK,
3742 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname,
3743 (status & STATUS_FD) ? "FDX" : "HDX"));
3744 sc->sc_tctl &= ~TCTL_COLD(0x3ff);
3745 sc->sc_fcrtl &= ~FCRTL_XONE;
3746 if (status & STATUS_FD)
3747 sc->sc_tctl |=
3748 TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
3749 else
3750 sc->sc_tctl |=
3751 TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
3752 if (ctrl & CTRL_TFCE)
3753 sc->sc_fcrtl |= FCRTL_XONE;
3754 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
3755 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
3756 WMREG_OLD_FCRTL : WMREG_FCRTL,
3757 sc->sc_fcrtl);
3758 sc->sc_tbi_linkup = 1;
3759 }
3760
3761 wm_tbi_set_linkled(sc);
3762 }
3763
3764 /*
3765 * wm_gmii_reset:
3766 *
3767 * Reset the PHY.
3768 */
3769 static void
3770 wm_gmii_reset(struct wm_softc *sc)
3771 {
3772 uint32_t reg;
3773
3774 if (sc->sc_type >= WM_T_82544) {
3775 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
3776 delay(20000);
3777
3778 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
3779 delay(20000);
3780 } else {
3781 /* The PHY reset pin is active-low. */
3782 reg = CSR_READ(sc, WMREG_CTRL_EXT);
3783 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
3784 CTRL_EXT_SWDPIN(4));
3785 reg |= CTRL_EXT_SWDPIO(4);
3786
3787 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
3788 delay(10);
3789
3790 CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
3791 delay(10);
3792
3793 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
3794 delay(10);
3795 #if 0
3796 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
3797 #endif
3798 }
3799 }
3800
3801 /*
3802 * wm_gmii_mediainit:
3803 *
3804 * Initialize media for use on 1000BASE-T devices.
3805 */
3806 static void
3807 wm_gmii_mediainit(struct wm_softc *sc)
3808 {
3809 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3810
3811 /* We have MII. */
3812 sc->sc_flags |= WM_F_HAS_MII;
3813
3814 sc->sc_tipg = TIPG_1000T_DFLT;
3815
3816 /*
3817 * Let the chip set speed/duplex on its own based on
3818 * signals from the PHY.
3819 */
3820 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE;
3821 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
3822
3823 /* Initialize our media structures and probe the GMII. */
3824 sc->sc_mii.mii_ifp = ifp;
3825
3826 if (sc->sc_type >= WM_T_82544) {
3827 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
3828 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
3829 } else {
3830 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg;
3831 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg;
3832 }
3833 sc->sc_mii.mii_statchg = wm_gmii_statchg;
3834
3835 wm_gmii_reset(sc);
3836
3837 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
3838 wm_gmii_mediastatus);
3839
3840 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
3841 MII_OFFSET_ANY, MIIF_DOPAUSE);
3842 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
3843 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
3844 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
3845 } else
3846 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
3847 }
3848
3849 /*
3850 * wm_gmii_mediastatus: [ifmedia interface function]
3851 *
3852 * Get the current interface media status on a 1000BASE-T device.
3853 */
3854 static void
3855 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
3856 {
3857 struct wm_softc *sc = ifp->if_softc;
3858
3859 mii_pollstat(&sc->sc_mii);
3860 ifmr->ifm_status = sc->sc_mii.mii_media_status;
3861 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) |
3862 sc->sc_flowflags;
3863 }
3864
3865 /*
3866 * wm_gmii_mediachange: [ifmedia interface function]
3867 *
3868 * Set hardware to newly-selected media on a 1000BASE-T device.
3869 */
3870 static int
3871 wm_gmii_mediachange(struct ifnet *ifp)
3872 {
3873 struct wm_softc *sc = ifp->if_softc;
3874
3875 if (ifp->if_flags & IFF_UP)
3876 mii_mediachg(&sc->sc_mii);
3877 return (0);
3878 }
3879
3880 #define MDI_IO CTRL_SWDPIN(2)
3881 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */
3882 #define MDI_CLK CTRL_SWDPIN(3)
3883
3884 static void
3885 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
3886 {
3887 uint32_t i, v;
3888
3889 v = CSR_READ(sc, WMREG_CTRL);
3890 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
3891 v |= MDI_DIR | CTRL_SWDPIO(3);
3892
3893 for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
3894 if (data & i)
3895 v |= MDI_IO;
3896 else
3897 v &= ~MDI_IO;
3898 CSR_WRITE(sc, WMREG_CTRL, v);
3899 delay(10);
3900 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
3901 delay(10);
3902 CSR_WRITE(sc, WMREG_CTRL, v);
3903 delay(10);
3904 }
3905 }
3906
3907 static uint32_t
3908 i82543_mii_recvbits(struct wm_softc *sc)
3909 {
3910 uint32_t v, i, data = 0;
3911
3912 v = CSR_READ(sc, WMREG_CTRL);
3913 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
3914 v |= CTRL_SWDPIO(3);
3915
3916 CSR_WRITE(sc, WMREG_CTRL, v);
3917 delay(10);
3918 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
3919 delay(10);
3920 CSR_WRITE(sc, WMREG_CTRL, v);
3921 delay(10);
3922
3923 for (i = 0; i < 16; i++) {
3924 data <<= 1;
3925 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
3926 delay(10);
3927 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
3928 data |= 1;
3929 CSR_WRITE(sc, WMREG_CTRL, v);
3930 delay(10);
3931 }
3932
3933 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
3934 delay(10);
3935 CSR_WRITE(sc, WMREG_CTRL, v);
3936 delay(10);
3937
3938 return (data);
3939 }
3940
3941 #undef MDI_IO
3942 #undef MDI_DIR
3943 #undef MDI_CLK
3944
3945 /*
3946 * wm_gmii_i82543_readreg: [mii interface function]
3947 *
3948 * Read a PHY register on the GMII (i82543 version).
3949 */
3950 static int
3951 wm_gmii_i82543_readreg(struct device *self, int phy, int reg)
3952 {
3953 struct wm_softc *sc = (void *) self;
3954 int rv;
3955
3956 i82543_mii_sendbits(sc, 0xffffffffU, 32);
3957 i82543_mii_sendbits(sc, reg | (phy << 5) |
3958 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
3959 rv = i82543_mii_recvbits(sc) & 0xffff;
3960
3961 DPRINTF(WM_DEBUG_GMII,
3962 ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
3963 sc->sc_dev.dv_xname, phy, reg, rv));
3964
3965 return (rv);
3966 }
3967
3968 /*
3969 * wm_gmii_i82543_writereg: [mii interface function]
3970 *
3971 * Write a PHY register on the GMII (i82543 version).
3972 */
3973 static void
3974 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val)
3975 {
3976 struct wm_softc *sc = (void *) self;
3977
3978 i82543_mii_sendbits(sc, 0xffffffffU, 32);
3979 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
3980 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
3981 (MII_COMMAND_START << 30), 32);
3982 }
3983
3984 /*
3985 * wm_gmii_i82544_readreg: [mii interface function]
3986 *
3987 * Read a PHY register on the GMII.
3988 */
3989 static int
3990 wm_gmii_i82544_readreg(struct device *self, int phy, int reg)
3991 {
3992 struct wm_softc *sc = (void *) self;
3993 uint32_t mdic = 0;
3994 int i, rv;
3995
3996 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
3997 MDIC_REGADD(reg));
3998
3999 for (i = 0; i < 100; i++) {
4000 mdic = CSR_READ(sc, WMREG_MDIC);
4001 if (mdic & MDIC_READY)
4002 break;
4003 delay(10);
4004 }
4005
4006 if ((mdic & MDIC_READY) == 0) {
4007 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
4008 sc->sc_dev.dv_xname, phy, reg);
4009 rv = 0;
4010 } else if (mdic & MDIC_E) {
4011 #if 0 /* This is normal if no PHY is present. */
4012 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
4013 sc->sc_dev.dv_xname, phy, reg);
4014 #endif
4015 rv = 0;
4016 } else {
4017 rv = MDIC_DATA(mdic);
4018 if (rv == 0xffff)
4019 rv = 0;
4020 }
4021
4022 return (rv);
4023 }
4024
4025 /*
4026 * wm_gmii_i82544_writereg: [mii interface function]
4027 *
4028 * Write a PHY register on the GMII.
4029 */
4030 static void
4031 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val)
4032 {
4033 struct wm_softc *sc = (void *) self;
4034 uint32_t mdic = 0;
4035 int i;
4036
4037 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
4038 MDIC_REGADD(reg) | MDIC_DATA(val));
4039
4040 for (i = 0; i < 100; i++) {
4041 mdic = CSR_READ(sc, WMREG_MDIC);
4042 if (mdic & MDIC_READY)
4043 break;
4044 delay(10);
4045 }
4046
4047 if ((mdic & MDIC_READY) == 0)
4048 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n",
4049 sc->sc_dev.dv_xname, phy, reg);
4050 else if (mdic & MDIC_E)
4051 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n",
4052 sc->sc_dev.dv_xname, phy, reg);
4053 }
4054
4055 /*
4056 * wm_gmii_statchg: [mii interface function]
4057 *
4058 * Callback from MII layer when media changes.
4059 */
4060 static void
4061 wm_gmii_statchg(struct device *self)
4062 {
4063 struct wm_softc *sc = (void *) self;
4064 struct mii_data *mii = &sc->sc_mii;
4065
4066 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
4067 sc->sc_tctl &= ~TCTL_COLD(0x3ff);
4068 sc->sc_fcrtl &= ~FCRTL_XONE;
4069
4070 /*
4071 * Get flow control negotiation result.
4072 */
4073 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
4074 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
4075 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
4076 mii->mii_media_active &= ~IFM_ETH_FMASK;
4077 }
4078
4079 if (sc->sc_flowflags & IFM_FLOW) {
4080 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) {
4081 sc->sc_ctrl |= CTRL_TFCE;
4082 sc->sc_fcrtl |= FCRTL_XONE;
4083 }
4084 if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
4085 sc->sc_ctrl |= CTRL_RFCE;
4086 }
4087
4088 if (sc->sc_mii.mii_media_active & IFM_FDX) {
4089 DPRINTF(WM_DEBUG_LINK,
4090 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname));
4091 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
4092 } else {
4093 DPRINTF(WM_DEBUG_LINK,
4094 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname));
4095 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
4096 }
4097
4098 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
4099 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
4100 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
4101 : WMREG_FCRTL, sc->sc_fcrtl);
4102 }
4103
4104 static int
4105 wm_is_onboard_nvm_eeprom(struct wm_softc *sc)
4106 {
4107 uint32_t eecd = 0;
4108
4109 if (sc->sc_type == WM_T_82573) {
4110 eecd = CSR_READ(sc, WMREG_EECD);
4111
4112 /* Isolate bits 15 & 16 */
4113 eecd = ((eecd >> 15) & 0x03);
4114
4115 /* If both bits are set, device is Flash type */
4116 if (eecd == 0x03) {
4117 return 0;
4118 }
4119 }
4120 return 1;
4121 }
4122
4123 static int
4124 wm_get_eeprom_semaphore(struct wm_softc *sc)
4125 {
4126 int32_t timeout;
4127 uint32_t swsm;
4128
4129 if ((sc->sc_flags & WM_F_EEPROM_SEMAPHORE) == 0)
4130 return 0;
4131
4132 /* Get the FW semaphore. */
4133 timeout = 1000 + 1; /* XXX */
4134 while (timeout) {
4135 swsm = CSR_READ(sc, WMREG_SWSM);
4136 swsm |= SWSM_SWESMBI;
4137 CSR_WRITE(sc, WMREG_SWSM, swsm);
4138 /* if we managed to set the bit we got the semaphore. */
4139 swsm = CSR_READ(sc, WMREG_SWSM);
4140 if (swsm & SWSM_SWESMBI)
4141 break;
4142
4143 delay(50);
4144 timeout--;
4145 }
4146
4147 if (timeout == 0) {
4148 /* Release semaphores */
4149 wm_put_eeprom_semaphore(sc);
4150 return 1;
4151 }
4152
4153 return 0;
4154 }
4155
4156 static void
4157 wm_put_eeprom_semaphore(struct wm_softc *sc)
4158 {
4159 uint32_t swsm;
4160
4161 if ((sc->sc_flags & WM_F_EEPROM_SEMAPHORE) == 0)
4162 return;
4163
4164 swsm = CSR_READ(sc, WMREG_SWSM);
4165 swsm &= ~(SWSM_SWESMBI);
4166 CSR_WRITE(sc, WMREG_SWSM, swsm);
4167 }
4168