if_wm.c revision 1.129
1 /* $NetBSD: if_wm.c,v 1.129 2006/11/16 04:30:02 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.129 2006/11/16 04:30:02 yamt Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 #include <sys/syslog.h> 67 68 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 69 70 #if NRND > 0 71 #include <sys/rnd.h> 72 #endif 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_ether.h> 78 79 #if NBPFILTER > 0 80 #include <net/bpf.h> 81 #endif 82 83 #include <netinet/in.h> /* XXX for struct ip */ 84 #include <netinet/in_systm.h> /* XXX for struct ip */ 85 #include <netinet/ip.h> /* XXX for struct ip */ 86 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 87 88 #include <machine/bus.h> 89 #include <machine/intr.h> 90 #include <machine/endian.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include <dev/mii/mii_bitbang.h> 95 #include <dev/mii/ikphyreg.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcidevs.h> 100 101 #include <dev/pci/if_wmreg.h> 102 103 #ifdef WM_DEBUG 104 #define WM_DEBUG_LINK 0x01 105 #define WM_DEBUG_TX 0x02 106 #define WM_DEBUG_RX 0x04 107 #define WM_DEBUG_GMII 0x08 108 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK|WM_DEBUG_GMII; 109 110 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 111 #else 112 #define DPRINTF(x, y) /* nothing */ 113 #endif /* WM_DEBUG */ 114 115 /* 116 * Transmit descriptor list size. Due to errata, we can only have 117 * 256 hardware descriptors in the ring on < 82544, but we use 4096 118 * on >= 82544. We tell the upper layers that they can queue a lot 119 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 120 * of them at a time. 121 * 122 * We allow up to 256 (!) DMA segments per packet. Pathological packet 123 * chains containing many small mbufs have been observed in zero-copy 124 * situations with jumbo frames. 125 */ 126 #define WM_NTXSEGS 256 127 #define WM_IFQUEUELEN 256 128 #define WM_TXQUEUELEN_MAX 64 129 #define WM_TXQUEUELEN_MAX_82547 16 130 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 131 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 132 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 133 #define WM_NTXDESC_82542 256 134 #define WM_NTXDESC_82544 4096 135 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 136 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 137 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 138 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 139 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 140 141 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 142 143 /* 144 * Receive descriptor list size. We have one Rx buffer for normal 145 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 146 * packet. We allocate 256 receive descriptors, each with a 2k 147 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 148 */ 149 #define WM_NRXDESC 256 150 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 151 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 152 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 153 154 /* 155 * Control structures are DMA'd to the i82542 chip. We allocate them in 156 * a single clump that maps to a single DMA segment to make several things 157 * easier. 158 */ 159 struct wm_control_data_82544 { 160 /* 161 * The receive descriptors. 162 */ 163 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 164 165 /* 166 * The transmit descriptors. Put these at the end, because 167 * we might use a smaller number of them. 168 */ 169 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 170 }; 171 172 struct wm_control_data_82542 { 173 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 174 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 175 }; 176 177 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 178 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 179 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 180 181 /* 182 * Software state for transmit jobs. 183 */ 184 struct wm_txsoft { 185 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 186 bus_dmamap_t txs_dmamap; /* our DMA map */ 187 int txs_firstdesc; /* first descriptor in packet */ 188 int txs_lastdesc; /* last descriptor in packet */ 189 int txs_ndesc; /* # of descriptors used */ 190 }; 191 192 /* 193 * Software state for receive buffers. Each descriptor gets a 194 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 195 * more than one buffer, we chain them together. 196 */ 197 struct wm_rxsoft { 198 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t rxs_dmamap; /* our DMA map */ 200 }; 201 202 typedef enum { 203 WM_T_unknown = 0, 204 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 205 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 206 WM_T_82543, /* i82543 */ 207 WM_T_82544, /* i82544 */ 208 WM_T_82540, /* i82540 */ 209 WM_T_82545, /* i82545 */ 210 WM_T_82545_3, /* i82545 3.0+ */ 211 WM_T_82546, /* i82546 */ 212 WM_T_82546_3, /* i82546 3.0+ */ 213 WM_T_82541, /* i82541 */ 214 WM_T_82541_2, /* i82541 2.0+ */ 215 WM_T_82547, /* i82547 */ 216 WM_T_82547_2, /* i82547 2.0+ */ 217 WM_T_82571, /* i82571 */ 218 WM_T_82572, /* i82572 */ 219 WM_T_82573, /* i82573 */ 220 WM_T_80003, /* i80003 */ 221 } wm_chip_type; 222 223 /* 224 * Software state per device. 225 */ 226 struct wm_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_space_tag_t sc_iot; /* I/O space tag */ 231 bus_space_handle_t sc_ioh; /* I/O space handle */ 232 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 233 struct ethercom sc_ethercom; /* ethernet common data */ 234 void *sc_sdhook; /* shutdown hook */ 235 void *sc_powerhook; /* power hook */ 236 pci_chipset_tag_t sc_pc; 237 pcitag_t sc_pcitag; 238 struct pci_conf_state sc_pciconf; 239 240 wm_chip_type sc_type; /* chip type */ 241 int sc_flags; /* flags; see below */ 242 int sc_bus_speed; /* PCI/PCIX bus speed */ 243 int sc_pcix_offset; /* PCIX capability register offset */ 244 int sc_flowflags; /* 802.3x flow control flags */ 245 246 void *sc_ih; /* interrupt cookie */ 247 248 int sc_ee_addrbits; /* EEPROM address bits */ 249 250 struct mii_data sc_mii; /* MII/media information */ 251 252 struct callout sc_tick_ch; /* tick callout */ 253 254 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 255 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 256 257 int sc_align_tweak; 258 259 /* 260 * Software state for the transmit and receive descriptors. 261 */ 262 int sc_txnum; /* must be a power of two */ 263 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 264 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 265 266 /* 267 * Control data structures. 268 */ 269 int sc_ntxdesc; /* must be a power of two */ 270 struct wm_control_data_82544 *sc_control_data; 271 #define sc_txdescs sc_control_data->wcd_txdescs 272 #define sc_rxdescs sc_control_data->wcd_rxdescs 273 274 #ifdef WM_EVENT_COUNTERS 275 /* Event counters. */ 276 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 277 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 278 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 279 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 280 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 281 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 282 struct evcnt sc_ev_linkintr; /* Link interrupts */ 283 284 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 285 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 286 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 287 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 288 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 289 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound */ 290 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 291 292 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 293 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 294 295 struct evcnt sc_ev_tu; /* Tx underrun */ 296 297 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 298 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 299 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 300 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 301 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 302 #endif /* WM_EVENT_COUNTERS */ 303 304 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 305 306 int sc_txfree; /* number of free Tx descriptors */ 307 int sc_txnext; /* next ready Tx descriptor */ 308 309 int sc_txsfree; /* number of free Tx jobs */ 310 int sc_txsnext; /* next free Tx job */ 311 int sc_txsdirty; /* dirty Tx jobs */ 312 313 /* These 5 variables are used only on the 82547. */ 314 int sc_txfifo_size; /* Tx FIFO size */ 315 int sc_txfifo_head; /* current head of FIFO */ 316 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 317 int sc_txfifo_stall; /* Tx FIFO is stalled */ 318 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 319 320 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 321 322 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 323 int sc_rxdiscard; 324 int sc_rxlen; 325 struct mbuf *sc_rxhead; 326 struct mbuf *sc_rxtail; 327 struct mbuf **sc_rxtailp; 328 329 uint32_t sc_ctrl; /* prototype CTRL register */ 330 #if 0 331 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 332 #endif 333 uint32_t sc_icr; /* prototype interrupt bits */ 334 uint32_t sc_itr; /* prototype intr throttling reg */ 335 uint32_t sc_tctl; /* prototype TCTL register */ 336 uint32_t sc_rctl; /* prototype RCTL register */ 337 uint32_t sc_txcw; /* prototype TXCW register */ 338 uint32_t sc_tipg; /* prototype TIPG register */ 339 uint32_t sc_fcrtl; /* prototype FCRTL register */ 340 uint32_t sc_pba; /* prototype PBA register */ 341 342 int sc_tbi_linkup; /* TBI link status */ 343 int sc_tbi_anstate; /* autonegotiation state */ 344 345 int sc_mchash_type; /* multicast filter offset */ 346 347 #if NRND > 0 348 rndsource_element_t rnd_source; /* random source */ 349 #endif 350 }; 351 352 #define WM_RXCHAIN_RESET(sc) \ 353 do { \ 354 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 355 *(sc)->sc_rxtailp = NULL; \ 356 (sc)->sc_rxlen = 0; \ 357 } while (/*CONSTCOND*/0) 358 359 #define WM_RXCHAIN_LINK(sc, m) \ 360 do { \ 361 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 362 (sc)->sc_rxtailp = &(m)->m_next; \ 363 } while (/*CONSTCOND*/0) 364 365 /* sc_flags */ 366 #define WM_F_HAS_MII 0x0001 /* has MII */ 367 #define WM_F_EEPROM_HANDSHAKE 0x0002 /* requires EEPROM handshake */ 368 #define WM_F_EEPROM_SEMAPHORE 0x0004 /* EEPROM with semaphore */ 369 #define WM_F_EEPROM_EERDEEWR 0x0008 /* EEPROM access via EERD/EEWR */ 370 #define WM_F_EEPROM_SPI 0x0010 /* EEPROM is SPI */ 371 #define WM_F_EEPROM_FLASH 0x0020 /* EEPROM is FLASH */ 372 #define WM_F_EEPROM_INVALID 0x0040 /* EEPROM not present (bad checksum) */ 373 #define WM_F_IOH_VALID 0x0080 /* I/O handle is valid */ 374 #define WM_F_BUS64 0x0100 /* bus is 64-bit */ 375 #define WM_F_PCIX 0x0200 /* bus is PCI-X */ 376 #define WM_F_CSA 0x0400 /* bus is CSA */ 377 #define WM_F_PCIE 0x0800 /* bus is PCI-Express */ 378 #define WM_F_SWFW_SYNC 0x1000 /* Software-Firmware synchronisation */ 379 380 #ifdef WM_EVENT_COUNTERS 381 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 382 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 383 #else 384 #define WM_EVCNT_INCR(ev) /* nothing */ 385 #define WM_EVCNT_ADD(ev, val) /* nothing */ 386 #endif 387 388 #define CSR_READ(sc, reg) \ 389 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 390 #define CSR_WRITE(sc, reg, val) \ 391 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 392 #define CSR_WRITE_FLUSH(sc) \ 393 (void) CSR_READ((sc), WMREG_STATUS) 394 395 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 396 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 397 398 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 399 #define WM_CDTXADDR_HI(sc, x) \ 400 (sizeof(bus_addr_t) == 8 ? \ 401 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 402 403 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 404 #define WM_CDRXADDR_HI(sc, x) \ 405 (sizeof(bus_addr_t) == 8 ? \ 406 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 407 408 #define WM_CDTXSYNC(sc, x, n, ops) \ 409 do { \ 410 int __x, __n; \ 411 \ 412 __x = (x); \ 413 __n = (n); \ 414 \ 415 /* If it will wrap around, sync to the end of the ring. */ \ 416 if ((__x + __n) > WM_NTXDESC(sc)) { \ 417 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 418 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 419 (WM_NTXDESC(sc) - __x), (ops)); \ 420 __n -= (WM_NTXDESC(sc) - __x); \ 421 __x = 0; \ 422 } \ 423 \ 424 /* Now sync whatever is left. */ \ 425 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 426 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 427 } while (/*CONSTCOND*/0) 428 429 #define WM_CDRXSYNC(sc, x, ops) \ 430 do { \ 431 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 432 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 433 } while (/*CONSTCOND*/0) 434 435 #define WM_INIT_RXDESC(sc, x) \ 436 do { \ 437 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 438 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 439 struct mbuf *__m = __rxs->rxs_mbuf; \ 440 \ 441 /* \ 442 * Note: We scoot the packet forward 2 bytes in the buffer \ 443 * so that the payload after the Ethernet header is aligned \ 444 * to a 4-byte boundary. \ 445 * \ 446 * XXX BRAINDAMAGE ALERT! \ 447 * The stupid chip uses the same size for every buffer, which \ 448 * is set in the Receive Control register. We are using the 2K \ 449 * size option, but what we REALLY want is (2K - 2)! For this \ 450 * reason, we can't "scoot" packets longer than the standard \ 451 * Ethernet MTU. On strict-alignment platforms, if the total \ 452 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 453 * the upper layer copy the headers. \ 454 */ \ 455 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 456 \ 457 wm_set_dma_addr(&__rxd->wrx_addr, \ 458 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 459 __rxd->wrx_len = 0; \ 460 __rxd->wrx_cksum = 0; \ 461 __rxd->wrx_status = 0; \ 462 __rxd->wrx_errors = 0; \ 463 __rxd->wrx_special = 0; \ 464 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 465 \ 466 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 467 } while (/*CONSTCOND*/0) 468 469 static void wm_start(struct ifnet *); 470 static void wm_watchdog(struct ifnet *); 471 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 472 static int wm_init(struct ifnet *); 473 static void wm_stop(struct ifnet *, int); 474 475 static void wm_shutdown(void *); 476 static void wm_powerhook(int, void *); 477 478 static void wm_reset(struct wm_softc *); 479 static void wm_rxdrain(struct wm_softc *); 480 static int wm_add_rxbuf(struct wm_softc *, int); 481 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 482 static int wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *); 483 static int wm_validate_eeprom_checksum(struct wm_softc *); 484 static void wm_tick(void *); 485 486 static void wm_set_filter(struct wm_softc *); 487 488 static int wm_intr(void *); 489 static void wm_txintr(struct wm_softc *); 490 static void wm_rxintr(struct wm_softc *); 491 static void wm_linkintr(struct wm_softc *, uint32_t); 492 493 static void wm_tbi_mediainit(struct wm_softc *); 494 static int wm_tbi_mediachange(struct ifnet *); 495 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 496 497 static void wm_tbi_set_linkled(struct wm_softc *); 498 static void wm_tbi_check_link(struct wm_softc *); 499 500 static void wm_gmii_reset(struct wm_softc *); 501 502 static int wm_gmii_i82543_readreg(struct device *, int, int); 503 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 504 505 static int wm_gmii_i82544_readreg(struct device *, int, int); 506 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 507 508 static int wm_gmii_i80003_readreg(struct device *, int, int); 509 static void wm_gmii_i80003_writereg(struct device *, int, int, int); 510 511 static void wm_gmii_statchg(struct device *); 512 513 static void wm_gmii_mediainit(struct wm_softc *); 514 static int wm_gmii_mediachange(struct ifnet *); 515 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 516 517 static int wm_kmrn_i80003_readreg(struct wm_softc *, int); 518 static void wm_kmrn_i80003_writereg(struct wm_softc *, int, int); 519 520 static int wm_match(struct device *, struct cfdata *, void *); 521 static void wm_attach(struct device *, struct device *, void *); 522 static int wm_is_onboard_nvm_eeprom(struct wm_softc *); 523 static int wm_get_swsm_semaphore(struct wm_softc *); 524 static void wm_put_swsm_semaphore(struct wm_softc *); 525 static int wm_poll_eerd_eewr_done(struct wm_softc *, int); 526 static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t); 527 static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t); 528 529 CFATTACH_DECL(wm, sizeof(struct wm_softc), 530 wm_match, wm_attach, NULL, NULL); 531 532 static void wm_82547_txfifo_stall(void *); 533 534 /* 535 * Devices supported by this driver. 536 */ 537 static const struct wm_product { 538 pci_vendor_id_t wmp_vendor; 539 pci_product_id_t wmp_product; 540 const char *wmp_name; 541 wm_chip_type wmp_type; 542 int wmp_flags; 543 #define WMP_F_1000X 0x01 544 #define WMP_F_1000T 0x02 545 } wm_products[] = { 546 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 547 "Intel i82542 1000BASE-X Ethernet", 548 WM_T_82542_2_1, WMP_F_1000X }, 549 550 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 551 "Intel i82543GC 1000BASE-X Ethernet", 552 WM_T_82543, WMP_F_1000X }, 553 554 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 555 "Intel i82543GC 1000BASE-T Ethernet", 556 WM_T_82543, WMP_F_1000T }, 557 558 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 559 "Intel i82544EI 1000BASE-T Ethernet", 560 WM_T_82544, WMP_F_1000T }, 561 562 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 563 "Intel i82544EI 1000BASE-X Ethernet", 564 WM_T_82544, WMP_F_1000X }, 565 566 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 567 "Intel i82544GC 1000BASE-T Ethernet", 568 WM_T_82544, WMP_F_1000T }, 569 570 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 571 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 572 WM_T_82544, WMP_F_1000T }, 573 574 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 575 "Intel i82540EM 1000BASE-T Ethernet", 576 WM_T_82540, WMP_F_1000T }, 577 578 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 579 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 580 WM_T_82540, WMP_F_1000T }, 581 582 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 583 "Intel i82540EP 1000BASE-T Ethernet", 584 WM_T_82540, WMP_F_1000T }, 585 586 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 587 "Intel i82540EP 1000BASE-T Ethernet", 588 WM_T_82540, WMP_F_1000T }, 589 590 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 591 "Intel i82540EP 1000BASE-T Ethernet", 592 WM_T_82540, WMP_F_1000T }, 593 594 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 595 "Intel i82545EM 1000BASE-T Ethernet", 596 WM_T_82545, WMP_F_1000T }, 597 598 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 599 "Intel i82545GM 1000BASE-T Ethernet", 600 WM_T_82545_3, WMP_F_1000T }, 601 602 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 603 "Intel i82545GM 1000BASE-X Ethernet", 604 WM_T_82545_3, WMP_F_1000X }, 605 #if 0 606 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 607 "Intel i82545GM Gigabit Ethernet (SERDES)", 608 WM_T_82545_3, WMP_F_SERDES }, 609 #endif 610 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 611 "Intel i82546EB 1000BASE-T Ethernet", 612 WM_T_82546, WMP_F_1000T }, 613 614 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 615 "Intel i82546EB 1000BASE-T Ethernet", 616 WM_T_82546, WMP_F_1000T }, 617 618 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 619 "Intel i82545EM 1000BASE-X Ethernet", 620 WM_T_82545, WMP_F_1000X }, 621 622 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 623 "Intel i82546EB 1000BASE-X Ethernet", 624 WM_T_82546, WMP_F_1000X }, 625 626 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 627 "Intel i82546GB 1000BASE-T Ethernet", 628 WM_T_82546_3, WMP_F_1000T }, 629 630 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 631 "Intel i82546GB 1000BASE-X Ethernet", 632 WM_T_82546_3, WMP_F_1000X }, 633 #if 0 634 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 635 "Intel i82546GB Gigabit Ethernet (SERDES)", 636 WM_T_82546_3, WMP_F_SERDES }, 637 #endif 638 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER, 639 "i82546GB quad-port Gigabit Ethernet", 640 WM_T_82546_3, WMP_F_1000T }, 641 642 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3, 643 "i82546GB quad-port Gigabit Ethernet (KSP3)", 644 WM_T_82546_3, WMP_F_1000T }, 645 646 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, 647 "Intel PRO/1000MT (82546GB)", 648 WM_T_82546_3, WMP_F_1000T }, 649 650 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 651 "Intel i82541EI 1000BASE-T Ethernet", 652 WM_T_82541, WMP_F_1000T }, 653 654 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, 655 "Intel i82541ER (LOM) 1000BASE-T Ethernet", 656 WM_T_82541, WMP_F_1000T }, 657 658 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 659 "Intel i82541EI Mobile 1000BASE-T Ethernet", 660 WM_T_82541, WMP_F_1000T }, 661 662 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 663 "Intel i82541ER 1000BASE-T Ethernet", 664 WM_T_82541_2, WMP_F_1000T }, 665 666 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 667 "Intel i82541GI 1000BASE-T Ethernet", 668 WM_T_82541_2, WMP_F_1000T }, 669 670 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 671 "Intel i82541GI Mobile 1000BASE-T Ethernet", 672 WM_T_82541_2, WMP_F_1000T }, 673 674 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 675 "Intel i82541PI 1000BASE-T Ethernet", 676 WM_T_82541_2, WMP_F_1000T }, 677 678 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 679 "Intel i82547EI 1000BASE-T Ethernet", 680 WM_T_82547, WMP_F_1000T }, 681 682 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, 683 "Intel i82547EI Moblie 1000BASE-T Ethernet", 684 WM_T_82547, WMP_F_1000T }, 685 686 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 687 "Intel i82547GI 1000BASE-T Ethernet", 688 WM_T_82547_2, WMP_F_1000T }, 689 690 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, 691 "Intel PRO/1000 PT (82571EB)", 692 WM_T_82571, WMP_F_1000T }, 693 694 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, 695 "Intel PRO/1000 PF (82571EB)", 696 WM_T_82571, WMP_F_1000X }, 697 #if 0 698 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, 699 "Intel PRO/1000 PB (82571EB)", 700 WM_T_82571, WMP_F_SERDES }, 701 #endif 702 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER, 703 "Intel PRO/1000 QT (82571EB)", 704 WM_T_82571, WMP_F_1000T }, 705 706 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, 707 "Intel i82572EI 1000baseT Ethernet", 708 WM_T_82572, WMP_F_1000T }, 709 710 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, 711 "Intel i82572EI 1000baseX Ethernet", 712 WM_T_82572, WMP_F_1000X }, 713 #if 0 714 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, 715 "Intel i82572EI Gigabit Ethernet (SERDES)", 716 WM_T_82572, WMP_F_SERDES }, 717 #endif 718 719 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, 720 "Intel i82572EI 1000baseT Ethernet", 721 WM_T_82572, WMP_F_1000T }, 722 723 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, 724 "Intel i82573E", 725 WM_T_82573, WMP_F_1000T }, 726 727 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, 728 "Intel i82573E IAMT", 729 WM_T_82573, WMP_F_1000T }, 730 731 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, 732 "Intel i82573L Gigabit Ethernet", 733 WM_T_82573, WMP_F_1000T }, 734 735 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT, 736 "i80003 dual 1000baseT Ethernet", 737 WM_T_80003, WMP_F_1000T }, 738 739 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT, 740 "i80003 dual 1000baseX Ethernet", 741 WM_T_80003, WMP_F_1000T }, 742 #if 0 743 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT, 744 "Intel i80003ES2 dual Gigabit Ethernet (SERDES)", 745 WM_T_80003, WMP_F_SERDES }, 746 #endif 747 748 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT, 749 "Intel i80003 1000baseT Ethernet", 750 WM_T_80003, WMP_F_1000T }, 751 #if 0 752 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT, 753 "Intel i80003 Gigabit Ethernet (SERDES)", 754 WM_T_80003, WMP_F_SERDES }, 755 #endif 756 757 { 0, 0, 758 NULL, 759 0, 0 }, 760 }; 761 762 #ifdef WM_EVENT_COUNTERS 763 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 764 #endif /* WM_EVENT_COUNTERS */ 765 766 #if 0 /* Not currently used */ 767 static inline uint32_t 768 wm_io_read(struct wm_softc *sc, int reg) 769 { 770 771 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 772 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 773 } 774 #endif 775 776 static inline void 777 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 778 { 779 780 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 781 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 782 } 783 784 static inline void 785 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 786 { 787 wa->wa_low = htole32(v & 0xffffffffU); 788 if (sizeof(bus_addr_t) == 8) 789 wa->wa_high = htole32((uint64_t) v >> 32); 790 else 791 wa->wa_high = 0; 792 } 793 794 static const struct wm_product * 795 wm_lookup(const struct pci_attach_args *pa) 796 { 797 const struct wm_product *wmp; 798 799 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 800 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 801 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 802 return (wmp); 803 } 804 return (NULL); 805 } 806 807 static int 808 wm_match(struct device *parent, struct cfdata *cf, void *aux) 809 { 810 struct pci_attach_args *pa = aux; 811 812 if (wm_lookup(pa) != NULL) 813 return (1); 814 815 return (0); 816 } 817 818 static void 819 wm_attach(struct device *parent, struct device *self, void *aux) 820 { 821 struct wm_softc *sc = (void *) self; 822 struct pci_attach_args *pa = aux; 823 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 824 pci_chipset_tag_t pc = pa->pa_pc; 825 pci_intr_handle_t ih; 826 size_t cdata_size; 827 const char *intrstr = NULL; 828 const char *eetype; 829 bus_space_tag_t memt; 830 bus_space_handle_t memh; 831 bus_dma_segment_t seg; 832 int memh_valid; 833 int i, rseg, error; 834 const struct wm_product *wmp; 835 prop_data_t ea; 836 prop_number_t pn; 837 uint8_t enaddr[ETHER_ADDR_LEN]; 838 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 839 pcireg_t preg, memtype; 840 uint32_t reg; 841 842 callout_init(&sc->sc_tick_ch); 843 844 wmp = wm_lookup(pa); 845 if (wmp == NULL) { 846 printf("\n"); 847 panic("wm_attach: impossible"); 848 } 849 850 sc->sc_pc = pa->pa_pc; 851 sc->sc_pcitag = pa->pa_tag; 852 853 if (pci_dma64_available(pa)) 854 sc->sc_dmat = pa->pa_dmat64; 855 else 856 sc->sc_dmat = pa->pa_dmat; 857 858 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 859 aprint_naive(": Ethernet controller\n"); 860 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 861 862 sc->sc_type = wmp->wmp_type; 863 if (sc->sc_type < WM_T_82543) { 864 if (preg < 2) { 865 aprint_error("%s: i82542 must be at least rev. 2\n", 866 sc->sc_dev.dv_xname); 867 return; 868 } 869 if (preg < 3) 870 sc->sc_type = WM_T_82542_2_0; 871 } 872 873 /* 874 * Map the device. All devices support memory-mapped acccess, 875 * and it is really required for normal operation. 876 */ 877 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 878 switch (memtype) { 879 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 880 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 881 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 882 memtype, 0, &memt, &memh, NULL, NULL) == 0); 883 break; 884 default: 885 memh_valid = 0; 886 } 887 888 if (memh_valid) { 889 sc->sc_st = memt; 890 sc->sc_sh = memh; 891 } else { 892 aprint_error("%s: unable to map device registers\n", 893 sc->sc_dev.dv_xname); 894 return; 895 } 896 897 /* 898 * In addition, i82544 and later support I/O mapped indirect 899 * register access. It is not desirable (nor supported in 900 * this driver) to use it for normal operation, though it is 901 * required to work around bugs in some chip versions. 902 */ 903 if (sc->sc_type >= WM_T_82544) { 904 /* First we have to find the I/O BAR. */ 905 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 906 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 907 PCI_MAPREG_TYPE_IO) 908 break; 909 } 910 if (i == PCI_MAPREG_END) 911 aprint_error("%s: WARNING: unable to find I/O BAR\n", 912 sc->sc_dev.dv_xname); 913 else { 914 /* 915 * The i8254x doesn't apparently respond when the 916 * I/O BAR is 0, which looks somewhat like it's not 917 * been configured. 918 */ 919 preg = pci_conf_read(pc, pa->pa_tag, i); 920 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 921 aprint_error("%s: WARNING: I/O BAR at zero.\n", 922 sc->sc_dev.dv_xname); 923 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 924 0, &sc->sc_iot, &sc->sc_ioh, 925 NULL, NULL) == 0) { 926 sc->sc_flags |= WM_F_IOH_VALID; 927 } else { 928 aprint_error("%s: WARNING: unable to map " 929 "I/O space\n", sc->sc_dev.dv_xname); 930 } 931 } 932 933 } 934 935 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 936 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 937 preg |= PCI_COMMAND_MASTER_ENABLE; 938 if (sc->sc_type < WM_T_82542_2_1) 939 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 940 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 941 942 /* power up chip */ 943 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 944 NULL)) && error != EOPNOTSUPP) { 945 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 946 error); 947 return; 948 } 949 950 /* 951 * Map and establish our interrupt. 952 */ 953 if (pci_intr_map(pa, &ih)) { 954 aprint_error("%s: unable to map interrupt\n", 955 sc->sc_dev.dv_xname); 956 return; 957 } 958 intrstr = pci_intr_string(pc, ih); 959 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 960 if (sc->sc_ih == NULL) { 961 aprint_error("%s: unable to establish interrupt", 962 sc->sc_dev.dv_xname); 963 if (intrstr != NULL) 964 aprint_normal(" at %s", intrstr); 965 aprint_normal("\n"); 966 return; 967 } 968 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 969 970 /* 971 * Determine a few things about the bus we're connected to. 972 */ 973 if (sc->sc_type < WM_T_82543) { 974 /* We don't really know the bus characteristics here. */ 975 sc->sc_bus_speed = 33; 976 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 977 /* 978 * CSA (Communication Streaming Architecture) is about as fast 979 * a 32-bit 66MHz PCI Bus. 980 */ 981 sc->sc_flags |= WM_F_CSA; 982 sc->sc_bus_speed = 66; 983 aprint_verbose("%s: Communication Streaming Architecture\n", 984 sc->sc_dev.dv_xname); 985 if (sc->sc_type == WM_T_82547) { 986 callout_init(&sc->sc_txfifo_ch); 987 callout_setfunc(&sc->sc_txfifo_ch, 988 wm_82547_txfifo_stall, sc); 989 aprint_verbose("%s: using 82547 Tx FIFO stall " 990 "work-around\n", sc->sc_dev.dv_xname); 991 } 992 } else if (sc->sc_type >= WM_T_82571) { 993 sc->sc_flags |= WM_F_PCIE | WM_F_EEPROM_SEMAPHORE; 994 aprint_verbose("%s: PCI-Express bus\n", sc->sc_dev.dv_xname); 995 } else { 996 reg = CSR_READ(sc, WMREG_STATUS); 997 if (reg & STATUS_BUS64) 998 sc->sc_flags |= WM_F_BUS64; 999 if (sc->sc_type >= WM_T_82544 && 1000 (reg & STATUS_PCIX_MODE) != 0) { 1001 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 1002 1003 sc->sc_flags |= WM_F_PCIX; 1004 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1005 PCI_CAP_PCIX, 1006 &sc->sc_pcix_offset, NULL) == 0) 1007 aprint_error("%s: unable to find PCIX " 1008 "capability\n", sc->sc_dev.dv_xname); 1009 else if (sc->sc_type != WM_T_82545_3 && 1010 sc->sc_type != WM_T_82546_3) { 1011 /* 1012 * Work around a problem caused by the BIOS 1013 * setting the max memory read byte count 1014 * incorrectly. 1015 */ 1016 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 1017 sc->sc_pcix_offset + PCI_PCIX_CMD); 1018 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 1019 sc->sc_pcix_offset + PCI_PCIX_STATUS); 1020 1021 bytecnt = 1022 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 1023 PCI_PCIX_CMD_BYTECNT_SHIFT; 1024 maxb = 1025 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 1026 PCI_PCIX_STATUS_MAXB_SHIFT; 1027 if (bytecnt > maxb) { 1028 aprint_verbose("%s: resetting PCI-X " 1029 "MMRBC: %d -> %d\n", 1030 sc->sc_dev.dv_xname, 1031 512 << bytecnt, 512 << maxb); 1032 pcix_cmd = (pcix_cmd & 1033 ~PCI_PCIX_CMD_BYTECNT_MASK) | 1034 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 1035 pci_conf_write(pa->pa_pc, pa->pa_tag, 1036 sc->sc_pcix_offset + PCI_PCIX_CMD, 1037 pcix_cmd); 1038 } 1039 } 1040 } 1041 /* 1042 * The quad port adapter is special; it has a PCIX-PCIX 1043 * bridge on the board, and can run the secondary bus at 1044 * a higher speed. 1045 */ 1046 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 1047 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 1048 : 66; 1049 } else if (sc->sc_flags & WM_F_PCIX) { 1050 switch (reg & STATUS_PCIXSPD_MASK) { 1051 case STATUS_PCIXSPD_50_66: 1052 sc->sc_bus_speed = 66; 1053 break; 1054 case STATUS_PCIXSPD_66_100: 1055 sc->sc_bus_speed = 100; 1056 break; 1057 case STATUS_PCIXSPD_100_133: 1058 sc->sc_bus_speed = 133; 1059 break; 1060 default: 1061 aprint_error( 1062 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 1063 sc->sc_dev.dv_xname, 1064 reg & STATUS_PCIXSPD_MASK); 1065 sc->sc_bus_speed = 66; 1066 } 1067 } else 1068 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 1069 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 1070 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 1071 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 1072 } 1073 1074 /* 1075 * Allocate the control data structures, and create and load the 1076 * DMA map for it. 1077 * 1078 * NOTE: All Tx descriptors must be in the same 4G segment of 1079 * memory. So must Rx descriptors. We simplify by allocating 1080 * both sets within the same 4G segment. 1081 */ 1082 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 1083 WM_NTXDESC_82542 : WM_NTXDESC_82544; 1084 cdata_size = sc->sc_type < WM_T_82544 ? 1085 sizeof(struct wm_control_data_82542) : 1086 sizeof(struct wm_control_data_82544); 1087 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 1088 (bus_size_t) 0x100000000ULL, 1089 &seg, 1, &rseg, 0)) != 0) { 1090 aprint_error( 1091 "%s: unable to allocate control data, error = %d\n", 1092 sc->sc_dev.dv_xname, error); 1093 goto fail_0; 1094 } 1095 1096 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 1097 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 1098 aprint_error("%s: unable to map control data, error = %d\n", 1099 sc->sc_dev.dv_xname, error); 1100 goto fail_1; 1101 } 1102 1103 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 1104 0, 0, &sc->sc_cddmamap)) != 0) { 1105 aprint_error("%s: unable to create control data DMA map, " 1106 "error = %d\n", sc->sc_dev.dv_xname, error); 1107 goto fail_2; 1108 } 1109 1110 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1111 sc->sc_control_data, cdata_size, NULL, 1112 0)) != 0) { 1113 aprint_error( 1114 "%s: unable to load control data DMA map, error = %d\n", 1115 sc->sc_dev.dv_xname, error); 1116 goto fail_3; 1117 } 1118 1119 1120 /* 1121 * Create the transmit buffer DMA maps. 1122 */ 1123 WM_TXQUEUELEN(sc) = 1124 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1125 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1126 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1127 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1128 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1129 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1130 aprint_error("%s: unable to create Tx DMA map %d, " 1131 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1132 goto fail_4; 1133 } 1134 } 1135 1136 /* 1137 * Create the receive buffer DMA maps. 1138 */ 1139 for (i = 0; i < WM_NRXDESC; i++) { 1140 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1141 MCLBYTES, 0, 0, 1142 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1143 aprint_error("%s: unable to create Rx DMA map %d, " 1144 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1145 goto fail_5; 1146 } 1147 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1148 } 1149 1150 /* clear interesting stat counters */ 1151 CSR_READ(sc, WMREG_COLC); 1152 CSR_READ(sc, WMREG_RXERRC); 1153 1154 /* 1155 * Reset the chip to a known state. 1156 */ 1157 wm_reset(sc); 1158 1159 /* 1160 * Get some information about the EEPROM. 1161 */ 1162 if (sc->sc_type == WM_T_80003) 1163 sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_SWFW_SYNC; 1164 else if (sc->sc_type == WM_T_82573) 1165 sc->sc_flags |= WM_F_EEPROM_EERDEEWR; 1166 else if (sc->sc_type > WM_T_82544) 1167 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1168 1169 if (sc->sc_type <= WM_T_82544) 1170 sc->sc_ee_addrbits = 6; 1171 else if (sc->sc_type <= WM_T_82546_3) { 1172 reg = CSR_READ(sc, WMREG_EECD); 1173 if (reg & EECD_EE_SIZE) 1174 sc->sc_ee_addrbits = 8; 1175 else 1176 sc->sc_ee_addrbits = 6; 1177 } else if (sc->sc_type <= WM_T_82547_2) { 1178 reg = CSR_READ(sc, WMREG_EECD); 1179 if (reg & EECD_EE_TYPE) { 1180 sc->sc_flags |= WM_F_EEPROM_SPI; 1181 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1182 } else 1183 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1184 } else if ((sc->sc_type == WM_T_82573) && 1185 (wm_is_onboard_nvm_eeprom(sc) == 0)) { 1186 sc->sc_flags |= WM_F_EEPROM_FLASH; 1187 } else { 1188 /* Assume everything else is SPI. */ 1189 reg = CSR_READ(sc, WMREG_EECD); 1190 sc->sc_flags |= WM_F_EEPROM_SPI; 1191 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1192 } 1193 1194 /* 1195 * Defer printing the EEPROM type until after verifying the checksum 1196 * This allows the EEPROM type to be printed correctly in the case 1197 * that no EEPROM is attached. 1198 */ 1199 1200 1201 /* 1202 * Validate the EEPROM checksum. If the checksum fails, flag this for 1203 * later, so we can fail future reads from the EEPROM. 1204 */ 1205 if (wm_validate_eeprom_checksum(sc)) 1206 sc->sc_flags |= WM_F_EEPROM_INVALID; 1207 1208 if (sc->sc_flags & WM_F_EEPROM_INVALID) 1209 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname); 1210 else if (sc->sc_flags & WM_F_EEPROM_FLASH) { 1211 aprint_verbose("%s: FLASH\n", sc->sc_dev.dv_xname); 1212 } else { 1213 if (sc->sc_flags & WM_F_EEPROM_SPI) 1214 eetype = "SPI"; 1215 else 1216 eetype = "MicroWire"; 1217 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1218 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1219 sc->sc_ee_addrbits, eetype); 1220 } 1221 1222 /* 1223 * Read the Ethernet address from the EEPROM, if not first found 1224 * in device properties. 1225 */ 1226 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 1227 if (ea != NULL) { 1228 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 1229 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 1230 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 1231 } else { 1232 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1233 sizeof(myea) / sizeof(myea[0]), myea)) { 1234 aprint_error("%s: unable to read Ethernet address\n", 1235 sc->sc_dev.dv_xname); 1236 return; 1237 } 1238 enaddr[0] = myea[0] & 0xff; 1239 enaddr[1] = myea[0] >> 8; 1240 enaddr[2] = myea[1] & 0xff; 1241 enaddr[3] = myea[1] >> 8; 1242 enaddr[4] = myea[2] & 0xff; 1243 enaddr[5] = myea[2] >> 8; 1244 } 1245 1246 /* 1247 * Toggle the LSB of the MAC address on the second port 1248 * of the dual port controller. 1249 */ 1250 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3 1251 || sc->sc_type == WM_T_82571 || sc->sc_type == WM_T_80003) { 1252 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1253 enaddr[5] ^= 1; 1254 } 1255 1256 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1257 ether_sprintf(enaddr)); 1258 1259 /* 1260 * Read the config info from the EEPROM, and set up various 1261 * bits in the control registers based on their contents. 1262 */ 1263 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1264 "i82543-cfg1"); 1265 if (pn != NULL) { 1266 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1267 cfg1 = (uint16_t) prop_number_integer_value(pn); 1268 } else { 1269 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1270 aprint_error("%s: unable to read CFG1\n", 1271 sc->sc_dev.dv_xname); 1272 return; 1273 } 1274 } 1275 1276 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1277 "i82543-cfg2"); 1278 if (pn != NULL) { 1279 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1280 cfg2 = (uint16_t) prop_number_integer_value(pn); 1281 } else { 1282 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1283 aprint_error("%s: unable to read CFG2\n", 1284 sc->sc_dev.dv_xname); 1285 return; 1286 } 1287 } 1288 1289 if (sc->sc_type >= WM_T_82544) { 1290 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1291 "i82543-swdpin"); 1292 if (pn != NULL) { 1293 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1294 swdpin = (uint16_t) prop_number_integer_value(pn); 1295 } else { 1296 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1297 aprint_error("%s: unable to read SWDPIN\n", 1298 sc->sc_dev.dv_xname); 1299 return; 1300 } 1301 } 1302 } 1303 1304 if (cfg1 & EEPROM_CFG1_ILOS) 1305 sc->sc_ctrl |= CTRL_ILOS; 1306 if (sc->sc_type >= WM_T_82544) { 1307 sc->sc_ctrl |= 1308 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1309 CTRL_SWDPIO_SHIFT; 1310 sc->sc_ctrl |= 1311 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1312 CTRL_SWDPINS_SHIFT; 1313 } else { 1314 sc->sc_ctrl |= 1315 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1316 CTRL_SWDPIO_SHIFT; 1317 } 1318 1319 #if 0 1320 if (sc->sc_type >= WM_T_82544) { 1321 if (cfg1 & EEPROM_CFG1_IPS0) 1322 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1323 if (cfg1 & EEPROM_CFG1_IPS1) 1324 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1325 sc->sc_ctrl_ext |= 1326 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1327 CTRL_EXT_SWDPIO_SHIFT; 1328 sc->sc_ctrl_ext |= 1329 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1330 CTRL_EXT_SWDPINS_SHIFT; 1331 } else { 1332 sc->sc_ctrl_ext |= 1333 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1334 CTRL_EXT_SWDPIO_SHIFT; 1335 } 1336 #endif 1337 1338 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1339 #if 0 1340 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1341 #endif 1342 1343 /* 1344 * Set up some register offsets that are different between 1345 * the i82542 and the i82543 and later chips. 1346 */ 1347 if (sc->sc_type < WM_T_82543) { 1348 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1349 sc->sc_tdt_reg = WMREG_OLD_TDT; 1350 } else { 1351 sc->sc_rdt_reg = WMREG_RDT; 1352 sc->sc_tdt_reg = WMREG_TDT; 1353 } 1354 1355 /* 1356 * Determine if we're TBI or GMII mode, and initialize the 1357 * media structures accordingly. 1358 */ 1359 if (sc->sc_type < WM_T_82543 || 1360 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1361 if (wmp->wmp_flags & WMP_F_1000T) 1362 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1363 "product!\n", sc->sc_dev.dv_xname); 1364 wm_tbi_mediainit(sc); 1365 } else { 1366 if (wmp->wmp_flags & WMP_F_1000X) 1367 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1368 "product!\n", sc->sc_dev.dv_xname); 1369 wm_gmii_mediainit(sc); 1370 } 1371 1372 ifp = &sc->sc_ethercom.ec_if; 1373 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1374 ifp->if_softc = sc; 1375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1376 ifp->if_ioctl = wm_ioctl; 1377 ifp->if_start = wm_start; 1378 ifp->if_watchdog = wm_watchdog; 1379 ifp->if_init = wm_init; 1380 ifp->if_stop = wm_stop; 1381 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1382 IFQ_SET_READY(&ifp->if_snd); 1383 1384 if (sc->sc_type != WM_T_82573) 1385 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1386 1387 /* 1388 * If we're a i82543 or greater, we can support VLANs. 1389 */ 1390 if (sc->sc_type >= WM_T_82543) 1391 sc->sc_ethercom.ec_capabilities |= 1392 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1393 1394 /* 1395 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1396 * on i82543 and later. 1397 */ 1398 if (sc->sc_type >= WM_T_82543) 1399 ifp->if_capabilities |= 1400 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1401 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1402 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1403 IFCAP_CSUM_TCPv6_Tx | 1404 IFCAP_CSUM_UDPv6_Tx; 1405 1406 /* 1407 * If we're a i82544 or greater (except i82547), we can do 1408 * TCP segmentation offload. 1409 */ 1410 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) 1411 ifp->if_capabilities |= IFCAP_TSOv4; 1412 1413 /* 1414 * Attach the interface. 1415 */ 1416 if_attach(ifp); 1417 ether_ifattach(ifp, enaddr); 1418 #if NRND > 0 1419 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1420 RND_TYPE_NET, 0); 1421 #endif 1422 1423 #ifdef WM_EVENT_COUNTERS 1424 /* Attach event counters. */ 1425 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1426 NULL, sc->sc_dev.dv_xname, "txsstall"); 1427 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1428 NULL, sc->sc_dev.dv_xname, "txdstall"); 1429 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1430 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1431 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1432 NULL, sc->sc_dev.dv_xname, "txdw"); 1433 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1434 NULL, sc->sc_dev.dv_xname, "txqe"); 1435 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1436 NULL, sc->sc_dev.dv_xname, "rxintr"); 1437 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1438 NULL, sc->sc_dev.dv_xname, "linkintr"); 1439 1440 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1441 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1442 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1443 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1444 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1445 NULL, sc->sc_dev.dv_xname, "txipsum"); 1446 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1447 NULL, sc->sc_dev.dv_xname, "txtusum"); 1448 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1449 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1450 1451 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1452 NULL, sc->sc_dev.dv_xname, "txtso"); 1453 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1454 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1455 1456 for (i = 0; i < WM_NTXSEGS; i++) { 1457 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1458 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1459 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1460 } 1461 1462 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1463 NULL, sc->sc_dev.dv_xname, "txdrop"); 1464 1465 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1466 NULL, sc->sc_dev.dv_xname, "tu"); 1467 1468 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1469 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1470 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1471 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1472 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1473 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1474 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1475 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1476 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1477 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1478 #endif /* WM_EVENT_COUNTERS */ 1479 1480 /* 1481 * Make sure the interface is shutdown during reboot. 1482 */ 1483 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1484 if (sc->sc_sdhook == NULL) 1485 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1486 sc->sc_dev.dv_xname); 1487 1488 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 1489 wm_powerhook, sc); 1490 if (sc->sc_powerhook == NULL) 1491 aprint_error("%s: can't establish powerhook\n", 1492 sc->sc_dev.dv_xname); 1493 return; 1494 1495 /* 1496 * Free any resources we've allocated during the failed attach 1497 * attempt. Do this in reverse order and fall through. 1498 */ 1499 fail_5: 1500 for (i = 0; i < WM_NRXDESC; i++) { 1501 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1502 bus_dmamap_destroy(sc->sc_dmat, 1503 sc->sc_rxsoft[i].rxs_dmamap); 1504 } 1505 fail_4: 1506 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1507 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1508 bus_dmamap_destroy(sc->sc_dmat, 1509 sc->sc_txsoft[i].txs_dmamap); 1510 } 1511 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1512 fail_3: 1513 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1514 fail_2: 1515 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1516 cdata_size); 1517 fail_1: 1518 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1519 fail_0: 1520 return; 1521 } 1522 1523 /* 1524 * wm_shutdown: 1525 * 1526 * Make sure the interface is stopped at reboot time. 1527 */ 1528 static void 1529 wm_shutdown(void *arg) 1530 { 1531 struct wm_softc *sc = arg; 1532 1533 wm_stop(&sc->sc_ethercom.ec_if, 1); 1534 } 1535 1536 static void 1537 wm_powerhook(int why, void *arg) 1538 { 1539 struct wm_softc *sc = arg; 1540 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1541 pci_chipset_tag_t pc = sc->sc_pc; 1542 pcitag_t tag = sc->sc_pcitag; 1543 1544 switch (why) { 1545 case PWR_SOFTSUSPEND: 1546 wm_shutdown(sc); 1547 break; 1548 case PWR_SOFTRESUME: 1549 ifp->if_flags &= ~IFF_RUNNING; 1550 wm_init(ifp); 1551 if (ifp->if_flags & IFF_RUNNING) 1552 wm_start(ifp); 1553 break; 1554 case PWR_SUSPEND: 1555 pci_conf_capture(pc, tag, &sc->sc_pciconf); 1556 break; 1557 case PWR_RESUME: 1558 pci_conf_restore(pc, tag, &sc->sc_pciconf); 1559 break; 1560 } 1561 1562 return; 1563 } 1564 1565 /* 1566 * wm_tx_offload: 1567 * 1568 * Set up TCP/IP checksumming parameters for the 1569 * specified packet. 1570 */ 1571 static int 1572 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1573 uint8_t *fieldsp) 1574 { 1575 struct mbuf *m0 = txs->txs_mbuf; 1576 struct livengood_tcpip_ctxdesc *t; 1577 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1578 struct ether_header *eh; 1579 int offset, iphl; 1580 uint8_t fields; 1581 1582 /* 1583 * XXX It would be nice if the mbuf pkthdr had offset 1584 * fields for the protocol headers. 1585 */ 1586 1587 eh = mtod(m0, struct ether_header *); 1588 switch (htons(eh->ether_type)) { 1589 case ETHERTYPE_IP: 1590 case ETHERTYPE_IPV6: 1591 offset = ETHER_HDR_LEN; 1592 break; 1593 1594 case ETHERTYPE_VLAN: 1595 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1596 break; 1597 1598 default: 1599 /* 1600 * Don't support this protocol or encapsulation. 1601 */ 1602 *fieldsp = 0; 1603 *cmdp = 0; 1604 return (0); 1605 } 1606 1607 if ((m0->m_pkthdr.csum_flags & 1608 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1609 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1610 } else { 1611 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1612 } 1613 1614 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1615 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1616 seg = 0; 1617 fields = 0; 1618 1619 if (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) { 1620 int hlen = offset + iphl; 1621 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1622 if (__predict_false(m0->m_len < 1623 (hlen + sizeof(struct tcphdr)))) { 1624 /* 1625 * TCP/IP headers are not in the first mbuf; we need 1626 * to do this the slow and painful way. Let's just 1627 * hope this doesn't happen very often. 1628 */ 1629 struct ip ip; 1630 struct tcphdr th; 1631 1632 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1633 1634 m_copydata(m0, offset, sizeof(ip), &ip); 1635 m_copydata(m0, hlen, sizeof(th), &th); 1636 1637 ip.ip_len = 0; 1638 1639 m_copyback(m0, offset + offsetof(struct ip, ip_len), 1640 sizeof(ip.ip_len), &ip.ip_len); 1641 1642 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1643 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1644 1645 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1646 sizeof(th.th_sum), &th.th_sum); 1647 1648 hlen += th.th_off << 2; 1649 } else { 1650 /* 1651 * TCP/IP headers are in the first mbuf; we can do 1652 * this the easy way. 1653 */ 1654 struct ip *ip = 1655 (struct ip *) (mtod(m0, caddr_t) + offset); 1656 struct tcphdr *th = 1657 (struct tcphdr *) (mtod(m0, caddr_t) + hlen); 1658 1659 ip->ip_len = 0; 1660 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1661 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1662 1663 hlen += th->th_off << 2; 1664 } 1665 1666 cmd |= WTX_TCPIP_CMD_TSE; 1667 cmdlen |= WTX_TCPIP_CMD_TSE | WTX_TCPIP_CMD_IP | 1668 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1669 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1670 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1671 } 1672 1673 /* 1674 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1675 * offload feature, if we load the context descriptor, we 1676 * MUST provide valid values for IPCSS and TUCSS fields. 1677 */ 1678 1679 ipcs = WTX_TCPIP_IPCSS(offset) | 1680 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1681 WTX_TCPIP_IPCSE(offset + iphl - 1); 1682 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1683 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1684 fields |= WTX_IXSM; 1685 } 1686 1687 offset += iphl; 1688 1689 if (m0->m_pkthdr.csum_flags & 1690 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1691 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1692 fields |= WTX_TXSM; 1693 tucs = WTX_TCPIP_TUCSS(offset) | 1694 WTX_TCPIP_TUCSO(offset + 1695 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1696 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1697 } else if ((m0->m_pkthdr.csum_flags & 1698 (M_CSUM_TCPv6|M_CSUM_UDPv6)) != 0) { 1699 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1700 fields |= WTX_TXSM; 1701 tucs = WTX_TCPIP_TUCSS(offset) | 1702 WTX_TCPIP_TUCSO(offset + 1703 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1704 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1705 } else { 1706 /* Just initialize it to a valid TCP context. */ 1707 tucs = WTX_TCPIP_TUCSS(offset) | 1708 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1709 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1710 } 1711 1712 /* Fill in the context descriptor. */ 1713 t = (struct livengood_tcpip_ctxdesc *) 1714 &sc->sc_txdescs[sc->sc_txnext]; 1715 t->tcpip_ipcs = htole32(ipcs); 1716 t->tcpip_tucs = htole32(tucs); 1717 t->tcpip_cmdlen = htole32(cmdlen); 1718 t->tcpip_seg = htole32(seg); 1719 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1720 1721 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1722 txs->txs_ndesc++; 1723 1724 *cmdp = cmd; 1725 *fieldsp = fields; 1726 1727 return (0); 1728 } 1729 1730 static void 1731 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1732 { 1733 struct mbuf *m; 1734 int i; 1735 1736 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1737 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1738 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1739 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1740 m->m_data, m->m_len, m->m_flags); 1741 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1742 i, i == 1 ? "" : "s"); 1743 } 1744 1745 /* 1746 * wm_82547_txfifo_stall: 1747 * 1748 * Callout used to wait for the 82547 Tx FIFO to drain, 1749 * reset the FIFO pointers, and restart packet transmission. 1750 */ 1751 static void 1752 wm_82547_txfifo_stall(void *arg) 1753 { 1754 struct wm_softc *sc = arg; 1755 int s; 1756 1757 s = splnet(); 1758 1759 if (sc->sc_txfifo_stall) { 1760 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1761 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1762 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1763 /* 1764 * Packets have drained. Stop transmitter, reset 1765 * FIFO pointers, restart transmitter, and kick 1766 * the packet queue. 1767 */ 1768 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1769 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1770 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1771 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1772 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1773 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1774 CSR_WRITE(sc, WMREG_TCTL, tctl); 1775 CSR_WRITE_FLUSH(sc); 1776 1777 sc->sc_txfifo_head = 0; 1778 sc->sc_txfifo_stall = 0; 1779 wm_start(&sc->sc_ethercom.ec_if); 1780 } else { 1781 /* 1782 * Still waiting for packets to drain; try again in 1783 * another tick. 1784 */ 1785 callout_schedule(&sc->sc_txfifo_ch, 1); 1786 } 1787 } 1788 1789 splx(s); 1790 } 1791 1792 /* 1793 * wm_82547_txfifo_bugchk: 1794 * 1795 * Check for bug condition in the 82547 Tx FIFO. We need to 1796 * prevent enqueueing a packet that would wrap around the end 1797 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1798 * 1799 * We do this by checking the amount of space before the end 1800 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1801 * the Tx FIFO, wait for all remaining packets to drain, reset 1802 * the internal FIFO pointers to the beginning, and restart 1803 * transmission on the interface. 1804 */ 1805 #define WM_FIFO_HDR 0x10 1806 #define WM_82547_PAD_LEN 0x3e0 1807 static int 1808 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1809 { 1810 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1811 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1812 1813 /* Just return if already stalled. */ 1814 if (sc->sc_txfifo_stall) 1815 return (1); 1816 1817 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1818 /* Stall only occurs in half-duplex mode. */ 1819 goto send_packet; 1820 } 1821 1822 if (len >= WM_82547_PAD_LEN + space) { 1823 sc->sc_txfifo_stall = 1; 1824 callout_schedule(&sc->sc_txfifo_ch, 1); 1825 return (1); 1826 } 1827 1828 send_packet: 1829 sc->sc_txfifo_head += len; 1830 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1831 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1832 1833 return (0); 1834 } 1835 1836 /* 1837 * wm_start: [ifnet interface function] 1838 * 1839 * Start packet transmission on the interface. 1840 */ 1841 static void 1842 wm_start(struct ifnet *ifp) 1843 { 1844 struct wm_softc *sc = ifp->if_softc; 1845 struct mbuf *m0; 1846 #if 0 /* XXXJRT */ 1847 struct m_tag *mtag; 1848 #endif 1849 struct wm_txsoft *txs; 1850 bus_dmamap_t dmamap; 1851 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 1852 bus_addr_t curaddr; 1853 bus_size_t seglen, curlen; 1854 uint32_t cksumcmd; 1855 uint8_t cksumfields; 1856 1857 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1858 return; 1859 1860 /* 1861 * Remember the previous number of free descriptors. 1862 */ 1863 ofree = sc->sc_txfree; 1864 1865 /* 1866 * Loop through the send queue, setting up transmit descriptors 1867 * until we drain the queue, or use up all available transmit 1868 * descriptors. 1869 */ 1870 for (;;) { 1871 /* Grab a packet off the queue. */ 1872 IFQ_POLL(&ifp->if_snd, m0); 1873 if (m0 == NULL) 1874 break; 1875 1876 DPRINTF(WM_DEBUG_TX, 1877 ("%s: TX: have packet to transmit: %p\n", 1878 sc->sc_dev.dv_xname, m0)); 1879 1880 /* Get a work queue entry. */ 1881 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1882 wm_txintr(sc); 1883 if (sc->sc_txsfree == 0) { 1884 DPRINTF(WM_DEBUG_TX, 1885 ("%s: TX: no free job descriptors\n", 1886 sc->sc_dev.dv_xname)); 1887 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1888 break; 1889 } 1890 } 1891 1892 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1893 dmamap = txs->txs_dmamap; 1894 1895 use_tso = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1896 1897 /* 1898 * So says the Linux driver: 1899 * The controller does a simple calculation to make sure 1900 * there is enough room in the FIFO before initiating the 1901 * DMA for each buffer. The calc is: 1902 * 4 = ceil(buffer len / MSS) 1903 * To make sure we don't overrun the FIFO, adjust the max 1904 * buffer len if the MSS drops. 1905 */ 1906 dmamap->dm_maxsegsz = 1907 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 1908 ? m0->m_pkthdr.segsz << 2 1909 : WTX_MAX_LEN; 1910 1911 /* 1912 * Load the DMA map. If this fails, the packet either 1913 * didn't fit in the allotted number of segments, or we 1914 * were short on resources. For the too-many-segments 1915 * case, we simply report an error and drop the packet, 1916 * since we can't sanely copy a jumbo packet to a single 1917 * buffer. 1918 */ 1919 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1920 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1921 if (error) { 1922 if (error == EFBIG) { 1923 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1924 log(LOG_ERR, "%s: Tx packet consumes too many " 1925 "DMA segments, dropping...\n", 1926 sc->sc_dev.dv_xname); 1927 IFQ_DEQUEUE(&ifp->if_snd, m0); 1928 wm_dump_mbuf_chain(sc, m0); 1929 m_freem(m0); 1930 continue; 1931 } 1932 /* 1933 * Short on resources, just stop for now. 1934 */ 1935 DPRINTF(WM_DEBUG_TX, 1936 ("%s: TX: dmamap load failed: %d\n", 1937 sc->sc_dev.dv_xname, error)); 1938 break; 1939 } 1940 1941 segs_needed = dmamap->dm_nsegs; 1942 if (use_tso) { 1943 /* For sentinel descriptor; see below. */ 1944 segs_needed++; 1945 } 1946 1947 /* 1948 * Ensure we have enough descriptors free to describe 1949 * the packet. Note, we always reserve one descriptor 1950 * at the end of the ring due to the semantics of the 1951 * TDT register, plus one more in the event we need 1952 * to load offload context. 1953 */ 1954 if (segs_needed > sc->sc_txfree - 2) { 1955 /* 1956 * Not enough free descriptors to transmit this 1957 * packet. We haven't committed anything yet, 1958 * so just unload the DMA map, put the packet 1959 * pack on the queue, and punt. Notify the upper 1960 * layer that there are no more slots left. 1961 */ 1962 DPRINTF(WM_DEBUG_TX, 1963 ("%s: TX: need %d (%d) descriptors, have %d\n", 1964 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1965 sc->sc_txfree - 1)); 1966 ifp->if_flags |= IFF_OACTIVE; 1967 bus_dmamap_unload(sc->sc_dmat, dmamap); 1968 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1969 break; 1970 } 1971 1972 /* 1973 * Check for 82547 Tx FIFO bug. We need to do this 1974 * once we know we can transmit the packet, since we 1975 * do some internal FIFO space accounting here. 1976 */ 1977 if (sc->sc_type == WM_T_82547 && 1978 wm_82547_txfifo_bugchk(sc, m0)) { 1979 DPRINTF(WM_DEBUG_TX, 1980 ("%s: TX: 82547 Tx FIFO bug detected\n", 1981 sc->sc_dev.dv_xname)); 1982 ifp->if_flags |= IFF_OACTIVE; 1983 bus_dmamap_unload(sc->sc_dmat, dmamap); 1984 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1985 break; 1986 } 1987 1988 IFQ_DEQUEUE(&ifp->if_snd, m0); 1989 1990 /* 1991 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1992 */ 1993 1994 DPRINTF(WM_DEBUG_TX, 1995 ("%s: TX: packet has %d (%d) DMA segments\n", 1996 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1997 1998 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1999 2000 /* 2001 * Store a pointer to the packet so that we can free it 2002 * later. 2003 * 2004 * Initially, we consider the number of descriptors the 2005 * packet uses the number of DMA segments. This may be 2006 * incremented by 1 if we do checksum offload (a descriptor 2007 * is used to set the checksum context). 2008 */ 2009 txs->txs_mbuf = m0; 2010 txs->txs_firstdesc = sc->sc_txnext; 2011 txs->txs_ndesc = segs_needed; 2012 2013 /* Set up offload parameters for this packet. */ 2014 if (m0->m_pkthdr.csum_flags & 2015 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 2016 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 2017 if (wm_tx_offload(sc, txs, &cksumcmd, 2018 &cksumfields) != 0) { 2019 /* Error message already displayed. */ 2020 bus_dmamap_unload(sc->sc_dmat, dmamap); 2021 continue; 2022 } 2023 } else { 2024 cksumcmd = 0; 2025 cksumfields = 0; 2026 } 2027 2028 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 2029 2030 /* Sync the DMA map. */ 2031 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2032 BUS_DMASYNC_PREWRITE); 2033 2034 /* 2035 * Initialize the transmit descriptor. 2036 */ 2037 for (nexttx = sc->sc_txnext, seg = 0; 2038 seg < dmamap->dm_nsegs; seg++) { 2039 for (seglen = dmamap->dm_segs[seg].ds_len, 2040 curaddr = dmamap->dm_segs[seg].ds_addr; 2041 seglen != 0; 2042 curaddr += curlen, seglen -= curlen, 2043 nexttx = WM_NEXTTX(sc, nexttx)) { 2044 curlen = seglen; 2045 2046 /* 2047 * So says the Linux driver: 2048 * Work around for premature descriptor 2049 * write-backs in TSO mode. Append a 2050 * 4-byte sentinel descriptor. 2051 */ 2052 if (use_tso && 2053 seg == dmamap->dm_nsegs - 1 && 2054 curlen > 8) 2055 curlen -= 4; 2056 2057 wm_set_dma_addr( 2058 &sc->sc_txdescs[nexttx].wtx_addr, 2059 curaddr); 2060 sc->sc_txdescs[nexttx].wtx_cmdlen = 2061 htole32(cksumcmd | curlen); 2062 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 2063 0; 2064 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 2065 cksumfields; 2066 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 2067 lasttx = nexttx; 2068 2069 DPRINTF(WM_DEBUG_TX, 2070 ("%s: TX: desc %d: low 0x%08lx, " 2071 "len 0x%04x\n", 2072 sc->sc_dev.dv_xname, nexttx, 2073 curaddr & 0xffffffffUL, (unsigned)curlen)); 2074 } 2075 } 2076 2077 KASSERT(lasttx != -1); 2078 2079 /* 2080 * Set up the command byte on the last descriptor of 2081 * the packet. If we're in the interrupt delay window, 2082 * delay the interrupt. 2083 */ 2084 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2085 htole32(WTX_CMD_EOP | WTX_CMD_RS); 2086 2087 #if 0 /* XXXJRT */ 2088 /* 2089 * If VLANs are enabled and the packet has a VLAN tag, set 2090 * up the descriptor to encapsulate the packet for us. 2091 * 2092 * This is only valid on the last descriptor of the packet. 2093 */ 2094 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 2095 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2096 htole32(WTX_CMD_VLE); 2097 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 2098 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 2099 } 2100 #endif /* XXXJRT */ 2101 2102 txs->txs_lastdesc = lasttx; 2103 2104 DPRINTF(WM_DEBUG_TX, 2105 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 2106 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 2107 2108 /* Sync the descriptors we're using. */ 2109 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 2110 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2111 2112 /* Give the packet to the chip. */ 2113 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 2114 2115 DPRINTF(WM_DEBUG_TX, 2116 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 2117 2118 DPRINTF(WM_DEBUG_TX, 2119 ("%s: TX: finished transmitting packet, job %d\n", 2120 sc->sc_dev.dv_xname, sc->sc_txsnext)); 2121 2122 /* Advance the tx pointer. */ 2123 sc->sc_txfree -= txs->txs_ndesc; 2124 sc->sc_txnext = nexttx; 2125 2126 sc->sc_txsfree--; 2127 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 2128 2129 #if NBPFILTER > 0 2130 /* Pass the packet to any BPF listeners. */ 2131 if (ifp->if_bpf) 2132 bpf_mtap(ifp->if_bpf, m0); 2133 #endif /* NBPFILTER > 0 */ 2134 } 2135 2136 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 2137 /* No more slots; notify upper layer. */ 2138 ifp->if_flags |= IFF_OACTIVE; 2139 } 2140 2141 if (sc->sc_txfree != ofree) { 2142 /* Set a watchdog timer in case the chip flakes out. */ 2143 ifp->if_timer = 5; 2144 } 2145 } 2146 2147 /* 2148 * wm_watchdog: [ifnet interface function] 2149 * 2150 * Watchdog timer handler. 2151 */ 2152 static void 2153 wm_watchdog(struct ifnet *ifp) 2154 { 2155 struct wm_softc *sc = ifp->if_softc; 2156 2157 /* 2158 * Since we're using delayed interrupts, sweep up 2159 * before we report an error. 2160 */ 2161 wm_txintr(sc); 2162 2163 if (sc->sc_txfree != WM_NTXDESC(sc)) { 2164 log(LOG_ERR, 2165 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 2166 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 2167 sc->sc_txnext); 2168 ifp->if_oerrors++; 2169 2170 /* Reset the interface. */ 2171 (void) wm_init(ifp); 2172 } 2173 2174 /* Try to get more packets going. */ 2175 wm_start(ifp); 2176 } 2177 2178 /* 2179 * wm_ioctl: [ifnet interface function] 2180 * 2181 * Handle control requests from the operator. 2182 */ 2183 static int 2184 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2185 { 2186 struct wm_softc *sc = ifp->if_softc; 2187 struct ifreq *ifr = (struct ifreq *) data; 2188 int s, error; 2189 2190 s = splnet(); 2191 2192 switch (cmd) { 2193 case SIOCSIFMEDIA: 2194 case SIOCGIFMEDIA: 2195 /* Flow control requires full-duplex mode. */ 2196 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2197 (ifr->ifr_media & IFM_FDX) == 0) 2198 ifr->ifr_media &= ~IFM_ETH_FMASK; 2199 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2200 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2201 /* We can do both TXPAUSE and RXPAUSE. */ 2202 ifr->ifr_media |= 2203 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2204 } 2205 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2206 } 2207 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2208 break; 2209 default: 2210 error = ether_ioctl(ifp, cmd, data); 2211 if (error == ENETRESET) { 2212 /* 2213 * Multicast list has changed; set the hardware filter 2214 * accordingly. 2215 */ 2216 if (ifp->if_flags & IFF_RUNNING) 2217 wm_set_filter(sc); 2218 error = 0; 2219 } 2220 break; 2221 } 2222 2223 /* Try to get more packets going. */ 2224 wm_start(ifp); 2225 2226 splx(s); 2227 return (error); 2228 } 2229 2230 /* 2231 * wm_intr: 2232 * 2233 * Interrupt service routine. 2234 */ 2235 static int 2236 wm_intr(void *arg) 2237 { 2238 struct wm_softc *sc = arg; 2239 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2240 uint32_t icr; 2241 int handled = 0; 2242 2243 while (1 /* CONSTCOND */) { 2244 icr = CSR_READ(sc, WMREG_ICR); 2245 if ((icr & sc->sc_icr) == 0) 2246 break; 2247 #if 0 /*NRND > 0*/ 2248 if (RND_ENABLED(&sc->rnd_source)) 2249 rnd_add_uint32(&sc->rnd_source, icr); 2250 #endif 2251 2252 handled = 1; 2253 2254 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2255 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2256 DPRINTF(WM_DEBUG_RX, 2257 ("%s: RX: got Rx intr 0x%08x\n", 2258 sc->sc_dev.dv_xname, 2259 icr & (ICR_RXDMT0|ICR_RXT0))); 2260 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2261 } 2262 #endif 2263 wm_rxintr(sc); 2264 2265 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2266 if (icr & ICR_TXDW) { 2267 DPRINTF(WM_DEBUG_TX, 2268 ("%s: TX: got TXDW interrupt\n", 2269 sc->sc_dev.dv_xname)); 2270 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2271 } 2272 #endif 2273 wm_txintr(sc); 2274 2275 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2276 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2277 wm_linkintr(sc, icr); 2278 } 2279 2280 if (icr & ICR_RXO) { 2281 ifp->if_ierrors++; 2282 #if defined(WM_DEBUG) 2283 log(LOG_WARNING, "%s: Receive overrun\n", 2284 sc->sc_dev.dv_xname); 2285 #endif /* defined(WM_DEBUG) */ 2286 } 2287 } 2288 2289 if (handled) { 2290 /* Try to get more packets going. */ 2291 wm_start(ifp); 2292 } 2293 2294 return (handled); 2295 } 2296 2297 /* 2298 * wm_txintr: 2299 * 2300 * Helper; handle transmit interrupts. 2301 */ 2302 static void 2303 wm_txintr(struct wm_softc *sc) 2304 { 2305 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2306 struct wm_txsoft *txs; 2307 uint8_t status; 2308 int i; 2309 2310 ifp->if_flags &= ~IFF_OACTIVE; 2311 2312 /* 2313 * Go through the Tx list and free mbufs for those 2314 * frames which have been transmitted. 2315 */ 2316 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2317 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2318 txs = &sc->sc_txsoft[i]; 2319 2320 DPRINTF(WM_DEBUG_TX, 2321 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2322 2323 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2324 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2325 2326 status = 2327 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2328 if ((status & WTX_ST_DD) == 0) { 2329 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2330 BUS_DMASYNC_PREREAD); 2331 break; 2332 } 2333 2334 DPRINTF(WM_DEBUG_TX, 2335 ("%s: TX: job %d done: descs %d..%d\n", 2336 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2337 txs->txs_lastdesc)); 2338 2339 /* 2340 * XXX We should probably be using the statistics 2341 * XXX registers, but I don't know if they exist 2342 * XXX on chips before the i82544. 2343 */ 2344 2345 #ifdef WM_EVENT_COUNTERS 2346 if (status & WTX_ST_TU) 2347 WM_EVCNT_INCR(&sc->sc_ev_tu); 2348 #endif /* WM_EVENT_COUNTERS */ 2349 2350 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2351 ifp->if_oerrors++; 2352 if (status & WTX_ST_LC) 2353 log(LOG_WARNING, "%s: late collision\n", 2354 sc->sc_dev.dv_xname); 2355 else if (status & WTX_ST_EC) { 2356 ifp->if_collisions += 16; 2357 log(LOG_WARNING, "%s: excessive collisions\n", 2358 sc->sc_dev.dv_xname); 2359 } 2360 } else 2361 ifp->if_opackets++; 2362 2363 sc->sc_txfree += txs->txs_ndesc; 2364 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2365 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2366 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2367 m_freem(txs->txs_mbuf); 2368 txs->txs_mbuf = NULL; 2369 } 2370 2371 /* Update the dirty transmit buffer pointer. */ 2372 sc->sc_txsdirty = i; 2373 DPRINTF(WM_DEBUG_TX, 2374 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2375 2376 /* 2377 * If there are no more pending transmissions, cancel the watchdog 2378 * timer. 2379 */ 2380 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2381 ifp->if_timer = 0; 2382 } 2383 2384 /* 2385 * wm_rxintr: 2386 * 2387 * Helper; handle receive interrupts. 2388 */ 2389 static void 2390 wm_rxintr(struct wm_softc *sc) 2391 { 2392 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2393 struct wm_rxsoft *rxs; 2394 struct mbuf *m; 2395 int i, len; 2396 uint8_t status, errors; 2397 2398 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2399 rxs = &sc->sc_rxsoft[i]; 2400 2401 DPRINTF(WM_DEBUG_RX, 2402 ("%s: RX: checking descriptor %d\n", 2403 sc->sc_dev.dv_xname, i)); 2404 2405 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2406 2407 status = sc->sc_rxdescs[i].wrx_status; 2408 errors = sc->sc_rxdescs[i].wrx_errors; 2409 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2410 2411 if ((status & WRX_ST_DD) == 0) { 2412 /* 2413 * We have processed all of the receive descriptors. 2414 */ 2415 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2416 break; 2417 } 2418 2419 if (__predict_false(sc->sc_rxdiscard)) { 2420 DPRINTF(WM_DEBUG_RX, 2421 ("%s: RX: discarding contents of descriptor %d\n", 2422 sc->sc_dev.dv_xname, i)); 2423 WM_INIT_RXDESC(sc, i); 2424 if (status & WRX_ST_EOP) { 2425 /* Reset our state. */ 2426 DPRINTF(WM_DEBUG_RX, 2427 ("%s: RX: resetting rxdiscard -> 0\n", 2428 sc->sc_dev.dv_xname)); 2429 sc->sc_rxdiscard = 0; 2430 } 2431 continue; 2432 } 2433 2434 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2435 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2436 2437 m = rxs->rxs_mbuf; 2438 2439 /* 2440 * Add a new receive buffer to the ring, unless of 2441 * course the length is zero. Treat the latter as a 2442 * failed mapping. 2443 */ 2444 if ((len == 0) || (wm_add_rxbuf(sc, i) != 0)) { 2445 /* 2446 * Failed, throw away what we've done so 2447 * far, and discard the rest of the packet. 2448 */ 2449 ifp->if_ierrors++; 2450 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2451 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2452 WM_INIT_RXDESC(sc, i); 2453 if ((status & WRX_ST_EOP) == 0) 2454 sc->sc_rxdiscard = 1; 2455 if (sc->sc_rxhead != NULL) 2456 m_freem(sc->sc_rxhead); 2457 WM_RXCHAIN_RESET(sc); 2458 DPRINTF(WM_DEBUG_RX, 2459 ("%s: RX: Rx buffer allocation failed, " 2460 "dropping packet%s\n", sc->sc_dev.dv_xname, 2461 sc->sc_rxdiscard ? " (discard)" : "")); 2462 continue; 2463 } 2464 2465 WM_RXCHAIN_LINK(sc, m); 2466 2467 m->m_len = len; 2468 2469 DPRINTF(WM_DEBUG_RX, 2470 ("%s: RX: buffer at %p len %d\n", 2471 sc->sc_dev.dv_xname, m->m_data, len)); 2472 2473 /* 2474 * If this is not the end of the packet, keep 2475 * looking. 2476 */ 2477 if ((status & WRX_ST_EOP) == 0) { 2478 sc->sc_rxlen += len; 2479 DPRINTF(WM_DEBUG_RX, 2480 ("%s: RX: not yet EOP, rxlen -> %d\n", 2481 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2482 continue; 2483 } 2484 2485 /* 2486 * Okay, we have the entire packet now. The chip is 2487 * configured to include the FCS (not all chips can 2488 * be configured to strip it), so we need to trim it. 2489 */ 2490 m->m_len -= ETHER_CRC_LEN; 2491 2492 *sc->sc_rxtailp = NULL; 2493 len = m->m_len + sc->sc_rxlen; 2494 m = sc->sc_rxhead; 2495 2496 WM_RXCHAIN_RESET(sc); 2497 2498 DPRINTF(WM_DEBUG_RX, 2499 ("%s: RX: have entire packet, len -> %d\n", 2500 sc->sc_dev.dv_xname, len)); 2501 2502 /* 2503 * If an error occurred, update stats and drop the packet. 2504 */ 2505 if (errors & 2506 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2507 ifp->if_ierrors++; 2508 if (errors & WRX_ER_SE) 2509 log(LOG_WARNING, "%s: symbol error\n", 2510 sc->sc_dev.dv_xname); 2511 else if (errors & WRX_ER_SEQ) 2512 log(LOG_WARNING, "%s: receive sequence error\n", 2513 sc->sc_dev.dv_xname); 2514 else if (errors & WRX_ER_CE) 2515 log(LOG_WARNING, "%s: CRC error\n", 2516 sc->sc_dev.dv_xname); 2517 m_freem(m); 2518 continue; 2519 } 2520 2521 /* 2522 * No errors. Receive the packet. 2523 */ 2524 m->m_pkthdr.rcvif = ifp; 2525 m->m_pkthdr.len = len; 2526 2527 #if 0 /* XXXJRT */ 2528 /* 2529 * If VLANs are enabled, VLAN packets have been unwrapped 2530 * for us. Associate the tag with the packet. 2531 */ 2532 if ((status & WRX_ST_VP) != 0) { 2533 VLAN_INPUT_TAG(ifp, m, 2534 le16toh(sc->sc_rxdescs[i].wrx_special, 2535 continue); 2536 } 2537 #endif /* XXXJRT */ 2538 2539 /* 2540 * Set up checksum info for this packet. 2541 */ 2542 if ((status & WRX_ST_IXSM) == 0) { 2543 if (status & WRX_ST_IPCS) { 2544 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2545 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2546 if (errors & WRX_ER_IPE) 2547 m->m_pkthdr.csum_flags |= 2548 M_CSUM_IPv4_BAD; 2549 } 2550 if (status & WRX_ST_TCPCS) { 2551 /* 2552 * Note: we don't know if this was TCP or UDP, 2553 * so we just set both bits, and expect the 2554 * upper layers to deal. 2555 */ 2556 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2557 m->m_pkthdr.csum_flags |= 2558 M_CSUM_TCPv4|M_CSUM_UDPv4; 2559 if (errors & WRX_ER_TCPE) 2560 m->m_pkthdr.csum_flags |= 2561 M_CSUM_TCP_UDP_BAD; 2562 } 2563 } 2564 2565 ifp->if_ipackets++; 2566 2567 #if NBPFILTER > 0 2568 /* Pass this up to any BPF listeners. */ 2569 if (ifp->if_bpf) 2570 bpf_mtap(ifp->if_bpf, m); 2571 #endif /* NBPFILTER > 0 */ 2572 2573 /* Pass it on. */ 2574 (*ifp->if_input)(ifp, m); 2575 } 2576 2577 /* Update the receive pointer. */ 2578 sc->sc_rxptr = i; 2579 2580 DPRINTF(WM_DEBUG_RX, 2581 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2582 } 2583 2584 /* 2585 * wm_linkintr: 2586 * 2587 * Helper; handle link interrupts. 2588 */ 2589 static void 2590 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2591 { 2592 uint32_t status; 2593 2594 /* 2595 * If we get a link status interrupt on a 1000BASE-T 2596 * device, just fall into the normal MII tick path. 2597 */ 2598 if (sc->sc_flags & WM_F_HAS_MII) { 2599 if (icr & ICR_LSC) { 2600 DPRINTF(WM_DEBUG_LINK, 2601 ("%s: LINK: LSC -> mii_tick\n", 2602 sc->sc_dev.dv_xname)); 2603 mii_tick(&sc->sc_mii); 2604 } else if (icr & ICR_RXSEQ) { 2605 DPRINTF(WM_DEBUG_LINK, 2606 ("%s: LINK Receive sequence error\n", 2607 sc->sc_dev.dv_xname)); 2608 } 2609 return; 2610 } 2611 2612 /* 2613 * If we are now receiving /C/, check for link again in 2614 * a couple of link clock ticks. 2615 */ 2616 if (icr & ICR_RXCFG) { 2617 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2618 sc->sc_dev.dv_xname)); 2619 sc->sc_tbi_anstate = 2; 2620 } 2621 2622 if (icr & ICR_LSC) { 2623 status = CSR_READ(sc, WMREG_STATUS); 2624 if (status & STATUS_LU) { 2625 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2626 sc->sc_dev.dv_xname, 2627 (status & STATUS_FD) ? "FDX" : "HDX")); 2628 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2629 sc->sc_fcrtl &= ~FCRTL_XONE; 2630 if (status & STATUS_FD) 2631 sc->sc_tctl |= 2632 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2633 else 2634 sc->sc_tctl |= 2635 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2636 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2637 sc->sc_fcrtl |= FCRTL_XONE; 2638 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2639 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2640 WMREG_OLD_FCRTL : WMREG_FCRTL, 2641 sc->sc_fcrtl); 2642 sc->sc_tbi_linkup = 1; 2643 } else { 2644 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2645 sc->sc_dev.dv_xname)); 2646 sc->sc_tbi_linkup = 0; 2647 } 2648 sc->sc_tbi_anstate = 2; 2649 wm_tbi_set_linkled(sc); 2650 } else if (icr & ICR_RXSEQ) { 2651 DPRINTF(WM_DEBUG_LINK, 2652 ("%s: LINK: Receive sequence error\n", 2653 sc->sc_dev.dv_xname)); 2654 } 2655 } 2656 2657 /* 2658 * wm_tick: 2659 * 2660 * One second timer, used to check link status, sweep up 2661 * completed transmit jobs, etc. 2662 */ 2663 static void 2664 wm_tick(void *arg) 2665 { 2666 struct wm_softc *sc = arg; 2667 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2668 int s; 2669 2670 s = splnet(); 2671 2672 if (sc->sc_type >= WM_T_82542_2_1) { 2673 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2674 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2675 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2676 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2677 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2678 } 2679 2680 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 2681 ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); 2682 2683 2684 if (sc->sc_flags & WM_F_HAS_MII) 2685 mii_tick(&sc->sc_mii); 2686 else 2687 wm_tbi_check_link(sc); 2688 2689 splx(s); 2690 2691 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2692 } 2693 2694 /* 2695 * wm_reset: 2696 * 2697 * Reset the i82542 chip. 2698 */ 2699 static void 2700 wm_reset(struct wm_softc *sc) 2701 { 2702 int i; 2703 2704 /* 2705 * Allocate on-chip memory according to the MTU size. 2706 * The Packet Buffer Allocation register must be written 2707 * before the chip is reset. 2708 */ 2709 switch (sc->sc_type) { 2710 case WM_T_82547: 2711 case WM_T_82547_2: 2712 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2713 PBA_22K : PBA_30K; 2714 sc->sc_txfifo_head = 0; 2715 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2716 sc->sc_txfifo_size = 2717 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2718 sc->sc_txfifo_stall = 0; 2719 break; 2720 case WM_T_82571: 2721 case WM_T_82572: 2722 case WM_T_80003: 2723 sc->sc_pba = PBA_32K; 2724 break; 2725 case WM_T_82573: 2726 sc->sc_pba = PBA_12K; 2727 break; 2728 default: 2729 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2730 PBA_40K : PBA_48K; 2731 break; 2732 } 2733 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2734 2735 switch (sc->sc_type) { 2736 case WM_T_82544: 2737 case WM_T_82540: 2738 case WM_T_82545: 2739 case WM_T_82546: 2740 case WM_T_82541: 2741 case WM_T_82541_2: 2742 /* 2743 * On some chipsets, a reset through a memory-mapped write 2744 * cycle can cause the chip to reset before completing the 2745 * write cycle. This causes major headache that can be 2746 * avoided by issuing the reset via indirect register writes 2747 * through I/O space. 2748 * 2749 * So, if we successfully mapped the I/O BAR at attach time, 2750 * use that. Otherwise, try our luck with a memory-mapped 2751 * reset. 2752 */ 2753 if (sc->sc_flags & WM_F_IOH_VALID) 2754 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2755 else 2756 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2757 break; 2758 2759 case WM_T_82545_3: 2760 case WM_T_82546_3: 2761 /* Use the shadow control register on these chips. */ 2762 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2763 break; 2764 2765 default: 2766 /* Everything else can safely use the documented method. */ 2767 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2768 break; 2769 } 2770 delay(10000); 2771 2772 for (i = 0; i < 1000; i++) { 2773 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2774 return; 2775 delay(20); 2776 } 2777 2778 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2779 log(LOG_ERR, "%s: reset failed to complete\n", 2780 sc->sc_dev.dv_xname); 2781 2782 if (sc->sc_type == WM_T_80003) { 2783 /* wait for eeprom to reload */ 2784 for (i = 1000; i > 0; i--) { 2785 if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD) 2786 break; 2787 } 2788 if (i == 0) { 2789 log(LOG_ERR, "%s: auto read from eeprom failed to " 2790 "complete\n", sc->sc_dev.dv_xname); 2791 } 2792 } 2793 } 2794 2795 /* 2796 * wm_init: [ifnet interface function] 2797 * 2798 * Initialize the interface. Must be called at splnet(). 2799 */ 2800 static int 2801 wm_init(struct ifnet *ifp) 2802 { 2803 struct wm_softc *sc = ifp->if_softc; 2804 struct wm_rxsoft *rxs; 2805 int i, error = 0; 2806 uint32_t reg; 2807 2808 /* 2809 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2810 * There is a small but measurable benefit to avoiding the adjusment 2811 * of the descriptor so that the headers are aligned, for normal mtu, 2812 * on such platforms. One possibility is that the DMA itself is 2813 * slightly more efficient if the front of the entire packet (instead 2814 * of the front of the headers) is aligned. 2815 * 2816 * Note we must always set align_tweak to 0 if we are using 2817 * jumbo frames. 2818 */ 2819 #ifdef __NO_STRICT_ALIGNMENT 2820 sc->sc_align_tweak = 0; 2821 #else 2822 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2823 sc->sc_align_tweak = 0; 2824 else 2825 sc->sc_align_tweak = 2; 2826 #endif /* __NO_STRICT_ALIGNMENT */ 2827 2828 /* Cancel any pending I/O. */ 2829 wm_stop(ifp, 0); 2830 2831 /* update statistics before reset */ 2832 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 2833 ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); 2834 2835 /* Reset the chip to a known state. */ 2836 wm_reset(sc); 2837 2838 /* Initialize the transmit descriptor ring. */ 2839 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2840 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2841 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2842 sc->sc_txfree = WM_NTXDESC(sc); 2843 sc->sc_txnext = 0; 2844 2845 if (sc->sc_type < WM_T_82543) { 2846 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2847 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2848 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2849 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2850 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2851 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2852 } else { 2853 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2854 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2855 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2856 CSR_WRITE(sc, WMREG_TDH, 0); 2857 CSR_WRITE(sc, WMREG_TDT, 0); 2858 CSR_WRITE(sc, WMREG_TIDV, 64); 2859 CSR_WRITE(sc, WMREG_TADV, 128); 2860 2861 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2862 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2863 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2864 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2865 } 2866 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2867 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2868 2869 /* Initialize the transmit job descriptors. */ 2870 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2871 sc->sc_txsoft[i].txs_mbuf = NULL; 2872 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2873 sc->sc_txsnext = 0; 2874 sc->sc_txsdirty = 0; 2875 2876 /* 2877 * Initialize the receive descriptor and receive job 2878 * descriptor rings. 2879 */ 2880 if (sc->sc_type < WM_T_82543) { 2881 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2882 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2883 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2884 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2885 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2886 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2887 2888 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2889 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2890 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2891 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2892 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2893 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2894 } else { 2895 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2896 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2897 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2898 CSR_WRITE(sc, WMREG_RDH, 0); 2899 CSR_WRITE(sc, WMREG_RDT, 0); 2900 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 2901 CSR_WRITE(sc, WMREG_RADV, 128); 2902 } 2903 for (i = 0; i < WM_NRXDESC; i++) { 2904 rxs = &sc->sc_rxsoft[i]; 2905 if (rxs->rxs_mbuf == NULL) { 2906 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2907 log(LOG_ERR, "%s: unable to allocate or map rx " 2908 "buffer %d, error = %d\n", 2909 sc->sc_dev.dv_xname, i, error); 2910 /* 2911 * XXX Should attempt to run with fewer receive 2912 * XXX buffers instead of just failing. 2913 */ 2914 wm_rxdrain(sc); 2915 goto out; 2916 } 2917 } else 2918 WM_INIT_RXDESC(sc, i); 2919 } 2920 sc->sc_rxptr = 0; 2921 sc->sc_rxdiscard = 0; 2922 WM_RXCHAIN_RESET(sc); 2923 2924 /* 2925 * Clear out the VLAN table -- we don't use it (yet). 2926 */ 2927 CSR_WRITE(sc, WMREG_VET, 0); 2928 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2929 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2930 2931 /* 2932 * Set up flow-control parameters. 2933 * 2934 * XXX Values could probably stand some tuning. 2935 */ 2936 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2937 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2938 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2939 2940 sc->sc_fcrtl = FCRTL_DFLT; 2941 if (sc->sc_type < WM_T_82543) { 2942 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2943 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2944 } else { 2945 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2946 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2947 } 2948 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2949 2950 #if 0 /* XXXJRT */ 2951 /* Deal with VLAN enables. */ 2952 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2953 sc->sc_ctrl |= CTRL_VME; 2954 else 2955 #endif /* XXXJRT */ 2956 sc->sc_ctrl &= ~CTRL_VME; 2957 2958 /* Write the control registers. */ 2959 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2960 if (sc->sc_type >= WM_T_80003 && (sc->sc_flags & WM_F_HAS_MII)) { 2961 int val; 2962 val = CSR_READ(sc, WMREG_CTRL_EXT); 2963 val &= ~CTRL_EXT_LINK_MODE_MASK; 2964 CSR_WRITE(sc, WMREG_CTRL_EXT, val); 2965 2966 /* Bypass RX and TX FIFO's */ 2967 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL, 2968 KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2969 KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2970 2971 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL, 2972 KUMCTRLSTA_INB_CTRL_DIS_PADDING | 2973 KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT); 2974 /* 2975 * Set the mac to wait the maximum time between each 2976 * iteration and increase the max iterations when 2977 * polling the phy; this fixes erroneous timeouts at 10Mbps. 2978 */ 2979 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS, 0xFFFF); 2980 val = wm_kmrn_i80003_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM); 2981 val |= 0x3F; 2982 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_INB_PARAM, val); 2983 } 2984 #if 0 2985 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2986 #endif 2987 2988 /* 2989 * Set up checksum offload parameters. 2990 */ 2991 reg = CSR_READ(sc, WMREG_RXCSUM); 2992 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 2993 reg |= RXCSUM_IPOFL; 2994 else 2995 reg &= ~RXCSUM_IPOFL; 2996 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2997 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2998 else { 2999 reg &= ~RXCSUM_TUOFL; 3000 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) 3001 reg &= ~RXCSUM_IPOFL; 3002 } 3003 CSR_WRITE(sc, WMREG_RXCSUM, reg); 3004 3005 /* 3006 * Set up the interrupt registers. 3007 */ 3008 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3009 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 3010 ICR_RXO | ICR_RXT0; 3011 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 3012 sc->sc_icr |= ICR_RXCFG; 3013 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 3014 3015 /* Set up the inter-packet gap. */ 3016 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 3017 3018 if (sc->sc_type >= WM_T_82543) { 3019 /* Set up the interrupt throttling register (units of 256ns) */ 3020 sc->sc_itr = 1000000000 / (7000 * 256); 3021 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 3022 } 3023 3024 #if 0 /* XXXJRT */ 3025 /* Set the VLAN ethernetype. */ 3026 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 3027 #endif 3028 3029 /* 3030 * Set up the transmit control register; we start out with 3031 * a collision distance suitable for FDX, but update it whe 3032 * we resolve the media type. 3033 */ 3034 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 3035 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3036 if (sc->sc_type >= WM_T_82571) 3037 sc->sc_tctl |= TCTL_MULR; 3038 if (sc->sc_type >= WM_T_80003) 3039 sc->sc_tctl |= TCTL_RTLC; 3040 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3041 3042 /* Set the media. */ 3043 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 3044 3045 /* 3046 * Set up the receive control register; we actually program 3047 * the register when we set the receive filter. Use multicast 3048 * address offset type 0. 3049 * 3050 * Only the i82544 has the ability to strip the incoming 3051 * CRC, so we don't enable that feature. 3052 */ 3053 sc->sc_mchash_type = 0; 3054 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF 3055 | RCTL_MO(sc->sc_mchash_type); 3056 3057 /* 82573 doesn't support jumbo frame */ 3058 if (sc->sc_type != WM_T_82573) 3059 sc->sc_rctl |= RCTL_LPE; 3060 3061 if (MCLBYTES == 2048) { 3062 sc->sc_rctl |= RCTL_2k; 3063 } else { 3064 if (sc->sc_type >= WM_T_82543) { 3065 switch(MCLBYTES) { 3066 case 4096: 3067 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 3068 break; 3069 case 8192: 3070 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 3071 break; 3072 case 16384: 3073 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 3074 break; 3075 default: 3076 panic("wm_init: MCLBYTES %d unsupported", 3077 MCLBYTES); 3078 break; 3079 } 3080 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 3081 } 3082 3083 /* Set the receive filter. */ 3084 wm_set_filter(sc); 3085 3086 /* Start the one second link check clock. */ 3087 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 3088 3089 /* ...all done! */ 3090 ifp->if_flags |= IFF_RUNNING; 3091 ifp->if_flags &= ~IFF_OACTIVE; 3092 3093 out: 3094 if (error) 3095 log(LOG_ERR, "%s: interface not running\n", 3096 sc->sc_dev.dv_xname); 3097 return (error); 3098 } 3099 3100 /* 3101 * wm_rxdrain: 3102 * 3103 * Drain the receive queue. 3104 */ 3105 static void 3106 wm_rxdrain(struct wm_softc *sc) 3107 { 3108 struct wm_rxsoft *rxs; 3109 int i; 3110 3111 for (i = 0; i < WM_NRXDESC; i++) { 3112 rxs = &sc->sc_rxsoft[i]; 3113 if (rxs->rxs_mbuf != NULL) { 3114 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3115 m_freem(rxs->rxs_mbuf); 3116 rxs->rxs_mbuf = NULL; 3117 } 3118 } 3119 } 3120 3121 /* 3122 * wm_stop: [ifnet interface function] 3123 * 3124 * Stop transmission on the interface. 3125 */ 3126 static void 3127 wm_stop(struct ifnet *ifp, int disable) 3128 { 3129 struct wm_softc *sc = ifp->if_softc; 3130 struct wm_txsoft *txs; 3131 int i; 3132 3133 /* Stop the one second clock. */ 3134 callout_stop(&sc->sc_tick_ch); 3135 3136 /* Stop the 82547 Tx FIFO stall check timer. */ 3137 if (sc->sc_type == WM_T_82547) 3138 callout_stop(&sc->sc_txfifo_ch); 3139 3140 if (sc->sc_flags & WM_F_HAS_MII) { 3141 /* Down the MII. */ 3142 mii_down(&sc->sc_mii); 3143 } 3144 3145 /* Stop the transmit and receive processes. */ 3146 CSR_WRITE(sc, WMREG_TCTL, 0); 3147 CSR_WRITE(sc, WMREG_RCTL, 0); 3148 3149 /* 3150 * Clear the interrupt mask to ensure the device cannot assert its 3151 * interrupt line. 3152 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 3153 * any currently pending or shared interrupt. 3154 */ 3155 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3156 sc->sc_icr = 0; 3157 3158 /* Release any queued transmit buffers. */ 3159 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 3160 txs = &sc->sc_txsoft[i]; 3161 if (txs->txs_mbuf != NULL) { 3162 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3163 m_freem(txs->txs_mbuf); 3164 txs->txs_mbuf = NULL; 3165 } 3166 } 3167 3168 if (disable) 3169 wm_rxdrain(sc); 3170 3171 /* Mark the interface as down and cancel the watchdog timer. */ 3172 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3173 ifp->if_timer = 0; 3174 } 3175 3176 /* 3177 * wm_acquire_eeprom: 3178 * 3179 * Perform the EEPROM handshake required on some chips. 3180 */ 3181 static int 3182 wm_acquire_eeprom(struct wm_softc *sc) 3183 { 3184 uint32_t reg; 3185 int x; 3186 int ret = 0; 3187 3188 /* always success */ 3189 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 3190 return 0; 3191 3192 if (sc->sc_flags & WM_F_SWFW_SYNC) { 3193 /* this will also do wm_get_swsm_semaphore() if needed */ 3194 ret = wm_get_swfw_semaphore(sc, SWFW_EEP_SM); 3195 } else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) { 3196 ret = wm_get_swsm_semaphore(sc); 3197 } 3198 3199 if (ret) 3200 return 1; 3201 3202 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3203 reg = CSR_READ(sc, WMREG_EECD); 3204 3205 /* Request EEPROM access. */ 3206 reg |= EECD_EE_REQ; 3207 CSR_WRITE(sc, WMREG_EECD, reg); 3208 3209 /* ..and wait for it to be granted. */ 3210 for (x = 0; x < 1000; x++) { 3211 reg = CSR_READ(sc, WMREG_EECD); 3212 if (reg & EECD_EE_GNT) 3213 break; 3214 delay(5); 3215 } 3216 if ((reg & EECD_EE_GNT) == 0) { 3217 aprint_error("%s: could not acquire EEPROM GNT\n", 3218 sc->sc_dev.dv_xname); 3219 reg &= ~EECD_EE_REQ; 3220 CSR_WRITE(sc, WMREG_EECD, reg); 3221 if (sc->sc_flags & WM_F_SWFW_SYNC) 3222 wm_put_swfw_semaphore(sc, SWFW_EEP_SM); 3223 else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 3224 wm_put_swsm_semaphore(sc); 3225 return (1); 3226 } 3227 } 3228 3229 return (0); 3230 } 3231 3232 /* 3233 * wm_release_eeprom: 3234 * 3235 * Release the EEPROM mutex. 3236 */ 3237 static void 3238 wm_release_eeprom(struct wm_softc *sc) 3239 { 3240 uint32_t reg; 3241 3242 /* always success */ 3243 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 3244 return; 3245 3246 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3247 reg = CSR_READ(sc, WMREG_EECD); 3248 reg &= ~EECD_EE_REQ; 3249 CSR_WRITE(sc, WMREG_EECD, reg); 3250 } 3251 3252 if (sc->sc_flags & WM_F_SWFW_SYNC) 3253 wm_put_swfw_semaphore(sc, SWFW_EEP_SM); 3254 else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 3255 wm_put_swsm_semaphore(sc); 3256 } 3257 3258 /* 3259 * wm_eeprom_sendbits: 3260 * 3261 * Send a series of bits to the EEPROM. 3262 */ 3263 static void 3264 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 3265 { 3266 uint32_t reg; 3267 int x; 3268 3269 reg = CSR_READ(sc, WMREG_EECD); 3270 3271 for (x = nbits; x > 0; x--) { 3272 if (bits & (1U << (x - 1))) 3273 reg |= EECD_DI; 3274 else 3275 reg &= ~EECD_DI; 3276 CSR_WRITE(sc, WMREG_EECD, reg); 3277 delay(2); 3278 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3279 delay(2); 3280 CSR_WRITE(sc, WMREG_EECD, reg); 3281 delay(2); 3282 } 3283 } 3284 3285 /* 3286 * wm_eeprom_recvbits: 3287 * 3288 * Receive a series of bits from the EEPROM. 3289 */ 3290 static void 3291 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 3292 { 3293 uint32_t reg, val; 3294 int x; 3295 3296 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 3297 3298 val = 0; 3299 for (x = nbits; x > 0; x--) { 3300 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3301 delay(2); 3302 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 3303 val |= (1U << (x - 1)); 3304 CSR_WRITE(sc, WMREG_EECD, reg); 3305 delay(2); 3306 } 3307 *valp = val; 3308 } 3309 3310 /* 3311 * wm_read_eeprom_uwire: 3312 * 3313 * Read a word from the EEPROM using the MicroWire protocol. 3314 */ 3315 static int 3316 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3317 { 3318 uint32_t reg, val; 3319 int i; 3320 3321 for (i = 0; i < wordcnt; i++) { 3322 /* Clear SK and DI. */ 3323 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3324 CSR_WRITE(sc, WMREG_EECD, reg); 3325 3326 /* Set CHIP SELECT. */ 3327 reg |= EECD_CS; 3328 CSR_WRITE(sc, WMREG_EECD, reg); 3329 delay(2); 3330 3331 /* Shift in the READ command. */ 3332 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3333 3334 /* Shift in address. */ 3335 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3336 3337 /* Shift out the data. */ 3338 wm_eeprom_recvbits(sc, &val, 16); 3339 data[i] = val & 0xffff; 3340 3341 /* Clear CHIP SELECT. */ 3342 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3343 CSR_WRITE(sc, WMREG_EECD, reg); 3344 delay(2); 3345 } 3346 3347 return (0); 3348 } 3349 3350 /* 3351 * wm_spi_eeprom_ready: 3352 * 3353 * Wait for a SPI EEPROM to be ready for commands. 3354 */ 3355 static int 3356 wm_spi_eeprom_ready(struct wm_softc *sc) 3357 { 3358 uint32_t val; 3359 int usec; 3360 3361 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3362 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3363 wm_eeprom_recvbits(sc, &val, 8); 3364 if ((val & SPI_SR_RDY) == 0) 3365 break; 3366 } 3367 if (usec >= SPI_MAX_RETRIES) { 3368 aprint_error("%s: EEPROM failed to become ready\n", 3369 sc->sc_dev.dv_xname); 3370 return (1); 3371 } 3372 return (0); 3373 } 3374 3375 /* 3376 * wm_read_eeprom_spi: 3377 * 3378 * Read a work from the EEPROM using the SPI protocol. 3379 */ 3380 static int 3381 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3382 { 3383 uint32_t reg, val; 3384 int i; 3385 uint8_t opc; 3386 3387 /* Clear SK and CS. */ 3388 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3389 CSR_WRITE(sc, WMREG_EECD, reg); 3390 delay(2); 3391 3392 if (wm_spi_eeprom_ready(sc)) 3393 return (1); 3394 3395 /* Toggle CS to flush commands. */ 3396 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3397 delay(2); 3398 CSR_WRITE(sc, WMREG_EECD, reg); 3399 delay(2); 3400 3401 opc = SPI_OPC_READ; 3402 if (sc->sc_ee_addrbits == 8 && word >= 128) 3403 opc |= SPI_OPC_A8; 3404 3405 wm_eeprom_sendbits(sc, opc, 8); 3406 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3407 3408 for (i = 0; i < wordcnt; i++) { 3409 wm_eeprom_recvbits(sc, &val, 16); 3410 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3411 } 3412 3413 /* Raise CS and clear SK. */ 3414 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3415 CSR_WRITE(sc, WMREG_EECD, reg); 3416 delay(2); 3417 3418 return (0); 3419 } 3420 3421 #define EEPROM_CHECKSUM 0xBABA 3422 #define EEPROM_SIZE 0x0040 3423 3424 /* 3425 * wm_validate_eeprom_checksum 3426 * 3427 * The checksum is defined as the sum of the first 64 (16 bit) words. 3428 */ 3429 static int 3430 wm_validate_eeprom_checksum(struct wm_softc *sc) 3431 { 3432 uint16_t checksum; 3433 uint16_t eeprom_data; 3434 int i; 3435 3436 checksum = 0; 3437 3438 for (i = 0; i < EEPROM_SIZE; i++) { 3439 if (wm_read_eeprom(sc, i, 1, &eeprom_data)) 3440 return 1; 3441 checksum += eeprom_data; 3442 } 3443 3444 if (checksum != (uint16_t) EEPROM_CHECKSUM) 3445 return 1; 3446 3447 return 0; 3448 } 3449 3450 /* 3451 * wm_read_eeprom: 3452 * 3453 * Read data from the serial EEPROM. 3454 */ 3455 static int 3456 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3457 { 3458 int rv; 3459 3460 if (sc->sc_flags & WM_F_EEPROM_INVALID) 3461 return 1; 3462 3463 if (wm_acquire_eeprom(sc)) 3464 return 1; 3465 3466 if (sc->sc_flags & WM_F_EEPROM_EERDEEWR) 3467 rv = wm_read_eeprom_eerd(sc, word, wordcnt, data); 3468 else if (sc->sc_flags & WM_F_EEPROM_SPI) 3469 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3470 else 3471 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3472 3473 wm_release_eeprom(sc); 3474 return rv; 3475 } 3476 3477 static int 3478 wm_read_eeprom_eerd(struct wm_softc *sc, int offset, int wordcnt, 3479 uint16_t *data) 3480 { 3481 int i, eerd = 0; 3482 int error = 0; 3483 3484 for (i = 0; i < wordcnt; i++) { 3485 eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START; 3486 3487 CSR_WRITE(sc, WMREG_EERD, eerd); 3488 error = wm_poll_eerd_eewr_done(sc, WMREG_EERD); 3489 if (error != 0) 3490 break; 3491 3492 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT); 3493 } 3494 3495 return error; 3496 } 3497 3498 static int 3499 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw) 3500 { 3501 uint32_t attempts = 100000; 3502 uint32_t i, reg = 0; 3503 int32_t done = -1; 3504 3505 for (i = 0; i < attempts; i++) { 3506 reg = CSR_READ(sc, rw); 3507 3508 if (reg & EERD_DONE) { 3509 done = 0; 3510 break; 3511 } 3512 delay(5); 3513 } 3514 3515 return done; 3516 } 3517 3518 /* 3519 * wm_add_rxbuf: 3520 * 3521 * Add a receive buffer to the indiciated descriptor. 3522 */ 3523 static int 3524 wm_add_rxbuf(struct wm_softc *sc, int idx) 3525 { 3526 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3527 struct mbuf *m; 3528 int error; 3529 3530 MGETHDR(m, M_DONTWAIT, MT_DATA); 3531 if (m == NULL) 3532 return (ENOBUFS); 3533 3534 MCLGET(m, M_DONTWAIT); 3535 if ((m->m_flags & M_EXT) == 0) { 3536 m_freem(m); 3537 return (ENOBUFS); 3538 } 3539 3540 if (rxs->rxs_mbuf != NULL) 3541 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3542 3543 rxs->rxs_mbuf = m; 3544 3545 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3546 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3547 BUS_DMA_READ|BUS_DMA_NOWAIT); 3548 if (error) { 3549 /* XXX XXX XXX */ 3550 printf("%s: unable to load rx DMA map %d, error = %d\n", 3551 sc->sc_dev.dv_xname, idx, error); 3552 panic("wm_add_rxbuf"); 3553 } 3554 3555 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3556 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3557 3558 WM_INIT_RXDESC(sc, idx); 3559 3560 return (0); 3561 } 3562 3563 /* 3564 * wm_set_ral: 3565 * 3566 * Set an entery in the receive address list. 3567 */ 3568 static void 3569 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3570 { 3571 uint32_t ral_lo, ral_hi; 3572 3573 if (enaddr != NULL) { 3574 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3575 (enaddr[3] << 24); 3576 ral_hi = enaddr[4] | (enaddr[5] << 8); 3577 ral_hi |= RAL_AV; 3578 } else { 3579 ral_lo = 0; 3580 ral_hi = 0; 3581 } 3582 3583 if (sc->sc_type >= WM_T_82544) { 3584 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3585 ral_lo); 3586 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3587 ral_hi); 3588 } else { 3589 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3590 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3591 } 3592 } 3593 3594 /* 3595 * wm_mchash: 3596 * 3597 * Compute the hash of the multicast address for the 4096-bit 3598 * multicast filter. 3599 */ 3600 static uint32_t 3601 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3602 { 3603 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3604 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3605 uint32_t hash; 3606 3607 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3608 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3609 3610 return (hash & 0xfff); 3611 } 3612 3613 /* 3614 * wm_set_filter: 3615 * 3616 * Set up the receive filter. 3617 */ 3618 static void 3619 wm_set_filter(struct wm_softc *sc) 3620 { 3621 struct ethercom *ec = &sc->sc_ethercom; 3622 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3623 struct ether_multi *enm; 3624 struct ether_multistep step; 3625 bus_addr_t mta_reg; 3626 uint32_t hash, reg, bit; 3627 int i; 3628 3629 if (sc->sc_type >= WM_T_82544) 3630 mta_reg = WMREG_CORDOVA_MTA; 3631 else 3632 mta_reg = WMREG_MTA; 3633 3634 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3635 3636 if (ifp->if_flags & IFF_BROADCAST) 3637 sc->sc_rctl |= RCTL_BAM; 3638 if (ifp->if_flags & IFF_PROMISC) { 3639 sc->sc_rctl |= RCTL_UPE; 3640 goto allmulti; 3641 } 3642 3643 /* 3644 * Set the station address in the first RAL slot, and 3645 * clear the remaining slots. 3646 */ 3647 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3648 for (i = 1; i < WM_RAL_TABSIZE; i++) 3649 wm_set_ral(sc, NULL, i); 3650 3651 /* Clear out the multicast table. */ 3652 for (i = 0; i < WM_MC_TABSIZE; i++) 3653 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3654 3655 ETHER_FIRST_MULTI(step, ec, enm); 3656 while (enm != NULL) { 3657 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3658 /* 3659 * We must listen to a range of multicast addresses. 3660 * For now, just accept all multicasts, rather than 3661 * trying to set only those filter bits needed to match 3662 * the range. (At this time, the only use of address 3663 * ranges is for IP multicast routing, for which the 3664 * range is big enough to require all bits set.) 3665 */ 3666 goto allmulti; 3667 } 3668 3669 hash = wm_mchash(sc, enm->enm_addrlo); 3670 3671 reg = (hash >> 5) & 0x7f; 3672 bit = hash & 0x1f; 3673 3674 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3675 hash |= 1U << bit; 3676 3677 /* XXX Hardware bug?? */ 3678 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3679 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3680 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3681 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3682 } else 3683 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3684 3685 ETHER_NEXT_MULTI(step, enm); 3686 } 3687 3688 ifp->if_flags &= ~IFF_ALLMULTI; 3689 goto setit; 3690 3691 allmulti: 3692 ifp->if_flags |= IFF_ALLMULTI; 3693 sc->sc_rctl |= RCTL_MPE; 3694 3695 setit: 3696 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3697 } 3698 3699 /* 3700 * wm_tbi_mediainit: 3701 * 3702 * Initialize media for use on 1000BASE-X devices. 3703 */ 3704 static void 3705 wm_tbi_mediainit(struct wm_softc *sc) 3706 { 3707 const char *sep = ""; 3708 3709 if (sc->sc_type < WM_T_82543) 3710 sc->sc_tipg = TIPG_WM_DFLT; 3711 else 3712 sc->sc_tipg = TIPG_LG_DFLT; 3713 3714 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3715 wm_tbi_mediastatus); 3716 3717 /* 3718 * SWD Pins: 3719 * 3720 * 0 = Link LED (output) 3721 * 1 = Loss Of Signal (input) 3722 */ 3723 sc->sc_ctrl |= CTRL_SWDPIO(0); 3724 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3725 3726 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3727 3728 #define ADD(ss, mm, dd) \ 3729 do { \ 3730 aprint_normal("%s%s", sep, ss); \ 3731 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3732 sep = ", "; \ 3733 } while (/*CONSTCOND*/0) 3734 3735 aprint_normal("%s: ", sc->sc_dev.dv_xname); 3736 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3737 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3738 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3739 aprint_normal("\n"); 3740 3741 #undef ADD 3742 3743 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3744 } 3745 3746 /* 3747 * wm_tbi_mediastatus: [ifmedia interface function] 3748 * 3749 * Get the current interface media status on a 1000BASE-X device. 3750 */ 3751 static void 3752 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3753 { 3754 struct wm_softc *sc = ifp->if_softc; 3755 uint32_t ctrl; 3756 3757 ifmr->ifm_status = IFM_AVALID; 3758 ifmr->ifm_active = IFM_ETHER; 3759 3760 if (sc->sc_tbi_linkup == 0) { 3761 ifmr->ifm_active |= IFM_NONE; 3762 return; 3763 } 3764 3765 ifmr->ifm_status |= IFM_ACTIVE; 3766 ifmr->ifm_active |= IFM_1000_SX; 3767 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3768 ifmr->ifm_active |= IFM_FDX; 3769 ctrl = CSR_READ(sc, WMREG_CTRL); 3770 if (ctrl & CTRL_RFCE) 3771 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3772 if (ctrl & CTRL_TFCE) 3773 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3774 } 3775 3776 /* 3777 * wm_tbi_mediachange: [ifmedia interface function] 3778 * 3779 * Set hardware to newly-selected media on a 1000BASE-X device. 3780 */ 3781 static int 3782 wm_tbi_mediachange(struct ifnet *ifp) 3783 { 3784 struct wm_softc *sc = ifp->if_softc; 3785 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3786 uint32_t status; 3787 int i; 3788 3789 sc->sc_txcw = ife->ifm_data; 3790 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3791 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3792 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3793 sc->sc_txcw |= TXCW_ANE; 3794 3795 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3796 delay(10000); 3797 3798 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3799 3800 sc->sc_tbi_anstate = 0; 3801 3802 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3803 /* Have signal; wait for the link to come up. */ 3804 for (i = 0; i < 50; i++) { 3805 delay(10000); 3806 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3807 break; 3808 } 3809 3810 status = CSR_READ(sc, WMREG_STATUS); 3811 if (status & STATUS_LU) { 3812 /* Link is up. */ 3813 DPRINTF(WM_DEBUG_LINK, 3814 ("%s: LINK: set media -> link up %s\n", 3815 sc->sc_dev.dv_xname, 3816 (status & STATUS_FD) ? "FDX" : "HDX")); 3817 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3818 sc->sc_fcrtl &= ~FCRTL_XONE; 3819 if (status & STATUS_FD) 3820 sc->sc_tctl |= 3821 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3822 else 3823 sc->sc_tctl |= 3824 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3825 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3826 sc->sc_fcrtl |= FCRTL_XONE; 3827 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3828 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3829 WMREG_OLD_FCRTL : WMREG_FCRTL, 3830 sc->sc_fcrtl); 3831 sc->sc_tbi_linkup = 1; 3832 } else { 3833 /* Link is down. */ 3834 DPRINTF(WM_DEBUG_LINK, 3835 ("%s: LINK: set media -> link down\n", 3836 sc->sc_dev.dv_xname)); 3837 sc->sc_tbi_linkup = 0; 3838 } 3839 } else { 3840 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3841 sc->sc_dev.dv_xname)); 3842 sc->sc_tbi_linkup = 0; 3843 } 3844 3845 wm_tbi_set_linkled(sc); 3846 3847 return (0); 3848 } 3849 3850 /* 3851 * wm_tbi_set_linkled: 3852 * 3853 * Update the link LED on 1000BASE-X devices. 3854 */ 3855 static void 3856 wm_tbi_set_linkled(struct wm_softc *sc) 3857 { 3858 3859 if (sc->sc_tbi_linkup) 3860 sc->sc_ctrl |= CTRL_SWDPIN(0); 3861 else 3862 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3863 3864 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3865 } 3866 3867 /* 3868 * wm_tbi_check_link: 3869 * 3870 * Check the link on 1000BASE-X devices. 3871 */ 3872 static void 3873 wm_tbi_check_link(struct wm_softc *sc) 3874 { 3875 uint32_t rxcw, ctrl, status; 3876 3877 if (sc->sc_tbi_anstate == 0) 3878 return; 3879 else if (sc->sc_tbi_anstate > 1) { 3880 DPRINTF(WM_DEBUG_LINK, 3881 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3882 sc->sc_tbi_anstate)); 3883 sc->sc_tbi_anstate--; 3884 return; 3885 } 3886 3887 sc->sc_tbi_anstate = 0; 3888 3889 rxcw = CSR_READ(sc, WMREG_RXCW); 3890 ctrl = CSR_READ(sc, WMREG_CTRL); 3891 status = CSR_READ(sc, WMREG_STATUS); 3892 3893 if ((status & STATUS_LU) == 0) { 3894 DPRINTF(WM_DEBUG_LINK, 3895 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3896 sc->sc_tbi_linkup = 0; 3897 } else { 3898 DPRINTF(WM_DEBUG_LINK, 3899 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3900 (status & STATUS_FD) ? "FDX" : "HDX")); 3901 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3902 sc->sc_fcrtl &= ~FCRTL_XONE; 3903 if (status & STATUS_FD) 3904 sc->sc_tctl |= 3905 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3906 else 3907 sc->sc_tctl |= 3908 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3909 if (ctrl & CTRL_TFCE) 3910 sc->sc_fcrtl |= FCRTL_XONE; 3911 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3912 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3913 WMREG_OLD_FCRTL : WMREG_FCRTL, 3914 sc->sc_fcrtl); 3915 sc->sc_tbi_linkup = 1; 3916 } 3917 3918 wm_tbi_set_linkled(sc); 3919 } 3920 3921 /* 3922 * wm_gmii_reset: 3923 * 3924 * Reset the PHY. 3925 */ 3926 static void 3927 wm_gmii_reset(struct wm_softc *sc) 3928 { 3929 uint32_t reg; 3930 int func = 0; /* XXX gcc */ 3931 3932 if (sc->sc_type >= WM_T_80003) { 3933 func = (CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1; 3934 if (wm_get_swfw_semaphore(sc, 3935 func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 3936 return; 3937 } 3938 if (sc->sc_type >= WM_T_82544) { 3939 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3940 delay(20000); 3941 3942 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3943 delay(20000); 3944 } else { 3945 /* The PHY reset pin is active-low. */ 3946 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3947 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3948 CTRL_EXT_SWDPIN(4)); 3949 reg |= CTRL_EXT_SWDPIO(4); 3950 3951 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3952 delay(10); 3953 3954 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3955 delay(10); 3956 3957 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3958 delay(10); 3959 #if 0 3960 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3961 #endif 3962 } 3963 if (sc->sc_type >= WM_T_80003) 3964 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 3965 } 3966 3967 /* 3968 * wm_gmii_mediainit: 3969 * 3970 * Initialize media for use on 1000BASE-T devices. 3971 */ 3972 static void 3973 wm_gmii_mediainit(struct wm_softc *sc) 3974 { 3975 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3976 3977 /* We have MII. */ 3978 sc->sc_flags |= WM_F_HAS_MII; 3979 3980 if (sc->sc_type >= WM_T_80003) 3981 sc->sc_tipg = TIPG_1000T_80003_DFLT; 3982 else 3983 sc->sc_tipg = TIPG_1000T_DFLT; 3984 3985 /* 3986 * Let the chip set speed/duplex on its own based on 3987 * signals from the PHY. 3988 * XXXbouyer - I'm not sure this is right for the 80003, 3989 * the em driver only sets CTRL_SLU here - but it seems to work. 3990 */ 3991 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3992 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3993 3994 /* Initialize our media structures and probe the GMII. */ 3995 sc->sc_mii.mii_ifp = ifp; 3996 3997 if (sc->sc_type >= WM_T_80003) { 3998 sc->sc_mii.mii_readreg = wm_gmii_i80003_readreg; 3999 sc->sc_mii.mii_writereg = wm_gmii_i80003_writereg; 4000 } else if (sc->sc_type >= WM_T_82544) { 4001 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 4002 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 4003 } else { 4004 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 4005 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 4006 } 4007 sc->sc_mii.mii_statchg = wm_gmii_statchg; 4008 4009 wm_gmii_reset(sc); 4010 4011 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 4012 wm_gmii_mediastatus); 4013 4014 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 4015 MII_OFFSET_ANY, MIIF_DOPAUSE); 4016 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 4017 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 4018 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 4019 } else 4020 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 4021 } 4022 4023 /* 4024 * wm_gmii_mediastatus: [ifmedia interface function] 4025 * 4026 * Get the current interface media status on a 1000BASE-T device. 4027 */ 4028 static void 4029 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 4030 { 4031 struct wm_softc *sc = ifp->if_softc; 4032 4033 mii_pollstat(&sc->sc_mii); 4034 ifmr->ifm_status = sc->sc_mii.mii_media_status; 4035 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 4036 sc->sc_flowflags; 4037 } 4038 4039 /* 4040 * wm_gmii_mediachange: [ifmedia interface function] 4041 * 4042 * Set hardware to newly-selected media on a 1000BASE-T device. 4043 */ 4044 static int 4045 wm_gmii_mediachange(struct ifnet *ifp) 4046 { 4047 struct wm_softc *sc = ifp->if_softc; 4048 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 4049 4050 if (ifp->if_flags & IFF_UP) { 4051 sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD); 4052 sc->sc_ctrl |= CTRL_SLU; 4053 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 4054 sc->sc_ctrl |= CTRL_ASDE; 4055 } else { 4056 sc->sc_ctrl &= ~CTRL_ASDE; 4057 sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX; 4058 if (ife->ifm_media & IFM_FDX) 4059 sc->sc_ctrl |= CTRL_FD; 4060 switch(IFM_SUBTYPE(ife->ifm_media)) { 4061 case IFM_10_T: 4062 sc->sc_ctrl |= CTRL_SPEED_10; 4063 break; 4064 case IFM_100_TX: 4065 sc->sc_ctrl |= CTRL_SPEED_100; 4066 break; 4067 case IFM_1000_T: 4068 sc->sc_ctrl |= CTRL_SPEED_1000; 4069 break; 4070 default: 4071 panic("wm_gmii_mediachange: bad media 0x%x", 4072 ife->ifm_media); 4073 } 4074 } 4075 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4076 mii_mediachg(&sc->sc_mii); 4077 } 4078 return (0); 4079 } 4080 4081 #define MDI_IO CTRL_SWDPIN(2) 4082 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 4083 #define MDI_CLK CTRL_SWDPIN(3) 4084 4085 static void 4086 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 4087 { 4088 uint32_t i, v; 4089 4090 v = CSR_READ(sc, WMREG_CTRL); 4091 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 4092 v |= MDI_DIR | CTRL_SWDPIO(3); 4093 4094 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 4095 if (data & i) 4096 v |= MDI_IO; 4097 else 4098 v &= ~MDI_IO; 4099 CSR_WRITE(sc, WMREG_CTRL, v); 4100 delay(10); 4101 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 4102 delay(10); 4103 CSR_WRITE(sc, WMREG_CTRL, v); 4104 delay(10); 4105 } 4106 } 4107 4108 static uint32_t 4109 i82543_mii_recvbits(struct wm_softc *sc) 4110 { 4111 uint32_t v, i, data = 0; 4112 4113 v = CSR_READ(sc, WMREG_CTRL); 4114 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 4115 v |= CTRL_SWDPIO(3); 4116 4117 CSR_WRITE(sc, WMREG_CTRL, v); 4118 delay(10); 4119 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 4120 delay(10); 4121 CSR_WRITE(sc, WMREG_CTRL, v); 4122 delay(10); 4123 4124 for (i = 0; i < 16; i++) { 4125 data <<= 1; 4126 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 4127 delay(10); 4128 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 4129 data |= 1; 4130 CSR_WRITE(sc, WMREG_CTRL, v); 4131 delay(10); 4132 } 4133 4134 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 4135 delay(10); 4136 CSR_WRITE(sc, WMREG_CTRL, v); 4137 delay(10); 4138 4139 return (data); 4140 } 4141 4142 #undef MDI_IO 4143 #undef MDI_DIR 4144 #undef MDI_CLK 4145 4146 /* 4147 * wm_gmii_i82543_readreg: [mii interface function] 4148 * 4149 * Read a PHY register on the GMII (i82543 version). 4150 */ 4151 static int 4152 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 4153 { 4154 struct wm_softc *sc = (void *) self; 4155 int rv; 4156 4157 i82543_mii_sendbits(sc, 0xffffffffU, 32); 4158 i82543_mii_sendbits(sc, reg | (phy << 5) | 4159 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 4160 rv = i82543_mii_recvbits(sc) & 0xffff; 4161 4162 DPRINTF(WM_DEBUG_GMII, 4163 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 4164 sc->sc_dev.dv_xname, phy, reg, rv)); 4165 4166 return (rv); 4167 } 4168 4169 /* 4170 * wm_gmii_i82543_writereg: [mii interface function] 4171 * 4172 * Write a PHY register on the GMII (i82543 version). 4173 */ 4174 static void 4175 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 4176 { 4177 struct wm_softc *sc = (void *) self; 4178 4179 i82543_mii_sendbits(sc, 0xffffffffU, 32); 4180 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 4181 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 4182 (MII_COMMAND_START << 30), 32); 4183 } 4184 4185 /* 4186 * wm_gmii_i82544_readreg: [mii interface function] 4187 * 4188 * Read a PHY register on the GMII. 4189 */ 4190 static int 4191 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 4192 { 4193 struct wm_softc *sc = (void *) self; 4194 uint32_t mdic = 0; 4195 int i, rv; 4196 4197 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 4198 MDIC_REGADD(reg)); 4199 4200 for (i = 0; i < 320; i++) { 4201 mdic = CSR_READ(sc, WMREG_MDIC); 4202 if (mdic & MDIC_READY) 4203 break; 4204 delay(10); 4205 } 4206 4207 if ((mdic & MDIC_READY) == 0) { 4208 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 4209 sc->sc_dev.dv_xname, phy, reg); 4210 rv = 0; 4211 } else if (mdic & MDIC_E) { 4212 #if 0 /* This is normal if no PHY is present. */ 4213 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 4214 sc->sc_dev.dv_xname, phy, reg); 4215 #endif 4216 rv = 0; 4217 } else { 4218 rv = MDIC_DATA(mdic); 4219 if (rv == 0xffff) 4220 rv = 0; 4221 } 4222 4223 return (rv); 4224 } 4225 4226 /* 4227 * wm_gmii_i82544_writereg: [mii interface function] 4228 * 4229 * Write a PHY register on the GMII. 4230 */ 4231 static void 4232 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 4233 { 4234 struct wm_softc *sc = (void *) self; 4235 uint32_t mdic = 0; 4236 int i; 4237 4238 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 4239 MDIC_REGADD(reg) | MDIC_DATA(val)); 4240 4241 for (i = 0; i < 320; i++) { 4242 mdic = CSR_READ(sc, WMREG_MDIC); 4243 if (mdic & MDIC_READY) 4244 break; 4245 delay(10); 4246 } 4247 4248 if ((mdic & MDIC_READY) == 0) 4249 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 4250 sc->sc_dev.dv_xname, phy, reg); 4251 else if (mdic & MDIC_E) 4252 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 4253 sc->sc_dev.dv_xname, phy, reg); 4254 } 4255 4256 /* 4257 * wm_gmii_i80003_readreg: [mii interface function] 4258 * 4259 * Read a PHY register on the kumeran 4260 * This could be handled by the PHY layer if we didn't have to lock the 4261 * ressource ... 4262 */ 4263 static int 4264 wm_gmii_i80003_readreg(struct device *self, int phy, int reg) 4265 { 4266 struct wm_softc *sc = (void *) self; 4267 int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1); 4268 int rv; 4269 4270 if (phy != 1) /* only one PHY on kumeran bus */ 4271 return 0; 4272 4273 if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4274 return 0; 4275 4276 if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 4277 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT, 4278 reg >> GG82563_PAGE_SHIFT); 4279 } else { 4280 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT, 4281 reg >> GG82563_PAGE_SHIFT); 4282 } 4283 4284 rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS); 4285 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4286 return (rv); 4287 } 4288 4289 /* 4290 * wm_gmii_i80003_writereg: [mii interface function] 4291 * 4292 * Write a PHY register on the kumeran. 4293 * This could be handled by the PHY layer if we didn't have to lock the 4294 * ressource ... 4295 */ 4296 static void 4297 wm_gmii_i80003_writereg(struct device *self, int phy, int reg, int val) 4298 { 4299 struct wm_softc *sc = (void *) self; 4300 int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1); 4301 4302 if (phy != 1) /* only one PHY on kumeran bus */ 4303 return; 4304 4305 if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4306 return; 4307 4308 if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 4309 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT, 4310 reg >> GG82563_PAGE_SHIFT); 4311 } else { 4312 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT, 4313 reg >> GG82563_PAGE_SHIFT); 4314 } 4315 4316 wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val); 4317 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4318 } 4319 4320 /* 4321 * wm_gmii_statchg: [mii interface function] 4322 * 4323 * Callback from MII layer when media changes. 4324 */ 4325 static void 4326 wm_gmii_statchg(struct device *self) 4327 { 4328 struct wm_softc *sc = (void *) self; 4329 struct mii_data *mii = &sc->sc_mii; 4330 4331 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 4332 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 4333 sc->sc_fcrtl &= ~FCRTL_XONE; 4334 4335 /* 4336 * Get flow control negotiation result. 4337 */ 4338 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 4339 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 4340 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 4341 mii->mii_media_active &= ~IFM_ETH_FMASK; 4342 } 4343 4344 if (sc->sc_flowflags & IFM_FLOW) { 4345 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 4346 sc->sc_ctrl |= CTRL_TFCE; 4347 sc->sc_fcrtl |= FCRTL_XONE; 4348 } 4349 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 4350 sc->sc_ctrl |= CTRL_RFCE; 4351 } 4352 4353 if (sc->sc_mii.mii_media_active & IFM_FDX) { 4354 DPRINTF(WM_DEBUG_LINK, 4355 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 4356 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4357 } else { 4358 DPRINTF(WM_DEBUG_LINK, 4359 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 4360 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 4361 } 4362 4363 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4364 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4365 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 4366 : WMREG_FCRTL, sc->sc_fcrtl); 4367 if (sc->sc_type >= WM_T_80003) { 4368 switch(IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 4369 case IFM_1000_T: 4370 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL, 4371 KUMCTRLSTA_HD_CTRL_1000_DEFAULT); 4372 sc->sc_tipg = TIPG_1000T_80003_DFLT; 4373 break; 4374 default: 4375 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL, 4376 KUMCTRLSTA_HD_CTRL_10_100_DEFAULT); 4377 sc->sc_tipg = TIPG_10_100_80003_DFLT; 4378 break; 4379 } 4380 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 4381 } 4382 } 4383 4384 /* 4385 * wm_kmrn_i80003_readreg: 4386 * 4387 * Read a kumeran register 4388 */ 4389 static int 4390 wm_kmrn_i80003_readreg(struct wm_softc *sc, int reg) 4391 { 4392 int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1); 4393 int rv; 4394 4395 if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4396 return 0; 4397 4398 CSR_WRITE(sc, WMREG_KUMCTRLSTA, 4399 ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | 4400 KUMCTRLSTA_REN); 4401 delay(2); 4402 4403 rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK; 4404 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4405 return (rv); 4406 } 4407 4408 /* 4409 * wm_kmrn_i80003_writereg: 4410 * 4411 * Write a kumeran register 4412 */ 4413 static void 4414 wm_kmrn_i80003_writereg(struct wm_softc *sc, int reg, int val) 4415 { 4416 int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1); 4417 4418 if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4419 return; 4420 4421 CSR_WRITE(sc, WMREG_KUMCTRLSTA, 4422 ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | 4423 (val & KUMCTRLSTA_MASK)); 4424 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4425 } 4426 4427 static int 4428 wm_is_onboard_nvm_eeprom(struct wm_softc *sc) 4429 { 4430 uint32_t eecd = 0; 4431 4432 if (sc->sc_type == WM_T_82573) { 4433 eecd = CSR_READ(sc, WMREG_EECD); 4434 4435 /* Isolate bits 15 & 16 */ 4436 eecd = ((eecd >> 15) & 0x03); 4437 4438 /* If both bits are set, device is Flash type */ 4439 if (eecd == 0x03) { 4440 return 0; 4441 } 4442 } 4443 return 1; 4444 } 4445 4446 static int 4447 wm_get_swsm_semaphore(struct wm_softc *sc) 4448 { 4449 int32_t timeout; 4450 uint32_t swsm; 4451 4452 /* Get the FW semaphore. */ 4453 timeout = 1000 + 1; /* XXX */ 4454 while (timeout) { 4455 swsm = CSR_READ(sc, WMREG_SWSM); 4456 swsm |= SWSM_SWESMBI; 4457 CSR_WRITE(sc, WMREG_SWSM, swsm); 4458 /* if we managed to set the bit we got the semaphore. */ 4459 swsm = CSR_READ(sc, WMREG_SWSM); 4460 if (swsm & SWSM_SWESMBI) 4461 break; 4462 4463 delay(50); 4464 timeout--; 4465 } 4466 4467 if (timeout == 0) { 4468 aprint_error("%s: could not acquire EEPROM GNT\n", 4469 sc->sc_dev.dv_xname); 4470 /* Release semaphores */ 4471 wm_put_swsm_semaphore(sc); 4472 return 1; 4473 } 4474 return 0; 4475 } 4476 4477 static void 4478 wm_put_swsm_semaphore(struct wm_softc *sc) 4479 { 4480 uint32_t swsm; 4481 4482 swsm = CSR_READ(sc, WMREG_SWSM); 4483 swsm &= ~(SWSM_SWESMBI); 4484 CSR_WRITE(sc, WMREG_SWSM, swsm); 4485 } 4486 4487 static int 4488 wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask) { 4489 uint32_t swfw_sync; 4490 uint32_t swmask = mask << SWFW_SOFT_SHIFT; 4491 uint32_t fwmask = mask << SWFW_FIRM_SHIFT; 4492 int timeout = 200; 4493 4494 for(timeout = 0; timeout < 200; timeout++) { 4495 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) { 4496 if (wm_get_swsm_semaphore(sc)) 4497 return 1; 4498 } 4499 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC); 4500 if ((swfw_sync & (swmask | fwmask)) == 0) { 4501 swfw_sync |= swmask; 4502 CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync); 4503 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 4504 wm_put_swsm_semaphore(sc); 4505 return 0; 4506 } 4507 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 4508 wm_put_swsm_semaphore(sc); 4509 delay(5000); 4510 } 4511 printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n", 4512 sc->sc_dev.dv_xname, mask, swfw_sync); 4513 return 1; 4514 } 4515 4516 static void 4517 wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask) { 4518 uint32_t swfw_sync; 4519 4520 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) { 4521 while (wm_get_swsm_semaphore(sc) != 0) 4522 continue; 4523 } 4524 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC); 4525 swfw_sync &= ~(mask << SWFW_SOFT_SHIFT); 4526 CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync); 4527 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 4528 wm_put_swsm_semaphore(sc); 4529 } 4530
Indexes created Tue Sep 23 14:10:03 GMT 2025