if_wm.c revision 1.145
1 /* $NetBSD: if_wm.c,v 1.145 2007/08/30 03:02:23 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /******************************************************************************* 39 40 Copyright (c) 2001-2005, Intel Corporation 41 All rights reserved. 42 43 Redistribution and use in source and binary forms, with or without 44 modification, are permitted provided that the following conditions are met: 45 46 1. Redistributions of source code must retain the above copyright notice, 47 this list of conditions and the following disclaimer. 48 49 2. Redistributions in binary form must reproduce the above copyright 50 notice, this list of conditions and the following disclaimer in the 51 documentation and/or other materials provided with the distribution. 52 53 3. Neither the name of the Intel Corporation nor the names of its 54 contributors may be used to endorse or promote products derived from 55 this software without specific prior written permission. 56 57 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 58 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 61 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 POSSIBILITY OF SUCH DAMAGE. 68 69 *******************************************************************************/ 70 /* 71 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 72 * 73 * TODO (in order of importance): 74 * 75 * - Rework how parameters are loaded from the EEPROM. 76 * - Figure out what to do with the i82545GM and i82546GB 77 * SERDES controllers. 78 * - Fix hw VLAN assist. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.145 2007/08/30 03:02:23 msaitoh Exp $"); 83 84 #include "bpfilter.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/ioctl.h> 95 #include <sys/errno.h> 96 #include <sys/device.h> 97 #include <sys/queue.h> 98 #include <sys/syslog.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <netinet/in.h> /* XXX for struct ip */ 116 #include <netinet/in_systm.h> /* XXX for struct ip */ 117 #include <netinet/ip.h> /* XXX for struct ip */ 118 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */ 119 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 120 121 #include <machine/bus.h> 122 #include <machine/intr.h> 123 #include <machine/endian.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/miivar.h> 127 #include <dev/mii/mii_bitbang.h> 128 #include <dev/mii/ikphyreg.h> 129 130 #include <dev/pci/pcireg.h> 131 #include <dev/pci/pcivar.h> 132 #include <dev/pci/pcidevs.h> 133 134 #include <dev/pci/if_wmreg.h> 135 136 #ifdef WM_DEBUG 137 #define WM_DEBUG_LINK 0x01 138 #define WM_DEBUG_TX 0x02 139 #define WM_DEBUG_RX 0x04 140 #define WM_DEBUG_GMII 0x08 141 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK|WM_DEBUG_GMII; 142 143 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 144 #else 145 #define DPRINTF(x, y) /* nothing */ 146 #endif /* WM_DEBUG */ 147 148 /* 149 * Transmit descriptor list size. Due to errata, we can only have 150 * 256 hardware descriptors in the ring on < 82544, but we use 4096 151 * on >= 82544. We tell the upper layers that they can queue a lot 152 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 153 * of them at a time. 154 * 155 * We allow up to 256 (!) DMA segments per packet. Pathological packet 156 * chains containing many small mbufs have been observed in zero-copy 157 * situations with jumbo frames. 158 */ 159 #define WM_NTXSEGS 256 160 #define WM_IFQUEUELEN 256 161 #define WM_TXQUEUELEN_MAX 64 162 #define WM_TXQUEUELEN_MAX_82547 16 163 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 164 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 165 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 166 #define WM_NTXDESC_82542 256 167 #define WM_NTXDESC_82544 4096 168 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 169 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 170 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 171 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 172 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 173 174 #define WM_MAXTXDMA round_page(IP_MAXPACKET) /* for TSO */ 175 176 /* 177 * Receive descriptor list size. We have one Rx buffer for normal 178 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 179 * packet. We allocate 256 receive descriptors, each with a 2k 180 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 181 */ 182 #define WM_NRXDESC 256 183 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 184 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 185 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 186 187 /* 188 * Control structures are DMA'd to the i82542 chip. We allocate them in 189 * a single clump that maps to a single DMA segment to make several things 190 * easier. 191 */ 192 struct wm_control_data_82544 { 193 /* 194 * The receive descriptors. 195 */ 196 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 197 198 /* 199 * The transmit descriptors. Put these at the end, because 200 * we might use a smaller number of them. 201 */ 202 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 203 }; 204 205 struct wm_control_data_82542 { 206 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 207 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 208 }; 209 210 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 211 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 212 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 213 214 /* 215 * Software state for transmit jobs. 216 */ 217 struct wm_txsoft { 218 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 219 bus_dmamap_t txs_dmamap; /* our DMA map */ 220 int txs_firstdesc; /* first descriptor in packet */ 221 int txs_lastdesc; /* last descriptor in packet */ 222 int txs_ndesc; /* # of descriptors used */ 223 }; 224 225 /* 226 * Software state for receive buffers. Each descriptor gets a 227 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 228 * more than one buffer, we chain them together. 229 */ 230 struct wm_rxsoft { 231 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 232 bus_dmamap_t rxs_dmamap; /* our DMA map */ 233 }; 234 235 typedef enum { 236 WM_T_unknown = 0, 237 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 238 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 239 WM_T_82543, /* i82543 */ 240 WM_T_82544, /* i82544 */ 241 WM_T_82540, /* i82540 */ 242 WM_T_82545, /* i82545 */ 243 WM_T_82545_3, /* i82545 3.0+ */ 244 WM_T_82546, /* i82546 */ 245 WM_T_82546_3, /* i82546 3.0+ */ 246 WM_T_82541, /* i82541 */ 247 WM_T_82541_2, /* i82541 2.0+ */ 248 WM_T_82547, /* i82547 */ 249 WM_T_82547_2, /* i82547 2.0+ */ 250 WM_T_82571, /* i82571 */ 251 WM_T_82572, /* i82572 */ 252 WM_T_82573, /* i82573 */ 253 WM_T_80003, /* i80003 */ 254 WM_T_ICH8, /* ICH8 LAN */ 255 WM_T_ICH9, /* ICH9 LAN */ 256 } wm_chip_type; 257 258 /* 259 * Software state per device. 260 */ 261 struct wm_softc { 262 struct device sc_dev; /* generic device information */ 263 bus_space_tag_t sc_st; /* bus space tag */ 264 bus_space_handle_t sc_sh; /* bus space handle */ 265 bus_space_tag_t sc_iot; /* I/O space tag */ 266 bus_space_handle_t sc_ioh; /* I/O space handle */ 267 bus_space_tag_t sc_flasht; /* flash registers space tag */ 268 bus_space_handle_t sc_flashh; /* flash registers space handle */ 269 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 270 struct ethercom sc_ethercom; /* ethernet common data */ 271 void *sc_sdhook; /* shutdown hook */ 272 void *sc_powerhook; /* power hook */ 273 pci_chipset_tag_t sc_pc; 274 pcitag_t sc_pcitag; 275 struct pci_conf_state sc_pciconf; 276 277 wm_chip_type sc_type; /* chip type */ 278 int sc_flags; /* flags; see below */ 279 int sc_bus_speed; /* PCI/PCIX bus speed */ 280 int sc_pcix_offset; /* PCIX capability register offset */ 281 int sc_flowflags; /* 802.3x flow control flags */ 282 283 void *sc_ih; /* interrupt cookie */ 284 285 int sc_ee_addrbits; /* EEPROM address bits */ 286 287 struct mii_data sc_mii; /* MII/media information */ 288 289 callout_t sc_tick_ch; /* tick callout */ 290 291 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 292 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 293 294 int sc_align_tweak; 295 296 /* 297 * Software state for the transmit and receive descriptors. 298 */ 299 int sc_txnum; /* must be a power of two */ 300 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 301 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 302 303 /* 304 * Control data structures. 305 */ 306 int sc_ntxdesc; /* must be a power of two */ 307 struct wm_control_data_82544 *sc_control_data; 308 #define sc_txdescs sc_control_data->wcd_txdescs 309 #define sc_rxdescs sc_control_data->wcd_rxdescs 310 311 #ifdef WM_EVENT_COUNTERS 312 /* Event counters. */ 313 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 314 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 315 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 316 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 317 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 318 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 319 struct evcnt sc_ev_linkintr; /* Link interrupts */ 320 321 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 322 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 323 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 324 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 325 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 326 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound (IPv4) */ 327 struct evcnt sc_ev_txtso6; /* TCP seg offload out-bound (IPv6) */ 328 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 329 330 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 331 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 332 333 struct evcnt sc_ev_tu; /* Tx underrun */ 334 335 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 336 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 337 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 338 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 339 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 340 #endif /* WM_EVENT_COUNTERS */ 341 342 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 343 344 int sc_txfree; /* number of free Tx descriptors */ 345 int sc_txnext; /* next ready Tx descriptor */ 346 347 int sc_txsfree; /* number of free Tx jobs */ 348 int sc_txsnext; /* next free Tx job */ 349 int sc_txsdirty; /* dirty Tx jobs */ 350 351 /* These 5 variables are used only on the 82547. */ 352 int sc_txfifo_size; /* Tx FIFO size */ 353 int sc_txfifo_head; /* current head of FIFO */ 354 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 355 int sc_txfifo_stall; /* Tx FIFO is stalled */ 356 callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 357 358 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 359 360 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 361 int sc_rxdiscard; 362 int sc_rxlen; 363 struct mbuf *sc_rxhead; 364 struct mbuf *sc_rxtail; 365 struct mbuf **sc_rxtailp; 366 367 uint32_t sc_ctrl; /* prototype CTRL register */ 368 #if 0 369 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 370 #endif 371 uint32_t sc_icr; /* prototype interrupt bits */ 372 uint32_t sc_itr; /* prototype intr throttling reg */ 373 uint32_t sc_tctl; /* prototype TCTL register */ 374 uint32_t sc_rctl; /* prototype RCTL register */ 375 uint32_t sc_txcw; /* prototype TXCW register */ 376 uint32_t sc_tipg; /* prototype TIPG register */ 377 uint32_t sc_fcrtl; /* prototype FCRTL register */ 378 uint32_t sc_pba; /* prototype PBA register */ 379 380 int sc_tbi_linkup; /* TBI link status */ 381 int sc_tbi_anstate; /* autonegotiation state */ 382 383 int sc_mchash_type; /* multicast filter offset */ 384 385 #if NRND > 0 386 rndsource_element_t rnd_source; /* random source */ 387 #endif 388 int sc_ich8_flash_base; 389 int sc_ich8_flash_bank_size; 390 }; 391 392 #define WM_RXCHAIN_RESET(sc) \ 393 do { \ 394 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 395 *(sc)->sc_rxtailp = NULL; \ 396 (sc)->sc_rxlen = 0; \ 397 } while (/*CONSTCOND*/0) 398 399 #define WM_RXCHAIN_LINK(sc, m) \ 400 do { \ 401 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 402 (sc)->sc_rxtailp = &(m)->m_next; \ 403 } while (/*CONSTCOND*/0) 404 405 /* sc_flags */ 406 #define WM_F_HAS_MII 0x0001 /* has MII */ 407 #define WM_F_EEPROM_HANDSHAKE 0x0002 /* requires EEPROM handshake */ 408 #define WM_F_EEPROM_SEMAPHORE 0x0004 /* EEPROM with semaphore */ 409 #define WM_F_EEPROM_EERDEEWR 0x0008 /* EEPROM access via EERD/EEWR */ 410 #define WM_F_EEPROM_SPI 0x0010 /* EEPROM is SPI */ 411 #define WM_F_EEPROM_FLASH 0x0020 /* EEPROM is FLASH */ 412 #define WM_F_EEPROM_INVALID 0x0040 /* EEPROM not present (bad checksum) */ 413 #define WM_F_IOH_VALID 0x0080 /* I/O handle is valid */ 414 #define WM_F_BUS64 0x0100 /* bus is 64-bit */ 415 #define WM_F_PCIX 0x0200 /* bus is PCI-X */ 416 #define WM_F_CSA 0x0400 /* bus is CSA */ 417 #define WM_F_PCIE 0x0800 /* bus is PCI-Express */ 418 #define WM_F_SWFW_SYNC 0x1000 /* Software-Firmware synchronisation */ 419 #define WM_F_SWFWHW_SYNC 0x2000 /* Software-Firmware synchronisation */ 420 421 #ifdef WM_EVENT_COUNTERS 422 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 423 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 424 #else 425 #define WM_EVCNT_INCR(ev) /* nothing */ 426 #define WM_EVCNT_ADD(ev, val) /* nothing */ 427 #endif 428 429 #define CSR_READ(sc, reg) \ 430 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 431 #define CSR_WRITE(sc, reg, val) \ 432 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 433 #define CSR_WRITE_FLUSH(sc) \ 434 (void) CSR_READ((sc), WMREG_STATUS) 435 436 #define ICH8_FLASH_READ32(sc, reg) \ 437 bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg)) 438 #define ICH8_FLASH_WRITE32(sc, reg, data) \ 439 bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) 440 441 #define ICH8_FLASH_READ16(sc, reg) \ 442 bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg)) 443 #define ICH8_FLASH_WRITE16(sc, reg, data) \ 444 bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data)) 445 446 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 447 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 448 449 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 450 #define WM_CDTXADDR_HI(sc, x) \ 451 (sizeof(bus_addr_t) == 8 ? \ 452 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 453 454 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 455 #define WM_CDRXADDR_HI(sc, x) \ 456 (sizeof(bus_addr_t) == 8 ? \ 457 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 458 459 #define WM_CDTXSYNC(sc, x, n, ops) \ 460 do { \ 461 int __x, __n; \ 462 \ 463 __x = (x); \ 464 __n = (n); \ 465 \ 466 /* If it will wrap around, sync to the end of the ring. */ \ 467 if ((__x + __n) > WM_NTXDESC(sc)) { \ 468 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 469 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 470 (WM_NTXDESC(sc) - __x), (ops)); \ 471 __n -= (WM_NTXDESC(sc) - __x); \ 472 __x = 0; \ 473 } \ 474 \ 475 /* Now sync whatever is left. */ \ 476 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 477 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 478 } while (/*CONSTCOND*/0) 479 480 #define WM_CDRXSYNC(sc, x, ops) \ 481 do { \ 482 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 483 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 484 } while (/*CONSTCOND*/0) 485 486 #define WM_INIT_RXDESC(sc, x) \ 487 do { \ 488 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 489 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 490 struct mbuf *__m = __rxs->rxs_mbuf; \ 491 \ 492 /* \ 493 * Note: We scoot the packet forward 2 bytes in the buffer \ 494 * so that the payload after the Ethernet header is aligned \ 495 * to a 4-byte boundary. \ 496 * \ 497 * XXX BRAINDAMAGE ALERT! \ 498 * The stupid chip uses the same size for every buffer, which \ 499 * is set in the Receive Control register. We are using the 2K \ 500 * size option, but what we REALLY want is (2K - 2)! For this \ 501 * reason, we can't "scoot" packets longer than the standard \ 502 * Ethernet MTU. On strict-alignment platforms, if the total \ 503 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 504 * the upper layer copy the headers. \ 505 */ \ 506 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 507 \ 508 wm_set_dma_addr(&__rxd->wrx_addr, \ 509 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 510 __rxd->wrx_len = 0; \ 511 __rxd->wrx_cksum = 0; \ 512 __rxd->wrx_status = 0; \ 513 __rxd->wrx_errors = 0; \ 514 __rxd->wrx_special = 0; \ 515 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 516 \ 517 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 518 } while (/*CONSTCOND*/0) 519 520 static void wm_start(struct ifnet *); 521 static void wm_watchdog(struct ifnet *); 522 static int wm_ioctl(struct ifnet *, u_long, void *); 523 static int wm_init(struct ifnet *); 524 static void wm_stop(struct ifnet *, int); 525 526 static void wm_shutdown(void *); 527 static void wm_powerhook(int, void *); 528 529 static void wm_reset(struct wm_softc *); 530 static void wm_rxdrain(struct wm_softc *); 531 static int wm_add_rxbuf(struct wm_softc *, int); 532 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 533 static int wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *); 534 static int wm_validate_eeprom_checksum(struct wm_softc *); 535 static void wm_tick(void *); 536 537 static void wm_set_filter(struct wm_softc *); 538 539 static int wm_intr(void *); 540 static void wm_txintr(struct wm_softc *); 541 static void wm_rxintr(struct wm_softc *); 542 static void wm_linkintr(struct wm_softc *, uint32_t); 543 544 static void wm_tbi_mediainit(struct wm_softc *); 545 static int wm_tbi_mediachange(struct ifnet *); 546 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 547 548 static void wm_tbi_set_linkled(struct wm_softc *); 549 static void wm_tbi_check_link(struct wm_softc *); 550 551 static void wm_gmii_reset(struct wm_softc *); 552 553 static int wm_gmii_i82543_readreg(struct device *, int, int); 554 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 555 556 static int wm_gmii_i82544_readreg(struct device *, int, int); 557 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 558 559 static int wm_gmii_i80003_readreg(struct device *, int, int); 560 static void wm_gmii_i80003_writereg(struct device *, int, int, int); 561 562 static void wm_gmii_statchg(struct device *); 563 564 static void wm_gmii_mediainit(struct wm_softc *); 565 static int wm_gmii_mediachange(struct ifnet *); 566 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 567 568 static int wm_kmrn_i80003_readreg(struct wm_softc *, int); 569 static void wm_kmrn_i80003_writereg(struct wm_softc *, int, int); 570 571 static int wm_match(struct device *, struct cfdata *, void *); 572 static void wm_attach(struct device *, struct device *, void *); 573 static int wm_is_onboard_nvm_eeprom(struct wm_softc *); 574 static void wm_get_auto_rd_dome(struct wm_softc *); 575 static int wm_get_swsm_semaphore(struct wm_softc *); 576 static void wm_put_swsm_semaphore(struct wm_softc *); 577 static int wm_poll_eerd_eewr_done(struct wm_softc *, int); 578 static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t); 579 static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t); 580 static int wm_get_swfwhw_semaphore(struct wm_softc *); 581 static void wm_put_swfwhw_semaphore(struct wm_softc *); 582 583 static int wm_read_eeprom_ich8(struct wm_softc *, int, int, uint16_t *); 584 static int32_t wm_ich8_cycle_init(struct wm_softc *); 585 static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t); 586 static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, 587 uint32_t, uint16_t *); 588 static int32_t wm_read_ich8_word(struct wm_softc *sc, uint32_t, uint16_t *); 589 590 CFATTACH_DECL(wm, sizeof(struct wm_softc), 591 wm_match, wm_attach, NULL, NULL); 592 593 static void wm_82547_txfifo_stall(void *); 594 595 /* 596 * Devices supported by this driver. 597 */ 598 static const struct wm_product { 599 pci_vendor_id_t wmp_vendor; 600 pci_product_id_t wmp_product; 601 const char *wmp_name; 602 wm_chip_type wmp_type; 603 int wmp_flags; 604 #define WMP_F_1000X 0x01 605 #define WMP_F_1000T 0x02 606 } wm_products[] = { 607 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 608 "Intel i82542 1000BASE-X Ethernet", 609 WM_T_82542_2_1, WMP_F_1000X }, 610 611 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 612 "Intel i82543GC 1000BASE-X Ethernet", 613 WM_T_82543, WMP_F_1000X }, 614 615 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 616 "Intel i82543GC 1000BASE-T Ethernet", 617 WM_T_82543, WMP_F_1000T }, 618 619 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 620 "Intel i82544EI 1000BASE-T Ethernet", 621 WM_T_82544, WMP_F_1000T }, 622 623 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 624 "Intel i82544EI 1000BASE-X Ethernet", 625 WM_T_82544, WMP_F_1000X }, 626 627 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 628 "Intel i82544GC 1000BASE-T Ethernet", 629 WM_T_82544, WMP_F_1000T }, 630 631 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 632 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 633 WM_T_82544, WMP_F_1000T }, 634 635 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 636 "Intel i82540EM 1000BASE-T Ethernet", 637 WM_T_82540, WMP_F_1000T }, 638 639 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 640 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 641 WM_T_82540, WMP_F_1000T }, 642 643 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 644 "Intel i82540EP 1000BASE-T Ethernet", 645 WM_T_82540, WMP_F_1000T }, 646 647 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 648 "Intel i82540EP 1000BASE-T Ethernet", 649 WM_T_82540, WMP_F_1000T }, 650 651 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 652 "Intel i82540EP 1000BASE-T Ethernet", 653 WM_T_82540, WMP_F_1000T }, 654 655 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 656 "Intel i82545EM 1000BASE-T Ethernet", 657 WM_T_82545, WMP_F_1000T }, 658 659 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 660 "Intel i82545GM 1000BASE-T Ethernet", 661 WM_T_82545_3, WMP_F_1000T }, 662 663 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 664 "Intel i82545GM 1000BASE-X Ethernet", 665 WM_T_82545_3, WMP_F_1000X }, 666 #if 0 667 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 668 "Intel i82545GM Gigabit Ethernet (SERDES)", 669 WM_T_82545_3, WMP_F_SERDES }, 670 #endif 671 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 672 "Intel i82546EB 1000BASE-T Ethernet", 673 WM_T_82546, WMP_F_1000T }, 674 675 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 676 "Intel i82546EB 1000BASE-T Ethernet", 677 WM_T_82546, WMP_F_1000T }, 678 679 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 680 "Intel i82545EM 1000BASE-X Ethernet", 681 WM_T_82545, WMP_F_1000X }, 682 683 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 684 "Intel i82546EB 1000BASE-X Ethernet", 685 WM_T_82546, WMP_F_1000X }, 686 687 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 688 "Intel i82546GB 1000BASE-T Ethernet", 689 WM_T_82546_3, WMP_F_1000T }, 690 691 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 692 "Intel i82546GB 1000BASE-X Ethernet", 693 WM_T_82546_3, WMP_F_1000X }, 694 #if 0 695 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 696 "Intel i82546GB Gigabit Ethernet (SERDES)", 697 WM_T_82546_3, WMP_F_SERDES }, 698 #endif 699 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER, 700 "i82546GB quad-port Gigabit Ethernet", 701 WM_T_82546_3, WMP_F_1000T }, 702 703 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3, 704 "i82546GB quad-port Gigabit Ethernet (KSP3)", 705 WM_T_82546_3, WMP_F_1000T }, 706 707 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, 708 "Intel PRO/1000MT (82546GB)", 709 WM_T_82546_3, WMP_F_1000T }, 710 711 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 712 "Intel i82541EI 1000BASE-T Ethernet", 713 WM_T_82541, WMP_F_1000T }, 714 715 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, 716 "Intel i82541ER (LOM) 1000BASE-T Ethernet", 717 WM_T_82541, WMP_F_1000T }, 718 719 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 720 "Intel i82541EI Mobile 1000BASE-T Ethernet", 721 WM_T_82541, WMP_F_1000T }, 722 723 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 724 "Intel i82541ER 1000BASE-T Ethernet", 725 WM_T_82541_2, WMP_F_1000T }, 726 727 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 728 "Intel i82541GI 1000BASE-T Ethernet", 729 WM_T_82541_2, WMP_F_1000T }, 730 731 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 732 "Intel i82541GI Mobile 1000BASE-T Ethernet", 733 WM_T_82541_2, WMP_F_1000T }, 734 735 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 736 "Intel i82541PI 1000BASE-T Ethernet", 737 WM_T_82541_2, WMP_F_1000T }, 738 739 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 740 "Intel i82547EI 1000BASE-T Ethernet", 741 WM_T_82547, WMP_F_1000T }, 742 743 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, 744 "Intel i82547EI Mobile 1000BASE-T Ethernet", 745 WM_T_82547, WMP_F_1000T }, 746 747 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 748 "Intel i82547GI 1000BASE-T Ethernet", 749 WM_T_82547_2, WMP_F_1000T }, 750 751 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, 752 "Intel PRO/1000 PT (82571EB)", 753 WM_T_82571, WMP_F_1000T }, 754 755 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, 756 "Intel PRO/1000 PF (82571EB)", 757 WM_T_82571, WMP_F_1000X }, 758 #if 0 759 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, 760 "Intel PRO/1000 PB (82571EB)", 761 WM_T_82571, WMP_F_SERDES }, 762 #endif 763 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER, 764 "Intel PRO/1000 QT (82571EB)", 765 WM_T_82571, WMP_F_1000T }, 766 767 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, 768 "Intel i82572EI 1000baseT Ethernet", 769 WM_T_82572, WMP_F_1000T }, 770 771 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, 772 "Intel i82572EI 1000baseX Ethernet", 773 WM_T_82572, WMP_F_1000X }, 774 #if 0 775 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, 776 "Intel i82572EI Gigabit Ethernet (SERDES)", 777 WM_T_82572, WMP_F_SERDES }, 778 #endif 779 780 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, 781 "Intel i82572EI 1000baseT Ethernet", 782 WM_T_82572, WMP_F_1000T }, 783 784 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, 785 "Intel i82573E", 786 WM_T_82573, WMP_F_1000T }, 787 788 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, 789 "Intel i82573E IAMT", 790 WM_T_82573, WMP_F_1000T }, 791 792 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, 793 "Intel i82573L Gigabit Ethernet", 794 WM_T_82573, WMP_F_1000T }, 795 796 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT, 797 "i80003 dual 1000baseT Ethernet", 798 WM_T_80003, WMP_F_1000T }, 799 800 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT, 801 "i80003 dual 1000baseX Ethernet", 802 WM_T_80003, WMP_F_1000T }, 803 #if 0 804 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT, 805 "Intel i80003ES2 dual Gigabit Ethernet (SERDES)", 806 WM_T_80003, WMP_F_SERDES }, 807 #endif 808 809 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT, 810 "Intel i80003 1000baseT Ethernet", 811 WM_T_80003, WMP_F_1000T }, 812 #if 0 813 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT, 814 "Intel i80003 Gigabit Ethernet (SERDES)", 815 WM_T_80003, WMP_F_SERDES }, 816 #endif 817 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT, 818 "Intel i82801H (M_AMT) LAN Controller", 819 WM_T_ICH8, WMP_F_1000T }, 820 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT, 821 "Intel i82801H (AMT) LAN Controller", 822 WM_T_ICH8, WMP_F_1000T }, 823 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN, 824 "Intel i82801H LAN Controller", 825 WM_T_ICH8, WMP_F_1000T }, 826 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN, 827 "Intel i82801H (IFE) LAN Controller", 828 WM_T_ICH8, WMP_F_1000T }, 829 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN, 830 "Intel i82801H (M) LAN Controller", 831 WM_T_ICH8, WMP_F_1000T }, 832 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT, 833 "Intel i82801H IFE (GT) LAN Controller", 834 WM_T_ICH8, WMP_F_1000T }, 835 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G, 836 "Intel i82801H IFE (G) LAN Controller", 837 WM_T_ICH8, WMP_F_1000T }, 838 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT, 839 "82801I (AMT) LAN Controller", 840 WM_T_ICH9, WMP_F_1000T }, 841 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE, 842 "82801I LAN Controller", 843 WM_T_ICH9, WMP_F_1000T }, 844 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G, 845 "82801I (G) LAN Controller", 846 WM_T_ICH9, WMP_F_1000T }, 847 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT, 848 "82801I (GT) LAN Controller", 849 WM_T_ICH9, WMP_F_1000T }, 850 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C, 851 "82801I (C) LAN Controller", 852 WM_T_ICH9, WMP_F_1000T }, 853 { 0, 0, 854 NULL, 855 0, 0 }, 856 }; 857 858 #ifdef WM_EVENT_COUNTERS 859 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 860 #endif /* WM_EVENT_COUNTERS */ 861 862 #if 0 /* Not currently used */ 863 static inline uint32_t 864 wm_io_read(struct wm_softc *sc, int reg) 865 { 866 867 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 868 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 869 } 870 #endif 871 872 static inline void 873 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 874 { 875 876 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 877 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 878 } 879 880 static inline void 881 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 882 { 883 wa->wa_low = htole32(v & 0xffffffffU); 884 if (sizeof(bus_addr_t) == 8) 885 wa->wa_high = htole32((uint64_t) v >> 32); 886 else 887 wa->wa_high = 0; 888 } 889 890 static const struct wm_product * 891 wm_lookup(const struct pci_attach_args *pa) 892 { 893 const struct wm_product *wmp; 894 895 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 896 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 897 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 898 return (wmp); 899 } 900 return (NULL); 901 } 902 903 static int 904 wm_match(struct device *parent, struct cfdata *cf, void *aux) 905 { 906 struct pci_attach_args *pa = aux; 907 908 if (wm_lookup(pa) != NULL) 909 return (1); 910 911 return (0); 912 } 913 914 static void 915 wm_attach(struct device *parent, struct device *self, void *aux) 916 { 917 struct wm_softc *sc = (void *) self; 918 struct pci_attach_args *pa = aux; 919 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 920 pci_chipset_tag_t pc = pa->pa_pc; 921 pci_intr_handle_t ih; 922 size_t cdata_size; 923 const char *intrstr = NULL; 924 const char *eetype; 925 bus_space_tag_t memt; 926 bus_space_handle_t memh; 927 bus_dma_segment_t seg; 928 int memh_valid; 929 int i, rseg, error; 930 const struct wm_product *wmp; 931 prop_data_t ea; 932 prop_number_t pn; 933 uint8_t enaddr[ETHER_ADDR_LEN]; 934 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 935 pcireg_t preg, memtype; 936 uint32_t reg; 937 938 callout_init(&sc->sc_tick_ch, 0); 939 940 wmp = wm_lookup(pa); 941 if (wmp == NULL) { 942 printf("\n"); 943 panic("wm_attach: impossible"); 944 } 945 946 sc->sc_pc = pa->pa_pc; 947 sc->sc_pcitag = pa->pa_tag; 948 949 if (pci_dma64_available(pa)) 950 sc->sc_dmat = pa->pa_dmat64; 951 else 952 sc->sc_dmat = pa->pa_dmat; 953 954 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 955 aprint_naive(": Ethernet controller\n"); 956 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 957 958 sc->sc_type = wmp->wmp_type; 959 if (sc->sc_type < WM_T_82543) { 960 if (preg < 2) { 961 aprint_error("%s: i82542 must be at least rev. 2\n", 962 sc->sc_dev.dv_xname); 963 return; 964 } 965 if (preg < 3) 966 sc->sc_type = WM_T_82542_2_0; 967 } 968 969 /* 970 * Map the device. All devices support memory-mapped acccess, 971 * and it is really required for normal operation. 972 */ 973 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 974 switch (memtype) { 975 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 976 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 977 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 978 memtype, 0, &memt, &memh, NULL, NULL) == 0); 979 break; 980 default: 981 memh_valid = 0; 982 } 983 984 if (memh_valid) { 985 sc->sc_st = memt; 986 sc->sc_sh = memh; 987 } else { 988 aprint_error("%s: unable to map device registers\n", 989 sc->sc_dev.dv_xname); 990 return; 991 } 992 993 /* 994 * In addition, i82544 and later support I/O mapped indirect 995 * register access. It is not desirable (nor supported in 996 * this driver) to use it for normal operation, though it is 997 * required to work around bugs in some chip versions. 998 */ 999 if (sc->sc_type >= WM_T_82544) { 1000 /* First we have to find the I/O BAR. */ 1001 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 1002 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 1003 PCI_MAPREG_TYPE_IO) 1004 break; 1005 } 1006 if (i == PCI_MAPREG_END) 1007 aprint_error("%s: WARNING: unable to find I/O BAR\n", 1008 sc->sc_dev.dv_xname); 1009 else { 1010 /* 1011 * The i8254x doesn't apparently respond when the 1012 * I/O BAR is 0, which looks somewhat like it's not 1013 * been configured. 1014 */ 1015 preg = pci_conf_read(pc, pa->pa_tag, i); 1016 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 1017 aprint_error("%s: WARNING: I/O BAR at zero.\n", 1018 sc->sc_dev.dv_xname); 1019 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 1020 0, &sc->sc_iot, &sc->sc_ioh, 1021 NULL, NULL) == 0) { 1022 sc->sc_flags |= WM_F_IOH_VALID; 1023 } else { 1024 aprint_error("%s: WARNING: unable to map " 1025 "I/O space\n", sc->sc_dev.dv_xname); 1026 } 1027 } 1028 1029 } 1030 1031 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 1032 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1033 preg |= PCI_COMMAND_MASTER_ENABLE; 1034 if (sc->sc_type < WM_T_82542_2_1) 1035 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 1036 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 1037 1038 /* power up chip */ 1039 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 1040 NULL)) && error != EOPNOTSUPP) { 1041 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 1042 error); 1043 return; 1044 } 1045 1046 /* 1047 * Map and establish our interrupt. 1048 */ 1049 if (pci_intr_map(pa, &ih)) { 1050 aprint_error("%s: unable to map interrupt\n", 1051 sc->sc_dev.dv_xname); 1052 return; 1053 } 1054 intrstr = pci_intr_string(pc, ih); 1055 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 1056 if (sc->sc_ih == NULL) { 1057 aprint_error("%s: unable to establish interrupt", 1058 sc->sc_dev.dv_xname); 1059 if (intrstr != NULL) 1060 aprint_normal(" at %s", intrstr); 1061 aprint_normal("\n"); 1062 return; 1063 } 1064 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1065 1066 /* 1067 * Determine a few things about the bus we're connected to. 1068 */ 1069 if (sc->sc_type < WM_T_82543) { 1070 /* We don't really know the bus characteristics here. */ 1071 sc->sc_bus_speed = 33; 1072 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 1073 /* 1074 * CSA (Communication Streaming Architecture) is about as fast 1075 * a 32-bit 66MHz PCI Bus. 1076 */ 1077 sc->sc_flags |= WM_F_CSA; 1078 sc->sc_bus_speed = 66; 1079 aprint_verbose("%s: Communication Streaming Architecture\n", 1080 sc->sc_dev.dv_xname); 1081 if (sc->sc_type == WM_T_82547) { 1082 callout_init(&sc->sc_txfifo_ch, 0); 1083 callout_setfunc(&sc->sc_txfifo_ch, 1084 wm_82547_txfifo_stall, sc); 1085 aprint_verbose("%s: using 82547 Tx FIFO stall " 1086 "work-around\n", sc->sc_dev.dv_xname); 1087 } 1088 } else if (sc->sc_type >= WM_T_82571) { 1089 sc->sc_flags |= WM_F_PCIE; 1090 if ((sc->sc_type != WM_T_ICH8) || (sc->sc_type != WM_T_ICH9)) 1091 sc->sc_flags |= WM_F_EEPROM_SEMAPHORE; 1092 aprint_verbose("%s: PCI-Express bus\n", sc->sc_dev.dv_xname); 1093 } else { 1094 reg = CSR_READ(sc, WMREG_STATUS); 1095 if (reg & STATUS_BUS64) 1096 sc->sc_flags |= WM_F_BUS64; 1097 if (sc->sc_type >= WM_T_82544 && 1098 (reg & STATUS_PCIX_MODE) != 0) { 1099 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 1100 1101 sc->sc_flags |= WM_F_PCIX; 1102 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1103 PCI_CAP_PCIX, 1104 &sc->sc_pcix_offset, NULL) == 0) 1105 aprint_error("%s: unable to find PCIX " 1106 "capability\n", sc->sc_dev.dv_xname); 1107 else if (sc->sc_type != WM_T_82545_3 && 1108 sc->sc_type != WM_T_82546_3) { 1109 /* 1110 * Work around a problem caused by the BIOS 1111 * setting the max memory read byte count 1112 * incorrectly. 1113 */ 1114 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 1115 sc->sc_pcix_offset + PCI_PCIX_CMD); 1116 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 1117 sc->sc_pcix_offset + PCI_PCIX_STATUS); 1118 1119 bytecnt = 1120 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 1121 PCI_PCIX_CMD_BYTECNT_SHIFT; 1122 maxb = 1123 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 1124 PCI_PCIX_STATUS_MAXB_SHIFT; 1125 if (bytecnt > maxb) { 1126 aprint_verbose("%s: resetting PCI-X " 1127 "MMRBC: %d -> %d\n", 1128 sc->sc_dev.dv_xname, 1129 512 << bytecnt, 512 << maxb); 1130 pcix_cmd = (pcix_cmd & 1131 ~PCI_PCIX_CMD_BYTECNT_MASK) | 1132 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 1133 pci_conf_write(pa->pa_pc, pa->pa_tag, 1134 sc->sc_pcix_offset + PCI_PCIX_CMD, 1135 pcix_cmd); 1136 } 1137 } 1138 } 1139 /* 1140 * The quad port adapter is special; it has a PCIX-PCIX 1141 * bridge on the board, and can run the secondary bus at 1142 * a higher speed. 1143 */ 1144 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 1145 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 1146 : 66; 1147 } else if (sc->sc_flags & WM_F_PCIX) { 1148 switch (reg & STATUS_PCIXSPD_MASK) { 1149 case STATUS_PCIXSPD_50_66: 1150 sc->sc_bus_speed = 66; 1151 break; 1152 case STATUS_PCIXSPD_66_100: 1153 sc->sc_bus_speed = 100; 1154 break; 1155 case STATUS_PCIXSPD_100_133: 1156 sc->sc_bus_speed = 133; 1157 break; 1158 default: 1159 aprint_error( 1160 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 1161 sc->sc_dev.dv_xname, 1162 reg & STATUS_PCIXSPD_MASK); 1163 sc->sc_bus_speed = 66; 1164 } 1165 } else 1166 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 1167 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 1168 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 1169 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 1170 } 1171 1172 /* 1173 * Allocate the control data structures, and create and load the 1174 * DMA map for it. 1175 * 1176 * NOTE: All Tx descriptors must be in the same 4G segment of 1177 * memory. So must Rx descriptors. We simplify by allocating 1178 * both sets within the same 4G segment. 1179 */ 1180 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 1181 WM_NTXDESC_82542 : WM_NTXDESC_82544; 1182 cdata_size = sc->sc_type < WM_T_82544 ? 1183 sizeof(struct wm_control_data_82542) : 1184 sizeof(struct wm_control_data_82544); 1185 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 1186 (bus_size_t) 0x100000000ULL, 1187 &seg, 1, &rseg, 0)) != 0) { 1188 aprint_error( 1189 "%s: unable to allocate control data, error = %d\n", 1190 sc->sc_dev.dv_xname, error); 1191 goto fail_0; 1192 } 1193 1194 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 1195 (void **)&sc->sc_control_data, 0)) != 0) { 1196 aprint_error("%s: unable to map control data, error = %d\n", 1197 sc->sc_dev.dv_xname, error); 1198 goto fail_1; 1199 } 1200 1201 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 1202 0, 0, &sc->sc_cddmamap)) != 0) { 1203 aprint_error("%s: unable to create control data DMA map, " 1204 "error = %d\n", sc->sc_dev.dv_xname, error); 1205 goto fail_2; 1206 } 1207 1208 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1209 sc->sc_control_data, cdata_size, NULL, 1210 0)) != 0) { 1211 aprint_error( 1212 "%s: unable to load control data DMA map, error = %d\n", 1213 sc->sc_dev.dv_xname, error); 1214 goto fail_3; 1215 } 1216 1217 1218 /* 1219 * Create the transmit buffer DMA maps. 1220 */ 1221 WM_TXQUEUELEN(sc) = 1222 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 1223 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 1224 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1225 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 1226 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1227 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1228 aprint_error("%s: unable to create Tx DMA map %d, " 1229 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1230 goto fail_4; 1231 } 1232 } 1233 1234 /* 1235 * Create the receive buffer DMA maps. 1236 */ 1237 for (i = 0; i < WM_NRXDESC; i++) { 1238 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1239 MCLBYTES, 0, 0, 1240 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1241 aprint_error("%s: unable to create Rx DMA map %d, " 1242 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1243 goto fail_5; 1244 } 1245 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1246 } 1247 1248 /* clear interesting stat counters */ 1249 CSR_READ(sc, WMREG_COLC); 1250 CSR_READ(sc, WMREG_RXERRC); 1251 1252 /* 1253 * Reset the chip to a known state. 1254 */ 1255 wm_reset(sc); 1256 1257 /* 1258 * Get some information about the EEPROM. 1259 */ 1260 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)) { 1261 uint32_t flash_size; 1262 sc->sc_flags |= WM_F_SWFWHW_SYNC | WM_F_EEPROM_FLASH; 1263 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH); 1264 if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0, 1265 &sc->sc_flasht, &sc->sc_flashh, NULL, NULL)) { 1266 printf("%s: can't map FLASH registers\n", 1267 sc->sc_dev.dv_xname); 1268 return; 1269 } 1270 flash_size = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG); 1271 sc->sc_ich8_flash_base = (flash_size & ICH_GFPREG_BASE_MASK) * 1272 ICH_FLASH_SECTOR_SIZE; 1273 sc->sc_ich8_flash_bank_size = 1274 ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; 1275 sc->sc_ich8_flash_bank_size -= 1276 (flash_size & ICH_GFPREG_BASE_MASK); 1277 sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 1278 sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t); 1279 } else if (sc->sc_type == WM_T_80003) 1280 sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_SWFW_SYNC; 1281 else if (sc->sc_type == WM_T_82573) 1282 sc->sc_flags |= WM_F_EEPROM_EERDEEWR; 1283 else if (sc->sc_type > WM_T_82544) 1284 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1285 1286 if (sc->sc_type <= WM_T_82544) 1287 sc->sc_ee_addrbits = 6; 1288 else if (sc->sc_type <= WM_T_82546_3) { 1289 reg = CSR_READ(sc, WMREG_EECD); 1290 if (reg & EECD_EE_SIZE) 1291 sc->sc_ee_addrbits = 8; 1292 else 1293 sc->sc_ee_addrbits = 6; 1294 } else if (sc->sc_type <= WM_T_82547_2) { 1295 reg = CSR_READ(sc, WMREG_EECD); 1296 if (reg & EECD_EE_TYPE) { 1297 sc->sc_flags |= WM_F_EEPROM_SPI; 1298 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1299 } else 1300 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1301 } else if ((sc->sc_type == WM_T_82573) && 1302 (wm_is_onboard_nvm_eeprom(sc) == 0)) { 1303 sc->sc_flags |= WM_F_EEPROM_FLASH; 1304 } else { 1305 /* Assume everything else is SPI. */ 1306 reg = CSR_READ(sc, WMREG_EECD); 1307 sc->sc_flags |= WM_F_EEPROM_SPI; 1308 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1309 } 1310 1311 /* 1312 * Defer printing the EEPROM type until after verifying the checksum 1313 * This allows the EEPROM type to be printed correctly in the case 1314 * that no EEPROM is attached. 1315 */ 1316 1317 1318 /* 1319 * Validate the EEPROM checksum. If the checksum fails, flag this for 1320 * later, so we can fail future reads from the EEPROM. 1321 */ 1322 if (wm_validate_eeprom_checksum(sc)) 1323 sc->sc_flags |= WM_F_EEPROM_INVALID; 1324 1325 if (sc->sc_flags & WM_F_EEPROM_INVALID) 1326 aprint_verbose("%s: No EEPROM\n", sc->sc_dev.dv_xname); 1327 else if (sc->sc_flags & WM_F_EEPROM_FLASH) { 1328 aprint_verbose("%s: FLASH\n", sc->sc_dev.dv_xname); 1329 } else { 1330 if (sc->sc_flags & WM_F_EEPROM_SPI) 1331 eetype = "SPI"; 1332 else 1333 eetype = "MicroWire"; 1334 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1335 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1336 sc->sc_ee_addrbits, eetype); 1337 } 1338 1339 /* 1340 * Read the Ethernet address from the EEPROM, if not first found 1341 * in device properties. 1342 */ 1343 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 1344 if (ea != NULL) { 1345 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 1346 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 1347 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 1348 } else { 1349 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1350 sizeof(myea) / sizeof(myea[0]), myea)) { 1351 aprint_error("%s: unable to read Ethernet address\n", 1352 sc->sc_dev.dv_xname); 1353 return; 1354 } 1355 enaddr[0] = myea[0] & 0xff; 1356 enaddr[1] = myea[0] >> 8; 1357 enaddr[2] = myea[1] & 0xff; 1358 enaddr[3] = myea[1] >> 8; 1359 enaddr[4] = myea[2] & 0xff; 1360 enaddr[5] = myea[2] >> 8; 1361 } 1362 1363 /* 1364 * Toggle the LSB of the MAC address on the second port 1365 * of the dual port controller. 1366 */ 1367 if (sc->sc_type == WM_T_82546 || sc->sc_type == WM_T_82546_3 1368 || sc->sc_type == WM_T_82571 || sc->sc_type == WM_T_80003) { 1369 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1370 enaddr[5] ^= 1; 1371 } 1372 1373 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1374 ether_sprintf(enaddr)); 1375 1376 /* 1377 * Read the config info from the EEPROM, and set up various 1378 * bits in the control registers based on their contents. 1379 */ 1380 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1381 "i82543-cfg1"); 1382 if (pn != NULL) { 1383 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1384 cfg1 = (uint16_t) prop_number_integer_value(pn); 1385 } else { 1386 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1387 aprint_error("%s: unable to read CFG1\n", 1388 sc->sc_dev.dv_xname); 1389 return; 1390 } 1391 } 1392 1393 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1394 "i82543-cfg2"); 1395 if (pn != NULL) { 1396 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1397 cfg2 = (uint16_t) prop_number_integer_value(pn); 1398 } else { 1399 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1400 aprint_error("%s: unable to read CFG2\n", 1401 sc->sc_dev.dv_xname); 1402 return; 1403 } 1404 } 1405 1406 if (sc->sc_type >= WM_T_82544) { 1407 pn = prop_dictionary_get(device_properties(&sc->sc_dev), 1408 "i82543-swdpin"); 1409 if (pn != NULL) { 1410 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1411 swdpin = (uint16_t) prop_number_integer_value(pn); 1412 } else { 1413 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1414 aprint_error("%s: unable to read SWDPIN\n", 1415 sc->sc_dev.dv_xname); 1416 return; 1417 } 1418 } 1419 } 1420 1421 if (cfg1 & EEPROM_CFG1_ILOS) 1422 sc->sc_ctrl |= CTRL_ILOS; 1423 if (sc->sc_type >= WM_T_82544) { 1424 sc->sc_ctrl |= 1425 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1426 CTRL_SWDPIO_SHIFT; 1427 sc->sc_ctrl |= 1428 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1429 CTRL_SWDPINS_SHIFT; 1430 } else { 1431 sc->sc_ctrl |= 1432 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1433 CTRL_SWDPIO_SHIFT; 1434 } 1435 1436 #if 0 1437 if (sc->sc_type >= WM_T_82544) { 1438 if (cfg1 & EEPROM_CFG1_IPS0) 1439 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1440 if (cfg1 & EEPROM_CFG1_IPS1) 1441 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1442 sc->sc_ctrl_ext |= 1443 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1444 CTRL_EXT_SWDPIO_SHIFT; 1445 sc->sc_ctrl_ext |= 1446 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1447 CTRL_EXT_SWDPINS_SHIFT; 1448 } else { 1449 sc->sc_ctrl_ext |= 1450 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1451 CTRL_EXT_SWDPIO_SHIFT; 1452 } 1453 #endif 1454 1455 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1456 #if 0 1457 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1458 #endif 1459 1460 /* 1461 * Set up some register offsets that are different between 1462 * the i82542 and the i82543 and later chips. 1463 */ 1464 if (sc->sc_type < WM_T_82543) { 1465 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1466 sc->sc_tdt_reg = WMREG_OLD_TDT; 1467 } else { 1468 sc->sc_rdt_reg = WMREG_RDT; 1469 sc->sc_tdt_reg = WMREG_TDT; 1470 } 1471 1472 /* 1473 * Determine if we're TBI or GMII mode, and initialize the 1474 * media structures accordingly. 1475 */ 1476 if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9 1477 || sc->sc_type == WM_T_82573) { 1478 /* STATUS_TBIMODE reserved/reused, can't rely on it */ 1479 wm_gmii_mediainit(sc); 1480 } else if (sc->sc_type < WM_T_82543 || 1481 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1482 if (wmp->wmp_flags & WMP_F_1000T) 1483 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1484 "product!\n", sc->sc_dev.dv_xname); 1485 wm_tbi_mediainit(sc); 1486 } else { 1487 if (wmp->wmp_flags & WMP_F_1000X) 1488 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1489 "product!\n", sc->sc_dev.dv_xname); 1490 wm_gmii_mediainit(sc); 1491 } 1492 1493 ifp = &sc->sc_ethercom.ec_if; 1494 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1495 ifp->if_softc = sc; 1496 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1497 ifp->if_ioctl = wm_ioctl; 1498 ifp->if_start = wm_start; 1499 ifp->if_watchdog = wm_watchdog; 1500 ifp->if_init = wm_init; 1501 ifp->if_stop = wm_stop; 1502 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1503 IFQ_SET_READY(&ifp->if_snd); 1504 1505 if (sc->sc_type != WM_T_82573 && sc->sc_type != WM_T_ICH8) 1506 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1507 1508 /* 1509 * If we're a i82543 or greater, we can support VLANs. 1510 */ 1511 if (sc->sc_type >= WM_T_82543) 1512 sc->sc_ethercom.ec_capabilities |= 1513 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1514 1515 /* 1516 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1517 * on i82543 and later. 1518 */ 1519 if (sc->sc_type >= WM_T_82543) { 1520 ifp->if_capabilities |= 1521 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1522 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1523 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1524 IFCAP_CSUM_TCPv6_Tx | 1525 IFCAP_CSUM_UDPv6_Tx; 1526 } 1527 1528 /* 1529 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL. 1530 * 1531 * 82541GI (8086:1076) ... no 1532 * 82572EI (8086:10b9) ... yes 1533 */ 1534 if (sc->sc_type >= WM_T_82571) { 1535 ifp->if_capabilities |= 1536 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1537 } 1538 1539 /* 1540 * If we're a i82544 or greater (except i82547), we can do 1541 * TCP segmentation offload. 1542 */ 1543 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) { 1544 ifp->if_capabilities |= IFCAP_TSOv4; 1545 } 1546 1547 if (sc->sc_type >= WM_T_82571) { 1548 ifp->if_capabilities |= IFCAP_TSOv6; 1549 } 1550 1551 /* 1552 * Attach the interface. 1553 */ 1554 if_attach(ifp); 1555 ether_ifattach(ifp, enaddr); 1556 #if NRND > 0 1557 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1558 RND_TYPE_NET, 0); 1559 #endif 1560 1561 #ifdef WM_EVENT_COUNTERS 1562 /* Attach event counters. */ 1563 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1564 NULL, sc->sc_dev.dv_xname, "txsstall"); 1565 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1566 NULL, sc->sc_dev.dv_xname, "txdstall"); 1567 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1568 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1569 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1570 NULL, sc->sc_dev.dv_xname, "txdw"); 1571 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1572 NULL, sc->sc_dev.dv_xname, "txqe"); 1573 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1574 NULL, sc->sc_dev.dv_xname, "rxintr"); 1575 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1576 NULL, sc->sc_dev.dv_xname, "linkintr"); 1577 1578 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1579 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1580 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1581 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1582 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1583 NULL, sc->sc_dev.dv_xname, "txipsum"); 1584 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1585 NULL, sc->sc_dev.dv_xname, "txtusum"); 1586 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 1587 NULL, sc->sc_dev.dv_xname, "txtusum6"); 1588 1589 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 1590 NULL, sc->sc_dev.dv_xname, "txtso"); 1591 evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC, 1592 NULL, sc->sc_dev.dv_xname, "txtso6"); 1593 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 1594 NULL, sc->sc_dev.dv_xname, "txtsopain"); 1595 1596 for (i = 0; i < WM_NTXSEGS; i++) { 1597 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1598 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1599 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1600 } 1601 1602 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1603 NULL, sc->sc_dev.dv_xname, "txdrop"); 1604 1605 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1606 NULL, sc->sc_dev.dv_xname, "tu"); 1607 1608 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1609 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1610 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1611 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1612 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1613 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1614 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1615 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1616 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1617 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1618 #endif /* WM_EVENT_COUNTERS */ 1619 1620 /* 1621 * Make sure the interface is shutdown during reboot. 1622 */ 1623 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1624 if (sc->sc_sdhook == NULL) 1625 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1626 sc->sc_dev.dv_xname); 1627 1628 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 1629 wm_powerhook, sc); 1630 if (sc->sc_powerhook == NULL) 1631 aprint_error("%s: can't establish powerhook\n", 1632 sc->sc_dev.dv_xname); 1633 return; 1634 1635 /* 1636 * Free any resources we've allocated during the failed attach 1637 * attempt. Do this in reverse order and fall through. 1638 */ 1639 fail_5: 1640 for (i = 0; i < WM_NRXDESC; i++) { 1641 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1642 bus_dmamap_destroy(sc->sc_dmat, 1643 sc->sc_rxsoft[i].rxs_dmamap); 1644 } 1645 fail_4: 1646 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1647 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1648 bus_dmamap_destroy(sc->sc_dmat, 1649 sc->sc_txsoft[i].txs_dmamap); 1650 } 1651 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1652 fail_3: 1653 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1654 fail_2: 1655 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1656 cdata_size); 1657 fail_1: 1658 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1659 fail_0: 1660 return; 1661 } 1662 1663 /* 1664 * wm_shutdown: 1665 * 1666 * Make sure the interface is stopped at reboot time. 1667 */ 1668 static void 1669 wm_shutdown(void *arg) 1670 { 1671 struct wm_softc *sc = arg; 1672 1673 wm_stop(&sc->sc_ethercom.ec_if, 1); 1674 } 1675 1676 static void 1677 wm_powerhook(int why, void *arg) 1678 { 1679 struct wm_softc *sc = arg; 1680 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1681 pci_chipset_tag_t pc = sc->sc_pc; 1682 pcitag_t tag = sc->sc_pcitag; 1683 1684 switch (why) { 1685 case PWR_SOFTSUSPEND: 1686 wm_shutdown(sc); 1687 break; 1688 case PWR_SOFTRESUME: 1689 ifp->if_flags &= ~IFF_RUNNING; 1690 wm_init(ifp); 1691 if (ifp->if_flags & IFF_RUNNING) 1692 wm_start(ifp); 1693 break; 1694 case PWR_SUSPEND: 1695 pci_conf_capture(pc, tag, &sc->sc_pciconf); 1696 break; 1697 case PWR_RESUME: 1698 pci_conf_restore(pc, tag, &sc->sc_pciconf); 1699 break; 1700 } 1701 1702 return; 1703 } 1704 1705 /* 1706 * wm_tx_offload: 1707 * 1708 * Set up TCP/IP checksumming parameters for the 1709 * specified packet. 1710 */ 1711 static int 1712 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1713 uint8_t *fieldsp) 1714 { 1715 struct mbuf *m0 = txs->txs_mbuf; 1716 struct livengood_tcpip_ctxdesc *t; 1717 uint32_t ipcs, tucs, cmd, cmdlen, seg; 1718 uint32_t ipcse; 1719 struct ether_header *eh; 1720 int offset, iphl; 1721 uint8_t fields; 1722 1723 /* 1724 * XXX It would be nice if the mbuf pkthdr had offset 1725 * fields for the protocol headers. 1726 */ 1727 1728 eh = mtod(m0, struct ether_header *); 1729 switch (htons(eh->ether_type)) { 1730 case ETHERTYPE_IP: 1731 case ETHERTYPE_IPV6: 1732 offset = ETHER_HDR_LEN; 1733 break; 1734 1735 case ETHERTYPE_VLAN: 1736 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1737 break; 1738 1739 default: 1740 /* 1741 * Don't support this protocol or encapsulation. 1742 */ 1743 *fieldsp = 0; 1744 *cmdp = 0; 1745 return (0); 1746 } 1747 1748 if ((m0->m_pkthdr.csum_flags & 1749 (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4)) != 0) { 1750 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1751 } else { 1752 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 1753 } 1754 ipcse = offset + iphl - 1; 1755 1756 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 1757 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 1758 seg = 0; 1759 fields = 0; 1760 1761 if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 1762 int hlen = offset + iphl; 1763 bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 1764 1765 if (__predict_false(m0->m_len < 1766 (hlen + sizeof(struct tcphdr)))) { 1767 /* 1768 * TCP/IP headers are not in the first mbuf; we need 1769 * to do this the slow and painful way. Let's just 1770 * hope this doesn't happen very often. 1771 */ 1772 struct tcphdr th; 1773 1774 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 1775 1776 m_copydata(m0, hlen, sizeof(th), &th); 1777 if (v4) { 1778 struct ip ip; 1779 1780 m_copydata(m0, offset, sizeof(ip), &ip); 1781 ip.ip_len = 0; 1782 m_copyback(m0, 1783 offset + offsetof(struct ip, ip_len), 1784 sizeof(ip.ip_len), &ip.ip_len); 1785 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 1786 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 1787 } else { 1788 struct ip6_hdr ip6; 1789 1790 m_copydata(m0, offset, sizeof(ip6), &ip6); 1791 ip6.ip6_plen = 0; 1792 m_copyback(m0, 1793 offset + offsetof(struct ip6_hdr, ip6_plen), 1794 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 1795 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 1796 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 1797 } 1798 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 1799 sizeof(th.th_sum), &th.th_sum); 1800 1801 hlen += th.th_off << 2; 1802 } else { 1803 /* 1804 * TCP/IP headers are in the first mbuf; we can do 1805 * this the easy way. 1806 */ 1807 struct tcphdr *th; 1808 1809 if (v4) { 1810 struct ip *ip = 1811 (void *)(mtod(m0, char *) + offset); 1812 th = (void *)(mtod(m0, char *) + hlen); 1813 1814 ip->ip_len = 0; 1815 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 1816 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1817 } else { 1818 struct ip6_hdr *ip6 = 1819 (void *)(mtod(m0, char *) + offset); 1820 th = (void *)(mtod(m0, char *) + hlen); 1821 1822 ip6->ip6_plen = 0; 1823 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 1824 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 1825 } 1826 hlen += th->th_off << 2; 1827 } 1828 1829 if (v4) { 1830 WM_EVCNT_INCR(&sc->sc_ev_txtso); 1831 cmdlen |= WTX_TCPIP_CMD_IP; 1832 } else { 1833 WM_EVCNT_INCR(&sc->sc_ev_txtso6); 1834 ipcse = 0; 1835 } 1836 cmd |= WTX_TCPIP_CMD_TSE; 1837 cmdlen |= WTX_TCPIP_CMD_TSE | 1838 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 1839 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 1840 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 1841 } 1842 1843 /* 1844 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1845 * offload feature, if we load the context descriptor, we 1846 * MUST provide valid values for IPCSS and TUCSS fields. 1847 */ 1848 1849 ipcs = WTX_TCPIP_IPCSS(offset) | 1850 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1851 WTX_TCPIP_IPCSE(ipcse); 1852 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4|M_CSUM_TSOv4)) { 1853 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1854 fields |= WTX_IXSM; 1855 } 1856 1857 offset += iphl; 1858 1859 if (m0->m_pkthdr.csum_flags & 1860 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TSOv4)) { 1861 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1862 fields |= WTX_TXSM; 1863 tucs = WTX_TCPIP_TUCSS(offset) | 1864 WTX_TCPIP_TUCSO(offset + 1865 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 1866 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1867 } else if ((m0->m_pkthdr.csum_flags & 1868 (M_CSUM_TCPv6|M_CSUM_UDPv6|M_CSUM_TSOv6)) != 0) { 1869 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 1870 fields |= WTX_TXSM; 1871 tucs = WTX_TCPIP_TUCSS(offset) | 1872 WTX_TCPIP_TUCSO(offset + 1873 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 1874 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1875 } else { 1876 /* Just initialize it to a valid TCP context. */ 1877 tucs = WTX_TCPIP_TUCSS(offset) | 1878 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1879 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1880 } 1881 1882 /* Fill in the context descriptor. */ 1883 t = (struct livengood_tcpip_ctxdesc *) 1884 &sc->sc_txdescs[sc->sc_txnext]; 1885 t->tcpip_ipcs = htole32(ipcs); 1886 t->tcpip_tucs = htole32(tucs); 1887 t->tcpip_cmdlen = htole32(cmdlen); 1888 t->tcpip_seg = htole32(seg); 1889 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1890 1891 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1892 txs->txs_ndesc++; 1893 1894 *cmdp = cmd; 1895 *fieldsp = fields; 1896 1897 return (0); 1898 } 1899 1900 static void 1901 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1902 { 1903 struct mbuf *m; 1904 int i; 1905 1906 log(LOG_DEBUG, "%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1907 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1908 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 1909 "m_flags = 0x%08x\n", sc->sc_dev.dv_xname, 1910 m->m_data, m->m_len, m->m_flags); 1911 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", sc->sc_dev.dv_xname, 1912 i, i == 1 ? "" : "s"); 1913 } 1914 1915 /* 1916 * wm_82547_txfifo_stall: 1917 * 1918 * Callout used to wait for the 82547 Tx FIFO to drain, 1919 * reset the FIFO pointers, and restart packet transmission. 1920 */ 1921 static void 1922 wm_82547_txfifo_stall(void *arg) 1923 { 1924 struct wm_softc *sc = arg; 1925 int s; 1926 1927 s = splnet(); 1928 1929 if (sc->sc_txfifo_stall) { 1930 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1931 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1932 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1933 /* 1934 * Packets have drained. Stop transmitter, reset 1935 * FIFO pointers, restart transmitter, and kick 1936 * the packet queue. 1937 */ 1938 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1939 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1940 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1941 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1942 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1943 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1944 CSR_WRITE(sc, WMREG_TCTL, tctl); 1945 CSR_WRITE_FLUSH(sc); 1946 1947 sc->sc_txfifo_head = 0; 1948 sc->sc_txfifo_stall = 0; 1949 wm_start(&sc->sc_ethercom.ec_if); 1950 } else { 1951 /* 1952 * Still waiting for packets to drain; try again in 1953 * another tick. 1954 */ 1955 callout_schedule(&sc->sc_txfifo_ch, 1); 1956 } 1957 } 1958 1959 splx(s); 1960 } 1961 1962 /* 1963 * wm_82547_txfifo_bugchk: 1964 * 1965 * Check for bug condition in the 82547 Tx FIFO. We need to 1966 * prevent enqueueing a packet that would wrap around the end 1967 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1968 * 1969 * We do this by checking the amount of space before the end 1970 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1971 * the Tx FIFO, wait for all remaining packets to drain, reset 1972 * the internal FIFO pointers to the beginning, and restart 1973 * transmission on the interface. 1974 */ 1975 #define WM_FIFO_HDR 0x10 1976 #define WM_82547_PAD_LEN 0x3e0 1977 static int 1978 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1979 { 1980 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1981 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1982 1983 /* Just return if already stalled. */ 1984 if (sc->sc_txfifo_stall) 1985 return (1); 1986 1987 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1988 /* Stall only occurs in half-duplex mode. */ 1989 goto send_packet; 1990 } 1991 1992 if (len >= WM_82547_PAD_LEN + space) { 1993 sc->sc_txfifo_stall = 1; 1994 callout_schedule(&sc->sc_txfifo_ch, 1); 1995 return (1); 1996 } 1997 1998 send_packet: 1999 sc->sc_txfifo_head += len; 2000 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 2001 sc->sc_txfifo_head -= sc->sc_txfifo_size; 2002 2003 return (0); 2004 } 2005 2006 /* 2007 * wm_start: [ifnet interface function] 2008 * 2009 * Start packet transmission on the interface. 2010 */ 2011 static void 2012 wm_start(struct ifnet *ifp) 2013 { 2014 struct wm_softc *sc = ifp->if_softc; 2015 struct mbuf *m0; 2016 #if 0 /* XXXJRT */ 2017 struct m_tag *mtag; 2018 #endif 2019 struct wm_txsoft *txs; 2020 bus_dmamap_t dmamap; 2021 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 2022 bus_addr_t curaddr; 2023 bus_size_t seglen, curlen; 2024 uint32_t cksumcmd; 2025 uint8_t cksumfields; 2026 2027 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 2028 return; 2029 2030 /* 2031 * Remember the previous number of free descriptors. 2032 */ 2033 ofree = sc->sc_txfree; 2034 2035 /* 2036 * Loop through the send queue, setting up transmit descriptors 2037 * until we drain the queue, or use up all available transmit 2038 * descriptors. 2039 */ 2040 for (;;) { 2041 /* Grab a packet off the queue. */ 2042 IFQ_POLL(&ifp->if_snd, m0); 2043 if (m0 == NULL) 2044 break; 2045 2046 DPRINTF(WM_DEBUG_TX, 2047 ("%s: TX: have packet to transmit: %p\n", 2048 sc->sc_dev.dv_xname, m0)); 2049 2050 /* Get a work queue entry. */ 2051 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 2052 wm_txintr(sc); 2053 if (sc->sc_txsfree == 0) { 2054 DPRINTF(WM_DEBUG_TX, 2055 ("%s: TX: no free job descriptors\n", 2056 sc->sc_dev.dv_xname)); 2057 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 2058 break; 2059 } 2060 } 2061 2062 txs = &sc->sc_txsoft[sc->sc_txsnext]; 2063 dmamap = txs->txs_dmamap; 2064 2065 use_tso = (m0->m_pkthdr.csum_flags & 2066 (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0; 2067 2068 /* 2069 * So says the Linux driver: 2070 * The controller does a simple calculation to make sure 2071 * there is enough room in the FIFO before initiating the 2072 * DMA for each buffer. The calc is: 2073 * 4 = ceil(buffer len / MSS) 2074 * To make sure we don't overrun the FIFO, adjust the max 2075 * buffer len if the MSS drops. 2076 */ 2077 dmamap->dm_maxsegsz = 2078 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 2079 ? m0->m_pkthdr.segsz << 2 2080 : WTX_MAX_LEN; 2081 2082 /* 2083 * Load the DMA map. If this fails, the packet either 2084 * didn't fit in the allotted number of segments, or we 2085 * were short on resources. For the too-many-segments 2086 * case, we simply report an error and drop the packet, 2087 * since we can't sanely copy a jumbo packet to a single 2088 * buffer. 2089 */ 2090 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 2091 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 2092 if (error) { 2093 if (error == EFBIG) { 2094 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 2095 log(LOG_ERR, "%s: Tx packet consumes too many " 2096 "DMA segments, dropping...\n", 2097 sc->sc_dev.dv_xname); 2098 IFQ_DEQUEUE(&ifp->if_snd, m0); 2099 wm_dump_mbuf_chain(sc, m0); 2100 m_freem(m0); 2101 continue; 2102 } 2103 /* 2104 * Short on resources, just stop for now. 2105 */ 2106 DPRINTF(WM_DEBUG_TX, 2107 ("%s: TX: dmamap load failed: %d\n", 2108 sc->sc_dev.dv_xname, error)); 2109 break; 2110 } 2111 2112 segs_needed = dmamap->dm_nsegs; 2113 if (use_tso) { 2114 /* For sentinel descriptor; see below. */ 2115 segs_needed++; 2116 } 2117 2118 /* 2119 * Ensure we have enough descriptors free to describe 2120 * the packet. Note, we always reserve one descriptor 2121 * at the end of the ring due to the semantics of the 2122 * TDT register, plus one more in the event we need 2123 * to load offload context. 2124 */ 2125 if (segs_needed > sc->sc_txfree - 2) { 2126 /* 2127 * Not enough free descriptors to transmit this 2128 * packet. We haven't committed anything yet, 2129 * so just unload the DMA map, put the packet 2130 * pack on the queue, and punt. Notify the upper 2131 * layer that there are no more slots left. 2132 */ 2133 DPRINTF(WM_DEBUG_TX, 2134 ("%s: TX: need %d (%d) descriptors, have %d\n", 2135 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 2136 sc->sc_txfree - 1)); 2137 ifp->if_flags |= IFF_OACTIVE; 2138 bus_dmamap_unload(sc->sc_dmat, dmamap); 2139 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 2140 break; 2141 } 2142 2143 /* 2144 * Check for 82547 Tx FIFO bug. We need to do this 2145 * once we know we can transmit the packet, since we 2146 * do some internal FIFO space accounting here. 2147 */ 2148 if (sc->sc_type == WM_T_82547 && 2149 wm_82547_txfifo_bugchk(sc, m0)) { 2150 DPRINTF(WM_DEBUG_TX, 2151 ("%s: TX: 82547 Tx FIFO bug detected\n", 2152 sc->sc_dev.dv_xname)); 2153 ifp->if_flags |= IFF_OACTIVE; 2154 bus_dmamap_unload(sc->sc_dmat, dmamap); 2155 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 2156 break; 2157 } 2158 2159 IFQ_DEQUEUE(&ifp->if_snd, m0); 2160 2161 /* 2162 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 2163 */ 2164 2165 DPRINTF(WM_DEBUG_TX, 2166 ("%s: TX: packet has %d (%d) DMA segments\n", 2167 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 2168 2169 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 2170 2171 /* 2172 * Store a pointer to the packet so that we can free it 2173 * later. 2174 * 2175 * Initially, we consider the number of descriptors the 2176 * packet uses the number of DMA segments. This may be 2177 * incremented by 1 if we do checksum offload (a descriptor 2178 * is used to set the checksum context). 2179 */ 2180 txs->txs_mbuf = m0; 2181 txs->txs_firstdesc = sc->sc_txnext; 2182 txs->txs_ndesc = segs_needed; 2183 2184 /* Set up offload parameters for this packet. */ 2185 if (m0->m_pkthdr.csum_flags & 2186 (M_CSUM_TSOv4|M_CSUM_TSOv6| 2187 M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 2188 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 2189 if (wm_tx_offload(sc, txs, &cksumcmd, 2190 &cksumfields) != 0) { 2191 /* Error message already displayed. */ 2192 bus_dmamap_unload(sc->sc_dmat, dmamap); 2193 continue; 2194 } 2195 } else { 2196 cksumcmd = 0; 2197 cksumfields = 0; 2198 } 2199 2200 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 2201 2202 /* Sync the DMA map. */ 2203 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2204 BUS_DMASYNC_PREWRITE); 2205 2206 /* 2207 * Initialize the transmit descriptor. 2208 */ 2209 for (nexttx = sc->sc_txnext, seg = 0; 2210 seg < dmamap->dm_nsegs; seg++) { 2211 for (seglen = dmamap->dm_segs[seg].ds_len, 2212 curaddr = dmamap->dm_segs[seg].ds_addr; 2213 seglen != 0; 2214 curaddr += curlen, seglen -= curlen, 2215 nexttx = WM_NEXTTX(sc, nexttx)) { 2216 curlen = seglen; 2217 2218 /* 2219 * So says the Linux driver: 2220 * Work around for premature descriptor 2221 * write-backs in TSO mode. Append a 2222 * 4-byte sentinel descriptor. 2223 */ 2224 if (use_tso && 2225 seg == dmamap->dm_nsegs - 1 && 2226 curlen > 8) 2227 curlen -= 4; 2228 2229 wm_set_dma_addr( 2230 &sc->sc_txdescs[nexttx].wtx_addr, 2231 curaddr); 2232 sc->sc_txdescs[nexttx].wtx_cmdlen = 2233 htole32(cksumcmd | curlen); 2234 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 2235 0; 2236 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 2237 cksumfields; 2238 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 2239 lasttx = nexttx; 2240 2241 DPRINTF(WM_DEBUG_TX, 2242 ("%s: TX: desc %d: low 0x%08lx, " 2243 "len 0x%04x\n", 2244 sc->sc_dev.dv_xname, nexttx, 2245 curaddr & 0xffffffffUL, (unsigned)curlen)); 2246 } 2247 } 2248 2249 KASSERT(lasttx != -1); 2250 2251 /* 2252 * Set up the command byte on the last descriptor of 2253 * the packet. If we're in the interrupt delay window, 2254 * delay the interrupt. 2255 */ 2256 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2257 htole32(WTX_CMD_EOP | WTX_CMD_RS); 2258 2259 #if 0 /* XXXJRT */ 2260 /* 2261 * If VLANs are enabled and the packet has a VLAN tag, set 2262 * up the descriptor to encapsulate the packet for us. 2263 * 2264 * This is only valid on the last descriptor of the packet. 2265 */ 2266 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 2267 sc->sc_txdescs[lasttx].wtx_cmdlen |= 2268 htole32(WTX_CMD_VLE); 2269 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 2270 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 2271 } 2272 #endif /* XXXJRT */ 2273 2274 txs->txs_lastdesc = lasttx; 2275 2276 DPRINTF(WM_DEBUG_TX, 2277 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 2278 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 2279 2280 /* Sync the descriptors we're using. */ 2281 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 2282 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2283 2284 /* Give the packet to the chip. */ 2285 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 2286 2287 DPRINTF(WM_DEBUG_TX, 2288 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 2289 2290 DPRINTF(WM_DEBUG_TX, 2291 ("%s: TX: finished transmitting packet, job %d\n", 2292 sc->sc_dev.dv_xname, sc->sc_txsnext)); 2293 2294 /* Advance the tx pointer. */ 2295 sc->sc_txfree -= txs->txs_ndesc; 2296 sc->sc_txnext = nexttx; 2297 2298 sc->sc_txsfree--; 2299 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 2300 2301 #if NBPFILTER > 0 2302 /* Pass the packet to any BPF listeners. */ 2303 if (ifp->if_bpf) 2304 bpf_mtap(ifp->if_bpf, m0); 2305 #endif /* NBPFILTER > 0 */ 2306 } 2307 2308 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 2309 /* No more slots; notify upper layer. */ 2310 ifp->if_flags |= IFF_OACTIVE; 2311 } 2312 2313 if (sc->sc_txfree != ofree) { 2314 /* Set a watchdog timer in case the chip flakes out. */ 2315 ifp->if_timer = 5; 2316 } 2317 } 2318 2319 /* 2320 * wm_watchdog: [ifnet interface function] 2321 * 2322 * Watchdog timer handler. 2323 */ 2324 static void 2325 wm_watchdog(struct ifnet *ifp) 2326 { 2327 struct wm_softc *sc = ifp->if_softc; 2328 2329 /* 2330 * Since we're using delayed interrupts, sweep up 2331 * before we report an error. 2332 */ 2333 wm_txintr(sc); 2334 2335 if (sc->sc_txfree != WM_NTXDESC(sc)) { 2336 log(LOG_ERR, 2337 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 2338 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 2339 sc->sc_txnext); 2340 ifp->if_oerrors++; 2341 2342 /* Reset the interface. */ 2343 (void) wm_init(ifp); 2344 } 2345 2346 /* Try to get more packets going. */ 2347 wm_start(ifp); 2348 } 2349 2350 /* 2351 * wm_ioctl: [ifnet interface function] 2352 * 2353 * Handle control requests from the operator. 2354 */ 2355 static int 2356 wm_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2357 { 2358 struct wm_softc *sc = ifp->if_softc; 2359 struct ifreq *ifr = (struct ifreq *) data; 2360 int s, error; 2361 2362 s = splnet(); 2363 2364 switch (cmd) { 2365 case SIOCSIFMEDIA: 2366 case SIOCGIFMEDIA: 2367 /* Flow control requires full-duplex mode. */ 2368 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2369 (ifr->ifr_media & IFM_FDX) == 0) 2370 ifr->ifr_media &= ~IFM_ETH_FMASK; 2371 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2372 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2373 /* We can do both TXPAUSE and RXPAUSE. */ 2374 ifr->ifr_media |= 2375 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2376 } 2377 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2378 } 2379 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2380 break; 2381 default: 2382 error = ether_ioctl(ifp, cmd, data); 2383 if (error == ENETRESET) { 2384 /* 2385 * Multicast list has changed; set the hardware filter 2386 * accordingly. 2387 */ 2388 if (ifp->if_flags & IFF_RUNNING) 2389 wm_set_filter(sc); 2390 error = 0; 2391 } 2392 break; 2393 } 2394 2395 /* Try to get more packets going. */ 2396 wm_start(ifp); 2397 2398 splx(s); 2399 return (error); 2400 } 2401 2402 /* 2403 * wm_intr: 2404 * 2405 * Interrupt service routine. 2406 */ 2407 static int 2408 wm_intr(void *arg) 2409 { 2410 struct wm_softc *sc = arg; 2411 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2412 uint32_t icr; 2413 int handled = 0; 2414 2415 while (1 /* CONSTCOND */) { 2416 icr = CSR_READ(sc, WMREG_ICR); 2417 if ((icr & sc->sc_icr) == 0) 2418 break; 2419 #if 0 /*NRND > 0*/ 2420 if (RND_ENABLED(&sc->rnd_source)) 2421 rnd_add_uint32(&sc->rnd_source, icr); 2422 #endif 2423 2424 handled = 1; 2425 2426 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2427 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 2428 DPRINTF(WM_DEBUG_RX, 2429 ("%s: RX: got Rx intr 0x%08x\n", 2430 sc->sc_dev.dv_xname, 2431 icr & (ICR_RXDMT0|ICR_RXT0))); 2432 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 2433 } 2434 #endif 2435 wm_rxintr(sc); 2436 2437 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 2438 if (icr & ICR_TXDW) { 2439 DPRINTF(WM_DEBUG_TX, 2440 ("%s: TX: got TXDW interrupt\n", 2441 sc->sc_dev.dv_xname)); 2442 WM_EVCNT_INCR(&sc->sc_ev_txdw); 2443 } 2444 #endif 2445 wm_txintr(sc); 2446 2447 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 2448 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 2449 wm_linkintr(sc, icr); 2450 } 2451 2452 if (icr & ICR_RXO) { 2453 ifp->if_ierrors++; 2454 #if defined(WM_DEBUG) 2455 log(LOG_WARNING, "%s: Receive overrun\n", 2456 sc->sc_dev.dv_xname); 2457 #endif /* defined(WM_DEBUG) */ 2458 } 2459 } 2460 2461 if (handled) { 2462 /* Try to get more packets going. */ 2463 wm_start(ifp); 2464 } 2465 2466 return (handled); 2467 } 2468 2469 /* 2470 * wm_txintr: 2471 * 2472 * Helper; handle transmit interrupts. 2473 */ 2474 static void 2475 wm_txintr(struct wm_softc *sc) 2476 { 2477 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2478 struct wm_txsoft *txs; 2479 uint8_t status; 2480 int i; 2481 2482 ifp->if_flags &= ~IFF_OACTIVE; 2483 2484 /* 2485 * Go through the Tx list and free mbufs for those 2486 * frames which have been transmitted. 2487 */ 2488 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2489 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2490 txs = &sc->sc_txsoft[i]; 2491 2492 DPRINTF(WM_DEBUG_TX, 2493 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2494 2495 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2496 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2497 2498 status = 2499 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2500 if ((status & WTX_ST_DD) == 0) { 2501 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2502 BUS_DMASYNC_PREREAD); 2503 break; 2504 } 2505 2506 DPRINTF(WM_DEBUG_TX, 2507 ("%s: TX: job %d done: descs %d..%d\n", 2508 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2509 txs->txs_lastdesc)); 2510 2511 /* 2512 * XXX We should probably be using the statistics 2513 * XXX registers, but I don't know if they exist 2514 * XXX on chips before the i82544. 2515 */ 2516 2517 #ifdef WM_EVENT_COUNTERS 2518 if (status & WTX_ST_TU) 2519 WM_EVCNT_INCR(&sc->sc_ev_tu); 2520 #endif /* WM_EVENT_COUNTERS */ 2521 2522 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2523 ifp->if_oerrors++; 2524 if (status & WTX_ST_LC) 2525 log(LOG_WARNING, "%s: late collision\n", 2526 sc->sc_dev.dv_xname); 2527 else if (status & WTX_ST_EC) { 2528 ifp->if_collisions += 16; 2529 log(LOG_WARNING, "%s: excessive collisions\n", 2530 sc->sc_dev.dv_xname); 2531 } 2532 } else 2533 ifp->if_opackets++; 2534 2535 sc->sc_txfree += txs->txs_ndesc; 2536 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2537 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2538 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2539 m_freem(txs->txs_mbuf); 2540 txs->txs_mbuf = NULL; 2541 } 2542 2543 /* Update the dirty transmit buffer pointer. */ 2544 sc->sc_txsdirty = i; 2545 DPRINTF(WM_DEBUG_TX, 2546 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2547 2548 /* 2549 * If there are no more pending transmissions, cancel the watchdog 2550 * timer. 2551 */ 2552 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2553 ifp->if_timer = 0; 2554 } 2555 2556 /* 2557 * wm_rxintr: 2558 * 2559 * Helper; handle receive interrupts. 2560 */ 2561 static void 2562 wm_rxintr(struct wm_softc *sc) 2563 { 2564 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2565 struct wm_rxsoft *rxs; 2566 struct mbuf *m; 2567 int i, len; 2568 uint8_t status, errors; 2569 2570 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2571 rxs = &sc->sc_rxsoft[i]; 2572 2573 DPRINTF(WM_DEBUG_RX, 2574 ("%s: RX: checking descriptor %d\n", 2575 sc->sc_dev.dv_xname, i)); 2576 2577 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2578 2579 status = sc->sc_rxdescs[i].wrx_status; 2580 errors = sc->sc_rxdescs[i].wrx_errors; 2581 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2582 2583 if ((status & WRX_ST_DD) == 0) { 2584 /* 2585 * We have processed all of the receive descriptors. 2586 */ 2587 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2588 break; 2589 } 2590 2591 if (__predict_false(sc->sc_rxdiscard)) { 2592 DPRINTF(WM_DEBUG_RX, 2593 ("%s: RX: discarding contents of descriptor %d\n", 2594 sc->sc_dev.dv_xname, i)); 2595 WM_INIT_RXDESC(sc, i); 2596 if (status & WRX_ST_EOP) { 2597 /* Reset our state. */ 2598 DPRINTF(WM_DEBUG_RX, 2599 ("%s: RX: resetting rxdiscard -> 0\n", 2600 sc->sc_dev.dv_xname)); 2601 sc->sc_rxdiscard = 0; 2602 } 2603 continue; 2604 } 2605 2606 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2607 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2608 2609 m = rxs->rxs_mbuf; 2610 2611 /* 2612 * Add a new receive buffer to the ring, unless of 2613 * course the length is zero. Treat the latter as a 2614 * failed mapping. 2615 */ 2616 if ((len == 0) || (wm_add_rxbuf(sc, i) != 0)) { 2617 /* 2618 * Failed, throw away what we've done so 2619 * far, and discard the rest of the packet. 2620 */ 2621 ifp->if_ierrors++; 2622 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2623 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2624 WM_INIT_RXDESC(sc, i); 2625 if ((status & WRX_ST_EOP) == 0) 2626 sc->sc_rxdiscard = 1; 2627 if (sc->sc_rxhead != NULL) 2628 m_freem(sc->sc_rxhead); 2629 WM_RXCHAIN_RESET(sc); 2630 DPRINTF(WM_DEBUG_RX, 2631 ("%s: RX: Rx buffer allocation failed, " 2632 "dropping packet%s\n", sc->sc_dev.dv_xname, 2633 sc->sc_rxdiscard ? " (discard)" : "")); 2634 continue; 2635 } 2636 2637 WM_RXCHAIN_LINK(sc, m); 2638 2639 m->m_len = len; 2640 2641 DPRINTF(WM_DEBUG_RX, 2642 ("%s: RX: buffer at %p len %d\n", 2643 sc->sc_dev.dv_xname, m->m_data, len)); 2644 2645 /* 2646 * If this is not the end of the packet, keep 2647 * looking. 2648 */ 2649 if ((status & WRX_ST_EOP) == 0) { 2650 sc->sc_rxlen += len; 2651 DPRINTF(WM_DEBUG_RX, 2652 ("%s: RX: not yet EOP, rxlen -> %d\n", 2653 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2654 continue; 2655 } 2656 2657 /* 2658 * Okay, we have the entire packet now. The chip is 2659 * configured to include the FCS (not all chips can 2660 * be configured to strip it), so we need to trim it. 2661 */ 2662 m->m_len -= ETHER_CRC_LEN; 2663 2664 *sc->sc_rxtailp = NULL; 2665 len = m->m_len + sc->sc_rxlen; 2666 m = sc->sc_rxhead; 2667 2668 WM_RXCHAIN_RESET(sc); 2669 2670 DPRINTF(WM_DEBUG_RX, 2671 ("%s: RX: have entire packet, len -> %d\n", 2672 sc->sc_dev.dv_xname, len)); 2673 2674 /* 2675 * If an error occurred, update stats and drop the packet. 2676 */ 2677 if (errors & 2678 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2679 ifp->if_ierrors++; 2680 if (errors & WRX_ER_SE) 2681 log(LOG_WARNING, "%s: symbol error\n", 2682 sc->sc_dev.dv_xname); 2683 else if (errors & WRX_ER_SEQ) 2684 log(LOG_WARNING, "%s: receive sequence error\n", 2685 sc->sc_dev.dv_xname); 2686 else if (errors & WRX_ER_CE) 2687 log(LOG_WARNING, "%s: CRC error\n", 2688 sc->sc_dev.dv_xname); 2689 m_freem(m); 2690 continue; 2691 } 2692 2693 /* 2694 * No errors. Receive the packet. 2695 */ 2696 m->m_pkthdr.rcvif = ifp; 2697 m->m_pkthdr.len = len; 2698 2699 #if 0 /* XXXJRT */ 2700 /* 2701 * If VLANs are enabled, VLAN packets have been unwrapped 2702 * for us. Associate the tag with the packet. 2703 */ 2704 if ((status & WRX_ST_VP) != 0) { 2705 VLAN_INPUT_TAG(ifp, m, 2706 le16toh(sc->sc_rxdescs[i].wrx_special, 2707 continue); 2708 } 2709 #endif /* XXXJRT */ 2710 2711 /* 2712 * Set up checksum info for this packet. 2713 */ 2714 if ((status & WRX_ST_IXSM) == 0) { 2715 if (status & WRX_ST_IPCS) { 2716 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2717 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2718 if (errors & WRX_ER_IPE) 2719 m->m_pkthdr.csum_flags |= 2720 M_CSUM_IPv4_BAD; 2721 } 2722 if (status & WRX_ST_TCPCS) { 2723 /* 2724 * Note: we don't know if this was TCP or UDP, 2725 * so we just set both bits, and expect the 2726 * upper layers to deal. 2727 */ 2728 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2729 m->m_pkthdr.csum_flags |= 2730 M_CSUM_TCPv4 | M_CSUM_UDPv4 | 2731 M_CSUM_TCPv6 | M_CSUM_UDPv6; 2732 if (errors & WRX_ER_TCPE) 2733 m->m_pkthdr.csum_flags |= 2734 M_CSUM_TCP_UDP_BAD; 2735 } 2736 } 2737 2738 ifp->if_ipackets++; 2739 2740 #if NBPFILTER > 0 2741 /* Pass this up to any BPF listeners. */ 2742 if (ifp->if_bpf) 2743 bpf_mtap(ifp->if_bpf, m); 2744 #endif /* NBPFILTER > 0 */ 2745 2746 /* Pass it on. */ 2747 (*ifp->if_input)(ifp, m); 2748 } 2749 2750 /* Update the receive pointer. */ 2751 sc->sc_rxptr = i; 2752 2753 DPRINTF(WM_DEBUG_RX, 2754 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2755 } 2756 2757 /* 2758 * wm_linkintr: 2759 * 2760 * Helper; handle link interrupts. 2761 */ 2762 static void 2763 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2764 { 2765 uint32_t status; 2766 2767 /* 2768 * If we get a link status interrupt on a 1000BASE-T 2769 * device, just fall into the normal MII tick path. 2770 */ 2771 if (sc->sc_flags & WM_F_HAS_MII) { 2772 if (icr & ICR_LSC) { 2773 DPRINTF(WM_DEBUG_LINK, 2774 ("%s: LINK: LSC -> mii_tick\n", 2775 sc->sc_dev.dv_xname)); 2776 mii_tick(&sc->sc_mii); 2777 } else if (icr & ICR_RXSEQ) { 2778 DPRINTF(WM_DEBUG_LINK, 2779 ("%s: LINK Receive sequence error\n", 2780 sc->sc_dev.dv_xname)); 2781 } 2782 return; 2783 } 2784 2785 /* 2786 * If we are now receiving /C/, check for link again in 2787 * a couple of link clock ticks. 2788 */ 2789 if (icr & ICR_RXCFG) { 2790 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2791 sc->sc_dev.dv_xname)); 2792 sc->sc_tbi_anstate = 2; 2793 } 2794 2795 if (icr & ICR_LSC) { 2796 status = CSR_READ(sc, WMREG_STATUS); 2797 if (status & STATUS_LU) { 2798 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2799 sc->sc_dev.dv_xname, 2800 (status & STATUS_FD) ? "FDX" : "HDX")); 2801 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2802 sc->sc_fcrtl &= ~FCRTL_XONE; 2803 if (status & STATUS_FD) 2804 sc->sc_tctl |= 2805 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2806 else 2807 sc->sc_tctl |= 2808 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2809 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2810 sc->sc_fcrtl |= FCRTL_XONE; 2811 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2812 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2813 WMREG_OLD_FCRTL : WMREG_FCRTL, 2814 sc->sc_fcrtl); 2815 sc->sc_tbi_linkup = 1; 2816 } else { 2817 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2818 sc->sc_dev.dv_xname)); 2819 sc->sc_tbi_linkup = 0; 2820 } 2821 sc->sc_tbi_anstate = 2; 2822 wm_tbi_set_linkled(sc); 2823 } else if (icr & ICR_RXSEQ) { 2824 DPRINTF(WM_DEBUG_LINK, 2825 ("%s: LINK: Receive sequence error\n", 2826 sc->sc_dev.dv_xname)); 2827 } 2828 } 2829 2830 /* 2831 * wm_tick: 2832 * 2833 * One second timer, used to check link status, sweep up 2834 * completed transmit jobs, etc. 2835 */ 2836 static void 2837 wm_tick(void *arg) 2838 { 2839 struct wm_softc *sc = arg; 2840 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2841 int s; 2842 2843 s = splnet(); 2844 2845 if (sc->sc_type >= WM_T_82542_2_1) { 2846 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2847 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2848 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2849 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2850 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2851 } 2852 2853 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 2854 ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); 2855 2856 2857 if (sc->sc_flags & WM_F_HAS_MII) 2858 mii_tick(&sc->sc_mii); 2859 else 2860 wm_tbi_check_link(sc); 2861 2862 splx(s); 2863 2864 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2865 } 2866 2867 /* 2868 * wm_reset: 2869 * 2870 * Reset the i82542 chip. 2871 */ 2872 static void 2873 wm_reset(struct wm_softc *sc) 2874 { 2875 2876 /* 2877 * Allocate on-chip memory according to the MTU size. 2878 * The Packet Buffer Allocation register must be written 2879 * before the chip is reset. 2880 */ 2881 switch (sc->sc_type) { 2882 case WM_T_82547: 2883 case WM_T_82547_2: 2884 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2885 PBA_22K : PBA_30K; 2886 sc->sc_txfifo_head = 0; 2887 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2888 sc->sc_txfifo_size = 2889 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2890 sc->sc_txfifo_stall = 0; 2891 break; 2892 case WM_T_82571: 2893 case WM_T_82572: 2894 case WM_T_80003: 2895 sc->sc_pba = PBA_32K; 2896 break; 2897 case WM_T_82573: 2898 sc->sc_pba = PBA_12K; 2899 break; 2900 case WM_T_ICH8: 2901 sc->sc_pba = PBA_8K; 2902 CSR_WRITE(sc, WMREG_PBS, PBA_16K); 2903 break; 2904 case WM_T_ICH9: 2905 sc->sc_pba = PBA_10K; 2906 break; 2907 default: 2908 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2909 PBA_40K : PBA_48K; 2910 break; 2911 } 2912 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2913 2914 if (sc->sc_flags & WM_F_PCIE) { 2915 int timeout = 800; 2916 2917 sc->sc_ctrl |= CTRL_GIO_M_DIS; 2918 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2919 2920 while (timeout) { 2921 if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA) == 0) 2922 break; 2923 delay(100); 2924 } 2925 } 2926 2927 /* clear interrupt */ 2928 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2929 2930 /* 2931 * 82541 Errata 29? & 82547 Errata 28? 2932 * See also the description about PHY_RST bit in CTRL register 2933 * in 8254x_GBe_SDM.pdf. 2934 */ 2935 if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) { 2936 CSR_WRITE(sc, WMREG_CTRL, 2937 CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET); 2938 delay(5000); 2939 } 2940 2941 switch (sc->sc_type) { 2942 case WM_T_82544: 2943 case WM_T_82540: 2944 case WM_T_82545: 2945 case WM_T_82546: 2946 case WM_T_82541: 2947 case WM_T_82541_2: 2948 /* 2949 * On some chipsets, a reset through a memory-mapped write 2950 * cycle can cause the chip to reset before completing the 2951 * write cycle. This causes major headache that can be 2952 * avoided by issuing the reset via indirect register writes 2953 * through I/O space. 2954 * 2955 * So, if we successfully mapped the I/O BAR at attach time, 2956 * use that. Otherwise, try our luck with a memory-mapped 2957 * reset. 2958 */ 2959 if (sc->sc_flags & WM_F_IOH_VALID) 2960 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2961 else 2962 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2963 break; 2964 2965 case WM_T_82545_3: 2966 case WM_T_82546_3: 2967 /* Use the shadow control register on these chips. */ 2968 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2969 break; 2970 2971 case WM_T_ICH8: 2972 case WM_T_ICH9: 2973 wm_get_swfwhw_semaphore(sc); 2974 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST | CTRL_PHY_RESET); 2975 delay(10000); 2976 2977 default: 2978 /* Everything else can safely use the documented method. */ 2979 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2980 break; 2981 } 2982 delay(10000); 2983 2984 switch(sc->sc_type) { 2985 case WM_T_82542_2_0: 2986 case WM_T_82542_2_1: 2987 case WM_T_82543: 2988 case WM_T_82544: 2989 delay(10); 2990 delay(2000); 2991 break; 2992 case WM_T_82541: 2993 case WM_T_82541_2: 2994 case WM_T_82547: 2995 case WM_T_82547_2: 2996 delay(20000); 2997 break; 2998 case WM_T_82573: 2999 delay(10); 3000 /* FALLTHROUGH */ 3001 default: 3002 /* check EECD_EE_AUTORD */ 3003 wm_get_auto_rd_dome(sc); 3004 } 3005 3006 #if 0 3007 for (i = 0; i < 1000; i++) { 3008 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) { 3009 return; 3010 } 3011 delay(20); 3012 } 3013 3014 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 3015 log(LOG_ERR, "%s: reset failed to complete\n", 3016 sc->sc_dev.dv_xname); 3017 #endif 3018 } 3019 3020 /* 3021 * wm_init: [ifnet interface function] 3022 * 3023 * Initialize the interface. Must be called at splnet(). 3024 */ 3025 static int 3026 wm_init(struct ifnet *ifp) 3027 { 3028 struct wm_softc *sc = ifp->if_softc; 3029 struct wm_rxsoft *rxs; 3030 int i, error = 0; 3031 uint32_t reg; 3032 3033 /* 3034 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 3035 * There is a small but measurable benefit to avoiding the adjusment 3036 * of the descriptor so that the headers are aligned, for normal mtu, 3037 * on such platforms. One possibility is that the DMA itself is 3038 * slightly more efficient if the front of the entire packet (instead 3039 * of the front of the headers) is aligned. 3040 * 3041 * Note we must always set align_tweak to 0 if we are using 3042 * jumbo frames. 3043 */ 3044 #ifdef __NO_STRICT_ALIGNMENT 3045 sc->sc_align_tweak = 0; 3046 #else 3047 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 3048 sc->sc_align_tweak = 0; 3049 else 3050 sc->sc_align_tweak = 2; 3051 #endif /* __NO_STRICT_ALIGNMENT */ 3052 3053 /* Cancel any pending I/O. */ 3054 wm_stop(ifp, 0); 3055 3056 /* update statistics before reset */ 3057 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 3058 ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); 3059 3060 /* Reset the chip to a known state. */ 3061 wm_reset(sc); 3062 3063 /* Initialize the transmit descriptor ring. */ 3064 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 3065 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 3066 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3067 sc->sc_txfree = WM_NTXDESC(sc); 3068 sc->sc_txnext = 0; 3069 3070 if (sc->sc_type < WM_T_82543) { 3071 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 3072 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 3073 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 3074 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 3075 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 3076 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 3077 } else { 3078 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 3079 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 3080 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 3081 CSR_WRITE(sc, WMREG_TDH, 0); 3082 CSR_WRITE(sc, WMREG_TDT, 0); 3083 CSR_WRITE(sc, WMREG_TIDV, 64); 3084 CSR_WRITE(sc, WMREG_TADV, 128); 3085 3086 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 3087 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 3088 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 3089 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 3090 } 3091 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 3092 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 3093 3094 /* Initialize the transmit job descriptors. */ 3095 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 3096 sc->sc_txsoft[i].txs_mbuf = NULL; 3097 sc->sc_txsfree = WM_TXQUEUELEN(sc); 3098 sc->sc_txsnext = 0; 3099 sc->sc_txsdirty = 0; 3100 3101 /* 3102 * Initialize the receive descriptor and receive job 3103 * descriptor rings. 3104 */ 3105 if (sc->sc_type < WM_T_82543) { 3106 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 3107 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 3108 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 3109 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 3110 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 3111 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 3112 3113 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 3114 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 3115 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 3116 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 3117 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 3118 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 3119 } else { 3120 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 3121 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 3122 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 3123 CSR_WRITE(sc, WMREG_RDH, 0); 3124 CSR_WRITE(sc, WMREG_RDT, 0); 3125 CSR_WRITE(sc, WMREG_RDTR, 0 | RDTR_FPD); 3126 CSR_WRITE(sc, WMREG_RADV, 128); 3127 } 3128 for (i = 0; i < WM_NRXDESC; i++) { 3129 rxs = &sc->sc_rxsoft[i]; 3130 if (rxs->rxs_mbuf == NULL) { 3131 if ((error = wm_add_rxbuf(sc, i)) != 0) { 3132 log(LOG_ERR, "%s: unable to allocate or map rx " 3133 "buffer %d, error = %d\n", 3134 sc->sc_dev.dv_xname, i, error); 3135 /* 3136 * XXX Should attempt to run with fewer receive 3137 * XXX buffers instead of just failing. 3138 */ 3139 wm_rxdrain(sc); 3140 goto out; 3141 } 3142 } else 3143 WM_INIT_RXDESC(sc, i); 3144 } 3145 sc->sc_rxptr = 0; 3146 sc->sc_rxdiscard = 0; 3147 WM_RXCHAIN_RESET(sc); 3148 3149 /* 3150 * Clear out the VLAN table -- we don't use it (yet). 3151 */ 3152 CSR_WRITE(sc, WMREG_VET, 0); 3153 for (i = 0; i < WM_VLAN_TABSIZE; i++) 3154 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 3155 3156 /* 3157 * Set up flow-control parameters. 3158 * 3159 * XXX Values could probably stand some tuning. 3160 */ 3161 if (sc->sc_type != WM_T_ICH8) { 3162 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 3163 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 3164 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 3165 } 3166 3167 sc->sc_fcrtl = FCRTL_DFLT; 3168 if (sc->sc_type < WM_T_82543) { 3169 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 3170 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 3171 } else { 3172 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 3173 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 3174 } 3175 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 3176 3177 #if 0 /* XXXJRT */ 3178 /* Deal with VLAN enables. */ 3179 if (VLAN_ATTACHED(&sc->sc_ethercom)) 3180 sc->sc_ctrl |= CTRL_VME; 3181 else 3182 #endif /* XXXJRT */ 3183 sc->sc_ctrl &= ~CTRL_VME; 3184 3185 /* Write the control registers. */ 3186 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3187 if (sc->sc_type >= WM_T_80003 && (sc->sc_flags & WM_F_HAS_MII)) { 3188 int val; 3189 val = CSR_READ(sc, WMREG_CTRL_EXT); 3190 val &= ~CTRL_EXT_LINK_MODE_MASK; 3191 CSR_WRITE(sc, WMREG_CTRL_EXT, val); 3192 3193 /* Bypass RX and TX FIFO's */ 3194 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL, 3195 KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 3196 KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 3197 3198 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL, 3199 KUMCTRLSTA_INB_CTRL_DIS_PADDING | 3200 KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT); 3201 /* 3202 * Set the mac to wait the maximum time between each 3203 * iteration and increase the max iterations when 3204 * polling the phy; this fixes erroneous timeouts at 10Mbps. 3205 */ 3206 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS, 0xFFFF); 3207 val = wm_kmrn_i80003_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM); 3208 val |= 0x3F; 3209 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_INB_PARAM, val); 3210 } 3211 #if 0 3212 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 3213 #endif 3214 3215 /* 3216 * Set up checksum offload parameters. 3217 */ 3218 reg = CSR_READ(sc, WMREG_RXCSUM); 3219 reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL); 3220 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 3221 reg |= RXCSUM_IPOFL; 3222 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 3223 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 3224 if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) 3225 reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL; 3226 CSR_WRITE(sc, WMREG_RXCSUM, reg); 3227 3228 /* 3229 * Set up the interrupt registers. 3230 */ 3231 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3232 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 3233 ICR_RXO | ICR_RXT0; 3234 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 3235 sc->sc_icr |= ICR_RXCFG; 3236 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 3237 3238 /* Set up the inter-packet gap. */ 3239 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 3240 3241 if (sc->sc_type >= WM_T_82543) { 3242 /* Set up the interrupt throttling register (units of 256ns) */ 3243 sc->sc_itr = 1000000000 / (7000 * 256); 3244 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 3245 } 3246 3247 #if 0 /* XXXJRT */ 3248 /* Set the VLAN ethernetype. */ 3249 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 3250 #endif 3251 3252 /* 3253 * Set up the transmit control register; we start out with 3254 * a collision distance suitable for FDX, but update it whe 3255 * we resolve the media type. 3256 */ 3257 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 3258 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3259 if (sc->sc_type >= WM_T_82571) 3260 sc->sc_tctl |= TCTL_MULR; 3261 if (sc->sc_type >= WM_T_80003) 3262 sc->sc_tctl |= TCTL_RTLC; 3263 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3264 3265 /* Set the media. */ 3266 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 3267 3268 /* 3269 * Set up the receive control register; we actually program 3270 * the register when we set the receive filter. Use multicast 3271 * address offset type 0. 3272 * 3273 * Only the i82544 has the ability to strip the incoming 3274 * CRC, so we don't enable that feature. 3275 */ 3276 sc->sc_mchash_type = 0; 3277 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF 3278 | RCTL_MO(sc->sc_mchash_type); 3279 3280 /* 82573 doesn't support jumbo frame */ 3281 if (sc->sc_type != WM_T_82573 && sc->sc_type != WM_T_ICH8) 3282 sc->sc_rctl |= RCTL_LPE; 3283 3284 if (MCLBYTES == 2048) { 3285 sc->sc_rctl |= RCTL_2k; 3286 } else { 3287 if (sc->sc_type >= WM_T_82543) { 3288 switch(MCLBYTES) { 3289 case 4096: 3290 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 3291 break; 3292 case 8192: 3293 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 3294 break; 3295 case 16384: 3296 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 3297 break; 3298 default: 3299 panic("wm_init: MCLBYTES %d unsupported", 3300 MCLBYTES); 3301 break; 3302 } 3303 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 3304 } 3305 3306 /* Set the receive filter. */ 3307 wm_set_filter(sc); 3308 3309 /* Start the one second link check clock. */ 3310 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 3311 3312 /* ...all done! */ 3313 ifp->if_flags |= IFF_RUNNING; 3314 ifp->if_flags &= ~IFF_OACTIVE; 3315 3316 out: 3317 if (error) 3318 log(LOG_ERR, "%s: interface not running\n", 3319 sc->sc_dev.dv_xname); 3320 return (error); 3321 } 3322 3323 /* 3324 * wm_rxdrain: 3325 * 3326 * Drain the receive queue. 3327 */ 3328 static void 3329 wm_rxdrain(struct wm_softc *sc) 3330 { 3331 struct wm_rxsoft *rxs; 3332 int i; 3333 3334 for (i = 0; i < WM_NRXDESC; i++) { 3335 rxs = &sc->sc_rxsoft[i]; 3336 if (rxs->rxs_mbuf != NULL) { 3337 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3338 m_freem(rxs->rxs_mbuf); 3339 rxs->rxs_mbuf = NULL; 3340 } 3341 } 3342 } 3343 3344 /* 3345 * wm_stop: [ifnet interface function] 3346 * 3347 * Stop transmission on the interface. 3348 */ 3349 static void 3350 wm_stop(struct ifnet *ifp, int disable) 3351 { 3352 struct wm_softc *sc = ifp->if_softc; 3353 struct wm_txsoft *txs; 3354 int i; 3355 3356 /* Stop the one second clock. */ 3357 callout_stop(&sc->sc_tick_ch); 3358 3359 /* Stop the 82547 Tx FIFO stall check timer. */ 3360 if (sc->sc_type == WM_T_82547) 3361 callout_stop(&sc->sc_txfifo_ch); 3362 3363 if (sc->sc_flags & WM_F_HAS_MII) { 3364 /* Down the MII. */ 3365 mii_down(&sc->sc_mii); 3366 } 3367 3368 /* Stop the transmit and receive processes. */ 3369 CSR_WRITE(sc, WMREG_TCTL, 0); 3370 CSR_WRITE(sc, WMREG_RCTL, 0); 3371 3372 /* 3373 * Clear the interrupt mask to ensure the device cannot assert its 3374 * interrupt line. 3375 * Clear sc->sc_icr to ensure wm_intr() makes no attempt to service 3376 * any currently pending or shared interrupt. 3377 */ 3378 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3379 sc->sc_icr = 0; 3380 3381 /* Release any queued transmit buffers. */ 3382 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 3383 txs = &sc->sc_txsoft[i]; 3384 if (txs->txs_mbuf != NULL) { 3385 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3386 m_freem(txs->txs_mbuf); 3387 txs->txs_mbuf = NULL; 3388 } 3389 } 3390 3391 if (disable) 3392 wm_rxdrain(sc); 3393 3394 /* Mark the interface as down and cancel the watchdog timer. */ 3395 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3396 ifp->if_timer = 0; 3397 } 3398 3399 void 3400 wm_get_auto_rd_dome(struct wm_softc *sc) 3401 { 3402 int i; 3403 3404 /* wait for eeprom to reload */ 3405 switch (sc->sc_type) { 3406 case WM_T_82571: 3407 case WM_T_82572: 3408 case WM_T_82573: 3409 case WM_T_80003: 3410 case WM_T_ICH8: 3411 case WM_T_ICH9: 3412 for (i = 10; i > 0; i--) { 3413 if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD) 3414 break; 3415 delay(1000); 3416 } 3417 if (i == 0) { 3418 log(LOG_ERR, "%s: auto read from eeprom failed to " 3419 "complete\n", sc->sc_dev.dv_xname); 3420 } 3421 break; 3422 default: 3423 delay(5000); 3424 break; 3425 } 3426 3427 /* Phy configuration starts after EECD_AUTO_RD is set */ 3428 if (sc->sc_type == WM_T_82573) 3429 delay(25000); 3430 } 3431 3432 /* 3433 * wm_acquire_eeprom: 3434 * 3435 * Perform the EEPROM handshake required on some chips. 3436 */ 3437 static int 3438 wm_acquire_eeprom(struct wm_softc *sc) 3439 { 3440 uint32_t reg; 3441 int x; 3442 int ret = 0; 3443 3444 /* always success */ 3445 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 3446 return 0; 3447 3448 if (sc->sc_flags & WM_F_SWFWHW_SYNC) { 3449 ret = wm_get_swfwhw_semaphore(sc); 3450 } else if (sc->sc_flags & WM_F_SWFW_SYNC) { 3451 /* this will also do wm_get_swsm_semaphore() if needed */ 3452 ret = wm_get_swfw_semaphore(sc, SWFW_EEP_SM); 3453 } else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) { 3454 ret = wm_get_swsm_semaphore(sc); 3455 } 3456 3457 if (ret) 3458 return 1; 3459 3460 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3461 reg = CSR_READ(sc, WMREG_EECD); 3462 3463 /* Request EEPROM access. */ 3464 reg |= EECD_EE_REQ; 3465 CSR_WRITE(sc, WMREG_EECD, reg); 3466 3467 /* ..and wait for it to be granted. */ 3468 for (x = 0; x < 1000; x++) { 3469 reg = CSR_READ(sc, WMREG_EECD); 3470 if (reg & EECD_EE_GNT) 3471 break; 3472 delay(5); 3473 } 3474 if ((reg & EECD_EE_GNT) == 0) { 3475 aprint_error("%s: could not acquire EEPROM GNT\n", 3476 sc->sc_dev.dv_xname); 3477 reg &= ~EECD_EE_REQ; 3478 CSR_WRITE(sc, WMREG_EECD, reg); 3479 if (sc->sc_flags & WM_F_SWFWHW_SYNC) 3480 wm_put_swfwhw_semaphore(sc); 3481 if (sc->sc_flags & WM_F_SWFW_SYNC) 3482 wm_put_swfw_semaphore(sc, SWFW_EEP_SM); 3483 else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 3484 wm_put_swsm_semaphore(sc); 3485 return (1); 3486 } 3487 } 3488 3489 return (0); 3490 } 3491 3492 /* 3493 * wm_release_eeprom: 3494 * 3495 * Release the EEPROM mutex. 3496 */ 3497 static void 3498 wm_release_eeprom(struct wm_softc *sc) 3499 { 3500 uint32_t reg; 3501 3502 /* always success */ 3503 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 3504 return; 3505 3506 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 3507 reg = CSR_READ(sc, WMREG_EECD); 3508 reg &= ~EECD_EE_REQ; 3509 CSR_WRITE(sc, WMREG_EECD, reg); 3510 } 3511 3512 if (sc->sc_flags & WM_F_SWFWHW_SYNC) 3513 wm_put_swfwhw_semaphore(sc); 3514 if (sc->sc_flags & WM_F_SWFW_SYNC) 3515 wm_put_swfw_semaphore(sc, SWFW_EEP_SM); 3516 else if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 3517 wm_put_swsm_semaphore(sc); 3518 } 3519 3520 /* 3521 * wm_eeprom_sendbits: 3522 * 3523 * Send a series of bits to the EEPROM. 3524 */ 3525 static void 3526 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 3527 { 3528 uint32_t reg; 3529 int x; 3530 3531 reg = CSR_READ(sc, WMREG_EECD); 3532 3533 for (x = nbits; x > 0; x--) { 3534 if (bits & (1U << (x - 1))) 3535 reg |= EECD_DI; 3536 else 3537 reg &= ~EECD_DI; 3538 CSR_WRITE(sc, WMREG_EECD, reg); 3539 delay(2); 3540 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3541 delay(2); 3542 CSR_WRITE(sc, WMREG_EECD, reg); 3543 delay(2); 3544 } 3545 } 3546 3547 /* 3548 * wm_eeprom_recvbits: 3549 * 3550 * Receive a series of bits from the EEPROM. 3551 */ 3552 static void 3553 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 3554 { 3555 uint32_t reg, val; 3556 int x; 3557 3558 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 3559 3560 val = 0; 3561 for (x = nbits; x > 0; x--) { 3562 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 3563 delay(2); 3564 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 3565 val |= (1U << (x - 1)); 3566 CSR_WRITE(sc, WMREG_EECD, reg); 3567 delay(2); 3568 } 3569 *valp = val; 3570 } 3571 3572 /* 3573 * wm_read_eeprom_uwire: 3574 * 3575 * Read a word from the EEPROM using the MicroWire protocol. 3576 */ 3577 static int 3578 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3579 { 3580 uint32_t reg, val; 3581 int i; 3582 3583 for (i = 0; i < wordcnt; i++) { 3584 /* Clear SK and DI. */ 3585 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 3586 CSR_WRITE(sc, WMREG_EECD, reg); 3587 3588 /* Set CHIP SELECT. */ 3589 reg |= EECD_CS; 3590 CSR_WRITE(sc, WMREG_EECD, reg); 3591 delay(2); 3592 3593 /* Shift in the READ command. */ 3594 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 3595 3596 /* Shift in address. */ 3597 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 3598 3599 /* Shift out the data. */ 3600 wm_eeprom_recvbits(sc, &val, 16); 3601 data[i] = val & 0xffff; 3602 3603 /* Clear CHIP SELECT. */ 3604 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 3605 CSR_WRITE(sc, WMREG_EECD, reg); 3606 delay(2); 3607 } 3608 3609 return (0); 3610 } 3611 3612 /* 3613 * wm_spi_eeprom_ready: 3614 * 3615 * Wait for a SPI EEPROM to be ready for commands. 3616 */ 3617 static int 3618 wm_spi_eeprom_ready(struct wm_softc *sc) 3619 { 3620 uint32_t val; 3621 int usec; 3622 3623 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 3624 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 3625 wm_eeprom_recvbits(sc, &val, 8); 3626 if ((val & SPI_SR_RDY) == 0) 3627 break; 3628 } 3629 if (usec >= SPI_MAX_RETRIES) { 3630 aprint_error("%s: EEPROM failed to become ready\n", 3631 sc->sc_dev.dv_xname); 3632 return (1); 3633 } 3634 return (0); 3635 } 3636 3637 /* 3638 * wm_read_eeprom_spi: 3639 * 3640 * Read a work from the EEPROM using the SPI protocol. 3641 */ 3642 static int 3643 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3644 { 3645 uint32_t reg, val; 3646 int i; 3647 uint8_t opc; 3648 3649 /* Clear SK and CS. */ 3650 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 3651 CSR_WRITE(sc, WMREG_EECD, reg); 3652 delay(2); 3653 3654 if (wm_spi_eeprom_ready(sc)) 3655 return (1); 3656 3657 /* Toggle CS to flush commands. */ 3658 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 3659 delay(2); 3660 CSR_WRITE(sc, WMREG_EECD, reg); 3661 delay(2); 3662 3663 opc = SPI_OPC_READ; 3664 if (sc->sc_ee_addrbits == 8 && word >= 128) 3665 opc |= SPI_OPC_A8; 3666 3667 wm_eeprom_sendbits(sc, opc, 8); 3668 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 3669 3670 for (i = 0; i < wordcnt; i++) { 3671 wm_eeprom_recvbits(sc, &val, 16); 3672 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 3673 } 3674 3675 /* Raise CS and clear SK. */ 3676 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 3677 CSR_WRITE(sc, WMREG_EECD, reg); 3678 delay(2); 3679 3680 return (0); 3681 } 3682 3683 #define EEPROM_CHECKSUM 0xBABA 3684 #define EEPROM_SIZE 0x0040 3685 3686 /* 3687 * wm_validate_eeprom_checksum 3688 * 3689 * The checksum is defined as the sum of the first 64 (16 bit) words. 3690 */ 3691 static int 3692 wm_validate_eeprom_checksum(struct wm_softc *sc) 3693 { 3694 uint16_t checksum; 3695 uint16_t eeprom_data; 3696 int i; 3697 3698 checksum = 0; 3699 3700 for (i = 0; i < EEPROM_SIZE; i++) { 3701 if (wm_read_eeprom(sc, i, 1, &eeprom_data)) 3702 return 1; 3703 checksum += eeprom_data; 3704 } 3705 3706 if (checksum != (uint16_t) EEPROM_CHECKSUM) 3707 return 1; 3708 3709 return 0; 3710 } 3711 3712 /* 3713 * wm_read_eeprom: 3714 * 3715 * Read data from the serial EEPROM. 3716 */ 3717 static int 3718 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3719 { 3720 int rv; 3721 3722 if (sc->sc_flags & WM_F_EEPROM_INVALID) 3723 return 1; 3724 3725 if (wm_acquire_eeprom(sc)) 3726 return 1; 3727 3728 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)) 3729 rv = wm_read_eeprom_ich8(sc, word, wordcnt, data); 3730 else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR) 3731 rv = wm_read_eeprom_eerd(sc, word, wordcnt, data); 3732 else if (sc->sc_flags & WM_F_EEPROM_SPI) 3733 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3734 else 3735 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3736 3737 wm_release_eeprom(sc); 3738 return rv; 3739 } 3740 3741 static int 3742 wm_read_eeprom_eerd(struct wm_softc *sc, int offset, int wordcnt, 3743 uint16_t *data) 3744 { 3745 int i, eerd = 0; 3746 int error = 0; 3747 3748 for (i = 0; i < wordcnt; i++) { 3749 eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START; 3750 3751 CSR_WRITE(sc, WMREG_EERD, eerd); 3752 error = wm_poll_eerd_eewr_done(sc, WMREG_EERD); 3753 if (error != 0) 3754 break; 3755 3756 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT); 3757 } 3758 3759 return error; 3760 } 3761 3762 static int 3763 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw) 3764 { 3765 uint32_t attempts = 100000; 3766 uint32_t i, reg = 0; 3767 int32_t done = -1; 3768 3769 for (i = 0; i < attempts; i++) { 3770 reg = CSR_READ(sc, rw); 3771 3772 if (reg & EERD_DONE) { 3773 done = 0; 3774 break; 3775 } 3776 delay(5); 3777 } 3778 3779 return done; 3780 } 3781 3782 /* 3783 * wm_add_rxbuf: 3784 * 3785 * Add a receive buffer to the indiciated descriptor. 3786 */ 3787 static int 3788 wm_add_rxbuf(struct wm_softc *sc, int idx) 3789 { 3790 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3791 struct mbuf *m; 3792 int error; 3793 3794 MGETHDR(m, M_DONTWAIT, MT_DATA); 3795 if (m == NULL) 3796 return (ENOBUFS); 3797 3798 MCLGET(m, M_DONTWAIT); 3799 if ((m->m_flags & M_EXT) == 0) { 3800 m_freem(m); 3801 return (ENOBUFS); 3802 } 3803 3804 if (rxs->rxs_mbuf != NULL) 3805 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3806 3807 rxs->rxs_mbuf = m; 3808 3809 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3810 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3811 BUS_DMA_READ|BUS_DMA_NOWAIT); 3812 if (error) { 3813 /* XXX XXX XXX */ 3814 printf("%s: unable to load rx DMA map %d, error = %d\n", 3815 sc->sc_dev.dv_xname, idx, error); 3816 panic("wm_add_rxbuf"); 3817 } 3818 3819 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3820 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3821 3822 WM_INIT_RXDESC(sc, idx); 3823 3824 return (0); 3825 } 3826 3827 /* 3828 * wm_set_ral: 3829 * 3830 * Set an entery in the receive address list. 3831 */ 3832 static void 3833 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3834 { 3835 uint32_t ral_lo, ral_hi; 3836 3837 if (enaddr != NULL) { 3838 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3839 (enaddr[3] << 24); 3840 ral_hi = enaddr[4] | (enaddr[5] << 8); 3841 ral_hi |= RAL_AV; 3842 } else { 3843 ral_lo = 0; 3844 ral_hi = 0; 3845 } 3846 3847 if (sc->sc_type >= WM_T_82544) { 3848 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3849 ral_lo); 3850 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3851 ral_hi); 3852 } else { 3853 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3854 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3855 } 3856 } 3857 3858 /* 3859 * wm_mchash: 3860 * 3861 * Compute the hash of the multicast address for the 4096-bit 3862 * multicast filter. 3863 */ 3864 static uint32_t 3865 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3866 { 3867 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3868 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3869 static const int ich8_lo_shift[4] = { 6, 5, 4, 2 }; 3870 static const int ich8_hi_shift[4] = { 2, 3, 4, 6 }; 3871 uint32_t hash; 3872 3873 if (sc->sc_type == WM_T_ICH8) { 3874 hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) | 3875 (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]); 3876 return (hash & 0x3ff); 3877 } 3878 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3879 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3880 3881 return (hash & 0xfff); 3882 } 3883 3884 /* 3885 * wm_set_filter: 3886 * 3887 * Set up the receive filter. 3888 */ 3889 static void 3890 wm_set_filter(struct wm_softc *sc) 3891 { 3892 struct ethercom *ec = &sc->sc_ethercom; 3893 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3894 struct ether_multi *enm; 3895 struct ether_multistep step; 3896 bus_addr_t mta_reg; 3897 uint32_t hash, reg, bit; 3898 int i, size; 3899 3900 if (sc->sc_type >= WM_T_82544) 3901 mta_reg = WMREG_CORDOVA_MTA; 3902 else 3903 mta_reg = WMREG_MTA; 3904 3905 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3906 3907 if (ifp->if_flags & IFF_BROADCAST) 3908 sc->sc_rctl |= RCTL_BAM; 3909 if (ifp->if_flags & IFF_PROMISC) { 3910 sc->sc_rctl |= RCTL_UPE; 3911 goto allmulti; 3912 } 3913 3914 /* 3915 * Set the station address in the first RAL slot, and 3916 * clear the remaining slots. 3917 */ 3918 if (sc->sc_type == WM_T_ICH8) 3919 size = WM_ICH8_RAL_TABSIZE; 3920 else 3921 size = WM_RAL_TABSIZE; 3922 wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 3923 for (i = 1; i < size; i++) 3924 wm_set_ral(sc, NULL, i); 3925 3926 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)) 3927 size = WM_ICH8_MC_TABSIZE; 3928 else 3929 size = WM_MC_TABSIZE; 3930 /* Clear out the multicast table. */ 3931 for (i = 0; i < size; i++) 3932 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3933 3934 ETHER_FIRST_MULTI(step, ec, enm); 3935 while (enm != NULL) { 3936 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3937 /* 3938 * We must listen to a range of multicast addresses. 3939 * For now, just accept all multicasts, rather than 3940 * trying to set only those filter bits needed to match 3941 * the range. (At this time, the only use of address 3942 * ranges is for IP multicast routing, for which the 3943 * range is big enough to require all bits set.) 3944 */ 3945 goto allmulti; 3946 } 3947 3948 hash = wm_mchash(sc, enm->enm_addrlo); 3949 3950 reg = (hash >> 5); 3951 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)) 3952 reg &= 0x1f; 3953 else 3954 reg &= 0x7f; 3955 bit = hash & 0x1f; 3956 3957 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3958 hash |= 1U << bit; 3959 3960 /* XXX Hardware bug?? */ 3961 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3962 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3963 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3964 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3965 } else 3966 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3967 3968 ETHER_NEXT_MULTI(step, enm); 3969 } 3970 3971 ifp->if_flags &= ~IFF_ALLMULTI; 3972 goto setit; 3973 3974 allmulti: 3975 ifp->if_flags |= IFF_ALLMULTI; 3976 sc->sc_rctl |= RCTL_MPE; 3977 3978 setit: 3979 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3980 } 3981 3982 /* 3983 * wm_tbi_mediainit: 3984 * 3985 * Initialize media for use on 1000BASE-X devices. 3986 */ 3987 static void 3988 wm_tbi_mediainit(struct wm_softc *sc) 3989 { 3990 const char *sep = ""; 3991 3992 if (sc->sc_type < WM_T_82543) 3993 sc->sc_tipg = TIPG_WM_DFLT; 3994 else 3995 sc->sc_tipg = TIPG_LG_DFLT; 3996 3997 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3998 wm_tbi_mediastatus); 3999 4000 /* 4001 * SWD Pins: 4002 * 4003 * 0 = Link LED (output) 4004 * 1 = Loss Of Signal (input) 4005 */ 4006 sc->sc_ctrl |= CTRL_SWDPIO(0); 4007 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 4008 4009 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4010 4011 #define ADD(ss, mm, dd) \ 4012 do { \ 4013 aprint_normal("%s%s", sep, ss); \ 4014 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 4015 sep = ", "; \ 4016 } while (/*CONSTCOND*/0) 4017 4018 aprint_normal("%s: ", sc->sc_dev.dv_xname); 4019 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 4020 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 4021 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 4022 aprint_normal("\n"); 4023 4024 #undef ADD 4025 4026 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 4027 } 4028 4029 /* 4030 * wm_tbi_mediastatus: [ifmedia interface function] 4031 * 4032 * Get the current interface media status on a 1000BASE-X device. 4033 */ 4034 static void 4035 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 4036 { 4037 struct wm_softc *sc = ifp->if_softc; 4038 uint32_t ctrl; 4039 4040 ifmr->ifm_status = IFM_AVALID; 4041 ifmr->ifm_active = IFM_ETHER; 4042 4043 if (sc->sc_tbi_linkup == 0) { 4044 ifmr->ifm_active |= IFM_NONE; 4045 return; 4046 } 4047 4048 ifmr->ifm_status |= IFM_ACTIVE; 4049 ifmr->ifm_active |= IFM_1000_SX; 4050 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 4051 ifmr->ifm_active |= IFM_FDX; 4052 ctrl = CSR_READ(sc, WMREG_CTRL); 4053 if (ctrl & CTRL_RFCE) 4054 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 4055 if (ctrl & CTRL_TFCE) 4056 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 4057 } 4058 4059 /* 4060 * wm_tbi_mediachange: [ifmedia interface function] 4061 * 4062 * Set hardware to newly-selected media on a 1000BASE-X device. 4063 */ 4064 static int 4065 wm_tbi_mediachange(struct ifnet *ifp) 4066 { 4067 struct wm_softc *sc = ifp->if_softc; 4068 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 4069 uint32_t status; 4070 int i; 4071 4072 sc->sc_txcw = ife->ifm_data; 4073 DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x on entry\n", 4074 sc->sc_dev.dv_xname,sc->sc_txcw)); 4075 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 4076 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 4077 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 4078 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 4079 sc->sc_txcw |= TXCW_ANE; 4080 } else { 4081 /*If autonegotiation is turned off, force link up and turn on full duplex*/ 4082 sc->sc_txcw &= ~TXCW_ANE; 4083 sc->sc_ctrl |= CTRL_SLU | CTRL_FD; 4084 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4085 delay(1000); 4086 } 4087 4088 DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n", 4089 sc->sc_dev.dv_xname,sc->sc_txcw)); 4090 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 4091 delay(10000); 4092 4093 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 4094 4095 sc->sc_tbi_anstate = 0; 4096 4097 i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1); 4098 DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", sc->sc_dev.dv_xname,i)); 4099 4100 /* 4101 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the 4102 * optics detect a signal, 0 if they don't. 4103 */ 4104 if (((i != 0) && (sc->sc_type >= WM_T_82544)) || (i == 0)) { 4105 /* Have signal; wait for the link to come up. */ 4106 4107 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 4108 /* 4109 * Reset the link, and let autonegotiation do its thing 4110 */ 4111 sc->sc_ctrl |= CTRL_LRST; 4112 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4113 delay(1000); 4114 sc->sc_ctrl &= ~CTRL_LRST; 4115 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4116 delay(1000); 4117 } 4118 4119 for (i = 0; i < 50; i++) { 4120 delay(10000); 4121 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 4122 break; 4123 } 4124 4125 DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n", 4126 sc->sc_dev.dv_xname,i)); 4127 4128 status = CSR_READ(sc, WMREG_STATUS); 4129 DPRINTF(WM_DEBUG_LINK, 4130 ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n", 4131 sc->sc_dev.dv_xname,status, STATUS_LU)); 4132 if (status & STATUS_LU) { 4133 /* Link is up. */ 4134 DPRINTF(WM_DEBUG_LINK, 4135 ("%s: LINK: set media -> link up %s\n", 4136 sc->sc_dev.dv_xname, 4137 (status & STATUS_FD) ? "FDX" : "HDX")); 4138 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 4139 sc->sc_fcrtl &= ~FCRTL_XONE; 4140 if (status & STATUS_FD) 4141 sc->sc_tctl |= 4142 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4143 else 4144 sc->sc_tctl |= 4145 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 4146 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 4147 sc->sc_fcrtl |= FCRTL_XONE; 4148 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4149 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 4150 WMREG_OLD_FCRTL : WMREG_FCRTL, 4151 sc->sc_fcrtl); 4152 sc->sc_tbi_linkup = 1; 4153 } else { 4154 /* Link is down. */ 4155 DPRINTF(WM_DEBUG_LINK, 4156 ("%s: LINK: set media -> link down\n", 4157 sc->sc_dev.dv_xname)); 4158 sc->sc_tbi_linkup = 0; 4159 } 4160 } else { 4161 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 4162 sc->sc_dev.dv_xname)); 4163 sc->sc_tbi_linkup = 0; 4164 } 4165 4166 wm_tbi_set_linkled(sc); 4167 4168 return (0); 4169 } 4170 4171 /* 4172 * wm_tbi_set_linkled: 4173 * 4174 * Update the link LED on 1000BASE-X devices. 4175 */ 4176 static void 4177 wm_tbi_set_linkled(struct wm_softc *sc) 4178 { 4179 4180 if (sc->sc_tbi_linkup) 4181 sc->sc_ctrl |= CTRL_SWDPIN(0); 4182 else 4183 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 4184 4185 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4186 } 4187 4188 /* 4189 * wm_tbi_check_link: 4190 * 4191 * Check the link on 1000BASE-X devices. 4192 */ 4193 static void 4194 wm_tbi_check_link(struct wm_softc *sc) 4195 { 4196 uint32_t rxcw, ctrl, status; 4197 4198 if (sc->sc_tbi_anstate == 0) 4199 return; 4200 else if (sc->sc_tbi_anstate > 1) { 4201 DPRINTF(WM_DEBUG_LINK, 4202 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 4203 sc->sc_tbi_anstate)); 4204 sc->sc_tbi_anstate--; 4205 return; 4206 } 4207 4208 sc->sc_tbi_anstate = 0; 4209 4210 rxcw = CSR_READ(sc, WMREG_RXCW); 4211 ctrl = CSR_READ(sc, WMREG_CTRL); 4212 status = CSR_READ(sc, WMREG_STATUS); 4213 4214 if ((status & STATUS_LU) == 0) { 4215 DPRINTF(WM_DEBUG_LINK, 4216 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 4217 sc->sc_tbi_linkup = 0; 4218 } else { 4219 DPRINTF(WM_DEBUG_LINK, 4220 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 4221 (status & STATUS_FD) ? "FDX" : "HDX")); 4222 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 4223 sc->sc_fcrtl &= ~FCRTL_XONE; 4224 if (status & STATUS_FD) 4225 sc->sc_tctl |= 4226 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4227 else 4228 sc->sc_tctl |= 4229 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 4230 if (ctrl & CTRL_TFCE) 4231 sc->sc_fcrtl |= FCRTL_XONE; 4232 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4233 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 4234 WMREG_OLD_FCRTL : WMREG_FCRTL, 4235 sc->sc_fcrtl); 4236 sc->sc_tbi_linkup = 1; 4237 } 4238 4239 wm_tbi_set_linkled(sc); 4240 } 4241 4242 /* 4243 * wm_gmii_reset: 4244 * 4245 * Reset the PHY. 4246 */ 4247 static void 4248 wm_gmii_reset(struct wm_softc *sc) 4249 { 4250 uint32_t reg; 4251 int func = 0; /* XXX gcc */ 4252 4253 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)) { 4254 if (wm_get_swfwhw_semaphore(sc)) 4255 return; 4256 } 4257 if (sc->sc_type == WM_T_80003) { 4258 func = (CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1; 4259 if (wm_get_swfw_semaphore(sc, 4260 func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4261 return; 4262 } 4263 if (sc->sc_type >= WM_T_82544) { 4264 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 4265 delay(20000); 4266 4267 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4268 delay(20000); 4269 } else { 4270 /* 4271 * With 82543, we need to force speed and duplex on the MAC 4272 * equal to what the PHY speed and duplex configuration is. 4273 * In addition, we need to perform a hardware reset on the PHY 4274 * to take it out of reset. 4275 */ 4276 sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX; 4277 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4278 4279 /* The PHY reset pin is active-low. */ 4280 reg = CSR_READ(sc, WMREG_CTRL_EXT); 4281 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 4282 CTRL_EXT_SWDPIN(4)); 4283 reg |= CTRL_EXT_SWDPIO(4); 4284 4285 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 4286 delay(10); 4287 4288 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 4289 delay(10000); 4290 4291 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 4292 delay(10); 4293 #if 0 4294 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 4295 #endif 4296 } 4297 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)) 4298 wm_put_swfwhw_semaphore(sc); 4299 if (sc->sc_type == WM_T_80003) 4300 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4301 } 4302 4303 /* 4304 * wm_gmii_mediainit: 4305 * 4306 * Initialize media for use on 1000BASE-T devices. 4307 */ 4308 static void 4309 wm_gmii_mediainit(struct wm_softc *sc) 4310 { 4311 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 4312 4313 /* We have MII. */ 4314 sc->sc_flags |= WM_F_HAS_MII; 4315 4316 if (sc->sc_type >= WM_T_80003) 4317 sc->sc_tipg = TIPG_1000T_80003_DFLT; 4318 else 4319 sc->sc_tipg = TIPG_1000T_DFLT; 4320 4321 /* 4322 * Let the chip set speed/duplex on its own based on 4323 * signals from the PHY. 4324 * XXXbouyer - I'm not sure this is right for the 80003, 4325 * the em driver only sets CTRL_SLU here - but it seems to work. 4326 */ 4327 sc->sc_ctrl |= CTRL_SLU; 4328 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4329 4330 /* Initialize our media structures and probe the GMII. */ 4331 sc->sc_mii.mii_ifp = ifp; 4332 4333 if (sc->sc_type >= WM_T_80003) { 4334 sc->sc_mii.mii_readreg = wm_gmii_i80003_readreg; 4335 sc->sc_mii.mii_writereg = wm_gmii_i80003_writereg; 4336 } else if (sc->sc_type >= WM_T_82544) { 4337 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 4338 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 4339 } else { 4340 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 4341 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 4342 } 4343 sc->sc_mii.mii_statchg = wm_gmii_statchg; 4344 4345 wm_gmii_reset(sc); 4346 4347 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 4348 wm_gmii_mediastatus); 4349 4350 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 4351 MII_OFFSET_ANY, MIIF_DOPAUSE); 4352 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 4353 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 4354 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 4355 } else 4356 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 4357 } 4358 4359 /* 4360 * wm_gmii_mediastatus: [ifmedia interface function] 4361 * 4362 * Get the current interface media status on a 1000BASE-T device. 4363 */ 4364 static void 4365 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 4366 { 4367 struct wm_softc *sc = ifp->if_softc; 4368 4369 mii_pollstat(&sc->sc_mii); 4370 ifmr->ifm_status = sc->sc_mii.mii_media_status; 4371 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 4372 sc->sc_flowflags; 4373 } 4374 4375 /* 4376 * wm_gmii_mediachange: [ifmedia interface function] 4377 * 4378 * Set hardware to newly-selected media on a 1000BASE-T device. 4379 */ 4380 static int 4381 wm_gmii_mediachange(struct ifnet *ifp) 4382 { 4383 struct wm_softc *sc = ifp->if_softc; 4384 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 4385 4386 if (ifp->if_flags & IFF_UP) { 4387 sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD); 4388 sc->sc_ctrl |= CTRL_SLU; 4389 if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 4390 || (sc->sc_type > WM_T_82543)) { 4391 sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX); 4392 } else { 4393 sc->sc_ctrl &= ~CTRL_ASDE; 4394 sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX; 4395 if (ife->ifm_media & IFM_FDX) 4396 sc->sc_ctrl |= CTRL_FD; 4397 switch(IFM_SUBTYPE(ife->ifm_media)) { 4398 case IFM_10_T: 4399 sc->sc_ctrl |= CTRL_SPEED_10; 4400 break; 4401 case IFM_100_TX: 4402 sc->sc_ctrl |= CTRL_SPEED_100; 4403 break; 4404 case IFM_1000_T: 4405 sc->sc_ctrl |= CTRL_SPEED_1000; 4406 break; 4407 default: 4408 panic("wm_gmii_mediachange: bad media 0x%x", 4409 ife->ifm_media); 4410 } 4411 } 4412 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4413 if (sc->sc_type <= WM_T_82543) 4414 wm_gmii_reset(sc); 4415 mii_mediachg(&sc->sc_mii); 4416 } 4417 return (0); 4418 } 4419 4420 #define MDI_IO CTRL_SWDPIN(2) 4421 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 4422 #define MDI_CLK CTRL_SWDPIN(3) 4423 4424 static void 4425 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 4426 { 4427 uint32_t i, v; 4428 4429 v = CSR_READ(sc, WMREG_CTRL); 4430 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 4431 v |= MDI_DIR | CTRL_SWDPIO(3); 4432 4433 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 4434 if (data & i) 4435 v |= MDI_IO; 4436 else 4437 v &= ~MDI_IO; 4438 CSR_WRITE(sc, WMREG_CTRL, v); 4439 delay(10); 4440 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 4441 delay(10); 4442 CSR_WRITE(sc, WMREG_CTRL, v); 4443 delay(10); 4444 } 4445 } 4446 4447 static uint32_t 4448 i82543_mii_recvbits(struct wm_softc *sc) 4449 { 4450 uint32_t v, i, data = 0; 4451 4452 v = CSR_READ(sc, WMREG_CTRL); 4453 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 4454 v |= CTRL_SWDPIO(3); 4455 4456 CSR_WRITE(sc, WMREG_CTRL, v); 4457 delay(10); 4458 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 4459 delay(10); 4460 CSR_WRITE(sc, WMREG_CTRL, v); 4461 delay(10); 4462 4463 for (i = 0; i < 16; i++) { 4464 data <<= 1; 4465 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 4466 delay(10); 4467 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 4468 data |= 1; 4469 CSR_WRITE(sc, WMREG_CTRL, v); 4470 delay(10); 4471 } 4472 4473 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 4474 delay(10); 4475 CSR_WRITE(sc, WMREG_CTRL, v); 4476 delay(10); 4477 4478 return (data); 4479 } 4480 4481 #undef MDI_IO 4482 #undef MDI_DIR 4483 #undef MDI_CLK 4484 4485 /* 4486 * wm_gmii_i82543_readreg: [mii interface function] 4487 * 4488 * Read a PHY register on the GMII (i82543 version). 4489 */ 4490 static int 4491 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 4492 { 4493 struct wm_softc *sc = (void *) self; 4494 int rv; 4495 4496 i82543_mii_sendbits(sc, 0xffffffffU, 32); 4497 i82543_mii_sendbits(sc, reg | (phy << 5) | 4498 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 4499 rv = i82543_mii_recvbits(sc) & 0xffff; 4500 4501 DPRINTF(WM_DEBUG_GMII, 4502 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 4503 sc->sc_dev.dv_xname, phy, reg, rv)); 4504 4505 return (rv); 4506 } 4507 4508 /* 4509 * wm_gmii_i82543_writereg: [mii interface function] 4510 * 4511 * Write a PHY register on the GMII (i82543 version). 4512 */ 4513 static void 4514 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 4515 { 4516 struct wm_softc *sc = (void *) self; 4517 4518 i82543_mii_sendbits(sc, 0xffffffffU, 32); 4519 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 4520 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 4521 (MII_COMMAND_START << 30), 32); 4522 } 4523 4524 /* 4525 * wm_gmii_i82544_readreg: [mii interface function] 4526 * 4527 * Read a PHY register on the GMII. 4528 */ 4529 static int 4530 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 4531 { 4532 struct wm_softc *sc = (void *) self; 4533 uint32_t mdic = 0; 4534 int i, rv; 4535 4536 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 4537 MDIC_REGADD(reg)); 4538 4539 for (i = 0; i < 320; i++) { 4540 mdic = CSR_READ(sc, WMREG_MDIC); 4541 if (mdic & MDIC_READY) 4542 break; 4543 delay(10); 4544 } 4545 4546 if ((mdic & MDIC_READY) == 0) { 4547 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 4548 sc->sc_dev.dv_xname, phy, reg); 4549 rv = 0; 4550 } else if (mdic & MDIC_E) { 4551 #if 0 /* This is normal if no PHY is present. */ 4552 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 4553 sc->sc_dev.dv_xname, phy, reg); 4554 #endif 4555 rv = 0; 4556 } else { 4557 rv = MDIC_DATA(mdic); 4558 if (rv == 0xffff) 4559 rv = 0; 4560 } 4561 4562 return (rv); 4563 } 4564 4565 /* 4566 * wm_gmii_i82544_writereg: [mii interface function] 4567 * 4568 * Write a PHY register on the GMII. 4569 */ 4570 static void 4571 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 4572 { 4573 struct wm_softc *sc = (void *) self; 4574 uint32_t mdic = 0; 4575 int i; 4576 4577 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 4578 MDIC_REGADD(reg) | MDIC_DATA(val)); 4579 4580 for (i = 0; i < 320; i++) { 4581 mdic = CSR_READ(sc, WMREG_MDIC); 4582 if (mdic & MDIC_READY) 4583 break; 4584 delay(10); 4585 } 4586 4587 if ((mdic & MDIC_READY) == 0) 4588 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 4589 sc->sc_dev.dv_xname, phy, reg); 4590 else if (mdic & MDIC_E) 4591 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 4592 sc->sc_dev.dv_xname, phy, reg); 4593 } 4594 4595 /* 4596 * wm_gmii_i80003_readreg: [mii interface function] 4597 * 4598 * Read a PHY register on the kumeran 4599 * This could be handled by the PHY layer if we didn't have to lock the 4600 * ressource ... 4601 */ 4602 static int 4603 wm_gmii_i80003_readreg(struct device *self, int phy, int reg) 4604 { 4605 struct wm_softc *sc = (void *) self; 4606 int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1); 4607 int rv; 4608 4609 if (phy != 1) /* only one PHY on kumeran bus */ 4610 return 0; 4611 4612 if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4613 return 0; 4614 4615 if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 4616 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT, 4617 reg >> GG82563_PAGE_SHIFT); 4618 } else { 4619 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT, 4620 reg >> GG82563_PAGE_SHIFT); 4621 } 4622 4623 rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS); 4624 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4625 return (rv); 4626 } 4627 4628 /* 4629 * wm_gmii_i80003_writereg: [mii interface function] 4630 * 4631 * Write a PHY register on the kumeran. 4632 * This could be handled by the PHY layer if we didn't have to lock the 4633 * ressource ... 4634 */ 4635 static void 4636 wm_gmii_i80003_writereg(struct device *self, int phy, int reg, int val) 4637 { 4638 struct wm_softc *sc = (void *) self; 4639 int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1); 4640 4641 if (phy != 1) /* only one PHY on kumeran bus */ 4642 return; 4643 4644 if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4645 return; 4646 4647 if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 4648 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT, 4649 reg >> GG82563_PAGE_SHIFT); 4650 } else { 4651 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT, 4652 reg >> GG82563_PAGE_SHIFT); 4653 } 4654 4655 wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val); 4656 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4657 } 4658 4659 /* 4660 * wm_gmii_statchg: [mii interface function] 4661 * 4662 * Callback from MII layer when media changes. 4663 */ 4664 static void 4665 wm_gmii_statchg(struct device *self) 4666 { 4667 struct wm_softc *sc = (void *) self; 4668 struct mii_data *mii = &sc->sc_mii; 4669 4670 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 4671 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 4672 sc->sc_fcrtl &= ~FCRTL_XONE; 4673 4674 /* 4675 * Get flow control negotiation result. 4676 */ 4677 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 4678 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 4679 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 4680 mii->mii_media_active &= ~IFM_ETH_FMASK; 4681 } 4682 4683 if (sc->sc_flowflags & IFM_FLOW) { 4684 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 4685 sc->sc_ctrl |= CTRL_TFCE; 4686 sc->sc_fcrtl |= FCRTL_XONE; 4687 } 4688 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 4689 sc->sc_ctrl |= CTRL_RFCE; 4690 } 4691 4692 if (sc->sc_mii.mii_media_active & IFM_FDX) { 4693 DPRINTF(WM_DEBUG_LINK, 4694 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 4695 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4696 } else { 4697 DPRINTF(WM_DEBUG_LINK, 4698 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 4699 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 4700 } 4701 4702 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 4703 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4704 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 4705 : WMREG_FCRTL, sc->sc_fcrtl); 4706 if (sc->sc_type >= WM_T_80003) { 4707 switch(IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 4708 case IFM_1000_T: 4709 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL, 4710 KUMCTRLSTA_HD_CTRL_1000_DEFAULT); 4711 sc->sc_tipg = TIPG_1000T_80003_DFLT; 4712 break; 4713 default: 4714 wm_kmrn_i80003_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL, 4715 KUMCTRLSTA_HD_CTRL_10_100_DEFAULT); 4716 sc->sc_tipg = TIPG_10_100_80003_DFLT; 4717 break; 4718 } 4719 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 4720 } 4721 } 4722 4723 /* 4724 * wm_kmrn_i80003_readreg: 4725 * 4726 * Read a kumeran register 4727 */ 4728 static int 4729 wm_kmrn_i80003_readreg(struct wm_softc *sc, int reg) 4730 { 4731 int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1); 4732 int rv; 4733 4734 if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4735 return 0; 4736 4737 CSR_WRITE(sc, WMREG_KUMCTRLSTA, 4738 ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | 4739 KUMCTRLSTA_REN); 4740 delay(2); 4741 4742 rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK; 4743 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4744 return (rv); 4745 } 4746 4747 /* 4748 * wm_kmrn_i80003_writereg: 4749 * 4750 * Write a kumeran register 4751 */ 4752 static void 4753 wm_kmrn_i80003_writereg(struct wm_softc *sc, int reg, int val) 4754 { 4755 int func = ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1); 4756 4757 if (wm_get_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM)) 4758 return; 4759 4760 CSR_WRITE(sc, WMREG_KUMCTRLSTA, 4761 ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | 4762 (val & KUMCTRLSTA_MASK)); 4763 wm_put_swfw_semaphore(sc, func ? SWFW_PHY1_SM : SWFW_PHY0_SM); 4764 } 4765 4766 static int 4767 wm_is_onboard_nvm_eeprom(struct wm_softc *sc) 4768 { 4769 uint32_t eecd = 0; 4770 4771 if (sc->sc_type == WM_T_82573) { 4772 eecd = CSR_READ(sc, WMREG_EECD); 4773 4774 /* Isolate bits 15 & 16 */ 4775 eecd = ((eecd >> 15) & 0x03); 4776 4777 /* If both bits are set, device is Flash type */ 4778 if (eecd == 0x03) { 4779 return 0; 4780 } 4781 } 4782 return 1; 4783 } 4784 4785 static int 4786 wm_get_swsm_semaphore(struct wm_softc *sc) 4787 { 4788 int32_t timeout; 4789 uint32_t swsm; 4790 4791 /* Get the FW semaphore. */ 4792 timeout = 1000 + 1; /* XXX */ 4793 while (timeout) { 4794 swsm = CSR_READ(sc, WMREG_SWSM); 4795 swsm |= SWSM_SWESMBI; 4796 CSR_WRITE(sc, WMREG_SWSM, swsm); 4797 /* if we managed to set the bit we got the semaphore. */ 4798 swsm = CSR_READ(sc, WMREG_SWSM); 4799 if (swsm & SWSM_SWESMBI) 4800 break; 4801 4802 delay(50); 4803 timeout--; 4804 } 4805 4806 if (timeout == 0) { 4807 aprint_error("%s: could not acquire EEPROM GNT\n", 4808 sc->sc_dev.dv_xname); 4809 /* Release semaphores */ 4810 wm_put_swsm_semaphore(sc); 4811 return 1; 4812 } 4813 return 0; 4814 } 4815 4816 static void 4817 wm_put_swsm_semaphore(struct wm_softc *sc) 4818 { 4819 uint32_t swsm; 4820 4821 swsm = CSR_READ(sc, WMREG_SWSM); 4822 swsm &= ~(SWSM_SWESMBI); 4823 CSR_WRITE(sc, WMREG_SWSM, swsm); 4824 } 4825 4826 static int 4827 wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask) 4828 { 4829 uint32_t swfw_sync; 4830 uint32_t swmask = mask << SWFW_SOFT_SHIFT; 4831 uint32_t fwmask = mask << SWFW_FIRM_SHIFT; 4832 int timeout = 200; 4833 4834 for(timeout = 0; timeout < 200; timeout++) { 4835 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) { 4836 if (wm_get_swsm_semaphore(sc)) 4837 return 1; 4838 } 4839 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC); 4840 if ((swfw_sync & (swmask | fwmask)) == 0) { 4841 swfw_sync |= swmask; 4842 CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync); 4843 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 4844 wm_put_swsm_semaphore(sc); 4845 return 0; 4846 } 4847 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 4848 wm_put_swsm_semaphore(sc); 4849 delay(5000); 4850 } 4851 printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n", 4852 sc->sc_dev.dv_xname, mask, swfw_sync); 4853 return 1; 4854 } 4855 4856 static void 4857 wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask) 4858 { 4859 uint32_t swfw_sync; 4860 4861 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) { 4862 while (wm_get_swsm_semaphore(sc) != 0) 4863 continue; 4864 } 4865 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC); 4866 swfw_sync &= ~(mask << SWFW_SOFT_SHIFT); 4867 CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync); 4868 if (sc->sc_flags & WM_F_EEPROM_SEMAPHORE) 4869 wm_put_swsm_semaphore(sc); 4870 } 4871 4872 static int 4873 wm_get_swfwhw_semaphore(struct wm_softc *sc) 4874 { 4875 uint32_t ext_ctrl; 4876 int timeout = 200; 4877 4878 for(timeout = 0; timeout < 200; timeout++) { 4879 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 4880 ext_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 4881 CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl); 4882 4883 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 4884 if (ext_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 4885 return 0; 4886 delay(5000); 4887 } 4888 printf("%s: failed to get swfwgw semaphore ext_ctrl 0x%x\n", 4889 sc->sc_dev.dv_xname, ext_ctrl); 4890 return 1; 4891 } 4892 4893 static void 4894 wm_put_swfwhw_semaphore(struct wm_softc *sc) 4895 { 4896 uint32_t ext_ctrl; 4897 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 4898 ext_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 4899 CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl); 4900 } 4901 4902 /****************************************************************************** 4903 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 4904 * register. 4905 * 4906 * sc - Struct containing variables accessed by shared code 4907 * offset - offset of word in the EEPROM to read 4908 * data - word read from the EEPROM 4909 * words - number of words to read 4910 *****************************************************************************/ 4911 static int 4912 wm_read_eeprom_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data) 4913 { 4914 int32_t error = 0; 4915 uint32_t flash_bank = 0; 4916 uint32_t act_offset = 0; 4917 uint32_t bank_offset = 0; 4918 uint16_t word = 0; 4919 uint16_t i = 0; 4920 4921 /* We need to know which is the valid flash bank. In the event 4922 * that we didn't allocate eeprom_shadow_ram, we may not be 4923 * managing flash_bank. So it cannot be trusted and needs 4924 * to be updated with each read. 4925 */ 4926 /* Value of bit 22 corresponds to the flash bank we're on. */ 4927 flash_bank = (CSR_READ(sc, WMREG_EECD) & EECD_SEC1VAL) ? 1 : 0; 4928 4929 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ 4930 bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2); 4931 4932 error = wm_get_swfwhw_semaphore(sc); 4933 if (error) 4934 return error; 4935 4936 for (i = 0; i < words; i++) { 4937 /* The NVM part needs a byte offset, hence * 2 */ 4938 act_offset = bank_offset + ((offset + i) * 2); 4939 error = wm_read_ich8_word(sc, act_offset, &word); 4940 if (error) 4941 break; 4942 data[i] = word; 4943 } 4944 4945 wm_put_swfwhw_semaphore(sc); 4946 return error; 4947 } 4948 4949 /****************************************************************************** 4950 * This function does initial flash setup so that a new read/write/erase cycle 4951 * can be started. 4952 * 4953 * sc - The pointer to the hw structure 4954 ****************************************************************************/ 4955 static int32_t 4956 wm_ich8_cycle_init(struct wm_softc *sc) 4957 { 4958 uint16_t hsfsts; 4959 int32_t error = 1; 4960 int32_t i = 0; 4961 4962 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 4963 4964 /* May be check the Flash Des Valid bit in Hw status */ 4965 if ((hsfsts & HSFSTS_FLDVAL) == 0) { 4966 return error; 4967 } 4968 4969 /* Clear FCERR in Hw status by writing 1 */ 4970 /* Clear DAEL in Hw status by writing a 1 */ 4971 hsfsts |= HSFSTS_ERR | HSFSTS_DAEL; 4972 4973 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 4974 4975 /* Either we should have a hardware SPI cycle in progress bit to check 4976 * against, in order to start a new cycle or FDONE bit should be changed 4977 * in the hardware so that it is 1 after harware reset, which can then be 4978 * used as an indication whether a cycle is in progress or has been 4979 * completed .. we should also have some software semaphore mechanism to 4980 * guard FDONE or the cycle in progress bit so that two threads access to 4981 * those bits can be sequentiallized or a way so that 2 threads dont 4982 * start the cycle at the same time */ 4983 4984 if ((hsfsts & HSFSTS_FLINPRO) == 0) { 4985 /* There is no cycle running at present, so we can start a cycle */ 4986 /* Begin by setting Flash Cycle Done. */ 4987 hsfsts |= HSFSTS_DONE; 4988 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 4989 error = 0; 4990 } else { 4991 /* otherwise poll for sometime so the current cycle has a chance 4992 * to end before giving up. */ 4993 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 4994 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 4995 if ((hsfsts & HSFSTS_FLINPRO) == 0) { 4996 error = 0; 4997 break; 4998 } 4999 delay(1); 5000 } 5001 if (error == 0) { 5002 /* Successful in waiting for previous cycle to timeout, 5003 * now set the Flash Cycle Done. */ 5004 hsfsts |= HSFSTS_DONE; 5005 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 5006 } 5007 } 5008 return error; 5009 } 5010 5011 /****************************************************************************** 5012 * This function starts a flash cycle and waits for its completion 5013 * 5014 * sc - The pointer to the hw structure 5015 ****************************************************************************/ 5016 static int32_t 5017 wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout) 5018 { 5019 uint16_t hsflctl; 5020 uint16_t hsfsts; 5021 int32_t error = 1; 5022 uint32_t i = 0; 5023 5024 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 5025 hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL); 5026 hsflctl |= HSFCTL_GO; 5027 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl); 5028 5029 /* wait till FDONE bit is set to 1 */ 5030 do { 5031 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 5032 if (hsfsts & HSFSTS_DONE) 5033 break; 5034 delay(1); 5035 i++; 5036 } while (i < timeout); 5037 if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0) { 5038 error = 0; 5039 } 5040 return error; 5041 } 5042 5043 /****************************************************************************** 5044 * Reads a byte or word from the NVM using the ICH8 flash access registers. 5045 * 5046 * sc - The pointer to the hw structure 5047 * index - The index of the byte or word to read. 5048 * size - Size of data to read, 1=byte 2=word 5049 * data - Pointer to the word to store the value read. 5050 *****************************************************************************/ 5051 static int32_t 5052 wm_read_ich8_data(struct wm_softc *sc, uint32_t index, 5053 uint32_t size, uint16_t* data) 5054 { 5055 uint16_t hsfsts; 5056 uint16_t hsflctl; 5057 uint32_t flash_linear_address; 5058 uint32_t flash_data = 0; 5059 int32_t error = 1; 5060 int32_t count = 0; 5061 5062 if (size < 1 || size > 2 || data == 0x0 || 5063 index > ICH_FLASH_LINEAR_ADDR_MASK) 5064 return error; 5065 5066 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 5067 sc->sc_ich8_flash_base; 5068 5069 do { 5070 delay(1); 5071 /* Steps */ 5072 error = wm_ich8_cycle_init(sc); 5073 if (error) 5074 break; 5075 5076 hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL); 5077 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 5078 hsflctl |= ((size - 1) << HSFCTL_BCOUNT_SHIFT) & HSFCTL_BCOUNT_MASK; 5079 hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT; 5080 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl); 5081 5082 /* Write the last 24 bits of index into Flash Linear address field in 5083 * Flash Address */ 5084 /* TODO: TBD maybe check the index against the size of flash */ 5085 5086 ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address); 5087 5088 error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT); 5089 5090 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole 5091 * sequence a few more times, else read in (shift in) the Flash Data0, 5092 * the order is least significant byte first msb to lsb */ 5093 if (error == 0) { 5094 flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0); 5095 if (size == 1) { 5096 *data = (uint8_t)(flash_data & 0x000000FF); 5097 } else if (size == 2) { 5098 *data = (uint16_t)(flash_data & 0x0000FFFF); 5099 } 5100 break; 5101 } else { 5102 /* If we've gotten here, then things are probably completely hosed, 5103 * but if the error condition is detected, it won't hurt to give 5104 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 5105 */ 5106 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 5107 if (hsfsts & HSFSTS_ERR) { 5108 /* Repeat for some time before giving up. */ 5109 continue; 5110 } else if ((hsfsts & HSFSTS_DONE) == 0) { 5111 break; 5112 } 5113 } 5114 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 5115 5116 return error; 5117 } 5118 5119 #if 0 5120 /****************************************************************************** 5121 * Reads a single byte from the NVM using the ICH8 flash access registers. 5122 * 5123 * sc - pointer to wm_hw structure 5124 * index - The index of the byte to read. 5125 * data - Pointer to a byte to store the value read. 5126 *****************************************************************************/ 5127 static int32_t 5128 wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data) 5129 { 5130 int32_t status; 5131 uint16_t word = 0; 5132 5133 status = wm_read_ich8_data(sc, index, 1, &word); 5134 if (status == 0) { 5135 *data = (uint8_t)word; 5136 } 5137 5138 return status; 5139 } 5140 #endif 5141 5142 /****************************************************************************** 5143 * Reads a word from the NVM using the ICH8 flash access registers. 5144 * 5145 * sc - pointer to wm_hw structure 5146 * index - The starting byte index of the word to read. 5147 * data - Pointer to a word to store the value read. 5148 *****************************************************************************/ 5149 static int32_t 5150 wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data) 5151 { 5152 int32_t status; 5153 5154 status = wm_read_ich8_data(sc, index, 2, data); 5155 return status; 5156 } 5157
Indexes created Fri Sep 26 08:10:20 GMT 2025