if_wm.c revision 1.394
1 /* $NetBSD: if_wm.c,v 1.394 2016/05/06 10:56:04 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /******************************************************************************* 39 40 Copyright (c) 2001-2005, Intel Corporation 41 All rights reserved. 42 43 Redistribution and use in source and binary forms, with or without 44 modification, are permitted provided that the following conditions are met: 45 46 1. Redistributions of source code must retain the above copyright notice, 47 this list of conditions and the following disclaimer. 48 49 2. Redistributions in binary form must reproduce the above copyright 50 notice, this list of conditions and the following disclaimer in the 51 documentation and/or other materials provided with the distribution. 52 53 3. Neither the name of the Intel Corporation nor the names of its 54 contributors may be used to endorse or promote products derived from 55 this software without specific prior written permission. 56 57 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 58 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 61 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 POSSIBILITY OF SUCH DAMAGE. 68 69 *******************************************************************************/ 70 /* 71 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 72 * 73 * TODO (in order of importance): 74 * 75 * - Check XXX'ed comments 76 * - Disable D0 LPLU on 8257[12356], 82580 and I350. 77 * - TX Multi queue 78 * - EEE (Energy Efficiency Ethernet) 79 * - Virtual Function 80 * - Set LED correctly (based on contents in EEPROM) 81 * - Rework how parameters are loaded from the EEPROM. 82 * - Image Unique ID 83 */ 84 85 #include <sys/cdefs.h> 86 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.394 2016/05/06 10:56:04 msaitoh Exp $"); 87 88 #ifdef _KERNEL_OPT 89 #include "opt_net_mpsafe.h" 90 #endif 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/callout.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kmem.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/ioctl.h> 101 #include <sys/errno.h> 102 #include <sys/device.h> 103 #include <sys/queue.h> 104 #include <sys/syslog.h> 105 #include <sys/interrupt.h> 106 107 #include <sys/rndsource.h> 108 109 #include <net/if.h> 110 #include <net/if_dl.h> 111 #include <net/if_media.h> 112 #include <net/if_ether.h> 113 114 #include <net/bpf.h> 115 116 #include <netinet/in.h> /* XXX for struct ip */ 117 #include <netinet/in_systm.h> /* XXX for struct ip */ 118 #include <netinet/ip.h> /* XXX for struct ip */ 119 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */ 120 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 121 122 #include <sys/bus.h> 123 #include <sys/intr.h> 124 #include <machine/endian.h> 125 126 #include <dev/mii/mii.h> 127 #include <dev/mii/miivar.h> 128 #include <dev/mii/miidevs.h> 129 #include <dev/mii/mii_bitbang.h> 130 #include <dev/mii/ikphyreg.h> 131 #include <dev/mii/igphyreg.h> 132 #include <dev/mii/igphyvar.h> 133 #include <dev/mii/inbmphyreg.h> 134 135 #include <dev/pci/pcireg.h> 136 #include <dev/pci/pcivar.h> 137 #include <dev/pci/pcidevs.h> 138 139 #include <dev/pci/if_wmreg.h> 140 #include <dev/pci/if_wmvar.h> 141 142 #ifdef WM_DEBUG 143 #define WM_DEBUG_LINK 0x01 144 #define WM_DEBUG_TX 0x02 145 #define WM_DEBUG_RX 0x04 146 #define WM_DEBUG_GMII 0x08 147 #define WM_DEBUG_MANAGE 0x10 148 #define WM_DEBUG_NVM 0x20 149 #define WM_DEBUG_INIT 0x40 150 int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII 151 | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT; 152 153 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 154 #else 155 #define DPRINTF(x, y) /* nothing */ 156 #endif /* WM_DEBUG */ 157 158 #ifdef NET_MPSAFE 159 #define WM_MPSAFE 1 160 #endif 161 162 /* 163 * This device driver's max interrupt numbers. 164 */ 165 #define WM_MAX_NTXINTR 16 166 #define WM_MAX_NRXINTR 16 167 #define WM_MAX_NINTR (WM_MAX_NTXINTR + WM_MAX_NRXINTR + 1) 168 169 /* 170 * Transmit descriptor list size. Due to errata, we can only have 171 * 256 hardware descriptors in the ring on < 82544, but we use 4096 172 * on >= 82544. We tell the upper layers that they can queue a lot 173 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 174 * of them at a time. 175 * 176 * We allow up to 256 (!) DMA segments per packet. Pathological packet 177 * chains containing many small mbufs have been observed in zero-copy 178 * situations with jumbo frames. 179 */ 180 #define WM_NTXSEGS 256 181 #define WM_IFQUEUELEN 256 182 #define WM_TXQUEUELEN_MAX 64 183 #define WM_TXQUEUELEN_MAX_82547 16 184 #define WM_TXQUEUELEN(txq) ((txq)->txq_num) 185 #define WM_TXQUEUELEN_MASK(txq) (WM_TXQUEUELEN(txq) - 1) 186 #define WM_TXQUEUE_GC(txq) (WM_TXQUEUELEN(txq) / 8) 187 #define WM_NTXDESC_82542 256 188 #define WM_NTXDESC_82544 4096 189 #define WM_NTXDESC(txq) ((txq)->txq_ndesc) 190 #define WM_NTXDESC_MASK(txq) (WM_NTXDESC(txq) - 1) 191 #define WM_TXDESCSIZE(txq) (WM_NTXDESC(txq) * sizeof(wiseman_txdesc_t)) 192 #define WM_NEXTTX(txq, x) (((x) + 1) & WM_NTXDESC_MASK(txq)) 193 #define WM_NEXTTXS(txq, x) (((x) + 1) & WM_TXQUEUELEN_MASK(txq)) 194 195 #define WM_MAXTXDMA (2 * round_page(IP_MAXPACKET)) /* for TSO */ 196 197 /* 198 * Receive descriptor list size. We have one Rx buffer for normal 199 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 200 * packet. We allocate 256 receive descriptors, each with a 2k 201 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 202 */ 203 #define WM_NRXDESC 256 204 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 205 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 206 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 207 208 typedef union txdescs { 209 wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544]; 210 nq_txdesc_t sctxu_nq_txdescs[WM_NTXDESC_82544]; 211 } txdescs_t; 212 213 #define WM_CDTXOFF(x) (sizeof(wiseman_txdesc_t) * x) 214 #define WM_CDRXOFF(x) (sizeof(wiseman_rxdesc_t) * x) 215 216 /* 217 * Software state for transmit jobs. 218 */ 219 struct wm_txsoft { 220 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 221 bus_dmamap_t txs_dmamap; /* our DMA map */ 222 int txs_firstdesc; /* first descriptor in packet */ 223 int txs_lastdesc; /* last descriptor in packet */ 224 int txs_ndesc; /* # of descriptors used */ 225 }; 226 227 /* 228 * Software state for receive buffers. Each descriptor gets a 229 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 230 * more than one buffer, we chain them together. 231 */ 232 struct wm_rxsoft { 233 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 234 bus_dmamap_t rxs_dmamap; /* our DMA map */ 235 }; 236 237 #define WM_LINKUP_TIMEOUT 50 238 239 static uint16_t swfwphysem[] = { 240 SWFW_PHY0_SM, 241 SWFW_PHY1_SM, 242 SWFW_PHY2_SM, 243 SWFW_PHY3_SM 244 }; 245 246 static const uint32_t wm_82580_rxpbs_table[] = { 247 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 248 }; 249 250 struct wm_softc; 251 252 struct wm_txqueue { 253 kmutex_t *txq_lock; /* lock for tx operations */ 254 255 struct wm_softc *txq_sc; 256 257 int txq_id; /* index of transmit queues */ 258 int txq_intr_idx; /* index of MSI-X tables */ 259 260 /* Software state for the transmit descriptors. */ 261 int txq_num; /* must be a power of two */ 262 struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX]; 263 264 /* TX control data structures. */ 265 int txq_ndesc; /* must be a power of two */ 266 txdescs_t *txq_descs_u; 267 bus_dmamap_t txq_desc_dmamap; /* control data DMA map */ 268 bus_dma_segment_t txq_desc_seg; /* control data segment */ 269 int txq_desc_rseg; /* real number of control segment */ 270 size_t txq_desc_size; /* control data size */ 271 #define txq_desc_dma txq_desc_dmamap->dm_segs[0].ds_addr 272 #define txq_descs txq_descs_u->sctxu_txdescs 273 #define txq_nq_descs txq_descs_u->sctxu_nq_txdescs 274 275 bus_addr_t txq_tdt_reg; /* offset of TDT register */ 276 277 int txq_free; /* number of free Tx descriptors */ 278 int txq_next; /* next ready Tx descriptor */ 279 280 int txq_sfree; /* number of free Tx jobs */ 281 int txq_snext; /* next free Tx job */ 282 int txq_sdirty; /* dirty Tx jobs */ 283 284 /* These 4 variables are used only on the 82547. */ 285 int txq_fifo_size; /* Tx FIFO size */ 286 int txq_fifo_head; /* current head of FIFO */ 287 uint32_t txq_fifo_addr; /* internal address of start of FIFO */ 288 int txq_fifo_stall; /* Tx FIFO is stalled */ 289 290 /* XXX which event counter is required? */ 291 }; 292 293 struct wm_rxqueue { 294 kmutex_t *rxq_lock; /* lock for rx operations */ 295 296 struct wm_softc *rxq_sc; 297 298 int rxq_id; /* index of receive queues */ 299 int rxq_intr_idx; /* index of MSI-X tables */ 300 301 /* Software state for the receive descriptors. */ 302 wiseman_rxdesc_t *rxq_descs; 303 304 /* RX control data structures. */ 305 struct wm_rxsoft rxq_soft[WM_NRXDESC]; 306 bus_dmamap_t rxq_desc_dmamap; /* control data DMA map */ 307 bus_dma_segment_t rxq_desc_seg; /* control data segment */ 308 int rxq_desc_rseg; /* real number of control segment */ 309 size_t rxq_desc_size; /* control data size */ 310 #define rxq_desc_dma rxq_desc_dmamap->dm_segs[0].ds_addr 311 312 bus_addr_t rxq_rdt_reg; /* offset of RDT register */ 313 314 int rxq_ptr; /* next ready Rx desc/queue ent */ 315 int rxq_discard; 316 int rxq_len; 317 struct mbuf *rxq_head; 318 struct mbuf *rxq_tail; 319 struct mbuf **rxq_tailp; 320 321 /* XXX which event counter is required? */ 322 }; 323 324 /* 325 * Software state per device. 326 */ 327 struct wm_softc { 328 device_t sc_dev; /* generic device information */ 329 bus_space_tag_t sc_st; /* bus space tag */ 330 bus_space_handle_t sc_sh; /* bus space handle */ 331 bus_size_t sc_ss; /* bus space size */ 332 bus_space_tag_t sc_iot; /* I/O space tag */ 333 bus_space_handle_t sc_ioh; /* I/O space handle */ 334 bus_size_t sc_ios; /* I/O space size */ 335 bus_space_tag_t sc_flasht; /* flash registers space tag */ 336 bus_space_handle_t sc_flashh; /* flash registers space handle */ 337 bus_size_t sc_flashs; /* flash registers space size */ 338 off_t sc_flashreg_offset; /* 339 * offset to flash registers from 340 * start of BAR 341 */ 342 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 343 344 struct ethercom sc_ethercom; /* ethernet common data */ 345 struct mii_data sc_mii; /* MII/media information */ 346 347 pci_chipset_tag_t sc_pc; 348 pcitag_t sc_pcitag; 349 int sc_bus_speed; /* PCI/PCIX bus speed */ 350 int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */ 351 352 uint16_t sc_pcidevid; /* PCI device ID */ 353 wm_chip_type sc_type; /* MAC type */ 354 int sc_rev; /* MAC revision */ 355 wm_phy_type sc_phytype; /* PHY type */ 356 uint32_t sc_mediatype; /* Media type (Copper, Fiber, SERDES)*/ 357 #define WM_MEDIATYPE_UNKNOWN 0x00 358 #define WM_MEDIATYPE_FIBER 0x01 359 #define WM_MEDIATYPE_COPPER 0x02 360 #define WM_MEDIATYPE_SERDES 0x03 /* Internal SERDES */ 361 int sc_funcid; /* unit number of the chip (0 to 3) */ 362 int sc_flags; /* flags; see below */ 363 int sc_if_flags; /* last if_flags */ 364 int sc_flowflags; /* 802.3x flow control flags */ 365 int sc_align_tweak; 366 367 void *sc_ihs[WM_MAX_NINTR]; /* 368 * interrupt cookie. 369 * legacy and msi use sc_ihs[0]. 370 */ 371 pci_intr_handle_t *sc_intrs; /* legacy and msi use sc_intrs[0] */ 372 int sc_nintrs; /* number of interrupts */ 373 374 int sc_link_intr_idx; /* index of MSI-X tables */ 375 376 callout_t sc_tick_ch; /* tick callout */ 377 bool sc_stopping; 378 379 int sc_nvm_ver_major; 380 int sc_nvm_ver_minor; 381 int sc_nvm_ver_build; 382 int sc_nvm_addrbits; /* NVM address bits */ 383 unsigned int sc_nvm_wordsize; /* NVM word size */ 384 int sc_ich8_flash_base; 385 int sc_ich8_flash_bank_size; 386 int sc_nvm_k1_enabled; 387 388 int sc_ntxqueues; 389 struct wm_txqueue *sc_txq; 390 391 int sc_nrxqueues; 392 struct wm_rxqueue *sc_rxq; 393 394 #ifdef WM_EVENT_COUNTERS 395 /* Event counters. */ 396 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 397 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 398 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 399 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 400 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 401 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 402 struct evcnt sc_ev_linkintr; /* Link interrupts */ 403 404 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 405 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 406 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 407 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 408 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 409 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound (IPv4) */ 410 struct evcnt sc_ev_txtso6; /* TCP seg offload out-bound (IPv6) */ 411 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 412 413 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 414 struct evcnt sc_ev_txdrop; /* Tx packets dropped(too many segs) */ 415 416 struct evcnt sc_ev_tu; /* Tx underrun */ 417 418 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 419 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 420 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 421 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 422 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 423 #endif /* WM_EVENT_COUNTERS */ 424 425 /* This variable are used only on the 82547. */ 426 callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 427 428 uint32_t sc_ctrl; /* prototype CTRL register */ 429 #if 0 430 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 431 #endif 432 uint32_t sc_icr; /* prototype interrupt bits */ 433 uint32_t sc_itr; /* prototype intr throttling reg */ 434 uint32_t sc_tctl; /* prototype TCTL register */ 435 uint32_t sc_rctl; /* prototype RCTL register */ 436 uint32_t sc_txcw; /* prototype TXCW register */ 437 uint32_t sc_tipg; /* prototype TIPG register */ 438 uint32_t sc_fcrtl; /* prototype FCRTL register */ 439 uint32_t sc_pba; /* prototype PBA register */ 440 441 int sc_tbi_linkup; /* TBI link status */ 442 int sc_tbi_serdes_anegticks; /* autonegotiation ticks */ 443 int sc_tbi_serdes_ticks; /* tbi ticks */ 444 445 int sc_mchash_type; /* multicast filter offset */ 446 447 krndsource_t rnd_source; /* random source */ 448 449 kmutex_t *sc_core_lock; /* lock for softc operations */ 450 451 struct if_percpuq *sc_ipq; /* softint-based input queues */ 452 }; 453 454 #define WM_TX_LOCK(_txq) if ((_txq)->txq_lock) mutex_enter((_txq)->txq_lock) 455 #define WM_TX_UNLOCK(_txq) if ((_txq)->txq_lock) mutex_exit((_txq)->txq_lock) 456 #define WM_TX_LOCKED(_txq) (!(_txq)->txq_lock || mutex_owned((_txq)->txq_lock)) 457 #define WM_RX_LOCK(_rxq) if ((_rxq)->rxq_lock) mutex_enter((_rxq)->rxq_lock) 458 #define WM_RX_UNLOCK(_rxq) if ((_rxq)->rxq_lock) mutex_exit((_rxq)->rxq_lock) 459 #define WM_RX_LOCKED(_rxq) (!(_rxq)->rxq_lock || mutex_owned((_rxq)->rxq_lock)) 460 #define WM_CORE_LOCK(_sc) if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock) 461 #define WM_CORE_UNLOCK(_sc) if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock) 462 #define WM_CORE_LOCKED(_sc) (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock)) 463 464 #ifdef WM_MPSAFE 465 #define CALLOUT_FLAGS CALLOUT_MPSAFE 466 #else 467 #define CALLOUT_FLAGS 0 468 #endif 469 470 #define WM_RXCHAIN_RESET(rxq) \ 471 do { \ 472 (rxq)->rxq_tailp = &(rxq)->rxq_head; \ 473 *(rxq)->rxq_tailp = NULL; \ 474 (rxq)->rxq_len = 0; \ 475 } while (/*CONSTCOND*/0) 476 477 #define WM_RXCHAIN_LINK(rxq, m) \ 478 do { \ 479 *(rxq)->rxq_tailp = (rxq)->rxq_tail = (m); \ 480 (rxq)->rxq_tailp = &(m)->m_next; \ 481 } while (/*CONSTCOND*/0) 482 483 #ifdef WM_EVENT_COUNTERS 484 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 485 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 486 #else 487 #define WM_EVCNT_INCR(ev) /* nothing */ 488 #define WM_EVCNT_ADD(ev, val) /* nothing */ 489 #endif 490 491 #define CSR_READ(sc, reg) \ 492 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 493 #define CSR_WRITE(sc, reg, val) \ 494 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 495 #define CSR_WRITE_FLUSH(sc) \ 496 (void) CSR_READ((sc), WMREG_STATUS) 497 498 #define ICH8_FLASH_READ32(sc, reg) \ 499 bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, \ 500 (reg) + sc->sc_flashreg_offset) 501 #define ICH8_FLASH_WRITE32(sc, reg, data) \ 502 bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, \ 503 (reg) + sc->sc_flashreg_offset, (data)) 504 505 #define ICH8_FLASH_READ16(sc, reg) \ 506 bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, \ 507 (reg) + sc->sc_flashreg_offset) 508 #define ICH8_FLASH_WRITE16(sc, reg, data) \ 509 bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, \ 510 (reg) + sc->sc_flashreg_offset, (data)) 511 512 #define WM_CDTXADDR(txq, x) ((txq)->txq_desc_dma + WM_CDTXOFF((x))) 513 #define WM_CDRXADDR(rxq, x) ((rxq)->rxq_desc_dma + WM_CDRXOFF((x))) 514 515 #define WM_CDTXADDR_LO(txq, x) (WM_CDTXADDR((txq), (x)) & 0xffffffffU) 516 #define WM_CDTXADDR_HI(txq, x) \ 517 (sizeof(bus_addr_t) == 8 ? \ 518 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0) 519 520 #define WM_CDRXADDR_LO(rxq, x) (WM_CDRXADDR((rxq), (x)) & 0xffffffffU) 521 #define WM_CDRXADDR_HI(rxq, x) \ 522 (sizeof(bus_addr_t) == 8 ? \ 523 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0) 524 525 /* 526 * Register read/write functions. 527 * Other than CSR_{READ|WRITE}(). 528 */ 529 #if 0 530 static inline uint32_t wm_io_read(struct wm_softc *, int); 531 #endif 532 static inline void wm_io_write(struct wm_softc *, int, uint32_t); 533 static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t, 534 uint32_t, uint32_t); 535 static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t); 536 537 /* 538 * Descriptor sync/init functions. 539 */ 540 static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int); 541 static inline void wm_cdrxsync(struct wm_rxqueue *, int, int); 542 static inline void wm_init_rxdesc(struct wm_rxqueue *, int); 543 544 /* 545 * Device driver interface functions and commonly used functions. 546 * match, attach, detach, init, start, stop, ioctl, watchdog and so on. 547 */ 548 static const struct wm_product *wm_lookup(const struct pci_attach_args *); 549 static int wm_match(device_t, cfdata_t, void *); 550 static void wm_attach(device_t, device_t, void *); 551 static int wm_detach(device_t, int); 552 static bool wm_suspend(device_t, const pmf_qual_t *); 553 static bool wm_resume(device_t, const pmf_qual_t *); 554 static void wm_watchdog(struct ifnet *); 555 static void wm_tick(void *); 556 static int wm_ifflags_cb(struct ethercom *); 557 static int wm_ioctl(struct ifnet *, u_long, void *); 558 /* MAC address related */ 559 static uint16_t wm_check_alt_mac_addr(struct wm_softc *); 560 static int wm_read_mac_addr(struct wm_softc *, uint8_t *); 561 static void wm_set_ral(struct wm_softc *, const uint8_t *, int); 562 static uint32_t wm_mchash(struct wm_softc *, const uint8_t *); 563 static void wm_set_filter(struct wm_softc *); 564 /* Reset and init related */ 565 static void wm_set_vlan(struct wm_softc *); 566 static void wm_set_pcie_completion_timeout(struct wm_softc *); 567 static void wm_get_auto_rd_done(struct wm_softc *); 568 static void wm_lan_init_done(struct wm_softc *); 569 static void wm_get_cfg_done(struct wm_softc *); 570 static void wm_initialize_hardware_bits(struct wm_softc *); 571 static uint32_t wm_rxpbs_adjust_82580(uint32_t); 572 static void wm_reset(struct wm_softc *); 573 static int wm_add_rxbuf(struct wm_rxqueue *, int); 574 static void wm_rxdrain(struct wm_rxqueue *); 575 static void wm_rss_getkey(uint8_t *); 576 static void wm_init_rss(struct wm_softc *); 577 static void wm_adjust_qnum(struct wm_softc *, int); 578 static int wm_setup_legacy(struct wm_softc *); 579 static int wm_setup_msix(struct wm_softc *); 580 static int wm_init(struct ifnet *); 581 static int wm_init_locked(struct ifnet *); 582 static void wm_stop(struct ifnet *, int); 583 static void wm_stop_locked(struct ifnet *, int); 584 static void wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *); 585 static void wm_82547_txfifo_stall(void *); 586 static int wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *); 587 /* DMA related */ 588 static int wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *); 589 static void wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *); 590 static void wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *); 591 static void wm_init_tx_regs(struct wm_softc *, struct wm_txqueue *); 592 static int wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *); 593 static void wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *); 594 static void wm_init_rx_regs(struct wm_softc *, struct wm_rxqueue *); 595 static int wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *); 596 static void wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *); 597 static void wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *); 598 static int wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *); 599 static void wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *); 600 static int wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *); 601 static void wm_init_tx_queue(struct wm_softc *, struct wm_txqueue *); 602 static int wm_init_rx_queue(struct wm_softc *, struct wm_rxqueue *); 603 static int wm_alloc_txrx_queues(struct wm_softc *); 604 static void wm_free_txrx_queues(struct wm_softc *); 605 static int wm_init_txrx_queues(struct wm_softc *); 606 /* Start */ 607 static int wm_tx_offload(struct wm_softc *, struct wm_txsoft *, 608 uint32_t *, uint8_t *); 609 static void wm_start(struct ifnet *); 610 static void wm_start_locked(struct ifnet *); 611 static int wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *, 612 uint32_t *, uint32_t *, bool *); 613 static void wm_nq_start(struct ifnet *); 614 static void wm_nq_start_locked(struct ifnet *); 615 /* Interrupt */ 616 static int wm_txeof(struct wm_softc *); 617 static void wm_rxeof(struct wm_rxqueue *); 618 static void wm_linkintr_gmii(struct wm_softc *, uint32_t); 619 static void wm_linkintr_tbi(struct wm_softc *, uint32_t); 620 static void wm_linkintr_serdes(struct wm_softc *, uint32_t); 621 static void wm_linkintr(struct wm_softc *, uint32_t); 622 static int wm_intr_legacy(void *); 623 static int wm_txintr_msix(void *); 624 static int wm_rxintr_msix(void *); 625 static int wm_linkintr_msix(void *); 626 627 /* 628 * Media related. 629 * GMII, SGMII, TBI, SERDES and SFP. 630 */ 631 /* Common */ 632 static void wm_tbi_serdes_set_linkled(struct wm_softc *); 633 /* GMII related */ 634 static void wm_gmii_reset(struct wm_softc *); 635 static int wm_get_phy_id_82575(struct wm_softc *); 636 static void wm_gmii_mediainit(struct wm_softc *, pci_product_id_t); 637 static int wm_gmii_mediachange(struct ifnet *); 638 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 639 static void wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int); 640 static uint32_t wm_i82543_mii_recvbits(struct wm_softc *); 641 static int wm_gmii_i82543_readreg(device_t, int, int); 642 static void wm_gmii_i82543_writereg(device_t, int, int, int); 643 static int wm_gmii_i82544_readreg(device_t, int, int); 644 static void wm_gmii_i82544_writereg(device_t, int, int, int); 645 static int wm_gmii_i80003_readreg(device_t, int, int); 646 static void wm_gmii_i80003_writereg(device_t, int, int, int); 647 static int wm_gmii_bm_readreg(device_t, int, int); 648 static void wm_gmii_bm_writereg(device_t, int, int, int); 649 static void wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int); 650 static int wm_gmii_hv_readreg(device_t, int, int); 651 static void wm_gmii_hv_writereg(device_t, int, int, int); 652 static int wm_gmii_82580_readreg(device_t, int, int); 653 static void wm_gmii_82580_writereg(device_t, int, int, int); 654 static int wm_gmii_gs40g_readreg(device_t, int, int); 655 static void wm_gmii_gs40g_writereg(device_t, int, int, int); 656 static void wm_gmii_statchg(struct ifnet *); 657 static int wm_kmrn_readreg(struct wm_softc *, int); 658 static void wm_kmrn_writereg(struct wm_softc *, int, int); 659 /* SGMII */ 660 static bool wm_sgmii_uses_mdio(struct wm_softc *); 661 static int wm_sgmii_readreg(device_t, int, int); 662 static void wm_sgmii_writereg(device_t, int, int, int); 663 /* TBI related */ 664 static void wm_tbi_mediainit(struct wm_softc *); 665 static int wm_tbi_mediachange(struct ifnet *); 666 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 667 static int wm_check_for_link(struct wm_softc *); 668 static void wm_tbi_tick(struct wm_softc *); 669 /* SERDES related */ 670 static void wm_serdes_power_up_link_82575(struct wm_softc *); 671 static int wm_serdes_mediachange(struct ifnet *); 672 static void wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *); 673 static void wm_serdes_tick(struct wm_softc *); 674 /* SFP related */ 675 static int wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *); 676 static uint32_t wm_sfp_get_media_type(struct wm_softc *); 677 678 /* 679 * NVM related. 680 * Microwire, SPI (w/wo EERD) and Flash. 681 */ 682 /* Misc functions */ 683 static void wm_eeprom_sendbits(struct wm_softc *, uint32_t, int); 684 static void wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int); 685 static int wm_nvm_set_addrbits_size_eecd(struct wm_softc *); 686 /* Microwire */ 687 static int wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *); 688 /* SPI */ 689 static int wm_nvm_ready_spi(struct wm_softc *); 690 static int wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *); 691 /* Using with EERD */ 692 static int wm_poll_eerd_eewr_done(struct wm_softc *, int); 693 static int wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *); 694 /* Flash */ 695 static int wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *, 696 unsigned int *); 697 static int32_t wm_ich8_cycle_init(struct wm_softc *); 698 static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t); 699 static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t, 700 uint32_t *); 701 static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *); 702 static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *); 703 static int32_t wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *); 704 static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *); 705 static int wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *); 706 /* iNVM */ 707 static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *); 708 static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *); 709 /* Lock, detecting NVM type, validate checksum and read */ 710 static int wm_nvm_acquire(struct wm_softc *); 711 static void wm_nvm_release(struct wm_softc *); 712 static int wm_nvm_is_onboard_eeprom(struct wm_softc *); 713 static int wm_nvm_get_flash_presence_i210(struct wm_softc *); 714 static int wm_nvm_validate_checksum(struct wm_softc *); 715 static void wm_nvm_version_invm(struct wm_softc *); 716 static void wm_nvm_version(struct wm_softc *); 717 static int wm_nvm_read(struct wm_softc *, int, int, uint16_t *); 718 719 /* 720 * Hardware semaphores. 721 * Very complexed... 722 */ 723 static int wm_get_swsm_semaphore(struct wm_softc *); 724 static void wm_put_swsm_semaphore(struct wm_softc *); 725 static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t); 726 static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t); 727 static int wm_get_swfwhw_semaphore(struct wm_softc *); 728 static void wm_put_swfwhw_semaphore(struct wm_softc *); 729 static int wm_get_hw_semaphore_82573(struct wm_softc *); 730 static void wm_put_hw_semaphore_82573(struct wm_softc *); 731 732 /* 733 * Management mode and power management related subroutines. 734 * BMC, AMT, suspend/resume and EEE. 735 */ 736 #ifdef WM_WOL 737 static int wm_check_mng_mode(struct wm_softc *); 738 static int wm_check_mng_mode_ich8lan(struct wm_softc *); 739 static int wm_check_mng_mode_82574(struct wm_softc *); 740 static int wm_check_mng_mode_generic(struct wm_softc *); 741 #endif 742 static int wm_enable_mng_pass_thru(struct wm_softc *); 743 static bool wm_phy_resetisblocked(struct wm_softc *); 744 static void wm_get_hw_control(struct wm_softc *); 745 static void wm_release_hw_control(struct wm_softc *); 746 static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool); 747 static void wm_smbustopci(struct wm_softc *); 748 static void wm_init_manageability(struct wm_softc *); 749 static void wm_release_manageability(struct wm_softc *); 750 static void wm_get_wakeup(struct wm_softc *); 751 #ifdef WM_WOL 752 static void wm_enable_phy_wakeup(struct wm_softc *); 753 static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *); 754 static void wm_enable_wakeup(struct wm_softc *); 755 #endif 756 /* LPLU (Low Power Link Up) */ 757 static void wm_lplu_d0_disable(struct wm_softc *); 758 static void wm_lplu_d0_disable_pch(struct wm_softc *); 759 /* EEE */ 760 static void wm_set_eee_i350(struct wm_softc *); 761 762 /* 763 * Workarounds (mainly PHY related). 764 * Basically, PHY's workarounds are in the PHY drivers. 765 */ 766 static void wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *); 767 static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *); 768 static void wm_hv_phy_workaround_ich8lan(struct wm_softc *); 769 static void wm_lv_phy_workaround_ich8lan(struct wm_softc *); 770 static void wm_k1_gig_workaround_hv(struct wm_softc *, int); 771 static void wm_set_mdio_slow_mode_hv(struct wm_softc *); 772 static void wm_configure_k1_ich8lan(struct wm_softc *, int); 773 static void wm_reset_init_script_82575(struct wm_softc *); 774 static void wm_reset_mdicnfg_82580(struct wm_softc *); 775 static void wm_pll_workaround_i210(struct wm_softc *); 776 777 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc), 778 wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 779 780 /* 781 * Devices supported by this driver. 782 */ 783 static const struct wm_product { 784 pci_vendor_id_t wmp_vendor; 785 pci_product_id_t wmp_product; 786 const char *wmp_name; 787 wm_chip_type wmp_type; 788 uint32_t wmp_flags; 789 #define WMP_F_UNKNOWN WM_MEDIATYPE_UNKNOWN 790 #define WMP_F_FIBER WM_MEDIATYPE_FIBER 791 #define WMP_F_COPPER WM_MEDIATYPE_COPPER 792 #define WMP_F_SERDES WM_MEDIATYPE_SERDES 793 #define WMP_MEDIATYPE(x) ((x) & 0x03) 794 } wm_products[] = { 795 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 796 "Intel i82542 1000BASE-X Ethernet", 797 WM_T_82542_2_1, WMP_F_FIBER }, 798 799 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 800 "Intel i82543GC 1000BASE-X Ethernet", 801 WM_T_82543, WMP_F_FIBER }, 802 803 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 804 "Intel i82543GC 1000BASE-T Ethernet", 805 WM_T_82543, WMP_F_COPPER }, 806 807 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 808 "Intel i82544EI 1000BASE-T Ethernet", 809 WM_T_82544, WMP_F_COPPER }, 810 811 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 812 "Intel i82544EI 1000BASE-X Ethernet", 813 WM_T_82544, WMP_F_FIBER }, 814 815 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 816 "Intel i82544GC 1000BASE-T Ethernet", 817 WM_T_82544, WMP_F_COPPER }, 818 819 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 820 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 821 WM_T_82544, WMP_F_COPPER }, 822 823 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 824 "Intel i82540EM 1000BASE-T Ethernet", 825 WM_T_82540, WMP_F_COPPER }, 826 827 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 828 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 829 WM_T_82540, WMP_F_COPPER }, 830 831 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 832 "Intel i82540EP 1000BASE-T Ethernet", 833 WM_T_82540, WMP_F_COPPER }, 834 835 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 836 "Intel i82540EP 1000BASE-T Ethernet", 837 WM_T_82540, WMP_F_COPPER }, 838 839 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 840 "Intel i82540EP 1000BASE-T Ethernet", 841 WM_T_82540, WMP_F_COPPER }, 842 843 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 844 "Intel i82545EM 1000BASE-T Ethernet", 845 WM_T_82545, WMP_F_COPPER }, 846 847 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 848 "Intel i82545GM 1000BASE-T Ethernet", 849 WM_T_82545_3, WMP_F_COPPER }, 850 851 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 852 "Intel i82545GM 1000BASE-X Ethernet", 853 WM_T_82545_3, WMP_F_FIBER }, 854 855 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 856 "Intel i82545GM Gigabit Ethernet (SERDES)", 857 WM_T_82545_3, WMP_F_SERDES }, 858 859 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 860 "Intel i82546EB 1000BASE-T Ethernet", 861 WM_T_82546, WMP_F_COPPER }, 862 863 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 864 "Intel i82546EB 1000BASE-T Ethernet", 865 WM_T_82546, WMP_F_COPPER }, 866 867 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 868 "Intel i82545EM 1000BASE-X Ethernet", 869 WM_T_82545, WMP_F_FIBER }, 870 871 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 872 "Intel i82546EB 1000BASE-X Ethernet", 873 WM_T_82546, WMP_F_FIBER }, 874 875 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 876 "Intel i82546GB 1000BASE-T Ethernet", 877 WM_T_82546_3, WMP_F_COPPER }, 878 879 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 880 "Intel i82546GB 1000BASE-X Ethernet", 881 WM_T_82546_3, WMP_F_FIBER }, 882 883 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 884 "Intel i82546GB Gigabit Ethernet (SERDES)", 885 WM_T_82546_3, WMP_F_SERDES }, 886 887 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER, 888 "i82546GB quad-port Gigabit Ethernet", 889 WM_T_82546_3, WMP_F_COPPER }, 890 891 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3, 892 "i82546GB quad-port Gigabit Ethernet (KSP3)", 893 WM_T_82546_3, WMP_F_COPPER }, 894 895 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, 896 "Intel PRO/1000MT (82546GB)", 897 WM_T_82546_3, WMP_F_COPPER }, 898 899 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 900 "Intel i82541EI 1000BASE-T Ethernet", 901 WM_T_82541, WMP_F_COPPER }, 902 903 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, 904 "Intel i82541ER (LOM) 1000BASE-T Ethernet", 905 WM_T_82541, WMP_F_COPPER }, 906 907 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 908 "Intel i82541EI Mobile 1000BASE-T Ethernet", 909 WM_T_82541, WMP_F_COPPER }, 910 911 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 912 "Intel i82541ER 1000BASE-T Ethernet", 913 WM_T_82541_2, WMP_F_COPPER }, 914 915 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 916 "Intel i82541GI 1000BASE-T Ethernet", 917 WM_T_82541_2, WMP_F_COPPER }, 918 919 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 920 "Intel i82541GI Mobile 1000BASE-T Ethernet", 921 WM_T_82541_2, WMP_F_COPPER }, 922 923 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 924 "Intel i82541PI 1000BASE-T Ethernet", 925 WM_T_82541_2, WMP_F_COPPER }, 926 927 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 928 "Intel i82547EI 1000BASE-T Ethernet", 929 WM_T_82547, WMP_F_COPPER }, 930 931 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, 932 "Intel i82547EI Mobile 1000BASE-T Ethernet", 933 WM_T_82547, WMP_F_COPPER }, 934 935 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 936 "Intel i82547GI 1000BASE-T Ethernet", 937 WM_T_82547_2, WMP_F_COPPER }, 938 939 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, 940 "Intel PRO/1000 PT (82571EB)", 941 WM_T_82571, WMP_F_COPPER }, 942 943 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, 944 "Intel PRO/1000 PF (82571EB)", 945 WM_T_82571, WMP_F_FIBER }, 946 947 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, 948 "Intel PRO/1000 PB (82571EB)", 949 WM_T_82571, WMP_F_SERDES }, 950 951 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER, 952 "Intel PRO/1000 QT (82571EB)", 953 WM_T_82571, WMP_F_COPPER }, 954 955 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER, 956 "Intel PRO/1000 PT Quad Port Server Adapter", 957 WM_T_82571, WMP_F_COPPER, }, 958 959 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER, 960 "Intel Gigabit PT Quad Port Server ExpressModule", 961 WM_T_82571, WMP_F_COPPER, }, 962 963 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES, 964 "Intel 82571EB Dual Gigabit Ethernet (SERDES)", 965 WM_T_82571, WMP_F_SERDES, }, 966 967 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES, 968 "Intel 82571EB Quad Gigabit Ethernet (SERDES)", 969 WM_T_82571, WMP_F_SERDES, }, 970 971 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER, 972 "Intel 82571EB Quad 1000baseX Ethernet", 973 WM_T_82571, WMP_F_FIBER, }, 974 975 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, 976 "Intel i82572EI 1000baseT Ethernet", 977 WM_T_82572, WMP_F_COPPER }, 978 979 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, 980 "Intel i82572EI 1000baseX Ethernet", 981 WM_T_82572, WMP_F_FIBER }, 982 983 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, 984 "Intel i82572EI Gigabit Ethernet (SERDES)", 985 WM_T_82572, WMP_F_SERDES }, 986 987 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, 988 "Intel i82572EI 1000baseT Ethernet", 989 WM_T_82572, WMP_F_COPPER }, 990 991 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, 992 "Intel i82573E", 993 WM_T_82573, WMP_F_COPPER }, 994 995 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, 996 "Intel i82573E IAMT", 997 WM_T_82573, WMP_F_COPPER }, 998 999 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, 1000 "Intel i82573L Gigabit Ethernet", 1001 WM_T_82573, WMP_F_COPPER }, 1002 1003 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L, 1004 "Intel i82574L", 1005 WM_T_82574, WMP_F_COPPER }, 1006 1007 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA, 1008 "Intel i82574L", 1009 WM_T_82574, WMP_F_COPPER }, 1010 1011 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V, 1012 "Intel i82583V", 1013 WM_T_82583, WMP_F_COPPER }, 1014 1015 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT, 1016 "i80003 dual 1000baseT Ethernet", 1017 WM_T_80003, WMP_F_COPPER }, 1018 1019 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT, 1020 "i80003 dual 1000baseX Ethernet", 1021 WM_T_80003, WMP_F_COPPER }, 1022 1023 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT, 1024 "Intel i80003ES2 dual Gigabit Ethernet (SERDES)", 1025 WM_T_80003, WMP_F_SERDES }, 1026 1027 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT, 1028 "Intel i80003 1000baseT Ethernet", 1029 WM_T_80003, WMP_F_COPPER }, 1030 1031 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT, 1032 "Intel i80003 Gigabit Ethernet (SERDES)", 1033 WM_T_80003, WMP_F_SERDES }, 1034 1035 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT, 1036 "Intel i82801H (M_AMT) LAN Controller", 1037 WM_T_ICH8, WMP_F_COPPER }, 1038 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT, 1039 "Intel i82801H (AMT) LAN Controller", 1040 WM_T_ICH8, WMP_F_COPPER }, 1041 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN, 1042 "Intel i82801H LAN Controller", 1043 WM_T_ICH8, WMP_F_COPPER }, 1044 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN, 1045 "Intel i82801H (IFE) LAN Controller", 1046 WM_T_ICH8, WMP_F_COPPER }, 1047 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN, 1048 "Intel i82801H (M) LAN Controller", 1049 WM_T_ICH8, WMP_F_COPPER }, 1050 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT, 1051 "Intel i82801H IFE (GT) LAN Controller", 1052 WM_T_ICH8, WMP_F_COPPER }, 1053 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G, 1054 "Intel i82801H IFE (G) LAN Controller", 1055 WM_T_ICH8, WMP_F_COPPER }, 1056 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT, 1057 "82801I (AMT) LAN Controller", 1058 WM_T_ICH9, WMP_F_COPPER }, 1059 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE, 1060 "82801I LAN Controller", 1061 WM_T_ICH9, WMP_F_COPPER }, 1062 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G, 1063 "82801I (G) LAN Controller", 1064 WM_T_ICH9, WMP_F_COPPER }, 1065 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT, 1066 "82801I (GT) LAN Controller", 1067 WM_T_ICH9, WMP_F_COPPER }, 1068 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C, 1069 "82801I (C) LAN Controller", 1070 WM_T_ICH9, WMP_F_COPPER }, 1071 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M, 1072 "82801I mobile LAN Controller", 1073 WM_T_ICH9, WMP_F_COPPER }, 1074 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IGP_M_V, 1075 "82801I mobile (V) LAN Controller", 1076 WM_T_ICH9, WMP_F_COPPER }, 1077 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M_AMT, 1078 "82801I mobile (AMT) LAN Controller", 1079 WM_T_ICH9, WMP_F_COPPER }, 1080 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_BM, 1081 "82567LM-4 LAN Controller", 1082 WM_T_ICH9, WMP_F_COPPER }, 1083 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_82567V_3, 1084 "82567V-3 LAN Controller", 1085 WM_T_ICH9, WMP_F_COPPER }, 1086 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LM, 1087 "82567LM-2 LAN Controller", 1088 WM_T_ICH10, WMP_F_COPPER }, 1089 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LF, 1090 "82567LF-2 LAN Controller", 1091 WM_T_ICH10, WMP_F_COPPER }, 1092 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LM, 1093 "82567LM-3 LAN Controller", 1094 WM_T_ICH10, WMP_F_COPPER }, 1095 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LF, 1096 "82567LF-3 LAN Controller", 1097 WM_T_ICH10, WMP_F_COPPER }, 1098 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_V, 1099 "82567V-2 LAN Controller", 1100 WM_T_ICH10, WMP_F_COPPER }, 1101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_V, 1102 "82567V-3? LAN Controller", 1103 WM_T_ICH10, WMP_F_COPPER }, 1104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HANKSVILLE, 1105 "HANKSVILLE LAN Controller", 1106 WM_T_ICH10, WMP_F_COPPER }, 1107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LM, 1108 "PCH LAN (82577LM) Controller", 1109 WM_T_PCH, WMP_F_COPPER }, 1110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LC, 1111 "PCH LAN (82577LC) Controller", 1112 WM_T_PCH, WMP_F_COPPER }, 1113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DM, 1114 "PCH LAN (82578DM) Controller", 1115 WM_T_PCH, WMP_F_COPPER }, 1116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC, 1117 "PCH LAN (82578DC) Controller", 1118 WM_T_PCH, WMP_F_COPPER }, 1119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM, 1120 "PCH2 LAN (82579LM) Controller", 1121 WM_T_PCH2, WMP_F_COPPER }, 1122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V, 1123 "PCH2 LAN (82579V) Controller", 1124 WM_T_PCH2, WMP_F_COPPER }, 1125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER, 1126 "82575EB dual-1000baseT Ethernet", 1127 WM_T_82575, WMP_F_COPPER }, 1128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES, 1129 "82575EB dual-1000baseX Ethernet (SERDES)", 1130 WM_T_82575, WMP_F_SERDES }, 1131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER, 1132 "82575GB quad-1000baseT Ethernet", 1133 WM_T_82575, WMP_F_COPPER }, 1134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM, 1135 "82575GB quad-1000baseT Ethernet (PM)", 1136 WM_T_82575, WMP_F_COPPER }, 1137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_COPPER, 1138 "82576 1000BaseT Ethernet", 1139 WM_T_82576, WMP_F_COPPER }, 1140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER, 1141 "82576 1000BaseX Ethernet", 1142 WM_T_82576, WMP_F_FIBER }, 1143 1144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES, 1145 "82576 gigabit Ethernet (SERDES)", 1146 WM_T_82576, WMP_F_SERDES }, 1147 1148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER, 1149 "82576 quad-1000BaseT Ethernet", 1150 WM_T_82576, WMP_F_COPPER }, 1151 1152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2, 1153 "82576 Gigabit ET2 Quad Port Server Adapter", 1154 WM_T_82576, WMP_F_COPPER }, 1155 1156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS, 1157 "82576 gigabit Ethernet", 1158 WM_T_82576, WMP_F_COPPER }, 1159 1160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES, 1161 "82576 gigabit Ethernet (SERDES)", 1162 WM_T_82576, WMP_F_SERDES }, 1163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD, 1164 "82576 quad-gigabit Ethernet (SERDES)", 1165 WM_T_82576, WMP_F_SERDES }, 1166 1167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER, 1168 "82580 1000BaseT Ethernet", 1169 WM_T_82580, WMP_F_COPPER }, 1170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER, 1171 "82580 1000BaseX Ethernet", 1172 WM_T_82580, WMP_F_FIBER }, 1173 1174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES, 1175 "82580 1000BaseT Ethernet (SERDES)", 1176 WM_T_82580, WMP_F_SERDES }, 1177 1178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII, 1179 "82580 gigabit Ethernet (SGMII)", 1180 WM_T_82580, WMP_F_COPPER }, 1181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL, 1182 "82580 dual-1000BaseT Ethernet", 1183 WM_T_82580, WMP_F_COPPER }, 1184 1185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER, 1186 "82580 quad-1000BaseX Ethernet", 1187 WM_T_82580, WMP_F_FIBER }, 1188 1189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII, 1190 "DH89XXCC Gigabit Ethernet (SGMII)", 1191 WM_T_82580, WMP_F_COPPER }, 1192 1193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES, 1194 "DH89XXCC Gigabit Ethernet (SERDES)", 1195 WM_T_82580, WMP_F_SERDES }, 1196 1197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE, 1198 "DH89XXCC 1000BASE-KX Ethernet", 1199 WM_T_82580, WMP_F_SERDES }, 1200 1201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP, 1202 "DH89XXCC Gigabit Ethernet (SFP)", 1203 WM_T_82580, WMP_F_SERDES }, 1204 1205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER, 1206 "I350 Gigabit Network Connection", 1207 WM_T_I350, WMP_F_COPPER }, 1208 1209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER, 1210 "I350 Gigabit Fiber Network Connection", 1211 WM_T_I350, WMP_F_FIBER }, 1212 1213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES, 1214 "I350 Gigabit Backplane Connection", 1215 WM_T_I350, WMP_F_SERDES }, 1216 1217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_DA4, 1218 "I350 Quad Port Gigabit Ethernet", 1219 WM_T_I350, WMP_F_SERDES }, 1220 1221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII, 1222 "I350 Gigabit Connection", 1223 WM_T_I350, WMP_F_COPPER }, 1224 1225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_1000KX, 1226 "I354 Gigabit Ethernet (KX)", 1227 WM_T_I354, WMP_F_SERDES }, 1228 1229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_SGMII, 1230 "I354 Gigabit Ethernet (SGMII)", 1231 WM_T_I354, WMP_F_COPPER }, 1232 1233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_25GBE, 1234 "I354 Gigabit Ethernet (2.5G)", 1235 WM_T_I354, WMP_F_COPPER }, 1236 1237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_T1, 1238 "I210-T1 Ethernet Server Adapter", 1239 WM_T_I210, WMP_F_COPPER }, 1240 1241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1, 1242 "I210 Ethernet (Copper OEM)", 1243 WM_T_I210, WMP_F_COPPER }, 1244 1245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT, 1246 "I210 Ethernet (Copper IT)", 1247 WM_T_I210, WMP_F_COPPER }, 1248 1249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_WOF, 1250 "I210 Ethernet (FLASH less)", 1251 WM_T_I210, WMP_F_COPPER }, 1252 1253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER, 1254 "I210 Gigabit Ethernet (Fiber)", 1255 WM_T_I210, WMP_F_FIBER }, 1256 1257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES, 1258 "I210 Gigabit Ethernet (SERDES)", 1259 WM_T_I210, WMP_F_SERDES }, 1260 1261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_WOF, 1262 "I210 Gigabit Ethernet (FLASH less)", 1263 WM_T_I210, WMP_F_SERDES }, 1264 1265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII, 1266 "I210 Gigabit Ethernet (SGMII)", 1267 WM_T_I210, WMP_F_COPPER }, 1268 1269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER, 1270 "I211 Ethernet (COPPER)", 1271 WM_T_I211, WMP_F_COPPER }, 1272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V, 1273 "I217 V Ethernet Connection", 1274 WM_T_PCH_LPT, WMP_F_COPPER }, 1275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM, 1276 "I217 LM Ethernet Connection", 1277 WM_T_PCH_LPT, WMP_F_COPPER }, 1278 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V, 1279 "I218 V Ethernet Connection", 1280 WM_T_PCH_LPT, WMP_F_COPPER }, 1281 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V2, 1282 "I218 V Ethernet Connection", 1283 WM_T_PCH_LPT, WMP_F_COPPER }, 1284 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V3, 1285 "I218 V Ethernet Connection", 1286 WM_T_PCH_LPT, WMP_F_COPPER }, 1287 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM, 1288 "I218 LM Ethernet Connection", 1289 WM_T_PCH_LPT, WMP_F_COPPER }, 1290 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM2, 1291 "I218 LM Ethernet Connection", 1292 WM_T_PCH_LPT, WMP_F_COPPER }, 1293 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3, 1294 "I218 LM Ethernet Connection", 1295 WM_T_PCH_LPT, WMP_F_COPPER }, 1296 #if 0 1297 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V, 1298 "I219 V Ethernet Connection", 1299 WM_T_PCH_SPT, WMP_F_COPPER }, 1300 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2, 1301 "I219 V Ethernet Connection", 1302 WM_T_PCH_SPT, WMP_F_COPPER }, 1303 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM, 1304 "I219 LM Ethernet Connection", 1305 WM_T_PCH_SPT, WMP_F_COPPER }, 1306 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2, 1307 "I219 LM Ethernet Connection", 1308 WM_T_PCH_SPT, WMP_F_COPPER }, 1309 #endif 1310 { 0, 0, 1311 NULL, 1312 0, 0 }, 1313 }; 1314 1315 #ifdef WM_EVENT_COUNTERS 1316 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 1317 #endif /* WM_EVENT_COUNTERS */ 1318 1319 1320 /* 1321 * Register read/write functions. 1322 * Other than CSR_{READ|WRITE}(). 1323 */ 1324 1325 #if 0 /* Not currently used */ 1326 static inline uint32_t 1327 wm_io_read(struct wm_softc *sc, int reg) 1328 { 1329 1330 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 1331 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 1332 } 1333 #endif 1334 1335 static inline void 1336 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 1337 { 1338 1339 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 1340 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 1341 } 1342 1343 static inline void 1344 wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off, 1345 uint32_t data) 1346 { 1347 uint32_t regval; 1348 int i; 1349 1350 regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT); 1351 1352 CSR_WRITE(sc, reg, regval); 1353 1354 for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) { 1355 delay(5); 1356 if (CSR_READ(sc, reg) & SCTL_CTL_READY) 1357 break; 1358 } 1359 if (i == SCTL_CTL_POLL_TIMEOUT) { 1360 aprint_error("%s: WARNING:" 1361 " i82575 reg 0x%08x setup did not indicate ready\n", 1362 device_xname(sc->sc_dev), reg); 1363 } 1364 } 1365 1366 static inline void 1367 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 1368 { 1369 wa->wa_low = htole32(v & 0xffffffffU); 1370 if (sizeof(bus_addr_t) == 8) 1371 wa->wa_high = htole32((uint64_t) v >> 32); 1372 else 1373 wa->wa_high = 0; 1374 } 1375 1376 /* 1377 * Descriptor sync/init functions. 1378 */ 1379 static inline void 1380 wm_cdtxsync(struct wm_txqueue *txq, int start, int num, int ops) 1381 { 1382 struct wm_softc *sc = txq->txq_sc; 1383 1384 /* If it will wrap around, sync to the end of the ring. */ 1385 if ((start + num) > WM_NTXDESC(txq)) { 1386 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, 1387 WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * 1388 (WM_NTXDESC(txq) - start), ops); 1389 num -= (WM_NTXDESC(txq) - start); 1390 start = 0; 1391 } 1392 1393 /* Now sync whatever is left. */ 1394 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, 1395 WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * num, ops); 1396 } 1397 1398 static inline void 1399 wm_cdrxsync(struct wm_rxqueue *rxq, int start, int ops) 1400 { 1401 struct wm_softc *sc = rxq->rxq_sc; 1402 1403 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap, 1404 WM_CDRXOFF(start), sizeof(wiseman_rxdesc_t), ops); 1405 } 1406 1407 static inline void 1408 wm_init_rxdesc(struct wm_rxqueue *rxq, int start) 1409 { 1410 struct wm_softc *sc = rxq->rxq_sc; 1411 struct wm_rxsoft *rxs = &rxq->rxq_soft[start]; 1412 wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start]; 1413 struct mbuf *m = rxs->rxs_mbuf; 1414 1415 /* 1416 * Note: We scoot the packet forward 2 bytes in the buffer 1417 * so that the payload after the Ethernet header is aligned 1418 * to a 4-byte boundary. 1419 1420 * XXX BRAINDAMAGE ALERT! 1421 * The stupid chip uses the same size for every buffer, which 1422 * is set in the Receive Control register. We are using the 2K 1423 * size option, but what we REALLY want is (2K - 2)! For this 1424 * reason, we can't "scoot" packets longer than the standard 1425 * Ethernet MTU. On strict-alignment platforms, if the total 1426 * size exceeds (2K - 2) we set align_tweak to 0 and let 1427 * the upper layer copy the headers. 1428 */ 1429 m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak; 1430 1431 wm_set_dma_addr(&rxd->wrx_addr, 1432 rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak); 1433 rxd->wrx_len = 0; 1434 rxd->wrx_cksum = 0; 1435 rxd->wrx_status = 0; 1436 rxd->wrx_errors = 0; 1437 rxd->wrx_special = 0; 1438 wm_cdrxsync(rxq, start, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1439 1440 CSR_WRITE(sc, rxq->rxq_rdt_reg, start); 1441 } 1442 1443 /* 1444 * Device driver interface functions and commonly used functions. 1445 * match, attach, detach, init, start, stop, ioctl, watchdog and so on. 1446 */ 1447 1448 /* Lookup supported device table */ 1449 static const struct wm_product * 1450 wm_lookup(const struct pci_attach_args *pa) 1451 { 1452 const struct wm_product *wmp; 1453 1454 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 1455 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 1456 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 1457 return wmp; 1458 } 1459 return NULL; 1460 } 1461 1462 /* The match function (ca_match) */ 1463 static int 1464 wm_match(device_t parent, cfdata_t cf, void *aux) 1465 { 1466 struct pci_attach_args *pa = aux; 1467 1468 if (wm_lookup(pa) != NULL) 1469 return 1; 1470 1471 return 0; 1472 } 1473 1474 /* The attach function (ca_attach) */ 1475 static void 1476 wm_attach(device_t parent, device_t self, void *aux) 1477 { 1478 struct wm_softc *sc = device_private(self); 1479 struct pci_attach_args *pa = aux; 1480 prop_dictionary_t dict; 1481 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1482 pci_chipset_tag_t pc = pa->pa_pc; 1483 int counts[PCI_INTR_TYPE_SIZE]; 1484 pci_intr_type_t max_type; 1485 const char *eetype, *xname; 1486 bus_space_tag_t memt; 1487 bus_space_handle_t memh; 1488 bus_size_t memsize; 1489 int memh_valid; 1490 int i, error; 1491 const struct wm_product *wmp; 1492 prop_data_t ea; 1493 prop_number_t pn; 1494 uint8_t enaddr[ETHER_ADDR_LEN]; 1495 uint16_t cfg1, cfg2, swdpin, nvmword; 1496 pcireg_t preg, memtype; 1497 uint16_t eeprom_data, apme_mask; 1498 bool force_clear_smbi; 1499 uint32_t link_mode; 1500 uint32_t reg; 1501 1502 sc->sc_dev = self; 1503 callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS); 1504 sc->sc_stopping = false; 1505 1506 wmp = wm_lookup(pa); 1507 #ifdef DIAGNOSTIC 1508 if (wmp == NULL) { 1509 printf("\n"); 1510 panic("wm_attach: impossible"); 1511 } 1512 #endif 1513 sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags); 1514 1515 sc->sc_pc = pa->pa_pc; 1516 sc->sc_pcitag = pa->pa_tag; 1517 1518 if (pci_dma64_available(pa)) 1519 sc->sc_dmat = pa->pa_dmat64; 1520 else 1521 sc->sc_dmat = pa->pa_dmat; 1522 1523 sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id); 1524 sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag,PCI_CLASS_REG)); 1525 pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1); 1526 1527 sc->sc_type = wmp->wmp_type; 1528 if (sc->sc_type < WM_T_82543) { 1529 if (sc->sc_rev < 2) { 1530 aprint_error_dev(sc->sc_dev, 1531 "i82542 must be at least rev. 2\n"); 1532 return; 1533 } 1534 if (sc->sc_rev < 3) 1535 sc->sc_type = WM_T_82542_2_0; 1536 } 1537 1538 /* 1539 * Disable MSI for Errata: 1540 * "Message Signaled Interrupt Feature May Corrupt Write Transactions" 1541 * 1542 * 82544: Errata 25 1543 * 82540: Errata 6 (easy to reproduce device timeout) 1544 * 82545: Errata 4 (easy to reproduce device timeout) 1545 * 82546: Errata 26 (easy to reproduce device timeout) 1546 * 82541: Errata 7 (easy to reproduce device timeout) 1547 * 1548 * "Byte Enables 2 and 3 are not set on MSI writes" 1549 * 1550 * 82571 & 82572: Errata 63 1551 */ 1552 if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571) 1553 || (sc->sc_type == WM_T_82572)) 1554 pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY; 1555 1556 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) 1557 || (sc->sc_type == WM_T_82580) 1558 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) 1559 || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) 1560 sc->sc_flags |= WM_F_NEWQUEUE; 1561 1562 /* Set device properties (mactype) */ 1563 dict = device_properties(sc->sc_dev); 1564 prop_dictionary_set_uint32(dict, "mactype", sc->sc_type); 1565 1566 /* 1567 * Map the device. All devices support memory-mapped acccess, 1568 * and it is really required for normal operation. 1569 */ 1570 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 1571 switch (memtype) { 1572 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1573 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1574 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 1575 memtype, 0, &memt, &memh, NULL, &memsize) == 0); 1576 break; 1577 default: 1578 memh_valid = 0; 1579 break; 1580 } 1581 1582 if (memh_valid) { 1583 sc->sc_st = memt; 1584 sc->sc_sh = memh; 1585 sc->sc_ss = memsize; 1586 } else { 1587 aprint_error_dev(sc->sc_dev, 1588 "unable to map device registers\n"); 1589 return; 1590 } 1591 1592 /* 1593 * In addition, i82544 and later support I/O mapped indirect 1594 * register access. It is not desirable (nor supported in 1595 * this driver) to use it for normal operation, though it is 1596 * required to work around bugs in some chip versions. 1597 */ 1598 if (sc->sc_type >= WM_T_82544) { 1599 /* First we have to find the I/O BAR. */ 1600 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 1601 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); 1602 if (memtype == PCI_MAPREG_TYPE_IO) 1603 break; 1604 if (PCI_MAPREG_MEM_TYPE(memtype) == 1605 PCI_MAPREG_MEM_TYPE_64BIT) 1606 i += 4; /* skip high bits, too */ 1607 } 1608 if (i < PCI_MAPREG_END) { 1609 /* 1610 * We found PCI_MAPREG_TYPE_IO. Note that 82580 1611 * (and newer?) chip has no PCI_MAPREG_TYPE_IO. 1612 * It's no problem because newer chips has no this 1613 * bug. 1614 * 1615 * The i8254x doesn't apparently respond when the 1616 * I/O BAR is 0, which looks somewhat like it's not 1617 * been configured. 1618 */ 1619 preg = pci_conf_read(pc, pa->pa_tag, i); 1620 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 1621 aprint_error_dev(sc->sc_dev, 1622 "WARNING: I/O BAR at zero.\n"); 1623 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 1624 0, &sc->sc_iot, &sc->sc_ioh, 1625 NULL, &sc->sc_ios) == 0) { 1626 sc->sc_flags |= WM_F_IOH_VALID; 1627 } else { 1628 aprint_error_dev(sc->sc_dev, 1629 "WARNING: unable to map I/O space\n"); 1630 } 1631 } 1632 1633 } 1634 1635 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 1636 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1637 preg |= PCI_COMMAND_MASTER_ENABLE; 1638 if (sc->sc_type < WM_T_82542_2_1) 1639 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 1640 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 1641 1642 /* power up chip */ 1643 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1644 NULL)) && error != EOPNOTSUPP) { 1645 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1646 return; 1647 } 1648 1649 wm_adjust_qnum(sc, pci_msix_count(pa->pa_pc, pa->pa_tag)); 1650 1651 /* Allocation settings */ 1652 max_type = PCI_INTR_TYPE_MSIX; 1653 counts[PCI_INTR_TYPE_MSIX] = sc->sc_ntxqueues + sc->sc_nrxqueues + 1; 1654 counts[PCI_INTR_TYPE_MSI] = 1; 1655 counts[PCI_INTR_TYPE_INTX] = 1; 1656 1657 alloc_retry: 1658 if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) { 1659 aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n"); 1660 return; 1661 } 1662 1663 if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) { 1664 error = wm_setup_msix(sc); 1665 if (error) { 1666 pci_intr_release(pc, sc->sc_intrs, 1667 counts[PCI_INTR_TYPE_MSIX]); 1668 1669 /* Setup for MSI: Disable MSI-X */ 1670 max_type = PCI_INTR_TYPE_MSI; 1671 counts[PCI_INTR_TYPE_MSI] = 1; 1672 counts[PCI_INTR_TYPE_INTX] = 1; 1673 goto alloc_retry; 1674 } 1675 } else if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) { 1676 wm_adjust_qnum(sc, 0); /* must not use multiqueue */ 1677 error = wm_setup_legacy(sc); 1678 if (error) { 1679 pci_intr_release(sc->sc_pc, sc->sc_intrs, 1680 counts[PCI_INTR_TYPE_MSI]); 1681 1682 /* The next try is for INTx: Disable MSI */ 1683 max_type = PCI_INTR_TYPE_INTX; 1684 counts[PCI_INTR_TYPE_INTX] = 1; 1685 goto alloc_retry; 1686 } 1687 } else { 1688 wm_adjust_qnum(sc, 0); /* must not use multiqueue */ 1689 error = wm_setup_legacy(sc); 1690 if (error) { 1691 pci_intr_release(sc->sc_pc, sc->sc_intrs, 1692 counts[PCI_INTR_TYPE_INTX]); 1693 return; 1694 } 1695 } 1696 1697 /* 1698 * Check the function ID (unit number of the chip). 1699 */ 1700 if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3) 1701 || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003) 1702 || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) 1703 || (sc->sc_type == WM_T_82580) 1704 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) 1705 sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS) 1706 >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK; 1707 else 1708 sc->sc_funcid = 0; 1709 1710 /* 1711 * Determine a few things about the bus we're connected to. 1712 */ 1713 if (sc->sc_type < WM_T_82543) { 1714 /* We don't really know the bus characteristics here. */ 1715 sc->sc_bus_speed = 33; 1716 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 1717 /* 1718 * CSA (Communication Streaming Architecture) is about as fast 1719 * a 32-bit 66MHz PCI Bus. 1720 */ 1721 sc->sc_flags |= WM_F_CSA; 1722 sc->sc_bus_speed = 66; 1723 aprint_verbose_dev(sc->sc_dev, 1724 "Communication Streaming Architecture\n"); 1725 if (sc->sc_type == WM_T_82547) { 1726 callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS); 1727 callout_setfunc(&sc->sc_txfifo_ch, 1728 wm_82547_txfifo_stall, sc); 1729 aprint_verbose_dev(sc->sc_dev, 1730 "using 82547 Tx FIFO stall work-around\n"); 1731 } 1732 } else if (sc->sc_type >= WM_T_82571) { 1733 sc->sc_flags |= WM_F_PCIE; 1734 if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) 1735 && (sc->sc_type != WM_T_ICH10) 1736 && (sc->sc_type != WM_T_PCH) 1737 && (sc->sc_type != WM_T_PCH2) 1738 && (sc->sc_type != WM_T_PCH_LPT) 1739 && (sc->sc_type != WM_T_PCH_SPT)) { 1740 /* ICH* and PCH* have no PCIe capability registers */ 1741 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1742 PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff, 1743 NULL) == 0) 1744 aprint_error_dev(sc->sc_dev, 1745 "unable to find PCIe capability\n"); 1746 } 1747 aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n"); 1748 } else { 1749 reg = CSR_READ(sc, WMREG_STATUS); 1750 if (reg & STATUS_BUS64) 1751 sc->sc_flags |= WM_F_BUS64; 1752 if ((reg & STATUS_PCIX_MODE) != 0) { 1753 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 1754 1755 sc->sc_flags |= WM_F_PCIX; 1756 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1757 PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0) 1758 aprint_error_dev(sc->sc_dev, 1759 "unable to find PCIX capability\n"); 1760 else if (sc->sc_type != WM_T_82545_3 && 1761 sc->sc_type != WM_T_82546_3) { 1762 /* 1763 * Work around a problem caused by the BIOS 1764 * setting the max memory read byte count 1765 * incorrectly. 1766 */ 1767 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 1768 sc->sc_pcixe_capoff + PCIX_CMD); 1769 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 1770 sc->sc_pcixe_capoff + PCIX_STATUS); 1771 1772 bytecnt = (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >> 1773 PCIX_CMD_BYTECNT_SHIFT; 1774 maxb = (pcix_sts & PCIX_STATUS_MAXB_MASK) >> 1775 PCIX_STATUS_MAXB_SHIFT; 1776 if (bytecnt > maxb) { 1777 aprint_verbose_dev(sc->sc_dev, 1778 "resetting PCI-X MMRBC: %d -> %d\n", 1779 512 << bytecnt, 512 << maxb); 1780 pcix_cmd = (pcix_cmd & 1781 ~PCIX_CMD_BYTECNT_MASK) | 1782 (maxb << PCIX_CMD_BYTECNT_SHIFT); 1783 pci_conf_write(pa->pa_pc, pa->pa_tag, 1784 sc->sc_pcixe_capoff + PCIX_CMD, 1785 pcix_cmd); 1786 } 1787 } 1788 } 1789 /* 1790 * The quad port adapter is special; it has a PCIX-PCIX 1791 * bridge on the board, and can run the secondary bus at 1792 * a higher speed. 1793 */ 1794 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 1795 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 1796 : 66; 1797 } else if (sc->sc_flags & WM_F_PCIX) { 1798 switch (reg & STATUS_PCIXSPD_MASK) { 1799 case STATUS_PCIXSPD_50_66: 1800 sc->sc_bus_speed = 66; 1801 break; 1802 case STATUS_PCIXSPD_66_100: 1803 sc->sc_bus_speed = 100; 1804 break; 1805 case STATUS_PCIXSPD_100_133: 1806 sc->sc_bus_speed = 133; 1807 break; 1808 default: 1809 aprint_error_dev(sc->sc_dev, 1810 "unknown PCIXSPD %d; assuming 66MHz\n", 1811 reg & STATUS_PCIXSPD_MASK); 1812 sc->sc_bus_speed = 66; 1813 break; 1814 } 1815 } else 1816 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 1817 aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", 1818 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 1819 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 1820 } 1821 1822 /* clear interesting stat counters */ 1823 CSR_READ(sc, WMREG_COLC); 1824 CSR_READ(sc, WMREG_RXERRC); 1825 1826 /* get PHY control from SMBus to PCIe */ 1827 if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2) 1828 || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) 1829 wm_smbustopci(sc); 1830 1831 /* Reset the chip to a known state. */ 1832 wm_reset(sc); 1833 1834 /* Get some information about the EEPROM. */ 1835 switch (sc->sc_type) { 1836 case WM_T_82542_2_0: 1837 case WM_T_82542_2_1: 1838 case WM_T_82543: 1839 case WM_T_82544: 1840 /* Microwire */ 1841 sc->sc_nvm_wordsize = 64; 1842 sc->sc_nvm_addrbits = 6; 1843 break; 1844 case WM_T_82540: 1845 case WM_T_82545: 1846 case WM_T_82545_3: 1847 case WM_T_82546: 1848 case WM_T_82546_3: 1849 /* Microwire */ 1850 reg = CSR_READ(sc, WMREG_EECD); 1851 if (reg & EECD_EE_SIZE) { 1852 sc->sc_nvm_wordsize = 256; 1853 sc->sc_nvm_addrbits = 8; 1854 } else { 1855 sc->sc_nvm_wordsize = 64; 1856 sc->sc_nvm_addrbits = 6; 1857 } 1858 sc->sc_flags |= WM_F_LOCK_EECD; 1859 break; 1860 case WM_T_82541: 1861 case WM_T_82541_2: 1862 case WM_T_82547: 1863 case WM_T_82547_2: 1864 sc->sc_flags |= WM_F_LOCK_EECD; 1865 reg = CSR_READ(sc, WMREG_EECD); 1866 if (reg & EECD_EE_TYPE) { 1867 /* SPI */ 1868 sc->sc_flags |= WM_F_EEPROM_SPI; 1869 wm_nvm_set_addrbits_size_eecd(sc); 1870 } else { 1871 /* Microwire */ 1872 if ((reg & EECD_EE_ABITS) != 0) { 1873 sc->sc_nvm_wordsize = 256; 1874 sc->sc_nvm_addrbits = 8; 1875 } else { 1876 sc->sc_nvm_wordsize = 64; 1877 sc->sc_nvm_addrbits = 6; 1878 } 1879 } 1880 break; 1881 case WM_T_82571: 1882 case WM_T_82572: 1883 /* SPI */ 1884 sc->sc_flags |= WM_F_EEPROM_SPI; 1885 wm_nvm_set_addrbits_size_eecd(sc); 1886 sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM; 1887 break; 1888 case WM_T_82573: 1889 sc->sc_flags |= WM_F_LOCK_SWSM; 1890 /* FALLTHROUGH */ 1891 case WM_T_82574: 1892 case WM_T_82583: 1893 if (wm_nvm_is_onboard_eeprom(sc) == 0) { 1894 sc->sc_flags |= WM_F_EEPROM_FLASH; 1895 sc->sc_nvm_wordsize = 2048; 1896 } else { 1897 /* SPI */ 1898 sc->sc_flags |= WM_F_EEPROM_SPI; 1899 wm_nvm_set_addrbits_size_eecd(sc); 1900 } 1901 sc->sc_flags |= WM_F_EEPROM_EERDEEWR; 1902 break; 1903 case WM_T_82575: 1904 case WM_T_82576: 1905 case WM_T_82580: 1906 case WM_T_I350: 1907 case WM_T_I354: 1908 case WM_T_80003: 1909 /* SPI */ 1910 sc->sc_flags |= WM_F_EEPROM_SPI; 1911 wm_nvm_set_addrbits_size_eecd(sc); 1912 sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW 1913 | WM_F_LOCK_SWSM; 1914 break; 1915 case WM_T_ICH8: 1916 case WM_T_ICH9: 1917 case WM_T_ICH10: 1918 case WM_T_PCH: 1919 case WM_T_PCH2: 1920 case WM_T_PCH_LPT: 1921 /* FLASH */ 1922 sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF; 1923 sc->sc_nvm_wordsize = 2048; 1924 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,WM_ICH8_FLASH); 1925 if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0, 1926 &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) { 1927 aprint_error_dev(sc->sc_dev, 1928 "can't map FLASH registers\n"); 1929 goto out; 1930 } 1931 reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG); 1932 sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) * 1933 ICH_FLASH_SECTOR_SIZE; 1934 sc->sc_ich8_flash_bank_size = 1935 ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 1936 sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK); 1937 sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 1938 sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t); 1939 sc->sc_flashreg_offset = 0; 1940 break; 1941 case WM_T_PCH_SPT: 1942 /* SPT has no GFPREG; flash registers mapped through BAR0 */ 1943 sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF; 1944 sc->sc_flasht = sc->sc_st; 1945 sc->sc_flashh = sc->sc_sh; 1946 sc->sc_ich8_flash_base = 0; 1947 sc->sc_nvm_wordsize = 1948 (((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1) 1949 * NVM_SIZE_MULTIPLIER; 1950 /* It is size in bytes, we want words */ 1951 sc->sc_nvm_wordsize /= 2; 1952 /* assume 2 banks */ 1953 sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2; 1954 sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET; 1955 break; 1956 case WM_T_I210: 1957 case WM_T_I211: 1958 if (wm_nvm_get_flash_presence_i210(sc)) { 1959 wm_nvm_set_addrbits_size_eecd(sc); 1960 sc->sc_flags |= WM_F_EEPROM_FLASH_HW; 1961 sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW; 1962 } else { 1963 sc->sc_nvm_wordsize = INVM_SIZE; 1964 sc->sc_flags |= WM_F_EEPROM_INVM; 1965 sc->sc_flags |= WM_F_LOCK_SWFW; 1966 } 1967 break; 1968 default: 1969 break; 1970 } 1971 1972 /* Ensure the SMBI bit is clear before first NVM or PHY access */ 1973 switch (sc->sc_type) { 1974 case WM_T_82571: 1975 case WM_T_82572: 1976 reg = CSR_READ(sc, WMREG_SWSM2); 1977 if ((reg & SWSM2_LOCK) == 0) { 1978 CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK); 1979 force_clear_smbi = true; 1980 } else 1981 force_clear_smbi = false; 1982 break; 1983 case WM_T_82573: 1984 case WM_T_82574: 1985 case WM_T_82583: 1986 force_clear_smbi = true; 1987 break; 1988 default: 1989 force_clear_smbi = false; 1990 break; 1991 } 1992 if (force_clear_smbi) { 1993 reg = CSR_READ(sc, WMREG_SWSM); 1994 if ((reg & SWSM_SMBI) != 0) 1995 aprint_error_dev(sc->sc_dev, 1996 "Please update the Bootagent\n"); 1997 CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI); 1998 } 1999 2000 /* 2001 * Defer printing the EEPROM type until after verifying the checksum 2002 * This allows the EEPROM type to be printed correctly in the case 2003 * that no EEPROM is attached. 2004 */ 2005 /* 2006 * Validate the EEPROM checksum. If the checksum fails, flag 2007 * this for later, so we can fail future reads from the EEPROM. 2008 */ 2009 if (wm_nvm_validate_checksum(sc)) { 2010 /* 2011 * Read twice again because some PCI-e parts fail the 2012 * first check due to the link being in sleep state. 2013 */ 2014 if (wm_nvm_validate_checksum(sc)) 2015 sc->sc_flags |= WM_F_EEPROM_INVALID; 2016 } 2017 2018 /* Set device properties (macflags) */ 2019 prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags); 2020 2021 if (sc->sc_flags & WM_F_EEPROM_INVALID) 2022 aprint_verbose_dev(sc->sc_dev, "No EEPROM"); 2023 else { 2024 aprint_verbose_dev(sc->sc_dev, "%u words ", 2025 sc->sc_nvm_wordsize); 2026 if (sc->sc_flags & WM_F_EEPROM_INVM) 2027 aprint_verbose("iNVM"); 2028 else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW) 2029 aprint_verbose("FLASH(HW)"); 2030 else if (sc->sc_flags & WM_F_EEPROM_FLASH) 2031 aprint_verbose("FLASH"); 2032 else { 2033 if (sc->sc_flags & WM_F_EEPROM_SPI) 2034 eetype = "SPI"; 2035 else 2036 eetype = "MicroWire"; 2037 aprint_verbose("(%d address bits) %s EEPROM", 2038 sc->sc_nvm_addrbits, eetype); 2039 } 2040 } 2041 wm_nvm_version(sc); 2042 aprint_verbose("\n"); 2043 2044 /* Check for I21[01] PLL workaround */ 2045 if (sc->sc_type == WM_T_I210) 2046 sc->sc_flags |= WM_F_PLL_WA_I210; 2047 if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) { 2048 /* NVM image release 3.25 has a workaround */ 2049 if ((sc->sc_nvm_ver_major < 3) 2050 || ((sc->sc_nvm_ver_major == 3) 2051 && (sc->sc_nvm_ver_minor < 25))) { 2052 aprint_verbose_dev(sc->sc_dev, 2053 "ROM image version %d.%d is older than 3.25\n", 2054 sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor); 2055 sc->sc_flags |= WM_F_PLL_WA_I210; 2056 } 2057 } 2058 if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) 2059 wm_pll_workaround_i210(sc); 2060 2061 wm_get_wakeup(sc); 2062 switch (sc->sc_type) { 2063 case WM_T_82571: 2064 case WM_T_82572: 2065 case WM_T_82573: 2066 case WM_T_82574: 2067 case WM_T_82583: 2068 case WM_T_80003: 2069 case WM_T_ICH8: 2070 case WM_T_ICH9: 2071 case WM_T_ICH10: 2072 case WM_T_PCH: 2073 case WM_T_PCH2: 2074 case WM_T_PCH_LPT: 2075 case WM_T_PCH_SPT: 2076 /* Non-AMT based hardware can now take control from firmware */ 2077 if ((sc->sc_flags & WM_F_HAS_AMT) == 0) 2078 wm_get_hw_control(sc); 2079 break; 2080 default: 2081 break; 2082 } 2083 2084 /* 2085 * Read the Ethernet address from the EEPROM, if not first found 2086 * in device properties. 2087 */ 2088 ea = prop_dictionary_get(dict, "mac-address"); 2089 if (ea != NULL) { 2090 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 2091 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 2092 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 2093 } else { 2094 if (wm_read_mac_addr(sc, enaddr) != 0) { 2095 aprint_error_dev(sc->sc_dev, 2096 "unable to read Ethernet address\n"); 2097 goto out; 2098 } 2099 } 2100 2101 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 2102 ether_sprintf(enaddr)); 2103 2104 /* 2105 * Read the config info from the EEPROM, and set up various 2106 * bits in the control registers based on their contents. 2107 */ 2108 pn = prop_dictionary_get(dict, "i82543-cfg1"); 2109 if (pn != NULL) { 2110 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 2111 cfg1 = (uint16_t) prop_number_integer_value(pn); 2112 } else { 2113 if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) { 2114 aprint_error_dev(sc->sc_dev, "unable to read CFG1\n"); 2115 goto out; 2116 } 2117 } 2118 2119 pn = prop_dictionary_get(dict, "i82543-cfg2"); 2120 if (pn != NULL) { 2121 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 2122 cfg2 = (uint16_t) prop_number_integer_value(pn); 2123 } else { 2124 if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) { 2125 aprint_error_dev(sc->sc_dev, "unable to read CFG2\n"); 2126 goto out; 2127 } 2128 } 2129 2130 /* check for WM_F_WOL */ 2131 switch (sc->sc_type) { 2132 case WM_T_82542_2_0: 2133 case WM_T_82542_2_1: 2134 case WM_T_82543: 2135 /* dummy? */ 2136 eeprom_data = 0; 2137 apme_mask = NVM_CFG3_APME; 2138 break; 2139 case WM_T_82544: 2140 apme_mask = NVM_CFG2_82544_APM_EN; 2141 eeprom_data = cfg2; 2142 break; 2143 case WM_T_82546: 2144 case WM_T_82546_3: 2145 case WM_T_82571: 2146 case WM_T_82572: 2147 case WM_T_82573: 2148 case WM_T_82574: 2149 case WM_T_82583: 2150 case WM_T_80003: 2151 default: 2152 apme_mask = NVM_CFG3_APME; 2153 wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB 2154 : NVM_OFF_CFG3_PORTA, 1, &eeprom_data); 2155 break; 2156 case WM_T_82575: 2157 case WM_T_82576: 2158 case WM_T_82580: 2159 case WM_T_I350: 2160 case WM_T_I354: /* XXX ok? */ 2161 case WM_T_ICH8: 2162 case WM_T_ICH9: 2163 case WM_T_ICH10: 2164 case WM_T_PCH: 2165 case WM_T_PCH2: 2166 case WM_T_PCH_LPT: 2167 case WM_T_PCH_SPT: 2168 /* XXX The funcid should be checked on some devices */ 2169 apme_mask = WUC_APME; 2170 eeprom_data = CSR_READ(sc, WMREG_WUC); 2171 break; 2172 } 2173 2174 /* Check for WM_F_WOL flag after the setting of the EEPROM stuff */ 2175 if ((eeprom_data & apme_mask) != 0) 2176 sc->sc_flags |= WM_F_WOL; 2177 #ifdef WM_DEBUG 2178 if ((sc->sc_flags & WM_F_WOL) != 0) 2179 printf("WOL\n"); 2180 #endif 2181 2182 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) { 2183 /* Check NVM for autonegotiation */ 2184 if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) { 2185 if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0) 2186 sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO; 2187 } 2188 } 2189 2190 /* 2191 * XXX need special handling for some multiple port cards 2192 * to disable a paticular port. 2193 */ 2194 2195 if (sc->sc_type >= WM_T_82544) { 2196 pn = prop_dictionary_get(dict, "i82543-swdpin"); 2197 if (pn != NULL) { 2198 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 2199 swdpin = (uint16_t) prop_number_integer_value(pn); 2200 } else { 2201 if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) { 2202 aprint_error_dev(sc->sc_dev, 2203 "unable to read SWDPIN\n"); 2204 goto out; 2205 } 2206 } 2207 } 2208 2209 if (cfg1 & NVM_CFG1_ILOS) 2210 sc->sc_ctrl |= CTRL_ILOS; 2211 2212 /* 2213 * XXX 2214 * This code isn't correct because pin 2 and 3 are located 2215 * in different position on newer chips. Check all datasheet. 2216 * 2217 * Until resolve this problem, check if a chip < 82580 2218 */ 2219 if (sc->sc_type <= WM_T_82580) { 2220 if (sc->sc_type >= WM_T_82544) { 2221 sc->sc_ctrl |= 2222 ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 2223 CTRL_SWDPIO_SHIFT; 2224 sc->sc_ctrl |= 2225 ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 2226 CTRL_SWDPINS_SHIFT; 2227 } else { 2228 sc->sc_ctrl |= 2229 ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) << 2230 CTRL_SWDPIO_SHIFT; 2231 } 2232 } 2233 2234 /* XXX For other than 82580? */ 2235 if (sc->sc_type == WM_T_82580) { 2236 wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword); 2237 if (nvmword & __BIT(13)) 2238 sc->sc_ctrl |= CTRL_ILOS; 2239 } 2240 2241 #if 0 2242 if (sc->sc_type >= WM_T_82544) { 2243 if (cfg1 & NVM_CFG1_IPS0) 2244 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 2245 if (cfg1 & NVM_CFG1_IPS1) 2246 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 2247 sc->sc_ctrl_ext |= 2248 ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 2249 CTRL_EXT_SWDPIO_SHIFT; 2250 sc->sc_ctrl_ext |= 2251 ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 2252 CTRL_EXT_SWDPINS_SHIFT; 2253 } else { 2254 sc->sc_ctrl_ext |= 2255 ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) << 2256 CTRL_EXT_SWDPIO_SHIFT; 2257 } 2258 #endif 2259 2260 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2261 #if 0 2262 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2263 #endif 2264 2265 if (sc->sc_type == WM_T_PCH) { 2266 uint16_t val; 2267 2268 /* Save the NVM K1 bit setting */ 2269 wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val); 2270 2271 if ((val & NVM_K1_CONFIG_ENABLE) != 0) 2272 sc->sc_nvm_k1_enabled = 1; 2273 else 2274 sc->sc_nvm_k1_enabled = 0; 2275 } 2276 2277 /* 2278 * Determine if we're TBI,GMII or SGMII mode, and initialize the 2279 * media structures accordingly. 2280 */ 2281 if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9 2282 || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH 2283 || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT 2284 || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573 2285 || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) { 2286 /* STATUS_TBIMODE reserved/reused, can't rely on it */ 2287 wm_gmii_mediainit(sc, wmp->wmp_product); 2288 } else if (sc->sc_type < WM_T_82543 || 2289 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 2290 if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) { 2291 aprint_error_dev(sc->sc_dev, 2292 "WARNING: TBIMODE set on 1000BASE-T product!\n"); 2293 sc->sc_mediatype = WM_MEDIATYPE_FIBER; 2294 } 2295 wm_tbi_mediainit(sc); 2296 } else { 2297 switch (sc->sc_type) { 2298 case WM_T_82575: 2299 case WM_T_82576: 2300 case WM_T_82580: 2301 case WM_T_I350: 2302 case WM_T_I354: 2303 case WM_T_I210: 2304 case WM_T_I211: 2305 reg = CSR_READ(sc, WMREG_CTRL_EXT); 2306 link_mode = reg & CTRL_EXT_LINK_MODE_MASK; 2307 switch (link_mode) { 2308 case CTRL_EXT_LINK_MODE_1000KX: 2309 aprint_verbose_dev(sc->sc_dev, "1000KX\n"); 2310 sc->sc_mediatype = WM_MEDIATYPE_SERDES; 2311 break; 2312 case CTRL_EXT_LINK_MODE_SGMII: 2313 if (wm_sgmii_uses_mdio(sc)) { 2314 aprint_verbose_dev(sc->sc_dev, 2315 "SGMII(MDIO)\n"); 2316 sc->sc_flags |= WM_F_SGMII; 2317 sc->sc_mediatype = WM_MEDIATYPE_COPPER; 2318 break; 2319 } 2320 aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n"); 2321 /*FALLTHROUGH*/ 2322 case CTRL_EXT_LINK_MODE_PCIE_SERDES: 2323 sc->sc_mediatype = wm_sfp_get_media_type(sc); 2324 if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) { 2325 if (link_mode 2326 == CTRL_EXT_LINK_MODE_SGMII) { 2327 sc->sc_mediatype 2328 = WM_MEDIATYPE_COPPER; 2329 sc->sc_flags |= WM_F_SGMII; 2330 } else { 2331 sc->sc_mediatype 2332 = WM_MEDIATYPE_SERDES; 2333 aprint_verbose_dev(sc->sc_dev, 2334 "SERDES\n"); 2335 } 2336 break; 2337 } 2338 if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) 2339 aprint_verbose_dev(sc->sc_dev, 2340 "SERDES\n"); 2341 2342 /* Change current link mode setting */ 2343 reg &= ~CTRL_EXT_LINK_MODE_MASK; 2344 switch (sc->sc_mediatype) { 2345 case WM_MEDIATYPE_COPPER: 2346 reg |= CTRL_EXT_LINK_MODE_SGMII; 2347 break; 2348 case WM_MEDIATYPE_SERDES: 2349 reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES; 2350 break; 2351 default: 2352 break; 2353 } 2354 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 2355 break; 2356 case CTRL_EXT_LINK_MODE_GMII: 2357 default: 2358 aprint_verbose_dev(sc->sc_dev, "Copper\n"); 2359 sc->sc_mediatype = WM_MEDIATYPE_COPPER; 2360 break; 2361 } 2362 2363 reg &= ~CTRL_EXT_I2C_ENA; 2364 if ((sc->sc_flags & WM_F_SGMII) != 0) 2365 reg |= CTRL_EXT_I2C_ENA; 2366 else 2367 reg &= ~CTRL_EXT_I2C_ENA; 2368 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 2369 2370 if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) 2371 wm_gmii_mediainit(sc, wmp->wmp_product); 2372 else 2373 wm_tbi_mediainit(sc); 2374 break; 2375 default: 2376 if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) 2377 aprint_error_dev(sc->sc_dev, 2378 "WARNING: TBIMODE clear on 1000BASE-X product!\n"); 2379 sc->sc_mediatype = WM_MEDIATYPE_COPPER; 2380 wm_gmii_mediainit(sc, wmp->wmp_product); 2381 } 2382 } 2383 2384 ifp = &sc->sc_ethercom.ec_if; 2385 xname = device_xname(sc->sc_dev); 2386 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 2387 ifp->if_softc = sc; 2388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2389 ifp->if_ioctl = wm_ioctl; 2390 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) 2391 ifp->if_start = wm_nq_start; 2392 else 2393 ifp->if_start = wm_start; 2394 ifp->if_watchdog = wm_watchdog; 2395 ifp->if_init = wm_init; 2396 ifp->if_stop = wm_stop; 2397 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 2398 IFQ_SET_READY(&ifp->if_snd); 2399 2400 /* Check for jumbo frame */ 2401 switch (sc->sc_type) { 2402 case WM_T_82573: 2403 /* XXX limited to 9234 if ASPM is disabled */ 2404 wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword); 2405 if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0) 2406 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2407 break; 2408 case WM_T_82571: 2409 case WM_T_82572: 2410 case WM_T_82574: 2411 case WM_T_82575: 2412 case WM_T_82576: 2413 case WM_T_82580: 2414 case WM_T_I350: 2415 case WM_T_I354: /* XXXX ok? */ 2416 case WM_T_I210: 2417 case WM_T_I211: 2418 case WM_T_80003: 2419 case WM_T_ICH9: 2420 case WM_T_ICH10: 2421 case WM_T_PCH2: /* PCH2 supports 9K frame size */ 2422 case WM_T_PCH_LPT: 2423 case WM_T_PCH_SPT: 2424 /* XXX limited to 9234 */ 2425 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2426 break; 2427 case WM_T_PCH: 2428 /* XXX limited to 4096 */ 2429 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2430 break; 2431 case WM_T_82542_2_0: 2432 case WM_T_82542_2_1: 2433 case WM_T_82583: 2434 case WM_T_ICH8: 2435 /* No support for jumbo frame */ 2436 break; 2437 default: 2438 /* ETHER_MAX_LEN_JUMBO */ 2439 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2440 break; 2441 } 2442 2443 /* If we're a i82543 or greater, we can support VLANs. */ 2444 if (sc->sc_type >= WM_T_82543) 2445 sc->sc_ethercom.ec_capabilities |= 2446 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 2447 2448 /* 2449 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 2450 * on i82543 and later. 2451 */ 2452 if (sc->sc_type >= WM_T_82543) { 2453 ifp->if_capabilities |= 2454 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2455 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2456 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 2457 IFCAP_CSUM_TCPv6_Tx | 2458 IFCAP_CSUM_UDPv6_Tx; 2459 } 2460 2461 /* 2462 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL. 2463 * 2464 * 82541GI (8086:1076) ... no 2465 * 82572EI (8086:10b9) ... yes 2466 */ 2467 if (sc->sc_type >= WM_T_82571) { 2468 ifp->if_capabilities |= 2469 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 2470 } 2471 2472 /* 2473 * If we're a i82544 or greater (except i82547), we can do 2474 * TCP segmentation offload. 2475 */ 2476 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) { 2477 ifp->if_capabilities |= IFCAP_TSOv4; 2478 } 2479 2480 if (sc->sc_type >= WM_T_82571) { 2481 ifp->if_capabilities |= IFCAP_TSOv6; 2482 } 2483 2484 #ifdef WM_MPSAFE 2485 sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 2486 #else 2487 sc->sc_core_lock = NULL; 2488 #endif 2489 2490 /* Attach the interface. */ 2491 if_initialize(ifp); 2492 sc->sc_ipq = if_percpuq_create(&sc->sc_ethercom.ec_if); 2493 ether_ifattach(ifp, enaddr); 2494 if_register(ifp); 2495 ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb); 2496 rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 2497 RND_FLAG_DEFAULT); 2498 2499 #ifdef WM_EVENT_COUNTERS 2500 /* Attach event counters. */ 2501 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 2502 NULL, xname, "txsstall"); 2503 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 2504 NULL, xname, "txdstall"); 2505 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 2506 NULL, xname, "txfifo_stall"); 2507 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 2508 NULL, xname, "txdw"); 2509 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 2510 NULL, xname, "txqe"); 2511 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 2512 NULL, xname, "rxintr"); 2513 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 2514 NULL, xname, "linkintr"); 2515 2516 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 2517 NULL, xname, "rxipsum"); 2518 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 2519 NULL, xname, "rxtusum"); 2520 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 2521 NULL, xname, "txipsum"); 2522 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 2523 NULL, xname, "txtusum"); 2524 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 2525 NULL, xname, "txtusum6"); 2526 2527 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 2528 NULL, xname, "txtso"); 2529 evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC, 2530 NULL, xname, "txtso6"); 2531 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 2532 NULL, xname, "txtsopain"); 2533 2534 for (i = 0; i < WM_NTXSEGS; i++) { 2535 snprintf(wm_txseg_evcnt_names[i], 2536 sizeof(wm_txseg_evcnt_names[i]), "txseg%d", i); 2537 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 2538 NULL, xname, wm_txseg_evcnt_names[i]); 2539 } 2540 2541 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 2542 NULL, xname, "txdrop"); 2543 2544 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 2545 NULL, xname, "tu"); 2546 2547 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 2548 NULL, xname, "tx_xoff"); 2549 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 2550 NULL, xname, "tx_xon"); 2551 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 2552 NULL, xname, "rx_xoff"); 2553 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 2554 NULL, xname, "rx_xon"); 2555 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 2556 NULL, xname, "rx_macctl"); 2557 #endif /* WM_EVENT_COUNTERS */ 2558 2559 if (pmf_device_register(self, wm_suspend, wm_resume)) 2560 pmf_class_network_register(self, ifp); 2561 else 2562 aprint_error_dev(self, "couldn't establish power handler\n"); 2563 2564 sc->sc_flags |= WM_F_ATTACHED; 2565 out: 2566 return; 2567 } 2568 2569 /* The detach function (ca_detach) */ 2570 static int 2571 wm_detach(device_t self, int flags __unused) 2572 { 2573 struct wm_softc *sc = device_private(self); 2574 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2575 int i; 2576 #ifndef WM_MPSAFE 2577 int s; 2578 #endif 2579 2580 if ((sc->sc_flags & WM_F_ATTACHED) == 0) 2581 return 0; 2582 2583 #ifndef WM_MPSAFE 2584 s = splnet(); 2585 #endif 2586 /* Stop the interface. Callouts are stopped in it. */ 2587 wm_stop(ifp, 1); 2588 2589 #ifndef WM_MPSAFE 2590 splx(s); 2591 #endif 2592 2593 pmf_device_deregister(self); 2594 2595 /* Tell the firmware about the release */ 2596 WM_CORE_LOCK(sc); 2597 wm_release_manageability(sc); 2598 wm_release_hw_control(sc); 2599 WM_CORE_UNLOCK(sc); 2600 2601 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2602 2603 /* Delete all remaining media. */ 2604 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2605 2606 ether_ifdetach(ifp); 2607 if_detach(ifp); 2608 if_percpuq_destroy(sc->sc_ipq); 2609 2610 /* Unload RX dmamaps and free mbufs */ 2611 for (i = 0; i < sc->sc_nrxqueues; i++) { 2612 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 2613 WM_RX_LOCK(rxq); 2614 wm_rxdrain(rxq); 2615 WM_RX_UNLOCK(rxq); 2616 } 2617 /* Must unlock here */ 2618 2619 wm_free_txrx_queues(sc); 2620 2621 /* Disestablish the interrupt handler */ 2622 for (i = 0; i < sc->sc_nintrs; i++) { 2623 if (sc->sc_ihs[i] != NULL) { 2624 pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]); 2625 sc->sc_ihs[i] = NULL; 2626 } 2627 } 2628 pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs); 2629 2630 /* Unmap the registers */ 2631 if (sc->sc_ss) { 2632 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss); 2633 sc->sc_ss = 0; 2634 } 2635 if (sc->sc_ios) { 2636 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 2637 sc->sc_ios = 0; 2638 } 2639 if (sc->sc_flashs) { 2640 bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs); 2641 sc->sc_flashs = 0; 2642 } 2643 2644 if (sc->sc_core_lock) 2645 mutex_obj_free(sc->sc_core_lock); 2646 2647 return 0; 2648 } 2649 2650 static bool 2651 wm_suspend(device_t self, const pmf_qual_t *qual) 2652 { 2653 struct wm_softc *sc = device_private(self); 2654 2655 wm_release_manageability(sc); 2656 wm_release_hw_control(sc); 2657 #ifdef WM_WOL 2658 wm_enable_wakeup(sc); 2659 #endif 2660 2661 return true; 2662 } 2663 2664 static bool 2665 wm_resume(device_t self, const pmf_qual_t *qual) 2666 { 2667 struct wm_softc *sc = device_private(self); 2668 2669 wm_init_manageability(sc); 2670 2671 return true; 2672 } 2673 2674 /* 2675 * wm_watchdog: [ifnet interface function] 2676 * 2677 * Watchdog timer handler. 2678 */ 2679 static void 2680 wm_watchdog(struct ifnet *ifp) 2681 { 2682 struct wm_softc *sc = ifp->if_softc; 2683 struct wm_txqueue *txq = &sc->sc_txq[0]; 2684 2685 /* 2686 * Since we're using delayed interrupts, sweep up 2687 * before we report an error. 2688 */ 2689 WM_TX_LOCK(txq); 2690 wm_txeof(sc); 2691 WM_TX_UNLOCK(txq); 2692 2693 if (txq->txq_free != WM_NTXDESC(txq)) { 2694 #ifdef WM_DEBUG 2695 int i, j; 2696 struct wm_txsoft *txs; 2697 #endif 2698 log(LOG_ERR, 2699 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 2700 device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree, 2701 txq->txq_next); 2702 ifp->if_oerrors++; 2703 #ifdef WM_DEBUG 2704 for (i = txq->txq_sdirty; i != txq->txq_snext ; 2705 i = WM_NEXTTXS(txq, i)) { 2706 txs = &txq->txq_soft[i]; 2707 printf("txs %d tx %d -> %d\n", 2708 i, txs->txs_firstdesc, txs->txs_lastdesc); 2709 for (j = txs->txs_firstdesc; ; 2710 j = WM_NEXTTX(txq, j)) { 2711 printf("\tdesc %d: 0x%" PRIx64 "\n", j, 2712 txq->txq_nq_descs[j].nqtx_data.nqtxd_addr); 2713 printf("\t %#08x%08x\n", 2714 txq->txq_nq_descs[j].nqtx_data.nqtxd_fields, 2715 txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen); 2716 if (j == txs->txs_lastdesc) 2717 break; 2718 } 2719 } 2720 #endif 2721 /* Reset the interface. */ 2722 (void) wm_init(ifp); 2723 } 2724 2725 /* Try to get more packets going. */ 2726 ifp->if_start(ifp); 2727 } 2728 2729 /* 2730 * wm_tick: 2731 * 2732 * One second timer, used to check link status, sweep up 2733 * completed transmit jobs, etc. 2734 */ 2735 static void 2736 wm_tick(void *arg) 2737 { 2738 struct wm_softc *sc = arg; 2739 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2740 #ifndef WM_MPSAFE 2741 int s; 2742 2743 s = splnet(); 2744 #endif 2745 2746 WM_CORE_LOCK(sc); 2747 2748 if (sc->sc_stopping) 2749 goto out; 2750 2751 if (sc->sc_type >= WM_T_82542_2_1) { 2752 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2753 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2754 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2755 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2756 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2757 } 2758 2759 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 2760 ifp->if_ierrors += 0ULL + /* ensure quad_t */ 2761 + CSR_READ(sc, WMREG_CRCERRS) 2762 + CSR_READ(sc, WMREG_ALGNERRC) 2763 + CSR_READ(sc, WMREG_SYMERRC) 2764 + CSR_READ(sc, WMREG_RXERRC) 2765 + CSR_READ(sc, WMREG_SEC) 2766 + CSR_READ(sc, WMREG_CEXTERR) 2767 + CSR_READ(sc, WMREG_RLEC); 2768 ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC) + CSR_READ(sc, WMREG_RNBC); 2769 2770 if (sc->sc_flags & WM_F_HAS_MII) 2771 mii_tick(&sc->sc_mii); 2772 else if ((sc->sc_type >= WM_T_82575) 2773 && (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) 2774 wm_serdes_tick(sc); 2775 else 2776 wm_tbi_tick(sc); 2777 2778 out: 2779 WM_CORE_UNLOCK(sc); 2780 #ifndef WM_MPSAFE 2781 splx(s); 2782 #endif 2783 2784 if (!sc->sc_stopping) 2785 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2786 } 2787 2788 static int 2789 wm_ifflags_cb(struct ethercom *ec) 2790 { 2791 struct ifnet *ifp = &ec->ec_if; 2792 struct wm_softc *sc = ifp->if_softc; 2793 int change = ifp->if_flags ^ sc->sc_if_flags; 2794 int rc = 0; 2795 2796 WM_CORE_LOCK(sc); 2797 2798 if (change != 0) 2799 sc->sc_if_flags = ifp->if_flags; 2800 2801 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 2802 rc = ENETRESET; 2803 goto out; 2804 } 2805 2806 if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2807 wm_set_filter(sc); 2808 2809 wm_set_vlan(sc); 2810 2811 out: 2812 WM_CORE_UNLOCK(sc); 2813 2814 return rc; 2815 } 2816 2817 /* 2818 * wm_ioctl: [ifnet interface function] 2819 * 2820 * Handle control requests from the operator. 2821 */ 2822 static int 2823 wm_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2824 { 2825 struct wm_softc *sc = ifp->if_softc; 2826 struct ifreq *ifr = (struct ifreq *) data; 2827 struct ifaddr *ifa = (struct ifaddr *)data; 2828 struct sockaddr_dl *sdl; 2829 int s, error; 2830 2831 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 2832 device_xname(sc->sc_dev), __func__)); 2833 #ifndef WM_MPSAFE 2834 s = splnet(); 2835 #endif 2836 switch (cmd) { 2837 case SIOCSIFMEDIA: 2838 case SIOCGIFMEDIA: 2839 WM_CORE_LOCK(sc); 2840 /* Flow control requires full-duplex mode. */ 2841 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2842 (ifr->ifr_media & IFM_FDX) == 0) 2843 ifr->ifr_media &= ~IFM_ETH_FMASK; 2844 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2845 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2846 /* We can do both TXPAUSE and RXPAUSE. */ 2847 ifr->ifr_media |= 2848 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2849 } 2850 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2851 } 2852 WM_CORE_UNLOCK(sc); 2853 #ifdef WM_MPSAFE 2854 s = splnet(); 2855 #endif 2856 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2857 #ifdef WM_MPSAFE 2858 splx(s); 2859 #endif 2860 break; 2861 case SIOCINITIFADDR: 2862 WM_CORE_LOCK(sc); 2863 if (ifa->ifa_addr->sa_family == AF_LINK) { 2864 sdl = satosdl(ifp->if_dl->ifa_addr); 2865 (void)sockaddr_dl_setaddr(sdl, sdl->sdl_len, 2866 LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen); 2867 /* unicast address is first multicast entry */ 2868 wm_set_filter(sc); 2869 error = 0; 2870 WM_CORE_UNLOCK(sc); 2871 break; 2872 } 2873 WM_CORE_UNLOCK(sc); 2874 /*FALLTHROUGH*/ 2875 default: 2876 #ifdef WM_MPSAFE 2877 s = splnet(); 2878 #endif 2879 /* It may call wm_start, so unlock here */ 2880 error = ether_ioctl(ifp, cmd, data); 2881 #ifdef WM_MPSAFE 2882 splx(s); 2883 #endif 2884 if (error != ENETRESET) 2885 break; 2886 2887 error = 0; 2888 2889 if (cmd == SIOCSIFCAP) { 2890 error = (*ifp->if_init)(ifp); 2891 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2892 ; 2893 else if (ifp->if_flags & IFF_RUNNING) { 2894 /* 2895 * Multicast list has changed; set the hardware filter 2896 * accordingly. 2897 */ 2898 WM_CORE_LOCK(sc); 2899 wm_set_filter(sc); 2900 WM_CORE_UNLOCK(sc); 2901 } 2902 break; 2903 } 2904 2905 #ifndef WM_MPSAFE 2906 splx(s); 2907 #endif 2908 return error; 2909 } 2910 2911 /* MAC address related */ 2912 2913 /* 2914 * Get the offset of MAC address and return it. 2915 * If error occured, use offset 0. 2916 */ 2917 static uint16_t 2918 wm_check_alt_mac_addr(struct wm_softc *sc) 2919 { 2920 uint16_t myea[ETHER_ADDR_LEN / 2]; 2921 uint16_t offset = NVM_OFF_MACADDR; 2922 2923 /* Try to read alternative MAC address pointer */ 2924 if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0) 2925 return 0; 2926 2927 /* Check pointer if it's valid or not. */ 2928 if ((offset == 0x0000) || (offset == 0xffff)) 2929 return 0; 2930 2931 offset += NVM_OFF_MACADDR_82571(sc->sc_funcid); 2932 /* 2933 * Check whether alternative MAC address is valid or not. 2934 * Some cards have non 0xffff pointer but those don't use 2935 * alternative MAC address in reality. 2936 * 2937 * Check whether the broadcast bit is set or not. 2938 */ 2939 if (wm_nvm_read(sc, offset, 1, myea) == 0) 2940 if (((myea[0] & 0xff) & 0x01) == 0) 2941 return offset; /* Found */ 2942 2943 /* Not found */ 2944 return 0; 2945 } 2946 2947 static int 2948 wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr) 2949 { 2950 uint16_t myea[ETHER_ADDR_LEN / 2]; 2951 uint16_t offset = NVM_OFF_MACADDR; 2952 int do_invert = 0; 2953 2954 switch (sc->sc_type) { 2955 case WM_T_82580: 2956 case WM_T_I350: 2957 case WM_T_I354: 2958 /* EEPROM Top Level Partitioning */ 2959 offset = NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + 0; 2960 break; 2961 case WM_T_82571: 2962 case WM_T_82575: 2963 case WM_T_82576: 2964 case WM_T_80003: 2965 case WM_T_I210: 2966 case WM_T_I211: 2967 offset = wm_check_alt_mac_addr(sc); 2968 if (offset == 0) 2969 if ((sc->sc_funcid & 0x01) == 1) 2970 do_invert = 1; 2971 break; 2972 default: 2973 if ((sc->sc_funcid & 0x01) == 1) 2974 do_invert = 1; 2975 break; 2976 } 2977 2978 if (wm_nvm_read(sc, offset, sizeof(myea) / sizeof(myea[0]), 2979 myea) != 0) 2980 goto bad; 2981 2982 enaddr[0] = myea[0] & 0xff; 2983 enaddr[1] = myea[0] >> 8; 2984 enaddr[2] = myea[1] & 0xff; 2985 enaddr[3] = myea[1] >> 8; 2986 enaddr[4] = myea[2] & 0xff; 2987 enaddr[5] = myea[2] >> 8; 2988 2989 /* 2990 * Toggle the LSB of the MAC address on the second port 2991 * of some dual port cards. 2992 */ 2993 if (do_invert != 0) 2994 enaddr[5] ^= 1; 2995 2996 return 0; 2997 2998 bad: 2999 return -1; 3000 } 3001 3002 /* 3003 * wm_set_ral: 3004 * 3005 * Set an entery in the receive address list. 3006 */ 3007 static void 3008 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3009 { 3010 uint32_t ral_lo, ral_hi; 3011 3012 if (enaddr != NULL) { 3013 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3014 (enaddr[3] << 24); 3015 ral_hi = enaddr[4] | (enaddr[5] << 8); 3016 ral_hi |= RAL_AV; 3017 } else { 3018 ral_lo = 0; 3019 ral_hi = 0; 3020 } 3021 3022 if (sc->sc_type >= WM_T_82544) { 3023 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3024 ral_lo); 3025 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3026 ral_hi); 3027 } else { 3028 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3029 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3030 } 3031 } 3032 3033 /* 3034 * wm_mchash: 3035 * 3036 * Compute the hash of the multicast address for the 4096-bit 3037 * multicast filter. 3038 */ 3039 static uint32_t 3040 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3041 { 3042 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3043 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3044 static const int ich8_lo_shift[4] = { 6, 5, 4, 2 }; 3045 static const int ich8_hi_shift[4] = { 2, 3, 4, 6 }; 3046 uint32_t hash; 3047 3048 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 3049 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 3050 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT) 3051 || (sc->sc_type == WM_T_PCH_SPT)) { 3052 hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) | 3053 (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]); 3054 return (hash & 0x3ff); 3055 } 3056 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3057 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3058 3059 return (hash & 0xfff); 3060 } 3061 3062 /* 3063 * wm_set_filter: 3064 * 3065 * Set up the receive filter. 3066 */ 3067 static void 3068 wm_set_filter(struct wm_softc *sc) 3069 { 3070 struct ethercom *ec = &sc->sc_ethercom; 3071 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3072 struct ether_multi *enm; 3073 struct ether_multistep step; 3074 bus_addr_t mta_reg; 3075 uint32_t hash, reg, bit; 3076 int i, size, ralmax; 3077 3078 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 3079 device_xname(sc->sc_dev), __func__)); 3080 if (sc->sc_type >= WM_T_82544) 3081 mta_reg = WMREG_CORDOVA_MTA; 3082 else 3083 mta_reg = WMREG_MTA; 3084 3085 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3086 3087 if (ifp->if_flags & IFF_BROADCAST) 3088 sc->sc_rctl |= RCTL_BAM; 3089 if (ifp->if_flags & IFF_PROMISC) { 3090 sc->sc_rctl |= RCTL_UPE; 3091 goto allmulti; 3092 } 3093 3094 /* 3095 * Set the station address in the first RAL slot, and 3096 * clear the remaining slots. 3097 */ 3098 if (sc->sc_type == WM_T_ICH8) 3099 size = WM_RAL_TABSIZE_ICH8 -1; 3100 else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10) 3101 || (sc->sc_type == WM_T_PCH)) 3102 size = WM_RAL_TABSIZE_ICH8; 3103 else if (sc->sc_type == WM_T_PCH2) 3104 size = WM_RAL_TABSIZE_PCH2; 3105 else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT)) 3106 size = WM_RAL_TABSIZE_PCH_LPT; 3107 else if (sc->sc_type == WM_T_82575) 3108 size = WM_RAL_TABSIZE_82575; 3109 else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580)) 3110 size = WM_RAL_TABSIZE_82576; 3111 else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) 3112 size = WM_RAL_TABSIZE_I350; 3113 else 3114 size = WM_RAL_TABSIZE; 3115 wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 3116 3117 if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) { 3118 i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC); 3119 switch (i) { 3120 case 0: 3121 /* We can use all entries */ 3122 ralmax = size; 3123 break; 3124 case 1: 3125 /* Only RAR[0] */ 3126 ralmax = 1; 3127 break; 3128 default: 3129 /* available SHRA + RAR[0] */ 3130 ralmax = i + 1; 3131 } 3132 } else 3133 ralmax = size; 3134 for (i = 1; i < size; i++) { 3135 if (i < ralmax) 3136 wm_set_ral(sc, NULL, i); 3137 } 3138 3139 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 3140 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 3141 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT) 3142 || (sc->sc_type == WM_T_PCH_SPT)) 3143 size = WM_ICH8_MC_TABSIZE; 3144 else 3145 size = WM_MC_TABSIZE; 3146 /* Clear out the multicast table. */ 3147 for (i = 0; i < size; i++) 3148 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3149 3150 ETHER_FIRST_MULTI(step, ec, enm); 3151 while (enm != NULL) { 3152 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3153 /* 3154 * We must listen to a range of multicast addresses. 3155 * For now, just accept all multicasts, rather than 3156 * trying to set only those filter bits needed to match 3157 * the range. (At this time, the only use of address 3158 * ranges is for IP multicast routing, for which the 3159 * range is big enough to require all bits set.) 3160 */ 3161 goto allmulti; 3162 } 3163 3164 hash = wm_mchash(sc, enm->enm_addrlo); 3165 3166 reg = (hash >> 5); 3167 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 3168 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 3169 || (sc->sc_type == WM_T_PCH2) 3170 || (sc->sc_type == WM_T_PCH_LPT) 3171 || (sc->sc_type == WM_T_PCH_SPT)) 3172 reg &= 0x1f; 3173 else 3174 reg &= 0x7f; 3175 bit = hash & 0x1f; 3176 3177 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3178 hash |= 1U << bit; 3179 3180 if (sc->sc_type == WM_T_82544 && (reg & 1) != 0) { 3181 /* 3182 * 82544 Errata 9: Certain register cannot be written 3183 * with particular alignments in PCI-X bus operation 3184 * (FCAH, MTA and VFTA). 3185 */ 3186 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3187 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3188 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3189 } else 3190 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3191 3192 ETHER_NEXT_MULTI(step, enm); 3193 } 3194 3195 ifp->if_flags &= ~IFF_ALLMULTI; 3196 goto setit; 3197 3198 allmulti: 3199 ifp->if_flags |= IFF_ALLMULTI; 3200 sc->sc_rctl |= RCTL_MPE; 3201 3202 setit: 3203 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3204 } 3205 3206 /* Reset and init related */ 3207 3208 static void 3209 wm_set_vlan(struct wm_softc *sc) 3210 { 3211 3212 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 3213 device_xname(sc->sc_dev), __func__)); 3214 /* Deal with VLAN enables. */ 3215 if (VLAN_ATTACHED(&sc->sc_ethercom)) 3216 sc->sc_ctrl |= CTRL_VME; 3217 else 3218 sc->sc_ctrl &= ~CTRL_VME; 3219 3220 /* Write the control registers. */ 3221 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3222 } 3223 3224 static void 3225 wm_set_pcie_completion_timeout(struct wm_softc *sc) 3226 { 3227 uint32_t gcr; 3228 pcireg_t ctrl2; 3229 3230 gcr = CSR_READ(sc, WMREG_GCR); 3231 3232 /* Only take action if timeout value is defaulted to 0 */ 3233 if ((gcr & GCR_CMPL_TMOUT_MASK) != 0) 3234 goto out; 3235 3236 if ((gcr & GCR_CAP_VER2) == 0) { 3237 gcr |= GCR_CMPL_TMOUT_10MS; 3238 goto out; 3239 } 3240 3241 ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3242 sc->sc_pcixe_capoff + PCIE_DCSR2); 3243 ctrl2 |= WM_PCIE_DCSR2_16MS; 3244 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3245 sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2); 3246 3247 out: 3248 /* Disable completion timeout resend */ 3249 gcr &= ~GCR_CMPL_TMOUT_RESEND; 3250 3251 CSR_WRITE(sc, WMREG_GCR, gcr); 3252 } 3253 3254 void 3255 wm_get_auto_rd_done(struct wm_softc *sc) 3256 { 3257 int i; 3258 3259 /* wait for eeprom to reload */ 3260 switch (sc->sc_type) { 3261 case WM_T_82571: 3262 case WM_T_82572: 3263 case WM_T_82573: 3264 case WM_T_82574: 3265 case WM_T_82583: 3266 case WM_T_82575: 3267 case WM_T_82576: 3268 case WM_T_82580: 3269 case WM_T_I350: 3270 case WM_T_I354: 3271 case WM_T_I210: 3272 case WM_T_I211: 3273 case WM_T_80003: 3274 case WM_T_ICH8: 3275 case WM_T_ICH9: 3276 for (i = 0; i < 10; i++) { 3277 if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD) 3278 break; 3279 delay(1000); 3280 } 3281 if (i == 10) { 3282 log(LOG_ERR, "%s: auto read from eeprom failed to " 3283 "complete\n", device_xname(sc->sc_dev)); 3284 } 3285 break; 3286 default: 3287 break; 3288 } 3289 } 3290 3291 void 3292 wm_lan_init_done(struct wm_softc *sc) 3293 { 3294 uint32_t reg = 0; 3295 int i; 3296 3297 /* wait for eeprom to reload */ 3298 switch (sc->sc_type) { 3299 case WM_T_ICH10: 3300 case WM_T_PCH: 3301 case WM_T_PCH2: 3302 case WM_T_PCH_LPT: 3303 case WM_T_PCH_SPT: 3304 for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) { 3305 reg = CSR_READ(sc, WMREG_STATUS); 3306 if ((reg & STATUS_LAN_INIT_DONE) != 0) 3307 break; 3308 delay(100); 3309 } 3310 if (i >= WM_ICH8_LAN_INIT_TIMEOUT) { 3311 log(LOG_ERR, "%s: %s: lan_init_done failed to " 3312 "complete\n", device_xname(sc->sc_dev), __func__); 3313 } 3314 break; 3315 default: 3316 panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), 3317 __func__); 3318 break; 3319 } 3320 3321 reg &= ~STATUS_LAN_INIT_DONE; 3322 CSR_WRITE(sc, WMREG_STATUS, reg); 3323 } 3324 3325 void 3326 wm_get_cfg_done(struct wm_softc *sc) 3327 { 3328 int mask; 3329 uint32_t reg; 3330 int i; 3331 3332 /* wait for eeprom to reload */ 3333 switch (sc->sc_type) { 3334 case WM_T_82542_2_0: 3335 case WM_T_82542_2_1: 3336 /* null */ 3337 break; 3338 case WM_T_82543: 3339 case WM_T_82544: 3340 case WM_T_82540: 3341 case WM_T_82545: 3342 case WM_T_82545_3: 3343 case WM_T_82546: 3344 case WM_T_82546_3: 3345 case WM_T_82541: 3346 case WM_T_82541_2: 3347 case WM_T_82547: 3348 case WM_T_82547_2: 3349 case WM_T_82573: 3350 case WM_T_82574: 3351 case WM_T_82583: 3352 /* generic */ 3353 delay(10*1000); 3354 break; 3355 case WM_T_80003: 3356 case WM_T_82571: 3357 case WM_T_82572: 3358 case WM_T_82575: 3359 case WM_T_82576: 3360 case WM_T_82580: 3361 case WM_T_I350: 3362 case WM_T_I354: 3363 case WM_T_I210: 3364 case WM_T_I211: 3365 if (sc->sc_type == WM_T_82571) { 3366 /* Only 82571 shares port 0 */ 3367 mask = EEMNGCTL_CFGDONE_0; 3368 } else 3369 mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid; 3370 for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) { 3371 if (CSR_READ(sc, WMREG_EEMNGCTL) & mask) 3372 break; 3373 delay(1000); 3374 } 3375 if (i >= WM_PHY_CFG_TIMEOUT) { 3376 DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n", 3377 device_xname(sc->sc_dev), __func__)); 3378 } 3379 break; 3380 case WM_T_ICH8: 3381 case WM_T_ICH9: 3382 case WM_T_ICH10: 3383 case WM_T_PCH: 3384 case WM_T_PCH2: 3385 case WM_T_PCH_LPT: 3386 case WM_T_PCH_SPT: 3387 delay(10*1000); 3388 if (sc->sc_type >= WM_T_ICH10) 3389 wm_lan_init_done(sc); 3390 else 3391 wm_get_auto_rd_done(sc); 3392 3393 reg = CSR_READ(sc, WMREG_STATUS); 3394 if ((reg & STATUS_PHYRA) != 0) 3395 CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA); 3396 break; 3397 default: 3398 panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), 3399 __func__); 3400 break; 3401 } 3402 } 3403 3404 /* Init hardware bits */ 3405 void 3406 wm_initialize_hardware_bits(struct wm_softc *sc) 3407 { 3408 uint32_t tarc0, tarc1, reg; 3409 3410 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 3411 device_xname(sc->sc_dev), __func__)); 3412 /* For 82571 variant, 80003 and ICHs */ 3413 if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583)) 3414 || (sc->sc_type >= WM_T_80003)) { 3415 3416 /* Transmit Descriptor Control 0 */ 3417 reg = CSR_READ(sc, WMREG_TXDCTL(0)); 3418 reg |= TXDCTL_COUNT_DESC; 3419 CSR_WRITE(sc, WMREG_TXDCTL(0), reg); 3420 3421 /* Transmit Descriptor Control 1 */ 3422 reg = CSR_READ(sc, WMREG_TXDCTL(1)); 3423 reg |= TXDCTL_COUNT_DESC; 3424 CSR_WRITE(sc, WMREG_TXDCTL(1), reg); 3425 3426 /* TARC0 */ 3427 tarc0 = CSR_READ(sc, WMREG_TARC0); 3428 switch (sc->sc_type) { 3429 case WM_T_82571: 3430 case WM_T_82572: 3431 case WM_T_82573: 3432 case WM_T_82574: 3433 case WM_T_82583: 3434 case WM_T_80003: 3435 /* Clear bits 30..27 */ 3436 tarc0 &= ~__BITS(30, 27); 3437 break; 3438 default: 3439 break; 3440 } 3441 3442 switch (sc->sc_type) { 3443 case WM_T_82571: 3444 case WM_T_82572: 3445 tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */ 3446 3447 tarc1 = CSR_READ(sc, WMREG_TARC1); 3448 tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */ 3449 tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */ 3450 /* 8257[12] Errata No.7 */ 3451 tarc1 |= __BIT(22); /* TARC1 bits 22 */ 3452 3453 /* TARC1 bit 28 */ 3454 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) 3455 tarc1 &= ~__BIT(28); 3456 else 3457 tarc1 |= __BIT(28); 3458 CSR_WRITE(sc, WMREG_TARC1, tarc1); 3459 3460 /* 3461 * 8257[12] Errata No.13 3462 * Disable Dyamic Clock Gating. 3463 */ 3464 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3465 reg &= ~CTRL_EXT_DMA_DYN_CLK; 3466 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3467 break; 3468 case WM_T_82573: 3469 case WM_T_82574: 3470 case WM_T_82583: 3471 if ((sc->sc_type == WM_T_82574) 3472 || (sc->sc_type == WM_T_82583)) 3473 tarc0 |= __BIT(26); /* TARC0 bit 26 */ 3474 3475 /* Extended Device Control */ 3476 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3477 reg &= ~__BIT(23); /* Clear bit 23 */ 3478 reg |= __BIT(22); /* Set bit 22 */ 3479 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3480 3481 /* Device Control */ 3482 sc->sc_ctrl &= ~__BIT(29); /* Clear bit 29 */ 3483 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3484 3485 /* PCIe Control Register */ 3486 /* 3487 * 82573 Errata (unknown). 3488 * 3489 * 82574 Errata 25 and 82583 Errata 12 3490 * "Dropped Rx Packets": 3491 * NVM Image Version 2.1.4 and newer has no this bug. 3492 */ 3493 reg = CSR_READ(sc, WMREG_GCR); 3494 reg |= GCR_L1_ACT_WITHOUT_L0S_RX; 3495 CSR_WRITE(sc, WMREG_GCR, reg); 3496 3497 if ((sc->sc_type == WM_T_82574) 3498 || (sc->sc_type == WM_T_82583)) { 3499 /* 3500 * Document says this bit must be set for 3501 * proper operation. 3502 */ 3503 reg = CSR_READ(sc, WMREG_GCR); 3504 reg |= __BIT(22); 3505 CSR_WRITE(sc, WMREG_GCR, reg); 3506 3507 /* 3508 * Apply workaround for hardware errata 3509 * documented in errata docs Fixes issue where 3510 * some error prone or unreliable PCIe 3511 * completions are occurring, particularly 3512 * with ASPM enabled. Without fix, issue can 3513 * cause Tx timeouts. 3514 */ 3515 reg = CSR_READ(sc, WMREG_GCR2); 3516 reg |= __BIT(0); 3517 CSR_WRITE(sc, WMREG_GCR2, reg); 3518 } 3519 break; 3520 case WM_T_80003: 3521 /* TARC0 */ 3522 if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER) 3523 || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) 3524 tarc0 &= ~__BIT(20); /* Clear bits 20 */ 3525 3526 /* TARC1 bit 28 */ 3527 tarc1 = CSR_READ(sc, WMREG_TARC1); 3528 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) 3529 tarc1 &= ~__BIT(28); 3530 else 3531 tarc1 |= __BIT(28); 3532 CSR_WRITE(sc, WMREG_TARC1, tarc1); 3533 break; 3534 case WM_T_ICH8: 3535 case WM_T_ICH9: 3536 case WM_T_ICH10: 3537 case WM_T_PCH: 3538 case WM_T_PCH2: 3539 case WM_T_PCH_LPT: 3540 case WM_T_PCH_SPT: 3541 /* TARC0 */ 3542 if ((sc->sc_type == WM_T_ICH8) 3543 || (sc->sc_type == WM_T_PCH_SPT)) { 3544 /* Set TARC0 bits 29 and 28 */ 3545 tarc0 |= __BITS(29, 28); 3546 } 3547 /* Set TARC0 bits 23,24,26,27 */ 3548 tarc0 |= __BITS(27, 26) | __BITS(24, 23); 3549 3550 /* CTRL_EXT */ 3551 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3552 reg |= __BIT(22); /* Set bit 22 */ 3553 /* 3554 * Enable PHY low-power state when MAC is at D3 3555 * w/o WoL 3556 */ 3557 if (sc->sc_type >= WM_T_PCH) 3558 reg |= CTRL_EXT_PHYPDEN; 3559 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3560 3561 /* TARC1 */ 3562 tarc1 = CSR_READ(sc, WMREG_TARC1); 3563 /* bit 28 */ 3564 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) 3565 tarc1 &= ~__BIT(28); 3566 else 3567 tarc1 |= __BIT(28); 3568 tarc1 |= __BIT(24) | __BIT(26) | __BIT(30); 3569 CSR_WRITE(sc, WMREG_TARC1, tarc1); 3570 3571 /* Device Status */ 3572 if (sc->sc_type == WM_T_ICH8) { 3573 reg = CSR_READ(sc, WMREG_STATUS); 3574 reg &= ~__BIT(31); 3575 CSR_WRITE(sc, WMREG_STATUS, reg); 3576 3577 } 3578 3579 /* IOSFPC */ 3580 if (sc->sc_type == WM_T_PCH_SPT) { 3581 reg = CSR_READ(sc, WMREG_IOSFPC); 3582 reg |= RCTL_RDMTS_HEX; /* XXX RTCL bit? */ 3583 CSR_WRITE(sc, WMREG_IOSFPC, reg); 3584 } 3585 /* 3586 * Work-around descriptor data corruption issue during 3587 * NFS v2 UDP traffic, just disable the NFS filtering 3588 * capability. 3589 */ 3590 reg = CSR_READ(sc, WMREG_RFCTL); 3591 reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS; 3592 CSR_WRITE(sc, WMREG_RFCTL, reg); 3593 break; 3594 default: 3595 break; 3596 } 3597 CSR_WRITE(sc, WMREG_TARC0, tarc0); 3598 3599 /* 3600 * 8257[12] Errata No.52 and some others. 3601 * Avoid RSS Hash Value bug. 3602 */ 3603 switch (sc->sc_type) { 3604 case WM_T_82571: 3605 case WM_T_82572: 3606 case WM_T_82573: 3607 case WM_T_80003: 3608 case WM_T_ICH8: 3609 reg = CSR_READ(sc, WMREG_RFCTL); 3610 reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS; 3611 CSR_WRITE(sc, WMREG_RFCTL, reg); 3612 break; 3613 default: 3614 break; 3615 } 3616 } 3617 } 3618 3619 static uint32_t 3620 wm_rxpbs_adjust_82580(uint32_t val) 3621 { 3622 uint32_t rv = 0; 3623 3624 if (val < __arraycount(wm_82580_rxpbs_table)) 3625 rv = wm_82580_rxpbs_table[val]; 3626 3627 return rv; 3628 } 3629 3630 /* 3631 * wm_reset: 3632 * 3633 * Reset the i82542 chip. 3634 */ 3635 static void 3636 wm_reset(struct wm_softc *sc) 3637 { 3638 int phy_reset = 0; 3639 int i, error = 0; 3640 uint32_t reg, mask; 3641 3642 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 3643 device_xname(sc->sc_dev), __func__)); 3644 /* 3645 * Allocate on-chip memory according to the MTU size. 3646 * The Packet Buffer Allocation register must be written 3647 * before the chip is reset. 3648 */ 3649 switch (sc->sc_type) { 3650 case WM_T_82547: 3651 case WM_T_82547_2: 3652 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 3653 PBA_22K : PBA_30K; 3654 for (i = 0; i < sc->sc_ntxqueues; i++) { 3655 struct wm_txqueue *txq = &sc->sc_txq[i]; 3656 txq->txq_fifo_head = 0; 3657 txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 3658 txq->txq_fifo_size = 3659 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 3660 txq->txq_fifo_stall = 0; 3661 } 3662 break; 3663 case WM_T_82571: 3664 case WM_T_82572: 3665 case WM_T_82575: /* XXX need special handing for jumbo frames */ 3666 case WM_T_80003: 3667 sc->sc_pba = PBA_32K; 3668 break; 3669 case WM_T_82573: 3670 sc->sc_pba = PBA_12K; 3671 break; 3672 case WM_T_82574: 3673 case WM_T_82583: 3674 sc->sc_pba = PBA_20K; 3675 break; 3676 case WM_T_82576: 3677 sc->sc_pba = CSR_READ(sc, WMREG_RXPBS); 3678 sc->sc_pba &= RXPBS_SIZE_MASK_82576; 3679 break; 3680 case WM_T_82580: 3681 case WM_T_I350: 3682 case WM_T_I354: 3683 sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS)); 3684 break; 3685 case WM_T_I210: 3686 case WM_T_I211: 3687 sc->sc_pba = PBA_34K; 3688 break; 3689 case WM_T_ICH8: 3690 /* Workaround for a bit corruption issue in FIFO memory */ 3691 sc->sc_pba = PBA_8K; 3692 CSR_WRITE(sc, WMREG_PBS, PBA_16K); 3693 break; 3694 case WM_T_ICH9: 3695 case WM_T_ICH10: 3696 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ? 3697 PBA_14K : PBA_10K; 3698 break; 3699 case WM_T_PCH: 3700 case WM_T_PCH2: 3701 case WM_T_PCH_LPT: 3702 case WM_T_PCH_SPT: 3703 sc->sc_pba = PBA_26K; 3704 break; 3705 default: 3706 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 3707 PBA_40K : PBA_48K; 3708 break; 3709 } 3710 /* 3711 * Only old or non-multiqueue devices have the PBA register 3712 * XXX Need special handling for 82575. 3713 */ 3714 if (((sc->sc_flags & WM_F_NEWQUEUE) == 0) 3715 || (sc->sc_type == WM_T_82575)) 3716 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 3717 3718 /* Prevent the PCI-E bus from sticking */ 3719 if (sc->sc_flags & WM_F_PCIE) { 3720 int timeout = 800; 3721 3722 sc->sc_ctrl |= CTRL_GIO_M_DIS; 3723 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3724 3725 while (timeout--) { 3726 if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA) 3727 == 0) 3728 break; 3729 delay(100); 3730 } 3731 } 3732 3733 /* Set the completion timeout for interface */ 3734 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) 3735 || (sc->sc_type == WM_T_82580) 3736 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) 3737 || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) 3738 wm_set_pcie_completion_timeout(sc); 3739 3740 /* Clear interrupt */ 3741 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3742 if (sc->sc_nintrs > 1) { 3743 if (sc->sc_type != WM_T_82574) { 3744 CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); 3745 CSR_WRITE(sc, WMREG_EIAC, 0); 3746 } else { 3747 CSR_WRITE(sc, WMREG_EIAC_82574, 0); 3748 } 3749 } 3750 3751 /* Stop the transmit and receive processes. */ 3752 CSR_WRITE(sc, WMREG_RCTL, 0); 3753 sc->sc_rctl &= ~RCTL_EN; 3754 CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP); 3755 CSR_WRITE_FLUSH(sc); 3756 3757 /* XXX set_tbi_sbp_82543() */ 3758 3759 delay(10*1000); 3760 3761 /* Must acquire the MDIO ownership before MAC reset */ 3762 switch (sc->sc_type) { 3763 case WM_T_82573: 3764 case WM_T_82574: 3765 case WM_T_82583: 3766 error = wm_get_hw_semaphore_82573(sc); 3767 break; 3768 default: 3769 break; 3770 } 3771 3772 /* 3773 * 82541 Errata 29? & 82547 Errata 28? 3774 * See also the description about PHY_RST bit in CTRL register 3775 * in 8254x_GBe_SDM.pdf. 3776 */ 3777 if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) { 3778 CSR_WRITE(sc, WMREG_CTRL, 3779 CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET); 3780 CSR_WRITE_FLUSH(sc); 3781 delay(5000); 3782 } 3783 3784 switch (sc->sc_type) { 3785 case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */ 3786 case WM_T_82541: 3787 case WM_T_82541_2: 3788 case WM_T_82547: 3789 case WM_T_82547_2: 3790 /* 3791 * On some chipsets, a reset through a memory-mapped write 3792 * cycle can cause the chip to reset before completing the 3793 * write cycle. This causes major headache that can be 3794 * avoided by issuing the reset via indirect register writes 3795 * through I/O space. 3796 * 3797 * So, if we successfully mapped the I/O BAR at attach time, 3798 * use that. Otherwise, try our luck with a memory-mapped 3799 * reset. 3800 */ 3801 if (sc->sc_flags & WM_F_IOH_VALID) 3802 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 3803 else 3804 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 3805 break; 3806 case WM_T_82545_3: 3807 case WM_T_82546_3: 3808 /* Use the shadow control register on these chips. */ 3809 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 3810 break; 3811 case WM_T_80003: 3812 mask = swfwphysem[sc->sc_funcid]; 3813 reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST; 3814 wm_get_swfw_semaphore(sc, mask); 3815 CSR_WRITE(sc, WMREG_CTRL, reg); 3816 wm_put_swfw_semaphore(sc, mask); 3817 break; 3818 case WM_T_ICH8: 3819 case WM_T_ICH9: 3820 case WM_T_ICH10: 3821 case WM_T_PCH: 3822 case WM_T_PCH2: 3823 case WM_T_PCH_LPT: 3824 case WM_T_PCH_SPT: 3825 reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST; 3826 if (wm_phy_resetisblocked(sc) == false) { 3827 /* 3828 * Gate automatic PHY configuration by hardware on 3829 * non-managed 82579 3830 */ 3831 if ((sc->sc_type == WM_T_PCH2) 3832 && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) 3833 == 0)) 3834 wm_gate_hw_phy_config_ich8lan(sc, true); 3835 3836 reg |= CTRL_PHY_RESET; 3837 phy_reset = 1; 3838 } else 3839 printf("XXX reset is blocked!!!\n"); 3840 wm_get_swfwhw_semaphore(sc); 3841 CSR_WRITE(sc, WMREG_CTRL, reg); 3842 /* Don't insert a completion barrier when reset */ 3843 delay(20*1000); 3844 wm_put_swfwhw_semaphore(sc); 3845 break; 3846 case WM_T_82580: 3847 case WM_T_I350: 3848 case WM_T_I354: 3849 case WM_T_I210: 3850 case WM_T_I211: 3851 CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST); 3852 if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII) 3853 CSR_WRITE_FLUSH(sc); 3854 delay(5000); 3855 break; 3856 case WM_T_82542_2_0: 3857 case WM_T_82542_2_1: 3858 case WM_T_82543: 3859 case WM_T_82540: 3860 case WM_T_82545: 3861 case WM_T_82546: 3862 case WM_T_82571: 3863 case WM_T_82572: 3864 case WM_T_82573: 3865 case WM_T_82574: 3866 case WM_T_82575: 3867 case WM_T_82576: 3868 case WM_T_82583: 3869 default: 3870 /* Everything else can safely use the documented method. */ 3871 CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST); 3872 break; 3873 } 3874 3875 /* Must release the MDIO ownership after MAC reset */ 3876 switch (sc->sc_type) { 3877 case WM_T_82573: 3878 case WM_T_82574: 3879 case WM_T_82583: 3880 if (error == 0) 3881 wm_put_hw_semaphore_82573(sc); 3882 break; 3883 default: 3884 break; 3885 } 3886 3887 if (phy_reset != 0) 3888 wm_get_cfg_done(sc); 3889 3890 /* reload EEPROM */ 3891 switch (sc->sc_type) { 3892 case WM_T_82542_2_0: 3893 case WM_T_82542_2_1: 3894 case WM_T_82543: 3895 case WM_T_82544: 3896 delay(10); 3897 reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST; 3898 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3899 CSR_WRITE_FLUSH(sc); 3900 delay(2000); 3901 break; 3902 case WM_T_82540: 3903 case WM_T_82545: 3904 case WM_T_82545_3: 3905 case WM_T_82546: 3906 case WM_T_82546_3: 3907 delay(5*1000); 3908 /* XXX Disable HW ARPs on ASF enabled adapters */ 3909 break; 3910 case WM_T_82541: 3911 case WM_T_82541_2: 3912 case WM_T_82547: 3913 case WM_T_82547_2: 3914 delay(20000); 3915 /* XXX Disable HW ARPs on ASF enabled adapters */ 3916 break; 3917 case WM_T_82571: 3918 case WM_T_82572: 3919 case WM_T_82573: 3920 case WM_T_82574: 3921 case WM_T_82583: 3922 if (sc->sc_flags & WM_F_EEPROM_FLASH) { 3923 delay(10); 3924 reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST; 3925 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3926 CSR_WRITE_FLUSH(sc); 3927 } 3928 /* check EECD_EE_AUTORD */ 3929 wm_get_auto_rd_done(sc); 3930 /* 3931 * Phy configuration from NVM just starts after EECD_AUTO_RD 3932 * is set. 3933 */ 3934 if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574) 3935 || (sc->sc_type == WM_T_82583)) 3936 delay(25*1000); 3937 break; 3938 case WM_T_82575: 3939 case WM_T_82576: 3940 case WM_T_82580: 3941 case WM_T_I350: 3942 case WM_T_I354: 3943 case WM_T_I210: 3944 case WM_T_I211: 3945 case WM_T_80003: 3946 /* check EECD_EE_AUTORD */ 3947 wm_get_auto_rd_done(sc); 3948 break; 3949 case WM_T_ICH8: 3950 case WM_T_ICH9: 3951 case WM_T_ICH10: 3952 case WM_T_PCH: 3953 case WM_T_PCH2: 3954 case WM_T_PCH_LPT: 3955 case WM_T_PCH_SPT: 3956 break; 3957 default: 3958 panic("%s: unknown type\n", __func__); 3959 } 3960 3961 /* Check whether EEPROM is present or not */ 3962 switch (sc->sc_type) { 3963 case WM_T_82575: 3964 case WM_T_82576: 3965 case WM_T_82580: 3966 case WM_T_I350: 3967 case WM_T_I354: 3968 case WM_T_ICH8: 3969 case WM_T_ICH9: 3970 if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) { 3971 /* Not found */ 3972 sc->sc_flags |= WM_F_EEPROM_INVALID; 3973 if (sc->sc_type == WM_T_82575) 3974 wm_reset_init_script_82575(sc); 3975 } 3976 break; 3977 default: 3978 break; 3979 } 3980 3981 if ((sc->sc_type == WM_T_82580) 3982 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) { 3983 /* clear global device reset status bit */ 3984 CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET); 3985 } 3986 3987 /* Clear any pending interrupt events. */ 3988 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3989 reg = CSR_READ(sc, WMREG_ICR); 3990 if (sc->sc_nintrs > 1) { 3991 if (sc->sc_type != WM_T_82574) { 3992 CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); 3993 CSR_WRITE(sc, WMREG_EIAC, 0); 3994 } else 3995 CSR_WRITE(sc, WMREG_EIAC_82574, 0); 3996 } 3997 3998 /* reload sc_ctrl */ 3999 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL); 4000 4001 if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211)) 4002 wm_set_eee_i350(sc); 4003 4004 /* dummy read from WUC */ 4005 if (sc->sc_type == WM_T_PCH) 4006 reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC); 4007 /* 4008 * For PCH, this write will make sure that any noise will be detected 4009 * as a CRC error and be dropped rather than show up as a bad packet 4010 * to the DMA engine 4011 */ 4012 if (sc->sc_type == WM_T_PCH) 4013 CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565); 4014 4015 if (sc->sc_type >= WM_T_82544) 4016 CSR_WRITE(sc, WMREG_WUC, 0); 4017 4018 wm_reset_mdicnfg_82580(sc); 4019 4020 if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) 4021 wm_pll_workaround_i210(sc); 4022 } 4023 4024 /* 4025 * wm_add_rxbuf: 4026 * 4027 * Add a receive buffer to the indiciated descriptor. 4028 */ 4029 static int 4030 wm_add_rxbuf(struct wm_rxqueue *rxq, int idx) 4031 { 4032 struct wm_softc *sc = rxq->rxq_sc; 4033 struct wm_rxsoft *rxs = &rxq->rxq_soft[idx]; 4034 struct mbuf *m; 4035 int error; 4036 4037 KASSERT(WM_RX_LOCKED(rxq)); 4038 4039 MGETHDR(m, M_DONTWAIT, MT_DATA); 4040 if (m == NULL) 4041 return ENOBUFS; 4042 4043 MCLGET(m, M_DONTWAIT); 4044 if ((m->m_flags & M_EXT) == 0) { 4045 m_freem(m); 4046 return ENOBUFS; 4047 } 4048 4049 if (rxs->rxs_mbuf != NULL) 4050 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 4051 4052 rxs->rxs_mbuf = m; 4053 4054 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 4055 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 4056 BUS_DMA_READ | BUS_DMA_NOWAIT); 4057 if (error) { 4058 /* XXX XXX XXX */ 4059 aprint_error_dev(sc->sc_dev, 4060 "unable to load rx DMA map %d, error = %d\n", 4061 idx, error); 4062 panic("wm_add_rxbuf"); 4063 } 4064 4065 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 4066 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 4067 4068 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 4069 if ((sc->sc_rctl & RCTL_EN) != 0) 4070 wm_init_rxdesc(rxq, idx); 4071 } else 4072 wm_init_rxdesc(rxq, idx); 4073 4074 return 0; 4075 } 4076 4077 /* 4078 * wm_rxdrain: 4079 * 4080 * Drain the receive queue. 4081 */ 4082 static void 4083 wm_rxdrain(struct wm_rxqueue *rxq) 4084 { 4085 struct wm_softc *sc = rxq->rxq_sc; 4086 struct wm_rxsoft *rxs; 4087 int i; 4088 4089 KASSERT(WM_RX_LOCKED(rxq)); 4090 4091 for (i = 0; i < WM_NRXDESC; i++) { 4092 rxs = &rxq->rxq_soft[i]; 4093 if (rxs->rxs_mbuf != NULL) { 4094 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 4095 m_freem(rxs->rxs_mbuf); 4096 rxs->rxs_mbuf = NULL; 4097 } 4098 } 4099 } 4100 4101 4102 /* 4103 * XXX copy from FreeBSD's sys/net/rss_config.c 4104 */ 4105 /* 4106 * RSS secret key, intended to prevent attacks on load-balancing. Its 4107 * effectiveness may be limited by algorithm choice and available entropy 4108 * during the boot. 4109 * 4110 * XXXRW: And that we don't randomize it yet! 4111 * 4112 * This is the default Microsoft RSS specification key which is also 4113 * the Chelsio T5 firmware default key. 4114 */ 4115 #define RSS_KEYSIZE 40 4116 static uint8_t wm_rss_key[RSS_KEYSIZE] = { 4117 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 4118 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 4119 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4, 4120 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c, 4121 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa, 4122 }; 4123 4124 /* 4125 * Caller must pass an array of size sizeof(rss_key). 4126 * 4127 * XXX 4128 * As if_ixgbe may use this function, this function should not be 4129 * if_wm specific function. 4130 */ 4131 static void 4132 wm_rss_getkey(uint8_t *key) 4133 { 4134 4135 memcpy(key, wm_rss_key, sizeof(wm_rss_key)); 4136 } 4137 4138 /* 4139 * Setup registers for RSS. 4140 * 4141 * XXX not yet VMDq support 4142 */ 4143 static void 4144 wm_init_rss(struct wm_softc *sc) 4145 { 4146 uint32_t mrqc, reta_reg, rss_key[RSSRK_NUM_REGS]; 4147 int i; 4148 4149 CTASSERT(sizeof(rss_key) == sizeof(wm_rss_key)); 4150 4151 for (i = 0; i < RETA_NUM_ENTRIES; i++) { 4152 int qid, reta_ent; 4153 4154 qid = i % sc->sc_nrxqueues; 4155 switch(sc->sc_type) { 4156 case WM_T_82574: 4157 reta_ent = __SHIFTIN(qid, 4158 RETA_ENT_QINDEX_MASK_82574); 4159 break; 4160 case WM_T_82575: 4161 reta_ent = __SHIFTIN(qid, 4162 RETA_ENT_QINDEX1_MASK_82575); 4163 break; 4164 default: 4165 reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK); 4166 break; 4167 } 4168 4169 reta_reg = CSR_READ(sc, WMREG_RETA_Q(i)); 4170 reta_reg &= ~RETA_ENTRY_MASK_Q(i); 4171 reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i)); 4172 CSR_WRITE(sc, WMREG_RETA_Q(i), reta_reg); 4173 } 4174 4175 wm_rss_getkey((uint8_t *)rss_key); 4176 for (i = 0; i < RSSRK_NUM_REGS; i++) 4177 CSR_WRITE(sc, WMREG_RSSRK(i), rss_key[i]); 4178 4179 if (sc->sc_type == WM_T_82574) 4180 mrqc = MRQC_ENABLE_RSS_MQ_82574; 4181 else 4182 mrqc = MRQC_ENABLE_RSS_MQ; 4183 4184 /* XXXX 4185 * The same as FreeBSD igb. 4186 * Why doesn't use MRQC_RSS_FIELD_IPV6_EX? 4187 */ 4188 mrqc |= (MRQC_RSS_FIELD_IPV4 | MRQC_RSS_FIELD_IPV4_TCP); 4189 mrqc |= (MRQC_RSS_FIELD_IPV6 | MRQC_RSS_FIELD_IPV6_TCP); 4190 mrqc |= (MRQC_RSS_FIELD_IPV4_UDP | MRQC_RSS_FIELD_IPV6_UDP); 4191 mrqc |= (MRQC_RSS_FIELD_IPV6_UDP_EX | MRQC_RSS_FIELD_IPV6_TCP_EX); 4192 4193 CSR_WRITE(sc, WMREG_MRQC, mrqc); 4194 } 4195 4196 /* 4197 * Adjust TX and RX queue numbers which the system actulally uses. 4198 * 4199 * The numbers are affected by below parameters. 4200 * - The nubmer of hardware queues 4201 * - The number of MSI-X vectors (= "nvectors" argument) 4202 * - ncpu 4203 */ 4204 static void 4205 wm_adjust_qnum(struct wm_softc *sc, int nvectors) 4206 { 4207 int hw_ntxqueues, hw_nrxqueues; 4208 4209 if (nvectors < 3) { 4210 sc->sc_ntxqueues = 1; 4211 sc->sc_nrxqueues = 1; 4212 return; 4213 } 4214 4215 switch(sc->sc_type) { 4216 case WM_T_82572: 4217 hw_ntxqueues = 2; 4218 hw_nrxqueues = 2; 4219 break; 4220 case WM_T_82574: 4221 hw_ntxqueues = 2; 4222 hw_nrxqueues = 2; 4223 break; 4224 case WM_T_82575: 4225 hw_ntxqueues = 4; 4226 hw_nrxqueues = 4; 4227 break; 4228 case WM_T_82576: 4229 hw_ntxqueues = 16; 4230 hw_nrxqueues = 16; 4231 break; 4232 case WM_T_82580: 4233 case WM_T_I350: 4234 case WM_T_I354: 4235 hw_ntxqueues = 8; 4236 hw_nrxqueues = 8; 4237 break; 4238 case WM_T_I210: 4239 hw_ntxqueues = 4; 4240 hw_nrxqueues = 4; 4241 break; 4242 case WM_T_I211: 4243 hw_ntxqueues = 2; 4244 hw_nrxqueues = 2; 4245 break; 4246 /* 4247 * As below ethernet controllers does not support MSI-X, 4248 * this driver let them not use multiqueue. 4249 * - WM_T_80003 4250 * - WM_T_ICH8 4251 * - WM_T_ICH9 4252 * - WM_T_ICH10 4253 * - WM_T_PCH 4254 * - WM_T_PCH2 4255 * - WM_T_PCH_LPT 4256 */ 4257 default: 4258 hw_ntxqueues = 1; 4259 hw_nrxqueues = 1; 4260 break; 4261 } 4262 4263 /* 4264 * As queues more then MSI-X vectors cannot improve scaling, we limit 4265 * the number of queues used actually. 4266 * 4267 * XXX 4268 * Currently, we separate TX queue interrupts and RX queue interrupts. 4269 * Howerver, the number of MSI-X vectors of recent controllers (such as 4270 * I354) expects that drivers bundle a TX queue interrupt and a RX 4271 * interrupt to one interrupt. e.g. FreeBSD's igb deals interrupts in 4272 * such a way. 4273 */ 4274 if (nvectors < hw_ntxqueues + hw_nrxqueues + 1) { 4275 sc->sc_ntxqueues = (nvectors - 1) / 2; 4276 sc->sc_nrxqueues = (nvectors - 1) / 2; 4277 } else { 4278 sc->sc_ntxqueues = hw_ntxqueues; 4279 sc->sc_nrxqueues = hw_nrxqueues; 4280 } 4281 4282 /* 4283 * As queues more then cpus cannot improve scaling, we limit 4284 * the number of queues used actually. 4285 */ 4286 if (ncpu < sc->sc_ntxqueues) 4287 sc->sc_ntxqueues = ncpu; 4288 if (ncpu < sc->sc_nrxqueues) 4289 sc->sc_nrxqueues = ncpu; 4290 4291 /* XXX Currently, this driver supports RX multiqueue only. */ 4292 sc->sc_ntxqueues = 1; 4293 } 4294 4295 /* 4296 * Both single interrupt MSI and INTx can use this function. 4297 */ 4298 static int 4299 wm_setup_legacy(struct wm_softc *sc) 4300 { 4301 pci_chipset_tag_t pc = sc->sc_pc; 4302 const char *intrstr = NULL; 4303 char intrbuf[PCI_INTRSTR_LEN]; 4304 int error; 4305 4306 error = wm_alloc_txrx_queues(sc); 4307 if (error) { 4308 aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n", 4309 error); 4310 return ENOMEM; 4311 } 4312 intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf, 4313 sizeof(intrbuf)); 4314 #ifdef WM_MPSAFE 4315 pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true); 4316 #endif 4317 sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0], 4318 IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev)); 4319 if (sc->sc_ihs[0] == NULL) { 4320 aprint_error_dev(sc->sc_dev,"unable to establish %s\n", 4321 (pci_intr_type(sc->sc_intrs[0]) 4322 == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 4323 return ENOMEM; 4324 } 4325 4326 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 4327 sc->sc_nintrs = 1; 4328 return 0; 4329 } 4330 4331 static int 4332 wm_setup_msix(struct wm_softc *sc) 4333 { 4334 void *vih; 4335 kcpuset_t *affinity; 4336 int qidx, error, intr_idx, tx_established, rx_established; 4337 pci_chipset_tag_t pc = sc->sc_pc; 4338 const char *intrstr = NULL; 4339 char intrbuf[PCI_INTRSTR_LEN]; 4340 char intr_xname[INTRDEVNAMEBUF]; 4341 /* 4342 * To avoid other devices' interrupts, the affinity of Tx/Rx interrupts 4343 * start from CPU#1. 4344 */ 4345 int affinity_offset = 1; 4346 4347 error = wm_alloc_txrx_queues(sc); 4348 if (error) { 4349 aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n", 4350 error); 4351 return ENOMEM; 4352 } 4353 4354 kcpuset_create(&affinity, false); 4355 intr_idx = 0; 4356 4357 /* 4358 * TX 4359 */ 4360 tx_established = 0; 4361 for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) { 4362 struct wm_txqueue *txq = &sc->sc_txq[qidx]; 4363 int affinity_to = (affinity_offset + intr_idx) % ncpu; 4364 4365 intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf, 4366 sizeof(intrbuf)); 4367 #ifdef WM_MPSAFE 4368 pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], 4369 PCI_INTR_MPSAFE, true); 4370 #endif 4371 memset(intr_xname, 0, sizeof(intr_xname)); 4372 snprintf(intr_xname, sizeof(intr_xname), "%sTX%d", 4373 device_xname(sc->sc_dev), qidx); 4374 vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx], 4375 IPL_NET, wm_txintr_msix, txq, intr_xname); 4376 if (vih == NULL) { 4377 aprint_error_dev(sc->sc_dev, 4378 "unable to establish MSI-X(for TX)%s%s\n", 4379 intrstr ? " at " : "", 4380 intrstr ? intrstr : ""); 4381 4382 goto fail_0; 4383 } 4384 kcpuset_zero(affinity); 4385 /* Round-robin affinity */ 4386 kcpuset_set(affinity, affinity_to); 4387 error = interrupt_distribute(vih, affinity, NULL); 4388 if (error == 0) { 4389 aprint_normal_dev(sc->sc_dev, 4390 "for TX interrupting at %s affinity to %u\n", 4391 intrstr, affinity_to); 4392 } else { 4393 aprint_normal_dev(sc->sc_dev, 4394 "for TX interrupting at %s\n", intrstr); 4395 } 4396 sc->sc_ihs[intr_idx] = vih; 4397 txq->txq_id = qidx; 4398 txq->txq_intr_idx = intr_idx; 4399 4400 tx_established++; 4401 intr_idx++; 4402 } 4403 4404 /* 4405 * RX 4406 */ 4407 rx_established = 0; 4408 for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) { 4409 struct wm_rxqueue *rxq = &sc->sc_rxq[qidx]; 4410 int affinity_to = (affinity_offset + intr_idx) % ncpu; 4411 4412 intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf, 4413 sizeof(intrbuf)); 4414 #ifdef WM_MPSAFE 4415 pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], 4416 PCI_INTR_MPSAFE, true); 4417 #endif 4418 memset(intr_xname, 0, sizeof(intr_xname)); 4419 snprintf(intr_xname, sizeof(intr_xname), "%sRX%d", 4420 device_xname(sc->sc_dev), qidx); 4421 vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx], 4422 IPL_NET, wm_rxintr_msix, rxq, intr_xname); 4423 if (vih == NULL) { 4424 aprint_error_dev(sc->sc_dev, 4425 "unable to establish MSI-X(for RX)%s%s\n", 4426 intrstr ? " at " : "", 4427 intrstr ? intrstr : ""); 4428 4429 goto fail_1; 4430 } 4431 kcpuset_zero(affinity); 4432 /* Round-robin affinity */ 4433 kcpuset_set(affinity, affinity_to); 4434 error = interrupt_distribute(vih, affinity, NULL); 4435 if (error == 0) { 4436 aprint_normal_dev(sc->sc_dev, 4437 "for RX interrupting at %s affinity to %u\n", 4438 intrstr, affinity_to); 4439 } else { 4440 aprint_normal_dev(sc->sc_dev, 4441 "for RX interrupting at %s\n", intrstr); 4442 } 4443 sc->sc_ihs[intr_idx] = vih; 4444 rxq->rxq_id = qidx; 4445 rxq->rxq_intr_idx = intr_idx; 4446 4447 rx_established++; 4448 intr_idx++; 4449 } 4450 4451 /* 4452 * LINK 4453 */ 4454 intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf, 4455 sizeof(intrbuf)); 4456 #ifdef WM_MPSAFE 4457 pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], PCI_INTR_MPSAFE, true); 4458 #endif 4459 memset(intr_xname, 0, sizeof(intr_xname)); 4460 snprintf(intr_xname, sizeof(intr_xname), "%sLINK", 4461 device_xname(sc->sc_dev)); 4462 vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx], 4463 IPL_NET, wm_linkintr_msix, sc, intr_xname); 4464 if (vih == NULL) { 4465 aprint_error_dev(sc->sc_dev, 4466 "unable to establish MSI-X(for LINK)%s%s\n", 4467 intrstr ? " at " : "", 4468 intrstr ? intrstr : ""); 4469 4470 goto fail_1; 4471 } 4472 /* keep default affinity to LINK interrupt */ 4473 aprint_normal_dev(sc->sc_dev, 4474 "for LINK interrupting at %s\n", intrstr); 4475 sc->sc_ihs[intr_idx] = vih; 4476 sc->sc_link_intr_idx = intr_idx; 4477 4478 sc->sc_nintrs = sc->sc_ntxqueues + sc->sc_nrxqueues + 1; 4479 kcpuset_destroy(affinity); 4480 return 0; 4481 4482 fail_1: 4483 for (qidx = 0; qidx < rx_established; qidx++) { 4484 struct wm_rxqueue *rxq = &sc->sc_rxq[qidx]; 4485 pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[rxq->rxq_intr_idx]); 4486 sc->sc_ihs[rxq->rxq_intr_idx] = NULL; 4487 } 4488 fail_0: 4489 for (qidx = 0; qidx < tx_established; qidx++) { 4490 struct wm_txqueue *txq = &sc->sc_txq[qidx]; 4491 pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[txq->txq_intr_idx]); 4492 sc->sc_ihs[txq->txq_intr_idx] = NULL; 4493 } 4494 4495 kcpuset_destroy(affinity); 4496 return ENOMEM; 4497 } 4498 4499 /* 4500 * wm_init: [ifnet interface function] 4501 * 4502 * Initialize the interface. 4503 */ 4504 static int 4505 wm_init(struct ifnet *ifp) 4506 { 4507 struct wm_softc *sc = ifp->if_softc; 4508 int ret; 4509 4510 WM_CORE_LOCK(sc); 4511 ret = wm_init_locked(ifp); 4512 WM_CORE_UNLOCK(sc); 4513 4514 return ret; 4515 } 4516 4517 static int 4518 wm_init_locked(struct ifnet *ifp) 4519 { 4520 struct wm_softc *sc = ifp->if_softc; 4521 int i, j, trynum, error = 0; 4522 uint32_t reg; 4523 4524 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 4525 device_xname(sc->sc_dev), __func__)); 4526 KASSERT(WM_CORE_LOCKED(sc)); 4527 /* 4528 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 4529 * There is a small but measurable benefit to avoiding the adjusment 4530 * of the descriptor so that the headers are aligned, for normal mtu, 4531 * on such platforms. One possibility is that the DMA itself is 4532 * slightly more efficient if the front of the entire packet (instead 4533 * of the front of the headers) is aligned. 4534 * 4535 * Note we must always set align_tweak to 0 if we are using 4536 * jumbo frames. 4537 */ 4538 #ifdef __NO_STRICT_ALIGNMENT 4539 sc->sc_align_tweak = 0; 4540 #else 4541 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 4542 sc->sc_align_tweak = 0; 4543 else 4544 sc->sc_align_tweak = 2; 4545 #endif /* __NO_STRICT_ALIGNMENT */ 4546 4547 /* Cancel any pending I/O. */ 4548 wm_stop_locked(ifp, 0); 4549 4550 /* update statistics before reset */ 4551 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 4552 ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); 4553 4554 /* Reset the chip to a known state. */ 4555 wm_reset(sc); 4556 4557 switch (sc->sc_type) { 4558 case WM_T_82571: 4559 case WM_T_82572: 4560 case WM_T_82573: 4561 case WM_T_82574: 4562 case WM_T_82583: 4563 case WM_T_80003: 4564 case WM_T_ICH8: 4565 case WM_T_ICH9: 4566 case WM_T_ICH10: 4567 case WM_T_PCH: 4568 case WM_T_PCH2: 4569 case WM_T_PCH_LPT: 4570 case WM_T_PCH_SPT: 4571 /* AMT based hardware can now take control from firmware */ 4572 if ((sc->sc_flags & WM_F_HAS_AMT) != 0) 4573 wm_get_hw_control(sc); 4574 break; 4575 default: 4576 break; 4577 } 4578 4579 /* Init hardware bits */ 4580 wm_initialize_hardware_bits(sc); 4581 4582 /* Reset the PHY. */ 4583 if (sc->sc_flags & WM_F_HAS_MII) 4584 wm_gmii_reset(sc); 4585 4586 /* Calculate (E)ITR value */ 4587 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 4588 sc->sc_itr = 450; /* For EITR */ 4589 } else if (sc->sc_type >= WM_T_82543) { 4590 /* 4591 * Set up the interrupt throttling register (units of 256ns) 4592 * Note that a footnote in Intel's documentation says this 4593 * ticker runs at 1/4 the rate when the chip is in 100Mbit 4594 * or 10Mbit mode. Empirically, it appears to be the case 4595 * that that is also true for the 1024ns units of the other 4596 * interrupt-related timer registers -- so, really, we ought 4597 * to divide this value by 4 when the link speed is low. 4598 * 4599 * XXX implement this division at link speed change! 4600 */ 4601 4602 /* 4603 * For N interrupts/sec, set this value to: 4604 * 1000000000 / (N * 256). Note that we set the 4605 * absolute and packet timer values to this value 4606 * divided by 4 to get "simple timer" behavior. 4607 */ 4608 4609 sc->sc_itr = 1500; /* 2604 ints/sec */ 4610 } 4611 4612 error = wm_init_txrx_queues(sc); 4613 if (error) 4614 goto out; 4615 4616 /* 4617 * Clear out the VLAN table -- we don't use it (yet). 4618 */ 4619 CSR_WRITE(sc, WMREG_VET, 0); 4620 if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) 4621 trynum = 10; /* Due to hw errata */ 4622 else 4623 trynum = 1; 4624 for (i = 0; i < WM_VLAN_TABSIZE; i++) 4625 for (j = 0; j < trynum; j++) 4626 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 4627 4628 /* 4629 * Set up flow-control parameters. 4630 * 4631 * XXX Values could probably stand some tuning. 4632 */ 4633 if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) 4634 && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH) 4635 && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT) 4636 && (sc->sc_type != WM_T_PCH_SPT)) { 4637 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 4638 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 4639 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 4640 } 4641 4642 sc->sc_fcrtl = FCRTL_DFLT; 4643 if (sc->sc_type < WM_T_82543) { 4644 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 4645 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 4646 } else { 4647 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 4648 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 4649 } 4650 4651 if (sc->sc_type == WM_T_80003) 4652 CSR_WRITE(sc, WMREG_FCTTV, 0xffff); 4653 else 4654 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 4655 4656 /* Writes the control register. */ 4657 wm_set_vlan(sc); 4658 4659 if (sc->sc_flags & WM_F_HAS_MII) { 4660 int val; 4661 4662 switch (sc->sc_type) { 4663 case WM_T_80003: 4664 case WM_T_ICH8: 4665 case WM_T_ICH9: 4666 case WM_T_ICH10: 4667 case WM_T_PCH: 4668 case WM_T_PCH2: 4669 case WM_T_PCH_LPT: 4670 case WM_T_PCH_SPT: 4671 /* 4672 * Set the mac to wait the maximum time between each 4673 * iteration and increase the max iterations when 4674 * polling the phy; this fixes erroneous timeouts at 4675 * 10Mbps. 4676 */ 4677 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS, 4678 0xFFFF); 4679 val = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM); 4680 val |= 0x3F; 4681 wm_kmrn_writereg(sc, 4682 KUMCTRLSTA_OFFSET_INB_PARAM, val); 4683 break; 4684 default: 4685 break; 4686 } 4687 4688 if (sc->sc_type == WM_T_80003) { 4689 val = CSR_READ(sc, WMREG_CTRL_EXT); 4690 val &= ~CTRL_EXT_LINK_MODE_MASK; 4691 CSR_WRITE(sc, WMREG_CTRL_EXT, val); 4692 4693 /* Bypass RX and TX FIFO's */ 4694 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL, 4695 KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 4696 | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 4697 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL, 4698 KUMCTRLSTA_INB_CTRL_DIS_PADDING | 4699 KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT); 4700 } 4701 } 4702 #if 0 4703 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 4704 #endif 4705 4706 /* Set up checksum offload parameters. */ 4707 reg = CSR_READ(sc, WMREG_RXCSUM); 4708 reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL); 4709 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 4710 reg |= RXCSUM_IPOFL; 4711 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 4712 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 4713 if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) 4714 reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL; 4715 CSR_WRITE(sc, WMREG_RXCSUM, reg); 4716 4717 /* Set up MSI-X */ 4718 if (sc->sc_nintrs > 1) { 4719 uint32_t ivar; 4720 struct wm_txqueue *txq; 4721 struct wm_rxqueue *rxq; 4722 int qid; 4723 4724 if (sc->sc_type == WM_T_82575) { 4725 /* Interrupt control */ 4726 reg = CSR_READ(sc, WMREG_CTRL_EXT); 4727 reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR; 4728 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 4729 4730 /* TX */ 4731 for (i = 0; i < sc->sc_ntxqueues; i++) { 4732 txq = &sc->sc_txq[i]; 4733 CSR_WRITE(sc, WMREG_MSIXBM(txq->txq_intr_idx), 4734 EITR_TX_QUEUE(txq->txq_id)); 4735 } 4736 /* RX */ 4737 for (i = 0; i < sc->sc_nrxqueues; i++) { 4738 rxq = &sc->sc_rxq[i]; 4739 CSR_WRITE(sc, WMREG_MSIXBM(rxq->rxq_intr_idx), 4740 EITR_RX_QUEUE(rxq->rxq_id)); 4741 } 4742 /* Link status */ 4743 CSR_WRITE(sc, WMREG_MSIXBM(sc->sc_link_intr_idx), 4744 EITR_OTHER); 4745 } else if (sc->sc_type == WM_T_82574) { 4746 /* Interrupt control */ 4747 reg = CSR_READ(sc, WMREG_CTRL_EXT); 4748 reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME; 4749 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 4750 4751 ivar = 0; 4752 /* TX */ 4753 for (i = 0; i < sc->sc_ntxqueues; i++) { 4754 txq = &sc->sc_txq[i]; 4755 ivar |= __SHIFTIN((IVAR_VALID_82574 4756 | txq->txq_intr_idx), 4757 IVAR_TX_MASK_Q_82574(txq->txq_id)); 4758 } 4759 /* RX */ 4760 for (i = 0; i < sc->sc_nrxqueues; i++) { 4761 rxq = &sc->sc_rxq[i]; 4762 ivar |= __SHIFTIN((IVAR_VALID_82574 4763 | rxq->rxq_intr_idx), 4764 IVAR_RX_MASK_Q_82574(rxq->rxq_id)); 4765 } 4766 /* Link status */ 4767 ivar |= __SHIFTIN((IVAR_VALID_82574 4768 | sc->sc_link_intr_idx), IVAR_OTHER_MASK); 4769 CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB); 4770 } else { 4771 /* Interrupt control */ 4772 CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | GPIE_MULTI_MSIX 4773 | GPIE_EIAME | GPIE_PBA); 4774 4775 switch (sc->sc_type) { 4776 case WM_T_82580: 4777 case WM_T_I350: 4778 case WM_T_I354: 4779 case WM_T_I210: 4780 case WM_T_I211: 4781 /* TX */ 4782 for (i = 0; i < sc->sc_ntxqueues; i++) { 4783 txq = &sc->sc_txq[i]; 4784 qid = txq->txq_id; 4785 ivar = CSR_READ(sc, WMREG_IVAR_Q(qid)); 4786 ivar &= ~IVAR_TX_MASK_Q(qid); 4787 ivar |= __SHIFTIN((txq->txq_intr_idx 4788 | IVAR_VALID), 4789 IVAR_TX_MASK_Q(qid)); 4790 CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar); 4791 } 4792 4793 /* RX */ 4794 for (i = 0; i < sc->sc_nrxqueues; i++) { 4795 rxq = &sc->sc_rxq[i]; 4796 qid = rxq->rxq_id; 4797 ivar = CSR_READ(sc, WMREG_IVAR_Q(qid)); 4798 ivar &= ~IVAR_RX_MASK_Q(qid); 4799 ivar |= __SHIFTIN((rxq->rxq_intr_idx 4800 | IVAR_VALID), 4801 IVAR_RX_MASK_Q(qid)); 4802 CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar); 4803 } 4804 break; 4805 case WM_T_82576: 4806 /* TX */ 4807 for (i = 0; i < sc->sc_ntxqueues; i++) { 4808 txq = &sc->sc_txq[i]; 4809 qid = txq->txq_id; 4810 ivar = CSR_READ(sc, 4811 WMREG_IVAR_Q_82576(qid)); 4812 ivar &= ~IVAR_TX_MASK_Q_82576(qid); 4813 ivar |= __SHIFTIN((txq->txq_intr_idx 4814 | IVAR_VALID), 4815 IVAR_TX_MASK_Q_82576(qid)); 4816 CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid), 4817 ivar); 4818 } 4819 4820 /* RX */ 4821 for (i = 0; i < sc->sc_nrxqueues; i++) { 4822 rxq = &sc->sc_rxq[i]; 4823 qid = rxq->rxq_id; 4824 ivar = CSR_READ(sc, 4825 WMREG_IVAR_Q_82576(qid)); 4826 ivar &= ~IVAR_RX_MASK_Q_82576(qid); 4827 ivar |= __SHIFTIN((rxq->rxq_intr_idx 4828 | IVAR_VALID), 4829 IVAR_RX_MASK_Q_82576(qid)); 4830 CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid), 4831 ivar); 4832 } 4833 break; 4834 default: 4835 break; 4836 } 4837 4838 /* Link status */ 4839 ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID), 4840 IVAR_MISC_OTHER); 4841 CSR_WRITE(sc, WMREG_IVAR_MISC, ivar); 4842 } 4843 4844 if (sc->sc_nrxqueues > 1) { 4845 wm_init_rss(sc); 4846 4847 /* 4848 ** NOTE: Receive Full-Packet Checksum Offload 4849 ** is mutually exclusive with Multiqueue. However 4850 ** this is not the same as TCP/IP checksums which 4851 ** still work. 4852 */ 4853 reg = CSR_READ(sc, WMREG_RXCSUM); 4854 reg |= RXCSUM_PCSD; 4855 CSR_WRITE(sc, WMREG_RXCSUM, reg); 4856 } 4857 } 4858 4859 /* Set up the interrupt registers. */ 4860 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 4861 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 4862 ICR_RXO | ICR_RXT0; 4863 if (sc->sc_nintrs > 1) { 4864 uint32_t mask; 4865 struct wm_txqueue *txq; 4866 struct wm_rxqueue *rxq; 4867 4868 switch (sc->sc_type) { 4869 case WM_T_82574: 4870 CSR_WRITE(sc, WMREG_EIAC_82574, 4871 WMREG_EIAC_82574_MSIX_MASK); 4872 sc->sc_icr |= WMREG_EIAC_82574_MSIX_MASK; 4873 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 4874 break; 4875 default: 4876 if (sc->sc_type == WM_T_82575) { 4877 mask = 0; 4878 for (i = 0; i < sc->sc_ntxqueues; i++) { 4879 txq = &sc->sc_txq[i]; 4880 mask |= EITR_TX_QUEUE(txq->txq_id); 4881 } 4882 for (i = 0; i < sc->sc_nrxqueues; i++) { 4883 rxq = &sc->sc_rxq[i]; 4884 mask |= EITR_RX_QUEUE(rxq->rxq_id); 4885 } 4886 mask |= EITR_OTHER; 4887 } else { 4888 mask = 0; 4889 for (i = 0; i < sc->sc_ntxqueues; i++) { 4890 txq = &sc->sc_txq[i]; 4891 mask |= 1 << txq->txq_intr_idx; 4892 } 4893 for (i = 0; i < sc->sc_nrxqueues; i++) { 4894 rxq = &sc->sc_rxq[i]; 4895 mask |= 1 << rxq->rxq_intr_idx; 4896 } 4897 mask |= 1 << sc->sc_link_intr_idx; 4898 } 4899 CSR_WRITE(sc, WMREG_EIAC, mask); 4900 CSR_WRITE(sc, WMREG_EIAM, mask); 4901 CSR_WRITE(sc, WMREG_EIMS, mask); 4902 CSR_WRITE(sc, WMREG_IMS, ICR_LSC); 4903 break; 4904 } 4905 } else 4906 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 4907 4908 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 4909 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 4910 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT) 4911 || (sc->sc_type == WM_T_PCH_SPT)) { 4912 reg = CSR_READ(sc, WMREG_KABGTXD); 4913 reg |= KABGTXD_BGSQLBIAS; 4914 CSR_WRITE(sc, WMREG_KABGTXD, reg); 4915 } 4916 4917 /* Set up the inter-packet gap. */ 4918 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 4919 4920 if (sc->sc_type >= WM_T_82543) { 4921 /* 4922 * XXX 82574 has both ITR and EITR. SET EITR when we use 4923 * the multi queue function with MSI-X. 4924 */ 4925 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 4926 int qidx; 4927 for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) { 4928 struct wm_txqueue *txq = &sc->sc_txq[qidx]; 4929 CSR_WRITE(sc, WMREG_EITR(txq->txq_intr_idx), 4930 sc->sc_itr); 4931 } 4932 for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) { 4933 struct wm_rxqueue *rxq = &sc->sc_rxq[qidx]; 4934 CSR_WRITE(sc, WMREG_EITR(rxq->rxq_intr_idx), 4935 sc->sc_itr); 4936 } 4937 /* 4938 * Link interrupts occur much less than TX 4939 * interrupts and RX interrupts. So, we don't 4940 * tune EINTR(WM_MSIX_LINKINTR_IDX) value like 4941 * FreeBSD's if_igb. 4942 */ 4943 } else 4944 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 4945 } 4946 4947 /* Set the VLAN ethernetype. */ 4948 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 4949 4950 /* 4951 * Set up the transmit control register; we start out with 4952 * a collision distance suitable for FDX, but update it whe 4953 * we resolve the media type. 4954 */ 4955 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC 4956 | TCTL_CT(TX_COLLISION_THRESHOLD) 4957 | TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4958 if (sc->sc_type >= WM_T_82571) 4959 sc->sc_tctl |= TCTL_MULR; 4960 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4961 4962 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 4963 /* Write TDT after TCTL.EN is set. See the document. */ 4964 CSR_WRITE(sc, WMREG_TDT(0), 0); 4965 } 4966 4967 if (sc->sc_type == WM_T_80003) { 4968 reg = CSR_READ(sc, WMREG_TCTL_EXT); 4969 reg &= ~TCTL_EXT_GCEX_MASK; 4970 reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 4971 CSR_WRITE(sc, WMREG_TCTL_EXT, reg); 4972 } 4973 4974 /* Set the media. */ 4975 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 4976 goto out; 4977 4978 /* Configure for OS presence */ 4979 wm_init_manageability(sc); 4980 4981 /* 4982 * Set up the receive control register; we actually program 4983 * the register when we set the receive filter. Use multicast 4984 * address offset type 0. 4985 * 4986 * Only the i82544 has the ability to strip the incoming 4987 * CRC, so we don't enable that feature. 4988 */ 4989 sc->sc_mchash_type = 0; 4990 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF 4991 | RCTL_MO(sc->sc_mchash_type); 4992 4993 /* 4994 * The I350 has a bug where it always strips the CRC whether 4995 * asked to or not. So ask for stripped CRC here and cope in rxeof 4996 */ 4997 if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) 4998 || (sc->sc_type == WM_T_I210)) 4999 sc->sc_rctl |= RCTL_SECRC; 5000 5001 if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0) 5002 && (ifp->if_mtu > ETHERMTU)) { 5003 sc->sc_rctl |= RCTL_LPE; 5004 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) 5005 CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO); 5006 } 5007 5008 if (MCLBYTES == 2048) { 5009 sc->sc_rctl |= RCTL_2k; 5010 } else { 5011 if (sc->sc_type >= WM_T_82543) { 5012 switch (MCLBYTES) { 5013 case 4096: 5014 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 5015 break; 5016 case 8192: 5017 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 5018 break; 5019 case 16384: 5020 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 5021 break; 5022 default: 5023 panic("wm_init: MCLBYTES %d unsupported", 5024 MCLBYTES); 5025 break; 5026 } 5027 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 5028 } 5029 5030 /* Set the receive filter. */ 5031 wm_set_filter(sc); 5032 5033 /* Enable ECC */ 5034 switch (sc->sc_type) { 5035 case WM_T_82571: 5036 reg = CSR_READ(sc, WMREG_PBA_ECC); 5037 reg |= PBA_ECC_CORR_EN; 5038 CSR_WRITE(sc, WMREG_PBA_ECC, reg); 5039 break; 5040 case WM_T_PCH_LPT: 5041 case WM_T_PCH_SPT: 5042 reg = CSR_READ(sc, WMREG_PBECCSTS); 5043 reg |= PBECCSTS_UNCORR_ECC_ENABLE; 5044 CSR_WRITE(sc, WMREG_PBECCSTS, reg); 5045 5046 reg = CSR_READ(sc, WMREG_CTRL); 5047 reg |= CTRL_MEHE; 5048 CSR_WRITE(sc, WMREG_CTRL, reg); 5049 break; 5050 default: 5051 break; 5052 } 5053 5054 /* On 575 and later set RDT only if RX enabled */ 5055 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 5056 int qidx; 5057 for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) { 5058 struct wm_rxqueue *rxq = &sc->sc_rxq[qidx]; 5059 for (i = 0; i < WM_NRXDESC; i++) { 5060 WM_RX_LOCK(rxq); 5061 wm_init_rxdesc(rxq, i); 5062 WM_RX_UNLOCK(rxq); 5063 5064 } 5065 } 5066 } 5067 5068 sc->sc_stopping = false; 5069 5070 /* Start the one second link check clock. */ 5071 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 5072 5073 /* ...all done! */ 5074 ifp->if_flags |= IFF_RUNNING; 5075 ifp->if_flags &= ~IFF_OACTIVE; 5076 5077 out: 5078 sc->sc_if_flags = ifp->if_flags; 5079 if (error) 5080 log(LOG_ERR, "%s: interface not running\n", 5081 device_xname(sc->sc_dev)); 5082 return error; 5083 } 5084 5085 /* 5086 * wm_stop: [ifnet interface function] 5087 * 5088 * Stop transmission on the interface. 5089 */ 5090 static void 5091 wm_stop(struct ifnet *ifp, int disable) 5092 { 5093 struct wm_softc *sc = ifp->if_softc; 5094 5095 WM_CORE_LOCK(sc); 5096 wm_stop_locked(ifp, disable); 5097 WM_CORE_UNLOCK(sc); 5098 } 5099 5100 static void 5101 wm_stop_locked(struct ifnet *ifp, int disable) 5102 { 5103 struct wm_softc *sc = ifp->if_softc; 5104 struct wm_txsoft *txs; 5105 int i, qidx; 5106 5107 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 5108 device_xname(sc->sc_dev), __func__)); 5109 KASSERT(WM_CORE_LOCKED(sc)); 5110 5111 sc->sc_stopping = true; 5112 5113 /* Stop the one second clock. */ 5114 callout_stop(&sc->sc_tick_ch); 5115 5116 /* Stop the 82547 Tx FIFO stall check timer. */ 5117 if (sc->sc_type == WM_T_82547) 5118 callout_stop(&sc->sc_txfifo_ch); 5119 5120 if (sc->sc_flags & WM_F_HAS_MII) { 5121 /* Down the MII. */ 5122 mii_down(&sc->sc_mii); 5123 } else { 5124 #if 0 5125 /* Should we clear PHY's status properly? */ 5126 wm_reset(sc); 5127 #endif 5128 } 5129 5130 /* Stop the transmit and receive processes. */ 5131 CSR_WRITE(sc, WMREG_TCTL, 0); 5132 CSR_WRITE(sc, WMREG_RCTL, 0); 5133 sc->sc_rctl &= ~RCTL_EN; 5134 5135 /* 5136 * Clear the interrupt mask to ensure the device cannot assert its 5137 * interrupt line. 5138 * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to 5139 * service any currently pending or shared interrupt. 5140 */ 5141 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 5142 sc->sc_icr = 0; 5143 if (sc->sc_nintrs > 1) { 5144 if (sc->sc_type != WM_T_82574) { 5145 CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); 5146 CSR_WRITE(sc, WMREG_EIAC, 0); 5147 } else 5148 CSR_WRITE(sc, WMREG_EIAC_82574, 0); 5149 } 5150 5151 /* Release any queued transmit buffers. */ 5152 for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) { 5153 struct wm_txqueue *txq = &sc->sc_txq[qidx]; 5154 WM_TX_LOCK(txq); 5155 for (i = 0; i < WM_TXQUEUELEN(txq); i++) { 5156 txs = &txq->txq_soft[i]; 5157 if (txs->txs_mbuf != NULL) { 5158 bus_dmamap_unload(sc->sc_dmat,txs->txs_dmamap); 5159 m_freem(txs->txs_mbuf); 5160 txs->txs_mbuf = NULL; 5161 } 5162 } 5163 if (sc->sc_type == WM_T_PCH_SPT) { 5164 pcireg_t preg; 5165 uint32_t reg; 5166 int nexttx; 5167 5168 /* First, disable MULR fix in FEXTNVM11 */ 5169 reg = CSR_READ(sc, WMREG_FEXTNVM11); 5170 reg |= FEXTNVM11_DIS_MULRFIX; 5171 CSR_WRITE(sc, WMREG_FEXTNVM11, reg); 5172 5173 preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 5174 WM_PCI_DESCRING_STATUS); 5175 if (preg & DESCRING_STATUS_FLUSH_REQ) { 5176 /* TX */ 5177 printf("XXX need TX flush (reg = %08x)\n", 5178 preg); 5179 wm_init_tx_descs(sc, txq); 5180 wm_init_tx_regs(sc, txq); 5181 nexttx = txq->txq_next; 5182 wm_set_dma_addr( 5183 &txq->txq_descs[nexttx].wtx_addr, 5184 WM_CDTXADDR(txq, nexttx)); 5185 txq->txq_descs[nexttx].wtx_cmdlen 5186 = htole32(WTX_CMD_IFCS | 512); 5187 wm_cdtxsync(txq, nexttx, 1, 5188 BUS_DMASYNC_PREREAD |BUS_DMASYNC_PREWRITE); 5189 CSR_WRITE(sc, WMREG_TCTL, TCTL_EN); 5190 CSR_WRITE(sc, WMREG_TDT(0), nexttx); 5191 CSR_WRITE_FLUSH(sc); 5192 delay(250); 5193 CSR_WRITE(sc, WMREG_TCTL, 0); 5194 } 5195 preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 5196 WM_PCI_DESCRING_STATUS); 5197 if (preg & DESCRING_STATUS_FLUSH_REQ) { 5198 /* RX */ 5199 printf("XXX need RX flush\n"); 5200 } 5201 } 5202 WM_TX_UNLOCK(txq); 5203 } 5204 5205 /* Mark the interface as down and cancel the watchdog timer. */ 5206 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5207 ifp->if_timer = 0; 5208 5209 if (disable) { 5210 for (i = 0; i < sc->sc_nrxqueues; i++) { 5211 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5212 WM_RX_LOCK(rxq); 5213 wm_rxdrain(rxq); 5214 WM_RX_UNLOCK(rxq); 5215 } 5216 } 5217 5218 #if 0 /* notyet */ 5219 if (sc->sc_type >= WM_T_82544) 5220 CSR_WRITE(sc, WMREG_WUC, 0); 5221 #endif 5222 } 5223 5224 static void 5225 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 5226 { 5227 struct mbuf *m; 5228 int i; 5229 5230 log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev)); 5231 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 5232 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 5233 "m_flags = 0x%08x\n", device_xname(sc->sc_dev), 5234 m->m_data, m->m_len, m->m_flags); 5235 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev), 5236 i, i == 1 ? "" : "s"); 5237 } 5238 5239 /* 5240 * wm_82547_txfifo_stall: 5241 * 5242 * Callout used to wait for the 82547 Tx FIFO to drain, 5243 * reset the FIFO pointers, and restart packet transmission. 5244 */ 5245 static void 5246 wm_82547_txfifo_stall(void *arg) 5247 { 5248 struct wm_softc *sc = arg; 5249 struct wm_txqueue *txq = sc->sc_txq; 5250 #ifndef WM_MPSAFE 5251 int s; 5252 5253 s = splnet(); 5254 #endif 5255 WM_TX_LOCK(txq); 5256 5257 if (sc->sc_stopping) 5258 goto out; 5259 5260 if (txq->txq_fifo_stall) { 5261 if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) && 5262 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 5263 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 5264 /* 5265 * Packets have drained. Stop transmitter, reset 5266 * FIFO pointers, restart transmitter, and kick 5267 * the packet queue. 5268 */ 5269 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 5270 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 5271 CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr); 5272 CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr); 5273 CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr); 5274 CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr); 5275 CSR_WRITE(sc, WMREG_TCTL, tctl); 5276 CSR_WRITE_FLUSH(sc); 5277 5278 txq->txq_fifo_head = 0; 5279 txq->txq_fifo_stall = 0; 5280 wm_start_locked(&sc->sc_ethercom.ec_if); 5281 } else { 5282 /* 5283 * Still waiting for packets to drain; try again in 5284 * another tick. 5285 */ 5286 callout_schedule(&sc->sc_txfifo_ch, 1); 5287 } 5288 } 5289 5290 out: 5291 WM_TX_UNLOCK(txq); 5292 #ifndef WM_MPSAFE 5293 splx(s); 5294 #endif 5295 } 5296 5297 /* 5298 * wm_82547_txfifo_bugchk: 5299 * 5300 * Check for bug condition in the 82547 Tx FIFO. We need to 5301 * prevent enqueueing a packet that would wrap around the end 5302 * if the Tx FIFO ring buffer, otherwise the chip will croak. 5303 * 5304 * We do this by checking the amount of space before the end 5305 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 5306 * the Tx FIFO, wait for all remaining packets to drain, reset 5307 * the internal FIFO pointers to the beginning, and restart 5308 * transmission on the interface. 5309 */ 5310 #define WM_FIFO_HDR 0x10 5311 #define WM_82547_PAD_LEN 0x3e0 5312 static int 5313 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 5314 { 5315 struct wm_txqueue *txq = &sc->sc_txq[0]; 5316 int space = txq->txq_fifo_size - txq->txq_fifo_head; 5317 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 5318 5319 /* Just return if already stalled. */ 5320 if (txq->txq_fifo_stall) 5321 return 1; 5322 5323 if (sc->sc_mii.mii_media_active & IFM_FDX) { 5324 /* Stall only occurs in half-duplex mode. */ 5325 goto send_packet; 5326 } 5327 5328 if (len >= WM_82547_PAD_LEN + space) { 5329 txq->txq_fifo_stall = 1; 5330 callout_schedule(&sc->sc_txfifo_ch, 1); 5331 return 1; 5332 } 5333 5334 send_packet: 5335 txq->txq_fifo_head += len; 5336 if (txq->txq_fifo_head >= txq->txq_fifo_size) 5337 txq->txq_fifo_head -= txq->txq_fifo_size; 5338 5339 return 0; 5340 } 5341 5342 static int 5343 wm_alloc_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq) 5344 { 5345 int error; 5346 5347 /* 5348 * Allocate the control data structures, and create and load the 5349 * DMA map for it. 5350 * 5351 * NOTE: All Tx descriptors must be in the same 4G segment of 5352 * memory. So must Rx descriptors. We simplify by allocating 5353 * both sets within the same 4G segment. 5354 */ 5355 if (sc->sc_type < WM_T_82544) { 5356 WM_NTXDESC(txq) = WM_NTXDESC_82542; 5357 txq->txq_desc_size = sizeof(wiseman_txdesc_t) *WM_NTXDESC(txq); 5358 } else { 5359 WM_NTXDESC(txq) = WM_NTXDESC_82544; 5360 txq->txq_desc_size = sizeof(txdescs_t); 5361 } 5362 5363 if ((error = bus_dmamem_alloc(sc->sc_dmat, txq->txq_desc_size, 5364 PAGE_SIZE, (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg, 5365 1, &txq->txq_desc_rseg, 0)) != 0) { 5366 aprint_error_dev(sc->sc_dev, 5367 "unable to allocate TX control data, error = %d\n", 5368 error); 5369 goto fail_0; 5370 } 5371 5372 if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg, 5373 txq->txq_desc_rseg, txq->txq_desc_size, 5374 (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) { 5375 aprint_error_dev(sc->sc_dev, 5376 "unable to map TX control data, error = %d\n", error); 5377 goto fail_1; 5378 } 5379 5380 if ((error = bus_dmamap_create(sc->sc_dmat, txq->txq_desc_size, 1, 5381 txq->txq_desc_size, 0, 0, &txq->txq_desc_dmamap)) != 0) { 5382 aprint_error_dev(sc->sc_dev, 5383 "unable to create TX control data DMA map, error = %d\n", 5384 error); 5385 goto fail_2; 5386 } 5387 5388 if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap, 5389 txq->txq_descs_u, txq->txq_desc_size, NULL, 0)) != 0) { 5390 aprint_error_dev(sc->sc_dev, 5391 "unable to load TX control data DMA map, error = %d\n", 5392 error); 5393 goto fail_3; 5394 } 5395 5396 return 0; 5397 5398 fail_3: 5399 bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap); 5400 fail_2: 5401 bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u, 5402 txq->txq_desc_size); 5403 fail_1: 5404 bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg); 5405 fail_0: 5406 return error; 5407 } 5408 5409 static void 5410 wm_free_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq) 5411 { 5412 5413 bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap); 5414 bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap); 5415 bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u, 5416 txq->txq_desc_size); 5417 bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg); 5418 } 5419 5420 static int 5421 wm_alloc_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq) 5422 { 5423 int error; 5424 5425 /* 5426 * Allocate the control data structures, and create and load the 5427 * DMA map for it. 5428 * 5429 * NOTE: All Tx descriptors must be in the same 4G segment of 5430 * memory. So must Rx descriptors. We simplify by allocating 5431 * both sets within the same 4G segment. 5432 */ 5433 rxq->rxq_desc_size = sizeof(wiseman_rxdesc_t) * WM_NRXDESC; 5434 if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq->rxq_desc_size, 5435 PAGE_SIZE, (bus_size_t) 0x100000000ULL, &rxq->rxq_desc_seg, 5436 1, &rxq->rxq_desc_rseg, 0)) != 0) { 5437 aprint_error_dev(sc->sc_dev, 5438 "unable to allocate RX control data, error = %d\n", 5439 error); 5440 goto fail_0; 5441 } 5442 5443 if ((error = bus_dmamem_map(sc->sc_dmat, &rxq->rxq_desc_seg, 5444 rxq->rxq_desc_rseg, rxq->rxq_desc_size, 5445 (void **)&rxq->rxq_descs, BUS_DMA_COHERENT)) != 0) { 5446 aprint_error_dev(sc->sc_dev, 5447 "unable to map RX control data, error = %d\n", error); 5448 goto fail_1; 5449 } 5450 5451 if ((error = bus_dmamap_create(sc->sc_dmat, rxq->rxq_desc_size, 1, 5452 rxq->rxq_desc_size, 0, 0, &rxq->rxq_desc_dmamap)) != 0) { 5453 aprint_error_dev(sc->sc_dev, 5454 "unable to create RX control data DMA map, error = %d\n", 5455 error); 5456 goto fail_2; 5457 } 5458 5459 if ((error = bus_dmamap_load(sc->sc_dmat, rxq->rxq_desc_dmamap, 5460 rxq->rxq_descs, rxq->rxq_desc_size, NULL, 0)) != 0) { 5461 aprint_error_dev(sc->sc_dev, 5462 "unable to load RX control data DMA map, error = %d\n", 5463 error); 5464 goto fail_3; 5465 } 5466 5467 return 0; 5468 5469 fail_3: 5470 bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap); 5471 fail_2: 5472 bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs, 5473 rxq->rxq_desc_size); 5474 fail_1: 5475 bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg); 5476 fail_0: 5477 return error; 5478 } 5479 5480 static void 5481 wm_free_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq) 5482 { 5483 5484 bus_dmamap_unload(sc->sc_dmat, rxq->rxq_desc_dmamap); 5485 bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap); 5486 bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs, 5487 rxq->rxq_desc_size); 5488 bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg); 5489 } 5490 5491 5492 static int 5493 wm_alloc_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq) 5494 { 5495 int i, error; 5496 5497 /* Create the transmit buffer DMA maps. */ 5498 WM_TXQUEUELEN(txq) = 5499 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 5500 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 5501 for (i = 0; i < WM_TXQUEUELEN(txq); i++) { 5502 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 5503 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 5504 &txq->txq_soft[i].txs_dmamap)) != 0) { 5505 aprint_error_dev(sc->sc_dev, 5506 "unable to create Tx DMA map %d, error = %d\n", 5507 i, error); 5508 goto fail; 5509 } 5510 } 5511 5512 return 0; 5513 5514 fail: 5515 for (i = 0; i < WM_TXQUEUELEN(txq); i++) { 5516 if (txq->txq_soft[i].txs_dmamap != NULL) 5517 bus_dmamap_destroy(sc->sc_dmat, 5518 txq->txq_soft[i].txs_dmamap); 5519 } 5520 return error; 5521 } 5522 5523 static void 5524 wm_free_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq) 5525 { 5526 int i; 5527 5528 for (i = 0; i < WM_TXQUEUELEN(txq); i++) { 5529 if (txq->txq_soft[i].txs_dmamap != NULL) 5530 bus_dmamap_destroy(sc->sc_dmat, 5531 txq->txq_soft[i].txs_dmamap); 5532 } 5533 } 5534 5535 static int 5536 wm_alloc_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq) 5537 { 5538 int i, error; 5539 5540 /* Create the receive buffer DMA maps. */ 5541 for (i = 0; i < WM_NRXDESC; i++) { 5542 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 5543 MCLBYTES, 0, 0, 5544 &rxq->rxq_soft[i].rxs_dmamap)) != 0) { 5545 aprint_error_dev(sc->sc_dev, 5546 "unable to create Rx DMA map %d error = %d\n", 5547 i, error); 5548 goto fail; 5549 } 5550 rxq->rxq_soft[i].rxs_mbuf = NULL; 5551 } 5552 5553 return 0; 5554 5555 fail: 5556 for (i = 0; i < WM_NRXDESC; i++) { 5557 if (rxq->rxq_soft[i].rxs_dmamap != NULL) 5558 bus_dmamap_destroy(sc->sc_dmat, 5559 rxq->rxq_soft[i].rxs_dmamap); 5560 } 5561 return error; 5562 } 5563 5564 static void 5565 wm_free_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq) 5566 { 5567 int i; 5568 5569 for (i = 0; i < WM_NRXDESC; i++) { 5570 if (rxq->rxq_soft[i].rxs_dmamap != NULL) 5571 bus_dmamap_destroy(sc->sc_dmat, 5572 rxq->rxq_soft[i].rxs_dmamap); 5573 } 5574 } 5575 5576 /* 5577 * wm_alloc_quques: 5578 * Allocate {tx,rx}descs and {tx,rx} buffers 5579 */ 5580 static int 5581 wm_alloc_txrx_queues(struct wm_softc *sc) 5582 { 5583 int i, error, tx_done, rx_done; 5584 5585 /* 5586 * For transmission 5587 */ 5588 sc->sc_txq = kmem_zalloc(sizeof(struct wm_txqueue) * sc->sc_ntxqueues, 5589 KM_SLEEP); 5590 if (sc->sc_txq == NULL) { 5591 aprint_error_dev(sc->sc_dev,"unable to allocate wm_txqueue\n"); 5592 error = ENOMEM; 5593 goto fail_0; 5594 } 5595 5596 error = 0; 5597 tx_done = 0; 5598 for (i = 0; i < sc->sc_ntxqueues; i++) { 5599 struct wm_txqueue *txq = &sc->sc_txq[i]; 5600 txq->txq_sc = sc; 5601 #ifdef WM_MPSAFE 5602 txq->txq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 5603 #else 5604 txq->txq_lock = NULL; 5605 #endif 5606 error = wm_alloc_tx_descs(sc, txq); 5607 if (error) 5608 break; 5609 error = wm_alloc_tx_buffer(sc, txq); 5610 if (error) { 5611 wm_free_tx_descs(sc, txq); 5612 break; 5613 } 5614 tx_done++; 5615 } 5616 if (error) 5617 goto fail_1; 5618 5619 /* 5620 * For recieve 5621 */ 5622 sc->sc_rxq = kmem_zalloc(sizeof(struct wm_rxqueue) * sc->sc_nrxqueues, 5623 KM_SLEEP); 5624 if (sc->sc_rxq == NULL) { 5625 aprint_error_dev(sc->sc_dev,"unable to allocate wm_rxqueue\n"); 5626 error = ENOMEM; 5627 goto fail_1; 5628 } 5629 5630 error = 0; 5631 rx_done = 0; 5632 for (i = 0; i < sc->sc_nrxqueues; i++) { 5633 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5634 rxq->rxq_sc = sc; 5635 #ifdef WM_MPSAFE 5636 rxq->rxq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 5637 #else 5638 rxq->rxq_lock = NULL; 5639 #endif 5640 error = wm_alloc_rx_descs(sc, rxq); 5641 if (error) 5642 break; 5643 5644 error = wm_alloc_rx_buffer(sc, rxq); 5645 if (error) { 5646 wm_free_rx_descs(sc, rxq); 5647 break; 5648 } 5649 5650 rx_done++; 5651 } 5652 if (error) 5653 goto fail_2; 5654 5655 return 0; 5656 5657 fail_2: 5658 for (i = 0; i < rx_done; i++) { 5659 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5660 wm_free_rx_buffer(sc, rxq); 5661 wm_free_rx_descs(sc, rxq); 5662 if (rxq->rxq_lock) 5663 mutex_obj_free(rxq->rxq_lock); 5664 } 5665 kmem_free(sc->sc_rxq, 5666 sizeof(struct wm_rxqueue) * sc->sc_nrxqueues); 5667 fail_1: 5668 for (i = 0; i < tx_done; i++) { 5669 struct wm_txqueue *txq = &sc->sc_txq[i]; 5670 wm_free_tx_buffer(sc, txq); 5671 wm_free_tx_descs(sc, txq); 5672 if (txq->txq_lock) 5673 mutex_obj_free(txq->txq_lock); 5674 } 5675 kmem_free(sc->sc_txq, 5676 sizeof(struct wm_txqueue) * sc->sc_ntxqueues); 5677 fail_0: 5678 return error; 5679 } 5680 5681 /* 5682 * wm_free_quques: 5683 * Free {tx,rx}descs and {tx,rx} buffers 5684 */ 5685 static void 5686 wm_free_txrx_queues(struct wm_softc *sc) 5687 { 5688 int i; 5689 5690 for (i = 0; i < sc->sc_nrxqueues; i++) { 5691 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5692 wm_free_rx_buffer(sc, rxq); 5693 wm_free_rx_descs(sc, rxq); 5694 if (rxq->rxq_lock) 5695 mutex_obj_free(rxq->rxq_lock); 5696 } 5697 kmem_free(sc->sc_rxq, sizeof(struct wm_rxqueue) * sc->sc_nrxqueues); 5698 5699 for (i = 0; i < sc->sc_ntxqueues; i++) { 5700 struct wm_txqueue *txq = &sc->sc_txq[i]; 5701 wm_free_tx_buffer(sc, txq); 5702 wm_free_tx_descs(sc, txq); 5703 if (txq->txq_lock) 5704 mutex_obj_free(txq->txq_lock); 5705 } 5706 kmem_free(sc->sc_txq, sizeof(struct wm_txqueue) * sc->sc_ntxqueues); 5707 } 5708 5709 static void 5710 wm_init_tx_descs(struct wm_softc *sc __unused, struct wm_txqueue *txq) 5711 { 5712 5713 KASSERT(WM_TX_LOCKED(txq)); 5714 5715 /* Initialize the transmit descriptor ring. */ 5716 memset(txq->txq_descs, 0, WM_TXDESCSIZE(txq)); 5717 wm_cdtxsync(txq, 0, WM_NTXDESC(txq), 5718 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5719 txq->txq_free = WM_NTXDESC(txq); 5720 txq->txq_next = 0; 5721 } 5722 5723 static void 5724 wm_init_tx_regs(struct wm_softc *sc, struct wm_txqueue *txq) 5725 { 5726 5727 KASSERT(WM_TX_LOCKED(txq)); 5728 5729 if (sc->sc_type < WM_T_82543) { 5730 CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(txq, 0)); 5731 CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(txq, 0)); 5732 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(txq)); 5733 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 5734 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 5735 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 5736 } else { 5737 int qid = txq->txq_id; 5738 5739 CSR_WRITE(sc, WMREG_TDBAH(qid), WM_CDTXADDR_HI(txq, 0)); 5740 CSR_WRITE(sc, WMREG_TDBAL(qid), WM_CDTXADDR_LO(txq, 0)); 5741 CSR_WRITE(sc, WMREG_TDLEN(qid), WM_TXDESCSIZE(txq)); 5742 CSR_WRITE(sc, WMREG_TDH(qid), 0); 5743 5744 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) 5745 /* 5746 * Don't write TDT before TCTL.EN is set. 5747 * See the document. 5748 */ 5749 CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_QUEUE_ENABLE 5750 | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0) 5751 | TXDCTL_WTHRESH(0)); 5752 else { 5753 /* ITR / 4 */ 5754 CSR_WRITE(sc, WMREG_TIDV, sc->sc_itr / 4); 5755 if (sc->sc_type >= WM_T_82540) { 5756 /* should be same */ 5757 CSR_WRITE(sc, WMREG_TADV, sc->sc_itr / 4); 5758 } 5759 5760 CSR_WRITE(sc, WMREG_TDT(qid), 0); 5761 CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_PTHRESH(0) | 5762 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 5763 } 5764 } 5765 } 5766 5767 static void 5768 wm_init_tx_buffer(struct wm_softc *sc __unused, struct wm_txqueue *txq) 5769 { 5770 int i; 5771 5772 KASSERT(WM_TX_LOCKED(txq)); 5773 5774 /* Initialize the transmit job descriptors. */ 5775 for (i = 0; i < WM_TXQUEUELEN(txq); i++) 5776 txq->txq_soft[i].txs_mbuf = NULL; 5777 txq->txq_sfree = WM_TXQUEUELEN(txq); 5778 txq->txq_snext = 0; 5779 txq->txq_sdirty = 0; 5780 } 5781 5782 static void 5783 wm_init_tx_queue(struct wm_softc *sc, struct wm_txqueue *txq) 5784 { 5785 5786 KASSERT(WM_TX_LOCKED(txq)); 5787 5788 /* 5789 * Set up some register offsets that are different between 5790 * the i82542 and the i82543 and later chips. 5791 */ 5792 if (sc->sc_type < WM_T_82543) 5793 txq->txq_tdt_reg = WMREG_OLD_TDT; 5794 else 5795 txq->txq_tdt_reg = WMREG_TDT(txq->txq_id); 5796 5797 wm_init_tx_descs(sc, txq); 5798 wm_init_tx_regs(sc, txq); 5799 wm_init_tx_buffer(sc, txq); 5800 } 5801 5802 static void 5803 wm_init_rx_regs(struct wm_softc *sc, struct wm_rxqueue *rxq) 5804 { 5805 5806 KASSERT(WM_RX_LOCKED(rxq)); 5807 5808 /* 5809 * Initialize the receive descriptor and receive job 5810 * descriptor rings. 5811 */ 5812 if (sc->sc_type < WM_T_82543) { 5813 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(rxq, 0)); 5814 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(rxq, 0)); 5815 CSR_WRITE(sc, WMREG_OLD_RDLEN0, 5816 sizeof(wiseman_rxdesc_t) * WM_NRXDESC); 5817 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 5818 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 5819 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 5820 5821 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 5822 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 5823 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 5824 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 5825 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 5826 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 5827 } else { 5828 int qid = rxq->rxq_id; 5829 5830 CSR_WRITE(sc, WMREG_RDBAH(qid), WM_CDRXADDR_HI(rxq, 0)); 5831 CSR_WRITE(sc, WMREG_RDBAL(qid), WM_CDRXADDR_LO(rxq, 0)); 5832 CSR_WRITE(sc, WMREG_RDLEN(qid), rxq->rxq_desc_size); 5833 5834 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 5835 if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1)) 5836 panic("%s: MCLBYTES %d unsupported for i2575 or higher\n", __func__, MCLBYTES); 5837 CSR_WRITE(sc, WMREG_SRRCTL(qid), SRRCTL_DESCTYPE_LEGACY 5838 | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT)); 5839 CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_QUEUE_ENABLE 5840 | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8) 5841 | RXDCTL_WTHRESH(1)); 5842 CSR_WRITE(sc, WMREG_RDH(qid), 0); 5843 CSR_WRITE(sc, WMREG_RDT(qid), 0); 5844 } else { 5845 CSR_WRITE(sc, WMREG_RDH(qid), 0); 5846 CSR_WRITE(sc, WMREG_RDT(qid), 0); 5847 /* ITR / 4 */ 5848 CSR_WRITE(sc, WMREG_RDTR, (sc->sc_itr / 4) | RDTR_FPD); 5849 /* MUST be same */ 5850 CSR_WRITE(sc, WMREG_RADV, sc->sc_itr / 4); 5851 CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_PTHRESH(0) | 5852 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 5853 } 5854 } 5855 } 5856 5857 static int 5858 wm_init_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq) 5859 { 5860 struct wm_rxsoft *rxs; 5861 int error, i; 5862 5863 KASSERT(WM_RX_LOCKED(rxq)); 5864 5865 for (i = 0; i < WM_NRXDESC; i++) { 5866 rxs = &rxq->rxq_soft[i]; 5867 if (rxs->rxs_mbuf == NULL) { 5868 if ((error = wm_add_rxbuf(rxq, i)) != 0) { 5869 log(LOG_ERR, "%s: unable to allocate or map " 5870 "rx buffer %d, error = %d\n", 5871 device_xname(sc->sc_dev), i, error); 5872 /* 5873 * XXX Should attempt to run with fewer receive 5874 * XXX buffers instead of just failing. 5875 */ 5876 wm_rxdrain(rxq); 5877 return ENOMEM; 5878 } 5879 } else { 5880 if ((sc->sc_flags & WM_F_NEWQUEUE) == 0) 5881 wm_init_rxdesc(rxq, i); 5882 /* 5883 * For 82575 and newer device, the RX descriptors 5884 * must be initialized after the setting of RCTL.EN in 5885 * wm_set_filter() 5886 */ 5887 } 5888 } 5889 rxq->rxq_ptr = 0; 5890 rxq->rxq_discard = 0; 5891 WM_RXCHAIN_RESET(rxq); 5892 5893 return 0; 5894 } 5895 5896 static int 5897 wm_init_rx_queue(struct wm_softc *sc, struct wm_rxqueue *rxq) 5898 { 5899 5900 KASSERT(WM_RX_LOCKED(rxq)); 5901 5902 /* 5903 * Set up some register offsets that are different between 5904 * the i82542 and the i82543 and later chips. 5905 */ 5906 if (sc->sc_type < WM_T_82543) 5907 rxq->rxq_rdt_reg = WMREG_OLD_RDT0; 5908 else 5909 rxq->rxq_rdt_reg = WMREG_RDT(rxq->rxq_id); 5910 5911 wm_init_rx_regs(sc, rxq); 5912 return wm_init_rx_buffer(sc, rxq); 5913 } 5914 5915 /* 5916 * wm_init_quques: 5917 * Initialize {tx,rx}descs and {tx,rx} buffers 5918 */ 5919 static int 5920 wm_init_txrx_queues(struct wm_softc *sc) 5921 { 5922 int i, error; 5923 5924 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 5925 device_xname(sc->sc_dev), __func__)); 5926 for (i = 0; i < sc->sc_ntxqueues; i++) { 5927 struct wm_txqueue *txq = &sc->sc_txq[i]; 5928 WM_TX_LOCK(txq); 5929 wm_init_tx_queue(sc, txq); 5930 WM_TX_UNLOCK(txq); 5931 } 5932 5933 error = 0; 5934 for (i = 0; i < sc->sc_nrxqueues; i++) { 5935 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5936 WM_RX_LOCK(rxq); 5937 error = wm_init_rx_queue(sc, rxq); 5938 WM_RX_UNLOCK(rxq); 5939 if (error) 5940 break; 5941 } 5942 5943 return error; 5944 } 5945 5946 /* 5947 * wm_tx_offload: 5948 * 5949 * Set up TCP/IP checksumming parameters for the 5950 * specified packet. 5951 */ 5952 static int 5953 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 5954 uint8_t *fieldsp) 5955 { 5956 struct wm_txqueue *txq = &sc->sc_txq[0]; 5957 struct mbuf *m0 = txs->txs_mbuf; 5958 struct livengood_tcpip_ctxdesc *t; 5959 uint32_t ipcs, tucs, cmd, cmdlen, seg; 5960 uint32_t ipcse; 5961 struct ether_header *eh; 5962 int offset, iphl; 5963 uint8_t fields; 5964 5965 /* 5966 * XXX It would be nice if the mbuf pkthdr had offset 5967 * fields for the protocol headers. 5968 */ 5969 5970 eh = mtod(m0, struct ether_header *); 5971 switch (htons(eh->ether_type)) { 5972 case ETHERTYPE_IP: 5973 case ETHERTYPE_IPV6: 5974 offset = ETHER_HDR_LEN; 5975 break; 5976 5977 case ETHERTYPE_VLAN: 5978 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5979 break; 5980 5981 default: 5982 /* 5983 * Don't support this protocol or encapsulation. 5984 */ 5985 *fieldsp = 0; 5986 *cmdp = 0; 5987 return 0; 5988 } 5989 5990 if ((m0->m_pkthdr.csum_flags & 5991 (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4)) != 0) { 5992 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5993 } else { 5994 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 5995 } 5996 ipcse = offset + iphl - 1; 5997 5998 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 5999 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 6000 seg = 0; 6001 fields = 0; 6002 6003 if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 6004 int hlen = offset + iphl; 6005 bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 6006 6007 if (__predict_false(m0->m_len < 6008 (hlen + sizeof(struct tcphdr)))) { 6009 /* 6010 * TCP/IP headers are not in the first mbuf; we need 6011 * to do this the slow and painful way. Let's just 6012 * hope this doesn't happen very often. 6013 */ 6014 struct tcphdr th; 6015 6016 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 6017 6018 m_copydata(m0, hlen, sizeof(th), &th); 6019 if (v4) { 6020 struct ip ip; 6021 6022 m_copydata(m0, offset, sizeof(ip), &ip); 6023 ip.ip_len = 0; 6024 m_copyback(m0, 6025 offset + offsetof(struct ip, ip_len), 6026 sizeof(ip.ip_len), &ip.ip_len); 6027 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 6028 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 6029 } else { 6030 struct ip6_hdr ip6; 6031 6032 m_copydata(m0, offset, sizeof(ip6), &ip6); 6033 ip6.ip6_plen = 0; 6034 m_copyback(m0, 6035 offset + offsetof(struct ip6_hdr, ip6_plen), 6036 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 6037 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 6038 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 6039 } 6040 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 6041 sizeof(th.th_sum), &th.th_sum); 6042 6043 hlen += th.th_off << 2; 6044 } else { 6045 /* 6046 * TCP/IP headers are in the first mbuf; we can do 6047 * this the easy way. 6048 */ 6049 struct tcphdr *th; 6050 6051 if (v4) { 6052 struct ip *ip = 6053 (void *)(mtod(m0, char *) + offset); 6054 th = (void *)(mtod(m0, char *) + hlen); 6055 6056 ip->ip_len = 0; 6057 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 6058 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 6059 } else { 6060 struct ip6_hdr *ip6 = 6061 (void *)(mtod(m0, char *) + offset); 6062 th = (void *)(mtod(m0, char *) + hlen); 6063 6064 ip6->ip6_plen = 0; 6065 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 6066 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 6067 } 6068 hlen += th->th_off << 2; 6069 } 6070 6071 if (v4) { 6072 WM_EVCNT_INCR(&sc->sc_ev_txtso); 6073 cmdlen |= WTX_TCPIP_CMD_IP; 6074 } else { 6075 WM_EVCNT_INCR(&sc->sc_ev_txtso6); 6076 ipcse = 0; 6077 } 6078 cmd |= WTX_TCPIP_CMD_TSE; 6079 cmdlen |= WTX_TCPIP_CMD_TSE | 6080 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 6081 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 6082 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 6083 } 6084 6085 /* 6086 * NOTE: Even if we're not using the IP or TCP/UDP checksum 6087 * offload feature, if we load the context descriptor, we 6088 * MUST provide valid values for IPCSS and TUCSS fields. 6089 */ 6090 6091 ipcs = WTX_TCPIP_IPCSS(offset) | 6092 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 6093 WTX_TCPIP_IPCSE(ipcse); 6094 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4 | M_CSUM_TSOv4)) { 6095 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 6096 fields |= WTX_IXSM; 6097 } 6098 6099 offset += iphl; 6100 6101 if (m0->m_pkthdr.csum_flags & 6102 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TSOv4)) { 6103 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 6104 fields |= WTX_TXSM; 6105 tucs = WTX_TCPIP_TUCSS(offset) | 6106 WTX_TCPIP_TUCSO(offset + 6107 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 6108 WTX_TCPIP_TUCSE(0) /* rest of packet */; 6109 } else if ((m0->m_pkthdr.csum_flags & 6110 (M_CSUM_TCPv6 | M_CSUM_UDPv6 | M_CSUM_TSOv6)) != 0) { 6111 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 6112 fields |= WTX_TXSM; 6113 tucs = WTX_TCPIP_TUCSS(offset) | 6114 WTX_TCPIP_TUCSO(offset + 6115 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 6116 WTX_TCPIP_TUCSE(0) /* rest of packet */; 6117 } else { 6118 /* Just initialize it to a valid TCP context. */ 6119 tucs = WTX_TCPIP_TUCSS(offset) | 6120 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 6121 WTX_TCPIP_TUCSE(0) /* rest of packet */; 6122 } 6123 6124 /* Fill in the context descriptor. */ 6125 t = (struct livengood_tcpip_ctxdesc *) 6126 &txq->txq_descs[txq->txq_next]; 6127 t->tcpip_ipcs = htole32(ipcs); 6128 t->tcpip_tucs = htole32(tucs); 6129 t->tcpip_cmdlen = htole32(cmdlen); 6130 t->tcpip_seg = htole32(seg); 6131 wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE); 6132 6133 txq->txq_next = WM_NEXTTX(txq, txq->txq_next); 6134 txs->txs_ndesc++; 6135 6136 *cmdp = cmd; 6137 *fieldsp = fields; 6138 6139 return 0; 6140 } 6141 6142 /* 6143 * wm_start: [ifnet interface function] 6144 * 6145 * Start packet transmission on the interface. 6146 */ 6147 static void 6148 wm_start(struct ifnet *ifp) 6149 { 6150 struct wm_softc *sc = ifp->if_softc; 6151 struct wm_txqueue *txq = &sc->sc_txq[0]; 6152 6153 WM_TX_LOCK(txq); 6154 if (!sc->sc_stopping) 6155 wm_start_locked(ifp); 6156 WM_TX_UNLOCK(txq); 6157 } 6158 6159 static void 6160 wm_start_locked(struct ifnet *ifp) 6161 { 6162 struct wm_softc *sc = ifp->if_softc; 6163 struct wm_txqueue *txq = &sc->sc_txq[0]; 6164 struct mbuf *m0; 6165 struct m_tag *mtag; 6166 struct wm_txsoft *txs; 6167 bus_dmamap_t dmamap; 6168 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 6169 bus_addr_t curaddr; 6170 bus_size_t seglen, curlen; 6171 uint32_t cksumcmd; 6172 uint8_t cksumfields; 6173 6174 KASSERT(WM_TX_LOCKED(txq)); 6175 6176 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 6177 return; 6178 6179 /* Remember the previous number of free descriptors. */ 6180 ofree = txq->txq_free; 6181 6182 /* 6183 * Loop through the send queue, setting up transmit descriptors 6184 * until we drain the queue, or use up all available transmit 6185 * descriptors. 6186 */ 6187 for (;;) { 6188 m0 = NULL; 6189 6190 /* Get a work queue entry. */ 6191 if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) { 6192 wm_txeof(sc); 6193 if (txq->txq_sfree == 0) { 6194 DPRINTF(WM_DEBUG_TX, 6195 ("%s: TX: no free job descriptors\n", 6196 device_xname(sc->sc_dev))); 6197 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 6198 break; 6199 } 6200 } 6201 6202 /* Grab a packet off the queue. */ 6203 IFQ_DEQUEUE(&ifp->if_snd, m0); 6204 if (m0 == NULL) 6205 break; 6206 6207 DPRINTF(WM_DEBUG_TX, 6208 ("%s: TX: have packet to transmit: %p\n", 6209 device_xname(sc->sc_dev), m0)); 6210 6211 txs = &txq->txq_soft[txq->txq_snext]; 6212 dmamap = txs->txs_dmamap; 6213 6214 use_tso = (m0->m_pkthdr.csum_flags & 6215 (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0; 6216 6217 /* 6218 * So says the Linux driver: 6219 * The controller does a simple calculation to make sure 6220 * there is enough room in the FIFO before initiating the 6221 * DMA for each buffer. The calc is: 6222 * 4 = ceil(buffer len / MSS) 6223 * To make sure we don't overrun the FIFO, adjust the max 6224 * buffer len if the MSS drops. 6225 */ 6226 dmamap->dm_maxsegsz = 6227 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 6228 ? m0->m_pkthdr.segsz << 2 6229 : WTX_MAX_LEN; 6230 6231 /* 6232 * Load the DMA map. If this fails, the packet either 6233 * didn't fit in the allotted number of segments, or we 6234 * were short on resources. For the too-many-segments 6235 * case, we simply report an error and drop the packet, 6236 * since we can't sanely copy a jumbo packet to a single 6237 * buffer. 6238 */ 6239 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 6240 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 6241 if (error) { 6242 if (error == EFBIG) { 6243 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 6244 log(LOG_ERR, "%s: Tx packet consumes too many " 6245 "DMA segments, dropping...\n", 6246 device_xname(sc->sc_dev)); 6247 wm_dump_mbuf_chain(sc, m0); 6248 m_freem(m0); 6249 continue; 6250 } 6251 /* Short on resources, just stop for now. */ 6252 DPRINTF(WM_DEBUG_TX, 6253 ("%s: TX: dmamap load failed: %d\n", 6254 device_xname(sc->sc_dev), error)); 6255 break; 6256 } 6257 6258 segs_needed = dmamap->dm_nsegs; 6259 if (use_tso) { 6260 /* For sentinel descriptor; see below. */ 6261 segs_needed++; 6262 } 6263 6264 /* 6265 * Ensure we have enough descriptors free to describe 6266 * the packet. Note, we always reserve one descriptor 6267 * at the end of the ring due to the semantics of the 6268 * TDT register, plus one more in the event we need 6269 * to load offload context. 6270 */ 6271 if (segs_needed > txq->txq_free - 2) { 6272 /* 6273 * Not enough free descriptors to transmit this 6274 * packet. We haven't committed anything yet, 6275 * so just unload the DMA map, put the packet 6276 * pack on the queue, and punt. Notify the upper 6277 * layer that there are no more slots left. 6278 */ 6279 DPRINTF(WM_DEBUG_TX, 6280 ("%s: TX: need %d (%d) descriptors, have %d\n", 6281 device_xname(sc->sc_dev), dmamap->dm_nsegs, 6282 segs_needed, txq->txq_free - 1)); 6283 ifp->if_flags |= IFF_OACTIVE; 6284 bus_dmamap_unload(sc->sc_dmat, dmamap); 6285 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 6286 break; 6287 } 6288 6289 /* 6290 * Check for 82547 Tx FIFO bug. We need to do this 6291 * once we know we can transmit the packet, since we 6292 * do some internal FIFO space accounting here. 6293 */ 6294 if (sc->sc_type == WM_T_82547 && 6295 wm_82547_txfifo_bugchk(sc, m0)) { 6296 DPRINTF(WM_DEBUG_TX, 6297 ("%s: TX: 82547 Tx FIFO bug detected\n", 6298 device_xname(sc->sc_dev))); 6299 ifp->if_flags |= IFF_OACTIVE; 6300 bus_dmamap_unload(sc->sc_dmat, dmamap); 6301 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 6302 break; 6303 } 6304 6305 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 6306 6307 DPRINTF(WM_DEBUG_TX, 6308 ("%s: TX: packet has %d (%d) DMA segments\n", 6309 device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed)); 6310 6311 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 6312 6313 /* 6314 * Store a pointer to the packet so that we can free it 6315 * later. 6316 * 6317 * Initially, we consider the number of descriptors the 6318 * packet uses the number of DMA segments. This may be 6319 * incremented by 1 if we do checksum offload (a descriptor 6320 * is used to set the checksum context). 6321 */ 6322 txs->txs_mbuf = m0; 6323 txs->txs_firstdesc = txq->txq_next; 6324 txs->txs_ndesc = segs_needed; 6325 6326 /* Set up offload parameters for this packet. */ 6327 if (m0->m_pkthdr.csum_flags & 6328 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | 6329 M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 | 6330 M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 6331 if (wm_tx_offload(sc, txs, &cksumcmd, 6332 &cksumfields) != 0) { 6333 /* Error message already displayed. */ 6334 bus_dmamap_unload(sc->sc_dmat, dmamap); 6335 continue; 6336 } 6337 } else { 6338 cksumcmd = 0; 6339 cksumfields = 0; 6340 } 6341 6342 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 6343 6344 /* Sync the DMA map. */ 6345 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 6346 BUS_DMASYNC_PREWRITE); 6347 6348 /* Initialize the transmit descriptor. */ 6349 for (nexttx = txq->txq_next, seg = 0; 6350 seg < dmamap->dm_nsegs; seg++) { 6351 for (seglen = dmamap->dm_segs[seg].ds_len, 6352 curaddr = dmamap->dm_segs[seg].ds_addr; 6353 seglen != 0; 6354 curaddr += curlen, seglen -= curlen, 6355 nexttx = WM_NEXTTX(txq, nexttx)) { 6356 curlen = seglen; 6357 6358 /* 6359 * So says the Linux driver: 6360 * Work around for premature descriptor 6361 * write-backs in TSO mode. Append a 6362 * 4-byte sentinel descriptor. 6363 */ 6364 if (use_tso && seg == dmamap->dm_nsegs - 1 && 6365 curlen > 8) 6366 curlen -= 4; 6367 6368 wm_set_dma_addr( 6369 &txq->txq_descs[nexttx].wtx_addr, curaddr); 6370 txq->txq_descs[nexttx].wtx_cmdlen 6371 = htole32(cksumcmd | curlen); 6372 txq->txq_descs[nexttx].wtx_fields.wtxu_status 6373 = 0; 6374 txq->txq_descs[nexttx].wtx_fields.wtxu_options 6375 = cksumfields; 6376 txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0; 6377 lasttx = nexttx; 6378 6379 DPRINTF(WM_DEBUG_TX, 6380 ("%s: TX: desc %d: low %#" PRIx64 ", " 6381 "len %#04zx\n", 6382 device_xname(sc->sc_dev), nexttx, 6383 (uint64_t)curaddr, curlen)); 6384 } 6385 } 6386 6387 KASSERT(lasttx != -1); 6388 6389 /* 6390 * Set up the command byte on the last descriptor of 6391 * the packet. If we're in the interrupt delay window, 6392 * delay the interrupt. 6393 */ 6394 txq->txq_descs[lasttx].wtx_cmdlen |= 6395 htole32(WTX_CMD_EOP | WTX_CMD_RS); 6396 6397 /* 6398 * If VLANs are enabled and the packet has a VLAN tag, set 6399 * up the descriptor to encapsulate the packet for us. 6400 * 6401 * This is only valid on the last descriptor of the packet. 6402 */ 6403 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 6404 txq->txq_descs[lasttx].wtx_cmdlen |= 6405 htole32(WTX_CMD_VLE); 6406 txq->txq_descs[lasttx].wtx_fields.wtxu_vlan 6407 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 6408 } 6409 6410 txs->txs_lastdesc = lasttx; 6411 6412 DPRINTF(WM_DEBUG_TX, 6413 ("%s: TX: desc %d: cmdlen 0x%08x\n", 6414 device_xname(sc->sc_dev), 6415 lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen))); 6416 6417 /* Sync the descriptors we're using. */ 6418 wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc, 6419 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6420 6421 /* Give the packet to the chip. */ 6422 CSR_WRITE(sc, txq->txq_tdt_reg, nexttx); 6423 6424 DPRINTF(WM_DEBUG_TX, 6425 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 6426 6427 DPRINTF(WM_DEBUG_TX, 6428 ("%s: TX: finished transmitting packet, job %d\n", 6429 device_xname(sc->sc_dev), txq->txq_snext)); 6430 6431 /* Advance the tx pointer. */ 6432 txq->txq_free -= txs->txs_ndesc; 6433 txq->txq_next = nexttx; 6434 6435 txq->txq_sfree--; 6436 txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext); 6437 6438 /* Pass the packet to any BPF listeners. */ 6439 bpf_mtap(ifp, m0); 6440 } 6441 6442 if (m0 != NULL) { 6443 ifp->if_flags |= IFF_OACTIVE; 6444 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 6445 DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n", 6446 __func__)); 6447 m_freem(m0); 6448 } 6449 6450 if (txq->txq_sfree == 0 || txq->txq_free <= 2) { 6451 /* No more slots; notify upper layer. */ 6452 ifp->if_flags |= IFF_OACTIVE; 6453 } 6454 6455 if (txq->txq_free != ofree) { 6456 /* Set a watchdog timer in case the chip flakes out. */ 6457 ifp->if_timer = 5; 6458 } 6459 } 6460 6461 /* 6462 * wm_nq_tx_offload: 6463 * 6464 * Set up TCP/IP checksumming parameters for the 6465 * specified packet, for NEWQUEUE devices 6466 */ 6467 static int 6468 wm_nq_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, 6469 uint32_t *cmdlenp, uint32_t *fieldsp, bool *do_csum) 6470 { 6471 struct wm_txqueue *txq = &sc->sc_txq[0]; 6472 struct mbuf *m0 = txs->txs_mbuf; 6473 struct m_tag *mtag; 6474 uint32_t vl_len, mssidx, cmdc; 6475 struct ether_header *eh; 6476 int offset, iphl; 6477 6478 /* 6479 * XXX It would be nice if the mbuf pkthdr had offset 6480 * fields for the protocol headers. 6481 */ 6482 *cmdlenp = 0; 6483 *fieldsp = 0; 6484 6485 eh = mtod(m0, struct ether_header *); 6486 switch (htons(eh->ether_type)) { 6487 case ETHERTYPE_IP: 6488 case ETHERTYPE_IPV6: 6489 offset = ETHER_HDR_LEN; 6490 break; 6491 6492 case ETHERTYPE_VLAN: 6493 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 6494 break; 6495 6496 default: 6497 /* Don't support this protocol or encapsulation. */ 6498 *do_csum = false; 6499 return 0; 6500 } 6501 *do_csum = true; 6502 *cmdlenp = NQTX_DTYP_D | NQTX_CMD_DEXT | NQTX_CMD_IFCS; 6503 cmdc = NQTX_DTYP_C | NQTX_CMD_DEXT; 6504 6505 vl_len = (offset << NQTXC_VLLEN_MACLEN_SHIFT); 6506 KASSERT((offset & ~NQTXC_VLLEN_MACLEN_MASK) == 0); 6507 6508 if ((m0->m_pkthdr.csum_flags & 6509 (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) { 6510 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 6511 } else { 6512 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 6513 } 6514 vl_len |= (iphl << NQTXC_VLLEN_IPLEN_SHIFT); 6515 KASSERT((iphl & ~NQTXC_VLLEN_IPLEN_MASK) == 0); 6516 6517 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 6518 vl_len |= ((VLAN_TAG_VALUE(mtag) & NQTXC_VLLEN_VLAN_MASK) 6519 << NQTXC_VLLEN_VLAN_SHIFT); 6520 *cmdlenp |= NQTX_CMD_VLE; 6521 } 6522 6523 mssidx = 0; 6524 6525 if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 6526 int hlen = offset + iphl; 6527 int tcp_hlen; 6528 bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 6529 6530 if (__predict_false(m0->m_len < 6531 (hlen + sizeof(struct tcphdr)))) { 6532 /* 6533 * TCP/IP headers are not in the first mbuf; we need 6534 * to do this the slow and painful way. Let's just 6535 * hope this doesn't happen very often. 6536 */ 6537 struct tcphdr th; 6538 6539 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 6540 6541 m_copydata(m0, hlen, sizeof(th), &th); 6542 if (v4) { 6543 struct ip ip; 6544 6545 m_copydata(m0, offset, sizeof(ip), &ip); 6546 ip.ip_len = 0; 6547 m_copyback(m0, 6548 offset + offsetof(struct ip, ip_len), 6549 sizeof(ip.ip_len), &ip.ip_len); 6550 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 6551 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 6552 } else { 6553 struct ip6_hdr ip6; 6554 6555 m_copydata(m0, offset, sizeof(ip6), &ip6); 6556 ip6.ip6_plen = 0; 6557 m_copyback(m0, 6558 offset + offsetof(struct ip6_hdr, ip6_plen), 6559 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 6560 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 6561 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 6562 } 6563 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 6564 sizeof(th.th_sum), &th.th_sum); 6565 6566 tcp_hlen = th.th_off << 2; 6567 } else { 6568 /* 6569 * TCP/IP headers are in the first mbuf; we can do 6570 * this the easy way. 6571 */ 6572 struct tcphdr *th; 6573 6574 if (v4) { 6575 struct ip *ip = 6576 (void *)(mtod(m0, char *) + offset); 6577 th = (void *)(mtod(m0, char *) + hlen); 6578 6579 ip->ip_len = 0; 6580 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 6581 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 6582 } else { 6583 struct ip6_hdr *ip6 = 6584 (void *)(mtod(m0, char *) + offset); 6585 th = (void *)(mtod(m0, char *) + hlen); 6586 6587 ip6->ip6_plen = 0; 6588 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 6589 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 6590 } 6591 tcp_hlen = th->th_off << 2; 6592 } 6593 hlen += tcp_hlen; 6594 *cmdlenp |= NQTX_CMD_TSE; 6595 6596 if (v4) { 6597 WM_EVCNT_INCR(&sc->sc_ev_txtso); 6598 *fieldsp |= NQTXD_FIELDS_IXSM | NQTXD_FIELDS_TUXSM; 6599 } else { 6600 WM_EVCNT_INCR(&sc->sc_ev_txtso6); 6601 *fieldsp |= NQTXD_FIELDS_TUXSM; 6602 } 6603 *fieldsp |= ((m0->m_pkthdr.len - hlen) << NQTXD_FIELDS_PAYLEN_SHIFT); 6604 KASSERT(((m0->m_pkthdr.len - hlen) & ~NQTXD_FIELDS_PAYLEN_MASK) == 0); 6605 mssidx |= (m0->m_pkthdr.segsz << NQTXC_MSSIDX_MSS_SHIFT); 6606 KASSERT((m0->m_pkthdr.segsz & ~NQTXC_MSSIDX_MSS_MASK) == 0); 6607 mssidx |= (tcp_hlen << NQTXC_MSSIDX_L4LEN_SHIFT); 6608 KASSERT((tcp_hlen & ~NQTXC_MSSIDX_L4LEN_MASK) == 0); 6609 } else { 6610 *fieldsp |= (m0->m_pkthdr.len << NQTXD_FIELDS_PAYLEN_SHIFT); 6611 KASSERT((m0->m_pkthdr.len & ~NQTXD_FIELDS_PAYLEN_MASK) == 0); 6612 } 6613 6614 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 6615 *fieldsp |= NQTXD_FIELDS_IXSM; 6616 cmdc |= NQTXC_CMD_IP4; 6617 } 6618 6619 if (m0->m_pkthdr.csum_flags & 6620 (M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) { 6621 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 6622 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4)) { 6623 cmdc |= NQTXC_CMD_TCP; 6624 } else { 6625 cmdc |= NQTXC_CMD_UDP; 6626 } 6627 cmdc |= NQTXC_CMD_IP4; 6628 *fieldsp |= NQTXD_FIELDS_TUXSM; 6629 } 6630 if (m0->m_pkthdr.csum_flags & 6631 (M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) { 6632 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 6633 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6)) { 6634 cmdc |= NQTXC_CMD_TCP; 6635 } else { 6636 cmdc |= NQTXC_CMD_UDP; 6637 } 6638 cmdc |= NQTXC_CMD_IP6; 6639 *fieldsp |= NQTXD_FIELDS_TUXSM; 6640 } 6641 6642 /* Fill in the context descriptor. */ 6643 txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_vl_len = 6644 htole32(vl_len); 6645 txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_sn = 0; 6646 txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_cmd = 6647 htole32(cmdc); 6648 txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_mssidx = 6649 htole32(mssidx); 6650 wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE); 6651 DPRINTF(WM_DEBUG_TX, 6652 ("%s: TX: context desc %d 0x%08x%08x\n", device_xname(sc->sc_dev), 6653 txq->txq_next, 0, vl_len)); 6654 DPRINTF(WM_DEBUG_TX, ("\t0x%08x%08x\n", mssidx, cmdc)); 6655 txq->txq_next = WM_NEXTTX(txq, txq->txq_next); 6656 txs->txs_ndesc++; 6657 return 0; 6658 } 6659 6660 /* 6661 * wm_nq_start: [ifnet interface function] 6662 * 6663 * Start packet transmission on the interface for NEWQUEUE devices 6664 */ 6665 static void 6666 wm_nq_start(struct ifnet *ifp) 6667 { 6668 struct wm_softc *sc = ifp->if_softc; 6669 struct wm_txqueue *txq = &sc->sc_txq[0]; 6670 6671 WM_TX_LOCK(txq); 6672 if (!sc->sc_stopping) 6673 wm_nq_start_locked(ifp); 6674 WM_TX_UNLOCK(txq); 6675 } 6676 6677 static void 6678 wm_nq_start_locked(struct ifnet *ifp) 6679 { 6680 struct wm_softc *sc = ifp->if_softc; 6681 struct wm_txqueue *txq = &sc->sc_txq[0]; 6682 struct mbuf *m0; 6683 struct m_tag *mtag; 6684 struct wm_txsoft *txs; 6685 bus_dmamap_t dmamap; 6686 int error, nexttx, lasttx = -1, seg, segs_needed; 6687 bool do_csum, sent; 6688 6689 KASSERT(WM_TX_LOCKED(txq)); 6690 6691 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 6692 return; 6693 6694 sent = false; 6695 6696 /* 6697 * Loop through the send queue, setting up transmit descriptors 6698 * until we drain the queue, or use up all available transmit 6699 * descriptors. 6700 */ 6701 for (;;) { 6702 m0 = NULL; 6703 6704 /* Get a work queue entry. */ 6705 if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) { 6706 wm_txeof(sc); 6707 if (txq->txq_sfree == 0) { 6708 DPRINTF(WM_DEBUG_TX, 6709 ("%s: TX: no free job descriptors\n", 6710 device_xname(sc->sc_dev))); 6711 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 6712 break; 6713 } 6714 } 6715 6716 /* Grab a packet off the queue. */ 6717 IFQ_DEQUEUE(&ifp->if_snd, m0); 6718 if (m0 == NULL) 6719 break; 6720 6721 DPRINTF(WM_DEBUG_TX, 6722 ("%s: TX: have packet to transmit: %p\n", 6723 device_xname(sc->sc_dev), m0)); 6724 6725 txs = &txq->txq_soft[txq->txq_snext]; 6726 dmamap = txs->txs_dmamap; 6727 6728 /* 6729 * Load the DMA map. If this fails, the packet either 6730 * didn't fit in the allotted number of segments, or we 6731 * were short on resources. For the too-many-segments 6732 * case, we simply report an error and drop the packet, 6733 * since we can't sanely copy a jumbo packet to a single 6734 * buffer. 6735 */ 6736 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 6737 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 6738 if (error) { 6739 if (error == EFBIG) { 6740 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 6741 log(LOG_ERR, "%s: Tx packet consumes too many " 6742 "DMA segments, dropping...\n", 6743 device_xname(sc->sc_dev)); 6744 wm_dump_mbuf_chain(sc, m0); 6745 m_freem(m0); 6746 continue; 6747 } 6748 /* Short on resources, just stop for now. */ 6749 DPRINTF(WM_DEBUG_TX, 6750 ("%s: TX: dmamap load failed: %d\n", 6751 device_xname(sc->sc_dev), error)); 6752 break; 6753 } 6754 6755 segs_needed = dmamap->dm_nsegs; 6756 6757 /* 6758 * Ensure we have enough descriptors free to describe 6759 * the packet. Note, we always reserve one descriptor 6760 * at the end of the ring due to the semantics of the 6761 * TDT register, plus one more in the event we need 6762 * to load offload context. 6763 */ 6764 if (segs_needed > txq->txq_free - 2) { 6765 /* 6766 * Not enough free descriptors to transmit this 6767 * packet. We haven't committed anything yet, 6768 * so just unload the DMA map, put the packet 6769 * pack on the queue, and punt. Notify the upper 6770 * layer that there are no more slots left. 6771 */ 6772 DPRINTF(WM_DEBUG_TX, 6773 ("%s: TX: need %d (%d) descriptors, have %d\n", 6774 device_xname(sc->sc_dev), dmamap->dm_nsegs, 6775 segs_needed, txq->txq_free - 1)); 6776 ifp->if_flags |= IFF_OACTIVE; 6777 bus_dmamap_unload(sc->sc_dmat, dmamap); 6778 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 6779 break; 6780 } 6781 6782 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 6783 6784 DPRINTF(WM_DEBUG_TX, 6785 ("%s: TX: packet has %d (%d) DMA segments\n", 6786 device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed)); 6787 6788 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 6789 6790 /* 6791 * Store a pointer to the packet so that we can free it 6792 * later. 6793 * 6794 * Initially, we consider the number of descriptors the 6795 * packet uses the number of DMA segments. This may be 6796 * incremented by 1 if we do checksum offload (a descriptor 6797 * is used to set the checksum context). 6798 */ 6799 txs->txs_mbuf = m0; 6800 txs->txs_firstdesc = txq->txq_next; 6801 txs->txs_ndesc = segs_needed; 6802 6803 /* Set up offload parameters for this packet. */ 6804 uint32_t cmdlen, fields, dcmdlen; 6805 if (m0->m_pkthdr.csum_flags & 6806 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | 6807 M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 | 6808 M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 6809 if (wm_nq_tx_offload(sc, txs, &cmdlen, &fields, 6810 &do_csum) != 0) { 6811 /* Error message already displayed. */ 6812 bus_dmamap_unload(sc->sc_dmat, dmamap); 6813 continue; 6814 } 6815 } else { 6816 do_csum = false; 6817 cmdlen = 0; 6818 fields = 0; 6819 } 6820 6821 /* Sync the DMA map. */ 6822 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 6823 BUS_DMASYNC_PREWRITE); 6824 6825 /* Initialize the first transmit descriptor. */ 6826 nexttx = txq->txq_next; 6827 if (!do_csum) { 6828 /* setup a legacy descriptor */ 6829 wm_set_dma_addr(&txq->txq_descs[nexttx].wtx_addr, 6830 dmamap->dm_segs[0].ds_addr); 6831 txq->txq_descs[nexttx].wtx_cmdlen = 6832 htole32(WTX_CMD_IFCS | dmamap->dm_segs[0].ds_len); 6833 txq->txq_descs[nexttx].wtx_fields.wtxu_status = 0; 6834 txq->txq_descs[nexttx].wtx_fields.wtxu_options = 0; 6835 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != 6836 NULL) { 6837 txq->txq_descs[nexttx].wtx_cmdlen |= 6838 htole32(WTX_CMD_VLE); 6839 txq->txq_descs[nexttx].wtx_fields.wtxu_vlan = 6840 htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 6841 } else { 6842 txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0; 6843 } 6844 dcmdlen = 0; 6845 } else { 6846 /* setup an advanced data descriptor */ 6847 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr = 6848 htole64(dmamap->dm_segs[0].ds_addr); 6849 KASSERT((dmamap->dm_segs[0].ds_len & cmdlen) == 0); 6850 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen = 6851 htole32(dmamap->dm_segs[0].ds_len | cmdlen ); 6852 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields = 6853 htole32(fields); 6854 DPRINTF(WM_DEBUG_TX, 6855 ("%s: TX: adv data desc %d 0x%" PRIx64 "\n", 6856 device_xname(sc->sc_dev), nexttx, 6857 (uint64_t)dmamap->dm_segs[0].ds_addr)); 6858 DPRINTF(WM_DEBUG_TX, 6859 ("\t 0x%08x%08x\n", fields, 6860 (uint32_t)dmamap->dm_segs[0].ds_len | cmdlen)); 6861 dcmdlen = NQTX_DTYP_D | NQTX_CMD_DEXT; 6862 } 6863 6864 lasttx = nexttx; 6865 nexttx = WM_NEXTTX(txq, nexttx); 6866 /* 6867 * fill in the next descriptors. legacy or adcanced format 6868 * is the same here 6869 */ 6870 for (seg = 1; seg < dmamap->dm_nsegs; 6871 seg++, nexttx = WM_NEXTTX(txq, nexttx)) { 6872 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr = 6873 htole64(dmamap->dm_segs[seg].ds_addr); 6874 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen = 6875 htole32(dcmdlen | dmamap->dm_segs[seg].ds_len); 6876 KASSERT((dcmdlen & dmamap->dm_segs[seg].ds_len) == 0); 6877 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields = 0; 6878 lasttx = nexttx; 6879 6880 DPRINTF(WM_DEBUG_TX, 6881 ("%s: TX: desc %d: %#" PRIx64 ", " 6882 "len %#04zx\n", 6883 device_xname(sc->sc_dev), nexttx, 6884 (uint64_t)dmamap->dm_segs[seg].ds_addr, 6885 dmamap->dm_segs[seg].ds_len)); 6886 } 6887 6888 KASSERT(lasttx != -1); 6889 6890 /* 6891 * Set up the command byte on the last descriptor of 6892 * the packet. If we're in the interrupt delay window, 6893 * delay the interrupt. 6894 */ 6895 KASSERT((WTX_CMD_EOP | WTX_CMD_RS) == 6896 (NQTX_CMD_EOP | NQTX_CMD_RS)); 6897 txq->txq_descs[lasttx].wtx_cmdlen |= 6898 htole32(WTX_CMD_EOP | WTX_CMD_RS); 6899 6900 txs->txs_lastdesc = lasttx; 6901 6902 DPRINTF(WM_DEBUG_TX, ("%s: TX: desc %d: cmdlen 0x%08x\n", 6903 device_xname(sc->sc_dev), 6904 lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen))); 6905 6906 /* Sync the descriptors we're using. */ 6907 wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc, 6908 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6909 6910 /* Give the packet to the chip. */ 6911 CSR_WRITE(sc, txq->txq_tdt_reg, nexttx); 6912 sent = true; 6913 6914 DPRINTF(WM_DEBUG_TX, 6915 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 6916 6917 DPRINTF(WM_DEBUG_TX, 6918 ("%s: TX: finished transmitting packet, job %d\n", 6919 device_xname(sc->sc_dev), txq->txq_snext)); 6920 6921 /* Advance the tx pointer. */ 6922 txq->txq_free -= txs->txs_ndesc; 6923 txq->txq_next = nexttx; 6924 6925 txq->txq_sfree--; 6926 txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext); 6927 6928 /* Pass the packet to any BPF listeners. */ 6929 bpf_mtap(ifp, m0); 6930 } 6931 6932 if (m0 != NULL) { 6933 ifp->if_flags |= IFF_OACTIVE; 6934 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 6935 DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n", 6936 __func__)); 6937 m_freem(m0); 6938 } 6939 6940 if (txq->txq_sfree == 0 || txq->txq_free <= 2) { 6941 /* No more slots; notify upper layer. */ 6942 ifp->if_flags |= IFF_OACTIVE; 6943 } 6944 6945 if (sent) { 6946 /* Set a watchdog timer in case the chip flakes out. */ 6947 ifp->if_timer = 5; 6948 } 6949 } 6950 6951 /* Interrupt */ 6952 6953 /* 6954 * wm_txeof: 6955 * 6956 * Helper; handle transmit interrupts. 6957 */ 6958 static int 6959 wm_txeof(struct wm_softc *sc) 6960 { 6961 struct wm_txqueue *txq = &sc->sc_txq[0]; 6962 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 6963 struct wm_txsoft *txs; 6964 bool processed = false; 6965 int count = 0; 6966 int i; 6967 uint8_t status; 6968 6969 if (sc->sc_stopping) 6970 return 0; 6971 6972 ifp->if_flags &= ~IFF_OACTIVE; 6973 6974 /* 6975 * Go through the Tx list and free mbufs for those 6976 * frames which have been transmitted. 6977 */ 6978 for (i = txq->txq_sdirty; txq->txq_sfree != WM_TXQUEUELEN(txq); 6979 i = WM_NEXTTXS(txq, i), txq->txq_sfree++) { 6980 txs = &txq->txq_soft[i]; 6981 6982 DPRINTF(WM_DEBUG_TX, ("%s: TX: checking job %d\n", 6983 device_xname(sc->sc_dev), i)); 6984 6985 wm_cdtxsync(txq, txs->txs_firstdesc, txs->txs_ndesc, 6986 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6987 6988 status = 6989 txq->txq_descs[txs->txs_lastdesc].wtx_fields.wtxu_status; 6990 if ((status & WTX_ST_DD) == 0) { 6991 wm_cdtxsync(txq, txs->txs_lastdesc, 1, 6992 BUS_DMASYNC_PREREAD); 6993 break; 6994 } 6995 6996 processed = true; 6997 count++; 6998 DPRINTF(WM_DEBUG_TX, 6999 ("%s: TX: job %d done: descs %d..%d\n", 7000 device_xname(sc->sc_dev), i, txs->txs_firstdesc, 7001 txs->txs_lastdesc)); 7002 7003 /* 7004 * XXX We should probably be using the statistics 7005 * XXX registers, but I don't know if they exist 7006 * XXX on chips before the i82544. 7007 */ 7008 7009 #ifdef WM_EVENT_COUNTERS 7010 if (status & WTX_ST_TU) 7011 WM_EVCNT_INCR(&sc->sc_ev_tu); 7012 #endif /* WM_EVENT_COUNTERS */ 7013 7014 if (status & (WTX_ST_EC | WTX_ST_LC)) { 7015 ifp->if_oerrors++; 7016 if (status & WTX_ST_LC) 7017 log(LOG_WARNING, "%s: late collision\n", 7018 device_xname(sc->sc_dev)); 7019 else if (status & WTX_ST_EC) { 7020 ifp->if_collisions += 16; 7021 log(LOG_WARNING, "%s: excessive collisions\n", 7022 device_xname(sc->sc_dev)); 7023 } 7024 } else 7025 ifp->if_opackets++; 7026 7027 txq->txq_free += txs->txs_ndesc; 7028 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 7029 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 7030 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 7031 m_freem(txs->txs_mbuf); 7032 txs->txs_mbuf = NULL; 7033 } 7034 7035 /* Update the dirty transmit buffer pointer. */ 7036 txq->txq_sdirty = i; 7037 DPRINTF(WM_DEBUG_TX, 7038 ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i)); 7039 7040 if (count != 0) 7041 rnd_add_uint32(&sc->rnd_source, count); 7042 7043 /* 7044 * If there are no more pending transmissions, cancel the watchdog 7045 * timer. 7046 */ 7047 if (txq->txq_sfree == WM_TXQUEUELEN(txq)) 7048 ifp->if_timer = 0; 7049 7050 return processed; 7051 } 7052 7053 /* 7054 * wm_rxeof: 7055 * 7056 * Helper; handle receive interrupts. 7057 */ 7058 static void 7059 wm_rxeof(struct wm_rxqueue *rxq) 7060 { 7061 struct wm_softc *sc = rxq->rxq_sc; 7062 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 7063 struct wm_rxsoft *rxs; 7064 struct mbuf *m; 7065 int i, len; 7066 int count = 0; 7067 uint8_t status, errors; 7068 uint16_t vlantag; 7069 7070 for (i = rxq->rxq_ptr;; i = WM_NEXTRX(i)) { 7071 rxs = &rxq->rxq_soft[i]; 7072 7073 DPRINTF(WM_DEBUG_RX, 7074 ("%s: RX: checking descriptor %d\n", 7075 device_xname(sc->sc_dev), i)); 7076 7077 wm_cdrxsync(rxq, i,BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 7078 7079 status = rxq->rxq_descs[i].wrx_status; 7080 errors = rxq->rxq_descs[i].wrx_errors; 7081 len = le16toh(rxq->rxq_descs[i].wrx_len); 7082 vlantag = rxq->rxq_descs[i].wrx_special; 7083 7084 if ((status & WRX_ST_DD) == 0) { 7085 /* We have processed all of the receive descriptors. */ 7086 wm_cdrxsync(rxq, i, BUS_DMASYNC_PREREAD); 7087 break; 7088 } 7089 7090 count++; 7091 if (__predict_false(rxq->rxq_discard)) { 7092 DPRINTF(WM_DEBUG_RX, 7093 ("%s: RX: discarding contents of descriptor %d\n", 7094 device_xname(sc->sc_dev), i)); 7095 wm_init_rxdesc(rxq, i); 7096 if (status & WRX_ST_EOP) { 7097 /* Reset our state. */ 7098 DPRINTF(WM_DEBUG_RX, 7099 ("%s: RX: resetting rxdiscard -> 0\n", 7100 device_xname(sc->sc_dev))); 7101 rxq->rxq_discard = 0; 7102 } 7103 continue; 7104 } 7105 7106 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 7107 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 7108 7109 m = rxs->rxs_mbuf; 7110 7111 /* 7112 * Add a new receive buffer to the ring, unless of 7113 * course the length is zero. Treat the latter as a 7114 * failed mapping. 7115 */ 7116 if ((len == 0) || (wm_add_rxbuf(rxq, i) != 0)) { 7117 /* 7118 * Failed, throw away what we've done so 7119 * far, and discard the rest of the packet. 7120 */ 7121 ifp->if_ierrors++; 7122 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 7123 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 7124 wm_init_rxdesc(rxq, i); 7125 if ((status & WRX_ST_EOP) == 0) 7126 rxq->rxq_discard = 1; 7127 if (rxq->rxq_head != NULL) 7128 m_freem(rxq->rxq_head); 7129 WM_RXCHAIN_RESET(rxq); 7130 DPRINTF(WM_DEBUG_RX, 7131 ("%s: RX: Rx buffer allocation failed, " 7132 "dropping packet%s\n", device_xname(sc->sc_dev), 7133 rxq->rxq_discard ? " (discard)" : "")); 7134 continue; 7135 } 7136 7137 m->m_len = len; 7138 rxq->rxq_len += len; 7139 DPRINTF(WM_DEBUG_RX, 7140 ("%s: RX: buffer at %p len %d\n", 7141 device_xname(sc->sc_dev), m->m_data, len)); 7142 7143 /* If this is not the end of the packet, keep looking. */ 7144 if ((status & WRX_ST_EOP) == 0) { 7145 WM_RXCHAIN_LINK(rxq, m); 7146 DPRINTF(WM_DEBUG_RX, 7147 ("%s: RX: not yet EOP, rxlen -> %d\n", 7148 device_xname(sc->sc_dev), rxq->rxq_len)); 7149 continue; 7150 } 7151 7152 /* 7153 * Okay, we have the entire packet now. The chip is 7154 * configured to include the FCS except I350 and I21[01] 7155 * (not all chips can be configured to strip it), 7156 * so we need to trim it. 7157 * May need to adjust length of previous mbuf in the 7158 * chain if the current mbuf is too short. 7159 * For an eratta, the RCTL_SECRC bit in RCTL register 7160 * is always set in I350, so we don't trim it. 7161 */ 7162 if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I354) 7163 && (sc->sc_type != WM_T_I210) 7164 && (sc->sc_type != WM_T_I211)) { 7165 if (m->m_len < ETHER_CRC_LEN) { 7166 rxq->rxq_tail->m_len 7167 -= (ETHER_CRC_LEN - m->m_len); 7168 m->m_len = 0; 7169 } else 7170 m->m_len -= ETHER_CRC_LEN; 7171 len = rxq->rxq_len - ETHER_CRC_LEN; 7172 } else 7173 len = rxq->rxq_len; 7174 7175 WM_RXCHAIN_LINK(rxq, m); 7176 7177 *rxq->rxq_tailp = NULL; 7178 m = rxq->rxq_head; 7179 7180 WM_RXCHAIN_RESET(rxq); 7181 7182 DPRINTF(WM_DEBUG_RX, 7183 ("%s: RX: have entire packet, len -> %d\n", 7184 device_xname(sc->sc_dev), len)); 7185 7186 /* If an error occurred, update stats and drop the packet. */ 7187 if (errors & 7188 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 7189 if (errors & WRX_ER_SE) 7190 log(LOG_WARNING, "%s: symbol error\n", 7191 device_xname(sc->sc_dev)); 7192 else if (errors & WRX_ER_SEQ) 7193 log(LOG_WARNING, "%s: receive sequence error\n", 7194 device_xname(sc->sc_dev)); 7195 else if (errors & WRX_ER_CE) 7196 log(LOG_WARNING, "%s: CRC error\n", 7197 device_xname(sc->sc_dev)); 7198 m_freem(m); 7199 continue; 7200 } 7201 7202 /* No errors. Receive the packet. */ 7203 m->m_pkthdr.rcvif = ifp; 7204 m->m_pkthdr.len = len; 7205 7206 /* 7207 * If VLANs are enabled, VLAN packets have been unwrapped 7208 * for us. Associate the tag with the packet. 7209 */ 7210 /* XXXX should check for i350 and i354 */ 7211 if ((status & WRX_ST_VP) != 0) { 7212 VLAN_INPUT_TAG(ifp, m, le16toh(vlantag), continue); 7213 } 7214 7215 /* Set up checksum info for this packet. */ 7216 if ((status & WRX_ST_IXSM) == 0) { 7217 if (status & WRX_ST_IPCS) { 7218 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 7219 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 7220 if (errors & WRX_ER_IPE) 7221 m->m_pkthdr.csum_flags |= 7222 M_CSUM_IPv4_BAD; 7223 } 7224 if (status & WRX_ST_TCPCS) { 7225 /* 7226 * Note: we don't know if this was TCP or UDP, 7227 * so we just set both bits, and expect the 7228 * upper layers to deal. 7229 */ 7230 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 7231 m->m_pkthdr.csum_flags |= 7232 M_CSUM_TCPv4 | M_CSUM_UDPv4 | 7233 M_CSUM_TCPv6 | M_CSUM_UDPv6; 7234 if (errors & WRX_ER_TCPE) 7235 m->m_pkthdr.csum_flags |= 7236 M_CSUM_TCP_UDP_BAD; 7237 } 7238 } 7239 7240 ifp->if_ipackets++; 7241 7242 WM_RX_UNLOCK(rxq); 7243 7244 /* Pass this up to any BPF listeners. */ 7245 bpf_mtap(ifp, m); 7246 7247 /* Pass it on. */ 7248 if_percpuq_enqueue(sc->sc_ipq, m); 7249 7250 WM_RX_LOCK(rxq); 7251 7252 if (sc->sc_stopping) 7253 break; 7254 } 7255 7256 /* Update the receive pointer. */ 7257 rxq->rxq_ptr = i; 7258 if (count != 0) 7259 rnd_add_uint32(&sc->rnd_source, count); 7260 7261 DPRINTF(WM_DEBUG_RX, 7262 ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i)); 7263 } 7264 7265 /* 7266 * wm_linkintr_gmii: 7267 * 7268 * Helper; handle link interrupts for GMII. 7269 */ 7270 static void 7271 wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr) 7272 { 7273 7274 KASSERT(WM_CORE_LOCKED(sc)); 7275 7276 DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev), 7277 __func__)); 7278 7279 if (icr & ICR_LSC) { 7280 uint32_t status = CSR_READ(sc, WMREG_STATUS); 7281 7282 if ((sc->sc_type == WM_T_ICH8) && ((status & STATUS_LU) == 0)) 7283 wm_gig_downshift_workaround_ich8lan(sc); 7284 7285 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> mii_pollstat\n", 7286 device_xname(sc->sc_dev))); 7287 mii_pollstat(&sc->sc_mii); 7288 if (sc->sc_type == WM_T_82543) { 7289 int miistatus, active; 7290 7291 /* 7292 * With 82543, we need to force speed and 7293 * duplex on the MAC equal to what the PHY 7294 * speed and duplex configuration is. 7295 */ 7296 miistatus = sc->sc_mii.mii_media_status; 7297 7298 if (miistatus & IFM_ACTIVE) { 7299 active = sc->sc_mii.mii_media_active; 7300 sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD); 7301 switch (IFM_SUBTYPE(active)) { 7302 case IFM_10_T: 7303 sc->sc_ctrl |= CTRL_SPEED_10; 7304 break; 7305 case IFM_100_TX: 7306 sc->sc_ctrl |= CTRL_SPEED_100; 7307 break; 7308 case IFM_1000_T: 7309 sc->sc_ctrl |= CTRL_SPEED_1000; 7310 break; 7311 default: 7312 /* 7313 * fiber? 7314 * Shoud not enter here. 7315 */ 7316 printf("unknown media (%x)\n", active); 7317 break; 7318 } 7319 if (active & IFM_FDX) 7320 sc->sc_ctrl |= CTRL_FD; 7321 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7322 } 7323 } else if ((sc->sc_type == WM_T_ICH8) 7324 && (sc->sc_phytype == WMPHY_IGP_3)) { 7325 wm_kmrn_lock_loss_workaround_ich8lan(sc); 7326 } else if (sc->sc_type == WM_T_PCH) { 7327 wm_k1_gig_workaround_hv(sc, 7328 ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0)); 7329 } 7330 7331 if ((sc->sc_phytype == WMPHY_82578) 7332 && (IFM_SUBTYPE(sc->sc_mii.mii_media_active) 7333 == IFM_1000_T)) { 7334 7335 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0) { 7336 delay(200*1000); /* XXX too big */ 7337 7338 /* Link stall fix for link up */ 7339 wm_gmii_hv_writereg(sc->sc_dev, 1, 7340 HV_MUX_DATA_CTRL, 7341 HV_MUX_DATA_CTRL_GEN_TO_MAC 7342 | HV_MUX_DATA_CTRL_FORCE_SPEED); 7343 wm_gmii_hv_writereg(sc->sc_dev, 1, 7344 HV_MUX_DATA_CTRL, 7345 HV_MUX_DATA_CTRL_GEN_TO_MAC); 7346 } 7347 } 7348 } else if (icr & ICR_RXSEQ) { 7349 DPRINTF(WM_DEBUG_LINK, ("%s: LINK Receive sequence error\n", 7350 device_xname(sc->sc_dev))); 7351 } 7352 } 7353 7354 /* 7355 * wm_linkintr_tbi: 7356 * 7357 * Helper; handle link interrupts for TBI mode. 7358 */ 7359 static void 7360 wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr) 7361 { 7362 uint32_t status; 7363 7364 DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev), 7365 __func__)); 7366 7367 status = CSR_READ(sc, WMREG_STATUS); 7368 if (icr & ICR_LSC) { 7369 if (status & STATUS_LU) { 7370 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 7371 device_xname(sc->sc_dev), 7372 (status & STATUS_FD) ? "FDX" : "HDX")); 7373 /* 7374 * NOTE: CTRL will update TFCE and RFCE automatically, 7375 * so we should update sc->sc_ctrl 7376 */ 7377 7378 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL); 7379 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 7380 sc->sc_fcrtl &= ~FCRTL_XONE; 7381 if (status & STATUS_FD) 7382 sc->sc_tctl |= 7383 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 7384 else 7385 sc->sc_tctl |= 7386 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 7387 if (sc->sc_ctrl & CTRL_TFCE) 7388 sc->sc_fcrtl |= FCRTL_XONE; 7389 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 7390 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 7391 WMREG_OLD_FCRTL : WMREG_FCRTL, 7392 sc->sc_fcrtl); 7393 sc->sc_tbi_linkup = 1; 7394 } else { 7395 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 7396 device_xname(sc->sc_dev))); 7397 sc->sc_tbi_linkup = 0; 7398 } 7399 /* Update LED */ 7400 wm_tbi_serdes_set_linkled(sc); 7401 } else if (icr & ICR_RXSEQ) { 7402 DPRINTF(WM_DEBUG_LINK, 7403 ("%s: LINK: Receive sequence error\n", 7404 device_xname(sc->sc_dev))); 7405 } 7406 } 7407 7408 /* 7409 * wm_linkintr_serdes: 7410 * 7411 * Helper; handle link interrupts for TBI mode. 7412 */ 7413 static void 7414 wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr) 7415 { 7416 struct mii_data *mii = &sc->sc_mii; 7417 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 7418 uint32_t pcs_adv, pcs_lpab, reg; 7419 7420 DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev), 7421 __func__)); 7422 7423 if (icr & ICR_LSC) { 7424 /* Check PCS */ 7425 reg = CSR_READ(sc, WMREG_PCS_LSTS); 7426 if ((reg & PCS_LSTS_LINKOK) != 0) { 7427 mii->mii_media_status |= IFM_ACTIVE; 7428 sc->sc_tbi_linkup = 1; 7429 } else { 7430 mii->mii_media_status |= IFM_NONE; 7431 sc->sc_tbi_linkup = 0; 7432 wm_tbi_serdes_set_linkled(sc); 7433 return; 7434 } 7435 mii->mii_media_active |= IFM_1000_SX; 7436 if ((reg & PCS_LSTS_FDX) != 0) 7437 mii->mii_media_active |= IFM_FDX; 7438 else 7439 mii->mii_media_active |= IFM_HDX; 7440 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 7441 /* Check flow */ 7442 reg = CSR_READ(sc, WMREG_PCS_LSTS); 7443 if ((reg & PCS_LSTS_AN_COMP) == 0) { 7444 DPRINTF(WM_DEBUG_LINK, 7445 ("XXX LINKOK but not ACOMP\n")); 7446 return; 7447 } 7448 pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV); 7449 pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB); 7450 DPRINTF(WM_DEBUG_LINK, 7451 ("XXX AN result %08x, %08x\n", pcs_adv, pcs_lpab)); 7452 if ((pcs_adv & TXCW_SYM_PAUSE) 7453 && (pcs_lpab & TXCW_SYM_PAUSE)) { 7454 mii->mii_media_active |= IFM_FLOW 7455 | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 7456 } else if (((pcs_adv & TXCW_SYM_PAUSE) == 0) 7457 && (pcs_adv & TXCW_ASYM_PAUSE) 7458 && (pcs_lpab & TXCW_SYM_PAUSE) 7459 && (pcs_lpab & TXCW_ASYM_PAUSE)) 7460 mii->mii_media_active |= IFM_FLOW 7461 | IFM_ETH_TXPAUSE; 7462 else if ((pcs_adv & TXCW_SYM_PAUSE) 7463 && (pcs_adv & TXCW_ASYM_PAUSE) 7464 && ((pcs_lpab & TXCW_SYM_PAUSE) == 0) 7465 && (pcs_lpab & TXCW_ASYM_PAUSE)) 7466 mii->mii_media_active |= IFM_FLOW 7467 | IFM_ETH_RXPAUSE; 7468 } 7469 /* Update LED */ 7470 wm_tbi_serdes_set_linkled(sc); 7471 } else { 7472 DPRINTF(WM_DEBUG_LINK, 7473 ("%s: LINK: Receive sequence error\n", 7474 device_xname(sc->sc_dev))); 7475 } 7476 } 7477 7478 /* 7479 * wm_linkintr: 7480 * 7481 * Helper; handle link interrupts. 7482 */ 7483 static void 7484 wm_linkintr(struct wm_softc *sc, uint32_t icr) 7485 { 7486 7487 KASSERT(WM_CORE_LOCKED(sc)); 7488 7489 if (sc->sc_flags & WM_F_HAS_MII) 7490 wm_linkintr_gmii(sc, icr); 7491 else if ((sc->sc_mediatype == WM_MEDIATYPE_SERDES) 7492 && (sc->sc_type >= WM_T_82575)) 7493 wm_linkintr_serdes(sc, icr); 7494 else 7495 wm_linkintr_tbi(sc, icr); 7496 } 7497 7498 /* 7499 * wm_intr_legacy: 7500 * 7501 * Interrupt service routine for INTx and MSI. 7502 */ 7503 static int 7504 wm_intr_legacy(void *arg) 7505 { 7506 struct wm_softc *sc = arg; 7507 struct wm_txqueue *txq = &sc->sc_txq[0]; 7508 struct wm_rxqueue *rxq = &sc->sc_rxq[0]; 7509 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 7510 uint32_t icr, rndval = 0; 7511 int handled = 0; 7512 7513 DPRINTF(WM_DEBUG_TX, 7514 ("%s: INTx: got intr\n", device_xname(sc->sc_dev))); 7515 while (1 /* CONSTCOND */) { 7516 icr = CSR_READ(sc, WMREG_ICR); 7517 if ((icr & sc->sc_icr) == 0) 7518 break; 7519 if (rndval == 0) 7520 rndval = icr; 7521 7522 WM_RX_LOCK(rxq); 7523 7524 if (sc->sc_stopping) { 7525 WM_RX_UNLOCK(rxq); 7526 break; 7527 } 7528 7529 handled = 1; 7530 7531 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 7532 if (icr & (ICR_RXDMT0 | ICR_RXT0)) { 7533 DPRINTF(WM_DEBUG_RX, 7534 ("%s: RX: got Rx intr 0x%08x\n", 7535 device_xname(sc->sc_dev), 7536 icr & (ICR_RXDMT0 | ICR_RXT0))); 7537 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 7538 } 7539 #endif 7540 wm_rxeof(rxq); 7541 7542 WM_RX_UNLOCK(rxq); 7543 WM_TX_LOCK(txq); 7544 7545 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 7546 if (icr & ICR_TXDW) { 7547 DPRINTF(WM_DEBUG_TX, 7548 ("%s: TX: got TXDW interrupt\n", 7549 device_xname(sc->sc_dev))); 7550 WM_EVCNT_INCR(&sc->sc_ev_txdw); 7551 } 7552 #endif 7553 wm_txeof(sc); 7554 7555 WM_TX_UNLOCK(txq); 7556 WM_CORE_LOCK(sc); 7557 7558 if (icr & (ICR_LSC | ICR_RXSEQ)) { 7559 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 7560 wm_linkintr(sc, icr); 7561 } 7562 7563 WM_CORE_UNLOCK(sc); 7564 7565 if (icr & ICR_RXO) { 7566 #if defined(WM_DEBUG) 7567 log(LOG_WARNING, "%s: Receive overrun\n", 7568 device_xname(sc->sc_dev)); 7569 #endif /* defined(WM_DEBUG) */ 7570 } 7571 } 7572 7573 rnd_add_uint32(&sc->rnd_source, rndval); 7574 7575 if (handled) { 7576 /* Try to get more packets going. */ 7577 ifp->if_start(ifp); 7578 } 7579 7580 return handled; 7581 } 7582 7583 /* 7584 * wm_txintr_msix: 7585 * 7586 * Interrupt service routine for TX complete interrupt for MSI-X. 7587 */ 7588 static int 7589 wm_txintr_msix(void *arg) 7590 { 7591 struct wm_txqueue *txq = arg; 7592 struct wm_softc *sc = txq->txq_sc; 7593 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 7594 int handled = 0; 7595 7596 DPRINTF(WM_DEBUG_TX, 7597 ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev))); 7598 7599 if (sc->sc_type == WM_T_82574) 7600 CSR_WRITE(sc, WMREG_IMC, ICR_TXQ(txq->txq_id)); 7601 else if (sc->sc_type == WM_T_82575) 7602 CSR_WRITE(sc, WMREG_EIMC, EITR_TX_QUEUE(txq->txq_id)); 7603 else 7604 CSR_WRITE(sc, WMREG_EIMC, 1 << txq->txq_intr_idx); 7605 7606 WM_TX_LOCK(txq); 7607 7608 if (sc->sc_stopping) 7609 goto out; 7610 7611 WM_EVCNT_INCR(&sc->sc_ev_txdw); 7612 handled = wm_txeof(sc); 7613 7614 out: 7615 WM_TX_UNLOCK(txq); 7616 7617 if (sc->sc_type == WM_T_82574) 7618 CSR_WRITE(sc, WMREG_IMS, ICR_TXQ(txq->txq_id)); 7619 else if (sc->sc_type == WM_T_82575) 7620 CSR_WRITE(sc, WMREG_EIMS, EITR_TX_QUEUE(txq->txq_id)); 7621 else 7622 CSR_WRITE(sc, WMREG_EIMS, 1 << txq->txq_intr_idx); 7623 7624 if (handled) { 7625 /* Try to get more packets going. */ 7626 ifp->if_start(ifp); 7627 } 7628 7629 return handled; 7630 } 7631 7632 /* 7633 * wm_rxintr_msix: 7634 * 7635 * Interrupt service routine for RX interrupt for MSI-X. 7636 */ 7637 static int 7638 wm_rxintr_msix(void *arg) 7639 { 7640 struct wm_rxqueue *rxq = arg; 7641 struct wm_softc *sc = rxq->rxq_sc; 7642 7643 DPRINTF(WM_DEBUG_RX, 7644 ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev))); 7645 7646 if (sc->sc_type == WM_T_82574) 7647 CSR_WRITE(sc, WMREG_IMC, ICR_RXQ(rxq->rxq_id)); 7648 else if (sc->sc_type == WM_T_82575) 7649 CSR_WRITE(sc, WMREG_EIMC, EITR_RX_QUEUE(rxq->rxq_id)); 7650 else 7651 CSR_WRITE(sc, WMREG_EIMC, 1 << rxq->rxq_intr_idx); 7652 7653 WM_RX_LOCK(rxq); 7654 7655 if (sc->sc_stopping) 7656 goto out; 7657 7658 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 7659 wm_rxeof(rxq); 7660 7661 out: 7662 WM_RX_UNLOCK(rxq); 7663 7664 if (sc->sc_type == WM_T_82574) 7665 CSR_WRITE(sc, WMREG_IMS, ICR_RXQ(rxq->rxq_id)); 7666 else if (sc->sc_type == WM_T_82575) 7667 CSR_WRITE(sc, WMREG_EIMS, EITR_RX_QUEUE(rxq->rxq_id)); 7668 else 7669 CSR_WRITE(sc, WMREG_EIMS, 1 << rxq->rxq_intr_idx); 7670 7671 return 1; 7672 } 7673 7674 /* 7675 * wm_linkintr_msix: 7676 * 7677 * Interrupt service routine for link status change for MSI-X. 7678 */ 7679 static int 7680 wm_linkintr_msix(void *arg) 7681 { 7682 struct wm_softc *sc = arg; 7683 uint32_t reg; 7684 7685 DPRINTF(WM_DEBUG_LINK, 7686 ("%s: LINK: got link intr\n", device_xname(sc->sc_dev))); 7687 7688 reg = CSR_READ(sc, WMREG_ICR); 7689 WM_CORE_LOCK(sc); 7690 if ((sc->sc_stopping) || ((reg & ICR_LSC) == 0)) 7691 goto out; 7692 7693 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 7694 wm_linkintr(sc, ICR_LSC); 7695 7696 out: 7697 WM_CORE_UNLOCK(sc); 7698 7699 if (sc->sc_type == WM_T_82574) 7700 CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC); 7701 else if (sc->sc_type == WM_T_82575) 7702 CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER); 7703 else 7704 CSR_WRITE(sc, WMREG_EIMS, 1 << sc->sc_link_intr_idx); 7705 7706 return 1; 7707 } 7708 7709 /* 7710 * Media related. 7711 * GMII, SGMII, TBI (and SERDES) 7712 */ 7713 7714 /* Common */ 7715 7716 /* 7717 * wm_tbi_serdes_set_linkled: 7718 * 7719 * Update the link LED on TBI and SERDES devices. 7720 */ 7721 static void 7722 wm_tbi_serdes_set_linkled(struct wm_softc *sc) 7723 { 7724 7725 if (sc->sc_tbi_linkup) 7726 sc->sc_ctrl |= CTRL_SWDPIN(0); 7727 else 7728 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 7729 7730 /* 82540 or newer devices are active low */ 7731 sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0; 7732 7733 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7734 } 7735 7736 /* GMII related */ 7737 7738 /* 7739 * wm_gmii_reset: 7740 * 7741 * Reset the PHY. 7742 */ 7743 static void 7744 wm_gmii_reset(struct wm_softc *sc) 7745 { 7746 uint32_t reg; 7747 int rv; 7748 7749 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 7750 device_xname(sc->sc_dev), __func__)); 7751 /* get phy semaphore */ 7752 switch (sc->sc_type) { 7753 case WM_T_82571: 7754 case WM_T_82572: 7755 case WM_T_82573: 7756 case WM_T_82574: 7757 case WM_T_82583: 7758 /* XXX should get sw semaphore, too */ 7759 rv = wm_get_swsm_semaphore(sc); 7760 break; 7761 case WM_T_82575: 7762 case WM_T_82576: 7763 case WM_T_82580: 7764 case WM_T_I350: 7765 case WM_T_I354: 7766 case WM_T_I210: 7767 case WM_T_I211: 7768 case WM_T_80003: 7769 rv = wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]); 7770 break; 7771 case WM_T_ICH8: 7772 case WM_T_ICH9: 7773 case WM_T_ICH10: 7774 case WM_T_PCH: 7775 case WM_T_PCH2: 7776 case WM_T_PCH_LPT: 7777 case WM_T_PCH_SPT: 7778 rv = wm_get_swfwhw_semaphore(sc); 7779 break; 7780 default: 7781 /* nothing to do*/ 7782 rv = 0; 7783 break; 7784 } 7785 if (rv != 0) { 7786 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 7787 __func__); 7788 return; 7789 } 7790 7791 switch (sc->sc_type) { 7792 case WM_T_82542_2_0: 7793 case WM_T_82542_2_1: 7794 /* null */ 7795 break; 7796 case WM_T_82543: 7797 /* 7798 * With 82543, we need to force speed and duplex on the MAC 7799 * equal to what the PHY speed and duplex configuration is. 7800 * In addition, we need to perform a hardware reset on the PHY 7801 * to take it out of reset. 7802 */ 7803 sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX; 7804 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7805 7806 /* The PHY reset pin is active-low. */ 7807 reg = CSR_READ(sc, WMREG_CTRL_EXT); 7808 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 7809 CTRL_EXT_SWDPIN(4)); 7810 reg |= CTRL_EXT_SWDPIO(4); 7811 7812 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 7813 CSR_WRITE_FLUSH(sc); 7814 delay(10*1000); 7815 7816 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 7817 CSR_WRITE_FLUSH(sc); 7818 delay(150); 7819 #if 0 7820 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 7821 #endif 7822 delay(20*1000); /* XXX extra delay to get PHY ID? */ 7823 break; 7824 case WM_T_82544: /* reset 10000us */ 7825 case WM_T_82540: 7826 case WM_T_82545: 7827 case WM_T_82545_3: 7828 case WM_T_82546: 7829 case WM_T_82546_3: 7830 case WM_T_82541: 7831 case WM_T_82541_2: 7832 case WM_T_82547: 7833 case WM_T_82547_2: 7834 case WM_T_82571: /* reset 100us */ 7835 case WM_T_82572: 7836 case WM_T_82573: 7837 case WM_T_82574: 7838 case WM_T_82575: 7839 case WM_T_82576: 7840 case WM_T_82580: 7841 case WM_T_I350: 7842 case WM_T_I354: 7843 case WM_T_I210: 7844 case WM_T_I211: 7845 case WM_T_82583: 7846 case WM_T_80003: 7847 /* generic reset */ 7848 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 7849 CSR_WRITE_FLUSH(sc); 7850 delay(20000); 7851 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7852 CSR_WRITE_FLUSH(sc); 7853 delay(20000); 7854 7855 if ((sc->sc_type == WM_T_82541) 7856 || (sc->sc_type == WM_T_82541_2) 7857 || (sc->sc_type == WM_T_82547) 7858 || (sc->sc_type == WM_T_82547_2)) { 7859 /* workaround for igp are done in igp_reset() */ 7860 /* XXX add code to set LED after phy reset */ 7861 } 7862 break; 7863 case WM_T_ICH8: 7864 case WM_T_ICH9: 7865 case WM_T_ICH10: 7866 case WM_T_PCH: 7867 case WM_T_PCH2: 7868 case WM_T_PCH_LPT: 7869 case WM_T_PCH_SPT: 7870 /* generic reset */ 7871 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 7872 CSR_WRITE_FLUSH(sc); 7873 delay(100); 7874 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7875 CSR_WRITE_FLUSH(sc); 7876 delay(150); 7877 break; 7878 default: 7879 panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), 7880 __func__); 7881 break; 7882 } 7883 7884 /* release PHY semaphore */ 7885 switch (sc->sc_type) { 7886 case WM_T_82571: 7887 case WM_T_82572: 7888 case WM_T_82573: 7889 case WM_T_82574: 7890 case WM_T_82583: 7891 /* XXX should put sw semaphore, too */ 7892 wm_put_swsm_semaphore(sc); 7893 break; 7894 case WM_T_82575: 7895 case WM_T_82576: 7896 case WM_T_82580: 7897 case WM_T_I350: 7898 case WM_T_I354: 7899 case WM_T_I210: 7900 case WM_T_I211: 7901 case WM_T_80003: 7902 wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]); 7903 break; 7904 case WM_T_ICH8: 7905 case WM_T_ICH9: 7906 case WM_T_ICH10: 7907 case WM_T_PCH: 7908 case WM_T_PCH2: 7909 case WM_T_PCH_LPT: 7910 case WM_T_PCH_SPT: 7911 wm_put_swfwhw_semaphore(sc); 7912 break; 7913 default: 7914 /* nothing to do */ 7915 rv = 0; 7916 break; 7917 } 7918 7919 /* get_cfg_done */ 7920 wm_get_cfg_done(sc); 7921 7922 /* extra setup */ 7923 switch (sc->sc_type) { 7924 case WM_T_82542_2_0: 7925 case WM_T_82542_2_1: 7926 case WM_T_82543: 7927 case WM_T_82544: 7928 case WM_T_82540: 7929 case WM_T_82545: 7930 case WM_T_82545_3: 7931 case WM_T_82546: 7932 case WM_T_82546_3: 7933 case WM_T_82541_2: 7934 case WM_T_82547_2: 7935 case WM_T_82571: 7936 case WM_T_82572: 7937 case WM_T_82573: 7938 case WM_T_82575: 7939 case WM_T_82576: 7940 case WM_T_82580: 7941 case WM_T_I350: 7942 case WM_T_I354: 7943 case WM_T_I210: 7944 case WM_T_I211: 7945 case WM_T_80003: 7946 /* null */ 7947 break; 7948 case WM_T_82574: 7949 case WM_T_82583: 7950 wm_lplu_d0_disable(sc); 7951 break; 7952 case WM_T_82541: 7953 case WM_T_82547: 7954 /* XXX Configure actively LED after PHY reset */ 7955 break; 7956 case WM_T_ICH8: 7957 case WM_T_ICH9: 7958 case WM_T_ICH10: 7959 case WM_T_PCH: 7960 case WM_T_PCH2: 7961 case WM_T_PCH_LPT: 7962 case WM_T_PCH_SPT: 7963 /* Allow time for h/w to get to a quiescent state afer reset */ 7964 delay(10*1000); 7965 7966 if (sc->sc_type == WM_T_PCH) 7967 wm_hv_phy_workaround_ich8lan(sc); 7968 7969 if (sc->sc_type == WM_T_PCH2) 7970 wm_lv_phy_workaround_ich8lan(sc); 7971 7972 if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)) { 7973 /* 7974 * dummy read to clear the phy wakeup bit after lcd 7975 * reset 7976 */ 7977 reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC); 7978 } 7979 7980 /* 7981 * XXX Configure the LCD with th extended configuration region 7982 * in NVM 7983 */ 7984 7985 /* Disable D0 LPLU. */ 7986 if (sc->sc_type >= WM_T_PCH) /* PCH* */ 7987 wm_lplu_d0_disable_pch(sc); 7988 else 7989 wm_lplu_d0_disable(sc); /* ICH* */ 7990 break; 7991 default: 7992 panic("%s: unknown type\n", __func__); 7993 break; 7994 } 7995 } 7996 7997 /* 7998 * wm_get_phy_id_82575: 7999 * 8000 * Return PHY ID. Return -1 if it failed. 8001 */ 8002 static int 8003 wm_get_phy_id_82575(struct wm_softc *sc) 8004 { 8005 uint32_t reg; 8006 int phyid = -1; 8007 8008 /* XXX */ 8009 if ((sc->sc_flags & WM_F_SGMII) == 0) 8010 return -1; 8011 8012 if (wm_sgmii_uses_mdio(sc)) { 8013 switch (sc->sc_type) { 8014 case WM_T_82575: 8015 case WM_T_82576: 8016 reg = CSR_READ(sc, WMREG_MDIC); 8017 phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT; 8018 break; 8019 case WM_T_82580: 8020 case WM_T_I350: 8021 case WM_T_I354: 8022 case WM_T_I210: 8023 case WM_T_I211: 8024 reg = CSR_READ(sc, WMREG_MDICNFG); 8025 phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT; 8026 break; 8027 default: 8028 return -1; 8029 } 8030 } 8031 8032 return phyid; 8033 } 8034 8035 8036 /* 8037 * wm_gmii_mediainit: 8038 * 8039 * Initialize media for use on 1000BASE-T devices. 8040 */ 8041 static void 8042 wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid) 8043 { 8044 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 8045 struct mii_data *mii = &sc->sc_mii; 8046 uint32_t reg; 8047 8048 /* We have GMII. */ 8049 sc->sc_flags |= WM_F_HAS_MII; 8050 8051 if (sc->sc_type == WM_T_80003) 8052 sc->sc_tipg = TIPG_1000T_80003_DFLT; 8053 else 8054 sc->sc_tipg = TIPG_1000T_DFLT; 8055 8056 /* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */ 8057 if ((sc->sc_type == WM_T_82580) 8058 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210) 8059 || (sc->sc_type == WM_T_I211)) { 8060 reg = CSR_READ(sc, WMREG_PHPM); 8061 reg &= ~PHPM_GO_LINK_D; 8062 CSR_WRITE(sc, WMREG_PHPM, reg); 8063 } 8064 8065 /* 8066 * Let the chip set speed/duplex on its own based on 8067 * signals from the PHY. 8068 * XXXbouyer - I'm not sure this is right for the 80003, 8069 * the em driver only sets CTRL_SLU here - but it seems to work. 8070 */ 8071 sc->sc_ctrl |= CTRL_SLU; 8072 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 8073 8074 /* Initialize our media structures and probe the GMII. */ 8075 mii->mii_ifp = ifp; 8076 8077 /* 8078 * Determine the PHY access method. 8079 * 8080 * For SGMII, use SGMII specific method. 8081 * 8082 * For some devices, we can determine the PHY access method 8083 * from sc_type. 8084 * 8085 * For ICH and PCH variants, it's difficult to determine the PHY 8086 * access method by sc_type, so use the PCI product ID for some 8087 * devices. 8088 * For other ICH8 variants, try to use igp's method. If the PHY 8089 * can't detect, then use bm's method. 8090 */ 8091 switch (prodid) { 8092 case PCI_PRODUCT_INTEL_PCH_M_LM: 8093 case PCI_PRODUCT_INTEL_PCH_M_LC: 8094 /* 82577 */ 8095 sc->sc_phytype = WMPHY_82577; 8096 break; 8097 case PCI_PRODUCT_INTEL_PCH_D_DM: 8098 case PCI_PRODUCT_INTEL_PCH_D_DC: 8099 /* 82578 */ 8100 sc->sc_phytype = WMPHY_82578; 8101 break; 8102 case PCI_PRODUCT_INTEL_PCH2_LV_LM: 8103 case PCI_PRODUCT_INTEL_PCH2_LV_V: 8104 /* 82579 */ 8105 sc->sc_phytype = WMPHY_82579; 8106 break; 8107 case PCI_PRODUCT_INTEL_82801I_BM: 8108 case PCI_PRODUCT_INTEL_82801J_R_BM_LM: 8109 case PCI_PRODUCT_INTEL_82801J_R_BM_LF: 8110 case PCI_PRODUCT_INTEL_82801J_D_BM_LM: 8111 case PCI_PRODUCT_INTEL_82801J_D_BM_LF: 8112 case PCI_PRODUCT_INTEL_82801J_R_BM_V: 8113 /* 82567 */ 8114 sc->sc_phytype = WMPHY_BM; 8115 mii->mii_readreg = wm_gmii_bm_readreg; 8116 mii->mii_writereg = wm_gmii_bm_writereg; 8117 break; 8118 default: 8119 if (((sc->sc_flags & WM_F_SGMII) != 0) 8120 && !wm_sgmii_uses_mdio(sc)){ 8121 /* SGMII */ 8122 mii->mii_readreg = wm_sgmii_readreg; 8123 mii->mii_writereg = wm_sgmii_writereg; 8124 } else if (sc->sc_type >= WM_T_80003) { 8125 /* 80003 */ 8126 mii->mii_readreg = wm_gmii_i80003_readreg; 8127 mii->mii_writereg = wm_gmii_i80003_writereg; 8128 } else if (sc->sc_type >= WM_T_I210) { 8129 /* I210 and I211 */ 8130 mii->mii_readreg = wm_gmii_gs40g_readreg; 8131 mii->mii_writereg = wm_gmii_gs40g_writereg; 8132 } else if (sc->sc_type >= WM_T_82580) { 8133 /* 82580, I350 and I354 */ 8134 sc->sc_phytype = WMPHY_82580; 8135 mii->mii_readreg = wm_gmii_82580_readreg; 8136 mii->mii_writereg = wm_gmii_82580_writereg; 8137 } else if (sc->sc_type >= WM_T_82544) { 8138 /* 82544, 0, [56], [17], 8257[1234] and 82583 */ 8139 mii->mii_readreg = wm_gmii_i82544_readreg; 8140 mii->mii_writereg = wm_gmii_i82544_writereg; 8141 } else { 8142 mii->mii_readreg = wm_gmii_i82543_readreg; 8143 mii->mii_writereg = wm_gmii_i82543_writereg; 8144 } 8145 break; 8146 } 8147 if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_SPT)) { 8148 /* All PCH* use _hv_ */ 8149 mii->mii_readreg = wm_gmii_hv_readreg; 8150 mii->mii_writereg = wm_gmii_hv_writereg; 8151 } 8152 mii->mii_statchg = wm_gmii_statchg; 8153 8154 wm_gmii_reset(sc); 8155 8156 sc->sc_ethercom.ec_mii = &sc->sc_mii; 8157 ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange, 8158 wm_gmii_mediastatus); 8159 8160 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) 8161 || (sc->sc_type == WM_T_82580) 8162 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) 8163 || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) { 8164 if ((sc->sc_flags & WM_F_SGMII) == 0) { 8165 /* Attach only one port */ 8166 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, 8167 MII_OFFSET_ANY, MIIF_DOPAUSE); 8168 } else { 8169 int i, id; 8170 uint32_t ctrl_ext; 8171 8172 id = wm_get_phy_id_82575(sc); 8173 if (id != -1) { 8174 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 8175 id, MII_OFFSET_ANY, MIIF_DOPAUSE); 8176 } 8177 if ((id == -1) 8178 || (LIST_FIRST(&mii->mii_phys) == NULL)) { 8179 /* Power on sgmii phy if it is disabled */ 8180 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT); 8181 CSR_WRITE(sc, WMREG_CTRL_EXT, 8182 ctrl_ext &~ CTRL_EXT_SWDPIN(3)); 8183 CSR_WRITE_FLUSH(sc); 8184 delay(300*1000); /* XXX too long */ 8185 8186 /* from 1 to 8 */ 8187 for (i = 1; i < 8; i++) 8188 mii_attach(sc->sc_dev, &sc->sc_mii, 8189 0xffffffff, i, MII_OFFSET_ANY, 8190 MIIF_DOPAUSE); 8191 8192 /* restore previous sfp cage power state */ 8193 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext); 8194 } 8195 } 8196 } else { 8197 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 8198 MII_OFFSET_ANY, MIIF_DOPAUSE); 8199 } 8200 8201 /* 8202 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call 8203 * wm_set_mdio_slow_mode_hv() for a workaround and retry. 8204 */ 8205 if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) && 8206 (LIST_FIRST(&mii->mii_phys) == NULL)) { 8207 wm_set_mdio_slow_mode_hv(sc); 8208 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 8209 MII_OFFSET_ANY, MIIF_DOPAUSE); 8210 } 8211 8212 /* 8213 * (For ICH8 variants) 8214 * If PHY detection failed, use BM's r/w function and retry. 8215 */ 8216 if (LIST_FIRST(&mii->mii_phys) == NULL) { 8217 /* if failed, retry with *_bm_* */ 8218 mii->mii_readreg = wm_gmii_bm_readreg; 8219 mii->mii_writereg = wm_gmii_bm_writereg; 8220 8221 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 8222 MII_OFFSET_ANY, MIIF_DOPAUSE); 8223 } 8224 8225 if (LIST_FIRST(&mii->mii_phys) == NULL) { 8226 /* Any PHY wasn't find */ 8227 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 8228 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 8229 sc->sc_phytype = WMPHY_NONE; 8230 } else { 8231 /* 8232 * PHY Found! 8233 * Check PHY type. 8234 */ 8235 uint32_t model; 8236 struct mii_softc *child; 8237 8238 child = LIST_FIRST(&mii->mii_phys); 8239 model = child->mii_mpd_model; 8240 if (model == MII_MODEL_yyINTEL_I82566) 8241 sc->sc_phytype = WMPHY_IGP_3; 8242 8243 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 8244 } 8245 } 8246 8247 /* 8248 * wm_gmii_mediachange: [ifmedia interface function] 8249 * 8250 * Set hardware to newly-selected media on a 1000BASE-T device. 8251 */ 8252 static int 8253 wm_gmii_mediachange(struct ifnet *ifp) 8254 { 8255 struct wm_softc *sc = ifp->if_softc; 8256 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 8257 int rc; 8258 8259 if ((ifp->if_flags & IFF_UP) == 0) 8260 return 0; 8261 8262 sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD); 8263 sc->sc_ctrl |= CTRL_SLU; 8264 if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 8265 || (sc->sc_type > WM_T_82543)) { 8266 sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX); 8267 } else { 8268 sc->sc_ctrl &= ~CTRL_ASDE; 8269 sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX; 8270 if (ife->ifm_media & IFM_FDX) 8271 sc->sc_ctrl |= CTRL_FD; 8272 switch (IFM_SUBTYPE(ife->ifm_media)) { 8273 case IFM_10_T: 8274 sc->sc_ctrl |= CTRL_SPEED_10; 8275 break; 8276 case IFM_100_TX: 8277 sc->sc_ctrl |= CTRL_SPEED_100; 8278 break; 8279 case IFM_1000_T: 8280 sc->sc_ctrl |= CTRL_SPEED_1000; 8281 break; 8282 default: 8283 panic("wm_gmii_mediachange: bad media 0x%x", 8284 ife->ifm_media); 8285 } 8286 } 8287 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 8288 if (sc->sc_type <= WM_T_82543) 8289 wm_gmii_reset(sc); 8290 8291 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 8292 return 0; 8293 return rc; 8294 } 8295 8296 /* 8297 * wm_gmii_mediastatus: [ifmedia interface function] 8298 * 8299 * Get the current interface media status on a 1000BASE-T device. 8300 */ 8301 static void 8302 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 8303 { 8304 struct wm_softc *sc = ifp->if_softc; 8305 8306 ether_mediastatus(ifp, ifmr); 8307 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) 8308 | sc->sc_flowflags; 8309 } 8310 8311 #define MDI_IO CTRL_SWDPIN(2) 8312 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 8313 #define MDI_CLK CTRL_SWDPIN(3) 8314 8315 static void 8316 wm_i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 8317 { 8318 uint32_t i, v; 8319 8320 v = CSR_READ(sc, WMREG_CTRL); 8321 v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 8322 v |= MDI_DIR | CTRL_SWDPIO(3); 8323 8324 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 8325 if (data & i) 8326 v |= MDI_IO; 8327 else 8328 v &= ~MDI_IO; 8329 CSR_WRITE(sc, WMREG_CTRL, v); 8330 CSR_WRITE_FLUSH(sc); 8331 delay(10); 8332 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 8333 CSR_WRITE_FLUSH(sc); 8334 delay(10); 8335 CSR_WRITE(sc, WMREG_CTRL, v); 8336 CSR_WRITE_FLUSH(sc); 8337 delay(10); 8338 } 8339 } 8340 8341 static uint32_t 8342 wm_i82543_mii_recvbits(struct wm_softc *sc) 8343 { 8344 uint32_t v, i, data = 0; 8345 8346 v = CSR_READ(sc, WMREG_CTRL); 8347 v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 8348 v |= CTRL_SWDPIO(3); 8349 8350 CSR_WRITE(sc, WMREG_CTRL, v); 8351 CSR_WRITE_FLUSH(sc); 8352 delay(10); 8353 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 8354 CSR_WRITE_FLUSH(sc); 8355 delay(10); 8356 CSR_WRITE(sc, WMREG_CTRL, v); 8357 CSR_WRITE_FLUSH(sc); 8358 delay(10); 8359 8360 for (i = 0; i < 16; i++) { 8361 data <<= 1; 8362 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 8363 CSR_WRITE_FLUSH(sc); 8364 delay(10); 8365 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 8366 data |= 1; 8367 CSR_WRITE(sc, WMREG_CTRL, v); 8368 CSR_WRITE_FLUSH(sc); 8369 delay(10); 8370 } 8371 8372 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 8373 CSR_WRITE_FLUSH(sc); 8374 delay(10); 8375 CSR_WRITE(sc, WMREG_CTRL, v); 8376 CSR_WRITE_FLUSH(sc); 8377 delay(10); 8378 8379 return data; 8380 } 8381 8382 #undef MDI_IO 8383 #undef MDI_DIR 8384 #undef MDI_CLK 8385 8386 /* 8387 * wm_gmii_i82543_readreg: [mii interface function] 8388 * 8389 * Read a PHY register on the GMII (i82543 version). 8390 */ 8391 static int 8392 wm_gmii_i82543_readreg(device_t self, int phy, int reg) 8393 { 8394 struct wm_softc *sc = device_private(self); 8395 int rv; 8396 8397 wm_i82543_mii_sendbits(sc, 0xffffffffU, 32); 8398 wm_i82543_mii_sendbits(sc, reg | (phy << 5) | 8399 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 8400 rv = wm_i82543_mii_recvbits(sc) & 0xffff; 8401 8402 DPRINTF(WM_DEBUG_GMII, ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 8403 device_xname(sc->sc_dev), phy, reg, rv)); 8404 8405 return rv; 8406 } 8407 8408 /* 8409 * wm_gmii_i82543_writereg: [mii interface function] 8410 * 8411 * Write a PHY register on the GMII (i82543 version). 8412 */ 8413 static void 8414 wm_gmii_i82543_writereg(device_t self, int phy, int reg, int val) 8415 { 8416 struct wm_softc *sc = device_private(self); 8417 8418 wm_i82543_mii_sendbits(sc, 0xffffffffU, 32); 8419 wm_i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 8420 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 8421 (MII_COMMAND_START << 30), 32); 8422 } 8423 8424 /* 8425 * wm_gmii_i82544_readreg: [mii interface function] 8426 * 8427 * Read a PHY register on the GMII. 8428 */ 8429 static int 8430 wm_gmii_i82544_readreg(device_t self, int phy, int reg) 8431 { 8432 struct wm_softc *sc = device_private(self); 8433 uint32_t mdic = 0; 8434 int i, rv; 8435 8436 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 8437 MDIC_REGADD(reg)); 8438 8439 for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) { 8440 mdic = CSR_READ(sc, WMREG_MDIC); 8441 if (mdic & MDIC_READY) 8442 break; 8443 delay(50); 8444 } 8445 8446 if ((mdic & MDIC_READY) == 0) { 8447 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 8448 device_xname(sc->sc_dev), phy, reg); 8449 rv = 0; 8450 } else if (mdic & MDIC_E) { 8451 #if 0 /* This is normal if no PHY is present. */ 8452 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 8453 device_xname(sc->sc_dev), phy, reg); 8454 #endif 8455 rv = 0; 8456 } else { 8457 rv = MDIC_DATA(mdic); 8458 if (rv == 0xffff) 8459 rv = 0; 8460 } 8461 8462 return rv; 8463 } 8464 8465 /* 8466 * wm_gmii_i82544_writereg: [mii interface function] 8467 * 8468 * Write a PHY register on the GMII. 8469 */ 8470 static void 8471 wm_gmii_i82544_writereg(device_t self, int phy, int reg, int val) 8472 { 8473 struct wm_softc *sc = device_private(self); 8474 uint32_t mdic = 0; 8475 int i; 8476 8477 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 8478 MDIC_REGADD(reg) | MDIC_DATA(val)); 8479 8480 for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) { 8481 mdic = CSR_READ(sc, WMREG_MDIC); 8482 if (mdic & MDIC_READY) 8483 break; 8484 delay(50); 8485 } 8486 8487 if ((mdic & MDIC_READY) == 0) 8488 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 8489 device_xname(sc->sc_dev), phy, reg); 8490 else if (mdic & MDIC_E) 8491 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 8492 device_xname(sc->sc_dev), phy, reg); 8493 } 8494 8495 /* 8496 * wm_gmii_i80003_readreg: [mii interface function] 8497 * 8498 * Read a PHY register on the kumeran 8499 * This could be handled by the PHY layer if we didn't have to lock the 8500 * ressource ... 8501 */ 8502 static int 8503 wm_gmii_i80003_readreg(device_t self, int phy, int reg) 8504 { 8505 struct wm_softc *sc = device_private(self); 8506 int sem; 8507 int rv; 8508 8509 if (phy != 1) /* only one PHY on kumeran bus */ 8510 return 0; 8511 8512 sem = swfwphysem[sc->sc_funcid]; 8513 if (wm_get_swfw_semaphore(sc, sem)) { 8514 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8515 __func__); 8516 return 0; 8517 } 8518 8519 if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 8520 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT, 8521 reg >> GG82563_PAGE_SHIFT); 8522 } else { 8523 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT, 8524 reg >> GG82563_PAGE_SHIFT); 8525 } 8526 /* Wait more 200us for a bug of the ready bit in the MDIC register */ 8527 delay(200); 8528 rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS); 8529 delay(200); 8530 8531 wm_put_swfw_semaphore(sc, sem); 8532 return rv; 8533 } 8534 8535 /* 8536 * wm_gmii_i80003_writereg: [mii interface function] 8537 * 8538 * Write a PHY register on the kumeran. 8539 * This could be handled by the PHY layer if we didn't have to lock the 8540 * ressource ... 8541 */ 8542 static void 8543 wm_gmii_i80003_writereg(device_t self, int phy, int reg, int val) 8544 { 8545 struct wm_softc *sc = device_private(self); 8546 int sem; 8547 8548 if (phy != 1) /* only one PHY on kumeran bus */ 8549 return; 8550 8551 sem = swfwphysem[sc->sc_funcid]; 8552 if (wm_get_swfw_semaphore(sc, sem)) { 8553 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8554 __func__); 8555 return; 8556 } 8557 8558 if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 8559 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT, 8560 reg >> GG82563_PAGE_SHIFT); 8561 } else { 8562 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT, 8563 reg >> GG82563_PAGE_SHIFT); 8564 } 8565 /* Wait more 200us for a bug of the ready bit in the MDIC register */ 8566 delay(200); 8567 wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val); 8568 delay(200); 8569 8570 wm_put_swfw_semaphore(sc, sem); 8571 } 8572 8573 /* 8574 * wm_gmii_bm_readreg: [mii interface function] 8575 * 8576 * Read a PHY register on the kumeran 8577 * This could be handled by the PHY layer if we didn't have to lock the 8578 * ressource ... 8579 */ 8580 static int 8581 wm_gmii_bm_readreg(device_t self, int phy, int reg) 8582 { 8583 struct wm_softc *sc = device_private(self); 8584 int sem; 8585 int rv; 8586 8587 sem = swfwphysem[sc->sc_funcid]; 8588 if (wm_get_swfw_semaphore(sc, sem)) { 8589 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8590 __func__); 8591 return 0; 8592 } 8593 8594 if (reg > BME1000_MAX_MULTI_PAGE_REG) { 8595 if (phy == 1) 8596 wm_gmii_i82544_writereg(self, phy, 8597 MII_IGPHY_PAGE_SELECT, reg); 8598 else 8599 wm_gmii_i82544_writereg(self, phy, 8600 GG82563_PHY_PAGE_SELECT, 8601 reg >> GG82563_PAGE_SHIFT); 8602 } 8603 8604 rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS); 8605 wm_put_swfw_semaphore(sc, sem); 8606 return rv; 8607 } 8608 8609 /* 8610 * wm_gmii_bm_writereg: [mii interface function] 8611 * 8612 * Write a PHY register on the kumeran. 8613 * This could be handled by the PHY layer if we didn't have to lock the 8614 * ressource ... 8615 */ 8616 static void 8617 wm_gmii_bm_writereg(device_t self, int phy, int reg, int val) 8618 { 8619 struct wm_softc *sc = device_private(self); 8620 int sem; 8621 8622 sem = swfwphysem[sc->sc_funcid]; 8623 if (wm_get_swfw_semaphore(sc, sem)) { 8624 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8625 __func__); 8626 return; 8627 } 8628 8629 if (reg > BME1000_MAX_MULTI_PAGE_REG) { 8630 if (phy == 1) 8631 wm_gmii_i82544_writereg(self, phy, 8632 MII_IGPHY_PAGE_SELECT, reg); 8633 else 8634 wm_gmii_i82544_writereg(self, phy, 8635 GG82563_PHY_PAGE_SELECT, 8636 reg >> GG82563_PAGE_SHIFT); 8637 } 8638 8639 wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val); 8640 wm_put_swfw_semaphore(sc, sem); 8641 } 8642 8643 static void 8644 wm_access_phy_wakeup_reg_bm(device_t self, int offset, int16_t *val, int rd) 8645 { 8646 struct wm_softc *sc = device_private(self); 8647 uint16_t regnum = BM_PHY_REG_NUM(offset); 8648 uint16_t wuce; 8649 8650 /* XXX Gig must be disabled for MDIO accesses to page 800 */ 8651 if (sc->sc_type == WM_T_PCH) { 8652 /* XXX e1000 driver do nothing... why? */ 8653 } 8654 8655 /* Set page 769 */ 8656 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8657 BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT); 8658 8659 wuce = wm_gmii_i82544_readreg(self, 1, BM_WUC_ENABLE_REG); 8660 8661 wuce &= ~BM_WUC_HOST_WU_BIT; 8662 wm_gmii_i82544_writereg(self, 1, BM_WUC_ENABLE_REG, 8663 wuce | BM_WUC_ENABLE_BIT); 8664 8665 /* Select page 800 */ 8666 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8667 BM_WUC_PAGE << BME1000_PAGE_SHIFT); 8668 8669 /* Write page 800 */ 8670 wm_gmii_i82544_writereg(self, 1, BM_WUC_ADDRESS_OPCODE, regnum); 8671 8672 if (rd) 8673 *val = wm_gmii_i82544_readreg(self, 1, BM_WUC_DATA_OPCODE); 8674 else 8675 wm_gmii_i82544_writereg(self, 1, BM_WUC_DATA_OPCODE, *val); 8676 8677 /* Set page 769 */ 8678 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8679 BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT); 8680 8681 wm_gmii_i82544_writereg(self, 1, BM_WUC_ENABLE_REG, wuce); 8682 } 8683 8684 /* 8685 * wm_gmii_hv_readreg: [mii interface function] 8686 * 8687 * Read a PHY register on the kumeran 8688 * This could be handled by the PHY layer if we didn't have to lock the 8689 * ressource ... 8690 */ 8691 static int 8692 wm_gmii_hv_readreg(device_t self, int phy, int reg) 8693 { 8694 struct wm_softc *sc = device_private(self); 8695 uint16_t page = BM_PHY_REG_PAGE(reg); 8696 uint16_t regnum = BM_PHY_REG_NUM(reg); 8697 uint16_t val; 8698 int rv; 8699 8700 if (wm_get_swfwhw_semaphore(sc)) { 8701 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8702 __func__); 8703 return 0; 8704 } 8705 8706 /* XXX Workaround failure in MDIO access while cable is disconnected */ 8707 if (sc->sc_phytype == WMPHY_82577) { 8708 /* XXX must write */ 8709 } 8710 8711 /* Page 800 works differently than the rest so it has its own func */ 8712 if (page == BM_WUC_PAGE) { 8713 wm_access_phy_wakeup_reg_bm(self, reg, &val, 1); 8714 return val; 8715 } 8716 8717 /* 8718 * Lower than page 768 works differently than the rest so it has its 8719 * own func 8720 */ 8721 if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) { 8722 printf("gmii_hv_readreg!!!\n"); 8723 return 0; 8724 } 8725 8726 if (regnum > BME1000_MAX_MULTI_PAGE_REG) { 8727 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8728 page << BME1000_PAGE_SHIFT); 8729 } 8730 8731 rv = wm_gmii_i82544_readreg(self, phy, regnum & IGPHY_MAXREGADDR); 8732 wm_put_swfwhw_semaphore(sc); 8733 return rv; 8734 } 8735 8736 /* 8737 * wm_gmii_hv_writereg: [mii interface function] 8738 * 8739 * Write a PHY register on the kumeran. 8740 * This could be handled by the PHY layer if we didn't have to lock the 8741 * ressource ... 8742 */ 8743 static void 8744 wm_gmii_hv_writereg(device_t self, int phy, int reg, int val) 8745 { 8746 struct wm_softc *sc = device_private(self); 8747 uint16_t page = BM_PHY_REG_PAGE(reg); 8748 uint16_t regnum = BM_PHY_REG_NUM(reg); 8749 8750 if (wm_get_swfwhw_semaphore(sc)) { 8751 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8752 __func__); 8753 return; 8754 } 8755 8756 /* XXX Workaround failure in MDIO access while cable is disconnected */ 8757 8758 /* Page 800 works differently than the rest so it has its own func */ 8759 if (page == BM_WUC_PAGE) { 8760 uint16_t tmp; 8761 8762 tmp = val; 8763 wm_access_phy_wakeup_reg_bm(self, reg, &tmp, 0); 8764 return; 8765 } 8766 8767 /* 8768 * Lower than page 768 works differently than the rest so it has its 8769 * own func 8770 */ 8771 if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) { 8772 printf("gmii_hv_writereg!!!\n"); 8773 return; 8774 } 8775 8776 /* 8777 * XXX Workaround MDIO accesses being disabled after entering IEEE 8778 * Power Down (whenever bit 11 of the PHY control register is set) 8779 */ 8780 8781 if (regnum > BME1000_MAX_MULTI_PAGE_REG) { 8782 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8783 page << BME1000_PAGE_SHIFT); 8784 } 8785 8786 wm_gmii_i82544_writereg(self, phy, regnum & IGPHY_MAXREGADDR, val); 8787 wm_put_swfwhw_semaphore(sc); 8788 } 8789 8790 /* 8791 * wm_gmii_82580_readreg: [mii interface function] 8792 * 8793 * Read a PHY register on the 82580 and I350. 8794 * This could be handled by the PHY layer if we didn't have to lock the 8795 * ressource ... 8796 */ 8797 static int 8798 wm_gmii_82580_readreg(device_t self, int phy, int reg) 8799 { 8800 struct wm_softc *sc = device_private(self); 8801 int sem; 8802 int rv; 8803 8804 sem = swfwphysem[sc->sc_funcid]; 8805 if (wm_get_swfw_semaphore(sc, sem)) { 8806 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8807 __func__); 8808 return 0; 8809 } 8810 8811 rv = wm_gmii_i82544_readreg(self, phy, reg); 8812 8813 wm_put_swfw_semaphore(sc, sem); 8814 return rv; 8815 } 8816 8817 /* 8818 * wm_gmii_82580_writereg: [mii interface function] 8819 * 8820 * Write a PHY register on the 82580 and I350. 8821 * This could be handled by the PHY layer if we didn't have to lock the 8822 * ressource ... 8823 */ 8824 static void 8825 wm_gmii_82580_writereg(device_t self, int phy, int reg, int val) 8826 { 8827 struct wm_softc *sc = device_private(self); 8828 int sem; 8829 8830 sem = swfwphysem[sc->sc_funcid]; 8831 if (wm_get_swfw_semaphore(sc, sem)) { 8832 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8833 __func__); 8834 return; 8835 } 8836 8837 wm_gmii_i82544_writereg(self, phy, reg, val); 8838 8839 wm_put_swfw_semaphore(sc, sem); 8840 } 8841 8842 /* 8843 * wm_gmii_gs40g_readreg: [mii interface function] 8844 * 8845 * Read a PHY register on the I2100 and I211. 8846 * This could be handled by the PHY layer if we didn't have to lock the 8847 * ressource ... 8848 */ 8849 static int 8850 wm_gmii_gs40g_readreg(device_t self, int phy, int reg) 8851 { 8852 struct wm_softc *sc = device_private(self); 8853 int sem; 8854 int page, offset; 8855 int rv; 8856 8857 /* Acquire semaphore */ 8858 sem = swfwphysem[sc->sc_funcid]; 8859 if (wm_get_swfw_semaphore(sc, sem)) { 8860 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8861 __func__); 8862 return 0; 8863 } 8864 8865 /* Page select */ 8866 page = reg >> GS40G_PAGE_SHIFT; 8867 wm_gmii_i82544_writereg(self, phy, GS40G_PAGE_SELECT, page); 8868 8869 /* Read reg */ 8870 offset = reg & GS40G_OFFSET_MASK; 8871 rv = wm_gmii_i82544_readreg(self, phy, offset); 8872 8873 wm_put_swfw_semaphore(sc, sem); 8874 return rv; 8875 } 8876 8877 /* 8878 * wm_gmii_gs40g_writereg: [mii interface function] 8879 * 8880 * Write a PHY register on the I210 and I211. 8881 * This could be handled by the PHY layer if we didn't have to lock the 8882 * ressource ... 8883 */ 8884 static void 8885 wm_gmii_gs40g_writereg(device_t self, int phy, int reg, int val) 8886 { 8887 struct wm_softc *sc = device_private(self); 8888 int sem; 8889 int page, offset; 8890 8891 /* Acquire semaphore */ 8892 sem = swfwphysem[sc->sc_funcid]; 8893 if (wm_get_swfw_semaphore(sc, sem)) { 8894 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8895 __func__); 8896 return; 8897 } 8898 8899 /* Page select */ 8900 page = reg >> GS40G_PAGE_SHIFT; 8901 wm_gmii_i82544_writereg(self, phy, GS40G_PAGE_SELECT, page); 8902 8903 /* Write reg */ 8904 offset = reg & GS40G_OFFSET_MASK; 8905 wm_gmii_i82544_writereg(self, phy, offset, val); 8906 8907 /* Release semaphore */ 8908 wm_put_swfw_semaphore(sc, sem); 8909 } 8910 8911 /* 8912 * wm_gmii_statchg: [mii interface function] 8913 * 8914 * Callback from MII layer when media changes. 8915 */ 8916 static void 8917 wm_gmii_statchg(struct ifnet *ifp) 8918 { 8919 struct wm_softc *sc = ifp->if_softc; 8920 struct mii_data *mii = &sc->sc_mii; 8921 8922 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 8923 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 8924 sc->sc_fcrtl &= ~FCRTL_XONE; 8925 8926 /* 8927 * Get flow control negotiation result. 8928 */ 8929 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 8930 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 8931 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 8932 mii->mii_media_active &= ~IFM_ETH_FMASK; 8933 } 8934 8935 if (sc->sc_flowflags & IFM_FLOW) { 8936 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 8937 sc->sc_ctrl |= CTRL_TFCE; 8938 sc->sc_fcrtl |= FCRTL_XONE; 8939 } 8940 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 8941 sc->sc_ctrl |= CTRL_RFCE; 8942 } 8943 8944 if (sc->sc_mii.mii_media_active & IFM_FDX) { 8945 DPRINTF(WM_DEBUG_LINK, 8946 ("%s: LINK: statchg: FDX\n", ifp->if_xname)); 8947 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 8948 } else { 8949 DPRINTF(WM_DEBUG_LINK, 8950 ("%s: LINK: statchg: HDX\n", ifp->if_xname)); 8951 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 8952 } 8953 8954 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 8955 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 8956 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 8957 : WMREG_FCRTL, sc->sc_fcrtl); 8958 if (sc->sc_type == WM_T_80003) { 8959 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 8960 case IFM_1000_T: 8961 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL, 8962 KUMCTRLSTA_HD_CTRL_1000_DEFAULT); 8963 sc->sc_tipg = TIPG_1000T_80003_DFLT; 8964 break; 8965 default: 8966 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL, 8967 KUMCTRLSTA_HD_CTRL_10_100_DEFAULT); 8968 sc->sc_tipg = TIPG_10_100_80003_DFLT; 8969 break; 8970 } 8971 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 8972 } 8973 } 8974 8975 /* 8976 * wm_kmrn_readreg: 8977 * 8978 * Read a kumeran register 8979 */ 8980 static int 8981 wm_kmrn_readreg(struct wm_softc *sc, int reg) 8982 { 8983 int rv; 8984 8985 if (sc->sc_flags & WM_F_LOCK_SWFW) { 8986 if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) { 8987 aprint_error_dev(sc->sc_dev, 8988 "%s: failed to get semaphore\n", __func__); 8989 return 0; 8990 } 8991 } else if (sc->sc_flags & WM_F_LOCK_EXTCNF) { 8992 if (wm_get_swfwhw_semaphore(sc)) { 8993 aprint_error_dev(sc->sc_dev, 8994 "%s: failed to get semaphore\n", __func__); 8995 return 0; 8996 } 8997 } 8998 8999 CSR_WRITE(sc, WMREG_KUMCTRLSTA, 9000 ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | 9001 KUMCTRLSTA_REN); 9002 CSR_WRITE_FLUSH(sc); 9003 delay(2); 9004 9005 rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK; 9006 9007 if (sc->sc_flags & WM_F_LOCK_SWFW) 9008 wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM); 9009 else if (sc->sc_flags & WM_F_LOCK_EXTCNF) 9010 wm_put_swfwhw_semaphore(sc); 9011 9012 return rv; 9013 } 9014 9015 /* 9016 * wm_kmrn_writereg: 9017 * 9018 * Write a kumeran register 9019 */ 9020 static void 9021 wm_kmrn_writereg(struct wm_softc *sc, int reg, int val) 9022 { 9023 9024 if (sc->sc_flags & WM_F_LOCK_SWFW) { 9025 if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) { 9026 aprint_error_dev(sc->sc_dev, 9027 "%s: failed to get semaphore\n", __func__); 9028 return; 9029 } 9030 } else if (sc->sc_flags & WM_F_LOCK_EXTCNF) { 9031 if (wm_get_swfwhw_semaphore(sc)) { 9032 aprint_error_dev(sc->sc_dev, 9033 "%s: failed to get semaphore\n", __func__); 9034 return; 9035 } 9036 } 9037 9038 CSR_WRITE(sc, WMREG_KUMCTRLSTA, 9039 ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | 9040 (val & KUMCTRLSTA_MASK)); 9041 9042 if (sc->sc_flags & WM_F_LOCK_SWFW) 9043 wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM); 9044 else if (sc->sc_flags & WM_F_LOCK_EXTCNF) 9045 wm_put_swfwhw_semaphore(sc); 9046 } 9047 9048 /* SGMII related */ 9049 9050 /* 9051 * wm_sgmii_uses_mdio 9052 * 9053 * Check whether the transaction is to the internal PHY or the external 9054 * MDIO interface. Return true if it's MDIO. 9055 */ 9056 static bool 9057 wm_sgmii_uses_mdio(struct wm_softc *sc) 9058 { 9059 uint32_t reg; 9060 bool ismdio = false; 9061 9062 switch (sc->sc_type) { 9063 case WM_T_82575: 9064 case WM_T_82576: 9065 reg = CSR_READ(sc, WMREG_MDIC); 9066 ismdio = ((reg & MDIC_DEST) != 0); 9067 break; 9068 case WM_T_82580: 9069 case WM_T_I350: 9070 case WM_T_I354: 9071 case WM_T_I210: 9072 case WM_T_I211: 9073 reg = CSR_READ(sc, WMREG_MDICNFG); 9074 ismdio = ((reg & MDICNFG_DEST) != 0); 9075 break; 9076 default: 9077 break; 9078 } 9079 9080 return ismdio; 9081 } 9082 9083 /* 9084 * wm_sgmii_readreg: [mii interface function] 9085 * 9086 * Read a PHY register on the SGMII 9087 * This could be handled by the PHY layer if we didn't have to lock the 9088 * ressource ... 9089 */ 9090 static int 9091 wm_sgmii_readreg(device_t self, int phy, int reg) 9092 { 9093 struct wm_softc *sc = device_private(self); 9094 uint32_t i2ccmd; 9095 int i, rv; 9096 9097 if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) { 9098 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 9099 __func__); 9100 return 0; 9101 } 9102 9103 i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT) 9104 | (phy << I2CCMD_PHY_ADDR_SHIFT) 9105 | I2CCMD_OPCODE_READ; 9106 CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd); 9107 9108 /* Poll the ready bit */ 9109 for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) { 9110 delay(50); 9111 i2ccmd = CSR_READ(sc, WMREG_I2CCMD); 9112 if (i2ccmd & I2CCMD_READY) 9113 break; 9114 } 9115 if ((i2ccmd & I2CCMD_READY) == 0) 9116 aprint_error_dev(sc->sc_dev, "I2CCMD Read did not complete\n"); 9117 if ((i2ccmd & I2CCMD_ERROR) != 0) 9118 aprint_error_dev(sc->sc_dev, "I2CCMD Error bit set\n"); 9119 9120 rv = ((i2ccmd >> 8) & 0x00ff) | ((i2ccmd << 8) & 0xff00); 9121 9122 wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]); 9123 return rv; 9124 } 9125 9126 /* 9127 * wm_sgmii_writereg: [mii interface function] 9128 * 9129 * Write a PHY register on the SGMII. 9130 * This could be handled by the PHY layer if we didn't have to lock the 9131 * ressource ... 9132 */ 9133 static void 9134 wm_sgmii_writereg(device_t self, int phy, int reg, int val) 9135 { 9136 struct wm_softc *sc = device_private(self); 9137 uint32_t i2ccmd; 9138 int i; 9139 int val_swapped; 9140 9141 if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) { 9142 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 9143 __func__); 9144 return; 9145 } 9146 /* Swap the data bytes for the I2C interface */ 9147 val_swapped = ((val >> 8) & 0x00FF) | ((val << 8) & 0xFF00); 9148 i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT) 9149 | (phy << I2CCMD_PHY_ADDR_SHIFT) 9150 | I2CCMD_OPCODE_WRITE | val_swapped; 9151 CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd); 9152 9153 /* Poll the ready bit */ 9154 for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) { 9155 delay(50); 9156 i2ccmd = CSR_READ(sc, WMREG_I2CCMD); 9157 if (i2ccmd & I2CCMD_READY) 9158 break; 9159 } 9160 if ((i2ccmd & I2CCMD_READY) == 0) 9161 aprint_error_dev(sc->sc_dev, "I2CCMD Write did not complete\n"); 9162 if ((i2ccmd & I2CCMD_ERROR) != 0) 9163 aprint_error_dev(sc->sc_dev, "I2CCMD Error bit set\n"); 9164 9165 wm_put_swfw_semaphore(sc, SWFW_PHY0_SM); 9166 } 9167 9168 /* TBI related */ 9169 9170 /* 9171 * wm_tbi_mediainit: 9172 * 9173 * Initialize media for use on 1000BASE-X devices. 9174 */ 9175 static void 9176 wm_tbi_mediainit(struct wm_softc *sc) 9177 { 9178 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 9179 const char *sep = ""; 9180 9181 if (sc->sc_type < WM_T_82543) 9182 sc->sc_tipg = TIPG_WM_DFLT; 9183 else 9184 sc->sc_tipg = TIPG_LG_DFLT; 9185 9186 sc->sc_tbi_serdes_anegticks = 5; 9187 9188 /* Initialize our media structures */ 9189 sc->sc_mii.mii_ifp = ifp; 9190 sc->sc_ethercom.ec_mii = &sc->sc_mii; 9191 9192 if ((sc->sc_type >= WM_T_82575) 9193 && (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) 9194 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, 9195 wm_serdes_mediachange, wm_serdes_mediastatus); 9196 else 9197 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, 9198 wm_tbi_mediachange, wm_tbi_mediastatus); 9199 9200 /* 9201 * SWD Pins: 9202 * 9203 * 0 = Link LED (output) 9204 * 1 = Loss Of Signal (input) 9205 */ 9206 sc->sc_ctrl |= CTRL_SWDPIO(0); 9207 9208 /* XXX Perhaps this is only for TBI */ 9209 if (sc->sc_mediatype != WM_MEDIATYPE_SERDES) 9210 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 9211 9212 if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) 9213 sc->sc_ctrl &= ~CTRL_LRST; 9214 9215 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9216 9217 #define ADD(ss, mm, dd) \ 9218 do { \ 9219 aprint_normal("%s%s", sep, ss); \ 9220 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | (mm), (dd), NULL); \ 9221 sep = ", "; \ 9222 } while (/*CONSTCOND*/0) 9223 9224 aprint_normal_dev(sc->sc_dev, ""); 9225 9226 /* Only 82545 is LX */ 9227 if (sc->sc_type == WM_T_82545) { 9228 ADD("1000baseLX", IFM_1000_LX, ANAR_X_HD); 9229 ADD("1000baseLX-FDX", IFM_1000_LX | IFM_FDX, ANAR_X_FD); 9230 } else { 9231 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 9232 ADD("1000baseSX-FDX", IFM_1000_SX | IFM_FDX, ANAR_X_FD); 9233 } 9234 ADD("auto", IFM_AUTO, ANAR_X_FD | ANAR_X_HD); 9235 aprint_normal("\n"); 9236 9237 #undef ADD 9238 9239 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 9240 } 9241 9242 /* 9243 * wm_tbi_mediachange: [ifmedia interface function] 9244 * 9245 * Set hardware to newly-selected media on a 1000BASE-X device. 9246 */ 9247 static int 9248 wm_tbi_mediachange(struct ifnet *ifp) 9249 { 9250 struct wm_softc *sc = ifp->if_softc; 9251 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 9252 uint32_t status; 9253 int i; 9254 9255 if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) { 9256 /* XXX need some work for >= 82571 and < 82575 */ 9257 if (sc->sc_type < WM_T_82575) 9258 return 0; 9259 } 9260 9261 if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572) 9262 || (sc->sc_type >= WM_T_82575)) 9263 CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK); 9264 9265 sc->sc_ctrl &= ~CTRL_LRST; 9266 sc->sc_txcw = TXCW_ANE; 9267 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 9268 sc->sc_txcw |= TXCW_FD | TXCW_HD; 9269 else if (ife->ifm_media & IFM_FDX) 9270 sc->sc_txcw |= TXCW_FD; 9271 else 9272 sc->sc_txcw |= TXCW_HD; 9273 9274 if ((sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 9275 sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE; 9276 9277 DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n", 9278 device_xname(sc->sc_dev), sc->sc_txcw)); 9279 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 9280 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9281 CSR_WRITE_FLUSH(sc); 9282 delay(1000); 9283 9284 i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1); 9285 DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i)); 9286 9287 /* 9288 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the 9289 * optics detect a signal, 0 if they don't. 9290 */ 9291 if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) { 9292 /* Have signal; wait for the link to come up. */ 9293 for (i = 0; i < WM_LINKUP_TIMEOUT; i++) { 9294 delay(10000); 9295 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 9296 break; 9297 } 9298 9299 DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n", 9300 device_xname(sc->sc_dev),i)); 9301 9302 status = CSR_READ(sc, WMREG_STATUS); 9303 DPRINTF(WM_DEBUG_LINK, 9304 ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n", 9305 device_xname(sc->sc_dev),status, STATUS_LU)); 9306 if (status & STATUS_LU) { 9307 /* Link is up. */ 9308 DPRINTF(WM_DEBUG_LINK, 9309 ("%s: LINK: set media -> link up %s\n", 9310 device_xname(sc->sc_dev), 9311 (status & STATUS_FD) ? "FDX" : "HDX")); 9312 9313 /* 9314 * NOTE: CTRL will update TFCE and RFCE automatically, 9315 * so we should update sc->sc_ctrl 9316 */ 9317 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL); 9318 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 9319 sc->sc_fcrtl &= ~FCRTL_XONE; 9320 if (status & STATUS_FD) 9321 sc->sc_tctl |= 9322 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 9323 else 9324 sc->sc_tctl |= 9325 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 9326 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 9327 sc->sc_fcrtl |= FCRTL_XONE; 9328 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 9329 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 9330 WMREG_OLD_FCRTL : WMREG_FCRTL, 9331 sc->sc_fcrtl); 9332 sc->sc_tbi_linkup = 1; 9333 } else { 9334 if (i == WM_LINKUP_TIMEOUT) 9335 wm_check_for_link(sc); 9336 /* Link is down. */ 9337 DPRINTF(WM_DEBUG_LINK, 9338 ("%s: LINK: set media -> link down\n", 9339 device_xname(sc->sc_dev))); 9340 sc->sc_tbi_linkup = 0; 9341 } 9342 } else { 9343 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 9344 device_xname(sc->sc_dev))); 9345 sc->sc_tbi_linkup = 0; 9346 } 9347 9348 wm_tbi_serdes_set_linkled(sc); 9349 9350 return 0; 9351 } 9352 9353 /* 9354 * wm_tbi_mediastatus: [ifmedia interface function] 9355 * 9356 * Get the current interface media status on a 1000BASE-X device. 9357 */ 9358 static void 9359 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 9360 { 9361 struct wm_softc *sc = ifp->if_softc; 9362 uint32_t ctrl, status; 9363 9364 ifmr->ifm_status = IFM_AVALID; 9365 ifmr->ifm_active = IFM_ETHER; 9366 9367 status = CSR_READ(sc, WMREG_STATUS); 9368 if ((status & STATUS_LU) == 0) { 9369 ifmr->ifm_active |= IFM_NONE; 9370 return; 9371 } 9372 9373 ifmr->ifm_status |= IFM_ACTIVE; 9374 /* Only 82545 is LX */ 9375 if (sc->sc_type == WM_T_82545) 9376 ifmr->ifm_active |= IFM_1000_LX; 9377 else 9378 ifmr->ifm_active |= IFM_1000_SX; 9379 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 9380 ifmr->ifm_active |= IFM_FDX; 9381 else 9382 ifmr->ifm_active |= IFM_HDX; 9383 ctrl = CSR_READ(sc, WMREG_CTRL); 9384 if (ctrl & CTRL_RFCE) 9385 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 9386 if (ctrl & CTRL_TFCE) 9387 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 9388 } 9389 9390 /* XXX TBI only */ 9391 static int 9392 wm_check_for_link(struct wm_softc *sc) 9393 { 9394 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 9395 uint32_t rxcw; 9396 uint32_t ctrl; 9397 uint32_t status; 9398 uint32_t sig; 9399 9400 if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) { 9401 /* XXX need some work for >= 82571 */ 9402 if (sc->sc_type >= WM_T_82571) { 9403 sc->sc_tbi_linkup = 1; 9404 return 0; 9405 } 9406 } 9407 9408 rxcw = CSR_READ(sc, WMREG_RXCW); 9409 ctrl = CSR_READ(sc, WMREG_CTRL); 9410 status = CSR_READ(sc, WMREG_STATUS); 9411 9412 sig = (sc->sc_type > WM_T_82544) ? CTRL_SWDPIN(1) : 0; 9413 9414 DPRINTF(WM_DEBUG_LINK, 9415 ("%s: %s: sig = %d, status_lu = %d, rxcw_c = %d\n", 9416 device_xname(sc->sc_dev), __func__, 9417 ((ctrl & CTRL_SWDPIN(1)) == sig), 9418 ((status & STATUS_LU) != 0), ((rxcw & RXCW_C) != 0))); 9419 9420 /* 9421 * SWDPIN LU RXCW 9422 * 0 0 0 9423 * 0 0 1 (should not happen) 9424 * 0 1 0 (should not happen) 9425 * 0 1 1 (should not happen) 9426 * 1 0 0 Disable autonego and force linkup 9427 * 1 0 1 got /C/ but not linkup yet 9428 * 1 1 0 (linkup) 9429 * 1 1 1 If IFM_AUTO, back to autonego 9430 * 9431 */ 9432 if (((ctrl & CTRL_SWDPIN(1)) == sig) 9433 && ((status & STATUS_LU) == 0) 9434 && ((rxcw & RXCW_C) == 0)) { 9435 DPRINTF(WM_DEBUG_LINK, ("%s: force linkup and fullduplex\n", 9436 __func__)); 9437 sc->sc_tbi_linkup = 0; 9438 /* Disable auto-negotiation in the TXCW register */ 9439 CSR_WRITE(sc, WMREG_TXCW, (sc->sc_txcw & ~TXCW_ANE)); 9440 9441 /* 9442 * Force link-up and also force full-duplex. 9443 * 9444 * NOTE: CTRL was updated TFCE and RFCE automatically, 9445 * so we should update sc->sc_ctrl 9446 */ 9447 sc->sc_ctrl = ctrl | CTRL_SLU | CTRL_FD; 9448 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9449 } else if (((status & STATUS_LU) != 0) 9450 && ((rxcw & RXCW_C) != 0) 9451 && (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)) { 9452 sc->sc_tbi_linkup = 1; 9453 DPRINTF(WM_DEBUG_LINK, ("%s: go back to autonego\n", 9454 __func__)); 9455 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 9456 CSR_WRITE(sc, WMREG_CTRL, (ctrl & ~CTRL_SLU)); 9457 } else if (((ctrl & CTRL_SWDPIN(1)) == sig) 9458 && ((rxcw & RXCW_C) != 0)) { 9459 DPRINTF(WM_DEBUG_LINK, ("/C/")); 9460 } else { 9461 DPRINTF(WM_DEBUG_LINK, ("%s: %x,%x,%x\n", __func__, rxcw, ctrl, 9462 status)); 9463 } 9464 9465 return 0; 9466 } 9467 9468 /* 9469 * wm_tbi_tick: 9470 * 9471 * Check the link on TBI devices. 9472 * This function acts as mii_tick(). 9473 */ 9474 static void 9475 wm_tbi_tick(struct wm_softc *sc) 9476 { 9477 struct mii_data *mii = &sc->sc_mii; 9478 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 9479 uint32_t status; 9480 9481 KASSERT(WM_CORE_LOCKED(sc)); 9482 9483 status = CSR_READ(sc, WMREG_STATUS); 9484 9485 /* XXX is this needed? */ 9486 (void)CSR_READ(sc, WMREG_RXCW); 9487 (void)CSR_READ(sc, WMREG_CTRL); 9488 9489 /* set link status */ 9490 if ((status & STATUS_LU) == 0) { 9491 DPRINTF(WM_DEBUG_LINK, 9492 ("%s: LINK: checklink -> down\n", 9493 device_xname(sc->sc_dev))); 9494 sc->sc_tbi_linkup = 0; 9495 } else if (sc->sc_tbi_linkup == 0) { 9496 DPRINTF(WM_DEBUG_LINK, 9497 ("%s: LINK: checklink -> up %s\n", 9498 device_xname(sc->sc_dev), 9499 (status & STATUS_FD) ? "FDX" : "HDX")); 9500 sc->sc_tbi_linkup = 1; 9501 sc->sc_tbi_serdes_ticks = 0; 9502 } 9503 9504 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) == 0) 9505 goto setled; 9506 9507 if ((status & STATUS_LU) == 0) { 9508 sc->sc_tbi_linkup = 0; 9509 /* If the timer expired, retry autonegotiation */ 9510 if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 9511 && (++sc->sc_tbi_serdes_ticks 9512 >= sc->sc_tbi_serdes_anegticks)) { 9513 DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n")); 9514 sc->sc_tbi_serdes_ticks = 0; 9515 /* 9516 * Reset the link, and let autonegotiation do 9517 * its thing 9518 */ 9519 sc->sc_ctrl |= CTRL_LRST; 9520 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9521 CSR_WRITE_FLUSH(sc); 9522 delay(1000); 9523 sc->sc_ctrl &= ~CTRL_LRST; 9524 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9525 CSR_WRITE_FLUSH(sc); 9526 delay(1000); 9527 CSR_WRITE(sc, WMREG_TXCW, 9528 sc->sc_txcw & ~TXCW_ANE); 9529 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 9530 } 9531 } 9532 9533 setled: 9534 wm_tbi_serdes_set_linkled(sc); 9535 } 9536 9537 /* SERDES related */ 9538 static void 9539 wm_serdes_power_up_link_82575(struct wm_softc *sc) 9540 { 9541 uint32_t reg; 9542 9543 if ((sc->sc_mediatype != WM_MEDIATYPE_SERDES) 9544 && ((sc->sc_flags & WM_F_SGMII) == 0)) 9545 return; 9546 9547 reg = CSR_READ(sc, WMREG_PCS_CFG); 9548 reg |= PCS_CFG_PCS_EN; 9549 CSR_WRITE(sc, WMREG_PCS_CFG, reg); 9550 9551 reg = CSR_READ(sc, WMREG_CTRL_EXT); 9552 reg &= ~CTRL_EXT_SWDPIN(3); 9553 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 9554 CSR_WRITE_FLUSH(sc); 9555 } 9556 9557 static int 9558 wm_serdes_mediachange(struct ifnet *ifp) 9559 { 9560 struct wm_softc *sc = ifp->if_softc; 9561 bool pcs_autoneg = true; /* XXX */ 9562 uint32_t ctrl_ext, pcs_lctl, reg; 9563 9564 /* XXX Currently, this function is not called on 8257[12] */ 9565 if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572) 9566 || (sc->sc_type >= WM_T_82575)) 9567 CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK); 9568 9569 wm_serdes_power_up_link_82575(sc); 9570 9571 sc->sc_ctrl |= CTRL_SLU; 9572 9573 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) 9574 sc->sc_ctrl |= CTRL_SWDPIN(0) | CTRL_SWDPIN(1); 9575 9576 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT); 9577 pcs_lctl = CSR_READ(sc, WMREG_PCS_LCTL); 9578 switch (ctrl_ext & CTRL_EXT_LINK_MODE_MASK) { 9579 case CTRL_EXT_LINK_MODE_SGMII: 9580 pcs_autoneg = true; 9581 pcs_lctl &= ~PCS_LCTL_AN_TIMEOUT; 9582 break; 9583 case CTRL_EXT_LINK_MODE_1000KX: 9584 pcs_autoneg = false; 9585 /* FALLTHROUGH */ 9586 default: 9587 if ((sc->sc_type == WM_T_82575) 9588 || (sc->sc_type == WM_T_82576)) { 9589 if ((sc->sc_flags & WM_F_PCS_DIS_AUTONEGO) != 0) 9590 pcs_autoneg = false; 9591 } 9592 sc->sc_ctrl |= CTRL_SPEED_1000 | CTRL_FRCSPD | CTRL_FD 9593 | CTRL_FRCFDX; 9594 pcs_lctl |= PCS_LCTL_FSV_1000 | PCS_LCTL_FDV_FULL; 9595 } 9596 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9597 9598 if (pcs_autoneg) { 9599 pcs_lctl |= PCS_LCTL_AN_ENABLE | PCS_LCTL_AN_RESTART; 9600 pcs_lctl &= ~PCS_LCTL_FORCE_FC; 9601 9602 reg = CSR_READ(sc, WMREG_PCS_ANADV); 9603 reg &= ~(TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE); 9604 reg |= TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE; 9605 CSR_WRITE(sc, WMREG_PCS_ANADV, reg); 9606 } else 9607 pcs_lctl |= PCS_LCTL_FSD | PCS_LCTL_FORCE_FC; 9608 9609 CSR_WRITE(sc, WMREG_PCS_LCTL, pcs_lctl); 9610 9611 9612 return 0; 9613 } 9614 9615 static void 9616 wm_serdes_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 9617 { 9618 struct wm_softc *sc = ifp->if_softc; 9619 struct mii_data *mii = &sc->sc_mii; 9620 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 9621 uint32_t pcs_adv, pcs_lpab, reg; 9622 9623 ifmr->ifm_status = IFM_AVALID; 9624 ifmr->ifm_active = IFM_ETHER; 9625 9626 /* Check PCS */ 9627 reg = CSR_READ(sc, WMREG_PCS_LSTS); 9628 if ((reg & PCS_LSTS_LINKOK) == 0) { 9629 ifmr->ifm_active |= IFM_NONE; 9630 sc->sc_tbi_linkup = 0; 9631 goto setled; 9632 } 9633 9634 sc->sc_tbi_linkup = 1; 9635 ifmr->ifm_status |= IFM_ACTIVE; 9636 ifmr->ifm_active |= IFM_1000_SX; /* XXX */ 9637 if ((reg & PCS_LSTS_FDX) != 0) 9638 ifmr->ifm_active |= IFM_FDX; 9639 else 9640 ifmr->ifm_active |= IFM_HDX; 9641 mii->mii_media_active &= ~IFM_ETH_FMASK; 9642 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 9643 /* Check flow */ 9644 reg = CSR_READ(sc, WMREG_PCS_LSTS); 9645 if ((reg & PCS_LSTS_AN_COMP) == 0) { 9646 DPRINTF(WM_DEBUG_LINK, ("XXX LINKOK but not ACOMP\n")); 9647 goto setled; 9648 } 9649 pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV); 9650 pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB); 9651 DPRINTF(WM_DEBUG_LINK, 9652 ("XXX AN result(2) %08x, %08x\n", pcs_adv, pcs_lpab)); 9653 if ((pcs_adv & TXCW_SYM_PAUSE) 9654 && (pcs_lpab & TXCW_SYM_PAUSE)) { 9655 mii->mii_media_active |= IFM_FLOW 9656 | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 9657 } else if (((pcs_adv & TXCW_SYM_PAUSE) == 0) 9658 && (pcs_adv & TXCW_ASYM_PAUSE) 9659 && (pcs_lpab & TXCW_SYM_PAUSE) 9660 && (pcs_lpab & TXCW_ASYM_PAUSE)) { 9661 mii->mii_media_active |= IFM_FLOW 9662 | IFM_ETH_TXPAUSE; 9663 } else if ((pcs_adv & TXCW_SYM_PAUSE) 9664 && (pcs_adv & TXCW_ASYM_PAUSE) 9665 && ((pcs_lpab & TXCW_SYM_PAUSE) == 0) 9666 && (pcs_lpab & TXCW_ASYM_PAUSE)) { 9667 mii->mii_media_active |= IFM_FLOW 9668 | IFM_ETH_RXPAUSE; 9669 } else { 9670 } 9671 } 9672 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) 9673 | (mii->mii_media_active & IFM_ETH_FMASK); 9674 setled: 9675 wm_tbi_serdes_set_linkled(sc); 9676 } 9677 9678 /* 9679 * wm_serdes_tick: 9680 * 9681 * Check the link on serdes devices. 9682 */ 9683 static void 9684 wm_serdes_tick(struct wm_softc *sc) 9685 { 9686 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 9687 struct mii_data *mii = &sc->sc_mii; 9688 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 9689 uint32_t reg; 9690 9691 KASSERT(WM_CORE_LOCKED(sc)); 9692 9693 mii->mii_media_status = IFM_AVALID; 9694 mii->mii_media_active = IFM_ETHER; 9695 9696 /* Check PCS */ 9697 reg = CSR_READ(sc, WMREG_PCS_LSTS); 9698 if ((reg & PCS_LSTS_LINKOK) != 0) { 9699 mii->mii_media_status |= IFM_ACTIVE; 9700 sc->sc_tbi_linkup = 1; 9701 sc->sc_tbi_serdes_ticks = 0; 9702 mii->mii_media_active |= IFM_1000_SX; /* XXX */ 9703 if ((reg & PCS_LSTS_FDX) != 0) 9704 mii->mii_media_active |= IFM_FDX; 9705 else 9706 mii->mii_media_active |= IFM_HDX; 9707 } else { 9708 mii->mii_media_status |= IFM_NONE; 9709 sc->sc_tbi_linkup = 0; 9710 /* If the timer expired, retry autonegotiation */ 9711 if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 9712 && (++sc->sc_tbi_serdes_ticks 9713 >= sc->sc_tbi_serdes_anegticks)) { 9714 DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n")); 9715 sc->sc_tbi_serdes_ticks = 0; 9716 /* XXX */ 9717 wm_serdes_mediachange(ifp); 9718 } 9719 } 9720 9721 wm_tbi_serdes_set_linkled(sc); 9722 } 9723 9724 /* SFP related */ 9725 9726 static int 9727 wm_sfp_read_data_byte(struct wm_softc *sc, uint16_t offset, uint8_t *data) 9728 { 9729 uint32_t i2ccmd; 9730 int i; 9731 9732 i2ccmd = (offset << I2CCMD_REG_ADDR_SHIFT) | I2CCMD_OPCODE_READ; 9733 CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd); 9734 9735 /* Poll the ready bit */ 9736 for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) { 9737 delay(50); 9738 i2ccmd = CSR_READ(sc, WMREG_I2CCMD); 9739 if (i2ccmd & I2CCMD_READY) 9740 break; 9741 } 9742 if ((i2ccmd & I2CCMD_READY) == 0) 9743 return -1; 9744 if ((i2ccmd & I2CCMD_ERROR) != 0) 9745 return -1; 9746 9747 *data = i2ccmd & 0x00ff; 9748 9749 return 0; 9750 } 9751 9752 static uint32_t 9753 wm_sfp_get_media_type(struct wm_softc *sc) 9754 { 9755 uint32_t ctrl_ext; 9756 uint8_t val = 0; 9757 int timeout = 3; 9758 uint32_t mediatype = WM_MEDIATYPE_UNKNOWN; 9759 int rv = -1; 9760 9761 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT); 9762 ctrl_ext &= ~CTRL_EXT_SWDPIN(3); 9763 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_I2C_ENA); 9764 CSR_WRITE_FLUSH(sc); 9765 9766 /* Read SFP module data */ 9767 while (timeout) { 9768 rv = wm_sfp_read_data_byte(sc, SFF_SFP_ID_OFF, &val); 9769 if (rv == 0) 9770 break; 9771 delay(100*1000); /* XXX too big */ 9772 timeout--; 9773 } 9774 if (rv != 0) 9775 goto out; 9776 switch (val) { 9777 case SFF_SFP_ID_SFF: 9778 aprint_normal_dev(sc->sc_dev, 9779 "Module/Connector soldered to board\n"); 9780 break; 9781 case SFF_SFP_ID_SFP: 9782 aprint_normal_dev(sc->sc_dev, "SFP\n"); 9783 break; 9784 case SFF_SFP_ID_UNKNOWN: 9785 goto out; 9786 default: 9787 break; 9788 } 9789 9790 rv = wm_sfp_read_data_byte(sc, SFF_SFP_ETH_FLAGS_OFF, &val); 9791 if (rv != 0) { 9792 goto out; 9793 } 9794 9795 if ((val & (SFF_SFP_ETH_FLAGS_1000SX | SFF_SFP_ETH_FLAGS_1000LX)) != 0) 9796 mediatype = WM_MEDIATYPE_SERDES; 9797 else if ((val & SFF_SFP_ETH_FLAGS_1000T) != 0){ 9798 sc->sc_flags |= WM_F_SGMII; 9799 mediatype = WM_MEDIATYPE_COPPER; 9800 } else if ((val & SFF_SFP_ETH_FLAGS_100FX) != 0){ 9801 sc->sc_flags |= WM_F_SGMII; 9802 mediatype = WM_MEDIATYPE_SERDES; 9803 } 9804 9805 out: 9806 /* Restore I2C interface setting */ 9807 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext); 9808 9809 return mediatype; 9810 } 9811 /* 9812 * NVM related. 9813 * Microwire, SPI (w/wo EERD) and Flash. 9814 */ 9815 9816 /* Both spi and uwire */ 9817 9818 /* 9819 * wm_eeprom_sendbits: 9820 * 9821 * Send a series of bits to the EEPROM. 9822 */ 9823 static void 9824 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 9825 { 9826 uint32_t reg; 9827 int x; 9828 9829 reg = CSR_READ(sc, WMREG_EECD); 9830 9831 for (x = nbits; x > 0; x--) { 9832 if (bits & (1U << (x - 1))) 9833 reg |= EECD_DI; 9834 else 9835 reg &= ~EECD_DI; 9836 CSR_WRITE(sc, WMREG_EECD, reg); 9837 CSR_WRITE_FLUSH(sc); 9838 delay(2); 9839 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 9840 CSR_WRITE_FLUSH(sc); 9841 delay(2); 9842 CSR_WRITE(sc, WMREG_EECD, reg); 9843 CSR_WRITE_FLUSH(sc); 9844 delay(2); 9845 } 9846 } 9847 9848 /* 9849 * wm_eeprom_recvbits: 9850 * 9851 * Receive a series of bits from the EEPROM. 9852 */ 9853 static void 9854 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 9855 { 9856 uint32_t reg, val; 9857 int x; 9858 9859 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 9860 9861 val = 0; 9862 for (x = nbits; x > 0; x--) { 9863 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 9864 CSR_WRITE_FLUSH(sc); 9865 delay(2); 9866 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 9867 val |= (1U << (x - 1)); 9868 CSR_WRITE(sc, WMREG_EECD, reg); 9869 CSR_WRITE_FLUSH(sc); 9870 delay(2); 9871 } 9872 *valp = val; 9873 } 9874 9875 /* Microwire */ 9876 9877 /* 9878 * wm_nvm_read_uwire: 9879 * 9880 * Read a word from the EEPROM using the MicroWire protocol. 9881 */ 9882 static int 9883 wm_nvm_read_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 9884 { 9885 uint32_t reg, val; 9886 int i; 9887 9888 for (i = 0; i < wordcnt; i++) { 9889 /* Clear SK and DI. */ 9890 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 9891 CSR_WRITE(sc, WMREG_EECD, reg); 9892 9893 /* 9894 * XXX: workaround for a bug in qemu-0.12.x and prior 9895 * and Xen. 9896 * 9897 * We use this workaround only for 82540 because qemu's 9898 * e1000 act as 82540. 9899 */ 9900 if (sc->sc_type == WM_T_82540) { 9901 reg |= EECD_SK; 9902 CSR_WRITE(sc, WMREG_EECD, reg); 9903 reg &= ~EECD_SK; 9904 CSR_WRITE(sc, WMREG_EECD, reg); 9905 CSR_WRITE_FLUSH(sc); 9906 delay(2); 9907 } 9908 /* XXX: end of workaround */ 9909 9910 /* Set CHIP SELECT. */ 9911 reg |= EECD_CS; 9912 CSR_WRITE(sc, WMREG_EECD, reg); 9913 CSR_WRITE_FLUSH(sc); 9914 delay(2); 9915 9916 /* Shift in the READ command. */ 9917 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 9918 9919 /* Shift in address. */ 9920 wm_eeprom_sendbits(sc, word + i, sc->sc_nvm_addrbits); 9921 9922 /* Shift out the data. */ 9923 wm_eeprom_recvbits(sc, &val, 16); 9924 data[i] = val & 0xffff; 9925 9926 /* Clear CHIP SELECT. */ 9927 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 9928 CSR_WRITE(sc, WMREG_EECD, reg); 9929 CSR_WRITE_FLUSH(sc); 9930 delay(2); 9931 } 9932 9933 return 0; 9934 } 9935 9936 /* SPI */ 9937 9938 /* 9939 * Set SPI and FLASH related information from the EECD register. 9940 * For 82541 and 82547, the word size is taken from EEPROM. 9941 */ 9942 static int 9943 wm_nvm_set_addrbits_size_eecd(struct wm_softc *sc) 9944 { 9945 int size; 9946 uint32_t reg; 9947 uint16_t data; 9948 9949 reg = CSR_READ(sc, WMREG_EECD); 9950 sc->sc_nvm_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 9951 9952 /* Read the size of NVM from EECD by default */ 9953 size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK); 9954 switch (sc->sc_type) { 9955 case WM_T_82541: 9956 case WM_T_82541_2: 9957 case WM_T_82547: 9958 case WM_T_82547_2: 9959 /* Set dummy value to access EEPROM */ 9960 sc->sc_nvm_wordsize = 64; 9961 wm_nvm_read(sc, NVM_OFF_EEPROM_SIZE, 1, &data); 9962 reg = data; 9963 size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK); 9964 if (size == 0) 9965 size = 6; /* 64 word size */ 9966 else 9967 size += NVM_WORD_SIZE_BASE_SHIFT + 1; 9968 break; 9969 case WM_T_80003: 9970 case WM_T_82571: 9971 case WM_T_82572: 9972 case WM_T_82573: /* SPI case */ 9973 case WM_T_82574: /* SPI case */ 9974 case WM_T_82583: /* SPI case */ 9975 size += NVM_WORD_SIZE_BASE_SHIFT; 9976 if (size > 14) 9977 size = 14; 9978 break; 9979 case WM_T_82575: 9980 case WM_T_82576: 9981 case WM_T_82580: 9982 case WM_T_I350: 9983 case WM_T_I354: 9984 case WM_T_I210: 9985 case WM_T_I211: 9986 size += NVM_WORD_SIZE_BASE_SHIFT; 9987 if (size > 15) 9988 size = 15; 9989 break; 9990 default: 9991 aprint_error_dev(sc->sc_dev, 9992 "%s: unknown device(%d)?\n", __func__, sc->sc_type); 9993 return -1; 9994 break; 9995 } 9996 9997 sc->sc_nvm_wordsize = 1 << size; 9998 9999 return 0; 10000 } 10001 10002 /* 10003 * wm_nvm_ready_spi: 10004 * 10005 * Wait for a SPI EEPROM to be ready for commands. 10006 */ 10007 static int 10008 wm_nvm_ready_spi(struct wm_softc *sc) 10009 { 10010 uint32_t val; 10011 int usec; 10012 10013 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 10014 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 10015 wm_eeprom_recvbits(sc, &val, 8); 10016 if ((val & SPI_SR_RDY) == 0) 10017 break; 10018 } 10019 if (usec >= SPI_MAX_RETRIES) { 10020 aprint_error_dev(sc->sc_dev,"EEPROM failed to become ready\n"); 10021 return 1; 10022 } 10023 return 0; 10024 } 10025 10026 /* 10027 * wm_nvm_read_spi: 10028 * 10029 * Read a work from the EEPROM using the SPI protocol. 10030 */ 10031 static int 10032 wm_nvm_read_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 10033 { 10034 uint32_t reg, val; 10035 int i; 10036 uint8_t opc; 10037 10038 /* Clear SK and CS. */ 10039 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 10040 CSR_WRITE(sc, WMREG_EECD, reg); 10041 CSR_WRITE_FLUSH(sc); 10042 delay(2); 10043 10044 if (wm_nvm_ready_spi(sc)) 10045 return 1; 10046 10047 /* Toggle CS to flush commands. */ 10048 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 10049 CSR_WRITE_FLUSH(sc); 10050 delay(2); 10051 CSR_WRITE(sc, WMREG_EECD, reg); 10052 CSR_WRITE_FLUSH(sc); 10053 delay(2); 10054 10055 opc = SPI_OPC_READ; 10056 if (sc->sc_nvm_addrbits == 8 && word >= 128) 10057 opc |= SPI_OPC_A8; 10058 10059 wm_eeprom_sendbits(sc, opc, 8); 10060 wm_eeprom_sendbits(sc, word << 1, sc->sc_nvm_addrbits); 10061 10062 for (i = 0; i < wordcnt; i++) { 10063 wm_eeprom_recvbits(sc, &val, 16); 10064 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 10065 } 10066 10067 /* Raise CS and clear SK. */ 10068 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 10069 CSR_WRITE(sc, WMREG_EECD, reg); 10070 CSR_WRITE_FLUSH(sc); 10071 delay(2); 10072 10073 return 0; 10074 } 10075 10076 /* Using with EERD */ 10077 10078 static int 10079 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw) 10080 { 10081 uint32_t attempts = 100000; 10082 uint32_t i, reg = 0; 10083 int32_t done = -1; 10084 10085 for (i = 0; i < attempts; i++) { 10086 reg = CSR_READ(sc, rw); 10087 10088 if (reg & EERD_DONE) { 10089 done = 0; 10090 break; 10091 } 10092 delay(5); 10093 } 10094 10095 return done; 10096 } 10097 10098 static int 10099 wm_nvm_read_eerd(struct wm_softc *sc, int offset, int wordcnt, 10100 uint16_t *data) 10101 { 10102 int i, eerd = 0; 10103 int error = 0; 10104 10105 for (i = 0; i < wordcnt; i++) { 10106 eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START; 10107 10108 CSR_WRITE(sc, WMREG_EERD, eerd); 10109 error = wm_poll_eerd_eewr_done(sc, WMREG_EERD); 10110 if (error != 0) 10111 break; 10112 10113 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT); 10114 } 10115 10116 return error; 10117 } 10118 10119 /* Flash */ 10120 10121 static int 10122 wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank) 10123 { 10124 uint32_t eecd; 10125 uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1; 10126 uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t); 10127 uint8_t sig_byte = 0; 10128 10129 switch (sc->sc_type) { 10130 case WM_T_PCH_SPT: 10131 /* 10132 * In SPT, read from the CTRL_EXT reg instead of accessing the 10133 * sector valid bits from the NVM. 10134 */ 10135 *bank = CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_NVMVS; 10136 if ((*bank == 0) || (*bank == 1)) { 10137 aprint_error_dev(sc->sc_dev, 10138 "%s: no valid NVM bank present\n", 10139 __func__); 10140 return -1; 10141 } else { 10142 *bank = *bank - 2; 10143 return 0; 10144 } 10145 case WM_T_ICH8: 10146 case WM_T_ICH9: 10147 eecd = CSR_READ(sc, WMREG_EECD); 10148 if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) { 10149 *bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0; 10150 return 0; 10151 } 10152 /* FALLTHROUGH */ 10153 default: 10154 /* Default to 0 */ 10155 *bank = 0; 10156 10157 /* Check bank 0 */ 10158 wm_read_ich8_byte(sc, act_offset, &sig_byte); 10159 if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) { 10160 *bank = 0; 10161 return 0; 10162 } 10163 10164 /* Check bank 1 */ 10165 wm_read_ich8_byte(sc, act_offset + bank1_offset, 10166 &sig_byte); 10167 if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) { 10168 *bank = 1; 10169 return 0; 10170 } 10171 } 10172 10173 DPRINTF(WM_DEBUG_NVM, ("%s: No valid NVM bank present\n", 10174 device_xname(sc->sc_dev))); 10175 return -1; 10176 } 10177 10178 /****************************************************************************** 10179 * This function does initial flash setup so that a new read/write/erase cycle 10180 * can be started. 10181 * 10182 * sc - The pointer to the hw structure 10183 ****************************************************************************/ 10184 static int32_t 10185 wm_ich8_cycle_init(struct wm_softc *sc) 10186 { 10187 uint16_t hsfsts; 10188 int32_t error = 1; 10189 int32_t i = 0; 10190 10191 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 10192 10193 /* May be check the Flash Des Valid bit in Hw status */ 10194 if ((hsfsts & HSFSTS_FLDVAL) == 0) { 10195 return error; 10196 } 10197 10198 /* Clear FCERR in Hw status by writing 1 */ 10199 /* Clear DAEL in Hw status by writing a 1 */ 10200 hsfsts |= HSFSTS_ERR | HSFSTS_DAEL; 10201 10202 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 10203 10204 /* 10205 * Either we should have a hardware SPI cycle in progress bit to check 10206 * against, in order to start a new cycle or FDONE bit should be 10207 * changed in the hardware so that it is 1 after harware reset, which 10208 * can then be used as an indication whether a cycle is in progress or 10209 * has been completed .. we should also have some software semaphore 10210 * mechanism to guard FDONE or the cycle in progress bit so that two 10211 * threads access to those bits can be sequentiallized or a way so that 10212 * 2 threads dont start the cycle at the same time 10213 */ 10214 10215 if ((hsfsts & HSFSTS_FLINPRO) == 0) { 10216 /* 10217 * There is no cycle running at present, so we can start a 10218 * cycle 10219 */ 10220 10221 /* Begin by setting Flash Cycle Done. */ 10222 hsfsts |= HSFSTS_DONE; 10223 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 10224 error = 0; 10225 } else { 10226 /* 10227 * otherwise poll for sometime so the current cycle has a 10228 * chance to end before giving up. 10229 */ 10230 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 10231 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 10232 if ((hsfsts & HSFSTS_FLINPRO) == 0) { 10233 error = 0; 10234 break; 10235 } 10236 delay(1); 10237 } 10238 if (error == 0) { 10239 /* 10240 * Successful in waiting for previous cycle to timeout, 10241 * now set the Flash Cycle Done. 10242 */ 10243 hsfsts |= HSFSTS_DONE; 10244 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 10245 } 10246 } 10247 return error; 10248 } 10249 10250 /****************************************************************************** 10251 * This function starts a flash cycle and waits for its completion 10252 * 10253 * sc - The pointer to the hw structure 10254 ****************************************************************************/ 10255 static int32_t 10256 wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout) 10257 { 10258 uint16_t hsflctl; 10259 uint16_t hsfsts; 10260 int32_t error = 1; 10261 uint32_t i = 0; 10262 10263 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 10264 hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL); 10265 hsflctl |= HSFCTL_GO; 10266 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl); 10267 10268 /* Wait till FDONE bit is set to 1 */ 10269 do { 10270 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 10271 if (hsfsts & HSFSTS_DONE) 10272 break; 10273 delay(1); 10274 i++; 10275 } while (i < timeout); 10276 if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0) 10277 error = 0; 10278 10279 return error; 10280 } 10281 10282 /****************************************************************************** 10283 * Reads a byte or (d)word from the NVM using the ICH8 flash access registers. 10284 * 10285 * sc - The pointer to the hw structure 10286 * index - The index of the byte or word to read. 10287 * size - Size of data to read, 1=byte 2=word, 4=dword 10288 * data - Pointer to the word to store the value read. 10289 *****************************************************************************/ 10290 static int32_t 10291 wm_read_ich8_data(struct wm_softc *sc, uint32_t index, 10292 uint32_t size, uint32_t *data) 10293 { 10294 uint16_t hsfsts; 10295 uint16_t hsflctl; 10296 uint32_t flash_linear_address; 10297 uint32_t flash_data = 0; 10298 int32_t error = 1; 10299 int32_t count = 0; 10300 10301 if (size < 1 || size > 4 || data == 0x0 || 10302 index > ICH_FLASH_LINEAR_ADDR_MASK) 10303 return error; 10304 10305 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10306 sc->sc_ich8_flash_base; 10307 10308 do { 10309 delay(1); 10310 /* Steps */ 10311 error = wm_ich8_cycle_init(sc); 10312 if (error) 10313 break; 10314 10315 hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL); 10316 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10317 hsflctl |= ((size - 1) << HSFCTL_BCOUNT_SHIFT) 10318 & HSFCTL_BCOUNT_MASK; 10319 hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT; 10320 if (sc->sc_type == WM_T_PCH_SPT) { 10321 /* 10322 * In SPT, This register is in Lan memory space, not 10323 * flash. Therefore, only 32 bit access is supported. 10324 */ 10325 ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFCTL, 10326 (uint32_t)hsflctl); 10327 } else 10328 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl); 10329 10330 /* 10331 * Write the last 24 bits of index into Flash Linear address 10332 * field in Flash Address 10333 */ 10334 /* TODO: TBD maybe check the index against the size of flash */ 10335 10336 ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address); 10337 10338 error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT); 10339 10340 /* 10341 * Check if FCERR is set to 1, if set to 1, clear it and try 10342 * the whole sequence a few more times, else read in (shift in) 10343 * the Flash Data0, the order is least significant byte first 10344 * msb to lsb 10345 */ 10346 if (error == 0) { 10347 flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0); 10348 if (size == 1) 10349 *data = (uint8_t)(flash_data & 0x000000FF); 10350 else if (size == 2) 10351 *data = (uint16_t)(flash_data & 0x0000FFFF); 10352 else if (size == 4) 10353 *data = (uint32_t)flash_data; 10354 break; 10355 } else { 10356 /* 10357 * If we've gotten here, then things are probably 10358 * completely hosed, but if the error condition is 10359 * detected, it won't hurt to give it another try... 10360 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 10361 */ 10362 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 10363 if (hsfsts & HSFSTS_ERR) { 10364 /* Repeat for some time before giving up. */ 10365 continue; 10366 } else if ((hsfsts & HSFSTS_DONE) == 0) 10367 break; 10368 } 10369 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10370 10371 return error; 10372 } 10373 10374 /****************************************************************************** 10375 * Reads a single byte from the NVM using the ICH8 flash access registers. 10376 * 10377 * sc - pointer to wm_hw structure 10378 * index - The index of the byte to read. 10379 * data - Pointer to a byte to store the value read. 10380 *****************************************************************************/ 10381 static int32_t 10382 wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data) 10383 { 10384 int32_t status; 10385 uint32_t word = 0; 10386 10387 status = wm_read_ich8_data(sc, index, 1, &word); 10388 if (status == 0) 10389 *data = (uint8_t)word; 10390 else 10391 *data = 0; 10392 10393 return status; 10394 } 10395 10396 /****************************************************************************** 10397 * Reads a word from the NVM using the ICH8 flash access registers. 10398 * 10399 * sc - pointer to wm_hw structure 10400 * index - The starting byte index of the word to read. 10401 * data - Pointer to a word to store the value read. 10402 *****************************************************************************/ 10403 static int32_t 10404 wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data) 10405 { 10406 int32_t status; 10407 uint32_t word = 0; 10408 10409 status = wm_read_ich8_data(sc, index, 2, &word); 10410 if (status == 0) 10411 *data = (uint16_t)word; 10412 else 10413 *data = 0; 10414 10415 return status; 10416 } 10417 10418 /****************************************************************************** 10419 * Reads a dword from the NVM using the ICH8 flash access registers. 10420 * 10421 * sc - pointer to wm_hw structure 10422 * index - The starting byte index of the word to read. 10423 * data - Pointer to a word to store the value read. 10424 *****************************************************************************/ 10425 static int32_t 10426 wm_read_ich8_dword(struct wm_softc *sc, uint32_t index, uint32_t *data) 10427 { 10428 int32_t status; 10429 10430 status = wm_read_ich8_data(sc, index, 4, data); 10431 return status; 10432 } 10433 10434 /****************************************************************************** 10435 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 10436 * register. 10437 * 10438 * sc - Struct containing variables accessed by shared code 10439 * offset - offset of word in the EEPROM to read 10440 * data - word read from the EEPROM 10441 * words - number of words to read 10442 *****************************************************************************/ 10443 static int 10444 wm_nvm_read_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data) 10445 { 10446 int32_t error = 0; 10447 uint32_t flash_bank = 0; 10448 uint32_t act_offset = 0; 10449 uint32_t bank_offset = 0; 10450 uint16_t word = 0; 10451 uint16_t i = 0; 10452 10453 /* 10454 * We need to know which is the valid flash bank. In the event 10455 * that we didn't allocate eeprom_shadow_ram, we may not be 10456 * managing flash_bank. So it cannot be trusted and needs 10457 * to be updated with each read. 10458 */ 10459 error = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank); 10460 if (error) { 10461 DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n", 10462 device_xname(sc->sc_dev))); 10463 flash_bank = 0; 10464 } 10465 10466 /* 10467 * Adjust offset appropriately if we're on bank 1 - adjust for word 10468 * size 10469 */ 10470 bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2); 10471 10472 error = wm_get_swfwhw_semaphore(sc); 10473 if (error) { 10474 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 10475 __func__); 10476 return error; 10477 } 10478 10479 for (i = 0; i < words; i++) { 10480 /* The NVM part needs a byte offset, hence * 2 */ 10481 act_offset = bank_offset + ((offset + i) * 2); 10482 error = wm_read_ich8_word(sc, act_offset, &word); 10483 if (error) { 10484 aprint_error_dev(sc->sc_dev, 10485 "%s: failed to read NVM\n", __func__); 10486 break; 10487 } 10488 data[i] = word; 10489 } 10490 10491 wm_put_swfwhw_semaphore(sc); 10492 return error; 10493 } 10494 10495 /****************************************************************************** 10496 * Reads a 16 bit word or words from the EEPROM using the SPT's flash access 10497 * register. 10498 * 10499 * sc - Struct containing variables accessed by shared code 10500 * offset - offset of word in the EEPROM to read 10501 * data - word read from the EEPROM 10502 * words - number of words to read 10503 *****************************************************************************/ 10504 static int 10505 wm_nvm_read_spt(struct wm_softc *sc, int offset, int words, uint16_t *data) 10506 { 10507 int32_t error = 0; 10508 uint32_t flash_bank = 0; 10509 uint32_t act_offset = 0; 10510 uint32_t bank_offset = 0; 10511 uint32_t dword = 0; 10512 uint16_t i = 0; 10513 10514 /* 10515 * We need to know which is the valid flash bank. In the event 10516 * that we didn't allocate eeprom_shadow_ram, we may not be 10517 * managing flash_bank. So it cannot be trusted and needs 10518 * to be updated with each read. 10519 */ 10520 error = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank); 10521 if (error) { 10522 DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n", 10523 device_xname(sc->sc_dev))); 10524 flash_bank = 0; 10525 } 10526 10527 /* 10528 * Adjust offset appropriately if we're on bank 1 - adjust for word 10529 * size 10530 */ 10531 bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2); 10532 10533 error = wm_get_swfwhw_semaphore(sc); 10534 if (error) { 10535 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 10536 __func__); 10537 return error; 10538 } 10539 10540 for (i = 0; i < words; i++) { 10541 /* The NVM part needs a byte offset, hence * 2 */ 10542 act_offset = bank_offset + ((offset + i) * 2); 10543 /* but we must read dword aligned, so mask ... */ 10544 error = wm_read_ich8_dword(sc, act_offset & ~0x3, &dword); 10545 if (error) { 10546 aprint_error_dev(sc->sc_dev, 10547 "%s: failed to read NVM\n", __func__); 10548 break; 10549 } 10550 /* ... and pick out low or high word */ 10551 if ((act_offset & 0x2) == 0) 10552 data[i] = (uint16_t)(dword & 0xFFFF); 10553 else 10554 data[i] = (uint16_t)((dword >> 16) & 0xFFFF); 10555 } 10556 10557 wm_put_swfwhw_semaphore(sc); 10558 return error; 10559 } 10560 10561 /* iNVM */ 10562 10563 static int 10564 wm_nvm_read_word_invm(struct wm_softc *sc, uint16_t address, uint16_t *data) 10565 { 10566 int32_t rv = 0; 10567 uint32_t invm_dword; 10568 uint16_t i; 10569 uint8_t record_type, word_address; 10570 10571 for (i = 0; i < INVM_SIZE; i++) { 10572 invm_dword = CSR_READ(sc, WM_INVM_DATA_REG(i)); 10573 /* Get record type */ 10574 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 10575 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 10576 break; 10577 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 10578 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 10579 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 10580 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 10581 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 10582 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 10583 if (word_address == address) { 10584 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 10585 rv = 0; 10586 break; 10587 } 10588 } 10589 } 10590 10591 return rv; 10592 } 10593 10594 static int 10595 wm_nvm_read_invm(struct wm_softc *sc, int offset, int words, uint16_t *data) 10596 { 10597 int rv = 0; 10598 int i; 10599 10600 for (i = 0; i < words; i++) { 10601 switch (offset + i) { 10602 case NVM_OFF_MACADDR: 10603 case NVM_OFF_MACADDR1: 10604 case NVM_OFF_MACADDR2: 10605 rv = wm_nvm_read_word_invm(sc, offset + i, &data[i]); 10606 if (rv != 0) { 10607 data[i] = 0xffff; 10608 rv = -1; 10609 } 10610 break; 10611 case NVM_OFF_CFG2: 10612 rv = wm_nvm_read_word_invm(sc, offset, data); 10613 if (rv != 0) { 10614 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 10615 rv = 0; 10616 } 10617 break; 10618 case NVM_OFF_CFG4: 10619 rv = wm_nvm_read_word_invm(sc, offset, data); 10620 if (rv != 0) { 10621 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 10622 rv = 0; 10623 } 10624 break; 10625 case NVM_OFF_LED_1_CFG: 10626 rv = wm_nvm_read_word_invm(sc, offset, data); 10627 if (rv != 0) { 10628 *data = NVM_LED_1_CFG_DEFAULT_I211; 10629 rv = 0; 10630 } 10631 break; 10632 case NVM_OFF_LED_0_2_CFG: 10633 rv = wm_nvm_read_word_invm(sc, offset, data); 10634 if (rv != 0) { 10635 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 10636 rv = 0; 10637 } 10638 break; 10639 case NVM_OFF_ID_LED_SETTINGS: 10640 rv = wm_nvm_read_word_invm(sc, offset, data); 10641 if (rv != 0) { 10642 *data = ID_LED_RESERVED_FFFF; 10643 rv = 0; 10644 } 10645 break; 10646 default: 10647 DPRINTF(WM_DEBUG_NVM, 10648 ("NVM word 0x%02x is not mapped.\n", offset)); 10649 *data = NVM_RESERVED_WORD; 10650 break; 10651 } 10652 } 10653 10654 return rv; 10655 } 10656 10657 /* Lock, detecting NVM type, validate checksum, version and read */ 10658 10659 /* 10660 * wm_nvm_acquire: 10661 * 10662 * Perform the EEPROM handshake required on some chips. 10663 */ 10664 static int 10665 wm_nvm_acquire(struct wm_softc *sc) 10666 { 10667 uint32_t reg; 10668 int x; 10669 int ret = 0; 10670 10671 /* always success */ 10672 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 10673 return 0; 10674 10675 if (sc->sc_flags & WM_F_LOCK_EXTCNF) { 10676 ret = wm_get_swfwhw_semaphore(sc); 10677 } else if (sc->sc_flags & WM_F_LOCK_SWFW) { 10678 /* This will also do wm_get_swsm_semaphore() if needed */ 10679 ret = wm_get_swfw_semaphore(sc, SWFW_EEP_SM); 10680 } else if (sc->sc_flags & WM_F_LOCK_SWSM) { 10681 ret = wm_get_swsm_semaphore(sc); 10682 } 10683 10684 if (ret) { 10685 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 10686 __func__); 10687 return 1; 10688 } 10689 10690 if (sc->sc_flags & WM_F_LOCK_EECD) { 10691 reg = CSR_READ(sc, WMREG_EECD); 10692 10693 /* Request EEPROM access. */ 10694 reg |= EECD_EE_REQ; 10695 CSR_WRITE(sc, WMREG_EECD, reg); 10696 10697 /* ..and wait for it to be granted. */ 10698 for (x = 0; x < 1000; x++) { 10699 reg = CSR_READ(sc, WMREG_EECD); 10700 if (reg & EECD_EE_GNT) 10701 break; 10702 delay(5); 10703 } 10704 if ((reg & EECD_EE_GNT) == 0) { 10705 aprint_error_dev(sc->sc_dev, 10706 "could not acquire EEPROM GNT\n"); 10707 reg &= ~EECD_EE_REQ; 10708 CSR_WRITE(sc, WMREG_EECD, reg); 10709 if (sc->sc_flags & WM_F_LOCK_EXTCNF) 10710 wm_put_swfwhw_semaphore(sc); 10711 if (sc->sc_flags & WM_F_LOCK_SWFW) 10712 wm_put_swfw_semaphore(sc, SWFW_EEP_SM); 10713 else if (sc->sc_flags & WM_F_LOCK_SWSM) 10714 wm_put_swsm_semaphore(sc); 10715 return 1; 10716 } 10717 } 10718 10719 return 0; 10720 } 10721 10722 /* 10723 * wm_nvm_release: 10724 * 10725 * Release the EEPROM mutex. 10726 */ 10727 static void 10728 wm_nvm_release(struct wm_softc *sc) 10729 { 10730 uint32_t reg; 10731 10732 /* always success */ 10733 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 10734 return; 10735 10736 if (sc->sc_flags & WM_F_LOCK_EECD) { 10737 reg = CSR_READ(sc, WMREG_EECD); 10738 reg &= ~EECD_EE_REQ; 10739 CSR_WRITE(sc, WMREG_EECD, reg); 10740 } 10741 10742 if (sc->sc_flags & WM_F_LOCK_EXTCNF) 10743 wm_put_swfwhw_semaphore(sc); 10744 if (sc->sc_flags & WM_F_LOCK_SWFW) 10745 wm_put_swfw_semaphore(sc, SWFW_EEP_SM); 10746 else if (sc->sc_flags & WM_F_LOCK_SWSM) 10747 wm_put_swsm_semaphore(sc); 10748 } 10749 10750 static int 10751 wm_nvm_is_onboard_eeprom(struct wm_softc *sc) 10752 { 10753 uint32_t eecd = 0; 10754 10755 if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574 10756 || sc->sc_type == WM_T_82583) { 10757 eecd = CSR_READ(sc, WMREG_EECD); 10758 10759 /* Isolate bits 15 & 16 */ 10760 eecd = ((eecd >> 15) & 0x03); 10761 10762 /* If both bits are set, device is Flash type */ 10763 if (eecd == 0x03) 10764 return 0; 10765 } 10766 return 1; 10767 } 10768 10769 static int 10770 wm_nvm_get_flash_presence_i210(struct wm_softc *sc) 10771 { 10772 uint32_t eec; 10773 10774 eec = CSR_READ(sc, WMREG_EEC); 10775 if ((eec & EEC_FLASH_DETECTED) != 0) 10776 return 1; 10777 10778 return 0; 10779 } 10780 10781 /* 10782 * wm_nvm_validate_checksum 10783 * 10784 * The checksum is defined as the sum of the first 64 (16 bit) words. 10785 */ 10786 static int 10787 wm_nvm_validate_checksum(struct wm_softc *sc) 10788 { 10789 uint16_t checksum; 10790 uint16_t eeprom_data; 10791 #ifdef WM_DEBUG 10792 uint16_t csum_wordaddr, valid_checksum; 10793 #endif 10794 int i; 10795 10796 checksum = 0; 10797 10798 /* Don't check for I211 */ 10799 if (sc->sc_type == WM_T_I211) 10800 return 0; 10801 10802 #ifdef WM_DEBUG 10803 if (sc->sc_type == WM_T_PCH_LPT) { 10804 csum_wordaddr = NVM_OFF_COMPAT; 10805 valid_checksum = NVM_COMPAT_VALID_CHECKSUM; 10806 } else { 10807 csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1; 10808 valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM; 10809 } 10810 10811 /* Dump EEPROM image for debug */ 10812 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 10813 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 10814 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) { 10815 /* XXX PCH_SPT? */ 10816 wm_nvm_read(sc, csum_wordaddr, 1, &eeprom_data); 10817 if ((eeprom_data & valid_checksum) == 0) { 10818 DPRINTF(WM_DEBUG_NVM, 10819 ("%s: NVM need to be updated (%04x != %04x)\n", 10820 device_xname(sc->sc_dev), eeprom_data, 10821 valid_checksum)); 10822 } 10823 } 10824 10825 if ((wm_debug & WM_DEBUG_NVM) != 0) { 10826 printf("%s: NVM dump:\n", device_xname(sc->sc_dev)); 10827 for (i = 0; i < NVM_SIZE; i++) { 10828 if (wm_nvm_read(sc, i, 1, &eeprom_data)) 10829 printf("XXXX "); 10830 else 10831 printf("%04hx ", eeprom_data); 10832 if (i % 8 == 7) 10833 printf("\n"); 10834 } 10835 } 10836 10837 #endif /* WM_DEBUG */ 10838 10839 for (i = 0; i < NVM_SIZE; i++) { 10840 if (wm_nvm_read(sc, i, 1, &eeprom_data)) 10841 return 1; 10842 checksum += eeprom_data; 10843 } 10844 10845 if (checksum != (uint16_t) NVM_CHECKSUM) { 10846 #ifdef WM_DEBUG 10847 printf("%s: NVM checksum mismatch (%04x != %04x)\n", 10848 device_xname(sc->sc_dev), checksum, NVM_CHECKSUM); 10849 #endif 10850 } 10851 10852 return 0; 10853 } 10854 10855 static void 10856 wm_nvm_version_invm(struct wm_softc *sc) 10857 { 10858 uint32_t dword; 10859 10860 /* 10861 * Linux's code to decode version is very strange, so we don't 10862 * obey that algorithm and just use word 61 as the document. 10863 * Perhaps it's not perfect though... 10864 * 10865 * Example: 10866 * 10867 * Word61: 00800030 -> Version 0.6 (I211 spec update notes about 0.6) 10868 */ 10869 dword = CSR_READ(sc, WM_INVM_DATA_REG(61)); 10870 dword = __SHIFTOUT(dword, INVM_VER_1); 10871 sc->sc_nvm_ver_major = __SHIFTOUT(dword, INVM_MAJOR); 10872 sc->sc_nvm_ver_minor = __SHIFTOUT(dword, INVM_MINOR); 10873 } 10874 10875 static void 10876 wm_nvm_version(struct wm_softc *sc) 10877 { 10878 uint16_t major, minor, build, patch; 10879 uint16_t uid0, uid1; 10880 uint16_t nvm_data; 10881 uint16_t off; 10882 bool check_version = false; 10883 bool check_optionrom = false; 10884 bool have_build = false; 10885 10886 /* 10887 * Version format: 10888 * 10889 * XYYZ 10890 * X0YZ 10891 * X0YY 10892 * 10893 * Example: 10894 * 10895 * 82571 0x50a2 5.10.2? (the spec update notes about 5.6-5.10) 10896 * 82571 0x50a6 5.10.6? 10897 * 82572 0x506a 5.6.10? 10898 * 82572EI 0x5069 5.6.9? 10899 * 82574L 0x1080 1.8.0? (the spec update notes about 2.1.4) 10900 * 0x2013 2.1.3? 10901 * 82583 0x10a0 1.10.0? (document says it's default vaule) 10902 */ 10903 wm_nvm_read(sc, NVM_OFF_IMAGE_UID1, 1, &uid1); 10904 switch (sc->sc_type) { 10905 case WM_T_82571: 10906 case WM_T_82572: 10907 case WM_T_82574: 10908 case WM_T_82583: 10909 check_version = true; 10910 check_optionrom = true; 10911 have_build = true; 10912 break; 10913 case WM_T_82575: 10914 case WM_T_82576: 10915 case WM_T_82580: 10916 if ((uid1 & NVM_MAJOR_MASK) != NVM_UID_VALID) 10917 check_version = true; 10918 break; 10919 case WM_T_I211: 10920 wm_nvm_version_invm(sc); 10921 goto printver; 10922 case WM_T_I210: 10923 if (!wm_nvm_get_flash_presence_i210(sc)) { 10924 wm_nvm_version_invm(sc); 10925 goto printver; 10926 } 10927 /* FALLTHROUGH */ 10928 case WM_T_I350: 10929 case WM_T_I354: 10930 check_version = true; 10931 check_optionrom = true; 10932 break; 10933 default: 10934 return; 10935 } 10936 if (check_version) { 10937 wm_nvm_read(sc, NVM_OFF_VERSION, 1, &nvm_data); 10938 major = (nvm_data & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 10939 if (have_build || ((nvm_data & 0x0f00) != 0x0000)) { 10940 minor = (nvm_data & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 10941 build = nvm_data & NVM_BUILD_MASK; 10942 have_build = true; 10943 } else 10944 minor = nvm_data & 0x00ff; 10945 10946 /* Decimal */ 10947 minor = (minor / 16) * 10 + (minor % 16); 10948 sc->sc_nvm_ver_major = major; 10949 sc->sc_nvm_ver_minor = minor; 10950 10951 printver: 10952 aprint_verbose(", version %d.%d", sc->sc_nvm_ver_major, 10953 sc->sc_nvm_ver_minor); 10954 if (have_build) { 10955 sc->sc_nvm_ver_build = build; 10956 aprint_verbose(".%d", build); 10957 } 10958 } 10959 if (check_optionrom) { 10960 wm_nvm_read(sc, NVM_OFF_COMB_VER_PTR, 1, &off); 10961 /* Option ROM Version */ 10962 if ((off != 0x0000) && (off != 0xffff)) { 10963 off += NVM_COMBO_VER_OFF; 10964 wm_nvm_read(sc, off + 1, 1, &uid1); 10965 wm_nvm_read(sc, off, 1, &uid0); 10966 if ((uid0 != 0) && (uid0 != 0xffff) 10967 && (uid1 != 0) && (uid1 != 0xffff)) { 10968 /* 16bits */ 10969 major = uid0 >> 8; 10970 build = (uid0 << 8) | (uid1 >> 8); 10971 patch = uid1 & 0x00ff; 10972 aprint_verbose(", option ROM Version %d.%d.%d", 10973 major, build, patch); 10974 } 10975 } 10976 } 10977 10978 wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0); 10979 aprint_verbose(", Image Unique ID %08x", (uid1 << 16) | uid0); 10980 } 10981 10982 /* 10983 * wm_nvm_read: 10984 * 10985 * Read data from the serial EEPROM. 10986 */ 10987 static int 10988 wm_nvm_read(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 10989 { 10990 int rv; 10991 10992 if (sc->sc_flags & WM_F_EEPROM_INVALID) 10993 return 1; 10994 10995 if (wm_nvm_acquire(sc)) 10996 return 1; 10997 10998 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 10999 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 11000 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) 11001 rv = wm_nvm_read_ich8(sc, word, wordcnt, data); 11002 else if (sc->sc_type == WM_T_PCH_SPT) 11003 rv = wm_nvm_read_spt(sc, word, wordcnt, data); 11004 else if (sc->sc_flags & WM_F_EEPROM_INVM) 11005 rv = wm_nvm_read_invm(sc, word, wordcnt, data); 11006 else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR) 11007 rv = wm_nvm_read_eerd(sc, word, wordcnt, data); 11008 else if (sc->sc_flags & WM_F_EEPROM_SPI) 11009 rv = wm_nvm_read_spi(sc, word, wordcnt, data); 11010 else 11011 rv = wm_nvm_read_uwire(sc, word, wordcnt, data); 11012 11013 wm_nvm_release(sc); 11014 return rv; 11015 } 11016 11017 /* 11018 * Hardware semaphores. 11019 * Very complexed... 11020 */ 11021 11022 static int 11023 wm_get_swsm_semaphore(struct wm_softc *sc) 11024 { 11025 int32_t timeout; 11026 uint32_t swsm; 11027 11028 if (sc->sc_flags & WM_F_LOCK_SWSM) { 11029 /* Get the SW semaphore. */ 11030 timeout = sc->sc_nvm_wordsize + 1; 11031 while (timeout) { 11032 swsm = CSR_READ(sc, WMREG_SWSM); 11033 11034 if ((swsm & SWSM_SMBI) == 0) 11035 break; 11036 11037 delay(50); 11038 timeout--; 11039 } 11040 11041 if (timeout == 0) { 11042 aprint_error_dev(sc->sc_dev, 11043 "could not acquire SWSM SMBI\n"); 11044 return 1; 11045 } 11046 } 11047 11048 /* Get the FW semaphore. */ 11049 timeout = sc->sc_nvm_wordsize + 1; 11050 while (timeout) { 11051 swsm = CSR_READ(sc, WMREG_SWSM); 11052 swsm |= SWSM_SWESMBI; 11053 CSR_WRITE(sc, WMREG_SWSM, swsm); 11054 /* If we managed to set the bit we got the semaphore. */ 11055 swsm = CSR_READ(sc, WMREG_SWSM); 11056 if (swsm & SWSM_SWESMBI) 11057 break; 11058 11059 delay(50); 11060 timeout--; 11061 } 11062 11063 if (timeout == 0) { 11064 aprint_error_dev(sc->sc_dev, 11065 "could not acquire SWSM SWESMBI\n"); 11066 /* Release semaphores */ 11067 wm_put_swsm_semaphore(sc); 11068 return 1; 11069 } 11070 return 0; 11071 } 11072 11073 static void 11074 wm_put_swsm_semaphore(struct wm_softc *sc) 11075 { 11076 uint32_t swsm; 11077 11078 swsm = CSR_READ(sc, WMREG_SWSM); 11079 swsm &= ~(SWSM_SMBI | SWSM_SWESMBI); 11080 CSR_WRITE(sc, WMREG_SWSM, swsm); 11081 } 11082 11083 static int 11084 wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask) 11085 { 11086 uint32_t swfw_sync; 11087 uint32_t swmask = mask << SWFW_SOFT_SHIFT; 11088 uint32_t fwmask = mask << SWFW_FIRM_SHIFT; 11089 int timeout = 200; 11090 11091 for (timeout = 0; timeout < 200; timeout++) { 11092 if (sc->sc_flags & WM_F_LOCK_SWSM) { 11093 if (wm_get_swsm_semaphore(sc)) { 11094 aprint_error_dev(sc->sc_dev, 11095 "%s: failed to get semaphore\n", 11096 __func__); 11097 return 1; 11098 } 11099 } 11100 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC); 11101 if ((swfw_sync & (swmask | fwmask)) == 0) { 11102 swfw_sync |= swmask; 11103 CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync); 11104 if (sc->sc_flags & WM_F_LOCK_SWSM) 11105 wm_put_swsm_semaphore(sc); 11106 return 0; 11107 } 11108 if (sc->sc_flags & WM_F_LOCK_SWSM) 11109 wm_put_swsm_semaphore(sc); 11110 delay(5000); 11111 } 11112 printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n", 11113 device_xname(sc->sc_dev), mask, swfw_sync); 11114 return 1; 11115 } 11116 11117 static void 11118 wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask) 11119 { 11120 uint32_t swfw_sync; 11121 11122 if (sc->sc_flags & WM_F_LOCK_SWSM) { 11123 while (wm_get_swsm_semaphore(sc) != 0) 11124 continue; 11125 } 11126 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC); 11127 swfw_sync &= ~(mask << SWFW_SOFT_SHIFT); 11128 CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync); 11129 if (sc->sc_flags & WM_F_LOCK_SWSM) 11130 wm_put_swsm_semaphore(sc); 11131 } 11132 11133 static int 11134 wm_get_swfwhw_semaphore(struct wm_softc *sc) 11135 { 11136 uint32_t ext_ctrl; 11137 int timeout = 200; 11138 11139 for (timeout = 0; timeout < 200; timeout++) { 11140 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 11141 ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP; 11142 CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl); 11143 11144 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 11145 if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) 11146 return 0; 11147 delay(5000); 11148 } 11149 printf("%s: failed to get swfwhw semaphore ext_ctrl 0x%x\n", 11150 device_xname(sc->sc_dev), ext_ctrl); 11151 return 1; 11152 } 11153 11154 static void 11155 wm_put_swfwhw_semaphore(struct wm_softc *sc) 11156 { 11157 uint32_t ext_ctrl; 11158 11159 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 11160 ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP; 11161 CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl); 11162 } 11163 11164 static int 11165 wm_get_hw_semaphore_82573(struct wm_softc *sc) 11166 { 11167 int i = 0; 11168 uint32_t reg; 11169 11170 reg = CSR_READ(sc, WMREG_EXTCNFCTR); 11171 do { 11172 CSR_WRITE(sc, WMREG_EXTCNFCTR, 11173 reg | EXTCNFCTR_MDIO_SW_OWNERSHIP); 11174 reg = CSR_READ(sc, WMREG_EXTCNFCTR); 11175 if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0) 11176 break; 11177 delay(2*1000); 11178 i++; 11179 } while (i < WM_MDIO_OWNERSHIP_TIMEOUT); 11180 11181 if (i == WM_MDIO_OWNERSHIP_TIMEOUT) { 11182 wm_put_hw_semaphore_82573(sc); 11183 log(LOG_ERR, "%s: Driver can't access the PHY\n", 11184 device_xname(sc->sc_dev)); 11185 return -1; 11186 } 11187 11188 return 0; 11189 } 11190 11191 static void 11192 wm_put_hw_semaphore_82573(struct wm_softc *sc) 11193 { 11194 uint32_t reg; 11195 11196 reg = CSR_READ(sc, WMREG_EXTCNFCTR); 11197 reg &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP; 11198 CSR_WRITE(sc, WMREG_EXTCNFCTR, reg); 11199 } 11200 11201 /* 11202 * Management mode and power management related subroutines. 11203 * BMC, AMT, suspend/resume and EEE. 11204 */ 11205 11206 #ifdef WM_WOL 11207 static int 11208 wm_check_mng_mode(struct wm_softc *sc) 11209 { 11210 int rv; 11211 11212 switch (sc->sc_type) { 11213 case WM_T_ICH8: 11214 case WM_T_ICH9: 11215 case WM_T_ICH10: 11216 case WM_T_PCH: 11217 case WM_T_PCH2: 11218 case WM_T_PCH_LPT: 11219 case WM_T_PCH_SPT: 11220 rv = wm_check_mng_mode_ich8lan(sc); 11221 break; 11222 case WM_T_82574: 11223 case WM_T_82583: 11224 rv = wm_check_mng_mode_82574(sc); 11225 break; 11226 case WM_T_82571: 11227 case WM_T_82572: 11228 case WM_T_82573: 11229 case WM_T_80003: 11230 rv = wm_check_mng_mode_generic(sc); 11231 break; 11232 default: 11233 /* noting to do */ 11234 rv = 0; 11235 break; 11236 } 11237 11238 return rv; 11239 } 11240 11241 static int 11242 wm_check_mng_mode_ich8lan(struct wm_softc *sc) 11243 { 11244 uint32_t fwsm; 11245 11246 fwsm = CSR_READ(sc, WMREG_FWSM); 11247 11248 if (((fwsm & FWSM_FW_VALID) != 0) 11249 && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE)) 11250 return 1; 11251 11252 return 0; 11253 } 11254 11255 static int 11256 wm_check_mng_mode_82574(struct wm_softc *sc) 11257 { 11258 uint16_t data; 11259 11260 wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data); 11261 11262 if ((data & NVM_CFG2_MNGM_MASK) != 0) 11263 return 1; 11264 11265 return 0; 11266 } 11267 11268 static int 11269 wm_check_mng_mode_generic(struct wm_softc *sc) 11270 { 11271 uint32_t fwsm; 11272 11273 fwsm = CSR_READ(sc, WMREG_FWSM); 11274 11275 if (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_IAMT_MODE) 11276 return 1; 11277 11278 return 0; 11279 } 11280 #endif /* WM_WOL */ 11281 11282 static int 11283 wm_enable_mng_pass_thru(struct wm_softc *sc) 11284 { 11285 uint32_t manc, fwsm, factps; 11286 11287 if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) == 0) 11288 return 0; 11289 11290 manc = CSR_READ(sc, WMREG_MANC); 11291 11292 DPRINTF(WM_DEBUG_MANAGE, ("%s: MANC (%08x)\n", 11293 device_xname(sc->sc_dev), manc)); 11294 if ((manc & MANC_RECV_TCO_EN) == 0) 11295 return 0; 11296 11297 if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) { 11298 fwsm = CSR_READ(sc, WMREG_FWSM); 11299 factps = CSR_READ(sc, WMREG_FACTPS); 11300 if (((factps & FACTPS_MNGCG) == 0) 11301 && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE)) 11302 return 1; 11303 } else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){ 11304 uint16_t data; 11305 11306 factps = CSR_READ(sc, WMREG_FACTPS); 11307 wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data); 11308 DPRINTF(WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n", 11309 device_xname(sc->sc_dev), factps, data)); 11310 if (((factps & FACTPS_MNGCG) == 0) 11311 && ((data & NVM_CFG2_MNGM_MASK) 11312 == (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT))) 11313 return 1; 11314 } else if (((manc & MANC_SMBUS_EN) != 0) 11315 && ((manc & MANC_ASF_EN) == 0)) 11316 return 1; 11317 11318 return 0; 11319 } 11320 11321 static bool 11322 wm_phy_resetisblocked(struct wm_softc *sc) 11323 { 11324 bool blocked = false; 11325 uint32_t reg; 11326 int i = 0; 11327 11328 switch (sc->sc_type) { 11329 case WM_T_ICH8: 11330 case WM_T_ICH9: 11331 case WM_T_ICH10: 11332 case WM_T_PCH: 11333 case WM_T_PCH2: 11334 case WM_T_PCH_LPT: 11335 case WM_T_PCH_SPT: 11336 do { 11337 reg = CSR_READ(sc, WMREG_FWSM); 11338 if ((reg & FWSM_RSPCIPHY) == 0) { 11339 blocked = true; 11340 delay(10*1000); 11341 continue; 11342 } 11343 blocked = false; 11344 } while (blocked && (i++ < 10)); 11345 return blocked; 11346 break; 11347 case WM_T_82571: 11348 case WM_T_82572: 11349 case WM_T_82573: 11350 case WM_T_82574: 11351 case WM_T_82583: 11352 case WM_T_80003: 11353 reg = CSR_READ(sc, WMREG_MANC); 11354 if ((reg & MANC_BLK_PHY_RST_ON_IDE) != 0) 11355 return true; 11356 else 11357 return false; 11358 break; 11359 default: 11360 /* no problem */ 11361 break; 11362 } 11363 11364 return false; 11365 } 11366 11367 static void 11368 wm_get_hw_control(struct wm_softc *sc) 11369 { 11370 uint32_t reg; 11371 11372 switch (sc->sc_type) { 11373 case WM_T_82573: 11374 reg = CSR_READ(sc, WMREG_SWSM); 11375 CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD); 11376 break; 11377 case WM_T_82571: 11378 case WM_T_82572: 11379 case WM_T_82574: 11380 case WM_T_82583: 11381 case WM_T_80003: 11382 case WM_T_ICH8: 11383 case WM_T_ICH9: 11384 case WM_T_ICH10: 11385 case WM_T_PCH: 11386 case WM_T_PCH2: 11387 case WM_T_PCH_LPT: 11388 case WM_T_PCH_SPT: 11389 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11390 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD); 11391 break; 11392 default: 11393 break; 11394 } 11395 } 11396 11397 static void 11398 wm_release_hw_control(struct wm_softc *sc) 11399 { 11400 uint32_t reg; 11401 11402 if ((sc->sc_flags & WM_F_HAS_MANAGE) == 0) 11403 return; 11404 11405 if (sc->sc_type == WM_T_82573) { 11406 reg = CSR_READ(sc, WMREG_SWSM); 11407 reg &= ~SWSM_DRV_LOAD; 11408 CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_DRV_LOAD); 11409 } else { 11410 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11411 CSR_WRITE(sc, WMREG_CTRL_EXT, reg & ~CTRL_EXT_DRV_LOAD); 11412 } 11413 } 11414 11415 static void 11416 wm_gate_hw_phy_config_ich8lan(struct wm_softc *sc, bool gate) 11417 { 11418 uint32_t reg; 11419 11420 if (sc->sc_type < WM_T_PCH2) 11421 return; 11422 11423 reg = CSR_READ(sc, WMREG_EXTCNFCTR); 11424 11425 if (gate) 11426 reg |= EXTCNFCTR_GATE_PHY_CFG; 11427 else 11428 reg &= ~EXTCNFCTR_GATE_PHY_CFG; 11429 11430 CSR_WRITE(sc, WMREG_EXTCNFCTR, reg); 11431 } 11432 11433 static void 11434 wm_smbustopci(struct wm_softc *sc) 11435 { 11436 uint32_t fwsm, reg; 11437 11438 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 11439 wm_gate_hw_phy_config_ich8lan(sc, true); 11440 11441 /* Acquire semaphore */ 11442 wm_get_swfwhw_semaphore(sc); 11443 11444 fwsm = CSR_READ(sc, WMREG_FWSM); 11445 if (((fwsm & FWSM_FW_VALID) == 0) 11446 && ((wm_phy_resetisblocked(sc) == false))) { 11447 if (sc->sc_type >= WM_T_PCH_LPT) { 11448 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11449 reg |= CTRL_EXT_FORCE_SMBUS; 11450 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 11451 CSR_WRITE_FLUSH(sc); 11452 delay(50*1000); 11453 } 11454 11455 /* Toggle LANPHYPC */ 11456 sc->sc_ctrl |= CTRL_LANPHYPC_OVERRIDE; 11457 sc->sc_ctrl &= ~CTRL_LANPHYPC_VALUE; 11458 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 11459 CSR_WRITE_FLUSH(sc); 11460 delay(10); 11461 sc->sc_ctrl &= ~CTRL_LANPHYPC_OVERRIDE; 11462 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 11463 CSR_WRITE_FLUSH(sc); 11464 delay(50*1000); 11465 11466 if (sc->sc_type >= WM_T_PCH_LPT) { 11467 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11468 reg &= ~CTRL_EXT_FORCE_SMBUS; 11469 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 11470 } 11471 } 11472 11473 /* Release semaphore */ 11474 wm_put_swfwhw_semaphore(sc); 11475 11476 /* 11477 * Ungate automatic PHY configuration by hardware on non-managed 82579 11478 */ 11479 if ((sc->sc_type == WM_T_PCH2) && ((fwsm & FWSM_FW_VALID) == 0)) 11480 wm_gate_hw_phy_config_ich8lan(sc, false); 11481 } 11482 11483 static void 11484 wm_init_manageability(struct wm_softc *sc) 11485 { 11486 11487 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 11488 device_xname(sc->sc_dev), __func__)); 11489 if (sc->sc_flags & WM_F_HAS_MANAGE) { 11490 uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H); 11491 uint32_t manc = CSR_READ(sc, WMREG_MANC); 11492 11493 /* Disable hardware interception of ARP */ 11494 manc &= ~MANC_ARP_EN; 11495 11496 /* Enable receiving management packets to the host */ 11497 if (sc->sc_type >= WM_T_82571) { 11498 manc |= MANC_EN_MNG2HOST; 11499 manc2h |= MANC2H_PORT_623| MANC2H_PORT_624; 11500 CSR_WRITE(sc, WMREG_MANC2H, manc2h); 11501 } 11502 11503 CSR_WRITE(sc, WMREG_MANC, manc); 11504 } 11505 } 11506 11507 static void 11508 wm_release_manageability(struct wm_softc *sc) 11509 { 11510 11511 if (sc->sc_flags & WM_F_HAS_MANAGE) { 11512 uint32_t manc = CSR_READ(sc, WMREG_MANC); 11513 11514 manc |= MANC_ARP_EN; 11515 if (sc->sc_type >= WM_T_82571) 11516 manc &= ~MANC_EN_MNG2HOST; 11517 11518 CSR_WRITE(sc, WMREG_MANC, manc); 11519 } 11520 } 11521 11522 static void 11523 wm_get_wakeup(struct wm_softc *sc) 11524 { 11525 11526 /* 0: HAS_AMT, ARC_SUBSYS_VALID, ASF_FIRMWARE_PRES */ 11527 switch (sc->sc_type) { 11528 case WM_T_82573: 11529 case WM_T_82583: 11530 sc->sc_flags |= WM_F_HAS_AMT; 11531 /* FALLTHROUGH */ 11532 case WM_T_80003: 11533 case WM_T_82541: 11534 case WM_T_82547: 11535 case WM_T_82571: 11536 case WM_T_82572: 11537 case WM_T_82574: 11538 case WM_T_82575: 11539 case WM_T_82576: 11540 case WM_T_82580: 11541 case WM_T_I350: 11542 case WM_T_I354: 11543 if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE) != 0) 11544 sc->sc_flags |= WM_F_ARC_SUBSYS_VALID; 11545 sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES; 11546 break; 11547 case WM_T_ICH8: 11548 case WM_T_ICH9: 11549 case WM_T_ICH10: 11550 case WM_T_PCH: 11551 case WM_T_PCH2: 11552 case WM_T_PCH_LPT: 11553 case WM_T_PCH_SPT: /* XXX only Q170 chipset? */ 11554 sc->sc_flags |= WM_F_HAS_AMT; 11555 sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES; 11556 break; 11557 default: 11558 break; 11559 } 11560 11561 /* 1: HAS_MANAGE */ 11562 if (wm_enable_mng_pass_thru(sc) != 0) 11563 sc->sc_flags |= WM_F_HAS_MANAGE; 11564 11565 #ifdef WM_DEBUG 11566 printf("\n"); 11567 if ((sc->sc_flags & WM_F_HAS_AMT) != 0) 11568 printf("HAS_AMT,"); 11569 if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) 11570 printf("ARC_SUBSYS_VALID,"); 11571 if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) != 0) 11572 printf("ASF_FIRMWARE_PRES,"); 11573 if ((sc->sc_flags & WM_F_HAS_MANAGE) != 0) 11574 printf("HAS_MANAGE,"); 11575 printf("\n"); 11576 #endif 11577 /* 11578 * Note that the WOL flags is set after the resetting of the eeprom 11579 * stuff 11580 */ 11581 } 11582 11583 #ifdef WM_WOL 11584 /* WOL in the newer chipset interfaces (pchlan) */ 11585 static void 11586 wm_enable_phy_wakeup(struct wm_softc *sc) 11587 { 11588 #if 0 11589 uint16_t preg; 11590 11591 /* Copy MAC RARs to PHY RARs */ 11592 11593 /* Copy MAC MTA to PHY MTA */ 11594 11595 /* Configure PHY Rx Control register */ 11596 11597 /* Enable PHY wakeup in MAC register */ 11598 11599 /* Configure and enable PHY wakeup in PHY registers */ 11600 11601 /* Activate PHY wakeup */ 11602 11603 /* XXX */ 11604 #endif 11605 } 11606 11607 /* Power down workaround on D3 */ 11608 static void 11609 wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *sc) 11610 { 11611 uint32_t reg; 11612 int i; 11613 11614 for (i = 0; i < 2; i++) { 11615 /* Disable link */ 11616 reg = CSR_READ(sc, WMREG_PHY_CTRL); 11617 reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS; 11618 CSR_WRITE(sc, WMREG_PHY_CTRL, reg); 11619 11620 /* 11621 * Call gig speed drop workaround on Gig disable before 11622 * accessing any PHY registers 11623 */ 11624 if (sc->sc_type == WM_T_ICH8) 11625 wm_gig_downshift_workaround_ich8lan(sc); 11626 11627 /* Write VR power-down enable */ 11628 reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL); 11629 reg &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 11630 reg |= IGP3_VR_CTRL_MODE_SHUTDOWN; 11631 sc->sc_mii.mii_writereg(sc->sc_dev, 1, IGP3_VR_CTRL, reg); 11632 11633 /* Read it back and test */ 11634 reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL); 11635 reg &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 11636 if ((reg == IGP3_VR_CTRL_MODE_SHUTDOWN) || (i != 0)) 11637 break; 11638 11639 /* Issue PHY reset and repeat at most one more time */ 11640 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 11641 } 11642 } 11643 11644 static void 11645 wm_enable_wakeup(struct wm_softc *sc) 11646 { 11647 uint32_t reg, pmreg; 11648 pcireg_t pmode; 11649 11650 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT, 11651 &pmreg, NULL) == 0) 11652 return; 11653 11654 /* Advertise the wakeup capability */ 11655 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_SWDPIN(2) 11656 | CTRL_SWDPIN(3)); 11657 CSR_WRITE(sc, WMREG_WUC, WUC_APME); 11658 11659 /* ICH workaround */ 11660 switch (sc->sc_type) { 11661 case WM_T_ICH8: 11662 case WM_T_ICH9: 11663 case WM_T_ICH10: 11664 case WM_T_PCH: 11665 case WM_T_PCH2: 11666 case WM_T_PCH_LPT: 11667 case WM_T_PCH_SPT: 11668 /* Disable gig during WOL */ 11669 reg = CSR_READ(sc, WMREG_PHY_CTRL); 11670 reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS; 11671 CSR_WRITE(sc, WMREG_PHY_CTRL, reg); 11672 if (sc->sc_type == WM_T_PCH) 11673 wm_gmii_reset(sc); 11674 11675 /* Power down workaround */ 11676 if (sc->sc_phytype == WMPHY_82577) { 11677 struct mii_softc *child; 11678 11679 /* Assume that the PHY is copper */ 11680 child = LIST_FIRST(&sc->sc_mii.mii_phys); 11681 if (child->mii_mpd_rev <= 2) 11682 sc->sc_mii.mii_writereg(sc->sc_dev, 1, 11683 (768 << 5) | 25, 0x0444); /* magic num */ 11684 } 11685 break; 11686 default: 11687 break; 11688 } 11689 11690 /* Keep the laser running on fiber adapters */ 11691 if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER) 11692 || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) { 11693 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11694 reg |= CTRL_EXT_SWDPIN(3); 11695 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 11696 } 11697 11698 reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG; 11699 #if 0 /* for the multicast packet */ 11700 reg |= WUFC_MC; 11701 CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE); 11702 #endif 11703 11704 if (sc->sc_type == WM_T_PCH) { 11705 wm_enable_phy_wakeup(sc); 11706 } else { 11707 CSR_WRITE(sc, WMREG_WUC, WUC_PME_EN); 11708 CSR_WRITE(sc, WMREG_WUFC, reg); 11709 } 11710 11711 if (((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 11712 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 11713 || (sc->sc_type == WM_T_PCH2)) 11714 && (sc->sc_phytype == WMPHY_IGP_3)) 11715 wm_igp3_phy_powerdown_workaround_ich8lan(sc); 11716 11717 /* Request PME */ 11718 pmode = pci_conf_read(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR); 11719 #if 0 11720 /* Disable WOL */ 11721 pmode &= ~(PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN); 11722 #else 11723 /* For WOL */ 11724 pmode |= PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN; 11725 #endif 11726 pci_conf_write(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR, pmode); 11727 } 11728 #endif /* WM_WOL */ 11729 11730 /* LPLU */ 11731 11732 static void 11733 wm_lplu_d0_disable(struct wm_softc *sc) 11734 { 11735 uint32_t reg; 11736 11737 reg = CSR_READ(sc, WMREG_PHY_CTRL); 11738 reg &= ~(PHY_CTRL_GBE_DIS | PHY_CTRL_D0A_LPLU); 11739 CSR_WRITE(sc, WMREG_PHY_CTRL, reg); 11740 } 11741 11742 static void 11743 wm_lplu_d0_disable_pch(struct wm_softc *sc) 11744 { 11745 uint32_t reg; 11746 11747 reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_OEM_BITS); 11748 reg &= ~(HV_OEM_BITS_A1KDIS | HV_OEM_BITS_LPLU); 11749 reg |= HV_OEM_BITS_ANEGNOW; 11750 wm_gmii_hv_writereg(sc->sc_dev, 1, HV_OEM_BITS, reg); 11751 } 11752 11753 /* EEE */ 11754 11755 static void 11756 wm_set_eee_i350(struct wm_softc *sc) 11757 { 11758 uint32_t ipcnfg, eeer; 11759 11760 ipcnfg = CSR_READ(sc, WMREG_IPCNFG); 11761 eeer = CSR_READ(sc, WMREG_EEER); 11762 11763 if ((sc->sc_flags & WM_F_EEE) != 0) { 11764 ipcnfg |= (IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN); 11765 eeer |= (EEER_TX_LPI_EN | EEER_RX_LPI_EN 11766 | EEER_LPI_FC); 11767 } else { 11768 ipcnfg &= ~(IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN); 11769 ipcnfg &= ~IPCNFG_10BASE_TE; 11770 eeer &= ~(EEER_TX_LPI_EN | EEER_RX_LPI_EN 11771 | EEER_LPI_FC); 11772 } 11773 11774 CSR_WRITE(sc, WMREG_IPCNFG, ipcnfg); 11775 CSR_WRITE(sc, WMREG_EEER, eeer); 11776 CSR_READ(sc, WMREG_IPCNFG); /* XXX flush? */ 11777 CSR_READ(sc, WMREG_EEER); /* XXX flush? */ 11778 } 11779 11780 /* 11781 * Workarounds (mainly PHY related). 11782 * Basically, PHY's workarounds are in the PHY drivers. 11783 */ 11784 11785 /* Work-around for 82566 Kumeran PCS lock loss */ 11786 static void 11787 wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *sc) 11788 { 11789 #if 0 11790 int miistatus, active, i; 11791 int reg; 11792 11793 miistatus = sc->sc_mii.mii_media_status; 11794 11795 /* If the link is not up, do nothing */ 11796 if ((miistatus & IFM_ACTIVE) == 0) 11797 return; 11798 11799 active = sc->sc_mii.mii_media_active; 11800 11801 /* Nothing to do if the link is other than 1Gbps */ 11802 if (IFM_SUBTYPE(active) != IFM_1000_T) 11803 return; 11804 11805 for (i = 0; i < 10; i++) { 11806 /* read twice */ 11807 reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG); 11808 reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG); 11809 if ((reg & IGP3_KMRN_DIAG_PCS_LOCK_LOSS) == 0) 11810 goto out; /* GOOD! */ 11811 11812 /* Reset the PHY */ 11813 wm_gmii_reset(sc); 11814 delay(5*1000); 11815 } 11816 11817 /* Disable GigE link negotiation */ 11818 reg = CSR_READ(sc, WMREG_PHY_CTRL); 11819 reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS; 11820 CSR_WRITE(sc, WMREG_PHY_CTRL, reg); 11821 11822 /* 11823 * Call gig speed drop workaround on Gig disable before accessing 11824 * any PHY registers. 11825 */ 11826 wm_gig_downshift_workaround_ich8lan(sc); 11827 11828 out: 11829 return; 11830 #endif 11831 } 11832 11833 /* WOL from S5 stops working */ 11834 static void 11835 wm_gig_downshift_workaround_ich8lan(struct wm_softc *sc) 11836 { 11837 uint16_t kmrn_reg; 11838 11839 /* Only for igp3 */ 11840 if (sc->sc_phytype == WMPHY_IGP_3) { 11841 kmrn_reg = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_DIAG); 11842 kmrn_reg |= KUMCTRLSTA_DIAG_NELPBK; 11843 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg); 11844 kmrn_reg &= ~KUMCTRLSTA_DIAG_NELPBK; 11845 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg); 11846 } 11847 } 11848 11849 /* 11850 * Workaround for pch's PHYs 11851 * XXX should be moved to new PHY driver? 11852 */ 11853 static void 11854 wm_hv_phy_workaround_ich8lan(struct wm_softc *sc) 11855 { 11856 if (sc->sc_phytype == WMPHY_82577) 11857 wm_set_mdio_slow_mode_hv(sc); 11858 11859 /* (PCH rev.2) && (82577 && (phy rev 2 or 3)) */ 11860 11861 /* (82577 && (phy rev 1 or 2)) || (82578 & phy rev 1)*/ 11862 11863 /* 82578 */ 11864 if (sc->sc_phytype == WMPHY_82578) { 11865 /* PCH rev. < 3 */ 11866 if (sc->sc_rev < 3) { 11867 /* XXX 6 bit shift? Why? Is it page2? */ 11868 wm_gmii_hv_writereg(sc->sc_dev, 1, ((1 << 6) | 0x29), 11869 0x66c0); 11870 wm_gmii_hv_writereg(sc->sc_dev, 1, ((1 << 6) | 0x1e), 11871 0xffff); 11872 } 11873 11874 /* XXX phy rev. < 2 */ 11875 } 11876 11877 /* Select page 0 */ 11878 11879 /* XXX acquire semaphore */ 11880 wm_gmii_i82544_writereg(sc->sc_dev, 1, MII_IGPHY_PAGE_SELECT, 0); 11881 /* XXX release semaphore */ 11882 11883 /* 11884 * Configure the K1 Si workaround during phy reset assuming there is 11885 * link so that it disables K1 if link is in 1Gbps. 11886 */ 11887 wm_k1_gig_workaround_hv(sc, 1); 11888 } 11889 11890 static void 11891 wm_lv_phy_workaround_ich8lan(struct wm_softc *sc) 11892 { 11893 11894 wm_set_mdio_slow_mode_hv(sc); 11895 } 11896 11897 static void 11898 wm_k1_gig_workaround_hv(struct wm_softc *sc, int link) 11899 { 11900 int k1_enable = sc->sc_nvm_k1_enabled; 11901 11902 /* XXX acquire semaphore */ 11903 11904 if (link) { 11905 k1_enable = 0; 11906 11907 /* Link stall fix for link up */ 11908 wm_gmii_hv_writereg(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x0100); 11909 } else { 11910 /* Link stall fix for link down */ 11911 wm_gmii_hv_writereg(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x4100); 11912 } 11913 11914 wm_configure_k1_ich8lan(sc, k1_enable); 11915 11916 /* XXX release semaphore */ 11917 } 11918 11919 static void 11920 wm_set_mdio_slow_mode_hv(struct wm_softc *sc) 11921 { 11922 uint32_t reg; 11923 11924 reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL); 11925 wm_gmii_hv_writereg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL, 11926 reg | HV_KMRN_MDIO_SLOW); 11927 } 11928 11929 static void 11930 wm_configure_k1_ich8lan(struct wm_softc *sc, int k1_enable) 11931 { 11932 uint32_t ctrl, ctrl_ext, tmp; 11933 uint16_t kmrn_reg; 11934 11935 kmrn_reg = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_K1_CONFIG); 11936 11937 if (k1_enable) 11938 kmrn_reg |= KUMCTRLSTA_K1_ENABLE; 11939 else 11940 kmrn_reg &= ~KUMCTRLSTA_K1_ENABLE; 11941 11942 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, kmrn_reg); 11943 11944 delay(20); 11945 11946 ctrl = CSR_READ(sc, WMREG_CTRL); 11947 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT); 11948 11949 tmp = ctrl & ~(CTRL_SPEED_1000 | CTRL_SPEED_100); 11950 tmp |= CTRL_FRCSPD; 11951 11952 CSR_WRITE(sc, WMREG_CTRL, tmp); 11953 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_SPD_BYPS); 11954 CSR_WRITE_FLUSH(sc); 11955 delay(20); 11956 11957 CSR_WRITE(sc, WMREG_CTRL, ctrl); 11958 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext); 11959 CSR_WRITE_FLUSH(sc); 11960 delay(20); 11961 } 11962 11963 /* special case - for 82575 - need to do manual init ... */ 11964 static void 11965 wm_reset_init_script_82575(struct wm_softc *sc) 11966 { 11967 /* 11968 * remark: this is untested code - we have no board without EEPROM 11969 * same setup as mentioned int the FreeBSD driver for the i82575 11970 */ 11971 11972 /* SerDes configuration via SERDESCTRL */ 11973 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x00, 0x0c); 11974 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x01, 0x78); 11975 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x1b, 0x23); 11976 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x23, 0x15); 11977 11978 /* CCM configuration via CCMCTL register */ 11979 wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x14, 0x00); 11980 wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x10, 0x00); 11981 11982 /* PCIe lanes configuration */ 11983 wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x00, 0xec); 11984 wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x61, 0xdf); 11985 wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x34, 0x05); 11986 wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x2f, 0x81); 11987 11988 /* PCIe PLL Configuration */ 11989 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x02, 0x47); 11990 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x14, 0x00); 11991 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x10, 0x00); 11992 } 11993 11994 static void 11995 wm_reset_mdicnfg_82580(struct wm_softc *sc) 11996 { 11997 uint32_t reg; 11998 uint16_t nvmword; 11999 int rv; 12000 12001 if ((sc->sc_flags & WM_F_SGMII) == 0) 12002 return; 12003 12004 rv = wm_nvm_read(sc, NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) 12005 + NVM_OFF_CFG3_PORTA, 1, &nvmword); 12006 if (rv != 0) { 12007 aprint_error_dev(sc->sc_dev, "%s: failed to read NVM\n", 12008 __func__); 12009 return; 12010 } 12011 12012 reg = CSR_READ(sc, WMREG_MDICNFG); 12013 if (nvmword & NVM_CFG3_PORTA_EXT_MDIO) 12014 reg |= MDICNFG_DEST; 12015 if (nvmword & NVM_CFG3_PORTA_COM_MDIO) 12016 reg |= MDICNFG_COM_MDIO; 12017 CSR_WRITE(sc, WMREG_MDICNFG, reg); 12018 } 12019 12020 /* 12021 * I210 Errata 25 and I211 Errata 10 12022 * Slow System Clock. 12023 */ 12024 static void 12025 wm_pll_workaround_i210(struct wm_softc *sc) 12026 { 12027 uint32_t mdicnfg, wuc; 12028 uint32_t reg; 12029 pcireg_t pcireg; 12030 uint32_t pmreg; 12031 uint16_t nvmword, tmp_nvmword; 12032 int phyval; 12033 bool wa_done = false; 12034 int i; 12035 12036 /* Save WUC and MDICNFG registers */ 12037 wuc = CSR_READ(sc, WMREG_WUC); 12038 mdicnfg = CSR_READ(sc, WMREG_MDICNFG); 12039 12040 reg = mdicnfg & ~MDICNFG_DEST; 12041 CSR_WRITE(sc, WMREG_MDICNFG, reg); 12042 12043 if (wm_nvm_read(sc, INVM_AUTOLOAD, 1, &nvmword) != 0) 12044 nvmword = INVM_DEFAULT_AL; 12045 tmp_nvmword = nvmword | INVM_PLL_WO_VAL; 12046 12047 /* Get Power Management cap offset */ 12048 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT, 12049 &pmreg, NULL) == 0) 12050 return; 12051 for (i = 0; i < WM_MAX_PLL_TRIES; i++) { 12052 phyval = wm_gmii_gs40g_readreg(sc->sc_dev, 1, 12053 GS40G_PHY_PLL_FREQ_PAGE | GS40G_PHY_PLL_FREQ_REG); 12054 12055 if ((phyval & GS40G_PHY_PLL_UNCONF) != GS40G_PHY_PLL_UNCONF) { 12056 break; /* OK */ 12057 } 12058 12059 wa_done = true; 12060 /* Directly reset the internal PHY */ 12061 reg = CSR_READ(sc, WMREG_CTRL); 12062 CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET); 12063 12064 reg = CSR_READ(sc, WMREG_CTRL_EXT); 12065 reg |= CTRL_EXT_PHYPDEN | CTRL_EXT_SDLPE; 12066 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 12067 12068 CSR_WRITE(sc, WMREG_WUC, 0); 12069 reg = (INVM_AUTOLOAD << 4) | (tmp_nvmword << 16); 12070 CSR_WRITE(sc, WMREG_EEARBC_I210, reg); 12071 12072 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 12073 pmreg + PCI_PMCSR); 12074 pcireg |= PCI_PMCSR_STATE_D3; 12075 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 12076 pmreg + PCI_PMCSR, pcireg); 12077 delay(1000); 12078 pcireg &= ~PCI_PMCSR_STATE_D3; 12079 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 12080 pmreg + PCI_PMCSR, pcireg); 12081 12082 reg = (INVM_AUTOLOAD << 4) | (nvmword << 16); 12083 CSR_WRITE(sc, WMREG_EEARBC_I210, reg); 12084 12085 /* Restore WUC register */ 12086 CSR_WRITE(sc, WMREG_WUC, wuc); 12087 } 12088 12089 /* Restore MDICNFG setting */ 12090 CSR_WRITE(sc, WMREG_MDICNFG, mdicnfg); 12091 if (wa_done) 12092 aprint_verbose_dev(sc->sc_dev, "I210 workaround done\n"); 12093 } 12094
Indexes created Thu Sep 25 16:09:42 GMT 2025