if_wm.c revision 1.396
1 /* $NetBSD: if_wm.c,v 1.396 2016/05/11 03:46:06 knakahara Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /******************************************************************************* 39 40 Copyright (c) 2001-2005, Intel Corporation 41 All rights reserved. 42 43 Redistribution and use in source and binary forms, with or without 44 modification, are permitted provided that the following conditions are met: 45 46 1. Redistributions of source code must retain the above copyright notice, 47 this list of conditions and the following disclaimer. 48 49 2. Redistributions in binary form must reproduce the above copyright 50 notice, this list of conditions and the following disclaimer in the 51 documentation and/or other materials provided with the distribution. 52 53 3. Neither the name of the Intel Corporation nor the names of its 54 contributors may be used to endorse or promote products derived from 55 this software without specific prior written permission. 56 57 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 58 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 61 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 POSSIBILITY OF SUCH DAMAGE. 68 69 *******************************************************************************/ 70 /* 71 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 72 * 73 * TODO (in order of importance): 74 * 75 * - Check XXX'ed comments 76 * - Disable D0 LPLU on 8257[12356], 82580 and I350. 77 * - TX Multi queue 78 * - EEE (Energy Efficiency Ethernet) 79 * - Virtual Function 80 * - Set LED correctly (based on contents in EEPROM) 81 * - Rework how parameters are loaded from the EEPROM. 82 * - Image Unique ID 83 */ 84 85 #include <sys/cdefs.h> 86 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.396 2016/05/11 03:46:06 knakahara Exp $"); 87 88 #ifdef _KERNEL_OPT 89 #include "opt_net_mpsafe.h" 90 #endif 91 92 #include <sys/param.h> 93 #include <sys/systm.h> 94 #include <sys/callout.h> 95 #include <sys/mbuf.h> 96 #include <sys/malloc.h> 97 #include <sys/kmem.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 #include <sys/ioctl.h> 101 #include <sys/errno.h> 102 #include <sys/device.h> 103 #include <sys/queue.h> 104 #include <sys/syslog.h> 105 #include <sys/interrupt.h> 106 107 #include <sys/rndsource.h> 108 109 #include <net/if.h> 110 #include <net/if_dl.h> 111 #include <net/if_media.h> 112 #include <net/if_ether.h> 113 114 #include <net/bpf.h> 115 116 #include <netinet/in.h> /* XXX for struct ip */ 117 #include <netinet/in_systm.h> /* XXX for struct ip */ 118 #include <netinet/ip.h> /* XXX for struct ip */ 119 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */ 120 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 121 122 #include <sys/bus.h> 123 #include <sys/intr.h> 124 #include <machine/endian.h> 125 126 #include <dev/mii/mii.h> 127 #include <dev/mii/miivar.h> 128 #include <dev/mii/miidevs.h> 129 #include <dev/mii/mii_bitbang.h> 130 #include <dev/mii/ikphyreg.h> 131 #include <dev/mii/igphyreg.h> 132 #include <dev/mii/igphyvar.h> 133 #include <dev/mii/inbmphyreg.h> 134 135 #include <dev/pci/pcireg.h> 136 #include <dev/pci/pcivar.h> 137 #include <dev/pci/pcidevs.h> 138 139 #include <dev/pci/if_wmreg.h> 140 #include <dev/pci/if_wmvar.h> 141 142 #ifdef WM_DEBUG 143 #define WM_DEBUG_LINK 0x01 144 #define WM_DEBUG_TX 0x02 145 #define WM_DEBUG_RX 0x04 146 #define WM_DEBUG_GMII 0x08 147 #define WM_DEBUG_MANAGE 0x10 148 #define WM_DEBUG_NVM 0x20 149 #define WM_DEBUG_INIT 0x40 150 int wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII 151 | WM_DEBUG_MANAGE | WM_DEBUG_NVM | WM_DEBUG_INIT; 152 153 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 154 #else 155 #define DPRINTF(x, y) /* nothing */ 156 #endif /* WM_DEBUG */ 157 158 #ifdef NET_MPSAFE 159 #define WM_MPSAFE 1 160 #endif 161 162 /* 163 * This device driver's max interrupt numbers. 164 */ 165 #define WM_MAX_NTXINTR 16 166 #define WM_MAX_NRXINTR 16 167 #define WM_MAX_NINTR (WM_MAX_NTXINTR + WM_MAX_NRXINTR + 1) 168 169 /* 170 * Transmit descriptor list size. Due to errata, we can only have 171 * 256 hardware descriptors in the ring on < 82544, but we use 4096 172 * on >= 82544. We tell the upper layers that they can queue a lot 173 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 174 * of them at a time. 175 * 176 * We allow up to 256 (!) DMA segments per packet. Pathological packet 177 * chains containing many small mbufs have been observed in zero-copy 178 * situations with jumbo frames. 179 */ 180 #define WM_NTXSEGS 256 181 #define WM_IFQUEUELEN 256 182 #define WM_TXQUEUELEN_MAX 64 183 #define WM_TXQUEUELEN_MAX_82547 16 184 #define WM_TXQUEUELEN(txq) ((txq)->txq_num) 185 #define WM_TXQUEUELEN_MASK(txq) (WM_TXQUEUELEN(txq) - 1) 186 #define WM_TXQUEUE_GC(txq) (WM_TXQUEUELEN(txq) / 8) 187 #define WM_NTXDESC_82542 256 188 #define WM_NTXDESC_82544 4096 189 #define WM_NTXDESC(txq) ((txq)->txq_ndesc) 190 #define WM_NTXDESC_MASK(txq) (WM_NTXDESC(txq) - 1) 191 #define WM_TXDESCSIZE(txq) (WM_NTXDESC(txq) * sizeof(wiseman_txdesc_t)) 192 #define WM_NEXTTX(txq, x) (((x) + 1) & WM_NTXDESC_MASK(txq)) 193 #define WM_NEXTTXS(txq, x) (((x) + 1) & WM_TXQUEUELEN_MASK(txq)) 194 195 #define WM_MAXTXDMA (2 * round_page(IP_MAXPACKET)) /* for TSO */ 196 197 /* 198 * Receive descriptor list size. We have one Rx buffer for normal 199 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 200 * packet. We allocate 256 receive descriptors, each with a 2k 201 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 202 */ 203 #define WM_NRXDESC 256 204 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 205 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 206 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 207 208 typedef union txdescs { 209 wiseman_txdesc_t sctxu_txdescs[WM_NTXDESC_82544]; 210 nq_txdesc_t sctxu_nq_txdescs[WM_NTXDESC_82544]; 211 } txdescs_t; 212 213 #define WM_CDTXOFF(x) (sizeof(wiseman_txdesc_t) * x) 214 #define WM_CDRXOFF(x) (sizeof(wiseman_rxdesc_t) * x) 215 216 /* 217 * Software state for transmit jobs. 218 */ 219 struct wm_txsoft { 220 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 221 bus_dmamap_t txs_dmamap; /* our DMA map */ 222 int txs_firstdesc; /* first descriptor in packet */ 223 int txs_lastdesc; /* last descriptor in packet */ 224 int txs_ndesc; /* # of descriptors used */ 225 }; 226 227 /* 228 * Software state for receive buffers. Each descriptor gets a 229 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 230 * more than one buffer, we chain them together. 231 */ 232 struct wm_rxsoft { 233 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 234 bus_dmamap_t rxs_dmamap; /* our DMA map */ 235 }; 236 237 #define WM_LINKUP_TIMEOUT 50 238 239 static uint16_t swfwphysem[] = { 240 SWFW_PHY0_SM, 241 SWFW_PHY1_SM, 242 SWFW_PHY2_SM, 243 SWFW_PHY3_SM 244 }; 245 246 static const uint32_t wm_82580_rxpbs_table[] = { 247 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 248 }; 249 250 struct wm_softc; 251 252 struct wm_txqueue { 253 kmutex_t *txq_lock; /* lock for tx operations */ 254 255 struct wm_softc *txq_sc; 256 257 int txq_id; /* index of transmit queues */ 258 int txq_intr_idx; /* index of MSI-X tables */ 259 260 /* Software state for the transmit descriptors. */ 261 int txq_num; /* must be a power of two */ 262 struct wm_txsoft txq_soft[WM_TXQUEUELEN_MAX]; 263 264 /* TX control data structures. */ 265 int txq_ndesc; /* must be a power of two */ 266 txdescs_t *txq_descs_u; 267 bus_dmamap_t txq_desc_dmamap; /* control data DMA map */ 268 bus_dma_segment_t txq_desc_seg; /* control data segment */ 269 int txq_desc_rseg; /* real number of control segment */ 270 size_t txq_desc_size; /* control data size */ 271 #define txq_desc_dma txq_desc_dmamap->dm_segs[0].ds_addr 272 #define txq_descs txq_descs_u->sctxu_txdescs 273 #define txq_nq_descs txq_descs_u->sctxu_nq_txdescs 274 275 bus_addr_t txq_tdt_reg; /* offset of TDT register */ 276 277 int txq_free; /* number of free Tx descriptors */ 278 int txq_next; /* next ready Tx descriptor */ 279 280 int txq_sfree; /* number of free Tx jobs */ 281 int txq_snext; /* next free Tx job */ 282 int txq_sdirty; /* dirty Tx jobs */ 283 284 /* These 4 variables are used only on the 82547. */ 285 int txq_fifo_size; /* Tx FIFO size */ 286 int txq_fifo_head; /* current head of FIFO */ 287 uint32_t txq_fifo_addr; /* internal address of start of FIFO */ 288 int txq_fifo_stall; /* Tx FIFO is stalled */ 289 290 /* XXX which event counter is required? */ 291 }; 292 293 struct wm_rxqueue { 294 kmutex_t *rxq_lock; /* lock for rx operations */ 295 296 struct wm_softc *rxq_sc; 297 298 int rxq_id; /* index of receive queues */ 299 int rxq_intr_idx; /* index of MSI-X tables */ 300 301 /* Software state for the receive descriptors. */ 302 wiseman_rxdesc_t *rxq_descs; 303 304 /* RX control data structures. */ 305 struct wm_rxsoft rxq_soft[WM_NRXDESC]; 306 bus_dmamap_t rxq_desc_dmamap; /* control data DMA map */ 307 bus_dma_segment_t rxq_desc_seg; /* control data segment */ 308 int rxq_desc_rseg; /* real number of control segment */ 309 size_t rxq_desc_size; /* control data size */ 310 #define rxq_desc_dma rxq_desc_dmamap->dm_segs[0].ds_addr 311 312 bus_addr_t rxq_rdt_reg; /* offset of RDT register */ 313 314 int rxq_ptr; /* next ready Rx desc/queue ent */ 315 int rxq_discard; 316 int rxq_len; 317 struct mbuf *rxq_head; 318 struct mbuf *rxq_tail; 319 struct mbuf **rxq_tailp; 320 321 /* XXX which event counter is required? */ 322 }; 323 324 /* 325 * Software state per device. 326 */ 327 struct wm_softc { 328 device_t sc_dev; /* generic device information */ 329 bus_space_tag_t sc_st; /* bus space tag */ 330 bus_space_handle_t sc_sh; /* bus space handle */ 331 bus_size_t sc_ss; /* bus space size */ 332 bus_space_tag_t sc_iot; /* I/O space tag */ 333 bus_space_handle_t sc_ioh; /* I/O space handle */ 334 bus_size_t sc_ios; /* I/O space size */ 335 bus_space_tag_t sc_flasht; /* flash registers space tag */ 336 bus_space_handle_t sc_flashh; /* flash registers space handle */ 337 bus_size_t sc_flashs; /* flash registers space size */ 338 off_t sc_flashreg_offset; /* 339 * offset to flash registers from 340 * start of BAR 341 */ 342 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 343 344 struct ethercom sc_ethercom; /* ethernet common data */ 345 struct mii_data sc_mii; /* MII/media information */ 346 347 pci_chipset_tag_t sc_pc; 348 pcitag_t sc_pcitag; 349 int sc_bus_speed; /* PCI/PCIX bus speed */ 350 int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */ 351 352 uint16_t sc_pcidevid; /* PCI device ID */ 353 wm_chip_type sc_type; /* MAC type */ 354 int sc_rev; /* MAC revision */ 355 wm_phy_type sc_phytype; /* PHY type */ 356 uint32_t sc_mediatype; /* Media type (Copper, Fiber, SERDES)*/ 357 #define WM_MEDIATYPE_UNKNOWN 0x00 358 #define WM_MEDIATYPE_FIBER 0x01 359 #define WM_MEDIATYPE_COPPER 0x02 360 #define WM_MEDIATYPE_SERDES 0x03 /* Internal SERDES */ 361 int sc_funcid; /* unit number of the chip (0 to 3) */ 362 int sc_flags; /* flags; see below */ 363 int sc_if_flags; /* last if_flags */ 364 int sc_flowflags; /* 802.3x flow control flags */ 365 int sc_align_tweak; 366 367 void *sc_ihs[WM_MAX_NINTR]; /* 368 * interrupt cookie. 369 * legacy and msi use sc_ihs[0]. 370 */ 371 pci_intr_handle_t *sc_intrs; /* legacy and msi use sc_intrs[0] */ 372 int sc_nintrs; /* number of interrupts */ 373 374 int sc_link_intr_idx; /* index of MSI-X tables */ 375 376 callout_t sc_tick_ch; /* tick callout */ 377 bool sc_stopping; 378 379 int sc_nvm_ver_major; 380 int sc_nvm_ver_minor; 381 int sc_nvm_ver_build; 382 int sc_nvm_addrbits; /* NVM address bits */ 383 unsigned int sc_nvm_wordsize; /* NVM word size */ 384 int sc_ich8_flash_base; 385 int sc_ich8_flash_bank_size; 386 int sc_nvm_k1_enabled; 387 388 int sc_ntxqueues; 389 struct wm_txqueue *sc_txq; 390 391 int sc_nrxqueues; 392 struct wm_rxqueue *sc_rxq; 393 394 #ifdef WM_EVENT_COUNTERS 395 /* Event counters. */ 396 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 397 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 398 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 399 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 400 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 401 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 402 struct evcnt sc_ev_linkintr; /* Link interrupts */ 403 404 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 405 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 406 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 407 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 408 struct evcnt sc_ev_txtusum6; /* TCP/UDP v6 cksums comp. out-bound */ 409 struct evcnt sc_ev_txtso; /* TCP seg offload out-bound (IPv4) */ 410 struct evcnt sc_ev_txtso6; /* TCP seg offload out-bound (IPv6) */ 411 struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */ 412 413 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 414 struct evcnt sc_ev_txdrop; /* Tx packets dropped(too many segs) */ 415 416 struct evcnt sc_ev_tu; /* Tx underrun */ 417 418 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 419 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 420 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 421 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 422 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 423 #endif /* WM_EVENT_COUNTERS */ 424 425 /* This variable are used only on the 82547. */ 426 callout_t sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 427 428 uint32_t sc_ctrl; /* prototype CTRL register */ 429 #if 0 430 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 431 #endif 432 uint32_t sc_icr; /* prototype interrupt bits */ 433 uint32_t sc_itr; /* prototype intr throttling reg */ 434 uint32_t sc_tctl; /* prototype TCTL register */ 435 uint32_t sc_rctl; /* prototype RCTL register */ 436 uint32_t sc_txcw; /* prototype TXCW register */ 437 uint32_t sc_tipg; /* prototype TIPG register */ 438 uint32_t sc_fcrtl; /* prototype FCRTL register */ 439 uint32_t sc_pba; /* prototype PBA register */ 440 441 int sc_tbi_linkup; /* TBI link status */ 442 int sc_tbi_serdes_anegticks; /* autonegotiation ticks */ 443 int sc_tbi_serdes_ticks; /* tbi ticks */ 444 445 int sc_mchash_type; /* multicast filter offset */ 446 447 krndsource_t rnd_source; /* random source */ 448 449 kmutex_t *sc_core_lock; /* lock for softc operations */ 450 451 struct if_percpuq *sc_ipq; /* softint-based input queues */ 452 }; 453 454 #define WM_TX_LOCK(_txq) if ((_txq)->txq_lock) mutex_enter((_txq)->txq_lock) 455 #define WM_TX_UNLOCK(_txq) if ((_txq)->txq_lock) mutex_exit((_txq)->txq_lock) 456 #define WM_TX_LOCKED(_txq) (!(_txq)->txq_lock || mutex_owned((_txq)->txq_lock)) 457 #define WM_RX_LOCK(_rxq) if ((_rxq)->rxq_lock) mutex_enter((_rxq)->rxq_lock) 458 #define WM_RX_UNLOCK(_rxq) if ((_rxq)->rxq_lock) mutex_exit((_rxq)->rxq_lock) 459 #define WM_RX_LOCKED(_rxq) (!(_rxq)->rxq_lock || mutex_owned((_rxq)->rxq_lock)) 460 #define WM_CORE_LOCK(_sc) if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock) 461 #define WM_CORE_UNLOCK(_sc) if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock) 462 #define WM_CORE_LOCKED(_sc) (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock)) 463 464 #ifdef WM_MPSAFE 465 #define CALLOUT_FLAGS CALLOUT_MPSAFE 466 #else 467 #define CALLOUT_FLAGS 0 468 #endif 469 470 #define WM_RXCHAIN_RESET(rxq) \ 471 do { \ 472 (rxq)->rxq_tailp = &(rxq)->rxq_head; \ 473 *(rxq)->rxq_tailp = NULL; \ 474 (rxq)->rxq_len = 0; \ 475 } while (/*CONSTCOND*/0) 476 477 #define WM_RXCHAIN_LINK(rxq, m) \ 478 do { \ 479 *(rxq)->rxq_tailp = (rxq)->rxq_tail = (m); \ 480 (rxq)->rxq_tailp = &(m)->m_next; \ 481 } while (/*CONSTCOND*/0) 482 483 #ifdef WM_EVENT_COUNTERS 484 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 485 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 486 #else 487 #define WM_EVCNT_INCR(ev) /* nothing */ 488 #define WM_EVCNT_ADD(ev, val) /* nothing */ 489 #endif 490 491 #define CSR_READ(sc, reg) \ 492 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 493 #define CSR_WRITE(sc, reg, val) \ 494 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 495 #define CSR_WRITE_FLUSH(sc) \ 496 (void) CSR_READ((sc), WMREG_STATUS) 497 498 #define ICH8_FLASH_READ32(sc, reg) \ 499 bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, \ 500 (reg) + sc->sc_flashreg_offset) 501 #define ICH8_FLASH_WRITE32(sc, reg, data) \ 502 bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, \ 503 (reg) + sc->sc_flashreg_offset, (data)) 504 505 #define ICH8_FLASH_READ16(sc, reg) \ 506 bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, \ 507 (reg) + sc->sc_flashreg_offset) 508 #define ICH8_FLASH_WRITE16(sc, reg, data) \ 509 bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, \ 510 (reg) + sc->sc_flashreg_offset, (data)) 511 512 #define WM_CDTXADDR(txq, x) ((txq)->txq_desc_dma + WM_CDTXOFF((x))) 513 #define WM_CDRXADDR(rxq, x) ((rxq)->rxq_desc_dma + WM_CDRXOFF((x))) 514 515 #define WM_CDTXADDR_LO(txq, x) (WM_CDTXADDR((txq), (x)) & 0xffffffffU) 516 #define WM_CDTXADDR_HI(txq, x) \ 517 (sizeof(bus_addr_t) == 8 ? \ 518 (uint64_t)WM_CDTXADDR((txq), (x)) >> 32 : 0) 519 520 #define WM_CDRXADDR_LO(rxq, x) (WM_CDRXADDR((rxq), (x)) & 0xffffffffU) 521 #define WM_CDRXADDR_HI(rxq, x) \ 522 (sizeof(bus_addr_t) == 8 ? \ 523 (uint64_t)WM_CDRXADDR((rxq), (x)) >> 32 : 0) 524 525 /* 526 * Register read/write functions. 527 * Other than CSR_{READ|WRITE}(). 528 */ 529 #if 0 530 static inline uint32_t wm_io_read(struct wm_softc *, int); 531 #endif 532 static inline void wm_io_write(struct wm_softc *, int, uint32_t); 533 static inline void wm_82575_write_8bit_ctlr_reg(struct wm_softc *, uint32_t, 534 uint32_t, uint32_t); 535 static inline void wm_set_dma_addr(volatile wiseman_addr_t *, bus_addr_t); 536 537 /* 538 * Descriptor sync/init functions. 539 */ 540 static inline void wm_cdtxsync(struct wm_txqueue *, int, int, int); 541 static inline void wm_cdrxsync(struct wm_rxqueue *, int, int); 542 static inline void wm_init_rxdesc(struct wm_rxqueue *, int); 543 544 /* 545 * Device driver interface functions and commonly used functions. 546 * match, attach, detach, init, start, stop, ioctl, watchdog and so on. 547 */ 548 static const struct wm_product *wm_lookup(const struct pci_attach_args *); 549 static int wm_match(device_t, cfdata_t, void *); 550 static void wm_attach(device_t, device_t, void *); 551 static int wm_detach(device_t, int); 552 static bool wm_suspend(device_t, const pmf_qual_t *); 553 static bool wm_resume(device_t, const pmf_qual_t *); 554 static void wm_watchdog(struct ifnet *); 555 static void wm_tick(void *); 556 static int wm_ifflags_cb(struct ethercom *); 557 static int wm_ioctl(struct ifnet *, u_long, void *); 558 /* MAC address related */ 559 static uint16_t wm_check_alt_mac_addr(struct wm_softc *); 560 static int wm_read_mac_addr(struct wm_softc *, uint8_t *); 561 static void wm_set_ral(struct wm_softc *, const uint8_t *, int); 562 static uint32_t wm_mchash(struct wm_softc *, const uint8_t *); 563 static void wm_set_filter(struct wm_softc *); 564 /* Reset and init related */ 565 static void wm_set_vlan(struct wm_softc *); 566 static void wm_set_pcie_completion_timeout(struct wm_softc *); 567 static void wm_get_auto_rd_done(struct wm_softc *); 568 static void wm_lan_init_done(struct wm_softc *); 569 static void wm_get_cfg_done(struct wm_softc *); 570 static void wm_initialize_hardware_bits(struct wm_softc *); 571 static uint32_t wm_rxpbs_adjust_82580(uint32_t); 572 static void wm_reset(struct wm_softc *); 573 static int wm_add_rxbuf(struct wm_rxqueue *, int); 574 static void wm_rxdrain(struct wm_rxqueue *); 575 static void wm_rss_getkey(uint8_t *); 576 static void wm_init_rss(struct wm_softc *); 577 static void wm_adjust_qnum(struct wm_softc *, int); 578 static int wm_setup_legacy(struct wm_softc *); 579 static int wm_setup_msix(struct wm_softc *); 580 static int wm_init(struct ifnet *); 581 static int wm_init_locked(struct ifnet *); 582 static void wm_stop(struct ifnet *, int); 583 static void wm_stop_locked(struct ifnet *, int); 584 static void wm_dump_mbuf_chain(struct wm_softc *, struct mbuf *); 585 static void wm_82547_txfifo_stall(void *); 586 static int wm_82547_txfifo_bugchk(struct wm_softc *, struct mbuf *); 587 /* DMA related */ 588 static int wm_alloc_tx_descs(struct wm_softc *, struct wm_txqueue *); 589 static void wm_free_tx_descs(struct wm_softc *, struct wm_txqueue *); 590 static void wm_init_tx_descs(struct wm_softc *, struct wm_txqueue *); 591 static void wm_init_tx_regs(struct wm_softc *, struct wm_txqueue *); 592 static int wm_alloc_rx_descs(struct wm_softc *, struct wm_rxqueue *); 593 static void wm_free_rx_descs(struct wm_softc *, struct wm_rxqueue *); 594 static void wm_init_rx_regs(struct wm_softc *, struct wm_rxqueue *); 595 static int wm_alloc_tx_buffer(struct wm_softc *, struct wm_txqueue *); 596 static void wm_free_tx_buffer(struct wm_softc *, struct wm_txqueue *); 597 static void wm_init_tx_buffer(struct wm_softc *, struct wm_txqueue *); 598 static int wm_alloc_rx_buffer(struct wm_softc *, struct wm_rxqueue *); 599 static void wm_free_rx_buffer(struct wm_softc *, struct wm_rxqueue *); 600 static int wm_init_rx_buffer(struct wm_softc *, struct wm_rxqueue *); 601 static void wm_init_tx_queue(struct wm_softc *, struct wm_txqueue *); 602 static int wm_init_rx_queue(struct wm_softc *, struct wm_rxqueue *); 603 static int wm_alloc_txrx_queues(struct wm_softc *); 604 static void wm_free_txrx_queues(struct wm_softc *); 605 static int wm_init_txrx_queues(struct wm_softc *); 606 /* Start */ 607 static int wm_tx_offload(struct wm_softc *, struct wm_txsoft *, 608 uint32_t *, uint8_t *); 609 static void wm_start(struct ifnet *); 610 static void wm_start_locked(struct ifnet *); 611 static int wm_nq_tx_offload(struct wm_softc *, struct wm_txsoft *, 612 uint32_t *, uint32_t *, bool *); 613 static void wm_nq_start(struct ifnet *); 614 static void wm_nq_start_locked(struct ifnet *); 615 /* Interrupt */ 616 static int wm_txeof(struct wm_softc *); 617 static void wm_rxeof(struct wm_rxqueue *); 618 static void wm_linkintr_gmii(struct wm_softc *, uint32_t); 619 static void wm_linkintr_tbi(struct wm_softc *, uint32_t); 620 static void wm_linkintr_serdes(struct wm_softc *, uint32_t); 621 static void wm_linkintr(struct wm_softc *, uint32_t); 622 static int wm_intr_legacy(void *); 623 static int wm_txintr_msix(void *); 624 static int wm_rxintr_msix(void *); 625 static int wm_linkintr_msix(void *); 626 627 /* 628 * Media related. 629 * GMII, SGMII, TBI, SERDES and SFP. 630 */ 631 /* Common */ 632 static void wm_tbi_serdes_set_linkled(struct wm_softc *); 633 /* GMII related */ 634 static void wm_gmii_reset(struct wm_softc *); 635 static int wm_get_phy_id_82575(struct wm_softc *); 636 static void wm_gmii_mediainit(struct wm_softc *, pci_product_id_t); 637 static int wm_gmii_mediachange(struct ifnet *); 638 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 639 static void wm_i82543_mii_sendbits(struct wm_softc *, uint32_t, int); 640 static uint32_t wm_i82543_mii_recvbits(struct wm_softc *); 641 static int wm_gmii_i82543_readreg(device_t, int, int); 642 static void wm_gmii_i82543_writereg(device_t, int, int, int); 643 static int wm_gmii_i82544_readreg(device_t, int, int); 644 static void wm_gmii_i82544_writereg(device_t, int, int, int); 645 static int wm_gmii_i80003_readreg(device_t, int, int); 646 static void wm_gmii_i80003_writereg(device_t, int, int, int); 647 static int wm_gmii_bm_readreg(device_t, int, int); 648 static void wm_gmii_bm_writereg(device_t, int, int, int); 649 static void wm_access_phy_wakeup_reg_bm(device_t, int, int16_t *, int); 650 static int wm_gmii_hv_readreg(device_t, int, int); 651 static void wm_gmii_hv_writereg(device_t, int, int, int); 652 static int wm_gmii_82580_readreg(device_t, int, int); 653 static void wm_gmii_82580_writereg(device_t, int, int, int); 654 static int wm_gmii_gs40g_readreg(device_t, int, int); 655 static void wm_gmii_gs40g_writereg(device_t, int, int, int); 656 static void wm_gmii_statchg(struct ifnet *); 657 static int wm_kmrn_readreg(struct wm_softc *, int); 658 static void wm_kmrn_writereg(struct wm_softc *, int, int); 659 /* SGMII */ 660 static bool wm_sgmii_uses_mdio(struct wm_softc *); 661 static int wm_sgmii_readreg(device_t, int, int); 662 static void wm_sgmii_writereg(device_t, int, int, int); 663 /* TBI related */ 664 static void wm_tbi_mediainit(struct wm_softc *); 665 static int wm_tbi_mediachange(struct ifnet *); 666 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 667 static int wm_check_for_link(struct wm_softc *); 668 static void wm_tbi_tick(struct wm_softc *); 669 /* SERDES related */ 670 static void wm_serdes_power_up_link_82575(struct wm_softc *); 671 static int wm_serdes_mediachange(struct ifnet *); 672 static void wm_serdes_mediastatus(struct ifnet *, struct ifmediareq *); 673 static void wm_serdes_tick(struct wm_softc *); 674 /* SFP related */ 675 static int wm_sfp_read_data_byte(struct wm_softc *, uint16_t, uint8_t *); 676 static uint32_t wm_sfp_get_media_type(struct wm_softc *); 677 678 /* 679 * NVM related. 680 * Microwire, SPI (w/wo EERD) and Flash. 681 */ 682 /* Misc functions */ 683 static void wm_eeprom_sendbits(struct wm_softc *, uint32_t, int); 684 static void wm_eeprom_recvbits(struct wm_softc *, uint32_t *, int); 685 static int wm_nvm_set_addrbits_size_eecd(struct wm_softc *); 686 /* Microwire */ 687 static int wm_nvm_read_uwire(struct wm_softc *, int, int, uint16_t *); 688 /* SPI */ 689 static int wm_nvm_ready_spi(struct wm_softc *); 690 static int wm_nvm_read_spi(struct wm_softc *, int, int, uint16_t *); 691 /* Using with EERD */ 692 static int wm_poll_eerd_eewr_done(struct wm_softc *, int); 693 static int wm_nvm_read_eerd(struct wm_softc *, int, int, uint16_t *); 694 /* Flash */ 695 static int wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *, 696 unsigned int *); 697 static int32_t wm_ich8_cycle_init(struct wm_softc *); 698 static int32_t wm_ich8_flash_cycle(struct wm_softc *, uint32_t); 699 static int32_t wm_read_ich8_data(struct wm_softc *, uint32_t, uint32_t, 700 uint32_t *); 701 static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *); 702 static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *); 703 static int32_t wm_read_ich8_dword(struct wm_softc *, uint32_t, uint32_t *); 704 static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *); 705 static int wm_nvm_read_spt(struct wm_softc *, int, int, uint16_t *); 706 /* iNVM */ 707 static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *); 708 static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *); 709 /* Lock, detecting NVM type, validate checksum and read */ 710 static int wm_nvm_acquire(struct wm_softc *); 711 static void wm_nvm_release(struct wm_softc *); 712 static int wm_nvm_is_onboard_eeprom(struct wm_softc *); 713 static int wm_nvm_get_flash_presence_i210(struct wm_softc *); 714 static int wm_nvm_validate_checksum(struct wm_softc *); 715 static void wm_nvm_version_invm(struct wm_softc *); 716 static void wm_nvm_version(struct wm_softc *); 717 static int wm_nvm_read(struct wm_softc *, int, int, uint16_t *); 718 719 /* 720 * Hardware semaphores. 721 * Very complexed... 722 */ 723 static int wm_get_swsm_semaphore(struct wm_softc *); 724 static void wm_put_swsm_semaphore(struct wm_softc *); 725 static int wm_get_swfw_semaphore(struct wm_softc *, uint16_t); 726 static void wm_put_swfw_semaphore(struct wm_softc *, uint16_t); 727 static int wm_get_swfwhw_semaphore(struct wm_softc *); 728 static void wm_put_swfwhw_semaphore(struct wm_softc *); 729 static int wm_get_hw_semaphore_82573(struct wm_softc *); 730 static void wm_put_hw_semaphore_82573(struct wm_softc *); 731 732 /* 733 * Management mode and power management related subroutines. 734 * BMC, AMT, suspend/resume and EEE. 735 */ 736 #ifdef WM_WOL 737 static int wm_check_mng_mode(struct wm_softc *); 738 static int wm_check_mng_mode_ich8lan(struct wm_softc *); 739 static int wm_check_mng_mode_82574(struct wm_softc *); 740 static int wm_check_mng_mode_generic(struct wm_softc *); 741 #endif 742 static int wm_enable_mng_pass_thru(struct wm_softc *); 743 static bool wm_phy_resetisblocked(struct wm_softc *); 744 static void wm_get_hw_control(struct wm_softc *); 745 static void wm_release_hw_control(struct wm_softc *); 746 static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, bool); 747 static void wm_smbustopci(struct wm_softc *); 748 static void wm_init_manageability(struct wm_softc *); 749 static void wm_release_manageability(struct wm_softc *); 750 static void wm_get_wakeup(struct wm_softc *); 751 #ifdef WM_WOL 752 static void wm_enable_phy_wakeup(struct wm_softc *); 753 static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *); 754 static void wm_enable_wakeup(struct wm_softc *); 755 #endif 756 /* LPLU (Low Power Link Up) */ 757 static void wm_lplu_d0_disable(struct wm_softc *); 758 static void wm_lplu_d0_disable_pch(struct wm_softc *); 759 /* EEE */ 760 static void wm_set_eee_i350(struct wm_softc *); 761 762 /* 763 * Workarounds (mainly PHY related). 764 * Basically, PHY's workarounds are in the PHY drivers. 765 */ 766 static void wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *); 767 static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *); 768 static void wm_hv_phy_workaround_ich8lan(struct wm_softc *); 769 static void wm_lv_phy_workaround_ich8lan(struct wm_softc *); 770 static void wm_k1_gig_workaround_hv(struct wm_softc *, int); 771 static void wm_set_mdio_slow_mode_hv(struct wm_softc *); 772 static void wm_configure_k1_ich8lan(struct wm_softc *, int); 773 static void wm_reset_init_script_82575(struct wm_softc *); 774 static void wm_reset_mdicnfg_82580(struct wm_softc *); 775 static void wm_pll_workaround_i210(struct wm_softc *); 776 777 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc), 778 wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 779 780 /* 781 * Devices supported by this driver. 782 */ 783 static const struct wm_product { 784 pci_vendor_id_t wmp_vendor; 785 pci_product_id_t wmp_product; 786 const char *wmp_name; 787 wm_chip_type wmp_type; 788 uint32_t wmp_flags; 789 #define WMP_F_UNKNOWN WM_MEDIATYPE_UNKNOWN 790 #define WMP_F_FIBER WM_MEDIATYPE_FIBER 791 #define WMP_F_COPPER WM_MEDIATYPE_COPPER 792 #define WMP_F_SERDES WM_MEDIATYPE_SERDES 793 #define WMP_MEDIATYPE(x) ((x) & 0x03) 794 } wm_products[] = { 795 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 796 "Intel i82542 1000BASE-X Ethernet", 797 WM_T_82542_2_1, WMP_F_FIBER }, 798 799 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 800 "Intel i82543GC 1000BASE-X Ethernet", 801 WM_T_82543, WMP_F_FIBER }, 802 803 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 804 "Intel i82543GC 1000BASE-T Ethernet", 805 WM_T_82543, WMP_F_COPPER }, 806 807 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 808 "Intel i82544EI 1000BASE-T Ethernet", 809 WM_T_82544, WMP_F_COPPER }, 810 811 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 812 "Intel i82544EI 1000BASE-X Ethernet", 813 WM_T_82544, WMP_F_FIBER }, 814 815 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 816 "Intel i82544GC 1000BASE-T Ethernet", 817 WM_T_82544, WMP_F_COPPER }, 818 819 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 820 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 821 WM_T_82544, WMP_F_COPPER }, 822 823 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 824 "Intel i82540EM 1000BASE-T Ethernet", 825 WM_T_82540, WMP_F_COPPER }, 826 827 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 828 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 829 WM_T_82540, WMP_F_COPPER }, 830 831 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 832 "Intel i82540EP 1000BASE-T Ethernet", 833 WM_T_82540, WMP_F_COPPER }, 834 835 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 836 "Intel i82540EP 1000BASE-T Ethernet", 837 WM_T_82540, WMP_F_COPPER }, 838 839 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 840 "Intel i82540EP 1000BASE-T Ethernet", 841 WM_T_82540, WMP_F_COPPER }, 842 843 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 844 "Intel i82545EM 1000BASE-T Ethernet", 845 WM_T_82545, WMP_F_COPPER }, 846 847 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 848 "Intel i82545GM 1000BASE-T Ethernet", 849 WM_T_82545_3, WMP_F_COPPER }, 850 851 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 852 "Intel i82545GM 1000BASE-X Ethernet", 853 WM_T_82545_3, WMP_F_FIBER }, 854 855 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 856 "Intel i82545GM Gigabit Ethernet (SERDES)", 857 WM_T_82545_3, WMP_F_SERDES }, 858 859 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 860 "Intel i82546EB 1000BASE-T Ethernet", 861 WM_T_82546, WMP_F_COPPER }, 862 863 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 864 "Intel i82546EB 1000BASE-T Ethernet", 865 WM_T_82546, WMP_F_COPPER }, 866 867 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 868 "Intel i82545EM 1000BASE-X Ethernet", 869 WM_T_82545, WMP_F_FIBER }, 870 871 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 872 "Intel i82546EB 1000BASE-X Ethernet", 873 WM_T_82546, WMP_F_FIBER }, 874 875 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 876 "Intel i82546GB 1000BASE-T Ethernet", 877 WM_T_82546_3, WMP_F_COPPER }, 878 879 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 880 "Intel i82546GB 1000BASE-X Ethernet", 881 WM_T_82546_3, WMP_F_FIBER }, 882 883 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 884 "Intel i82546GB Gigabit Ethernet (SERDES)", 885 WM_T_82546_3, WMP_F_SERDES }, 886 887 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER, 888 "i82546GB quad-port Gigabit Ethernet", 889 WM_T_82546_3, WMP_F_COPPER }, 890 891 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3, 892 "i82546GB quad-port Gigabit Ethernet (KSP3)", 893 WM_T_82546_3, WMP_F_COPPER }, 894 895 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE, 896 "Intel PRO/1000MT (82546GB)", 897 WM_T_82546_3, WMP_F_COPPER }, 898 899 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 900 "Intel i82541EI 1000BASE-T Ethernet", 901 WM_T_82541, WMP_F_COPPER }, 902 903 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM, 904 "Intel i82541ER (LOM) 1000BASE-T Ethernet", 905 WM_T_82541, WMP_F_COPPER }, 906 907 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 908 "Intel i82541EI Mobile 1000BASE-T Ethernet", 909 WM_T_82541, WMP_F_COPPER }, 910 911 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 912 "Intel i82541ER 1000BASE-T Ethernet", 913 WM_T_82541_2, WMP_F_COPPER }, 914 915 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 916 "Intel i82541GI 1000BASE-T Ethernet", 917 WM_T_82541_2, WMP_F_COPPER }, 918 919 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 920 "Intel i82541GI Mobile 1000BASE-T Ethernet", 921 WM_T_82541_2, WMP_F_COPPER }, 922 923 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541PI, 924 "Intel i82541PI 1000BASE-T Ethernet", 925 WM_T_82541_2, WMP_F_COPPER }, 926 927 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 928 "Intel i82547EI 1000BASE-T Ethernet", 929 WM_T_82547, WMP_F_COPPER }, 930 931 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE, 932 "Intel i82547EI Mobile 1000BASE-T Ethernet", 933 WM_T_82547, WMP_F_COPPER }, 934 935 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 936 "Intel i82547GI 1000BASE-T Ethernet", 937 WM_T_82547_2, WMP_F_COPPER }, 938 939 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER, 940 "Intel PRO/1000 PT (82571EB)", 941 WM_T_82571, WMP_F_COPPER }, 942 943 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER, 944 "Intel PRO/1000 PF (82571EB)", 945 WM_T_82571, WMP_F_FIBER }, 946 947 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES, 948 "Intel PRO/1000 PB (82571EB)", 949 WM_T_82571, WMP_F_SERDES }, 950 951 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER, 952 "Intel PRO/1000 QT (82571EB)", 953 WM_T_82571, WMP_F_COPPER }, 954 955 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER, 956 "Intel PRO/1000 PT Quad Port Server Adapter", 957 WM_T_82571, WMP_F_COPPER, }, 958 959 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_COPPER, 960 "Intel Gigabit PT Quad Port Server ExpressModule", 961 WM_T_82571, WMP_F_COPPER, }, 962 963 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_DUAL_SERDES, 964 "Intel 82571EB Dual Gigabit Ethernet (SERDES)", 965 WM_T_82571, WMP_F_SERDES, }, 966 967 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_SERDES, 968 "Intel 82571EB Quad Gigabit Ethernet (SERDES)", 969 WM_T_82571, WMP_F_SERDES, }, 970 971 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER, 972 "Intel 82571EB Quad 1000baseX Ethernet", 973 WM_T_82571, WMP_F_FIBER, }, 974 975 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER, 976 "Intel i82572EI 1000baseT Ethernet", 977 WM_T_82572, WMP_F_COPPER }, 978 979 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER, 980 "Intel i82572EI 1000baseX Ethernet", 981 WM_T_82572, WMP_F_FIBER }, 982 983 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES, 984 "Intel i82572EI Gigabit Ethernet (SERDES)", 985 WM_T_82572, WMP_F_SERDES }, 986 987 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI, 988 "Intel i82572EI 1000baseT Ethernet", 989 WM_T_82572, WMP_F_COPPER }, 990 991 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E, 992 "Intel i82573E", 993 WM_T_82573, WMP_F_COPPER }, 994 995 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT, 996 "Intel i82573E IAMT", 997 WM_T_82573, WMP_F_COPPER }, 998 999 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L, 1000 "Intel i82573L Gigabit Ethernet", 1001 WM_T_82573, WMP_F_COPPER }, 1002 1003 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L, 1004 "Intel i82574L", 1005 WM_T_82574, WMP_F_COPPER }, 1006 1007 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA, 1008 "Intel i82574L", 1009 WM_T_82574, WMP_F_COPPER }, 1010 1011 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V, 1012 "Intel i82583V", 1013 WM_T_82583, WMP_F_COPPER }, 1014 1015 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT, 1016 "i80003 dual 1000baseT Ethernet", 1017 WM_T_80003, WMP_F_COPPER }, 1018 1019 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT, 1020 "i80003 dual 1000baseX Ethernet", 1021 WM_T_80003, WMP_F_COPPER }, 1022 1023 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT, 1024 "Intel i80003ES2 dual Gigabit Ethernet (SERDES)", 1025 WM_T_80003, WMP_F_SERDES }, 1026 1027 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT, 1028 "Intel i80003 1000baseT Ethernet", 1029 WM_T_80003, WMP_F_COPPER }, 1030 1031 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT, 1032 "Intel i80003 Gigabit Ethernet (SERDES)", 1033 WM_T_80003, WMP_F_SERDES }, 1034 1035 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_AMT, 1036 "Intel i82801H (M_AMT) LAN Controller", 1037 WM_T_ICH8, WMP_F_COPPER }, 1038 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_AMT, 1039 "Intel i82801H (AMT) LAN Controller", 1040 WM_T_ICH8, WMP_F_COPPER }, 1041 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_LAN, 1042 "Intel i82801H LAN Controller", 1043 WM_T_ICH8, WMP_F_COPPER }, 1044 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_LAN, 1045 "Intel i82801H (IFE) LAN Controller", 1046 WM_T_ICH8, WMP_F_COPPER }, 1047 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_M_LAN, 1048 "Intel i82801H (M) LAN Controller", 1049 WM_T_ICH8, WMP_F_COPPER }, 1050 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_GT, 1051 "Intel i82801H IFE (GT) LAN Controller", 1052 WM_T_ICH8, WMP_F_COPPER }, 1053 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IFE_G, 1054 "Intel i82801H IFE (G) LAN Controller", 1055 WM_T_ICH8, WMP_F_COPPER }, 1056 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_AMT, 1057 "82801I (AMT) LAN Controller", 1058 WM_T_ICH9, WMP_F_COPPER }, 1059 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE, 1060 "82801I LAN Controller", 1061 WM_T_ICH9, WMP_F_COPPER }, 1062 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_G, 1063 "82801I (G) LAN Controller", 1064 WM_T_ICH9, WMP_F_COPPER }, 1065 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IFE_GT, 1066 "82801I (GT) LAN Controller", 1067 WM_T_ICH9, WMP_F_COPPER }, 1068 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_C, 1069 "82801I (C) LAN Controller", 1070 WM_T_ICH9, WMP_F_COPPER }, 1071 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M, 1072 "82801I mobile LAN Controller", 1073 WM_T_ICH9, WMP_F_COPPER }, 1074 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_IGP_M_V, 1075 "82801I mobile (V) LAN Controller", 1076 WM_T_ICH9, WMP_F_COPPER }, 1077 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_IGP_M_AMT, 1078 "82801I mobile (AMT) LAN Controller", 1079 WM_T_ICH9, WMP_F_COPPER }, 1080 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_BM, 1081 "82567LM-4 LAN Controller", 1082 WM_T_ICH9, WMP_F_COPPER }, 1083 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_82567V_3, 1084 "82567V-3 LAN Controller", 1085 WM_T_ICH9, WMP_F_COPPER }, 1086 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LM, 1087 "82567LM-2 LAN Controller", 1088 WM_T_ICH10, WMP_F_COPPER }, 1089 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_LF, 1090 "82567LF-2 LAN Controller", 1091 WM_T_ICH10, WMP_F_COPPER }, 1092 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LM, 1093 "82567LM-3 LAN Controller", 1094 WM_T_ICH10, WMP_F_COPPER }, 1095 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_LF, 1096 "82567LF-3 LAN Controller", 1097 WM_T_ICH10, WMP_F_COPPER }, 1098 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_R_BM_V, 1099 "82567V-2 LAN Controller", 1100 WM_T_ICH10, WMP_F_COPPER }, 1101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801J_D_BM_V, 1102 "82567V-3? LAN Controller", 1103 WM_T_ICH10, WMP_F_COPPER }, 1104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_HANKSVILLE, 1105 "HANKSVILLE LAN Controller", 1106 WM_T_ICH10, WMP_F_COPPER }, 1107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LM, 1108 "PCH LAN (82577LM) Controller", 1109 WM_T_PCH, WMP_F_COPPER }, 1110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_M_LC, 1111 "PCH LAN (82577LC) Controller", 1112 WM_T_PCH, WMP_F_COPPER }, 1113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DM, 1114 "PCH LAN (82578DM) Controller", 1115 WM_T_PCH, WMP_F_COPPER }, 1116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH_D_DC, 1117 "PCH LAN (82578DC) Controller", 1118 WM_T_PCH, WMP_F_COPPER }, 1119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_LM, 1120 "PCH2 LAN (82579LM) Controller", 1121 WM_T_PCH2, WMP_F_COPPER }, 1122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PCH2_LV_V, 1123 "PCH2 LAN (82579V) Controller", 1124 WM_T_PCH2, WMP_F_COPPER }, 1125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER, 1126 "82575EB dual-1000baseT Ethernet", 1127 WM_T_82575, WMP_F_COPPER }, 1128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES, 1129 "82575EB dual-1000baseX Ethernet (SERDES)", 1130 WM_T_82575, WMP_F_SERDES }, 1131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER, 1132 "82575GB quad-1000baseT Ethernet", 1133 WM_T_82575, WMP_F_COPPER }, 1134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM, 1135 "82575GB quad-1000baseT Ethernet (PM)", 1136 WM_T_82575, WMP_F_COPPER }, 1137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_COPPER, 1138 "82576 1000BaseT Ethernet", 1139 WM_T_82576, WMP_F_COPPER }, 1140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER, 1141 "82576 1000BaseX Ethernet", 1142 WM_T_82576, WMP_F_FIBER }, 1143 1144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES, 1145 "82576 gigabit Ethernet (SERDES)", 1146 WM_T_82576, WMP_F_SERDES }, 1147 1148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER, 1149 "82576 quad-1000BaseT Ethernet", 1150 WM_T_82576, WMP_F_COPPER }, 1151 1152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER_ET2, 1153 "82576 Gigabit ET2 Quad Port Server Adapter", 1154 WM_T_82576, WMP_F_COPPER }, 1155 1156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS, 1157 "82576 gigabit Ethernet", 1158 WM_T_82576, WMP_F_COPPER }, 1159 1160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES, 1161 "82576 gigabit Ethernet (SERDES)", 1162 WM_T_82576, WMP_F_SERDES }, 1163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD, 1164 "82576 quad-gigabit Ethernet (SERDES)", 1165 WM_T_82576, WMP_F_SERDES }, 1166 1167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER, 1168 "82580 1000BaseT Ethernet", 1169 WM_T_82580, WMP_F_COPPER }, 1170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER, 1171 "82580 1000BaseX Ethernet", 1172 WM_T_82580, WMP_F_FIBER }, 1173 1174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES, 1175 "82580 1000BaseT Ethernet (SERDES)", 1176 WM_T_82580, WMP_F_SERDES }, 1177 1178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII, 1179 "82580 gigabit Ethernet (SGMII)", 1180 WM_T_82580, WMP_F_COPPER }, 1181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL, 1182 "82580 dual-1000BaseT Ethernet", 1183 WM_T_82580, WMP_F_COPPER }, 1184 1185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER, 1186 "82580 quad-1000BaseX Ethernet", 1187 WM_T_82580, WMP_F_FIBER }, 1188 1189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII, 1190 "DH89XXCC Gigabit Ethernet (SGMII)", 1191 WM_T_82580, WMP_F_COPPER }, 1192 1193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES, 1194 "DH89XXCC Gigabit Ethernet (SERDES)", 1195 WM_T_82580, WMP_F_SERDES }, 1196 1197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE, 1198 "DH89XXCC 1000BASE-KX Ethernet", 1199 WM_T_82580, WMP_F_SERDES }, 1200 1201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP, 1202 "DH89XXCC Gigabit Ethernet (SFP)", 1203 WM_T_82580, WMP_F_SERDES }, 1204 1205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER, 1206 "I350 Gigabit Network Connection", 1207 WM_T_I350, WMP_F_COPPER }, 1208 1209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER, 1210 "I350 Gigabit Fiber Network Connection", 1211 WM_T_I350, WMP_F_FIBER }, 1212 1213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES, 1214 "I350 Gigabit Backplane Connection", 1215 WM_T_I350, WMP_F_SERDES }, 1216 1217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_DA4, 1218 "I350 Quad Port Gigabit Ethernet", 1219 WM_T_I350, WMP_F_SERDES }, 1220 1221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII, 1222 "I350 Gigabit Connection", 1223 WM_T_I350, WMP_F_COPPER }, 1224 1225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_1000KX, 1226 "I354 Gigabit Ethernet (KX)", 1227 WM_T_I354, WMP_F_SERDES }, 1228 1229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_SGMII, 1230 "I354 Gigabit Ethernet (SGMII)", 1231 WM_T_I354, WMP_F_COPPER }, 1232 1233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C2000_25GBE, 1234 "I354 Gigabit Ethernet (2.5G)", 1235 WM_T_I354, WMP_F_COPPER }, 1236 1237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_T1, 1238 "I210-T1 Ethernet Server Adapter", 1239 WM_T_I210, WMP_F_COPPER }, 1240 1241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_OEM1, 1242 "I210 Ethernet (Copper OEM)", 1243 WM_T_I210, WMP_F_COPPER }, 1244 1245 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_IT, 1246 "I210 Ethernet (Copper IT)", 1247 WM_T_I210, WMP_F_COPPER }, 1248 1249 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_WOF, 1250 "I210 Ethernet (FLASH less)", 1251 WM_T_I210, WMP_F_COPPER }, 1252 1253 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER, 1254 "I210 Gigabit Ethernet (Fiber)", 1255 WM_T_I210, WMP_F_FIBER }, 1256 1257 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES, 1258 "I210 Gigabit Ethernet (SERDES)", 1259 WM_T_I210, WMP_F_SERDES }, 1260 1261 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_WOF, 1262 "I210 Gigabit Ethernet (FLASH less)", 1263 WM_T_I210, WMP_F_SERDES }, 1264 1265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII, 1266 "I210 Gigabit Ethernet (SGMII)", 1267 WM_T_I210, WMP_F_COPPER }, 1268 1269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER, 1270 "I211 Ethernet (COPPER)", 1271 WM_T_I211, WMP_F_COPPER }, 1272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V, 1273 "I217 V Ethernet Connection", 1274 WM_T_PCH_LPT, WMP_F_COPPER }, 1275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM, 1276 "I217 LM Ethernet Connection", 1277 WM_T_PCH_LPT, WMP_F_COPPER }, 1278 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V, 1279 "I218 V Ethernet Connection", 1280 WM_T_PCH_LPT, WMP_F_COPPER }, 1281 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V2, 1282 "I218 V Ethernet Connection", 1283 WM_T_PCH_LPT, WMP_F_COPPER }, 1284 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V3, 1285 "I218 V Ethernet Connection", 1286 WM_T_PCH_LPT, WMP_F_COPPER }, 1287 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM, 1288 "I218 LM Ethernet Connection", 1289 WM_T_PCH_LPT, WMP_F_COPPER }, 1290 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM2, 1291 "I218 LM Ethernet Connection", 1292 WM_T_PCH_LPT, WMP_F_COPPER }, 1293 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM3, 1294 "I218 LM Ethernet Connection", 1295 WM_T_PCH_LPT, WMP_F_COPPER }, 1296 #if 0 1297 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V, 1298 "I219 V Ethernet Connection", 1299 WM_T_PCH_SPT, WMP_F_COPPER }, 1300 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_V2, 1301 "I219 V Ethernet Connection", 1302 WM_T_PCH_SPT, WMP_F_COPPER }, 1303 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM, 1304 "I219 LM Ethernet Connection", 1305 WM_T_PCH_SPT, WMP_F_COPPER }, 1306 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I219_LM2, 1307 "I219 LM Ethernet Connection", 1308 WM_T_PCH_SPT, WMP_F_COPPER }, 1309 #endif 1310 { 0, 0, 1311 NULL, 1312 0, 0 }, 1313 }; 1314 1315 #ifdef WM_EVENT_COUNTERS 1316 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 1317 #endif /* WM_EVENT_COUNTERS */ 1318 1319 1320 /* 1321 * Register read/write functions. 1322 * Other than CSR_{READ|WRITE}(). 1323 */ 1324 1325 #if 0 /* Not currently used */ 1326 static inline uint32_t 1327 wm_io_read(struct wm_softc *sc, int reg) 1328 { 1329 1330 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 1331 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 1332 } 1333 #endif 1334 1335 static inline void 1336 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 1337 { 1338 1339 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 1340 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 1341 } 1342 1343 static inline void 1344 wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off, 1345 uint32_t data) 1346 { 1347 uint32_t regval; 1348 int i; 1349 1350 regval = (data & SCTL_CTL_DATA_MASK) | (off << SCTL_CTL_ADDR_SHIFT); 1351 1352 CSR_WRITE(sc, reg, regval); 1353 1354 for (i = 0; i < SCTL_CTL_POLL_TIMEOUT; i++) { 1355 delay(5); 1356 if (CSR_READ(sc, reg) & SCTL_CTL_READY) 1357 break; 1358 } 1359 if (i == SCTL_CTL_POLL_TIMEOUT) { 1360 aprint_error("%s: WARNING:" 1361 " i82575 reg 0x%08x setup did not indicate ready\n", 1362 device_xname(sc->sc_dev), reg); 1363 } 1364 } 1365 1366 static inline void 1367 wm_set_dma_addr(volatile wiseman_addr_t *wa, bus_addr_t v) 1368 { 1369 wa->wa_low = htole32(v & 0xffffffffU); 1370 if (sizeof(bus_addr_t) == 8) 1371 wa->wa_high = htole32((uint64_t) v >> 32); 1372 else 1373 wa->wa_high = 0; 1374 } 1375 1376 /* 1377 * Descriptor sync/init functions. 1378 */ 1379 static inline void 1380 wm_cdtxsync(struct wm_txqueue *txq, int start, int num, int ops) 1381 { 1382 struct wm_softc *sc = txq->txq_sc; 1383 1384 /* If it will wrap around, sync to the end of the ring. */ 1385 if ((start + num) > WM_NTXDESC(txq)) { 1386 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, 1387 WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * 1388 (WM_NTXDESC(txq) - start), ops); 1389 num -= (WM_NTXDESC(txq) - start); 1390 start = 0; 1391 } 1392 1393 /* Now sync whatever is left. */ 1394 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_dmamap, 1395 WM_CDTXOFF(start), sizeof(wiseman_txdesc_t) * num, ops); 1396 } 1397 1398 static inline void 1399 wm_cdrxsync(struct wm_rxqueue *rxq, int start, int ops) 1400 { 1401 struct wm_softc *sc = rxq->rxq_sc; 1402 1403 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_dmamap, 1404 WM_CDRXOFF(start), sizeof(wiseman_rxdesc_t), ops); 1405 } 1406 1407 static inline void 1408 wm_init_rxdesc(struct wm_rxqueue *rxq, int start) 1409 { 1410 struct wm_softc *sc = rxq->rxq_sc; 1411 struct wm_rxsoft *rxs = &rxq->rxq_soft[start]; 1412 wiseman_rxdesc_t *rxd = &rxq->rxq_descs[start]; 1413 struct mbuf *m = rxs->rxs_mbuf; 1414 1415 /* 1416 * Note: We scoot the packet forward 2 bytes in the buffer 1417 * so that the payload after the Ethernet header is aligned 1418 * to a 4-byte boundary. 1419 1420 * XXX BRAINDAMAGE ALERT! 1421 * The stupid chip uses the same size for every buffer, which 1422 * is set in the Receive Control register. We are using the 2K 1423 * size option, but what we REALLY want is (2K - 2)! For this 1424 * reason, we can't "scoot" packets longer than the standard 1425 * Ethernet MTU. On strict-alignment platforms, if the total 1426 * size exceeds (2K - 2) we set align_tweak to 0 and let 1427 * the upper layer copy the headers. 1428 */ 1429 m->m_data = m->m_ext.ext_buf + sc->sc_align_tweak; 1430 1431 wm_set_dma_addr(&rxd->wrx_addr, 1432 rxs->rxs_dmamap->dm_segs[0].ds_addr + sc->sc_align_tweak); 1433 rxd->wrx_len = 0; 1434 rxd->wrx_cksum = 0; 1435 rxd->wrx_status = 0; 1436 rxd->wrx_errors = 0; 1437 rxd->wrx_special = 0; 1438 wm_cdrxsync(rxq, start, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1439 1440 CSR_WRITE(sc, rxq->rxq_rdt_reg, start); 1441 } 1442 1443 /* 1444 * Device driver interface functions and commonly used functions. 1445 * match, attach, detach, init, start, stop, ioctl, watchdog and so on. 1446 */ 1447 1448 /* Lookup supported device table */ 1449 static const struct wm_product * 1450 wm_lookup(const struct pci_attach_args *pa) 1451 { 1452 const struct wm_product *wmp; 1453 1454 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 1455 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 1456 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 1457 return wmp; 1458 } 1459 return NULL; 1460 } 1461 1462 /* The match function (ca_match) */ 1463 static int 1464 wm_match(device_t parent, cfdata_t cf, void *aux) 1465 { 1466 struct pci_attach_args *pa = aux; 1467 1468 if (wm_lookup(pa) != NULL) 1469 return 1; 1470 1471 return 0; 1472 } 1473 1474 /* The attach function (ca_attach) */ 1475 static void 1476 wm_attach(device_t parent, device_t self, void *aux) 1477 { 1478 struct wm_softc *sc = device_private(self); 1479 struct pci_attach_args *pa = aux; 1480 prop_dictionary_t dict; 1481 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1482 pci_chipset_tag_t pc = pa->pa_pc; 1483 int counts[PCI_INTR_TYPE_SIZE]; 1484 pci_intr_type_t max_type; 1485 const char *eetype, *xname; 1486 bus_space_tag_t memt; 1487 bus_space_handle_t memh; 1488 bus_size_t memsize; 1489 int memh_valid; 1490 int i, error; 1491 const struct wm_product *wmp; 1492 prop_data_t ea; 1493 prop_number_t pn; 1494 uint8_t enaddr[ETHER_ADDR_LEN]; 1495 uint16_t cfg1, cfg2, swdpin, nvmword; 1496 pcireg_t preg, memtype; 1497 uint16_t eeprom_data, apme_mask; 1498 bool force_clear_smbi; 1499 uint32_t link_mode; 1500 uint32_t reg; 1501 1502 sc->sc_dev = self; 1503 callout_init(&sc->sc_tick_ch, CALLOUT_FLAGS); 1504 sc->sc_stopping = false; 1505 1506 wmp = wm_lookup(pa); 1507 #ifdef DIAGNOSTIC 1508 if (wmp == NULL) { 1509 printf("\n"); 1510 panic("wm_attach: impossible"); 1511 } 1512 #endif 1513 sc->sc_mediatype = WMP_MEDIATYPE(wmp->wmp_flags); 1514 1515 sc->sc_pc = pa->pa_pc; 1516 sc->sc_pcitag = pa->pa_tag; 1517 1518 if (pci_dma64_available(pa)) 1519 sc->sc_dmat = pa->pa_dmat64; 1520 else 1521 sc->sc_dmat = pa->pa_dmat; 1522 1523 sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id); 1524 sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag,PCI_CLASS_REG)); 1525 pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1); 1526 1527 sc->sc_type = wmp->wmp_type; 1528 if (sc->sc_type < WM_T_82543) { 1529 if (sc->sc_rev < 2) { 1530 aprint_error_dev(sc->sc_dev, 1531 "i82542 must be at least rev. 2\n"); 1532 return; 1533 } 1534 if (sc->sc_rev < 3) 1535 sc->sc_type = WM_T_82542_2_0; 1536 } 1537 1538 /* 1539 * Disable MSI for Errata: 1540 * "Message Signaled Interrupt Feature May Corrupt Write Transactions" 1541 * 1542 * 82544: Errata 25 1543 * 82540: Errata 6 (easy to reproduce device timeout) 1544 * 82545: Errata 4 (easy to reproduce device timeout) 1545 * 82546: Errata 26 (easy to reproduce device timeout) 1546 * 82541: Errata 7 (easy to reproduce device timeout) 1547 * 1548 * "Byte Enables 2 and 3 are not set on MSI writes" 1549 * 1550 * 82571 & 82572: Errata 63 1551 */ 1552 if ((sc->sc_type <= WM_T_82541_2) || (sc->sc_type == WM_T_82571) 1553 || (sc->sc_type == WM_T_82572)) 1554 pa->pa_flags &= ~PCI_FLAGS_MSI_OKAY; 1555 1556 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) 1557 || (sc->sc_type == WM_T_82580) 1558 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) 1559 || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) 1560 sc->sc_flags |= WM_F_NEWQUEUE; 1561 1562 /* Set device properties (mactype) */ 1563 dict = device_properties(sc->sc_dev); 1564 prop_dictionary_set_uint32(dict, "mactype", sc->sc_type); 1565 1566 /* 1567 * Map the device. All devices support memory-mapped acccess, 1568 * and it is really required for normal operation. 1569 */ 1570 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 1571 switch (memtype) { 1572 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1573 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1574 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 1575 memtype, 0, &memt, &memh, NULL, &memsize) == 0); 1576 break; 1577 default: 1578 memh_valid = 0; 1579 break; 1580 } 1581 1582 if (memh_valid) { 1583 sc->sc_st = memt; 1584 sc->sc_sh = memh; 1585 sc->sc_ss = memsize; 1586 } else { 1587 aprint_error_dev(sc->sc_dev, 1588 "unable to map device registers\n"); 1589 return; 1590 } 1591 1592 /* 1593 * In addition, i82544 and later support I/O mapped indirect 1594 * register access. It is not desirable (nor supported in 1595 * this driver) to use it for normal operation, though it is 1596 * required to work around bugs in some chip versions. 1597 */ 1598 if (sc->sc_type >= WM_T_82544) { 1599 /* First we have to find the I/O BAR. */ 1600 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 1601 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); 1602 if (memtype == PCI_MAPREG_TYPE_IO) 1603 break; 1604 if (PCI_MAPREG_MEM_TYPE(memtype) == 1605 PCI_MAPREG_MEM_TYPE_64BIT) 1606 i += 4; /* skip high bits, too */ 1607 } 1608 if (i < PCI_MAPREG_END) { 1609 /* 1610 * We found PCI_MAPREG_TYPE_IO. Note that 82580 1611 * (and newer?) chip has no PCI_MAPREG_TYPE_IO. 1612 * It's no problem because newer chips has no this 1613 * bug. 1614 * 1615 * The i8254x doesn't apparently respond when the 1616 * I/O BAR is 0, which looks somewhat like it's not 1617 * been configured. 1618 */ 1619 preg = pci_conf_read(pc, pa->pa_tag, i); 1620 if (PCI_MAPREG_MEM_ADDR(preg) == 0) { 1621 aprint_error_dev(sc->sc_dev, 1622 "WARNING: I/O BAR at zero.\n"); 1623 } else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 1624 0, &sc->sc_iot, &sc->sc_ioh, 1625 NULL, &sc->sc_ios) == 0) { 1626 sc->sc_flags |= WM_F_IOH_VALID; 1627 } else { 1628 aprint_error_dev(sc->sc_dev, 1629 "WARNING: unable to map I/O space\n"); 1630 } 1631 } 1632 1633 } 1634 1635 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 1636 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1637 preg |= PCI_COMMAND_MASTER_ENABLE; 1638 if (sc->sc_type < WM_T_82542_2_1) 1639 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 1640 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 1641 1642 /* power up chip */ 1643 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1644 NULL)) && error != EOPNOTSUPP) { 1645 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1646 return; 1647 } 1648 1649 wm_adjust_qnum(sc, pci_msix_count(pa->pa_pc, pa->pa_tag)); 1650 1651 /* Allocation settings */ 1652 max_type = PCI_INTR_TYPE_MSIX; 1653 counts[PCI_INTR_TYPE_MSIX] = sc->sc_ntxqueues + sc->sc_nrxqueues + 1; 1654 counts[PCI_INTR_TYPE_MSI] = 1; 1655 counts[PCI_INTR_TYPE_INTX] = 1; 1656 1657 alloc_retry: 1658 if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) { 1659 aprint_error_dev(sc->sc_dev, "failed to allocate interrupt\n"); 1660 return; 1661 } 1662 1663 if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSIX) { 1664 error = wm_setup_msix(sc); 1665 if (error) { 1666 pci_intr_release(pc, sc->sc_intrs, 1667 counts[PCI_INTR_TYPE_MSIX]); 1668 1669 /* Setup for MSI: Disable MSI-X */ 1670 max_type = PCI_INTR_TYPE_MSI; 1671 counts[PCI_INTR_TYPE_MSI] = 1; 1672 counts[PCI_INTR_TYPE_INTX] = 1; 1673 goto alloc_retry; 1674 } 1675 } else if (pci_intr_type(sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) { 1676 wm_adjust_qnum(sc, 0); /* must not use multiqueue */ 1677 error = wm_setup_legacy(sc); 1678 if (error) { 1679 pci_intr_release(sc->sc_pc, sc->sc_intrs, 1680 counts[PCI_INTR_TYPE_MSI]); 1681 1682 /* The next try is for INTx: Disable MSI */ 1683 max_type = PCI_INTR_TYPE_INTX; 1684 counts[PCI_INTR_TYPE_INTX] = 1; 1685 goto alloc_retry; 1686 } 1687 } else { 1688 wm_adjust_qnum(sc, 0); /* must not use multiqueue */ 1689 error = wm_setup_legacy(sc); 1690 if (error) { 1691 pci_intr_release(sc->sc_pc, sc->sc_intrs, 1692 counts[PCI_INTR_TYPE_INTX]); 1693 return; 1694 } 1695 } 1696 1697 /* 1698 * Check the function ID (unit number of the chip). 1699 */ 1700 if ((sc->sc_type == WM_T_82546) || (sc->sc_type == WM_T_82546_3) 1701 || (sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_80003) 1702 || (sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) 1703 || (sc->sc_type == WM_T_82580) 1704 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) 1705 sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS) 1706 >> STATUS_FUNCID_SHIFT) & STATUS_FUNCID_MASK; 1707 else 1708 sc->sc_funcid = 0; 1709 1710 /* 1711 * Determine a few things about the bus we're connected to. 1712 */ 1713 if (sc->sc_type < WM_T_82543) { 1714 /* We don't really know the bus characteristics here. */ 1715 sc->sc_bus_speed = 33; 1716 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 1717 /* 1718 * CSA (Communication Streaming Architecture) is about as fast 1719 * a 32-bit 66MHz PCI Bus. 1720 */ 1721 sc->sc_flags |= WM_F_CSA; 1722 sc->sc_bus_speed = 66; 1723 aprint_verbose_dev(sc->sc_dev, 1724 "Communication Streaming Architecture\n"); 1725 if (sc->sc_type == WM_T_82547) { 1726 callout_init(&sc->sc_txfifo_ch, CALLOUT_FLAGS); 1727 callout_setfunc(&sc->sc_txfifo_ch, 1728 wm_82547_txfifo_stall, sc); 1729 aprint_verbose_dev(sc->sc_dev, 1730 "using 82547 Tx FIFO stall work-around\n"); 1731 } 1732 } else if (sc->sc_type >= WM_T_82571) { 1733 sc->sc_flags |= WM_F_PCIE; 1734 if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) 1735 && (sc->sc_type != WM_T_ICH10) 1736 && (sc->sc_type != WM_T_PCH) 1737 && (sc->sc_type != WM_T_PCH2) 1738 && (sc->sc_type != WM_T_PCH_LPT) 1739 && (sc->sc_type != WM_T_PCH_SPT)) { 1740 /* ICH* and PCH* have no PCIe capability registers */ 1741 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1742 PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff, 1743 NULL) == 0) 1744 aprint_error_dev(sc->sc_dev, 1745 "unable to find PCIe capability\n"); 1746 } 1747 aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n"); 1748 } else { 1749 reg = CSR_READ(sc, WMREG_STATUS); 1750 if (reg & STATUS_BUS64) 1751 sc->sc_flags |= WM_F_BUS64; 1752 if ((reg & STATUS_PCIX_MODE) != 0) { 1753 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 1754 1755 sc->sc_flags |= WM_F_PCIX; 1756 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1757 PCI_CAP_PCIX, &sc->sc_pcixe_capoff, NULL) == 0) 1758 aprint_error_dev(sc->sc_dev, 1759 "unable to find PCIX capability\n"); 1760 else if (sc->sc_type != WM_T_82545_3 && 1761 sc->sc_type != WM_T_82546_3) { 1762 /* 1763 * Work around a problem caused by the BIOS 1764 * setting the max memory read byte count 1765 * incorrectly. 1766 */ 1767 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 1768 sc->sc_pcixe_capoff + PCIX_CMD); 1769 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 1770 sc->sc_pcixe_capoff + PCIX_STATUS); 1771 1772 bytecnt = (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >> 1773 PCIX_CMD_BYTECNT_SHIFT; 1774 maxb = (pcix_sts & PCIX_STATUS_MAXB_MASK) >> 1775 PCIX_STATUS_MAXB_SHIFT; 1776 if (bytecnt > maxb) { 1777 aprint_verbose_dev(sc->sc_dev, 1778 "resetting PCI-X MMRBC: %d -> %d\n", 1779 512 << bytecnt, 512 << maxb); 1780 pcix_cmd = (pcix_cmd & 1781 ~PCIX_CMD_BYTECNT_MASK) | 1782 (maxb << PCIX_CMD_BYTECNT_SHIFT); 1783 pci_conf_write(pa->pa_pc, pa->pa_tag, 1784 sc->sc_pcixe_capoff + PCIX_CMD, 1785 pcix_cmd); 1786 } 1787 } 1788 } 1789 /* 1790 * The quad port adapter is special; it has a PCIX-PCIX 1791 * bridge on the board, and can run the secondary bus at 1792 * a higher speed. 1793 */ 1794 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 1795 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 1796 : 66; 1797 } else if (sc->sc_flags & WM_F_PCIX) { 1798 switch (reg & STATUS_PCIXSPD_MASK) { 1799 case STATUS_PCIXSPD_50_66: 1800 sc->sc_bus_speed = 66; 1801 break; 1802 case STATUS_PCIXSPD_66_100: 1803 sc->sc_bus_speed = 100; 1804 break; 1805 case STATUS_PCIXSPD_100_133: 1806 sc->sc_bus_speed = 133; 1807 break; 1808 default: 1809 aprint_error_dev(sc->sc_dev, 1810 "unknown PCIXSPD %d; assuming 66MHz\n", 1811 reg & STATUS_PCIXSPD_MASK); 1812 sc->sc_bus_speed = 66; 1813 break; 1814 } 1815 } else 1816 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 1817 aprint_verbose_dev(sc->sc_dev, "%d-bit %dMHz %s bus\n", 1818 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 1819 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 1820 } 1821 1822 /* clear interesting stat counters */ 1823 CSR_READ(sc, WMREG_COLC); 1824 CSR_READ(sc, WMREG_RXERRC); 1825 1826 /* get PHY control from SMBus to PCIe */ 1827 if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2) 1828 || (sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) 1829 wm_smbustopci(sc); 1830 1831 /* Reset the chip to a known state. */ 1832 wm_reset(sc); 1833 1834 /* Get some information about the EEPROM. */ 1835 switch (sc->sc_type) { 1836 case WM_T_82542_2_0: 1837 case WM_T_82542_2_1: 1838 case WM_T_82543: 1839 case WM_T_82544: 1840 /* Microwire */ 1841 sc->sc_nvm_wordsize = 64; 1842 sc->sc_nvm_addrbits = 6; 1843 break; 1844 case WM_T_82540: 1845 case WM_T_82545: 1846 case WM_T_82545_3: 1847 case WM_T_82546: 1848 case WM_T_82546_3: 1849 /* Microwire */ 1850 reg = CSR_READ(sc, WMREG_EECD); 1851 if (reg & EECD_EE_SIZE) { 1852 sc->sc_nvm_wordsize = 256; 1853 sc->sc_nvm_addrbits = 8; 1854 } else { 1855 sc->sc_nvm_wordsize = 64; 1856 sc->sc_nvm_addrbits = 6; 1857 } 1858 sc->sc_flags |= WM_F_LOCK_EECD; 1859 break; 1860 case WM_T_82541: 1861 case WM_T_82541_2: 1862 case WM_T_82547: 1863 case WM_T_82547_2: 1864 sc->sc_flags |= WM_F_LOCK_EECD; 1865 reg = CSR_READ(sc, WMREG_EECD); 1866 if (reg & EECD_EE_TYPE) { 1867 /* SPI */ 1868 sc->sc_flags |= WM_F_EEPROM_SPI; 1869 wm_nvm_set_addrbits_size_eecd(sc); 1870 } else { 1871 /* Microwire */ 1872 if ((reg & EECD_EE_ABITS) != 0) { 1873 sc->sc_nvm_wordsize = 256; 1874 sc->sc_nvm_addrbits = 8; 1875 } else { 1876 sc->sc_nvm_wordsize = 64; 1877 sc->sc_nvm_addrbits = 6; 1878 } 1879 } 1880 break; 1881 case WM_T_82571: 1882 case WM_T_82572: 1883 /* SPI */ 1884 sc->sc_flags |= WM_F_EEPROM_SPI; 1885 wm_nvm_set_addrbits_size_eecd(sc); 1886 sc->sc_flags |= WM_F_LOCK_EECD | WM_F_LOCK_SWSM; 1887 break; 1888 case WM_T_82573: 1889 sc->sc_flags |= WM_F_LOCK_SWSM; 1890 /* FALLTHROUGH */ 1891 case WM_T_82574: 1892 case WM_T_82583: 1893 if (wm_nvm_is_onboard_eeprom(sc) == 0) { 1894 sc->sc_flags |= WM_F_EEPROM_FLASH; 1895 sc->sc_nvm_wordsize = 2048; 1896 } else { 1897 /* SPI */ 1898 sc->sc_flags |= WM_F_EEPROM_SPI; 1899 wm_nvm_set_addrbits_size_eecd(sc); 1900 } 1901 sc->sc_flags |= WM_F_EEPROM_EERDEEWR; 1902 break; 1903 case WM_T_82575: 1904 case WM_T_82576: 1905 case WM_T_82580: 1906 case WM_T_I350: 1907 case WM_T_I354: 1908 case WM_T_80003: 1909 /* SPI */ 1910 sc->sc_flags |= WM_F_EEPROM_SPI; 1911 wm_nvm_set_addrbits_size_eecd(sc); 1912 sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW 1913 | WM_F_LOCK_SWSM; 1914 break; 1915 case WM_T_ICH8: 1916 case WM_T_ICH9: 1917 case WM_T_ICH10: 1918 case WM_T_PCH: 1919 case WM_T_PCH2: 1920 case WM_T_PCH_LPT: 1921 /* FLASH */ 1922 sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF; 1923 sc->sc_nvm_wordsize = 2048; 1924 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,WM_ICH8_FLASH); 1925 if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0, 1926 &sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) { 1927 aprint_error_dev(sc->sc_dev, 1928 "can't map FLASH registers\n"); 1929 goto out; 1930 } 1931 reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG); 1932 sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) * 1933 ICH_FLASH_SECTOR_SIZE; 1934 sc->sc_ich8_flash_bank_size = 1935 ((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 1936 sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK); 1937 sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 1938 sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t); 1939 sc->sc_flashreg_offset = 0; 1940 break; 1941 case WM_T_PCH_SPT: 1942 /* SPT has no GFPREG; flash registers mapped through BAR0 */ 1943 sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF; 1944 sc->sc_flasht = sc->sc_st; 1945 sc->sc_flashh = sc->sc_sh; 1946 sc->sc_ich8_flash_base = 0; 1947 sc->sc_nvm_wordsize = 1948 (((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1) 1949 * NVM_SIZE_MULTIPLIER; 1950 /* It is size in bytes, we want words */ 1951 sc->sc_nvm_wordsize /= 2; 1952 /* assume 2 banks */ 1953 sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2; 1954 sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET; 1955 break; 1956 case WM_T_I210: 1957 case WM_T_I211: 1958 if (wm_nvm_get_flash_presence_i210(sc)) { 1959 wm_nvm_set_addrbits_size_eecd(sc); 1960 sc->sc_flags |= WM_F_EEPROM_FLASH_HW; 1961 sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW; 1962 } else { 1963 sc->sc_nvm_wordsize = INVM_SIZE; 1964 sc->sc_flags |= WM_F_EEPROM_INVM; 1965 sc->sc_flags |= WM_F_LOCK_SWFW; 1966 } 1967 break; 1968 default: 1969 break; 1970 } 1971 1972 /* Ensure the SMBI bit is clear before first NVM or PHY access */ 1973 switch (sc->sc_type) { 1974 case WM_T_82571: 1975 case WM_T_82572: 1976 reg = CSR_READ(sc, WMREG_SWSM2); 1977 if ((reg & SWSM2_LOCK) == 0) { 1978 CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK); 1979 force_clear_smbi = true; 1980 } else 1981 force_clear_smbi = false; 1982 break; 1983 case WM_T_82573: 1984 case WM_T_82574: 1985 case WM_T_82583: 1986 force_clear_smbi = true; 1987 break; 1988 default: 1989 force_clear_smbi = false; 1990 break; 1991 } 1992 if (force_clear_smbi) { 1993 reg = CSR_READ(sc, WMREG_SWSM); 1994 if ((reg & SWSM_SMBI) != 0) 1995 aprint_error_dev(sc->sc_dev, 1996 "Please update the Bootagent\n"); 1997 CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI); 1998 } 1999 2000 /* 2001 * Defer printing the EEPROM type until after verifying the checksum 2002 * This allows the EEPROM type to be printed correctly in the case 2003 * that no EEPROM is attached. 2004 */ 2005 /* 2006 * Validate the EEPROM checksum. If the checksum fails, flag 2007 * this for later, so we can fail future reads from the EEPROM. 2008 */ 2009 if (wm_nvm_validate_checksum(sc)) { 2010 /* 2011 * Read twice again because some PCI-e parts fail the 2012 * first check due to the link being in sleep state. 2013 */ 2014 if (wm_nvm_validate_checksum(sc)) 2015 sc->sc_flags |= WM_F_EEPROM_INVALID; 2016 } 2017 2018 /* Set device properties (macflags) */ 2019 prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags); 2020 2021 if (sc->sc_flags & WM_F_EEPROM_INVALID) 2022 aprint_verbose_dev(sc->sc_dev, "No EEPROM"); 2023 else { 2024 aprint_verbose_dev(sc->sc_dev, "%u words ", 2025 sc->sc_nvm_wordsize); 2026 if (sc->sc_flags & WM_F_EEPROM_INVM) 2027 aprint_verbose("iNVM"); 2028 else if (sc->sc_flags & WM_F_EEPROM_FLASH_HW) 2029 aprint_verbose("FLASH(HW)"); 2030 else if (sc->sc_flags & WM_F_EEPROM_FLASH) 2031 aprint_verbose("FLASH"); 2032 else { 2033 if (sc->sc_flags & WM_F_EEPROM_SPI) 2034 eetype = "SPI"; 2035 else 2036 eetype = "MicroWire"; 2037 aprint_verbose("(%d address bits) %s EEPROM", 2038 sc->sc_nvm_addrbits, eetype); 2039 } 2040 } 2041 wm_nvm_version(sc); 2042 aprint_verbose("\n"); 2043 2044 /* Check for I21[01] PLL workaround */ 2045 if (sc->sc_type == WM_T_I210) 2046 sc->sc_flags |= WM_F_PLL_WA_I210; 2047 if ((sc->sc_type == WM_T_I210) && wm_nvm_get_flash_presence_i210(sc)) { 2048 /* NVM image release 3.25 has a workaround */ 2049 if ((sc->sc_nvm_ver_major < 3) 2050 || ((sc->sc_nvm_ver_major == 3) 2051 && (sc->sc_nvm_ver_minor < 25))) { 2052 aprint_verbose_dev(sc->sc_dev, 2053 "ROM image version %d.%d is older than 3.25\n", 2054 sc->sc_nvm_ver_major, sc->sc_nvm_ver_minor); 2055 sc->sc_flags |= WM_F_PLL_WA_I210; 2056 } 2057 } 2058 if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) 2059 wm_pll_workaround_i210(sc); 2060 2061 wm_get_wakeup(sc); 2062 switch (sc->sc_type) { 2063 case WM_T_82571: 2064 case WM_T_82572: 2065 case WM_T_82573: 2066 case WM_T_82574: 2067 case WM_T_82583: 2068 case WM_T_80003: 2069 case WM_T_ICH8: 2070 case WM_T_ICH9: 2071 case WM_T_ICH10: 2072 case WM_T_PCH: 2073 case WM_T_PCH2: 2074 case WM_T_PCH_LPT: 2075 case WM_T_PCH_SPT: 2076 /* Non-AMT based hardware can now take control from firmware */ 2077 if ((sc->sc_flags & WM_F_HAS_AMT) == 0) 2078 wm_get_hw_control(sc); 2079 break; 2080 default: 2081 break; 2082 } 2083 2084 /* 2085 * Read the Ethernet address from the EEPROM, if not first found 2086 * in device properties. 2087 */ 2088 ea = prop_dictionary_get(dict, "mac-address"); 2089 if (ea != NULL) { 2090 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 2091 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 2092 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 2093 } else { 2094 if (wm_read_mac_addr(sc, enaddr) != 0) { 2095 aprint_error_dev(sc->sc_dev, 2096 "unable to read Ethernet address\n"); 2097 goto out; 2098 } 2099 } 2100 2101 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 2102 ether_sprintf(enaddr)); 2103 2104 /* 2105 * Read the config info from the EEPROM, and set up various 2106 * bits in the control registers based on their contents. 2107 */ 2108 pn = prop_dictionary_get(dict, "i82543-cfg1"); 2109 if (pn != NULL) { 2110 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 2111 cfg1 = (uint16_t) prop_number_integer_value(pn); 2112 } else { 2113 if (wm_nvm_read(sc, NVM_OFF_CFG1, 1, &cfg1)) { 2114 aprint_error_dev(sc->sc_dev, "unable to read CFG1\n"); 2115 goto out; 2116 } 2117 } 2118 2119 pn = prop_dictionary_get(dict, "i82543-cfg2"); 2120 if (pn != NULL) { 2121 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 2122 cfg2 = (uint16_t) prop_number_integer_value(pn); 2123 } else { 2124 if (wm_nvm_read(sc, NVM_OFF_CFG2, 1, &cfg2)) { 2125 aprint_error_dev(sc->sc_dev, "unable to read CFG2\n"); 2126 goto out; 2127 } 2128 } 2129 2130 /* check for WM_F_WOL */ 2131 switch (sc->sc_type) { 2132 case WM_T_82542_2_0: 2133 case WM_T_82542_2_1: 2134 case WM_T_82543: 2135 /* dummy? */ 2136 eeprom_data = 0; 2137 apme_mask = NVM_CFG3_APME; 2138 break; 2139 case WM_T_82544: 2140 apme_mask = NVM_CFG2_82544_APM_EN; 2141 eeprom_data = cfg2; 2142 break; 2143 case WM_T_82546: 2144 case WM_T_82546_3: 2145 case WM_T_82571: 2146 case WM_T_82572: 2147 case WM_T_82573: 2148 case WM_T_82574: 2149 case WM_T_82583: 2150 case WM_T_80003: 2151 default: 2152 apme_mask = NVM_CFG3_APME; 2153 wm_nvm_read(sc, (sc->sc_funcid == 1) ? NVM_OFF_CFG3_PORTB 2154 : NVM_OFF_CFG3_PORTA, 1, &eeprom_data); 2155 break; 2156 case WM_T_82575: 2157 case WM_T_82576: 2158 case WM_T_82580: 2159 case WM_T_I350: 2160 case WM_T_I354: /* XXX ok? */ 2161 case WM_T_ICH8: 2162 case WM_T_ICH9: 2163 case WM_T_ICH10: 2164 case WM_T_PCH: 2165 case WM_T_PCH2: 2166 case WM_T_PCH_LPT: 2167 case WM_T_PCH_SPT: 2168 /* XXX The funcid should be checked on some devices */ 2169 apme_mask = WUC_APME; 2170 eeprom_data = CSR_READ(sc, WMREG_WUC); 2171 break; 2172 } 2173 2174 /* Check for WM_F_WOL flag after the setting of the EEPROM stuff */ 2175 if ((eeprom_data & apme_mask) != 0) 2176 sc->sc_flags |= WM_F_WOL; 2177 #ifdef WM_DEBUG 2178 if ((sc->sc_flags & WM_F_WOL) != 0) 2179 printf("WOL\n"); 2180 #endif 2181 2182 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) { 2183 /* Check NVM for autonegotiation */ 2184 if (wm_nvm_read(sc, NVM_OFF_COMPAT, 1, &nvmword) == 0) { 2185 if ((nvmword & NVM_COMPAT_SERDES_FORCE_MODE) != 0) 2186 sc->sc_flags |= WM_F_PCS_DIS_AUTONEGO; 2187 } 2188 } 2189 2190 /* 2191 * XXX need special handling for some multiple port cards 2192 * to disable a paticular port. 2193 */ 2194 2195 if (sc->sc_type >= WM_T_82544) { 2196 pn = prop_dictionary_get(dict, "i82543-swdpin"); 2197 if (pn != NULL) { 2198 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 2199 swdpin = (uint16_t) prop_number_integer_value(pn); 2200 } else { 2201 if (wm_nvm_read(sc, NVM_OFF_SWDPIN, 1, &swdpin)) { 2202 aprint_error_dev(sc->sc_dev, 2203 "unable to read SWDPIN\n"); 2204 goto out; 2205 } 2206 } 2207 } 2208 2209 if (cfg1 & NVM_CFG1_ILOS) 2210 sc->sc_ctrl |= CTRL_ILOS; 2211 2212 /* 2213 * XXX 2214 * This code isn't correct because pin 2 and 3 are located 2215 * in different position on newer chips. Check all datasheet. 2216 * 2217 * Until resolve this problem, check if a chip < 82580 2218 */ 2219 if (sc->sc_type <= WM_T_82580) { 2220 if (sc->sc_type >= WM_T_82544) { 2221 sc->sc_ctrl |= 2222 ((swdpin >> NVM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 2223 CTRL_SWDPIO_SHIFT; 2224 sc->sc_ctrl |= 2225 ((swdpin >> NVM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 2226 CTRL_SWDPINS_SHIFT; 2227 } else { 2228 sc->sc_ctrl |= 2229 ((cfg1 >> NVM_CFG1_SWDPIO_SHIFT) & 0xf) << 2230 CTRL_SWDPIO_SHIFT; 2231 } 2232 } 2233 2234 /* XXX For other than 82580? */ 2235 if (sc->sc_type == WM_T_82580) { 2236 wm_nvm_read(sc, NVM_OFF_CFG3_PORTA, 1, &nvmword); 2237 if (nvmword & __BIT(13)) 2238 sc->sc_ctrl |= CTRL_ILOS; 2239 } 2240 2241 #if 0 2242 if (sc->sc_type >= WM_T_82544) { 2243 if (cfg1 & NVM_CFG1_IPS0) 2244 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 2245 if (cfg1 & NVM_CFG1_IPS1) 2246 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 2247 sc->sc_ctrl_ext |= 2248 ((swdpin >> (NVM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 2249 CTRL_EXT_SWDPIO_SHIFT; 2250 sc->sc_ctrl_ext |= 2251 ((swdpin >> (NVM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 2252 CTRL_EXT_SWDPINS_SHIFT; 2253 } else { 2254 sc->sc_ctrl_ext |= 2255 ((cfg2 >> NVM_CFG2_SWDPIO_SHIFT) & 0xf) << 2256 CTRL_EXT_SWDPIO_SHIFT; 2257 } 2258 #endif 2259 2260 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2261 #if 0 2262 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2263 #endif 2264 2265 if (sc->sc_type == WM_T_PCH) { 2266 uint16_t val; 2267 2268 /* Save the NVM K1 bit setting */ 2269 wm_nvm_read(sc, NVM_OFF_K1_CONFIG, 1, &val); 2270 2271 if ((val & NVM_K1_CONFIG_ENABLE) != 0) 2272 sc->sc_nvm_k1_enabled = 1; 2273 else 2274 sc->sc_nvm_k1_enabled = 0; 2275 } 2276 2277 /* 2278 * Determine if we're TBI,GMII or SGMII mode, and initialize the 2279 * media structures accordingly. 2280 */ 2281 if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9 2282 || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH 2283 || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT 2284 || sc->sc_type == WM_T_PCH_SPT || sc->sc_type == WM_T_82573 2285 || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) { 2286 /* STATUS_TBIMODE reserved/reused, can't rely on it */ 2287 wm_gmii_mediainit(sc, wmp->wmp_product); 2288 } else if (sc->sc_type < WM_T_82543 || 2289 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 2290 if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) { 2291 aprint_error_dev(sc->sc_dev, 2292 "WARNING: TBIMODE set on 1000BASE-T product!\n"); 2293 sc->sc_mediatype = WM_MEDIATYPE_FIBER; 2294 } 2295 wm_tbi_mediainit(sc); 2296 } else { 2297 switch (sc->sc_type) { 2298 case WM_T_82575: 2299 case WM_T_82576: 2300 case WM_T_82580: 2301 case WM_T_I350: 2302 case WM_T_I354: 2303 case WM_T_I210: 2304 case WM_T_I211: 2305 reg = CSR_READ(sc, WMREG_CTRL_EXT); 2306 link_mode = reg & CTRL_EXT_LINK_MODE_MASK; 2307 switch (link_mode) { 2308 case CTRL_EXT_LINK_MODE_1000KX: 2309 aprint_verbose_dev(sc->sc_dev, "1000KX\n"); 2310 sc->sc_mediatype = WM_MEDIATYPE_SERDES; 2311 break; 2312 case CTRL_EXT_LINK_MODE_SGMII: 2313 if (wm_sgmii_uses_mdio(sc)) { 2314 aprint_verbose_dev(sc->sc_dev, 2315 "SGMII(MDIO)\n"); 2316 sc->sc_flags |= WM_F_SGMII; 2317 sc->sc_mediatype = WM_MEDIATYPE_COPPER; 2318 break; 2319 } 2320 aprint_verbose_dev(sc->sc_dev, "SGMII(I2C)\n"); 2321 /*FALLTHROUGH*/ 2322 case CTRL_EXT_LINK_MODE_PCIE_SERDES: 2323 sc->sc_mediatype = wm_sfp_get_media_type(sc); 2324 if (sc->sc_mediatype == WM_MEDIATYPE_UNKNOWN) { 2325 if (link_mode 2326 == CTRL_EXT_LINK_MODE_SGMII) { 2327 sc->sc_mediatype 2328 = WM_MEDIATYPE_COPPER; 2329 sc->sc_flags |= WM_F_SGMII; 2330 } else { 2331 sc->sc_mediatype 2332 = WM_MEDIATYPE_SERDES; 2333 aprint_verbose_dev(sc->sc_dev, 2334 "SERDES\n"); 2335 } 2336 break; 2337 } 2338 if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) 2339 aprint_verbose_dev(sc->sc_dev, 2340 "SERDES\n"); 2341 2342 /* Change current link mode setting */ 2343 reg &= ~CTRL_EXT_LINK_MODE_MASK; 2344 switch (sc->sc_mediatype) { 2345 case WM_MEDIATYPE_COPPER: 2346 reg |= CTRL_EXT_LINK_MODE_SGMII; 2347 break; 2348 case WM_MEDIATYPE_SERDES: 2349 reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES; 2350 break; 2351 default: 2352 break; 2353 } 2354 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 2355 break; 2356 case CTRL_EXT_LINK_MODE_GMII: 2357 default: 2358 aprint_verbose_dev(sc->sc_dev, "Copper\n"); 2359 sc->sc_mediatype = WM_MEDIATYPE_COPPER; 2360 break; 2361 } 2362 2363 reg &= ~CTRL_EXT_I2C_ENA; 2364 if ((sc->sc_flags & WM_F_SGMII) != 0) 2365 reg |= CTRL_EXT_I2C_ENA; 2366 else 2367 reg &= ~CTRL_EXT_I2C_ENA; 2368 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 2369 2370 if (sc->sc_mediatype == WM_MEDIATYPE_COPPER) 2371 wm_gmii_mediainit(sc, wmp->wmp_product); 2372 else 2373 wm_tbi_mediainit(sc); 2374 break; 2375 default: 2376 if (sc->sc_mediatype == WM_MEDIATYPE_FIBER) 2377 aprint_error_dev(sc->sc_dev, 2378 "WARNING: TBIMODE clear on 1000BASE-X product!\n"); 2379 sc->sc_mediatype = WM_MEDIATYPE_COPPER; 2380 wm_gmii_mediainit(sc, wmp->wmp_product); 2381 } 2382 } 2383 2384 ifp = &sc->sc_ethercom.ec_if; 2385 xname = device_xname(sc->sc_dev); 2386 strlcpy(ifp->if_xname, xname, IFNAMSIZ); 2387 ifp->if_softc = sc; 2388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2389 ifp->if_ioctl = wm_ioctl; 2390 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) 2391 ifp->if_start = wm_nq_start; 2392 else 2393 ifp->if_start = wm_start; 2394 ifp->if_watchdog = wm_watchdog; 2395 ifp->if_init = wm_init; 2396 ifp->if_stop = wm_stop; 2397 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 2398 IFQ_SET_READY(&ifp->if_snd); 2399 2400 /* Check for jumbo frame */ 2401 switch (sc->sc_type) { 2402 case WM_T_82573: 2403 /* XXX limited to 9234 if ASPM is disabled */ 2404 wm_nvm_read(sc, NVM_OFF_INIT_3GIO_3, 1, &nvmword); 2405 if ((nvmword & NVM_3GIO_3_ASPM_MASK) != 0) 2406 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2407 break; 2408 case WM_T_82571: 2409 case WM_T_82572: 2410 case WM_T_82574: 2411 case WM_T_82575: 2412 case WM_T_82576: 2413 case WM_T_82580: 2414 case WM_T_I350: 2415 case WM_T_I354: /* XXXX ok? */ 2416 case WM_T_I210: 2417 case WM_T_I211: 2418 case WM_T_80003: 2419 case WM_T_ICH9: 2420 case WM_T_ICH10: 2421 case WM_T_PCH2: /* PCH2 supports 9K frame size */ 2422 case WM_T_PCH_LPT: 2423 case WM_T_PCH_SPT: 2424 /* XXX limited to 9234 */ 2425 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2426 break; 2427 case WM_T_PCH: 2428 /* XXX limited to 4096 */ 2429 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2430 break; 2431 case WM_T_82542_2_0: 2432 case WM_T_82542_2_1: 2433 case WM_T_82583: 2434 case WM_T_ICH8: 2435 /* No support for jumbo frame */ 2436 break; 2437 default: 2438 /* ETHER_MAX_LEN_JUMBO */ 2439 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 2440 break; 2441 } 2442 2443 /* If we're a i82543 or greater, we can support VLANs. */ 2444 if (sc->sc_type >= WM_T_82543) 2445 sc->sc_ethercom.ec_capabilities |= 2446 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 2447 2448 /* 2449 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 2450 * on i82543 and later. 2451 */ 2452 if (sc->sc_type >= WM_T_82543) { 2453 ifp->if_capabilities |= 2454 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2455 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2456 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 2457 IFCAP_CSUM_TCPv6_Tx | 2458 IFCAP_CSUM_UDPv6_Tx; 2459 } 2460 2461 /* 2462 * XXXyamt: i'm not sure which chips support RXCSUM_IPV6OFL. 2463 * 2464 * 82541GI (8086:1076) ... no 2465 * 82572EI (8086:10b9) ... yes 2466 */ 2467 if (sc->sc_type >= WM_T_82571) { 2468 ifp->if_capabilities |= 2469 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 2470 } 2471 2472 /* 2473 * If we're a i82544 or greater (except i82547), we can do 2474 * TCP segmentation offload. 2475 */ 2476 if (sc->sc_type >= WM_T_82544 && sc->sc_type != WM_T_82547) { 2477 ifp->if_capabilities |= IFCAP_TSOv4; 2478 } 2479 2480 if (sc->sc_type >= WM_T_82571) { 2481 ifp->if_capabilities |= IFCAP_TSOv6; 2482 } 2483 2484 #ifdef WM_MPSAFE 2485 sc->sc_core_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 2486 #else 2487 sc->sc_core_lock = NULL; 2488 #endif 2489 2490 /* Attach the interface. */ 2491 if_initialize(ifp); 2492 sc->sc_ipq = if_percpuq_create(&sc->sc_ethercom.ec_if); 2493 ether_ifattach(ifp, enaddr); 2494 if_register(ifp); 2495 ether_set_ifflags_cb(&sc->sc_ethercom, wm_ifflags_cb); 2496 rnd_attach_source(&sc->rnd_source, xname, RND_TYPE_NET, 2497 RND_FLAG_DEFAULT); 2498 2499 #ifdef WM_EVENT_COUNTERS 2500 /* Attach event counters. */ 2501 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 2502 NULL, xname, "txsstall"); 2503 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 2504 NULL, xname, "txdstall"); 2505 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 2506 NULL, xname, "txfifo_stall"); 2507 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 2508 NULL, xname, "txdw"); 2509 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 2510 NULL, xname, "txqe"); 2511 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 2512 NULL, xname, "rxintr"); 2513 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 2514 NULL, xname, "linkintr"); 2515 2516 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 2517 NULL, xname, "rxipsum"); 2518 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 2519 NULL, xname, "rxtusum"); 2520 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 2521 NULL, xname, "txipsum"); 2522 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 2523 NULL, xname, "txtusum"); 2524 evcnt_attach_dynamic(&sc->sc_ev_txtusum6, EVCNT_TYPE_MISC, 2525 NULL, xname, "txtusum6"); 2526 2527 evcnt_attach_dynamic(&sc->sc_ev_txtso, EVCNT_TYPE_MISC, 2528 NULL, xname, "txtso"); 2529 evcnt_attach_dynamic(&sc->sc_ev_txtso6, EVCNT_TYPE_MISC, 2530 NULL, xname, "txtso6"); 2531 evcnt_attach_dynamic(&sc->sc_ev_txtsopain, EVCNT_TYPE_MISC, 2532 NULL, xname, "txtsopain"); 2533 2534 for (i = 0; i < WM_NTXSEGS; i++) { 2535 snprintf(wm_txseg_evcnt_names[i], 2536 sizeof(wm_txseg_evcnt_names[i]), "txseg%d", i); 2537 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 2538 NULL, xname, wm_txseg_evcnt_names[i]); 2539 } 2540 2541 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 2542 NULL, xname, "txdrop"); 2543 2544 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 2545 NULL, xname, "tu"); 2546 2547 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 2548 NULL, xname, "tx_xoff"); 2549 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 2550 NULL, xname, "tx_xon"); 2551 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 2552 NULL, xname, "rx_xoff"); 2553 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 2554 NULL, xname, "rx_xon"); 2555 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 2556 NULL, xname, "rx_macctl"); 2557 #endif /* WM_EVENT_COUNTERS */ 2558 2559 if (pmf_device_register(self, wm_suspend, wm_resume)) 2560 pmf_class_network_register(self, ifp); 2561 else 2562 aprint_error_dev(self, "couldn't establish power handler\n"); 2563 2564 sc->sc_flags |= WM_F_ATTACHED; 2565 out: 2566 return; 2567 } 2568 2569 /* The detach function (ca_detach) */ 2570 static int 2571 wm_detach(device_t self, int flags __unused) 2572 { 2573 struct wm_softc *sc = device_private(self); 2574 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2575 int i; 2576 #ifndef WM_MPSAFE 2577 int s; 2578 #endif 2579 2580 if ((sc->sc_flags & WM_F_ATTACHED) == 0) 2581 return 0; 2582 2583 #ifndef WM_MPSAFE 2584 s = splnet(); 2585 #endif 2586 /* Stop the interface. Callouts are stopped in it. */ 2587 wm_stop(ifp, 1); 2588 2589 #ifndef WM_MPSAFE 2590 splx(s); 2591 #endif 2592 2593 pmf_device_deregister(self); 2594 2595 /* Tell the firmware about the release */ 2596 WM_CORE_LOCK(sc); 2597 wm_release_manageability(sc); 2598 wm_release_hw_control(sc); 2599 WM_CORE_UNLOCK(sc); 2600 2601 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2602 2603 /* Delete all remaining media. */ 2604 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2605 2606 ether_ifdetach(ifp); 2607 if_detach(ifp); 2608 if_percpuq_destroy(sc->sc_ipq); 2609 2610 /* Unload RX dmamaps and free mbufs */ 2611 for (i = 0; i < sc->sc_nrxqueues; i++) { 2612 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 2613 WM_RX_LOCK(rxq); 2614 wm_rxdrain(rxq); 2615 WM_RX_UNLOCK(rxq); 2616 } 2617 /* Must unlock here */ 2618 2619 /* Disestablish the interrupt handler */ 2620 for (i = 0; i < sc->sc_nintrs; i++) { 2621 if (sc->sc_ihs[i] != NULL) { 2622 pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]); 2623 sc->sc_ihs[i] = NULL; 2624 } 2625 } 2626 pci_intr_release(sc->sc_pc, sc->sc_intrs, sc->sc_nintrs); 2627 2628 wm_free_txrx_queues(sc); 2629 2630 /* Unmap the registers */ 2631 if (sc->sc_ss) { 2632 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_ss); 2633 sc->sc_ss = 0; 2634 } 2635 if (sc->sc_ios) { 2636 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 2637 sc->sc_ios = 0; 2638 } 2639 if (sc->sc_flashs) { 2640 bus_space_unmap(sc->sc_flasht, sc->sc_flashh, sc->sc_flashs); 2641 sc->sc_flashs = 0; 2642 } 2643 2644 if (sc->sc_core_lock) 2645 mutex_obj_free(sc->sc_core_lock); 2646 2647 return 0; 2648 } 2649 2650 static bool 2651 wm_suspend(device_t self, const pmf_qual_t *qual) 2652 { 2653 struct wm_softc *sc = device_private(self); 2654 2655 wm_release_manageability(sc); 2656 wm_release_hw_control(sc); 2657 #ifdef WM_WOL 2658 wm_enable_wakeup(sc); 2659 #endif 2660 2661 return true; 2662 } 2663 2664 static bool 2665 wm_resume(device_t self, const pmf_qual_t *qual) 2666 { 2667 struct wm_softc *sc = device_private(self); 2668 2669 wm_init_manageability(sc); 2670 2671 return true; 2672 } 2673 2674 /* 2675 * wm_watchdog: [ifnet interface function] 2676 * 2677 * Watchdog timer handler. 2678 */ 2679 static void 2680 wm_watchdog(struct ifnet *ifp) 2681 { 2682 struct wm_softc *sc = ifp->if_softc; 2683 struct wm_txqueue *txq = &sc->sc_txq[0]; 2684 2685 /* 2686 * Since we're using delayed interrupts, sweep up 2687 * before we report an error. 2688 */ 2689 WM_TX_LOCK(txq); 2690 wm_txeof(sc); 2691 WM_TX_UNLOCK(txq); 2692 2693 if (txq->txq_free != WM_NTXDESC(txq)) { 2694 #ifdef WM_DEBUG 2695 int i, j; 2696 struct wm_txsoft *txs; 2697 #endif 2698 log(LOG_ERR, 2699 "%s: device timeout (txfree %d txsfree %d txnext %d)\n", 2700 device_xname(sc->sc_dev), txq->txq_free, txq->txq_sfree, 2701 txq->txq_next); 2702 ifp->if_oerrors++; 2703 #ifdef WM_DEBUG 2704 for (i = txq->txq_sdirty; i != txq->txq_snext ; 2705 i = WM_NEXTTXS(txq, i)) { 2706 txs = &txq->txq_soft[i]; 2707 printf("txs %d tx %d -> %d\n", 2708 i, txs->txs_firstdesc, txs->txs_lastdesc); 2709 for (j = txs->txs_firstdesc; ; 2710 j = WM_NEXTTX(txq, j)) { 2711 printf("\tdesc %d: 0x%" PRIx64 "\n", j, 2712 txq->txq_nq_descs[j].nqtx_data.nqtxd_addr); 2713 printf("\t %#08x%08x\n", 2714 txq->txq_nq_descs[j].nqtx_data.nqtxd_fields, 2715 txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen); 2716 if (j == txs->txs_lastdesc) 2717 break; 2718 } 2719 } 2720 #endif 2721 /* Reset the interface. */ 2722 (void) wm_init(ifp); 2723 } 2724 2725 /* Try to get more packets going. */ 2726 ifp->if_start(ifp); 2727 } 2728 2729 /* 2730 * wm_tick: 2731 * 2732 * One second timer, used to check link status, sweep up 2733 * completed transmit jobs, etc. 2734 */ 2735 static void 2736 wm_tick(void *arg) 2737 { 2738 struct wm_softc *sc = arg; 2739 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2740 #ifndef WM_MPSAFE 2741 int s; 2742 2743 s = splnet(); 2744 #endif 2745 2746 WM_CORE_LOCK(sc); 2747 2748 if (sc->sc_stopping) 2749 goto out; 2750 2751 if (sc->sc_type >= WM_T_82542_2_1) { 2752 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2753 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2754 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2755 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2756 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2757 } 2758 2759 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 2760 ifp->if_ierrors += 0ULL + /* ensure quad_t */ 2761 + CSR_READ(sc, WMREG_CRCERRS) 2762 + CSR_READ(sc, WMREG_ALGNERRC) 2763 + CSR_READ(sc, WMREG_SYMERRC) 2764 + CSR_READ(sc, WMREG_RXERRC) 2765 + CSR_READ(sc, WMREG_SEC) 2766 + CSR_READ(sc, WMREG_CEXTERR) 2767 + CSR_READ(sc, WMREG_RLEC); 2768 ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC) + CSR_READ(sc, WMREG_RNBC); 2769 2770 if (sc->sc_flags & WM_F_HAS_MII) 2771 mii_tick(&sc->sc_mii); 2772 else if ((sc->sc_type >= WM_T_82575) 2773 && (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) 2774 wm_serdes_tick(sc); 2775 else 2776 wm_tbi_tick(sc); 2777 2778 out: 2779 WM_CORE_UNLOCK(sc); 2780 #ifndef WM_MPSAFE 2781 splx(s); 2782 #endif 2783 2784 if (!sc->sc_stopping) 2785 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2786 } 2787 2788 static int 2789 wm_ifflags_cb(struct ethercom *ec) 2790 { 2791 struct ifnet *ifp = &ec->ec_if; 2792 struct wm_softc *sc = ifp->if_softc; 2793 int change = ifp->if_flags ^ sc->sc_if_flags; 2794 int rc = 0; 2795 2796 WM_CORE_LOCK(sc); 2797 2798 if (change != 0) 2799 sc->sc_if_flags = ifp->if_flags; 2800 2801 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 2802 rc = ENETRESET; 2803 goto out; 2804 } 2805 2806 if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2807 wm_set_filter(sc); 2808 2809 wm_set_vlan(sc); 2810 2811 out: 2812 WM_CORE_UNLOCK(sc); 2813 2814 return rc; 2815 } 2816 2817 /* 2818 * wm_ioctl: [ifnet interface function] 2819 * 2820 * Handle control requests from the operator. 2821 */ 2822 static int 2823 wm_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2824 { 2825 struct wm_softc *sc = ifp->if_softc; 2826 struct ifreq *ifr = (struct ifreq *) data; 2827 struct ifaddr *ifa = (struct ifaddr *)data; 2828 struct sockaddr_dl *sdl; 2829 int s, error; 2830 2831 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 2832 device_xname(sc->sc_dev), __func__)); 2833 #ifndef WM_MPSAFE 2834 s = splnet(); 2835 #endif 2836 switch (cmd) { 2837 case SIOCSIFMEDIA: 2838 case SIOCGIFMEDIA: 2839 WM_CORE_LOCK(sc); 2840 /* Flow control requires full-duplex mode. */ 2841 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 2842 (ifr->ifr_media & IFM_FDX) == 0) 2843 ifr->ifr_media &= ~IFM_ETH_FMASK; 2844 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 2845 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 2846 /* We can do both TXPAUSE and RXPAUSE. */ 2847 ifr->ifr_media |= 2848 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 2849 } 2850 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 2851 } 2852 WM_CORE_UNLOCK(sc); 2853 #ifdef WM_MPSAFE 2854 s = splnet(); 2855 #endif 2856 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2857 #ifdef WM_MPSAFE 2858 splx(s); 2859 #endif 2860 break; 2861 case SIOCINITIFADDR: 2862 WM_CORE_LOCK(sc); 2863 if (ifa->ifa_addr->sa_family == AF_LINK) { 2864 sdl = satosdl(ifp->if_dl->ifa_addr); 2865 (void)sockaddr_dl_setaddr(sdl, sdl->sdl_len, 2866 LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen); 2867 /* unicast address is first multicast entry */ 2868 wm_set_filter(sc); 2869 error = 0; 2870 WM_CORE_UNLOCK(sc); 2871 break; 2872 } 2873 WM_CORE_UNLOCK(sc); 2874 /*FALLTHROUGH*/ 2875 default: 2876 #ifdef WM_MPSAFE 2877 s = splnet(); 2878 #endif 2879 /* It may call wm_start, so unlock here */ 2880 error = ether_ioctl(ifp, cmd, data); 2881 #ifdef WM_MPSAFE 2882 splx(s); 2883 #endif 2884 if (error != ENETRESET) 2885 break; 2886 2887 error = 0; 2888 2889 if (cmd == SIOCSIFCAP) { 2890 error = (*ifp->if_init)(ifp); 2891 } else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2892 ; 2893 else if (ifp->if_flags & IFF_RUNNING) { 2894 /* 2895 * Multicast list has changed; set the hardware filter 2896 * accordingly. 2897 */ 2898 WM_CORE_LOCK(sc); 2899 wm_set_filter(sc); 2900 WM_CORE_UNLOCK(sc); 2901 } 2902 break; 2903 } 2904 2905 #ifndef WM_MPSAFE 2906 splx(s); 2907 #endif 2908 return error; 2909 } 2910 2911 /* MAC address related */ 2912 2913 /* 2914 * Get the offset of MAC address and return it. 2915 * If error occured, use offset 0. 2916 */ 2917 static uint16_t 2918 wm_check_alt_mac_addr(struct wm_softc *sc) 2919 { 2920 uint16_t myea[ETHER_ADDR_LEN / 2]; 2921 uint16_t offset = NVM_OFF_MACADDR; 2922 2923 /* Try to read alternative MAC address pointer */ 2924 if (wm_nvm_read(sc, NVM_OFF_ALT_MAC_ADDR_PTR, 1, &offset) != 0) 2925 return 0; 2926 2927 /* Check pointer if it's valid or not. */ 2928 if ((offset == 0x0000) || (offset == 0xffff)) 2929 return 0; 2930 2931 offset += NVM_OFF_MACADDR_82571(sc->sc_funcid); 2932 /* 2933 * Check whether alternative MAC address is valid or not. 2934 * Some cards have non 0xffff pointer but those don't use 2935 * alternative MAC address in reality. 2936 * 2937 * Check whether the broadcast bit is set or not. 2938 */ 2939 if (wm_nvm_read(sc, offset, 1, myea) == 0) 2940 if (((myea[0] & 0xff) & 0x01) == 0) 2941 return offset; /* Found */ 2942 2943 /* Not found */ 2944 return 0; 2945 } 2946 2947 static int 2948 wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr) 2949 { 2950 uint16_t myea[ETHER_ADDR_LEN / 2]; 2951 uint16_t offset = NVM_OFF_MACADDR; 2952 int do_invert = 0; 2953 2954 switch (sc->sc_type) { 2955 case WM_T_82580: 2956 case WM_T_I350: 2957 case WM_T_I354: 2958 /* EEPROM Top Level Partitioning */ 2959 offset = NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) + 0; 2960 break; 2961 case WM_T_82571: 2962 case WM_T_82575: 2963 case WM_T_82576: 2964 case WM_T_80003: 2965 case WM_T_I210: 2966 case WM_T_I211: 2967 offset = wm_check_alt_mac_addr(sc); 2968 if (offset == 0) 2969 if ((sc->sc_funcid & 0x01) == 1) 2970 do_invert = 1; 2971 break; 2972 default: 2973 if ((sc->sc_funcid & 0x01) == 1) 2974 do_invert = 1; 2975 break; 2976 } 2977 2978 if (wm_nvm_read(sc, offset, sizeof(myea) / sizeof(myea[0]), 2979 myea) != 0) 2980 goto bad; 2981 2982 enaddr[0] = myea[0] & 0xff; 2983 enaddr[1] = myea[0] >> 8; 2984 enaddr[2] = myea[1] & 0xff; 2985 enaddr[3] = myea[1] >> 8; 2986 enaddr[4] = myea[2] & 0xff; 2987 enaddr[5] = myea[2] >> 8; 2988 2989 /* 2990 * Toggle the LSB of the MAC address on the second port 2991 * of some dual port cards. 2992 */ 2993 if (do_invert != 0) 2994 enaddr[5] ^= 1; 2995 2996 return 0; 2997 2998 bad: 2999 return -1; 3000 } 3001 3002 /* 3003 * wm_set_ral: 3004 * 3005 * Set an entery in the receive address list. 3006 */ 3007 static void 3008 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3009 { 3010 uint32_t ral_lo, ral_hi; 3011 3012 if (enaddr != NULL) { 3013 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3014 (enaddr[3] << 24); 3015 ral_hi = enaddr[4] | (enaddr[5] << 8); 3016 ral_hi |= RAL_AV; 3017 } else { 3018 ral_lo = 0; 3019 ral_hi = 0; 3020 } 3021 3022 if (sc->sc_type >= WM_T_82544) { 3023 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3024 ral_lo); 3025 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3026 ral_hi); 3027 } else { 3028 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3029 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3030 } 3031 } 3032 3033 /* 3034 * wm_mchash: 3035 * 3036 * Compute the hash of the multicast address for the 4096-bit 3037 * multicast filter. 3038 */ 3039 static uint32_t 3040 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3041 { 3042 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3043 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3044 static const int ich8_lo_shift[4] = { 6, 5, 4, 2 }; 3045 static const int ich8_hi_shift[4] = { 2, 3, 4, 6 }; 3046 uint32_t hash; 3047 3048 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 3049 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 3050 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT) 3051 || (sc->sc_type == WM_T_PCH_SPT)) { 3052 hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) | 3053 (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]); 3054 return (hash & 0x3ff); 3055 } 3056 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3057 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3058 3059 return (hash & 0xfff); 3060 } 3061 3062 /* 3063 * wm_set_filter: 3064 * 3065 * Set up the receive filter. 3066 */ 3067 static void 3068 wm_set_filter(struct wm_softc *sc) 3069 { 3070 struct ethercom *ec = &sc->sc_ethercom; 3071 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3072 struct ether_multi *enm; 3073 struct ether_multistep step; 3074 bus_addr_t mta_reg; 3075 uint32_t hash, reg, bit; 3076 int i, size, ralmax; 3077 3078 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 3079 device_xname(sc->sc_dev), __func__)); 3080 if (sc->sc_type >= WM_T_82544) 3081 mta_reg = WMREG_CORDOVA_MTA; 3082 else 3083 mta_reg = WMREG_MTA; 3084 3085 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3086 3087 if (ifp->if_flags & IFF_BROADCAST) 3088 sc->sc_rctl |= RCTL_BAM; 3089 if (ifp->if_flags & IFF_PROMISC) { 3090 sc->sc_rctl |= RCTL_UPE; 3091 goto allmulti; 3092 } 3093 3094 /* 3095 * Set the station address in the first RAL slot, and 3096 * clear the remaining slots. 3097 */ 3098 if (sc->sc_type == WM_T_ICH8) 3099 size = WM_RAL_TABSIZE_ICH8 -1; 3100 else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10) 3101 || (sc->sc_type == WM_T_PCH)) 3102 size = WM_RAL_TABSIZE_ICH8; 3103 else if (sc->sc_type == WM_T_PCH2) 3104 size = WM_RAL_TABSIZE_PCH2; 3105 else if ((sc->sc_type == WM_T_PCH_LPT) ||(sc->sc_type == WM_T_PCH_SPT)) 3106 size = WM_RAL_TABSIZE_PCH_LPT; 3107 else if (sc->sc_type == WM_T_82575) 3108 size = WM_RAL_TABSIZE_82575; 3109 else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580)) 3110 size = WM_RAL_TABSIZE_82576; 3111 else if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) 3112 size = WM_RAL_TABSIZE_I350; 3113 else 3114 size = WM_RAL_TABSIZE; 3115 wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0); 3116 3117 if ((sc->sc_type == WM_T_PCH_LPT) || (sc->sc_type == WM_T_PCH_SPT)) { 3118 i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC); 3119 switch (i) { 3120 case 0: 3121 /* We can use all entries */ 3122 ralmax = size; 3123 break; 3124 case 1: 3125 /* Only RAR[0] */ 3126 ralmax = 1; 3127 break; 3128 default: 3129 /* available SHRA + RAR[0] */ 3130 ralmax = i + 1; 3131 } 3132 } else 3133 ralmax = size; 3134 for (i = 1; i < size; i++) { 3135 if (i < ralmax) 3136 wm_set_ral(sc, NULL, i); 3137 } 3138 3139 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 3140 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 3141 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT) 3142 || (sc->sc_type == WM_T_PCH_SPT)) 3143 size = WM_ICH8_MC_TABSIZE; 3144 else 3145 size = WM_MC_TABSIZE; 3146 /* Clear out the multicast table. */ 3147 for (i = 0; i < size; i++) 3148 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3149 3150 ETHER_FIRST_MULTI(step, ec, enm); 3151 while (enm != NULL) { 3152 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3153 /* 3154 * We must listen to a range of multicast addresses. 3155 * For now, just accept all multicasts, rather than 3156 * trying to set only those filter bits needed to match 3157 * the range. (At this time, the only use of address 3158 * ranges is for IP multicast routing, for which the 3159 * range is big enough to require all bits set.) 3160 */ 3161 goto allmulti; 3162 } 3163 3164 hash = wm_mchash(sc, enm->enm_addrlo); 3165 3166 reg = (hash >> 5); 3167 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 3168 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 3169 || (sc->sc_type == WM_T_PCH2) 3170 || (sc->sc_type == WM_T_PCH_LPT) 3171 || (sc->sc_type == WM_T_PCH_SPT)) 3172 reg &= 0x1f; 3173 else 3174 reg &= 0x7f; 3175 bit = hash & 0x1f; 3176 3177 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3178 hash |= 1U << bit; 3179 3180 if (sc->sc_type == WM_T_82544 && (reg & 1) != 0) { 3181 /* 3182 * 82544 Errata 9: Certain register cannot be written 3183 * with particular alignments in PCI-X bus operation 3184 * (FCAH, MTA and VFTA). 3185 */ 3186 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3187 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3188 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3189 } else 3190 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3191 3192 ETHER_NEXT_MULTI(step, enm); 3193 } 3194 3195 ifp->if_flags &= ~IFF_ALLMULTI; 3196 goto setit; 3197 3198 allmulti: 3199 ifp->if_flags |= IFF_ALLMULTI; 3200 sc->sc_rctl |= RCTL_MPE; 3201 3202 setit: 3203 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3204 } 3205 3206 /* Reset and init related */ 3207 3208 static void 3209 wm_set_vlan(struct wm_softc *sc) 3210 { 3211 3212 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 3213 device_xname(sc->sc_dev), __func__)); 3214 /* Deal with VLAN enables. */ 3215 if (VLAN_ATTACHED(&sc->sc_ethercom)) 3216 sc->sc_ctrl |= CTRL_VME; 3217 else 3218 sc->sc_ctrl &= ~CTRL_VME; 3219 3220 /* Write the control registers. */ 3221 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3222 } 3223 3224 static void 3225 wm_set_pcie_completion_timeout(struct wm_softc *sc) 3226 { 3227 uint32_t gcr; 3228 pcireg_t ctrl2; 3229 3230 gcr = CSR_READ(sc, WMREG_GCR); 3231 3232 /* Only take action if timeout value is defaulted to 0 */ 3233 if ((gcr & GCR_CMPL_TMOUT_MASK) != 0) 3234 goto out; 3235 3236 if ((gcr & GCR_CAP_VER2) == 0) { 3237 gcr |= GCR_CMPL_TMOUT_10MS; 3238 goto out; 3239 } 3240 3241 ctrl2 = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 3242 sc->sc_pcixe_capoff + PCIE_DCSR2); 3243 ctrl2 |= WM_PCIE_DCSR2_16MS; 3244 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 3245 sc->sc_pcixe_capoff + PCIE_DCSR2, ctrl2); 3246 3247 out: 3248 /* Disable completion timeout resend */ 3249 gcr &= ~GCR_CMPL_TMOUT_RESEND; 3250 3251 CSR_WRITE(sc, WMREG_GCR, gcr); 3252 } 3253 3254 void 3255 wm_get_auto_rd_done(struct wm_softc *sc) 3256 { 3257 int i; 3258 3259 /* wait for eeprom to reload */ 3260 switch (sc->sc_type) { 3261 case WM_T_82571: 3262 case WM_T_82572: 3263 case WM_T_82573: 3264 case WM_T_82574: 3265 case WM_T_82583: 3266 case WM_T_82575: 3267 case WM_T_82576: 3268 case WM_T_82580: 3269 case WM_T_I350: 3270 case WM_T_I354: 3271 case WM_T_I210: 3272 case WM_T_I211: 3273 case WM_T_80003: 3274 case WM_T_ICH8: 3275 case WM_T_ICH9: 3276 for (i = 0; i < 10; i++) { 3277 if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD) 3278 break; 3279 delay(1000); 3280 } 3281 if (i == 10) { 3282 log(LOG_ERR, "%s: auto read from eeprom failed to " 3283 "complete\n", device_xname(sc->sc_dev)); 3284 } 3285 break; 3286 default: 3287 break; 3288 } 3289 } 3290 3291 void 3292 wm_lan_init_done(struct wm_softc *sc) 3293 { 3294 uint32_t reg = 0; 3295 int i; 3296 3297 /* wait for eeprom to reload */ 3298 switch (sc->sc_type) { 3299 case WM_T_ICH10: 3300 case WM_T_PCH: 3301 case WM_T_PCH2: 3302 case WM_T_PCH_LPT: 3303 case WM_T_PCH_SPT: 3304 for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) { 3305 reg = CSR_READ(sc, WMREG_STATUS); 3306 if ((reg & STATUS_LAN_INIT_DONE) != 0) 3307 break; 3308 delay(100); 3309 } 3310 if (i >= WM_ICH8_LAN_INIT_TIMEOUT) { 3311 log(LOG_ERR, "%s: %s: lan_init_done failed to " 3312 "complete\n", device_xname(sc->sc_dev), __func__); 3313 } 3314 break; 3315 default: 3316 panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), 3317 __func__); 3318 break; 3319 } 3320 3321 reg &= ~STATUS_LAN_INIT_DONE; 3322 CSR_WRITE(sc, WMREG_STATUS, reg); 3323 } 3324 3325 void 3326 wm_get_cfg_done(struct wm_softc *sc) 3327 { 3328 int mask; 3329 uint32_t reg; 3330 int i; 3331 3332 /* wait for eeprom to reload */ 3333 switch (sc->sc_type) { 3334 case WM_T_82542_2_0: 3335 case WM_T_82542_2_1: 3336 /* null */ 3337 break; 3338 case WM_T_82543: 3339 case WM_T_82544: 3340 case WM_T_82540: 3341 case WM_T_82545: 3342 case WM_T_82545_3: 3343 case WM_T_82546: 3344 case WM_T_82546_3: 3345 case WM_T_82541: 3346 case WM_T_82541_2: 3347 case WM_T_82547: 3348 case WM_T_82547_2: 3349 case WM_T_82573: 3350 case WM_T_82574: 3351 case WM_T_82583: 3352 /* generic */ 3353 delay(10*1000); 3354 break; 3355 case WM_T_80003: 3356 case WM_T_82571: 3357 case WM_T_82572: 3358 case WM_T_82575: 3359 case WM_T_82576: 3360 case WM_T_82580: 3361 case WM_T_I350: 3362 case WM_T_I354: 3363 case WM_T_I210: 3364 case WM_T_I211: 3365 if (sc->sc_type == WM_T_82571) { 3366 /* Only 82571 shares port 0 */ 3367 mask = EEMNGCTL_CFGDONE_0; 3368 } else 3369 mask = EEMNGCTL_CFGDONE_0 << sc->sc_funcid; 3370 for (i = 0; i < WM_PHY_CFG_TIMEOUT; i++) { 3371 if (CSR_READ(sc, WMREG_EEMNGCTL) & mask) 3372 break; 3373 delay(1000); 3374 } 3375 if (i >= WM_PHY_CFG_TIMEOUT) { 3376 DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n", 3377 device_xname(sc->sc_dev), __func__)); 3378 } 3379 break; 3380 case WM_T_ICH8: 3381 case WM_T_ICH9: 3382 case WM_T_ICH10: 3383 case WM_T_PCH: 3384 case WM_T_PCH2: 3385 case WM_T_PCH_LPT: 3386 case WM_T_PCH_SPT: 3387 delay(10*1000); 3388 if (sc->sc_type >= WM_T_ICH10) 3389 wm_lan_init_done(sc); 3390 else 3391 wm_get_auto_rd_done(sc); 3392 3393 reg = CSR_READ(sc, WMREG_STATUS); 3394 if ((reg & STATUS_PHYRA) != 0) 3395 CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA); 3396 break; 3397 default: 3398 panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), 3399 __func__); 3400 break; 3401 } 3402 } 3403 3404 /* Init hardware bits */ 3405 void 3406 wm_initialize_hardware_bits(struct wm_softc *sc) 3407 { 3408 uint32_t tarc0, tarc1, reg; 3409 3410 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 3411 device_xname(sc->sc_dev), __func__)); 3412 /* For 82571 variant, 80003 and ICHs */ 3413 if (((sc->sc_type >= WM_T_82571) && (sc->sc_type <= WM_T_82583)) 3414 || (sc->sc_type >= WM_T_80003)) { 3415 3416 /* Transmit Descriptor Control 0 */ 3417 reg = CSR_READ(sc, WMREG_TXDCTL(0)); 3418 reg |= TXDCTL_COUNT_DESC; 3419 CSR_WRITE(sc, WMREG_TXDCTL(0), reg); 3420 3421 /* Transmit Descriptor Control 1 */ 3422 reg = CSR_READ(sc, WMREG_TXDCTL(1)); 3423 reg |= TXDCTL_COUNT_DESC; 3424 CSR_WRITE(sc, WMREG_TXDCTL(1), reg); 3425 3426 /* TARC0 */ 3427 tarc0 = CSR_READ(sc, WMREG_TARC0); 3428 switch (sc->sc_type) { 3429 case WM_T_82571: 3430 case WM_T_82572: 3431 case WM_T_82573: 3432 case WM_T_82574: 3433 case WM_T_82583: 3434 case WM_T_80003: 3435 /* Clear bits 30..27 */ 3436 tarc0 &= ~__BITS(30, 27); 3437 break; 3438 default: 3439 break; 3440 } 3441 3442 switch (sc->sc_type) { 3443 case WM_T_82571: 3444 case WM_T_82572: 3445 tarc0 |= __BITS(26, 23); /* TARC0 bits 23-26 */ 3446 3447 tarc1 = CSR_READ(sc, WMREG_TARC1); 3448 tarc1 &= ~__BITS(30, 29); /* Clear bits 30 and 29 */ 3449 tarc1 |= __BITS(26, 24); /* TARC1 bits 26-24 */ 3450 /* 8257[12] Errata No.7 */ 3451 tarc1 |= __BIT(22); /* TARC1 bits 22 */ 3452 3453 /* TARC1 bit 28 */ 3454 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) 3455 tarc1 &= ~__BIT(28); 3456 else 3457 tarc1 |= __BIT(28); 3458 CSR_WRITE(sc, WMREG_TARC1, tarc1); 3459 3460 /* 3461 * 8257[12] Errata No.13 3462 * Disable Dyamic Clock Gating. 3463 */ 3464 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3465 reg &= ~CTRL_EXT_DMA_DYN_CLK; 3466 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3467 break; 3468 case WM_T_82573: 3469 case WM_T_82574: 3470 case WM_T_82583: 3471 if ((sc->sc_type == WM_T_82574) 3472 || (sc->sc_type == WM_T_82583)) 3473 tarc0 |= __BIT(26); /* TARC0 bit 26 */ 3474 3475 /* Extended Device Control */ 3476 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3477 reg &= ~__BIT(23); /* Clear bit 23 */ 3478 reg |= __BIT(22); /* Set bit 22 */ 3479 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3480 3481 /* Device Control */ 3482 sc->sc_ctrl &= ~__BIT(29); /* Clear bit 29 */ 3483 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3484 3485 /* PCIe Control Register */ 3486 /* 3487 * 82573 Errata (unknown). 3488 * 3489 * 82574 Errata 25 and 82583 Errata 12 3490 * "Dropped Rx Packets": 3491 * NVM Image Version 2.1.4 and newer has no this bug. 3492 */ 3493 reg = CSR_READ(sc, WMREG_GCR); 3494 reg |= GCR_L1_ACT_WITHOUT_L0S_RX; 3495 CSR_WRITE(sc, WMREG_GCR, reg); 3496 3497 if ((sc->sc_type == WM_T_82574) 3498 || (sc->sc_type == WM_T_82583)) { 3499 /* 3500 * Document says this bit must be set for 3501 * proper operation. 3502 */ 3503 reg = CSR_READ(sc, WMREG_GCR); 3504 reg |= __BIT(22); 3505 CSR_WRITE(sc, WMREG_GCR, reg); 3506 3507 /* 3508 * Apply workaround for hardware errata 3509 * documented in errata docs Fixes issue where 3510 * some error prone or unreliable PCIe 3511 * completions are occurring, particularly 3512 * with ASPM enabled. Without fix, issue can 3513 * cause Tx timeouts. 3514 */ 3515 reg = CSR_READ(sc, WMREG_GCR2); 3516 reg |= __BIT(0); 3517 CSR_WRITE(sc, WMREG_GCR2, reg); 3518 } 3519 break; 3520 case WM_T_80003: 3521 /* TARC0 */ 3522 if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER) 3523 || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) 3524 tarc0 &= ~__BIT(20); /* Clear bits 20 */ 3525 3526 /* TARC1 bit 28 */ 3527 tarc1 = CSR_READ(sc, WMREG_TARC1); 3528 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) 3529 tarc1 &= ~__BIT(28); 3530 else 3531 tarc1 |= __BIT(28); 3532 CSR_WRITE(sc, WMREG_TARC1, tarc1); 3533 break; 3534 case WM_T_ICH8: 3535 case WM_T_ICH9: 3536 case WM_T_ICH10: 3537 case WM_T_PCH: 3538 case WM_T_PCH2: 3539 case WM_T_PCH_LPT: 3540 case WM_T_PCH_SPT: 3541 /* TARC0 */ 3542 if ((sc->sc_type == WM_T_ICH8) 3543 || (sc->sc_type == WM_T_PCH_SPT)) { 3544 /* Set TARC0 bits 29 and 28 */ 3545 tarc0 |= __BITS(29, 28); 3546 } 3547 /* Set TARC0 bits 23,24,26,27 */ 3548 tarc0 |= __BITS(27, 26) | __BITS(24, 23); 3549 3550 /* CTRL_EXT */ 3551 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3552 reg |= __BIT(22); /* Set bit 22 */ 3553 /* 3554 * Enable PHY low-power state when MAC is at D3 3555 * w/o WoL 3556 */ 3557 if (sc->sc_type >= WM_T_PCH) 3558 reg |= CTRL_EXT_PHYPDEN; 3559 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3560 3561 /* TARC1 */ 3562 tarc1 = CSR_READ(sc, WMREG_TARC1); 3563 /* bit 28 */ 3564 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0) 3565 tarc1 &= ~__BIT(28); 3566 else 3567 tarc1 |= __BIT(28); 3568 tarc1 |= __BIT(24) | __BIT(26) | __BIT(30); 3569 CSR_WRITE(sc, WMREG_TARC1, tarc1); 3570 3571 /* Device Status */ 3572 if (sc->sc_type == WM_T_ICH8) { 3573 reg = CSR_READ(sc, WMREG_STATUS); 3574 reg &= ~__BIT(31); 3575 CSR_WRITE(sc, WMREG_STATUS, reg); 3576 3577 } 3578 3579 /* IOSFPC */ 3580 if (sc->sc_type == WM_T_PCH_SPT) { 3581 reg = CSR_READ(sc, WMREG_IOSFPC); 3582 reg |= RCTL_RDMTS_HEX; /* XXX RTCL bit? */ 3583 CSR_WRITE(sc, WMREG_IOSFPC, reg); 3584 } 3585 /* 3586 * Work-around descriptor data corruption issue during 3587 * NFS v2 UDP traffic, just disable the NFS filtering 3588 * capability. 3589 */ 3590 reg = CSR_READ(sc, WMREG_RFCTL); 3591 reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS; 3592 CSR_WRITE(sc, WMREG_RFCTL, reg); 3593 break; 3594 default: 3595 break; 3596 } 3597 CSR_WRITE(sc, WMREG_TARC0, tarc0); 3598 3599 /* 3600 * 8257[12] Errata No.52 and some others. 3601 * Avoid RSS Hash Value bug. 3602 */ 3603 switch (sc->sc_type) { 3604 case WM_T_82571: 3605 case WM_T_82572: 3606 case WM_T_82573: 3607 case WM_T_80003: 3608 case WM_T_ICH8: 3609 reg = CSR_READ(sc, WMREG_RFCTL); 3610 reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS; 3611 CSR_WRITE(sc, WMREG_RFCTL, reg); 3612 break; 3613 default: 3614 break; 3615 } 3616 } 3617 } 3618 3619 static uint32_t 3620 wm_rxpbs_adjust_82580(uint32_t val) 3621 { 3622 uint32_t rv = 0; 3623 3624 if (val < __arraycount(wm_82580_rxpbs_table)) 3625 rv = wm_82580_rxpbs_table[val]; 3626 3627 return rv; 3628 } 3629 3630 /* 3631 * wm_reset: 3632 * 3633 * Reset the i82542 chip. 3634 */ 3635 static void 3636 wm_reset(struct wm_softc *sc) 3637 { 3638 int phy_reset = 0; 3639 int i, error = 0; 3640 uint32_t reg, mask; 3641 3642 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 3643 device_xname(sc->sc_dev), __func__)); 3644 /* 3645 * Allocate on-chip memory according to the MTU size. 3646 * The Packet Buffer Allocation register must be written 3647 * before the chip is reset. 3648 */ 3649 switch (sc->sc_type) { 3650 case WM_T_82547: 3651 case WM_T_82547_2: 3652 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 3653 PBA_22K : PBA_30K; 3654 for (i = 0; i < sc->sc_ntxqueues; i++) { 3655 struct wm_txqueue *txq = &sc->sc_txq[i]; 3656 txq->txq_fifo_head = 0; 3657 txq->txq_fifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 3658 txq->txq_fifo_size = 3659 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 3660 txq->txq_fifo_stall = 0; 3661 } 3662 break; 3663 case WM_T_82571: 3664 case WM_T_82572: 3665 case WM_T_82575: /* XXX need special handing for jumbo frames */ 3666 case WM_T_80003: 3667 sc->sc_pba = PBA_32K; 3668 break; 3669 case WM_T_82573: 3670 sc->sc_pba = PBA_12K; 3671 break; 3672 case WM_T_82574: 3673 case WM_T_82583: 3674 sc->sc_pba = PBA_20K; 3675 break; 3676 case WM_T_82576: 3677 sc->sc_pba = CSR_READ(sc, WMREG_RXPBS); 3678 sc->sc_pba &= RXPBS_SIZE_MASK_82576; 3679 break; 3680 case WM_T_82580: 3681 case WM_T_I350: 3682 case WM_T_I354: 3683 sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS)); 3684 break; 3685 case WM_T_I210: 3686 case WM_T_I211: 3687 sc->sc_pba = PBA_34K; 3688 break; 3689 case WM_T_ICH8: 3690 /* Workaround for a bit corruption issue in FIFO memory */ 3691 sc->sc_pba = PBA_8K; 3692 CSR_WRITE(sc, WMREG_PBS, PBA_16K); 3693 break; 3694 case WM_T_ICH9: 3695 case WM_T_ICH10: 3696 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 4096 ? 3697 PBA_14K : PBA_10K; 3698 break; 3699 case WM_T_PCH: 3700 case WM_T_PCH2: 3701 case WM_T_PCH_LPT: 3702 case WM_T_PCH_SPT: 3703 sc->sc_pba = PBA_26K; 3704 break; 3705 default: 3706 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 3707 PBA_40K : PBA_48K; 3708 break; 3709 } 3710 /* 3711 * Only old or non-multiqueue devices have the PBA register 3712 * XXX Need special handling for 82575. 3713 */ 3714 if (((sc->sc_flags & WM_F_NEWQUEUE) == 0) 3715 || (sc->sc_type == WM_T_82575)) 3716 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 3717 3718 /* Prevent the PCI-E bus from sticking */ 3719 if (sc->sc_flags & WM_F_PCIE) { 3720 int timeout = 800; 3721 3722 sc->sc_ctrl |= CTRL_GIO_M_DIS; 3723 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3724 3725 while (timeout--) { 3726 if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA) 3727 == 0) 3728 break; 3729 delay(100); 3730 } 3731 } 3732 3733 /* Set the completion timeout for interface */ 3734 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) 3735 || (sc->sc_type == WM_T_82580) 3736 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) 3737 || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) 3738 wm_set_pcie_completion_timeout(sc); 3739 3740 /* Clear interrupt */ 3741 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3742 if (sc->sc_nintrs > 1) { 3743 if (sc->sc_type != WM_T_82574) { 3744 CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); 3745 CSR_WRITE(sc, WMREG_EIAC, 0); 3746 } else { 3747 CSR_WRITE(sc, WMREG_EIAC_82574, 0); 3748 } 3749 } 3750 3751 /* Stop the transmit and receive processes. */ 3752 CSR_WRITE(sc, WMREG_RCTL, 0); 3753 sc->sc_rctl &= ~RCTL_EN; 3754 CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP); 3755 CSR_WRITE_FLUSH(sc); 3756 3757 /* XXX set_tbi_sbp_82543() */ 3758 3759 delay(10*1000); 3760 3761 /* Must acquire the MDIO ownership before MAC reset */ 3762 switch (sc->sc_type) { 3763 case WM_T_82573: 3764 case WM_T_82574: 3765 case WM_T_82583: 3766 error = wm_get_hw_semaphore_82573(sc); 3767 break; 3768 default: 3769 break; 3770 } 3771 3772 /* 3773 * 82541 Errata 29? & 82547 Errata 28? 3774 * See also the description about PHY_RST bit in CTRL register 3775 * in 8254x_GBe_SDM.pdf. 3776 */ 3777 if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) { 3778 CSR_WRITE(sc, WMREG_CTRL, 3779 CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET); 3780 CSR_WRITE_FLUSH(sc); 3781 delay(5000); 3782 } 3783 3784 switch (sc->sc_type) { 3785 case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */ 3786 case WM_T_82541: 3787 case WM_T_82541_2: 3788 case WM_T_82547: 3789 case WM_T_82547_2: 3790 /* 3791 * On some chipsets, a reset through a memory-mapped write 3792 * cycle can cause the chip to reset before completing the 3793 * write cycle. This causes major headache that can be 3794 * avoided by issuing the reset via indirect register writes 3795 * through I/O space. 3796 * 3797 * So, if we successfully mapped the I/O BAR at attach time, 3798 * use that. Otherwise, try our luck with a memory-mapped 3799 * reset. 3800 */ 3801 if (sc->sc_flags & WM_F_IOH_VALID) 3802 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 3803 else 3804 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 3805 break; 3806 case WM_T_82545_3: 3807 case WM_T_82546_3: 3808 /* Use the shadow control register on these chips. */ 3809 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 3810 break; 3811 case WM_T_80003: 3812 mask = swfwphysem[sc->sc_funcid]; 3813 reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST; 3814 wm_get_swfw_semaphore(sc, mask); 3815 CSR_WRITE(sc, WMREG_CTRL, reg); 3816 wm_put_swfw_semaphore(sc, mask); 3817 break; 3818 case WM_T_ICH8: 3819 case WM_T_ICH9: 3820 case WM_T_ICH10: 3821 case WM_T_PCH: 3822 case WM_T_PCH2: 3823 case WM_T_PCH_LPT: 3824 case WM_T_PCH_SPT: 3825 reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST; 3826 if (wm_phy_resetisblocked(sc) == false) { 3827 /* 3828 * Gate automatic PHY configuration by hardware on 3829 * non-managed 82579 3830 */ 3831 if ((sc->sc_type == WM_T_PCH2) 3832 && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) 3833 == 0)) 3834 wm_gate_hw_phy_config_ich8lan(sc, true); 3835 3836 reg |= CTRL_PHY_RESET; 3837 phy_reset = 1; 3838 } else 3839 printf("XXX reset is blocked!!!\n"); 3840 wm_get_swfwhw_semaphore(sc); 3841 CSR_WRITE(sc, WMREG_CTRL, reg); 3842 /* Don't insert a completion barrier when reset */ 3843 delay(20*1000); 3844 wm_put_swfwhw_semaphore(sc); 3845 break; 3846 case WM_T_82580: 3847 case WM_T_I350: 3848 case WM_T_I354: 3849 case WM_T_I210: 3850 case WM_T_I211: 3851 CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST); 3852 if (sc->sc_pcidevid != PCI_PRODUCT_INTEL_DH89XXCC_SGMII) 3853 CSR_WRITE_FLUSH(sc); 3854 delay(5000); 3855 break; 3856 case WM_T_82542_2_0: 3857 case WM_T_82542_2_1: 3858 case WM_T_82543: 3859 case WM_T_82540: 3860 case WM_T_82545: 3861 case WM_T_82546: 3862 case WM_T_82571: 3863 case WM_T_82572: 3864 case WM_T_82573: 3865 case WM_T_82574: 3866 case WM_T_82575: 3867 case WM_T_82576: 3868 case WM_T_82583: 3869 default: 3870 /* Everything else can safely use the documented method. */ 3871 CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST); 3872 break; 3873 } 3874 3875 /* Must release the MDIO ownership after MAC reset */ 3876 switch (sc->sc_type) { 3877 case WM_T_82573: 3878 case WM_T_82574: 3879 case WM_T_82583: 3880 if (error == 0) 3881 wm_put_hw_semaphore_82573(sc); 3882 break; 3883 default: 3884 break; 3885 } 3886 3887 if (phy_reset != 0) 3888 wm_get_cfg_done(sc); 3889 3890 /* reload EEPROM */ 3891 switch (sc->sc_type) { 3892 case WM_T_82542_2_0: 3893 case WM_T_82542_2_1: 3894 case WM_T_82543: 3895 case WM_T_82544: 3896 delay(10); 3897 reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST; 3898 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3899 CSR_WRITE_FLUSH(sc); 3900 delay(2000); 3901 break; 3902 case WM_T_82540: 3903 case WM_T_82545: 3904 case WM_T_82545_3: 3905 case WM_T_82546: 3906 case WM_T_82546_3: 3907 delay(5*1000); 3908 /* XXX Disable HW ARPs on ASF enabled adapters */ 3909 break; 3910 case WM_T_82541: 3911 case WM_T_82541_2: 3912 case WM_T_82547: 3913 case WM_T_82547_2: 3914 delay(20000); 3915 /* XXX Disable HW ARPs on ASF enabled adapters */ 3916 break; 3917 case WM_T_82571: 3918 case WM_T_82572: 3919 case WM_T_82573: 3920 case WM_T_82574: 3921 case WM_T_82583: 3922 if (sc->sc_flags & WM_F_EEPROM_FLASH) { 3923 delay(10); 3924 reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST; 3925 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3926 CSR_WRITE_FLUSH(sc); 3927 } 3928 /* check EECD_EE_AUTORD */ 3929 wm_get_auto_rd_done(sc); 3930 /* 3931 * Phy configuration from NVM just starts after EECD_AUTO_RD 3932 * is set. 3933 */ 3934 if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574) 3935 || (sc->sc_type == WM_T_82583)) 3936 delay(25*1000); 3937 break; 3938 case WM_T_82575: 3939 case WM_T_82576: 3940 case WM_T_82580: 3941 case WM_T_I350: 3942 case WM_T_I354: 3943 case WM_T_I210: 3944 case WM_T_I211: 3945 case WM_T_80003: 3946 /* check EECD_EE_AUTORD */ 3947 wm_get_auto_rd_done(sc); 3948 break; 3949 case WM_T_ICH8: 3950 case WM_T_ICH9: 3951 case WM_T_ICH10: 3952 case WM_T_PCH: 3953 case WM_T_PCH2: 3954 case WM_T_PCH_LPT: 3955 case WM_T_PCH_SPT: 3956 break; 3957 default: 3958 panic("%s: unknown type\n", __func__); 3959 } 3960 3961 /* Check whether EEPROM is present or not */ 3962 switch (sc->sc_type) { 3963 case WM_T_82575: 3964 case WM_T_82576: 3965 case WM_T_82580: 3966 case WM_T_I350: 3967 case WM_T_I354: 3968 case WM_T_ICH8: 3969 case WM_T_ICH9: 3970 if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) { 3971 /* Not found */ 3972 sc->sc_flags |= WM_F_EEPROM_INVALID; 3973 if (sc->sc_type == WM_T_82575) 3974 wm_reset_init_script_82575(sc); 3975 } 3976 break; 3977 default: 3978 break; 3979 } 3980 3981 if ((sc->sc_type == WM_T_82580) 3982 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) { 3983 /* clear global device reset status bit */ 3984 CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET); 3985 } 3986 3987 /* Clear any pending interrupt events. */ 3988 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 3989 reg = CSR_READ(sc, WMREG_ICR); 3990 if (sc->sc_nintrs > 1) { 3991 if (sc->sc_type != WM_T_82574) { 3992 CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); 3993 CSR_WRITE(sc, WMREG_EIAC, 0); 3994 } else 3995 CSR_WRITE(sc, WMREG_EIAC_82574, 0); 3996 } 3997 3998 /* reload sc_ctrl */ 3999 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL); 4000 4001 if ((sc->sc_type >= WM_T_I350) && (sc->sc_type <= WM_T_I211)) 4002 wm_set_eee_i350(sc); 4003 4004 /* dummy read from WUC */ 4005 if (sc->sc_type == WM_T_PCH) 4006 reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC); 4007 /* 4008 * For PCH, this write will make sure that any noise will be detected 4009 * as a CRC error and be dropped rather than show up as a bad packet 4010 * to the DMA engine 4011 */ 4012 if (sc->sc_type == WM_T_PCH) 4013 CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565); 4014 4015 if (sc->sc_type >= WM_T_82544) 4016 CSR_WRITE(sc, WMREG_WUC, 0); 4017 4018 wm_reset_mdicnfg_82580(sc); 4019 4020 if ((sc->sc_flags & WM_F_PLL_WA_I210) != 0) 4021 wm_pll_workaround_i210(sc); 4022 } 4023 4024 /* 4025 * wm_add_rxbuf: 4026 * 4027 * Add a receive buffer to the indiciated descriptor. 4028 */ 4029 static int 4030 wm_add_rxbuf(struct wm_rxqueue *rxq, int idx) 4031 { 4032 struct wm_softc *sc = rxq->rxq_sc; 4033 struct wm_rxsoft *rxs = &rxq->rxq_soft[idx]; 4034 struct mbuf *m; 4035 int error; 4036 4037 KASSERT(WM_RX_LOCKED(rxq)); 4038 4039 MGETHDR(m, M_DONTWAIT, MT_DATA); 4040 if (m == NULL) 4041 return ENOBUFS; 4042 4043 MCLGET(m, M_DONTWAIT); 4044 if ((m->m_flags & M_EXT) == 0) { 4045 m_freem(m); 4046 return ENOBUFS; 4047 } 4048 4049 if (rxs->rxs_mbuf != NULL) 4050 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 4051 4052 rxs->rxs_mbuf = m; 4053 4054 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 4055 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 4056 BUS_DMA_READ | BUS_DMA_NOWAIT); 4057 if (error) { 4058 /* XXX XXX XXX */ 4059 aprint_error_dev(sc->sc_dev, 4060 "unable to load rx DMA map %d, error = %d\n", 4061 idx, error); 4062 panic("wm_add_rxbuf"); 4063 } 4064 4065 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 4066 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 4067 4068 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 4069 if ((sc->sc_rctl & RCTL_EN) != 0) 4070 wm_init_rxdesc(rxq, idx); 4071 } else 4072 wm_init_rxdesc(rxq, idx); 4073 4074 return 0; 4075 } 4076 4077 /* 4078 * wm_rxdrain: 4079 * 4080 * Drain the receive queue. 4081 */ 4082 static void 4083 wm_rxdrain(struct wm_rxqueue *rxq) 4084 { 4085 struct wm_softc *sc = rxq->rxq_sc; 4086 struct wm_rxsoft *rxs; 4087 int i; 4088 4089 KASSERT(WM_RX_LOCKED(rxq)); 4090 4091 for (i = 0; i < WM_NRXDESC; i++) { 4092 rxs = &rxq->rxq_soft[i]; 4093 if (rxs->rxs_mbuf != NULL) { 4094 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 4095 m_freem(rxs->rxs_mbuf); 4096 rxs->rxs_mbuf = NULL; 4097 } 4098 } 4099 } 4100 4101 4102 /* 4103 * XXX copy from FreeBSD's sys/net/rss_config.c 4104 */ 4105 /* 4106 * RSS secret key, intended to prevent attacks on load-balancing. Its 4107 * effectiveness may be limited by algorithm choice and available entropy 4108 * during the boot. 4109 * 4110 * XXXRW: And that we don't randomize it yet! 4111 * 4112 * This is the default Microsoft RSS specification key which is also 4113 * the Chelsio T5 firmware default key. 4114 */ 4115 #define RSS_KEYSIZE 40 4116 static uint8_t wm_rss_key[RSS_KEYSIZE] = { 4117 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 4118 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 4119 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4, 4120 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c, 4121 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa, 4122 }; 4123 4124 /* 4125 * Caller must pass an array of size sizeof(rss_key). 4126 * 4127 * XXX 4128 * As if_ixgbe may use this function, this function should not be 4129 * if_wm specific function. 4130 */ 4131 static void 4132 wm_rss_getkey(uint8_t *key) 4133 { 4134 4135 memcpy(key, wm_rss_key, sizeof(wm_rss_key)); 4136 } 4137 4138 /* 4139 * Setup registers for RSS. 4140 * 4141 * XXX not yet VMDq support 4142 */ 4143 static void 4144 wm_init_rss(struct wm_softc *sc) 4145 { 4146 uint32_t mrqc, reta_reg, rss_key[RSSRK_NUM_REGS]; 4147 int i; 4148 4149 CTASSERT(sizeof(rss_key) == sizeof(wm_rss_key)); 4150 4151 for (i = 0; i < RETA_NUM_ENTRIES; i++) { 4152 int qid, reta_ent; 4153 4154 qid = i % sc->sc_nrxqueues; 4155 switch(sc->sc_type) { 4156 case WM_T_82574: 4157 reta_ent = __SHIFTIN(qid, 4158 RETA_ENT_QINDEX_MASK_82574); 4159 break; 4160 case WM_T_82575: 4161 reta_ent = __SHIFTIN(qid, 4162 RETA_ENT_QINDEX1_MASK_82575); 4163 break; 4164 default: 4165 reta_ent = __SHIFTIN(qid, RETA_ENT_QINDEX_MASK); 4166 break; 4167 } 4168 4169 reta_reg = CSR_READ(sc, WMREG_RETA_Q(i)); 4170 reta_reg &= ~RETA_ENTRY_MASK_Q(i); 4171 reta_reg |= __SHIFTIN(reta_ent, RETA_ENTRY_MASK_Q(i)); 4172 CSR_WRITE(sc, WMREG_RETA_Q(i), reta_reg); 4173 } 4174 4175 wm_rss_getkey((uint8_t *)rss_key); 4176 for (i = 0; i < RSSRK_NUM_REGS; i++) 4177 CSR_WRITE(sc, WMREG_RSSRK(i), rss_key[i]); 4178 4179 if (sc->sc_type == WM_T_82574) 4180 mrqc = MRQC_ENABLE_RSS_MQ_82574; 4181 else 4182 mrqc = MRQC_ENABLE_RSS_MQ; 4183 4184 /* XXXX 4185 * The same as FreeBSD igb. 4186 * Why doesn't use MRQC_RSS_FIELD_IPV6_EX? 4187 */ 4188 mrqc |= (MRQC_RSS_FIELD_IPV4 | MRQC_RSS_FIELD_IPV4_TCP); 4189 mrqc |= (MRQC_RSS_FIELD_IPV6 | MRQC_RSS_FIELD_IPV6_TCP); 4190 mrqc |= (MRQC_RSS_FIELD_IPV4_UDP | MRQC_RSS_FIELD_IPV6_UDP); 4191 mrqc |= (MRQC_RSS_FIELD_IPV6_UDP_EX | MRQC_RSS_FIELD_IPV6_TCP_EX); 4192 4193 CSR_WRITE(sc, WMREG_MRQC, mrqc); 4194 } 4195 4196 /* 4197 * Adjust TX and RX queue numbers which the system actulally uses. 4198 * 4199 * The numbers are affected by below parameters. 4200 * - The nubmer of hardware queues 4201 * - The number of MSI-X vectors (= "nvectors" argument) 4202 * - ncpu 4203 */ 4204 static void 4205 wm_adjust_qnum(struct wm_softc *sc, int nvectors) 4206 { 4207 int hw_ntxqueues, hw_nrxqueues; 4208 4209 if (nvectors < 3) { 4210 sc->sc_ntxqueues = 1; 4211 sc->sc_nrxqueues = 1; 4212 return; 4213 } 4214 4215 switch(sc->sc_type) { 4216 case WM_T_82572: 4217 hw_ntxqueues = 2; 4218 hw_nrxqueues = 2; 4219 break; 4220 case WM_T_82574: 4221 hw_ntxqueues = 2; 4222 hw_nrxqueues = 2; 4223 break; 4224 case WM_T_82575: 4225 hw_ntxqueues = 4; 4226 hw_nrxqueues = 4; 4227 break; 4228 case WM_T_82576: 4229 hw_ntxqueues = 16; 4230 hw_nrxqueues = 16; 4231 break; 4232 case WM_T_82580: 4233 case WM_T_I350: 4234 case WM_T_I354: 4235 hw_ntxqueues = 8; 4236 hw_nrxqueues = 8; 4237 break; 4238 case WM_T_I210: 4239 hw_ntxqueues = 4; 4240 hw_nrxqueues = 4; 4241 break; 4242 case WM_T_I211: 4243 hw_ntxqueues = 2; 4244 hw_nrxqueues = 2; 4245 break; 4246 /* 4247 * As below ethernet controllers does not support MSI-X, 4248 * this driver let them not use multiqueue. 4249 * - WM_T_80003 4250 * - WM_T_ICH8 4251 * - WM_T_ICH9 4252 * - WM_T_ICH10 4253 * - WM_T_PCH 4254 * - WM_T_PCH2 4255 * - WM_T_PCH_LPT 4256 */ 4257 default: 4258 hw_ntxqueues = 1; 4259 hw_nrxqueues = 1; 4260 break; 4261 } 4262 4263 /* 4264 * As queues more then MSI-X vectors cannot improve scaling, we limit 4265 * the number of queues used actually. 4266 * 4267 * XXX 4268 * Currently, we separate TX queue interrupts and RX queue interrupts. 4269 * Howerver, the number of MSI-X vectors of recent controllers (such as 4270 * I354) expects that drivers bundle a TX queue interrupt and a RX 4271 * interrupt to one interrupt. e.g. FreeBSD's igb deals interrupts in 4272 * such a way. 4273 */ 4274 if (nvectors < hw_ntxqueues + hw_nrxqueues + 1) { 4275 sc->sc_ntxqueues = (nvectors - 1) / 2; 4276 sc->sc_nrxqueues = (nvectors - 1) / 2; 4277 } else { 4278 sc->sc_ntxqueues = hw_ntxqueues; 4279 sc->sc_nrxqueues = hw_nrxqueues; 4280 } 4281 4282 /* 4283 * As queues more then cpus cannot improve scaling, we limit 4284 * the number of queues used actually. 4285 */ 4286 if (ncpu < sc->sc_ntxqueues) 4287 sc->sc_ntxqueues = ncpu; 4288 if (ncpu < sc->sc_nrxqueues) 4289 sc->sc_nrxqueues = ncpu; 4290 4291 /* XXX Currently, this driver supports RX multiqueue only. */ 4292 sc->sc_ntxqueues = 1; 4293 } 4294 4295 /* 4296 * Both single interrupt MSI and INTx can use this function. 4297 */ 4298 static int 4299 wm_setup_legacy(struct wm_softc *sc) 4300 { 4301 pci_chipset_tag_t pc = sc->sc_pc; 4302 const char *intrstr = NULL; 4303 char intrbuf[PCI_INTRSTR_LEN]; 4304 int error; 4305 4306 error = wm_alloc_txrx_queues(sc); 4307 if (error) { 4308 aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n", 4309 error); 4310 return ENOMEM; 4311 } 4312 intrstr = pci_intr_string(pc, sc->sc_intrs[0], intrbuf, 4313 sizeof(intrbuf)); 4314 #ifdef WM_MPSAFE 4315 pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true); 4316 #endif 4317 sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0], 4318 IPL_NET, wm_intr_legacy, sc, device_xname(sc->sc_dev)); 4319 if (sc->sc_ihs[0] == NULL) { 4320 aprint_error_dev(sc->sc_dev,"unable to establish %s\n", 4321 (pci_intr_type(sc->sc_intrs[0]) 4322 == PCI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 4323 return ENOMEM; 4324 } 4325 4326 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 4327 sc->sc_nintrs = 1; 4328 return 0; 4329 } 4330 4331 static int 4332 wm_setup_msix(struct wm_softc *sc) 4333 { 4334 void *vih; 4335 kcpuset_t *affinity; 4336 int qidx, error, intr_idx, tx_established, rx_established; 4337 pci_chipset_tag_t pc = sc->sc_pc; 4338 const char *intrstr = NULL; 4339 char intrbuf[PCI_INTRSTR_LEN]; 4340 char intr_xname[INTRDEVNAMEBUF]; 4341 /* 4342 * To avoid other devices' interrupts, the affinity of Tx/Rx interrupts 4343 * start from CPU#1. 4344 */ 4345 int affinity_offset = 1; 4346 4347 error = wm_alloc_txrx_queues(sc); 4348 if (error) { 4349 aprint_error_dev(sc->sc_dev, "cannot allocate queues %d\n", 4350 error); 4351 return ENOMEM; 4352 } 4353 4354 kcpuset_create(&affinity, false); 4355 intr_idx = 0; 4356 4357 /* 4358 * TX 4359 */ 4360 tx_established = 0; 4361 for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) { 4362 struct wm_txqueue *txq = &sc->sc_txq[qidx]; 4363 int affinity_to = (affinity_offset + intr_idx) % ncpu; 4364 4365 intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf, 4366 sizeof(intrbuf)); 4367 #ifdef WM_MPSAFE 4368 pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], 4369 PCI_INTR_MPSAFE, true); 4370 #endif 4371 memset(intr_xname, 0, sizeof(intr_xname)); 4372 snprintf(intr_xname, sizeof(intr_xname), "%sTX%d", 4373 device_xname(sc->sc_dev), qidx); 4374 vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx], 4375 IPL_NET, wm_txintr_msix, txq, intr_xname); 4376 if (vih == NULL) { 4377 aprint_error_dev(sc->sc_dev, 4378 "unable to establish MSI-X(for TX)%s%s\n", 4379 intrstr ? " at " : "", 4380 intrstr ? intrstr : ""); 4381 4382 goto fail_0; 4383 } 4384 kcpuset_zero(affinity); 4385 /* Round-robin affinity */ 4386 kcpuset_set(affinity, affinity_to); 4387 error = interrupt_distribute(vih, affinity, NULL); 4388 if (error == 0) { 4389 aprint_normal_dev(sc->sc_dev, 4390 "for TX interrupting at %s affinity to %u\n", 4391 intrstr, affinity_to); 4392 } else { 4393 aprint_normal_dev(sc->sc_dev, 4394 "for TX interrupting at %s\n", intrstr); 4395 } 4396 sc->sc_ihs[intr_idx] = vih; 4397 txq->txq_id = qidx; 4398 txq->txq_intr_idx = intr_idx; 4399 4400 tx_established++; 4401 intr_idx++; 4402 } 4403 4404 /* 4405 * RX 4406 */ 4407 rx_established = 0; 4408 for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) { 4409 struct wm_rxqueue *rxq = &sc->sc_rxq[qidx]; 4410 int affinity_to = (affinity_offset + intr_idx) % ncpu; 4411 4412 intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf, 4413 sizeof(intrbuf)); 4414 #ifdef WM_MPSAFE 4415 pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], 4416 PCI_INTR_MPSAFE, true); 4417 #endif 4418 memset(intr_xname, 0, sizeof(intr_xname)); 4419 snprintf(intr_xname, sizeof(intr_xname), "%sRX%d", 4420 device_xname(sc->sc_dev), qidx); 4421 vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx], 4422 IPL_NET, wm_rxintr_msix, rxq, intr_xname); 4423 if (vih == NULL) { 4424 aprint_error_dev(sc->sc_dev, 4425 "unable to establish MSI-X(for RX)%s%s\n", 4426 intrstr ? " at " : "", 4427 intrstr ? intrstr : ""); 4428 4429 goto fail_1; 4430 } 4431 kcpuset_zero(affinity); 4432 /* Round-robin affinity */ 4433 kcpuset_set(affinity, affinity_to); 4434 error = interrupt_distribute(vih, affinity, NULL); 4435 if (error == 0) { 4436 aprint_normal_dev(sc->sc_dev, 4437 "for RX interrupting at %s affinity to %u\n", 4438 intrstr, affinity_to); 4439 } else { 4440 aprint_normal_dev(sc->sc_dev, 4441 "for RX interrupting at %s\n", intrstr); 4442 } 4443 sc->sc_ihs[intr_idx] = vih; 4444 rxq->rxq_id = qidx; 4445 rxq->rxq_intr_idx = intr_idx; 4446 4447 rx_established++; 4448 intr_idx++; 4449 } 4450 4451 /* 4452 * LINK 4453 */ 4454 intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf, 4455 sizeof(intrbuf)); 4456 #ifdef WM_MPSAFE 4457 pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], PCI_INTR_MPSAFE, true); 4458 #endif 4459 memset(intr_xname, 0, sizeof(intr_xname)); 4460 snprintf(intr_xname, sizeof(intr_xname), "%sLINK", 4461 device_xname(sc->sc_dev)); 4462 vih = pci_intr_establish_xname(pc, sc->sc_intrs[intr_idx], 4463 IPL_NET, wm_linkintr_msix, sc, intr_xname); 4464 if (vih == NULL) { 4465 aprint_error_dev(sc->sc_dev, 4466 "unable to establish MSI-X(for LINK)%s%s\n", 4467 intrstr ? " at " : "", 4468 intrstr ? intrstr : ""); 4469 4470 goto fail_1; 4471 } 4472 /* keep default affinity to LINK interrupt */ 4473 aprint_normal_dev(sc->sc_dev, 4474 "for LINK interrupting at %s\n", intrstr); 4475 sc->sc_ihs[intr_idx] = vih; 4476 sc->sc_link_intr_idx = intr_idx; 4477 4478 sc->sc_nintrs = sc->sc_ntxqueues + sc->sc_nrxqueues + 1; 4479 kcpuset_destroy(affinity); 4480 return 0; 4481 4482 fail_1: 4483 for (qidx = 0; qidx < rx_established; qidx++) { 4484 struct wm_rxqueue *rxq = &sc->sc_rxq[qidx]; 4485 pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[rxq->rxq_intr_idx]); 4486 sc->sc_ihs[rxq->rxq_intr_idx] = NULL; 4487 } 4488 fail_0: 4489 for (qidx = 0; qidx < tx_established; qidx++) { 4490 struct wm_txqueue *txq = &sc->sc_txq[qidx]; 4491 pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[txq->txq_intr_idx]); 4492 sc->sc_ihs[txq->txq_intr_idx] = NULL; 4493 } 4494 4495 kcpuset_destroy(affinity); 4496 return ENOMEM; 4497 } 4498 4499 /* 4500 * wm_init: [ifnet interface function] 4501 * 4502 * Initialize the interface. 4503 */ 4504 static int 4505 wm_init(struct ifnet *ifp) 4506 { 4507 struct wm_softc *sc = ifp->if_softc; 4508 int ret; 4509 4510 WM_CORE_LOCK(sc); 4511 ret = wm_init_locked(ifp); 4512 WM_CORE_UNLOCK(sc); 4513 4514 return ret; 4515 } 4516 4517 static int 4518 wm_init_locked(struct ifnet *ifp) 4519 { 4520 struct wm_softc *sc = ifp->if_softc; 4521 int i, j, trynum, error = 0; 4522 uint32_t reg; 4523 4524 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 4525 device_xname(sc->sc_dev), __func__)); 4526 KASSERT(WM_CORE_LOCKED(sc)); 4527 /* 4528 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 4529 * There is a small but measurable benefit to avoiding the adjusment 4530 * of the descriptor so that the headers are aligned, for normal mtu, 4531 * on such platforms. One possibility is that the DMA itself is 4532 * slightly more efficient if the front of the entire packet (instead 4533 * of the front of the headers) is aligned. 4534 * 4535 * Note we must always set align_tweak to 0 if we are using 4536 * jumbo frames. 4537 */ 4538 #ifdef __NO_STRICT_ALIGNMENT 4539 sc->sc_align_tweak = 0; 4540 #else 4541 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 4542 sc->sc_align_tweak = 0; 4543 else 4544 sc->sc_align_tweak = 2; 4545 #endif /* __NO_STRICT_ALIGNMENT */ 4546 4547 /* Cancel any pending I/O. */ 4548 wm_stop_locked(ifp, 0); 4549 4550 /* update statistics before reset */ 4551 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 4552 ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); 4553 4554 /* Reset the chip to a known state. */ 4555 wm_reset(sc); 4556 4557 switch (sc->sc_type) { 4558 case WM_T_82571: 4559 case WM_T_82572: 4560 case WM_T_82573: 4561 case WM_T_82574: 4562 case WM_T_82583: 4563 case WM_T_80003: 4564 case WM_T_ICH8: 4565 case WM_T_ICH9: 4566 case WM_T_ICH10: 4567 case WM_T_PCH: 4568 case WM_T_PCH2: 4569 case WM_T_PCH_LPT: 4570 case WM_T_PCH_SPT: 4571 /* AMT based hardware can now take control from firmware */ 4572 if ((sc->sc_flags & WM_F_HAS_AMT) != 0) 4573 wm_get_hw_control(sc); 4574 break; 4575 default: 4576 break; 4577 } 4578 4579 /* Init hardware bits */ 4580 wm_initialize_hardware_bits(sc); 4581 4582 /* Reset the PHY. */ 4583 if (sc->sc_flags & WM_F_HAS_MII) 4584 wm_gmii_reset(sc); 4585 4586 /* Calculate (E)ITR value */ 4587 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 4588 sc->sc_itr = 450; /* For EITR */ 4589 } else if (sc->sc_type >= WM_T_82543) { 4590 /* 4591 * Set up the interrupt throttling register (units of 256ns) 4592 * Note that a footnote in Intel's documentation says this 4593 * ticker runs at 1/4 the rate when the chip is in 100Mbit 4594 * or 10Mbit mode. Empirically, it appears to be the case 4595 * that that is also true for the 1024ns units of the other 4596 * interrupt-related timer registers -- so, really, we ought 4597 * to divide this value by 4 when the link speed is low. 4598 * 4599 * XXX implement this division at link speed change! 4600 */ 4601 4602 /* 4603 * For N interrupts/sec, set this value to: 4604 * 1000000000 / (N * 256). Note that we set the 4605 * absolute and packet timer values to this value 4606 * divided by 4 to get "simple timer" behavior. 4607 */ 4608 4609 sc->sc_itr = 1500; /* 2604 ints/sec */ 4610 } 4611 4612 error = wm_init_txrx_queues(sc); 4613 if (error) 4614 goto out; 4615 4616 /* 4617 * Clear out the VLAN table -- we don't use it (yet). 4618 */ 4619 CSR_WRITE(sc, WMREG_VET, 0); 4620 if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) 4621 trynum = 10; /* Due to hw errata */ 4622 else 4623 trynum = 1; 4624 for (i = 0; i < WM_VLAN_TABSIZE; i++) 4625 for (j = 0; j < trynum; j++) 4626 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 4627 4628 /* 4629 * Set up flow-control parameters. 4630 * 4631 * XXX Values could probably stand some tuning. 4632 */ 4633 if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9) 4634 && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH) 4635 && (sc->sc_type != WM_T_PCH2) && (sc->sc_type != WM_T_PCH_LPT) 4636 && (sc->sc_type != WM_T_PCH_SPT)) { 4637 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 4638 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 4639 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 4640 } 4641 4642 sc->sc_fcrtl = FCRTL_DFLT; 4643 if (sc->sc_type < WM_T_82543) { 4644 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 4645 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 4646 } else { 4647 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 4648 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 4649 } 4650 4651 if (sc->sc_type == WM_T_80003) 4652 CSR_WRITE(sc, WMREG_FCTTV, 0xffff); 4653 else 4654 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 4655 4656 /* Writes the control register. */ 4657 wm_set_vlan(sc); 4658 4659 if (sc->sc_flags & WM_F_HAS_MII) { 4660 int val; 4661 4662 switch (sc->sc_type) { 4663 case WM_T_80003: 4664 case WM_T_ICH8: 4665 case WM_T_ICH9: 4666 case WM_T_ICH10: 4667 case WM_T_PCH: 4668 case WM_T_PCH2: 4669 case WM_T_PCH_LPT: 4670 case WM_T_PCH_SPT: 4671 /* 4672 * Set the mac to wait the maximum time between each 4673 * iteration and increase the max iterations when 4674 * polling the phy; this fixes erroneous timeouts at 4675 * 10Mbps. 4676 */ 4677 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS, 4678 0xFFFF); 4679 val = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM); 4680 val |= 0x3F; 4681 wm_kmrn_writereg(sc, 4682 KUMCTRLSTA_OFFSET_INB_PARAM, val); 4683 break; 4684 default: 4685 break; 4686 } 4687 4688 if (sc->sc_type == WM_T_80003) { 4689 val = CSR_READ(sc, WMREG_CTRL_EXT); 4690 val &= ~CTRL_EXT_LINK_MODE_MASK; 4691 CSR_WRITE(sc, WMREG_CTRL_EXT, val); 4692 4693 /* Bypass RX and TX FIFO's */ 4694 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL, 4695 KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 4696 | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 4697 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL, 4698 KUMCTRLSTA_INB_CTRL_DIS_PADDING | 4699 KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT); 4700 } 4701 } 4702 #if 0 4703 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 4704 #endif 4705 4706 /* Set up checksum offload parameters. */ 4707 reg = CSR_READ(sc, WMREG_RXCSUM); 4708 reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL); 4709 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 4710 reg |= RXCSUM_IPOFL; 4711 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 4712 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 4713 if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) 4714 reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL; 4715 CSR_WRITE(sc, WMREG_RXCSUM, reg); 4716 4717 /* Set up MSI-X */ 4718 if (sc->sc_nintrs > 1) { 4719 uint32_t ivar; 4720 struct wm_txqueue *txq; 4721 struct wm_rxqueue *rxq; 4722 int qid; 4723 4724 if (sc->sc_type == WM_T_82575) { 4725 /* Interrupt control */ 4726 reg = CSR_READ(sc, WMREG_CTRL_EXT); 4727 reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR; 4728 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 4729 4730 /* TX */ 4731 for (i = 0; i < sc->sc_ntxqueues; i++) { 4732 txq = &sc->sc_txq[i]; 4733 CSR_WRITE(sc, WMREG_MSIXBM(txq->txq_intr_idx), 4734 EITR_TX_QUEUE(txq->txq_id)); 4735 } 4736 /* RX */ 4737 for (i = 0; i < sc->sc_nrxqueues; i++) { 4738 rxq = &sc->sc_rxq[i]; 4739 CSR_WRITE(sc, WMREG_MSIXBM(rxq->rxq_intr_idx), 4740 EITR_RX_QUEUE(rxq->rxq_id)); 4741 } 4742 /* Link status */ 4743 CSR_WRITE(sc, WMREG_MSIXBM(sc->sc_link_intr_idx), 4744 EITR_OTHER); 4745 } else if (sc->sc_type == WM_T_82574) { 4746 /* Interrupt control */ 4747 reg = CSR_READ(sc, WMREG_CTRL_EXT); 4748 reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME; 4749 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 4750 4751 ivar = 0; 4752 /* TX */ 4753 for (i = 0; i < sc->sc_ntxqueues; i++) { 4754 txq = &sc->sc_txq[i]; 4755 ivar |= __SHIFTIN((IVAR_VALID_82574 4756 | txq->txq_intr_idx), 4757 IVAR_TX_MASK_Q_82574(txq->txq_id)); 4758 } 4759 /* RX */ 4760 for (i = 0; i < sc->sc_nrxqueues; i++) { 4761 rxq = &sc->sc_rxq[i]; 4762 ivar |= __SHIFTIN((IVAR_VALID_82574 4763 | rxq->rxq_intr_idx), 4764 IVAR_RX_MASK_Q_82574(rxq->rxq_id)); 4765 } 4766 /* Link status */ 4767 ivar |= __SHIFTIN((IVAR_VALID_82574 4768 | sc->sc_link_intr_idx), IVAR_OTHER_MASK); 4769 CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB); 4770 } else { 4771 /* Interrupt control */ 4772 CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | GPIE_MULTI_MSIX 4773 | GPIE_EIAME | GPIE_PBA); 4774 4775 switch (sc->sc_type) { 4776 case WM_T_82580: 4777 case WM_T_I350: 4778 case WM_T_I354: 4779 case WM_T_I210: 4780 case WM_T_I211: 4781 /* TX */ 4782 for (i = 0; i < sc->sc_ntxqueues; i++) { 4783 txq = &sc->sc_txq[i]; 4784 qid = txq->txq_id; 4785 ivar = CSR_READ(sc, WMREG_IVAR_Q(qid)); 4786 ivar &= ~IVAR_TX_MASK_Q(qid); 4787 ivar |= __SHIFTIN((txq->txq_intr_idx 4788 | IVAR_VALID), 4789 IVAR_TX_MASK_Q(qid)); 4790 CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar); 4791 } 4792 4793 /* RX */ 4794 for (i = 0; i < sc->sc_nrxqueues; i++) { 4795 rxq = &sc->sc_rxq[i]; 4796 qid = rxq->rxq_id; 4797 ivar = CSR_READ(sc, WMREG_IVAR_Q(qid)); 4798 ivar &= ~IVAR_RX_MASK_Q(qid); 4799 ivar |= __SHIFTIN((rxq->rxq_intr_idx 4800 | IVAR_VALID), 4801 IVAR_RX_MASK_Q(qid)); 4802 CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar); 4803 } 4804 break; 4805 case WM_T_82576: 4806 /* TX */ 4807 for (i = 0; i < sc->sc_ntxqueues; i++) { 4808 txq = &sc->sc_txq[i]; 4809 qid = txq->txq_id; 4810 ivar = CSR_READ(sc, 4811 WMREG_IVAR_Q_82576(qid)); 4812 ivar &= ~IVAR_TX_MASK_Q_82576(qid); 4813 ivar |= __SHIFTIN((txq->txq_intr_idx 4814 | IVAR_VALID), 4815 IVAR_TX_MASK_Q_82576(qid)); 4816 CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid), 4817 ivar); 4818 } 4819 4820 /* RX */ 4821 for (i = 0; i < sc->sc_nrxqueues; i++) { 4822 rxq = &sc->sc_rxq[i]; 4823 qid = rxq->rxq_id; 4824 ivar = CSR_READ(sc, 4825 WMREG_IVAR_Q_82576(qid)); 4826 ivar &= ~IVAR_RX_MASK_Q_82576(qid); 4827 ivar |= __SHIFTIN((rxq->rxq_intr_idx 4828 | IVAR_VALID), 4829 IVAR_RX_MASK_Q_82576(qid)); 4830 CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid), 4831 ivar); 4832 } 4833 break; 4834 default: 4835 break; 4836 } 4837 4838 /* Link status */ 4839 ivar = __SHIFTIN((sc->sc_link_intr_idx | IVAR_VALID), 4840 IVAR_MISC_OTHER); 4841 CSR_WRITE(sc, WMREG_IVAR_MISC, ivar); 4842 } 4843 4844 if (sc->sc_nrxqueues > 1) { 4845 wm_init_rss(sc); 4846 4847 /* 4848 ** NOTE: Receive Full-Packet Checksum Offload 4849 ** is mutually exclusive with Multiqueue. However 4850 ** this is not the same as TCP/IP checksums which 4851 ** still work. 4852 */ 4853 reg = CSR_READ(sc, WMREG_RXCSUM); 4854 reg |= RXCSUM_PCSD; 4855 CSR_WRITE(sc, WMREG_RXCSUM, reg); 4856 } 4857 } 4858 4859 /* Set up the interrupt registers. */ 4860 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 4861 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 4862 ICR_RXO | ICR_RXT0; 4863 if (sc->sc_nintrs > 1) { 4864 uint32_t mask; 4865 struct wm_txqueue *txq; 4866 struct wm_rxqueue *rxq; 4867 4868 switch (sc->sc_type) { 4869 case WM_T_82574: 4870 CSR_WRITE(sc, WMREG_EIAC_82574, 4871 WMREG_EIAC_82574_MSIX_MASK); 4872 sc->sc_icr |= WMREG_EIAC_82574_MSIX_MASK; 4873 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 4874 break; 4875 default: 4876 if (sc->sc_type == WM_T_82575) { 4877 mask = 0; 4878 for (i = 0; i < sc->sc_ntxqueues; i++) { 4879 txq = &sc->sc_txq[i]; 4880 mask |= EITR_TX_QUEUE(txq->txq_id); 4881 } 4882 for (i = 0; i < sc->sc_nrxqueues; i++) { 4883 rxq = &sc->sc_rxq[i]; 4884 mask |= EITR_RX_QUEUE(rxq->rxq_id); 4885 } 4886 mask |= EITR_OTHER; 4887 } else { 4888 mask = 0; 4889 for (i = 0; i < sc->sc_ntxqueues; i++) { 4890 txq = &sc->sc_txq[i]; 4891 mask |= 1 << txq->txq_intr_idx; 4892 } 4893 for (i = 0; i < sc->sc_nrxqueues; i++) { 4894 rxq = &sc->sc_rxq[i]; 4895 mask |= 1 << rxq->rxq_intr_idx; 4896 } 4897 mask |= 1 << sc->sc_link_intr_idx; 4898 } 4899 CSR_WRITE(sc, WMREG_EIAC, mask); 4900 CSR_WRITE(sc, WMREG_EIAM, mask); 4901 CSR_WRITE(sc, WMREG_EIMS, mask); 4902 CSR_WRITE(sc, WMREG_IMS, ICR_LSC); 4903 break; 4904 } 4905 } else 4906 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 4907 4908 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 4909 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 4910 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT) 4911 || (sc->sc_type == WM_T_PCH_SPT)) { 4912 reg = CSR_READ(sc, WMREG_KABGTXD); 4913 reg |= KABGTXD_BGSQLBIAS; 4914 CSR_WRITE(sc, WMREG_KABGTXD, reg); 4915 } 4916 4917 /* Set up the inter-packet gap. */ 4918 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 4919 4920 if (sc->sc_type >= WM_T_82543) { 4921 /* 4922 * XXX 82574 has both ITR and EITR. SET EITR when we use 4923 * the multi queue function with MSI-X. 4924 */ 4925 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 4926 int qidx; 4927 for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) { 4928 struct wm_txqueue *txq = &sc->sc_txq[qidx]; 4929 CSR_WRITE(sc, WMREG_EITR(txq->txq_intr_idx), 4930 sc->sc_itr); 4931 } 4932 for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) { 4933 struct wm_rxqueue *rxq = &sc->sc_rxq[qidx]; 4934 CSR_WRITE(sc, WMREG_EITR(rxq->rxq_intr_idx), 4935 sc->sc_itr); 4936 } 4937 /* 4938 * Link interrupts occur much less than TX 4939 * interrupts and RX interrupts. So, we don't 4940 * tune EINTR(WM_MSIX_LINKINTR_IDX) value like 4941 * FreeBSD's if_igb. 4942 */ 4943 } else 4944 CSR_WRITE(sc, WMREG_ITR, sc->sc_itr); 4945 } 4946 4947 /* Set the VLAN ethernetype. */ 4948 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 4949 4950 /* 4951 * Set up the transmit control register; we start out with 4952 * a collision distance suitable for FDX, but update it whe 4953 * we resolve the media type. 4954 */ 4955 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC 4956 | TCTL_CT(TX_COLLISION_THRESHOLD) 4957 | TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 4958 if (sc->sc_type >= WM_T_82571) 4959 sc->sc_tctl |= TCTL_MULR; 4960 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 4961 4962 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 4963 /* Write TDT after TCTL.EN is set. See the document. */ 4964 CSR_WRITE(sc, WMREG_TDT(0), 0); 4965 } 4966 4967 if (sc->sc_type == WM_T_80003) { 4968 reg = CSR_READ(sc, WMREG_TCTL_EXT); 4969 reg &= ~TCTL_EXT_GCEX_MASK; 4970 reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 4971 CSR_WRITE(sc, WMREG_TCTL_EXT, reg); 4972 } 4973 4974 /* Set the media. */ 4975 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 4976 goto out; 4977 4978 /* Configure for OS presence */ 4979 wm_init_manageability(sc); 4980 4981 /* 4982 * Set up the receive control register; we actually program 4983 * the register when we set the receive filter. Use multicast 4984 * address offset type 0. 4985 * 4986 * Only the i82544 has the ability to strip the incoming 4987 * CRC, so we don't enable that feature. 4988 */ 4989 sc->sc_mchash_type = 0; 4990 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF 4991 | RCTL_MO(sc->sc_mchash_type); 4992 4993 /* 4994 * The I350 has a bug where it always strips the CRC whether 4995 * asked to or not. So ask for stripped CRC here and cope in rxeof 4996 */ 4997 if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) 4998 || (sc->sc_type == WM_T_I210)) 4999 sc->sc_rctl |= RCTL_SECRC; 5000 5001 if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0) 5002 && (ifp->if_mtu > ETHERMTU)) { 5003 sc->sc_rctl |= RCTL_LPE; 5004 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) 5005 CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO); 5006 } 5007 5008 if (MCLBYTES == 2048) { 5009 sc->sc_rctl |= RCTL_2k; 5010 } else { 5011 if (sc->sc_type >= WM_T_82543) { 5012 switch (MCLBYTES) { 5013 case 4096: 5014 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 5015 break; 5016 case 8192: 5017 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 5018 break; 5019 case 16384: 5020 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 5021 break; 5022 default: 5023 panic("wm_init: MCLBYTES %d unsupported", 5024 MCLBYTES); 5025 break; 5026 } 5027 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 5028 } 5029 5030 /* Set the receive filter. */ 5031 wm_set_filter(sc); 5032 5033 /* Enable ECC */ 5034 switch (sc->sc_type) { 5035 case WM_T_82571: 5036 reg = CSR_READ(sc, WMREG_PBA_ECC); 5037 reg |= PBA_ECC_CORR_EN; 5038 CSR_WRITE(sc, WMREG_PBA_ECC, reg); 5039 break; 5040 case WM_T_PCH_LPT: 5041 case WM_T_PCH_SPT: 5042 reg = CSR_READ(sc, WMREG_PBECCSTS); 5043 reg |= PBECCSTS_UNCORR_ECC_ENABLE; 5044 CSR_WRITE(sc, WMREG_PBECCSTS, reg); 5045 5046 reg = CSR_READ(sc, WMREG_CTRL); 5047 reg |= CTRL_MEHE; 5048 CSR_WRITE(sc, WMREG_CTRL, reg); 5049 break; 5050 default: 5051 break; 5052 } 5053 5054 /* On 575 and later set RDT only if RX enabled */ 5055 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 5056 int qidx; 5057 for (qidx = 0; qidx < sc->sc_nrxqueues; qidx++) { 5058 struct wm_rxqueue *rxq = &sc->sc_rxq[qidx]; 5059 for (i = 0; i < WM_NRXDESC; i++) { 5060 WM_RX_LOCK(rxq); 5061 wm_init_rxdesc(rxq, i); 5062 WM_RX_UNLOCK(rxq); 5063 5064 } 5065 } 5066 } 5067 5068 sc->sc_stopping = false; 5069 5070 /* Start the one second link check clock. */ 5071 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 5072 5073 /* ...all done! */ 5074 ifp->if_flags |= IFF_RUNNING; 5075 ifp->if_flags &= ~IFF_OACTIVE; 5076 5077 out: 5078 sc->sc_if_flags = ifp->if_flags; 5079 if (error) 5080 log(LOG_ERR, "%s: interface not running\n", 5081 device_xname(sc->sc_dev)); 5082 return error; 5083 } 5084 5085 /* 5086 * wm_stop: [ifnet interface function] 5087 * 5088 * Stop transmission on the interface. 5089 */ 5090 static void 5091 wm_stop(struct ifnet *ifp, int disable) 5092 { 5093 struct wm_softc *sc = ifp->if_softc; 5094 5095 WM_CORE_LOCK(sc); 5096 wm_stop_locked(ifp, disable); 5097 WM_CORE_UNLOCK(sc); 5098 } 5099 5100 static void 5101 wm_stop_locked(struct ifnet *ifp, int disable) 5102 { 5103 struct wm_softc *sc = ifp->if_softc; 5104 struct wm_txsoft *txs; 5105 int i, qidx; 5106 5107 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 5108 device_xname(sc->sc_dev), __func__)); 5109 KASSERT(WM_CORE_LOCKED(sc)); 5110 5111 sc->sc_stopping = true; 5112 5113 /* Stop the one second clock. */ 5114 callout_stop(&sc->sc_tick_ch); 5115 5116 /* Stop the 82547 Tx FIFO stall check timer. */ 5117 if (sc->sc_type == WM_T_82547) 5118 callout_stop(&sc->sc_txfifo_ch); 5119 5120 if (sc->sc_flags & WM_F_HAS_MII) { 5121 /* Down the MII. */ 5122 mii_down(&sc->sc_mii); 5123 } else { 5124 #if 0 5125 /* Should we clear PHY's status properly? */ 5126 wm_reset(sc); 5127 #endif 5128 } 5129 5130 /* Stop the transmit and receive processes. */ 5131 CSR_WRITE(sc, WMREG_TCTL, 0); 5132 CSR_WRITE(sc, WMREG_RCTL, 0); 5133 sc->sc_rctl &= ~RCTL_EN; 5134 5135 /* 5136 * Clear the interrupt mask to ensure the device cannot assert its 5137 * interrupt line. 5138 * Clear sc->sc_icr to ensure wm_intr_legacy() makes no attempt to 5139 * service any currently pending or shared interrupt. 5140 */ 5141 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 5142 sc->sc_icr = 0; 5143 if (sc->sc_nintrs > 1) { 5144 if (sc->sc_type != WM_T_82574) { 5145 CSR_WRITE(sc, WMREG_EIMC, 0xffffffffU); 5146 CSR_WRITE(sc, WMREG_EIAC, 0); 5147 } else 5148 CSR_WRITE(sc, WMREG_EIAC_82574, 0); 5149 } 5150 5151 /* Release any queued transmit buffers. */ 5152 for (qidx = 0; qidx < sc->sc_ntxqueues; qidx++) { 5153 struct wm_txqueue *txq = &sc->sc_txq[qidx]; 5154 WM_TX_LOCK(txq); 5155 for (i = 0; i < WM_TXQUEUELEN(txq); i++) { 5156 txs = &txq->txq_soft[i]; 5157 if (txs->txs_mbuf != NULL) { 5158 bus_dmamap_unload(sc->sc_dmat,txs->txs_dmamap); 5159 m_freem(txs->txs_mbuf); 5160 txs->txs_mbuf = NULL; 5161 } 5162 } 5163 if (sc->sc_type == WM_T_PCH_SPT) { 5164 pcireg_t preg; 5165 uint32_t reg; 5166 int nexttx; 5167 5168 /* First, disable MULR fix in FEXTNVM11 */ 5169 reg = CSR_READ(sc, WMREG_FEXTNVM11); 5170 reg |= FEXTNVM11_DIS_MULRFIX; 5171 CSR_WRITE(sc, WMREG_FEXTNVM11, reg); 5172 5173 preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 5174 WM_PCI_DESCRING_STATUS); 5175 reg = CSR_READ(sc, WMREG_TDLEN(0)); 5176 printf("XXX RST: FLUSH = %lu, len = %u\n", 5177 preg & DESCRING_STATUS_FLUSH_REQ, reg); 5178 if (((preg & DESCRING_STATUS_FLUSH_REQ) != 0) 5179 && (reg != 0)) { 5180 /* TX */ 5181 printf("XXX need TX flush (reg = %08x)\n", 5182 preg); 5183 wm_init_tx_descs(sc, txq); 5184 wm_init_tx_regs(sc, txq); 5185 nexttx = txq->txq_next; 5186 wm_set_dma_addr( 5187 &txq->txq_descs[nexttx].wtx_addr, 5188 WM_CDTXADDR(txq, nexttx)); 5189 txq->txq_descs[nexttx].wtx_cmdlen 5190 = htole32(WTX_CMD_IFCS | 512); 5191 wm_cdtxsync(txq, nexttx, 1, 5192 BUS_DMASYNC_PREREAD |BUS_DMASYNC_PREWRITE); 5193 CSR_WRITE(sc, WMREG_TCTL, TCTL_EN); 5194 CSR_WRITE(sc, WMREG_TDT(0), nexttx); 5195 CSR_WRITE_FLUSH(sc); 5196 delay(250); 5197 CSR_WRITE(sc, WMREG_TCTL, 0); 5198 } 5199 preg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 5200 WM_PCI_DESCRING_STATUS); 5201 if (preg & DESCRING_STATUS_FLUSH_REQ) { 5202 /* RX */ 5203 printf("XXX need RX flush\n"); 5204 } 5205 } 5206 WM_TX_UNLOCK(txq); 5207 } 5208 5209 /* Mark the interface as down and cancel the watchdog timer. */ 5210 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5211 ifp->if_timer = 0; 5212 5213 if (disable) { 5214 for (i = 0; i < sc->sc_nrxqueues; i++) { 5215 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5216 WM_RX_LOCK(rxq); 5217 wm_rxdrain(rxq); 5218 WM_RX_UNLOCK(rxq); 5219 } 5220 } 5221 5222 #if 0 /* notyet */ 5223 if (sc->sc_type >= WM_T_82544) 5224 CSR_WRITE(sc, WMREG_WUC, 0); 5225 #endif 5226 } 5227 5228 static void 5229 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 5230 { 5231 struct mbuf *m; 5232 int i; 5233 5234 log(LOG_DEBUG, "%s: mbuf chain:\n", device_xname(sc->sc_dev)); 5235 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 5236 log(LOG_DEBUG, "%s:\tm_data = %p, m_len = %d, " 5237 "m_flags = 0x%08x\n", device_xname(sc->sc_dev), 5238 m->m_data, m->m_len, m->m_flags); 5239 log(LOG_DEBUG, "%s:\t%d mbuf%s in chain\n", device_xname(sc->sc_dev), 5240 i, i == 1 ? "" : "s"); 5241 } 5242 5243 /* 5244 * wm_82547_txfifo_stall: 5245 * 5246 * Callout used to wait for the 82547 Tx FIFO to drain, 5247 * reset the FIFO pointers, and restart packet transmission. 5248 */ 5249 static void 5250 wm_82547_txfifo_stall(void *arg) 5251 { 5252 struct wm_softc *sc = arg; 5253 struct wm_txqueue *txq = sc->sc_txq; 5254 #ifndef WM_MPSAFE 5255 int s; 5256 5257 s = splnet(); 5258 #endif 5259 WM_TX_LOCK(txq); 5260 5261 if (sc->sc_stopping) 5262 goto out; 5263 5264 if (txq->txq_fifo_stall) { 5265 if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) && 5266 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 5267 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 5268 /* 5269 * Packets have drained. Stop transmitter, reset 5270 * FIFO pointers, restart transmitter, and kick 5271 * the packet queue. 5272 */ 5273 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 5274 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 5275 CSR_WRITE(sc, WMREG_TDFT, txq->txq_fifo_addr); 5276 CSR_WRITE(sc, WMREG_TDFH, txq->txq_fifo_addr); 5277 CSR_WRITE(sc, WMREG_TDFTS, txq->txq_fifo_addr); 5278 CSR_WRITE(sc, WMREG_TDFHS, txq->txq_fifo_addr); 5279 CSR_WRITE(sc, WMREG_TCTL, tctl); 5280 CSR_WRITE_FLUSH(sc); 5281 5282 txq->txq_fifo_head = 0; 5283 txq->txq_fifo_stall = 0; 5284 wm_start_locked(&sc->sc_ethercom.ec_if); 5285 } else { 5286 /* 5287 * Still waiting for packets to drain; try again in 5288 * another tick. 5289 */ 5290 callout_schedule(&sc->sc_txfifo_ch, 1); 5291 } 5292 } 5293 5294 out: 5295 WM_TX_UNLOCK(txq); 5296 #ifndef WM_MPSAFE 5297 splx(s); 5298 #endif 5299 } 5300 5301 /* 5302 * wm_82547_txfifo_bugchk: 5303 * 5304 * Check for bug condition in the 82547 Tx FIFO. We need to 5305 * prevent enqueueing a packet that would wrap around the end 5306 * if the Tx FIFO ring buffer, otherwise the chip will croak. 5307 * 5308 * We do this by checking the amount of space before the end 5309 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 5310 * the Tx FIFO, wait for all remaining packets to drain, reset 5311 * the internal FIFO pointers to the beginning, and restart 5312 * transmission on the interface. 5313 */ 5314 #define WM_FIFO_HDR 0x10 5315 #define WM_82547_PAD_LEN 0x3e0 5316 static int 5317 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 5318 { 5319 struct wm_txqueue *txq = &sc->sc_txq[0]; 5320 int space = txq->txq_fifo_size - txq->txq_fifo_head; 5321 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 5322 5323 /* Just return if already stalled. */ 5324 if (txq->txq_fifo_stall) 5325 return 1; 5326 5327 if (sc->sc_mii.mii_media_active & IFM_FDX) { 5328 /* Stall only occurs in half-duplex mode. */ 5329 goto send_packet; 5330 } 5331 5332 if (len >= WM_82547_PAD_LEN + space) { 5333 txq->txq_fifo_stall = 1; 5334 callout_schedule(&sc->sc_txfifo_ch, 1); 5335 return 1; 5336 } 5337 5338 send_packet: 5339 txq->txq_fifo_head += len; 5340 if (txq->txq_fifo_head >= txq->txq_fifo_size) 5341 txq->txq_fifo_head -= txq->txq_fifo_size; 5342 5343 return 0; 5344 } 5345 5346 static int 5347 wm_alloc_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq) 5348 { 5349 int error; 5350 5351 /* 5352 * Allocate the control data structures, and create and load the 5353 * DMA map for it. 5354 * 5355 * NOTE: All Tx descriptors must be in the same 4G segment of 5356 * memory. So must Rx descriptors. We simplify by allocating 5357 * both sets within the same 4G segment. 5358 */ 5359 if (sc->sc_type < WM_T_82544) { 5360 WM_NTXDESC(txq) = WM_NTXDESC_82542; 5361 txq->txq_desc_size = sizeof(wiseman_txdesc_t) *WM_NTXDESC(txq); 5362 } else { 5363 WM_NTXDESC(txq) = WM_NTXDESC_82544; 5364 txq->txq_desc_size = sizeof(txdescs_t); 5365 } 5366 5367 if ((error = bus_dmamem_alloc(sc->sc_dmat, txq->txq_desc_size, 5368 PAGE_SIZE, (bus_size_t) 0x100000000ULL, &txq->txq_desc_seg, 5369 1, &txq->txq_desc_rseg, 0)) != 0) { 5370 aprint_error_dev(sc->sc_dev, 5371 "unable to allocate TX control data, error = %d\n", 5372 error); 5373 goto fail_0; 5374 } 5375 5376 if ((error = bus_dmamem_map(sc->sc_dmat, &txq->txq_desc_seg, 5377 txq->txq_desc_rseg, txq->txq_desc_size, 5378 (void **)&txq->txq_descs_u, BUS_DMA_COHERENT)) != 0) { 5379 aprint_error_dev(sc->sc_dev, 5380 "unable to map TX control data, error = %d\n", error); 5381 goto fail_1; 5382 } 5383 5384 if ((error = bus_dmamap_create(sc->sc_dmat, txq->txq_desc_size, 1, 5385 txq->txq_desc_size, 0, 0, &txq->txq_desc_dmamap)) != 0) { 5386 aprint_error_dev(sc->sc_dev, 5387 "unable to create TX control data DMA map, error = %d\n", 5388 error); 5389 goto fail_2; 5390 } 5391 5392 if ((error = bus_dmamap_load(sc->sc_dmat, txq->txq_desc_dmamap, 5393 txq->txq_descs_u, txq->txq_desc_size, NULL, 0)) != 0) { 5394 aprint_error_dev(sc->sc_dev, 5395 "unable to load TX control data DMA map, error = %d\n", 5396 error); 5397 goto fail_3; 5398 } 5399 5400 return 0; 5401 5402 fail_3: 5403 bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap); 5404 fail_2: 5405 bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u, 5406 txq->txq_desc_size); 5407 fail_1: 5408 bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg); 5409 fail_0: 5410 return error; 5411 } 5412 5413 static void 5414 wm_free_tx_descs(struct wm_softc *sc, struct wm_txqueue *txq) 5415 { 5416 5417 bus_dmamap_unload(sc->sc_dmat, txq->txq_desc_dmamap); 5418 bus_dmamap_destroy(sc->sc_dmat, txq->txq_desc_dmamap); 5419 bus_dmamem_unmap(sc->sc_dmat, (void *)txq->txq_descs_u, 5420 txq->txq_desc_size); 5421 bus_dmamem_free(sc->sc_dmat, &txq->txq_desc_seg, txq->txq_desc_rseg); 5422 } 5423 5424 static int 5425 wm_alloc_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq) 5426 { 5427 int error; 5428 5429 /* 5430 * Allocate the control data structures, and create and load the 5431 * DMA map for it. 5432 * 5433 * NOTE: All Tx descriptors must be in the same 4G segment of 5434 * memory. So must Rx descriptors. We simplify by allocating 5435 * both sets within the same 4G segment. 5436 */ 5437 rxq->rxq_desc_size = sizeof(wiseman_rxdesc_t) * WM_NRXDESC; 5438 if ((error = bus_dmamem_alloc(sc->sc_dmat, rxq->rxq_desc_size, 5439 PAGE_SIZE, (bus_size_t) 0x100000000ULL, &rxq->rxq_desc_seg, 5440 1, &rxq->rxq_desc_rseg, 0)) != 0) { 5441 aprint_error_dev(sc->sc_dev, 5442 "unable to allocate RX control data, error = %d\n", 5443 error); 5444 goto fail_0; 5445 } 5446 5447 if ((error = bus_dmamem_map(sc->sc_dmat, &rxq->rxq_desc_seg, 5448 rxq->rxq_desc_rseg, rxq->rxq_desc_size, 5449 (void **)&rxq->rxq_descs, BUS_DMA_COHERENT)) != 0) { 5450 aprint_error_dev(sc->sc_dev, 5451 "unable to map RX control data, error = %d\n", error); 5452 goto fail_1; 5453 } 5454 5455 if ((error = bus_dmamap_create(sc->sc_dmat, rxq->rxq_desc_size, 1, 5456 rxq->rxq_desc_size, 0, 0, &rxq->rxq_desc_dmamap)) != 0) { 5457 aprint_error_dev(sc->sc_dev, 5458 "unable to create RX control data DMA map, error = %d\n", 5459 error); 5460 goto fail_2; 5461 } 5462 5463 if ((error = bus_dmamap_load(sc->sc_dmat, rxq->rxq_desc_dmamap, 5464 rxq->rxq_descs, rxq->rxq_desc_size, NULL, 0)) != 0) { 5465 aprint_error_dev(sc->sc_dev, 5466 "unable to load RX control data DMA map, error = %d\n", 5467 error); 5468 goto fail_3; 5469 } 5470 5471 return 0; 5472 5473 fail_3: 5474 bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap); 5475 fail_2: 5476 bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs, 5477 rxq->rxq_desc_size); 5478 fail_1: 5479 bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg); 5480 fail_0: 5481 return error; 5482 } 5483 5484 static void 5485 wm_free_rx_descs(struct wm_softc *sc, struct wm_rxqueue *rxq) 5486 { 5487 5488 bus_dmamap_unload(sc->sc_dmat, rxq->rxq_desc_dmamap); 5489 bus_dmamap_destroy(sc->sc_dmat, rxq->rxq_desc_dmamap); 5490 bus_dmamem_unmap(sc->sc_dmat, (void *)rxq->rxq_descs, 5491 rxq->rxq_desc_size); 5492 bus_dmamem_free(sc->sc_dmat, &rxq->rxq_desc_seg, rxq->rxq_desc_rseg); 5493 } 5494 5495 5496 static int 5497 wm_alloc_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq) 5498 { 5499 int i, error; 5500 5501 /* Create the transmit buffer DMA maps. */ 5502 WM_TXQUEUELEN(txq) = 5503 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 5504 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 5505 for (i = 0; i < WM_TXQUEUELEN(txq); i++) { 5506 if ((error = bus_dmamap_create(sc->sc_dmat, WM_MAXTXDMA, 5507 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 5508 &txq->txq_soft[i].txs_dmamap)) != 0) { 5509 aprint_error_dev(sc->sc_dev, 5510 "unable to create Tx DMA map %d, error = %d\n", 5511 i, error); 5512 goto fail; 5513 } 5514 } 5515 5516 return 0; 5517 5518 fail: 5519 for (i = 0; i < WM_TXQUEUELEN(txq); i++) { 5520 if (txq->txq_soft[i].txs_dmamap != NULL) 5521 bus_dmamap_destroy(sc->sc_dmat, 5522 txq->txq_soft[i].txs_dmamap); 5523 } 5524 return error; 5525 } 5526 5527 static void 5528 wm_free_tx_buffer(struct wm_softc *sc, struct wm_txqueue *txq) 5529 { 5530 int i; 5531 5532 for (i = 0; i < WM_TXQUEUELEN(txq); i++) { 5533 if (txq->txq_soft[i].txs_dmamap != NULL) 5534 bus_dmamap_destroy(sc->sc_dmat, 5535 txq->txq_soft[i].txs_dmamap); 5536 } 5537 } 5538 5539 static int 5540 wm_alloc_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq) 5541 { 5542 int i, error; 5543 5544 /* Create the receive buffer DMA maps. */ 5545 for (i = 0; i < WM_NRXDESC; i++) { 5546 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 5547 MCLBYTES, 0, 0, 5548 &rxq->rxq_soft[i].rxs_dmamap)) != 0) { 5549 aprint_error_dev(sc->sc_dev, 5550 "unable to create Rx DMA map %d error = %d\n", 5551 i, error); 5552 goto fail; 5553 } 5554 rxq->rxq_soft[i].rxs_mbuf = NULL; 5555 } 5556 5557 return 0; 5558 5559 fail: 5560 for (i = 0; i < WM_NRXDESC; i++) { 5561 if (rxq->rxq_soft[i].rxs_dmamap != NULL) 5562 bus_dmamap_destroy(sc->sc_dmat, 5563 rxq->rxq_soft[i].rxs_dmamap); 5564 } 5565 return error; 5566 } 5567 5568 static void 5569 wm_free_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq) 5570 { 5571 int i; 5572 5573 for (i = 0; i < WM_NRXDESC; i++) { 5574 if (rxq->rxq_soft[i].rxs_dmamap != NULL) 5575 bus_dmamap_destroy(sc->sc_dmat, 5576 rxq->rxq_soft[i].rxs_dmamap); 5577 } 5578 } 5579 5580 /* 5581 * wm_alloc_quques: 5582 * Allocate {tx,rx}descs and {tx,rx} buffers 5583 */ 5584 static int 5585 wm_alloc_txrx_queues(struct wm_softc *sc) 5586 { 5587 int i, error, tx_done, rx_done; 5588 5589 /* 5590 * For transmission 5591 */ 5592 sc->sc_txq = kmem_zalloc(sizeof(struct wm_txqueue) * sc->sc_ntxqueues, 5593 KM_SLEEP); 5594 if (sc->sc_txq == NULL) { 5595 aprint_error_dev(sc->sc_dev,"unable to allocate wm_txqueue\n"); 5596 error = ENOMEM; 5597 goto fail_0; 5598 } 5599 5600 error = 0; 5601 tx_done = 0; 5602 for (i = 0; i < sc->sc_ntxqueues; i++) { 5603 struct wm_txqueue *txq = &sc->sc_txq[i]; 5604 txq->txq_sc = sc; 5605 #ifdef WM_MPSAFE 5606 txq->txq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 5607 #else 5608 txq->txq_lock = NULL; 5609 #endif 5610 error = wm_alloc_tx_descs(sc, txq); 5611 if (error) 5612 break; 5613 error = wm_alloc_tx_buffer(sc, txq); 5614 if (error) { 5615 wm_free_tx_descs(sc, txq); 5616 break; 5617 } 5618 tx_done++; 5619 } 5620 if (error) 5621 goto fail_1; 5622 5623 /* 5624 * For recieve 5625 */ 5626 sc->sc_rxq = kmem_zalloc(sizeof(struct wm_rxqueue) * sc->sc_nrxqueues, 5627 KM_SLEEP); 5628 if (sc->sc_rxq == NULL) { 5629 aprint_error_dev(sc->sc_dev,"unable to allocate wm_rxqueue\n"); 5630 error = ENOMEM; 5631 goto fail_1; 5632 } 5633 5634 error = 0; 5635 rx_done = 0; 5636 for (i = 0; i < sc->sc_nrxqueues; i++) { 5637 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5638 rxq->rxq_sc = sc; 5639 #ifdef WM_MPSAFE 5640 rxq->rxq_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET); 5641 #else 5642 rxq->rxq_lock = NULL; 5643 #endif 5644 error = wm_alloc_rx_descs(sc, rxq); 5645 if (error) 5646 break; 5647 5648 error = wm_alloc_rx_buffer(sc, rxq); 5649 if (error) { 5650 wm_free_rx_descs(sc, rxq); 5651 break; 5652 } 5653 5654 rx_done++; 5655 } 5656 if (error) 5657 goto fail_2; 5658 5659 return 0; 5660 5661 fail_2: 5662 for (i = 0; i < rx_done; i++) { 5663 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5664 wm_free_rx_buffer(sc, rxq); 5665 wm_free_rx_descs(sc, rxq); 5666 if (rxq->rxq_lock) 5667 mutex_obj_free(rxq->rxq_lock); 5668 } 5669 kmem_free(sc->sc_rxq, 5670 sizeof(struct wm_rxqueue) * sc->sc_nrxqueues); 5671 fail_1: 5672 for (i = 0; i < tx_done; i++) { 5673 struct wm_txqueue *txq = &sc->sc_txq[i]; 5674 wm_free_tx_buffer(sc, txq); 5675 wm_free_tx_descs(sc, txq); 5676 if (txq->txq_lock) 5677 mutex_obj_free(txq->txq_lock); 5678 } 5679 kmem_free(sc->sc_txq, 5680 sizeof(struct wm_txqueue) * sc->sc_ntxqueues); 5681 fail_0: 5682 return error; 5683 } 5684 5685 /* 5686 * wm_free_quques: 5687 * Free {tx,rx}descs and {tx,rx} buffers 5688 */ 5689 static void 5690 wm_free_txrx_queues(struct wm_softc *sc) 5691 { 5692 int i; 5693 5694 for (i = 0; i < sc->sc_nrxqueues; i++) { 5695 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5696 wm_free_rx_buffer(sc, rxq); 5697 wm_free_rx_descs(sc, rxq); 5698 if (rxq->rxq_lock) 5699 mutex_obj_free(rxq->rxq_lock); 5700 } 5701 kmem_free(sc->sc_rxq, sizeof(struct wm_rxqueue) * sc->sc_nrxqueues); 5702 5703 for (i = 0; i < sc->sc_ntxqueues; i++) { 5704 struct wm_txqueue *txq = &sc->sc_txq[i]; 5705 wm_free_tx_buffer(sc, txq); 5706 wm_free_tx_descs(sc, txq); 5707 if (txq->txq_lock) 5708 mutex_obj_free(txq->txq_lock); 5709 } 5710 kmem_free(sc->sc_txq, sizeof(struct wm_txqueue) * sc->sc_ntxqueues); 5711 } 5712 5713 static void 5714 wm_init_tx_descs(struct wm_softc *sc __unused, struct wm_txqueue *txq) 5715 { 5716 5717 KASSERT(WM_TX_LOCKED(txq)); 5718 5719 /* Initialize the transmit descriptor ring. */ 5720 memset(txq->txq_descs, 0, WM_TXDESCSIZE(txq)); 5721 wm_cdtxsync(txq, 0, WM_NTXDESC(txq), 5722 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5723 txq->txq_free = WM_NTXDESC(txq); 5724 txq->txq_next = 0; 5725 } 5726 5727 static void 5728 wm_init_tx_regs(struct wm_softc *sc, struct wm_txqueue *txq) 5729 { 5730 5731 KASSERT(WM_TX_LOCKED(txq)); 5732 5733 if (sc->sc_type < WM_T_82543) { 5734 CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(txq, 0)); 5735 CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(txq, 0)); 5736 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(txq)); 5737 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 5738 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 5739 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 5740 } else { 5741 int qid = txq->txq_id; 5742 5743 CSR_WRITE(sc, WMREG_TDBAH(qid), WM_CDTXADDR_HI(txq, 0)); 5744 CSR_WRITE(sc, WMREG_TDBAL(qid), WM_CDTXADDR_LO(txq, 0)); 5745 CSR_WRITE(sc, WMREG_TDLEN(qid), WM_TXDESCSIZE(txq)); 5746 CSR_WRITE(sc, WMREG_TDH(qid), 0); 5747 5748 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) 5749 /* 5750 * Don't write TDT before TCTL.EN is set. 5751 * See the document. 5752 */ 5753 CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_QUEUE_ENABLE 5754 | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0) 5755 | TXDCTL_WTHRESH(0)); 5756 else { 5757 /* ITR / 4 */ 5758 CSR_WRITE(sc, WMREG_TIDV, sc->sc_itr / 4); 5759 if (sc->sc_type >= WM_T_82540) { 5760 /* should be same */ 5761 CSR_WRITE(sc, WMREG_TADV, sc->sc_itr / 4); 5762 } 5763 5764 CSR_WRITE(sc, WMREG_TDT(qid), 0); 5765 CSR_WRITE(sc, WMREG_TXDCTL(qid), TXDCTL_PTHRESH(0) | 5766 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 5767 } 5768 } 5769 } 5770 5771 static void 5772 wm_init_tx_buffer(struct wm_softc *sc __unused, struct wm_txqueue *txq) 5773 { 5774 int i; 5775 5776 KASSERT(WM_TX_LOCKED(txq)); 5777 5778 /* Initialize the transmit job descriptors. */ 5779 for (i = 0; i < WM_TXQUEUELEN(txq); i++) 5780 txq->txq_soft[i].txs_mbuf = NULL; 5781 txq->txq_sfree = WM_TXQUEUELEN(txq); 5782 txq->txq_snext = 0; 5783 txq->txq_sdirty = 0; 5784 } 5785 5786 static void 5787 wm_init_tx_queue(struct wm_softc *sc, struct wm_txqueue *txq) 5788 { 5789 5790 KASSERT(WM_TX_LOCKED(txq)); 5791 5792 /* 5793 * Set up some register offsets that are different between 5794 * the i82542 and the i82543 and later chips. 5795 */ 5796 if (sc->sc_type < WM_T_82543) 5797 txq->txq_tdt_reg = WMREG_OLD_TDT; 5798 else 5799 txq->txq_tdt_reg = WMREG_TDT(txq->txq_id); 5800 5801 wm_init_tx_descs(sc, txq); 5802 wm_init_tx_regs(sc, txq); 5803 wm_init_tx_buffer(sc, txq); 5804 } 5805 5806 static void 5807 wm_init_rx_regs(struct wm_softc *sc, struct wm_rxqueue *rxq) 5808 { 5809 5810 KASSERT(WM_RX_LOCKED(rxq)); 5811 5812 /* 5813 * Initialize the receive descriptor and receive job 5814 * descriptor rings. 5815 */ 5816 if (sc->sc_type < WM_T_82543) { 5817 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(rxq, 0)); 5818 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(rxq, 0)); 5819 CSR_WRITE(sc, WMREG_OLD_RDLEN0, 5820 sizeof(wiseman_rxdesc_t) * WM_NRXDESC); 5821 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 5822 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 5823 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 5824 5825 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 5826 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 5827 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 5828 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 5829 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 5830 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 5831 } else { 5832 int qid = rxq->rxq_id; 5833 5834 CSR_WRITE(sc, WMREG_RDBAH(qid), WM_CDRXADDR_HI(rxq, 0)); 5835 CSR_WRITE(sc, WMREG_RDBAL(qid), WM_CDRXADDR_LO(rxq, 0)); 5836 CSR_WRITE(sc, WMREG_RDLEN(qid), rxq->rxq_desc_size); 5837 5838 if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) { 5839 if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1)) 5840 panic("%s: MCLBYTES %d unsupported for i2575 or higher\n", __func__, MCLBYTES); 5841 CSR_WRITE(sc, WMREG_SRRCTL(qid), SRRCTL_DESCTYPE_LEGACY 5842 | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT)); 5843 CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_QUEUE_ENABLE 5844 | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8) 5845 | RXDCTL_WTHRESH(1)); 5846 CSR_WRITE(sc, WMREG_RDH(qid), 0); 5847 CSR_WRITE(sc, WMREG_RDT(qid), 0); 5848 } else { 5849 CSR_WRITE(sc, WMREG_RDH(qid), 0); 5850 CSR_WRITE(sc, WMREG_RDT(qid), 0); 5851 /* ITR / 4 */ 5852 CSR_WRITE(sc, WMREG_RDTR, (sc->sc_itr / 4) | RDTR_FPD); 5853 /* MUST be same */ 5854 CSR_WRITE(sc, WMREG_RADV, sc->sc_itr / 4); 5855 CSR_WRITE(sc, WMREG_RXDCTL(qid), RXDCTL_PTHRESH(0) | 5856 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 5857 } 5858 } 5859 } 5860 5861 static int 5862 wm_init_rx_buffer(struct wm_softc *sc, struct wm_rxqueue *rxq) 5863 { 5864 struct wm_rxsoft *rxs; 5865 int error, i; 5866 5867 KASSERT(WM_RX_LOCKED(rxq)); 5868 5869 for (i = 0; i < WM_NRXDESC; i++) { 5870 rxs = &rxq->rxq_soft[i]; 5871 if (rxs->rxs_mbuf == NULL) { 5872 if ((error = wm_add_rxbuf(rxq, i)) != 0) { 5873 log(LOG_ERR, "%s: unable to allocate or map " 5874 "rx buffer %d, error = %d\n", 5875 device_xname(sc->sc_dev), i, error); 5876 /* 5877 * XXX Should attempt to run with fewer receive 5878 * XXX buffers instead of just failing. 5879 */ 5880 wm_rxdrain(rxq); 5881 return ENOMEM; 5882 } 5883 } else { 5884 if ((sc->sc_flags & WM_F_NEWQUEUE) == 0) 5885 wm_init_rxdesc(rxq, i); 5886 /* 5887 * For 82575 and newer device, the RX descriptors 5888 * must be initialized after the setting of RCTL.EN in 5889 * wm_set_filter() 5890 */ 5891 } 5892 } 5893 rxq->rxq_ptr = 0; 5894 rxq->rxq_discard = 0; 5895 WM_RXCHAIN_RESET(rxq); 5896 5897 return 0; 5898 } 5899 5900 static int 5901 wm_init_rx_queue(struct wm_softc *sc, struct wm_rxqueue *rxq) 5902 { 5903 5904 KASSERT(WM_RX_LOCKED(rxq)); 5905 5906 /* 5907 * Set up some register offsets that are different between 5908 * the i82542 and the i82543 and later chips. 5909 */ 5910 if (sc->sc_type < WM_T_82543) 5911 rxq->rxq_rdt_reg = WMREG_OLD_RDT0; 5912 else 5913 rxq->rxq_rdt_reg = WMREG_RDT(rxq->rxq_id); 5914 5915 wm_init_rx_regs(sc, rxq); 5916 return wm_init_rx_buffer(sc, rxq); 5917 } 5918 5919 /* 5920 * wm_init_quques: 5921 * Initialize {tx,rx}descs and {tx,rx} buffers 5922 */ 5923 static int 5924 wm_init_txrx_queues(struct wm_softc *sc) 5925 { 5926 int i, error; 5927 5928 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 5929 device_xname(sc->sc_dev), __func__)); 5930 for (i = 0; i < sc->sc_ntxqueues; i++) { 5931 struct wm_txqueue *txq = &sc->sc_txq[i]; 5932 WM_TX_LOCK(txq); 5933 wm_init_tx_queue(sc, txq); 5934 WM_TX_UNLOCK(txq); 5935 } 5936 5937 error = 0; 5938 for (i = 0; i < sc->sc_nrxqueues; i++) { 5939 struct wm_rxqueue *rxq = &sc->sc_rxq[i]; 5940 WM_RX_LOCK(rxq); 5941 error = wm_init_rx_queue(sc, rxq); 5942 WM_RX_UNLOCK(rxq); 5943 if (error) 5944 break; 5945 } 5946 5947 return error; 5948 } 5949 5950 /* 5951 * wm_tx_offload: 5952 * 5953 * Set up TCP/IP checksumming parameters for the 5954 * specified packet. 5955 */ 5956 static int 5957 wm_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 5958 uint8_t *fieldsp) 5959 { 5960 struct wm_txqueue *txq = &sc->sc_txq[0]; 5961 struct mbuf *m0 = txs->txs_mbuf; 5962 struct livengood_tcpip_ctxdesc *t; 5963 uint32_t ipcs, tucs, cmd, cmdlen, seg; 5964 uint32_t ipcse; 5965 struct ether_header *eh; 5966 int offset, iphl; 5967 uint8_t fields; 5968 5969 /* 5970 * XXX It would be nice if the mbuf pkthdr had offset 5971 * fields for the protocol headers. 5972 */ 5973 5974 eh = mtod(m0, struct ether_header *); 5975 switch (htons(eh->ether_type)) { 5976 case ETHERTYPE_IP: 5977 case ETHERTYPE_IPV6: 5978 offset = ETHER_HDR_LEN; 5979 break; 5980 5981 case ETHERTYPE_VLAN: 5982 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 5983 break; 5984 5985 default: 5986 /* 5987 * Don't support this protocol or encapsulation. 5988 */ 5989 *fieldsp = 0; 5990 *cmdp = 0; 5991 return 0; 5992 } 5993 5994 if ((m0->m_pkthdr.csum_flags & 5995 (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4)) != 0) { 5996 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 5997 } else { 5998 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 5999 } 6000 ipcse = offset + iphl - 1; 6001 6002 cmd = WTX_CMD_DEXT | WTX_DTYP_D; 6003 cmdlen = WTX_CMD_DEXT | WTX_DTYP_C | WTX_CMD_IDE; 6004 seg = 0; 6005 fields = 0; 6006 6007 if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 6008 int hlen = offset + iphl; 6009 bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 6010 6011 if (__predict_false(m0->m_len < 6012 (hlen + sizeof(struct tcphdr)))) { 6013 /* 6014 * TCP/IP headers are not in the first mbuf; we need 6015 * to do this the slow and painful way. Let's just 6016 * hope this doesn't happen very often. 6017 */ 6018 struct tcphdr th; 6019 6020 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 6021 6022 m_copydata(m0, hlen, sizeof(th), &th); 6023 if (v4) { 6024 struct ip ip; 6025 6026 m_copydata(m0, offset, sizeof(ip), &ip); 6027 ip.ip_len = 0; 6028 m_copyback(m0, 6029 offset + offsetof(struct ip, ip_len), 6030 sizeof(ip.ip_len), &ip.ip_len); 6031 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 6032 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 6033 } else { 6034 struct ip6_hdr ip6; 6035 6036 m_copydata(m0, offset, sizeof(ip6), &ip6); 6037 ip6.ip6_plen = 0; 6038 m_copyback(m0, 6039 offset + offsetof(struct ip6_hdr, ip6_plen), 6040 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 6041 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 6042 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 6043 } 6044 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 6045 sizeof(th.th_sum), &th.th_sum); 6046 6047 hlen += th.th_off << 2; 6048 } else { 6049 /* 6050 * TCP/IP headers are in the first mbuf; we can do 6051 * this the easy way. 6052 */ 6053 struct tcphdr *th; 6054 6055 if (v4) { 6056 struct ip *ip = 6057 (void *)(mtod(m0, char *) + offset); 6058 th = (void *)(mtod(m0, char *) + hlen); 6059 6060 ip->ip_len = 0; 6061 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 6062 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 6063 } else { 6064 struct ip6_hdr *ip6 = 6065 (void *)(mtod(m0, char *) + offset); 6066 th = (void *)(mtod(m0, char *) + hlen); 6067 6068 ip6->ip6_plen = 0; 6069 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 6070 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 6071 } 6072 hlen += th->th_off << 2; 6073 } 6074 6075 if (v4) { 6076 WM_EVCNT_INCR(&sc->sc_ev_txtso); 6077 cmdlen |= WTX_TCPIP_CMD_IP; 6078 } else { 6079 WM_EVCNT_INCR(&sc->sc_ev_txtso6); 6080 ipcse = 0; 6081 } 6082 cmd |= WTX_TCPIP_CMD_TSE; 6083 cmdlen |= WTX_TCPIP_CMD_TSE | 6084 WTX_TCPIP_CMD_TCP | (m0->m_pkthdr.len - hlen); 6085 seg = WTX_TCPIP_SEG_HDRLEN(hlen) | 6086 WTX_TCPIP_SEG_MSS(m0->m_pkthdr.segsz); 6087 } 6088 6089 /* 6090 * NOTE: Even if we're not using the IP or TCP/UDP checksum 6091 * offload feature, if we load the context descriptor, we 6092 * MUST provide valid values for IPCSS and TUCSS fields. 6093 */ 6094 6095 ipcs = WTX_TCPIP_IPCSS(offset) | 6096 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 6097 WTX_TCPIP_IPCSE(ipcse); 6098 if (m0->m_pkthdr.csum_flags & (M_CSUM_IPv4 | M_CSUM_TSOv4)) { 6099 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 6100 fields |= WTX_IXSM; 6101 } 6102 6103 offset += iphl; 6104 6105 if (m0->m_pkthdr.csum_flags & 6106 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TSOv4)) { 6107 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 6108 fields |= WTX_TXSM; 6109 tucs = WTX_TCPIP_TUCSS(offset) | 6110 WTX_TCPIP_TUCSO(offset + 6111 M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data)) | 6112 WTX_TCPIP_TUCSE(0) /* rest of packet */; 6113 } else if ((m0->m_pkthdr.csum_flags & 6114 (M_CSUM_TCPv6 | M_CSUM_UDPv6 | M_CSUM_TSOv6)) != 0) { 6115 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 6116 fields |= WTX_TXSM; 6117 tucs = WTX_TCPIP_TUCSS(offset) | 6118 WTX_TCPIP_TUCSO(offset + 6119 M_CSUM_DATA_IPv6_OFFSET(m0->m_pkthdr.csum_data)) | 6120 WTX_TCPIP_TUCSE(0) /* rest of packet */; 6121 } else { 6122 /* Just initialize it to a valid TCP context. */ 6123 tucs = WTX_TCPIP_TUCSS(offset) | 6124 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 6125 WTX_TCPIP_TUCSE(0) /* rest of packet */; 6126 } 6127 6128 /* Fill in the context descriptor. */ 6129 t = (struct livengood_tcpip_ctxdesc *) 6130 &txq->txq_descs[txq->txq_next]; 6131 t->tcpip_ipcs = htole32(ipcs); 6132 t->tcpip_tucs = htole32(tucs); 6133 t->tcpip_cmdlen = htole32(cmdlen); 6134 t->tcpip_seg = htole32(seg); 6135 wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE); 6136 6137 txq->txq_next = WM_NEXTTX(txq, txq->txq_next); 6138 txs->txs_ndesc++; 6139 6140 *cmdp = cmd; 6141 *fieldsp = fields; 6142 6143 return 0; 6144 } 6145 6146 /* 6147 * wm_start: [ifnet interface function] 6148 * 6149 * Start packet transmission on the interface. 6150 */ 6151 static void 6152 wm_start(struct ifnet *ifp) 6153 { 6154 struct wm_softc *sc = ifp->if_softc; 6155 struct wm_txqueue *txq = &sc->sc_txq[0]; 6156 6157 WM_TX_LOCK(txq); 6158 if (!sc->sc_stopping) 6159 wm_start_locked(ifp); 6160 WM_TX_UNLOCK(txq); 6161 } 6162 6163 static void 6164 wm_start_locked(struct ifnet *ifp) 6165 { 6166 struct wm_softc *sc = ifp->if_softc; 6167 struct wm_txqueue *txq = &sc->sc_txq[0]; 6168 struct mbuf *m0; 6169 struct m_tag *mtag; 6170 struct wm_txsoft *txs; 6171 bus_dmamap_t dmamap; 6172 int error, nexttx, lasttx = -1, ofree, seg, segs_needed, use_tso; 6173 bus_addr_t curaddr; 6174 bus_size_t seglen, curlen; 6175 uint32_t cksumcmd; 6176 uint8_t cksumfields; 6177 6178 KASSERT(WM_TX_LOCKED(txq)); 6179 6180 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 6181 return; 6182 6183 /* Remember the previous number of free descriptors. */ 6184 ofree = txq->txq_free; 6185 6186 /* 6187 * Loop through the send queue, setting up transmit descriptors 6188 * until we drain the queue, or use up all available transmit 6189 * descriptors. 6190 */ 6191 for (;;) { 6192 m0 = NULL; 6193 6194 /* Get a work queue entry. */ 6195 if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) { 6196 wm_txeof(sc); 6197 if (txq->txq_sfree == 0) { 6198 DPRINTF(WM_DEBUG_TX, 6199 ("%s: TX: no free job descriptors\n", 6200 device_xname(sc->sc_dev))); 6201 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 6202 break; 6203 } 6204 } 6205 6206 /* Grab a packet off the queue. */ 6207 IFQ_DEQUEUE(&ifp->if_snd, m0); 6208 if (m0 == NULL) 6209 break; 6210 6211 DPRINTF(WM_DEBUG_TX, 6212 ("%s: TX: have packet to transmit: %p\n", 6213 device_xname(sc->sc_dev), m0)); 6214 6215 txs = &txq->txq_soft[txq->txq_snext]; 6216 dmamap = txs->txs_dmamap; 6217 6218 use_tso = (m0->m_pkthdr.csum_flags & 6219 (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0; 6220 6221 /* 6222 * So says the Linux driver: 6223 * The controller does a simple calculation to make sure 6224 * there is enough room in the FIFO before initiating the 6225 * DMA for each buffer. The calc is: 6226 * 4 = ceil(buffer len / MSS) 6227 * To make sure we don't overrun the FIFO, adjust the max 6228 * buffer len if the MSS drops. 6229 */ 6230 dmamap->dm_maxsegsz = 6231 (use_tso && (m0->m_pkthdr.segsz << 2) < WTX_MAX_LEN) 6232 ? m0->m_pkthdr.segsz << 2 6233 : WTX_MAX_LEN; 6234 6235 /* 6236 * Load the DMA map. If this fails, the packet either 6237 * didn't fit in the allotted number of segments, or we 6238 * were short on resources. For the too-many-segments 6239 * case, we simply report an error and drop the packet, 6240 * since we can't sanely copy a jumbo packet to a single 6241 * buffer. 6242 */ 6243 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 6244 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 6245 if (error) { 6246 if (error == EFBIG) { 6247 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 6248 log(LOG_ERR, "%s: Tx packet consumes too many " 6249 "DMA segments, dropping...\n", 6250 device_xname(sc->sc_dev)); 6251 wm_dump_mbuf_chain(sc, m0); 6252 m_freem(m0); 6253 continue; 6254 } 6255 /* Short on resources, just stop for now. */ 6256 DPRINTF(WM_DEBUG_TX, 6257 ("%s: TX: dmamap load failed: %d\n", 6258 device_xname(sc->sc_dev), error)); 6259 break; 6260 } 6261 6262 segs_needed = dmamap->dm_nsegs; 6263 if (use_tso) { 6264 /* For sentinel descriptor; see below. */ 6265 segs_needed++; 6266 } 6267 6268 /* 6269 * Ensure we have enough descriptors free to describe 6270 * the packet. Note, we always reserve one descriptor 6271 * at the end of the ring due to the semantics of the 6272 * TDT register, plus one more in the event we need 6273 * to load offload context. 6274 */ 6275 if (segs_needed > txq->txq_free - 2) { 6276 /* 6277 * Not enough free descriptors to transmit this 6278 * packet. We haven't committed anything yet, 6279 * so just unload the DMA map, put the packet 6280 * pack on the queue, and punt. Notify the upper 6281 * layer that there are no more slots left. 6282 */ 6283 DPRINTF(WM_DEBUG_TX, 6284 ("%s: TX: need %d (%d) descriptors, have %d\n", 6285 device_xname(sc->sc_dev), dmamap->dm_nsegs, 6286 segs_needed, txq->txq_free - 1)); 6287 ifp->if_flags |= IFF_OACTIVE; 6288 bus_dmamap_unload(sc->sc_dmat, dmamap); 6289 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 6290 break; 6291 } 6292 6293 /* 6294 * Check for 82547 Tx FIFO bug. We need to do this 6295 * once we know we can transmit the packet, since we 6296 * do some internal FIFO space accounting here. 6297 */ 6298 if (sc->sc_type == WM_T_82547 && 6299 wm_82547_txfifo_bugchk(sc, m0)) { 6300 DPRINTF(WM_DEBUG_TX, 6301 ("%s: TX: 82547 Tx FIFO bug detected\n", 6302 device_xname(sc->sc_dev))); 6303 ifp->if_flags |= IFF_OACTIVE; 6304 bus_dmamap_unload(sc->sc_dmat, dmamap); 6305 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 6306 break; 6307 } 6308 6309 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 6310 6311 DPRINTF(WM_DEBUG_TX, 6312 ("%s: TX: packet has %d (%d) DMA segments\n", 6313 device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed)); 6314 6315 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 6316 6317 /* 6318 * Store a pointer to the packet so that we can free it 6319 * later. 6320 * 6321 * Initially, we consider the number of descriptors the 6322 * packet uses the number of DMA segments. This may be 6323 * incremented by 1 if we do checksum offload (a descriptor 6324 * is used to set the checksum context). 6325 */ 6326 txs->txs_mbuf = m0; 6327 txs->txs_firstdesc = txq->txq_next; 6328 txs->txs_ndesc = segs_needed; 6329 6330 /* Set up offload parameters for this packet. */ 6331 if (m0->m_pkthdr.csum_flags & 6332 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | 6333 M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 | 6334 M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 6335 if (wm_tx_offload(sc, txs, &cksumcmd, 6336 &cksumfields) != 0) { 6337 /* Error message already displayed. */ 6338 bus_dmamap_unload(sc->sc_dmat, dmamap); 6339 continue; 6340 } 6341 } else { 6342 cksumcmd = 0; 6343 cksumfields = 0; 6344 } 6345 6346 cksumcmd |= WTX_CMD_IDE | WTX_CMD_IFCS; 6347 6348 /* Sync the DMA map. */ 6349 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 6350 BUS_DMASYNC_PREWRITE); 6351 6352 /* Initialize the transmit descriptor. */ 6353 for (nexttx = txq->txq_next, seg = 0; 6354 seg < dmamap->dm_nsegs; seg++) { 6355 for (seglen = dmamap->dm_segs[seg].ds_len, 6356 curaddr = dmamap->dm_segs[seg].ds_addr; 6357 seglen != 0; 6358 curaddr += curlen, seglen -= curlen, 6359 nexttx = WM_NEXTTX(txq, nexttx)) { 6360 curlen = seglen; 6361 6362 /* 6363 * So says the Linux driver: 6364 * Work around for premature descriptor 6365 * write-backs in TSO mode. Append a 6366 * 4-byte sentinel descriptor. 6367 */ 6368 if (use_tso && seg == dmamap->dm_nsegs - 1 && 6369 curlen > 8) 6370 curlen -= 4; 6371 6372 wm_set_dma_addr( 6373 &txq->txq_descs[nexttx].wtx_addr, curaddr); 6374 txq->txq_descs[nexttx].wtx_cmdlen 6375 = htole32(cksumcmd | curlen); 6376 txq->txq_descs[nexttx].wtx_fields.wtxu_status 6377 = 0; 6378 txq->txq_descs[nexttx].wtx_fields.wtxu_options 6379 = cksumfields; 6380 txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0; 6381 lasttx = nexttx; 6382 6383 DPRINTF(WM_DEBUG_TX, 6384 ("%s: TX: desc %d: low %#" PRIx64 ", " 6385 "len %#04zx\n", 6386 device_xname(sc->sc_dev), nexttx, 6387 (uint64_t)curaddr, curlen)); 6388 } 6389 } 6390 6391 KASSERT(lasttx != -1); 6392 6393 /* 6394 * Set up the command byte on the last descriptor of 6395 * the packet. If we're in the interrupt delay window, 6396 * delay the interrupt. 6397 */ 6398 txq->txq_descs[lasttx].wtx_cmdlen |= 6399 htole32(WTX_CMD_EOP | WTX_CMD_RS); 6400 6401 /* 6402 * If VLANs are enabled and the packet has a VLAN tag, set 6403 * up the descriptor to encapsulate the packet for us. 6404 * 6405 * This is only valid on the last descriptor of the packet. 6406 */ 6407 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 6408 txq->txq_descs[lasttx].wtx_cmdlen |= 6409 htole32(WTX_CMD_VLE); 6410 txq->txq_descs[lasttx].wtx_fields.wtxu_vlan 6411 = htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 6412 } 6413 6414 txs->txs_lastdesc = lasttx; 6415 6416 DPRINTF(WM_DEBUG_TX, 6417 ("%s: TX: desc %d: cmdlen 0x%08x\n", 6418 device_xname(sc->sc_dev), 6419 lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen))); 6420 6421 /* Sync the descriptors we're using. */ 6422 wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc, 6423 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6424 6425 /* Give the packet to the chip. */ 6426 CSR_WRITE(sc, txq->txq_tdt_reg, nexttx); 6427 6428 DPRINTF(WM_DEBUG_TX, 6429 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 6430 6431 DPRINTF(WM_DEBUG_TX, 6432 ("%s: TX: finished transmitting packet, job %d\n", 6433 device_xname(sc->sc_dev), txq->txq_snext)); 6434 6435 /* Advance the tx pointer. */ 6436 txq->txq_free -= txs->txs_ndesc; 6437 txq->txq_next = nexttx; 6438 6439 txq->txq_sfree--; 6440 txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext); 6441 6442 /* Pass the packet to any BPF listeners. */ 6443 bpf_mtap(ifp, m0); 6444 } 6445 6446 if (m0 != NULL) { 6447 ifp->if_flags |= IFF_OACTIVE; 6448 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 6449 DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n", 6450 __func__)); 6451 m_freem(m0); 6452 } 6453 6454 if (txq->txq_sfree == 0 || txq->txq_free <= 2) { 6455 /* No more slots; notify upper layer. */ 6456 ifp->if_flags |= IFF_OACTIVE; 6457 } 6458 6459 if (txq->txq_free != ofree) { 6460 /* Set a watchdog timer in case the chip flakes out. */ 6461 ifp->if_timer = 5; 6462 } 6463 } 6464 6465 /* 6466 * wm_nq_tx_offload: 6467 * 6468 * Set up TCP/IP checksumming parameters for the 6469 * specified packet, for NEWQUEUE devices 6470 */ 6471 static int 6472 wm_nq_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs, 6473 uint32_t *cmdlenp, uint32_t *fieldsp, bool *do_csum) 6474 { 6475 struct wm_txqueue *txq = &sc->sc_txq[0]; 6476 struct mbuf *m0 = txs->txs_mbuf; 6477 struct m_tag *mtag; 6478 uint32_t vl_len, mssidx, cmdc; 6479 struct ether_header *eh; 6480 int offset, iphl; 6481 6482 /* 6483 * XXX It would be nice if the mbuf pkthdr had offset 6484 * fields for the protocol headers. 6485 */ 6486 *cmdlenp = 0; 6487 *fieldsp = 0; 6488 6489 eh = mtod(m0, struct ether_header *); 6490 switch (htons(eh->ether_type)) { 6491 case ETHERTYPE_IP: 6492 case ETHERTYPE_IPV6: 6493 offset = ETHER_HDR_LEN; 6494 break; 6495 6496 case ETHERTYPE_VLAN: 6497 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 6498 break; 6499 6500 default: 6501 /* Don't support this protocol or encapsulation. */ 6502 *do_csum = false; 6503 return 0; 6504 } 6505 *do_csum = true; 6506 *cmdlenp = NQTX_DTYP_D | NQTX_CMD_DEXT | NQTX_CMD_IFCS; 6507 cmdc = NQTX_DTYP_C | NQTX_CMD_DEXT; 6508 6509 vl_len = (offset << NQTXC_VLLEN_MACLEN_SHIFT); 6510 KASSERT((offset & ~NQTXC_VLLEN_MACLEN_MASK) == 0); 6511 6512 if ((m0->m_pkthdr.csum_flags & 6513 (M_CSUM_TSOv4 | M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_IPv4)) != 0) { 6514 iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 6515 } else { 6516 iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data); 6517 } 6518 vl_len |= (iphl << NQTXC_VLLEN_IPLEN_SHIFT); 6519 KASSERT((iphl & ~NQTXC_VLLEN_IPLEN_MASK) == 0); 6520 6521 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 6522 vl_len |= ((VLAN_TAG_VALUE(mtag) & NQTXC_VLLEN_VLAN_MASK) 6523 << NQTXC_VLLEN_VLAN_SHIFT); 6524 *cmdlenp |= NQTX_CMD_VLE; 6525 } 6526 6527 mssidx = 0; 6528 6529 if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) { 6530 int hlen = offset + iphl; 6531 int tcp_hlen; 6532 bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0; 6533 6534 if (__predict_false(m0->m_len < 6535 (hlen + sizeof(struct tcphdr)))) { 6536 /* 6537 * TCP/IP headers are not in the first mbuf; we need 6538 * to do this the slow and painful way. Let's just 6539 * hope this doesn't happen very often. 6540 */ 6541 struct tcphdr th; 6542 6543 WM_EVCNT_INCR(&sc->sc_ev_txtsopain); 6544 6545 m_copydata(m0, hlen, sizeof(th), &th); 6546 if (v4) { 6547 struct ip ip; 6548 6549 m_copydata(m0, offset, sizeof(ip), &ip); 6550 ip.ip_len = 0; 6551 m_copyback(m0, 6552 offset + offsetof(struct ip, ip_len), 6553 sizeof(ip.ip_len), &ip.ip_len); 6554 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr, 6555 ip.ip_dst.s_addr, htons(IPPROTO_TCP)); 6556 } else { 6557 struct ip6_hdr ip6; 6558 6559 m_copydata(m0, offset, sizeof(ip6), &ip6); 6560 ip6.ip6_plen = 0; 6561 m_copyback(m0, 6562 offset + offsetof(struct ip6_hdr, ip6_plen), 6563 sizeof(ip6.ip6_plen), &ip6.ip6_plen); 6564 th.th_sum = in6_cksum_phdr(&ip6.ip6_src, 6565 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP)); 6566 } 6567 m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum), 6568 sizeof(th.th_sum), &th.th_sum); 6569 6570 tcp_hlen = th.th_off << 2; 6571 } else { 6572 /* 6573 * TCP/IP headers are in the first mbuf; we can do 6574 * this the easy way. 6575 */ 6576 struct tcphdr *th; 6577 6578 if (v4) { 6579 struct ip *ip = 6580 (void *)(mtod(m0, char *) + offset); 6581 th = (void *)(mtod(m0, char *) + hlen); 6582 6583 ip->ip_len = 0; 6584 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr, 6585 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 6586 } else { 6587 struct ip6_hdr *ip6 = 6588 (void *)(mtod(m0, char *) + offset); 6589 th = (void *)(mtod(m0, char *) + hlen); 6590 6591 ip6->ip6_plen = 0; 6592 th->th_sum = in6_cksum_phdr(&ip6->ip6_src, 6593 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP)); 6594 } 6595 tcp_hlen = th->th_off << 2; 6596 } 6597 hlen += tcp_hlen; 6598 *cmdlenp |= NQTX_CMD_TSE; 6599 6600 if (v4) { 6601 WM_EVCNT_INCR(&sc->sc_ev_txtso); 6602 *fieldsp |= NQTXD_FIELDS_IXSM | NQTXD_FIELDS_TUXSM; 6603 } else { 6604 WM_EVCNT_INCR(&sc->sc_ev_txtso6); 6605 *fieldsp |= NQTXD_FIELDS_TUXSM; 6606 } 6607 *fieldsp |= ((m0->m_pkthdr.len - hlen) << NQTXD_FIELDS_PAYLEN_SHIFT); 6608 KASSERT(((m0->m_pkthdr.len - hlen) & ~NQTXD_FIELDS_PAYLEN_MASK) == 0); 6609 mssidx |= (m0->m_pkthdr.segsz << NQTXC_MSSIDX_MSS_SHIFT); 6610 KASSERT((m0->m_pkthdr.segsz & ~NQTXC_MSSIDX_MSS_MASK) == 0); 6611 mssidx |= (tcp_hlen << NQTXC_MSSIDX_L4LEN_SHIFT); 6612 KASSERT((tcp_hlen & ~NQTXC_MSSIDX_L4LEN_MASK) == 0); 6613 } else { 6614 *fieldsp |= (m0->m_pkthdr.len << NQTXD_FIELDS_PAYLEN_SHIFT); 6615 KASSERT((m0->m_pkthdr.len & ~NQTXD_FIELDS_PAYLEN_MASK) == 0); 6616 } 6617 6618 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 6619 *fieldsp |= NQTXD_FIELDS_IXSM; 6620 cmdc |= NQTXC_CMD_IP4; 6621 } 6622 6623 if (m0->m_pkthdr.csum_flags & 6624 (M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) { 6625 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 6626 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4)) { 6627 cmdc |= NQTXC_CMD_TCP; 6628 } else { 6629 cmdc |= NQTXC_CMD_UDP; 6630 } 6631 cmdc |= NQTXC_CMD_IP4; 6632 *fieldsp |= NQTXD_FIELDS_TUXSM; 6633 } 6634 if (m0->m_pkthdr.csum_flags & 6635 (M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) { 6636 WM_EVCNT_INCR(&sc->sc_ev_txtusum6); 6637 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6)) { 6638 cmdc |= NQTXC_CMD_TCP; 6639 } else { 6640 cmdc |= NQTXC_CMD_UDP; 6641 } 6642 cmdc |= NQTXC_CMD_IP6; 6643 *fieldsp |= NQTXD_FIELDS_TUXSM; 6644 } 6645 6646 /* Fill in the context descriptor. */ 6647 txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_vl_len = 6648 htole32(vl_len); 6649 txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_sn = 0; 6650 txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_cmd = 6651 htole32(cmdc); 6652 txq->txq_nq_descs[txq->txq_next].nqrx_ctx.nqtxc_mssidx = 6653 htole32(mssidx); 6654 wm_cdtxsync(txq, txq->txq_next, 1, BUS_DMASYNC_PREWRITE); 6655 DPRINTF(WM_DEBUG_TX, 6656 ("%s: TX: context desc %d 0x%08x%08x\n", device_xname(sc->sc_dev), 6657 txq->txq_next, 0, vl_len)); 6658 DPRINTF(WM_DEBUG_TX, ("\t0x%08x%08x\n", mssidx, cmdc)); 6659 txq->txq_next = WM_NEXTTX(txq, txq->txq_next); 6660 txs->txs_ndesc++; 6661 return 0; 6662 } 6663 6664 /* 6665 * wm_nq_start: [ifnet interface function] 6666 * 6667 * Start packet transmission on the interface for NEWQUEUE devices 6668 */ 6669 static void 6670 wm_nq_start(struct ifnet *ifp) 6671 { 6672 struct wm_softc *sc = ifp->if_softc; 6673 struct wm_txqueue *txq = &sc->sc_txq[0]; 6674 6675 WM_TX_LOCK(txq); 6676 if (!sc->sc_stopping) 6677 wm_nq_start_locked(ifp); 6678 WM_TX_UNLOCK(txq); 6679 } 6680 6681 static void 6682 wm_nq_start_locked(struct ifnet *ifp) 6683 { 6684 struct wm_softc *sc = ifp->if_softc; 6685 struct wm_txqueue *txq = &sc->sc_txq[0]; 6686 struct mbuf *m0; 6687 struct m_tag *mtag; 6688 struct wm_txsoft *txs; 6689 bus_dmamap_t dmamap; 6690 int error, nexttx, lasttx = -1, seg, segs_needed; 6691 bool do_csum, sent; 6692 6693 KASSERT(WM_TX_LOCKED(txq)); 6694 6695 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 6696 return; 6697 6698 sent = false; 6699 6700 /* 6701 * Loop through the send queue, setting up transmit descriptors 6702 * until we drain the queue, or use up all available transmit 6703 * descriptors. 6704 */ 6705 for (;;) { 6706 m0 = NULL; 6707 6708 /* Get a work queue entry. */ 6709 if (txq->txq_sfree < WM_TXQUEUE_GC(txq)) { 6710 wm_txeof(sc); 6711 if (txq->txq_sfree == 0) { 6712 DPRINTF(WM_DEBUG_TX, 6713 ("%s: TX: no free job descriptors\n", 6714 device_xname(sc->sc_dev))); 6715 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 6716 break; 6717 } 6718 } 6719 6720 /* Grab a packet off the queue. */ 6721 IFQ_DEQUEUE(&ifp->if_snd, m0); 6722 if (m0 == NULL) 6723 break; 6724 6725 DPRINTF(WM_DEBUG_TX, 6726 ("%s: TX: have packet to transmit: %p\n", 6727 device_xname(sc->sc_dev), m0)); 6728 6729 txs = &txq->txq_soft[txq->txq_snext]; 6730 dmamap = txs->txs_dmamap; 6731 6732 /* 6733 * Load the DMA map. If this fails, the packet either 6734 * didn't fit in the allotted number of segments, or we 6735 * were short on resources. For the too-many-segments 6736 * case, we simply report an error and drop the packet, 6737 * since we can't sanely copy a jumbo packet to a single 6738 * buffer. 6739 */ 6740 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 6741 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 6742 if (error) { 6743 if (error == EFBIG) { 6744 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 6745 log(LOG_ERR, "%s: Tx packet consumes too many " 6746 "DMA segments, dropping...\n", 6747 device_xname(sc->sc_dev)); 6748 wm_dump_mbuf_chain(sc, m0); 6749 m_freem(m0); 6750 continue; 6751 } 6752 /* Short on resources, just stop for now. */ 6753 DPRINTF(WM_DEBUG_TX, 6754 ("%s: TX: dmamap load failed: %d\n", 6755 device_xname(sc->sc_dev), error)); 6756 break; 6757 } 6758 6759 segs_needed = dmamap->dm_nsegs; 6760 6761 /* 6762 * Ensure we have enough descriptors free to describe 6763 * the packet. Note, we always reserve one descriptor 6764 * at the end of the ring due to the semantics of the 6765 * TDT register, plus one more in the event we need 6766 * to load offload context. 6767 */ 6768 if (segs_needed > txq->txq_free - 2) { 6769 /* 6770 * Not enough free descriptors to transmit this 6771 * packet. We haven't committed anything yet, 6772 * so just unload the DMA map, put the packet 6773 * pack on the queue, and punt. Notify the upper 6774 * layer that there are no more slots left. 6775 */ 6776 DPRINTF(WM_DEBUG_TX, 6777 ("%s: TX: need %d (%d) descriptors, have %d\n", 6778 device_xname(sc->sc_dev), dmamap->dm_nsegs, 6779 segs_needed, txq->txq_free - 1)); 6780 ifp->if_flags |= IFF_OACTIVE; 6781 bus_dmamap_unload(sc->sc_dmat, dmamap); 6782 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 6783 break; 6784 } 6785 6786 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 6787 6788 DPRINTF(WM_DEBUG_TX, 6789 ("%s: TX: packet has %d (%d) DMA segments\n", 6790 device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed)); 6791 6792 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 6793 6794 /* 6795 * Store a pointer to the packet so that we can free it 6796 * later. 6797 * 6798 * Initially, we consider the number of descriptors the 6799 * packet uses the number of DMA segments. This may be 6800 * incremented by 1 if we do checksum offload (a descriptor 6801 * is used to set the checksum context). 6802 */ 6803 txs->txs_mbuf = m0; 6804 txs->txs_firstdesc = txq->txq_next; 6805 txs->txs_ndesc = segs_needed; 6806 6807 /* Set up offload parameters for this packet. */ 6808 uint32_t cmdlen, fields, dcmdlen; 6809 if (m0->m_pkthdr.csum_flags & 6810 (M_CSUM_TSOv4 | M_CSUM_TSOv6 | 6811 M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4 | 6812 M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 6813 if (wm_nq_tx_offload(sc, txs, &cmdlen, &fields, 6814 &do_csum) != 0) { 6815 /* Error message already displayed. */ 6816 bus_dmamap_unload(sc->sc_dmat, dmamap); 6817 continue; 6818 } 6819 } else { 6820 do_csum = false; 6821 cmdlen = 0; 6822 fields = 0; 6823 } 6824 6825 /* Sync the DMA map. */ 6826 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 6827 BUS_DMASYNC_PREWRITE); 6828 6829 /* Initialize the first transmit descriptor. */ 6830 nexttx = txq->txq_next; 6831 if (!do_csum) { 6832 /* setup a legacy descriptor */ 6833 wm_set_dma_addr(&txq->txq_descs[nexttx].wtx_addr, 6834 dmamap->dm_segs[0].ds_addr); 6835 txq->txq_descs[nexttx].wtx_cmdlen = 6836 htole32(WTX_CMD_IFCS | dmamap->dm_segs[0].ds_len); 6837 txq->txq_descs[nexttx].wtx_fields.wtxu_status = 0; 6838 txq->txq_descs[nexttx].wtx_fields.wtxu_options = 0; 6839 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != 6840 NULL) { 6841 txq->txq_descs[nexttx].wtx_cmdlen |= 6842 htole32(WTX_CMD_VLE); 6843 txq->txq_descs[nexttx].wtx_fields.wtxu_vlan = 6844 htole16(VLAN_TAG_VALUE(mtag) & 0xffff); 6845 } else { 6846 txq->txq_descs[nexttx].wtx_fields.wtxu_vlan =0; 6847 } 6848 dcmdlen = 0; 6849 } else { 6850 /* setup an advanced data descriptor */ 6851 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr = 6852 htole64(dmamap->dm_segs[0].ds_addr); 6853 KASSERT((dmamap->dm_segs[0].ds_len & cmdlen) == 0); 6854 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen = 6855 htole32(dmamap->dm_segs[0].ds_len | cmdlen ); 6856 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields = 6857 htole32(fields); 6858 DPRINTF(WM_DEBUG_TX, 6859 ("%s: TX: adv data desc %d 0x%" PRIx64 "\n", 6860 device_xname(sc->sc_dev), nexttx, 6861 (uint64_t)dmamap->dm_segs[0].ds_addr)); 6862 DPRINTF(WM_DEBUG_TX, 6863 ("\t 0x%08x%08x\n", fields, 6864 (uint32_t)dmamap->dm_segs[0].ds_len | cmdlen)); 6865 dcmdlen = NQTX_DTYP_D | NQTX_CMD_DEXT; 6866 } 6867 6868 lasttx = nexttx; 6869 nexttx = WM_NEXTTX(txq, nexttx); 6870 /* 6871 * fill in the next descriptors. legacy or adcanced format 6872 * is the same here 6873 */ 6874 for (seg = 1; seg < dmamap->dm_nsegs; 6875 seg++, nexttx = WM_NEXTTX(txq, nexttx)) { 6876 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_addr = 6877 htole64(dmamap->dm_segs[seg].ds_addr); 6878 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_cmdlen = 6879 htole32(dcmdlen | dmamap->dm_segs[seg].ds_len); 6880 KASSERT((dcmdlen & dmamap->dm_segs[seg].ds_len) == 0); 6881 txq->txq_nq_descs[nexttx].nqtx_data.nqtxd_fields = 0; 6882 lasttx = nexttx; 6883 6884 DPRINTF(WM_DEBUG_TX, 6885 ("%s: TX: desc %d: %#" PRIx64 ", " 6886 "len %#04zx\n", 6887 device_xname(sc->sc_dev), nexttx, 6888 (uint64_t)dmamap->dm_segs[seg].ds_addr, 6889 dmamap->dm_segs[seg].ds_len)); 6890 } 6891 6892 KASSERT(lasttx != -1); 6893 6894 /* 6895 * Set up the command byte on the last descriptor of 6896 * the packet. If we're in the interrupt delay window, 6897 * delay the interrupt. 6898 */ 6899 KASSERT((WTX_CMD_EOP | WTX_CMD_RS) == 6900 (NQTX_CMD_EOP | NQTX_CMD_RS)); 6901 txq->txq_descs[lasttx].wtx_cmdlen |= 6902 htole32(WTX_CMD_EOP | WTX_CMD_RS); 6903 6904 txs->txs_lastdesc = lasttx; 6905 6906 DPRINTF(WM_DEBUG_TX, ("%s: TX: desc %d: cmdlen 0x%08x\n", 6907 device_xname(sc->sc_dev), 6908 lasttx, le32toh(txq->txq_descs[lasttx].wtx_cmdlen))); 6909 6910 /* Sync the descriptors we're using. */ 6911 wm_cdtxsync(txq, txq->txq_next, txs->txs_ndesc, 6912 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6913 6914 /* Give the packet to the chip. */ 6915 CSR_WRITE(sc, txq->txq_tdt_reg, nexttx); 6916 sent = true; 6917 6918 DPRINTF(WM_DEBUG_TX, 6919 ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx)); 6920 6921 DPRINTF(WM_DEBUG_TX, 6922 ("%s: TX: finished transmitting packet, job %d\n", 6923 device_xname(sc->sc_dev), txq->txq_snext)); 6924 6925 /* Advance the tx pointer. */ 6926 txq->txq_free -= txs->txs_ndesc; 6927 txq->txq_next = nexttx; 6928 6929 txq->txq_sfree--; 6930 txq->txq_snext = WM_NEXTTXS(txq, txq->txq_snext); 6931 6932 /* Pass the packet to any BPF listeners. */ 6933 bpf_mtap(ifp, m0); 6934 } 6935 6936 if (m0 != NULL) { 6937 ifp->if_flags |= IFF_OACTIVE; 6938 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 6939 DPRINTF(WM_DEBUG_TX, ("%s: TX: error after IFQ_DEQUEUE\n", 6940 __func__)); 6941 m_freem(m0); 6942 } 6943 6944 if (txq->txq_sfree == 0 || txq->txq_free <= 2) { 6945 /* No more slots; notify upper layer. */ 6946 ifp->if_flags |= IFF_OACTIVE; 6947 } 6948 6949 if (sent) { 6950 /* Set a watchdog timer in case the chip flakes out. */ 6951 ifp->if_timer = 5; 6952 } 6953 } 6954 6955 /* Interrupt */ 6956 6957 /* 6958 * wm_txeof: 6959 * 6960 * Helper; handle transmit interrupts. 6961 */ 6962 static int 6963 wm_txeof(struct wm_softc *sc) 6964 { 6965 struct wm_txqueue *txq = &sc->sc_txq[0]; 6966 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 6967 struct wm_txsoft *txs; 6968 bool processed = false; 6969 int count = 0; 6970 int i; 6971 uint8_t status; 6972 6973 if (sc->sc_stopping) 6974 return 0; 6975 6976 ifp->if_flags &= ~IFF_OACTIVE; 6977 6978 /* 6979 * Go through the Tx list and free mbufs for those 6980 * frames which have been transmitted. 6981 */ 6982 for (i = txq->txq_sdirty; txq->txq_sfree != WM_TXQUEUELEN(txq); 6983 i = WM_NEXTTXS(txq, i), txq->txq_sfree++) { 6984 txs = &txq->txq_soft[i]; 6985 6986 DPRINTF(WM_DEBUG_TX, ("%s: TX: checking job %d\n", 6987 device_xname(sc->sc_dev), i)); 6988 6989 wm_cdtxsync(txq, txs->txs_firstdesc, txs->txs_ndesc, 6990 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6991 6992 status = 6993 txq->txq_descs[txs->txs_lastdesc].wtx_fields.wtxu_status; 6994 if ((status & WTX_ST_DD) == 0) { 6995 wm_cdtxsync(txq, txs->txs_lastdesc, 1, 6996 BUS_DMASYNC_PREREAD); 6997 break; 6998 } 6999 7000 processed = true; 7001 count++; 7002 DPRINTF(WM_DEBUG_TX, 7003 ("%s: TX: job %d done: descs %d..%d\n", 7004 device_xname(sc->sc_dev), i, txs->txs_firstdesc, 7005 txs->txs_lastdesc)); 7006 7007 /* 7008 * XXX We should probably be using the statistics 7009 * XXX registers, but I don't know if they exist 7010 * XXX on chips before the i82544. 7011 */ 7012 7013 #ifdef WM_EVENT_COUNTERS 7014 if (status & WTX_ST_TU) 7015 WM_EVCNT_INCR(&sc->sc_ev_tu); 7016 #endif /* WM_EVENT_COUNTERS */ 7017 7018 if (status & (WTX_ST_EC | WTX_ST_LC)) { 7019 ifp->if_oerrors++; 7020 if (status & WTX_ST_LC) 7021 log(LOG_WARNING, "%s: late collision\n", 7022 device_xname(sc->sc_dev)); 7023 else if (status & WTX_ST_EC) { 7024 ifp->if_collisions += 16; 7025 log(LOG_WARNING, "%s: excessive collisions\n", 7026 device_xname(sc->sc_dev)); 7027 } 7028 } else 7029 ifp->if_opackets++; 7030 7031 txq->txq_free += txs->txs_ndesc; 7032 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 7033 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 7034 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 7035 m_freem(txs->txs_mbuf); 7036 txs->txs_mbuf = NULL; 7037 } 7038 7039 /* Update the dirty transmit buffer pointer. */ 7040 txq->txq_sdirty = i; 7041 DPRINTF(WM_DEBUG_TX, 7042 ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i)); 7043 7044 if (count != 0) 7045 rnd_add_uint32(&sc->rnd_source, count); 7046 7047 /* 7048 * If there are no more pending transmissions, cancel the watchdog 7049 * timer. 7050 */ 7051 if (txq->txq_sfree == WM_TXQUEUELEN(txq)) 7052 ifp->if_timer = 0; 7053 7054 return processed; 7055 } 7056 7057 /* 7058 * wm_rxeof: 7059 * 7060 * Helper; handle receive interrupts. 7061 */ 7062 static void 7063 wm_rxeof(struct wm_rxqueue *rxq) 7064 { 7065 struct wm_softc *sc = rxq->rxq_sc; 7066 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 7067 struct wm_rxsoft *rxs; 7068 struct mbuf *m; 7069 int i, len; 7070 int count = 0; 7071 uint8_t status, errors; 7072 uint16_t vlantag; 7073 7074 for (i = rxq->rxq_ptr;; i = WM_NEXTRX(i)) { 7075 rxs = &rxq->rxq_soft[i]; 7076 7077 DPRINTF(WM_DEBUG_RX, 7078 ("%s: RX: checking descriptor %d\n", 7079 device_xname(sc->sc_dev), i)); 7080 7081 wm_cdrxsync(rxq, i,BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 7082 7083 status = rxq->rxq_descs[i].wrx_status; 7084 errors = rxq->rxq_descs[i].wrx_errors; 7085 len = le16toh(rxq->rxq_descs[i].wrx_len); 7086 vlantag = rxq->rxq_descs[i].wrx_special; 7087 7088 if ((status & WRX_ST_DD) == 0) { 7089 /* We have processed all of the receive descriptors. */ 7090 wm_cdrxsync(rxq, i, BUS_DMASYNC_PREREAD); 7091 break; 7092 } 7093 7094 count++; 7095 if (__predict_false(rxq->rxq_discard)) { 7096 DPRINTF(WM_DEBUG_RX, 7097 ("%s: RX: discarding contents of descriptor %d\n", 7098 device_xname(sc->sc_dev), i)); 7099 wm_init_rxdesc(rxq, i); 7100 if (status & WRX_ST_EOP) { 7101 /* Reset our state. */ 7102 DPRINTF(WM_DEBUG_RX, 7103 ("%s: RX: resetting rxdiscard -> 0\n", 7104 device_xname(sc->sc_dev))); 7105 rxq->rxq_discard = 0; 7106 } 7107 continue; 7108 } 7109 7110 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 7111 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 7112 7113 m = rxs->rxs_mbuf; 7114 7115 /* 7116 * Add a new receive buffer to the ring, unless of 7117 * course the length is zero. Treat the latter as a 7118 * failed mapping. 7119 */ 7120 if ((len == 0) || (wm_add_rxbuf(rxq, i) != 0)) { 7121 /* 7122 * Failed, throw away what we've done so 7123 * far, and discard the rest of the packet. 7124 */ 7125 ifp->if_ierrors++; 7126 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 7127 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 7128 wm_init_rxdesc(rxq, i); 7129 if ((status & WRX_ST_EOP) == 0) 7130 rxq->rxq_discard = 1; 7131 if (rxq->rxq_head != NULL) 7132 m_freem(rxq->rxq_head); 7133 WM_RXCHAIN_RESET(rxq); 7134 DPRINTF(WM_DEBUG_RX, 7135 ("%s: RX: Rx buffer allocation failed, " 7136 "dropping packet%s\n", device_xname(sc->sc_dev), 7137 rxq->rxq_discard ? " (discard)" : "")); 7138 continue; 7139 } 7140 7141 m->m_len = len; 7142 rxq->rxq_len += len; 7143 DPRINTF(WM_DEBUG_RX, 7144 ("%s: RX: buffer at %p len %d\n", 7145 device_xname(sc->sc_dev), m->m_data, len)); 7146 7147 /* If this is not the end of the packet, keep looking. */ 7148 if ((status & WRX_ST_EOP) == 0) { 7149 WM_RXCHAIN_LINK(rxq, m); 7150 DPRINTF(WM_DEBUG_RX, 7151 ("%s: RX: not yet EOP, rxlen -> %d\n", 7152 device_xname(sc->sc_dev), rxq->rxq_len)); 7153 continue; 7154 } 7155 7156 /* 7157 * Okay, we have the entire packet now. The chip is 7158 * configured to include the FCS except I350 and I21[01] 7159 * (not all chips can be configured to strip it), 7160 * so we need to trim it. 7161 * May need to adjust length of previous mbuf in the 7162 * chain if the current mbuf is too short. 7163 * For an eratta, the RCTL_SECRC bit in RCTL register 7164 * is always set in I350, so we don't trim it. 7165 */ 7166 if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I354) 7167 && (sc->sc_type != WM_T_I210) 7168 && (sc->sc_type != WM_T_I211)) { 7169 if (m->m_len < ETHER_CRC_LEN) { 7170 rxq->rxq_tail->m_len 7171 -= (ETHER_CRC_LEN - m->m_len); 7172 m->m_len = 0; 7173 } else 7174 m->m_len -= ETHER_CRC_LEN; 7175 len = rxq->rxq_len - ETHER_CRC_LEN; 7176 } else 7177 len = rxq->rxq_len; 7178 7179 WM_RXCHAIN_LINK(rxq, m); 7180 7181 *rxq->rxq_tailp = NULL; 7182 m = rxq->rxq_head; 7183 7184 WM_RXCHAIN_RESET(rxq); 7185 7186 DPRINTF(WM_DEBUG_RX, 7187 ("%s: RX: have entire packet, len -> %d\n", 7188 device_xname(sc->sc_dev), len)); 7189 7190 /* If an error occurred, update stats and drop the packet. */ 7191 if (errors & 7192 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 7193 if (errors & WRX_ER_SE) 7194 log(LOG_WARNING, "%s: symbol error\n", 7195 device_xname(sc->sc_dev)); 7196 else if (errors & WRX_ER_SEQ) 7197 log(LOG_WARNING, "%s: receive sequence error\n", 7198 device_xname(sc->sc_dev)); 7199 else if (errors & WRX_ER_CE) 7200 log(LOG_WARNING, "%s: CRC error\n", 7201 device_xname(sc->sc_dev)); 7202 m_freem(m); 7203 continue; 7204 } 7205 7206 /* No errors. Receive the packet. */ 7207 m->m_pkthdr.rcvif = ifp; 7208 m->m_pkthdr.len = len; 7209 7210 /* 7211 * If VLANs are enabled, VLAN packets have been unwrapped 7212 * for us. Associate the tag with the packet. 7213 */ 7214 /* XXXX should check for i350 and i354 */ 7215 if ((status & WRX_ST_VP) != 0) { 7216 VLAN_INPUT_TAG(ifp, m, le16toh(vlantag), continue); 7217 } 7218 7219 /* Set up checksum info for this packet. */ 7220 if ((status & WRX_ST_IXSM) == 0) { 7221 if (status & WRX_ST_IPCS) { 7222 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 7223 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 7224 if (errors & WRX_ER_IPE) 7225 m->m_pkthdr.csum_flags |= 7226 M_CSUM_IPv4_BAD; 7227 } 7228 if (status & WRX_ST_TCPCS) { 7229 /* 7230 * Note: we don't know if this was TCP or UDP, 7231 * so we just set both bits, and expect the 7232 * upper layers to deal. 7233 */ 7234 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 7235 m->m_pkthdr.csum_flags |= 7236 M_CSUM_TCPv4 | M_CSUM_UDPv4 | 7237 M_CSUM_TCPv6 | M_CSUM_UDPv6; 7238 if (errors & WRX_ER_TCPE) 7239 m->m_pkthdr.csum_flags |= 7240 M_CSUM_TCP_UDP_BAD; 7241 } 7242 } 7243 7244 ifp->if_ipackets++; 7245 7246 WM_RX_UNLOCK(rxq); 7247 7248 /* Pass this up to any BPF listeners. */ 7249 bpf_mtap(ifp, m); 7250 7251 /* Pass it on. */ 7252 if_percpuq_enqueue(sc->sc_ipq, m); 7253 7254 WM_RX_LOCK(rxq); 7255 7256 if (sc->sc_stopping) 7257 break; 7258 } 7259 7260 /* Update the receive pointer. */ 7261 rxq->rxq_ptr = i; 7262 if (count != 0) 7263 rnd_add_uint32(&sc->rnd_source, count); 7264 7265 DPRINTF(WM_DEBUG_RX, 7266 ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i)); 7267 } 7268 7269 /* 7270 * wm_linkintr_gmii: 7271 * 7272 * Helper; handle link interrupts for GMII. 7273 */ 7274 static void 7275 wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr) 7276 { 7277 7278 KASSERT(WM_CORE_LOCKED(sc)); 7279 7280 DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev), 7281 __func__)); 7282 7283 if (icr & ICR_LSC) { 7284 uint32_t status = CSR_READ(sc, WMREG_STATUS); 7285 7286 if ((sc->sc_type == WM_T_ICH8) && ((status & STATUS_LU) == 0)) 7287 wm_gig_downshift_workaround_ich8lan(sc); 7288 7289 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> mii_pollstat\n", 7290 device_xname(sc->sc_dev))); 7291 mii_pollstat(&sc->sc_mii); 7292 if (sc->sc_type == WM_T_82543) { 7293 int miistatus, active; 7294 7295 /* 7296 * With 82543, we need to force speed and 7297 * duplex on the MAC equal to what the PHY 7298 * speed and duplex configuration is. 7299 */ 7300 miistatus = sc->sc_mii.mii_media_status; 7301 7302 if (miistatus & IFM_ACTIVE) { 7303 active = sc->sc_mii.mii_media_active; 7304 sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD); 7305 switch (IFM_SUBTYPE(active)) { 7306 case IFM_10_T: 7307 sc->sc_ctrl |= CTRL_SPEED_10; 7308 break; 7309 case IFM_100_TX: 7310 sc->sc_ctrl |= CTRL_SPEED_100; 7311 break; 7312 case IFM_1000_T: 7313 sc->sc_ctrl |= CTRL_SPEED_1000; 7314 break; 7315 default: 7316 /* 7317 * fiber? 7318 * Shoud not enter here. 7319 */ 7320 printf("unknown media (%x)\n", active); 7321 break; 7322 } 7323 if (active & IFM_FDX) 7324 sc->sc_ctrl |= CTRL_FD; 7325 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7326 } 7327 } else if ((sc->sc_type == WM_T_ICH8) 7328 && (sc->sc_phytype == WMPHY_IGP_3)) { 7329 wm_kmrn_lock_loss_workaround_ich8lan(sc); 7330 } else if (sc->sc_type == WM_T_PCH) { 7331 wm_k1_gig_workaround_hv(sc, 7332 ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0)); 7333 } 7334 7335 if ((sc->sc_phytype == WMPHY_82578) 7336 && (IFM_SUBTYPE(sc->sc_mii.mii_media_active) 7337 == IFM_1000_T)) { 7338 7339 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0) { 7340 delay(200*1000); /* XXX too big */ 7341 7342 /* Link stall fix for link up */ 7343 wm_gmii_hv_writereg(sc->sc_dev, 1, 7344 HV_MUX_DATA_CTRL, 7345 HV_MUX_DATA_CTRL_GEN_TO_MAC 7346 | HV_MUX_DATA_CTRL_FORCE_SPEED); 7347 wm_gmii_hv_writereg(sc->sc_dev, 1, 7348 HV_MUX_DATA_CTRL, 7349 HV_MUX_DATA_CTRL_GEN_TO_MAC); 7350 } 7351 } 7352 } else if (icr & ICR_RXSEQ) { 7353 DPRINTF(WM_DEBUG_LINK, ("%s: LINK Receive sequence error\n", 7354 device_xname(sc->sc_dev))); 7355 } 7356 } 7357 7358 /* 7359 * wm_linkintr_tbi: 7360 * 7361 * Helper; handle link interrupts for TBI mode. 7362 */ 7363 static void 7364 wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr) 7365 { 7366 uint32_t status; 7367 7368 DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev), 7369 __func__)); 7370 7371 status = CSR_READ(sc, WMREG_STATUS); 7372 if (icr & ICR_LSC) { 7373 if (status & STATUS_LU) { 7374 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 7375 device_xname(sc->sc_dev), 7376 (status & STATUS_FD) ? "FDX" : "HDX")); 7377 /* 7378 * NOTE: CTRL will update TFCE and RFCE automatically, 7379 * so we should update sc->sc_ctrl 7380 */ 7381 7382 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL); 7383 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 7384 sc->sc_fcrtl &= ~FCRTL_XONE; 7385 if (status & STATUS_FD) 7386 sc->sc_tctl |= 7387 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 7388 else 7389 sc->sc_tctl |= 7390 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 7391 if (sc->sc_ctrl & CTRL_TFCE) 7392 sc->sc_fcrtl |= FCRTL_XONE; 7393 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 7394 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 7395 WMREG_OLD_FCRTL : WMREG_FCRTL, 7396 sc->sc_fcrtl); 7397 sc->sc_tbi_linkup = 1; 7398 } else { 7399 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 7400 device_xname(sc->sc_dev))); 7401 sc->sc_tbi_linkup = 0; 7402 } 7403 /* Update LED */ 7404 wm_tbi_serdes_set_linkled(sc); 7405 } else if (icr & ICR_RXSEQ) { 7406 DPRINTF(WM_DEBUG_LINK, 7407 ("%s: LINK: Receive sequence error\n", 7408 device_xname(sc->sc_dev))); 7409 } 7410 } 7411 7412 /* 7413 * wm_linkintr_serdes: 7414 * 7415 * Helper; handle link interrupts for TBI mode. 7416 */ 7417 static void 7418 wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr) 7419 { 7420 struct mii_data *mii = &sc->sc_mii; 7421 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 7422 uint32_t pcs_adv, pcs_lpab, reg; 7423 7424 DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev), 7425 __func__)); 7426 7427 if (icr & ICR_LSC) { 7428 /* Check PCS */ 7429 reg = CSR_READ(sc, WMREG_PCS_LSTS); 7430 if ((reg & PCS_LSTS_LINKOK) != 0) { 7431 mii->mii_media_status |= IFM_ACTIVE; 7432 sc->sc_tbi_linkup = 1; 7433 } else { 7434 mii->mii_media_status |= IFM_NONE; 7435 sc->sc_tbi_linkup = 0; 7436 wm_tbi_serdes_set_linkled(sc); 7437 return; 7438 } 7439 mii->mii_media_active |= IFM_1000_SX; 7440 if ((reg & PCS_LSTS_FDX) != 0) 7441 mii->mii_media_active |= IFM_FDX; 7442 else 7443 mii->mii_media_active |= IFM_HDX; 7444 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 7445 /* Check flow */ 7446 reg = CSR_READ(sc, WMREG_PCS_LSTS); 7447 if ((reg & PCS_LSTS_AN_COMP) == 0) { 7448 DPRINTF(WM_DEBUG_LINK, 7449 ("XXX LINKOK but not ACOMP\n")); 7450 return; 7451 } 7452 pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV); 7453 pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB); 7454 DPRINTF(WM_DEBUG_LINK, 7455 ("XXX AN result %08x, %08x\n", pcs_adv, pcs_lpab)); 7456 if ((pcs_adv & TXCW_SYM_PAUSE) 7457 && (pcs_lpab & TXCW_SYM_PAUSE)) { 7458 mii->mii_media_active |= IFM_FLOW 7459 | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 7460 } else if (((pcs_adv & TXCW_SYM_PAUSE) == 0) 7461 && (pcs_adv & TXCW_ASYM_PAUSE) 7462 && (pcs_lpab & TXCW_SYM_PAUSE) 7463 && (pcs_lpab & TXCW_ASYM_PAUSE)) 7464 mii->mii_media_active |= IFM_FLOW 7465 | IFM_ETH_TXPAUSE; 7466 else if ((pcs_adv & TXCW_SYM_PAUSE) 7467 && (pcs_adv & TXCW_ASYM_PAUSE) 7468 && ((pcs_lpab & TXCW_SYM_PAUSE) == 0) 7469 && (pcs_lpab & TXCW_ASYM_PAUSE)) 7470 mii->mii_media_active |= IFM_FLOW 7471 | IFM_ETH_RXPAUSE; 7472 } 7473 /* Update LED */ 7474 wm_tbi_serdes_set_linkled(sc); 7475 } else { 7476 DPRINTF(WM_DEBUG_LINK, 7477 ("%s: LINK: Receive sequence error\n", 7478 device_xname(sc->sc_dev))); 7479 } 7480 } 7481 7482 /* 7483 * wm_linkintr: 7484 * 7485 * Helper; handle link interrupts. 7486 */ 7487 static void 7488 wm_linkintr(struct wm_softc *sc, uint32_t icr) 7489 { 7490 7491 KASSERT(WM_CORE_LOCKED(sc)); 7492 7493 if (sc->sc_flags & WM_F_HAS_MII) 7494 wm_linkintr_gmii(sc, icr); 7495 else if ((sc->sc_mediatype == WM_MEDIATYPE_SERDES) 7496 && (sc->sc_type >= WM_T_82575)) 7497 wm_linkintr_serdes(sc, icr); 7498 else 7499 wm_linkintr_tbi(sc, icr); 7500 } 7501 7502 /* 7503 * wm_intr_legacy: 7504 * 7505 * Interrupt service routine for INTx and MSI. 7506 */ 7507 static int 7508 wm_intr_legacy(void *arg) 7509 { 7510 struct wm_softc *sc = arg; 7511 struct wm_txqueue *txq = &sc->sc_txq[0]; 7512 struct wm_rxqueue *rxq = &sc->sc_rxq[0]; 7513 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 7514 uint32_t icr, rndval = 0; 7515 int handled = 0; 7516 7517 DPRINTF(WM_DEBUG_TX, 7518 ("%s: INTx: got intr\n", device_xname(sc->sc_dev))); 7519 while (1 /* CONSTCOND */) { 7520 icr = CSR_READ(sc, WMREG_ICR); 7521 if ((icr & sc->sc_icr) == 0) 7522 break; 7523 if (rndval == 0) 7524 rndval = icr; 7525 7526 WM_RX_LOCK(rxq); 7527 7528 if (sc->sc_stopping) { 7529 WM_RX_UNLOCK(rxq); 7530 break; 7531 } 7532 7533 handled = 1; 7534 7535 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 7536 if (icr & (ICR_RXDMT0 | ICR_RXT0)) { 7537 DPRINTF(WM_DEBUG_RX, 7538 ("%s: RX: got Rx intr 0x%08x\n", 7539 device_xname(sc->sc_dev), 7540 icr & (ICR_RXDMT0 | ICR_RXT0))); 7541 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 7542 } 7543 #endif 7544 wm_rxeof(rxq); 7545 7546 WM_RX_UNLOCK(rxq); 7547 WM_TX_LOCK(txq); 7548 7549 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 7550 if (icr & ICR_TXDW) { 7551 DPRINTF(WM_DEBUG_TX, 7552 ("%s: TX: got TXDW interrupt\n", 7553 device_xname(sc->sc_dev))); 7554 WM_EVCNT_INCR(&sc->sc_ev_txdw); 7555 } 7556 #endif 7557 wm_txeof(sc); 7558 7559 WM_TX_UNLOCK(txq); 7560 WM_CORE_LOCK(sc); 7561 7562 if (icr & (ICR_LSC | ICR_RXSEQ)) { 7563 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 7564 wm_linkintr(sc, icr); 7565 } 7566 7567 WM_CORE_UNLOCK(sc); 7568 7569 if (icr & ICR_RXO) { 7570 #if defined(WM_DEBUG) 7571 log(LOG_WARNING, "%s: Receive overrun\n", 7572 device_xname(sc->sc_dev)); 7573 #endif /* defined(WM_DEBUG) */ 7574 } 7575 } 7576 7577 rnd_add_uint32(&sc->rnd_source, rndval); 7578 7579 if (handled) { 7580 /* Try to get more packets going. */ 7581 ifp->if_start(ifp); 7582 } 7583 7584 return handled; 7585 } 7586 7587 /* 7588 * wm_txintr_msix: 7589 * 7590 * Interrupt service routine for TX complete interrupt for MSI-X. 7591 */ 7592 static int 7593 wm_txintr_msix(void *arg) 7594 { 7595 struct wm_txqueue *txq = arg; 7596 struct wm_softc *sc = txq->txq_sc; 7597 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 7598 int handled = 0; 7599 7600 DPRINTF(WM_DEBUG_TX, 7601 ("%s: TX: got Tx intr\n", device_xname(sc->sc_dev))); 7602 7603 if (sc->sc_type == WM_T_82574) 7604 CSR_WRITE(sc, WMREG_IMC, ICR_TXQ(txq->txq_id)); 7605 else if (sc->sc_type == WM_T_82575) 7606 CSR_WRITE(sc, WMREG_EIMC, EITR_TX_QUEUE(txq->txq_id)); 7607 else 7608 CSR_WRITE(sc, WMREG_EIMC, 1 << txq->txq_intr_idx); 7609 7610 WM_TX_LOCK(txq); 7611 7612 if (sc->sc_stopping) 7613 goto out; 7614 7615 WM_EVCNT_INCR(&sc->sc_ev_txdw); 7616 handled = wm_txeof(sc); 7617 7618 out: 7619 WM_TX_UNLOCK(txq); 7620 7621 if (sc->sc_type == WM_T_82574) 7622 CSR_WRITE(sc, WMREG_IMS, ICR_TXQ(txq->txq_id)); 7623 else if (sc->sc_type == WM_T_82575) 7624 CSR_WRITE(sc, WMREG_EIMS, EITR_TX_QUEUE(txq->txq_id)); 7625 else 7626 CSR_WRITE(sc, WMREG_EIMS, 1 << txq->txq_intr_idx); 7627 7628 if (handled) { 7629 /* Try to get more packets going. */ 7630 ifp->if_start(ifp); 7631 } 7632 7633 return handled; 7634 } 7635 7636 /* 7637 * wm_rxintr_msix: 7638 * 7639 * Interrupt service routine for RX interrupt for MSI-X. 7640 */ 7641 static int 7642 wm_rxintr_msix(void *arg) 7643 { 7644 struct wm_rxqueue *rxq = arg; 7645 struct wm_softc *sc = rxq->rxq_sc; 7646 7647 DPRINTF(WM_DEBUG_RX, 7648 ("%s: RX: got Rx intr\n", device_xname(sc->sc_dev))); 7649 7650 if (sc->sc_type == WM_T_82574) 7651 CSR_WRITE(sc, WMREG_IMC, ICR_RXQ(rxq->rxq_id)); 7652 else if (sc->sc_type == WM_T_82575) 7653 CSR_WRITE(sc, WMREG_EIMC, EITR_RX_QUEUE(rxq->rxq_id)); 7654 else 7655 CSR_WRITE(sc, WMREG_EIMC, 1 << rxq->rxq_intr_idx); 7656 7657 WM_RX_LOCK(rxq); 7658 7659 if (sc->sc_stopping) 7660 goto out; 7661 7662 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 7663 wm_rxeof(rxq); 7664 7665 out: 7666 WM_RX_UNLOCK(rxq); 7667 7668 if (sc->sc_type == WM_T_82574) 7669 CSR_WRITE(sc, WMREG_IMS, ICR_RXQ(rxq->rxq_id)); 7670 else if (sc->sc_type == WM_T_82575) 7671 CSR_WRITE(sc, WMREG_EIMS, EITR_RX_QUEUE(rxq->rxq_id)); 7672 else 7673 CSR_WRITE(sc, WMREG_EIMS, 1 << rxq->rxq_intr_idx); 7674 7675 return 1; 7676 } 7677 7678 /* 7679 * wm_linkintr_msix: 7680 * 7681 * Interrupt service routine for link status change for MSI-X. 7682 */ 7683 static int 7684 wm_linkintr_msix(void *arg) 7685 { 7686 struct wm_softc *sc = arg; 7687 uint32_t reg; 7688 7689 DPRINTF(WM_DEBUG_LINK, 7690 ("%s: LINK: got link intr\n", device_xname(sc->sc_dev))); 7691 7692 reg = CSR_READ(sc, WMREG_ICR); 7693 WM_CORE_LOCK(sc); 7694 if ((sc->sc_stopping) || ((reg & ICR_LSC) == 0)) 7695 goto out; 7696 7697 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 7698 wm_linkintr(sc, ICR_LSC); 7699 7700 out: 7701 WM_CORE_UNLOCK(sc); 7702 7703 if (sc->sc_type == WM_T_82574) 7704 CSR_WRITE(sc, WMREG_IMS, ICR_OTHER | ICR_LSC); 7705 else if (sc->sc_type == WM_T_82575) 7706 CSR_WRITE(sc, WMREG_EIMS, EITR_OTHER); 7707 else 7708 CSR_WRITE(sc, WMREG_EIMS, 1 << sc->sc_link_intr_idx); 7709 7710 return 1; 7711 } 7712 7713 /* 7714 * Media related. 7715 * GMII, SGMII, TBI (and SERDES) 7716 */ 7717 7718 /* Common */ 7719 7720 /* 7721 * wm_tbi_serdes_set_linkled: 7722 * 7723 * Update the link LED on TBI and SERDES devices. 7724 */ 7725 static void 7726 wm_tbi_serdes_set_linkled(struct wm_softc *sc) 7727 { 7728 7729 if (sc->sc_tbi_linkup) 7730 sc->sc_ctrl |= CTRL_SWDPIN(0); 7731 else 7732 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 7733 7734 /* 82540 or newer devices are active low */ 7735 sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0; 7736 7737 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7738 } 7739 7740 /* GMII related */ 7741 7742 /* 7743 * wm_gmii_reset: 7744 * 7745 * Reset the PHY. 7746 */ 7747 static void 7748 wm_gmii_reset(struct wm_softc *sc) 7749 { 7750 uint32_t reg; 7751 int rv; 7752 7753 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 7754 device_xname(sc->sc_dev), __func__)); 7755 /* get phy semaphore */ 7756 switch (sc->sc_type) { 7757 case WM_T_82571: 7758 case WM_T_82572: 7759 case WM_T_82573: 7760 case WM_T_82574: 7761 case WM_T_82583: 7762 /* XXX should get sw semaphore, too */ 7763 rv = wm_get_swsm_semaphore(sc); 7764 break; 7765 case WM_T_82575: 7766 case WM_T_82576: 7767 case WM_T_82580: 7768 case WM_T_I350: 7769 case WM_T_I354: 7770 case WM_T_I210: 7771 case WM_T_I211: 7772 case WM_T_80003: 7773 rv = wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]); 7774 break; 7775 case WM_T_ICH8: 7776 case WM_T_ICH9: 7777 case WM_T_ICH10: 7778 case WM_T_PCH: 7779 case WM_T_PCH2: 7780 case WM_T_PCH_LPT: 7781 case WM_T_PCH_SPT: 7782 rv = wm_get_swfwhw_semaphore(sc); 7783 break; 7784 default: 7785 /* nothing to do*/ 7786 rv = 0; 7787 break; 7788 } 7789 if (rv != 0) { 7790 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 7791 __func__); 7792 return; 7793 } 7794 7795 switch (sc->sc_type) { 7796 case WM_T_82542_2_0: 7797 case WM_T_82542_2_1: 7798 /* null */ 7799 break; 7800 case WM_T_82543: 7801 /* 7802 * With 82543, we need to force speed and duplex on the MAC 7803 * equal to what the PHY speed and duplex configuration is. 7804 * In addition, we need to perform a hardware reset on the PHY 7805 * to take it out of reset. 7806 */ 7807 sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX; 7808 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7809 7810 /* The PHY reset pin is active-low. */ 7811 reg = CSR_READ(sc, WMREG_CTRL_EXT); 7812 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 7813 CTRL_EXT_SWDPIN(4)); 7814 reg |= CTRL_EXT_SWDPIO(4); 7815 7816 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 7817 CSR_WRITE_FLUSH(sc); 7818 delay(10*1000); 7819 7820 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 7821 CSR_WRITE_FLUSH(sc); 7822 delay(150); 7823 #if 0 7824 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 7825 #endif 7826 delay(20*1000); /* XXX extra delay to get PHY ID? */ 7827 break; 7828 case WM_T_82544: /* reset 10000us */ 7829 case WM_T_82540: 7830 case WM_T_82545: 7831 case WM_T_82545_3: 7832 case WM_T_82546: 7833 case WM_T_82546_3: 7834 case WM_T_82541: 7835 case WM_T_82541_2: 7836 case WM_T_82547: 7837 case WM_T_82547_2: 7838 case WM_T_82571: /* reset 100us */ 7839 case WM_T_82572: 7840 case WM_T_82573: 7841 case WM_T_82574: 7842 case WM_T_82575: 7843 case WM_T_82576: 7844 case WM_T_82580: 7845 case WM_T_I350: 7846 case WM_T_I354: 7847 case WM_T_I210: 7848 case WM_T_I211: 7849 case WM_T_82583: 7850 case WM_T_80003: 7851 /* generic reset */ 7852 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 7853 CSR_WRITE_FLUSH(sc); 7854 delay(20000); 7855 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7856 CSR_WRITE_FLUSH(sc); 7857 delay(20000); 7858 7859 if ((sc->sc_type == WM_T_82541) 7860 || (sc->sc_type == WM_T_82541_2) 7861 || (sc->sc_type == WM_T_82547) 7862 || (sc->sc_type == WM_T_82547_2)) { 7863 /* workaround for igp are done in igp_reset() */ 7864 /* XXX add code to set LED after phy reset */ 7865 } 7866 break; 7867 case WM_T_ICH8: 7868 case WM_T_ICH9: 7869 case WM_T_ICH10: 7870 case WM_T_PCH: 7871 case WM_T_PCH2: 7872 case WM_T_PCH_LPT: 7873 case WM_T_PCH_SPT: 7874 /* generic reset */ 7875 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 7876 CSR_WRITE_FLUSH(sc); 7877 delay(100); 7878 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 7879 CSR_WRITE_FLUSH(sc); 7880 delay(150); 7881 break; 7882 default: 7883 panic("%s: %s: unknown type\n", device_xname(sc->sc_dev), 7884 __func__); 7885 break; 7886 } 7887 7888 /* release PHY semaphore */ 7889 switch (sc->sc_type) { 7890 case WM_T_82571: 7891 case WM_T_82572: 7892 case WM_T_82573: 7893 case WM_T_82574: 7894 case WM_T_82583: 7895 /* XXX should put sw semaphore, too */ 7896 wm_put_swsm_semaphore(sc); 7897 break; 7898 case WM_T_82575: 7899 case WM_T_82576: 7900 case WM_T_82580: 7901 case WM_T_I350: 7902 case WM_T_I354: 7903 case WM_T_I210: 7904 case WM_T_I211: 7905 case WM_T_80003: 7906 wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]); 7907 break; 7908 case WM_T_ICH8: 7909 case WM_T_ICH9: 7910 case WM_T_ICH10: 7911 case WM_T_PCH: 7912 case WM_T_PCH2: 7913 case WM_T_PCH_LPT: 7914 case WM_T_PCH_SPT: 7915 wm_put_swfwhw_semaphore(sc); 7916 break; 7917 default: 7918 /* nothing to do */ 7919 rv = 0; 7920 break; 7921 } 7922 7923 /* get_cfg_done */ 7924 wm_get_cfg_done(sc); 7925 7926 /* extra setup */ 7927 switch (sc->sc_type) { 7928 case WM_T_82542_2_0: 7929 case WM_T_82542_2_1: 7930 case WM_T_82543: 7931 case WM_T_82544: 7932 case WM_T_82540: 7933 case WM_T_82545: 7934 case WM_T_82545_3: 7935 case WM_T_82546: 7936 case WM_T_82546_3: 7937 case WM_T_82541_2: 7938 case WM_T_82547_2: 7939 case WM_T_82571: 7940 case WM_T_82572: 7941 case WM_T_82573: 7942 case WM_T_82575: 7943 case WM_T_82576: 7944 case WM_T_82580: 7945 case WM_T_I350: 7946 case WM_T_I354: 7947 case WM_T_I210: 7948 case WM_T_I211: 7949 case WM_T_80003: 7950 /* null */ 7951 break; 7952 case WM_T_82574: 7953 case WM_T_82583: 7954 wm_lplu_d0_disable(sc); 7955 break; 7956 case WM_T_82541: 7957 case WM_T_82547: 7958 /* XXX Configure actively LED after PHY reset */ 7959 break; 7960 case WM_T_ICH8: 7961 case WM_T_ICH9: 7962 case WM_T_ICH10: 7963 case WM_T_PCH: 7964 case WM_T_PCH2: 7965 case WM_T_PCH_LPT: 7966 case WM_T_PCH_SPT: 7967 /* Allow time for h/w to get to a quiescent state afer reset */ 7968 delay(10*1000); 7969 7970 if (sc->sc_type == WM_T_PCH) 7971 wm_hv_phy_workaround_ich8lan(sc); 7972 7973 if (sc->sc_type == WM_T_PCH2) 7974 wm_lv_phy_workaround_ich8lan(sc); 7975 7976 if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)) { 7977 /* 7978 * dummy read to clear the phy wakeup bit after lcd 7979 * reset 7980 */ 7981 reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC); 7982 } 7983 7984 /* 7985 * XXX Configure the LCD with th extended configuration region 7986 * in NVM 7987 */ 7988 7989 /* Disable D0 LPLU. */ 7990 if (sc->sc_type >= WM_T_PCH) /* PCH* */ 7991 wm_lplu_d0_disable_pch(sc); 7992 else 7993 wm_lplu_d0_disable(sc); /* ICH* */ 7994 break; 7995 default: 7996 panic("%s: unknown type\n", __func__); 7997 break; 7998 } 7999 } 8000 8001 /* 8002 * wm_get_phy_id_82575: 8003 * 8004 * Return PHY ID. Return -1 if it failed. 8005 */ 8006 static int 8007 wm_get_phy_id_82575(struct wm_softc *sc) 8008 { 8009 uint32_t reg; 8010 int phyid = -1; 8011 8012 /* XXX */ 8013 if ((sc->sc_flags & WM_F_SGMII) == 0) 8014 return -1; 8015 8016 if (wm_sgmii_uses_mdio(sc)) { 8017 switch (sc->sc_type) { 8018 case WM_T_82575: 8019 case WM_T_82576: 8020 reg = CSR_READ(sc, WMREG_MDIC); 8021 phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT; 8022 break; 8023 case WM_T_82580: 8024 case WM_T_I350: 8025 case WM_T_I354: 8026 case WM_T_I210: 8027 case WM_T_I211: 8028 reg = CSR_READ(sc, WMREG_MDICNFG); 8029 phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT; 8030 break; 8031 default: 8032 return -1; 8033 } 8034 } 8035 8036 return phyid; 8037 } 8038 8039 8040 /* 8041 * wm_gmii_mediainit: 8042 * 8043 * Initialize media for use on 1000BASE-T devices. 8044 */ 8045 static void 8046 wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid) 8047 { 8048 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 8049 struct mii_data *mii = &sc->sc_mii; 8050 uint32_t reg; 8051 8052 /* We have GMII. */ 8053 sc->sc_flags |= WM_F_HAS_MII; 8054 8055 if (sc->sc_type == WM_T_80003) 8056 sc->sc_tipg = TIPG_1000T_80003_DFLT; 8057 else 8058 sc->sc_tipg = TIPG_1000T_DFLT; 8059 8060 /* XXX Not for I354? FreeBSD's e1000_82575.c doesn't include it */ 8061 if ((sc->sc_type == WM_T_82580) 8062 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210) 8063 || (sc->sc_type == WM_T_I211)) { 8064 reg = CSR_READ(sc, WMREG_PHPM); 8065 reg &= ~PHPM_GO_LINK_D; 8066 CSR_WRITE(sc, WMREG_PHPM, reg); 8067 } 8068 8069 /* 8070 * Let the chip set speed/duplex on its own based on 8071 * signals from the PHY. 8072 * XXXbouyer - I'm not sure this is right for the 80003, 8073 * the em driver only sets CTRL_SLU here - but it seems to work. 8074 */ 8075 sc->sc_ctrl |= CTRL_SLU; 8076 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 8077 8078 /* Initialize our media structures and probe the GMII. */ 8079 mii->mii_ifp = ifp; 8080 8081 /* 8082 * Determine the PHY access method. 8083 * 8084 * For SGMII, use SGMII specific method. 8085 * 8086 * For some devices, we can determine the PHY access method 8087 * from sc_type. 8088 * 8089 * For ICH and PCH variants, it's difficult to determine the PHY 8090 * access method by sc_type, so use the PCI product ID for some 8091 * devices. 8092 * For other ICH8 variants, try to use igp's method. If the PHY 8093 * can't detect, then use bm's method. 8094 */ 8095 switch (prodid) { 8096 case PCI_PRODUCT_INTEL_PCH_M_LM: 8097 case PCI_PRODUCT_INTEL_PCH_M_LC: 8098 /* 82577 */ 8099 sc->sc_phytype = WMPHY_82577; 8100 break; 8101 case PCI_PRODUCT_INTEL_PCH_D_DM: 8102 case PCI_PRODUCT_INTEL_PCH_D_DC: 8103 /* 82578 */ 8104 sc->sc_phytype = WMPHY_82578; 8105 break; 8106 case PCI_PRODUCT_INTEL_PCH2_LV_LM: 8107 case PCI_PRODUCT_INTEL_PCH2_LV_V: 8108 /* 82579 */ 8109 sc->sc_phytype = WMPHY_82579; 8110 break; 8111 case PCI_PRODUCT_INTEL_82801I_BM: 8112 case PCI_PRODUCT_INTEL_82801J_R_BM_LM: 8113 case PCI_PRODUCT_INTEL_82801J_R_BM_LF: 8114 case PCI_PRODUCT_INTEL_82801J_D_BM_LM: 8115 case PCI_PRODUCT_INTEL_82801J_D_BM_LF: 8116 case PCI_PRODUCT_INTEL_82801J_R_BM_V: 8117 /* 82567 */ 8118 sc->sc_phytype = WMPHY_BM; 8119 mii->mii_readreg = wm_gmii_bm_readreg; 8120 mii->mii_writereg = wm_gmii_bm_writereg; 8121 break; 8122 default: 8123 if (((sc->sc_flags & WM_F_SGMII) != 0) 8124 && !wm_sgmii_uses_mdio(sc)){ 8125 /* SGMII */ 8126 mii->mii_readreg = wm_sgmii_readreg; 8127 mii->mii_writereg = wm_sgmii_writereg; 8128 } else if (sc->sc_type >= WM_T_80003) { 8129 /* 80003 */ 8130 mii->mii_readreg = wm_gmii_i80003_readreg; 8131 mii->mii_writereg = wm_gmii_i80003_writereg; 8132 } else if (sc->sc_type >= WM_T_I210) { 8133 /* I210 and I211 */ 8134 mii->mii_readreg = wm_gmii_gs40g_readreg; 8135 mii->mii_writereg = wm_gmii_gs40g_writereg; 8136 } else if (sc->sc_type >= WM_T_82580) { 8137 /* 82580, I350 and I354 */ 8138 sc->sc_phytype = WMPHY_82580; 8139 mii->mii_readreg = wm_gmii_82580_readreg; 8140 mii->mii_writereg = wm_gmii_82580_writereg; 8141 } else if (sc->sc_type >= WM_T_82544) { 8142 /* 82544, 0, [56], [17], 8257[1234] and 82583 */ 8143 mii->mii_readreg = wm_gmii_i82544_readreg; 8144 mii->mii_writereg = wm_gmii_i82544_writereg; 8145 } else { 8146 mii->mii_readreg = wm_gmii_i82543_readreg; 8147 mii->mii_writereg = wm_gmii_i82543_writereg; 8148 } 8149 break; 8150 } 8151 if ((sc->sc_type >= WM_T_PCH) && (sc->sc_type <= WM_T_PCH_SPT)) { 8152 /* All PCH* use _hv_ */ 8153 mii->mii_readreg = wm_gmii_hv_readreg; 8154 mii->mii_writereg = wm_gmii_hv_writereg; 8155 } 8156 mii->mii_statchg = wm_gmii_statchg; 8157 8158 wm_gmii_reset(sc); 8159 8160 sc->sc_ethercom.ec_mii = &sc->sc_mii; 8161 ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange, 8162 wm_gmii_mediastatus); 8163 8164 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576) 8165 || (sc->sc_type == WM_T_82580) 8166 || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354) 8167 || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211)) { 8168 if ((sc->sc_flags & WM_F_SGMII) == 0) { 8169 /* Attach only one port */ 8170 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, 8171 MII_OFFSET_ANY, MIIF_DOPAUSE); 8172 } else { 8173 int i, id; 8174 uint32_t ctrl_ext; 8175 8176 id = wm_get_phy_id_82575(sc); 8177 if (id != -1) { 8178 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 8179 id, MII_OFFSET_ANY, MIIF_DOPAUSE); 8180 } 8181 if ((id == -1) 8182 || (LIST_FIRST(&mii->mii_phys) == NULL)) { 8183 /* Power on sgmii phy if it is disabled */ 8184 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT); 8185 CSR_WRITE(sc, WMREG_CTRL_EXT, 8186 ctrl_ext &~ CTRL_EXT_SWDPIN(3)); 8187 CSR_WRITE_FLUSH(sc); 8188 delay(300*1000); /* XXX too long */ 8189 8190 /* from 1 to 8 */ 8191 for (i = 1; i < 8; i++) 8192 mii_attach(sc->sc_dev, &sc->sc_mii, 8193 0xffffffff, i, MII_OFFSET_ANY, 8194 MIIF_DOPAUSE); 8195 8196 /* restore previous sfp cage power state */ 8197 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext); 8198 } 8199 } 8200 } else { 8201 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 8202 MII_OFFSET_ANY, MIIF_DOPAUSE); 8203 } 8204 8205 /* 8206 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call 8207 * wm_set_mdio_slow_mode_hv() for a workaround and retry. 8208 */ 8209 if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) && 8210 (LIST_FIRST(&mii->mii_phys) == NULL)) { 8211 wm_set_mdio_slow_mode_hv(sc); 8212 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 8213 MII_OFFSET_ANY, MIIF_DOPAUSE); 8214 } 8215 8216 /* 8217 * (For ICH8 variants) 8218 * If PHY detection failed, use BM's r/w function and retry. 8219 */ 8220 if (LIST_FIRST(&mii->mii_phys) == NULL) { 8221 /* if failed, retry with *_bm_* */ 8222 mii->mii_readreg = wm_gmii_bm_readreg; 8223 mii->mii_writereg = wm_gmii_bm_writereg; 8224 8225 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 8226 MII_OFFSET_ANY, MIIF_DOPAUSE); 8227 } 8228 8229 if (LIST_FIRST(&mii->mii_phys) == NULL) { 8230 /* Any PHY wasn't find */ 8231 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 8232 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 8233 sc->sc_phytype = WMPHY_NONE; 8234 } else { 8235 /* 8236 * PHY Found! 8237 * Check PHY type. 8238 */ 8239 uint32_t model; 8240 struct mii_softc *child; 8241 8242 child = LIST_FIRST(&mii->mii_phys); 8243 model = child->mii_mpd_model; 8244 if (model == MII_MODEL_yyINTEL_I82566) 8245 sc->sc_phytype = WMPHY_IGP_3; 8246 8247 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 8248 } 8249 } 8250 8251 /* 8252 * wm_gmii_mediachange: [ifmedia interface function] 8253 * 8254 * Set hardware to newly-selected media on a 1000BASE-T device. 8255 */ 8256 static int 8257 wm_gmii_mediachange(struct ifnet *ifp) 8258 { 8259 struct wm_softc *sc = ifp->if_softc; 8260 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 8261 int rc; 8262 8263 if ((ifp->if_flags & IFF_UP) == 0) 8264 return 0; 8265 8266 sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD); 8267 sc->sc_ctrl |= CTRL_SLU; 8268 if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 8269 || (sc->sc_type > WM_T_82543)) { 8270 sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX); 8271 } else { 8272 sc->sc_ctrl &= ~CTRL_ASDE; 8273 sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX; 8274 if (ife->ifm_media & IFM_FDX) 8275 sc->sc_ctrl |= CTRL_FD; 8276 switch (IFM_SUBTYPE(ife->ifm_media)) { 8277 case IFM_10_T: 8278 sc->sc_ctrl |= CTRL_SPEED_10; 8279 break; 8280 case IFM_100_TX: 8281 sc->sc_ctrl |= CTRL_SPEED_100; 8282 break; 8283 case IFM_1000_T: 8284 sc->sc_ctrl |= CTRL_SPEED_1000; 8285 break; 8286 default: 8287 panic("wm_gmii_mediachange: bad media 0x%x", 8288 ife->ifm_media); 8289 } 8290 } 8291 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 8292 if (sc->sc_type <= WM_T_82543) 8293 wm_gmii_reset(sc); 8294 8295 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 8296 return 0; 8297 return rc; 8298 } 8299 8300 /* 8301 * wm_gmii_mediastatus: [ifmedia interface function] 8302 * 8303 * Get the current interface media status on a 1000BASE-T device. 8304 */ 8305 static void 8306 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 8307 { 8308 struct wm_softc *sc = ifp->if_softc; 8309 8310 ether_mediastatus(ifp, ifmr); 8311 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) 8312 | sc->sc_flowflags; 8313 } 8314 8315 #define MDI_IO CTRL_SWDPIN(2) 8316 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 8317 #define MDI_CLK CTRL_SWDPIN(3) 8318 8319 static void 8320 wm_i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 8321 { 8322 uint32_t i, v; 8323 8324 v = CSR_READ(sc, WMREG_CTRL); 8325 v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 8326 v |= MDI_DIR | CTRL_SWDPIO(3); 8327 8328 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 8329 if (data & i) 8330 v |= MDI_IO; 8331 else 8332 v &= ~MDI_IO; 8333 CSR_WRITE(sc, WMREG_CTRL, v); 8334 CSR_WRITE_FLUSH(sc); 8335 delay(10); 8336 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 8337 CSR_WRITE_FLUSH(sc); 8338 delay(10); 8339 CSR_WRITE(sc, WMREG_CTRL, v); 8340 CSR_WRITE_FLUSH(sc); 8341 delay(10); 8342 } 8343 } 8344 8345 static uint32_t 8346 wm_i82543_mii_recvbits(struct wm_softc *sc) 8347 { 8348 uint32_t v, i, data = 0; 8349 8350 v = CSR_READ(sc, WMREG_CTRL); 8351 v &= ~(MDI_IO | MDI_CLK | (CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 8352 v |= CTRL_SWDPIO(3); 8353 8354 CSR_WRITE(sc, WMREG_CTRL, v); 8355 CSR_WRITE_FLUSH(sc); 8356 delay(10); 8357 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 8358 CSR_WRITE_FLUSH(sc); 8359 delay(10); 8360 CSR_WRITE(sc, WMREG_CTRL, v); 8361 CSR_WRITE_FLUSH(sc); 8362 delay(10); 8363 8364 for (i = 0; i < 16; i++) { 8365 data <<= 1; 8366 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 8367 CSR_WRITE_FLUSH(sc); 8368 delay(10); 8369 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 8370 data |= 1; 8371 CSR_WRITE(sc, WMREG_CTRL, v); 8372 CSR_WRITE_FLUSH(sc); 8373 delay(10); 8374 } 8375 8376 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 8377 CSR_WRITE_FLUSH(sc); 8378 delay(10); 8379 CSR_WRITE(sc, WMREG_CTRL, v); 8380 CSR_WRITE_FLUSH(sc); 8381 delay(10); 8382 8383 return data; 8384 } 8385 8386 #undef MDI_IO 8387 #undef MDI_DIR 8388 #undef MDI_CLK 8389 8390 /* 8391 * wm_gmii_i82543_readreg: [mii interface function] 8392 * 8393 * Read a PHY register on the GMII (i82543 version). 8394 */ 8395 static int 8396 wm_gmii_i82543_readreg(device_t self, int phy, int reg) 8397 { 8398 struct wm_softc *sc = device_private(self); 8399 int rv; 8400 8401 wm_i82543_mii_sendbits(sc, 0xffffffffU, 32); 8402 wm_i82543_mii_sendbits(sc, reg | (phy << 5) | 8403 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 8404 rv = wm_i82543_mii_recvbits(sc) & 0xffff; 8405 8406 DPRINTF(WM_DEBUG_GMII, ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 8407 device_xname(sc->sc_dev), phy, reg, rv)); 8408 8409 return rv; 8410 } 8411 8412 /* 8413 * wm_gmii_i82543_writereg: [mii interface function] 8414 * 8415 * Write a PHY register on the GMII (i82543 version). 8416 */ 8417 static void 8418 wm_gmii_i82543_writereg(device_t self, int phy, int reg, int val) 8419 { 8420 struct wm_softc *sc = device_private(self); 8421 8422 wm_i82543_mii_sendbits(sc, 0xffffffffU, 32); 8423 wm_i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 8424 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 8425 (MII_COMMAND_START << 30), 32); 8426 } 8427 8428 /* 8429 * wm_gmii_i82544_readreg: [mii interface function] 8430 * 8431 * Read a PHY register on the GMII. 8432 */ 8433 static int 8434 wm_gmii_i82544_readreg(device_t self, int phy, int reg) 8435 { 8436 struct wm_softc *sc = device_private(self); 8437 uint32_t mdic = 0; 8438 int i, rv; 8439 8440 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 8441 MDIC_REGADD(reg)); 8442 8443 for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) { 8444 mdic = CSR_READ(sc, WMREG_MDIC); 8445 if (mdic & MDIC_READY) 8446 break; 8447 delay(50); 8448 } 8449 8450 if ((mdic & MDIC_READY) == 0) { 8451 log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n", 8452 device_xname(sc->sc_dev), phy, reg); 8453 rv = 0; 8454 } else if (mdic & MDIC_E) { 8455 #if 0 /* This is normal if no PHY is present. */ 8456 log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n", 8457 device_xname(sc->sc_dev), phy, reg); 8458 #endif 8459 rv = 0; 8460 } else { 8461 rv = MDIC_DATA(mdic); 8462 if (rv == 0xffff) 8463 rv = 0; 8464 } 8465 8466 return rv; 8467 } 8468 8469 /* 8470 * wm_gmii_i82544_writereg: [mii interface function] 8471 * 8472 * Write a PHY register on the GMII. 8473 */ 8474 static void 8475 wm_gmii_i82544_writereg(device_t self, int phy, int reg, int val) 8476 { 8477 struct wm_softc *sc = device_private(self); 8478 uint32_t mdic = 0; 8479 int i; 8480 8481 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 8482 MDIC_REGADD(reg) | MDIC_DATA(val)); 8483 8484 for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) { 8485 mdic = CSR_READ(sc, WMREG_MDIC); 8486 if (mdic & MDIC_READY) 8487 break; 8488 delay(50); 8489 } 8490 8491 if ((mdic & MDIC_READY) == 0) 8492 log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n", 8493 device_xname(sc->sc_dev), phy, reg); 8494 else if (mdic & MDIC_E) 8495 log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n", 8496 device_xname(sc->sc_dev), phy, reg); 8497 } 8498 8499 /* 8500 * wm_gmii_i80003_readreg: [mii interface function] 8501 * 8502 * Read a PHY register on the kumeran 8503 * This could be handled by the PHY layer if we didn't have to lock the 8504 * ressource ... 8505 */ 8506 static int 8507 wm_gmii_i80003_readreg(device_t self, int phy, int reg) 8508 { 8509 struct wm_softc *sc = device_private(self); 8510 int sem; 8511 int rv; 8512 8513 if (phy != 1) /* only one PHY on kumeran bus */ 8514 return 0; 8515 8516 sem = swfwphysem[sc->sc_funcid]; 8517 if (wm_get_swfw_semaphore(sc, sem)) { 8518 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8519 __func__); 8520 return 0; 8521 } 8522 8523 if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 8524 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT, 8525 reg >> GG82563_PAGE_SHIFT); 8526 } else { 8527 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT, 8528 reg >> GG82563_PAGE_SHIFT); 8529 } 8530 /* Wait more 200us for a bug of the ready bit in the MDIC register */ 8531 delay(200); 8532 rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS); 8533 delay(200); 8534 8535 wm_put_swfw_semaphore(sc, sem); 8536 return rv; 8537 } 8538 8539 /* 8540 * wm_gmii_i80003_writereg: [mii interface function] 8541 * 8542 * Write a PHY register on the kumeran. 8543 * This could be handled by the PHY layer if we didn't have to lock the 8544 * ressource ... 8545 */ 8546 static void 8547 wm_gmii_i80003_writereg(device_t self, int phy, int reg, int val) 8548 { 8549 struct wm_softc *sc = device_private(self); 8550 int sem; 8551 8552 if (phy != 1) /* only one PHY on kumeran bus */ 8553 return; 8554 8555 sem = swfwphysem[sc->sc_funcid]; 8556 if (wm_get_swfw_semaphore(sc, sem)) { 8557 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8558 __func__); 8559 return; 8560 } 8561 8562 if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 8563 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT, 8564 reg >> GG82563_PAGE_SHIFT); 8565 } else { 8566 wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT, 8567 reg >> GG82563_PAGE_SHIFT); 8568 } 8569 /* Wait more 200us for a bug of the ready bit in the MDIC register */ 8570 delay(200); 8571 wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val); 8572 delay(200); 8573 8574 wm_put_swfw_semaphore(sc, sem); 8575 } 8576 8577 /* 8578 * wm_gmii_bm_readreg: [mii interface function] 8579 * 8580 * Read a PHY register on the kumeran 8581 * This could be handled by the PHY layer if we didn't have to lock the 8582 * ressource ... 8583 */ 8584 static int 8585 wm_gmii_bm_readreg(device_t self, int phy, int reg) 8586 { 8587 struct wm_softc *sc = device_private(self); 8588 int sem; 8589 int rv; 8590 8591 sem = swfwphysem[sc->sc_funcid]; 8592 if (wm_get_swfw_semaphore(sc, sem)) { 8593 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8594 __func__); 8595 return 0; 8596 } 8597 8598 if (reg > BME1000_MAX_MULTI_PAGE_REG) { 8599 if (phy == 1) 8600 wm_gmii_i82544_writereg(self, phy, 8601 MII_IGPHY_PAGE_SELECT, reg); 8602 else 8603 wm_gmii_i82544_writereg(self, phy, 8604 GG82563_PHY_PAGE_SELECT, 8605 reg >> GG82563_PAGE_SHIFT); 8606 } 8607 8608 rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS); 8609 wm_put_swfw_semaphore(sc, sem); 8610 return rv; 8611 } 8612 8613 /* 8614 * wm_gmii_bm_writereg: [mii interface function] 8615 * 8616 * Write a PHY register on the kumeran. 8617 * This could be handled by the PHY layer if we didn't have to lock the 8618 * ressource ... 8619 */ 8620 static void 8621 wm_gmii_bm_writereg(device_t self, int phy, int reg, int val) 8622 { 8623 struct wm_softc *sc = device_private(self); 8624 int sem; 8625 8626 sem = swfwphysem[sc->sc_funcid]; 8627 if (wm_get_swfw_semaphore(sc, sem)) { 8628 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8629 __func__); 8630 return; 8631 } 8632 8633 if (reg > BME1000_MAX_MULTI_PAGE_REG) { 8634 if (phy == 1) 8635 wm_gmii_i82544_writereg(self, phy, 8636 MII_IGPHY_PAGE_SELECT, reg); 8637 else 8638 wm_gmii_i82544_writereg(self, phy, 8639 GG82563_PHY_PAGE_SELECT, 8640 reg >> GG82563_PAGE_SHIFT); 8641 } 8642 8643 wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val); 8644 wm_put_swfw_semaphore(sc, sem); 8645 } 8646 8647 static void 8648 wm_access_phy_wakeup_reg_bm(device_t self, int offset, int16_t *val, int rd) 8649 { 8650 struct wm_softc *sc = device_private(self); 8651 uint16_t regnum = BM_PHY_REG_NUM(offset); 8652 uint16_t wuce; 8653 8654 /* XXX Gig must be disabled for MDIO accesses to page 800 */ 8655 if (sc->sc_type == WM_T_PCH) { 8656 /* XXX e1000 driver do nothing... why? */ 8657 } 8658 8659 /* Set page 769 */ 8660 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8661 BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT); 8662 8663 wuce = wm_gmii_i82544_readreg(self, 1, BM_WUC_ENABLE_REG); 8664 8665 wuce &= ~BM_WUC_HOST_WU_BIT; 8666 wm_gmii_i82544_writereg(self, 1, BM_WUC_ENABLE_REG, 8667 wuce | BM_WUC_ENABLE_BIT); 8668 8669 /* Select page 800 */ 8670 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8671 BM_WUC_PAGE << BME1000_PAGE_SHIFT); 8672 8673 /* Write page 800 */ 8674 wm_gmii_i82544_writereg(self, 1, BM_WUC_ADDRESS_OPCODE, regnum); 8675 8676 if (rd) 8677 *val = wm_gmii_i82544_readreg(self, 1, BM_WUC_DATA_OPCODE); 8678 else 8679 wm_gmii_i82544_writereg(self, 1, BM_WUC_DATA_OPCODE, *val); 8680 8681 /* Set page 769 */ 8682 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8683 BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT); 8684 8685 wm_gmii_i82544_writereg(self, 1, BM_WUC_ENABLE_REG, wuce); 8686 } 8687 8688 /* 8689 * wm_gmii_hv_readreg: [mii interface function] 8690 * 8691 * Read a PHY register on the kumeran 8692 * This could be handled by the PHY layer if we didn't have to lock the 8693 * ressource ... 8694 */ 8695 static int 8696 wm_gmii_hv_readreg(device_t self, int phy, int reg) 8697 { 8698 struct wm_softc *sc = device_private(self); 8699 uint16_t page = BM_PHY_REG_PAGE(reg); 8700 uint16_t regnum = BM_PHY_REG_NUM(reg); 8701 uint16_t val; 8702 int rv; 8703 8704 if (wm_get_swfwhw_semaphore(sc)) { 8705 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8706 __func__); 8707 return 0; 8708 } 8709 8710 /* XXX Workaround failure in MDIO access while cable is disconnected */ 8711 if (sc->sc_phytype == WMPHY_82577) { 8712 /* XXX must write */ 8713 } 8714 8715 /* Page 800 works differently than the rest so it has its own func */ 8716 if (page == BM_WUC_PAGE) { 8717 wm_access_phy_wakeup_reg_bm(self, reg, &val, 1); 8718 return val; 8719 } 8720 8721 /* 8722 * Lower than page 768 works differently than the rest so it has its 8723 * own func 8724 */ 8725 if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) { 8726 printf("gmii_hv_readreg!!!\n"); 8727 return 0; 8728 } 8729 8730 if (regnum > BME1000_MAX_MULTI_PAGE_REG) { 8731 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8732 page << BME1000_PAGE_SHIFT); 8733 } 8734 8735 rv = wm_gmii_i82544_readreg(self, phy, regnum & IGPHY_MAXREGADDR); 8736 wm_put_swfwhw_semaphore(sc); 8737 return rv; 8738 } 8739 8740 /* 8741 * wm_gmii_hv_writereg: [mii interface function] 8742 * 8743 * Write a PHY register on the kumeran. 8744 * This could be handled by the PHY layer if we didn't have to lock the 8745 * ressource ... 8746 */ 8747 static void 8748 wm_gmii_hv_writereg(device_t self, int phy, int reg, int val) 8749 { 8750 struct wm_softc *sc = device_private(self); 8751 uint16_t page = BM_PHY_REG_PAGE(reg); 8752 uint16_t regnum = BM_PHY_REG_NUM(reg); 8753 8754 if (wm_get_swfwhw_semaphore(sc)) { 8755 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8756 __func__); 8757 return; 8758 } 8759 8760 /* XXX Workaround failure in MDIO access while cable is disconnected */ 8761 8762 /* Page 800 works differently than the rest so it has its own func */ 8763 if (page == BM_WUC_PAGE) { 8764 uint16_t tmp; 8765 8766 tmp = val; 8767 wm_access_phy_wakeup_reg_bm(self, reg, &tmp, 0); 8768 return; 8769 } 8770 8771 /* 8772 * Lower than page 768 works differently than the rest so it has its 8773 * own func 8774 */ 8775 if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) { 8776 printf("gmii_hv_writereg!!!\n"); 8777 return; 8778 } 8779 8780 /* 8781 * XXX Workaround MDIO accesses being disabled after entering IEEE 8782 * Power Down (whenever bit 11 of the PHY control register is set) 8783 */ 8784 8785 if (regnum > BME1000_MAX_MULTI_PAGE_REG) { 8786 wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT, 8787 page << BME1000_PAGE_SHIFT); 8788 } 8789 8790 wm_gmii_i82544_writereg(self, phy, regnum & IGPHY_MAXREGADDR, val); 8791 wm_put_swfwhw_semaphore(sc); 8792 } 8793 8794 /* 8795 * wm_gmii_82580_readreg: [mii interface function] 8796 * 8797 * Read a PHY register on the 82580 and I350. 8798 * This could be handled by the PHY layer if we didn't have to lock the 8799 * ressource ... 8800 */ 8801 static int 8802 wm_gmii_82580_readreg(device_t self, int phy, int reg) 8803 { 8804 struct wm_softc *sc = device_private(self); 8805 int sem; 8806 int rv; 8807 8808 sem = swfwphysem[sc->sc_funcid]; 8809 if (wm_get_swfw_semaphore(sc, sem)) { 8810 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8811 __func__); 8812 return 0; 8813 } 8814 8815 rv = wm_gmii_i82544_readreg(self, phy, reg); 8816 8817 wm_put_swfw_semaphore(sc, sem); 8818 return rv; 8819 } 8820 8821 /* 8822 * wm_gmii_82580_writereg: [mii interface function] 8823 * 8824 * Write a PHY register on the 82580 and I350. 8825 * This could be handled by the PHY layer if we didn't have to lock the 8826 * ressource ... 8827 */ 8828 static void 8829 wm_gmii_82580_writereg(device_t self, int phy, int reg, int val) 8830 { 8831 struct wm_softc *sc = device_private(self); 8832 int sem; 8833 8834 sem = swfwphysem[sc->sc_funcid]; 8835 if (wm_get_swfw_semaphore(sc, sem)) { 8836 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8837 __func__); 8838 return; 8839 } 8840 8841 wm_gmii_i82544_writereg(self, phy, reg, val); 8842 8843 wm_put_swfw_semaphore(sc, sem); 8844 } 8845 8846 /* 8847 * wm_gmii_gs40g_readreg: [mii interface function] 8848 * 8849 * Read a PHY register on the I2100 and I211. 8850 * This could be handled by the PHY layer if we didn't have to lock the 8851 * ressource ... 8852 */ 8853 static int 8854 wm_gmii_gs40g_readreg(device_t self, int phy, int reg) 8855 { 8856 struct wm_softc *sc = device_private(self); 8857 int sem; 8858 int page, offset; 8859 int rv; 8860 8861 /* Acquire semaphore */ 8862 sem = swfwphysem[sc->sc_funcid]; 8863 if (wm_get_swfw_semaphore(sc, sem)) { 8864 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8865 __func__); 8866 return 0; 8867 } 8868 8869 /* Page select */ 8870 page = reg >> GS40G_PAGE_SHIFT; 8871 wm_gmii_i82544_writereg(self, phy, GS40G_PAGE_SELECT, page); 8872 8873 /* Read reg */ 8874 offset = reg & GS40G_OFFSET_MASK; 8875 rv = wm_gmii_i82544_readreg(self, phy, offset); 8876 8877 wm_put_swfw_semaphore(sc, sem); 8878 return rv; 8879 } 8880 8881 /* 8882 * wm_gmii_gs40g_writereg: [mii interface function] 8883 * 8884 * Write a PHY register on the I210 and I211. 8885 * This could be handled by the PHY layer if we didn't have to lock the 8886 * ressource ... 8887 */ 8888 static void 8889 wm_gmii_gs40g_writereg(device_t self, int phy, int reg, int val) 8890 { 8891 struct wm_softc *sc = device_private(self); 8892 int sem; 8893 int page, offset; 8894 8895 /* Acquire semaphore */ 8896 sem = swfwphysem[sc->sc_funcid]; 8897 if (wm_get_swfw_semaphore(sc, sem)) { 8898 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 8899 __func__); 8900 return; 8901 } 8902 8903 /* Page select */ 8904 page = reg >> GS40G_PAGE_SHIFT; 8905 wm_gmii_i82544_writereg(self, phy, GS40G_PAGE_SELECT, page); 8906 8907 /* Write reg */ 8908 offset = reg & GS40G_OFFSET_MASK; 8909 wm_gmii_i82544_writereg(self, phy, offset, val); 8910 8911 /* Release semaphore */ 8912 wm_put_swfw_semaphore(sc, sem); 8913 } 8914 8915 /* 8916 * wm_gmii_statchg: [mii interface function] 8917 * 8918 * Callback from MII layer when media changes. 8919 */ 8920 static void 8921 wm_gmii_statchg(struct ifnet *ifp) 8922 { 8923 struct wm_softc *sc = ifp->if_softc; 8924 struct mii_data *mii = &sc->sc_mii; 8925 8926 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 8927 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 8928 sc->sc_fcrtl &= ~FCRTL_XONE; 8929 8930 /* 8931 * Get flow control negotiation result. 8932 */ 8933 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 8934 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 8935 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 8936 mii->mii_media_active &= ~IFM_ETH_FMASK; 8937 } 8938 8939 if (sc->sc_flowflags & IFM_FLOW) { 8940 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 8941 sc->sc_ctrl |= CTRL_TFCE; 8942 sc->sc_fcrtl |= FCRTL_XONE; 8943 } 8944 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 8945 sc->sc_ctrl |= CTRL_RFCE; 8946 } 8947 8948 if (sc->sc_mii.mii_media_active & IFM_FDX) { 8949 DPRINTF(WM_DEBUG_LINK, 8950 ("%s: LINK: statchg: FDX\n", ifp->if_xname)); 8951 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 8952 } else { 8953 DPRINTF(WM_DEBUG_LINK, 8954 ("%s: LINK: statchg: HDX\n", ifp->if_xname)); 8955 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 8956 } 8957 8958 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 8959 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 8960 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 8961 : WMREG_FCRTL, sc->sc_fcrtl); 8962 if (sc->sc_type == WM_T_80003) { 8963 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 8964 case IFM_1000_T: 8965 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL, 8966 KUMCTRLSTA_HD_CTRL_1000_DEFAULT); 8967 sc->sc_tipg = TIPG_1000T_80003_DFLT; 8968 break; 8969 default: 8970 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL, 8971 KUMCTRLSTA_HD_CTRL_10_100_DEFAULT); 8972 sc->sc_tipg = TIPG_10_100_80003_DFLT; 8973 break; 8974 } 8975 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 8976 } 8977 } 8978 8979 /* 8980 * wm_kmrn_readreg: 8981 * 8982 * Read a kumeran register 8983 */ 8984 static int 8985 wm_kmrn_readreg(struct wm_softc *sc, int reg) 8986 { 8987 int rv; 8988 8989 if (sc->sc_flags & WM_F_LOCK_SWFW) { 8990 if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) { 8991 aprint_error_dev(sc->sc_dev, 8992 "%s: failed to get semaphore\n", __func__); 8993 return 0; 8994 } 8995 } else if (sc->sc_flags & WM_F_LOCK_EXTCNF) { 8996 if (wm_get_swfwhw_semaphore(sc)) { 8997 aprint_error_dev(sc->sc_dev, 8998 "%s: failed to get semaphore\n", __func__); 8999 return 0; 9000 } 9001 } 9002 9003 CSR_WRITE(sc, WMREG_KUMCTRLSTA, 9004 ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | 9005 KUMCTRLSTA_REN); 9006 CSR_WRITE_FLUSH(sc); 9007 delay(2); 9008 9009 rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK; 9010 9011 if (sc->sc_flags & WM_F_LOCK_SWFW) 9012 wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM); 9013 else if (sc->sc_flags & WM_F_LOCK_EXTCNF) 9014 wm_put_swfwhw_semaphore(sc); 9015 9016 return rv; 9017 } 9018 9019 /* 9020 * wm_kmrn_writereg: 9021 * 9022 * Write a kumeran register 9023 */ 9024 static void 9025 wm_kmrn_writereg(struct wm_softc *sc, int reg, int val) 9026 { 9027 9028 if (sc->sc_flags & WM_F_LOCK_SWFW) { 9029 if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) { 9030 aprint_error_dev(sc->sc_dev, 9031 "%s: failed to get semaphore\n", __func__); 9032 return; 9033 } 9034 } else if (sc->sc_flags & WM_F_LOCK_EXTCNF) { 9035 if (wm_get_swfwhw_semaphore(sc)) { 9036 aprint_error_dev(sc->sc_dev, 9037 "%s: failed to get semaphore\n", __func__); 9038 return; 9039 } 9040 } 9041 9042 CSR_WRITE(sc, WMREG_KUMCTRLSTA, 9043 ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | 9044 (val & KUMCTRLSTA_MASK)); 9045 9046 if (sc->sc_flags & WM_F_LOCK_SWFW) 9047 wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM); 9048 else if (sc->sc_flags & WM_F_LOCK_EXTCNF) 9049 wm_put_swfwhw_semaphore(sc); 9050 } 9051 9052 /* SGMII related */ 9053 9054 /* 9055 * wm_sgmii_uses_mdio 9056 * 9057 * Check whether the transaction is to the internal PHY or the external 9058 * MDIO interface. Return true if it's MDIO. 9059 */ 9060 static bool 9061 wm_sgmii_uses_mdio(struct wm_softc *sc) 9062 { 9063 uint32_t reg; 9064 bool ismdio = false; 9065 9066 switch (sc->sc_type) { 9067 case WM_T_82575: 9068 case WM_T_82576: 9069 reg = CSR_READ(sc, WMREG_MDIC); 9070 ismdio = ((reg & MDIC_DEST) != 0); 9071 break; 9072 case WM_T_82580: 9073 case WM_T_I350: 9074 case WM_T_I354: 9075 case WM_T_I210: 9076 case WM_T_I211: 9077 reg = CSR_READ(sc, WMREG_MDICNFG); 9078 ismdio = ((reg & MDICNFG_DEST) != 0); 9079 break; 9080 default: 9081 break; 9082 } 9083 9084 return ismdio; 9085 } 9086 9087 /* 9088 * wm_sgmii_readreg: [mii interface function] 9089 * 9090 * Read a PHY register on the SGMII 9091 * This could be handled by the PHY layer if we didn't have to lock the 9092 * ressource ... 9093 */ 9094 static int 9095 wm_sgmii_readreg(device_t self, int phy, int reg) 9096 { 9097 struct wm_softc *sc = device_private(self); 9098 uint32_t i2ccmd; 9099 int i, rv; 9100 9101 if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) { 9102 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 9103 __func__); 9104 return 0; 9105 } 9106 9107 i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT) 9108 | (phy << I2CCMD_PHY_ADDR_SHIFT) 9109 | I2CCMD_OPCODE_READ; 9110 CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd); 9111 9112 /* Poll the ready bit */ 9113 for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) { 9114 delay(50); 9115 i2ccmd = CSR_READ(sc, WMREG_I2CCMD); 9116 if (i2ccmd & I2CCMD_READY) 9117 break; 9118 } 9119 if ((i2ccmd & I2CCMD_READY) == 0) 9120 aprint_error_dev(sc->sc_dev, "I2CCMD Read did not complete\n"); 9121 if ((i2ccmd & I2CCMD_ERROR) != 0) 9122 aprint_error_dev(sc->sc_dev, "I2CCMD Error bit set\n"); 9123 9124 rv = ((i2ccmd >> 8) & 0x00ff) | ((i2ccmd << 8) & 0xff00); 9125 9126 wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]); 9127 return rv; 9128 } 9129 9130 /* 9131 * wm_sgmii_writereg: [mii interface function] 9132 * 9133 * Write a PHY register on the SGMII. 9134 * This could be handled by the PHY layer if we didn't have to lock the 9135 * ressource ... 9136 */ 9137 static void 9138 wm_sgmii_writereg(device_t self, int phy, int reg, int val) 9139 { 9140 struct wm_softc *sc = device_private(self); 9141 uint32_t i2ccmd; 9142 int i; 9143 int val_swapped; 9144 9145 if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) { 9146 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 9147 __func__); 9148 return; 9149 } 9150 /* Swap the data bytes for the I2C interface */ 9151 val_swapped = ((val >> 8) & 0x00FF) | ((val << 8) & 0xFF00); 9152 i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT) 9153 | (phy << I2CCMD_PHY_ADDR_SHIFT) 9154 | I2CCMD_OPCODE_WRITE | val_swapped; 9155 CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd); 9156 9157 /* Poll the ready bit */ 9158 for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) { 9159 delay(50); 9160 i2ccmd = CSR_READ(sc, WMREG_I2CCMD); 9161 if (i2ccmd & I2CCMD_READY) 9162 break; 9163 } 9164 if ((i2ccmd & I2CCMD_READY) == 0) 9165 aprint_error_dev(sc->sc_dev, "I2CCMD Write did not complete\n"); 9166 if ((i2ccmd & I2CCMD_ERROR) != 0) 9167 aprint_error_dev(sc->sc_dev, "I2CCMD Error bit set\n"); 9168 9169 wm_put_swfw_semaphore(sc, SWFW_PHY0_SM); 9170 } 9171 9172 /* TBI related */ 9173 9174 /* 9175 * wm_tbi_mediainit: 9176 * 9177 * Initialize media for use on 1000BASE-X devices. 9178 */ 9179 static void 9180 wm_tbi_mediainit(struct wm_softc *sc) 9181 { 9182 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 9183 const char *sep = ""; 9184 9185 if (sc->sc_type < WM_T_82543) 9186 sc->sc_tipg = TIPG_WM_DFLT; 9187 else 9188 sc->sc_tipg = TIPG_LG_DFLT; 9189 9190 sc->sc_tbi_serdes_anegticks = 5; 9191 9192 /* Initialize our media structures */ 9193 sc->sc_mii.mii_ifp = ifp; 9194 sc->sc_ethercom.ec_mii = &sc->sc_mii; 9195 9196 if ((sc->sc_type >= WM_T_82575) 9197 && (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) 9198 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, 9199 wm_serdes_mediachange, wm_serdes_mediastatus); 9200 else 9201 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, 9202 wm_tbi_mediachange, wm_tbi_mediastatus); 9203 9204 /* 9205 * SWD Pins: 9206 * 9207 * 0 = Link LED (output) 9208 * 1 = Loss Of Signal (input) 9209 */ 9210 sc->sc_ctrl |= CTRL_SWDPIO(0); 9211 9212 /* XXX Perhaps this is only for TBI */ 9213 if (sc->sc_mediatype != WM_MEDIATYPE_SERDES) 9214 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 9215 9216 if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) 9217 sc->sc_ctrl &= ~CTRL_LRST; 9218 9219 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9220 9221 #define ADD(ss, mm, dd) \ 9222 do { \ 9223 aprint_normal("%s%s", sep, ss); \ 9224 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | (mm), (dd), NULL); \ 9225 sep = ", "; \ 9226 } while (/*CONSTCOND*/0) 9227 9228 aprint_normal_dev(sc->sc_dev, ""); 9229 9230 /* Only 82545 is LX */ 9231 if (sc->sc_type == WM_T_82545) { 9232 ADD("1000baseLX", IFM_1000_LX, ANAR_X_HD); 9233 ADD("1000baseLX-FDX", IFM_1000_LX | IFM_FDX, ANAR_X_FD); 9234 } else { 9235 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 9236 ADD("1000baseSX-FDX", IFM_1000_SX | IFM_FDX, ANAR_X_FD); 9237 } 9238 ADD("auto", IFM_AUTO, ANAR_X_FD | ANAR_X_HD); 9239 aprint_normal("\n"); 9240 9241 #undef ADD 9242 9243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 9244 } 9245 9246 /* 9247 * wm_tbi_mediachange: [ifmedia interface function] 9248 * 9249 * Set hardware to newly-selected media on a 1000BASE-X device. 9250 */ 9251 static int 9252 wm_tbi_mediachange(struct ifnet *ifp) 9253 { 9254 struct wm_softc *sc = ifp->if_softc; 9255 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 9256 uint32_t status; 9257 int i; 9258 9259 if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) { 9260 /* XXX need some work for >= 82571 and < 82575 */ 9261 if (sc->sc_type < WM_T_82575) 9262 return 0; 9263 } 9264 9265 if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572) 9266 || (sc->sc_type >= WM_T_82575)) 9267 CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK); 9268 9269 sc->sc_ctrl &= ~CTRL_LRST; 9270 sc->sc_txcw = TXCW_ANE; 9271 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 9272 sc->sc_txcw |= TXCW_FD | TXCW_HD; 9273 else if (ife->ifm_media & IFM_FDX) 9274 sc->sc_txcw |= TXCW_FD; 9275 else 9276 sc->sc_txcw |= TXCW_HD; 9277 9278 if ((sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 9279 sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE; 9280 9281 DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n", 9282 device_xname(sc->sc_dev), sc->sc_txcw)); 9283 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 9284 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9285 CSR_WRITE_FLUSH(sc); 9286 delay(1000); 9287 9288 i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1); 9289 DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i)); 9290 9291 /* 9292 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the 9293 * optics detect a signal, 0 if they don't. 9294 */ 9295 if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) { 9296 /* Have signal; wait for the link to come up. */ 9297 for (i = 0; i < WM_LINKUP_TIMEOUT; i++) { 9298 delay(10000); 9299 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 9300 break; 9301 } 9302 9303 DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n", 9304 device_xname(sc->sc_dev),i)); 9305 9306 status = CSR_READ(sc, WMREG_STATUS); 9307 DPRINTF(WM_DEBUG_LINK, 9308 ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n", 9309 device_xname(sc->sc_dev),status, STATUS_LU)); 9310 if (status & STATUS_LU) { 9311 /* Link is up. */ 9312 DPRINTF(WM_DEBUG_LINK, 9313 ("%s: LINK: set media -> link up %s\n", 9314 device_xname(sc->sc_dev), 9315 (status & STATUS_FD) ? "FDX" : "HDX")); 9316 9317 /* 9318 * NOTE: CTRL will update TFCE and RFCE automatically, 9319 * so we should update sc->sc_ctrl 9320 */ 9321 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL); 9322 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 9323 sc->sc_fcrtl &= ~FCRTL_XONE; 9324 if (status & STATUS_FD) 9325 sc->sc_tctl |= 9326 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 9327 else 9328 sc->sc_tctl |= 9329 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 9330 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 9331 sc->sc_fcrtl |= FCRTL_XONE; 9332 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 9333 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 9334 WMREG_OLD_FCRTL : WMREG_FCRTL, 9335 sc->sc_fcrtl); 9336 sc->sc_tbi_linkup = 1; 9337 } else { 9338 if (i == WM_LINKUP_TIMEOUT) 9339 wm_check_for_link(sc); 9340 /* Link is down. */ 9341 DPRINTF(WM_DEBUG_LINK, 9342 ("%s: LINK: set media -> link down\n", 9343 device_xname(sc->sc_dev))); 9344 sc->sc_tbi_linkup = 0; 9345 } 9346 } else { 9347 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 9348 device_xname(sc->sc_dev))); 9349 sc->sc_tbi_linkup = 0; 9350 } 9351 9352 wm_tbi_serdes_set_linkled(sc); 9353 9354 return 0; 9355 } 9356 9357 /* 9358 * wm_tbi_mediastatus: [ifmedia interface function] 9359 * 9360 * Get the current interface media status on a 1000BASE-X device. 9361 */ 9362 static void 9363 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 9364 { 9365 struct wm_softc *sc = ifp->if_softc; 9366 uint32_t ctrl, status; 9367 9368 ifmr->ifm_status = IFM_AVALID; 9369 ifmr->ifm_active = IFM_ETHER; 9370 9371 status = CSR_READ(sc, WMREG_STATUS); 9372 if ((status & STATUS_LU) == 0) { 9373 ifmr->ifm_active |= IFM_NONE; 9374 return; 9375 } 9376 9377 ifmr->ifm_status |= IFM_ACTIVE; 9378 /* Only 82545 is LX */ 9379 if (sc->sc_type == WM_T_82545) 9380 ifmr->ifm_active |= IFM_1000_LX; 9381 else 9382 ifmr->ifm_active |= IFM_1000_SX; 9383 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 9384 ifmr->ifm_active |= IFM_FDX; 9385 else 9386 ifmr->ifm_active |= IFM_HDX; 9387 ctrl = CSR_READ(sc, WMREG_CTRL); 9388 if (ctrl & CTRL_RFCE) 9389 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 9390 if (ctrl & CTRL_TFCE) 9391 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 9392 } 9393 9394 /* XXX TBI only */ 9395 static int 9396 wm_check_for_link(struct wm_softc *sc) 9397 { 9398 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 9399 uint32_t rxcw; 9400 uint32_t ctrl; 9401 uint32_t status; 9402 uint32_t sig; 9403 9404 if (sc->sc_mediatype == WM_MEDIATYPE_SERDES) { 9405 /* XXX need some work for >= 82571 */ 9406 if (sc->sc_type >= WM_T_82571) { 9407 sc->sc_tbi_linkup = 1; 9408 return 0; 9409 } 9410 } 9411 9412 rxcw = CSR_READ(sc, WMREG_RXCW); 9413 ctrl = CSR_READ(sc, WMREG_CTRL); 9414 status = CSR_READ(sc, WMREG_STATUS); 9415 9416 sig = (sc->sc_type > WM_T_82544) ? CTRL_SWDPIN(1) : 0; 9417 9418 DPRINTF(WM_DEBUG_LINK, 9419 ("%s: %s: sig = %d, status_lu = %d, rxcw_c = %d\n", 9420 device_xname(sc->sc_dev), __func__, 9421 ((ctrl & CTRL_SWDPIN(1)) == sig), 9422 ((status & STATUS_LU) != 0), ((rxcw & RXCW_C) != 0))); 9423 9424 /* 9425 * SWDPIN LU RXCW 9426 * 0 0 0 9427 * 0 0 1 (should not happen) 9428 * 0 1 0 (should not happen) 9429 * 0 1 1 (should not happen) 9430 * 1 0 0 Disable autonego and force linkup 9431 * 1 0 1 got /C/ but not linkup yet 9432 * 1 1 0 (linkup) 9433 * 1 1 1 If IFM_AUTO, back to autonego 9434 * 9435 */ 9436 if (((ctrl & CTRL_SWDPIN(1)) == sig) 9437 && ((status & STATUS_LU) == 0) 9438 && ((rxcw & RXCW_C) == 0)) { 9439 DPRINTF(WM_DEBUG_LINK, ("%s: force linkup and fullduplex\n", 9440 __func__)); 9441 sc->sc_tbi_linkup = 0; 9442 /* Disable auto-negotiation in the TXCW register */ 9443 CSR_WRITE(sc, WMREG_TXCW, (sc->sc_txcw & ~TXCW_ANE)); 9444 9445 /* 9446 * Force link-up and also force full-duplex. 9447 * 9448 * NOTE: CTRL was updated TFCE and RFCE automatically, 9449 * so we should update sc->sc_ctrl 9450 */ 9451 sc->sc_ctrl = ctrl | CTRL_SLU | CTRL_FD; 9452 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9453 } else if (((status & STATUS_LU) != 0) 9454 && ((rxcw & RXCW_C) != 0) 9455 && (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)) { 9456 sc->sc_tbi_linkup = 1; 9457 DPRINTF(WM_DEBUG_LINK, ("%s: go back to autonego\n", 9458 __func__)); 9459 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 9460 CSR_WRITE(sc, WMREG_CTRL, (ctrl & ~CTRL_SLU)); 9461 } else if (((ctrl & CTRL_SWDPIN(1)) == sig) 9462 && ((rxcw & RXCW_C) != 0)) { 9463 DPRINTF(WM_DEBUG_LINK, ("/C/")); 9464 } else { 9465 DPRINTF(WM_DEBUG_LINK, ("%s: %x,%x,%x\n", __func__, rxcw, ctrl, 9466 status)); 9467 } 9468 9469 return 0; 9470 } 9471 9472 /* 9473 * wm_tbi_tick: 9474 * 9475 * Check the link on TBI devices. 9476 * This function acts as mii_tick(). 9477 */ 9478 static void 9479 wm_tbi_tick(struct wm_softc *sc) 9480 { 9481 struct mii_data *mii = &sc->sc_mii; 9482 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 9483 uint32_t status; 9484 9485 KASSERT(WM_CORE_LOCKED(sc)); 9486 9487 status = CSR_READ(sc, WMREG_STATUS); 9488 9489 /* XXX is this needed? */ 9490 (void)CSR_READ(sc, WMREG_RXCW); 9491 (void)CSR_READ(sc, WMREG_CTRL); 9492 9493 /* set link status */ 9494 if ((status & STATUS_LU) == 0) { 9495 DPRINTF(WM_DEBUG_LINK, 9496 ("%s: LINK: checklink -> down\n", 9497 device_xname(sc->sc_dev))); 9498 sc->sc_tbi_linkup = 0; 9499 } else if (sc->sc_tbi_linkup == 0) { 9500 DPRINTF(WM_DEBUG_LINK, 9501 ("%s: LINK: checklink -> up %s\n", 9502 device_xname(sc->sc_dev), 9503 (status & STATUS_FD) ? "FDX" : "HDX")); 9504 sc->sc_tbi_linkup = 1; 9505 sc->sc_tbi_serdes_ticks = 0; 9506 } 9507 9508 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) == 0) 9509 goto setled; 9510 9511 if ((status & STATUS_LU) == 0) { 9512 sc->sc_tbi_linkup = 0; 9513 /* If the timer expired, retry autonegotiation */ 9514 if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 9515 && (++sc->sc_tbi_serdes_ticks 9516 >= sc->sc_tbi_serdes_anegticks)) { 9517 DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n")); 9518 sc->sc_tbi_serdes_ticks = 0; 9519 /* 9520 * Reset the link, and let autonegotiation do 9521 * its thing 9522 */ 9523 sc->sc_ctrl |= CTRL_LRST; 9524 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9525 CSR_WRITE_FLUSH(sc); 9526 delay(1000); 9527 sc->sc_ctrl &= ~CTRL_LRST; 9528 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9529 CSR_WRITE_FLUSH(sc); 9530 delay(1000); 9531 CSR_WRITE(sc, WMREG_TXCW, 9532 sc->sc_txcw & ~TXCW_ANE); 9533 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 9534 } 9535 } 9536 9537 setled: 9538 wm_tbi_serdes_set_linkled(sc); 9539 } 9540 9541 /* SERDES related */ 9542 static void 9543 wm_serdes_power_up_link_82575(struct wm_softc *sc) 9544 { 9545 uint32_t reg; 9546 9547 if ((sc->sc_mediatype != WM_MEDIATYPE_SERDES) 9548 && ((sc->sc_flags & WM_F_SGMII) == 0)) 9549 return; 9550 9551 reg = CSR_READ(sc, WMREG_PCS_CFG); 9552 reg |= PCS_CFG_PCS_EN; 9553 CSR_WRITE(sc, WMREG_PCS_CFG, reg); 9554 9555 reg = CSR_READ(sc, WMREG_CTRL_EXT); 9556 reg &= ~CTRL_EXT_SWDPIN(3); 9557 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 9558 CSR_WRITE_FLUSH(sc); 9559 } 9560 9561 static int 9562 wm_serdes_mediachange(struct ifnet *ifp) 9563 { 9564 struct wm_softc *sc = ifp->if_softc; 9565 bool pcs_autoneg = true; /* XXX */ 9566 uint32_t ctrl_ext, pcs_lctl, reg; 9567 9568 /* XXX Currently, this function is not called on 8257[12] */ 9569 if ((sc->sc_type == WM_T_82571) || (sc->sc_type == WM_T_82572) 9570 || (sc->sc_type >= WM_T_82575)) 9571 CSR_WRITE(sc, WMREG_SCTL, SCTL_DISABLE_SERDES_LOOPBACK); 9572 9573 wm_serdes_power_up_link_82575(sc); 9574 9575 sc->sc_ctrl |= CTRL_SLU; 9576 9577 if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)) 9578 sc->sc_ctrl |= CTRL_SWDPIN(0) | CTRL_SWDPIN(1); 9579 9580 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT); 9581 pcs_lctl = CSR_READ(sc, WMREG_PCS_LCTL); 9582 switch (ctrl_ext & CTRL_EXT_LINK_MODE_MASK) { 9583 case CTRL_EXT_LINK_MODE_SGMII: 9584 pcs_autoneg = true; 9585 pcs_lctl &= ~PCS_LCTL_AN_TIMEOUT; 9586 break; 9587 case CTRL_EXT_LINK_MODE_1000KX: 9588 pcs_autoneg = false; 9589 /* FALLTHROUGH */ 9590 default: 9591 if ((sc->sc_type == WM_T_82575) 9592 || (sc->sc_type == WM_T_82576)) { 9593 if ((sc->sc_flags & WM_F_PCS_DIS_AUTONEGO) != 0) 9594 pcs_autoneg = false; 9595 } 9596 sc->sc_ctrl |= CTRL_SPEED_1000 | CTRL_FRCSPD | CTRL_FD 9597 | CTRL_FRCFDX; 9598 pcs_lctl |= PCS_LCTL_FSV_1000 | PCS_LCTL_FDV_FULL; 9599 } 9600 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 9601 9602 if (pcs_autoneg) { 9603 pcs_lctl |= PCS_LCTL_AN_ENABLE | PCS_LCTL_AN_RESTART; 9604 pcs_lctl &= ~PCS_LCTL_FORCE_FC; 9605 9606 reg = CSR_READ(sc, WMREG_PCS_ANADV); 9607 reg &= ~(TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE); 9608 reg |= TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE; 9609 CSR_WRITE(sc, WMREG_PCS_ANADV, reg); 9610 } else 9611 pcs_lctl |= PCS_LCTL_FSD | PCS_LCTL_FORCE_FC; 9612 9613 CSR_WRITE(sc, WMREG_PCS_LCTL, pcs_lctl); 9614 9615 9616 return 0; 9617 } 9618 9619 static void 9620 wm_serdes_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 9621 { 9622 struct wm_softc *sc = ifp->if_softc; 9623 struct mii_data *mii = &sc->sc_mii; 9624 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 9625 uint32_t pcs_adv, pcs_lpab, reg; 9626 9627 ifmr->ifm_status = IFM_AVALID; 9628 ifmr->ifm_active = IFM_ETHER; 9629 9630 /* Check PCS */ 9631 reg = CSR_READ(sc, WMREG_PCS_LSTS); 9632 if ((reg & PCS_LSTS_LINKOK) == 0) { 9633 ifmr->ifm_active |= IFM_NONE; 9634 sc->sc_tbi_linkup = 0; 9635 goto setled; 9636 } 9637 9638 sc->sc_tbi_linkup = 1; 9639 ifmr->ifm_status |= IFM_ACTIVE; 9640 ifmr->ifm_active |= IFM_1000_SX; /* XXX */ 9641 if ((reg & PCS_LSTS_FDX) != 0) 9642 ifmr->ifm_active |= IFM_FDX; 9643 else 9644 ifmr->ifm_active |= IFM_HDX; 9645 mii->mii_media_active &= ~IFM_ETH_FMASK; 9646 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 9647 /* Check flow */ 9648 reg = CSR_READ(sc, WMREG_PCS_LSTS); 9649 if ((reg & PCS_LSTS_AN_COMP) == 0) { 9650 DPRINTF(WM_DEBUG_LINK, ("XXX LINKOK but not ACOMP\n")); 9651 goto setled; 9652 } 9653 pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV); 9654 pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB); 9655 DPRINTF(WM_DEBUG_LINK, 9656 ("XXX AN result(2) %08x, %08x\n", pcs_adv, pcs_lpab)); 9657 if ((pcs_adv & TXCW_SYM_PAUSE) 9658 && (pcs_lpab & TXCW_SYM_PAUSE)) { 9659 mii->mii_media_active |= IFM_FLOW 9660 | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 9661 } else if (((pcs_adv & TXCW_SYM_PAUSE) == 0) 9662 && (pcs_adv & TXCW_ASYM_PAUSE) 9663 && (pcs_lpab & TXCW_SYM_PAUSE) 9664 && (pcs_lpab & TXCW_ASYM_PAUSE)) { 9665 mii->mii_media_active |= IFM_FLOW 9666 | IFM_ETH_TXPAUSE; 9667 } else if ((pcs_adv & TXCW_SYM_PAUSE) 9668 && (pcs_adv & TXCW_ASYM_PAUSE) 9669 && ((pcs_lpab & TXCW_SYM_PAUSE) == 0) 9670 && (pcs_lpab & TXCW_ASYM_PAUSE)) { 9671 mii->mii_media_active |= IFM_FLOW 9672 | IFM_ETH_RXPAUSE; 9673 } else { 9674 } 9675 } 9676 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) 9677 | (mii->mii_media_active & IFM_ETH_FMASK); 9678 setled: 9679 wm_tbi_serdes_set_linkled(sc); 9680 } 9681 9682 /* 9683 * wm_serdes_tick: 9684 * 9685 * Check the link on serdes devices. 9686 */ 9687 static void 9688 wm_serdes_tick(struct wm_softc *sc) 9689 { 9690 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 9691 struct mii_data *mii = &sc->sc_mii; 9692 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 9693 uint32_t reg; 9694 9695 KASSERT(WM_CORE_LOCKED(sc)); 9696 9697 mii->mii_media_status = IFM_AVALID; 9698 mii->mii_media_active = IFM_ETHER; 9699 9700 /* Check PCS */ 9701 reg = CSR_READ(sc, WMREG_PCS_LSTS); 9702 if ((reg & PCS_LSTS_LINKOK) != 0) { 9703 mii->mii_media_status |= IFM_ACTIVE; 9704 sc->sc_tbi_linkup = 1; 9705 sc->sc_tbi_serdes_ticks = 0; 9706 mii->mii_media_active |= IFM_1000_SX; /* XXX */ 9707 if ((reg & PCS_LSTS_FDX) != 0) 9708 mii->mii_media_active |= IFM_FDX; 9709 else 9710 mii->mii_media_active |= IFM_HDX; 9711 } else { 9712 mii->mii_media_status |= IFM_NONE; 9713 sc->sc_tbi_linkup = 0; 9714 /* If the timer expired, retry autonegotiation */ 9715 if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) 9716 && (++sc->sc_tbi_serdes_ticks 9717 >= sc->sc_tbi_serdes_anegticks)) { 9718 DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n")); 9719 sc->sc_tbi_serdes_ticks = 0; 9720 /* XXX */ 9721 wm_serdes_mediachange(ifp); 9722 } 9723 } 9724 9725 wm_tbi_serdes_set_linkled(sc); 9726 } 9727 9728 /* SFP related */ 9729 9730 static int 9731 wm_sfp_read_data_byte(struct wm_softc *sc, uint16_t offset, uint8_t *data) 9732 { 9733 uint32_t i2ccmd; 9734 int i; 9735 9736 i2ccmd = (offset << I2CCMD_REG_ADDR_SHIFT) | I2CCMD_OPCODE_READ; 9737 CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd); 9738 9739 /* Poll the ready bit */ 9740 for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) { 9741 delay(50); 9742 i2ccmd = CSR_READ(sc, WMREG_I2CCMD); 9743 if (i2ccmd & I2CCMD_READY) 9744 break; 9745 } 9746 if ((i2ccmd & I2CCMD_READY) == 0) 9747 return -1; 9748 if ((i2ccmd & I2CCMD_ERROR) != 0) 9749 return -1; 9750 9751 *data = i2ccmd & 0x00ff; 9752 9753 return 0; 9754 } 9755 9756 static uint32_t 9757 wm_sfp_get_media_type(struct wm_softc *sc) 9758 { 9759 uint32_t ctrl_ext; 9760 uint8_t val = 0; 9761 int timeout = 3; 9762 uint32_t mediatype = WM_MEDIATYPE_UNKNOWN; 9763 int rv = -1; 9764 9765 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT); 9766 ctrl_ext &= ~CTRL_EXT_SWDPIN(3); 9767 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_I2C_ENA); 9768 CSR_WRITE_FLUSH(sc); 9769 9770 /* Read SFP module data */ 9771 while (timeout) { 9772 rv = wm_sfp_read_data_byte(sc, SFF_SFP_ID_OFF, &val); 9773 if (rv == 0) 9774 break; 9775 delay(100*1000); /* XXX too big */ 9776 timeout--; 9777 } 9778 if (rv != 0) 9779 goto out; 9780 switch (val) { 9781 case SFF_SFP_ID_SFF: 9782 aprint_normal_dev(sc->sc_dev, 9783 "Module/Connector soldered to board\n"); 9784 break; 9785 case SFF_SFP_ID_SFP: 9786 aprint_normal_dev(sc->sc_dev, "SFP\n"); 9787 break; 9788 case SFF_SFP_ID_UNKNOWN: 9789 goto out; 9790 default: 9791 break; 9792 } 9793 9794 rv = wm_sfp_read_data_byte(sc, SFF_SFP_ETH_FLAGS_OFF, &val); 9795 if (rv != 0) { 9796 goto out; 9797 } 9798 9799 if ((val & (SFF_SFP_ETH_FLAGS_1000SX | SFF_SFP_ETH_FLAGS_1000LX)) != 0) 9800 mediatype = WM_MEDIATYPE_SERDES; 9801 else if ((val & SFF_SFP_ETH_FLAGS_1000T) != 0){ 9802 sc->sc_flags |= WM_F_SGMII; 9803 mediatype = WM_MEDIATYPE_COPPER; 9804 } else if ((val & SFF_SFP_ETH_FLAGS_100FX) != 0){ 9805 sc->sc_flags |= WM_F_SGMII; 9806 mediatype = WM_MEDIATYPE_SERDES; 9807 } 9808 9809 out: 9810 /* Restore I2C interface setting */ 9811 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext); 9812 9813 return mediatype; 9814 } 9815 /* 9816 * NVM related. 9817 * Microwire, SPI (w/wo EERD) and Flash. 9818 */ 9819 9820 /* Both spi and uwire */ 9821 9822 /* 9823 * wm_eeprom_sendbits: 9824 * 9825 * Send a series of bits to the EEPROM. 9826 */ 9827 static void 9828 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 9829 { 9830 uint32_t reg; 9831 int x; 9832 9833 reg = CSR_READ(sc, WMREG_EECD); 9834 9835 for (x = nbits; x > 0; x--) { 9836 if (bits & (1U << (x - 1))) 9837 reg |= EECD_DI; 9838 else 9839 reg &= ~EECD_DI; 9840 CSR_WRITE(sc, WMREG_EECD, reg); 9841 CSR_WRITE_FLUSH(sc); 9842 delay(2); 9843 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 9844 CSR_WRITE_FLUSH(sc); 9845 delay(2); 9846 CSR_WRITE(sc, WMREG_EECD, reg); 9847 CSR_WRITE_FLUSH(sc); 9848 delay(2); 9849 } 9850 } 9851 9852 /* 9853 * wm_eeprom_recvbits: 9854 * 9855 * Receive a series of bits from the EEPROM. 9856 */ 9857 static void 9858 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 9859 { 9860 uint32_t reg, val; 9861 int x; 9862 9863 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 9864 9865 val = 0; 9866 for (x = nbits; x > 0; x--) { 9867 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 9868 CSR_WRITE_FLUSH(sc); 9869 delay(2); 9870 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 9871 val |= (1U << (x - 1)); 9872 CSR_WRITE(sc, WMREG_EECD, reg); 9873 CSR_WRITE_FLUSH(sc); 9874 delay(2); 9875 } 9876 *valp = val; 9877 } 9878 9879 /* Microwire */ 9880 9881 /* 9882 * wm_nvm_read_uwire: 9883 * 9884 * Read a word from the EEPROM using the MicroWire protocol. 9885 */ 9886 static int 9887 wm_nvm_read_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 9888 { 9889 uint32_t reg, val; 9890 int i; 9891 9892 for (i = 0; i < wordcnt; i++) { 9893 /* Clear SK and DI. */ 9894 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 9895 CSR_WRITE(sc, WMREG_EECD, reg); 9896 9897 /* 9898 * XXX: workaround for a bug in qemu-0.12.x and prior 9899 * and Xen. 9900 * 9901 * We use this workaround only for 82540 because qemu's 9902 * e1000 act as 82540. 9903 */ 9904 if (sc->sc_type == WM_T_82540) { 9905 reg |= EECD_SK; 9906 CSR_WRITE(sc, WMREG_EECD, reg); 9907 reg &= ~EECD_SK; 9908 CSR_WRITE(sc, WMREG_EECD, reg); 9909 CSR_WRITE_FLUSH(sc); 9910 delay(2); 9911 } 9912 /* XXX: end of workaround */ 9913 9914 /* Set CHIP SELECT. */ 9915 reg |= EECD_CS; 9916 CSR_WRITE(sc, WMREG_EECD, reg); 9917 CSR_WRITE_FLUSH(sc); 9918 delay(2); 9919 9920 /* Shift in the READ command. */ 9921 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 9922 9923 /* Shift in address. */ 9924 wm_eeprom_sendbits(sc, word + i, sc->sc_nvm_addrbits); 9925 9926 /* Shift out the data. */ 9927 wm_eeprom_recvbits(sc, &val, 16); 9928 data[i] = val & 0xffff; 9929 9930 /* Clear CHIP SELECT. */ 9931 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 9932 CSR_WRITE(sc, WMREG_EECD, reg); 9933 CSR_WRITE_FLUSH(sc); 9934 delay(2); 9935 } 9936 9937 return 0; 9938 } 9939 9940 /* SPI */ 9941 9942 /* 9943 * Set SPI and FLASH related information from the EECD register. 9944 * For 82541 and 82547, the word size is taken from EEPROM. 9945 */ 9946 static int 9947 wm_nvm_set_addrbits_size_eecd(struct wm_softc *sc) 9948 { 9949 int size; 9950 uint32_t reg; 9951 uint16_t data; 9952 9953 reg = CSR_READ(sc, WMREG_EECD); 9954 sc->sc_nvm_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 9955 9956 /* Read the size of NVM from EECD by default */ 9957 size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK); 9958 switch (sc->sc_type) { 9959 case WM_T_82541: 9960 case WM_T_82541_2: 9961 case WM_T_82547: 9962 case WM_T_82547_2: 9963 /* Set dummy value to access EEPROM */ 9964 sc->sc_nvm_wordsize = 64; 9965 wm_nvm_read(sc, NVM_OFF_EEPROM_SIZE, 1, &data); 9966 reg = data; 9967 size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK); 9968 if (size == 0) 9969 size = 6; /* 64 word size */ 9970 else 9971 size += NVM_WORD_SIZE_BASE_SHIFT + 1; 9972 break; 9973 case WM_T_80003: 9974 case WM_T_82571: 9975 case WM_T_82572: 9976 case WM_T_82573: /* SPI case */ 9977 case WM_T_82574: /* SPI case */ 9978 case WM_T_82583: /* SPI case */ 9979 size += NVM_WORD_SIZE_BASE_SHIFT; 9980 if (size > 14) 9981 size = 14; 9982 break; 9983 case WM_T_82575: 9984 case WM_T_82576: 9985 case WM_T_82580: 9986 case WM_T_I350: 9987 case WM_T_I354: 9988 case WM_T_I210: 9989 case WM_T_I211: 9990 size += NVM_WORD_SIZE_BASE_SHIFT; 9991 if (size > 15) 9992 size = 15; 9993 break; 9994 default: 9995 aprint_error_dev(sc->sc_dev, 9996 "%s: unknown device(%d)?\n", __func__, sc->sc_type); 9997 return -1; 9998 break; 9999 } 10000 10001 sc->sc_nvm_wordsize = 1 << size; 10002 10003 return 0; 10004 } 10005 10006 /* 10007 * wm_nvm_ready_spi: 10008 * 10009 * Wait for a SPI EEPROM to be ready for commands. 10010 */ 10011 static int 10012 wm_nvm_ready_spi(struct wm_softc *sc) 10013 { 10014 uint32_t val; 10015 int usec; 10016 10017 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 10018 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 10019 wm_eeprom_recvbits(sc, &val, 8); 10020 if ((val & SPI_SR_RDY) == 0) 10021 break; 10022 } 10023 if (usec >= SPI_MAX_RETRIES) { 10024 aprint_error_dev(sc->sc_dev,"EEPROM failed to become ready\n"); 10025 return 1; 10026 } 10027 return 0; 10028 } 10029 10030 /* 10031 * wm_nvm_read_spi: 10032 * 10033 * Read a work from the EEPROM using the SPI protocol. 10034 */ 10035 static int 10036 wm_nvm_read_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 10037 { 10038 uint32_t reg, val; 10039 int i; 10040 uint8_t opc; 10041 10042 /* Clear SK and CS. */ 10043 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 10044 CSR_WRITE(sc, WMREG_EECD, reg); 10045 CSR_WRITE_FLUSH(sc); 10046 delay(2); 10047 10048 if (wm_nvm_ready_spi(sc)) 10049 return 1; 10050 10051 /* Toggle CS to flush commands. */ 10052 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 10053 CSR_WRITE_FLUSH(sc); 10054 delay(2); 10055 CSR_WRITE(sc, WMREG_EECD, reg); 10056 CSR_WRITE_FLUSH(sc); 10057 delay(2); 10058 10059 opc = SPI_OPC_READ; 10060 if (sc->sc_nvm_addrbits == 8 && word >= 128) 10061 opc |= SPI_OPC_A8; 10062 10063 wm_eeprom_sendbits(sc, opc, 8); 10064 wm_eeprom_sendbits(sc, word << 1, sc->sc_nvm_addrbits); 10065 10066 for (i = 0; i < wordcnt; i++) { 10067 wm_eeprom_recvbits(sc, &val, 16); 10068 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 10069 } 10070 10071 /* Raise CS and clear SK. */ 10072 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 10073 CSR_WRITE(sc, WMREG_EECD, reg); 10074 CSR_WRITE_FLUSH(sc); 10075 delay(2); 10076 10077 return 0; 10078 } 10079 10080 /* Using with EERD */ 10081 10082 static int 10083 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw) 10084 { 10085 uint32_t attempts = 100000; 10086 uint32_t i, reg = 0; 10087 int32_t done = -1; 10088 10089 for (i = 0; i < attempts; i++) { 10090 reg = CSR_READ(sc, rw); 10091 10092 if (reg & EERD_DONE) { 10093 done = 0; 10094 break; 10095 } 10096 delay(5); 10097 } 10098 10099 return done; 10100 } 10101 10102 static int 10103 wm_nvm_read_eerd(struct wm_softc *sc, int offset, int wordcnt, 10104 uint16_t *data) 10105 { 10106 int i, eerd = 0; 10107 int error = 0; 10108 10109 for (i = 0; i < wordcnt; i++) { 10110 eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START; 10111 10112 CSR_WRITE(sc, WMREG_EERD, eerd); 10113 error = wm_poll_eerd_eewr_done(sc, WMREG_EERD); 10114 if (error != 0) 10115 break; 10116 10117 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT); 10118 } 10119 10120 return error; 10121 } 10122 10123 /* Flash */ 10124 10125 static int 10126 wm_nvm_valid_bank_detect_ich8lan(struct wm_softc *sc, unsigned int *bank) 10127 { 10128 uint32_t eecd; 10129 uint32_t act_offset = ICH_NVM_SIG_WORD * 2 + 1; 10130 uint32_t bank1_offset = sc->sc_ich8_flash_bank_size * sizeof(uint16_t); 10131 uint8_t sig_byte = 0; 10132 10133 switch (sc->sc_type) { 10134 case WM_T_PCH_SPT: 10135 /* 10136 * In SPT, read from the CTRL_EXT reg instead of accessing the 10137 * sector valid bits from the NVM. 10138 */ 10139 *bank = CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_NVMVS; 10140 if ((*bank == 0) || (*bank == 1)) { 10141 aprint_error_dev(sc->sc_dev, 10142 "%s: no valid NVM bank present\n", 10143 __func__); 10144 return -1; 10145 } else { 10146 *bank = *bank - 2; 10147 return 0; 10148 } 10149 case WM_T_ICH8: 10150 case WM_T_ICH9: 10151 eecd = CSR_READ(sc, WMREG_EECD); 10152 if ((eecd & EECD_SEC1VAL_VALMASK) == EECD_SEC1VAL_VALMASK) { 10153 *bank = ((eecd & EECD_SEC1VAL) != 0) ? 1 : 0; 10154 return 0; 10155 } 10156 /* FALLTHROUGH */ 10157 default: 10158 /* Default to 0 */ 10159 *bank = 0; 10160 10161 /* Check bank 0 */ 10162 wm_read_ich8_byte(sc, act_offset, &sig_byte); 10163 if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) { 10164 *bank = 0; 10165 return 0; 10166 } 10167 10168 /* Check bank 1 */ 10169 wm_read_ich8_byte(sc, act_offset + bank1_offset, 10170 &sig_byte); 10171 if ((sig_byte & ICH_NVM_VALID_SIG_MASK) == ICH_NVM_SIG_VALUE) { 10172 *bank = 1; 10173 return 0; 10174 } 10175 } 10176 10177 DPRINTF(WM_DEBUG_NVM, ("%s: No valid NVM bank present\n", 10178 device_xname(sc->sc_dev))); 10179 return -1; 10180 } 10181 10182 /****************************************************************************** 10183 * This function does initial flash setup so that a new read/write/erase cycle 10184 * can be started. 10185 * 10186 * sc - The pointer to the hw structure 10187 ****************************************************************************/ 10188 static int32_t 10189 wm_ich8_cycle_init(struct wm_softc *sc) 10190 { 10191 uint16_t hsfsts; 10192 int32_t error = 1; 10193 int32_t i = 0; 10194 10195 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 10196 10197 /* May be check the Flash Des Valid bit in Hw status */ 10198 if ((hsfsts & HSFSTS_FLDVAL) == 0) { 10199 return error; 10200 } 10201 10202 /* Clear FCERR in Hw status by writing 1 */ 10203 /* Clear DAEL in Hw status by writing a 1 */ 10204 hsfsts |= HSFSTS_ERR | HSFSTS_DAEL; 10205 10206 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 10207 10208 /* 10209 * Either we should have a hardware SPI cycle in progress bit to check 10210 * against, in order to start a new cycle or FDONE bit should be 10211 * changed in the hardware so that it is 1 after harware reset, which 10212 * can then be used as an indication whether a cycle is in progress or 10213 * has been completed .. we should also have some software semaphore 10214 * mechanism to guard FDONE or the cycle in progress bit so that two 10215 * threads access to those bits can be sequentiallized or a way so that 10216 * 2 threads dont start the cycle at the same time 10217 */ 10218 10219 if ((hsfsts & HSFSTS_FLINPRO) == 0) { 10220 /* 10221 * There is no cycle running at present, so we can start a 10222 * cycle 10223 */ 10224 10225 /* Begin by setting Flash Cycle Done. */ 10226 hsfsts |= HSFSTS_DONE; 10227 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 10228 error = 0; 10229 } else { 10230 /* 10231 * otherwise poll for sometime so the current cycle has a 10232 * chance to end before giving up. 10233 */ 10234 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 10235 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 10236 if ((hsfsts & HSFSTS_FLINPRO) == 0) { 10237 error = 0; 10238 break; 10239 } 10240 delay(1); 10241 } 10242 if (error == 0) { 10243 /* 10244 * Successful in waiting for previous cycle to timeout, 10245 * now set the Flash Cycle Done. 10246 */ 10247 hsfsts |= HSFSTS_DONE; 10248 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFSTS, hsfsts); 10249 } 10250 } 10251 return error; 10252 } 10253 10254 /****************************************************************************** 10255 * This function starts a flash cycle and waits for its completion 10256 * 10257 * sc - The pointer to the hw structure 10258 ****************************************************************************/ 10259 static int32_t 10260 wm_ich8_flash_cycle(struct wm_softc *sc, uint32_t timeout) 10261 { 10262 uint16_t hsflctl; 10263 uint16_t hsfsts; 10264 int32_t error = 1; 10265 uint32_t i = 0; 10266 10267 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 10268 hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL); 10269 hsflctl |= HSFCTL_GO; 10270 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl); 10271 10272 /* Wait till FDONE bit is set to 1 */ 10273 do { 10274 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 10275 if (hsfsts & HSFSTS_DONE) 10276 break; 10277 delay(1); 10278 i++; 10279 } while (i < timeout); 10280 if ((hsfsts & HSFSTS_DONE) == 1 && (hsfsts & HSFSTS_ERR) == 0) 10281 error = 0; 10282 10283 return error; 10284 } 10285 10286 /****************************************************************************** 10287 * Reads a byte or (d)word from the NVM using the ICH8 flash access registers. 10288 * 10289 * sc - The pointer to the hw structure 10290 * index - The index of the byte or word to read. 10291 * size - Size of data to read, 1=byte 2=word, 4=dword 10292 * data - Pointer to the word to store the value read. 10293 *****************************************************************************/ 10294 static int32_t 10295 wm_read_ich8_data(struct wm_softc *sc, uint32_t index, 10296 uint32_t size, uint32_t *data) 10297 { 10298 uint16_t hsfsts; 10299 uint16_t hsflctl; 10300 uint32_t flash_linear_address; 10301 uint32_t flash_data = 0; 10302 int32_t error = 1; 10303 int32_t count = 0; 10304 10305 if (size < 1 || size > 4 || data == 0x0 || 10306 index > ICH_FLASH_LINEAR_ADDR_MASK) 10307 return error; 10308 10309 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10310 sc->sc_ich8_flash_base; 10311 10312 do { 10313 delay(1); 10314 /* Steps */ 10315 error = wm_ich8_cycle_init(sc); 10316 if (error) 10317 break; 10318 10319 hsflctl = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFCTL); 10320 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10321 hsflctl |= ((size - 1) << HSFCTL_BCOUNT_SHIFT) 10322 & HSFCTL_BCOUNT_MASK; 10323 hsflctl |= ICH_CYCLE_READ << HSFCTL_CYCLE_SHIFT; 10324 if (sc->sc_type == WM_T_PCH_SPT) { 10325 /* 10326 * In SPT, This register is in Lan memory space, not 10327 * flash. Therefore, only 32 bit access is supported. 10328 */ 10329 ICH8_FLASH_WRITE32(sc, ICH_FLASH_HSFCTL, 10330 (uint32_t)hsflctl); 10331 } else 10332 ICH8_FLASH_WRITE16(sc, ICH_FLASH_HSFCTL, hsflctl); 10333 10334 /* 10335 * Write the last 24 bits of index into Flash Linear address 10336 * field in Flash Address 10337 */ 10338 /* TODO: TBD maybe check the index against the size of flash */ 10339 10340 ICH8_FLASH_WRITE32(sc, ICH_FLASH_FADDR, flash_linear_address); 10341 10342 error = wm_ich8_flash_cycle(sc, ICH_FLASH_COMMAND_TIMEOUT); 10343 10344 /* 10345 * Check if FCERR is set to 1, if set to 1, clear it and try 10346 * the whole sequence a few more times, else read in (shift in) 10347 * the Flash Data0, the order is least significant byte first 10348 * msb to lsb 10349 */ 10350 if (error == 0) { 10351 flash_data = ICH8_FLASH_READ32(sc, ICH_FLASH_FDATA0); 10352 if (size == 1) 10353 *data = (uint8_t)(flash_data & 0x000000FF); 10354 else if (size == 2) 10355 *data = (uint16_t)(flash_data & 0x0000FFFF); 10356 else if (size == 4) 10357 *data = (uint32_t)flash_data; 10358 break; 10359 } else { 10360 /* 10361 * If we've gotten here, then things are probably 10362 * completely hosed, but if the error condition is 10363 * detected, it won't hurt to give it another try... 10364 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 10365 */ 10366 hsfsts = ICH8_FLASH_READ16(sc, ICH_FLASH_HSFSTS); 10367 if (hsfsts & HSFSTS_ERR) { 10368 /* Repeat for some time before giving up. */ 10369 continue; 10370 } else if ((hsfsts & HSFSTS_DONE) == 0) 10371 break; 10372 } 10373 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10374 10375 return error; 10376 } 10377 10378 /****************************************************************************** 10379 * Reads a single byte from the NVM using the ICH8 flash access registers. 10380 * 10381 * sc - pointer to wm_hw structure 10382 * index - The index of the byte to read. 10383 * data - Pointer to a byte to store the value read. 10384 *****************************************************************************/ 10385 static int32_t 10386 wm_read_ich8_byte(struct wm_softc *sc, uint32_t index, uint8_t* data) 10387 { 10388 int32_t status; 10389 uint32_t word = 0; 10390 10391 status = wm_read_ich8_data(sc, index, 1, &word); 10392 if (status == 0) 10393 *data = (uint8_t)word; 10394 else 10395 *data = 0; 10396 10397 return status; 10398 } 10399 10400 /****************************************************************************** 10401 * Reads a word from the NVM using the ICH8 flash access registers. 10402 * 10403 * sc - pointer to wm_hw structure 10404 * index - The starting byte index of the word to read. 10405 * data - Pointer to a word to store the value read. 10406 *****************************************************************************/ 10407 static int32_t 10408 wm_read_ich8_word(struct wm_softc *sc, uint32_t index, uint16_t *data) 10409 { 10410 int32_t status; 10411 uint32_t word = 0; 10412 10413 status = wm_read_ich8_data(sc, index, 2, &word); 10414 if (status == 0) 10415 *data = (uint16_t)word; 10416 else 10417 *data = 0; 10418 10419 return status; 10420 } 10421 10422 /****************************************************************************** 10423 * Reads a dword from the NVM using the ICH8 flash access registers. 10424 * 10425 * sc - pointer to wm_hw structure 10426 * index - The starting byte index of the word to read. 10427 * data - Pointer to a word to store the value read. 10428 *****************************************************************************/ 10429 static int32_t 10430 wm_read_ich8_dword(struct wm_softc *sc, uint32_t index, uint32_t *data) 10431 { 10432 int32_t status; 10433 10434 status = wm_read_ich8_data(sc, index, 4, data); 10435 return status; 10436 } 10437 10438 /****************************************************************************** 10439 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 10440 * register. 10441 * 10442 * sc - Struct containing variables accessed by shared code 10443 * offset - offset of word in the EEPROM to read 10444 * data - word read from the EEPROM 10445 * words - number of words to read 10446 *****************************************************************************/ 10447 static int 10448 wm_nvm_read_ich8(struct wm_softc *sc, int offset, int words, uint16_t *data) 10449 { 10450 int32_t error = 0; 10451 uint32_t flash_bank = 0; 10452 uint32_t act_offset = 0; 10453 uint32_t bank_offset = 0; 10454 uint16_t word = 0; 10455 uint16_t i = 0; 10456 10457 /* 10458 * We need to know which is the valid flash bank. In the event 10459 * that we didn't allocate eeprom_shadow_ram, we may not be 10460 * managing flash_bank. So it cannot be trusted and needs 10461 * to be updated with each read. 10462 */ 10463 error = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank); 10464 if (error) { 10465 DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n", 10466 device_xname(sc->sc_dev))); 10467 flash_bank = 0; 10468 } 10469 10470 /* 10471 * Adjust offset appropriately if we're on bank 1 - adjust for word 10472 * size 10473 */ 10474 bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2); 10475 10476 error = wm_get_swfwhw_semaphore(sc); 10477 if (error) { 10478 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 10479 __func__); 10480 return error; 10481 } 10482 10483 for (i = 0; i < words; i++) { 10484 /* The NVM part needs a byte offset, hence * 2 */ 10485 act_offset = bank_offset + ((offset + i) * 2); 10486 error = wm_read_ich8_word(sc, act_offset, &word); 10487 if (error) { 10488 aprint_error_dev(sc->sc_dev, 10489 "%s: failed to read NVM\n", __func__); 10490 break; 10491 } 10492 data[i] = word; 10493 } 10494 10495 wm_put_swfwhw_semaphore(sc); 10496 return error; 10497 } 10498 10499 /****************************************************************************** 10500 * Reads a 16 bit word or words from the EEPROM using the SPT's flash access 10501 * register. 10502 * 10503 * sc - Struct containing variables accessed by shared code 10504 * offset - offset of word in the EEPROM to read 10505 * data - word read from the EEPROM 10506 * words - number of words to read 10507 *****************************************************************************/ 10508 static int 10509 wm_nvm_read_spt(struct wm_softc *sc, int offset, int words, uint16_t *data) 10510 { 10511 int32_t error = 0; 10512 uint32_t flash_bank = 0; 10513 uint32_t act_offset = 0; 10514 uint32_t bank_offset = 0; 10515 uint32_t dword = 0; 10516 uint16_t i = 0; 10517 10518 /* 10519 * We need to know which is the valid flash bank. In the event 10520 * that we didn't allocate eeprom_shadow_ram, we may not be 10521 * managing flash_bank. So it cannot be trusted and needs 10522 * to be updated with each read. 10523 */ 10524 error = wm_nvm_valid_bank_detect_ich8lan(sc, &flash_bank); 10525 if (error) { 10526 DPRINTF(WM_DEBUG_NVM, ("%s: failed to detect NVM bank\n", 10527 device_xname(sc->sc_dev))); 10528 flash_bank = 0; 10529 } 10530 10531 /* 10532 * Adjust offset appropriately if we're on bank 1 - adjust for word 10533 * size 10534 */ 10535 bank_offset = flash_bank * (sc->sc_ich8_flash_bank_size * 2); 10536 10537 error = wm_get_swfwhw_semaphore(sc); 10538 if (error) { 10539 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 10540 __func__); 10541 return error; 10542 } 10543 10544 for (i = 0; i < words; i++) { 10545 /* The NVM part needs a byte offset, hence * 2 */ 10546 act_offset = bank_offset + ((offset + i) * 2); 10547 /* but we must read dword aligned, so mask ... */ 10548 error = wm_read_ich8_dword(sc, act_offset & ~0x3, &dword); 10549 if (error) { 10550 aprint_error_dev(sc->sc_dev, 10551 "%s: failed to read NVM\n", __func__); 10552 break; 10553 } 10554 /* ... and pick out low or high word */ 10555 if ((act_offset & 0x2) == 0) 10556 data[i] = (uint16_t)(dword & 0xFFFF); 10557 else 10558 data[i] = (uint16_t)((dword >> 16) & 0xFFFF); 10559 } 10560 10561 wm_put_swfwhw_semaphore(sc); 10562 return error; 10563 } 10564 10565 /* iNVM */ 10566 10567 static int 10568 wm_nvm_read_word_invm(struct wm_softc *sc, uint16_t address, uint16_t *data) 10569 { 10570 int32_t rv = 0; 10571 uint32_t invm_dword; 10572 uint16_t i; 10573 uint8_t record_type, word_address; 10574 10575 for (i = 0; i < INVM_SIZE; i++) { 10576 invm_dword = CSR_READ(sc, WM_INVM_DATA_REG(i)); 10577 /* Get record type */ 10578 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 10579 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 10580 break; 10581 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 10582 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 10583 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 10584 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 10585 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 10586 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 10587 if (word_address == address) { 10588 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 10589 rv = 0; 10590 break; 10591 } 10592 } 10593 } 10594 10595 return rv; 10596 } 10597 10598 static int 10599 wm_nvm_read_invm(struct wm_softc *sc, int offset, int words, uint16_t *data) 10600 { 10601 int rv = 0; 10602 int i; 10603 10604 for (i = 0; i < words; i++) { 10605 switch (offset + i) { 10606 case NVM_OFF_MACADDR: 10607 case NVM_OFF_MACADDR1: 10608 case NVM_OFF_MACADDR2: 10609 rv = wm_nvm_read_word_invm(sc, offset + i, &data[i]); 10610 if (rv != 0) { 10611 data[i] = 0xffff; 10612 rv = -1; 10613 } 10614 break; 10615 case NVM_OFF_CFG2: 10616 rv = wm_nvm_read_word_invm(sc, offset, data); 10617 if (rv != 0) { 10618 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 10619 rv = 0; 10620 } 10621 break; 10622 case NVM_OFF_CFG4: 10623 rv = wm_nvm_read_word_invm(sc, offset, data); 10624 if (rv != 0) { 10625 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 10626 rv = 0; 10627 } 10628 break; 10629 case NVM_OFF_LED_1_CFG: 10630 rv = wm_nvm_read_word_invm(sc, offset, data); 10631 if (rv != 0) { 10632 *data = NVM_LED_1_CFG_DEFAULT_I211; 10633 rv = 0; 10634 } 10635 break; 10636 case NVM_OFF_LED_0_2_CFG: 10637 rv = wm_nvm_read_word_invm(sc, offset, data); 10638 if (rv != 0) { 10639 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 10640 rv = 0; 10641 } 10642 break; 10643 case NVM_OFF_ID_LED_SETTINGS: 10644 rv = wm_nvm_read_word_invm(sc, offset, data); 10645 if (rv != 0) { 10646 *data = ID_LED_RESERVED_FFFF; 10647 rv = 0; 10648 } 10649 break; 10650 default: 10651 DPRINTF(WM_DEBUG_NVM, 10652 ("NVM word 0x%02x is not mapped.\n", offset)); 10653 *data = NVM_RESERVED_WORD; 10654 break; 10655 } 10656 } 10657 10658 return rv; 10659 } 10660 10661 /* Lock, detecting NVM type, validate checksum, version and read */ 10662 10663 /* 10664 * wm_nvm_acquire: 10665 * 10666 * Perform the EEPROM handshake required on some chips. 10667 */ 10668 static int 10669 wm_nvm_acquire(struct wm_softc *sc) 10670 { 10671 uint32_t reg; 10672 int x; 10673 int ret = 0; 10674 10675 /* always success */ 10676 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 10677 return 0; 10678 10679 if (sc->sc_flags & WM_F_LOCK_EXTCNF) { 10680 ret = wm_get_swfwhw_semaphore(sc); 10681 } else if (sc->sc_flags & WM_F_LOCK_SWFW) { 10682 /* This will also do wm_get_swsm_semaphore() if needed */ 10683 ret = wm_get_swfw_semaphore(sc, SWFW_EEP_SM); 10684 } else if (sc->sc_flags & WM_F_LOCK_SWSM) { 10685 ret = wm_get_swsm_semaphore(sc); 10686 } 10687 10688 if (ret) { 10689 aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n", 10690 __func__); 10691 return 1; 10692 } 10693 10694 if (sc->sc_flags & WM_F_LOCK_EECD) { 10695 reg = CSR_READ(sc, WMREG_EECD); 10696 10697 /* Request EEPROM access. */ 10698 reg |= EECD_EE_REQ; 10699 CSR_WRITE(sc, WMREG_EECD, reg); 10700 10701 /* ..and wait for it to be granted. */ 10702 for (x = 0; x < 1000; x++) { 10703 reg = CSR_READ(sc, WMREG_EECD); 10704 if (reg & EECD_EE_GNT) 10705 break; 10706 delay(5); 10707 } 10708 if ((reg & EECD_EE_GNT) == 0) { 10709 aprint_error_dev(sc->sc_dev, 10710 "could not acquire EEPROM GNT\n"); 10711 reg &= ~EECD_EE_REQ; 10712 CSR_WRITE(sc, WMREG_EECD, reg); 10713 if (sc->sc_flags & WM_F_LOCK_EXTCNF) 10714 wm_put_swfwhw_semaphore(sc); 10715 if (sc->sc_flags & WM_F_LOCK_SWFW) 10716 wm_put_swfw_semaphore(sc, SWFW_EEP_SM); 10717 else if (sc->sc_flags & WM_F_LOCK_SWSM) 10718 wm_put_swsm_semaphore(sc); 10719 return 1; 10720 } 10721 } 10722 10723 return 0; 10724 } 10725 10726 /* 10727 * wm_nvm_release: 10728 * 10729 * Release the EEPROM mutex. 10730 */ 10731 static void 10732 wm_nvm_release(struct wm_softc *sc) 10733 { 10734 uint32_t reg; 10735 10736 /* always success */ 10737 if ((sc->sc_flags & WM_F_EEPROM_FLASH) != 0) 10738 return; 10739 10740 if (sc->sc_flags & WM_F_LOCK_EECD) { 10741 reg = CSR_READ(sc, WMREG_EECD); 10742 reg &= ~EECD_EE_REQ; 10743 CSR_WRITE(sc, WMREG_EECD, reg); 10744 } 10745 10746 if (sc->sc_flags & WM_F_LOCK_EXTCNF) 10747 wm_put_swfwhw_semaphore(sc); 10748 if (sc->sc_flags & WM_F_LOCK_SWFW) 10749 wm_put_swfw_semaphore(sc, SWFW_EEP_SM); 10750 else if (sc->sc_flags & WM_F_LOCK_SWSM) 10751 wm_put_swsm_semaphore(sc); 10752 } 10753 10754 static int 10755 wm_nvm_is_onboard_eeprom(struct wm_softc *sc) 10756 { 10757 uint32_t eecd = 0; 10758 10759 if (sc->sc_type == WM_T_82573 || sc->sc_type == WM_T_82574 10760 || sc->sc_type == WM_T_82583) { 10761 eecd = CSR_READ(sc, WMREG_EECD); 10762 10763 /* Isolate bits 15 & 16 */ 10764 eecd = ((eecd >> 15) & 0x03); 10765 10766 /* If both bits are set, device is Flash type */ 10767 if (eecd == 0x03) 10768 return 0; 10769 } 10770 return 1; 10771 } 10772 10773 static int 10774 wm_nvm_get_flash_presence_i210(struct wm_softc *sc) 10775 { 10776 uint32_t eec; 10777 10778 eec = CSR_READ(sc, WMREG_EEC); 10779 if ((eec & EEC_FLASH_DETECTED) != 0) 10780 return 1; 10781 10782 return 0; 10783 } 10784 10785 /* 10786 * wm_nvm_validate_checksum 10787 * 10788 * The checksum is defined as the sum of the first 64 (16 bit) words. 10789 */ 10790 static int 10791 wm_nvm_validate_checksum(struct wm_softc *sc) 10792 { 10793 uint16_t checksum; 10794 uint16_t eeprom_data; 10795 #ifdef WM_DEBUG 10796 uint16_t csum_wordaddr, valid_checksum; 10797 #endif 10798 int i; 10799 10800 checksum = 0; 10801 10802 /* Don't check for I211 */ 10803 if (sc->sc_type == WM_T_I211) 10804 return 0; 10805 10806 #ifdef WM_DEBUG 10807 if (sc->sc_type == WM_T_PCH_LPT) { 10808 csum_wordaddr = NVM_OFF_COMPAT; 10809 valid_checksum = NVM_COMPAT_VALID_CHECKSUM; 10810 } else { 10811 csum_wordaddr = NVM_OFF_FUTURE_INIT_WORD1; 10812 valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM; 10813 } 10814 10815 /* Dump EEPROM image for debug */ 10816 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 10817 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 10818 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) { 10819 /* XXX PCH_SPT? */ 10820 wm_nvm_read(sc, csum_wordaddr, 1, &eeprom_data); 10821 if ((eeprom_data & valid_checksum) == 0) { 10822 DPRINTF(WM_DEBUG_NVM, 10823 ("%s: NVM need to be updated (%04x != %04x)\n", 10824 device_xname(sc->sc_dev), eeprom_data, 10825 valid_checksum)); 10826 } 10827 } 10828 10829 if ((wm_debug & WM_DEBUG_NVM) != 0) { 10830 printf("%s: NVM dump:\n", device_xname(sc->sc_dev)); 10831 for (i = 0; i < NVM_SIZE; i++) { 10832 if (wm_nvm_read(sc, i, 1, &eeprom_data)) 10833 printf("XXXX "); 10834 else 10835 printf("%04hx ", eeprom_data); 10836 if (i % 8 == 7) 10837 printf("\n"); 10838 } 10839 } 10840 10841 #endif /* WM_DEBUG */ 10842 10843 for (i = 0; i < NVM_SIZE; i++) { 10844 if (wm_nvm_read(sc, i, 1, &eeprom_data)) 10845 return 1; 10846 checksum += eeprom_data; 10847 } 10848 10849 if (checksum != (uint16_t) NVM_CHECKSUM) { 10850 #ifdef WM_DEBUG 10851 printf("%s: NVM checksum mismatch (%04x != %04x)\n", 10852 device_xname(sc->sc_dev), checksum, NVM_CHECKSUM); 10853 #endif 10854 } 10855 10856 return 0; 10857 } 10858 10859 static void 10860 wm_nvm_version_invm(struct wm_softc *sc) 10861 { 10862 uint32_t dword; 10863 10864 /* 10865 * Linux's code to decode version is very strange, so we don't 10866 * obey that algorithm and just use word 61 as the document. 10867 * Perhaps it's not perfect though... 10868 * 10869 * Example: 10870 * 10871 * Word61: 00800030 -> Version 0.6 (I211 spec update notes about 0.6) 10872 */ 10873 dword = CSR_READ(sc, WM_INVM_DATA_REG(61)); 10874 dword = __SHIFTOUT(dword, INVM_VER_1); 10875 sc->sc_nvm_ver_major = __SHIFTOUT(dword, INVM_MAJOR); 10876 sc->sc_nvm_ver_minor = __SHIFTOUT(dword, INVM_MINOR); 10877 } 10878 10879 static void 10880 wm_nvm_version(struct wm_softc *sc) 10881 { 10882 uint16_t major, minor, build, patch; 10883 uint16_t uid0, uid1; 10884 uint16_t nvm_data; 10885 uint16_t off; 10886 bool check_version = false; 10887 bool check_optionrom = false; 10888 bool have_build = false; 10889 10890 /* 10891 * Version format: 10892 * 10893 * XYYZ 10894 * X0YZ 10895 * X0YY 10896 * 10897 * Example: 10898 * 10899 * 82571 0x50a2 5.10.2? (the spec update notes about 5.6-5.10) 10900 * 82571 0x50a6 5.10.6? 10901 * 82572 0x506a 5.6.10? 10902 * 82572EI 0x5069 5.6.9? 10903 * 82574L 0x1080 1.8.0? (the spec update notes about 2.1.4) 10904 * 0x2013 2.1.3? 10905 * 82583 0x10a0 1.10.0? (document says it's default vaule) 10906 */ 10907 wm_nvm_read(sc, NVM_OFF_IMAGE_UID1, 1, &uid1); 10908 switch (sc->sc_type) { 10909 case WM_T_82571: 10910 case WM_T_82572: 10911 case WM_T_82574: 10912 case WM_T_82583: 10913 check_version = true; 10914 check_optionrom = true; 10915 have_build = true; 10916 break; 10917 case WM_T_82575: 10918 case WM_T_82576: 10919 case WM_T_82580: 10920 if ((uid1 & NVM_MAJOR_MASK) != NVM_UID_VALID) 10921 check_version = true; 10922 break; 10923 case WM_T_I211: 10924 wm_nvm_version_invm(sc); 10925 goto printver; 10926 case WM_T_I210: 10927 if (!wm_nvm_get_flash_presence_i210(sc)) { 10928 wm_nvm_version_invm(sc); 10929 goto printver; 10930 } 10931 /* FALLTHROUGH */ 10932 case WM_T_I350: 10933 case WM_T_I354: 10934 check_version = true; 10935 check_optionrom = true; 10936 break; 10937 default: 10938 return; 10939 } 10940 if (check_version) { 10941 wm_nvm_read(sc, NVM_OFF_VERSION, 1, &nvm_data); 10942 major = (nvm_data & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 10943 if (have_build || ((nvm_data & 0x0f00) != 0x0000)) { 10944 minor = (nvm_data & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 10945 build = nvm_data & NVM_BUILD_MASK; 10946 have_build = true; 10947 } else 10948 minor = nvm_data & 0x00ff; 10949 10950 /* Decimal */ 10951 minor = (minor / 16) * 10 + (minor % 16); 10952 sc->sc_nvm_ver_major = major; 10953 sc->sc_nvm_ver_minor = minor; 10954 10955 printver: 10956 aprint_verbose(", version %d.%d", sc->sc_nvm_ver_major, 10957 sc->sc_nvm_ver_minor); 10958 if (have_build) { 10959 sc->sc_nvm_ver_build = build; 10960 aprint_verbose(".%d", build); 10961 } 10962 } 10963 if (check_optionrom) { 10964 wm_nvm_read(sc, NVM_OFF_COMB_VER_PTR, 1, &off); 10965 /* Option ROM Version */ 10966 if ((off != 0x0000) && (off != 0xffff)) { 10967 off += NVM_COMBO_VER_OFF; 10968 wm_nvm_read(sc, off + 1, 1, &uid1); 10969 wm_nvm_read(sc, off, 1, &uid0); 10970 if ((uid0 != 0) && (uid0 != 0xffff) 10971 && (uid1 != 0) && (uid1 != 0xffff)) { 10972 /* 16bits */ 10973 major = uid0 >> 8; 10974 build = (uid0 << 8) | (uid1 >> 8); 10975 patch = uid1 & 0x00ff; 10976 aprint_verbose(", option ROM Version %d.%d.%d", 10977 major, build, patch); 10978 } 10979 } 10980 } 10981 10982 wm_nvm_read(sc, NVM_OFF_IMAGE_UID0, 1, &uid0); 10983 aprint_verbose(", Image Unique ID %08x", (uid1 << 16) | uid0); 10984 } 10985 10986 /* 10987 * wm_nvm_read: 10988 * 10989 * Read data from the serial EEPROM. 10990 */ 10991 static int 10992 wm_nvm_read(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 10993 { 10994 int rv; 10995 10996 if (sc->sc_flags & WM_F_EEPROM_INVALID) 10997 return 1; 10998 10999 if (wm_nvm_acquire(sc)) 11000 return 1; 11001 11002 if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 11003 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 11004 || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) 11005 rv = wm_nvm_read_ich8(sc, word, wordcnt, data); 11006 else if (sc->sc_type == WM_T_PCH_SPT) 11007 rv = wm_nvm_read_spt(sc, word, wordcnt, data); 11008 else if (sc->sc_flags & WM_F_EEPROM_INVM) 11009 rv = wm_nvm_read_invm(sc, word, wordcnt, data); 11010 else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR) 11011 rv = wm_nvm_read_eerd(sc, word, wordcnt, data); 11012 else if (sc->sc_flags & WM_F_EEPROM_SPI) 11013 rv = wm_nvm_read_spi(sc, word, wordcnt, data); 11014 else 11015 rv = wm_nvm_read_uwire(sc, word, wordcnt, data); 11016 11017 wm_nvm_release(sc); 11018 return rv; 11019 } 11020 11021 /* 11022 * Hardware semaphores. 11023 * Very complexed... 11024 */ 11025 11026 static int 11027 wm_get_swsm_semaphore(struct wm_softc *sc) 11028 { 11029 int32_t timeout; 11030 uint32_t swsm; 11031 11032 if (sc->sc_flags & WM_F_LOCK_SWSM) { 11033 /* Get the SW semaphore. */ 11034 timeout = sc->sc_nvm_wordsize + 1; 11035 while (timeout) { 11036 swsm = CSR_READ(sc, WMREG_SWSM); 11037 11038 if ((swsm & SWSM_SMBI) == 0) 11039 break; 11040 11041 delay(50); 11042 timeout--; 11043 } 11044 11045 if (timeout == 0) { 11046 aprint_error_dev(sc->sc_dev, 11047 "could not acquire SWSM SMBI\n"); 11048 return 1; 11049 } 11050 } 11051 11052 /* Get the FW semaphore. */ 11053 timeout = sc->sc_nvm_wordsize + 1; 11054 while (timeout) { 11055 swsm = CSR_READ(sc, WMREG_SWSM); 11056 swsm |= SWSM_SWESMBI; 11057 CSR_WRITE(sc, WMREG_SWSM, swsm); 11058 /* If we managed to set the bit we got the semaphore. */ 11059 swsm = CSR_READ(sc, WMREG_SWSM); 11060 if (swsm & SWSM_SWESMBI) 11061 break; 11062 11063 delay(50); 11064 timeout--; 11065 } 11066 11067 if (timeout == 0) { 11068 aprint_error_dev(sc->sc_dev, 11069 "could not acquire SWSM SWESMBI\n"); 11070 /* Release semaphores */ 11071 wm_put_swsm_semaphore(sc); 11072 return 1; 11073 } 11074 return 0; 11075 } 11076 11077 static void 11078 wm_put_swsm_semaphore(struct wm_softc *sc) 11079 { 11080 uint32_t swsm; 11081 11082 swsm = CSR_READ(sc, WMREG_SWSM); 11083 swsm &= ~(SWSM_SMBI | SWSM_SWESMBI); 11084 CSR_WRITE(sc, WMREG_SWSM, swsm); 11085 } 11086 11087 static int 11088 wm_get_swfw_semaphore(struct wm_softc *sc, uint16_t mask) 11089 { 11090 uint32_t swfw_sync; 11091 uint32_t swmask = mask << SWFW_SOFT_SHIFT; 11092 uint32_t fwmask = mask << SWFW_FIRM_SHIFT; 11093 int timeout = 200; 11094 11095 for (timeout = 0; timeout < 200; timeout++) { 11096 if (sc->sc_flags & WM_F_LOCK_SWSM) { 11097 if (wm_get_swsm_semaphore(sc)) { 11098 aprint_error_dev(sc->sc_dev, 11099 "%s: failed to get semaphore\n", 11100 __func__); 11101 return 1; 11102 } 11103 } 11104 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC); 11105 if ((swfw_sync & (swmask | fwmask)) == 0) { 11106 swfw_sync |= swmask; 11107 CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync); 11108 if (sc->sc_flags & WM_F_LOCK_SWSM) 11109 wm_put_swsm_semaphore(sc); 11110 return 0; 11111 } 11112 if (sc->sc_flags & WM_F_LOCK_SWSM) 11113 wm_put_swsm_semaphore(sc); 11114 delay(5000); 11115 } 11116 printf("%s: failed to get swfw semaphore mask 0x%x swfw 0x%x\n", 11117 device_xname(sc->sc_dev), mask, swfw_sync); 11118 return 1; 11119 } 11120 11121 static void 11122 wm_put_swfw_semaphore(struct wm_softc *sc, uint16_t mask) 11123 { 11124 uint32_t swfw_sync; 11125 11126 if (sc->sc_flags & WM_F_LOCK_SWSM) { 11127 while (wm_get_swsm_semaphore(sc) != 0) 11128 continue; 11129 } 11130 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC); 11131 swfw_sync &= ~(mask << SWFW_SOFT_SHIFT); 11132 CSR_WRITE(sc, WMREG_SW_FW_SYNC, swfw_sync); 11133 if (sc->sc_flags & WM_F_LOCK_SWSM) 11134 wm_put_swsm_semaphore(sc); 11135 } 11136 11137 static int 11138 wm_get_swfwhw_semaphore(struct wm_softc *sc) 11139 { 11140 uint32_t ext_ctrl; 11141 int timeout = 200; 11142 11143 for (timeout = 0; timeout < 200; timeout++) { 11144 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 11145 ext_ctrl |= EXTCNFCTR_MDIO_SW_OWNERSHIP; 11146 CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl); 11147 11148 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 11149 if (ext_ctrl & EXTCNFCTR_MDIO_SW_OWNERSHIP) 11150 return 0; 11151 delay(5000); 11152 } 11153 printf("%s: failed to get swfwhw semaphore ext_ctrl 0x%x\n", 11154 device_xname(sc->sc_dev), ext_ctrl); 11155 return 1; 11156 } 11157 11158 static void 11159 wm_put_swfwhw_semaphore(struct wm_softc *sc) 11160 { 11161 uint32_t ext_ctrl; 11162 11163 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR); 11164 ext_ctrl &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP; 11165 CSR_WRITE(sc, WMREG_EXTCNFCTR, ext_ctrl); 11166 } 11167 11168 static int 11169 wm_get_hw_semaphore_82573(struct wm_softc *sc) 11170 { 11171 int i = 0; 11172 uint32_t reg; 11173 11174 reg = CSR_READ(sc, WMREG_EXTCNFCTR); 11175 do { 11176 CSR_WRITE(sc, WMREG_EXTCNFCTR, 11177 reg | EXTCNFCTR_MDIO_SW_OWNERSHIP); 11178 reg = CSR_READ(sc, WMREG_EXTCNFCTR); 11179 if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0) 11180 break; 11181 delay(2*1000); 11182 i++; 11183 } while (i < WM_MDIO_OWNERSHIP_TIMEOUT); 11184 11185 if (i == WM_MDIO_OWNERSHIP_TIMEOUT) { 11186 wm_put_hw_semaphore_82573(sc); 11187 log(LOG_ERR, "%s: Driver can't access the PHY\n", 11188 device_xname(sc->sc_dev)); 11189 return -1; 11190 } 11191 11192 return 0; 11193 } 11194 11195 static void 11196 wm_put_hw_semaphore_82573(struct wm_softc *sc) 11197 { 11198 uint32_t reg; 11199 11200 reg = CSR_READ(sc, WMREG_EXTCNFCTR); 11201 reg &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP; 11202 CSR_WRITE(sc, WMREG_EXTCNFCTR, reg); 11203 } 11204 11205 /* 11206 * Management mode and power management related subroutines. 11207 * BMC, AMT, suspend/resume and EEE. 11208 */ 11209 11210 #ifdef WM_WOL 11211 static int 11212 wm_check_mng_mode(struct wm_softc *sc) 11213 { 11214 int rv; 11215 11216 switch (sc->sc_type) { 11217 case WM_T_ICH8: 11218 case WM_T_ICH9: 11219 case WM_T_ICH10: 11220 case WM_T_PCH: 11221 case WM_T_PCH2: 11222 case WM_T_PCH_LPT: 11223 case WM_T_PCH_SPT: 11224 rv = wm_check_mng_mode_ich8lan(sc); 11225 break; 11226 case WM_T_82574: 11227 case WM_T_82583: 11228 rv = wm_check_mng_mode_82574(sc); 11229 break; 11230 case WM_T_82571: 11231 case WM_T_82572: 11232 case WM_T_82573: 11233 case WM_T_80003: 11234 rv = wm_check_mng_mode_generic(sc); 11235 break; 11236 default: 11237 /* noting to do */ 11238 rv = 0; 11239 break; 11240 } 11241 11242 return rv; 11243 } 11244 11245 static int 11246 wm_check_mng_mode_ich8lan(struct wm_softc *sc) 11247 { 11248 uint32_t fwsm; 11249 11250 fwsm = CSR_READ(sc, WMREG_FWSM); 11251 11252 if (((fwsm & FWSM_FW_VALID) != 0) 11253 && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE)) 11254 return 1; 11255 11256 return 0; 11257 } 11258 11259 static int 11260 wm_check_mng_mode_82574(struct wm_softc *sc) 11261 { 11262 uint16_t data; 11263 11264 wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data); 11265 11266 if ((data & NVM_CFG2_MNGM_MASK) != 0) 11267 return 1; 11268 11269 return 0; 11270 } 11271 11272 static int 11273 wm_check_mng_mode_generic(struct wm_softc *sc) 11274 { 11275 uint32_t fwsm; 11276 11277 fwsm = CSR_READ(sc, WMREG_FWSM); 11278 11279 if (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_IAMT_MODE) 11280 return 1; 11281 11282 return 0; 11283 } 11284 #endif /* WM_WOL */ 11285 11286 static int 11287 wm_enable_mng_pass_thru(struct wm_softc *sc) 11288 { 11289 uint32_t manc, fwsm, factps; 11290 11291 if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) == 0) 11292 return 0; 11293 11294 manc = CSR_READ(sc, WMREG_MANC); 11295 11296 DPRINTF(WM_DEBUG_MANAGE, ("%s: MANC (%08x)\n", 11297 device_xname(sc->sc_dev), manc)); 11298 if ((manc & MANC_RECV_TCO_EN) == 0) 11299 return 0; 11300 11301 if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) { 11302 fwsm = CSR_READ(sc, WMREG_FWSM); 11303 factps = CSR_READ(sc, WMREG_FACTPS); 11304 if (((factps & FACTPS_MNGCG) == 0) 11305 && (__SHIFTOUT(fwsm, FWSM_MODE) == MNG_ICH_IAMT_MODE)) 11306 return 1; 11307 } else if ((sc->sc_type == WM_T_82574) || (sc->sc_type == WM_T_82583)){ 11308 uint16_t data; 11309 11310 factps = CSR_READ(sc, WMREG_FACTPS); 11311 wm_nvm_read(sc, NVM_OFF_CFG2, 1, &data); 11312 DPRINTF(WM_DEBUG_MANAGE, ("%s: FACTPS = %08x, CFG2=%04x\n", 11313 device_xname(sc->sc_dev), factps, data)); 11314 if (((factps & FACTPS_MNGCG) == 0) 11315 && ((data & NVM_CFG2_MNGM_MASK) 11316 == (NVM_CFG2_MNGM_PT << NVM_CFG2_MNGM_SHIFT))) 11317 return 1; 11318 } else if (((manc & MANC_SMBUS_EN) != 0) 11319 && ((manc & MANC_ASF_EN) == 0)) 11320 return 1; 11321 11322 return 0; 11323 } 11324 11325 static bool 11326 wm_phy_resetisblocked(struct wm_softc *sc) 11327 { 11328 bool blocked = false; 11329 uint32_t reg; 11330 int i = 0; 11331 11332 switch (sc->sc_type) { 11333 case WM_T_ICH8: 11334 case WM_T_ICH9: 11335 case WM_T_ICH10: 11336 case WM_T_PCH: 11337 case WM_T_PCH2: 11338 case WM_T_PCH_LPT: 11339 case WM_T_PCH_SPT: 11340 do { 11341 reg = CSR_READ(sc, WMREG_FWSM); 11342 if ((reg & FWSM_RSPCIPHY) == 0) { 11343 blocked = true; 11344 delay(10*1000); 11345 continue; 11346 } 11347 blocked = false; 11348 } while (blocked && (i++ < 10)); 11349 return blocked; 11350 break; 11351 case WM_T_82571: 11352 case WM_T_82572: 11353 case WM_T_82573: 11354 case WM_T_82574: 11355 case WM_T_82583: 11356 case WM_T_80003: 11357 reg = CSR_READ(sc, WMREG_MANC); 11358 if ((reg & MANC_BLK_PHY_RST_ON_IDE) != 0) 11359 return true; 11360 else 11361 return false; 11362 break; 11363 default: 11364 /* no problem */ 11365 break; 11366 } 11367 11368 return false; 11369 } 11370 11371 static void 11372 wm_get_hw_control(struct wm_softc *sc) 11373 { 11374 uint32_t reg; 11375 11376 switch (sc->sc_type) { 11377 case WM_T_82573: 11378 reg = CSR_READ(sc, WMREG_SWSM); 11379 CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD); 11380 break; 11381 case WM_T_82571: 11382 case WM_T_82572: 11383 case WM_T_82574: 11384 case WM_T_82583: 11385 case WM_T_80003: 11386 case WM_T_ICH8: 11387 case WM_T_ICH9: 11388 case WM_T_ICH10: 11389 case WM_T_PCH: 11390 case WM_T_PCH2: 11391 case WM_T_PCH_LPT: 11392 case WM_T_PCH_SPT: 11393 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11394 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD); 11395 break; 11396 default: 11397 break; 11398 } 11399 } 11400 11401 static void 11402 wm_release_hw_control(struct wm_softc *sc) 11403 { 11404 uint32_t reg; 11405 11406 if ((sc->sc_flags & WM_F_HAS_MANAGE) == 0) 11407 return; 11408 11409 if (sc->sc_type == WM_T_82573) { 11410 reg = CSR_READ(sc, WMREG_SWSM); 11411 reg &= ~SWSM_DRV_LOAD; 11412 CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_DRV_LOAD); 11413 } else { 11414 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11415 CSR_WRITE(sc, WMREG_CTRL_EXT, reg & ~CTRL_EXT_DRV_LOAD); 11416 } 11417 } 11418 11419 static void 11420 wm_gate_hw_phy_config_ich8lan(struct wm_softc *sc, bool gate) 11421 { 11422 uint32_t reg; 11423 11424 if (sc->sc_type < WM_T_PCH2) 11425 return; 11426 11427 reg = CSR_READ(sc, WMREG_EXTCNFCTR); 11428 11429 if (gate) 11430 reg |= EXTCNFCTR_GATE_PHY_CFG; 11431 else 11432 reg &= ~EXTCNFCTR_GATE_PHY_CFG; 11433 11434 CSR_WRITE(sc, WMREG_EXTCNFCTR, reg); 11435 } 11436 11437 static void 11438 wm_smbustopci(struct wm_softc *sc) 11439 { 11440 uint32_t fwsm, reg; 11441 11442 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 11443 wm_gate_hw_phy_config_ich8lan(sc, true); 11444 11445 /* Acquire semaphore */ 11446 wm_get_swfwhw_semaphore(sc); 11447 11448 fwsm = CSR_READ(sc, WMREG_FWSM); 11449 if (((fwsm & FWSM_FW_VALID) == 0) 11450 && ((wm_phy_resetisblocked(sc) == false))) { 11451 if (sc->sc_type >= WM_T_PCH_LPT) { 11452 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11453 reg |= CTRL_EXT_FORCE_SMBUS; 11454 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 11455 CSR_WRITE_FLUSH(sc); 11456 delay(50*1000); 11457 } 11458 11459 /* Toggle LANPHYPC */ 11460 sc->sc_ctrl |= CTRL_LANPHYPC_OVERRIDE; 11461 sc->sc_ctrl &= ~CTRL_LANPHYPC_VALUE; 11462 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 11463 CSR_WRITE_FLUSH(sc); 11464 delay(10); 11465 sc->sc_ctrl &= ~CTRL_LANPHYPC_OVERRIDE; 11466 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 11467 CSR_WRITE_FLUSH(sc); 11468 delay(50*1000); 11469 11470 if (sc->sc_type >= WM_T_PCH_LPT) { 11471 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11472 reg &= ~CTRL_EXT_FORCE_SMBUS; 11473 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 11474 } 11475 } 11476 11477 /* Release semaphore */ 11478 wm_put_swfwhw_semaphore(sc); 11479 11480 /* 11481 * Ungate automatic PHY configuration by hardware on non-managed 82579 11482 */ 11483 if ((sc->sc_type == WM_T_PCH2) && ((fwsm & FWSM_FW_VALID) == 0)) 11484 wm_gate_hw_phy_config_ich8lan(sc, false); 11485 } 11486 11487 static void 11488 wm_init_manageability(struct wm_softc *sc) 11489 { 11490 11491 DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n", 11492 device_xname(sc->sc_dev), __func__)); 11493 if (sc->sc_flags & WM_F_HAS_MANAGE) { 11494 uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H); 11495 uint32_t manc = CSR_READ(sc, WMREG_MANC); 11496 11497 /* Disable hardware interception of ARP */ 11498 manc &= ~MANC_ARP_EN; 11499 11500 /* Enable receiving management packets to the host */ 11501 if (sc->sc_type >= WM_T_82571) { 11502 manc |= MANC_EN_MNG2HOST; 11503 manc2h |= MANC2H_PORT_623| MANC2H_PORT_624; 11504 CSR_WRITE(sc, WMREG_MANC2H, manc2h); 11505 } 11506 11507 CSR_WRITE(sc, WMREG_MANC, manc); 11508 } 11509 } 11510 11511 static void 11512 wm_release_manageability(struct wm_softc *sc) 11513 { 11514 11515 if (sc->sc_flags & WM_F_HAS_MANAGE) { 11516 uint32_t manc = CSR_READ(sc, WMREG_MANC); 11517 11518 manc |= MANC_ARP_EN; 11519 if (sc->sc_type >= WM_T_82571) 11520 manc &= ~MANC_EN_MNG2HOST; 11521 11522 CSR_WRITE(sc, WMREG_MANC, manc); 11523 } 11524 } 11525 11526 static void 11527 wm_get_wakeup(struct wm_softc *sc) 11528 { 11529 11530 /* 0: HAS_AMT, ARC_SUBSYS_VALID, ASF_FIRMWARE_PRES */ 11531 switch (sc->sc_type) { 11532 case WM_T_82573: 11533 case WM_T_82583: 11534 sc->sc_flags |= WM_F_HAS_AMT; 11535 /* FALLTHROUGH */ 11536 case WM_T_80003: 11537 case WM_T_82541: 11538 case WM_T_82547: 11539 case WM_T_82571: 11540 case WM_T_82572: 11541 case WM_T_82574: 11542 case WM_T_82575: 11543 case WM_T_82576: 11544 case WM_T_82580: 11545 case WM_T_I350: 11546 case WM_T_I354: 11547 if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE) != 0) 11548 sc->sc_flags |= WM_F_ARC_SUBSYS_VALID; 11549 sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES; 11550 break; 11551 case WM_T_ICH8: 11552 case WM_T_ICH9: 11553 case WM_T_ICH10: 11554 case WM_T_PCH: 11555 case WM_T_PCH2: 11556 case WM_T_PCH_LPT: 11557 case WM_T_PCH_SPT: /* XXX only Q170 chipset? */ 11558 sc->sc_flags |= WM_F_HAS_AMT; 11559 sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES; 11560 break; 11561 default: 11562 break; 11563 } 11564 11565 /* 1: HAS_MANAGE */ 11566 if (wm_enable_mng_pass_thru(sc) != 0) 11567 sc->sc_flags |= WM_F_HAS_MANAGE; 11568 11569 #ifdef WM_DEBUG 11570 printf("\n"); 11571 if ((sc->sc_flags & WM_F_HAS_AMT) != 0) 11572 printf("HAS_AMT,"); 11573 if ((sc->sc_flags & WM_F_ARC_SUBSYS_VALID) != 0) 11574 printf("ARC_SUBSYS_VALID,"); 11575 if ((sc->sc_flags & WM_F_ASF_FIRMWARE_PRES) != 0) 11576 printf("ASF_FIRMWARE_PRES,"); 11577 if ((sc->sc_flags & WM_F_HAS_MANAGE) != 0) 11578 printf("HAS_MANAGE,"); 11579 printf("\n"); 11580 #endif 11581 /* 11582 * Note that the WOL flags is set after the resetting of the eeprom 11583 * stuff 11584 */ 11585 } 11586 11587 #ifdef WM_WOL 11588 /* WOL in the newer chipset interfaces (pchlan) */ 11589 static void 11590 wm_enable_phy_wakeup(struct wm_softc *sc) 11591 { 11592 #if 0 11593 uint16_t preg; 11594 11595 /* Copy MAC RARs to PHY RARs */ 11596 11597 /* Copy MAC MTA to PHY MTA */ 11598 11599 /* Configure PHY Rx Control register */ 11600 11601 /* Enable PHY wakeup in MAC register */ 11602 11603 /* Configure and enable PHY wakeup in PHY registers */ 11604 11605 /* Activate PHY wakeup */ 11606 11607 /* XXX */ 11608 #endif 11609 } 11610 11611 /* Power down workaround on D3 */ 11612 static void 11613 wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *sc) 11614 { 11615 uint32_t reg; 11616 int i; 11617 11618 for (i = 0; i < 2; i++) { 11619 /* Disable link */ 11620 reg = CSR_READ(sc, WMREG_PHY_CTRL); 11621 reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS; 11622 CSR_WRITE(sc, WMREG_PHY_CTRL, reg); 11623 11624 /* 11625 * Call gig speed drop workaround on Gig disable before 11626 * accessing any PHY registers 11627 */ 11628 if (sc->sc_type == WM_T_ICH8) 11629 wm_gig_downshift_workaround_ich8lan(sc); 11630 11631 /* Write VR power-down enable */ 11632 reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL); 11633 reg &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 11634 reg |= IGP3_VR_CTRL_MODE_SHUTDOWN; 11635 sc->sc_mii.mii_writereg(sc->sc_dev, 1, IGP3_VR_CTRL, reg); 11636 11637 /* Read it back and test */ 11638 reg = sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL); 11639 reg &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 11640 if ((reg == IGP3_VR_CTRL_MODE_SHUTDOWN) || (i != 0)) 11641 break; 11642 11643 /* Issue PHY reset and repeat at most one more time */ 11644 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 11645 } 11646 } 11647 11648 static void 11649 wm_enable_wakeup(struct wm_softc *sc) 11650 { 11651 uint32_t reg, pmreg; 11652 pcireg_t pmode; 11653 11654 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT, 11655 &pmreg, NULL) == 0) 11656 return; 11657 11658 /* Advertise the wakeup capability */ 11659 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_SWDPIN(2) 11660 | CTRL_SWDPIN(3)); 11661 CSR_WRITE(sc, WMREG_WUC, WUC_APME); 11662 11663 /* ICH workaround */ 11664 switch (sc->sc_type) { 11665 case WM_T_ICH8: 11666 case WM_T_ICH9: 11667 case WM_T_ICH10: 11668 case WM_T_PCH: 11669 case WM_T_PCH2: 11670 case WM_T_PCH_LPT: 11671 case WM_T_PCH_SPT: 11672 /* Disable gig during WOL */ 11673 reg = CSR_READ(sc, WMREG_PHY_CTRL); 11674 reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS; 11675 CSR_WRITE(sc, WMREG_PHY_CTRL, reg); 11676 if (sc->sc_type == WM_T_PCH) 11677 wm_gmii_reset(sc); 11678 11679 /* Power down workaround */ 11680 if (sc->sc_phytype == WMPHY_82577) { 11681 struct mii_softc *child; 11682 11683 /* Assume that the PHY is copper */ 11684 child = LIST_FIRST(&sc->sc_mii.mii_phys); 11685 if (child->mii_mpd_rev <= 2) 11686 sc->sc_mii.mii_writereg(sc->sc_dev, 1, 11687 (768 << 5) | 25, 0x0444); /* magic num */ 11688 } 11689 break; 11690 default: 11691 break; 11692 } 11693 11694 /* Keep the laser running on fiber adapters */ 11695 if ((sc->sc_mediatype == WM_MEDIATYPE_FIBER) 11696 || (sc->sc_mediatype == WM_MEDIATYPE_SERDES)) { 11697 reg = CSR_READ(sc, WMREG_CTRL_EXT); 11698 reg |= CTRL_EXT_SWDPIN(3); 11699 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 11700 } 11701 11702 reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG; 11703 #if 0 /* for the multicast packet */ 11704 reg |= WUFC_MC; 11705 CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE); 11706 #endif 11707 11708 if (sc->sc_type == WM_T_PCH) { 11709 wm_enable_phy_wakeup(sc); 11710 } else { 11711 CSR_WRITE(sc, WMREG_WUC, WUC_PME_EN); 11712 CSR_WRITE(sc, WMREG_WUFC, reg); 11713 } 11714 11715 if (((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9) 11716 || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH) 11717 || (sc->sc_type == WM_T_PCH2)) 11718 && (sc->sc_phytype == WMPHY_IGP_3)) 11719 wm_igp3_phy_powerdown_workaround_ich8lan(sc); 11720 11721 /* Request PME */ 11722 pmode = pci_conf_read(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR); 11723 #if 0 11724 /* Disable WOL */ 11725 pmode &= ~(PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN); 11726 #else 11727 /* For WOL */ 11728 pmode |= PCI_PMCSR_PME_STS | PCI_PMCSR_PME_EN; 11729 #endif 11730 pci_conf_write(sc->sc_pc, sc->sc_pcitag, pmreg + PCI_PMCSR, pmode); 11731 } 11732 #endif /* WM_WOL */ 11733 11734 /* LPLU */ 11735 11736 static void 11737 wm_lplu_d0_disable(struct wm_softc *sc) 11738 { 11739 uint32_t reg; 11740 11741 reg = CSR_READ(sc, WMREG_PHY_CTRL); 11742 reg &= ~(PHY_CTRL_GBE_DIS | PHY_CTRL_D0A_LPLU); 11743 CSR_WRITE(sc, WMREG_PHY_CTRL, reg); 11744 } 11745 11746 static void 11747 wm_lplu_d0_disable_pch(struct wm_softc *sc) 11748 { 11749 uint32_t reg; 11750 11751 reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_OEM_BITS); 11752 reg &= ~(HV_OEM_BITS_A1KDIS | HV_OEM_BITS_LPLU); 11753 reg |= HV_OEM_BITS_ANEGNOW; 11754 wm_gmii_hv_writereg(sc->sc_dev, 1, HV_OEM_BITS, reg); 11755 } 11756 11757 /* EEE */ 11758 11759 static void 11760 wm_set_eee_i350(struct wm_softc *sc) 11761 { 11762 uint32_t ipcnfg, eeer; 11763 11764 ipcnfg = CSR_READ(sc, WMREG_IPCNFG); 11765 eeer = CSR_READ(sc, WMREG_EEER); 11766 11767 if ((sc->sc_flags & WM_F_EEE) != 0) { 11768 ipcnfg |= (IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN); 11769 eeer |= (EEER_TX_LPI_EN | EEER_RX_LPI_EN 11770 | EEER_LPI_FC); 11771 } else { 11772 ipcnfg &= ~(IPCNFG_EEE_1G_AN | IPCNFG_EEE_100M_AN); 11773 ipcnfg &= ~IPCNFG_10BASE_TE; 11774 eeer &= ~(EEER_TX_LPI_EN | EEER_RX_LPI_EN 11775 | EEER_LPI_FC); 11776 } 11777 11778 CSR_WRITE(sc, WMREG_IPCNFG, ipcnfg); 11779 CSR_WRITE(sc, WMREG_EEER, eeer); 11780 CSR_READ(sc, WMREG_IPCNFG); /* XXX flush? */ 11781 CSR_READ(sc, WMREG_EEER); /* XXX flush? */ 11782 } 11783 11784 /* 11785 * Workarounds (mainly PHY related). 11786 * Basically, PHY's workarounds are in the PHY drivers. 11787 */ 11788 11789 /* Work-around for 82566 Kumeran PCS lock loss */ 11790 static void 11791 wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *sc) 11792 { 11793 #if 0 11794 int miistatus, active, i; 11795 int reg; 11796 11797 miistatus = sc->sc_mii.mii_media_status; 11798 11799 /* If the link is not up, do nothing */ 11800 if ((miistatus & IFM_ACTIVE) == 0) 11801 return; 11802 11803 active = sc->sc_mii.mii_media_active; 11804 11805 /* Nothing to do if the link is other than 1Gbps */ 11806 if (IFM_SUBTYPE(active) != IFM_1000_T) 11807 return; 11808 11809 for (i = 0; i < 10; i++) { 11810 /* read twice */ 11811 reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG); 11812 reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG); 11813 if ((reg & IGP3_KMRN_DIAG_PCS_LOCK_LOSS) == 0) 11814 goto out; /* GOOD! */ 11815 11816 /* Reset the PHY */ 11817 wm_gmii_reset(sc); 11818 delay(5*1000); 11819 } 11820 11821 /* Disable GigE link negotiation */ 11822 reg = CSR_READ(sc, WMREG_PHY_CTRL); 11823 reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS; 11824 CSR_WRITE(sc, WMREG_PHY_CTRL, reg); 11825 11826 /* 11827 * Call gig speed drop workaround on Gig disable before accessing 11828 * any PHY registers. 11829 */ 11830 wm_gig_downshift_workaround_ich8lan(sc); 11831 11832 out: 11833 return; 11834 #endif 11835 } 11836 11837 /* WOL from S5 stops working */ 11838 static void 11839 wm_gig_downshift_workaround_ich8lan(struct wm_softc *sc) 11840 { 11841 uint16_t kmrn_reg; 11842 11843 /* Only for igp3 */ 11844 if (sc->sc_phytype == WMPHY_IGP_3) { 11845 kmrn_reg = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_DIAG); 11846 kmrn_reg |= KUMCTRLSTA_DIAG_NELPBK; 11847 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg); 11848 kmrn_reg &= ~KUMCTRLSTA_DIAG_NELPBK; 11849 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg); 11850 } 11851 } 11852 11853 /* 11854 * Workaround for pch's PHYs 11855 * XXX should be moved to new PHY driver? 11856 */ 11857 static void 11858 wm_hv_phy_workaround_ich8lan(struct wm_softc *sc) 11859 { 11860 if (sc->sc_phytype == WMPHY_82577) 11861 wm_set_mdio_slow_mode_hv(sc); 11862 11863 /* (PCH rev.2) && (82577 && (phy rev 2 or 3)) */ 11864 11865 /* (82577 && (phy rev 1 or 2)) || (82578 & phy rev 1)*/ 11866 11867 /* 82578 */ 11868 if (sc->sc_phytype == WMPHY_82578) { 11869 /* PCH rev. < 3 */ 11870 if (sc->sc_rev < 3) { 11871 /* XXX 6 bit shift? Why? Is it page2? */ 11872 wm_gmii_hv_writereg(sc->sc_dev, 1, ((1 << 6) | 0x29), 11873 0x66c0); 11874 wm_gmii_hv_writereg(sc->sc_dev, 1, ((1 << 6) | 0x1e), 11875 0xffff); 11876 } 11877 11878 /* XXX phy rev. < 2 */ 11879 } 11880 11881 /* Select page 0 */ 11882 11883 /* XXX acquire semaphore */ 11884 wm_gmii_i82544_writereg(sc->sc_dev, 1, MII_IGPHY_PAGE_SELECT, 0); 11885 /* XXX release semaphore */ 11886 11887 /* 11888 * Configure the K1 Si workaround during phy reset assuming there is 11889 * link so that it disables K1 if link is in 1Gbps. 11890 */ 11891 wm_k1_gig_workaround_hv(sc, 1); 11892 } 11893 11894 static void 11895 wm_lv_phy_workaround_ich8lan(struct wm_softc *sc) 11896 { 11897 11898 wm_set_mdio_slow_mode_hv(sc); 11899 } 11900 11901 static void 11902 wm_k1_gig_workaround_hv(struct wm_softc *sc, int link) 11903 { 11904 int k1_enable = sc->sc_nvm_k1_enabled; 11905 11906 /* XXX acquire semaphore */ 11907 11908 if (link) { 11909 k1_enable = 0; 11910 11911 /* Link stall fix for link up */ 11912 wm_gmii_hv_writereg(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x0100); 11913 } else { 11914 /* Link stall fix for link down */ 11915 wm_gmii_hv_writereg(sc->sc_dev, 1, IGP3_KMRN_DIAG, 0x4100); 11916 } 11917 11918 wm_configure_k1_ich8lan(sc, k1_enable); 11919 11920 /* XXX release semaphore */ 11921 } 11922 11923 static void 11924 wm_set_mdio_slow_mode_hv(struct wm_softc *sc) 11925 { 11926 uint32_t reg; 11927 11928 reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL); 11929 wm_gmii_hv_writereg(sc->sc_dev, 1, HV_KMRN_MODE_CTRL, 11930 reg | HV_KMRN_MDIO_SLOW); 11931 } 11932 11933 static void 11934 wm_configure_k1_ich8lan(struct wm_softc *sc, int k1_enable) 11935 { 11936 uint32_t ctrl, ctrl_ext, tmp; 11937 uint16_t kmrn_reg; 11938 11939 kmrn_reg = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_K1_CONFIG); 11940 11941 if (k1_enable) 11942 kmrn_reg |= KUMCTRLSTA_K1_ENABLE; 11943 else 11944 kmrn_reg &= ~KUMCTRLSTA_K1_ENABLE; 11945 11946 wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_K1_CONFIG, kmrn_reg); 11947 11948 delay(20); 11949 11950 ctrl = CSR_READ(sc, WMREG_CTRL); 11951 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT); 11952 11953 tmp = ctrl & ~(CTRL_SPEED_1000 | CTRL_SPEED_100); 11954 tmp |= CTRL_FRCSPD; 11955 11956 CSR_WRITE(sc, WMREG_CTRL, tmp); 11957 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext | CTRL_EXT_SPD_BYPS); 11958 CSR_WRITE_FLUSH(sc); 11959 delay(20); 11960 11961 CSR_WRITE(sc, WMREG_CTRL, ctrl); 11962 CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext); 11963 CSR_WRITE_FLUSH(sc); 11964 delay(20); 11965 } 11966 11967 /* special case - for 82575 - need to do manual init ... */ 11968 static void 11969 wm_reset_init_script_82575(struct wm_softc *sc) 11970 { 11971 /* 11972 * remark: this is untested code - we have no board without EEPROM 11973 * same setup as mentioned int the FreeBSD driver for the i82575 11974 */ 11975 11976 /* SerDes configuration via SERDESCTRL */ 11977 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x00, 0x0c); 11978 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x01, 0x78); 11979 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x1b, 0x23); 11980 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCTL, 0x23, 0x15); 11981 11982 /* CCM configuration via CCMCTL register */ 11983 wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x14, 0x00); 11984 wm_82575_write_8bit_ctlr_reg(sc, WMREG_CCMCTL, 0x10, 0x00); 11985 11986 /* PCIe lanes configuration */ 11987 wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x00, 0xec); 11988 wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x61, 0xdf); 11989 wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x34, 0x05); 11990 wm_82575_write_8bit_ctlr_reg(sc, WMREG_GIOCTL, 0x2f, 0x81); 11991 11992 /* PCIe PLL Configuration */ 11993 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x02, 0x47); 11994 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x14, 0x00); 11995 wm_82575_write_8bit_ctlr_reg(sc, WMREG_SCCTL, 0x10, 0x00); 11996 } 11997 11998 static void 11999 wm_reset_mdicnfg_82580(struct wm_softc *sc) 12000 { 12001 uint32_t reg; 12002 uint16_t nvmword; 12003 int rv; 12004 12005 if ((sc->sc_flags & WM_F_SGMII) == 0) 12006 return; 12007 12008 rv = wm_nvm_read(sc, NVM_OFF_LAN_FUNC_82580(sc->sc_funcid) 12009 + NVM_OFF_CFG3_PORTA, 1, &nvmword); 12010 if (rv != 0) { 12011 aprint_error_dev(sc->sc_dev, "%s: failed to read NVM\n", 12012 __func__); 12013 return; 12014 } 12015 12016 reg = CSR_READ(sc, WMREG_MDICNFG); 12017 if (nvmword & NVM_CFG3_PORTA_EXT_MDIO) 12018 reg |= MDICNFG_DEST; 12019 if (nvmword & NVM_CFG3_PORTA_COM_MDIO) 12020 reg |= MDICNFG_COM_MDIO; 12021 CSR_WRITE(sc, WMREG_MDICNFG, reg); 12022 } 12023 12024 /* 12025 * I210 Errata 25 and I211 Errata 10 12026 * Slow System Clock. 12027 */ 12028 static void 12029 wm_pll_workaround_i210(struct wm_softc *sc) 12030 { 12031 uint32_t mdicnfg, wuc; 12032 uint32_t reg; 12033 pcireg_t pcireg; 12034 uint32_t pmreg; 12035 uint16_t nvmword, tmp_nvmword; 12036 int phyval; 12037 bool wa_done = false; 12038 int i; 12039 12040 /* Save WUC and MDICNFG registers */ 12041 wuc = CSR_READ(sc, WMREG_WUC); 12042 mdicnfg = CSR_READ(sc, WMREG_MDICNFG); 12043 12044 reg = mdicnfg & ~MDICNFG_DEST; 12045 CSR_WRITE(sc, WMREG_MDICNFG, reg); 12046 12047 if (wm_nvm_read(sc, INVM_AUTOLOAD, 1, &nvmword) != 0) 12048 nvmword = INVM_DEFAULT_AL; 12049 tmp_nvmword = nvmword | INVM_PLL_WO_VAL; 12050 12051 /* Get Power Management cap offset */ 12052 if (pci_get_capability(sc->sc_pc, sc->sc_pcitag, PCI_CAP_PWRMGMT, 12053 &pmreg, NULL) == 0) 12054 return; 12055 for (i = 0; i < WM_MAX_PLL_TRIES; i++) { 12056 phyval = wm_gmii_gs40g_readreg(sc->sc_dev, 1, 12057 GS40G_PHY_PLL_FREQ_PAGE | GS40G_PHY_PLL_FREQ_REG); 12058 12059 if ((phyval & GS40G_PHY_PLL_UNCONF) != GS40G_PHY_PLL_UNCONF) { 12060 break; /* OK */ 12061 } 12062 12063 wa_done = true; 12064 /* Directly reset the internal PHY */ 12065 reg = CSR_READ(sc, WMREG_CTRL); 12066 CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET); 12067 12068 reg = CSR_READ(sc, WMREG_CTRL_EXT); 12069 reg |= CTRL_EXT_PHYPDEN | CTRL_EXT_SDLPE; 12070 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 12071 12072 CSR_WRITE(sc, WMREG_WUC, 0); 12073 reg = (INVM_AUTOLOAD << 4) | (tmp_nvmword << 16); 12074 CSR_WRITE(sc, WMREG_EEARBC_I210, reg); 12075 12076 pcireg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 12077 pmreg + PCI_PMCSR); 12078 pcireg |= PCI_PMCSR_STATE_D3; 12079 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 12080 pmreg + PCI_PMCSR, pcireg); 12081 delay(1000); 12082 pcireg &= ~PCI_PMCSR_STATE_D3; 12083 pci_conf_write(sc->sc_pc, sc->sc_pcitag, 12084 pmreg + PCI_PMCSR, pcireg); 12085 12086 reg = (INVM_AUTOLOAD << 4) | (nvmword << 16); 12087 CSR_WRITE(sc, WMREG_EEARBC_I210, reg); 12088 12089 /* Restore WUC register */ 12090 CSR_WRITE(sc, WMREG_WUC, wuc); 12091 } 12092 12093 /* Restore MDICNFG setting */ 12094 CSR_WRITE(sc, WMREG_MDICNFG, mdicnfg); 12095 if (wa_done) 12096 aprint_verbose_dev(sc->sc_dev, "I210 workaround done\n"); 12097 } 12098
Indexes created Tue Sep 23 07:09:52 GMT 2025