if_wm.c revision 1.78
1 /* $NetBSD: if_wm.c,v 1.78 2004/10/05 20:14:52 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.78 2004/10/05 20:14:52 thorpej Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 67 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 68 69 #if NRND > 0 70 #include <sys/rnd.h> 71 #endif 72 73 #include <net/if.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_ether.h> 77 78 #if NBPFILTER > 0 79 #include <net/bpf.h> 80 #endif 81 82 #include <netinet/in.h> /* XXX for struct ip */ 83 #include <netinet/in_systm.h> /* XXX for struct ip */ 84 #include <netinet/ip.h> /* XXX for struct ip */ 85 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 #include <machine/endian.h> 90 91 #include <dev/mii/mii.h> 92 #include <dev/mii/miivar.h> 93 #include <dev/mii/mii_bitbang.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include <dev/pci/if_wmreg.h> 100 101 #ifdef WM_DEBUG 102 #define WM_DEBUG_LINK 0x01 103 #define WM_DEBUG_TX 0x02 104 #define WM_DEBUG_RX 0x04 105 #define WM_DEBUG_GMII 0x08 106 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 107 108 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 109 #else 110 #define DPRINTF(x, y) /* nothing */ 111 #endif /* WM_DEBUG */ 112 113 /* 114 * Transmit descriptor list size. Due to errata, we can only have 115 * 256 hardware descriptors in the ring on < 82544, but we use 4096 116 * on >= 82544. We tell the upper layers that they can queue a lot 117 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 118 * of them at a time. 119 * 120 * We allow up to 256 (!) DMA segments per packet. Pathological packet 121 * chains containing many small mbufs have been observed in zero-copy 122 * situations with jumbo frames. 123 */ 124 #define WM_NTXSEGS 256 125 #define WM_IFQUEUELEN 256 126 #define WM_TXQUEUELEN_MAX 64 127 #define WM_TXQUEUELEN_MAX_82547 16 128 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 129 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 130 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 131 #define WM_NTXDESC_82542 256 132 #define WM_NTXDESC_82544 4096 133 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 134 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 135 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 136 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 137 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 138 139 /* 140 * Receive descriptor list size. We have one Rx buffer for normal 141 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 142 * packet. We allocate 256 receive descriptors, each with a 2k 143 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 144 */ 145 #define WM_NRXDESC 256 146 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 147 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 148 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 149 150 /* 151 * Control structures are DMA'd to the i82542 chip. We allocate them in 152 * a single clump that maps to a single DMA segment to make serveral things 153 * easier. 154 */ 155 struct wm_control_data_82544 { 156 /* 157 * The receive descriptors. 158 */ 159 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 160 161 /* 162 * The transmit descriptors. Put these at the end, because 163 * we might use a smaller number of them. 164 */ 165 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 166 }; 167 168 struct wm_control_data_82542 { 169 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 170 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 171 }; 172 173 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 174 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 175 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 176 177 /* 178 * Software state for transmit jobs. 179 */ 180 struct wm_txsoft { 181 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 182 bus_dmamap_t txs_dmamap; /* our DMA map */ 183 int txs_firstdesc; /* first descriptor in packet */ 184 int txs_lastdesc; /* last descriptor in packet */ 185 int txs_ndesc; /* # of descriptors used */ 186 }; 187 188 /* 189 * Software state for receive buffers. Each descriptor gets a 190 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 191 * more than one buffer, we chain them together. 192 */ 193 struct wm_rxsoft { 194 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 195 bus_dmamap_t rxs_dmamap; /* our DMA map */ 196 }; 197 198 typedef enum { 199 WM_T_unknown = 0, 200 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 201 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 202 WM_T_82543, /* i82543 */ 203 WM_T_82544, /* i82544 */ 204 WM_T_82540, /* i82540 */ 205 WM_T_82545, /* i82545 */ 206 WM_T_82545_3, /* i82545 3.0+ */ 207 WM_T_82546, /* i82546 */ 208 WM_T_82546_3, /* i82546 3.0+ */ 209 WM_T_82541, /* i82541 */ 210 WM_T_82541_2, /* i82541 2.0+ */ 211 WM_T_82547, /* i82547 */ 212 WM_T_82547_2, /* i82547 2.0+ */ 213 } wm_chip_type; 214 215 /* 216 * Software state per device. 217 */ 218 struct wm_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_space_tag_t sc_iot; /* I/O space tag */ 223 bus_space_handle_t sc_ioh; /* I/O space handle */ 224 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 225 struct ethercom sc_ethercom; /* ethernet common data */ 226 void *sc_sdhook; /* shutdown hook */ 227 228 wm_chip_type sc_type; /* chip type */ 229 int sc_flags; /* flags; see below */ 230 int sc_bus_speed; /* PCI/PCIX bus speed */ 231 int sc_pcix_offset; /* PCIX capability register offset */ 232 int sc_flowflags; /* 802.3x flow control flags */ 233 234 void *sc_ih; /* interrupt cookie */ 235 236 int sc_ee_addrbits; /* EEPROM address bits */ 237 238 struct mii_data sc_mii; /* MII/media information */ 239 240 struct callout sc_tick_ch; /* tick callout */ 241 242 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 243 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 244 245 int sc_align_tweak; 246 247 /* 248 * Software state for the transmit and receive descriptors. 249 */ 250 int sc_txnum; /* must be a power of two */ 251 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 252 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 253 254 /* 255 * Control data structures. 256 */ 257 int sc_ntxdesc; /* must be a power of two */ 258 struct wm_control_data_82544 *sc_control_data; 259 #define sc_txdescs sc_control_data->wcd_txdescs 260 #define sc_rxdescs sc_control_data->wcd_rxdescs 261 262 #ifdef WM_EVENT_COUNTERS 263 /* Event counters. */ 264 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 265 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 266 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 267 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 268 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 269 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 270 struct evcnt sc_ev_linkintr; /* Link interrupts */ 271 272 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 273 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 274 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 275 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 276 277 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 278 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 279 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 280 281 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 282 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 283 284 struct evcnt sc_ev_tu; /* Tx underrun */ 285 286 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 287 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 288 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 289 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 290 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 291 #endif /* WM_EVENT_COUNTERS */ 292 293 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 294 295 int sc_txfree; /* number of free Tx descriptors */ 296 int sc_txnext; /* next ready Tx descriptor */ 297 298 int sc_txsfree; /* number of free Tx jobs */ 299 int sc_txsnext; /* next free Tx job */ 300 int sc_txsdirty; /* dirty Tx jobs */ 301 302 /* These 5 variables are used only on the 82547. */ 303 int sc_txfifo_size; /* Tx FIFO size */ 304 int sc_txfifo_head; /* current head of FIFO */ 305 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 306 int sc_txfifo_stall; /* Tx FIFO is stalled */ 307 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 308 309 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 310 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 311 312 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 313 314 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 315 int sc_rxdiscard; 316 int sc_rxlen; 317 struct mbuf *sc_rxhead; 318 struct mbuf *sc_rxtail; 319 struct mbuf **sc_rxtailp; 320 321 uint32_t sc_ctrl; /* prototype CTRL register */ 322 #if 0 323 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 324 #endif 325 uint32_t sc_icr; /* prototype interrupt bits */ 326 uint32_t sc_tctl; /* prototype TCTL register */ 327 uint32_t sc_rctl; /* prototype RCTL register */ 328 uint32_t sc_txcw; /* prototype TXCW register */ 329 uint32_t sc_tipg; /* prototype TIPG register */ 330 uint32_t sc_fcrtl; /* prototype FCRTL register */ 331 uint32_t sc_pba; /* prototype PBA register */ 332 333 int sc_tbi_linkup; /* TBI link status */ 334 int sc_tbi_anstate; /* autonegotiation state */ 335 336 int sc_mchash_type; /* multicast filter offset */ 337 338 #if NRND > 0 339 rndsource_element_t rnd_source; /* random source */ 340 #endif 341 }; 342 343 #define WM_RXCHAIN_RESET(sc) \ 344 do { \ 345 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 346 *(sc)->sc_rxtailp = NULL; \ 347 (sc)->sc_rxlen = 0; \ 348 } while (/*CONSTCOND*/0) 349 350 #define WM_RXCHAIN_LINK(sc, m) \ 351 do { \ 352 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 353 (sc)->sc_rxtailp = &(m)->m_next; \ 354 } while (/*CONSTCOND*/0) 355 356 /* sc_flags */ 357 #define WM_F_HAS_MII 0x01 /* has MII */ 358 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 359 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 360 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 361 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 362 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 363 #define WM_F_CSA 0x80 /* bus is CSA */ 364 365 #ifdef WM_EVENT_COUNTERS 366 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 367 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 368 #else 369 #define WM_EVCNT_INCR(ev) /* nothing */ 370 #define WM_EVCNT_ADD(ev, val) /* nothing */ 371 #endif 372 373 #define CSR_READ(sc, reg) \ 374 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 375 #define CSR_WRITE(sc, reg, val) \ 376 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 377 #define CSR_WRITE_FLUSH(sc) \ 378 (void) CSR_READ((sc), WMREG_STATUS) 379 380 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 381 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 382 383 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 384 #define WM_CDTXADDR_HI(sc, x) \ 385 (sizeof(bus_addr_t) == 8 ? \ 386 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 387 388 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 389 #define WM_CDRXADDR_HI(sc, x) \ 390 (sizeof(bus_addr_t) == 8 ? \ 391 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 392 393 #define WM_CDTXSYNC(sc, x, n, ops) \ 394 do { \ 395 int __x, __n; \ 396 \ 397 __x = (x); \ 398 __n = (n); \ 399 \ 400 /* If it will wrap around, sync to the end of the ring. */ \ 401 if ((__x + __n) > WM_NTXDESC(sc)) { \ 402 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 403 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 404 (WM_NTXDESC(sc) - __x), (ops)); \ 405 __n -= (WM_NTXDESC(sc) - __x); \ 406 __x = 0; \ 407 } \ 408 \ 409 /* Now sync whatever is left. */ \ 410 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 411 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 412 } while (/*CONSTCOND*/0) 413 414 #define WM_CDRXSYNC(sc, x, ops) \ 415 do { \ 416 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 417 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 418 } while (/*CONSTCOND*/0) 419 420 #define WM_INIT_RXDESC(sc, x) \ 421 do { \ 422 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 423 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 424 struct mbuf *__m = __rxs->rxs_mbuf; \ 425 \ 426 /* \ 427 * Note: We scoot the packet forward 2 bytes in the buffer \ 428 * so that the payload after the Ethernet header is aligned \ 429 * to a 4-byte boundary. \ 430 * \ 431 * XXX BRAINDAMAGE ALERT! \ 432 * The stupid chip uses the same size for every buffer, which \ 433 * is set in the Receive Control register. We are using the 2K \ 434 * size option, but what we REALLY want is (2K - 2)! For this \ 435 * reason, we can't "scoot" packets longer than the standard \ 436 * Ethernet MTU. On strict-alignment platforms, if the total \ 437 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 438 * the upper layer copy the headers. \ 439 */ \ 440 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 441 \ 442 wm_set_dma_addr(&__rxd->wrx_addr, \ 443 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 444 __rxd->wrx_len = 0; \ 445 __rxd->wrx_cksum = 0; \ 446 __rxd->wrx_status = 0; \ 447 __rxd->wrx_errors = 0; \ 448 __rxd->wrx_special = 0; \ 449 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 450 \ 451 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 452 } while (/*CONSTCOND*/0) 453 454 static void wm_start(struct ifnet *); 455 static void wm_watchdog(struct ifnet *); 456 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 457 static int wm_init(struct ifnet *); 458 static void wm_stop(struct ifnet *, int); 459 460 static void wm_shutdown(void *); 461 462 static void wm_reset(struct wm_softc *); 463 static void wm_rxdrain(struct wm_softc *); 464 static int wm_add_rxbuf(struct wm_softc *, int); 465 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 466 static void wm_tick(void *); 467 468 static void wm_set_filter(struct wm_softc *); 469 470 static int wm_intr(void *); 471 static void wm_txintr(struct wm_softc *); 472 static void wm_rxintr(struct wm_softc *); 473 static void wm_linkintr(struct wm_softc *, uint32_t); 474 475 static void wm_tbi_mediainit(struct wm_softc *); 476 static int wm_tbi_mediachange(struct ifnet *); 477 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 478 479 static void wm_tbi_set_linkled(struct wm_softc *); 480 static void wm_tbi_check_link(struct wm_softc *); 481 482 static void wm_gmii_reset(struct wm_softc *); 483 484 static int wm_gmii_i82543_readreg(struct device *, int, int); 485 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 486 487 static int wm_gmii_i82544_readreg(struct device *, int, int); 488 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 489 490 static void wm_gmii_statchg(struct device *); 491 492 static void wm_gmii_mediainit(struct wm_softc *); 493 static int wm_gmii_mediachange(struct ifnet *); 494 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 495 496 static int wm_match(struct device *, struct cfdata *, void *); 497 static void wm_attach(struct device *, struct device *, void *); 498 499 CFATTACH_DECL(wm, sizeof(struct wm_softc), 500 wm_match, wm_attach, NULL, NULL); 501 502 static void wm_82547_txfifo_stall(void *); 503 504 /* 505 * Devices supported by this driver. 506 */ 507 static const struct wm_product { 508 pci_vendor_id_t wmp_vendor; 509 pci_product_id_t wmp_product; 510 const char *wmp_name; 511 wm_chip_type wmp_type; 512 int wmp_flags; 513 #define WMP_F_1000X 0x01 514 #define WMP_F_1000T 0x02 515 } wm_products[] = { 516 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 517 "Intel i82542 1000BASE-X Ethernet", 518 WM_T_82542_2_1, WMP_F_1000X }, 519 520 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 521 "Intel i82543GC 1000BASE-X Ethernet", 522 WM_T_82543, WMP_F_1000X }, 523 524 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 525 "Intel i82543GC 1000BASE-T Ethernet", 526 WM_T_82543, WMP_F_1000T }, 527 528 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 529 "Intel i82544EI 1000BASE-T Ethernet", 530 WM_T_82544, WMP_F_1000T }, 531 532 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 533 "Intel i82544EI 1000BASE-X Ethernet", 534 WM_T_82544, WMP_F_1000X }, 535 536 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 537 "Intel i82544GC 1000BASE-T Ethernet", 538 WM_T_82544, WMP_F_1000T }, 539 540 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 541 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 542 WM_T_82544, WMP_F_1000T }, 543 544 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 545 "Intel i82540EM 1000BASE-T Ethernet", 546 WM_T_82540, WMP_F_1000T }, 547 548 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 549 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 550 WM_T_82540, WMP_F_1000T }, 551 552 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 553 "Intel i82540EP 1000BASE-T Ethernet", 554 WM_T_82540, WMP_F_1000T }, 555 556 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 557 "Intel i82540EP 1000BASE-T Ethernet", 558 WM_T_82540, WMP_F_1000T }, 559 560 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 561 "Intel i82540EP 1000BASE-T Ethernet", 562 WM_T_82540, WMP_F_1000T }, 563 564 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 565 "Intel i82545EM 1000BASE-T Ethernet", 566 WM_T_82545, WMP_F_1000T }, 567 568 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 569 "Intel i82545GM 1000BASE-T Ethernet", 570 WM_T_82545_3, WMP_F_1000T }, 571 572 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 573 "Intel i82545GM 1000BASE-X Ethernet", 574 WM_T_82545_3, WMP_F_1000X }, 575 #if 0 576 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 577 "Intel i82545GM Gigabit Ethernet (SERDES)", 578 WM_T_82545_3, WMP_F_SERDES }, 579 #endif 580 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 581 "Intel i82546EB 1000BASE-T Ethernet", 582 WM_T_82546, WMP_F_1000T }, 583 584 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 585 "Intel i82546EB 1000BASE-T Ethernet", 586 WM_T_82546, WMP_F_1000T }, 587 588 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 589 "Intel i82545EM 1000BASE-X Ethernet", 590 WM_T_82545, WMP_F_1000X }, 591 592 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 593 "Intel i82546EB 1000BASE-X Ethernet", 594 WM_T_82546, WMP_F_1000X }, 595 596 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 597 "Intel i82546GB 1000BASE-T Ethernet", 598 WM_T_82546_3, WMP_F_1000T }, 599 600 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 601 "Intel i82546GB 1000BASE-X Ethernet", 602 WM_T_82546_3, WMP_F_1000X }, 603 #if 0 604 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 605 "Intel i82546GB Gigabit Ethernet (SERDES)", 606 WM_T_82546_3, WMP_F_SERDES }, 607 #endif 608 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 609 "Intel i82541EI 1000BASE-T Ethernet", 610 WM_T_82541, WMP_F_1000T }, 611 612 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 613 "Intel i82541EI Mobile 1000BASE-T Ethernet", 614 WM_T_82541, WMP_F_1000T }, 615 616 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 617 "Intel i82541ER 1000BASE-T Ethernet", 618 WM_T_82541_2, WMP_F_1000T }, 619 620 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 621 "Intel i82541GI 1000BASE-T Ethernet", 622 WM_T_82541_2, WMP_F_1000T }, 623 624 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 625 "Intel i82541GI Mobile 1000BASE-T Ethernet", 626 WM_T_82541_2, WMP_F_1000T }, 627 628 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 629 "Intel i82547EI 1000BASE-T Ethernet", 630 WM_T_82547, WMP_F_1000T }, 631 632 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 633 "Intel i82547GI 1000BASE-T Ethernet", 634 WM_T_82547_2, WMP_F_1000T }, 635 { 0, 0, 636 NULL, 637 0, 0 }, 638 }; 639 640 #ifdef WM_EVENT_COUNTERS 641 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 642 #endif /* WM_EVENT_COUNTERS */ 643 644 #if 0 /* Not currently used */ 645 static __inline uint32_t 646 wm_io_read(struct wm_softc *sc, int reg) 647 { 648 649 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 650 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 651 } 652 #endif 653 654 static __inline void 655 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 656 { 657 658 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 659 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 660 } 661 662 static __inline void 663 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 664 { 665 wa->wa_low = htole32(v & 0xffffffffU); 666 if (sizeof(bus_addr_t) == 8) 667 wa->wa_high = htole32((uint64_t) v >> 32); 668 else 669 wa->wa_high = 0; 670 } 671 672 static const struct wm_product * 673 wm_lookup(const struct pci_attach_args *pa) 674 { 675 const struct wm_product *wmp; 676 677 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 678 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 679 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 680 return (wmp); 681 } 682 return (NULL); 683 } 684 685 static int 686 wm_match(struct device *parent, struct cfdata *cf, void *aux) 687 { 688 struct pci_attach_args *pa = aux; 689 690 if (wm_lookup(pa) != NULL) 691 return (1); 692 693 return (0); 694 } 695 696 static void 697 wm_attach(struct device *parent, struct device *self, void *aux) 698 { 699 struct wm_softc *sc = (void *) self; 700 struct pci_attach_args *pa = aux; 701 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 702 pci_chipset_tag_t pc = pa->pa_pc; 703 pci_intr_handle_t ih; 704 size_t cdata_size; 705 const char *intrstr = NULL; 706 const char *eetype; 707 bus_space_tag_t memt; 708 bus_space_handle_t memh; 709 bus_dma_segment_t seg; 710 int memh_valid; 711 int i, rseg, error; 712 const struct wm_product *wmp; 713 uint8_t enaddr[ETHER_ADDR_LEN]; 714 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 715 pcireg_t preg, memtype; 716 uint32_t reg; 717 int pmreg; 718 719 callout_init(&sc->sc_tick_ch); 720 721 wmp = wm_lookup(pa); 722 if (wmp == NULL) { 723 printf("\n"); 724 panic("wm_attach: impossible"); 725 } 726 727 if (pci_dma64_available(pa)) 728 sc->sc_dmat = pa->pa_dmat64; 729 else 730 sc->sc_dmat = pa->pa_dmat; 731 732 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 733 aprint_naive(": Ethernet controller\n"); 734 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 735 736 sc->sc_type = wmp->wmp_type; 737 if (sc->sc_type < WM_T_82543) { 738 if (preg < 2) { 739 aprint_error("%s: i82542 must be at least rev. 2\n", 740 sc->sc_dev.dv_xname); 741 return; 742 } 743 if (preg < 3) 744 sc->sc_type = WM_T_82542_2_0; 745 } 746 747 /* 748 * Map the device. All devices support memory-mapped acccess, 749 * and it is really required for normal operation. 750 */ 751 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 752 switch (memtype) { 753 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 754 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 755 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 756 memtype, 0, &memt, &memh, NULL, NULL) == 0); 757 break; 758 default: 759 memh_valid = 0; 760 } 761 762 if (memh_valid) { 763 sc->sc_st = memt; 764 sc->sc_sh = memh; 765 } else { 766 aprint_error("%s: unable to map device registers\n", 767 sc->sc_dev.dv_xname); 768 return; 769 } 770 771 /* 772 * In addition, i82544 and later support I/O mapped indirect 773 * register access. It is not desirable (nor supported in 774 * this driver) to use it for normal operation, though it is 775 * required to work around bugs in some chip versions. 776 */ 777 if (sc->sc_type >= WM_T_82544) { 778 /* First we have to find the I/O BAR. */ 779 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 780 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 781 PCI_MAPREG_TYPE_IO) 782 break; 783 } 784 if (i == PCI_MAPREG_END) 785 aprint_error("%s: WARNING: unable to find I/O BAR\n", 786 sc->sc_dev.dv_xname); 787 else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 788 0, &sc->sc_iot, &sc->sc_ioh, 789 NULL, NULL) == 0) 790 sc->sc_flags |= WM_F_IOH_VALID; 791 else 792 aprint_error("%s: WARNING: unable to map I/O space\n", 793 sc->sc_dev.dv_xname); 794 } 795 796 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 797 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 798 preg |= PCI_COMMAND_MASTER_ENABLE; 799 if (sc->sc_type < WM_T_82542_2_1) 800 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 801 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 802 803 /* Get it out of power save mode, if needed. */ 804 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 805 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 806 PCI_PMCSR_STATE_MASK; 807 if (preg == PCI_PMCSR_STATE_D3) { 808 /* 809 * The card has lost all configuration data in 810 * this state, so punt. 811 */ 812 aprint_error("%s: unable to wake from power state D3\n", 813 sc->sc_dev.dv_xname); 814 return; 815 } 816 if (preg != PCI_PMCSR_STATE_D0) { 817 aprint_normal("%s: waking up from power state D%d\n", 818 sc->sc_dev.dv_xname, preg); 819 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 820 PCI_PMCSR_STATE_D0); 821 } 822 } 823 824 /* 825 * Map and establish our interrupt. 826 */ 827 if (pci_intr_map(pa, &ih)) { 828 aprint_error("%s: unable to map interrupt\n", 829 sc->sc_dev.dv_xname); 830 return; 831 } 832 intrstr = pci_intr_string(pc, ih); 833 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 834 if (sc->sc_ih == NULL) { 835 aprint_error("%s: unable to establish interrupt", 836 sc->sc_dev.dv_xname); 837 if (intrstr != NULL) 838 aprint_normal(" at %s", intrstr); 839 aprint_normal("\n"); 840 return; 841 } 842 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 843 844 /* 845 * Determine a few things about the bus we're connected to. 846 */ 847 if (sc->sc_type < WM_T_82543) { 848 /* We don't really know the bus characteristics here. */ 849 sc->sc_bus_speed = 33; 850 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 851 /* 852 * CSA (Communication Streaming Architecture) is about as fast 853 * a 32-bit 66MHz PCI Bus. 854 */ 855 sc->sc_flags |= WM_F_CSA; 856 sc->sc_bus_speed = 66; 857 aprint_verbose("%s: Communication Streaming Architecture\n", 858 sc->sc_dev.dv_xname); 859 if (sc->sc_type == WM_T_82547) { 860 callout_init(&sc->sc_txfifo_ch); 861 callout_setfunc(&sc->sc_txfifo_ch, 862 wm_82547_txfifo_stall, sc); 863 aprint_verbose("%s: using 82547 Tx FIFO stall " 864 "work-around\n", sc->sc_dev.dv_xname); 865 } 866 } else { 867 reg = CSR_READ(sc, WMREG_STATUS); 868 if (reg & STATUS_BUS64) 869 sc->sc_flags |= WM_F_BUS64; 870 if (sc->sc_type >= WM_T_82544 && 871 (reg & STATUS_PCIX_MODE) != 0) { 872 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 873 874 sc->sc_flags |= WM_F_PCIX; 875 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 876 PCI_CAP_PCIX, 877 &sc->sc_pcix_offset, NULL) == 0) 878 aprint_error("%s: unable to find PCIX " 879 "capability\n", sc->sc_dev.dv_xname); 880 else if (sc->sc_type != WM_T_82545_3 && 881 sc->sc_type != WM_T_82546_3) { 882 /* 883 * Work around a problem caused by the BIOS 884 * setting the max memory read byte count 885 * incorrectly. 886 */ 887 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 888 sc->sc_pcix_offset + PCI_PCIX_CMD); 889 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 890 sc->sc_pcix_offset + PCI_PCIX_STATUS); 891 892 bytecnt = 893 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 894 PCI_PCIX_CMD_BYTECNT_SHIFT; 895 maxb = 896 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 897 PCI_PCIX_STATUS_MAXB_SHIFT; 898 if (bytecnt > maxb) { 899 aprint_verbose("%s: resetting PCI-X " 900 "MMRBC: %d -> %d\n", 901 sc->sc_dev.dv_xname, 902 512 << bytecnt, 512 << maxb); 903 pcix_cmd = (pcix_cmd & 904 ~PCI_PCIX_CMD_BYTECNT_MASK) | 905 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 906 pci_conf_write(pa->pa_pc, pa->pa_tag, 907 sc->sc_pcix_offset + PCI_PCIX_CMD, 908 pcix_cmd); 909 } 910 } 911 } 912 /* 913 * The quad port adapter is special; it has a PCIX-PCIX 914 * bridge on the board, and can run the secondary bus at 915 * a higher speed. 916 */ 917 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 918 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 919 : 66; 920 } else if (sc->sc_flags & WM_F_PCIX) { 921 switch (reg & STATUS_PCIXSPD_MASK) { 922 case STATUS_PCIXSPD_50_66: 923 sc->sc_bus_speed = 66; 924 break; 925 case STATUS_PCIXSPD_66_100: 926 sc->sc_bus_speed = 100; 927 break; 928 case STATUS_PCIXSPD_100_133: 929 sc->sc_bus_speed = 133; 930 break; 931 default: 932 aprint_error( 933 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 934 sc->sc_dev.dv_xname, 935 reg & STATUS_PCIXSPD_MASK); 936 sc->sc_bus_speed = 66; 937 } 938 } else 939 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 940 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 941 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 942 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 943 } 944 945 /* 946 * Allocate the control data structures, and create and load the 947 * DMA map for it. 948 * 949 * NOTE: All Tx descriptors must be in the same 4G segment of 950 * memory. So must Rx descriptors. We simplify by allocating 951 * both sets within the same 4G segment. 952 */ 953 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 954 WM_NTXDESC_82542 : WM_NTXDESC_82544; 955 cdata_size = sc->sc_type < WM_T_82544 ? 956 sizeof(struct wm_control_data_82542) : 957 sizeof(struct wm_control_data_82544); 958 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 959 (bus_size_t) 0x100000000ULL, 960 &seg, 1, &rseg, 0)) != 0) { 961 aprint_error( 962 "%s: unable to allocate control data, error = %d\n", 963 sc->sc_dev.dv_xname, error); 964 goto fail_0; 965 } 966 967 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 968 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 969 aprint_error("%s: unable to map control data, error = %d\n", 970 sc->sc_dev.dv_xname, error); 971 goto fail_1; 972 } 973 974 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 975 0, 0, &sc->sc_cddmamap)) != 0) { 976 aprint_error("%s: unable to create control data DMA map, " 977 "error = %d\n", sc->sc_dev.dv_xname, error); 978 goto fail_2; 979 } 980 981 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 982 sc->sc_control_data, cdata_size, NULL, 983 0)) != 0) { 984 aprint_error( 985 "%s: unable to load control data DMA map, error = %d\n", 986 sc->sc_dev.dv_xname, error); 987 goto fail_3; 988 } 989 990 991 /* 992 * Create the transmit buffer DMA maps. 993 */ 994 WM_TXQUEUELEN(sc) = 995 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 996 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 997 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 998 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 999 WM_NTXSEGS, MCLBYTES, 0, 0, 1000 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1001 aprint_error("%s: unable to create Tx DMA map %d, " 1002 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1003 goto fail_4; 1004 } 1005 } 1006 1007 /* 1008 * Create the receive buffer DMA maps. 1009 */ 1010 for (i = 0; i < WM_NRXDESC; i++) { 1011 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1012 MCLBYTES, 0, 0, 1013 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1014 aprint_error("%s: unable to create Rx DMA map %d, " 1015 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1016 goto fail_5; 1017 } 1018 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1019 } 1020 1021 /* 1022 * Reset the chip to a known state. 1023 */ 1024 wm_reset(sc); 1025 1026 /* 1027 * Get some information about the EEPROM. 1028 */ 1029 if (sc->sc_type >= WM_T_82540) 1030 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1031 if (sc->sc_type <= WM_T_82544) 1032 sc->sc_ee_addrbits = 6; 1033 else if (sc->sc_type <= WM_T_82546_3) { 1034 reg = CSR_READ(sc, WMREG_EECD); 1035 if (reg & EECD_EE_SIZE) 1036 sc->sc_ee_addrbits = 8; 1037 else 1038 sc->sc_ee_addrbits = 6; 1039 } else if (sc->sc_type <= WM_T_82547_2) { 1040 reg = CSR_READ(sc, WMREG_EECD); 1041 if (reg & EECD_EE_TYPE) { 1042 sc->sc_flags |= WM_F_EEPROM_SPI; 1043 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1044 } else 1045 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1046 } else { 1047 /* Assume everything else is SPI. */ 1048 reg = CSR_READ(sc, WMREG_EECD); 1049 sc->sc_flags |= WM_F_EEPROM_SPI; 1050 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1051 } 1052 if (sc->sc_flags & WM_F_EEPROM_SPI) 1053 eetype = "SPI"; 1054 else 1055 eetype = "MicroWire"; 1056 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1057 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1058 sc->sc_ee_addrbits, eetype); 1059 1060 /* 1061 * Read the Ethernet address from the EEPROM. 1062 */ 1063 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1064 sizeof(myea) / sizeof(myea[0]), myea)) { 1065 aprint_error("%s: unable to read Ethernet address\n", 1066 sc->sc_dev.dv_xname); 1067 return; 1068 } 1069 enaddr[0] = myea[0] & 0xff; 1070 enaddr[1] = myea[0] >> 8; 1071 enaddr[2] = myea[1] & 0xff; 1072 enaddr[3] = myea[1] >> 8; 1073 enaddr[4] = myea[2] & 0xff; 1074 enaddr[5] = myea[2] >> 8; 1075 1076 /* 1077 * Toggle the LSB of the MAC address on the second port 1078 * of the i82546. 1079 */ 1080 if (sc->sc_type == WM_T_82546) { 1081 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1082 enaddr[5] ^= 1; 1083 } 1084 1085 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1086 ether_sprintf(enaddr)); 1087 1088 /* 1089 * Read the config info from the EEPROM, and set up various 1090 * bits in the control registers based on their contents. 1091 */ 1092 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1093 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1094 sc->sc_dev.dv_xname); 1095 return; 1096 } 1097 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1098 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1099 sc->sc_dev.dv_xname); 1100 return; 1101 } 1102 if (sc->sc_type >= WM_T_82544) { 1103 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1104 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1105 sc->sc_dev.dv_xname); 1106 return; 1107 } 1108 } 1109 1110 if (cfg1 & EEPROM_CFG1_ILOS) 1111 sc->sc_ctrl |= CTRL_ILOS; 1112 if (sc->sc_type >= WM_T_82544) { 1113 sc->sc_ctrl |= 1114 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1115 CTRL_SWDPIO_SHIFT; 1116 sc->sc_ctrl |= 1117 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1118 CTRL_SWDPINS_SHIFT; 1119 } else { 1120 sc->sc_ctrl |= 1121 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1122 CTRL_SWDPIO_SHIFT; 1123 } 1124 1125 #if 0 1126 if (sc->sc_type >= WM_T_82544) { 1127 if (cfg1 & EEPROM_CFG1_IPS0) 1128 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1129 if (cfg1 & EEPROM_CFG1_IPS1) 1130 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1131 sc->sc_ctrl_ext |= 1132 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1133 CTRL_EXT_SWDPIO_SHIFT; 1134 sc->sc_ctrl_ext |= 1135 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1136 CTRL_EXT_SWDPINS_SHIFT; 1137 } else { 1138 sc->sc_ctrl_ext |= 1139 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1140 CTRL_EXT_SWDPIO_SHIFT; 1141 } 1142 #endif 1143 1144 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1145 #if 0 1146 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1147 #endif 1148 1149 /* 1150 * Set up some register offsets that are different between 1151 * the i82542 and the i82543 and later chips. 1152 */ 1153 if (sc->sc_type < WM_T_82543) { 1154 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1155 sc->sc_tdt_reg = WMREG_OLD_TDT; 1156 } else { 1157 sc->sc_rdt_reg = WMREG_RDT; 1158 sc->sc_tdt_reg = WMREG_TDT; 1159 } 1160 1161 /* 1162 * Determine if we're TBI or GMII mode, and initialize the 1163 * media structures accordingly. 1164 */ 1165 if (sc->sc_type < WM_T_82543 || 1166 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1167 if (wmp->wmp_flags & WMP_F_1000T) 1168 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1169 "product!\n", sc->sc_dev.dv_xname); 1170 wm_tbi_mediainit(sc); 1171 } else { 1172 if (wmp->wmp_flags & WMP_F_1000X) 1173 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1174 "product!\n", sc->sc_dev.dv_xname); 1175 wm_gmii_mediainit(sc); 1176 } 1177 1178 ifp = &sc->sc_ethercom.ec_if; 1179 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1180 ifp->if_softc = sc; 1181 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1182 ifp->if_ioctl = wm_ioctl; 1183 ifp->if_start = wm_start; 1184 ifp->if_watchdog = wm_watchdog; 1185 ifp->if_init = wm_init; 1186 ifp->if_stop = wm_stop; 1187 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1188 IFQ_SET_READY(&ifp->if_snd); 1189 1190 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1191 1192 /* 1193 * If we're a i82543 or greater, we can support VLANs. 1194 */ 1195 if (sc->sc_type >= WM_T_82543) 1196 sc->sc_ethercom.ec_capabilities |= 1197 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1198 1199 /* 1200 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1201 * on i82543 and later. 1202 */ 1203 if (sc->sc_type >= WM_T_82543) 1204 ifp->if_capabilities |= 1205 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1206 1207 /* 1208 * Attach the interface. 1209 */ 1210 if_attach(ifp); 1211 ether_ifattach(ifp, enaddr); 1212 #if NRND > 0 1213 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1214 RND_TYPE_NET, 0); 1215 #endif 1216 1217 #ifdef WM_EVENT_COUNTERS 1218 /* Attach event counters. */ 1219 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1220 NULL, sc->sc_dev.dv_xname, "txsstall"); 1221 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1222 NULL, sc->sc_dev.dv_xname, "txdstall"); 1223 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1224 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1225 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1226 NULL, sc->sc_dev.dv_xname, "txdw"); 1227 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1228 NULL, sc->sc_dev.dv_xname, "txqe"); 1229 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1230 NULL, sc->sc_dev.dv_xname, "rxintr"); 1231 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1232 NULL, sc->sc_dev.dv_xname, "linkintr"); 1233 1234 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1235 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1236 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1237 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1238 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1239 NULL, sc->sc_dev.dv_xname, "txipsum"); 1240 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1241 NULL, sc->sc_dev.dv_xname, "txtusum"); 1242 1243 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 1244 NULL, sc->sc_dev.dv_xname, "txctx init"); 1245 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 1246 NULL, sc->sc_dev.dv_xname, "txctx hit"); 1247 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 1248 NULL, sc->sc_dev.dv_xname, "txctx miss"); 1249 1250 for (i = 0; i < WM_NTXSEGS; i++) { 1251 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1252 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1253 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1254 } 1255 1256 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1257 NULL, sc->sc_dev.dv_xname, "txdrop"); 1258 1259 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "tu"); 1261 1262 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1264 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1265 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1266 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1267 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1268 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1269 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1270 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1271 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1272 #endif /* WM_EVENT_COUNTERS */ 1273 1274 /* 1275 * Make sure the interface is shutdown during reboot. 1276 */ 1277 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1278 if (sc->sc_sdhook == NULL) 1279 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1280 sc->sc_dev.dv_xname); 1281 return; 1282 1283 /* 1284 * Free any resources we've allocated during the failed attach 1285 * attempt. Do this in reverse order and fall through. 1286 */ 1287 fail_5: 1288 for (i = 0; i < WM_NRXDESC; i++) { 1289 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1290 bus_dmamap_destroy(sc->sc_dmat, 1291 sc->sc_rxsoft[i].rxs_dmamap); 1292 } 1293 fail_4: 1294 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1295 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1296 bus_dmamap_destroy(sc->sc_dmat, 1297 sc->sc_txsoft[i].txs_dmamap); 1298 } 1299 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1300 fail_3: 1301 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1302 fail_2: 1303 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1304 cdata_size); 1305 fail_1: 1306 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1307 fail_0: 1308 return; 1309 } 1310 1311 /* 1312 * wm_shutdown: 1313 * 1314 * Make sure the interface is stopped at reboot time. 1315 */ 1316 static void 1317 wm_shutdown(void *arg) 1318 { 1319 struct wm_softc *sc = arg; 1320 1321 wm_stop(&sc->sc_ethercom.ec_if, 1); 1322 } 1323 1324 /* 1325 * wm_tx_cksum: 1326 * 1327 * Set up TCP/IP checksumming parameters for the 1328 * specified packet. 1329 */ 1330 static int 1331 wm_tx_cksum(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1332 uint8_t *fieldsp) 1333 { 1334 struct mbuf *m0 = txs->txs_mbuf; 1335 struct livengood_tcpip_ctxdesc *t; 1336 uint32_t ipcs, tucs; 1337 struct ip *ip; 1338 struct ether_header *eh; 1339 int offset, iphl; 1340 uint8_t fields = 0; 1341 1342 /* 1343 * XXX It would be nice if the mbuf pkthdr had offset 1344 * fields for the protocol headers. 1345 */ 1346 1347 eh = mtod(m0, struct ether_header *); 1348 switch (htons(eh->ether_type)) { 1349 case ETHERTYPE_IP: 1350 iphl = sizeof(struct ip); 1351 offset = ETHER_HDR_LEN; 1352 break; 1353 1354 case ETHERTYPE_VLAN: 1355 iphl = sizeof(struct ip); 1356 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1357 break; 1358 1359 default: 1360 /* 1361 * Don't support this protocol or encapsulation. 1362 */ 1363 *fieldsp = 0; 1364 *cmdp = 0; 1365 return (0); 1366 } 1367 1368 if (m0->m_len < (offset + iphl)) { 1369 if ((txs->txs_mbuf = m_pullup(m0, offset + iphl)) == NULL) { 1370 printf("%s: wm_tx_cksum: mbuf allocation failed, " 1371 "packet dropped\n", sc->sc_dev.dv_xname); 1372 return (ENOMEM); 1373 } 1374 m0 = txs->txs_mbuf; 1375 } 1376 1377 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 1378 iphl = ip->ip_hl << 2; 1379 1380 /* 1381 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1382 * offload feature, if we load the context descriptor, we 1383 * MUST provide valid values for IPCSS and TUCSS fields. 1384 */ 1385 1386 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1387 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1388 fields |= WTX_IXSM; 1389 ipcs = WTX_TCPIP_IPCSS(offset) | 1390 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1391 WTX_TCPIP_IPCSE(offset + iphl - 1); 1392 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1393 /* Use the cached value. */ 1394 ipcs = sc->sc_txctx_ipcs; 1395 } else { 1396 /* Just initialize it to the likely value anyway. */ 1397 ipcs = WTX_TCPIP_IPCSS(offset) | 1398 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1399 WTX_TCPIP_IPCSE(offset + iphl - 1); 1400 } 1401 1402 offset += iphl; 1403 1404 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1405 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1406 fields |= WTX_TXSM; 1407 tucs = WTX_TCPIP_TUCSS(offset) | 1408 WTX_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) | 1409 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1410 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1411 /* Use the cached value. */ 1412 tucs = sc->sc_txctx_tucs; 1413 } else { 1414 /* Just initialize it to a valid TCP context. */ 1415 tucs = WTX_TCPIP_TUCSS(offset) | 1416 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1417 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1418 } 1419 1420 if (sc->sc_txctx_ipcs == ipcs && 1421 sc->sc_txctx_tucs == tucs) { 1422 /* Cached context is fine. */ 1423 WM_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1424 } else { 1425 /* Fill in the context descriptor. */ 1426 #ifdef WM_EVENT_COUNTERS 1427 if (sc->sc_txctx_ipcs == 0xffffffff && 1428 sc->sc_txctx_tucs == 0xffffffff) 1429 WM_EVCNT_INCR(&sc->sc_ev_txctx_init); 1430 else 1431 WM_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1432 #endif 1433 t = (struct livengood_tcpip_ctxdesc *) 1434 &sc->sc_txdescs[sc->sc_txnext]; 1435 t->tcpip_ipcs = htole32(ipcs); 1436 t->tcpip_tucs = htole32(tucs); 1437 t->tcpip_cmdlen = htole32(WTX_CMD_DEXT | WTX_DTYP_C); 1438 t->tcpip_seg = 0; 1439 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1440 1441 sc->sc_txctx_ipcs = ipcs; 1442 sc->sc_txctx_tucs = tucs; 1443 1444 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1445 txs->txs_ndesc++; 1446 } 1447 1448 *cmdp = WTX_CMD_DEXT | WTX_DTYP_D; 1449 *fieldsp = fields; 1450 1451 return (0); 1452 } 1453 1454 static void 1455 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1456 { 1457 struct mbuf *m; 1458 int i; 1459 1460 printf("%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1461 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1462 printf("\tm_data = %p, m_len = %d, m_flags = 0x%08x\n", 1463 m->m_data, m->m_len, m->m_flags); 1464 printf("\t%d mbuf%s in chain\n", i, i == 1 ? "" : "s"); 1465 } 1466 1467 /* 1468 * wm_82547_txfifo_stall: 1469 * 1470 * Callout used to wait for the 82547 Tx FIFO to drain, 1471 * reset the FIFO pointers, and restart packet transmission. 1472 */ 1473 static void 1474 wm_82547_txfifo_stall(void *arg) 1475 { 1476 struct wm_softc *sc = arg; 1477 int s; 1478 1479 s = splnet(); 1480 1481 if (sc->sc_txfifo_stall) { 1482 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1483 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1484 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1485 /* 1486 * Packets have drained. Stop transmitter, reset 1487 * FIFO pointers, restart transmitter, and kick 1488 * the packet queue. 1489 */ 1490 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1491 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1492 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1493 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1494 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1495 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1496 CSR_WRITE(sc, WMREG_TCTL, tctl); 1497 CSR_WRITE_FLUSH(sc); 1498 1499 sc->sc_txfifo_head = 0; 1500 sc->sc_txfifo_stall = 0; 1501 wm_start(&sc->sc_ethercom.ec_if); 1502 } else { 1503 /* 1504 * Still waiting for packets to drain; try again in 1505 * another tick. 1506 */ 1507 callout_schedule(&sc->sc_txfifo_ch, 1); 1508 } 1509 } 1510 1511 splx(s); 1512 } 1513 1514 /* 1515 * wm_82547_txfifo_bugchk: 1516 * 1517 * Check for bug condition in the 82547 Tx FIFO. We need to 1518 * prevent enqueueing a packet that would wrap around the end 1519 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1520 * 1521 * We do this by checking the amount of space before the end 1522 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1523 * the Tx FIFO, wait for all remaining packets to drain, reset 1524 * the internal FIFO pointers to the beginning, and restart 1525 * transmission on the interface. 1526 */ 1527 #define WM_FIFO_HDR 0x10 1528 #define WM_82547_PAD_LEN 0x3e0 1529 static int 1530 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1531 { 1532 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1533 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1534 1535 /* Just return if already stalled. */ 1536 if (sc->sc_txfifo_stall) 1537 return (1); 1538 1539 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1540 /* Stall only occurs in half-duplex mode. */ 1541 goto send_packet; 1542 } 1543 1544 if (len >= WM_82547_PAD_LEN + space) { 1545 sc->sc_txfifo_stall = 1; 1546 callout_schedule(&sc->sc_txfifo_ch, 1); 1547 return (1); 1548 } 1549 1550 send_packet: 1551 sc->sc_txfifo_head += len; 1552 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1553 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1554 1555 return (0); 1556 } 1557 1558 /* 1559 * wm_start: [ifnet interface function] 1560 * 1561 * Start packet transmission on the interface. 1562 */ 1563 static void 1564 wm_start(struct ifnet *ifp) 1565 { 1566 struct wm_softc *sc = ifp->if_softc; 1567 struct mbuf *m0; 1568 #if 0 /* XXXJRT */ 1569 struct m_tag *mtag; 1570 #endif 1571 struct wm_txsoft *txs; 1572 bus_dmamap_t dmamap; 1573 int error, nexttx, lasttx = -1, ofree, seg; 1574 uint32_t cksumcmd; 1575 uint8_t cksumfields; 1576 1577 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1578 return; 1579 1580 /* 1581 * Remember the previous number of free descriptors. 1582 */ 1583 ofree = sc->sc_txfree; 1584 1585 /* 1586 * Loop through the send queue, setting up transmit descriptors 1587 * until we drain the queue, or use up all available transmit 1588 * descriptors. 1589 */ 1590 for (;;) { 1591 /* Grab a packet off the queue. */ 1592 IFQ_POLL(&ifp->if_snd, m0); 1593 if (m0 == NULL) 1594 break; 1595 1596 DPRINTF(WM_DEBUG_TX, 1597 ("%s: TX: have packet to transmit: %p\n", 1598 sc->sc_dev.dv_xname, m0)); 1599 1600 /* Get a work queue entry. */ 1601 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1602 wm_txintr(sc); 1603 if (sc->sc_txsfree == 0) { 1604 DPRINTF(WM_DEBUG_TX, 1605 ("%s: TX: no free job descriptors\n", 1606 sc->sc_dev.dv_xname)); 1607 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1608 break; 1609 } 1610 } 1611 1612 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1613 dmamap = txs->txs_dmamap; 1614 1615 /* 1616 * Load the DMA map. If this fails, the packet either 1617 * didn't fit in the allotted number of segments, or we 1618 * were short on resources. For the too-many-segments 1619 * case, we simply report an error and drop the packet, 1620 * since we can't sanely copy a jumbo packet to a single 1621 * buffer. 1622 */ 1623 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1624 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1625 if (error) { 1626 if (error == EFBIG) { 1627 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1628 printf("%s: Tx packet consumes too many " 1629 "DMA segments, dropping...\n", 1630 sc->sc_dev.dv_xname); 1631 IFQ_DEQUEUE(&ifp->if_snd, m0); 1632 wm_dump_mbuf_chain(sc, m0); 1633 m_freem(m0); 1634 continue; 1635 } 1636 /* 1637 * Short on resources, just stop for now. 1638 */ 1639 DPRINTF(WM_DEBUG_TX, 1640 ("%s: TX: dmamap load failed: %d\n", 1641 sc->sc_dev.dv_xname, error)); 1642 break; 1643 } 1644 1645 /* 1646 * Ensure we have enough descriptors free to describe 1647 * the packet. Note, we always reserve one descriptor 1648 * at the end of the ring due to the semantics of the 1649 * TDT register, plus one more in the event we need 1650 * to re-load checksum offload context. 1651 */ 1652 if (dmamap->dm_nsegs > (sc->sc_txfree - 2)) { 1653 /* 1654 * Not enough free descriptors to transmit this 1655 * packet. We haven't committed anything yet, 1656 * so just unload the DMA map, put the packet 1657 * pack on the queue, and punt. Notify the upper 1658 * layer that there are no more slots left. 1659 */ 1660 DPRINTF(WM_DEBUG_TX, 1661 ("%s: TX: need %d descriptors, have %d\n", 1662 sc->sc_dev.dv_xname, dmamap->dm_nsegs, 1663 sc->sc_txfree - 1)); 1664 ifp->if_flags |= IFF_OACTIVE; 1665 bus_dmamap_unload(sc->sc_dmat, dmamap); 1666 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1667 break; 1668 } 1669 1670 /* 1671 * Check for 82547 Tx FIFO bug. We need to do this 1672 * once we know we can transmit the packet, since we 1673 * do some internal FIFO space accounting here. 1674 */ 1675 if (sc->sc_type == WM_T_82547 && 1676 wm_82547_txfifo_bugchk(sc, m0)) { 1677 DPRINTF(WM_DEBUG_TX, 1678 ("%s: TX: 82547 Tx FIFO bug detected\n", 1679 sc->sc_dev.dv_xname)); 1680 ifp->if_flags |= IFF_OACTIVE; 1681 bus_dmamap_unload(sc->sc_dmat, dmamap); 1682 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1683 break; 1684 } 1685 1686 IFQ_DEQUEUE(&ifp->if_snd, m0); 1687 1688 /* 1689 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1690 */ 1691 1692 /* Sync the DMA map. */ 1693 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1694 BUS_DMASYNC_PREWRITE); 1695 1696 DPRINTF(WM_DEBUG_TX, 1697 ("%s: TX: packet has %d DMA segments\n", 1698 sc->sc_dev.dv_xname, dmamap->dm_nsegs)); 1699 1700 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1701 1702 /* 1703 * Store a pointer to the packet so that we can free it 1704 * later. 1705 * 1706 * Initially, we consider the number of descriptors the 1707 * packet uses the number of DMA segments. This may be 1708 * incremented by 1 if we do checksum offload (a descriptor 1709 * is used to set the checksum context). 1710 */ 1711 txs->txs_mbuf = m0; 1712 txs->txs_firstdesc = sc->sc_txnext; 1713 txs->txs_ndesc = dmamap->dm_nsegs; 1714 1715 /* 1716 * Set up checksum offload parameters for 1717 * this packet. 1718 */ 1719 if (m0->m_pkthdr.csum_flags & 1720 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1721 if (wm_tx_cksum(sc, txs, &cksumcmd, 1722 &cksumfields) != 0) { 1723 /* Error message already displayed. */ 1724 bus_dmamap_unload(sc->sc_dmat, dmamap); 1725 continue; 1726 } 1727 } else { 1728 cksumcmd = 0; 1729 cksumfields = 0; 1730 } 1731 1732 cksumcmd |= WTX_CMD_IDE; 1733 1734 /* 1735 * Initialize the transmit descriptor. 1736 */ 1737 for (nexttx = sc->sc_txnext, seg = 0; 1738 seg < dmamap->dm_nsegs; 1739 seg++, nexttx = WM_NEXTTX(sc, nexttx)) { 1740 wm_set_dma_addr(&sc->sc_txdescs[nexttx].wtx_addr, 1741 dmamap->dm_segs[seg].ds_addr); 1742 sc->sc_txdescs[nexttx].wtx_cmdlen = 1743 htole32(cksumcmd | dmamap->dm_segs[seg].ds_len); 1744 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 0; 1745 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1746 cksumfields; 1747 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1748 lasttx = nexttx; 1749 1750 DPRINTF(WM_DEBUG_TX, 1751 ("%s: TX: desc %d: low 0x%08x, len 0x%04x\n", 1752 sc->sc_dev.dv_xname, nexttx, 1753 (u_int)le32toh(dmamap->dm_segs[seg].ds_addr), 1754 (u_int)le32toh(dmamap->dm_segs[seg].ds_len))); 1755 } 1756 1757 KASSERT(lasttx != -1); 1758 1759 /* 1760 * Set up the command byte on the last descriptor of 1761 * the packet. If we're in the interrupt delay window, 1762 * delay the interrupt. 1763 */ 1764 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1765 htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS); 1766 1767 #if 0 /* XXXJRT */ 1768 /* 1769 * If VLANs are enabled and the packet has a VLAN tag, set 1770 * up the descriptor to encapsulate the packet for us. 1771 * 1772 * This is only valid on the last descriptor of the packet. 1773 */ 1774 if (sc->sc_ethercom.ec_nvlans != 0 && 1775 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1776 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1777 htole32(WTX_CMD_VLE); 1778 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1779 = htole16(*(u_int *)(mtag + 1) & 0xffff); 1780 } 1781 #endif /* XXXJRT */ 1782 1783 txs->txs_lastdesc = lasttx; 1784 1785 DPRINTF(WM_DEBUG_TX, 1786 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1787 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1788 1789 /* Sync the descriptors we're using. */ 1790 WM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1791 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1792 1793 /* Give the packet to the chip. */ 1794 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1795 1796 DPRINTF(WM_DEBUG_TX, 1797 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1798 1799 DPRINTF(WM_DEBUG_TX, 1800 ("%s: TX: finished transmitting packet, job %d\n", 1801 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1802 1803 /* Advance the tx pointer. */ 1804 sc->sc_txfree -= txs->txs_ndesc; 1805 sc->sc_txnext = nexttx; 1806 1807 sc->sc_txsfree--; 1808 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1809 1810 #if NBPFILTER > 0 1811 /* Pass the packet to any BPF listeners. */ 1812 if (ifp->if_bpf) 1813 bpf_mtap(ifp->if_bpf, m0); 1814 #endif /* NBPFILTER > 0 */ 1815 } 1816 1817 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1818 /* No more slots; notify upper layer. */ 1819 ifp->if_flags |= IFF_OACTIVE; 1820 } 1821 1822 if (sc->sc_txfree != ofree) { 1823 /* Set a watchdog timer in case the chip flakes out. */ 1824 ifp->if_timer = 5; 1825 } 1826 } 1827 1828 /* 1829 * wm_watchdog: [ifnet interface function] 1830 * 1831 * Watchdog timer handler. 1832 */ 1833 static void 1834 wm_watchdog(struct ifnet *ifp) 1835 { 1836 struct wm_softc *sc = ifp->if_softc; 1837 1838 /* 1839 * Since we're using delayed interrupts, sweep up 1840 * before we report an error. 1841 */ 1842 wm_txintr(sc); 1843 1844 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1845 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1846 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1847 sc->sc_txnext); 1848 ifp->if_oerrors++; 1849 1850 /* Reset the interface. */ 1851 (void) wm_init(ifp); 1852 } 1853 1854 /* Try to get more packets going. */ 1855 wm_start(ifp); 1856 } 1857 1858 /* 1859 * wm_ioctl: [ifnet interface function] 1860 * 1861 * Handle control requests from the operator. 1862 */ 1863 static int 1864 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1865 { 1866 struct wm_softc *sc = ifp->if_softc; 1867 struct ifreq *ifr = (struct ifreq *) data; 1868 int s, error; 1869 1870 s = splnet(); 1871 1872 switch (cmd) { 1873 case SIOCSIFMEDIA: 1874 case SIOCGIFMEDIA: 1875 /* Flow control requires full-duplex mode. */ 1876 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1877 (ifr->ifr_media & IFM_FDX) == 0) 1878 ifr->ifr_media &= ~IFM_ETH_FMASK; 1879 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1880 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1881 /* We can do both TXPAUSE and RXPAUSE. */ 1882 ifr->ifr_media |= 1883 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1884 } 1885 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1886 } 1887 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1888 break; 1889 default: 1890 error = ether_ioctl(ifp, cmd, data); 1891 if (error == ENETRESET) { 1892 /* 1893 * Multicast list has changed; set the hardware filter 1894 * accordingly. 1895 */ 1896 wm_set_filter(sc); 1897 error = 0; 1898 } 1899 break; 1900 } 1901 1902 /* Try to get more packets going. */ 1903 wm_start(ifp); 1904 1905 splx(s); 1906 return (error); 1907 } 1908 1909 /* 1910 * wm_intr: 1911 * 1912 * Interrupt service routine. 1913 */ 1914 static int 1915 wm_intr(void *arg) 1916 { 1917 struct wm_softc *sc = arg; 1918 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1919 uint32_t icr; 1920 int wantinit, handled = 0; 1921 1922 for (wantinit = 0; wantinit == 0;) { 1923 icr = CSR_READ(sc, WMREG_ICR); 1924 if ((icr & sc->sc_icr) == 0) 1925 break; 1926 1927 #if 0 /*NRND > 0*/ 1928 if (RND_ENABLED(&sc->rnd_source)) 1929 rnd_add_uint32(&sc->rnd_source, icr); 1930 #endif 1931 1932 handled = 1; 1933 1934 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1935 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1936 DPRINTF(WM_DEBUG_RX, 1937 ("%s: RX: got Rx intr 0x%08x\n", 1938 sc->sc_dev.dv_xname, 1939 icr & (ICR_RXDMT0|ICR_RXT0))); 1940 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 1941 } 1942 #endif 1943 wm_rxintr(sc); 1944 1945 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1946 if (icr & ICR_TXDW) { 1947 DPRINTF(WM_DEBUG_TX, 1948 ("%s: TX: got TXDW interrupt\n", 1949 sc->sc_dev.dv_xname)); 1950 WM_EVCNT_INCR(&sc->sc_ev_txdw); 1951 } 1952 #endif 1953 wm_txintr(sc); 1954 1955 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 1956 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 1957 wm_linkintr(sc, icr); 1958 } 1959 1960 if (icr & ICR_RXO) { 1961 printf("%s: Receive overrun\n", sc->sc_dev.dv_xname); 1962 wantinit = 1; 1963 } 1964 } 1965 1966 if (handled) { 1967 if (wantinit) 1968 wm_init(ifp); 1969 1970 /* Try to get more packets going. */ 1971 wm_start(ifp); 1972 } 1973 1974 return (handled); 1975 } 1976 1977 /* 1978 * wm_txintr: 1979 * 1980 * Helper; handle transmit interrupts. 1981 */ 1982 static void 1983 wm_txintr(struct wm_softc *sc) 1984 { 1985 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1986 struct wm_txsoft *txs; 1987 uint8_t status; 1988 int i; 1989 1990 ifp->if_flags &= ~IFF_OACTIVE; 1991 1992 /* 1993 * Go through the Tx list and free mbufs for those 1994 * frames which have been transmitted. 1995 */ 1996 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 1997 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 1998 txs = &sc->sc_txsoft[i]; 1999 2000 DPRINTF(WM_DEBUG_TX, 2001 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2002 2003 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 2004 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2005 2006 status = 2007 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2008 if ((status & WTX_ST_DD) == 0) { 2009 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2010 BUS_DMASYNC_PREREAD); 2011 break; 2012 } 2013 2014 DPRINTF(WM_DEBUG_TX, 2015 ("%s: TX: job %d done: descs %d..%d\n", 2016 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2017 txs->txs_lastdesc)); 2018 2019 /* 2020 * XXX We should probably be using the statistics 2021 * XXX registers, but I don't know if they exist 2022 * XXX on chips before the i82544. 2023 */ 2024 2025 #ifdef WM_EVENT_COUNTERS 2026 if (status & WTX_ST_TU) 2027 WM_EVCNT_INCR(&sc->sc_ev_tu); 2028 #endif /* WM_EVENT_COUNTERS */ 2029 2030 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2031 ifp->if_oerrors++; 2032 if (status & WTX_ST_LC) 2033 printf("%s: late collision\n", 2034 sc->sc_dev.dv_xname); 2035 else if (status & WTX_ST_EC) { 2036 ifp->if_collisions += 16; 2037 printf("%s: excessive collisions\n", 2038 sc->sc_dev.dv_xname); 2039 } 2040 } else 2041 ifp->if_opackets++; 2042 2043 sc->sc_txfree += txs->txs_ndesc; 2044 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2045 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2046 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2047 m_freem(txs->txs_mbuf); 2048 txs->txs_mbuf = NULL; 2049 } 2050 2051 /* Update the dirty transmit buffer pointer. */ 2052 sc->sc_txsdirty = i; 2053 DPRINTF(WM_DEBUG_TX, 2054 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2055 2056 /* 2057 * If there are no more pending transmissions, cancel the watchdog 2058 * timer. 2059 */ 2060 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2061 ifp->if_timer = 0; 2062 } 2063 2064 /* 2065 * wm_rxintr: 2066 * 2067 * Helper; handle receive interrupts. 2068 */ 2069 static void 2070 wm_rxintr(struct wm_softc *sc) 2071 { 2072 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2073 struct wm_rxsoft *rxs; 2074 struct mbuf *m; 2075 int i, len; 2076 uint8_t status, errors; 2077 2078 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2079 rxs = &sc->sc_rxsoft[i]; 2080 2081 DPRINTF(WM_DEBUG_RX, 2082 ("%s: RX: checking descriptor %d\n", 2083 sc->sc_dev.dv_xname, i)); 2084 2085 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2086 2087 status = sc->sc_rxdescs[i].wrx_status; 2088 errors = sc->sc_rxdescs[i].wrx_errors; 2089 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2090 2091 if ((status & WRX_ST_DD) == 0) { 2092 /* 2093 * We have processed all of the receive descriptors. 2094 */ 2095 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2096 break; 2097 } 2098 2099 if (__predict_false(sc->sc_rxdiscard)) { 2100 DPRINTF(WM_DEBUG_RX, 2101 ("%s: RX: discarding contents of descriptor %d\n", 2102 sc->sc_dev.dv_xname, i)); 2103 WM_INIT_RXDESC(sc, i); 2104 if (status & WRX_ST_EOP) { 2105 /* Reset our state. */ 2106 DPRINTF(WM_DEBUG_RX, 2107 ("%s: RX: resetting rxdiscard -> 0\n", 2108 sc->sc_dev.dv_xname)); 2109 sc->sc_rxdiscard = 0; 2110 } 2111 continue; 2112 } 2113 2114 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2115 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2116 2117 m = rxs->rxs_mbuf; 2118 2119 /* 2120 * Add a new receive buffer to the ring. 2121 */ 2122 if (wm_add_rxbuf(sc, i) != 0) { 2123 /* 2124 * Failed, throw away what we've done so 2125 * far, and discard the rest of the packet. 2126 */ 2127 ifp->if_ierrors++; 2128 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2129 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2130 WM_INIT_RXDESC(sc, i); 2131 if ((status & WRX_ST_EOP) == 0) 2132 sc->sc_rxdiscard = 1; 2133 if (sc->sc_rxhead != NULL) 2134 m_freem(sc->sc_rxhead); 2135 WM_RXCHAIN_RESET(sc); 2136 DPRINTF(WM_DEBUG_RX, 2137 ("%s: RX: Rx buffer allocation failed, " 2138 "dropping packet%s\n", sc->sc_dev.dv_xname, 2139 sc->sc_rxdiscard ? " (discard)" : "")); 2140 continue; 2141 } 2142 2143 WM_RXCHAIN_LINK(sc, m); 2144 2145 m->m_len = len; 2146 2147 DPRINTF(WM_DEBUG_RX, 2148 ("%s: RX: buffer at %p len %d\n", 2149 sc->sc_dev.dv_xname, m->m_data, len)); 2150 2151 /* 2152 * If this is not the end of the packet, keep 2153 * looking. 2154 */ 2155 if ((status & WRX_ST_EOP) == 0) { 2156 sc->sc_rxlen += len; 2157 DPRINTF(WM_DEBUG_RX, 2158 ("%s: RX: not yet EOP, rxlen -> %d\n", 2159 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2160 continue; 2161 } 2162 2163 /* 2164 * Okay, we have the entire packet now... 2165 */ 2166 *sc->sc_rxtailp = NULL; 2167 m = sc->sc_rxhead; 2168 len += sc->sc_rxlen; 2169 2170 WM_RXCHAIN_RESET(sc); 2171 2172 DPRINTF(WM_DEBUG_RX, 2173 ("%s: RX: have entire packet, len -> %d\n", 2174 sc->sc_dev.dv_xname, len)); 2175 2176 /* 2177 * If an error occurred, update stats and drop the packet. 2178 */ 2179 if (errors & 2180 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2181 ifp->if_ierrors++; 2182 if (errors & WRX_ER_SE) 2183 printf("%s: symbol error\n", 2184 sc->sc_dev.dv_xname); 2185 else if (errors & WRX_ER_SEQ) 2186 printf("%s: receive sequence error\n", 2187 sc->sc_dev.dv_xname); 2188 else if (errors & WRX_ER_CE) 2189 printf("%s: CRC error\n", 2190 sc->sc_dev.dv_xname); 2191 m_freem(m); 2192 continue; 2193 } 2194 2195 /* 2196 * No errors. Receive the packet. 2197 * 2198 * Note, we have configured the chip to include the 2199 * CRC with every packet. 2200 */ 2201 m->m_flags |= M_HASFCS; 2202 m->m_pkthdr.rcvif = ifp; 2203 m->m_pkthdr.len = len; 2204 2205 #if 0 /* XXXJRT */ 2206 /* 2207 * If VLANs are enabled, VLAN packets have been unwrapped 2208 * for us. Associate the tag with the packet. 2209 */ 2210 if (sc->sc_ethercom.ec_nvlans != 0 && 2211 (status & WRX_ST_VP) != 0) { 2212 struct m_tag *vtag; 2213 2214 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2215 M_NOWAIT); 2216 if (vtag == NULL) { 2217 ifp->if_ierrors++; 2218 printf("%s: unable to allocate VLAN tag\n", 2219 sc->sc_dev.dv_xname); 2220 m_freem(m); 2221 continue; 2222 } 2223 2224 *(u_int *)(vtag + 1) = 2225 le16toh(sc->sc_rxdescs[i].wrx_special); 2226 } 2227 #endif /* XXXJRT */ 2228 2229 /* 2230 * Set up checksum info for this packet. 2231 */ 2232 if (status & WRX_ST_IPCS) { 2233 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2234 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2235 if (errors & WRX_ER_IPE) 2236 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2237 } 2238 if (status & WRX_ST_TCPCS) { 2239 /* 2240 * Note: we don't know if this was TCP or UDP, 2241 * so we just set both bits, and expect the 2242 * upper layers to deal. 2243 */ 2244 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2245 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2246 if (errors & WRX_ER_TCPE) 2247 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2248 } 2249 2250 ifp->if_ipackets++; 2251 2252 #if NBPFILTER > 0 2253 /* Pass this up to any BPF listeners. */ 2254 if (ifp->if_bpf) 2255 bpf_mtap(ifp->if_bpf, m); 2256 #endif /* NBPFILTER > 0 */ 2257 2258 /* Pass it on. */ 2259 (*ifp->if_input)(ifp, m); 2260 } 2261 2262 /* Update the receive pointer. */ 2263 sc->sc_rxptr = i; 2264 2265 DPRINTF(WM_DEBUG_RX, 2266 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2267 } 2268 2269 /* 2270 * wm_linkintr: 2271 * 2272 * Helper; handle link interrupts. 2273 */ 2274 static void 2275 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2276 { 2277 uint32_t status; 2278 2279 /* 2280 * If we get a link status interrupt on a 1000BASE-T 2281 * device, just fall into the normal MII tick path. 2282 */ 2283 if (sc->sc_flags & WM_F_HAS_MII) { 2284 if (icr & ICR_LSC) { 2285 DPRINTF(WM_DEBUG_LINK, 2286 ("%s: LINK: LSC -> mii_tick\n", 2287 sc->sc_dev.dv_xname)); 2288 mii_tick(&sc->sc_mii); 2289 } else if (icr & ICR_RXSEQ) { 2290 DPRINTF(WM_DEBUG_LINK, 2291 ("%s: LINK Receive sequence error\n", 2292 sc->sc_dev.dv_xname)); 2293 } 2294 return; 2295 } 2296 2297 /* 2298 * If we are now receiving /C/, check for link again in 2299 * a couple of link clock ticks. 2300 */ 2301 if (icr & ICR_RXCFG) { 2302 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2303 sc->sc_dev.dv_xname)); 2304 sc->sc_tbi_anstate = 2; 2305 } 2306 2307 if (icr & ICR_LSC) { 2308 status = CSR_READ(sc, WMREG_STATUS); 2309 if (status & STATUS_LU) { 2310 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2311 sc->sc_dev.dv_xname, 2312 (status & STATUS_FD) ? "FDX" : "HDX")); 2313 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2314 sc->sc_fcrtl &= ~FCRTL_XONE; 2315 if (status & STATUS_FD) 2316 sc->sc_tctl |= 2317 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2318 else 2319 sc->sc_tctl |= 2320 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2321 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2322 sc->sc_fcrtl |= FCRTL_XONE; 2323 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2324 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2325 WMREG_OLD_FCRTL : WMREG_FCRTL, 2326 sc->sc_fcrtl); 2327 sc->sc_tbi_linkup = 1; 2328 } else { 2329 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2330 sc->sc_dev.dv_xname)); 2331 sc->sc_tbi_linkup = 0; 2332 } 2333 sc->sc_tbi_anstate = 2; 2334 wm_tbi_set_linkled(sc); 2335 } else if (icr & ICR_RXSEQ) { 2336 DPRINTF(WM_DEBUG_LINK, 2337 ("%s: LINK: Receive sequence error\n", 2338 sc->sc_dev.dv_xname)); 2339 } 2340 } 2341 2342 /* 2343 * wm_tick: 2344 * 2345 * One second timer, used to check link status, sweep up 2346 * completed transmit jobs, etc. 2347 */ 2348 static void 2349 wm_tick(void *arg) 2350 { 2351 struct wm_softc *sc = arg; 2352 int s; 2353 2354 s = splnet(); 2355 2356 if (sc->sc_type >= WM_T_82542_2_1) { 2357 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2358 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2359 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2360 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2361 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2362 } 2363 2364 if (sc->sc_flags & WM_F_HAS_MII) 2365 mii_tick(&sc->sc_mii); 2366 else 2367 wm_tbi_check_link(sc); 2368 2369 splx(s); 2370 2371 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2372 } 2373 2374 /* 2375 * wm_reset: 2376 * 2377 * Reset the i82542 chip. 2378 */ 2379 static void 2380 wm_reset(struct wm_softc *sc) 2381 { 2382 int i; 2383 2384 /* 2385 * Allocate on-chip memory according to the MTU size. 2386 * The Packet Buffer Allocation register must be written 2387 * before the chip is reset. 2388 */ 2389 if (sc->sc_type < WM_T_82547) { 2390 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2391 PBA_40K : PBA_48K; 2392 } else { 2393 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2394 PBA_22K : PBA_30K; 2395 sc->sc_txfifo_head = 0; 2396 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2397 sc->sc_txfifo_size = 2398 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2399 sc->sc_txfifo_stall = 0; 2400 } 2401 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2402 2403 switch (sc->sc_type) { 2404 case WM_T_82544: 2405 case WM_T_82540: 2406 case WM_T_82545: 2407 case WM_T_82546: 2408 case WM_T_82541: 2409 case WM_T_82541_2: 2410 /* 2411 * These chips have a problem with the memory-mapped 2412 * write cycle when issuing the reset, so use I/O-mapped 2413 * access, if possible. 2414 */ 2415 if (sc->sc_flags & WM_F_IOH_VALID) 2416 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2417 else 2418 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2419 break; 2420 2421 case WM_T_82545_3: 2422 case WM_T_82546_3: 2423 /* Use the shadow control register on these chips. */ 2424 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2425 break; 2426 2427 default: 2428 /* Everything else can safely use the documented method. */ 2429 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2430 break; 2431 } 2432 delay(10000); 2433 2434 for (i = 0; i < 1000; i++) { 2435 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2436 return; 2437 delay(20); 2438 } 2439 2440 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2441 printf("%s: WARNING: reset failed to complete\n", 2442 sc->sc_dev.dv_xname); 2443 } 2444 2445 /* 2446 * wm_init: [ifnet interface function] 2447 * 2448 * Initialize the interface. Must be called at splnet(). 2449 */ 2450 static int 2451 wm_init(struct ifnet *ifp) 2452 { 2453 struct wm_softc *sc = ifp->if_softc; 2454 struct wm_rxsoft *rxs; 2455 int i, error = 0; 2456 uint32_t reg; 2457 2458 /* 2459 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2460 * There is a small but measurable benefit to avoiding the adjusment 2461 * of the descriptor so that the headers are aligned, for normal mtu, 2462 * on such platforms. One possibility is that the DMA itself is 2463 * slightly more efficient if the front of the entire packet (instead 2464 * of the front of the headers) is aligned. 2465 * 2466 * Note we must always set align_tweak to 0 if we are using 2467 * jumbo frames. 2468 */ 2469 #ifdef __NO_STRICT_ALIGNMENT 2470 sc->sc_align_tweak = 0; 2471 #else 2472 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2473 sc->sc_align_tweak = 0; 2474 else 2475 sc->sc_align_tweak = 2; 2476 #endif /* __NO_STRICT_ALIGNMENT */ 2477 2478 /* Cancel any pending I/O. */ 2479 wm_stop(ifp, 0); 2480 2481 /* Reset the chip to a known state. */ 2482 wm_reset(sc); 2483 2484 /* Initialize the transmit descriptor ring. */ 2485 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2486 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2487 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2488 sc->sc_txfree = WM_NTXDESC(sc); 2489 sc->sc_txnext = 0; 2490 2491 sc->sc_txctx_ipcs = 0xffffffff; 2492 sc->sc_txctx_tucs = 0xffffffff; 2493 2494 if (sc->sc_type < WM_T_82543) { 2495 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2496 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2497 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2498 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2499 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2500 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2501 } else { 2502 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2503 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2504 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2505 CSR_WRITE(sc, WMREG_TDH, 0); 2506 CSR_WRITE(sc, WMREG_TDT, 0); 2507 CSR_WRITE(sc, WMREG_TIDV, 128); 2508 2509 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2510 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2511 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2512 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2513 } 2514 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2515 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2516 2517 /* Initialize the transmit job descriptors. */ 2518 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2519 sc->sc_txsoft[i].txs_mbuf = NULL; 2520 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2521 sc->sc_txsnext = 0; 2522 sc->sc_txsdirty = 0; 2523 2524 /* 2525 * Initialize the receive descriptor and receive job 2526 * descriptor rings. 2527 */ 2528 if (sc->sc_type < WM_T_82543) { 2529 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2530 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2531 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2532 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2533 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2534 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2535 2536 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2537 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2538 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2539 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2540 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2541 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2542 } else { 2543 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2544 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2545 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2546 CSR_WRITE(sc, WMREG_RDH, 0); 2547 CSR_WRITE(sc, WMREG_RDT, 0); 2548 CSR_WRITE(sc, WMREG_RDTR, 28 | RDTR_FPD); 2549 } 2550 for (i = 0; i < WM_NRXDESC; i++) { 2551 rxs = &sc->sc_rxsoft[i]; 2552 if (rxs->rxs_mbuf == NULL) { 2553 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2554 printf("%s: unable to allocate or map rx " 2555 "buffer %d, error = %d\n", 2556 sc->sc_dev.dv_xname, i, error); 2557 /* 2558 * XXX Should attempt to run with fewer receive 2559 * XXX buffers instead of just failing. 2560 */ 2561 wm_rxdrain(sc); 2562 goto out; 2563 } 2564 } else 2565 WM_INIT_RXDESC(sc, i); 2566 } 2567 sc->sc_rxptr = 0; 2568 sc->sc_rxdiscard = 0; 2569 WM_RXCHAIN_RESET(sc); 2570 2571 /* 2572 * Clear out the VLAN table -- we don't use it (yet). 2573 */ 2574 CSR_WRITE(sc, WMREG_VET, 0); 2575 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2576 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2577 2578 /* 2579 * Set up flow-control parameters. 2580 * 2581 * XXX Values could probably stand some tuning. 2582 */ 2583 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2584 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2585 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2586 2587 sc->sc_fcrtl = FCRTL_DFLT; 2588 if (sc->sc_type < WM_T_82543) { 2589 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2590 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2591 } else { 2592 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2593 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2594 } 2595 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2596 2597 #if 0 /* XXXJRT */ 2598 /* Deal with VLAN enables. */ 2599 if (sc->sc_ethercom.ec_nvlans != 0) 2600 sc->sc_ctrl |= CTRL_VME; 2601 else 2602 #endif /* XXXJRT */ 2603 sc->sc_ctrl &= ~CTRL_VME; 2604 2605 /* Write the control registers. */ 2606 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2607 #if 0 2608 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2609 #endif 2610 2611 /* 2612 * Set up checksum offload parameters. 2613 */ 2614 reg = CSR_READ(sc, WMREG_RXCSUM); 2615 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2616 reg |= RXCSUM_IPOFL; 2617 else 2618 reg &= ~RXCSUM_IPOFL; 2619 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2620 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2621 else { 2622 reg &= ~RXCSUM_TUOFL; 2623 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2624 reg &= ~RXCSUM_IPOFL; 2625 } 2626 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2627 2628 /* 2629 * Set up the interrupt registers. 2630 */ 2631 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2632 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2633 ICR_RXO | ICR_RXT0; 2634 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2635 sc->sc_icr |= ICR_RXCFG; 2636 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2637 2638 /* Set up the inter-packet gap. */ 2639 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2640 2641 #if 0 /* XXXJRT */ 2642 /* Set the VLAN ethernetype. */ 2643 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2644 #endif 2645 2646 /* 2647 * Set up the transmit control register; we start out with 2648 * a collision distance suitable for FDX, but update it whe 2649 * we resolve the media type. 2650 */ 2651 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2652 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2653 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2654 2655 /* Set the media. */ 2656 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2657 2658 /* 2659 * Set up the receive control register; we actually program 2660 * the register when we set the receive filter. Use multicast 2661 * address offset type 0. 2662 * 2663 * Only the i82544 has the ability to strip the incoming 2664 * CRC, so we don't enable that feature. 2665 */ 2666 sc->sc_mchash_type = 0; 2667 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2668 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2669 2670 if(MCLBYTES == 2048) { 2671 sc->sc_rctl |= RCTL_2k; 2672 } else { 2673 if(sc->sc_type >= WM_T_82543) { 2674 switch(MCLBYTES) { 2675 case 4096: 2676 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2677 break; 2678 case 8192: 2679 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2680 break; 2681 case 16384: 2682 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2683 break; 2684 default: 2685 panic("wm_init: MCLBYTES %d unsupported", 2686 MCLBYTES); 2687 break; 2688 } 2689 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2690 } 2691 2692 /* Set the receive filter. */ 2693 wm_set_filter(sc); 2694 2695 /* Start the one second link check clock. */ 2696 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2697 2698 /* ...all done! */ 2699 ifp->if_flags |= IFF_RUNNING; 2700 ifp->if_flags &= ~IFF_OACTIVE; 2701 2702 out: 2703 if (error) 2704 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2705 return (error); 2706 } 2707 2708 /* 2709 * wm_rxdrain: 2710 * 2711 * Drain the receive queue. 2712 */ 2713 static void 2714 wm_rxdrain(struct wm_softc *sc) 2715 { 2716 struct wm_rxsoft *rxs; 2717 int i; 2718 2719 for (i = 0; i < WM_NRXDESC; i++) { 2720 rxs = &sc->sc_rxsoft[i]; 2721 if (rxs->rxs_mbuf != NULL) { 2722 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2723 m_freem(rxs->rxs_mbuf); 2724 rxs->rxs_mbuf = NULL; 2725 } 2726 } 2727 } 2728 2729 /* 2730 * wm_stop: [ifnet interface function] 2731 * 2732 * Stop transmission on the interface. 2733 */ 2734 static void 2735 wm_stop(struct ifnet *ifp, int disable) 2736 { 2737 struct wm_softc *sc = ifp->if_softc; 2738 struct wm_txsoft *txs; 2739 int i; 2740 2741 /* Stop the one second clock. */ 2742 callout_stop(&sc->sc_tick_ch); 2743 2744 /* Stop the 82547 Tx FIFO stall check timer. */ 2745 if (sc->sc_type == WM_T_82547) 2746 callout_stop(&sc->sc_txfifo_ch); 2747 2748 if (sc->sc_flags & WM_F_HAS_MII) { 2749 /* Down the MII. */ 2750 mii_down(&sc->sc_mii); 2751 } 2752 2753 /* Stop the transmit and receive processes. */ 2754 CSR_WRITE(sc, WMREG_TCTL, 0); 2755 CSR_WRITE(sc, WMREG_RCTL, 0); 2756 2757 /* Release any queued transmit buffers. */ 2758 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2759 txs = &sc->sc_txsoft[i]; 2760 if (txs->txs_mbuf != NULL) { 2761 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2762 m_freem(txs->txs_mbuf); 2763 txs->txs_mbuf = NULL; 2764 } 2765 } 2766 2767 if (disable) 2768 wm_rxdrain(sc); 2769 2770 /* Mark the interface as down and cancel the watchdog timer. */ 2771 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2772 ifp->if_timer = 0; 2773 } 2774 2775 /* 2776 * wm_acquire_eeprom: 2777 * 2778 * Perform the EEPROM handshake required on some chips. 2779 */ 2780 static int 2781 wm_acquire_eeprom(struct wm_softc *sc) 2782 { 2783 uint32_t reg; 2784 int x; 2785 2786 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2787 reg = CSR_READ(sc, WMREG_EECD); 2788 2789 /* Request EEPROM access. */ 2790 reg |= EECD_EE_REQ; 2791 CSR_WRITE(sc, WMREG_EECD, reg); 2792 2793 /* ..and wait for it to be granted. */ 2794 for (x = 0; x < 100; x++) { 2795 reg = CSR_READ(sc, WMREG_EECD); 2796 if (reg & EECD_EE_GNT) 2797 break; 2798 delay(5); 2799 } 2800 if ((reg & EECD_EE_GNT) == 0) { 2801 aprint_error("%s: could not acquire EEPROM GNT\n", 2802 sc->sc_dev.dv_xname); 2803 reg &= ~EECD_EE_REQ; 2804 CSR_WRITE(sc, WMREG_EECD, reg); 2805 return (1); 2806 } 2807 } 2808 2809 return (0); 2810 } 2811 2812 /* 2813 * wm_release_eeprom: 2814 * 2815 * Release the EEPROM mutex. 2816 */ 2817 static void 2818 wm_release_eeprom(struct wm_softc *sc) 2819 { 2820 uint32_t reg; 2821 2822 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2823 reg = CSR_READ(sc, WMREG_EECD); 2824 reg &= ~EECD_EE_REQ; 2825 CSR_WRITE(sc, WMREG_EECD, reg); 2826 } 2827 } 2828 2829 /* 2830 * wm_eeprom_sendbits: 2831 * 2832 * Send a series of bits to the EEPROM. 2833 */ 2834 static void 2835 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2836 { 2837 uint32_t reg; 2838 int x; 2839 2840 reg = CSR_READ(sc, WMREG_EECD); 2841 2842 for (x = nbits; x > 0; x--) { 2843 if (bits & (1U << (x - 1))) 2844 reg |= EECD_DI; 2845 else 2846 reg &= ~EECD_DI; 2847 CSR_WRITE(sc, WMREG_EECD, reg); 2848 delay(2); 2849 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2850 delay(2); 2851 CSR_WRITE(sc, WMREG_EECD, reg); 2852 delay(2); 2853 } 2854 } 2855 2856 /* 2857 * wm_eeprom_recvbits: 2858 * 2859 * Receive a series of bits from the EEPROM. 2860 */ 2861 static void 2862 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2863 { 2864 uint32_t reg, val; 2865 int x; 2866 2867 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2868 2869 val = 0; 2870 for (x = nbits; x > 0; x--) { 2871 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2872 delay(2); 2873 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2874 val |= (1U << (x - 1)); 2875 CSR_WRITE(sc, WMREG_EECD, reg); 2876 delay(2); 2877 } 2878 *valp = val; 2879 } 2880 2881 /* 2882 * wm_read_eeprom_uwire: 2883 * 2884 * Read a word from the EEPROM using the MicroWire protocol. 2885 */ 2886 static int 2887 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2888 { 2889 uint32_t reg, val; 2890 int i; 2891 2892 for (i = 0; i < wordcnt; i++) { 2893 /* Clear SK and DI. */ 2894 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2895 CSR_WRITE(sc, WMREG_EECD, reg); 2896 2897 /* Set CHIP SELECT. */ 2898 reg |= EECD_CS; 2899 CSR_WRITE(sc, WMREG_EECD, reg); 2900 delay(2); 2901 2902 /* Shift in the READ command. */ 2903 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2904 2905 /* Shift in address. */ 2906 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2907 2908 /* Shift out the data. */ 2909 wm_eeprom_recvbits(sc, &val, 16); 2910 data[i] = val & 0xffff; 2911 2912 /* Clear CHIP SELECT. */ 2913 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2914 CSR_WRITE(sc, WMREG_EECD, reg); 2915 delay(2); 2916 } 2917 2918 return (0); 2919 } 2920 2921 /* 2922 * wm_spi_eeprom_ready: 2923 * 2924 * Wait for a SPI EEPROM to be ready for commands. 2925 */ 2926 static int 2927 wm_spi_eeprom_ready(struct wm_softc *sc) 2928 { 2929 uint32_t val; 2930 int usec; 2931 2932 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 2933 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 2934 wm_eeprom_recvbits(sc, &val, 8); 2935 if ((val & SPI_SR_RDY) == 0) 2936 break; 2937 } 2938 if (usec >= SPI_MAX_RETRIES) { 2939 aprint_error("%s: EEPROM failed to become ready\n", 2940 sc->sc_dev.dv_xname); 2941 return (1); 2942 } 2943 return (0); 2944 } 2945 2946 /* 2947 * wm_read_eeprom_spi: 2948 * 2949 * Read a work from the EEPROM using the SPI protocol. 2950 */ 2951 static int 2952 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2953 { 2954 uint32_t reg, val; 2955 int i; 2956 uint8_t opc; 2957 2958 /* Clear SK and CS. */ 2959 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 2960 CSR_WRITE(sc, WMREG_EECD, reg); 2961 delay(2); 2962 2963 if (wm_spi_eeprom_ready(sc)) 2964 return (1); 2965 2966 /* Toggle CS to flush commands. */ 2967 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 2968 delay(2); 2969 CSR_WRITE(sc, WMREG_EECD, reg); 2970 delay(2); 2971 2972 opc = SPI_OPC_READ; 2973 if (sc->sc_ee_addrbits == 8 && word >= 128) 2974 opc |= SPI_OPC_A8; 2975 2976 wm_eeprom_sendbits(sc, opc, 8); 2977 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 2978 2979 for (i = 0; i < wordcnt; i++) { 2980 wm_eeprom_recvbits(sc, &val, 16); 2981 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 2982 } 2983 2984 /* Raise CS and clear SK. */ 2985 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 2986 CSR_WRITE(sc, WMREG_EECD, reg); 2987 delay(2); 2988 2989 return (0); 2990 } 2991 2992 /* 2993 * wm_read_eeprom: 2994 * 2995 * Read data from the serial EEPROM. 2996 */ 2997 static int 2998 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2999 { 3000 int rv; 3001 3002 if (wm_acquire_eeprom(sc)) 3003 return (1); 3004 3005 if (sc->sc_flags & WM_F_EEPROM_SPI) 3006 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3007 else 3008 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3009 3010 wm_release_eeprom(sc); 3011 return (rv); 3012 } 3013 3014 /* 3015 * wm_add_rxbuf: 3016 * 3017 * Add a receive buffer to the indiciated descriptor. 3018 */ 3019 static int 3020 wm_add_rxbuf(struct wm_softc *sc, int idx) 3021 { 3022 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3023 struct mbuf *m; 3024 int error; 3025 3026 MGETHDR(m, M_DONTWAIT, MT_DATA); 3027 if (m == NULL) 3028 return (ENOBUFS); 3029 3030 MCLGET(m, M_DONTWAIT); 3031 if ((m->m_flags & M_EXT) == 0) { 3032 m_freem(m); 3033 return (ENOBUFS); 3034 } 3035 3036 if (rxs->rxs_mbuf != NULL) 3037 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3038 3039 rxs->rxs_mbuf = m; 3040 3041 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3042 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3043 BUS_DMA_READ|BUS_DMA_NOWAIT); 3044 if (error) { 3045 printf("%s: unable to load rx DMA map %d, error = %d\n", 3046 sc->sc_dev.dv_xname, idx, error); 3047 panic("wm_add_rxbuf"); /* XXX XXX XXX */ 3048 } 3049 3050 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3051 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3052 3053 WM_INIT_RXDESC(sc, idx); 3054 3055 return (0); 3056 } 3057 3058 /* 3059 * wm_set_ral: 3060 * 3061 * Set an entery in the receive address list. 3062 */ 3063 static void 3064 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3065 { 3066 uint32_t ral_lo, ral_hi; 3067 3068 if (enaddr != NULL) { 3069 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3070 (enaddr[3] << 24); 3071 ral_hi = enaddr[4] | (enaddr[5] << 8); 3072 ral_hi |= RAL_AV; 3073 } else { 3074 ral_lo = 0; 3075 ral_hi = 0; 3076 } 3077 3078 if (sc->sc_type >= WM_T_82544) { 3079 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3080 ral_lo); 3081 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3082 ral_hi); 3083 } else { 3084 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3085 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3086 } 3087 } 3088 3089 /* 3090 * wm_mchash: 3091 * 3092 * Compute the hash of the multicast address for the 4096-bit 3093 * multicast filter. 3094 */ 3095 static uint32_t 3096 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3097 { 3098 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3099 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3100 uint32_t hash; 3101 3102 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3103 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3104 3105 return (hash & 0xfff); 3106 } 3107 3108 /* 3109 * wm_set_filter: 3110 * 3111 * Set up the receive filter. 3112 */ 3113 static void 3114 wm_set_filter(struct wm_softc *sc) 3115 { 3116 struct ethercom *ec = &sc->sc_ethercom; 3117 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3118 struct ether_multi *enm; 3119 struct ether_multistep step; 3120 bus_addr_t mta_reg; 3121 uint32_t hash, reg, bit; 3122 int i; 3123 3124 if (sc->sc_type >= WM_T_82544) 3125 mta_reg = WMREG_CORDOVA_MTA; 3126 else 3127 mta_reg = WMREG_MTA; 3128 3129 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3130 3131 if (ifp->if_flags & IFF_BROADCAST) 3132 sc->sc_rctl |= RCTL_BAM; 3133 if (ifp->if_flags & IFF_PROMISC) { 3134 sc->sc_rctl |= RCTL_UPE; 3135 goto allmulti; 3136 } 3137 3138 /* 3139 * Set the station address in the first RAL slot, and 3140 * clear the remaining slots. 3141 */ 3142 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3143 for (i = 1; i < WM_RAL_TABSIZE; i++) 3144 wm_set_ral(sc, NULL, i); 3145 3146 /* Clear out the multicast table. */ 3147 for (i = 0; i < WM_MC_TABSIZE; i++) 3148 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3149 3150 ETHER_FIRST_MULTI(step, ec, enm); 3151 while (enm != NULL) { 3152 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3153 /* 3154 * We must listen to a range of multicast addresses. 3155 * For now, just accept all multicasts, rather than 3156 * trying to set only those filter bits needed to match 3157 * the range. (At this time, the only use of address 3158 * ranges is for IP multicast routing, for which the 3159 * range is big enough to require all bits set.) 3160 */ 3161 goto allmulti; 3162 } 3163 3164 hash = wm_mchash(sc, enm->enm_addrlo); 3165 3166 reg = (hash >> 5) & 0x7f; 3167 bit = hash & 0x1f; 3168 3169 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3170 hash |= 1U << bit; 3171 3172 /* XXX Hardware bug?? */ 3173 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3174 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3175 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3176 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3177 } else 3178 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3179 3180 ETHER_NEXT_MULTI(step, enm); 3181 } 3182 3183 ifp->if_flags &= ~IFF_ALLMULTI; 3184 goto setit; 3185 3186 allmulti: 3187 ifp->if_flags |= IFF_ALLMULTI; 3188 sc->sc_rctl |= RCTL_MPE; 3189 3190 setit: 3191 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3192 } 3193 3194 /* 3195 * wm_tbi_mediainit: 3196 * 3197 * Initialize media for use on 1000BASE-X devices. 3198 */ 3199 static void 3200 wm_tbi_mediainit(struct wm_softc *sc) 3201 { 3202 const char *sep = ""; 3203 3204 if (sc->sc_type < WM_T_82543) 3205 sc->sc_tipg = TIPG_WM_DFLT; 3206 else 3207 sc->sc_tipg = TIPG_LG_DFLT; 3208 3209 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3210 wm_tbi_mediastatus); 3211 3212 /* 3213 * SWD Pins: 3214 * 3215 * 0 = Link LED (output) 3216 * 1 = Loss Of Signal (input) 3217 */ 3218 sc->sc_ctrl |= CTRL_SWDPIO(0); 3219 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3220 3221 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3222 3223 #define ADD(ss, mm, dd) \ 3224 do { \ 3225 printf("%s%s", sep, ss); \ 3226 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3227 sep = ", "; \ 3228 } while (/*CONSTCOND*/0) 3229 3230 printf("%s: ", sc->sc_dev.dv_xname); 3231 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3232 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3233 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3234 printf("\n"); 3235 3236 #undef ADD 3237 3238 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3239 } 3240 3241 /* 3242 * wm_tbi_mediastatus: [ifmedia interface function] 3243 * 3244 * Get the current interface media status on a 1000BASE-X device. 3245 */ 3246 static void 3247 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3248 { 3249 struct wm_softc *sc = ifp->if_softc; 3250 uint32_t ctrl; 3251 3252 ifmr->ifm_status = IFM_AVALID; 3253 ifmr->ifm_active = IFM_ETHER; 3254 3255 if (sc->sc_tbi_linkup == 0) { 3256 ifmr->ifm_active |= IFM_NONE; 3257 return; 3258 } 3259 3260 ifmr->ifm_status |= IFM_ACTIVE; 3261 ifmr->ifm_active |= IFM_1000_SX; 3262 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3263 ifmr->ifm_active |= IFM_FDX; 3264 ctrl = CSR_READ(sc, WMREG_CTRL); 3265 if (ctrl & CTRL_RFCE) 3266 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3267 if (ctrl & CTRL_TFCE) 3268 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3269 } 3270 3271 /* 3272 * wm_tbi_mediachange: [ifmedia interface function] 3273 * 3274 * Set hardware to newly-selected media on a 1000BASE-X device. 3275 */ 3276 static int 3277 wm_tbi_mediachange(struct ifnet *ifp) 3278 { 3279 struct wm_softc *sc = ifp->if_softc; 3280 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3281 uint32_t status; 3282 int i; 3283 3284 sc->sc_txcw = ife->ifm_data; 3285 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3286 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3287 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3288 sc->sc_txcw |= TXCW_ANE; 3289 3290 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3291 delay(10000); 3292 3293 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3294 3295 sc->sc_tbi_anstate = 0; 3296 3297 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3298 /* Have signal; wait for the link to come up. */ 3299 for (i = 0; i < 50; i++) { 3300 delay(10000); 3301 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3302 break; 3303 } 3304 3305 status = CSR_READ(sc, WMREG_STATUS); 3306 if (status & STATUS_LU) { 3307 /* Link is up. */ 3308 DPRINTF(WM_DEBUG_LINK, 3309 ("%s: LINK: set media -> link up %s\n", 3310 sc->sc_dev.dv_xname, 3311 (status & STATUS_FD) ? "FDX" : "HDX")); 3312 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3313 sc->sc_fcrtl &= ~FCRTL_XONE; 3314 if (status & STATUS_FD) 3315 sc->sc_tctl |= 3316 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3317 else 3318 sc->sc_tctl |= 3319 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3320 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3321 sc->sc_fcrtl |= FCRTL_XONE; 3322 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3323 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3324 WMREG_OLD_FCRTL : WMREG_FCRTL, 3325 sc->sc_fcrtl); 3326 sc->sc_tbi_linkup = 1; 3327 } else { 3328 /* Link is down. */ 3329 DPRINTF(WM_DEBUG_LINK, 3330 ("%s: LINK: set media -> link down\n", 3331 sc->sc_dev.dv_xname)); 3332 sc->sc_tbi_linkup = 0; 3333 } 3334 } else { 3335 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3336 sc->sc_dev.dv_xname)); 3337 sc->sc_tbi_linkup = 0; 3338 } 3339 3340 wm_tbi_set_linkled(sc); 3341 3342 return (0); 3343 } 3344 3345 /* 3346 * wm_tbi_set_linkled: 3347 * 3348 * Update the link LED on 1000BASE-X devices. 3349 */ 3350 static void 3351 wm_tbi_set_linkled(struct wm_softc *sc) 3352 { 3353 3354 if (sc->sc_tbi_linkup) 3355 sc->sc_ctrl |= CTRL_SWDPIN(0); 3356 else 3357 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3358 3359 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3360 } 3361 3362 /* 3363 * wm_tbi_check_link: 3364 * 3365 * Check the link on 1000BASE-X devices. 3366 */ 3367 static void 3368 wm_tbi_check_link(struct wm_softc *sc) 3369 { 3370 uint32_t rxcw, ctrl, status; 3371 3372 if (sc->sc_tbi_anstate == 0) 3373 return; 3374 else if (sc->sc_tbi_anstate > 1) { 3375 DPRINTF(WM_DEBUG_LINK, 3376 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3377 sc->sc_tbi_anstate)); 3378 sc->sc_tbi_anstate--; 3379 return; 3380 } 3381 3382 sc->sc_tbi_anstate = 0; 3383 3384 rxcw = CSR_READ(sc, WMREG_RXCW); 3385 ctrl = CSR_READ(sc, WMREG_CTRL); 3386 status = CSR_READ(sc, WMREG_STATUS); 3387 3388 if ((status & STATUS_LU) == 0) { 3389 DPRINTF(WM_DEBUG_LINK, 3390 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3391 sc->sc_tbi_linkup = 0; 3392 } else { 3393 DPRINTF(WM_DEBUG_LINK, 3394 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3395 (status & STATUS_FD) ? "FDX" : "HDX")); 3396 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3397 sc->sc_fcrtl &= ~FCRTL_XONE; 3398 if (status & STATUS_FD) 3399 sc->sc_tctl |= 3400 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3401 else 3402 sc->sc_tctl |= 3403 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3404 if (ctrl & CTRL_TFCE) 3405 sc->sc_fcrtl |= FCRTL_XONE; 3406 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3407 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3408 WMREG_OLD_FCRTL : WMREG_FCRTL, 3409 sc->sc_fcrtl); 3410 sc->sc_tbi_linkup = 1; 3411 } 3412 3413 wm_tbi_set_linkled(sc); 3414 } 3415 3416 /* 3417 * wm_gmii_reset: 3418 * 3419 * Reset the PHY. 3420 */ 3421 static void 3422 wm_gmii_reset(struct wm_softc *sc) 3423 { 3424 uint32_t reg; 3425 3426 if (sc->sc_type >= WM_T_82544) { 3427 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3428 delay(20000); 3429 3430 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3431 delay(20000); 3432 } else { 3433 /* The PHY reset pin is active-low. */ 3434 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3435 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3436 CTRL_EXT_SWDPIN(4)); 3437 reg |= CTRL_EXT_SWDPIO(4); 3438 3439 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3440 delay(10); 3441 3442 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3443 delay(10); 3444 3445 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3446 delay(10); 3447 #if 0 3448 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3449 #endif 3450 } 3451 } 3452 3453 /* 3454 * wm_gmii_mediainit: 3455 * 3456 * Initialize media for use on 1000BASE-T devices. 3457 */ 3458 static void 3459 wm_gmii_mediainit(struct wm_softc *sc) 3460 { 3461 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3462 3463 /* We have MII. */ 3464 sc->sc_flags |= WM_F_HAS_MII; 3465 3466 sc->sc_tipg = TIPG_1000T_DFLT; 3467 3468 /* 3469 * Let the chip set speed/duplex on its own based on 3470 * signals from the PHY. 3471 */ 3472 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3473 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3474 3475 /* Initialize our media structures and probe the GMII. */ 3476 sc->sc_mii.mii_ifp = ifp; 3477 3478 if (sc->sc_type >= WM_T_82544) { 3479 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3480 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3481 } else { 3482 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3483 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3484 } 3485 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3486 3487 wm_gmii_reset(sc); 3488 3489 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3490 wm_gmii_mediastatus); 3491 3492 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3493 MII_OFFSET_ANY, MIIF_DOPAUSE); 3494 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3495 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3496 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3497 } else 3498 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3499 } 3500 3501 /* 3502 * wm_gmii_mediastatus: [ifmedia interface function] 3503 * 3504 * Get the current interface media status on a 1000BASE-T device. 3505 */ 3506 static void 3507 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3508 { 3509 struct wm_softc *sc = ifp->if_softc; 3510 3511 mii_pollstat(&sc->sc_mii); 3512 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3513 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3514 sc->sc_flowflags; 3515 } 3516 3517 /* 3518 * wm_gmii_mediachange: [ifmedia interface function] 3519 * 3520 * Set hardware to newly-selected media on a 1000BASE-T device. 3521 */ 3522 static int 3523 wm_gmii_mediachange(struct ifnet *ifp) 3524 { 3525 struct wm_softc *sc = ifp->if_softc; 3526 3527 if (ifp->if_flags & IFF_UP) 3528 mii_mediachg(&sc->sc_mii); 3529 return (0); 3530 } 3531 3532 #define MDI_IO CTRL_SWDPIN(2) 3533 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3534 #define MDI_CLK CTRL_SWDPIN(3) 3535 3536 static void 3537 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3538 { 3539 uint32_t i, v; 3540 3541 v = CSR_READ(sc, WMREG_CTRL); 3542 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3543 v |= MDI_DIR | CTRL_SWDPIO(3); 3544 3545 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3546 if (data & i) 3547 v |= MDI_IO; 3548 else 3549 v &= ~MDI_IO; 3550 CSR_WRITE(sc, WMREG_CTRL, v); 3551 delay(10); 3552 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3553 delay(10); 3554 CSR_WRITE(sc, WMREG_CTRL, v); 3555 delay(10); 3556 } 3557 } 3558 3559 static uint32_t 3560 i82543_mii_recvbits(struct wm_softc *sc) 3561 { 3562 uint32_t v, i, data = 0; 3563 3564 v = CSR_READ(sc, WMREG_CTRL); 3565 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3566 v |= CTRL_SWDPIO(3); 3567 3568 CSR_WRITE(sc, WMREG_CTRL, v); 3569 delay(10); 3570 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3571 delay(10); 3572 CSR_WRITE(sc, WMREG_CTRL, v); 3573 delay(10); 3574 3575 for (i = 0; i < 16; i++) { 3576 data <<= 1; 3577 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3578 delay(10); 3579 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3580 data |= 1; 3581 CSR_WRITE(sc, WMREG_CTRL, v); 3582 delay(10); 3583 } 3584 3585 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3586 delay(10); 3587 CSR_WRITE(sc, WMREG_CTRL, v); 3588 delay(10); 3589 3590 return (data); 3591 } 3592 3593 #undef MDI_IO 3594 #undef MDI_DIR 3595 #undef MDI_CLK 3596 3597 /* 3598 * wm_gmii_i82543_readreg: [mii interface function] 3599 * 3600 * Read a PHY register on the GMII (i82543 version). 3601 */ 3602 static int 3603 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3604 { 3605 struct wm_softc *sc = (void *) self; 3606 int rv; 3607 3608 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3609 i82543_mii_sendbits(sc, reg | (phy << 5) | 3610 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3611 rv = i82543_mii_recvbits(sc) & 0xffff; 3612 3613 DPRINTF(WM_DEBUG_GMII, 3614 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3615 sc->sc_dev.dv_xname, phy, reg, rv)); 3616 3617 return (rv); 3618 } 3619 3620 /* 3621 * wm_gmii_i82543_writereg: [mii interface function] 3622 * 3623 * Write a PHY register on the GMII (i82543 version). 3624 */ 3625 static void 3626 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3627 { 3628 struct wm_softc *sc = (void *) self; 3629 3630 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3631 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3632 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3633 (MII_COMMAND_START << 30), 32); 3634 } 3635 3636 /* 3637 * wm_gmii_i82544_readreg: [mii interface function] 3638 * 3639 * Read a PHY register on the GMII. 3640 */ 3641 static int 3642 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3643 { 3644 struct wm_softc *sc = (void *) self; 3645 uint32_t mdic = 0; 3646 int i, rv; 3647 3648 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3649 MDIC_REGADD(reg)); 3650 3651 for (i = 0; i < 100; i++) { 3652 mdic = CSR_READ(sc, WMREG_MDIC); 3653 if (mdic & MDIC_READY) 3654 break; 3655 delay(10); 3656 } 3657 3658 if ((mdic & MDIC_READY) == 0) { 3659 printf("%s: MDIC read timed out: phy %d reg %d\n", 3660 sc->sc_dev.dv_xname, phy, reg); 3661 rv = 0; 3662 } else if (mdic & MDIC_E) { 3663 #if 0 /* This is normal if no PHY is present. */ 3664 printf("%s: MDIC read error: phy %d reg %d\n", 3665 sc->sc_dev.dv_xname, phy, reg); 3666 #endif 3667 rv = 0; 3668 } else { 3669 rv = MDIC_DATA(mdic); 3670 if (rv == 0xffff) 3671 rv = 0; 3672 } 3673 3674 return (rv); 3675 } 3676 3677 /* 3678 * wm_gmii_i82544_writereg: [mii interface function] 3679 * 3680 * Write a PHY register on the GMII. 3681 */ 3682 static void 3683 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3684 { 3685 struct wm_softc *sc = (void *) self; 3686 uint32_t mdic = 0; 3687 int i; 3688 3689 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3690 MDIC_REGADD(reg) | MDIC_DATA(val)); 3691 3692 for (i = 0; i < 100; i++) { 3693 mdic = CSR_READ(sc, WMREG_MDIC); 3694 if (mdic & MDIC_READY) 3695 break; 3696 delay(10); 3697 } 3698 3699 if ((mdic & MDIC_READY) == 0) 3700 printf("%s: MDIC write timed out: phy %d reg %d\n", 3701 sc->sc_dev.dv_xname, phy, reg); 3702 else if (mdic & MDIC_E) 3703 printf("%s: MDIC write error: phy %d reg %d\n", 3704 sc->sc_dev.dv_xname, phy, reg); 3705 } 3706 3707 /* 3708 * wm_gmii_statchg: [mii interface function] 3709 * 3710 * Callback from MII layer when media changes. 3711 */ 3712 static void 3713 wm_gmii_statchg(struct device *self) 3714 { 3715 struct wm_softc *sc = (void *) self; 3716 struct mii_data *mii = &sc->sc_mii; 3717 3718 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3719 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3720 sc->sc_fcrtl &= ~FCRTL_XONE; 3721 3722 /* 3723 * Get flow control negotiation result. 3724 */ 3725 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3726 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3727 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3728 mii->mii_media_active &= ~IFM_ETH_FMASK; 3729 } 3730 3731 if (sc->sc_flowflags & IFM_FLOW) { 3732 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3733 sc->sc_ctrl |= CTRL_TFCE; 3734 sc->sc_fcrtl |= FCRTL_XONE; 3735 } 3736 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3737 sc->sc_ctrl |= CTRL_RFCE; 3738 } 3739 3740 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3741 DPRINTF(WM_DEBUG_LINK, 3742 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3743 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3744 } else { 3745 DPRINTF(WM_DEBUG_LINK, 3746 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3747 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3748 } 3749 3750 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3751 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3752 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3753 : WMREG_FCRTL, sc->sc_fcrtl); 3754 } 3755
Indexes created Tue Sep 23 07:09:52 GMT 2025