if_wm.c revision 1.80
1 /* $NetBSD: if_wm.c,v 1.80 2004/10/06 00:04:01 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the Intel i8254x family of Gigabit Ethernet chips. 40 * 41 * TODO (in order of importance): 42 * 43 * - Rework how parameters are loaded from the EEPROM. 44 * - Figure out what to do with the i82545GM and i82546GB 45 * SERDES controllers. 46 * - Fix hw VLAN assist. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.80 2004/10/06 00:04:01 thorpej Exp $"); 51 52 #include "bpfilter.h" 53 #include "rnd.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/callout.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/device.h> 65 #include <sys/queue.h> 66 67 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 68 69 #if NRND > 0 70 #include <sys/rnd.h> 71 #endif 72 73 #include <net/if.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_ether.h> 77 78 #if NBPFILTER > 0 79 #include <net/bpf.h> 80 #endif 81 82 #include <netinet/in.h> /* XXX for struct ip */ 83 #include <netinet/in_systm.h> /* XXX for struct ip */ 84 #include <netinet/ip.h> /* XXX for struct ip */ 85 #include <netinet/tcp.h> /* XXX for struct tcphdr */ 86 87 #include <machine/bus.h> 88 #include <machine/intr.h> 89 #include <machine/endian.h> 90 91 #include <dev/mii/mii.h> 92 #include <dev/mii/miivar.h> 93 #include <dev/mii/mii_bitbang.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include <dev/pci/if_wmreg.h> 100 101 #ifdef WM_DEBUG 102 #define WM_DEBUG_LINK 0x01 103 #define WM_DEBUG_TX 0x02 104 #define WM_DEBUG_RX 0x04 105 #define WM_DEBUG_GMII 0x08 106 int wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; 107 108 #define DPRINTF(x, y) if (wm_debug & (x)) printf y 109 #else 110 #define DPRINTF(x, y) /* nothing */ 111 #endif /* WM_DEBUG */ 112 113 /* 114 * Transmit descriptor list size. Due to errata, we can only have 115 * 256 hardware descriptors in the ring on < 82544, but we use 4096 116 * on >= 82544. We tell the upper layers that they can queue a lot 117 * of packets, and we go ahead and manage up to 64 (16 for the i82547) 118 * of them at a time. 119 * 120 * We allow up to 256 (!) DMA segments per packet. Pathological packet 121 * chains containing many small mbufs have been observed in zero-copy 122 * situations with jumbo frames. 123 */ 124 #define WM_NTXSEGS 256 125 #define WM_IFQUEUELEN 256 126 #define WM_TXQUEUELEN_MAX 64 127 #define WM_TXQUEUELEN_MAX_82547 16 128 #define WM_TXQUEUELEN(sc) ((sc)->sc_txnum) 129 #define WM_TXQUEUELEN_MASK(sc) (WM_TXQUEUELEN(sc) - 1) 130 #define WM_TXQUEUE_GC(sc) (WM_TXQUEUELEN(sc) / 8) 131 #define WM_NTXDESC_82542 256 132 #define WM_NTXDESC_82544 4096 133 #define WM_NTXDESC(sc) ((sc)->sc_ntxdesc) 134 #define WM_NTXDESC_MASK(sc) (WM_NTXDESC(sc) - 1) 135 #define WM_TXDESCSIZE(sc) (WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t)) 136 #define WM_NEXTTX(sc, x) (((x) + 1) & WM_NTXDESC_MASK(sc)) 137 #define WM_NEXTTXS(sc, x) (((x) + 1) & WM_TXQUEUELEN_MASK(sc)) 138 139 /* 140 * Receive descriptor list size. We have one Rx buffer for normal 141 * sized packets. Jumbo packets consume 5 Rx buffers for a full-sized 142 * packet. We allocate 256 receive descriptors, each with a 2k 143 * buffer (MCLBYTES), which gives us room for 50 jumbo packets. 144 */ 145 #define WM_NRXDESC 256 146 #define WM_NRXDESC_MASK (WM_NRXDESC - 1) 147 #define WM_NEXTRX(x) (((x) + 1) & WM_NRXDESC_MASK) 148 #define WM_PREVRX(x) (((x) - 1) & WM_NRXDESC_MASK) 149 150 /* 151 * Control structures are DMA'd to the i82542 chip. We allocate them in 152 * a single clump that maps to a single DMA segment to make serveral things 153 * easier. 154 */ 155 struct wm_control_data_82544 { 156 /* 157 * The receive descriptors. 158 */ 159 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 160 161 /* 162 * The transmit descriptors. Put these at the end, because 163 * we might use a smaller number of them. 164 */ 165 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82544]; 166 }; 167 168 struct wm_control_data_82542 { 169 wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC]; 170 wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542]; 171 }; 172 173 #define WM_CDOFF(x) offsetof(struct wm_control_data_82544, x) 174 #define WM_CDTXOFF(x) WM_CDOFF(wcd_txdescs[(x)]) 175 #define WM_CDRXOFF(x) WM_CDOFF(wcd_rxdescs[(x)]) 176 177 /* 178 * Software state for transmit jobs. 179 */ 180 struct wm_txsoft { 181 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 182 bus_dmamap_t txs_dmamap; /* our DMA map */ 183 int txs_firstdesc; /* first descriptor in packet */ 184 int txs_lastdesc; /* last descriptor in packet */ 185 int txs_ndesc; /* # of descriptors used */ 186 }; 187 188 /* 189 * Software state for receive buffers. Each descriptor gets a 190 * 2k (MCLBYTES) buffer and a DMA map. For packets which fill 191 * more than one buffer, we chain them together. 192 */ 193 struct wm_rxsoft { 194 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 195 bus_dmamap_t rxs_dmamap; /* our DMA map */ 196 }; 197 198 typedef enum { 199 WM_T_unknown = 0, 200 WM_T_82542_2_0, /* i82542 2.0 (really old) */ 201 WM_T_82542_2_1, /* i82542 2.1+ (old) */ 202 WM_T_82543, /* i82543 */ 203 WM_T_82544, /* i82544 */ 204 WM_T_82540, /* i82540 */ 205 WM_T_82545, /* i82545 */ 206 WM_T_82545_3, /* i82545 3.0+ */ 207 WM_T_82546, /* i82546 */ 208 WM_T_82546_3, /* i82546 3.0+ */ 209 WM_T_82541, /* i82541 */ 210 WM_T_82541_2, /* i82541 2.0+ */ 211 WM_T_82547, /* i82547 */ 212 WM_T_82547_2, /* i82547 2.0+ */ 213 } wm_chip_type; 214 215 /* 216 * Software state per device. 217 */ 218 struct wm_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_space_tag_t sc_iot; /* I/O space tag */ 223 bus_space_handle_t sc_ioh; /* I/O space handle */ 224 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 225 struct ethercom sc_ethercom; /* ethernet common data */ 226 void *sc_sdhook; /* shutdown hook */ 227 228 wm_chip_type sc_type; /* chip type */ 229 int sc_flags; /* flags; see below */ 230 int sc_bus_speed; /* PCI/PCIX bus speed */ 231 int sc_pcix_offset; /* PCIX capability register offset */ 232 int sc_flowflags; /* 802.3x flow control flags */ 233 234 void *sc_ih; /* interrupt cookie */ 235 236 int sc_ee_addrbits; /* EEPROM address bits */ 237 238 struct mii_data sc_mii; /* MII/media information */ 239 240 struct callout sc_tick_ch; /* tick callout */ 241 242 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 243 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 244 245 int sc_align_tweak; 246 247 /* 248 * Software state for the transmit and receive descriptors. 249 */ 250 int sc_txnum; /* must be a power of two */ 251 struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX]; 252 struct wm_rxsoft sc_rxsoft[WM_NRXDESC]; 253 254 /* 255 * Control data structures. 256 */ 257 int sc_ntxdesc; /* must be a power of two */ 258 struct wm_control_data_82544 *sc_control_data; 259 #define sc_txdescs sc_control_data->wcd_txdescs 260 #define sc_rxdescs sc_control_data->wcd_rxdescs 261 262 #ifdef WM_EVENT_COUNTERS 263 /* Event counters. */ 264 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 265 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 266 struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */ 267 struct evcnt sc_ev_txdw; /* Tx descriptor interrupts */ 268 struct evcnt sc_ev_txqe; /* Tx queue empty interrupts */ 269 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 270 struct evcnt sc_ev_linkintr; /* Link interrupts */ 271 272 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 273 struct evcnt sc_ev_rxtusum; /* TCP/UDP cksums checked in-bound */ 274 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 275 struct evcnt sc_ev_txtusum; /* TCP/UDP cksums comp. out-bound */ 276 277 struct evcnt sc_ev_txctx_init; /* Tx cksum context cache initialized */ 278 struct evcnt sc_ev_txctx_hit; /* Tx cksum context cache hit */ 279 struct evcnt sc_ev_txctx_miss; /* Tx cksum context cache miss */ 280 281 struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */ 282 struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */ 283 284 struct evcnt sc_ev_tu; /* Tx underrun */ 285 286 struct evcnt sc_ev_tx_xoff; /* Tx PAUSE(!0) frames */ 287 struct evcnt sc_ev_tx_xon; /* Tx PAUSE(0) frames */ 288 struct evcnt sc_ev_rx_xoff; /* Rx PAUSE(!0) frames */ 289 struct evcnt sc_ev_rx_xon; /* Rx PAUSE(0) frames */ 290 struct evcnt sc_ev_rx_macctl; /* Rx Unsupported */ 291 #endif /* WM_EVENT_COUNTERS */ 292 293 bus_addr_t sc_tdt_reg; /* offset of TDT register */ 294 295 int sc_txfree; /* number of free Tx descriptors */ 296 int sc_txnext; /* next ready Tx descriptor */ 297 298 int sc_txsfree; /* number of free Tx jobs */ 299 int sc_txsnext; /* next free Tx job */ 300 int sc_txsdirty; /* dirty Tx jobs */ 301 302 /* These 5 variables are used only on the 82547. */ 303 int sc_txfifo_size; /* Tx FIFO size */ 304 int sc_txfifo_head; /* current head of FIFO */ 305 uint32_t sc_txfifo_addr; /* internal address of start of FIFO */ 306 int sc_txfifo_stall; /* Tx FIFO is stalled */ 307 struct callout sc_txfifo_ch; /* Tx FIFO stall work-around timer */ 308 309 uint32_t sc_txctx_ipcs; /* cached Tx IP cksum ctx */ 310 uint32_t sc_txctx_tucs; /* cached Tx TCP/UDP cksum ctx */ 311 312 bus_addr_t sc_rdt_reg; /* offset of RDT register */ 313 314 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 315 int sc_rxdiscard; 316 int sc_rxlen; 317 struct mbuf *sc_rxhead; 318 struct mbuf *sc_rxtail; 319 struct mbuf **sc_rxtailp; 320 321 uint32_t sc_ctrl; /* prototype CTRL register */ 322 #if 0 323 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 324 #endif 325 uint32_t sc_icr; /* prototype interrupt bits */ 326 uint32_t sc_tctl; /* prototype TCTL register */ 327 uint32_t sc_rctl; /* prototype RCTL register */ 328 uint32_t sc_txcw; /* prototype TXCW register */ 329 uint32_t sc_tipg; /* prototype TIPG register */ 330 uint32_t sc_fcrtl; /* prototype FCRTL register */ 331 uint32_t sc_pba; /* prototype PBA register */ 332 333 int sc_tbi_linkup; /* TBI link status */ 334 int sc_tbi_anstate; /* autonegotiation state */ 335 336 int sc_mchash_type; /* multicast filter offset */ 337 338 #if NRND > 0 339 rndsource_element_t rnd_source; /* random source */ 340 #endif 341 }; 342 343 #define WM_RXCHAIN_RESET(sc) \ 344 do { \ 345 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 346 *(sc)->sc_rxtailp = NULL; \ 347 (sc)->sc_rxlen = 0; \ 348 } while (/*CONSTCOND*/0) 349 350 #define WM_RXCHAIN_LINK(sc, m) \ 351 do { \ 352 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 353 (sc)->sc_rxtailp = &(m)->m_next; \ 354 } while (/*CONSTCOND*/0) 355 356 /* sc_flags */ 357 #define WM_F_HAS_MII 0x01 /* has MII */ 358 #define WM_F_EEPROM_HANDSHAKE 0x02 /* requires EEPROM handshake */ 359 #define WM_F_EEPROM_SPI 0x04 /* EEPROM is SPI */ 360 #define WM_F_IOH_VALID 0x10 /* I/O handle is valid */ 361 #define WM_F_BUS64 0x20 /* bus is 64-bit */ 362 #define WM_F_PCIX 0x40 /* bus is PCI-X */ 363 #define WM_F_CSA 0x80 /* bus is CSA */ 364 365 #ifdef WM_EVENT_COUNTERS 366 #define WM_EVCNT_INCR(ev) (ev)->ev_count++ 367 #define WM_EVCNT_ADD(ev, val) (ev)->ev_count += (val) 368 #else 369 #define WM_EVCNT_INCR(ev) /* nothing */ 370 #define WM_EVCNT_ADD(ev, val) /* nothing */ 371 #endif 372 373 #define CSR_READ(sc, reg) \ 374 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 375 #define CSR_WRITE(sc, reg, val) \ 376 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 377 #define CSR_WRITE_FLUSH(sc) \ 378 (void) CSR_READ((sc), WMREG_STATUS) 379 380 #define WM_CDTXADDR(sc, x) ((sc)->sc_cddma + WM_CDTXOFF((x))) 381 #define WM_CDRXADDR(sc, x) ((sc)->sc_cddma + WM_CDRXOFF((x))) 382 383 #define WM_CDTXADDR_LO(sc, x) (WM_CDTXADDR((sc), (x)) & 0xffffffffU) 384 #define WM_CDTXADDR_HI(sc, x) \ 385 (sizeof(bus_addr_t) == 8 ? \ 386 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0) 387 388 #define WM_CDRXADDR_LO(sc, x) (WM_CDRXADDR((sc), (x)) & 0xffffffffU) 389 #define WM_CDRXADDR_HI(sc, x) \ 390 (sizeof(bus_addr_t) == 8 ? \ 391 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0) 392 393 #define WM_CDTXSYNC(sc, x, n, ops) \ 394 do { \ 395 int __x, __n; \ 396 \ 397 __x = (x); \ 398 __n = (n); \ 399 \ 400 /* If it will wrap around, sync to the end of the ring. */ \ 401 if ((__x + __n) > WM_NTXDESC(sc)) { \ 402 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 403 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * \ 404 (WM_NTXDESC(sc) - __x), (ops)); \ 405 __n -= (WM_NTXDESC(sc) - __x); \ 406 __x = 0; \ 407 } \ 408 \ 409 /* Now sync whatever is left. */ \ 410 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 411 WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops)); \ 412 } while (/*CONSTCOND*/0) 413 414 #define WM_CDRXSYNC(sc, x, ops) \ 415 do { \ 416 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 417 WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops)); \ 418 } while (/*CONSTCOND*/0) 419 420 #define WM_INIT_RXDESC(sc, x) \ 421 do { \ 422 struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 423 wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)]; \ 424 struct mbuf *__m = __rxs->rxs_mbuf; \ 425 \ 426 /* \ 427 * Note: We scoot the packet forward 2 bytes in the buffer \ 428 * so that the payload after the Ethernet header is aligned \ 429 * to a 4-byte boundary. \ 430 * \ 431 * XXX BRAINDAMAGE ALERT! \ 432 * The stupid chip uses the same size for every buffer, which \ 433 * is set in the Receive Control register. We are using the 2K \ 434 * size option, but what we REALLY want is (2K - 2)! For this \ 435 * reason, we can't "scoot" packets longer than the standard \ 436 * Ethernet MTU. On strict-alignment platforms, if the total \ 437 * size exceeds (2K - 2) we set align_tweak to 0 and let \ 438 * the upper layer copy the headers. \ 439 */ \ 440 __m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak; \ 441 \ 442 wm_set_dma_addr(&__rxd->wrx_addr, \ 443 __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \ 444 __rxd->wrx_len = 0; \ 445 __rxd->wrx_cksum = 0; \ 446 __rxd->wrx_status = 0; \ 447 __rxd->wrx_errors = 0; \ 448 __rxd->wrx_special = 0; \ 449 WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 450 \ 451 CSR_WRITE((sc), (sc)->sc_rdt_reg, (x)); \ 452 } while (/*CONSTCOND*/0) 453 454 static void wm_start(struct ifnet *); 455 static void wm_watchdog(struct ifnet *); 456 static int wm_ioctl(struct ifnet *, u_long, caddr_t); 457 static int wm_init(struct ifnet *); 458 static void wm_stop(struct ifnet *, int); 459 460 static void wm_shutdown(void *); 461 462 static void wm_reset(struct wm_softc *); 463 static void wm_rxdrain(struct wm_softc *); 464 static int wm_add_rxbuf(struct wm_softc *, int); 465 static int wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *); 466 static void wm_tick(void *); 467 468 static void wm_set_filter(struct wm_softc *); 469 470 static int wm_intr(void *); 471 static void wm_txintr(struct wm_softc *); 472 static void wm_rxintr(struct wm_softc *); 473 static void wm_linkintr(struct wm_softc *, uint32_t); 474 475 static void wm_tbi_mediainit(struct wm_softc *); 476 static int wm_tbi_mediachange(struct ifnet *); 477 static void wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *); 478 479 static void wm_tbi_set_linkled(struct wm_softc *); 480 static void wm_tbi_check_link(struct wm_softc *); 481 482 static void wm_gmii_reset(struct wm_softc *); 483 484 static int wm_gmii_i82543_readreg(struct device *, int, int); 485 static void wm_gmii_i82543_writereg(struct device *, int, int, int); 486 487 static int wm_gmii_i82544_readreg(struct device *, int, int); 488 static void wm_gmii_i82544_writereg(struct device *, int, int, int); 489 490 static void wm_gmii_statchg(struct device *); 491 492 static void wm_gmii_mediainit(struct wm_softc *); 493 static int wm_gmii_mediachange(struct ifnet *); 494 static void wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *); 495 496 static int wm_match(struct device *, struct cfdata *, void *); 497 static void wm_attach(struct device *, struct device *, void *); 498 499 CFATTACH_DECL(wm, sizeof(struct wm_softc), 500 wm_match, wm_attach, NULL, NULL); 501 502 static void wm_82547_txfifo_stall(void *); 503 504 /* 505 * Devices supported by this driver. 506 */ 507 static const struct wm_product { 508 pci_vendor_id_t wmp_vendor; 509 pci_product_id_t wmp_product; 510 const char *wmp_name; 511 wm_chip_type wmp_type; 512 int wmp_flags; 513 #define WMP_F_1000X 0x01 514 #define WMP_F_1000T 0x02 515 } wm_products[] = { 516 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542, 517 "Intel i82542 1000BASE-X Ethernet", 518 WM_T_82542_2_1, WMP_F_1000X }, 519 520 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER, 521 "Intel i82543GC 1000BASE-X Ethernet", 522 WM_T_82543, WMP_F_1000X }, 523 524 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER, 525 "Intel i82543GC 1000BASE-T Ethernet", 526 WM_T_82543, WMP_F_1000T }, 527 528 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER, 529 "Intel i82544EI 1000BASE-T Ethernet", 530 WM_T_82544, WMP_F_1000T }, 531 532 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER, 533 "Intel i82544EI 1000BASE-X Ethernet", 534 WM_T_82544, WMP_F_1000X }, 535 536 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER, 537 "Intel i82544GC 1000BASE-T Ethernet", 538 WM_T_82544, WMP_F_1000T }, 539 540 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM, 541 "Intel i82544GC (LOM) 1000BASE-T Ethernet", 542 WM_T_82544, WMP_F_1000T }, 543 544 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM, 545 "Intel i82540EM 1000BASE-T Ethernet", 546 WM_T_82540, WMP_F_1000T }, 547 548 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM, 549 "Intel i82540EM (LOM) 1000BASE-T Ethernet", 550 WM_T_82540, WMP_F_1000T }, 551 552 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM, 553 "Intel i82540EP 1000BASE-T Ethernet", 554 WM_T_82540, WMP_F_1000T }, 555 556 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP, 557 "Intel i82540EP 1000BASE-T Ethernet", 558 WM_T_82540, WMP_F_1000T }, 559 560 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP, 561 "Intel i82540EP 1000BASE-T Ethernet", 562 WM_T_82540, WMP_F_1000T }, 563 564 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER, 565 "Intel i82545EM 1000BASE-T Ethernet", 566 WM_T_82545, WMP_F_1000T }, 567 568 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER, 569 "Intel i82545GM 1000BASE-T Ethernet", 570 WM_T_82545_3, WMP_F_1000T }, 571 572 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER, 573 "Intel i82545GM 1000BASE-X Ethernet", 574 WM_T_82545_3, WMP_F_1000X }, 575 #if 0 576 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES, 577 "Intel i82545GM Gigabit Ethernet (SERDES)", 578 WM_T_82545_3, WMP_F_SERDES }, 579 #endif 580 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER, 581 "Intel i82546EB 1000BASE-T Ethernet", 582 WM_T_82546, WMP_F_1000T }, 583 584 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD, 585 "Intel i82546EB 1000BASE-T Ethernet", 586 WM_T_82546, WMP_F_1000T }, 587 588 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER, 589 "Intel i82545EM 1000BASE-X Ethernet", 590 WM_T_82545, WMP_F_1000X }, 591 592 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER, 593 "Intel i82546EB 1000BASE-X Ethernet", 594 WM_T_82546, WMP_F_1000X }, 595 596 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER, 597 "Intel i82546GB 1000BASE-T Ethernet", 598 WM_T_82546_3, WMP_F_1000T }, 599 600 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER, 601 "Intel i82546GB 1000BASE-X Ethernet", 602 WM_T_82546_3, WMP_F_1000X }, 603 #if 0 604 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES, 605 "Intel i82546GB Gigabit Ethernet (SERDES)", 606 WM_T_82546_3, WMP_F_SERDES }, 607 #endif 608 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI, 609 "Intel i82541EI 1000BASE-T Ethernet", 610 WM_T_82541, WMP_F_1000T }, 611 612 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE, 613 "Intel i82541EI Mobile 1000BASE-T Ethernet", 614 WM_T_82541, WMP_F_1000T }, 615 616 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER, 617 "Intel i82541ER 1000BASE-T Ethernet", 618 WM_T_82541_2, WMP_F_1000T }, 619 620 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI, 621 "Intel i82541GI 1000BASE-T Ethernet", 622 WM_T_82541_2, WMP_F_1000T }, 623 624 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE, 625 "Intel i82541GI Mobile 1000BASE-T Ethernet", 626 WM_T_82541_2, WMP_F_1000T }, 627 628 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI, 629 "Intel i82547EI 1000BASE-T Ethernet", 630 WM_T_82547, WMP_F_1000T }, 631 632 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI, 633 "Intel i82547GI 1000BASE-T Ethernet", 634 WM_T_82547_2, WMP_F_1000T }, 635 { 0, 0, 636 NULL, 637 0, 0 }, 638 }; 639 640 #ifdef WM_EVENT_COUNTERS 641 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")]; 642 #endif /* WM_EVENT_COUNTERS */ 643 644 #if 0 /* Not currently used */ 645 static __inline uint32_t 646 wm_io_read(struct wm_softc *sc, int reg) 647 { 648 649 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 650 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4)); 651 } 652 #endif 653 654 static __inline void 655 wm_io_write(struct wm_softc *sc, int reg, uint32_t val) 656 { 657 658 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg); 659 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 4, val); 660 } 661 662 static __inline void 663 wm_set_dma_addr(__volatile wiseman_addr_t *wa, bus_addr_t v) 664 { 665 wa->wa_low = htole32(v & 0xffffffffU); 666 if (sizeof(bus_addr_t) == 8) 667 wa->wa_high = htole32((uint64_t) v >> 32); 668 else 669 wa->wa_high = 0; 670 } 671 672 static const struct wm_product * 673 wm_lookup(const struct pci_attach_args *pa) 674 { 675 const struct wm_product *wmp; 676 677 for (wmp = wm_products; wmp->wmp_name != NULL; wmp++) { 678 if (PCI_VENDOR(pa->pa_id) == wmp->wmp_vendor && 679 PCI_PRODUCT(pa->pa_id) == wmp->wmp_product) 680 return (wmp); 681 } 682 return (NULL); 683 } 684 685 static int 686 wm_match(struct device *parent, struct cfdata *cf, void *aux) 687 { 688 struct pci_attach_args *pa = aux; 689 690 if (wm_lookup(pa) != NULL) 691 return (1); 692 693 return (0); 694 } 695 696 static void 697 wm_attach(struct device *parent, struct device *self, void *aux) 698 { 699 struct wm_softc *sc = (void *) self; 700 struct pci_attach_args *pa = aux; 701 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 702 pci_chipset_tag_t pc = pa->pa_pc; 703 pci_intr_handle_t ih; 704 size_t cdata_size; 705 const char *intrstr = NULL; 706 const char *eetype; 707 bus_space_tag_t memt; 708 bus_space_handle_t memh; 709 bus_dma_segment_t seg; 710 int memh_valid; 711 int i, rseg, error; 712 const struct wm_product *wmp; 713 uint8_t enaddr[ETHER_ADDR_LEN]; 714 uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin; 715 pcireg_t preg, memtype; 716 uint32_t reg; 717 int pmreg; 718 719 callout_init(&sc->sc_tick_ch); 720 721 wmp = wm_lookup(pa); 722 if (wmp == NULL) { 723 printf("\n"); 724 panic("wm_attach: impossible"); 725 } 726 727 if (pci_dma64_available(pa)) 728 sc->sc_dmat = pa->pa_dmat64; 729 else 730 sc->sc_dmat = pa->pa_dmat; 731 732 preg = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG)); 733 aprint_naive(": Ethernet controller\n"); 734 aprint_normal(": %s, rev. %d\n", wmp->wmp_name, preg); 735 736 sc->sc_type = wmp->wmp_type; 737 if (sc->sc_type < WM_T_82543) { 738 if (preg < 2) { 739 aprint_error("%s: i82542 must be at least rev. 2\n", 740 sc->sc_dev.dv_xname); 741 return; 742 } 743 if (preg < 3) 744 sc->sc_type = WM_T_82542_2_0; 745 } 746 747 /* 748 * Map the device. All devices support memory-mapped acccess, 749 * and it is really required for normal operation. 750 */ 751 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_PCI_MMBA); 752 switch (memtype) { 753 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 754 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 755 memh_valid = (pci_mapreg_map(pa, WM_PCI_MMBA, 756 memtype, 0, &memt, &memh, NULL, NULL) == 0); 757 break; 758 default: 759 memh_valid = 0; 760 } 761 762 if (memh_valid) { 763 sc->sc_st = memt; 764 sc->sc_sh = memh; 765 } else { 766 aprint_error("%s: unable to map device registers\n", 767 sc->sc_dev.dv_xname); 768 return; 769 } 770 771 /* 772 * In addition, i82544 and later support I/O mapped indirect 773 * register access. It is not desirable (nor supported in 774 * this driver) to use it for normal operation, though it is 775 * required to work around bugs in some chip versions. 776 */ 777 if (sc->sc_type >= WM_T_82544) { 778 /* First we have to find the I/O BAR. */ 779 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 780 if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, i) == 781 PCI_MAPREG_TYPE_IO) 782 break; 783 } 784 if (i == PCI_MAPREG_END) 785 aprint_error("%s: WARNING: unable to find I/O BAR\n", 786 sc->sc_dev.dv_xname); 787 else if (pci_mapreg_map(pa, i, PCI_MAPREG_TYPE_IO, 788 0, &sc->sc_iot, &sc->sc_ioh, 789 NULL, NULL) == 0) 790 sc->sc_flags |= WM_F_IOH_VALID; 791 else 792 aprint_error("%s: WARNING: unable to map I/O space\n", 793 sc->sc_dev.dv_xname); 794 } 795 796 /* Enable bus mastering. Disable MWI on the i82542 2.0. */ 797 preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 798 preg |= PCI_COMMAND_MASTER_ENABLE; 799 if (sc->sc_type < WM_T_82542_2_1) 800 preg &= ~PCI_COMMAND_INVALIDATE_ENABLE; 801 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg); 802 803 /* Get it out of power save mode, if needed. */ 804 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 805 preg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 806 PCI_PMCSR_STATE_MASK; 807 if (preg == PCI_PMCSR_STATE_D3) { 808 /* 809 * The card has lost all configuration data in 810 * this state, so punt. 811 */ 812 aprint_error("%s: unable to wake from power state D3\n", 813 sc->sc_dev.dv_xname); 814 return; 815 } 816 if (preg != PCI_PMCSR_STATE_D0) { 817 aprint_normal("%s: waking up from power state D%d\n", 818 sc->sc_dev.dv_xname, preg); 819 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 820 PCI_PMCSR_STATE_D0); 821 } 822 } 823 824 /* 825 * Map and establish our interrupt. 826 */ 827 if (pci_intr_map(pa, &ih)) { 828 aprint_error("%s: unable to map interrupt\n", 829 sc->sc_dev.dv_xname); 830 return; 831 } 832 intrstr = pci_intr_string(pc, ih); 833 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wm_intr, sc); 834 if (sc->sc_ih == NULL) { 835 aprint_error("%s: unable to establish interrupt", 836 sc->sc_dev.dv_xname); 837 if (intrstr != NULL) 838 aprint_normal(" at %s", intrstr); 839 aprint_normal("\n"); 840 return; 841 } 842 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 843 844 /* 845 * Determine a few things about the bus we're connected to. 846 */ 847 if (sc->sc_type < WM_T_82543) { 848 /* We don't really know the bus characteristics here. */ 849 sc->sc_bus_speed = 33; 850 } else if (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) { 851 /* 852 * CSA (Communication Streaming Architecture) is about as fast 853 * a 32-bit 66MHz PCI Bus. 854 */ 855 sc->sc_flags |= WM_F_CSA; 856 sc->sc_bus_speed = 66; 857 aprint_verbose("%s: Communication Streaming Architecture\n", 858 sc->sc_dev.dv_xname); 859 if (sc->sc_type == WM_T_82547) { 860 callout_init(&sc->sc_txfifo_ch); 861 callout_setfunc(&sc->sc_txfifo_ch, 862 wm_82547_txfifo_stall, sc); 863 aprint_verbose("%s: using 82547 Tx FIFO stall " 864 "work-around\n", sc->sc_dev.dv_xname); 865 } 866 } else { 867 reg = CSR_READ(sc, WMREG_STATUS); 868 if (reg & STATUS_BUS64) 869 sc->sc_flags |= WM_F_BUS64; 870 if (sc->sc_type >= WM_T_82544 && 871 (reg & STATUS_PCIX_MODE) != 0) { 872 pcireg_t pcix_cmd, pcix_sts, bytecnt, maxb; 873 874 sc->sc_flags |= WM_F_PCIX; 875 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 876 PCI_CAP_PCIX, 877 &sc->sc_pcix_offset, NULL) == 0) 878 aprint_error("%s: unable to find PCIX " 879 "capability\n", sc->sc_dev.dv_xname); 880 else if (sc->sc_type != WM_T_82545_3 && 881 sc->sc_type != WM_T_82546_3) { 882 /* 883 * Work around a problem caused by the BIOS 884 * setting the max memory read byte count 885 * incorrectly. 886 */ 887 pcix_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, 888 sc->sc_pcix_offset + PCI_PCIX_CMD); 889 pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag, 890 sc->sc_pcix_offset + PCI_PCIX_STATUS); 891 892 bytecnt = 893 (pcix_cmd & PCI_PCIX_CMD_BYTECNT_MASK) >> 894 PCI_PCIX_CMD_BYTECNT_SHIFT; 895 maxb = 896 (pcix_sts & PCI_PCIX_STATUS_MAXB_MASK) >> 897 PCI_PCIX_STATUS_MAXB_SHIFT; 898 if (bytecnt > maxb) { 899 aprint_verbose("%s: resetting PCI-X " 900 "MMRBC: %d -> %d\n", 901 sc->sc_dev.dv_xname, 902 512 << bytecnt, 512 << maxb); 903 pcix_cmd = (pcix_cmd & 904 ~PCI_PCIX_CMD_BYTECNT_MASK) | 905 (maxb << PCI_PCIX_CMD_BYTECNT_SHIFT); 906 pci_conf_write(pa->pa_pc, pa->pa_tag, 907 sc->sc_pcix_offset + PCI_PCIX_CMD, 908 pcix_cmd); 909 } 910 } 911 } 912 /* 913 * The quad port adapter is special; it has a PCIX-PCIX 914 * bridge on the board, and can run the secondary bus at 915 * a higher speed. 916 */ 917 if (wmp->wmp_product == PCI_PRODUCT_INTEL_82546EB_QUAD) { 918 sc->sc_bus_speed = (sc->sc_flags & WM_F_PCIX) ? 120 919 : 66; 920 } else if (sc->sc_flags & WM_F_PCIX) { 921 switch (reg & STATUS_PCIXSPD_MASK) { 922 case STATUS_PCIXSPD_50_66: 923 sc->sc_bus_speed = 66; 924 break; 925 case STATUS_PCIXSPD_66_100: 926 sc->sc_bus_speed = 100; 927 break; 928 case STATUS_PCIXSPD_100_133: 929 sc->sc_bus_speed = 133; 930 break; 931 default: 932 aprint_error( 933 "%s: unknown PCIXSPD %d; assuming 66MHz\n", 934 sc->sc_dev.dv_xname, 935 reg & STATUS_PCIXSPD_MASK); 936 sc->sc_bus_speed = 66; 937 } 938 } else 939 sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33; 940 aprint_verbose("%s: %d-bit %dMHz %s bus\n", sc->sc_dev.dv_xname, 941 (sc->sc_flags & WM_F_BUS64) ? 64 : 32, sc->sc_bus_speed, 942 (sc->sc_flags & WM_F_PCIX) ? "PCIX" : "PCI"); 943 } 944 945 /* 946 * Allocate the control data structures, and create and load the 947 * DMA map for it. 948 * 949 * NOTE: All Tx descriptors must be in the same 4G segment of 950 * memory. So must Rx descriptors. We simplify by allocating 951 * both sets within the same 4G segment. 952 */ 953 WM_NTXDESC(sc) = sc->sc_type < WM_T_82544 ? 954 WM_NTXDESC_82542 : WM_NTXDESC_82544; 955 cdata_size = sc->sc_type < WM_T_82544 ? 956 sizeof(struct wm_control_data_82542) : 957 sizeof(struct wm_control_data_82544); 958 if ((error = bus_dmamem_alloc(sc->sc_dmat, cdata_size, PAGE_SIZE, 959 (bus_size_t) 0x100000000ULL, 960 &seg, 1, &rseg, 0)) != 0) { 961 aprint_error( 962 "%s: unable to allocate control data, error = %d\n", 963 sc->sc_dev.dv_xname, error); 964 goto fail_0; 965 } 966 967 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, cdata_size, 968 (caddr_t *)&sc->sc_control_data, 0)) != 0) { 969 aprint_error("%s: unable to map control data, error = %d\n", 970 sc->sc_dev.dv_xname, error); 971 goto fail_1; 972 } 973 974 if ((error = bus_dmamap_create(sc->sc_dmat, cdata_size, 1, cdata_size, 975 0, 0, &sc->sc_cddmamap)) != 0) { 976 aprint_error("%s: unable to create control data DMA map, " 977 "error = %d\n", sc->sc_dev.dv_xname, error); 978 goto fail_2; 979 } 980 981 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 982 sc->sc_control_data, cdata_size, NULL, 983 0)) != 0) { 984 aprint_error( 985 "%s: unable to load control data DMA map, error = %d\n", 986 sc->sc_dev.dv_xname, error); 987 goto fail_3; 988 } 989 990 991 /* 992 * Create the transmit buffer DMA maps. 993 */ 994 WM_TXQUEUELEN(sc) = 995 (sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ? 996 WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX; 997 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 998 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 999 WM_NTXSEGS, WTX_MAX_LEN, 0, 0, 1000 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1001 aprint_error("%s: unable to create Tx DMA map %d, " 1002 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1003 goto fail_4; 1004 } 1005 } 1006 1007 /* 1008 * Create the receive buffer DMA maps. 1009 */ 1010 for (i = 0; i < WM_NRXDESC; i++) { 1011 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1012 MCLBYTES, 0, 0, 1013 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1014 aprint_error("%s: unable to create Rx DMA map %d, " 1015 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1016 goto fail_5; 1017 } 1018 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1019 } 1020 1021 /* 1022 * Reset the chip to a known state. 1023 */ 1024 wm_reset(sc); 1025 1026 /* 1027 * Get some information about the EEPROM. 1028 */ 1029 if (sc->sc_type >= WM_T_82540) 1030 sc->sc_flags |= WM_F_EEPROM_HANDSHAKE; 1031 if (sc->sc_type <= WM_T_82544) 1032 sc->sc_ee_addrbits = 6; 1033 else if (sc->sc_type <= WM_T_82546_3) { 1034 reg = CSR_READ(sc, WMREG_EECD); 1035 if (reg & EECD_EE_SIZE) 1036 sc->sc_ee_addrbits = 8; 1037 else 1038 sc->sc_ee_addrbits = 6; 1039 } else if (sc->sc_type <= WM_T_82547_2) { 1040 reg = CSR_READ(sc, WMREG_EECD); 1041 if (reg & EECD_EE_TYPE) { 1042 sc->sc_flags |= WM_F_EEPROM_SPI; 1043 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1044 } else 1045 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 8 : 6; 1046 } else { 1047 /* Assume everything else is SPI. */ 1048 reg = CSR_READ(sc, WMREG_EECD); 1049 sc->sc_flags |= WM_F_EEPROM_SPI; 1050 sc->sc_ee_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8; 1051 } 1052 if (sc->sc_flags & WM_F_EEPROM_SPI) 1053 eetype = "SPI"; 1054 else 1055 eetype = "MicroWire"; 1056 aprint_verbose("%s: %u word (%d address bits) %s EEPROM\n", 1057 sc->sc_dev.dv_xname, 1U << sc->sc_ee_addrbits, 1058 sc->sc_ee_addrbits, eetype); 1059 1060 /* 1061 * Read the Ethernet address from the EEPROM. 1062 */ 1063 if (wm_read_eeprom(sc, EEPROM_OFF_MACADDR, 1064 sizeof(myea) / sizeof(myea[0]), myea)) { 1065 aprint_error("%s: unable to read Ethernet address\n", 1066 sc->sc_dev.dv_xname); 1067 return; 1068 } 1069 enaddr[0] = myea[0] & 0xff; 1070 enaddr[1] = myea[0] >> 8; 1071 enaddr[2] = myea[1] & 0xff; 1072 enaddr[3] = myea[1] >> 8; 1073 enaddr[4] = myea[2] & 0xff; 1074 enaddr[5] = myea[2] >> 8; 1075 1076 /* 1077 * Toggle the LSB of the MAC address on the second port 1078 * of the i82546. 1079 */ 1080 if (sc->sc_type == WM_T_82546) { 1081 if ((CSR_READ(sc, WMREG_STATUS) >> STATUS_FUNCID_SHIFT) & 1) 1082 enaddr[5] ^= 1; 1083 } 1084 1085 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1086 ether_sprintf(enaddr)); 1087 1088 /* 1089 * Read the config info from the EEPROM, and set up various 1090 * bits in the control registers based on their contents. 1091 */ 1092 if (wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1)) { 1093 aprint_error("%s: unable to read CFG1 from EEPROM\n", 1094 sc->sc_dev.dv_xname); 1095 return; 1096 } 1097 if (wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2)) { 1098 aprint_error("%s: unable to read CFG2 from EEPROM\n", 1099 sc->sc_dev.dv_xname); 1100 return; 1101 } 1102 if (sc->sc_type >= WM_T_82544) { 1103 if (wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin)) { 1104 aprint_error("%s: unable to read SWDPIN from EEPROM\n", 1105 sc->sc_dev.dv_xname); 1106 return; 1107 } 1108 } 1109 1110 if (cfg1 & EEPROM_CFG1_ILOS) 1111 sc->sc_ctrl |= CTRL_ILOS; 1112 if (sc->sc_type >= WM_T_82544) { 1113 sc->sc_ctrl |= 1114 ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) << 1115 CTRL_SWDPIO_SHIFT; 1116 sc->sc_ctrl |= 1117 ((swdpin >> EEPROM_SWDPIN_SWDPIN_SHIFT) & 0xf) << 1118 CTRL_SWDPINS_SHIFT; 1119 } else { 1120 sc->sc_ctrl |= 1121 ((cfg1 >> EEPROM_CFG1_SWDPIO_SHIFT) & 0xf) << 1122 CTRL_SWDPIO_SHIFT; 1123 } 1124 1125 #if 0 1126 if (sc->sc_type >= WM_T_82544) { 1127 if (cfg1 & EEPROM_CFG1_IPS0) 1128 sc->sc_ctrl_ext |= CTRL_EXT_IPS; 1129 if (cfg1 & EEPROM_CFG1_IPS1) 1130 sc->sc_ctrl_ext |= CTRL_EXT_IPS1; 1131 sc->sc_ctrl_ext |= 1132 ((swdpin >> (EEPROM_SWDPIN_SWDPIO_SHIFT + 4)) & 0xd) << 1133 CTRL_EXT_SWDPIO_SHIFT; 1134 sc->sc_ctrl_ext |= 1135 ((swdpin >> (EEPROM_SWDPIN_SWDPIN_SHIFT + 4)) & 0xd) << 1136 CTRL_EXT_SWDPINS_SHIFT; 1137 } else { 1138 sc->sc_ctrl_ext |= 1139 ((cfg2 >> EEPROM_CFG2_SWDPIO_SHIFT) & 0xf) << 1140 CTRL_EXT_SWDPIO_SHIFT; 1141 } 1142 #endif 1143 1144 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1145 #if 0 1146 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 1147 #endif 1148 1149 /* 1150 * Set up some register offsets that are different between 1151 * the i82542 and the i82543 and later chips. 1152 */ 1153 if (sc->sc_type < WM_T_82543) { 1154 sc->sc_rdt_reg = WMREG_OLD_RDT0; 1155 sc->sc_tdt_reg = WMREG_OLD_TDT; 1156 } else { 1157 sc->sc_rdt_reg = WMREG_RDT; 1158 sc->sc_tdt_reg = WMREG_TDT; 1159 } 1160 1161 /* 1162 * Determine if we're TBI or GMII mode, and initialize the 1163 * media structures accordingly. 1164 */ 1165 if (sc->sc_type < WM_T_82543 || 1166 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 1167 if (wmp->wmp_flags & WMP_F_1000T) 1168 aprint_error("%s: WARNING: TBIMODE set on 1000BASE-T " 1169 "product!\n", sc->sc_dev.dv_xname); 1170 wm_tbi_mediainit(sc); 1171 } else { 1172 if (wmp->wmp_flags & WMP_F_1000X) 1173 aprint_error("%s: WARNING: TBIMODE clear on 1000BASE-X " 1174 "product!\n", sc->sc_dev.dv_xname); 1175 wm_gmii_mediainit(sc); 1176 } 1177 1178 ifp = &sc->sc_ethercom.ec_if; 1179 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1180 ifp->if_softc = sc; 1181 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1182 ifp->if_ioctl = wm_ioctl; 1183 ifp->if_start = wm_start; 1184 ifp->if_watchdog = wm_watchdog; 1185 ifp->if_init = wm_init; 1186 ifp->if_stop = wm_stop; 1187 IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN)); 1188 IFQ_SET_READY(&ifp->if_snd); 1189 1190 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 1191 1192 /* 1193 * If we're a i82543 or greater, we can support VLANs. 1194 */ 1195 if (sc->sc_type >= WM_T_82543) 1196 sc->sc_ethercom.ec_capabilities |= 1197 ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */; 1198 1199 /* 1200 * We can perform TCPv4 and UDPv4 checkums in-bound. Only 1201 * on i82543 and later. 1202 */ 1203 if (sc->sc_type >= WM_T_82543) 1204 ifp->if_capabilities |= 1205 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1206 1207 /* 1208 * Attach the interface. 1209 */ 1210 if_attach(ifp); 1211 ether_ifattach(ifp, enaddr); 1212 #if NRND > 0 1213 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1214 RND_TYPE_NET, 0); 1215 #endif 1216 1217 #ifdef WM_EVENT_COUNTERS 1218 /* Attach event counters. */ 1219 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1220 NULL, sc->sc_dev.dv_xname, "txsstall"); 1221 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1222 NULL, sc->sc_dev.dv_xname, "txdstall"); 1223 evcnt_attach_dynamic(&sc->sc_ev_txfifo_stall, EVCNT_TYPE_MISC, 1224 NULL, sc->sc_dev.dv_xname, "txfifo_stall"); 1225 evcnt_attach_dynamic(&sc->sc_ev_txdw, EVCNT_TYPE_INTR, 1226 NULL, sc->sc_dev.dv_xname, "txdw"); 1227 evcnt_attach_dynamic(&sc->sc_ev_txqe, EVCNT_TYPE_INTR, 1228 NULL, sc->sc_dev.dv_xname, "txqe"); 1229 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1230 NULL, sc->sc_dev.dv_xname, "rxintr"); 1231 evcnt_attach_dynamic(&sc->sc_ev_linkintr, EVCNT_TYPE_INTR, 1232 NULL, sc->sc_dev.dv_xname, "linkintr"); 1233 1234 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1235 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1236 evcnt_attach_dynamic(&sc->sc_ev_rxtusum, EVCNT_TYPE_MISC, 1237 NULL, sc->sc_dev.dv_xname, "rxtusum"); 1238 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1239 NULL, sc->sc_dev.dv_xname, "txipsum"); 1240 evcnt_attach_dynamic(&sc->sc_ev_txtusum, EVCNT_TYPE_MISC, 1241 NULL, sc->sc_dev.dv_xname, "txtusum"); 1242 1243 evcnt_attach_dynamic(&sc->sc_ev_txctx_init, EVCNT_TYPE_MISC, 1244 NULL, sc->sc_dev.dv_xname, "txctx init"); 1245 evcnt_attach_dynamic(&sc->sc_ev_txctx_hit, EVCNT_TYPE_MISC, 1246 NULL, sc->sc_dev.dv_xname, "txctx hit"); 1247 evcnt_attach_dynamic(&sc->sc_ev_txctx_miss, EVCNT_TYPE_MISC, 1248 NULL, sc->sc_dev.dv_xname, "txctx miss"); 1249 1250 for (i = 0; i < WM_NTXSEGS; i++) { 1251 sprintf(wm_txseg_evcnt_names[i], "txseg%d", i); 1252 evcnt_attach_dynamic(&sc->sc_ev_txseg[i], EVCNT_TYPE_MISC, 1253 NULL, sc->sc_dev.dv_xname, wm_txseg_evcnt_names[i]); 1254 } 1255 1256 evcnt_attach_dynamic(&sc->sc_ev_txdrop, EVCNT_TYPE_MISC, 1257 NULL, sc->sc_dev.dv_xname, "txdrop"); 1258 1259 evcnt_attach_dynamic(&sc->sc_ev_tu, EVCNT_TYPE_MISC, 1260 NULL, sc->sc_dev.dv_xname, "tu"); 1261 1262 evcnt_attach_dynamic(&sc->sc_ev_tx_xoff, EVCNT_TYPE_MISC, 1263 NULL, sc->sc_dev.dv_xname, "tx_xoff"); 1264 evcnt_attach_dynamic(&sc->sc_ev_tx_xon, EVCNT_TYPE_MISC, 1265 NULL, sc->sc_dev.dv_xname, "tx_xon"); 1266 evcnt_attach_dynamic(&sc->sc_ev_rx_xoff, EVCNT_TYPE_MISC, 1267 NULL, sc->sc_dev.dv_xname, "rx_xoff"); 1268 evcnt_attach_dynamic(&sc->sc_ev_rx_xon, EVCNT_TYPE_MISC, 1269 NULL, sc->sc_dev.dv_xname, "rx_xon"); 1270 evcnt_attach_dynamic(&sc->sc_ev_rx_macctl, EVCNT_TYPE_MISC, 1271 NULL, sc->sc_dev.dv_xname, "rx_macctl"); 1272 #endif /* WM_EVENT_COUNTERS */ 1273 1274 /* 1275 * Make sure the interface is shutdown during reboot. 1276 */ 1277 sc->sc_sdhook = shutdownhook_establish(wm_shutdown, sc); 1278 if (sc->sc_sdhook == NULL) 1279 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 1280 sc->sc_dev.dv_xname); 1281 return; 1282 1283 /* 1284 * Free any resources we've allocated during the failed attach 1285 * attempt. Do this in reverse order and fall through. 1286 */ 1287 fail_5: 1288 for (i = 0; i < WM_NRXDESC; i++) { 1289 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1290 bus_dmamap_destroy(sc->sc_dmat, 1291 sc->sc_rxsoft[i].rxs_dmamap); 1292 } 1293 fail_4: 1294 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 1295 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1296 bus_dmamap_destroy(sc->sc_dmat, 1297 sc->sc_txsoft[i].txs_dmamap); 1298 } 1299 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1300 fail_3: 1301 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1302 fail_2: 1303 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1304 cdata_size); 1305 fail_1: 1306 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1307 fail_0: 1308 return; 1309 } 1310 1311 /* 1312 * wm_shutdown: 1313 * 1314 * Make sure the interface is stopped at reboot time. 1315 */ 1316 static void 1317 wm_shutdown(void *arg) 1318 { 1319 struct wm_softc *sc = arg; 1320 1321 wm_stop(&sc->sc_ethercom.ec_if, 1); 1322 } 1323 1324 /* 1325 * wm_tx_cksum: 1326 * 1327 * Set up TCP/IP checksumming parameters for the 1328 * specified packet. 1329 */ 1330 static int 1331 wm_tx_cksum(struct wm_softc *sc, struct wm_txsoft *txs, uint32_t *cmdp, 1332 uint8_t *fieldsp) 1333 { 1334 struct mbuf *m0 = txs->txs_mbuf; 1335 struct livengood_tcpip_ctxdesc *t; 1336 uint32_t ipcs, tucs; 1337 struct ip *ip; 1338 struct ether_header *eh; 1339 int offset, iphl; 1340 uint8_t fields = 0; 1341 1342 /* 1343 * XXX It would be nice if the mbuf pkthdr had offset 1344 * fields for the protocol headers. 1345 */ 1346 1347 eh = mtod(m0, struct ether_header *); 1348 switch (htons(eh->ether_type)) { 1349 case ETHERTYPE_IP: 1350 iphl = sizeof(struct ip); 1351 offset = ETHER_HDR_LEN; 1352 break; 1353 1354 case ETHERTYPE_VLAN: 1355 iphl = sizeof(struct ip); 1356 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1357 break; 1358 1359 default: 1360 /* 1361 * Don't support this protocol or encapsulation. 1362 */ 1363 *fieldsp = 0; 1364 *cmdp = 0; 1365 return (0); 1366 } 1367 1368 if (m0->m_len < (offset + iphl)) { 1369 if ((txs->txs_mbuf = m_pullup(m0, offset + iphl)) == NULL) { 1370 printf("%s: wm_tx_cksum: mbuf allocation failed, " 1371 "packet dropped\n", sc->sc_dev.dv_xname); 1372 return (ENOMEM); 1373 } 1374 m0 = txs->txs_mbuf; 1375 } 1376 1377 ip = (struct ip *) (mtod(m0, caddr_t) + offset); 1378 iphl = ip->ip_hl << 2; 1379 1380 /* 1381 * NOTE: Even if we're not using the IP or TCP/UDP checksum 1382 * offload feature, if we load the context descriptor, we 1383 * MUST provide valid values for IPCSS and TUCSS fields. 1384 */ 1385 1386 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1387 WM_EVCNT_INCR(&sc->sc_ev_txipsum); 1388 fields |= WTX_IXSM; 1389 ipcs = WTX_TCPIP_IPCSS(offset) | 1390 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1391 WTX_TCPIP_IPCSE(offset + iphl - 1); 1392 } else if (__predict_true(sc->sc_txctx_ipcs != 0xffffffff)) { 1393 /* Use the cached value. */ 1394 ipcs = sc->sc_txctx_ipcs; 1395 } else { 1396 /* Just initialize it to the likely value anyway. */ 1397 ipcs = WTX_TCPIP_IPCSS(offset) | 1398 WTX_TCPIP_IPCSO(offset + offsetof(struct ip, ip_sum)) | 1399 WTX_TCPIP_IPCSE(offset + iphl - 1); 1400 } 1401 1402 offset += iphl; 1403 1404 if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1405 WM_EVCNT_INCR(&sc->sc_ev_txtusum); 1406 fields |= WTX_TXSM; 1407 tucs = WTX_TCPIP_TUCSS(offset) | 1408 WTX_TCPIP_TUCSO(offset + m0->m_pkthdr.csum_data) | 1409 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1410 } else if (__predict_true(sc->sc_txctx_tucs != 0xffffffff)) { 1411 /* Use the cached value. */ 1412 tucs = sc->sc_txctx_tucs; 1413 } else { 1414 /* Just initialize it to a valid TCP context. */ 1415 tucs = WTX_TCPIP_TUCSS(offset) | 1416 WTX_TCPIP_TUCSO(offset + offsetof(struct tcphdr, th_sum)) | 1417 WTX_TCPIP_TUCSE(0) /* rest of packet */; 1418 } 1419 1420 if (sc->sc_txctx_ipcs == ipcs && 1421 sc->sc_txctx_tucs == tucs) { 1422 /* Cached context is fine. */ 1423 WM_EVCNT_INCR(&sc->sc_ev_txctx_hit); 1424 } else { 1425 /* Fill in the context descriptor. */ 1426 #ifdef WM_EVENT_COUNTERS 1427 if (sc->sc_txctx_ipcs == 0xffffffff && 1428 sc->sc_txctx_tucs == 0xffffffff) 1429 WM_EVCNT_INCR(&sc->sc_ev_txctx_init); 1430 else 1431 WM_EVCNT_INCR(&sc->sc_ev_txctx_miss); 1432 #endif 1433 t = (struct livengood_tcpip_ctxdesc *) 1434 &sc->sc_txdescs[sc->sc_txnext]; 1435 t->tcpip_ipcs = htole32(ipcs); 1436 t->tcpip_tucs = htole32(tucs); 1437 t->tcpip_cmdlen = htole32(WTX_CMD_DEXT | WTX_DTYP_C); 1438 t->tcpip_seg = 0; 1439 WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE); 1440 1441 sc->sc_txctx_ipcs = ipcs; 1442 sc->sc_txctx_tucs = tucs; 1443 1444 sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext); 1445 txs->txs_ndesc++; 1446 } 1447 1448 *cmdp = WTX_CMD_DEXT | WTX_DTYP_D; 1449 *fieldsp = fields; 1450 1451 return (0); 1452 } 1453 1454 static void 1455 wm_dump_mbuf_chain(struct wm_softc *sc, struct mbuf *m0) 1456 { 1457 struct mbuf *m; 1458 int i; 1459 1460 printf("%s: mbuf chain:\n", sc->sc_dev.dv_xname); 1461 for (m = m0, i = 0; m != NULL; m = m->m_next, i++) 1462 printf("\tm_data = %p, m_len = %d, m_flags = 0x%08x\n", 1463 m->m_data, m->m_len, m->m_flags); 1464 printf("\t%d mbuf%s in chain\n", i, i == 1 ? "" : "s"); 1465 } 1466 1467 /* 1468 * wm_82547_txfifo_stall: 1469 * 1470 * Callout used to wait for the 82547 Tx FIFO to drain, 1471 * reset the FIFO pointers, and restart packet transmission. 1472 */ 1473 static void 1474 wm_82547_txfifo_stall(void *arg) 1475 { 1476 struct wm_softc *sc = arg; 1477 int s; 1478 1479 s = splnet(); 1480 1481 if (sc->sc_txfifo_stall) { 1482 if (CSR_READ(sc, WMREG_TDT) == CSR_READ(sc, WMREG_TDH) && 1483 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) && 1484 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) { 1485 /* 1486 * Packets have drained. Stop transmitter, reset 1487 * FIFO pointers, restart transmitter, and kick 1488 * the packet queue. 1489 */ 1490 uint32_t tctl = CSR_READ(sc, WMREG_TCTL); 1491 CSR_WRITE(sc, WMREG_TCTL, tctl & ~TCTL_EN); 1492 CSR_WRITE(sc, WMREG_TDFT, sc->sc_txfifo_addr); 1493 CSR_WRITE(sc, WMREG_TDFH, sc->sc_txfifo_addr); 1494 CSR_WRITE(sc, WMREG_TDFTS, sc->sc_txfifo_addr); 1495 CSR_WRITE(sc, WMREG_TDFHS, sc->sc_txfifo_addr); 1496 CSR_WRITE(sc, WMREG_TCTL, tctl); 1497 CSR_WRITE_FLUSH(sc); 1498 1499 sc->sc_txfifo_head = 0; 1500 sc->sc_txfifo_stall = 0; 1501 wm_start(&sc->sc_ethercom.ec_if); 1502 } else { 1503 /* 1504 * Still waiting for packets to drain; try again in 1505 * another tick. 1506 */ 1507 callout_schedule(&sc->sc_txfifo_ch, 1); 1508 } 1509 } 1510 1511 splx(s); 1512 } 1513 1514 /* 1515 * wm_82547_txfifo_bugchk: 1516 * 1517 * Check for bug condition in the 82547 Tx FIFO. We need to 1518 * prevent enqueueing a packet that would wrap around the end 1519 * if the Tx FIFO ring buffer, otherwise the chip will croak. 1520 * 1521 * We do this by checking the amount of space before the end 1522 * of the Tx FIFO buffer. If the packet will not fit, we "stall" 1523 * the Tx FIFO, wait for all remaining packets to drain, reset 1524 * the internal FIFO pointers to the beginning, and restart 1525 * transmission on the interface. 1526 */ 1527 #define WM_FIFO_HDR 0x10 1528 #define WM_82547_PAD_LEN 0x3e0 1529 static int 1530 wm_82547_txfifo_bugchk(struct wm_softc *sc, struct mbuf *m0) 1531 { 1532 int space = sc->sc_txfifo_size - sc->sc_txfifo_head; 1533 int len = roundup(m0->m_pkthdr.len + WM_FIFO_HDR, WM_FIFO_HDR); 1534 1535 /* Just return if already stalled. */ 1536 if (sc->sc_txfifo_stall) 1537 return (1); 1538 1539 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1540 /* Stall only occurs in half-duplex mode. */ 1541 goto send_packet; 1542 } 1543 1544 if (len >= WM_82547_PAD_LEN + space) { 1545 sc->sc_txfifo_stall = 1; 1546 callout_schedule(&sc->sc_txfifo_ch, 1); 1547 return (1); 1548 } 1549 1550 send_packet: 1551 sc->sc_txfifo_head += len; 1552 if (sc->sc_txfifo_head >= sc->sc_txfifo_size) 1553 sc->sc_txfifo_head -= sc->sc_txfifo_size; 1554 1555 return (0); 1556 } 1557 1558 /* 1559 * wm_start: [ifnet interface function] 1560 * 1561 * Start packet transmission on the interface. 1562 */ 1563 static void 1564 wm_start(struct ifnet *ifp) 1565 { 1566 struct wm_softc *sc = ifp->if_softc; 1567 struct mbuf *m0; 1568 #if 0 /* XXXJRT */ 1569 struct m_tag *mtag; 1570 #endif 1571 struct wm_txsoft *txs; 1572 bus_dmamap_t dmamap; 1573 int error, nexttx, lasttx = -1, ofree, seg, segs_needed; 1574 bus_addr_t curaddr; 1575 bus_size_t seglen, curlen; 1576 uint32_t cksumcmd; 1577 uint8_t cksumfields; 1578 1579 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1580 return; 1581 1582 /* 1583 * Remember the previous number of free descriptors. 1584 */ 1585 ofree = sc->sc_txfree; 1586 1587 /* 1588 * Loop through the send queue, setting up transmit descriptors 1589 * until we drain the queue, or use up all available transmit 1590 * descriptors. 1591 */ 1592 for (;;) { 1593 /* Grab a packet off the queue. */ 1594 IFQ_POLL(&ifp->if_snd, m0); 1595 if (m0 == NULL) 1596 break; 1597 1598 DPRINTF(WM_DEBUG_TX, 1599 ("%s: TX: have packet to transmit: %p\n", 1600 sc->sc_dev.dv_xname, m0)); 1601 1602 /* Get a work queue entry. */ 1603 if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) { 1604 wm_txintr(sc); 1605 if (sc->sc_txsfree == 0) { 1606 DPRINTF(WM_DEBUG_TX, 1607 ("%s: TX: no free job descriptors\n", 1608 sc->sc_dev.dv_xname)); 1609 WM_EVCNT_INCR(&sc->sc_ev_txsstall); 1610 break; 1611 } 1612 } 1613 1614 txs = &sc->sc_txsoft[sc->sc_txsnext]; 1615 dmamap = txs->txs_dmamap; 1616 1617 /* 1618 * Load the DMA map. If this fails, the packet either 1619 * didn't fit in the allotted number of segments, or we 1620 * were short on resources. For the too-many-segments 1621 * case, we simply report an error and drop the packet, 1622 * since we can't sanely copy a jumbo packet to a single 1623 * buffer. 1624 */ 1625 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1626 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1627 if (error) { 1628 if (error == EFBIG) { 1629 WM_EVCNT_INCR(&sc->sc_ev_txdrop); 1630 printf("%s: Tx packet consumes too many " 1631 "DMA segments, dropping...\n", 1632 sc->sc_dev.dv_xname); 1633 IFQ_DEQUEUE(&ifp->if_snd, m0); 1634 wm_dump_mbuf_chain(sc, m0); 1635 m_freem(m0); 1636 continue; 1637 } 1638 /* 1639 * Short on resources, just stop for now. 1640 */ 1641 DPRINTF(WM_DEBUG_TX, 1642 ("%s: TX: dmamap load failed: %d\n", 1643 sc->sc_dev.dv_xname, error)); 1644 break; 1645 } 1646 1647 segs_needed = dmamap->dm_nsegs; 1648 1649 /* 1650 * Ensure we have enough descriptors free to describe 1651 * the packet. Note, we always reserve one descriptor 1652 * at the end of the ring due to the semantics of the 1653 * TDT register, plus one more in the event we need 1654 * to re-load checksum offload context. 1655 */ 1656 if (segs_needed > sc->sc_txfree - 2) { 1657 /* 1658 * Not enough free descriptors to transmit this 1659 * packet. We haven't committed anything yet, 1660 * so just unload the DMA map, put the packet 1661 * pack on the queue, and punt. Notify the upper 1662 * layer that there are no more slots left. 1663 */ 1664 DPRINTF(WM_DEBUG_TX, 1665 ("%s: TX: need %d (%) descriptors, have %d\n", 1666 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed, 1667 sc->sc_txfree - 1)); 1668 ifp->if_flags |= IFF_OACTIVE; 1669 bus_dmamap_unload(sc->sc_dmat, dmamap); 1670 WM_EVCNT_INCR(&sc->sc_ev_txdstall); 1671 break; 1672 } 1673 1674 /* 1675 * Check for 82547 Tx FIFO bug. We need to do this 1676 * once we know we can transmit the packet, since we 1677 * do some internal FIFO space accounting here. 1678 */ 1679 if (sc->sc_type == WM_T_82547 && 1680 wm_82547_txfifo_bugchk(sc, m0)) { 1681 DPRINTF(WM_DEBUG_TX, 1682 ("%s: TX: 82547 Tx FIFO bug detected\n", 1683 sc->sc_dev.dv_xname)); 1684 ifp->if_flags |= IFF_OACTIVE; 1685 bus_dmamap_unload(sc->sc_dmat, dmamap); 1686 WM_EVCNT_INCR(&sc->sc_ev_txfifo_stall); 1687 break; 1688 } 1689 1690 IFQ_DEQUEUE(&ifp->if_snd, m0); 1691 1692 /* 1693 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1694 */ 1695 1696 /* Sync the DMA map. */ 1697 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1698 BUS_DMASYNC_PREWRITE); 1699 1700 DPRINTF(WM_DEBUG_TX, 1701 ("%s: TX: packet has %d (%d) DMA segments\n", 1702 sc->sc_dev.dv_xname, dmamap->dm_nsegs, segs_needed)); 1703 1704 WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]); 1705 1706 /* 1707 * Store a pointer to the packet so that we can free it 1708 * later. 1709 * 1710 * Initially, we consider the number of descriptors the 1711 * packet uses the number of DMA segments. This may be 1712 * incremented by 1 if we do checksum offload (a descriptor 1713 * is used to set the checksum context). 1714 */ 1715 txs->txs_mbuf = m0; 1716 txs->txs_firstdesc = sc->sc_txnext; 1717 txs->txs_ndesc = segs_needed; 1718 1719 /* 1720 * Set up checksum offload parameters for 1721 * this packet. 1722 */ 1723 if (m0->m_pkthdr.csum_flags & 1724 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1725 if (wm_tx_cksum(sc, txs, &cksumcmd, 1726 &cksumfields) != 0) { 1727 /* Error message already displayed. */ 1728 bus_dmamap_unload(sc->sc_dmat, dmamap); 1729 continue; 1730 } 1731 } else { 1732 cksumcmd = 0; 1733 cksumfields = 0; 1734 } 1735 1736 cksumcmd |= WTX_CMD_IDE; 1737 1738 /* 1739 * Initialize the transmit descriptor. 1740 */ 1741 for (nexttx = sc->sc_txnext, seg = 0; 1742 seg < dmamap->dm_nsegs; seg++) { 1743 for (seglen = dmamap->dm_segs[seg].ds_len, 1744 curaddr = dmamap->dm_segs[seg].ds_addr; 1745 seglen != 0; 1746 curaddr += curlen, seglen -= curlen, 1747 nexttx = WM_NEXTTX(sc, nexttx)) { 1748 curlen = seglen; 1749 1750 wm_set_dma_addr( 1751 &sc->sc_txdescs[nexttx].wtx_addr, 1752 curaddr); 1753 sc->sc_txdescs[nexttx].wtx_cmdlen = 1754 htole32(cksumcmd | curlen); 1755 sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 1756 0; 1757 sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 1758 cksumfields; 1759 sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0; 1760 lasttx = nexttx; 1761 1762 DPRINTF(WM_DEBUG_TX, 1763 ("%s: TX: desc %d: low 0x%08x, " 1764 "len 0x%04x\n", 1765 sc->sc_dev.dv_xname, nexttx, 1766 curaddr & 0xffffffffU, curlen, curlen)); 1767 } 1768 } 1769 1770 KASSERT(lasttx != -1); 1771 1772 /* 1773 * Set up the command byte on the last descriptor of 1774 * the packet. If we're in the interrupt delay window, 1775 * delay the interrupt. 1776 */ 1777 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1778 htole32(WTX_CMD_EOP | WTX_CMD_IFCS | WTX_CMD_RS); 1779 1780 #if 0 /* XXXJRT */ 1781 /* 1782 * If VLANs are enabled and the packet has a VLAN tag, set 1783 * up the descriptor to encapsulate the packet for us. 1784 * 1785 * This is only valid on the last descriptor of the packet. 1786 */ 1787 if (sc->sc_ethercom.ec_nvlans != 0 && 1788 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1789 sc->sc_txdescs[lasttx].wtx_cmdlen |= 1790 htole32(WTX_CMD_VLE); 1791 sc->sc_txdescs[lasttx].wtx_fields.wtxu_vlan 1792 = htole16(*(u_int *)(mtag + 1) & 0xffff); 1793 } 1794 #endif /* XXXJRT */ 1795 1796 txs->txs_lastdesc = lasttx; 1797 1798 DPRINTF(WM_DEBUG_TX, 1799 ("%s: TX: desc %d: cmdlen 0x%08x\n", sc->sc_dev.dv_xname, 1800 lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen))); 1801 1802 /* Sync the descriptors we're using. */ 1803 WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc, 1804 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1805 1806 /* Give the packet to the chip. */ 1807 CSR_WRITE(sc, sc->sc_tdt_reg, nexttx); 1808 1809 DPRINTF(WM_DEBUG_TX, 1810 ("%s: TX: TDT -> %d\n", sc->sc_dev.dv_xname, nexttx)); 1811 1812 DPRINTF(WM_DEBUG_TX, 1813 ("%s: TX: finished transmitting packet, job %d\n", 1814 sc->sc_dev.dv_xname, sc->sc_txsnext)); 1815 1816 /* Advance the tx pointer. */ 1817 sc->sc_txfree -= txs->txs_ndesc; 1818 sc->sc_txnext = nexttx; 1819 1820 sc->sc_txsfree--; 1821 sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext); 1822 1823 #if NBPFILTER > 0 1824 /* Pass the packet to any BPF listeners. */ 1825 if (ifp->if_bpf) 1826 bpf_mtap(ifp->if_bpf, m0); 1827 #endif /* NBPFILTER > 0 */ 1828 } 1829 1830 if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) { 1831 /* No more slots; notify upper layer. */ 1832 ifp->if_flags |= IFF_OACTIVE; 1833 } 1834 1835 if (sc->sc_txfree != ofree) { 1836 /* Set a watchdog timer in case the chip flakes out. */ 1837 ifp->if_timer = 5; 1838 } 1839 } 1840 1841 /* 1842 * wm_watchdog: [ifnet interface function] 1843 * 1844 * Watchdog timer handler. 1845 */ 1846 static void 1847 wm_watchdog(struct ifnet *ifp) 1848 { 1849 struct wm_softc *sc = ifp->if_softc; 1850 1851 /* 1852 * Since we're using delayed interrupts, sweep up 1853 * before we report an error. 1854 */ 1855 wm_txintr(sc); 1856 1857 if (sc->sc_txfree != WM_NTXDESC(sc)) { 1858 printf("%s: device timeout (txfree %d txsfree %d txnext %d)\n", 1859 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree, 1860 sc->sc_txnext); 1861 ifp->if_oerrors++; 1862 1863 /* Reset the interface. */ 1864 (void) wm_init(ifp); 1865 } 1866 1867 /* Try to get more packets going. */ 1868 wm_start(ifp); 1869 } 1870 1871 /* 1872 * wm_ioctl: [ifnet interface function] 1873 * 1874 * Handle control requests from the operator. 1875 */ 1876 static int 1877 wm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1878 { 1879 struct wm_softc *sc = ifp->if_softc; 1880 struct ifreq *ifr = (struct ifreq *) data; 1881 int s, error; 1882 1883 s = splnet(); 1884 1885 switch (cmd) { 1886 case SIOCSIFMEDIA: 1887 case SIOCGIFMEDIA: 1888 /* Flow control requires full-duplex mode. */ 1889 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1890 (ifr->ifr_media & IFM_FDX) == 0) 1891 ifr->ifr_media &= ~IFM_ETH_FMASK; 1892 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1893 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1894 /* We can do both TXPAUSE and RXPAUSE. */ 1895 ifr->ifr_media |= 1896 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1897 } 1898 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1899 } 1900 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1901 break; 1902 default: 1903 error = ether_ioctl(ifp, cmd, data); 1904 if (error == ENETRESET) { 1905 /* 1906 * Multicast list has changed; set the hardware filter 1907 * accordingly. 1908 */ 1909 wm_set_filter(sc); 1910 error = 0; 1911 } 1912 break; 1913 } 1914 1915 /* Try to get more packets going. */ 1916 wm_start(ifp); 1917 1918 splx(s); 1919 return (error); 1920 } 1921 1922 /* 1923 * wm_intr: 1924 * 1925 * Interrupt service routine. 1926 */ 1927 static int 1928 wm_intr(void *arg) 1929 { 1930 struct wm_softc *sc = arg; 1931 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1932 uint32_t icr; 1933 int wantinit, handled = 0; 1934 1935 for (wantinit = 0; wantinit == 0;) { 1936 icr = CSR_READ(sc, WMREG_ICR); 1937 if ((icr & sc->sc_icr) == 0) 1938 break; 1939 1940 #if 0 /*NRND > 0*/ 1941 if (RND_ENABLED(&sc->rnd_source)) 1942 rnd_add_uint32(&sc->rnd_source, icr); 1943 #endif 1944 1945 handled = 1; 1946 1947 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1948 if (icr & (ICR_RXDMT0|ICR_RXT0)) { 1949 DPRINTF(WM_DEBUG_RX, 1950 ("%s: RX: got Rx intr 0x%08x\n", 1951 sc->sc_dev.dv_xname, 1952 icr & (ICR_RXDMT0|ICR_RXT0))); 1953 WM_EVCNT_INCR(&sc->sc_ev_rxintr); 1954 } 1955 #endif 1956 wm_rxintr(sc); 1957 1958 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS) 1959 if (icr & ICR_TXDW) { 1960 DPRINTF(WM_DEBUG_TX, 1961 ("%s: TX: got TXDW interrupt\n", 1962 sc->sc_dev.dv_xname)); 1963 WM_EVCNT_INCR(&sc->sc_ev_txdw); 1964 } 1965 #endif 1966 wm_txintr(sc); 1967 1968 if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) { 1969 WM_EVCNT_INCR(&sc->sc_ev_linkintr); 1970 wm_linkintr(sc, icr); 1971 } 1972 1973 if (icr & ICR_RXO) { 1974 printf("%s: Receive overrun\n", sc->sc_dev.dv_xname); 1975 wantinit = 1; 1976 } 1977 } 1978 1979 if (handled) { 1980 if (wantinit) 1981 wm_init(ifp); 1982 1983 /* Try to get more packets going. */ 1984 wm_start(ifp); 1985 } 1986 1987 return (handled); 1988 } 1989 1990 /* 1991 * wm_txintr: 1992 * 1993 * Helper; handle transmit interrupts. 1994 */ 1995 static void 1996 wm_txintr(struct wm_softc *sc) 1997 { 1998 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1999 struct wm_txsoft *txs; 2000 uint8_t status; 2001 int i; 2002 2003 ifp->if_flags &= ~IFF_OACTIVE; 2004 2005 /* 2006 * Go through the Tx list and free mbufs for those 2007 * frames which have been transmitted. 2008 */ 2009 for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc); 2010 i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) { 2011 txs = &sc->sc_txsoft[i]; 2012 2013 DPRINTF(WM_DEBUG_TX, 2014 ("%s: TX: checking job %d\n", sc->sc_dev.dv_xname, i)); 2015 2016 WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc, 2017 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2018 2019 status = 2020 sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status; 2021 if ((status & WTX_ST_DD) == 0) { 2022 WM_CDTXSYNC(sc, txs->txs_lastdesc, 1, 2023 BUS_DMASYNC_PREREAD); 2024 break; 2025 } 2026 2027 DPRINTF(WM_DEBUG_TX, 2028 ("%s: TX: job %d done: descs %d..%d\n", 2029 sc->sc_dev.dv_xname, i, txs->txs_firstdesc, 2030 txs->txs_lastdesc)); 2031 2032 /* 2033 * XXX We should probably be using the statistics 2034 * XXX registers, but I don't know if they exist 2035 * XXX on chips before the i82544. 2036 */ 2037 2038 #ifdef WM_EVENT_COUNTERS 2039 if (status & WTX_ST_TU) 2040 WM_EVCNT_INCR(&sc->sc_ev_tu); 2041 #endif /* WM_EVENT_COUNTERS */ 2042 2043 if (status & (WTX_ST_EC|WTX_ST_LC)) { 2044 ifp->if_oerrors++; 2045 if (status & WTX_ST_LC) 2046 printf("%s: late collision\n", 2047 sc->sc_dev.dv_xname); 2048 else if (status & WTX_ST_EC) { 2049 ifp->if_collisions += 16; 2050 printf("%s: excessive collisions\n", 2051 sc->sc_dev.dv_xname); 2052 } 2053 } else 2054 ifp->if_opackets++; 2055 2056 sc->sc_txfree += txs->txs_ndesc; 2057 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2058 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2059 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2060 m_freem(txs->txs_mbuf); 2061 txs->txs_mbuf = NULL; 2062 } 2063 2064 /* Update the dirty transmit buffer pointer. */ 2065 sc->sc_txsdirty = i; 2066 DPRINTF(WM_DEBUG_TX, 2067 ("%s: TX: txsdirty -> %d\n", sc->sc_dev.dv_xname, i)); 2068 2069 /* 2070 * If there are no more pending transmissions, cancel the watchdog 2071 * timer. 2072 */ 2073 if (sc->sc_txsfree == WM_TXQUEUELEN(sc)) 2074 ifp->if_timer = 0; 2075 } 2076 2077 /* 2078 * wm_rxintr: 2079 * 2080 * Helper; handle receive interrupts. 2081 */ 2082 static void 2083 wm_rxintr(struct wm_softc *sc) 2084 { 2085 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2086 struct wm_rxsoft *rxs; 2087 struct mbuf *m; 2088 int i, len; 2089 uint8_t status, errors; 2090 2091 for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) { 2092 rxs = &sc->sc_rxsoft[i]; 2093 2094 DPRINTF(WM_DEBUG_RX, 2095 ("%s: RX: checking descriptor %d\n", 2096 sc->sc_dev.dv_xname, i)); 2097 2098 WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2099 2100 status = sc->sc_rxdescs[i].wrx_status; 2101 errors = sc->sc_rxdescs[i].wrx_errors; 2102 len = le16toh(sc->sc_rxdescs[i].wrx_len); 2103 2104 if ((status & WRX_ST_DD) == 0) { 2105 /* 2106 * We have processed all of the receive descriptors. 2107 */ 2108 WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 2109 break; 2110 } 2111 2112 if (__predict_false(sc->sc_rxdiscard)) { 2113 DPRINTF(WM_DEBUG_RX, 2114 ("%s: RX: discarding contents of descriptor %d\n", 2115 sc->sc_dev.dv_xname, i)); 2116 WM_INIT_RXDESC(sc, i); 2117 if (status & WRX_ST_EOP) { 2118 /* Reset our state. */ 2119 DPRINTF(WM_DEBUG_RX, 2120 ("%s: RX: resetting rxdiscard -> 0\n", 2121 sc->sc_dev.dv_xname)); 2122 sc->sc_rxdiscard = 0; 2123 } 2124 continue; 2125 } 2126 2127 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2128 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2129 2130 m = rxs->rxs_mbuf; 2131 2132 /* 2133 * Add a new receive buffer to the ring. 2134 */ 2135 if (wm_add_rxbuf(sc, i) != 0) { 2136 /* 2137 * Failed, throw away what we've done so 2138 * far, and discard the rest of the packet. 2139 */ 2140 ifp->if_ierrors++; 2141 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2142 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2143 WM_INIT_RXDESC(sc, i); 2144 if ((status & WRX_ST_EOP) == 0) 2145 sc->sc_rxdiscard = 1; 2146 if (sc->sc_rxhead != NULL) 2147 m_freem(sc->sc_rxhead); 2148 WM_RXCHAIN_RESET(sc); 2149 DPRINTF(WM_DEBUG_RX, 2150 ("%s: RX: Rx buffer allocation failed, " 2151 "dropping packet%s\n", sc->sc_dev.dv_xname, 2152 sc->sc_rxdiscard ? " (discard)" : "")); 2153 continue; 2154 } 2155 2156 WM_RXCHAIN_LINK(sc, m); 2157 2158 m->m_len = len; 2159 2160 DPRINTF(WM_DEBUG_RX, 2161 ("%s: RX: buffer at %p len %d\n", 2162 sc->sc_dev.dv_xname, m->m_data, len)); 2163 2164 /* 2165 * If this is not the end of the packet, keep 2166 * looking. 2167 */ 2168 if ((status & WRX_ST_EOP) == 0) { 2169 sc->sc_rxlen += len; 2170 DPRINTF(WM_DEBUG_RX, 2171 ("%s: RX: not yet EOP, rxlen -> %d\n", 2172 sc->sc_dev.dv_xname, sc->sc_rxlen)); 2173 continue; 2174 } 2175 2176 /* 2177 * Okay, we have the entire packet now... 2178 */ 2179 *sc->sc_rxtailp = NULL; 2180 m = sc->sc_rxhead; 2181 len += sc->sc_rxlen; 2182 2183 WM_RXCHAIN_RESET(sc); 2184 2185 DPRINTF(WM_DEBUG_RX, 2186 ("%s: RX: have entire packet, len -> %d\n", 2187 sc->sc_dev.dv_xname, len)); 2188 2189 /* 2190 * If an error occurred, update stats and drop the packet. 2191 */ 2192 if (errors & 2193 (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) { 2194 ifp->if_ierrors++; 2195 if (errors & WRX_ER_SE) 2196 printf("%s: symbol error\n", 2197 sc->sc_dev.dv_xname); 2198 else if (errors & WRX_ER_SEQ) 2199 printf("%s: receive sequence error\n", 2200 sc->sc_dev.dv_xname); 2201 else if (errors & WRX_ER_CE) 2202 printf("%s: CRC error\n", 2203 sc->sc_dev.dv_xname); 2204 m_freem(m); 2205 continue; 2206 } 2207 2208 /* 2209 * No errors. Receive the packet. 2210 * 2211 * Note, we have configured the chip to include the 2212 * CRC with every packet. 2213 */ 2214 m->m_flags |= M_HASFCS; 2215 m->m_pkthdr.rcvif = ifp; 2216 m->m_pkthdr.len = len; 2217 2218 #if 0 /* XXXJRT */ 2219 /* 2220 * If VLANs are enabled, VLAN packets have been unwrapped 2221 * for us. Associate the tag with the packet. 2222 */ 2223 if (sc->sc_ethercom.ec_nvlans != 0 && 2224 (status & WRX_ST_VP) != 0) { 2225 struct m_tag *vtag; 2226 2227 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2228 M_NOWAIT); 2229 if (vtag == NULL) { 2230 ifp->if_ierrors++; 2231 printf("%s: unable to allocate VLAN tag\n", 2232 sc->sc_dev.dv_xname); 2233 m_freem(m); 2234 continue; 2235 } 2236 2237 *(u_int *)(vtag + 1) = 2238 le16toh(sc->sc_rxdescs[i].wrx_special); 2239 } 2240 #endif /* XXXJRT */ 2241 2242 /* 2243 * Set up checksum info for this packet. 2244 */ 2245 if (status & WRX_ST_IPCS) { 2246 WM_EVCNT_INCR(&sc->sc_ev_rxipsum); 2247 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2248 if (errors & WRX_ER_IPE) 2249 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2250 } 2251 if (status & WRX_ST_TCPCS) { 2252 /* 2253 * Note: we don't know if this was TCP or UDP, 2254 * so we just set both bits, and expect the 2255 * upper layers to deal. 2256 */ 2257 WM_EVCNT_INCR(&sc->sc_ev_rxtusum); 2258 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4|M_CSUM_UDPv4; 2259 if (errors & WRX_ER_TCPE) 2260 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 2261 } 2262 2263 ifp->if_ipackets++; 2264 2265 #if NBPFILTER > 0 2266 /* Pass this up to any BPF listeners. */ 2267 if (ifp->if_bpf) 2268 bpf_mtap(ifp->if_bpf, m); 2269 #endif /* NBPFILTER > 0 */ 2270 2271 /* Pass it on. */ 2272 (*ifp->if_input)(ifp, m); 2273 } 2274 2275 /* Update the receive pointer. */ 2276 sc->sc_rxptr = i; 2277 2278 DPRINTF(WM_DEBUG_RX, 2279 ("%s: RX: rxptr -> %d\n", sc->sc_dev.dv_xname, i)); 2280 } 2281 2282 /* 2283 * wm_linkintr: 2284 * 2285 * Helper; handle link interrupts. 2286 */ 2287 static void 2288 wm_linkintr(struct wm_softc *sc, uint32_t icr) 2289 { 2290 uint32_t status; 2291 2292 /* 2293 * If we get a link status interrupt on a 1000BASE-T 2294 * device, just fall into the normal MII tick path. 2295 */ 2296 if (sc->sc_flags & WM_F_HAS_MII) { 2297 if (icr & ICR_LSC) { 2298 DPRINTF(WM_DEBUG_LINK, 2299 ("%s: LINK: LSC -> mii_tick\n", 2300 sc->sc_dev.dv_xname)); 2301 mii_tick(&sc->sc_mii); 2302 } else if (icr & ICR_RXSEQ) { 2303 DPRINTF(WM_DEBUG_LINK, 2304 ("%s: LINK Receive sequence error\n", 2305 sc->sc_dev.dv_xname)); 2306 } 2307 return; 2308 } 2309 2310 /* 2311 * If we are now receiving /C/, check for link again in 2312 * a couple of link clock ticks. 2313 */ 2314 if (icr & ICR_RXCFG) { 2315 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n", 2316 sc->sc_dev.dv_xname)); 2317 sc->sc_tbi_anstate = 2; 2318 } 2319 2320 if (icr & ICR_LSC) { 2321 status = CSR_READ(sc, WMREG_STATUS); 2322 if (status & STATUS_LU) { 2323 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n", 2324 sc->sc_dev.dv_xname, 2325 (status & STATUS_FD) ? "FDX" : "HDX")); 2326 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 2327 sc->sc_fcrtl &= ~FCRTL_XONE; 2328 if (status & STATUS_FD) 2329 sc->sc_tctl |= 2330 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2331 else 2332 sc->sc_tctl |= 2333 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 2334 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 2335 sc->sc_fcrtl |= FCRTL_XONE; 2336 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2337 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 2338 WMREG_OLD_FCRTL : WMREG_FCRTL, 2339 sc->sc_fcrtl); 2340 sc->sc_tbi_linkup = 1; 2341 } else { 2342 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n", 2343 sc->sc_dev.dv_xname)); 2344 sc->sc_tbi_linkup = 0; 2345 } 2346 sc->sc_tbi_anstate = 2; 2347 wm_tbi_set_linkled(sc); 2348 } else if (icr & ICR_RXSEQ) { 2349 DPRINTF(WM_DEBUG_LINK, 2350 ("%s: LINK: Receive sequence error\n", 2351 sc->sc_dev.dv_xname)); 2352 } 2353 } 2354 2355 /* 2356 * wm_tick: 2357 * 2358 * One second timer, used to check link status, sweep up 2359 * completed transmit jobs, etc. 2360 */ 2361 static void 2362 wm_tick(void *arg) 2363 { 2364 struct wm_softc *sc = arg; 2365 int s; 2366 2367 s = splnet(); 2368 2369 if (sc->sc_type >= WM_T_82542_2_1) { 2370 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC)); 2371 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC)); 2372 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC)); 2373 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC)); 2374 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC)); 2375 } 2376 2377 if (sc->sc_flags & WM_F_HAS_MII) 2378 mii_tick(&sc->sc_mii); 2379 else 2380 wm_tbi_check_link(sc); 2381 2382 splx(s); 2383 2384 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2385 } 2386 2387 /* 2388 * wm_reset: 2389 * 2390 * Reset the i82542 chip. 2391 */ 2392 static void 2393 wm_reset(struct wm_softc *sc) 2394 { 2395 int i; 2396 2397 /* 2398 * Allocate on-chip memory according to the MTU size. 2399 * The Packet Buffer Allocation register must be written 2400 * before the chip is reset. 2401 */ 2402 if (sc->sc_type < WM_T_82547) { 2403 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2404 PBA_40K : PBA_48K; 2405 } else { 2406 sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ? 2407 PBA_22K : PBA_30K; 2408 sc->sc_txfifo_head = 0; 2409 sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT; 2410 sc->sc_txfifo_size = 2411 (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT; 2412 sc->sc_txfifo_stall = 0; 2413 } 2414 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 2415 2416 switch (sc->sc_type) { 2417 case WM_T_82544: 2418 case WM_T_82540: 2419 case WM_T_82545: 2420 case WM_T_82546: 2421 case WM_T_82541: 2422 case WM_T_82541_2: 2423 /* 2424 * These chips have a problem with the memory-mapped 2425 * write cycle when issuing the reset, so use I/O-mapped 2426 * access, if possible. 2427 */ 2428 if (sc->sc_flags & WM_F_IOH_VALID) 2429 wm_io_write(sc, WMREG_CTRL, CTRL_RST); 2430 else 2431 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2432 break; 2433 2434 case WM_T_82545_3: 2435 case WM_T_82546_3: 2436 /* Use the shadow control register on these chips. */ 2437 CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST); 2438 break; 2439 2440 default: 2441 /* Everything else can safely use the documented method. */ 2442 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 2443 break; 2444 } 2445 delay(10000); 2446 2447 for (i = 0; i < 1000; i++) { 2448 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 2449 return; 2450 delay(20); 2451 } 2452 2453 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 2454 printf("%s: WARNING: reset failed to complete\n", 2455 sc->sc_dev.dv_xname); 2456 } 2457 2458 /* 2459 * wm_init: [ifnet interface function] 2460 * 2461 * Initialize the interface. Must be called at splnet(). 2462 */ 2463 static int 2464 wm_init(struct ifnet *ifp) 2465 { 2466 struct wm_softc *sc = ifp->if_softc; 2467 struct wm_rxsoft *rxs; 2468 int i, error = 0; 2469 uint32_t reg; 2470 2471 /* 2472 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 2473 * There is a small but measurable benefit to avoiding the adjusment 2474 * of the descriptor so that the headers are aligned, for normal mtu, 2475 * on such platforms. One possibility is that the DMA itself is 2476 * slightly more efficient if the front of the entire packet (instead 2477 * of the front of the headers) is aligned. 2478 * 2479 * Note we must always set align_tweak to 0 if we are using 2480 * jumbo frames. 2481 */ 2482 #ifdef __NO_STRICT_ALIGNMENT 2483 sc->sc_align_tweak = 0; 2484 #else 2485 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 2486 sc->sc_align_tweak = 0; 2487 else 2488 sc->sc_align_tweak = 2; 2489 #endif /* __NO_STRICT_ALIGNMENT */ 2490 2491 /* Cancel any pending I/O. */ 2492 wm_stop(ifp, 0); 2493 2494 /* Reset the chip to a known state. */ 2495 wm_reset(sc); 2496 2497 /* Initialize the transmit descriptor ring. */ 2498 memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc)); 2499 WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc), 2500 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2501 sc->sc_txfree = WM_NTXDESC(sc); 2502 sc->sc_txnext = 0; 2503 2504 sc->sc_txctx_ipcs = 0xffffffff; 2505 sc->sc_txctx_tucs = 0xffffffff; 2506 2507 if (sc->sc_type < WM_T_82543) { 2508 CSR_WRITE(sc, WMREG_OLD_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2509 CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2510 CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc)); 2511 CSR_WRITE(sc, WMREG_OLD_TDH, 0); 2512 CSR_WRITE(sc, WMREG_OLD_TDT, 0); 2513 CSR_WRITE(sc, WMREG_OLD_TIDV, 128); 2514 } else { 2515 CSR_WRITE(sc, WMREG_TBDAH, WM_CDTXADDR_HI(sc, 0)); 2516 CSR_WRITE(sc, WMREG_TBDAL, WM_CDTXADDR_LO(sc, 0)); 2517 CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc)); 2518 CSR_WRITE(sc, WMREG_TDH, 0); 2519 CSR_WRITE(sc, WMREG_TDT, 0); 2520 CSR_WRITE(sc, WMREG_TIDV, 128); 2521 2522 CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 2523 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); 2524 CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) | 2525 RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1)); 2526 } 2527 CSR_WRITE(sc, WMREG_TQSA_LO, 0); 2528 CSR_WRITE(sc, WMREG_TQSA_HI, 0); 2529 2530 /* Initialize the transmit job descriptors. */ 2531 for (i = 0; i < WM_TXQUEUELEN(sc); i++) 2532 sc->sc_txsoft[i].txs_mbuf = NULL; 2533 sc->sc_txsfree = WM_TXQUEUELEN(sc); 2534 sc->sc_txsnext = 0; 2535 sc->sc_txsdirty = 0; 2536 2537 /* 2538 * Initialize the receive descriptor and receive job 2539 * descriptor rings. 2540 */ 2541 if (sc->sc_type < WM_T_82543) { 2542 CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0)); 2543 CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0)); 2544 CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs)); 2545 CSR_WRITE(sc, WMREG_OLD_RDH0, 0); 2546 CSR_WRITE(sc, WMREG_OLD_RDT0, 0); 2547 CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD); 2548 2549 CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0); 2550 CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0); 2551 CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0); 2552 CSR_WRITE(sc, WMREG_OLD_RDH1, 0); 2553 CSR_WRITE(sc, WMREG_OLD_RDT1, 0); 2554 CSR_WRITE(sc, WMREG_OLD_RDTR1, 0); 2555 } else { 2556 CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0)); 2557 CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0)); 2558 CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 2559 CSR_WRITE(sc, WMREG_RDH, 0); 2560 CSR_WRITE(sc, WMREG_RDT, 0); 2561 CSR_WRITE(sc, WMREG_RDTR, 28 | RDTR_FPD); 2562 } 2563 for (i = 0; i < WM_NRXDESC; i++) { 2564 rxs = &sc->sc_rxsoft[i]; 2565 if (rxs->rxs_mbuf == NULL) { 2566 if ((error = wm_add_rxbuf(sc, i)) != 0) { 2567 printf("%s: unable to allocate or map rx " 2568 "buffer %d, error = %d\n", 2569 sc->sc_dev.dv_xname, i, error); 2570 /* 2571 * XXX Should attempt to run with fewer receive 2572 * XXX buffers instead of just failing. 2573 */ 2574 wm_rxdrain(sc); 2575 goto out; 2576 } 2577 } else 2578 WM_INIT_RXDESC(sc, i); 2579 } 2580 sc->sc_rxptr = 0; 2581 sc->sc_rxdiscard = 0; 2582 WM_RXCHAIN_RESET(sc); 2583 2584 /* 2585 * Clear out the VLAN table -- we don't use it (yet). 2586 */ 2587 CSR_WRITE(sc, WMREG_VET, 0); 2588 for (i = 0; i < WM_VLAN_TABSIZE; i++) 2589 CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0); 2590 2591 /* 2592 * Set up flow-control parameters. 2593 * 2594 * XXX Values could probably stand some tuning. 2595 */ 2596 CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST); 2597 CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST); 2598 CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL); 2599 2600 sc->sc_fcrtl = FCRTL_DFLT; 2601 if (sc->sc_type < WM_T_82543) { 2602 CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT); 2603 CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl); 2604 } else { 2605 CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT); 2606 CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl); 2607 } 2608 CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT); 2609 2610 #if 0 /* XXXJRT */ 2611 /* Deal with VLAN enables. */ 2612 if (sc->sc_ethercom.ec_nvlans != 0) 2613 sc->sc_ctrl |= CTRL_VME; 2614 else 2615 #endif /* XXXJRT */ 2616 sc->sc_ctrl &= ~CTRL_VME; 2617 2618 /* Write the control registers. */ 2619 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 2620 #if 0 2621 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 2622 #endif 2623 2624 /* 2625 * Set up checksum offload parameters. 2626 */ 2627 reg = CSR_READ(sc, WMREG_RXCSUM); 2628 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 2629 reg |= RXCSUM_IPOFL; 2630 else 2631 reg &= ~RXCSUM_IPOFL; 2632 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4)) 2633 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 2634 else { 2635 reg &= ~RXCSUM_TUOFL; 2636 if ((ifp->if_capenable & IFCAP_CSUM_IPv4) == 0) 2637 reg &= ~RXCSUM_IPOFL; 2638 } 2639 CSR_WRITE(sc, WMREG_RXCSUM, reg); 2640 2641 /* 2642 * Set up the interrupt registers. 2643 */ 2644 CSR_WRITE(sc, WMREG_IMC, 0xffffffffU); 2645 sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 | 2646 ICR_RXO | ICR_RXT0; 2647 if ((sc->sc_flags & WM_F_HAS_MII) == 0) 2648 sc->sc_icr |= ICR_RXCFG; 2649 CSR_WRITE(sc, WMREG_IMS, sc->sc_icr); 2650 2651 /* Set up the inter-packet gap. */ 2652 CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg); 2653 2654 #if 0 /* XXXJRT */ 2655 /* Set the VLAN ethernetype. */ 2656 CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN); 2657 #endif 2658 2659 /* 2660 * Set up the transmit control register; we start out with 2661 * a collision distance suitable for FDX, but update it whe 2662 * we resolve the media type. 2663 */ 2664 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 2665 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 2666 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 2667 2668 /* Set the media. */ 2669 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 2670 2671 /* 2672 * Set up the receive control register; we actually program 2673 * the register when we set the receive filter. Use multicast 2674 * address offset type 0. 2675 * 2676 * Only the i82544 has the ability to strip the incoming 2677 * CRC, so we don't enable that feature. 2678 */ 2679 sc->sc_mchash_type = 0; 2680 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 2681 RCTL_DPF | RCTL_MO(sc->sc_mchash_type); 2682 2683 if(MCLBYTES == 2048) { 2684 sc->sc_rctl |= RCTL_2k; 2685 } else { 2686 if(sc->sc_type >= WM_T_82543) { 2687 switch(MCLBYTES) { 2688 case 4096: 2689 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 2690 break; 2691 case 8192: 2692 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 2693 break; 2694 case 16384: 2695 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 2696 break; 2697 default: 2698 panic("wm_init: MCLBYTES %d unsupported", 2699 MCLBYTES); 2700 break; 2701 } 2702 } else panic("wm_init: i82542 requires MCLBYTES = 2048"); 2703 } 2704 2705 /* Set the receive filter. */ 2706 wm_set_filter(sc); 2707 2708 /* Start the one second link check clock. */ 2709 callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc); 2710 2711 /* ...all done! */ 2712 ifp->if_flags |= IFF_RUNNING; 2713 ifp->if_flags &= ~IFF_OACTIVE; 2714 2715 out: 2716 if (error) 2717 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2718 return (error); 2719 } 2720 2721 /* 2722 * wm_rxdrain: 2723 * 2724 * Drain the receive queue. 2725 */ 2726 static void 2727 wm_rxdrain(struct wm_softc *sc) 2728 { 2729 struct wm_rxsoft *rxs; 2730 int i; 2731 2732 for (i = 0; i < WM_NRXDESC; i++) { 2733 rxs = &sc->sc_rxsoft[i]; 2734 if (rxs->rxs_mbuf != NULL) { 2735 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2736 m_freem(rxs->rxs_mbuf); 2737 rxs->rxs_mbuf = NULL; 2738 } 2739 } 2740 } 2741 2742 /* 2743 * wm_stop: [ifnet interface function] 2744 * 2745 * Stop transmission on the interface. 2746 */ 2747 static void 2748 wm_stop(struct ifnet *ifp, int disable) 2749 { 2750 struct wm_softc *sc = ifp->if_softc; 2751 struct wm_txsoft *txs; 2752 int i; 2753 2754 /* Stop the one second clock. */ 2755 callout_stop(&sc->sc_tick_ch); 2756 2757 /* Stop the 82547 Tx FIFO stall check timer. */ 2758 if (sc->sc_type == WM_T_82547) 2759 callout_stop(&sc->sc_txfifo_ch); 2760 2761 if (sc->sc_flags & WM_F_HAS_MII) { 2762 /* Down the MII. */ 2763 mii_down(&sc->sc_mii); 2764 } 2765 2766 /* Stop the transmit and receive processes. */ 2767 CSR_WRITE(sc, WMREG_TCTL, 0); 2768 CSR_WRITE(sc, WMREG_RCTL, 0); 2769 2770 /* Release any queued transmit buffers. */ 2771 for (i = 0; i < WM_TXQUEUELEN(sc); i++) { 2772 txs = &sc->sc_txsoft[i]; 2773 if (txs->txs_mbuf != NULL) { 2774 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2775 m_freem(txs->txs_mbuf); 2776 txs->txs_mbuf = NULL; 2777 } 2778 } 2779 2780 if (disable) 2781 wm_rxdrain(sc); 2782 2783 /* Mark the interface as down and cancel the watchdog timer. */ 2784 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2785 ifp->if_timer = 0; 2786 } 2787 2788 /* 2789 * wm_acquire_eeprom: 2790 * 2791 * Perform the EEPROM handshake required on some chips. 2792 */ 2793 static int 2794 wm_acquire_eeprom(struct wm_softc *sc) 2795 { 2796 uint32_t reg; 2797 int x; 2798 2799 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2800 reg = CSR_READ(sc, WMREG_EECD); 2801 2802 /* Request EEPROM access. */ 2803 reg |= EECD_EE_REQ; 2804 CSR_WRITE(sc, WMREG_EECD, reg); 2805 2806 /* ..and wait for it to be granted. */ 2807 for (x = 0; x < 100; x++) { 2808 reg = CSR_READ(sc, WMREG_EECD); 2809 if (reg & EECD_EE_GNT) 2810 break; 2811 delay(5); 2812 } 2813 if ((reg & EECD_EE_GNT) == 0) { 2814 aprint_error("%s: could not acquire EEPROM GNT\n", 2815 sc->sc_dev.dv_xname); 2816 reg &= ~EECD_EE_REQ; 2817 CSR_WRITE(sc, WMREG_EECD, reg); 2818 return (1); 2819 } 2820 } 2821 2822 return (0); 2823 } 2824 2825 /* 2826 * wm_release_eeprom: 2827 * 2828 * Release the EEPROM mutex. 2829 */ 2830 static void 2831 wm_release_eeprom(struct wm_softc *sc) 2832 { 2833 uint32_t reg; 2834 2835 if (sc->sc_flags & WM_F_EEPROM_HANDSHAKE) { 2836 reg = CSR_READ(sc, WMREG_EECD); 2837 reg &= ~EECD_EE_REQ; 2838 CSR_WRITE(sc, WMREG_EECD, reg); 2839 } 2840 } 2841 2842 /* 2843 * wm_eeprom_sendbits: 2844 * 2845 * Send a series of bits to the EEPROM. 2846 */ 2847 static void 2848 wm_eeprom_sendbits(struct wm_softc *sc, uint32_t bits, int nbits) 2849 { 2850 uint32_t reg; 2851 int x; 2852 2853 reg = CSR_READ(sc, WMREG_EECD); 2854 2855 for (x = nbits; x > 0; x--) { 2856 if (bits & (1U << (x - 1))) 2857 reg |= EECD_DI; 2858 else 2859 reg &= ~EECD_DI; 2860 CSR_WRITE(sc, WMREG_EECD, reg); 2861 delay(2); 2862 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2863 delay(2); 2864 CSR_WRITE(sc, WMREG_EECD, reg); 2865 delay(2); 2866 } 2867 } 2868 2869 /* 2870 * wm_eeprom_recvbits: 2871 * 2872 * Receive a series of bits from the EEPROM. 2873 */ 2874 static void 2875 wm_eeprom_recvbits(struct wm_softc *sc, uint32_t *valp, int nbits) 2876 { 2877 uint32_t reg, val; 2878 int x; 2879 2880 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI; 2881 2882 val = 0; 2883 for (x = nbits; x > 0; x--) { 2884 CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK); 2885 delay(2); 2886 if (CSR_READ(sc, WMREG_EECD) & EECD_DO) 2887 val |= (1U << (x - 1)); 2888 CSR_WRITE(sc, WMREG_EECD, reg); 2889 delay(2); 2890 } 2891 *valp = val; 2892 } 2893 2894 /* 2895 * wm_read_eeprom_uwire: 2896 * 2897 * Read a word from the EEPROM using the MicroWire protocol. 2898 */ 2899 static int 2900 wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2901 { 2902 uint32_t reg, val; 2903 int i; 2904 2905 for (i = 0; i < wordcnt; i++) { 2906 /* Clear SK and DI. */ 2907 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI); 2908 CSR_WRITE(sc, WMREG_EECD, reg); 2909 2910 /* Set CHIP SELECT. */ 2911 reg |= EECD_CS; 2912 CSR_WRITE(sc, WMREG_EECD, reg); 2913 delay(2); 2914 2915 /* Shift in the READ command. */ 2916 wm_eeprom_sendbits(sc, UWIRE_OPC_READ, 3); 2917 2918 /* Shift in address. */ 2919 wm_eeprom_sendbits(sc, word + i, sc->sc_ee_addrbits); 2920 2921 /* Shift out the data. */ 2922 wm_eeprom_recvbits(sc, &val, 16); 2923 data[i] = val & 0xffff; 2924 2925 /* Clear CHIP SELECT. */ 2926 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS; 2927 CSR_WRITE(sc, WMREG_EECD, reg); 2928 delay(2); 2929 } 2930 2931 return (0); 2932 } 2933 2934 /* 2935 * wm_spi_eeprom_ready: 2936 * 2937 * Wait for a SPI EEPROM to be ready for commands. 2938 */ 2939 static int 2940 wm_spi_eeprom_ready(struct wm_softc *sc) 2941 { 2942 uint32_t val; 2943 int usec; 2944 2945 for (usec = 0; usec < SPI_MAX_RETRIES; delay(5), usec += 5) { 2946 wm_eeprom_sendbits(sc, SPI_OPC_RDSR, 8); 2947 wm_eeprom_recvbits(sc, &val, 8); 2948 if ((val & SPI_SR_RDY) == 0) 2949 break; 2950 } 2951 if (usec >= SPI_MAX_RETRIES) { 2952 aprint_error("%s: EEPROM failed to become ready\n", 2953 sc->sc_dev.dv_xname); 2954 return (1); 2955 } 2956 return (0); 2957 } 2958 2959 /* 2960 * wm_read_eeprom_spi: 2961 * 2962 * Read a work from the EEPROM using the SPI protocol. 2963 */ 2964 static int 2965 wm_read_eeprom_spi(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 2966 { 2967 uint32_t reg, val; 2968 int i; 2969 uint8_t opc; 2970 2971 /* Clear SK and CS. */ 2972 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS); 2973 CSR_WRITE(sc, WMREG_EECD, reg); 2974 delay(2); 2975 2976 if (wm_spi_eeprom_ready(sc)) 2977 return (1); 2978 2979 /* Toggle CS to flush commands. */ 2980 CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS); 2981 delay(2); 2982 CSR_WRITE(sc, WMREG_EECD, reg); 2983 delay(2); 2984 2985 opc = SPI_OPC_READ; 2986 if (sc->sc_ee_addrbits == 8 && word >= 128) 2987 opc |= SPI_OPC_A8; 2988 2989 wm_eeprom_sendbits(sc, opc, 8); 2990 wm_eeprom_sendbits(sc, word << 1, sc->sc_ee_addrbits); 2991 2992 for (i = 0; i < wordcnt; i++) { 2993 wm_eeprom_recvbits(sc, &val, 16); 2994 data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8); 2995 } 2996 2997 /* Raise CS and clear SK. */ 2998 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS; 2999 CSR_WRITE(sc, WMREG_EECD, reg); 3000 delay(2); 3001 3002 return (0); 3003 } 3004 3005 /* 3006 * wm_read_eeprom: 3007 * 3008 * Read data from the serial EEPROM. 3009 */ 3010 static int 3011 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data) 3012 { 3013 int rv; 3014 3015 if (wm_acquire_eeprom(sc)) 3016 return (1); 3017 3018 if (sc->sc_flags & WM_F_EEPROM_SPI) 3019 rv = wm_read_eeprom_spi(sc, word, wordcnt, data); 3020 else 3021 rv = wm_read_eeprom_uwire(sc, word, wordcnt, data); 3022 3023 wm_release_eeprom(sc); 3024 return (rv); 3025 } 3026 3027 /* 3028 * wm_add_rxbuf: 3029 * 3030 * Add a receive buffer to the indiciated descriptor. 3031 */ 3032 static int 3033 wm_add_rxbuf(struct wm_softc *sc, int idx) 3034 { 3035 struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3036 struct mbuf *m; 3037 int error; 3038 3039 MGETHDR(m, M_DONTWAIT, MT_DATA); 3040 if (m == NULL) 3041 return (ENOBUFS); 3042 3043 MCLGET(m, M_DONTWAIT); 3044 if ((m->m_flags & M_EXT) == 0) { 3045 m_freem(m); 3046 return (ENOBUFS); 3047 } 3048 3049 if (rxs->rxs_mbuf != NULL) 3050 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3051 3052 rxs->rxs_mbuf = m; 3053 3054 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3055 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m, 3056 BUS_DMA_READ|BUS_DMA_NOWAIT); 3057 if (error) { 3058 printf("%s: unable to load rx DMA map %d, error = %d\n", 3059 sc->sc_dev.dv_xname, idx, error); 3060 panic("wm_add_rxbuf"); /* XXX XXX XXX */ 3061 } 3062 3063 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3064 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3065 3066 WM_INIT_RXDESC(sc, idx); 3067 3068 return (0); 3069 } 3070 3071 /* 3072 * wm_set_ral: 3073 * 3074 * Set an entery in the receive address list. 3075 */ 3076 static void 3077 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx) 3078 { 3079 uint32_t ral_lo, ral_hi; 3080 3081 if (enaddr != NULL) { 3082 ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 3083 (enaddr[3] << 24); 3084 ral_hi = enaddr[4] | (enaddr[5] << 8); 3085 ral_hi |= RAL_AV; 3086 } else { 3087 ral_lo = 0; 3088 ral_hi = 0; 3089 } 3090 3091 if (sc->sc_type >= WM_T_82544) { 3092 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx), 3093 ral_lo); 3094 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx), 3095 ral_hi); 3096 } else { 3097 CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo); 3098 CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi); 3099 } 3100 } 3101 3102 /* 3103 * wm_mchash: 3104 * 3105 * Compute the hash of the multicast address for the 4096-bit 3106 * multicast filter. 3107 */ 3108 static uint32_t 3109 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr) 3110 { 3111 static const int lo_shift[4] = { 4, 3, 2, 0 }; 3112 static const int hi_shift[4] = { 4, 5, 6, 8 }; 3113 uint32_t hash; 3114 3115 hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) | 3116 (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]); 3117 3118 return (hash & 0xfff); 3119 } 3120 3121 /* 3122 * wm_set_filter: 3123 * 3124 * Set up the receive filter. 3125 */ 3126 static void 3127 wm_set_filter(struct wm_softc *sc) 3128 { 3129 struct ethercom *ec = &sc->sc_ethercom; 3130 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3131 struct ether_multi *enm; 3132 struct ether_multistep step; 3133 bus_addr_t mta_reg; 3134 uint32_t hash, reg, bit; 3135 int i; 3136 3137 if (sc->sc_type >= WM_T_82544) 3138 mta_reg = WMREG_CORDOVA_MTA; 3139 else 3140 mta_reg = WMREG_MTA; 3141 3142 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 3143 3144 if (ifp->if_flags & IFF_BROADCAST) 3145 sc->sc_rctl |= RCTL_BAM; 3146 if (ifp->if_flags & IFF_PROMISC) { 3147 sc->sc_rctl |= RCTL_UPE; 3148 goto allmulti; 3149 } 3150 3151 /* 3152 * Set the station address in the first RAL slot, and 3153 * clear the remaining slots. 3154 */ 3155 wm_set_ral(sc, LLADDR(ifp->if_sadl), 0); 3156 for (i = 1; i < WM_RAL_TABSIZE; i++) 3157 wm_set_ral(sc, NULL, i); 3158 3159 /* Clear out the multicast table. */ 3160 for (i = 0; i < WM_MC_TABSIZE; i++) 3161 CSR_WRITE(sc, mta_reg + (i << 2), 0); 3162 3163 ETHER_FIRST_MULTI(step, ec, enm); 3164 while (enm != NULL) { 3165 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3166 /* 3167 * We must listen to a range of multicast addresses. 3168 * For now, just accept all multicasts, rather than 3169 * trying to set only those filter bits needed to match 3170 * the range. (At this time, the only use of address 3171 * ranges is for IP multicast routing, for which the 3172 * range is big enough to require all bits set.) 3173 */ 3174 goto allmulti; 3175 } 3176 3177 hash = wm_mchash(sc, enm->enm_addrlo); 3178 3179 reg = (hash >> 5) & 0x7f; 3180 bit = hash & 0x1f; 3181 3182 hash = CSR_READ(sc, mta_reg + (reg << 2)); 3183 hash |= 1U << bit; 3184 3185 /* XXX Hardware bug?? */ 3186 if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) { 3187 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2)); 3188 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3189 CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit); 3190 } else 3191 CSR_WRITE(sc, mta_reg + (reg << 2), hash); 3192 3193 ETHER_NEXT_MULTI(step, enm); 3194 } 3195 3196 ifp->if_flags &= ~IFF_ALLMULTI; 3197 goto setit; 3198 3199 allmulti: 3200 ifp->if_flags |= IFF_ALLMULTI; 3201 sc->sc_rctl |= RCTL_MPE; 3202 3203 setit: 3204 CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl); 3205 } 3206 3207 /* 3208 * wm_tbi_mediainit: 3209 * 3210 * Initialize media for use on 1000BASE-X devices. 3211 */ 3212 static void 3213 wm_tbi_mediainit(struct wm_softc *sc) 3214 { 3215 const char *sep = ""; 3216 3217 if (sc->sc_type < WM_T_82543) 3218 sc->sc_tipg = TIPG_WM_DFLT; 3219 else 3220 sc->sc_tipg = TIPG_LG_DFLT; 3221 3222 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange, 3223 wm_tbi_mediastatus); 3224 3225 /* 3226 * SWD Pins: 3227 * 3228 * 0 = Link LED (output) 3229 * 1 = Loss Of Signal (input) 3230 */ 3231 sc->sc_ctrl |= CTRL_SWDPIO(0); 3232 sc->sc_ctrl &= ~CTRL_SWDPIO(1); 3233 3234 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3235 3236 #define ADD(ss, mm, dd) \ 3237 do { \ 3238 printf("%s%s", sep, ss); \ 3239 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL); \ 3240 sep = ", "; \ 3241 } while (/*CONSTCOND*/0) 3242 3243 printf("%s: ", sc->sc_dev.dv_xname); 3244 ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD); 3245 ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD); 3246 ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD); 3247 printf("\n"); 3248 3249 #undef ADD 3250 3251 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3252 } 3253 3254 /* 3255 * wm_tbi_mediastatus: [ifmedia interface function] 3256 * 3257 * Get the current interface media status on a 1000BASE-X device. 3258 */ 3259 static void 3260 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3261 { 3262 struct wm_softc *sc = ifp->if_softc; 3263 uint32_t ctrl; 3264 3265 ifmr->ifm_status = IFM_AVALID; 3266 ifmr->ifm_active = IFM_ETHER; 3267 3268 if (sc->sc_tbi_linkup == 0) { 3269 ifmr->ifm_active |= IFM_NONE; 3270 return; 3271 } 3272 3273 ifmr->ifm_status |= IFM_ACTIVE; 3274 ifmr->ifm_active |= IFM_1000_SX; 3275 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD) 3276 ifmr->ifm_active |= IFM_FDX; 3277 ctrl = CSR_READ(sc, WMREG_CTRL); 3278 if (ctrl & CTRL_RFCE) 3279 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 3280 if (ctrl & CTRL_TFCE) 3281 ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 3282 } 3283 3284 /* 3285 * wm_tbi_mediachange: [ifmedia interface function] 3286 * 3287 * Set hardware to newly-selected media on a 1000BASE-X device. 3288 */ 3289 static int 3290 wm_tbi_mediachange(struct ifnet *ifp) 3291 { 3292 struct wm_softc *sc = ifp->if_softc; 3293 struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur; 3294 uint32_t status; 3295 int i; 3296 3297 sc->sc_txcw = ife->ifm_data; 3298 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 3299 (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0) 3300 sc->sc_txcw |= ANAR_X_PAUSE_SYM | ANAR_X_PAUSE_ASYM; 3301 sc->sc_txcw |= TXCW_ANE; 3302 3303 CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw); 3304 delay(10000); 3305 3306 /* NOTE: CTRL will update TFCE and RFCE automatically. */ 3307 3308 sc->sc_tbi_anstate = 0; 3309 3310 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1)) == 0) { 3311 /* Have signal; wait for the link to come up. */ 3312 for (i = 0; i < 50; i++) { 3313 delay(10000); 3314 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU) 3315 break; 3316 } 3317 3318 status = CSR_READ(sc, WMREG_STATUS); 3319 if (status & STATUS_LU) { 3320 /* Link is up. */ 3321 DPRINTF(WM_DEBUG_LINK, 3322 ("%s: LINK: set media -> link up %s\n", 3323 sc->sc_dev.dv_xname, 3324 (status & STATUS_FD) ? "FDX" : "HDX")); 3325 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3326 sc->sc_fcrtl &= ~FCRTL_XONE; 3327 if (status & STATUS_FD) 3328 sc->sc_tctl |= 3329 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3330 else 3331 sc->sc_tctl |= 3332 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3333 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE) 3334 sc->sc_fcrtl |= FCRTL_XONE; 3335 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3336 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3337 WMREG_OLD_FCRTL : WMREG_FCRTL, 3338 sc->sc_fcrtl); 3339 sc->sc_tbi_linkup = 1; 3340 } else { 3341 /* Link is down. */ 3342 DPRINTF(WM_DEBUG_LINK, 3343 ("%s: LINK: set media -> link down\n", 3344 sc->sc_dev.dv_xname)); 3345 sc->sc_tbi_linkup = 0; 3346 } 3347 } else { 3348 DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n", 3349 sc->sc_dev.dv_xname)); 3350 sc->sc_tbi_linkup = 0; 3351 } 3352 3353 wm_tbi_set_linkled(sc); 3354 3355 return (0); 3356 } 3357 3358 /* 3359 * wm_tbi_set_linkled: 3360 * 3361 * Update the link LED on 1000BASE-X devices. 3362 */ 3363 static void 3364 wm_tbi_set_linkled(struct wm_softc *sc) 3365 { 3366 3367 if (sc->sc_tbi_linkup) 3368 sc->sc_ctrl |= CTRL_SWDPIN(0); 3369 else 3370 sc->sc_ctrl &= ~CTRL_SWDPIN(0); 3371 3372 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3373 } 3374 3375 /* 3376 * wm_tbi_check_link: 3377 * 3378 * Check the link on 1000BASE-X devices. 3379 */ 3380 static void 3381 wm_tbi_check_link(struct wm_softc *sc) 3382 { 3383 uint32_t rxcw, ctrl, status; 3384 3385 if (sc->sc_tbi_anstate == 0) 3386 return; 3387 else if (sc->sc_tbi_anstate > 1) { 3388 DPRINTF(WM_DEBUG_LINK, 3389 ("%s: LINK: anstate %d\n", sc->sc_dev.dv_xname, 3390 sc->sc_tbi_anstate)); 3391 sc->sc_tbi_anstate--; 3392 return; 3393 } 3394 3395 sc->sc_tbi_anstate = 0; 3396 3397 rxcw = CSR_READ(sc, WMREG_RXCW); 3398 ctrl = CSR_READ(sc, WMREG_CTRL); 3399 status = CSR_READ(sc, WMREG_STATUS); 3400 3401 if ((status & STATUS_LU) == 0) { 3402 DPRINTF(WM_DEBUG_LINK, 3403 ("%s: LINK: checklink -> down\n", sc->sc_dev.dv_xname)); 3404 sc->sc_tbi_linkup = 0; 3405 } else { 3406 DPRINTF(WM_DEBUG_LINK, 3407 ("%s: LINK: checklink -> up %s\n", sc->sc_dev.dv_xname, 3408 (status & STATUS_FD) ? "FDX" : "HDX")); 3409 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3410 sc->sc_fcrtl &= ~FCRTL_XONE; 3411 if (status & STATUS_FD) 3412 sc->sc_tctl |= 3413 TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3414 else 3415 sc->sc_tctl |= 3416 TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3417 if (ctrl & CTRL_TFCE) 3418 sc->sc_fcrtl |= FCRTL_XONE; 3419 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3420 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? 3421 WMREG_OLD_FCRTL : WMREG_FCRTL, 3422 sc->sc_fcrtl); 3423 sc->sc_tbi_linkup = 1; 3424 } 3425 3426 wm_tbi_set_linkled(sc); 3427 } 3428 3429 /* 3430 * wm_gmii_reset: 3431 * 3432 * Reset the PHY. 3433 */ 3434 static void 3435 wm_gmii_reset(struct wm_softc *sc) 3436 { 3437 uint32_t reg; 3438 3439 if (sc->sc_type >= WM_T_82544) { 3440 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 3441 delay(20000); 3442 3443 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3444 delay(20000); 3445 } else { 3446 /* The PHY reset pin is active-low. */ 3447 reg = CSR_READ(sc, WMREG_CTRL_EXT); 3448 reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) | 3449 CTRL_EXT_SWDPIN(4)); 3450 reg |= CTRL_EXT_SWDPIO(4); 3451 3452 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3453 delay(10); 3454 3455 CSR_WRITE(sc, WMREG_CTRL_EXT, reg); 3456 delay(10); 3457 3458 CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4)); 3459 delay(10); 3460 #if 0 3461 sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4); 3462 #endif 3463 } 3464 } 3465 3466 /* 3467 * wm_gmii_mediainit: 3468 * 3469 * Initialize media for use on 1000BASE-T devices. 3470 */ 3471 static void 3472 wm_gmii_mediainit(struct wm_softc *sc) 3473 { 3474 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3475 3476 /* We have MII. */ 3477 sc->sc_flags |= WM_F_HAS_MII; 3478 3479 sc->sc_tipg = TIPG_1000T_DFLT; 3480 3481 /* 3482 * Let the chip set speed/duplex on its own based on 3483 * signals from the PHY. 3484 */ 3485 sc->sc_ctrl |= CTRL_SLU | CTRL_ASDE; 3486 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3487 3488 /* Initialize our media structures and probe the GMII. */ 3489 sc->sc_mii.mii_ifp = ifp; 3490 3491 if (sc->sc_type >= WM_T_82544) { 3492 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 3493 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 3494 } else { 3495 sc->sc_mii.mii_readreg = wm_gmii_i82543_readreg; 3496 sc->sc_mii.mii_writereg = wm_gmii_i82543_writereg; 3497 } 3498 sc->sc_mii.mii_statchg = wm_gmii_statchg; 3499 3500 wm_gmii_reset(sc); 3501 3502 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 3503 wm_gmii_mediastatus); 3504 3505 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 3506 MII_OFFSET_ANY, MIIF_DOPAUSE); 3507 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 3508 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 3509 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 3510 } else 3511 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 3512 } 3513 3514 /* 3515 * wm_gmii_mediastatus: [ifmedia interface function] 3516 * 3517 * Get the current interface media status on a 1000BASE-T device. 3518 */ 3519 static void 3520 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3521 { 3522 struct wm_softc *sc = ifp->if_softc; 3523 3524 mii_pollstat(&sc->sc_mii); 3525 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3526 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3527 sc->sc_flowflags; 3528 } 3529 3530 /* 3531 * wm_gmii_mediachange: [ifmedia interface function] 3532 * 3533 * Set hardware to newly-selected media on a 1000BASE-T device. 3534 */ 3535 static int 3536 wm_gmii_mediachange(struct ifnet *ifp) 3537 { 3538 struct wm_softc *sc = ifp->if_softc; 3539 3540 if (ifp->if_flags & IFF_UP) 3541 mii_mediachg(&sc->sc_mii); 3542 return (0); 3543 } 3544 3545 #define MDI_IO CTRL_SWDPIN(2) 3546 #define MDI_DIR CTRL_SWDPIO(2) /* host -> PHY */ 3547 #define MDI_CLK CTRL_SWDPIN(3) 3548 3549 static void 3550 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits) 3551 { 3552 uint32_t i, v; 3553 3554 v = CSR_READ(sc, WMREG_CTRL); 3555 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3556 v |= MDI_DIR | CTRL_SWDPIO(3); 3557 3558 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 3559 if (data & i) 3560 v |= MDI_IO; 3561 else 3562 v &= ~MDI_IO; 3563 CSR_WRITE(sc, WMREG_CTRL, v); 3564 delay(10); 3565 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3566 delay(10); 3567 CSR_WRITE(sc, WMREG_CTRL, v); 3568 delay(10); 3569 } 3570 } 3571 3572 static uint32_t 3573 i82543_mii_recvbits(struct wm_softc *sc) 3574 { 3575 uint32_t v, i, data = 0; 3576 3577 v = CSR_READ(sc, WMREG_CTRL); 3578 v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT)); 3579 v |= CTRL_SWDPIO(3); 3580 3581 CSR_WRITE(sc, WMREG_CTRL, v); 3582 delay(10); 3583 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3584 delay(10); 3585 CSR_WRITE(sc, WMREG_CTRL, v); 3586 delay(10); 3587 3588 for (i = 0; i < 16; i++) { 3589 data <<= 1; 3590 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3591 delay(10); 3592 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO) 3593 data |= 1; 3594 CSR_WRITE(sc, WMREG_CTRL, v); 3595 delay(10); 3596 } 3597 3598 CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK); 3599 delay(10); 3600 CSR_WRITE(sc, WMREG_CTRL, v); 3601 delay(10); 3602 3603 return (data); 3604 } 3605 3606 #undef MDI_IO 3607 #undef MDI_DIR 3608 #undef MDI_CLK 3609 3610 /* 3611 * wm_gmii_i82543_readreg: [mii interface function] 3612 * 3613 * Read a PHY register on the GMII (i82543 version). 3614 */ 3615 static int 3616 wm_gmii_i82543_readreg(struct device *self, int phy, int reg) 3617 { 3618 struct wm_softc *sc = (void *) self; 3619 int rv; 3620 3621 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3622 i82543_mii_sendbits(sc, reg | (phy << 5) | 3623 (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14); 3624 rv = i82543_mii_recvbits(sc) & 0xffff; 3625 3626 DPRINTF(WM_DEBUG_GMII, 3627 ("%s: GMII: read phy %d reg %d -> 0x%04x\n", 3628 sc->sc_dev.dv_xname, phy, reg, rv)); 3629 3630 return (rv); 3631 } 3632 3633 /* 3634 * wm_gmii_i82543_writereg: [mii interface function] 3635 * 3636 * Write a PHY register on the GMII (i82543 version). 3637 */ 3638 static void 3639 wm_gmii_i82543_writereg(struct device *self, int phy, int reg, int val) 3640 { 3641 struct wm_softc *sc = (void *) self; 3642 3643 i82543_mii_sendbits(sc, 0xffffffffU, 32); 3644 i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) | 3645 (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) | 3646 (MII_COMMAND_START << 30), 32); 3647 } 3648 3649 /* 3650 * wm_gmii_i82544_readreg: [mii interface function] 3651 * 3652 * Read a PHY register on the GMII. 3653 */ 3654 static int 3655 wm_gmii_i82544_readreg(struct device *self, int phy, int reg) 3656 { 3657 struct wm_softc *sc = (void *) self; 3658 uint32_t mdic = 0; 3659 int i, rv; 3660 3661 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) | 3662 MDIC_REGADD(reg)); 3663 3664 for (i = 0; i < 100; i++) { 3665 mdic = CSR_READ(sc, WMREG_MDIC); 3666 if (mdic & MDIC_READY) 3667 break; 3668 delay(10); 3669 } 3670 3671 if ((mdic & MDIC_READY) == 0) { 3672 printf("%s: MDIC read timed out: phy %d reg %d\n", 3673 sc->sc_dev.dv_xname, phy, reg); 3674 rv = 0; 3675 } else if (mdic & MDIC_E) { 3676 #if 0 /* This is normal if no PHY is present. */ 3677 printf("%s: MDIC read error: phy %d reg %d\n", 3678 sc->sc_dev.dv_xname, phy, reg); 3679 #endif 3680 rv = 0; 3681 } else { 3682 rv = MDIC_DATA(mdic); 3683 if (rv == 0xffff) 3684 rv = 0; 3685 } 3686 3687 return (rv); 3688 } 3689 3690 /* 3691 * wm_gmii_i82544_writereg: [mii interface function] 3692 * 3693 * Write a PHY register on the GMII. 3694 */ 3695 static void 3696 wm_gmii_i82544_writereg(struct device *self, int phy, int reg, int val) 3697 { 3698 struct wm_softc *sc = (void *) self; 3699 uint32_t mdic = 0; 3700 int i; 3701 3702 CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) | 3703 MDIC_REGADD(reg) | MDIC_DATA(val)); 3704 3705 for (i = 0; i < 100; i++) { 3706 mdic = CSR_READ(sc, WMREG_MDIC); 3707 if (mdic & MDIC_READY) 3708 break; 3709 delay(10); 3710 } 3711 3712 if ((mdic & MDIC_READY) == 0) 3713 printf("%s: MDIC write timed out: phy %d reg %d\n", 3714 sc->sc_dev.dv_xname, phy, reg); 3715 else if (mdic & MDIC_E) 3716 printf("%s: MDIC write error: phy %d reg %d\n", 3717 sc->sc_dev.dv_xname, phy, reg); 3718 } 3719 3720 /* 3721 * wm_gmii_statchg: [mii interface function] 3722 * 3723 * Callback from MII layer when media changes. 3724 */ 3725 static void 3726 wm_gmii_statchg(struct device *self) 3727 { 3728 struct wm_softc *sc = (void *) self; 3729 struct mii_data *mii = &sc->sc_mii; 3730 3731 sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE); 3732 sc->sc_tctl &= ~TCTL_COLD(0x3ff); 3733 sc->sc_fcrtl &= ~FCRTL_XONE; 3734 3735 /* 3736 * Get flow control negotiation result. 3737 */ 3738 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3739 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3740 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3741 mii->mii_media_active &= ~IFM_ETH_FMASK; 3742 } 3743 3744 if (sc->sc_flowflags & IFM_FLOW) { 3745 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) { 3746 sc->sc_ctrl |= CTRL_TFCE; 3747 sc->sc_fcrtl |= FCRTL_XONE; 3748 } 3749 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3750 sc->sc_ctrl |= CTRL_RFCE; 3751 } 3752 3753 if (sc->sc_mii.mii_media_active & IFM_FDX) { 3754 DPRINTF(WM_DEBUG_LINK, 3755 ("%s: LINK: statchg: FDX\n", sc->sc_dev.dv_xname)); 3756 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX); 3757 } else { 3758 DPRINTF(WM_DEBUG_LINK, 3759 ("%s: LINK: statchg: HDX\n", sc->sc_dev.dv_xname)); 3760 sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX); 3761 } 3762 3763 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 3764 CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl); 3765 CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL 3766 : WMREG_FCRTL, sc->sc_fcrtl); 3767 } 3768
Indexes created Mon Sep 22 21:09:42 GMT 2025